projects / mirror_qemu.git / blame
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|---|---|---|
| 38388f7e RH |
1 | # AArch64 SVE instruction descriptions |
| 2 | # | |
| 3 | # Copyright (c) 2017 Linaro, Ltd | |
| 4 | # | |
| 5 | # This library is free software; you can redistribute it and/or | |
| 6 | # modify it under the terms of the GNU Lesser General Public | |
| 7 | # License as published by the Free Software Foundation; either | |
| 8 | # version 2 of the License, or (at your option) any later version. | |
| 9 | # | |
| 10 | # This library is distributed in the hope that it will be useful, | |
| 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
| 13 | # Lesser General Public License for more details. | |
| 14 | # | |
| 15 | # You should have received a copy of the GNU Lesser General Public | |
| 16 | # License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
| 17 | ||
| 18 | # | |
| 19 | # This file is processed by scripts/decodetree.py | |
| 20 | # | |
| 21 | ||
| d1822297 RH |
22 | ########################################################################### |
| 23 | # Named fields. These are primarily for disjoint fields. | |
| 24 | ||
| f25a2361 | 25 | %imm4_16_p1 16:4 !function=plus1 |
| ccd841c3 | 26 | %imm6_22_5 22:1 5:5 |
| 30562ab7 | 27 | %imm7_22_16 22:2 16:5 |
| b94f8f60 | 28 | %imm8_16_10 16:5 10:3 |
| d1822297 | 29 | %imm9_16_10 16:s6 10:3 |
| 1a039c7e | 30 | %size_23 23:2 |
| d1822297 | 31 | |
| ccd841c3 RH |
32 | # A combination of tsz:imm3 -- extract esize. |
| 33 | %tszimm_esz 22:2 5:5 !function=tszimm_esz | |
| 34 | # A combination of tsz:imm3 -- extract (2 * esize) - (tsz:imm3) | |
| 35 | %tszimm_shr 22:2 5:5 !function=tszimm_shr | |
| 36 | # A combination of tsz:imm3 -- extract (tsz:imm3) - esize | |
| 37 | %tszimm_shl 22:2 5:5 !function=tszimm_shl | |
| 38 | ||
| d9d78dcc RH |
39 | # Similarly for the tszh/tszl pair at 22/16 for zzi |
| 40 | %tszimm16_esz 22:2 16:5 !function=tszimm_esz | |
| 41 | %tszimm16_shr 22:2 16:5 !function=tszimm_shr | |
| 42 | %tszimm16_shl 22:2 16:5 !function=tszimm_shl | |
| 43 | ||
| f25a2361 RH |
44 | # Signed 8-bit immediate, optionally shifted left by 8. |
| 45 | %sh8_i8s 5:9 !function=expand_imm_sh8s | |
| 6e6a157d RH |
46 | # Unsigned 8-bit immediate, optionally shifted left by 8. |
| 47 | %sh8_i8u 5:9 !function=expand_imm_sh8u | |
| f25a2361 | 48 | |
| c4e7c493 RH |
49 | # Unsigned load of msz into esz=2, represented as a dtype. |
| 50 | %msz_dtype 23:2 !function=msz_dtype | |
| 51 | ||
| f97cfd59 RH |
52 | # Either a copy of rd (at bit 0), or a different source |
| 53 | # as propagated via the MOVPRFX instruction. | |
| 54 | %reg_movprfx 0:5 | |
| 55 | ||
| 38388f7e RH |
56 | ########################################################################### |
| 57 | # Named attribute sets. These are used to make nice(er) names | |
| 58 | # when creating helpers common to those for the individual | |
| 59 | # instruction patterns. | |
| 60 | ||
| 028e2a7b | 61 | &rr_esz rd rn esz |
| d1822297 | 62 | &rri rd rn imm |
| e1fa1164 | 63 | &rr_dbm rd rn dbm |
| 4b242d9c | 64 | &rrri rd rn rm imm |
| d9d78dcc | 65 | &rri_esz rd rn imm esz |
| 38388f7e | 66 | &rrr_esz rd rn rm esz |
| 047cec97 | 67 | &rpr_esz rd pg rn esz |
| 35da316f | 68 | &rpr_s rd pg rn s |
| 516e246a | 69 | &rprr_s rd pg rn rm s |
| f97cfd59 | 70 | &rprr_esz rd pg rn rm esz |
| 96a36e4a | 71 | &rprrr_esz rd pg rn rm ra esz |
| ccd841c3 | 72 | &rpri_esz rd pg rn imm esz |
| 24e82e68 RH |
73 | &ptrue rd esz pat s |
| 74 | &incdec_cnt rd pat esz imm d u | |
| 75 | &incdec2_cnt rd rn pat esz imm d u | |
| 9ee3a611 RH |
76 | &incdec_pred rd pg esz d u |
| 77 | &incdec2_pred rd rn pg esz d u | |
| c4e7c493 RH |
78 | &rprr_load rd pg rn rm dtype nreg |
| 79 | &rpri_load rd pg rn imm dtype nreg | |
| 1a039c7e RH |
80 | &rprr_store rd pg rn rm msz esz nreg |
| 81 | &rpri_store rd pg rn imm msz esz nreg | |
| 38388f7e RH |
82 | |
| 83 | ########################################################################### | |
| 84 | # Named instruction formats. These are generally used to | |
| 85 | # reduce the amount of duplication between instruction patterns. | |
| 86 | ||
| 028e2a7b RH |
87 | # Two operand with unused vector element size |
| 88 | @pd_pn_e0 ........ ........ ....... rn:4 . rd:4 &rr_esz esz=0 | |
| 89 | ||
| 90 | # Two operand | |
| 91 | @pd_pn ........ esz:2 .. .... ....... rn:4 . rd:4 &rr_esz | |
| 0762cd42 | 92 | @rd_rn ........ esz:2 ...... ...... rn:5 rd:5 &rr_esz |
| 028e2a7b | 93 | |
| 35da316f RH |
94 | # Two operand with governing predicate, flags setting |
| 95 | @pd_pg_pn_s ........ . s:1 ...... .. pg:4 . rn:4 . rd:4 &rpr_s | |
| 96 | ||
| 38388f7e RH |
97 | # Three operand with unused vector element size |
| 98 | @rd_rn_rm_e0 ........ ... rm:5 ... ... rn:5 rd:5 &rrr_esz esz=0 | |
| 99 | ||
| 516e246a RH |
100 | # Three predicate operand, with governing predicate, flag setting |
| 101 | @pd_pg_pn_pm_s ........ . s:1 .. rm:4 .. pg:4 . rn:4 . rd:4 &rprr_s | |
| 102 | ||
| fea98f9c RH |
103 | # Three operand, vector element size |
| 104 | @rd_rn_rm ........ esz:2 . rm:5 ... ... rn:5 rd:5 &rrr_esz | |
| d731d8cb | 105 | @pd_pn_pm ........ esz:2 .. rm:4 ....... rn:4 . rd:4 &rrr_esz |
| 30562ab7 RH |
106 | @rdn_rm ........ esz:2 ...... ...... rm:5 rd:5 \ |
| 107 | &rrr_esz rn=%reg_movprfx | |
| 6e6a157d RH |
108 | @rdn_sh_i8u ........ esz:2 ...... ...... ..... rd:5 \ |
| 109 | &rri_esz rn=%reg_movprfx imm=%sh8_i8u | |
| 110 | @rdn_i8u ........ esz:2 ...... ... imm:8 rd:5 \ | |
| 111 | &rri_esz rn=%reg_movprfx | |
| 112 | @rdn_i8s ........ esz:2 ...... ... imm:s8 rd:5 \ | |
| 113 | &rri_esz rn=%reg_movprfx | |
| fea98f9c | 114 | |
| 4b242d9c RH |
115 | # Three operand with "memory" size, aka immediate left shift |
| 116 | @rd_rn_msz_rm ........ ... rm:5 .... imm:2 rn:5 rd:5 &rrri | |
| 117 | ||
| f97cfd59 RH |
118 | # Two register operand, with governing predicate, vector element size |
| 119 | @rdn_pg_rm ........ esz:2 ... ... ... pg:3 rm:5 rd:5 \ | |
| 120 | &rprr_esz rn=%reg_movprfx | |
| 121 | @rdm_pg_rn ........ esz:2 ... ... ... pg:3 rn:5 rd:5 \ | |
| 122 | &rprr_esz rm=%reg_movprfx | |
| d3fe4a29 | 123 | @rd_pg4_rn_rm ........ esz:2 . rm:5 .. pg:4 rn:5 rd:5 &rprr_esz |
| 757f9cff | 124 | @pd_pg_rn_rm ........ esz:2 . rm:5 ... pg:3 rn:5 . rd:4 &rprr_esz |
| f97cfd59 | 125 | |
| 96a36e4a RH |
126 | # Three register operand, with governing predicate, vector element size |
| 127 | @rda_pg_rn_rm ........ esz:2 . rm:5 ... pg:3 rn:5 rd:5 \ | |
| 128 | &rprrr_esz ra=%reg_movprfx | |
| 129 | @rdn_pg_ra_rm ........ esz:2 . rm:5 ... pg:3 ra:5 rd:5 \ | |
| 130 | &rprrr_esz rn=%reg_movprfx | |
| 131 | ||
| 047cec97 RH |
132 | # One register operand, with governing predicate, vector element size |
| 133 | @rd_pg_rn ........ esz:2 ... ... ... pg:3 rn:5 rd:5 &rpr_esz | |
| 9ee3a611 | 134 | @rd_pg4_pn ........ esz:2 ... ... .. pg:4 . rn:4 rd:5 &rpr_esz |
| 047cec97 | 135 | |
| 8092c6a3 RH |
136 | # One register operand, with governing predicate, no vector element size |
| 137 | @rd_pg_rn_e0 ........ .. ... ... ... pg:3 rn:5 rd:5 &rpr_esz esz=0 | |
| 138 | ||
| 96f922cc RH |
139 | # Two register operands with a 6-bit signed immediate. |
| 140 | @rd_rn_i6 ........ ... rn:5 ..... imm:s6 rd:5 &rri | |
| 141 | ||
| ccd841c3 RH |
142 | # Two register operand, one immediate operand, with predicate, |
| 143 | # element size encoded as TSZHL. User must fill in imm. | |
| 144 | @rdn_pg_tszimm ........ .. ... ... ... pg:3 ..... rd:5 \ | |
| 145 | &rpri_esz rn=%reg_movprfx esz=%tszimm_esz | |
| 146 | ||
| d9d78dcc RH |
147 | # Similarly without predicate. |
| 148 | @rd_rn_tszimm ........ .. ... ... ...... rn:5 rd:5 \ | |
| 149 | &rri_esz esz=%tszimm16_esz | |
| 150 | ||
| f25a2361 RH |
151 | # Two register operand, one immediate operand, with 4-bit predicate. |
| 152 | # User must fill in imm. | |
| 153 | @rdn_pg4 ........ esz:2 .. pg:4 ... ........ rd:5 \ | |
| 154 | &rpri_esz rn=%reg_movprfx | |
| 155 | ||
| e1fa1164 RH |
156 | # Two register operand, one encoded bitmask. |
| 157 | @rdn_dbm ........ .. .... dbm:13 rd:5 \ | |
| 158 | &rr_dbm rn=%reg_movprfx | |
| 159 | ||
| 38cadeba RH |
160 | # Predicate output, vector and immediate input, |
| 161 | # controlling predicate, element size. | |
| 162 | @pd_pg_rn_i7 ........ esz:2 . imm:7 . pg:3 rn:5 . rd:4 &rpri_esz | |
| 163 | @pd_pg_rn_i5 ........ esz:2 . imm:s5 ... pg:3 rn:5 . rd:4 &rpri_esz | |
| 164 | ||
| d1822297 RH |
165 | # Basic Load/Store with 9-bit immediate offset |
| 166 | @pd_rn_i9 ........ ........ ...... rn:5 . rd:4 \ | |
| 167 | &rri imm=%imm9_16_10 | |
| 168 | @rd_rn_i9 ........ ........ ...... rn:5 rd:5 \ | |
| 169 | &rri imm=%imm9_16_10 | |
| 170 | ||
| 24e82e68 RH |
171 | # One register, pattern, and uint4+1. |
| 172 | # User must fill in U and D. | |
| 173 | @incdec_cnt ........ esz:2 .. .... ...... pat:5 rd:5 \ | |
| 174 | &incdec_cnt imm=%imm4_16_p1 | |
| 175 | @incdec2_cnt ........ esz:2 .. .... ...... pat:5 rd:5 \ | |
| 176 | &incdec2_cnt imm=%imm4_16_p1 rn=%reg_movprfx | |
| 177 | ||
| 9ee3a611 RH |
178 | # One register, predicate. |
| 179 | # User must fill in U and D. | |
| 180 | @incdec_pred ........ esz:2 .... .. ..... .. pg:4 rd:5 &incdec_pred | |
| 181 | @incdec2_pred ........ esz:2 .... .. ..... .. pg:4 rd:5 \ | |
| 182 | &incdec2_pred rn=%reg_movprfx | |
| 183 | ||
| c4e7c493 RH |
184 | # Loads; user must fill in NREG. |
| 185 | @rprr_load_dt ....... dtype:4 rm:5 ... pg:3 rn:5 rd:5 &rprr_load | |
| 186 | @rpri_load_dt ....... dtype:4 . imm:s4 ... pg:3 rn:5 rd:5 &rpri_load | |
| 187 | ||
| 188 | @rprr_load_msz ....... .... rm:5 ... pg:3 rn:5 rd:5 \ | |
| 189 | &rprr_load dtype=%msz_dtype | |
| 190 | @rpri_load_msz ....... .... . imm:s4 ... pg:3 rn:5 rd:5 \ | |
| 191 | &rpri_load dtype=%msz_dtype | |
| 192 | ||
| 1a039c7e RH |
193 | # Stores; user must fill in ESZ, MSZ, NREG as needed. |
| 194 | @rprr_store ....... .. .. rm:5 ... pg:3 rn:5 rd:5 &rprr_store | |
| 195 | @rpri_store_msz ....... msz:2 .. . imm:s4 ... pg:3 rn:5 rd:5 &rpri_store | |
| 196 | @rprr_store_esz_n0 ....... .. esz:2 rm:5 ... pg:3 rn:5 rd:5 \ | |
| 197 | &rprr_store nreg=0 | |
| 198 | ||
| 38388f7e RH |
199 | ########################################################################### |
| 200 | # Instruction patterns. Grouped according to the SVE encodingindex.xhtml. | |
| 201 | ||
| f97cfd59 RH |
202 | ### SVE Integer Arithmetic - Binary Predicated Group |
| 203 | ||
| 204 | # SVE bitwise logical vector operations (predicated) | |
| 205 | ORR_zpzz 00000100 .. 011 000 000 ... ..... ..... @rdn_pg_rm | |
| 206 | EOR_zpzz 00000100 .. 011 001 000 ... ..... ..... @rdn_pg_rm | |
| 207 | AND_zpzz 00000100 .. 011 010 000 ... ..... ..... @rdn_pg_rm | |
| 208 | BIC_zpzz 00000100 .. 011 011 000 ... ..... ..... @rdn_pg_rm | |
| 209 | ||
| 210 | # SVE integer add/subtract vectors (predicated) | |
| 211 | ADD_zpzz 00000100 .. 000 000 000 ... ..... ..... @rdn_pg_rm | |
| 212 | SUB_zpzz 00000100 .. 000 001 000 ... ..... ..... @rdn_pg_rm | |
| 213 | SUB_zpzz 00000100 .. 000 011 000 ... ..... ..... @rdm_pg_rn # SUBR | |
| 214 | ||
| 215 | # SVE integer min/max/difference (predicated) | |
| 216 | SMAX_zpzz 00000100 .. 001 000 000 ... ..... ..... @rdn_pg_rm | |
| 217 | UMAX_zpzz 00000100 .. 001 001 000 ... ..... ..... @rdn_pg_rm | |
| 218 | SMIN_zpzz 00000100 .. 001 010 000 ... ..... ..... @rdn_pg_rm | |
| 219 | UMIN_zpzz 00000100 .. 001 011 000 ... ..... ..... @rdn_pg_rm | |
| 220 | SABD_zpzz 00000100 .. 001 100 000 ... ..... ..... @rdn_pg_rm | |
| 221 | UABD_zpzz 00000100 .. 001 101 000 ... ..... ..... @rdn_pg_rm | |
| 222 | ||
| 223 | # SVE integer multiply/divide (predicated) | |
| 224 | MUL_zpzz 00000100 .. 010 000 000 ... ..... ..... @rdn_pg_rm | |
| 225 | SMULH_zpzz 00000100 .. 010 010 000 ... ..... ..... @rdn_pg_rm | |
| 226 | UMULH_zpzz 00000100 .. 010 011 000 ... ..... ..... @rdn_pg_rm | |
| 227 | # Note that divide requires size >= 2; below 2 is unallocated. | |
| 228 | SDIV_zpzz 00000100 .. 010 100 000 ... ..... ..... @rdn_pg_rm | |
| 229 | UDIV_zpzz 00000100 .. 010 101 000 ... ..... ..... @rdn_pg_rm | |
| 230 | SDIV_zpzz 00000100 .. 010 110 000 ... ..... ..... @rdm_pg_rn # SDIVR | |
| 231 | UDIV_zpzz 00000100 .. 010 111 000 ... ..... ..... @rdm_pg_rn # UDIVR | |
| 232 | ||
| 047cec97 RH |
233 | ### SVE Integer Reduction Group |
| 234 | ||
| 235 | # SVE bitwise logical reduction (predicated) | |
| 236 | ORV 00000100 .. 011 000 001 ... ..... ..... @rd_pg_rn | |
| 237 | EORV 00000100 .. 011 001 001 ... ..... ..... @rd_pg_rn | |
| 238 | ANDV 00000100 .. 011 010 001 ... ..... ..... @rd_pg_rn | |
| 239 | ||
| 240 | # SVE integer add reduction (predicated) | |
| 241 | # Note that saddv requires size != 3. | |
| 242 | UADDV 00000100 .. 000 001 001 ... ..... ..... @rd_pg_rn | |
| 243 | SADDV 00000100 .. 000 000 001 ... ..... ..... @rd_pg_rn | |
| 244 | ||
| 245 | # SVE integer min/max reduction (predicated) | |
| 246 | SMAXV 00000100 .. 001 000 001 ... ..... ..... @rd_pg_rn | |
| 247 | UMAXV 00000100 .. 001 001 001 ... ..... ..... @rd_pg_rn | |
| 248 | SMINV 00000100 .. 001 010 001 ... ..... ..... @rd_pg_rn | |
| 249 | UMINV 00000100 .. 001 011 001 ... ..... ..... @rd_pg_rn | |
| 250 | ||
| ccd841c3 RH |
251 | ### SVE Shift by Immediate - Predicated Group |
| 252 | ||
| 253 | # SVE bitwise shift by immediate (predicated) | |
| 254 | ASR_zpzi 00000100 .. 000 000 100 ... .. ... ..... \ | |
| 255 | @rdn_pg_tszimm imm=%tszimm_shr | |
| 256 | LSR_zpzi 00000100 .. 000 001 100 ... .. ... ..... \ | |
| 257 | @rdn_pg_tszimm imm=%tszimm_shr | |
| 258 | LSL_zpzi 00000100 .. 000 011 100 ... .. ... ..... \ | |
| 259 | @rdn_pg_tszimm imm=%tszimm_shl | |
| 260 | ASRD 00000100 .. 000 100 100 ... .. ... ..... \ | |
| 261 | @rdn_pg_tszimm imm=%tszimm_shr | |
| 262 | ||
| 27721dbb RH |
263 | # SVE bitwise shift by vector (predicated) |
| 264 | ASR_zpzz 00000100 .. 010 000 100 ... ..... ..... @rdn_pg_rm | |
| 265 | LSR_zpzz 00000100 .. 010 001 100 ... ..... ..... @rdn_pg_rm | |
| 266 | LSL_zpzz 00000100 .. 010 011 100 ... ..... ..... @rdn_pg_rm | |
| 267 | ASR_zpzz 00000100 .. 010 100 100 ... ..... ..... @rdm_pg_rn # ASRR | |
| 268 | LSR_zpzz 00000100 .. 010 101 100 ... ..... ..... @rdm_pg_rn # LSRR | |
| 269 | LSL_zpzz 00000100 .. 010 111 100 ... ..... ..... @rdm_pg_rn # LSLR | |
| 270 | ||
| fe7f8dfb RH |
271 | # SVE bitwise shift by wide elements (predicated) |
| 272 | # Note these require size != 3. | |
| 273 | ASR_zpzw 00000100 .. 011 000 100 ... ..... ..... @rdn_pg_rm | |
| 274 | LSR_zpzw 00000100 .. 011 001 100 ... ..... ..... @rdn_pg_rm | |
| 275 | LSL_zpzw 00000100 .. 011 011 100 ... ..... ..... @rdn_pg_rm | |
| 276 | ||
| afac6d04 RH |
277 | ### SVE Integer Arithmetic - Unary Predicated Group |
| 278 | ||
| 279 | # SVE unary bit operations (predicated) | |
| 280 | # Note esz != 0 for FABS and FNEG. | |
| 281 | CLS 00000100 .. 011 000 101 ... ..... ..... @rd_pg_rn | |
| 282 | CLZ 00000100 .. 011 001 101 ... ..... ..... @rd_pg_rn | |
| 283 | CNT_zpz 00000100 .. 011 010 101 ... ..... ..... @rd_pg_rn | |
| 284 | CNOT 00000100 .. 011 011 101 ... ..... ..... @rd_pg_rn | |
| 285 | NOT_zpz 00000100 .. 011 110 101 ... ..... ..... @rd_pg_rn | |
| 286 | FABS 00000100 .. 011 100 101 ... ..... ..... @rd_pg_rn | |
| 287 | FNEG 00000100 .. 011 101 101 ... ..... ..... @rd_pg_rn | |
| 288 | ||
| 289 | # SVE integer unary operations (predicated) | |
| 290 | # Note esz > original size for extensions. | |
| 291 | ABS 00000100 .. 010 110 101 ... ..... ..... @rd_pg_rn | |
| 292 | NEG 00000100 .. 010 111 101 ... ..... ..... @rd_pg_rn | |
| 293 | SXTB 00000100 .. 010 000 101 ... ..... ..... @rd_pg_rn | |
| 294 | UXTB 00000100 .. 010 001 101 ... ..... ..... @rd_pg_rn | |
| 295 | SXTH 00000100 .. 010 010 101 ... ..... ..... @rd_pg_rn | |
| 296 | UXTH 00000100 .. 010 011 101 ... ..... ..... @rd_pg_rn | |
| 297 | SXTW 00000100 .. 010 100 101 ... ..... ..... @rd_pg_rn | |
| 298 | UXTW 00000100 .. 010 101 101 ... ..... ..... @rd_pg_rn | |
| 299 | ||
| 96a36e4a RH |
300 | ### SVE Integer Multiply-Add Group |
| 301 | ||
| 302 | # SVE integer multiply-add writing addend (predicated) | |
| 303 | MLA 00000100 .. 0 ..... 010 ... ..... ..... @rda_pg_rn_rm | |
| 304 | MLS 00000100 .. 0 ..... 011 ... ..... ..... @rda_pg_rn_rm | |
| 305 | ||
| 306 | # SVE integer multiply-add writing multiplicand (predicated) | |
| 307 | MLA 00000100 .. 0 ..... 110 ... ..... ..... @rdn_pg_ra_rm # MAD | |
| 308 | MLS 00000100 .. 0 ..... 111 ... ..... ..... @rdn_pg_ra_rm # MSB | |
| 309 | ||
| fea98f9c RH |
310 | ### SVE Integer Arithmetic - Unpredicated Group |
| 311 | ||
| 312 | # SVE integer add/subtract vectors (unpredicated) | |
| 313 | ADD_zzz 00000100 .. 1 ..... 000 000 ..... ..... @rd_rn_rm | |
| 314 | SUB_zzz 00000100 .. 1 ..... 000 001 ..... ..... @rd_rn_rm | |
| 315 | SQADD_zzz 00000100 .. 1 ..... 000 100 ..... ..... @rd_rn_rm | |
| 316 | UQADD_zzz 00000100 .. 1 ..... 000 101 ..... ..... @rd_rn_rm | |
| 317 | SQSUB_zzz 00000100 .. 1 ..... 000 110 ..... ..... @rd_rn_rm | |
| 318 | UQSUB_zzz 00000100 .. 1 ..... 000 111 ..... ..... @rd_rn_rm | |
| 319 | ||
| 38388f7e RH |
320 | ### SVE Logical - Unpredicated Group |
| 321 | ||
| 322 | # SVE bitwise logical operations (unpredicated) | |
| 323 | AND_zzz 00000100 00 1 ..... 001 100 ..... ..... @rd_rn_rm_e0 | |
| 324 | ORR_zzz 00000100 01 1 ..... 001 100 ..... ..... @rd_rn_rm_e0 | |
| 325 | EOR_zzz 00000100 10 1 ..... 001 100 ..... ..... @rd_rn_rm_e0 | |
| 326 | BIC_zzz 00000100 11 1 ..... 001 100 ..... ..... @rd_rn_rm_e0 | |
| d1822297 | 327 | |
| 9a56c9c3 RH |
328 | ### SVE Index Generation Group |
| 329 | ||
| 330 | # SVE index generation (immediate start, immediate increment) | |
| 331 | INDEX_ii 00000100 esz:2 1 imm2:s5 010000 imm1:s5 rd:5 | |
| 332 | ||
| 333 | # SVE index generation (immediate start, register increment) | |
| 334 | INDEX_ir 00000100 esz:2 1 rm:5 010010 imm:s5 rd:5 | |
| 335 | ||
| 336 | # SVE index generation (register start, immediate increment) | |
| 337 | INDEX_ri 00000100 esz:2 1 imm:s5 010001 rn:5 rd:5 | |
| 338 | ||
| 339 | # SVE index generation (register start, register increment) | |
| 340 | INDEX_rr 00000100 .. 1 ..... 010011 ..... ..... @rd_rn_rm | |
| 341 | ||
| 96f922cc RH |
342 | ### SVE Stack Allocation Group |
| 343 | ||
| 344 | # SVE stack frame adjustment | |
| 345 | ADDVL 00000100 001 ..... 01010 ...... ..... @rd_rn_i6 | |
| 346 | ADDPL 00000100 011 ..... 01010 ...... ..... @rd_rn_i6 | |
| 347 | ||
| 348 | # SVE stack frame size | |
| 349 | RDVL 00000100 101 11111 01010 imm:s6 rd:5 | |
| 350 | ||
| d9d78dcc RH |
351 | ### SVE Bitwise Shift - Unpredicated Group |
| 352 | ||
| 353 | # SVE bitwise shift by immediate (unpredicated) | |
| 354 | ASR_zzi 00000100 .. 1 ..... 1001 00 ..... ..... \ | |
| 355 | @rd_rn_tszimm imm=%tszimm16_shr | |
| 356 | LSR_zzi 00000100 .. 1 ..... 1001 01 ..... ..... \ | |
| 357 | @rd_rn_tszimm imm=%tszimm16_shr | |
| 358 | LSL_zzi 00000100 .. 1 ..... 1001 11 ..... ..... \ | |
| 359 | @rd_rn_tszimm imm=%tszimm16_shl | |
| 360 | ||
| 361 | # SVE bitwise shift by wide elements (unpredicated) | |
| 362 | # Note esz != 3 | |
| 363 | ASR_zzw 00000100 .. 1 ..... 1000 00 ..... ..... @rd_rn_rm | |
| 364 | LSR_zzw 00000100 .. 1 ..... 1000 01 ..... ..... @rd_rn_rm | |
| 365 | LSL_zzw 00000100 .. 1 ..... 1000 11 ..... ..... @rd_rn_rm | |
| 366 | ||
| 4b242d9c RH |
367 | ### SVE Compute Vector Address Group |
| 368 | ||
| 369 | # SVE vector address generation | |
| 370 | ADR_s32 00000100 00 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm | |
| 371 | ADR_u32 00000100 01 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm | |
| 372 | ADR_p32 00000100 10 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm | |
| 373 | ADR_p64 00000100 11 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm | |
| 374 | ||
| 0762cd42 RH |
375 | ### SVE Integer Misc - Unpredicated Group |
| 376 | ||
| 377 | # SVE floating-point exponential accelerator | |
| 378 | # Note esz != 0 | |
| 379 | FEXPA 00000100 .. 1 00000 101110 ..... ..... @rd_rn | |
| 380 | ||
| a1f233f2 RH |
381 | # SVE floating-point trig select coefficient |
| 382 | # Note esz != 0 | |
| 383 | FTSSEL 00000100 .. 1 ..... 101100 ..... ..... @rd_rn_rm | |
| 384 | ||
| 24e82e68 RH |
385 | ### SVE Element Count Group |
| 386 | ||
| 387 | # SVE element count | |
| 388 | CNT_r 00000100 .. 10 .... 1110 0 0 ..... ..... @incdec_cnt d=0 u=1 | |
| 389 | ||
| 390 | # SVE inc/dec register by element count | |
| 391 | INCDEC_r 00000100 .. 11 .... 1110 0 d:1 ..... ..... @incdec_cnt u=1 | |
| 392 | ||
| 393 | # SVE saturating inc/dec register by element count | |
| 394 | SINCDEC_r_32 00000100 .. 10 .... 1111 d:1 u:1 ..... ..... @incdec_cnt | |
| 395 | SINCDEC_r_64 00000100 .. 11 .... 1111 d:1 u:1 ..... ..... @incdec_cnt | |
| 396 | ||
| 397 | # SVE inc/dec vector by element count | |
| 398 | # Note this requires esz != 0. | |
| 399 | INCDEC_v 00000100 .. 1 1 .... 1100 0 d:1 ..... ..... @incdec2_cnt u=1 | |
| 400 | ||
| 401 | # SVE saturating inc/dec vector by element count | |
| 402 | # Note these require esz != 0. | |
| 403 | SINCDEC_v 00000100 .. 1 0 .... 1100 d:1 u:1 ..... ..... @incdec2_cnt | |
| 516e246a | 404 | |
| e1fa1164 RH |
405 | ### SVE Bitwise Immediate Group |
| 406 | ||
| 407 | # SVE bitwise logical with immediate (unpredicated) | |
| 408 | ORR_zzi 00000101 00 0000 ............. ..... @rdn_dbm | |
| 409 | EOR_zzi 00000101 01 0000 ............. ..... @rdn_dbm | |
| 410 | AND_zzi 00000101 10 0000 ............. ..... @rdn_dbm | |
| 411 | ||
| 412 | # SVE broadcast bitmask immediate | |
| 413 | DUPM 00000101 11 0000 dbm:13 rd:5 | |
| 414 | ||
| f25a2361 RH |
415 | ### SVE Integer Wide Immediate - Predicated Group |
| 416 | ||
| 417 | # SVE copy floating-point immediate (predicated) | |
| 418 | FCPY 00000101 .. 01 .... 110 imm:8 ..... @rdn_pg4 | |
| 419 | ||
| 420 | # SVE copy integer immediate (predicated) | |
| 421 | CPY_m_i 00000101 .. 01 .... 01 . ........ ..... @rdn_pg4 imm=%sh8_i8s | |
| 422 | CPY_z_i 00000101 .. 01 .... 00 . ........ ..... @rdn_pg4 imm=%sh8_i8s | |
| 423 | ||
| b94f8f60 RH |
424 | ### SVE Permute - Extract Group |
| 425 | ||
| 426 | # SVE extract vector (immediate offset) | |
| 427 | EXT 00000101 001 ..... 000 ... rm:5 rd:5 \ | |
| 428 | &rrri rn=%reg_movprfx imm=%imm8_16_10 | |
| 429 | ||
| 30562ab7 RH |
430 | ### SVE Permute - Unpredicated Group |
| 431 | ||
| 432 | # SVE broadcast general register | |
| 433 | DUP_s 00000101 .. 1 00000 001110 ..... ..... @rd_rn | |
| 434 | ||
| 435 | # SVE broadcast indexed element | |
| 436 | DUP_x 00000101 .. 1 ..... 001000 rn:5 rd:5 \ | |
| 437 | &rri imm=%imm7_22_16 | |
| 438 | ||
| 439 | # SVE insert SIMD&FP scalar register | |
| 440 | INSR_f 00000101 .. 1 10100 001110 ..... ..... @rdn_rm | |
| 441 | ||
| 442 | # SVE insert general register | |
| 443 | INSR_r 00000101 .. 1 00100 001110 ..... ..... @rdn_rm | |
| 444 | ||
| 445 | # SVE reverse vector elements | |
| 446 | REV_v 00000101 .. 1 11000 001110 ..... ..... @rd_rn | |
| 447 | ||
| 448 | # SVE vector table lookup | |
| 449 | TBL 00000101 .. 1 ..... 001100 ..... ..... @rd_rn_rm | |
| 450 | ||
| 451 | # SVE unpack vector elements | |
| 452 | UNPK 00000101 esz:2 1100 u:1 h:1 001110 rn:5 rd:5 | |
| 453 | ||
| d731d8cb RH |
454 | ### SVE Permute - Predicates Group |
| 455 | ||
| 456 | # SVE permute predicate elements | |
| 457 | ZIP1_p 00000101 .. 10 .... 010 000 0 .... 0 .... @pd_pn_pm | |
| 458 | ZIP2_p 00000101 .. 10 .... 010 001 0 .... 0 .... @pd_pn_pm | |
| 459 | UZP1_p 00000101 .. 10 .... 010 010 0 .... 0 .... @pd_pn_pm | |
| 460 | UZP2_p 00000101 .. 10 .... 010 011 0 .... 0 .... @pd_pn_pm | |
| 461 | TRN1_p 00000101 .. 10 .... 010 100 0 .... 0 .... @pd_pn_pm | |
| 462 | TRN2_p 00000101 .. 10 .... 010 101 0 .... 0 .... @pd_pn_pm | |
| 463 | ||
| 464 | # SVE reverse predicate elements | |
| 465 | REV_p 00000101 .. 11 0100 010 000 0 .... 0 .... @pd_pn | |
| 466 | ||
| 467 | # SVE unpack predicate elements | |
| 468 | PUNPKLO 00000101 00 11 0000 010 000 0 .... 0 .... @pd_pn_e0 | |
| 469 | PUNPKHI 00000101 00 11 0001 010 000 0 .... 0 .... @pd_pn_e0 | |
| 470 | ||
| 234b48e9 RH |
471 | ### SVE Permute - Interleaving Group |
| 472 | ||
| 473 | # SVE permute vector elements | |
| 474 | ZIP1_z 00000101 .. 1 ..... 011 000 ..... ..... @rd_rn_rm | |
| 475 | ZIP2_z 00000101 .. 1 ..... 011 001 ..... ..... @rd_rn_rm | |
| 476 | UZP1_z 00000101 .. 1 ..... 011 010 ..... ..... @rd_rn_rm | |
| 477 | UZP2_z 00000101 .. 1 ..... 011 011 ..... ..... @rd_rn_rm | |
| 478 | TRN1_z 00000101 .. 1 ..... 011 100 ..... ..... @rd_rn_rm | |
| 479 | TRN2_z 00000101 .. 1 ..... 011 101 ..... ..... @rd_rn_rm | |
| 480 | ||
| 3ca879ae RH |
481 | ### SVE Permute - Predicated Group |
| 482 | ||
| 483 | # SVE compress active elements | |
| 484 | # Note esz >= 2 | |
| 485 | COMPACT 00000101 .. 100001 100 ... ..... ..... @rd_pg_rn | |
| 486 | ||
| ef23cb72 RH |
487 | # SVE conditionally broadcast element to vector |
| 488 | CLASTA_z 00000101 .. 10100 0 100 ... ..... ..... @rdn_pg_rm | |
| 489 | CLASTB_z 00000101 .. 10100 1 100 ... ..... ..... @rdn_pg_rm | |
| 490 | ||
| 491 | # SVE conditionally copy element to SIMD&FP scalar | |
| 492 | CLASTA_v 00000101 .. 10101 0 100 ... ..... ..... @rd_pg_rn | |
| 493 | CLASTB_v 00000101 .. 10101 1 100 ... ..... ..... @rd_pg_rn | |
| 494 | ||
| 495 | # SVE conditionally copy element to general register | |
| 496 | CLASTA_r 00000101 .. 11000 0 101 ... ..... ..... @rd_pg_rn | |
| 497 | CLASTB_r 00000101 .. 11000 1 101 ... ..... ..... @rd_pg_rn | |
| 498 | ||
| 499 | # SVE copy element to SIMD&FP scalar register | |
| 500 | LASTA_v 00000101 .. 10001 0 100 ... ..... ..... @rd_pg_rn | |
| 501 | LASTB_v 00000101 .. 10001 1 100 ... ..... ..... @rd_pg_rn | |
| 502 | ||
| 503 | # SVE copy element to general register | |
| 504 | LASTA_r 00000101 .. 10000 0 101 ... ..... ..... @rd_pg_rn | |
| 505 | LASTB_r 00000101 .. 10000 1 101 ... ..... ..... @rd_pg_rn | |
| 506 | ||
| 792a5578 RH |
507 | # SVE copy element from SIMD&FP scalar register |
| 508 | CPY_m_v 00000101 .. 100000 100 ... ..... ..... @rd_pg_rn | |
| 509 | ||
| 510 | # SVE copy element from general register to vector (predicated) | |
| 511 | CPY_m_r 00000101 .. 101000 101 ... ..... ..... @rd_pg_rn | |
| 512 | ||
| dae8fb90 RH |
513 | # SVE reverse within elements |
| 514 | # Note esz >= operation size | |
| 515 | REVB 00000101 .. 1001 00 100 ... ..... ..... @rd_pg_rn | |
| 516 | REVH 00000101 .. 1001 01 100 ... ..... ..... @rd_pg_rn | |
| 517 | REVW 00000101 .. 1001 10 100 ... ..... ..... @rd_pg_rn | |
| 518 | RBIT 00000101 .. 1001 11 100 ... ..... ..... @rd_pg_rn | |
| 519 | ||
| b48ff240 RH |
520 | # SVE vector splice (predicated) |
| 521 | SPLICE 00000101 .. 101 100 100 ... ..... ..... @rdn_pg_rm | |
| 522 | ||
| d3fe4a29 RH |
523 | ### SVE Select Vectors Group |
| 524 | ||
| 525 | # SVE select vector elements (predicated) | |
| 526 | SEL_zpzz 00000101 .. 1 ..... 11 .... ..... ..... @rd_pg4_rn_rm | |
| 527 | ||
| 757f9cff RH |
528 | ### SVE Integer Compare - Vectors Group |
| 529 | ||
| 530 | # SVE integer compare_vectors | |
| 531 | CMPHS_ppzz 00100100 .. 0 ..... 000 ... ..... 0 .... @pd_pg_rn_rm | |
| 532 | CMPHI_ppzz 00100100 .. 0 ..... 000 ... ..... 1 .... @pd_pg_rn_rm | |
| 533 | CMPGE_ppzz 00100100 .. 0 ..... 100 ... ..... 0 .... @pd_pg_rn_rm | |
| 534 | CMPGT_ppzz 00100100 .. 0 ..... 100 ... ..... 1 .... @pd_pg_rn_rm | |
| 535 | CMPEQ_ppzz 00100100 .. 0 ..... 101 ... ..... 0 .... @pd_pg_rn_rm | |
| 536 | CMPNE_ppzz 00100100 .. 0 ..... 101 ... ..... 1 .... @pd_pg_rn_rm | |
| 537 | ||
| 538 | # SVE integer compare with wide elements | |
| 539 | # Note these require esz != 3. | |
| 540 | CMPEQ_ppzw 00100100 .. 0 ..... 001 ... ..... 0 .... @pd_pg_rn_rm | |
| 541 | CMPNE_ppzw 00100100 .. 0 ..... 001 ... ..... 1 .... @pd_pg_rn_rm | |
| 542 | CMPGE_ppzw 00100100 .. 0 ..... 010 ... ..... 0 .... @pd_pg_rn_rm | |
| 543 | CMPGT_ppzw 00100100 .. 0 ..... 010 ... ..... 1 .... @pd_pg_rn_rm | |
| 544 | CMPLT_ppzw 00100100 .. 0 ..... 011 ... ..... 0 .... @pd_pg_rn_rm | |
| 545 | CMPLE_ppzw 00100100 .. 0 ..... 011 ... ..... 1 .... @pd_pg_rn_rm | |
| 546 | CMPHS_ppzw 00100100 .. 0 ..... 110 ... ..... 0 .... @pd_pg_rn_rm | |
| 547 | CMPHI_ppzw 00100100 .. 0 ..... 110 ... ..... 1 .... @pd_pg_rn_rm | |
| 548 | CMPLO_ppzw 00100100 .. 0 ..... 111 ... ..... 0 .... @pd_pg_rn_rm | |
| 549 | CMPLS_ppzw 00100100 .. 0 ..... 111 ... ..... 1 .... @pd_pg_rn_rm | |
| 550 | ||
| 38cadeba RH |
551 | ### SVE Integer Compare - Unsigned Immediate Group |
| 552 | ||
| 553 | # SVE integer compare with unsigned immediate | |
| 554 | CMPHS_ppzi 00100100 .. 1 ....... 0 ... ..... 0 .... @pd_pg_rn_i7 | |
| 555 | CMPHI_ppzi 00100100 .. 1 ....... 0 ... ..... 1 .... @pd_pg_rn_i7 | |
| 556 | CMPLO_ppzi 00100100 .. 1 ....... 1 ... ..... 0 .... @pd_pg_rn_i7 | |
| 557 | CMPLS_ppzi 00100100 .. 1 ....... 1 ... ..... 1 .... @pd_pg_rn_i7 | |
| 558 | ||
| 559 | ### SVE Integer Compare - Signed Immediate Group | |
| 560 | ||
| 561 | # SVE integer compare with signed immediate | |
| 562 | CMPGE_ppzi 00100101 .. 0 ..... 000 ... ..... 0 .... @pd_pg_rn_i5 | |
| 563 | CMPGT_ppzi 00100101 .. 0 ..... 000 ... ..... 1 .... @pd_pg_rn_i5 | |
| 564 | CMPLT_ppzi 00100101 .. 0 ..... 001 ... ..... 0 .... @pd_pg_rn_i5 | |
| 565 | CMPLE_ppzi 00100101 .. 0 ..... 001 ... ..... 1 .... @pd_pg_rn_i5 | |
| 566 | CMPEQ_ppzi 00100101 .. 0 ..... 100 ... ..... 0 .... @pd_pg_rn_i5 | |
| 567 | CMPNE_ppzi 00100101 .. 0 ..... 100 ... ..... 1 .... @pd_pg_rn_i5 | |
| 568 | ||
| e1fa1164 RH |
569 | ### SVE Predicate Logical Operations Group |
| 570 | ||
| 516e246a RH |
571 | # SVE predicate logical operations |
| 572 | AND_pppp 00100101 0. 00 .... 01 .... 0 .... 0 .... @pd_pg_pn_pm_s | |
| 573 | BIC_pppp 00100101 0. 00 .... 01 .... 0 .... 1 .... @pd_pg_pn_pm_s | |
| 574 | EOR_pppp 00100101 0. 00 .... 01 .... 1 .... 0 .... @pd_pg_pn_pm_s | |
| 575 | SEL_pppp 00100101 0. 00 .... 01 .... 1 .... 1 .... @pd_pg_pn_pm_s | |
| 576 | ORR_pppp 00100101 1. 00 .... 01 .... 0 .... 0 .... @pd_pg_pn_pm_s | |
| 577 | ORN_pppp 00100101 1. 00 .... 01 .... 0 .... 1 .... @pd_pg_pn_pm_s | |
| 578 | NOR_pppp 00100101 1. 00 .... 01 .... 1 .... 0 .... @pd_pg_pn_pm_s | |
| 579 | NAND_pppp 00100101 1. 00 .... 01 .... 1 .... 1 .... @pd_pg_pn_pm_s | |
| 580 | ||
| 9e18d7a6 RH |
581 | ### SVE Predicate Misc Group |
| 582 | ||
| 583 | # SVE predicate test | |
| 584 | PTEST 00100101 01 010000 11 pg:4 0 rn:4 0 0000 | |
| 585 | ||
| 028e2a7b RH |
586 | # SVE predicate initialize |
| 587 | PTRUE 00100101 esz:2 01100 s:1 111000 pat:5 0 rd:4 | |
| 588 | ||
| 589 | # SVE initialize FFR | |
| 590 | SETFFR 00100101 0010 1100 1001 0000 0000 0000 | |
| 591 | ||
| 592 | # SVE zero predicate register | |
| 593 | PFALSE 00100101 0001 1000 1110 0100 0000 rd:4 | |
| 594 | ||
| 595 | # SVE predicate read from FFR (predicated) | |
| 596 | RDFFR_p 00100101 0 s:1 0110001111000 pg:4 0 rd:4 | |
| 597 | ||
| 598 | # SVE predicate read from FFR (unpredicated) | |
| 599 | RDFFR 00100101 0001 1001 1111 0000 0000 rd:4 | |
| 600 | ||
| 601 | # SVE FFR write from predicate (WRFFR) | |
| 602 | WRFFR 00100101 0010 1000 1001 000 rn:4 00000 | |
| 603 | ||
| 604 | # SVE predicate first active | |
| 605 | PFIRST 00100101 01 011 000 11000 00 .... 0 .... @pd_pn_e0 | |
| 606 | ||
| 607 | # SVE predicate next active | |
| 608 | PNEXT 00100101 .. 011 001 11000 10 .... 0 .... @pd_pn | |
| 609 | ||
| 35da316f RH |
610 | ### SVE Partition Break Group |
| 611 | ||
| 612 | # SVE propagate break from previous partition | |
| 613 | BRKPA 00100101 0. 00 .... 11 .... 0 .... 0 .... @pd_pg_pn_pm_s | |
| 614 | BRKPB 00100101 0. 00 .... 11 .... 0 .... 1 .... @pd_pg_pn_pm_s | |
| 615 | ||
| 616 | # SVE partition break condition | |
| 617 | BRKA_z 00100101 0. 01000001 .... 0 .... 0 .... @pd_pg_pn_s | |
| 618 | BRKB_z 00100101 1. 01000001 .... 0 .... 0 .... @pd_pg_pn_s | |
| 619 | BRKA_m 00100101 0. 01000001 .... 0 .... 1 .... @pd_pg_pn_s | |
| 620 | BRKB_m 00100101 1. 01000001 .... 0 .... 1 .... @pd_pg_pn_s | |
| 621 | ||
| 622 | # SVE propagate break to next partition | |
| 623 | BRKN 00100101 0. 01100001 .... 0 .... 0 .... @pd_pg_pn_s | |
| 624 | ||
| 9ee3a611 RH |
625 | ### SVE Predicate Count Group |
| 626 | ||
| 627 | # SVE predicate count | |
| 628 | CNTP 00100101 .. 100 000 10 .... 0 .... ..... @rd_pg4_pn | |
| 629 | ||
| 630 | # SVE inc/dec register by predicate count | |
| 631 | INCDECP_r 00100101 .. 10110 d:1 10001 00 .... ..... @incdec_pred u=1 | |
| 632 | ||
| 633 | # SVE inc/dec vector by predicate count | |
| 634 | INCDECP_z 00100101 .. 10110 d:1 10000 00 .... ..... @incdec2_pred u=1 | |
| 635 | ||
| 636 | # SVE saturating inc/dec register by predicate count | |
| 637 | SINCDECP_r_32 00100101 .. 1010 d:1 u:1 10001 00 .... ..... @incdec_pred | |
| 638 | SINCDECP_r_64 00100101 .. 1010 d:1 u:1 10001 10 .... ..... @incdec_pred | |
| 639 | ||
| 640 | # SVE saturating inc/dec vector by predicate count | |
| 641 | SINCDECP_z 00100101 .. 1010 d:1 u:1 10000 00 .... ..... @incdec2_pred | |
| 642 | ||
| caf1cefc RH |
643 | ### SVE Integer Compare - Scalars Group |
| 644 | ||
| 645 | # SVE conditionally terminate scalars | |
| 646 | CTERM 00100101 1 sf:1 1 rm:5 001000 rn:5 ne:1 0000 | |
| 647 | ||
| 648 | # SVE integer compare scalar count and limit | |
| 649 | WHILE 00100101 esz:2 1 rm:5 000 sf:1 u:1 1 rn:5 eq:1 rd:4 | |
| 650 | ||
| ed491961 RH |
651 | ### SVE Integer Wide Immediate - Unpredicated Group |
| 652 | ||
| 653 | # SVE broadcast floating-point immediate (unpredicated) | |
| 654 | FDUP 00100101 esz:2 111 00 1110 imm:8 rd:5 | |
| 655 | ||
| 656 | # SVE broadcast integer immediate (unpredicated) | |
| 657 | DUP_i 00100101 esz:2 111 00 011 . ........ rd:5 imm=%sh8_i8s | |
| 658 | ||
| 6e6a157d RH |
659 | # SVE integer add/subtract immediate (unpredicated) |
| 660 | ADD_zzi 00100101 .. 100 000 11 . ........ ..... @rdn_sh_i8u | |
| 661 | SUB_zzi 00100101 .. 100 001 11 . ........ ..... @rdn_sh_i8u | |
| 662 | SUBR_zzi 00100101 .. 100 011 11 . ........ ..... @rdn_sh_i8u | |
| 663 | SQADD_zzi 00100101 .. 100 100 11 . ........ ..... @rdn_sh_i8u | |
| 664 | UQADD_zzi 00100101 .. 100 101 11 . ........ ..... @rdn_sh_i8u | |
| 665 | SQSUB_zzi 00100101 .. 100 110 11 . ........ ..... @rdn_sh_i8u | |
| 666 | UQSUB_zzi 00100101 .. 100 111 11 . ........ ..... @rdn_sh_i8u | |
| 667 | ||
| 668 | # SVE integer min/max immediate (unpredicated) | |
| 669 | SMAX_zzi 00100101 .. 101 000 110 ........ ..... @rdn_i8s | |
| 670 | UMAX_zzi 00100101 .. 101 001 110 ........ ..... @rdn_i8u | |
| 671 | SMIN_zzi 00100101 .. 101 010 110 ........ ..... @rdn_i8s | |
| 672 | UMIN_zzi 00100101 .. 101 011 110 ........ ..... @rdn_i8u | |
| 673 | ||
| 674 | # SVE integer multiply immediate (unpredicated) | |
| 675 | MUL_zzi 00100101 .. 110 000 110 ........ ..... @rdn_i8s | |
| 676 | ||
| 29b80469 RH |
677 | ### SVE Floating Point Arithmetic - Unpredicated Group |
| 678 | ||
| 679 | # SVE floating-point arithmetic (unpredicated) | |
| 680 | FADD_zzz 01100101 .. 0 ..... 000 000 ..... ..... @rd_rn_rm | |
| 681 | FSUB_zzz 01100101 .. 0 ..... 000 001 ..... ..... @rd_rn_rm | |
| 682 | FMUL_zzz 01100101 .. 0 ..... 000 010 ..... ..... @rd_rn_rm | |
| 683 | FTSMUL 01100101 .. 0 ..... 000 011 ..... ..... @rd_rn_rm | |
| 684 | FRECPS 01100101 .. 0 ..... 000 110 ..... ..... @rd_rn_rm | |
| 685 | FRSQRTS 01100101 .. 0 ..... 000 111 ..... ..... @rd_rn_rm | |
| 686 | ||
| ec3b87c2 RH |
687 | ### SVE FP Arithmetic Predicated Group |
| 688 | ||
| 689 | # SVE floating-point arithmetic (predicated) | |
| 690 | FADD_zpzz 01100101 .. 00 0000 100 ... ..... ..... @rdn_pg_rm | |
| 691 | FSUB_zpzz 01100101 .. 00 0001 100 ... ..... ..... @rdn_pg_rm | |
| 692 | FMUL_zpzz 01100101 .. 00 0010 100 ... ..... ..... @rdn_pg_rm | |
| 693 | FSUB_zpzz 01100101 .. 00 0011 100 ... ..... ..... @rdm_pg_rn # FSUBR | |
| 694 | FMAXNM_zpzz 01100101 .. 00 0100 100 ... ..... ..... @rdn_pg_rm | |
| 695 | FMINNM_zpzz 01100101 .. 00 0101 100 ... ..... ..... @rdn_pg_rm | |
| 696 | FMAX_zpzz 01100101 .. 00 0110 100 ... ..... ..... @rdn_pg_rm | |
| 697 | FMIN_zpzz 01100101 .. 00 0111 100 ... ..... ..... @rdn_pg_rm | |
| 698 | FABD 01100101 .. 00 1000 100 ... ..... ..... @rdn_pg_rm | |
| 699 | FSCALE 01100101 .. 00 1001 100 ... ..... ..... @rdn_pg_rm | |
| 700 | FMULX 01100101 .. 00 1010 100 ... ..... ..... @rdn_pg_rm | |
| 701 | FDIV 01100101 .. 00 1100 100 ... ..... ..... @rdm_pg_rn # FDIVR | |
| 702 | FDIV 01100101 .. 00 1101 100 ... ..... ..... @rdn_pg_rm | |
| 703 | ||
| 8092c6a3 RH |
704 | ### SVE FP Unary Operations Predicated Group |
| 705 | ||
| 706 | # SVE integer convert to floating-point | |
| 707 | SCVTF_hh 01100101 01 010 01 0 101 ... ..... ..... @rd_pg_rn_e0 | |
| 708 | SCVTF_sh 01100101 01 010 10 0 101 ... ..... ..... @rd_pg_rn_e0 | |
| 709 | SCVTF_dh 01100101 01 010 11 0 101 ... ..... ..... @rd_pg_rn_e0 | |
| 710 | SCVTF_ss 01100101 10 010 10 0 101 ... ..... ..... @rd_pg_rn_e0 | |
| 711 | SCVTF_sd 01100101 11 010 00 0 101 ... ..... ..... @rd_pg_rn_e0 | |
| 712 | SCVTF_ds 01100101 11 010 10 0 101 ... ..... ..... @rd_pg_rn_e0 | |
| 713 | SCVTF_dd 01100101 11 010 11 0 101 ... ..... ..... @rd_pg_rn_e0 | |
| 714 | ||
| 715 | UCVTF_hh 01100101 01 010 01 1 101 ... ..... ..... @rd_pg_rn_e0 | |
| 716 | UCVTF_sh 01100101 01 010 10 1 101 ... ..... ..... @rd_pg_rn_e0 | |
| 717 | UCVTF_dh 01100101 01 010 11 1 101 ... ..... ..... @rd_pg_rn_e0 | |
| 718 | UCVTF_ss 01100101 10 010 10 1 101 ... ..... ..... @rd_pg_rn_e0 | |
| 719 | UCVTF_sd 01100101 11 010 00 1 101 ... ..... ..... @rd_pg_rn_e0 | |
| 720 | UCVTF_ds 01100101 11 010 10 1 101 ... ..... ..... @rd_pg_rn_e0 | |
| 721 | UCVTF_dd 01100101 11 010 11 1 101 ... ..... ..... @rd_pg_rn_e0 | |
| 722 | ||
| d1822297 RH |
723 | ### SVE Memory - 32-bit Gather and Unsized Contiguous Group |
| 724 | ||
| 725 | # SVE load predicate register | |
| 726 | LDR_pri 10000101 10 ...... 000 ... ..... 0 .... @pd_rn_i9 | |
| 727 | ||
| 728 | # SVE load vector register | |
| 729 | LDR_zri 10000101 10 ...... 010 ... ..... ..... @rd_rn_i9 | |
| c4e7c493 RH |
730 | |
| 731 | ### SVE Memory Contiguous Load Group | |
| 732 | ||
| 733 | # SVE contiguous load (scalar plus scalar) | |
| 734 | LD_zprr 1010010 .... ..... 010 ... ..... ..... @rprr_load_dt nreg=0 | |
| 735 | ||
| e2654d75 RH |
736 | # SVE contiguous first-fault load (scalar plus scalar) |
| 737 | LDFF1_zprr 1010010 .... ..... 011 ... ..... ..... @rprr_load_dt nreg=0 | |
| 738 | ||
| c4e7c493 RH |
739 | # SVE contiguous load (scalar plus immediate) |
| 740 | LD_zpri 1010010 .... 0.... 101 ... ..... ..... @rpri_load_dt nreg=0 | |
| 741 | ||
| e2654d75 RH |
742 | # SVE contiguous non-fault load (scalar plus immediate) |
| 743 | LDNF1_zpri 1010010 .... 1.... 101 ... ..... ..... @rpri_load_dt nreg=0 | |
| 744 | ||
| c4e7c493 RH |
745 | # SVE contiguous non-temporal load (scalar plus scalar) |
| 746 | # LDNT1B, LDNT1H, LDNT1W, LDNT1D | |
| 747 | # SVE load multiple structures (scalar plus scalar) | |
| 748 | # LD2B, LD2H, LD2W, LD2D; etc. | |
| 749 | LD_zprr 1010010 .. nreg:2 ..... 110 ... ..... ..... @rprr_load_msz | |
| 750 | ||
| 751 | # SVE contiguous non-temporal load (scalar plus immediate) | |
| 752 | # LDNT1B, LDNT1H, LDNT1W, LDNT1D | |
| 753 | # SVE load multiple structures (scalar plus immediate) | |
| 754 | # LD2B, LD2H, LD2W, LD2D; etc. | |
| 755 | LD_zpri 1010010 .. nreg:2 0.... 111 ... ..... ..... @rpri_load_msz | |
| 1a039c7e | 756 | |
| 05abe304 RH |
757 | # SVE load and broadcast quadword (scalar plus scalar) |
| 758 | LD1RQ_zprr 1010010 .. 00 ..... 000 ... ..... ..... \ | |
| 759 | @rprr_load_msz nreg=0 | |
| 760 | ||
| 761 | # SVE load and broadcast quadword (scalar plus immediate) | |
| 762 | # LD1RQB, LD1RQH, LD1RQS, LD1RQD | |
| 763 | LD1RQ_zpri 1010010 .. 00 0.... 001 ... ..... ..... \ | |
| 764 | @rpri_load_msz nreg=0 | |
| 765 | ||
| 1a039c7e RH |
766 | ### SVE Memory Store Group |
| 767 | ||
| 768 | # SVE contiguous store (scalar plus immediate) | |
| 769 | # ST1B, ST1H, ST1W, ST1D; require msz <= esz | |
| 770 | ST_zpri 1110010 .. esz:2 0.... 111 ... ..... ..... \ | |
| 771 | @rpri_store_msz nreg=0 | |
| 772 | ||
| 773 | # SVE contiguous store (scalar plus scalar) | |
| 774 | # ST1B, ST1H, ST1W, ST1D; require msz <= esz | |
| 775 | # Enumerate msz lest we conflict with STR_zri. | |
| 776 | ST_zprr 1110010 00 .. ..... 010 ... ..... ..... \ | |
| 777 | @rprr_store_esz_n0 msz=0 | |
| 778 | ST_zprr 1110010 01 .. ..... 010 ... ..... ..... \ | |
| 779 | @rprr_store_esz_n0 msz=1 | |
| 780 | ST_zprr 1110010 10 .. ..... 010 ... ..... ..... \ | |
| 781 | @rprr_store_esz_n0 msz=2 | |
| 782 | ST_zprr 1110010 11 11 ..... 010 ... ..... ..... \ | |
| 783 | @rprr_store msz=3 esz=3 nreg=0 | |
| 784 | ||
| 785 | # SVE contiguous non-temporal store (scalar plus immediate) (nreg == 0) | |
| 786 | # SVE store multiple structures (scalar plus immediate) (nreg != 0) | |
| 787 | ST_zpri 1110010 .. nreg:2 1.... 111 ... ..... ..... \ | |
| 788 | @rpri_store_msz esz=%size_23 | |
| 789 | ||
| 790 | # SVE contiguous non-temporal store (scalar plus scalar) (nreg == 0) | |
| 791 | # SVE store multiple structures (scalar plus scalar) (nreg != 0) | |
| 792 | ST_zprr 1110010 msz:2 nreg:2 ..... 011 ... ..... ..... \ | |
| 793 | @rprr_store esz=%size_23 |