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target/arm: Convert T16, Conditional branches, Supervisor call
[mirror_qemu.git] / target / arm / t16.decode
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f97b454e
RH		 1# Thumb1 instructions
2#
3# Copyright (c) 2019 Linaro, Ltd
4#
5# This library is free software; you can redistribute it and/or
6# modify it under the terms of the GNU Lesser General Public
7# License as published by the Free Software Foundation; either
8# version 2 of the License, or (at your option) any later version.
9#
10# This library is distributed in the hope that it will be useful,
11# but WITHOUT ANY WARRANTY; without even the implied warranty of
12# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13# Lesser General Public License for more details.
14#
15# You should have received a copy of the GNU Lesser General Public
16# License along with this library; if not, see <http://www.gnu.org/licenses/>.
17
18#
19# This file is processed by scripts/decodetree.py
20#
080c4ead 21
56e6250e 22&empty !extern
080c4ead
RH		 23&s_rrr_shi !extern s rd rn rm shim shty
24&s_rrr_shr !extern s rn rd rm rs shty
25&s_rri_rot !extern s rn rd imm rot
26&s_rrrr !extern s rd rn rm ra
e6f69612 27&rrr_rot !extern rd rn rm rot
ae3002b0 28&rr !extern rd rm
1cb13234 29&ri !extern rd imm
a0ef0774 30&r !extern rm
629fcaa7 31&i !extern imm
d1d22917 32&ldst_rr !extern p w u rn rt rm shimm shtype
07afd747 33&ldst_ri !extern p w u rn rt imm
6e8514ba 34&ldst_block !extern rn i b u w list
20556e7b
RH		 35&setend !extern E
36&cps !extern mode imod M A I F
629fcaa7 37&ci !extern cond imm
080c4ead
RH		 38
39# Set S if the instruction is outside of an IT block.
40%s !function=t16_setflags
41
42# Data-processing (two low registers)
43
44%reg_0 0:3
45
46@lll_noshr ...... .... rm:3 rd:3 \
47 &s_rrr_shi %s rn=%reg_0 shim=0 shty=0
48@xll_noshr ...... .... rm:3 rn:3 \
49 &s_rrr_shi s=1 rd=0 shim=0 shty=0
50@lxl_shr ...... .... rs:3 rd:3 \
51 &s_rrr_shr %s rm=%reg_0 rn=0
52
53AND_rrri 010000 0000 ... ... @lll_noshr
54EOR_rrri 010000 0001 ... ... @lll_noshr
55MOV_rxrr 010000 0010 ... ... @lxl_shr shty=0 # LSL
56MOV_rxrr 010000 0011 ... ... @lxl_shr shty=1 # LSR
57MOV_rxrr 010000 0100 ... ... @lxl_shr shty=2 # ASR
58ADC_rrri 010000 0101 ... ... @lll_noshr
59SBC_rrri 010000 0110 ... ... @lll_noshr
60MOV_rxrr 010000 0111 ... ... @lxl_shr shty=3 # ROR
61TST_xrri 010000 1000 ... ... @xll_noshr
62RSB_rri 010000 1001 rn:3 rd:3 &s_rri_rot %s imm=0 rot=0
63CMP_xrri 010000 1010 ... ... @xll_noshr
64CMN_xrri 010000 1011 ... ... @xll_noshr
65ORR_rrri 010000 1100 ... ... @lll_noshr
66MUL 010000 1101 rn:3 rd:3 &s_rrrr %s rm=%reg_0 ra=0
67BIC_rrri 010000 1110 ... ... @lll_noshr
68MVN_rxri 010000 1111 ... ... @lll_noshr
d1d22917
RH		 69
70# Load/store (register offset)
71
72@ldst_rr ....... rm:3 rn:3 rt:3 \
73 &ldst_rr p=1 w=0 u=1 shimm=0 shtype=0
74
75STR_rr 0101 000 ... ... ... @ldst_rr
76STRH_rr 0101 001 ... ... ... @ldst_rr
77STRB_rr 0101 010 ... ... ... @ldst_rr
78LDRSB_rr 0101 011 ... ... ... @ldst_rr
79LDR_rr 0101 100 ... ... ... @ldst_rr
80LDRH_rr 0101 101 ... ... ... @ldst_rr
81LDRB_rr 0101 110 ... ... ... @ldst_rr
82LDRSH_rr 0101 111 ... ... ... @ldst_rr
07afd747
RH		 83
84# Load/store word/byte (immediate offset)
85
86%imm5_6x4 6:5 !function=times_4
87
88@ldst_ri_1 ..... imm:5 rn:3 rt:3 \
89 &ldst_ri p=1 w=0 u=1
90@ldst_ri_4 ..... ..... rn:3 rt:3 \
91 &ldst_ri p=1 w=0 u=1 imm=%imm5_6x4
92
93STR_ri 01100 ..... ... ... @ldst_ri_4
94LDR_ri 01101 ..... ... ... @ldst_ri_4
95STRB_ri 01110 ..... ... ... @ldst_ri_1
96LDRB_ri 01111 ..... ... ... @ldst_ri_1
97
98# Load/store halfword (immediate offset)
99
100%imm5_6x2 6:5 !function=times_2
101@ldst_ri_2 ..... ..... rn:3 rt:3 \
102 &ldst_ri p=1 w=0 u=1 imm=%imm5_6x2
103
104STRH_ri 10000 ..... ... ... @ldst_ri_2
105LDRH_ri 10001 ..... ... ... @ldst_ri_2
106
107# Load/store (SP-relative)
108
109%imm8_0x4 0:8 !function=times_4
110@ldst_spec_i ..... rt:3 ........ \
111 &ldst_ri p=1 w=0 u=1 imm=%imm8_0x4
112
113STR_ri 10010 ... ........ @ldst_spec_i rn=13
114LDR_ri 10011 ... ........ @ldst_spec_i rn=13
1cb13234
RH		 115
116# Add PC/SP (immediate)
117
118ADR 10100 rd:3 ........ imm=%imm8_0x4
119ADD_rri 10101 rd:3 ........ \
120 &s_rri_rot rn=13 s=0 rot=0 imm=%imm8_0x4 # SP
6e8514ba
RH		 121
122# Load/store multiple
123
124@ldstm ..... rn:3 list:8 &ldst_block i=1 b=0 u=0 w=1
125
126STM 11000 ... ........ @ldstm
127LDM_t16 11001 ... ........ @ldstm
c4d3095b
RH		 128
129# Add/subtract (three low registers)
130
131@addsub_3 ....... rm:3 rn:3 rd:3 \
132 &s_rrr_shi %s shim=0 shty=0
133
134ADD_rrri 0001100 ... ... ... @addsub_3
135SUB_rrri 0001101 ... ... ... @addsub_3
136
137# Add/subtract (two low registers and immediate)
138
139@addsub_2i ....... imm:3 rn:3 rd:3 \
140 &s_rri_rot %s rot=0
141
142ADD_rri 0001 110 ... ... ... @addsub_2i
143SUB_rri 0001 111 ... ... ... @addsub_2i
6c6d237a
RH		 144
145# Add, subtract, compare, move (one low register and immediate)
146
147%reg_8 8:3
148@arith_1i ..... rd:3 imm:8 \
149 &s_rri_rot rot=0 rn=%reg_8
150
151MOV_rxi 00100 ... ........ @arith_1i %s
152CMP_xri 00101 ... ........ @arith_1i s=1
153ADD_rri 00110 ... ........ @arith_1i %s
154SUB_rri 00111 ... ........ @arith_1i %s
a0ef0774 155
90aa0421
RH		 156# Add, compare, move (two high registers)
157
158%reg_0_7 7:1 0:3
159@addsub_2h .... .... . rm:4 ... \
160 &s_rrr_shi rd=%reg_0_7 rn=%reg_0_7 shim=0 shty=0
161
162ADD_rrri 0100 0100 . .... ... @addsub_2h s=0
163CMP_xrri 0100 0101 . .... ... @addsub_2h s=1
164MOV_rxri 0100 0110 . .... ... @addsub_2h s=0
165
2e6a646d
RH		 166# Adjust SP (immediate)
167
168%imm7_0x4 0:7 !function=times_4
169@addsub_sp_i .... .... . ....... \
170 &s_rri_rot s=0 rd=13 rn=13 rot=0 imm=%imm7_0x4
171
172ADD_rri 1011 0000 0 ....... @addsub_sp_i
173SUB_rri 1011 0000 1 ....... @addsub_sp_i
174
a0ef0774
RH		 175# Branch and exchange
176
177@branchr .... .... . rm:4 ... &r
178
179BX 0100 0111 0 .... 000 @branchr
180BLX_r 0100 0111 1 .... 000 @branchr
181BXNS 0100 0111 0 .... 100 @branchr
182BLXNS 0100 0111 1 .... 100 @branchr
e6f69612
RH		 183
184# Extend
185
186@extend .... .... .. rm:3 rd:3 &rrr_rot rn=15 rot=0
187
188SXTAH 1011 0010 00 ... ... @extend
189SXTAB 1011 0010 01 ... ... @extend
190UXTAH 1011 0010 10 ... ... @extend
191UXTAB 1011 0010 11 ... ... @extend
20556e7b
RH		 192
193# Change processor state
194
195%imod 4:1 !function=plus_2
196
197SETEND 1011 0110 010 1 E:1 000 &setend
198{
199 CPS 1011 0110 011 . 0 A:1 I:1 F:1 &cps mode=0 M=0 %imod
200 CPS_v7m 1011 0110 011 im:1 00 I:1 F:1
201}
ae3002b0
RH		 202
203# Reverse bytes
204
205@rdm .... .... .. rm:3 rd:3 &rr
206
207REV 1011 1010 00 ... ... @rdm
208REV16 1011 1010 01 ... ... @rdm
209REVSH 1011 1010 11 ... ... @rdm
56e6250e
RH		 210
211# Hints
212
213{
214 YIELD 1011 1111 0001 0000
215 WFE 1011 1111 0010 0000
216 WFI 1011 1111 0011 0000
217
218 # TODO: Implement SEV, SEVL; may help SMP performance.
219 # SEV 1011 1111 0100 0000
220 # SEVL 1011 1111 0101 0000
221
222 # The canonical nop has the second nibble as 0000, but the whole of the
223 # rest of the space is a reserved hint, behaves as nop.
224 NOP 1011 1111 ---- 0000
225}
564b125f
RH		 226
227# Push and Pop
228
229%push_list 0:9 !function=t16_push_list
230%pop_list 0:9 !function=t16_pop_list
231
232STM 1011 010 ......... \
233 &ldst_block i=0 b=1 u=0 w=1 rn=13 list=%push_list
234LDM_t16 1011 110 ......... \
235 &ldst_block i=1 b=0 u=0 w=1 rn=13 list=%pop_list
629fcaa7
RH		 236
237# Conditional branches, Supervisor call
238
239%imm8_0x2 0:s8 !function=times_2
240
241{
242 UDF 1101 1110 ---- ----
243 SVC 1101 1111 imm:8 &i
244 B_cond_thumb 1101 cond:4 ........ &ci imm=%imm8_0x2
245}
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