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target/arm: Convert T16 add, compare, move (two high registers)
[mirror_qemu.git] / target / arm / t16.decode
CommitLineData
f97b454e
RH		 1# Thumb1 instructions
2#
3# Copyright (c) 2019 Linaro, Ltd
4#
5# This library is free software; you can redistribute it and/or
6# modify it under the terms of the GNU Lesser General Public
7# License as published by the Free Software Foundation; either
8# version 2 of the License, or (at your option) any later version.
9#
10# This library is distributed in the hope that it will be useful,
11# but WITHOUT ANY WARRANTY; without even the implied warranty of
12# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13# Lesser General Public License for more details.
14#
15# You should have received a copy of the GNU Lesser General Public
16# License along with this library; if not, see <http://www.gnu.org/licenses/>.
17
18#
19# This file is processed by scripts/decodetree.py
20#
080c4ead
RH		 21
22&s_rrr_shi !extern s rd rn rm shim shty
23&s_rrr_shr !extern s rn rd rm rs shty
24&s_rri_rot !extern s rn rd imm rot
25&s_rrrr !extern s rd rn rm ra
1cb13234 26&ri !extern rd imm
a0ef0774 27&r !extern rm
d1d22917 28&ldst_rr !extern p w u rn rt rm shimm shtype
07afd747 29&ldst_ri !extern p w u rn rt imm
6e8514ba 30&ldst_block !extern rn i b u w list
080c4ead
RH		 31
32# Set S if the instruction is outside of an IT block.
33%s !function=t16_setflags
34
35# Data-processing (two low registers)
36
37%reg_0 0:3
38
39@lll_noshr ...... .... rm:3 rd:3 \
40 &s_rrr_shi %s rn=%reg_0 shim=0 shty=0
41@xll_noshr ...... .... rm:3 rn:3 \
42 &s_rrr_shi s=1 rd=0 shim=0 shty=0
43@lxl_shr ...... .... rs:3 rd:3 \
44 &s_rrr_shr %s rm=%reg_0 rn=0
45
46AND_rrri 010000 0000 ... ... @lll_noshr
47EOR_rrri 010000 0001 ... ... @lll_noshr
48MOV_rxrr 010000 0010 ... ... @lxl_shr shty=0 # LSL
49MOV_rxrr 010000 0011 ... ... @lxl_shr shty=1 # LSR
50MOV_rxrr 010000 0100 ... ... @lxl_shr shty=2 # ASR
51ADC_rrri 010000 0101 ... ... @lll_noshr
52SBC_rrri 010000 0110 ... ... @lll_noshr
53MOV_rxrr 010000 0111 ... ... @lxl_shr shty=3 # ROR
54TST_xrri 010000 1000 ... ... @xll_noshr
55RSB_rri 010000 1001 rn:3 rd:3 &s_rri_rot %s imm=0 rot=0
56CMP_xrri 010000 1010 ... ... @xll_noshr
57CMN_xrri 010000 1011 ... ... @xll_noshr
58ORR_rrri 010000 1100 ... ... @lll_noshr
59MUL 010000 1101 rn:3 rd:3 &s_rrrr %s rm=%reg_0 ra=0
60BIC_rrri 010000 1110 ... ... @lll_noshr
61MVN_rxri 010000 1111 ... ... @lll_noshr
d1d22917
RH		 62
63# Load/store (register offset)
64
65@ldst_rr ....... rm:3 rn:3 rt:3 \
66 &ldst_rr p=1 w=0 u=1 shimm=0 shtype=0
67
68STR_rr 0101 000 ... ... ... @ldst_rr
69STRH_rr 0101 001 ... ... ... @ldst_rr
70STRB_rr 0101 010 ... ... ... @ldst_rr
71LDRSB_rr 0101 011 ... ... ... @ldst_rr
72LDR_rr 0101 100 ... ... ... @ldst_rr
73LDRH_rr 0101 101 ... ... ... @ldst_rr
74LDRB_rr 0101 110 ... ... ... @ldst_rr
75LDRSH_rr 0101 111 ... ... ... @ldst_rr
07afd747
RH		 76
77# Load/store word/byte (immediate offset)
78
79%imm5_6x4 6:5 !function=times_4
80
81@ldst_ri_1 ..... imm:5 rn:3 rt:3 \
82 &ldst_ri p=1 w=0 u=1
83@ldst_ri_4 ..... ..... rn:3 rt:3 \
84 &ldst_ri p=1 w=0 u=1 imm=%imm5_6x4
85
86STR_ri 01100 ..... ... ... @ldst_ri_4
87LDR_ri 01101 ..... ... ... @ldst_ri_4
88STRB_ri 01110 ..... ... ... @ldst_ri_1
89LDRB_ri 01111 ..... ... ... @ldst_ri_1
90
91# Load/store halfword (immediate offset)
92
93%imm5_6x2 6:5 !function=times_2
94@ldst_ri_2 ..... ..... rn:3 rt:3 \
95 &ldst_ri p=1 w=0 u=1 imm=%imm5_6x2
96
97STRH_ri 10000 ..... ... ... @ldst_ri_2
98LDRH_ri 10001 ..... ... ... @ldst_ri_2
99
100# Load/store (SP-relative)
101
102%imm8_0x4 0:8 !function=times_4
103@ldst_spec_i ..... rt:3 ........ \
104 &ldst_ri p=1 w=0 u=1 imm=%imm8_0x4
105
106STR_ri 10010 ... ........ @ldst_spec_i rn=13
107LDR_ri 10011 ... ........ @ldst_spec_i rn=13
1cb13234
RH		 108
109# Add PC/SP (immediate)
110
111ADR 10100 rd:3 ........ imm=%imm8_0x4
112ADD_rri 10101 rd:3 ........ \
113 &s_rri_rot rn=13 s=0 rot=0 imm=%imm8_0x4 # SP
6e8514ba
RH		 114
115# Load/store multiple
116
117@ldstm ..... rn:3 list:8 &ldst_block i=1 b=0 u=0 w=1
118
119STM 11000 ... ........ @ldstm
120LDM_t16 11001 ... ........ @ldstm
c4d3095b
RH		 121
122# Add/subtract (three low registers)
123
124@addsub_3 ....... rm:3 rn:3 rd:3 \
125 &s_rrr_shi %s shim=0 shty=0
126
127ADD_rrri 0001100 ... ... ... @addsub_3
128SUB_rrri 0001101 ... ... ... @addsub_3
129
130# Add/subtract (two low registers and immediate)
131
132@addsub_2i ....... imm:3 rn:3 rd:3 \
133 &s_rri_rot %s rot=0
134
135ADD_rri 0001 110 ... ... ... @addsub_2i
136SUB_rri 0001 111 ... ... ... @addsub_2i
6c6d237a
RH		 137
138# Add, subtract, compare, move (one low register and immediate)
139
140%reg_8 8:3
141@arith_1i ..... rd:3 imm:8 \
142 &s_rri_rot rot=0 rn=%reg_8
143
144MOV_rxi 00100 ... ........ @arith_1i %s
145CMP_xri 00101 ... ........ @arith_1i s=1
146ADD_rri 00110 ... ........ @arith_1i %s
147SUB_rri 00111 ... ........ @arith_1i %s
a0ef0774 148
90aa0421
RH		 149# Add, compare, move (two high registers)
150
151%reg_0_7 7:1 0:3
152@addsub_2h .... .... . rm:4 ... \
153 &s_rrr_shi rd=%reg_0_7 rn=%reg_0_7 shim=0 shty=0
154
155ADD_rrri 0100 0100 . .... ... @addsub_2h s=0
156CMP_xrri 0100 0101 . .... ... @addsub_2h s=1
157MOV_rxri 0100 0110 . .... ... @addsub_2h s=0
158
a0ef0774
RH		 159# Branch and exchange
160
161@branchr .... .... . rm:4 ... &r
162
163BX 0100 0111 0 .... 000 @branchr
164BLX_r 0100 0111 1 .... 000 @branchr
165BXNS 0100 0111 0 .... 100 @branchr
166BLXNS 0100 0111 1 .... 100 @branchr
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