[mirror_qemu.git] / target / arm / t16.decode

# Thumb1 instructions
#
#  Copyright (c) 2019 Linaro, Ltd
#
# This library is free software; you can redistribute it and/or
# modify it under the terms of the GNU Lesser General Public
# License as published by the Free Software Foundation; either
# version 2 of the License, or (at your option) any later version.
#
# This library is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
# Lesser General Public License for more details.
#
# You should have received a copy of the GNU Lesser General Public
# License along with this library; if not, see <http://www.gnu.org/licenses/>.

#
# This file is processed by scripts/decodetree.py
#

&s_rrr_shi       !extern s rd rn rm shim shty
&s_rrr_shr       !extern s rn rd rm rs shty
&s_rri_rot       !extern s rn rd imm rot
&s_rrrr          !extern s rd rn rm ra
&rrr_rot         !extern rd rn rm rot
&rr              !extern rd rm
&ri              !extern rd imm
&r               !extern rm
&ldst_rr         !extern p w u rn rt rm shimm shtype
&ldst_ri         !extern p w u rn rt imm
&ldst_block      !extern rn i b u w list
&setend          !extern E
&cps             !extern mode imod M A I F

# Set S if the instruction is outside of an IT block.
%s               !function=t16_setflags

# Data-processing (two low registers)

%reg_0           0:3

@lll_noshr       ...... .... rm:3 rd:3 \
                 &s_rrr_shi %s rn=%reg_0 shim=0 shty=0
@xll_noshr       ...... .... rm:3 rn:3 \
                 &s_rrr_shi s=1 rd=0 shim=0 shty=0
@lxl_shr         ...... .... rs:3 rd:3 \
                 &s_rrr_shr %s rm=%reg_0 rn=0

AND_rrri         010000 0000 ... ...            @lll_noshr
EOR_rrri         010000 0001 ... ...            @lll_noshr
MOV_rxrr         010000 0010 ... ...            @lxl_shr shty=0  # LSL
MOV_rxrr         010000 0011 ... ...            @lxl_shr shty=1  # LSR
MOV_rxrr         010000 0100 ... ...            @lxl_shr shty=2  # ASR
ADC_rrri         010000 0101 ... ...            @lll_noshr
SBC_rrri         010000 0110 ... ...            @lll_noshr
MOV_rxrr         010000 0111 ... ...            @lxl_shr shty=3  # ROR
TST_xrri         010000 1000 ... ...            @xll_noshr
RSB_rri          010000 1001 rn:3 rd:3          &s_rri_rot %s imm=0 rot=0
CMP_xrri         010000 1010 ... ...            @xll_noshr
CMN_xrri         010000 1011 ... ...            @xll_noshr
ORR_rrri         010000 1100 ... ...            @lll_noshr
MUL              010000 1101 rn:3 rd:3          &s_rrrr %s rm=%reg_0 ra=0
BIC_rrri         010000 1110 ... ...            @lll_noshr
MVN_rxri         010000 1111 ... ...            @lll_noshr

# Load/store (register offset)

@ldst_rr         ....... rm:3 rn:3 rt:3 \
                 &ldst_rr p=1 w=0 u=1 shimm=0 shtype=0

STR_rr           0101 000 ... ... ...           @ldst_rr
STRH_rr          0101 001 ... ... ...           @ldst_rr
STRB_rr          0101 010 ... ... ...           @ldst_rr
LDRSB_rr         0101 011 ... ... ...           @ldst_rr
LDR_rr           0101 100 ... ... ...           @ldst_rr
LDRH_rr          0101 101 ... ... ...           @ldst_rr
LDRB_rr          0101 110 ... ... ...           @ldst_rr
LDRSH_rr         0101 111 ... ... ...           @ldst_rr

# Load/store word/byte (immediate offset)

%imm5_6x4       6:5 !function=times_4

@ldst_ri_1      ..... imm:5 rn:3 rt:3 \
                &ldst_ri p=1 w=0 u=1
@ldst_ri_4      ..... ..... rn:3 rt:3 \
                &ldst_ri p=1 w=0 u=1 imm=%imm5_6x4

STR_ri          01100 ..... ... ...             @ldst_ri_4
LDR_ri          01101 ..... ... ...             @ldst_ri_4
STRB_ri         01110 ..... ... ...             @ldst_ri_1
LDRB_ri         01111 ..... ... ...             @ldst_ri_1

# Load/store halfword (immediate offset)

%imm5_6x2       6:5 !function=times_2
@ldst_ri_2      ..... ..... rn:3 rt:3 \
                &ldst_ri p=1 w=0 u=1 imm=%imm5_6x2

STRH_ri         10000 ..... ... ...             @ldst_ri_2
LDRH_ri         10001 ..... ... ...             @ldst_ri_2

# Load/store (SP-relative)

%imm8_0x4       0:8 !function=times_4
@ldst_spec_i    ..... rt:3 ........ \
                &ldst_ri p=1 w=0 u=1 imm=%imm8_0x4

STR_ri          10010 ... ........              @ldst_spec_i rn=13
LDR_ri          10011 ... ........              @ldst_spec_i rn=13

# Add PC/SP (immediate)

ADR             10100 rd:3 ........             imm=%imm8_0x4
ADD_rri         10101 rd:3 ........ \
                &s_rri_rot rn=13 s=0 rot=0 imm=%imm8_0x4  # SP

# Load/store multiple

@ldstm          ..... rn:3 list:8               &ldst_block i=1 b=0 u=0 w=1

STM             11000 ... ........              @ldstm
LDM_t16         11001 ... ........              @ldstm

# Add/subtract (three low registers)

@addsub_3       ....... rm:3 rn:3 rd:3 \
                &s_rrr_shi %s shim=0 shty=0

ADD_rrri        0001100 ... ... ...             @addsub_3
SUB_rrri        0001101 ... ... ...             @addsub_3

# Add/subtract (two low registers and immediate)

@addsub_2i      ....... imm:3 rn:3 rd:3 \
                &s_rri_rot %s rot=0

ADD_rri         0001 110 ... ... ...            @addsub_2i
SUB_rri         0001 111 ... ... ...            @addsub_2i

# Add, subtract, compare, move (one low register and immediate)

%reg_8          8:3
@arith_1i       ..... rd:3 imm:8 \
                &s_rri_rot rot=0 rn=%reg_8

MOV_rxi         00100 ... ........              @arith_1i %s
CMP_xri         00101 ... ........              @arith_1i s=1
ADD_rri         00110 ... ........              @arith_1i %s
SUB_rri         00111 ... ........              @arith_1i %s

# Add, compare, move (two high registers)

%reg_0_7        7:1 0:3
@addsub_2h      .... .... . rm:4 ... \
                &s_rrr_shi rd=%reg_0_7 rn=%reg_0_7 shim=0 shty=0

ADD_rrri        0100 0100 . .... ...            @addsub_2h s=0
CMP_xrri        0100 0101 . .... ...            @addsub_2h s=1
MOV_rxri        0100 0110 . .... ...            @addsub_2h s=0

# Adjust SP (immediate)

%imm7_0x4       0:7 !function=times_4
@addsub_sp_i    .... .... . ....... \
                &s_rri_rot s=0 rd=13 rn=13 rot=0 imm=%imm7_0x4

ADD_rri         1011 0000 0 .......             @addsub_sp_i
SUB_rri         1011 0000 1 .......             @addsub_sp_i

# Branch and exchange

@branchr        .... .... . rm:4 ...            &r

BX              0100 0111 0 .... 000            @branchr
BLX_r           0100 0111 1 .... 000            @branchr
BXNS            0100 0111 0 .... 100            @branchr
BLXNS           0100 0111 1 .... 100            @branchr

# Extend

@extend         .... .... .. rm:3 rd:3          &rrr_rot rn=15 rot=0

SXTAH           1011 0010 00 ... ...            @extend
SXTAB           1011 0010 01 ... ...            @extend
UXTAH           1011 0010 10 ... ...            @extend
UXTAB           1011 0010 11 ... ...            @extend

# Change processor state

%imod           4:1 !function=plus_2

SETEND          1011 0110 010 1 E:1 000         &setend
{
  CPS           1011 0110 011 . 0 A:1 I:1 F:1   &cps mode=0 M=0 %imod
  CPS_v7m       1011 0110 011 im:1 00 I:1 F:1
}

# Reverse bytes

@rdm            .... .... .. rm:3 rd:3          &rr

REV             1011 1010 00 ... ...            @rdm
REV16           1011 1010 01 ... ...            @rdm
REVSH           1011 1010 11 ... ...            @rdm
Commit	Line	Data
f97b454e RH	1	# Thumb1 instructions
	2	#
	3	# Copyright (c) 2019 Linaro, Ltd
	4	#
	5	# This library is free software; you can redistribute it and/or
	6	# modify it under the terms of the GNU Lesser General Public
	7	# License as published by the Free Software Foundation; either
	8	# version 2 of the License, or (at your option) any later version.
	9	#
	10	# This library is distributed in the hope that it will be useful,
	11	# but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	13	# Lesser General Public License for more details.
	14	#
	15	# You should have received a copy of the GNU Lesser General Public
	16	# License along with this library; if not, see <http://www.gnu.org/licenses/>.
	17
	18	#
	19	# This file is processed by scripts/decodetree.py
	20	#
080c4ead RH	21
	22	&s_rrr_shi !extern s rd rn rm shim shty
	23	&s_rrr_shr !extern s rn rd rm rs shty
	24	&s_rri_rot !extern s rn rd imm rot
	25	&s_rrrr !extern s rd rn rm ra
e6f69612	26	&rrr_rot !extern rd rn rm rot
ae3002b0	27	&rr !extern rd rm
1cb13234	28	&ri !extern rd imm
a0ef0774	29	&r !extern rm
d1d22917	30	&ldst_rr !extern p w u rn rt rm shimm shtype
07afd747	31	&ldst_ri !extern p w u rn rt imm
6e8514ba	32	&ldst_block !extern rn i b u w list
20556e7b RH	33	&setend !extern E
20556e7b RH	34	&cps !extern mode imod M A I F
080c4ead RH	35
	36	# Set S if the instruction is outside of an IT block.
	37	%s !function=t16_setflags
	38
	39	# Data-processing (two low registers)
	40
	41	%reg_0 0:3
	42
	43	@lll_noshr ...... .... rm:3 rd:3 \
	44	&s_rrr_shi %s rn=%reg_0 shim=0 shty=0
	45	@xll_noshr ...... .... rm:3 rn:3 \
	46	&s_rrr_shi s=1 rd=0 shim=0 shty=0
	47	@lxl_shr ...... .... rs:3 rd:3 \
	48	&s_rrr_shr %s rm=%reg_0 rn=0
	49
	50	AND_rrri 010000 0000 ... ... @lll_noshr
	51	EOR_rrri 010000 0001 ... ... @lll_noshr
	52	MOV_rxrr 010000 0010 ... ... @lxl_shr shty=0 # LSL
	53	MOV_rxrr 010000 0011 ... ... @lxl_shr shty=1 # LSR
	54	MOV_rxrr 010000 0100 ... ... @lxl_shr shty=2 # ASR
	55	ADC_rrri 010000 0101 ... ... @lll_noshr
	56	SBC_rrri 010000 0110 ... ... @lll_noshr
	57	MOV_rxrr 010000 0111 ... ... @lxl_shr shty=3 # ROR
	58	TST_xrri 010000 1000 ... ... @xll_noshr
	59	RSB_rri 010000 1001 rn:3 rd:3 &s_rri_rot %s imm=0 rot=0
	60	CMP_xrri 010000 1010 ... ... @xll_noshr
	61	CMN_xrri 010000 1011 ... ... @xll_noshr
	62	ORR_rrri 010000 1100 ... ... @lll_noshr
	63	MUL 010000 1101 rn:3 rd:3 &s_rrrr %s rm=%reg_0 ra=0
	64	BIC_rrri 010000 1110 ... ... @lll_noshr
	65	MVN_rxri 010000 1111 ... ... @lll_noshr
d1d22917 RH	66
	67	# Load/store (register offset)
	68
	69	@ldst_rr ....... rm:3 rn:3 rt:3 \
	70	&ldst_rr p=1 w=0 u=1 shimm=0 shtype=0
	71
	72	STR_rr 0101 000 ... ... ... @ldst_rr
	73	STRH_rr 0101 001 ... ... ... @ldst_rr
	74	STRB_rr 0101 010 ... ... ... @ldst_rr
	75	LDRSB_rr 0101 011 ... ... ... @ldst_rr
	76	LDR_rr 0101 100 ... ... ... @ldst_rr
	77	LDRH_rr 0101 101 ... ... ... @ldst_rr
	78	LDRB_rr 0101 110 ... ... ... @ldst_rr
	79	LDRSH_rr 0101 111 ... ... ... @ldst_rr
07afd747 RH	80
	81	# Load/store word/byte (immediate offset)
	82
	83	%imm5_6x4 6:5 !function=times_4
	84
	85	@ldst_ri_1 ..... imm:5 rn:3 rt:3 \
	86	&ldst_ri p=1 w=0 u=1
	87	@ldst_ri_4 ..... ..... rn:3 rt:3 \
	88	&ldst_ri p=1 w=0 u=1 imm=%imm5_6x4
	89
	90	STR_ri 01100 ..... ... ... @ldst_ri_4
	91	LDR_ri 01101 ..... ... ... @ldst_ri_4
	92	STRB_ri 01110 ..... ... ... @ldst_ri_1
	93	LDRB_ri 01111 ..... ... ... @ldst_ri_1
	94
	95	# Load/store halfword (immediate offset)
	96
	97	%imm5_6x2 6:5 !function=times_2
	98	@ldst_ri_2 ..... ..... rn:3 rt:3 \
	99	&ldst_ri p=1 w=0 u=1 imm=%imm5_6x2
	100
	101	STRH_ri 10000 ..... ... ... @ldst_ri_2
	102	LDRH_ri 10001 ..... ... ... @ldst_ri_2
	103
	104	# Load/store (SP-relative)
	105
	106	%imm8_0x4 0:8 !function=times_4
	107	@ldst_spec_i ..... rt:3 ........ \
	108	&ldst_ri p=1 w=0 u=1 imm=%imm8_0x4
	109
	110	STR_ri 10010 ... ........ @ldst_spec_i rn=13
	111	LDR_ri 10011 ... ........ @ldst_spec_i rn=13
1cb13234 RH	112
	113	# Add PC/SP (immediate)
	114
	115	ADR 10100 rd:3 ........ imm=%imm8_0x4
	116	ADD_rri 10101 rd:3 ........ \
	117	&s_rri_rot rn=13 s=0 rot=0 imm=%imm8_0x4 # SP
6e8514ba RH	118
	119	# Load/store multiple
	120
	121	@ldstm ..... rn:3 list:8 &ldst_block i=1 b=0 u=0 w=1
	122
	123	STM 11000 ... ........ @ldstm
	124	LDM_t16 11001 ... ........ @ldstm
c4d3095b RH	125
	126	# Add/subtract (three low registers)
	127
	128	@addsub_3 ....... rm:3 rn:3 rd:3 \
	129	&s_rrr_shi %s shim=0 shty=0
	130
	131	ADD_rrri 0001100 ... ... ... @addsub_3
	132	SUB_rrri 0001101 ... ... ... @addsub_3
	133
	134	# Add/subtract (two low registers and immediate)
	135
	136	@addsub_2i ....... imm:3 rn:3 rd:3 \
	137	&s_rri_rot %s rot=0
	138
	139	ADD_rri 0001 110 ... ... ... @addsub_2i
	140	SUB_rri 0001 111 ... ... ... @addsub_2i
6c6d237a RH	141
	142	# Add, subtract, compare, move (one low register and immediate)
	143
	144	%reg_8 8:3
	145	@arith_1i ..... rd:3 imm:8 \
	146	&s_rri_rot rot=0 rn=%reg_8
	147
	148	MOV_rxi 00100 ... ........ @arith_1i %s
	149	CMP_xri 00101 ... ........ @arith_1i s=1
	150	ADD_rri 00110 ... ........ @arith_1i %s
	151	SUB_rri 00111 ... ........ @arith_1i %s
a0ef0774	152
90aa0421 RH	153	# Add, compare, move (two high registers)
	154
	155	%reg_0_7 7:1 0:3
	156	@addsub_2h .... .... . rm:4 ... \
	157	&s_rrr_shi rd=%reg_0_7 rn=%reg_0_7 shim=0 shty=0
	158
	159	ADD_rrri 0100 0100 . .... ... @addsub_2h s=0
	160	CMP_xrri 0100 0101 . .... ... @addsub_2h s=1
	161	MOV_rxri 0100 0110 . .... ... @addsub_2h s=0
	162
2e6a646d RH	163	# Adjust SP (immediate)
	164
	165	%imm7_0x4 0:7 !function=times_4
	166	@addsub_sp_i .... .... . ....... \
	167	&s_rri_rot s=0 rd=13 rn=13 rot=0 imm=%imm7_0x4
	168
	169	ADD_rri 1011 0000 0 ....... @addsub_sp_i
	170	SUB_rri 1011 0000 1 ....... @addsub_sp_i
	171
a0ef0774 RH	172	# Branch and exchange
	173
	174	@branchr .... .... . rm:4 ... &r
	175
	176	BX 0100 0111 0 .... 000 @branchr
	177	BLX_r 0100 0111 1 .... 000 @branchr
	178	BXNS 0100 0111 0 .... 100 @branchr
	179	BLXNS 0100 0111 1 .... 100 @branchr
e6f69612 RH	180
	181	# Extend
	182
	183	@extend .... .... .. rm:3 rd:3 &rrr_rot rn=15 rot=0
	184
	185	SXTAH 1011 0010 00 ... ... @extend
	186	SXTAB 1011 0010 01 ... ... @extend
	187	UXTAH 1011 0010 10 ... ... @extend
	188	UXTAB 1011 0010 11 ... ... @extend
20556e7b RH	189
	190	# Change processor state
	191
	192	%imod 4:1 !function=plus_2
	193
	194	SETEND 1011 0110 010 1 E:1 000 &setend
	195	{
	196	CPS 1011 0110 011 . 0 A:1 I:1 F:1 &cps mode=0 M=0 %imod
	197	CPS_v7m 1011 0110 011 im:1 00 I:1 F:1
	198	}
ae3002b0 RH	199
	200	# Reverse bytes
	201
	202	@rdm .... .... .. rm:3 rd:3 &rr
	203
	204	REV 1011 1010 00 ... ... @rdm
	205	REV16 1011 1010 01 ... ... @rdm
	206	REVSH 1011 1010 11 ... ... @rdm