projects / mirror_qemu.git / blame
| Commit | Line | Data |
|---|---|---|
| 51409b9e RH |
1 | # Thumb2 instructions |
| 2 | # | |
| 3 | # Copyright (c) 2019 Linaro, Ltd | |
| 4 | # | |
| 5 | # This library is free software; you can redistribute it and/or | |
| 6 | # modify it under the terms of the GNU Lesser General Public | |
| 7 | # License as published by the Free Software Foundation; either | |
| 8 | # version 2 of the License, or (at your option) any later version. | |
| 9 | # | |
| 10 | # This library is distributed in the hope that it will be useful, | |
| 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
| 13 | # Lesser General Public License for more details. | |
| 14 | # | |
| 15 | # You should have received a copy of the GNU Lesser General Public | |
| 16 | # License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
| 17 | ||
| 18 | # | |
| 19 | # This file is processed by scripts/decodetree.py | |
| 20 | # | |
| 25ae32c5 RH |
21 | |
| 22 | &s_rrr_shi !extern s rd rn rm shim shty | |
| 5be2c123 | 23 | &s_rrr_shr !extern s rn rd rm rs shty |
| 581c6ebd | 24 | &s_rri_rot !extern s rn rd imm rot |
| 25ae32c5 RH |
25 | |
| 26 | # Data-processing (register) | |
| 27 | ||
| 28 | %imm5_12_6 12:3 6:2 | |
| 29 | ||
| 30 | @s_rrr_shi ....... .... s:1 rn:4 .... rd:4 .. shty:2 rm:4 \ | |
| 31 | &s_rrr_shi shim=%imm5_12_6 | |
| 32 | @s_rxr_shi ....... .... s:1 .... .... rd:4 .. shty:2 rm:4 \ | |
| 33 | &s_rrr_shi shim=%imm5_12_6 rn=0 | |
| 34 | @S_xrr_shi ....... .... . rn:4 .... .... .. shty:2 rm:4 \ | |
| 35 | &s_rrr_shi shim=%imm5_12_6 s=1 rd=0 | |
| 36 | ||
| 37 | { | |
| 38 | TST_xrri 1110101 0000 1 .... 0 ... 1111 .... .... @S_xrr_shi | |
| 39 | AND_rrri 1110101 0000 . .... 0 ... .... .... .... @s_rrr_shi | |
| 40 | } | |
| 41 | BIC_rrri 1110101 0001 . .... 0 ... .... .... .... @s_rrr_shi | |
| 42 | { | |
| 43 | MOV_rxri 1110101 0010 . 1111 0 ... .... .... .... @s_rxr_shi | |
| 44 | ORR_rrri 1110101 0010 . .... 0 ... .... .... .... @s_rrr_shi | |
| 45 | } | |
| 46 | { | |
| 47 | MVN_rxri 1110101 0011 . 1111 0 ... .... .... .... @s_rxr_shi | |
| 48 | ORN_rrri 1110101 0011 . .... 0 ... .... .... .... @s_rrr_shi | |
| 49 | } | |
| 50 | { | |
| 51 | TEQ_xrri 1110101 0100 1 .... 0 ... 1111 .... .... @S_xrr_shi | |
| 52 | EOR_rrri 1110101 0100 . .... 0 ... .... .... .... @s_rrr_shi | |
| 53 | } | |
| 54 | # PKHBT, PKHTB at opc1 = 0110 | |
| 55 | { | |
| 56 | CMN_xrri 1110101 1000 1 .... 0 ... 1111 .... .... @S_xrr_shi | |
| 57 | ADD_rrri 1110101 1000 . .... 0 ... .... .... .... @s_rrr_shi | |
| 58 | } | |
| 59 | ADC_rrri 1110101 1010 . .... 0 ... .... .... .... @s_rrr_shi | |
| 60 | SBC_rrri 1110101 1011 . .... 0 ... .... .... .... @s_rrr_shi | |
| 61 | { | |
| 62 | CMP_xrri 1110101 1101 1 .... 0 ... 1111 .... .... @S_xrr_shi | |
| 63 | SUB_rrri 1110101 1101 . .... 0 ... .... .... .... @s_rrr_shi | |
| 64 | } | |
| 65 | RSB_rrri 1110101 1110 . .... 0 ... .... .... .... @s_rrr_shi | |
| 5be2c123 RH |
66 | |
| 67 | # Data-processing (register-shifted register) | |
| 68 | ||
| 69 | MOV_rxrr 1111 1010 0 shty:2 s:1 rm:4 1111 rd:4 0000 rs:4 \ | |
| 70 | &s_rrr_shr rn=0 | |
| 581c6ebd RH |
71 | |
| 72 | # Data-processing (immediate) | |
| 73 | ||
| 74 | %t32extrot 26:1 12:3 0:8 !function=t32_expandimm_rot | |
| 75 | %t32extimm 26:1 12:3 0:8 !function=t32_expandimm_imm | |
| 76 | ||
| 77 | @s_rri_rot ....... .... s:1 rn:4 . ... rd:4 ........ \ | |
| 78 | &s_rri_rot imm=%t32extimm rot=%t32extrot | |
| 79 | @s_rxi_rot ....... .... s:1 .... . ... rd:4 ........ \ | |
| 80 | &s_rri_rot imm=%t32extimm rot=%t32extrot rn=0 | |
| 81 | @S_xri_rot ....... .... . rn:4 . ... .... ........ \ | |
| 82 | &s_rri_rot imm=%t32extimm rot=%t32extrot s=1 rd=0 | |
| 83 | ||
| 84 | { | |
| 85 | TST_xri 1111 0.0 0000 1 .... 0 ... 1111 ........ @S_xri_rot | |
| 86 | AND_rri 1111 0.0 0000 . .... 0 ... .... ........ @s_rri_rot | |
| 87 | } | |
| 88 | BIC_rri 1111 0.0 0001 . .... 0 ... .... ........ @s_rri_rot | |
| 89 | { | |
| 90 | MOV_rxi 1111 0.0 0010 . 1111 0 ... .... ........ @s_rxi_rot | |
| 91 | ORR_rri 1111 0.0 0010 . .... 0 ... .... ........ @s_rri_rot | |
| 92 | } | |
| 93 | { | |
| 94 | MVN_rxi 1111 0.0 0011 . 1111 0 ... .... ........ @s_rxi_rot | |
| 95 | ORN_rri 1111 0.0 0011 . .... 0 ... .... ........ @s_rri_rot | |
| 96 | } | |
| 97 | { | |
| 98 | TEQ_xri 1111 0.0 0100 1 .... 0 ... 1111 ........ @S_xri_rot | |
| 99 | EOR_rri 1111 0.0 0100 . .... 0 ... .... ........ @s_rri_rot | |
| 100 | } | |
| 101 | { | |
| 102 | CMN_xri 1111 0.0 1000 1 .... 0 ... 1111 ........ @S_xri_rot | |
| 103 | ADD_rri 1111 0.0 1000 . .... 0 ... .... ........ @s_rri_rot | |
| 104 | } | |
| 105 | ADC_rri 1111 0.0 1010 . .... 0 ... .... ........ @s_rri_rot | |
| 106 | SBC_rri 1111 0.0 1011 . .... 0 ... .... ........ @s_rri_rot | |
| 107 | { | |
| 108 | CMP_xri 1111 0.0 1101 1 .... 0 ... 1111 ........ @S_xri_rot | |
| 109 | SUB_rri 1111 0.0 1101 . .... 0 ... .... ........ @s_rri_rot | |
| 110 | } | |
| 111 | RSB_rri 1111 0.0 1110 . .... 0 ... .... ........ @s_rri_rot |