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39920a04 FR |
1 | /* |
2 | * QEMU AArch64 TCG CPUs | |
3 | * | |
4 | * Copyright (c) 2013 Linaro Ltd | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version 2 | |
9 | * of the License, or (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, see | |
18 | * <http://www.gnu.org/licenses/gpl-2.0.html> | |
19 | */ | |
20 | ||
21 | #include "qemu/osdep.h" | |
22 | #include "qapi/error.h" | |
23 | #include "cpu.h" | |
24 | #include "qemu/module.h" | |
25 | #include "qapi/visitor.h" | |
26 | #include "hw/qdev-properties.h" | |
27 | #include "internals.h" | |
28 | #include "cpregs.h" | |
29 | ||
30 | static void aarch64_a35_initfn(Object *obj) | |
31 | { | |
32 | ARMCPU *cpu = ARM_CPU(obj); | |
33 | ||
34 | cpu->dtb_compatible = "arm,cortex-a35"; | |
35 | set_feature(&cpu->env, ARM_FEATURE_V8); | |
36 | set_feature(&cpu->env, ARM_FEATURE_NEON); | |
37 | set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); | |
38 | set_feature(&cpu->env, ARM_FEATURE_AARCH64); | |
39 | set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); | |
40 | set_feature(&cpu->env, ARM_FEATURE_EL2); | |
41 | set_feature(&cpu->env, ARM_FEATURE_EL3); | |
42 | set_feature(&cpu->env, ARM_FEATURE_PMU); | |
43 | ||
44 | /* From B2.2 AArch64 identification registers. */ | |
45 | cpu->midr = 0x411fd040; | |
46 | cpu->revidr = 0; | |
47 | cpu->ctr = 0x84448004; | |
48 | cpu->isar.id_pfr0 = 0x00000131; | |
49 | cpu->isar.id_pfr1 = 0x00011011; | |
50 | cpu->isar.id_dfr0 = 0x03010066; | |
51 | cpu->id_afr0 = 0; | |
52 | cpu->isar.id_mmfr0 = 0x10201105; | |
53 | cpu->isar.id_mmfr1 = 0x40000000; | |
54 | cpu->isar.id_mmfr2 = 0x01260000; | |
55 | cpu->isar.id_mmfr3 = 0x02102211; | |
56 | cpu->isar.id_isar0 = 0x02101110; | |
57 | cpu->isar.id_isar1 = 0x13112111; | |
58 | cpu->isar.id_isar2 = 0x21232042; | |
59 | cpu->isar.id_isar3 = 0x01112131; | |
60 | cpu->isar.id_isar4 = 0x00011142; | |
61 | cpu->isar.id_isar5 = 0x00011121; | |
62 | cpu->isar.id_aa64pfr0 = 0x00002222; | |
63 | cpu->isar.id_aa64pfr1 = 0; | |
64 | cpu->isar.id_aa64dfr0 = 0x10305106; | |
65 | cpu->isar.id_aa64dfr1 = 0; | |
66 | cpu->isar.id_aa64isar0 = 0x00011120; | |
67 | cpu->isar.id_aa64isar1 = 0; | |
68 | cpu->isar.id_aa64mmfr0 = 0x00101122; | |
69 | cpu->isar.id_aa64mmfr1 = 0; | |
70 | cpu->clidr = 0x0a200023; | |
71 | cpu->dcz_blocksize = 4; | |
72 | ||
73 | /* From B2.4 AArch64 Virtual Memory control registers */ | |
74 | cpu->reset_sctlr = 0x00c50838; | |
75 | ||
76 | /* From B2.10 AArch64 performance monitor registers */ | |
77 | cpu->isar.reset_pmcr_el0 = 0x410a3000; | |
78 | ||
79 | /* From B2.29 Cache ID registers */ | |
80 | cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */ | |
81 | cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */ | |
82 | cpu->ccsidr[2] = 0x703fe03a; /* 512KB L2 cache */ | |
83 | ||
84 | /* From B3.5 VGIC Type register */ | |
85 | cpu->gic_num_lrs = 4; | |
86 | cpu->gic_vpribits = 5; | |
87 | cpu->gic_vprebits = 5; | |
88 | cpu->gic_pribits = 5; | |
89 | ||
90 | /* From C6.4 Debug ID Register */ | |
91 | cpu->isar.dbgdidr = 0x3516d000; | |
92 | /* From C6.5 Debug Device ID Register */ | |
93 | cpu->isar.dbgdevid = 0x00110f13; | |
94 | /* From C6.6 Debug Device ID Register 1 */ | |
95 | cpu->isar.dbgdevid1 = 0x2; | |
96 | ||
97 | /* From Cortex-A35 SIMD and Floating-point Support r1p0 */ | |
98 | /* From 3.2 AArch32 register summary */ | |
99 | cpu->reset_fpsid = 0x41034043; | |
100 | ||
101 | /* From 2.2 AArch64 register summary */ | |
102 | cpu->isar.mvfr0 = 0x10110222; | |
103 | cpu->isar.mvfr1 = 0x12111111; | |
104 | cpu->isar.mvfr2 = 0x00000043; | |
105 | ||
106 | /* These values are the same with A53/A57/A72. */ | |
107 | define_cortex_a72_a57_a53_cp_reginfo(cpu); | |
108 | } | |
109 | ||
110 | static void cpu_max_get_sve_max_vq(Object *obj, Visitor *v, const char *name, | |
111 | void *opaque, Error **errp) | |
112 | { | |
113 | ARMCPU *cpu = ARM_CPU(obj); | |
114 | uint32_t value; | |
115 | ||
116 | /* All vector lengths are disabled when SVE is off. */ | |
117 | if (!cpu_isar_feature(aa64_sve, cpu)) { | |
118 | value = 0; | |
119 | } else { | |
120 | value = cpu->sve_max_vq; | |
121 | } | |
122 | visit_type_uint32(v, name, &value, errp); | |
123 | } | |
124 | ||
125 | static void cpu_max_set_sve_max_vq(Object *obj, Visitor *v, const char *name, | |
126 | void *opaque, Error **errp) | |
127 | { | |
128 | ARMCPU *cpu = ARM_CPU(obj); | |
129 | uint32_t max_vq; | |
130 | ||
131 | if (!visit_type_uint32(v, name, &max_vq, errp)) { | |
132 | return; | |
133 | } | |
134 | ||
135 | if (max_vq == 0 || max_vq > ARM_MAX_VQ) { | |
136 | error_setg(errp, "unsupported SVE vector length"); | |
137 | error_append_hint(errp, "Valid sve-max-vq in range [1-%d]\n", | |
138 | ARM_MAX_VQ); | |
139 | return; | |
140 | } | |
141 | ||
142 | cpu->sve_max_vq = max_vq; | |
143 | } | |
144 | ||
a834d547 RH |
145 | static bool cpu_arm_get_rme(Object *obj, Error **errp) |
146 | { | |
147 | ARMCPU *cpu = ARM_CPU(obj); | |
148 | return cpu_isar_feature(aa64_rme, cpu); | |
149 | } | |
150 | ||
151 | static void cpu_arm_set_rme(Object *obj, bool value, Error **errp) | |
152 | { | |
153 | ARMCPU *cpu = ARM_CPU(obj); | |
154 | uint64_t t; | |
155 | ||
156 | t = cpu->isar.id_aa64pfr0; | |
157 | t = FIELD_DP64(t, ID_AA64PFR0, RME, value); | |
158 | cpu->isar.id_aa64pfr0 = t; | |
159 | } | |
160 | ||
161 | static void cpu_max_set_l0gptsz(Object *obj, Visitor *v, const char *name, | |
162 | void *opaque, Error **errp) | |
163 | { | |
164 | ARMCPU *cpu = ARM_CPU(obj); | |
165 | uint32_t value; | |
166 | ||
167 | if (!visit_type_uint32(v, name, &value, errp)) { | |
168 | return; | |
169 | } | |
170 | ||
171 | /* Encode the value for the GPCCR_EL3 field. */ | |
172 | switch (value) { | |
173 | case 30: | |
174 | case 34: | |
175 | case 36: | |
176 | case 39: | |
177 | cpu->reset_l0gptsz = value - 30; | |
178 | break; | |
179 | default: | |
180 | error_setg(errp, "invalid value for l0gptsz"); | |
181 | error_append_hint(errp, "valid values are 30, 34, 36, 39\n"); | |
182 | break; | |
183 | } | |
184 | } | |
185 | ||
186 | static void cpu_max_get_l0gptsz(Object *obj, Visitor *v, const char *name, | |
187 | void *opaque, Error **errp) | |
188 | { | |
189 | ARMCPU *cpu = ARM_CPU(obj); | |
190 | uint32_t value = cpu->reset_l0gptsz + 30; | |
191 | ||
192 | visit_type_uint32(v, name, &value, errp); | |
193 | } | |
194 | ||
39920a04 FR |
195 | static Property arm_cpu_lpa2_property = |
196 | DEFINE_PROP_BOOL("lpa2", ARMCPU, prop_lpa2, true); | |
197 | ||
198 | static void aarch64_a55_initfn(Object *obj) | |
199 | { | |
200 | ARMCPU *cpu = ARM_CPU(obj); | |
201 | ||
202 | cpu->dtb_compatible = "arm,cortex-a55"; | |
203 | set_feature(&cpu->env, ARM_FEATURE_V8); | |
204 | set_feature(&cpu->env, ARM_FEATURE_NEON); | |
205 | set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); | |
206 | set_feature(&cpu->env, ARM_FEATURE_AARCH64); | |
207 | set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); | |
208 | set_feature(&cpu->env, ARM_FEATURE_EL2); | |
209 | set_feature(&cpu->env, ARM_FEATURE_EL3); | |
210 | set_feature(&cpu->env, ARM_FEATURE_PMU); | |
211 | ||
212 | /* Ordered by B2.4 AArch64 registers by functional group */ | |
213 | cpu->clidr = 0x82000023; | |
214 | cpu->ctr = 0x84448004; /* L1Ip = VIPT */ | |
215 | cpu->dcz_blocksize = 4; /* 64 bytes */ | |
216 | cpu->isar.id_aa64dfr0 = 0x0000000010305408ull; | |
217 | cpu->isar.id_aa64isar0 = 0x0000100010211120ull; | |
218 | cpu->isar.id_aa64isar1 = 0x0000000000100001ull; | |
219 | cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull; | |
220 | cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull; | |
221 | cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull; | |
222 | cpu->isar.id_aa64pfr0 = 0x0000000010112222ull; | |
223 | cpu->isar.id_aa64pfr1 = 0x0000000000000010ull; | |
224 | cpu->id_afr0 = 0x00000000; | |
225 | cpu->isar.id_dfr0 = 0x04010088; | |
226 | cpu->isar.id_isar0 = 0x02101110; | |
227 | cpu->isar.id_isar1 = 0x13112111; | |
228 | cpu->isar.id_isar2 = 0x21232042; | |
229 | cpu->isar.id_isar3 = 0x01112131; | |
230 | cpu->isar.id_isar4 = 0x00011142; | |
231 | cpu->isar.id_isar5 = 0x01011121; | |
232 | cpu->isar.id_isar6 = 0x00000010; | |
233 | cpu->isar.id_mmfr0 = 0x10201105; | |
234 | cpu->isar.id_mmfr1 = 0x40000000; | |
235 | cpu->isar.id_mmfr2 = 0x01260000; | |
236 | cpu->isar.id_mmfr3 = 0x02122211; | |
237 | cpu->isar.id_mmfr4 = 0x00021110; | |
238 | cpu->isar.id_pfr0 = 0x10010131; | |
239 | cpu->isar.id_pfr1 = 0x00011011; | |
240 | cpu->isar.id_pfr2 = 0x00000011; | |
241 | cpu->midr = 0x412FD050; /* r2p0 */ | |
242 | cpu->revidr = 0; | |
243 | ||
244 | /* From B2.23 CCSIDR_EL1 */ | |
245 | cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */ | |
246 | cpu->ccsidr[1] = 0x200fe01a; /* 32KB L1 icache */ | |
247 | cpu->ccsidr[2] = 0x703fe07a; /* 512KB L2 cache */ | |
248 | ||
249 | /* From B2.96 SCTLR_EL3 */ | |
250 | cpu->reset_sctlr = 0x30c50838; | |
251 | ||
252 | /* From B4.45 ICH_VTR_EL2 */ | |
253 | cpu->gic_num_lrs = 4; | |
254 | cpu->gic_vpribits = 5; | |
255 | cpu->gic_vprebits = 5; | |
256 | cpu->gic_pribits = 5; | |
257 | ||
258 | cpu->isar.mvfr0 = 0x10110222; | |
259 | cpu->isar.mvfr1 = 0x13211111; | |
260 | cpu->isar.mvfr2 = 0x00000043; | |
261 | ||
262 | /* From D5.4 AArch64 PMU register summary */ | |
263 | cpu->isar.reset_pmcr_el0 = 0x410b3000; | |
264 | } | |
265 | ||
266 | static void aarch64_a72_initfn(Object *obj) | |
267 | { | |
268 | ARMCPU *cpu = ARM_CPU(obj); | |
269 | ||
270 | cpu->dtb_compatible = "arm,cortex-a72"; | |
271 | set_feature(&cpu->env, ARM_FEATURE_V8); | |
272 | set_feature(&cpu->env, ARM_FEATURE_NEON); | |
273 | set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); | |
274 | set_feature(&cpu->env, ARM_FEATURE_AARCH64); | |
275 | set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); | |
276 | set_feature(&cpu->env, ARM_FEATURE_EL2); | |
277 | set_feature(&cpu->env, ARM_FEATURE_EL3); | |
278 | set_feature(&cpu->env, ARM_FEATURE_PMU); | |
279 | cpu->midr = 0x410fd083; | |
280 | cpu->revidr = 0x00000000; | |
281 | cpu->reset_fpsid = 0x41034080; | |
282 | cpu->isar.mvfr0 = 0x10110222; | |
283 | cpu->isar.mvfr1 = 0x12111111; | |
284 | cpu->isar.mvfr2 = 0x00000043; | |
285 | cpu->ctr = 0x8444c004; | |
286 | cpu->reset_sctlr = 0x00c50838; | |
287 | cpu->isar.id_pfr0 = 0x00000131; | |
288 | cpu->isar.id_pfr1 = 0x00011011; | |
289 | cpu->isar.id_dfr0 = 0x03010066; | |
290 | cpu->id_afr0 = 0x00000000; | |
291 | cpu->isar.id_mmfr0 = 0x10201105; | |
292 | cpu->isar.id_mmfr1 = 0x40000000; | |
293 | cpu->isar.id_mmfr2 = 0x01260000; | |
294 | cpu->isar.id_mmfr3 = 0x02102211; | |
295 | cpu->isar.id_isar0 = 0x02101110; | |
296 | cpu->isar.id_isar1 = 0x13112111; | |
297 | cpu->isar.id_isar2 = 0x21232042; | |
298 | cpu->isar.id_isar3 = 0x01112131; | |
299 | cpu->isar.id_isar4 = 0x00011142; | |
300 | cpu->isar.id_isar5 = 0x00011121; | |
301 | cpu->isar.id_aa64pfr0 = 0x00002222; | |
302 | cpu->isar.id_aa64dfr0 = 0x10305106; | |
303 | cpu->isar.id_aa64isar0 = 0x00011120; | |
304 | cpu->isar.id_aa64mmfr0 = 0x00001124; | |
305 | cpu->isar.dbgdidr = 0x3516d000; | |
306 | cpu->isar.dbgdevid = 0x01110f13; | |
307 | cpu->isar.dbgdevid1 = 0x2; | |
308 | cpu->isar.reset_pmcr_el0 = 0x41023000; | |
309 | cpu->clidr = 0x0a200023; | |
310 | cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */ | |
311 | cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */ | |
312 | cpu->ccsidr[2] = 0x707fe07a; /* 1MB L2 cache */ | |
313 | cpu->dcz_blocksize = 4; /* 64 bytes */ | |
314 | cpu->gic_num_lrs = 4; | |
315 | cpu->gic_vpribits = 5; | |
316 | cpu->gic_vprebits = 5; | |
317 | cpu->gic_pribits = 5; | |
318 | define_cortex_a72_a57_a53_cp_reginfo(cpu); | |
319 | } | |
320 | ||
321 | static void aarch64_a76_initfn(Object *obj) | |
322 | { | |
323 | ARMCPU *cpu = ARM_CPU(obj); | |
324 | ||
325 | cpu->dtb_compatible = "arm,cortex-a76"; | |
326 | set_feature(&cpu->env, ARM_FEATURE_V8); | |
327 | set_feature(&cpu->env, ARM_FEATURE_NEON); | |
328 | set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); | |
329 | set_feature(&cpu->env, ARM_FEATURE_AARCH64); | |
330 | set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); | |
331 | set_feature(&cpu->env, ARM_FEATURE_EL2); | |
332 | set_feature(&cpu->env, ARM_FEATURE_EL3); | |
333 | set_feature(&cpu->env, ARM_FEATURE_PMU); | |
334 | ||
335 | /* Ordered by B2.4 AArch64 registers by functional group */ | |
336 | cpu->clidr = 0x82000023; | |
337 | cpu->ctr = 0x8444C004; | |
338 | cpu->dcz_blocksize = 4; | |
339 | cpu->isar.id_aa64dfr0 = 0x0000000010305408ull; | |
340 | cpu->isar.id_aa64isar0 = 0x0000100010211120ull; | |
341 | cpu->isar.id_aa64isar1 = 0x0000000000100001ull; | |
342 | cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull; | |
343 | cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull; | |
344 | cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull; | |
345 | cpu->isar.id_aa64pfr0 = 0x1100000010111112ull; /* GIC filled in later */ | |
346 | cpu->isar.id_aa64pfr1 = 0x0000000000000010ull; | |
347 | cpu->id_afr0 = 0x00000000; | |
348 | cpu->isar.id_dfr0 = 0x04010088; | |
349 | cpu->isar.id_isar0 = 0x02101110; | |
350 | cpu->isar.id_isar1 = 0x13112111; | |
351 | cpu->isar.id_isar2 = 0x21232042; | |
352 | cpu->isar.id_isar3 = 0x01112131; | |
353 | cpu->isar.id_isar4 = 0x00010142; | |
354 | cpu->isar.id_isar5 = 0x01011121; | |
355 | cpu->isar.id_isar6 = 0x00000010; | |
356 | cpu->isar.id_mmfr0 = 0x10201105; | |
357 | cpu->isar.id_mmfr1 = 0x40000000; | |
358 | cpu->isar.id_mmfr2 = 0x01260000; | |
359 | cpu->isar.id_mmfr3 = 0x02122211; | |
360 | cpu->isar.id_mmfr4 = 0x00021110; | |
361 | cpu->isar.id_pfr0 = 0x10010131; | |
362 | cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */ | |
363 | cpu->isar.id_pfr2 = 0x00000011; | |
364 | cpu->midr = 0x414fd0b1; /* r4p1 */ | |
365 | cpu->revidr = 0; | |
366 | ||
367 | /* From B2.18 CCSIDR_EL1 */ | |
368 | cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */ | |
369 | cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */ | |
370 | cpu->ccsidr[2] = 0x707fe03a; /* 512KB L2 cache */ | |
371 | ||
372 | /* From B2.93 SCTLR_EL3 */ | |
373 | cpu->reset_sctlr = 0x30c50838; | |
374 | ||
375 | /* From B4.23 ICH_VTR_EL2 */ | |
376 | cpu->gic_num_lrs = 4; | |
377 | cpu->gic_vpribits = 5; | |
378 | cpu->gic_vprebits = 5; | |
379 | cpu->gic_pribits = 5; | |
380 | ||
381 | /* From B5.1 AdvSIMD AArch64 register summary */ | |
382 | cpu->isar.mvfr0 = 0x10110222; | |
383 | cpu->isar.mvfr1 = 0x13211111; | |
384 | cpu->isar.mvfr2 = 0x00000043; | |
385 | ||
386 | /* From D5.1 AArch64 PMU register summary */ | |
387 | cpu->isar.reset_pmcr_el0 = 0x410b3000; | |
388 | } | |
389 | ||
390 | static void aarch64_a64fx_initfn(Object *obj) | |
391 | { | |
392 | ARMCPU *cpu = ARM_CPU(obj); | |
393 | ||
394 | cpu->dtb_compatible = "arm,a64fx"; | |
395 | set_feature(&cpu->env, ARM_FEATURE_V8); | |
396 | set_feature(&cpu->env, ARM_FEATURE_NEON); | |
397 | set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); | |
398 | set_feature(&cpu->env, ARM_FEATURE_AARCH64); | |
399 | set_feature(&cpu->env, ARM_FEATURE_EL2); | |
400 | set_feature(&cpu->env, ARM_FEATURE_EL3); | |
401 | set_feature(&cpu->env, ARM_FEATURE_PMU); | |
402 | cpu->midr = 0x461f0010; | |
403 | cpu->revidr = 0x00000000; | |
404 | cpu->ctr = 0x86668006; | |
405 | cpu->reset_sctlr = 0x30000180; | |
406 | cpu->isar.id_aa64pfr0 = 0x0000000101111111; /* No RAS Extensions */ | |
407 | cpu->isar.id_aa64pfr1 = 0x0000000000000000; | |
408 | cpu->isar.id_aa64dfr0 = 0x0000000010305408; | |
409 | cpu->isar.id_aa64dfr1 = 0x0000000000000000; | |
410 | cpu->id_aa64afr0 = 0x0000000000000000; | |
411 | cpu->id_aa64afr1 = 0x0000000000000000; | |
412 | cpu->isar.id_aa64mmfr0 = 0x0000000000001122; | |
413 | cpu->isar.id_aa64mmfr1 = 0x0000000011212100; | |
414 | cpu->isar.id_aa64mmfr2 = 0x0000000000001011; | |
415 | cpu->isar.id_aa64isar0 = 0x0000000010211120; | |
416 | cpu->isar.id_aa64isar1 = 0x0000000000010001; | |
417 | cpu->isar.id_aa64zfr0 = 0x0000000000000000; | |
418 | cpu->clidr = 0x0000000080000023; | |
419 | cpu->ccsidr[0] = 0x7007e01c; /* 64KB L1 dcache */ | |
420 | cpu->ccsidr[1] = 0x2007e01c; /* 64KB L1 icache */ | |
421 | cpu->ccsidr[2] = 0x70ffe07c; /* 8MB L2 cache */ | |
422 | cpu->dcz_blocksize = 6; /* 256 bytes */ | |
423 | cpu->gic_num_lrs = 4; | |
424 | cpu->gic_vpribits = 5; | |
425 | cpu->gic_vprebits = 5; | |
426 | cpu->gic_pribits = 5; | |
427 | ||
428 | /* The A64FX supports only 128, 256 and 512 bit vector lengths */ | |
429 | aarch64_add_sve_properties(obj); | |
430 | cpu->sve_vq.supported = (1 << 0) /* 128bit */ | |
431 | | (1 << 1) /* 256bit */ | |
432 | | (1 << 3); /* 512bit */ | |
433 | ||
434 | cpu->isar.reset_pmcr_el0 = 0x46014040; | |
435 | ||
436 | /* TODO: Add A64FX specific HPC extension registers */ | |
437 | } | |
438 | ||
439 | static const ARMCPRegInfo neoverse_n1_cp_reginfo[] = { | |
440 | { .name = "ATCR_EL1", .state = ARM_CP_STATE_AA64, | |
441 | .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 7, .opc2 = 0, | |
442 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
443 | { .name = "ATCR_EL2", .state = ARM_CP_STATE_AA64, | |
444 | .opc0 = 3, .opc1 = 4, .crn = 15, .crm = 7, .opc2 = 0, | |
445 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
446 | { .name = "ATCR_EL3", .state = ARM_CP_STATE_AA64, | |
447 | .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 7, .opc2 = 0, | |
448 | .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
449 | { .name = "ATCR_EL12", .state = ARM_CP_STATE_AA64, | |
450 | .opc0 = 3, .opc1 = 5, .crn = 15, .crm = 7, .opc2 = 0, | |
451 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
452 | { .name = "AVTCR_EL2", .state = ARM_CP_STATE_AA64, | |
453 | .opc0 = 3, .opc1 = 4, .crn = 15, .crm = 7, .opc2 = 1, | |
454 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
455 | { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64, | |
456 | .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 0, | |
457 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
458 | { .name = "CPUACTLR2_EL1", .state = ARM_CP_STATE_AA64, | |
459 | .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 1, | |
460 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
461 | { .name = "CPUACTLR3_EL1", .state = ARM_CP_STATE_AA64, | |
462 | .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 2, | |
463 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
464 | /* | |
465 | * Report CPUCFR_EL1.SCU as 1, as we do not implement the DSU | |
466 | * (and in particular its system registers). | |
467 | */ | |
468 | { .name = "CPUCFR_EL1", .state = ARM_CP_STATE_AA64, | |
469 | .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 0, .opc2 = 0, | |
470 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 4 }, | |
471 | { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64, | |
472 | .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 4, | |
473 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0x961563010 }, | |
474 | { .name = "CPUPCR_EL3", .state = ARM_CP_STATE_AA64, | |
475 | .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 1, | |
476 | .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
477 | { .name = "CPUPMR_EL3", .state = ARM_CP_STATE_AA64, | |
478 | .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 3, | |
479 | .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
480 | { .name = "CPUPOR_EL3", .state = ARM_CP_STATE_AA64, | |
481 | .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 2, | |
482 | .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
483 | { .name = "CPUPSELR_EL3", .state = ARM_CP_STATE_AA64, | |
484 | .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 0, | |
485 | .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
486 | { .name = "CPUPWRCTLR_EL1", .state = ARM_CP_STATE_AA64, | |
487 | .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 7, | |
488 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
489 | { .name = "ERXPFGCDN_EL1", .state = ARM_CP_STATE_AA64, | |
490 | .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 2, | |
491 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
492 | { .name = "ERXPFGCTL_EL1", .state = ARM_CP_STATE_AA64, | |
493 | .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 1, | |
494 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
495 | { .name = "ERXPFGF_EL1", .state = ARM_CP_STATE_AA64, | |
496 | .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 0, | |
497 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
498 | }; | |
499 | ||
500 | static void define_neoverse_n1_cp_reginfo(ARMCPU *cpu) | |
501 | { | |
502 | define_arm_cp_regs(cpu, neoverse_n1_cp_reginfo); | |
503 | } | |
504 | ||
505 | static void aarch64_neoverse_n1_initfn(Object *obj) | |
506 | { | |
507 | ARMCPU *cpu = ARM_CPU(obj); | |
508 | ||
509 | cpu->dtb_compatible = "arm,neoverse-n1"; | |
510 | set_feature(&cpu->env, ARM_FEATURE_V8); | |
511 | set_feature(&cpu->env, ARM_FEATURE_NEON); | |
512 | set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); | |
513 | set_feature(&cpu->env, ARM_FEATURE_AARCH64); | |
514 | set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); | |
515 | set_feature(&cpu->env, ARM_FEATURE_EL2); | |
516 | set_feature(&cpu->env, ARM_FEATURE_EL3); | |
517 | set_feature(&cpu->env, ARM_FEATURE_PMU); | |
518 | ||
519 | /* Ordered by B2.4 AArch64 registers by functional group */ | |
520 | cpu->clidr = 0x82000023; | |
521 | cpu->ctr = 0x8444c004; | |
522 | cpu->dcz_blocksize = 4; | |
523 | cpu->isar.id_aa64dfr0 = 0x0000000110305408ull; | |
524 | cpu->isar.id_aa64isar0 = 0x0000100010211120ull; | |
525 | cpu->isar.id_aa64isar1 = 0x0000000000100001ull; | |
526 | cpu->isar.id_aa64mmfr0 = 0x0000000000101125ull; | |
527 | cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull; | |
528 | cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull; | |
529 | cpu->isar.id_aa64pfr0 = 0x1100000010111112ull; /* GIC filled in later */ | |
530 | cpu->isar.id_aa64pfr1 = 0x0000000000000020ull; | |
531 | cpu->id_afr0 = 0x00000000; | |
532 | cpu->isar.id_dfr0 = 0x04010088; | |
533 | cpu->isar.id_isar0 = 0x02101110; | |
534 | cpu->isar.id_isar1 = 0x13112111; | |
535 | cpu->isar.id_isar2 = 0x21232042; | |
536 | cpu->isar.id_isar3 = 0x01112131; | |
537 | cpu->isar.id_isar4 = 0x00010142; | |
538 | cpu->isar.id_isar5 = 0x01011121; | |
539 | cpu->isar.id_isar6 = 0x00000010; | |
540 | cpu->isar.id_mmfr0 = 0x10201105; | |
541 | cpu->isar.id_mmfr1 = 0x40000000; | |
542 | cpu->isar.id_mmfr2 = 0x01260000; | |
543 | cpu->isar.id_mmfr3 = 0x02122211; | |
544 | cpu->isar.id_mmfr4 = 0x00021110; | |
545 | cpu->isar.id_pfr0 = 0x10010131; | |
546 | cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */ | |
547 | cpu->isar.id_pfr2 = 0x00000011; | |
548 | cpu->midr = 0x414fd0c1; /* r4p1 */ | |
549 | cpu->revidr = 0; | |
550 | ||
551 | /* From B2.23 CCSIDR_EL1 */ | |
552 | cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */ | |
553 | cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */ | |
554 | cpu->ccsidr[2] = 0x70ffe03a; /* 1MB L2 cache */ | |
555 | ||
556 | /* From B2.98 SCTLR_EL3 */ | |
557 | cpu->reset_sctlr = 0x30c50838; | |
558 | ||
559 | /* From B4.23 ICH_VTR_EL2 */ | |
560 | cpu->gic_num_lrs = 4; | |
561 | cpu->gic_vpribits = 5; | |
562 | cpu->gic_vprebits = 5; | |
563 | cpu->gic_pribits = 5; | |
564 | ||
565 | /* From B5.1 AdvSIMD AArch64 register summary */ | |
566 | cpu->isar.mvfr0 = 0x10110222; | |
567 | cpu->isar.mvfr1 = 0x13211111; | |
568 | cpu->isar.mvfr2 = 0x00000043; | |
569 | ||
570 | /* From D5.1 AArch64 PMU register summary */ | |
571 | cpu->isar.reset_pmcr_el0 = 0x410c3000; | |
572 | ||
573 | define_neoverse_n1_cp_reginfo(cpu); | |
574 | } | |
575 | ||
576 | /* | |
577 | * -cpu max: a CPU with as many features enabled as our emulation supports. | |
20cf68ef | 578 | * The version of '-cpu max' for qemu-system-arm is defined in cpu32.c; |
39920a04 FR |
579 | * this only needs to handle 64 bits. |
580 | */ | |
581 | void aarch64_max_tcg_initfn(Object *obj) | |
582 | { | |
583 | ARMCPU *cpu = ARM_CPU(obj); | |
584 | uint64_t t; | |
585 | uint32_t u; | |
586 | ||
587 | /* | |
588 | * Reset MIDR so the guest doesn't mistake our 'max' CPU type for a real | |
589 | * one and try to apply errata workarounds or use impdef features we | |
590 | * don't provide. | |
591 | * An IMPLEMENTER field of 0 means "reserved for software use"; | |
592 | * ARCHITECTURE must be 0xf indicating "v7 or later, check ID registers | |
593 | * to see which features are present"; | |
594 | * the VARIANT, PARTNUM and REVISION fields are all implementation | |
595 | * defined and we choose to define PARTNUM just in case guest | |
596 | * code needs to distinguish this QEMU CPU from other software | |
597 | * implementations, though this shouldn't be needed. | |
598 | */ | |
599 | t = FIELD_DP64(0, MIDR_EL1, IMPLEMENTER, 0); | |
600 | t = FIELD_DP64(t, MIDR_EL1, ARCHITECTURE, 0xf); | |
601 | t = FIELD_DP64(t, MIDR_EL1, PARTNUM, 'Q'); | |
602 | t = FIELD_DP64(t, MIDR_EL1, VARIANT, 0); | |
603 | t = FIELD_DP64(t, MIDR_EL1, REVISION, 0); | |
604 | cpu->midr = t; | |
605 | ||
606 | /* | |
607 | * We're going to set FEAT_S2FWB, which mandates that CLIDR_EL1.{LoUU,LoUIS} | |
608 | * are zero. | |
609 | */ | |
610 | u = cpu->clidr; | |
611 | u = FIELD_DP32(u, CLIDR_EL1, LOUIS, 0); | |
612 | u = FIELD_DP32(u, CLIDR_EL1, LOUU, 0); | |
613 | cpu->clidr = u; | |
614 | ||
615 | t = cpu->isar.id_aa64isar0; | |
616 | t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* FEAT_PMULL */ | |
617 | t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1); /* FEAT_SHA1 */ | |
618 | t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* FEAT_SHA512 */ | |
619 | t = FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1); | |
620 | t = FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2); /* FEAT_LSE */ | |
621 | t = FIELD_DP64(t, ID_AA64ISAR0, RDM, 1); /* FEAT_RDM */ | |
622 | t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1); /* FEAT_SHA3 */ | |
623 | t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 1); /* FEAT_SM3 */ | |
624 | t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1); /* FEAT_SM4 */ | |
625 | t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1); /* FEAT_DotProd */ | |
626 | t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1); /* FEAT_FHM */ | |
627 | t = FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* FEAT_FlagM2 */ | |
628 | t = FIELD_DP64(t, ID_AA64ISAR0, TLB, 2); /* FEAT_TLBIRANGE */ | |
629 | t = FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1); /* FEAT_RNG */ | |
630 | cpu->isar.id_aa64isar0 = t; | |
631 | ||
632 | t = cpu->isar.id_aa64isar1; | |
633 | t = FIELD_DP64(t, ID_AA64ISAR1, DPB, 2); /* FEAT_DPB2 */ | |
634 | t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1); /* FEAT_JSCVT */ | |
635 | t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1); /* FEAT_FCMA */ | |
636 | t = FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2); /* FEAT_LRCPC2 */ | |
637 | t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1); /* FEAT_FRINTTS */ | |
638 | t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1); /* FEAT_SB */ | |
639 | t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); /* FEAT_SPECRES */ | |
640 | t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 1); /* FEAT_BF16 */ | |
641 | t = FIELD_DP64(t, ID_AA64ISAR1, DGH, 1); /* FEAT_DGH */ | |
642 | t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1); /* FEAT_I8MM */ | |
643 | cpu->isar.id_aa64isar1 = t; | |
644 | ||
645 | t = cpu->isar.id_aa64pfr0; | |
646 | t = FIELD_DP64(t, ID_AA64PFR0, FP, 1); /* FEAT_FP16 */ | |
647 | t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); /* FEAT_FP16 */ | |
648 | t = FIELD_DP64(t, ID_AA64PFR0, RAS, 2); /* FEAT_RASv1p1 + FEAT_DoubleFault */ | |
649 | t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1); | |
650 | t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */ | |
651 | t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */ | |
652 | t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 2); /* FEAT_CSV2_2 */ | |
653 | t = FIELD_DP64(t, ID_AA64PFR0, CSV3, 1); /* FEAT_CSV3 */ | |
654 | cpu->isar.id_aa64pfr0 = t; | |
655 | ||
656 | t = cpu->isar.id_aa64pfr1; | |
657 | t = FIELD_DP64(t, ID_AA64PFR1, BT, 1); /* FEAT_BTI */ | |
658 | t = FIELD_DP64(t, ID_AA64PFR1, SSBS, 2); /* FEAT_SSBS2 */ | |
659 | /* | |
660 | * Begin with full support for MTE. This will be downgraded to MTE=0 | |
661 | * during realize if the board provides no tag memory, much like | |
662 | * we do for EL2 with the virtualization=on property. | |
663 | */ | |
664 | t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3); /* FEAT_MTE3 */ | |
665 | t = FIELD_DP64(t, ID_AA64PFR1, RAS_FRAC, 0); /* FEAT_RASv1p1 + FEAT_DoubleFault */ | |
666 | t = FIELD_DP64(t, ID_AA64PFR1, SME, 1); /* FEAT_SME */ | |
667 | t = FIELD_DP64(t, ID_AA64PFR1, CSV2_FRAC, 0); /* FEAT_CSV2_2 */ | |
668 | cpu->isar.id_aa64pfr1 = t; | |
669 | ||
670 | t = cpu->isar.id_aa64mmfr0; | |
671 | t = FIELD_DP64(t, ID_AA64MMFR0, PARANGE, 6); /* FEAT_LPA: 52 bits */ | |
672 | t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16, 1); /* 16k pages supported */ | |
673 | t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16_2, 2); /* 16k stage2 supported */ | |
674 | t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN64_2, 2); /* 64k stage2 supported */ | |
675 | t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN4_2, 2); /* 4k stage2 supported */ | |
676 | t = FIELD_DP64(t, ID_AA64MMFR0, FGT, 1); /* FEAT_FGT */ | |
677 | cpu->isar.id_aa64mmfr0 = t; | |
678 | ||
679 | t = cpu->isar.id_aa64mmfr1; | |
680 | t = FIELD_DP64(t, ID_AA64MMFR1, HAFDBS, 2); /* FEAT_HAFDBS */ | |
681 | t = FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* FEAT_VMID16 */ | |
682 | t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1); /* FEAT_VHE */ | |
683 | t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* FEAT_HPDS */ | |
684 | t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1); /* FEAT_LOR */ | |
685 | t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 3); /* FEAT_PAN3 */ | |
686 | t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* FEAT_XNX */ | |
687 | t = FIELD_DP64(t, ID_AA64MMFR1, ETS, 1); /* FEAT_ETS */ | |
688 | t = FIELD_DP64(t, ID_AA64MMFR1, HCX, 1); /* FEAT_HCX */ | |
689 | cpu->isar.id_aa64mmfr1 = t; | |
690 | ||
691 | t = cpu->isar.id_aa64mmfr2; | |
692 | t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* FEAT_TTCNP */ | |
693 | t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); /* FEAT_UAO */ | |
694 | t = FIELD_DP64(t, ID_AA64MMFR2, IESB, 1); /* FEAT_IESB */ | |
695 | t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */ | |
696 | t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* FEAT_TTST */ | |
59b6b42c | 697 | t = FIELD_DP64(t, ID_AA64MMFR2, AT, 1); /* FEAT_LSE2 */ |
39920a04 FR |
698 | t = FIELD_DP64(t, ID_AA64MMFR2, IDS, 1); /* FEAT_IDST */ |
699 | t = FIELD_DP64(t, ID_AA64MMFR2, FWB, 1); /* FEAT_S2FWB */ | |
700 | t = FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* FEAT_TTL */ | |
701 | t = FIELD_DP64(t, ID_AA64MMFR2, BBM, 2); /* FEAT_BBM at level 2 */ | |
702 | t = FIELD_DP64(t, ID_AA64MMFR2, EVT, 2); /* FEAT_EVT */ | |
703 | t = FIELD_DP64(t, ID_AA64MMFR2, E0PD, 1); /* FEAT_E0PD */ | |
704 | cpu->isar.id_aa64mmfr2 = t; | |
705 | ||
706 | t = cpu->isar.id_aa64zfr0; | |
707 | t = FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 1); | |
708 | t = FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* FEAT_SVE_PMULL128 */ | |
709 | t = FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1); /* FEAT_SVE_BitPerm */ | |
710 | t = FIELD_DP64(t, ID_AA64ZFR0, BFLOAT16, 1); /* FEAT_BF16 */ | |
711 | t = FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1); /* FEAT_SVE_SHA3 */ | |
712 | t = FIELD_DP64(t, ID_AA64ZFR0, SM4, 1); /* FEAT_SVE_SM4 */ | |
713 | t = FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1); /* FEAT_I8MM */ | |
714 | t = FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1); /* FEAT_F32MM */ | |
715 | t = FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1); /* FEAT_F64MM */ | |
716 | cpu->isar.id_aa64zfr0 = t; | |
717 | ||
718 | t = cpu->isar.id_aa64dfr0; | |
719 | t = FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 9); /* FEAT_Debugv8p4 */ | |
720 | t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 6); /* FEAT_PMUv3p5 */ | |
721 | cpu->isar.id_aa64dfr0 = t; | |
722 | ||
723 | t = cpu->isar.id_aa64smfr0; | |
724 | t = FIELD_DP64(t, ID_AA64SMFR0, F32F32, 1); /* FEAT_SME */ | |
725 | t = FIELD_DP64(t, ID_AA64SMFR0, B16F32, 1); /* FEAT_SME */ | |
726 | t = FIELD_DP64(t, ID_AA64SMFR0, F16F32, 1); /* FEAT_SME */ | |
727 | t = FIELD_DP64(t, ID_AA64SMFR0, I8I32, 0xf); /* FEAT_SME */ | |
728 | t = FIELD_DP64(t, ID_AA64SMFR0, F64F64, 1); /* FEAT_SME_F64F64 */ | |
729 | t = FIELD_DP64(t, ID_AA64SMFR0, I16I64, 0xf); /* FEAT_SME_I16I64 */ | |
730 | t = FIELD_DP64(t, ID_AA64SMFR0, FA64, 1); /* FEAT_SME_FA64 */ | |
731 | cpu->isar.id_aa64smfr0 = t; | |
732 | ||
733 | /* Replicate the same data to the 32-bit id registers. */ | |
734 | aa32_max_features(cpu); | |
735 | ||
736 | #ifdef CONFIG_USER_ONLY | |
737 | /* | |
738 | * For usermode -cpu max we can use a larger and more efficient DCZ | |
739 | * blocksize since we don't have to follow what the hardware does. | |
740 | */ | |
741 | cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */ | |
742 | cpu->dcz_blocksize = 7; /* 512 bytes */ | |
743 | #endif | |
744 | ||
745 | cpu->sve_vq.supported = MAKE_64BIT_MASK(0, ARM_MAX_VQ); | |
746 | cpu->sme_vq.supported = SVE_VQ_POW2_MAP; | |
747 | ||
748 | aarch64_add_pauth_properties(obj); | |
749 | aarch64_add_sve_properties(obj); | |
750 | aarch64_add_sme_properties(obj); | |
751 | object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_max_vq, | |
752 | cpu_max_set_sve_max_vq, NULL, NULL); | |
a834d547 RH |
753 | object_property_add_bool(obj, "x-rme", cpu_arm_get_rme, cpu_arm_set_rme); |
754 | object_property_add(obj, "x-l0gptsz", "uint32", cpu_max_get_l0gptsz, | |
755 | cpu_max_set_l0gptsz, NULL, NULL); | |
39920a04 FR |
756 | qdev_property_add_static(DEVICE(obj), &arm_cpu_lpa2_property); |
757 | } | |
758 | ||
759 | static const ARMCPUInfo aarch64_cpus[] = { | |
760 | { .name = "cortex-a35", .initfn = aarch64_a35_initfn }, | |
761 | { .name = "cortex-a55", .initfn = aarch64_a55_initfn }, | |
762 | { .name = "cortex-a72", .initfn = aarch64_a72_initfn }, | |
763 | { .name = "cortex-a76", .initfn = aarch64_a76_initfn }, | |
764 | { .name = "a64fx", .initfn = aarch64_a64fx_initfn }, | |
765 | { .name = "neoverse-n1", .initfn = aarch64_neoverse_n1_initfn }, | |
766 | }; | |
767 | ||
768 | static void aarch64_cpu_register_types(void) | |
769 | { | |
770 | size_t i; | |
771 | ||
772 | for (i = 0; i < ARRAY_SIZE(aarch64_cpus); ++i) { | |
773 | aarch64_cpu_register(&aarch64_cpus[i]); | |
774 | } | |
775 | } | |
776 | ||
777 | type_init(aarch64_cpu_register_types) |