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14ade10f AG |
1 | /* |
2 | * AArch64 translation | |
3 | * | |
4 | * Copyright (c) 2013 Alexander Graf <agraf@suse.de> | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
74c21bd0 | 19 | #include "qemu/osdep.h" |
14ade10f AG |
20 | |
21 | #include "cpu.h" | |
63c91552 | 22 | #include "exec/exec-all.h" |
14ade10f AG |
23 | #include "tcg-op.h" |
24 | #include "qemu/log.h" | |
1d854765 | 25 | #include "arm_ldst.h" |
14ade10f | 26 | #include "translate.h" |
ccd38087 | 27 | #include "internals.h" |
14ade10f AG |
28 | #include "qemu/host-utils.h" |
29 | ||
8012c84f | 30 | #include "exec/semihost.h" |
40f860cd PM |
31 | #include "exec/gen-icount.h" |
32 | ||
2ef6175a RH |
33 | #include "exec/helper-proto.h" |
34 | #include "exec/helper-gen.h" | |
508127e2 | 35 | #include "exec/log.h" |
14ade10f | 36 | |
a7e30d84 LV |
37 | #include "trace-tcg.h" |
38 | ||
14ade10f AG |
39 | static TCGv_i64 cpu_X[32]; |
40 | static TCGv_i64 cpu_pc; | |
14ade10f | 41 | |
fa2ef212 | 42 | /* Load/store exclusive handling */ |
fa2ef212 | 43 | static TCGv_i64 cpu_exclusive_high; |
6feecb8b | 44 | static TCGv_i64 cpu_reg(DisasContext *s, int reg); |
fa2ef212 | 45 | |
14ade10f AG |
46 | static const char *regnames[] = { |
47 | "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", | |
48 | "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", | |
49 | "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", | |
50 | "x24", "x25", "x26", "x27", "x28", "x29", "lr", "sp" | |
51 | }; | |
52 | ||
832ffa1c AG |
53 | enum a64_shift_type { |
54 | A64_SHIFT_TYPE_LSL = 0, | |
55 | A64_SHIFT_TYPE_LSR = 1, | |
56 | A64_SHIFT_TYPE_ASR = 2, | |
57 | A64_SHIFT_TYPE_ROR = 3 | |
58 | }; | |
59 | ||
384b26fb AB |
60 | /* Table based decoder typedefs - used when the relevant bits for decode |
61 | * are too awkwardly scattered across the instruction (eg SIMD). | |
62 | */ | |
63 | typedef void AArch64DecodeFn(DisasContext *s, uint32_t insn); | |
64 | ||
65 | typedef struct AArch64DecodeTable { | |
66 | uint32_t pattern; | |
67 | uint32_t mask; | |
68 | AArch64DecodeFn *disas_fn; | |
69 | } AArch64DecodeTable; | |
70 | ||
1f8a73af | 71 | /* Function prototype for gen_ functions for calling Neon helpers */ |
0a79bc87 | 72 | typedef void NeonGenOneOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32); |
1f8a73af | 73 | typedef void NeonGenTwoOpFn(TCGv_i32, TCGv_i32, TCGv_i32); |
6d9571f7 | 74 | typedef void NeonGenTwoOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32); |
70d7f984 | 75 | typedef void NeonGenTwo64OpFn(TCGv_i64, TCGv_i64, TCGv_i64); |
a847f32c | 76 | typedef void NeonGenTwo64OpEnvFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i64); |
d980fd59 PM |
77 | typedef void NeonGenNarrowFn(TCGv_i32, TCGv_i64); |
78 | typedef void NeonGenNarrowEnvFn(TCGv_i32, TCGv_ptr, TCGv_i64); | |
70d7f984 | 79 | typedef void NeonGenWidenFn(TCGv_i64, TCGv_i32); |
8908f4d1 AB |
80 | typedef void NeonGenTwoSingleOPFn(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_ptr); |
81 | typedef void NeonGenTwoDoubleOPFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_ptr); | |
6781fa11 | 82 | typedef void NeonGenOneOpFn(TCGv_i64, TCGv_i64); |
f6fe04d5 | 83 | typedef void CryptoTwoOpEnvFn(TCGv_ptr, TCGv_i32, TCGv_i32); |
5acc765c | 84 | typedef void CryptoThreeOpEnvFn(TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32); |
1f8a73af | 85 | |
14ade10f AG |
86 | /* initialize TCG globals. */ |
87 | void a64_translate_init(void) | |
88 | { | |
89 | int i; | |
90 | ||
e1ccc054 | 91 | cpu_pc = tcg_global_mem_new_i64(cpu_env, |
14ade10f AG |
92 | offsetof(CPUARMState, pc), |
93 | "pc"); | |
94 | for (i = 0; i < 32; i++) { | |
e1ccc054 | 95 | cpu_X[i] = tcg_global_mem_new_i64(cpu_env, |
14ade10f AG |
96 | offsetof(CPUARMState, xregs[i]), |
97 | regnames[i]); | |
98 | } | |
99 | ||
e1ccc054 | 100 | cpu_exclusive_high = tcg_global_mem_new_i64(cpu_env, |
fa2ef212 | 101 | offsetof(CPUARMState, exclusive_high), "exclusive_high"); |
14ade10f AG |
102 | } |
103 | ||
8bd5c820 | 104 | static inline int get_a64_user_mem_index(DisasContext *s) |
579d21cc | 105 | { |
8bd5c820 | 106 | /* Return the core mmu_idx to use for A64 "unprivileged load/store" insns: |
579d21cc PM |
107 | * if EL1, access as if EL0; otherwise access at current EL |
108 | */ | |
8bd5c820 PM |
109 | ARMMMUIdx useridx; |
110 | ||
579d21cc PM |
111 | switch (s->mmu_idx) { |
112 | case ARMMMUIdx_S12NSE1: | |
8bd5c820 PM |
113 | useridx = ARMMMUIdx_S12NSE0; |
114 | break; | |
579d21cc | 115 | case ARMMMUIdx_S1SE1: |
8bd5c820 PM |
116 | useridx = ARMMMUIdx_S1SE0; |
117 | break; | |
579d21cc PM |
118 | case ARMMMUIdx_S2NS: |
119 | g_assert_not_reached(); | |
120 | default: | |
8bd5c820 PM |
121 | useridx = s->mmu_idx; |
122 | break; | |
579d21cc | 123 | } |
8bd5c820 | 124 | return arm_to_core_mmu_idx(useridx); |
579d21cc PM |
125 | } |
126 | ||
14ade10f AG |
127 | void aarch64_cpu_dump_state(CPUState *cs, FILE *f, |
128 | fprintf_function cpu_fprintf, int flags) | |
129 | { | |
130 | ARMCPU *cpu = ARM_CPU(cs); | |
131 | CPUARMState *env = &cpu->env; | |
d356312f | 132 | uint32_t psr = pstate_read(env); |
14ade10f | 133 | int i; |
08b8e0f5 | 134 | int el = arm_current_el(env); |
06e5cf7a | 135 | const char *ns_status; |
14ade10f AG |
136 | |
137 | cpu_fprintf(f, "PC=%016"PRIx64" SP=%016"PRIx64"\n", | |
138 | env->pc, env->xregs[31]); | |
139 | for (i = 0; i < 31; i++) { | |
140 | cpu_fprintf(f, "X%02d=%016"PRIx64, i, env->xregs[i]); | |
141 | if ((i % 4) == 3) { | |
142 | cpu_fprintf(f, "\n"); | |
143 | } else { | |
144 | cpu_fprintf(f, " "); | |
145 | } | |
146 | } | |
06e5cf7a PM |
147 | |
148 | if (arm_feature(env, ARM_FEATURE_EL3) && el != 3) { | |
149 | ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; | |
150 | } else { | |
151 | ns_status = ""; | |
152 | } | |
153 | ||
154 | cpu_fprintf(f, "\nPSTATE=%08x %c%c%c%c %sEL%d%c\n", | |
d356312f PM |
155 | psr, |
156 | psr & PSTATE_N ? 'N' : '-', | |
157 | psr & PSTATE_Z ? 'Z' : '-', | |
158 | psr & PSTATE_C ? 'C' : '-', | |
08b8e0f5 | 159 | psr & PSTATE_V ? 'V' : '-', |
06e5cf7a | 160 | ns_status, |
08b8e0f5 PM |
161 | el, |
162 | psr & PSTATE_SP ? 'h' : 't'); | |
f6d8a314 AG |
163 | |
164 | if (flags & CPU_DUMP_FPU) { | |
165 | int numvfpregs = 32; | |
166 | for (i = 0; i < numvfpregs; i += 2) { | |
167 | uint64_t vlo = float64_val(env->vfp.regs[i * 2]); | |
168 | uint64_t vhi = float64_val(env->vfp.regs[(i * 2) + 1]); | |
169 | cpu_fprintf(f, "q%02d=%016" PRIx64 ":%016" PRIx64 " ", | |
170 | i, vhi, vlo); | |
171 | vlo = float64_val(env->vfp.regs[(i + 1) * 2]); | |
172 | vhi = float64_val(env->vfp.regs[((i + 1) * 2) + 1]); | |
173 | cpu_fprintf(f, "q%02d=%016" PRIx64 ":%016" PRIx64 "\n", | |
174 | i + 1, vhi, vlo); | |
175 | } | |
176 | cpu_fprintf(f, "FPCR: %08x FPSR: %08x\n", | |
177 | vfp_get_fpcr(env), vfp_get_fpsr(env)); | |
178 | } | |
14ade10f AG |
179 | } |
180 | ||
181 | void gen_a64_set_pc_im(uint64_t val) | |
182 | { | |
183 | tcg_gen_movi_i64(cpu_pc, val); | |
184 | } | |
185 | ||
6feecb8b TH |
186 | /* Load the PC from a generic TCG variable. |
187 | * | |
188 | * If address tagging is enabled via the TCR TBI bits, then loading | |
189 | * an address into the PC will clear out any tag in the it: | |
190 | * + for EL2 and EL3 there is only one TBI bit, and if it is set | |
191 | * then the address is zero-extended, clearing bits [63:56] | |
192 | * + for EL0 and EL1, TBI0 controls addresses with bit 55 == 0 | |
193 | * and TBI1 controls addressses with bit 55 == 1. | |
194 | * If the appropriate TBI bit is set for the address then | |
195 | * the address is sign-extended from bit 55 into bits [63:56] | |
196 | * | |
197 | * We can avoid doing this for relative-branches, because the | |
198 | * PC + offset can never overflow into the tag bits (assuming | |
199 | * that virtual addresses are less than 56 bits wide, as they | |
200 | * are currently), but we must handle it for branch-to-register. | |
201 | */ | |
202 | static void gen_a64_set_pc(DisasContext *s, TCGv_i64 src) | |
203 | { | |
204 | ||
205 | if (s->current_el <= 1) { | |
206 | /* Test if NEITHER or BOTH TBI values are set. If so, no need to | |
207 | * examine bit 55 of address, can just generate code. | |
208 | * If mixed, then test via generated code | |
209 | */ | |
210 | if (s->tbi0 && s->tbi1) { | |
211 | TCGv_i64 tmp_reg = tcg_temp_new_i64(); | |
212 | /* Both bits set, sign extension from bit 55 into [63:56] will | |
213 | * cover both cases | |
214 | */ | |
215 | tcg_gen_shli_i64(tmp_reg, src, 8); | |
216 | tcg_gen_sari_i64(cpu_pc, tmp_reg, 8); | |
217 | tcg_temp_free_i64(tmp_reg); | |
218 | } else if (!s->tbi0 && !s->tbi1) { | |
219 | /* Neither bit set, just load it as-is */ | |
220 | tcg_gen_mov_i64(cpu_pc, src); | |
221 | } else { | |
222 | TCGv_i64 tcg_tmpval = tcg_temp_new_i64(); | |
223 | TCGv_i64 tcg_bit55 = tcg_temp_new_i64(); | |
224 | TCGv_i64 tcg_zero = tcg_const_i64(0); | |
225 | ||
226 | tcg_gen_andi_i64(tcg_bit55, src, (1ull << 55)); | |
227 | ||
228 | if (s->tbi0) { | |
229 | /* tbi0==1, tbi1==0, so 0-fill upper byte if bit 55 = 0 */ | |
230 | tcg_gen_andi_i64(tcg_tmpval, src, | |
231 | 0x00FFFFFFFFFFFFFFull); | |
232 | tcg_gen_movcond_i64(TCG_COND_EQ, cpu_pc, tcg_bit55, tcg_zero, | |
233 | tcg_tmpval, src); | |
234 | } else { | |
235 | /* tbi0==0, tbi1==1, so 1-fill upper byte if bit 55 = 1 */ | |
236 | tcg_gen_ori_i64(tcg_tmpval, src, | |
237 | 0xFF00000000000000ull); | |
238 | tcg_gen_movcond_i64(TCG_COND_NE, cpu_pc, tcg_bit55, tcg_zero, | |
239 | tcg_tmpval, src); | |
240 | } | |
241 | tcg_temp_free_i64(tcg_zero); | |
242 | tcg_temp_free_i64(tcg_bit55); | |
243 | tcg_temp_free_i64(tcg_tmpval); | |
244 | } | |
245 | } else { /* EL > 1 */ | |
246 | if (s->tbi0) { | |
247 | /* Force tag byte to all zero */ | |
248 | tcg_gen_andi_i64(cpu_pc, src, 0x00FFFFFFFFFFFFFFull); | |
249 | } else { | |
250 | /* Load unmodified address */ | |
251 | tcg_gen_mov_i64(cpu_pc, src); | |
252 | } | |
253 | } | |
254 | } | |
255 | ||
259cb684 RH |
256 | typedef struct DisasCompare64 { |
257 | TCGCond cond; | |
258 | TCGv_i64 value; | |
259 | } DisasCompare64; | |
260 | ||
261 | static void a64_test_cc(DisasCompare64 *c64, int cc) | |
262 | { | |
263 | DisasCompare c32; | |
264 | ||
265 | arm_test_cc(&c32, cc); | |
266 | ||
267 | /* Sign-extend the 32-bit value so that the GE/LT comparisons work | |
268 | * properly. The NE/EQ comparisons are also fine with this choice. */ | |
269 | c64->cond = c32.cond; | |
270 | c64->value = tcg_temp_new_i64(); | |
271 | tcg_gen_ext_i32_i64(c64->value, c32.value); | |
272 | ||
273 | arm_free_cc(&c32); | |
274 | } | |
275 | ||
276 | static void a64_free_cc(DisasCompare64 *c64) | |
277 | { | |
278 | tcg_temp_free_i64(c64->value); | |
279 | } | |
280 | ||
d4a2dc67 | 281 | static void gen_exception_internal(int excp) |
14ade10f | 282 | { |
d4a2dc67 PM |
283 | TCGv_i32 tcg_excp = tcg_const_i32(excp); |
284 | ||
285 | assert(excp_is_internal(excp)); | |
286 | gen_helper_exception_internal(cpu_env, tcg_excp); | |
287 | tcg_temp_free_i32(tcg_excp); | |
288 | } | |
289 | ||
73710361 | 290 | static void gen_exception(int excp, uint32_t syndrome, uint32_t target_el) |
d4a2dc67 PM |
291 | { |
292 | TCGv_i32 tcg_excp = tcg_const_i32(excp); | |
293 | TCGv_i32 tcg_syn = tcg_const_i32(syndrome); | |
73710361 | 294 | TCGv_i32 tcg_el = tcg_const_i32(target_el); |
d4a2dc67 | 295 | |
73710361 GB |
296 | gen_helper_exception_with_syndrome(cpu_env, tcg_excp, |
297 | tcg_syn, tcg_el); | |
298 | tcg_temp_free_i32(tcg_el); | |
d4a2dc67 PM |
299 | tcg_temp_free_i32(tcg_syn); |
300 | tcg_temp_free_i32(tcg_excp); | |
301 | } | |
302 | ||
303 | static void gen_exception_internal_insn(DisasContext *s, int offset, int excp) | |
304 | { | |
305 | gen_a64_set_pc_im(s->pc - offset); | |
306 | gen_exception_internal(excp); | |
307 | s->is_jmp = DISAS_EXC; | |
14ade10f AG |
308 | } |
309 | ||
d4a2dc67 | 310 | static void gen_exception_insn(DisasContext *s, int offset, int excp, |
73710361 | 311 | uint32_t syndrome, uint32_t target_el) |
14ade10f AG |
312 | { |
313 | gen_a64_set_pc_im(s->pc - offset); | |
73710361 | 314 | gen_exception(excp, syndrome, target_el); |
40f860cd PM |
315 | s->is_jmp = DISAS_EXC; |
316 | } | |
317 | ||
7ea47fe7 PM |
318 | static void gen_ss_advance(DisasContext *s) |
319 | { | |
320 | /* If the singlestep state is Active-not-pending, advance to | |
321 | * Active-pending. | |
322 | */ | |
323 | if (s->ss_active) { | |
324 | s->pstate_ss = 0; | |
325 | gen_helper_clear_pstate_ss(cpu_env); | |
326 | } | |
327 | } | |
328 | ||
329 | static void gen_step_complete_exception(DisasContext *s) | |
330 | { | |
331 | /* We just completed step of an insn. Move from Active-not-pending | |
332 | * to Active-pending, and then also take the swstep exception. | |
333 | * This corresponds to making the (IMPDEF) choice to prioritize | |
334 | * swstep exceptions over asynchronous exceptions taken to an exception | |
335 | * level where debug is disabled. This choice has the advantage that | |
336 | * we do not need to maintain internal state corresponding to the | |
337 | * ISV/EX syndrome bits between completion of the step and generation | |
338 | * of the exception, and our syndrome information is always correct. | |
339 | */ | |
340 | gen_ss_advance(s); | |
73710361 GB |
341 | gen_exception(EXCP_UDEF, syn_swstep(s->ss_same_el, 1, s->is_ldex), |
342 | default_exception_el(s)); | |
7ea47fe7 PM |
343 | s->is_jmp = DISAS_EXC; |
344 | } | |
345 | ||
40f860cd PM |
346 | static inline bool use_goto_tb(DisasContext *s, int n, uint64_t dest) |
347 | { | |
7ea47fe7 PM |
348 | /* No direct tb linking with singlestep (either QEMU's or the ARM |
349 | * debug architecture kind) or deterministic io | |
350 | */ | |
351 | if (s->singlestep_enabled || s->ss_active || (s->tb->cflags & CF_LAST_IO)) { | |
40f860cd PM |
352 | return false; |
353 | } | |
354 | ||
90aa39a1 | 355 | #ifndef CONFIG_USER_ONLY |
40f860cd PM |
356 | /* Only link tbs from inside the same guest page */ |
357 | if ((s->tb->pc & TARGET_PAGE_MASK) != (dest & TARGET_PAGE_MASK)) { | |
358 | return false; | |
359 | } | |
90aa39a1 | 360 | #endif |
40f860cd PM |
361 | |
362 | return true; | |
363 | } | |
364 | ||
365 | static inline void gen_goto_tb(DisasContext *s, int n, uint64_t dest) | |
366 | { | |
367 | TranslationBlock *tb; | |
368 | ||
369 | tb = s->tb; | |
370 | if (use_goto_tb(s, n, dest)) { | |
371 | tcg_gen_goto_tb(n); | |
372 | gen_a64_set_pc_im(dest); | |
0624976f | 373 | tcg_gen_exit_tb((intptr_t)tb + n); |
40f860cd PM |
374 | s->is_jmp = DISAS_TB_JUMP; |
375 | } else { | |
376 | gen_a64_set_pc_im(dest); | |
7ea47fe7 PM |
377 | if (s->ss_active) { |
378 | gen_step_complete_exception(s); | |
379 | } else if (s->singlestep_enabled) { | |
d4a2dc67 | 380 | gen_exception_internal(EXCP_DEBUG); |
cc9c1ed1 | 381 | } else { |
e7872236 | 382 | tcg_gen_lookup_and_goto_ptr(cpu_pc); |
cc9c1ed1 | 383 | s->is_jmp = DISAS_TB_JUMP; |
40f860cd | 384 | } |
40f860cd | 385 | } |
14ade10f AG |
386 | } |
387 | ||
ad7ee8a2 | 388 | static void unallocated_encoding(DisasContext *s) |
14ade10f | 389 | { |
d4a2dc67 | 390 | /* Unallocated and reserved encodings are uncategorized */ |
73710361 GB |
391 | gen_exception_insn(s, 4, EXCP_UDEF, syn_uncategorized(), |
392 | default_exception_el(s)); | |
14ade10f AG |
393 | } |
394 | ||
ad7ee8a2 CF |
395 | #define unsupported_encoding(s, insn) \ |
396 | do { \ | |
397 | qemu_log_mask(LOG_UNIMP, \ | |
398 | "%s:%d: unsupported instruction encoding 0x%08x " \ | |
399 | "at pc=%016" PRIx64 "\n", \ | |
400 | __FILE__, __LINE__, insn, s->pc - 4); \ | |
401 | unallocated_encoding(s); \ | |
402 | } while (0); | |
14ade10f | 403 | |
11e169de AG |
404 | static void init_tmp_a64_array(DisasContext *s) |
405 | { | |
406 | #ifdef CONFIG_DEBUG_TCG | |
407 | int i; | |
408 | for (i = 0; i < ARRAY_SIZE(s->tmp_a64); i++) { | |
409 | TCGV_UNUSED_I64(s->tmp_a64[i]); | |
410 | } | |
411 | #endif | |
412 | s->tmp_a64_count = 0; | |
413 | } | |
414 | ||
415 | static void free_tmp_a64(DisasContext *s) | |
416 | { | |
417 | int i; | |
418 | for (i = 0; i < s->tmp_a64_count; i++) { | |
419 | tcg_temp_free_i64(s->tmp_a64[i]); | |
420 | } | |
421 | init_tmp_a64_array(s); | |
422 | } | |
423 | ||
424 | static TCGv_i64 new_tmp_a64(DisasContext *s) | |
425 | { | |
426 | assert(s->tmp_a64_count < TMP_A64_MAX); | |
427 | return s->tmp_a64[s->tmp_a64_count++] = tcg_temp_new_i64(); | |
428 | } | |
429 | ||
430 | static TCGv_i64 new_tmp_a64_zero(DisasContext *s) | |
431 | { | |
432 | TCGv_i64 t = new_tmp_a64(s); | |
433 | tcg_gen_movi_i64(t, 0); | |
434 | return t; | |
435 | } | |
436 | ||
71b46089 AG |
437 | /* |
438 | * Register access functions | |
439 | * | |
440 | * These functions are used for directly accessing a register in where | |
441 | * changes to the final register value are likely to be made. If you | |
442 | * need to use a register for temporary calculation (e.g. index type | |
443 | * operations) use the read_* form. | |
444 | * | |
445 | * B1.2.1 Register mappings | |
446 | * | |
447 | * In instruction register encoding 31 can refer to ZR (zero register) or | |
448 | * the SP (stack pointer) depending on context. In QEMU's case we map SP | |
449 | * to cpu_X[31] and ZR accesses to a temporary which can be discarded. | |
450 | * This is the point of the _sp forms. | |
451 | */ | |
11e169de AG |
452 | static TCGv_i64 cpu_reg(DisasContext *s, int reg) |
453 | { | |
454 | if (reg == 31) { | |
455 | return new_tmp_a64_zero(s); | |
456 | } else { | |
457 | return cpu_X[reg]; | |
458 | } | |
459 | } | |
460 | ||
71b46089 AG |
461 | /* register access for when 31 == SP */ |
462 | static TCGv_i64 cpu_reg_sp(DisasContext *s, int reg) | |
463 | { | |
464 | return cpu_X[reg]; | |
465 | } | |
466 | ||
60e53388 AG |
467 | /* read a cpu register in 32bit/64bit mode. Returns a TCGv_i64 |
468 | * representing the register contents. This TCGv is an auto-freed | |
469 | * temporary so it need not be explicitly freed, and may be modified. | |
470 | */ | |
471 | static TCGv_i64 read_cpu_reg(DisasContext *s, int reg, int sf) | |
472 | { | |
473 | TCGv_i64 v = new_tmp_a64(s); | |
474 | if (reg != 31) { | |
475 | if (sf) { | |
476 | tcg_gen_mov_i64(v, cpu_X[reg]); | |
477 | } else { | |
478 | tcg_gen_ext32u_i64(v, cpu_X[reg]); | |
479 | } | |
480 | } else { | |
481 | tcg_gen_movi_i64(v, 0); | |
482 | } | |
483 | return v; | |
484 | } | |
485 | ||
4a08d475 PM |
486 | static TCGv_i64 read_cpu_reg_sp(DisasContext *s, int reg, int sf) |
487 | { | |
488 | TCGv_i64 v = new_tmp_a64(s); | |
489 | if (sf) { | |
490 | tcg_gen_mov_i64(v, cpu_X[reg]); | |
491 | } else { | |
492 | tcg_gen_ext32u_i64(v, cpu_X[reg]); | |
493 | } | |
494 | return v; | |
495 | } | |
496 | ||
90e49638 PM |
497 | /* We should have at some point before trying to access an FP register |
498 | * done the necessary access check, so assert that | |
499 | * (a) we did the check and | |
500 | * (b) we didn't then just plough ahead anyway if it failed. | |
501 | * Print the instruction pattern in the abort message so we can figure | |
502 | * out what we need to fix if a user encounters this problem in the wild. | |
503 | */ | |
504 | static inline void assert_fp_access_checked(DisasContext *s) | |
505 | { | |
506 | #ifdef CONFIG_DEBUG_TCG | |
9dbbc748 | 507 | if (unlikely(!s->fp_access_checked || s->fp_excp_el)) { |
90e49638 PM |
508 | fprintf(stderr, "target-arm: FP access check missing for " |
509 | "instruction 0x%08x\n", s->insn); | |
510 | abort(); | |
511 | } | |
512 | #endif | |
513 | } | |
514 | ||
72430bf5 AB |
515 | /* Return the offset into CPUARMState of an element of specified |
516 | * size, 'element' places in from the least significant end of | |
517 | * the FP/vector register Qn. | |
518 | */ | |
90e49638 PM |
519 | static inline int vec_reg_offset(DisasContext *s, int regno, |
520 | int element, TCGMemOp size) | |
72430bf5 | 521 | { |
416d72b9 | 522 | int offs = 0; |
72430bf5 AB |
523 | #ifdef HOST_WORDS_BIGENDIAN |
524 | /* This is complicated slightly because vfp.regs[2n] is | |
525 | * still the low half and vfp.regs[2n+1] the high half | |
526 | * of the 128 bit vector, even on big endian systems. | |
527 | * Calculate the offset assuming a fully bigendian 128 bits, | |
528 | * then XOR to account for the order of the two 64 bit halves. | |
529 | */ | |
530 | offs += (16 - ((element + 1) * (1 << size))); | |
531 | offs ^= 8; | |
532 | #else | |
533 | offs += element * (1 << size); | |
534 | #endif | |
416d72b9 | 535 | offs += offsetof(CPUARMState, vfp.regs[regno * 2]); |
90e49638 | 536 | assert_fp_access_checked(s); |
72430bf5 AB |
537 | return offs; |
538 | } | |
539 | ||
e2f90565 PM |
540 | /* Return the offset into CPUARMState of a slice (from |
541 | * the least significant end) of FP register Qn (ie | |
542 | * Dn, Sn, Hn or Bn). | |
543 | * (Note that this is not the same mapping as for A32; see cpu.h) | |
544 | */ | |
90e49638 | 545 | static inline int fp_reg_offset(DisasContext *s, int regno, TCGMemOp size) |
e2f90565 PM |
546 | { |
547 | int offs = offsetof(CPUARMState, vfp.regs[regno * 2]); | |
548 | #ifdef HOST_WORDS_BIGENDIAN | |
549 | offs += (8 - (1 << size)); | |
550 | #endif | |
90e49638 | 551 | assert_fp_access_checked(s); |
e2f90565 PM |
552 | return offs; |
553 | } | |
554 | ||
555 | /* Offset of the high half of the 128 bit vector Qn */ | |
90e49638 | 556 | static inline int fp_reg_hi_offset(DisasContext *s, int regno) |
e2f90565 | 557 | { |
90e49638 | 558 | assert_fp_access_checked(s); |
e2f90565 PM |
559 | return offsetof(CPUARMState, vfp.regs[regno * 2 + 1]); |
560 | } | |
561 | ||
ec73d2e0 AG |
562 | /* Convenience accessors for reading and writing single and double |
563 | * FP registers. Writing clears the upper parts of the associated | |
564 | * 128 bit vector register, as required by the architecture. | |
565 | * Note that unlike the GP register accessors, the values returned | |
566 | * by the read functions must be manually freed. | |
567 | */ | |
568 | static TCGv_i64 read_fp_dreg(DisasContext *s, int reg) | |
569 | { | |
570 | TCGv_i64 v = tcg_temp_new_i64(); | |
571 | ||
90e49638 | 572 | tcg_gen_ld_i64(v, cpu_env, fp_reg_offset(s, reg, MO_64)); |
ec73d2e0 AG |
573 | return v; |
574 | } | |
575 | ||
576 | static TCGv_i32 read_fp_sreg(DisasContext *s, int reg) | |
577 | { | |
578 | TCGv_i32 v = tcg_temp_new_i32(); | |
579 | ||
90e49638 | 580 | tcg_gen_ld_i32(v, cpu_env, fp_reg_offset(s, reg, MO_32)); |
ec73d2e0 AG |
581 | return v; |
582 | } | |
583 | ||
584 | static void write_fp_dreg(DisasContext *s, int reg, TCGv_i64 v) | |
585 | { | |
586 | TCGv_i64 tcg_zero = tcg_const_i64(0); | |
587 | ||
90e49638 PM |
588 | tcg_gen_st_i64(v, cpu_env, fp_reg_offset(s, reg, MO_64)); |
589 | tcg_gen_st_i64(tcg_zero, cpu_env, fp_reg_hi_offset(s, reg)); | |
ec73d2e0 AG |
590 | tcg_temp_free_i64(tcg_zero); |
591 | } | |
592 | ||
593 | static void write_fp_sreg(DisasContext *s, int reg, TCGv_i32 v) | |
594 | { | |
595 | TCGv_i64 tmp = tcg_temp_new_i64(); | |
596 | ||
597 | tcg_gen_extu_i32_i64(tmp, v); | |
598 | write_fp_dreg(s, reg, tmp); | |
599 | tcg_temp_free_i64(tmp); | |
600 | } | |
601 | ||
602 | static TCGv_ptr get_fpstatus_ptr(void) | |
603 | { | |
604 | TCGv_ptr statusptr = tcg_temp_new_ptr(); | |
605 | int offset; | |
606 | ||
607 | /* In A64 all instructions (both FP and Neon) use the FPCR; | |
608 | * there is no equivalent of the A32 Neon "standard FPSCR value" | |
609 | * and all operations use vfp.fp_status. | |
610 | */ | |
611 | offset = offsetof(CPUARMState, vfp.fp_status); | |
612 | tcg_gen_addi_ptr(statusptr, cpu_env, offset); | |
613 | return statusptr; | |
614 | } | |
615 | ||
832ffa1c AG |
616 | /* Set ZF and NF based on a 64 bit result. This is alas fiddlier |
617 | * than the 32 bit equivalent. | |
618 | */ | |
619 | static inline void gen_set_NZ64(TCGv_i64 result) | |
620 | { | |
7cb36e18 RH |
621 | tcg_gen_extr_i64_i32(cpu_ZF, cpu_NF, result); |
622 | tcg_gen_or_i32(cpu_ZF, cpu_ZF, cpu_NF); | |
832ffa1c AG |
623 | } |
624 | ||
625 | /* Set NZCV as for a logical operation: NZ as per result, CV cleared. */ | |
626 | static inline void gen_logic_CC(int sf, TCGv_i64 result) | |
627 | { | |
628 | if (sf) { | |
629 | gen_set_NZ64(result); | |
630 | } else { | |
ecc7b3aa | 631 | tcg_gen_extrl_i64_i32(cpu_ZF, result); |
7cb36e18 | 632 | tcg_gen_mov_i32(cpu_NF, cpu_ZF); |
832ffa1c AG |
633 | } |
634 | tcg_gen_movi_i32(cpu_CF, 0); | |
635 | tcg_gen_movi_i32(cpu_VF, 0); | |
636 | } | |
637 | ||
b0ff21b4 AB |
638 | /* dest = T0 + T1; compute C, N, V and Z flags */ |
639 | static void gen_add_CC(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1) | |
640 | { | |
641 | if (sf) { | |
642 | TCGv_i64 result, flag, tmp; | |
643 | result = tcg_temp_new_i64(); | |
644 | flag = tcg_temp_new_i64(); | |
645 | tmp = tcg_temp_new_i64(); | |
646 | ||
647 | tcg_gen_movi_i64(tmp, 0); | |
648 | tcg_gen_add2_i64(result, flag, t0, tmp, t1, tmp); | |
649 | ||
ecc7b3aa | 650 | tcg_gen_extrl_i64_i32(cpu_CF, flag); |
b0ff21b4 AB |
651 | |
652 | gen_set_NZ64(result); | |
653 | ||
654 | tcg_gen_xor_i64(flag, result, t0); | |
655 | tcg_gen_xor_i64(tmp, t0, t1); | |
656 | tcg_gen_andc_i64(flag, flag, tmp); | |
657 | tcg_temp_free_i64(tmp); | |
7cb36e18 | 658 | tcg_gen_extrh_i64_i32(cpu_VF, flag); |
b0ff21b4 AB |
659 | |
660 | tcg_gen_mov_i64(dest, result); | |
661 | tcg_temp_free_i64(result); | |
662 | tcg_temp_free_i64(flag); | |
663 | } else { | |
664 | /* 32 bit arithmetic */ | |
665 | TCGv_i32 t0_32 = tcg_temp_new_i32(); | |
666 | TCGv_i32 t1_32 = tcg_temp_new_i32(); | |
667 | TCGv_i32 tmp = tcg_temp_new_i32(); | |
668 | ||
669 | tcg_gen_movi_i32(tmp, 0); | |
ecc7b3aa RH |
670 | tcg_gen_extrl_i64_i32(t0_32, t0); |
671 | tcg_gen_extrl_i64_i32(t1_32, t1); | |
b0ff21b4 AB |
672 | tcg_gen_add2_i32(cpu_NF, cpu_CF, t0_32, tmp, t1_32, tmp); |
673 | tcg_gen_mov_i32(cpu_ZF, cpu_NF); | |
674 | tcg_gen_xor_i32(cpu_VF, cpu_NF, t0_32); | |
675 | tcg_gen_xor_i32(tmp, t0_32, t1_32); | |
676 | tcg_gen_andc_i32(cpu_VF, cpu_VF, tmp); | |
677 | tcg_gen_extu_i32_i64(dest, cpu_NF); | |
678 | ||
679 | tcg_temp_free_i32(tmp); | |
680 | tcg_temp_free_i32(t0_32); | |
681 | tcg_temp_free_i32(t1_32); | |
682 | } | |
683 | } | |
684 | ||
685 | /* dest = T0 - T1; compute C, N, V and Z flags */ | |
686 | static void gen_sub_CC(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1) | |
687 | { | |
688 | if (sf) { | |
689 | /* 64 bit arithmetic */ | |
690 | TCGv_i64 result, flag, tmp; | |
691 | ||
692 | result = tcg_temp_new_i64(); | |
693 | flag = tcg_temp_new_i64(); | |
694 | tcg_gen_sub_i64(result, t0, t1); | |
695 | ||
696 | gen_set_NZ64(result); | |
697 | ||
698 | tcg_gen_setcond_i64(TCG_COND_GEU, flag, t0, t1); | |
ecc7b3aa | 699 | tcg_gen_extrl_i64_i32(cpu_CF, flag); |
b0ff21b4 AB |
700 | |
701 | tcg_gen_xor_i64(flag, result, t0); | |
702 | tmp = tcg_temp_new_i64(); | |
703 | tcg_gen_xor_i64(tmp, t0, t1); | |
704 | tcg_gen_and_i64(flag, flag, tmp); | |
705 | tcg_temp_free_i64(tmp); | |
7cb36e18 | 706 | tcg_gen_extrh_i64_i32(cpu_VF, flag); |
b0ff21b4 AB |
707 | tcg_gen_mov_i64(dest, result); |
708 | tcg_temp_free_i64(flag); | |
709 | tcg_temp_free_i64(result); | |
710 | } else { | |
711 | /* 32 bit arithmetic */ | |
712 | TCGv_i32 t0_32 = tcg_temp_new_i32(); | |
713 | TCGv_i32 t1_32 = tcg_temp_new_i32(); | |
714 | TCGv_i32 tmp; | |
715 | ||
ecc7b3aa RH |
716 | tcg_gen_extrl_i64_i32(t0_32, t0); |
717 | tcg_gen_extrl_i64_i32(t1_32, t1); | |
b0ff21b4 AB |
718 | tcg_gen_sub_i32(cpu_NF, t0_32, t1_32); |
719 | tcg_gen_mov_i32(cpu_ZF, cpu_NF); | |
720 | tcg_gen_setcond_i32(TCG_COND_GEU, cpu_CF, t0_32, t1_32); | |
721 | tcg_gen_xor_i32(cpu_VF, cpu_NF, t0_32); | |
722 | tmp = tcg_temp_new_i32(); | |
723 | tcg_gen_xor_i32(tmp, t0_32, t1_32); | |
724 | tcg_temp_free_i32(t0_32); | |
725 | tcg_temp_free_i32(t1_32); | |
726 | tcg_gen_and_i32(cpu_VF, cpu_VF, tmp); | |
727 | tcg_temp_free_i32(tmp); | |
728 | tcg_gen_extu_i32_i64(dest, cpu_NF); | |
729 | } | |
730 | } | |
731 | ||
643dbb07 CF |
732 | /* dest = T0 + T1 + CF; do not compute flags. */ |
733 | static void gen_adc(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1) | |
734 | { | |
735 | TCGv_i64 flag = tcg_temp_new_i64(); | |
736 | tcg_gen_extu_i32_i64(flag, cpu_CF); | |
737 | tcg_gen_add_i64(dest, t0, t1); | |
738 | tcg_gen_add_i64(dest, dest, flag); | |
739 | tcg_temp_free_i64(flag); | |
740 | ||
741 | if (!sf) { | |
742 | tcg_gen_ext32u_i64(dest, dest); | |
743 | } | |
744 | } | |
745 | ||
746 | /* dest = T0 + T1 + CF; compute C, N, V and Z flags. */ | |
747 | static void gen_adc_CC(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1) | |
748 | { | |
749 | if (sf) { | |
750 | TCGv_i64 result, cf_64, vf_64, tmp; | |
751 | result = tcg_temp_new_i64(); | |
752 | cf_64 = tcg_temp_new_i64(); | |
753 | vf_64 = tcg_temp_new_i64(); | |
754 | tmp = tcg_const_i64(0); | |
755 | ||
756 | tcg_gen_extu_i32_i64(cf_64, cpu_CF); | |
757 | tcg_gen_add2_i64(result, cf_64, t0, tmp, cf_64, tmp); | |
758 | tcg_gen_add2_i64(result, cf_64, result, cf_64, t1, tmp); | |
ecc7b3aa | 759 | tcg_gen_extrl_i64_i32(cpu_CF, cf_64); |
643dbb07 CF |
760 | gen_set_NZ64(result); |
761 | ||
762 | tcg_gen_xor_i64(vf_64, result, t0); | |
763 | tcg_gen_xor_i64(tmp, t0, t1); | |
764 | tcg_gen_andc_i64(vf_64, vf_64, tmp); | |
7cb36e18 | 765 | tcg_gen_extrh_i64_i32(cpu_VF, vf_64); |
643dbb07 CF |
766 | |
767 | tcg_gen_mov_i64(dest, result); | |
768 | ||
769 | tcg_temp_free_i64(tmp); | |
770 | tcg_temp_free_i64(vf_64); | |
771 | tcg_temp_free_i64(cf_64); | |
772 | tcg_temp_free_i64(result); | |
773 | } else { | |
774 | TCGv_i32 t0_32, t1_32, tmp; | |
775 | t0_32 = tcg_temp_new_i32(); | |
776 | t1_32 = tcg_temp_new_i32(); | |
777 | tmp = tcg_const_i32(0); | |
778 | ||
ecc7b3aa RH |
779 | tcg_gen_extrl_i64_i32(t0_32, t0); |
780 | tcg_gen_extrl_i64_i32(t1_32, t1); | |
643dbb07 CF |
781 | tcg_gen_add2_i32(cpu_NF, cpu_CF, t0_32, tmp, cpu_CF, tmp); |
782 | tcg_gen_add2_i32(cpu_NF, cpu_CF, cpu_NF, cpu_CF, t1_32, tmp); | |
783 | ||
784 | tcg_gen_mov_i32(cpu_ZF, cpu_NF); | |
785 | tcg_gen_xor_i32(cpu_VF, cpu_NF, t0_32); | |
786 | tcg_gen_xor_i32(tmp, t0_32, t1_32); | |
787 | tcg_gen_andc_i32(cpu_VF, cpu_VF, tmp); | |
788 | tcg_gen_extu_i32_i64(dest, cpu_NF); | |
789 | ||
790 | tcg_temp_free_i32(tmp); | |
791 | tcg_temp_free_i32(t1_32); | |
792 | tcg_temp_free_i32(t0_32); | |
793 | } | |
794 | } | |
795 | ||
4a08d475 PM |
796 | /* |
797 | * Load/Store generators | |
798 | */ | |
799 | ||
800 | /* | |
60510aed | 801 | * Store from GPR register to memory. |
4a08d475 | 802 | */ |
60510aed | 803 | static void do_gpr_st_memidx(DisasContext *s, TCGv_i64 source, |
aaa1f954 EI |
804 | TCGv_i64 tcg_addr, int size, int memidx, |
805 | bool iss_valid, | |
806 | unsigned int iss_srt, | |
807 | bool iss_sf, bool iss_ar) | |
60510aed PM |
808 | { |
809 | g_assert(size <= 3); | |
aa6489da | 810 | tcg_gen_qemu_st_i64(source, tcg_addr, memidx, s->be_data + size); |
aaa1f954 EI |
811 | |
812 | if (iss_valid) { | |
813 | uint32_t syn; | |
814 | ||
815 | syn = syn_data_abort_with_iss(0, | |
816 | size, | |
817 | false, | |
818 | iss_srt, | |
819 | iss_sf, | |
820 | iss_ar, | |
821 | 0, 0, 0, 0, 0, false); | |
822 | disas_set_insn_syndrome(s, syn); | |
823 | } | |
60510aed PM |
824 | } |
825 | ||
4a08d475 | 826 | static void do_gpr_st(DisasContext *s, TCGv_i64 source, |
aaa1f954 EI |
827 | TCGv_i64 tcg_addr, int size, |
828 | bool iss_valid, | |
829 | unsigned int iss_srt, | |
830 | bool iss_sf, bool iss_ar) | |
4a08d475 | 831 | { |
aaa1f954 EI |
832 | do_gpr_st_memidx(s, source, tcg_addr, size, get_mem_index(s), |
833 | iss_valid, iss_srt, iss_sf, iss_ar); | |
4a08d475 PM |
834 | } |
835 | ||
836 | /* | |
837 | * Load from memory to GPR register | |
838 | */ | |
aaa1f954 EI |
839 | static void do_gpr_ld_memidx(DisasContext *s, |
840 | TCGv_i64 dest, TCGv_i64 tcg_addr, | |
841 | int size, bool is_signed, | |
842 | bool extend, int memidx, | |
843 | bool iss_valid, unsigned int iss_srt, | |
844 | bool iss_sf, bool iss_ar) | |
4a08d475 | 845 | { |
aa6489da | 846 | TCGMemOp memop = s->be_data + size; |
4a08d475 PM |
847 | |
848 | g_assert(size <= 3); | |
849 | ||
850 | if (is_signed) { | |
851 | memop += MO_SIGN; | |
852 | } | |
853 | ||
60510aed | 854 | tcg_gen_qemu_ld_i64(dest, tcg_addr, memidx, memop); |
4a08d475 PM |
855 | |
856 | if (extend && is_signed) { | |
857 | g_assert(size < 3); | |
858 | tcg_gen_ext32u_i64(dest, dest); | |
859 | } | |
aaa1f954 EI |
860 | |
861 | if (iss_valid) { | |
862 | uint32_t syn; | |
863 | ||
864 | syn = syn_data_abort_with_iss(0, | |
865 | size, | |
866 | is_signed, | |
867 | iss_srt, | |
868 | iss_sf, | |
869 | iss_ar, | |
870 | 0, 0, 0, 0, 0, false); | |
871 | disas_set_insn_syndrome(s, syn); | |
872 | } | |
4a08d475 PM |
873 | } |
874 | ||
aaa1f954 EI |
875 | static void do_gpr_ld(DisasContext *s, |
876 | TCGv_i64 dest, TCGv_i64 tcg_addr, | |
877 | int size, bool is_signed, bool extend, | |
878 | bool iss_valid, unsigned int iss_srt, | |
879 | bool iss_sf, bool iss_ar) | |
60510aed PM |
880 | { |
881 | do_gpr_ld_memidx(s, dest, tcg_addr, size, is_signed, extend, | |
aaa1f954 EI |
882 | get_mem_index(s), |
883 | iss_valid, iss_srt, iss_sf, iss_ar); | |
60510aed PM |
884 | } |
885 | ||
4a08d475 PM |
886 | /* |
887 | * Store from FP register to memory | |
888 | */ | |
889 | static void do_fp_st(DisasContext *s, int srcidx, TCGv_i64 tcg_addr, int size) | |
890 | { | |
891 | /* This writes the bottom N bits of a 128 bit wide vector to memory */ | |
4a08d475 | 892 | TCGv_i64 tmp = tcg_temp_new_i64(); |
90e49638 | 893 | tcg_gen_ld_i64(tmp, cpu_env, fp_reg_offset(s, srcidx, MO_64)); |
4a08d475 | 894 | if (size < 4) { |
aa6489da PC |
895 | tcg_gen_qemu_st_i64(tmp, tcg_addr, get_mem_index(s), |
896 | s->be_data + size); | |
4a08d475 | 897 | } else { |
aa6489da | 898 | bool be = s->be_data == MO_BE; |
4a08d475 | 899 | TCGv_i64 tcg_hiaddr = tcg_temp_new_i64(); |
aa6489da | 900 | |
4a08d475 | 901 | tcg_gen_addi_i64(tcg_hiaddr, tcg_addr, 8); |
aa6489da PC |
902 | tcg_gen_qemu_st_i64(tmp, be ? tcg_hiaddr : tcg_addr, get_mem_index(s), |
903 | s->be_data | MO_Q); | |
904 | tcg_gen_ld_i64(tmp, cpu_env, fp_reg_hi_offset(s, srcidx)); | |
905 | tcg_gen_qemu_st_i64(tmp, be ? tcg_addr : tcg_hiaddr, get_mem_index(s), | |
906 | s->be_data | MO_Q); | |
4a08d475 PM |
907 | tcg_temp_free_i64(tcg_hiaddr); |
908 | } | |
909 | ||
910 | tcg_temp_free_i64(tmp); | |
911 | } | |
912 | ||
913 | /* | |
914 | * Load from memory to FP register | |
915 | */ | |
916 | static void do_fp_ld(DisasContext *s, int destidx, TCGv_i64 tcg_addr, int size) | |
917 | { | |
918 | /* This always zero-extends and writes to a full 128 bit wide vector */ | |
4a08d475 PM |
919 | TCGv_i64 tmplo = tcg_temp_new_i64(); |
920 | TCGv_i64 tmphi; | |
921 | ||
922 | if (size < 4) { | |
aa6489da | 923 | TCGMemOp memop = s->be_data + size; |
4a08d475 PM |
924 | tmphi = tcg_const_i64(0); |
925 | tcg_gen_qemu_ld_i64(tmplo, tcg_addr, get_mem_index(s), memop); | |
926 | } else { | |
aa6489da | 927 | bool be = s->be_data == MO_BE; |
4a08d475 | 928 | TCGv_i64 tcg_hiaddr; |
aa6489da | 929 | |
4a08d475 PM |
930 | tmphi = tcg_temp_new_i64(); |
931 | tcg_hiaddr = tcg_temp_new_i64(); | |
932 | ||
4a08d475 | 933 | tcg_gen_addi_i64(tcg_hiaddr, tcg_addr, 8); |
aa6489da PC |
934 | tcg_gen_qemu_ld_i64(tmplo, be ? tcg_hiaddr : tcg_addr, get_mem_index(s), |
935 | s->be_data | MO_Q); | |
936 | tcg_gen_qemu_ld_i64(tmphi, be ? tcg_addr : tcg_hiaddr, get_mem_index(s), | |
937 | s->be_data | MO_Q); | |
4a08d475 PM |
938 | tcg_temp_free_i64(tcg_hiaddr); |
939 | } | |
940 | ||
90e49638 PM |
941 | tcg_gen_st_i64(tmplo, cpu_env, fp_reg_offset(s, destidx, MO_64)); |
942 | tcg_gen_st_i64(tmphi, cpu_env, fp_reg_hi_offset(s, destidx)); | |
4a08d475 PM |
943 | |
944 | tcg_temp_free_i64(tmplo); | |
945 | tcg_temp_free_i64(tmphi); | |
946 | } | |
947 | ||
72430bf5 AB |
948 | /* |
949 | * Vector load/store helpers. | |
950 | * | |
951 | * The principal difference between this and a FP load is that we don't | |
952 | * zero extend as we are filling a partial chunk of the vector register. | |
953 | * These functions don't support 128 bit loads/stores, which would be | |
954 | * normal load/store operations. | |
a08582f4 PM |
955 | * |
956 | * The _i32 versions are useful when operating on 32 bit quantities | |
957 | * (eg for floating point single or using Neon helper functions). | |
72430bf5 AB |
958 | */ |
959 | ||
960 | /* Get value of an element within a vector register */ | |
961 | static void read_vec_element(DisasContext *s, TCGv_i64 tcg_dest, int srcidx, | |
962 | int element, TCGMemOp memop) | |
963 | { | |
90e49638 | 964 | int vect_off = vec_reg_offset(s, srcidx, element, memop & MO_SIZE); |
72430bf5 AB |
965 | switch (memop) { |
966 | case MO_8: | |
967 | tcg_gen_ld8u_i64(tcg_dest, cpu_env, vect_off); | |
968 | break; | |
969 | case MO_16: | |
970 | tcg_gen_ld16u_i64(tcg_dest, cpu_env, vect_off); | |
971 | break; | |
972 | case MO_32: | |
973 | tcg_gen_ld32u_i64(tcg_dest, cpu_env, vect_off); | |
974 | break; | |
975 | case MO_8|MO_SIGN: | |
976 | tcg_gen_ld8s_i64(tcg_dest, cpu_env, vect_off); | |
977 | break; | |
978 | case MO_16|MO_SIGN: | |
979 | tcg_gen_ld16s_i64(tcg_dest, cpu_env, vect_off); | |
980 | break; | |
981 | case MO_32|MO_SIGN: | |
982 | tcg_gen_ld32s_i64(tcg_dest, cpu_env, vect_off); | |
983 | break; | |
984 | case MO_64: | |
985 | case MO_64|MO_SIGN: | |
986 | tcg_gen_ld_i64(tcg_dest, cpu_env, vect_off); | |
987 | break; | |
988 | default: | |
989 | g_assert_not_reached(); | |
990 | } | |
991 | } | |
992 | ||
a08582f4 PM |
993 | static void read_vec_element_i32(DisasContext *s, TCGv_i32 tcg_dest, int srcidx, |
994 | int element, TCGMemOp memop) | |
995 | { | |
90e49638 | 996 | int vect_off = vec_reg_offset(s, srcidx, element, memop & MO_SIZE); |
a08582f4 PM |
997 | switch (memop) { |
998 | case MO_8: | |
999 | tcg_gen_ld8u_i32(tcg_dest, cpu_env, vect_off); | |
1000 | break; | |
1001 | case MO_16: | |
1002 | tcg_gen_ld16u_i32(tcg_dest, cpu_env, vect_off); | |
1003 | break; | |
1004 | case MO_8|MO_SIGN: | |
1005 | tcg_gen_ld8s_i32(tcg_dest, cpu_env, vect_off); | |
1006 | break; | |
1007 | case MO_16|MO_SIGN: | |
1008 | tcg_gen_ld16s_i32(tcg_dest, cpu_env, vect_off); | |
1009 | break; | |
1010 | case MO_32: | |
1011 | case MO_32|MO_SIGN: | |
1012 | tcg_gen_ld_i32(tcg_dest, cpu_env, vect_off); | |
1013 | break; | |
1014 | default: | |
1015 | g_assert_not_reached(); | |
1016 | } | |
1017 | } | |
1018 | ||
72430bf5 AB |
1019 | /* Set value of an element within a vector register */ |
1020 | static void write_vec_element(DisasContext *s, TCGv_i64 tcg_src, int destidx, | |
1021 | int element, TCGMemOp memop) | |
1022 | { | |
90e49638 | 1023 | int vect_off = vec_reg_offset(s, destidx, element, memop & MO_SIZE); |
72430bf5 AB |
1024 | switch (memop) { |
1025 | case MO_8: | |
1026 | tcg_gen_st8_i64(tcg_src, cpu_env, vect_off); | |
1027 | break; | |
1028 | case MO_16: | |
1029 | tcg_gen_st16_i64(tcg_src, cpu_env, vect_off); | |
1030 | break; | |
1031 | case MO_32: | |
1032 | tcg_gen_st32_i64(tcg_src, cpu_env, vect_off); | |
1033 | break; | |
1034 | case MO_64: | |
1035 | tcg_gen_st_i64(tcg_src, cpu_env, vect_off); | |
1036 | break; | |
1037 | default: | |
1038 | g_assert_not_reached(); | |
1039 | } | |
1040 | } | |
1041 | ||
1f8a73af PM |
1042 | static void write_vec_element_i32(DisasContext *s, TCGv_i32 tcg_src, |
1043 | int destidx, int element, TCGMemOp memop) | |
1044 | { | |
90e49638 | 1045 | int vect_off = vec_reg_offset(s, destidx, element, memop & MO_SIZE); |
1f8a73af PM |
1046 | switch (memop) { |
1047 | case MO_8: | |
1048 | tcg_gen_st8_i32(tcg_src, cpu_env, vect_off); | |
1049 | break; | |
1050 | case MO_16: | |
1051 | tcg_gen_st16_i32(tcg_src, cpu_env, vect_off); | |
1052 | break; | |
1053 | case MO_32: | |
1054 | tcg_gen_st_i32(tcg_src, cpu_env, vect_off); | |
1055 | break; | |
1056 | default: | |
1057 | g_assert_not_reached(); | |
1058 | } | |
1059 | } | |
1060 | ||
72430bf5 AB |
1061 | /* Clear the high 64 bits of a 128 bit vector (in general non-quad |
1062 | * vector ops all need to do this). | |
1063 | */ | |
1064 | static void clear_vec_high(DisasContext *s, int rd) | |
1065 | { | |
1066 | TCGv_i64 tcg_zero = tcg_const_i64(0); | |
1067 | ||
1068 | write_vec_element(s, tcg_zero, rd, 1, MO_64); | |
1069 | tcg_temp_free_i64(tcg_zero); | |
1070 | } | |
1071 | ||
1072 | /* Store from vector register to memory */ | |
1073 | static void do_vec_st(DisasContext *s, int srcidx, int element, | |
1074 | TCGv_i64 tcg_addr, int size) | |
1075 | { | |
aa6489da | 1076 | TCGMemOp memop = s->be_data + size; |
72430bf5 AB |
1077 | TCGv_i64 tcg_tmp = tcg_temp_new_i64(); |
1078 | ||
1079 | read_vec_element(s, tcg_tmp, srcidx, element, size); | |
1080 | tcg_gen_qemu_st_i64(tcg_tmp, tcg_addr, get_mem_index(s), memop); | |
1081 | ||
1082 | tcg_temp_free_i64(tcg_tmp); | |
1083 | } | |
1084 | ||
1085 | /* Load from memory to vector register */ | |
1086 | static void do_vec_ld(DisasContext *s, int destidx, int element, | |
1087 | TCGv_i64 tcg_addr, int size) | |
1088 | { | |
aa6489da | 1089 | TCGMemOp memop = s->be_data + size; |
72430bf5 AB |
1090 | TCGv_i64 tcg_tmp = tcg_temp_new_i64(); |
1091 | ||
1092 | tcg_gen_qemu_ld_i64(tcg_tmp, tcg_addr, get_mem_index(s), memop); | |
1093 | write_vec_element(s, tcg_tmp, destidx, element, size); | |
1094 | ||
1095 | tcg_temp_free_i64(tcg_tmp); | |
1096 | } | |
1097 | ||
8c6afa6a PM |
1098 | /* Check that FP/Neon access is enabled. If it is, return |
1099 | * true. If not, emit code to generate an appropriate exception, | |
1100 | * and return false; the caller should not emit any code for | |
1101 | * the instruction. Note that this check must happen after all | |
1102 | * unallocated-encoding checks (otherwise the syndrome information | |
1103 | * for the resulting exception will be incorrect). | |
1104 | */ | |
1105 | static inline bool fp_access_check(DisasContext *s) | |
1106 | { | |
90e49638 PM |
1107 | assert(!s->fp_access_checked); |
1108 | s->fp_access_checked = true; | |
1109 | ||
9dbbc748 | 1110 | if (!s->fp_excp_el) { |
8c6afa6a PM |
1111 | return true; |
1112 | } | |
1113 | ||
73710361 | 1114 | gen_exception_insn(s, 4, EXCP_UDEF, syn_fp_access_trap(1, 0xe, false), |
9dbbc748 | 1115 | s->fp_excp_el); |
8c6afa6a PM |
1116 | return false; |
1117 | } | |
1118 | ||
229b7a05 AB |
1119 | /* |
1120 | * This utility function is for doing register extension with an | |
1121 | * optional shift. You will likely want to pass a temporary for the | |
1122 | * destination register. See DecodeRegExtend() in the ARM ARM. | |
1123 | */ | |
1124 | static void ext_and_shift_reg(TCGv_i64 tcg_out, TCGv_i64 tcg_in, | |
1125 | int option, unsigned int shift) | |
1126 | { | |
1127 | int extsize = extract32(option, 0, 2); | |
1128 | bool is_signed = extract32(option, 2, 1); | |
1129 | ||
1130 | if (is_signed) { | |
1131 | switch (extsize) { | |
1132 | case 0: | |
1133 | tcg_gen_ext8s_i64(tcg_out, tcg_in); | |
1134 | break; | |
1135 | case 1: | |
1136 | tcg_gen_ext16s_i64(tcg_out, tcg_in); | |
1137 | break; | |
1138 | case 2: | |
1139 | tcg_gen_ext32s_i64(tcg_out, tcg_in); | |
1140 | break; | |
1141 | case 3: | |
1142 | tcg_gen_mov_i64(tcg_out, tcg_in); | |
1143 | break; | |
1144 | } | |
1145 | } else { | |
1146 | switch (extsize) { | |
1147 | case 0: | |
1148 | tcg_gen_ext8u_i64(tcg_out, tcg_in); | |
1149 | break; | |
1150 | case 1: | |
1151 | tcg_gen_ext16u_i64(tcg_out, tcg_in); | |
1152 | break; | |
1153 | case 2: | |
1154 | tcg_gen_ext32u_i64(tcg_out, tcg_in); | |
1155 | break; | |
1156 | case 3: | |
1157 | tcg_gen_mov_i64(tcg_out, tcg_in); | |
1158 | break; | |
1159 | } | |
1160 | } | |
1161 | ||
1162 | if (shift) { | |
1163 | tcg_gen_shli_i64(tcg_out, tcg_out, shift); | |
1164 | } | |
1165 | } | |
1166 | ||
4a08d475 PM |
1167 | static inline void gen_check_sp_alignment(DisasContext *s) |
1168 | { | |
1169 | /* The AArch64 architecture mandates that (if enabled via PSTATE | |
1170 | * or SCTLR bits) there is a check that SP is 16-aligned on every | |
1171 | * SP-relative load or store (with an exception generated if it is not). | |
1172 | * In line with general QEMU practice regarding misaligned accesses, | |
1173 | * we omit these checks for the sake of guest program performance. | |
1174 | * This function is provided as a hook so we can more easily add these | |
1175 | * checks in future (possibly as a "favour catching guest program bugs | |
1176 | * over speed" user selectable option). | |
1177 | */ | |
1178 | } | |
1179 | ||
384b26fb AB |
1180 | /* |
1181 | * This provides a simple table based table lookup decoder. It is | |
1182 | * intended to be used when the relevant bits for decode are too | |
1183 | * awkwardly placed and switch/if based logic would be confusing and | |
1184 | * deeply nested. Since it's a linear search through the table, tables | |
1185 | * should be kept small. | |
1186 | * | |
1187 | * It returns the first handler where insn & mask == pattern, or | |
1188 | * NULL if there is no match. | |
1189 | * The table is terminated by an empty mask (i.e. 0) | |
1190 | */ | |
1191 | static inline AArch64DecodeFn *lookup_disas_fn(const AArch64DecodeTable *table, | |
1192 | uint32_t insn) | |
1193 | { | |
1194 | const AArch64DecodeTable *tptr = table; | |
1195 | ||
1196 | while (tptr->mask) { | |
1197 | if ((insn & tptr->mask) == tptr->pattern) { | |
1198 | return tptr->disas_fn; | |
1199 | } | |
1200 | tptr++; | |
1201 | } | |
1202 | return NULL; | |
1203 | } | |
1204 | ||
ad7ee8a2 CF |
1205 | /* |
1206 | * the instruction disassembly implemented here matches | |
1207 | * the instruction encoding classifications in chapter 3 (C3) | |
1208 | * of the ARM Architecture Reference Manual (DDI0487A_a) | |
1209 | */ | |
1210 | ||
11e169de AG |
1211 | /* C3.2.7 Unconditional branch (immediate) |
1212 | * 31 30 26 25 0 | |
1213 | * +----+-----------+-------------------------------------+ | |
1214 | * | op | 0 0 1 0 1 | imm26 | | |
1215 | * +----+-----------+-------------------------------------+ | |
1216 | */ | |
ad7ee8a2 CF |
1217 | static void disas_uncond_b_imm(DisasContext *s, uint32_t insn) |
1218 | { | |
11e169de AG |
1219 | uint64_t addr = s->pc + sextract32(insn, 0, 26) * 4 - 4; |
1220 | ||
1743d55c | 1221 | if (insn & (1U << 31)) { |
11e169de AG |
1222 | /* C5.6.26 BL Branch with link */ |
1223 | tcg_gen_movi_i64(cpu_reg(s, 30), s->pc); | |
1224 | } | |
1225 | ||
1226 | /* C5.6.20 B Branch / C5.6.26 BL Branch with link */ | |
1227 | gen_goto_tb(s, 0, addr); | |
ad7ee8a2 CF |
1228 | } |
1229 | ||
60e53388 AG |
1230 | /* C3.2.1 Compare & branch (immediate) |
1231 | * 31 30 25 24 23 5 4 0 | |
1232 | * +----+-------------+----+---------------------+--------+ | |
1233 | * | sf | 0 1 1 0 1 0 | op | imm19 | Rt | | |
1234 | * +----+-------------+----+---------------------+--------+ | |
1235 | */ | |
ad7ee8a2 CF |
1236 | static void disas_comp_b_imm(DisasContext *s, uint32_t insn) |
1237 | { | |
60e53388 AG |
1238 | unsigned int sf, op, rt; |
1239 | uint64_t addr; | |
42a268c2 | 1240 | TCGLabel *label_match; |
60e53388 AG |
1241 | TCGv_i64 tcg_cmp; |
1242 | ||
1243 | sf = extract32(insn, 31, 1); | |
1244 | op = extract32(insn, 24, 1); /* 0: CBZ; 1: CBNZ */ | |
1245 | rt = extract32(insn, 0, 5); | |
1246 | addr = s->pc + sextract32(insn, 5, 19) * 4 - 4; | |
1247 | ||
1248 | tcg_cmp = read_cpu_reg(s, rt, sf); | |
1249 | label_match = gen_new_label(); | |
1250 | ||
1251 | tcg_gen_brcondi_i64(op ? TCG_COND_NE : TCG_COND_EQ, | |
1252 | tcg_cmp, 0, label_match); | |
1253 | ||
1254 | gen_goto_tb(s, 0, s->pc); | |
1255 | gen_set_label(label_match); | |
1256 | gen_goto_tb(s, 1, addr); | |
ad7ee8a2 CF |
1257 | } |
1258 | ||
db0f7958 AG |
1259 | /* C3.2.5 Test & branch (immediate) |
1260 | * 31 30 25 24 23 19 18 5 4 0 | |
1261 | * +----+-------------+----+-------+-------------+------+ | |
1262 | * | b5 | 0 1 1 0 1 1 | op | b40 | imm14 | Rt | | |
1263 | * +----+-------------+----+-------+-------------+------+ | |
1264 | */ | |
ad7ee8a2 CF |
1265 | static void disas_test_b_imm(DisasContext *s, uint32_t insn) |
1266 | { | |
db0f7958 AG |
1267 | unsigned int bit_pos, op, rt; |
1268 | uint64_t addr; | |
42a268c2 | 1269 | TCGLabel *label_match; |
db0f7958 AG |
1270 | TCGv_i64 tcg_cmp; |
1271 | ||
1272 | bit_pos = (extract32(insn, 31, 1) << 5) | extract32(insn, 19, 5); | |
1273 | op = extract32(insn, 24, 1); /* 0: TBZ; 1: TBNZ */ | |
1274 | addr = s->pc + sextract32(insn, 5, 14) * 4 - 4; | |
1275 | rt = extract32(insn, 0, 5); | |
1276 | ||
1277 | tcg_cmp = tcg_temp_new_i64(); | |
1278 | tcg_gen_andi_i64(tcg_cmp, cpu_reg(s, rt), (1ULL << bit_pos)); | |
1279 | label_match = gen_new_label(); | |
1280 | tcg_gen_brcondi_i64(op ? TCG_COND_NE : TCG_COND_EQ, | |
1281 | tcg_cmp, 0, label_match); | |
1282 | tcg_temp_free_i64(tcg_cmp); | |
1283 | gen_goto_tb(s, 0, s->pc); | |
1284 | gen_set_label(label_match); | |
1285 | gen_goto_tb(s, 1, addr); | |
ad7ee8a2 CF |
1286 | } |
1287 | ||
39fb730a AG |
1288 | /* C3.2.2 / C5.6.19 Conditional branch (immediate) |
1289 | * 31 25 24 23 5 4 3 0 | |
1290 | * +---------------+----+---------------------+----+------+ | |
1291 | * | 0 1 0 1 0 1 0 | o1 | imm19 | o0 | cond | | |
1292 | * +---------------+----+---------------------+----+------+ | |
1293 | */ | |
ad7ee8a2 CF |
1294 | static void disas_cond_b_imm(DisasContext *s, uint32_t insn) |
1295 | { | |
39fb730a AG |
1296 | unsigned int cond; |
1297 | uint64_t addr; | |
1298 | ||
1299 | if ((insn & (1 << 4)) || (insn & (1 << 24))) { | |
1300 | unallocated_encoding(s); | |
1301 | return; | |
1302 | } | |
1303 | addr = s->pc + sextract32(insn, 5, 19) * 4 - 4; | |
1304 | cond = extract32(insn, 0, 4); | |
1305 | ||
1306 | if (cond < 0x0e) { | |
1307 | /* genuinely conditional branches */ | |
42a268c2 | 1308 | TCGLabel *label_match = gen_new_label(); |
39fb730a AG |
1309 | arm_gen_test_cc(cond, label_match); |
1310 | gen_goto_tb(s, 0, s->pc); | |
1311 | gen_set_label(label_match); | |
1312 | gen_goto_tb(s, 1, addr); | |
1313 | } else { | |
1314 | /* 0xe and 0xf are both "always" conditions */ | |
1315 | gen_goto_tb(s, 0, addr); | |
1316 | } | |
ad7ee8a2 CF |
1317 | } |
1318 | ||
87462e0f CF |
1319 | /* C5.6.68 HINT */ |
1320 | static void handle_hint(DisasContext *s, uint32_t insn, | |
1321 | unsigned int op1, unsigned int op2, unsigned int crm) | |
1322 | { | |
1323 | unsigned int selector = crm << 3 | op2; | |
1324 | ||
1325 | if (op1 != 3) { | |
1326 | unallocated_encoding(s); | |
1327 | return; | |
1328 | } | |
1329 | ||
1330 | switch (selector) { | |
1331 | case 0: /* NOP */ | |
1332 | return; | |
1ed69e82 PM |
1333 | case 3: /* WFI */ |
1334 | s->is_jmp = DISAS_WFI; | |
1335 | return; | |
87462e0f | 1336 | case 1: /* YIELD */ |
c22edfeb AB |
1337 | if (!parallel_cpus) { |
1338 | s->is_jmp = DISAS_YIELD; | |
1339 | } | |
049e24a1 | 1340 | return; |
87462e0f | 1341 | case 2: /* WFE */ |
c22edfeb AB |
1342 | if (!parallel_cpus) { |
1343 | s->is_jmp = DISAS_WFE; | |
1344 | } | |
252ec405 | 1345 | return; |
87462e0f CF |
1346 | case 4: /* SEV */ |
1347 | case 5: /* SEVL */ | |
1348 | /* we treat all as NOP at least for now */ | |
1349 | return; | |
1350 | default: | |
1351 | /* default specified as NOP equivalent */ | |
1352 | return; | |
1353 | } | |
1354 | } | |
1355 | ||
fa2ef212 MM |
1356 | static void gen_clrex(DisasContext *s, uint32_t insn) |
1357 | { | |
1358 | tcg_gen_movi_i64(cpu_exclusive_addr, -1); | |
1359 | } | |
1360 | ||
87462e0f CF |
1361 | /* CLREX, DSB, DMB, ISB */ |
1362 | static void handle_sync(DisasContext *s, uint32_t insn, | |
1363 | unsigned int op1, unsigned int op2, unsigned int crm) | |
1364 | { | |
ce1bd93f PK |
1365 | TCGBar bar; |
1366 | ||
87462e0f CF |
1367 | if (op1 != 3) { |
1368 | unallocated_encoding(s); | |
1369 | return; | |
1370 | } | |
1371 | ||
1372 | switch (op2) { | |
1373 | case 2: /* CLREX */ | |
fa2ef212 | 1374 | gen_clrex(s, insn); |
87462e0f CF |
1375 | return; |
1376 | case 4: /* DSB */ | |
1377 | case 5: /* DMB */ | |
ce1bd93f PK |
1378 | switch (crm & 3) { |
1379 | case 1: /* MBReqTypes_Reads */ | |
1380 | bar = TCG_BAR_SC | TCG_MO_LD_LD | TCG_MO_LD_ST; | |
1381 | break; | |
1382 | case 2: /* MBReqTypes_Writes */ | |
1383 | bar = TCG_BAR_SC | TCG_MO_ST_ST; | |
1384 | break; | |
1385 | default: /* MBReqTypes_All */ | |
1386 | bar = TCG_BAR_SC | TCG_MO_ALL; | |
1387 | break; | |
1388 | } | |
1389 | tcg_gen_mb(bar); | |
87462e0f | 1390 | return; |
6df99dec SS |
1391 | case 6: /* ISB */ |
1392 | /* We need to break the TB after this insn to execute | |
1393 | * a self-modified code correctly and also to take | |
1394 | * any pending interrupts immediately. | |
1395 | */ | |
1396 | s->is_jmp = DISAS_UPDATE; | |
1397 | return; | |
87462e0f CF |
1398 | default: |
1399 | unallocated_encoding(s); | |
1400 | return; | |
1401 | } | |
1402 | } | |
1403 | ||
1404 | /* C5.6.130 MSR (immediate) - move immediate to processor state field */ | |
1405 | static void handle_msr_i(DisasContext *s, uint32_t insn, | |
1406 | unsigned int op1, unsigned int op2, unsigned int crm) | |
1407 | { | |
9cfa0b4e PM |
1408 | int op = op1 << 3 | op2; |
1409 | switch (op) { | |
1410 | case 0x05: /* SPSel */ | |
dcbff19b | 1411 | if (s->current_el == 0) { |
9cfa0b4e PM |
1412 | unallocated_encoding(s); |
1413 | return; | |
1414 | } | |
1415 | /* fall through */ | |
1416 | case 0x1e: /* DAIFSet */ | |
1417 | case 0x1f: /* DAIFClear */ | |
1418 | { | |
1419 | TCGv_i32 tcg_imm = tcg_const_i32(crm); | |
1420 | TCGv_i32 tcg_op = tcg_const_i32(op); | |
1421 | gen_a64_set_pc_im(s->pc - 4); | |
1422 | gen_helper_msr_i_pstate(cpu_env, tcg_op, tcg_imm); | |
1423 | tcg_temp_free_i32(tcg_imm); | |
1424 | tcg_temp_free_i32(tcg_op); | |
8da54b25 RH |
1425 | /* For DAIFClear, exit the cpu loop to re-evaluate pending IRQs. */ |
1426 | gen_a64_set_pc_im(s->pc); | |
1427 | s->is_jmp = (op == 0x1f ? DISAS_EXIT : DISAS_JUMP); | |
9cfa0b4e PM |
1428 | break; |
1429 | } | |
1430 | default: | |
1431 | unallocated_encoding(s); | |
1432 | return; | |
1433 | } | |
87462e0f CF |
1434 | } |
1435 | ||
b0d2b7d0 PM |
1436 | static void gen_get_nzcv(TCGv_i64 tcg_rt) |
1437 | { | |
1438 | TCGv_i32 tmp = tcg_temp_new_i32(); | |
1439 | TCGv_i32 nzcv = tcg_temp_new_i32(); | |
1440 | ||
1441 | /* build bit 31, N */ | |
1743d55c | 1442 | tcg_gen_andi_i32(nzcv, cpu_NF, (1U << 31)); |
b0d2b7d0 PM |
1443 | /* build bit 30, Z */ |
1444 | tcg_gen_setcondi_i32(TCG_COND_EQ, tmp, cpu_ZF, 0); | |
1445 | tcg_gen_deposit_i32(nzcv, nzcv, tmp, 30, 1); | |
1446 | /* build bit 29, C */ | |
1447 | tcg_gen_deposit_i32(nzcv, nzcv, cpu_CF, 29, 1); | |
1448 | /* build bit 28, V */ | |
1449 | tcg_gen_shri_i32(tmp, cpu_VF, 31); | |
1450 | tcg_gen_deposit_i32(nzcv, nzcv, tmp, 28, 1); | |
1451 | /* generate result */ | |
1452 | tcg_gen_extu_i32_i64(tcg_rt, nzcv); | |
1453 | ||
1454 | tcg_temp_free_i32(nzcv); | |
1455 | tcg_temp_free_i32(tmp); | |
1456 | } | |
1457 | ||
1458 | static void gen_set_nzcv(TCGv_i64 tcg_rt) | |
1459 | ||
1460 | { | |
1461 | TCGv_i32 nzcv = tcg_temp_new_i32(); | |
1462 | ||
1463 | /* take NZCV from R[t] */ | |
ecc7b3aa | 1464 | tcg_gen_extrl_i64_i32(nzcv, tcg_rt); |
b0d2b7d0 PM |
1465 | |
1466 | /* bit 31, N */ | |
1743d55c | 1467 | tcg_gen_andi_i32(cpu_NF, nzcv, (1U << 31)); |
b0d2b7d0 PM |
1468 | /* bit 30, Z */ |
1469 | tcg_gen_andi_i32(cpu_ZF, nzcv, (1 << 30)); | |
1470 | tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_ZF, cpu_ZF, 0); | |
1471 | /* bit 29, C */ | |
1472 | tcg_gen_andi_i32(cpu_CF, nzcv, (1 << 29)); | |
1473 | tcg_gen_shri_i32(cpu_CF, cpu_CF, 29); | |
1474 | /* bit 28, V */ | |
1475 | tcg_gen_andi_i32(cpu_VF, nzcv, (1 << 28)); | |
1476 | tcg_gen_shli_i32(cpu_VF, cpu_VF, 3); | |
1477 | tcg_temp_free_i32(nzcv); | |
1478 | } | |
1479 | ||
fea50522 PM |
1480 | /* C5.6.129 MRS - move from system register |
1481 | * C5.6.131 MSR (register) - move to system register | |
1482 | * C5.6.204 SYS | |
1483 | * C5.6.205 SYSL | |
1484 | * These are all essentially the same insn in 'read' and 'write' | |
1485 | * versions, with varying op0 fields. | |
1486 | */ | |
1487 | static void handle_sys(DisasContext *s, uint32_t insn, bool isread, | |
1488 | unsigned int op0, unsigned int op1, unsigned int op2, | |
87462e0f CF |
1489 | unsigned int crn, unsigned int crm, unsigned int rt) |
1490 | { | |
fea50522 PM |
1491 | const ARMCPRegInfo *ri; |
1492 | TCGv_i64 tcg_rt; | |
87462e0f | 1493 | |
fea50522 PM |
1494 | ri = get_arm_cp_reginfo(s->cp_regs, |
1495 | ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, | |
1496 | crn, crm, op0, op1, op2)); | |
87462e0f | 1497 | |
fea50522 | 1498 | if (!ri) { |
626187d8 PM |
1499 | /* Unknown register; this might be a guest error or a QEMU |
1500 | * unimplemented feature. | |
1501 | */ | |
1502 | qemu_log_mask(LOG_UNIMP, "%s access to unsupported AArch64 " | |
1503 | "system register op0:%d op1:%d crn:%d crm:%d op2:%d\n", | |
1504 | isread ? "read" : "write", op0, op1, crn, crm, op2); | |
fea50522 PM |
1505 | unallocated_encoding(s); |
1506 | return; | |
1507 | } | |
1508 | ||
1509 | /* Check access permissions */ | |
dcbff19b | 1510 | if (!cp_access_ok(s->current_el, ri, isread)) { |
fea50522 PM |
1511 | unallocated_encoding(s); |
1512 | return; | |
1513 | } | |
1514 | ||
f59df3f2 PM |
1515 | if (ri->accessfn) { |
1516 | /* Emit code to perform further access permissions checks at | |
1517 | * runtime; this may result in an exception. | |
1518 | */ | |
1519 | TCGv_ptr tmpptr; | |
3f208fd7 | 1520 | TCGv_i32 tcg_syn, tcg_isread; |
8bcbf37c PM |
1521 | uint32_t syndrome; |
1522 | ||
f59df3f2 PM |
1523 | gen_a64_set_pc_im(s->pc - 4); |
1524 | tmpptr = tcg_const_ptr(ri); | |
8bcbf37c PM |
1525 | syndrome = syn_aa64_sysregtrap(op0, op1, op2, crn, crm, rt, isread); |
1526 | tcg_syn = tcg_const_i32(syndrome); | |
3f208fd7 PM |
1527 | tcg_isread = tcg_const_i32(isread); |
1528 | gen_helper_access_check_cp_reg(cpu_env, tmpptr, tcg_syn, tcg_isread); | |
f59df3f2 | 1529 | tcg_temp_free_ptr(tmpptr); |
8bcbf37c | 1530 | tcg_temp_free_i32(tcg_syn); |
3f208fd7 | 1531 | tcg_temp_free_i32(tcg_isread); |
f59df3f2 PM |
1532 | } |
1533 | ||
fea50522 PM |
1534 | /* Handle special cases first */ |
1535 | switch (ri->type & ~(ARM_CP_FLAG_MASK & ~ARM_CP_SPECIAL)) { | |
1536 | case ARM_CP_NOP: | |
1537 | return; | |
b0d2b7d0 PM |
1538 | case ARM_CP_NZCV: |
1539 | tcg_rt = cpu_reg(s, rt); | |
1540 | if (isread) { | |
1541 | gen_get_nzcv(tcg_rt); | |
1542 | } else { | |
1543 | gen_set_nzcv(tcg_rt); | |
1544 | } | |
1545 | return; | |
0eef9d98 PM |
1546 | case ARM_CP_CURRENTEL: |
1547 | /* Reads as current EL value from pstate, which is | |
1548 | * guaranteed to be constant by the tb flags. | |
1549 | */ | |
1550 | tcg_rt = cpu_reg(s, rt); | |
dcbff19b | 1551 | tcg_gen_movi_i64(tcg_rt, s->current_el << 2); |
0eef9d98 | 1552 | return; |
aca3f40b PM |
1553 | case ARM_CP_DC_ZVA: |
1554 | /* Writes clear the aligned block of memory which rt points into. */ | |
1555 | tcg_rt = cpu_reg(s, rt); | |
1556 | gen_helper_dc_zva(cpu_env, tcg_rt); | |
1557 | return; | |
fea50522 PM |
1558 | default: |
1559 | break; | |
1560 | } | |
1561 | ||
bd79255d | 1562 | if ((s->tb->cflags & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) { |
fea50522 PM |
1563 | gen_io_start(); |
1564 | } | |
1565 | ||
1566 | tcg_rt = cpu_reg(s, rt); | |
1567 | ||
1568 | if (isread) { | |
1569 | if (ri->type & ARM_CP_CONST) { | |
1570 | tcg_gen_movi_i64(tcg_rt, ri->resetvalue); | |
1571 | } else if (ri->readfn) { | |
1572 | TCGv_ptr tmpptr; | |
fea50522 PM |
1573 | tmpptr = tcg_const_ptr(ri); |
1574 | gen_helper_get_cp_reg64(tcg_rt, cpu_env, tmpptr); | |
1575 | tcg_temp_free_ptr(tmpptr); | |
1576 | } else { | |
1577 | tcg_gen_ld_i64(tcg_rt, cpu_env, ri->fieldoffset); | |
1578 | } | |
1579 | } else { | |
1580 | if (ri->type & ARM_CP_CONST) { | |
1581 | /* If not forbidden by access permissions, treat as WI */ | |
1582 | return; | |
1583 | } else if (ri->writefn) { | |
1584 | TCGv_ptr tmpptr; | |
fea50522 PM |
1585 | tmpptr = tcg_const_ptr(ri); |
1586 | gen_helper_set_cp_reg64(cpu_env, tmpptr, tcg_rt); | |
1587 | tcg_temp_free_ptr(tmpptr); | |
1588 | } else { | |
1589 | tcg_gen_st_i64(tcg_rt, cpu_env, ri->fieldoffset); | |
1590 | } | |
1591 | } | |
1592 | ||
bd79255d | 1593 | if ((s->tb->cflags & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) { |
fea50522 PM |
1594 | /* I/O operations must end the TB here (whether read or write) */ |
1595 | gen_io_end(); | |
1596 | s->is_jmp = DISAS_UPDATE; | |
1597 | } else if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) { | |
1598 | /* We default to ending the TB on a coprocessor register write, | |
1599 | * but allow this to be suppressed by the register definition | |
1600 | * (usually only necessary to work around guest bugs). | |
1601 | */ | |
1602 | s->is_jmp = DISAS_UPDATE; | |
1603 | } | |
ad7ee8a2 CF |
1604 | } |
1605 | ||
87462e0f CF |
1606 | /* C3.2.4 System |
1607 | * 31 22 21 20 19 18 16 15 12 11 8 7 5 4 0 | |
1608 | * +---------------------+---+-----+-----+-------+-------+-----+------+ | |
1609 | * | 1 1 0 1 0 1 0 1 0 0 | L | op0 | op1 | CRn | CRm | op2 | Rt | | |
1610 | * +---------------------+---+-----+-----+-------+-------+-----+------+ | |
1611 | */ | |
1612 | static void disas_system(DisasContext *s, uint32_t insn) | |
1613 | { | |
1614 | unsigned int l, op0, op1, crn, crm, op2, rt; | |
1615 | l = extract32(insn, 21, 1); | |
1616 | op0 = extract32(insn, 19, 2); | |
1617 | op1 = extract32(insn, 16, 3); | |
1618 | crn = extract32(insn, 12, 4); | |
1619 | crm = extract32(insn, 8, 4); | |
1620 | op2 = extract32(insn, 5, 3); | |
1621 | rt = extract32(insn, 0, 5); | |
1622 | ||
1623 | if (op0 == 0) { | |
1624 | if (l || rt != 31) { | |
1625 | unallocated_encoding(s); | |
1626 | return; | |
1627 | } | |
1628 | switch (crn) { | |
1629 | case 2: /* C5.6.68 HINT */ | |
1630 | handle_hint(s, insn, op1, op2, crm); | |
1631 | break; | |
1632 | case 3: /* CLREX, DSB, DMB, ISB */ | |
1633 | handle_sync(s, insn, op1, op2, crm); | |
1634 | break; | |
1635 | case 4: /* C5.6.130 MSR (immediate) */ | |
1636 | handle_msr_i(s, insn, op1, op2, crm); | |
1637 | break; | |
1638 | default: | |
1639 | unallocated_encoding(s); | |
1640 | break; | |
1641 | } | |
1642 | return; | |
1643 | } | |
fea50522 | 1644 | handle_sys(s, insn, l, op0, op1, op2, crn, crm, rt); |
87462e0f CF |
1645 | } |
1646 | ||
9618e809 AG |
1647 | /* C3.2.3 Exception generation |
1648 | * | |
1649 | * 31 24 23 21 20 5 4 2 1 0 | |
1650 | * +-----------------+-----+------------------------+-----+----+ | |
1651 | * | 1 1 0 1 0 1 0 0 | opc | imm16 | op2 | LL | | |
1652 | * +-----------------------+------------------------+----------+ | |
1653 | */ | |
ad7ee8a2 CF |
1654 | static void disas_exc(DisasContext *s, uint32_t insn) |
1655 | { | |
9618e809 AG |
1656 | int opc = extract32(insn, 21, 3); |
1657 | int op2_ll = extract32(insn, 0, 5); | |
d4a2dc67 | 1658 | int imm16 = extract32(insn, 5, 16); |
e0d6e6a5 | 1659 | TCGv_i32 tmp; |
9618e809 AG |
1660 | |
1661 | switch (opc) { | |
1662 | case 0: | |
7ea47fe7 PM |
1663 | /* For SVC, HVC and SMC we advance the single-step state |
1664 | * machine before taking the exception. This is architecturally | |
1665 | * mandated, to ensure that single-stepping a system call | |
1666 | * instruction works properly. | |
1667 | */ | |
35979d71 | 1668 | switch (op2_ll) { |
957956b3 | 1669 | case 1: /* SVC */ |
35979d71 | 1670 | gen_ss_advance(s); |
73710361 GB |
1671 | gen_exception_insn(s, 0, EXCP_SWI, syn_aa64_svc(imm16), |
1672 | default_exception_el(s)); | |
35979d71 | 1673 | break; |
957956b3 | 1674 | case 2: /* HVC */ |
dcbff19b | 1675 | if (s->current_el == 0) { |
35979d71 EI |
1676 | unallocated_encoding(s); |
1677 | break; | |
1678 | } | |
1679 | /* The pre HVC helper handles cases when HVC gets trapped | |
1680 | * as an undefined insn by runtime configuration. | |
1681 | */ | |
1682 | gen_a64_set_pc_im(s->pc - 4); | |
1683 | gen_helper_pre_hvc(cpu_env); | |
1684 | gen_ss_advance(s); | |
73710361 | 1685 | gen_exception_insn(s, 0, EXCP_HVC, syn_aa64_hvc(imm16), 2); |
35979d71 | 1686 | break; |
957956b3 | 1687 | case 3: /* SMC */ |
dcbff19b | 1688 | if (s->current_el == 0) { |
e0d6e6a5 EI |
1689 | unallocated_encoding(s); |
1690 | break; | |
1691 | } | |
1692 | gen_a64_set_pc_im(s->pc - 4); | |
1693 | tmp = tcg_const_i32(syn_aa64_smc(imm16)); | |
1694 | gen_helper_pre_smc(cpu_env, tmp); | |
1695 | tcg_temp_free_i32(tmp); | |
1696 | gen_ss_advance(s); | |
73710361 | 1697 | gen_exception_insn(s, 0, EXCP_SMC, syn_aa64_smc(imm16), 3); |
e0d6e6a5 | 1698 | break; |
35979d71 EI |
1699 | default: |
1700 | unallocated_encoding(s); | |
1701 | break; | |
1702 | } | |
9618e809 AG |
1703 | break; |
1704 | case 1: | |
1705 | if (op2_ll != 0) { | |
1706 | unallocated_encoding(s); | |
1707 | break; | |
1708 | } | |
1709 | /* BRK */ | |
73710361 GB |
1710 | gen_exception_insn(s, 4, EXCP_BKPT, syn_aa64_bkpt(imm16), |
1711 | default_exception_el(s)); | |
9618e809 AG |
1712 | break; |
1713 | case 2: | |
1714 | if (op2_ll != 0) { | |
1715 | unallocated_encoding(s); | |
1716 | break; | |
1717 | } | |
8012c84f PM |
1718 | /* HLT. This has two purposes. |
1719 | * Architecturally, it is an external halting debug instruction. | |
1720 | * Since QEMU doesn't implement external debug, we treat this as | |
1721 | * it is required for halting debug disabled: it will UNDEF. | |
1722 | * Secondly, "HLT 0xf000" is the A64 semihosting syscall instruction. | |
1723 | */ | |
1724 | if (semihosting_enabled() && imm16 == 0xf000) { | |
1725 | #ifndef CONFIG_USER_ONLY | |
1726 | /* In system mode, don't allow userspace access to semihosting, | |
1727 | * to provide some semblance of security (and for consistency | |
1728 | * with our 32-bit semihosting). | |
1729 | */ | |
1730 | if (s->current_el == 0) { | |
1731 | unsupported_encoding(s, insn); | |
1732 | break; | |
1733 | } | |
1734 | #endif | |
1735 | gen_exception_internal_insn(s, 0, EXCP_SEMIHOST); | |
1736 | } else { | |
1737 | unsupported_encoding(s, insn); | |
1738 | } | |
9618e809 AG |
1739 | break; |
1740 | case 5: | |
1741 | if (op2_ll < 1 || op2_ll > 3) { | |
1742 | unallocated_encoding(s); | |
1743 | break; | |
1744 | } | |
1745 | /* DCPS1, DCPS2, DCPS3 */ | |
1746 | unsupported_encoding(s, insn); | |
1747 | break; | |
1748 | default: | |
1749 | unallocated_encoding(s); | |
1750 | break; | |
1751 | } | |
ad7ee8a2 CF |
1752 | } |
1753 | ||
b001c8c3 AG |
1754 | /* C3.2.7 Unconditional branch (register) |
1755 | * 31 25 24 21 20 16 15 10 9 5 4 0 | |
1756 | * +---------------+-------+-------+-------+------+-------+ | |
1757 | * | 1 1 0 1 0 1 1 | opc | op2 | op3 | Rn | op4 | | |
1758 | * +---------------+-------+-------+-------+------+-------+ | |
1759 | */ | |
ad7ee8a2 CF |
1760 | static void disas_uncond_b_reg(DisasContext *s, uint32_t insn) |
1761 | { | |
b001c8c3 AG |
1762 | unsigned int opc, op2, op3, rn, op4; |
1763 | ||
1764 | opc = extract32(insn, 21, 4); | |
1765 | op2 = extract32(insn, 16, 5); | |
1766 | op3 = extract32(insn, 10, 6); | |
1767 | rn = extract32(insn, 5, 5); | |
1768 | op4 = extract32(insn, 0, 5); | |
1769 | ||
1770 | if (op4 != 0x0 || op3 != 0x0 || op2 != 0x1f) { | |
1771 | unallocated_encoding(s); | |
1772 | return; | |
1773 | } | |
1774 | ||
1775 | switch (opc) { | |
1776 | case 0: /* BR */ | |
b001c8c3 | 1777 | case 1: /* BLR */ |
6feecb8b TH |
1778 | case 2: /* RET */ |
1779 | gen_a64_set_pc(s, cpu_reg(s, rn)); | |
1780 | /* BLR also needs to load return address */ | |
1781 | if (opc == 1) { | |
1782 | tcg_gen_movi_i64(cpu_reg(s, 30), s->pc); | |
1783 | } | |
b001c8c3 AG |
1784 | break; |
1785 | case 4: /* ERET */ | |
dcbff19b | 1786 | if (s->current_el == 0) { |
14c521d4 EI |
1787 | unallocated_encoding(s); |
1788 | return; | |
1789 | } | |
52e60cdd RH |
1790 | gen_helper_exception_return(cpu_env); |
1791 | s->is_jmp = DISAS_JUMP; | |
1792 | return; | |
b001c8c3 AG |
1793 | case 5: /* DRPS */ |
1794 | if (rn != 0x1f) { | |
1795 | unallocated_encoding(s); | |
1796 | } else { | |
1797 | unsupported_encoding(s, insn); | |
1798 | } | |
1799 | return; | |
1800 | default: | |
1801 | unallocated_encoding(s); | |
1802 | return; | |
1803 | } | |
1804 | ||
b001c8c3 | 1805 | s->is_jmp = DISAS_JUMP; |
ad7ee8a2 CF |
1806 | } |
1807 | ||
1808 | /* C3.2 Branches, exception generating and system instructions */ | |
1809 | static void disas_b_exc_sys(DisasContext *s, uint32_t insn) | |
1810 | { | |
1811 | switch (extract32(insn, 25, 7)) { | |
1812 | case 0x0a: case 0x0b: | |
1813 | case 0x4a: case 0x4b: /* Unconditional branch (immediate) */ | |
1814 | disas_uncond_b_imm(s, insn); | |
1815 | break; | |
1816 | case 0x1a: case 0x5a: /* Compare & branch (immediate) */ | |
1817 | disas_comp_b_imm(s, insn); | |
1818 | break; | |
1819 | case 0x1b: case 0x5b: /* Test & branch (immediate) */ | |
1820 | disas_test_b_imm(s, insn); | |
1821 | break; | |
1822 | case 0x2a: /* Conditional branch (immediate) */ | |
1823 | disas_cond_b_imm(s, insn); | |
1824 | break; | |
1825 | case 0x6a: /* Exception generation / System */ | |
1826 | if (insn & (1 << 24)) { | |
1827 | disas_system(s, insn); | |
1828 | } else { | |
1829 | disas_exc(s, insn); | |
1830 | } | |
1831 | break; | |
1832 | case 0x6b: /* Unconditional branch (register) */ | |
1833 | disas_uncond_b_reg(s, insn); | |
1834 | break; | |
1835 | default: | |
1836 | unallocated_encoding(s); | |
1837 | break; | |
1838 | } | |
1839 | } | |
1840 | ||
5460da50 AB |
1841 | /* |
1842 | * Load/Store exclusive instructions are implemented by remembering | |
1843 | * the value/address loaded, and seeing if these are the same | |
1844 | * when the store is performed. This is not actually the architecturally | |
1845 | * mandated semantics, but it works for typical guest code sequences | |
1846 | * and avoids having to monitor regular stores. | |
1847 | * | |
1848 | * The store exclusive uses the atomic cmpxchg primitives to avoid | |
1849 | * races in multi-threaded linux-user and when MTTCG softmmu is | |
1850 | * enabled. | |
1851 | */ | |
fa2ef212 MM |
1852 | static void gen_load_exclusive(DisasContext *s, int rt, int rt2, |
1853 | TCGv_i64 addr, int size, bool is_pair) | |
1854 | { | |
1855 | TCGv_i64 tmp = tcg_temp_new_i64(); | |
5460da50 | 1856 | TCGMemOp memop = s->be_data + size; |
fa2ef212 MM |
1857 | |
1858 | g_assert(size <= 3); | |
5460da50 AB |
1859 | tcg_gen_qemu_ld_i64(tmp, addr, get_mem_index(s), memop); |
1860 | ||
fa2ef212 | 1861 | if (is_pair) { |
5460da50 | 1862 | TCGv_i64 addr2 = tcg_temp_new_i64(); |
fa2ef212 MM |
1863 | TCGv_i64 hitmp = tcg_temp_new_i64(); |
1864 | ||
5460da50 AB |
1865 | g_assert(size >= 2); |
1866 | tcg_gen_addi_i64(addr2, addr, 1 << size); | |
1867 | tcg_gen_qemu_ld_i64(hitmp, addr2, get_mem_index(s), memop); | |
1868 | tcg_temp_free_i64(addr2); | |
fa2ef212 MM |
1869 | tcg_gen_mov_i64(cpu_exclusive_high, hitmp); |
1870 | tcg_gen_mov_i64(cpu_reg(s, rt2), hitmp); | |
1871 | tcg_temp_free_i64(hitmp); | |
1872 | } | |
1873 | ||
1874 | tcg_gen_mov_i64(cpu_exclusive_val, tmp); | |
1875 | tcg_gen_mov_i64(cpu_reg(s, rt), tmp); | |
1876 | ||
1877 | tcg_temp_free_i64(tmp); | |
1878 | tcg_gen_mov_i64(cpu_exclusive_addr, addr); | |
1879 | } | |
1880 | ||
fa2ef212 | 1881 | static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2, |
d324b36a | 1882 | TCGv_i64 inaddr, int size, int is_pair) |
fa2ef212 | 1883 | { |
d324b36a PM |
1884 | /* if (env->exclusive_addr == addr && env->exclusive_val == [addr] |
1885 | * && (!is_pair || env->exclusive_high == [addr + datasize])) { | |
1886 | * [addr] = {Rt}; | |
1887 | * if (is_pair) { | |
1888 | * [addr + datasize] = {Rt2}; | |
1889 | * } | |
1890 | * {Rd} = 0; | |
1891 | * } else { | |
1892 | * {Rd} = 1; | |
1893 | * } | |
1894 | * env->exclusive_addr = -1; | |
1895 | */ | |
42a268c2 RH |
1896 | TCGLabel *fail_label = gen_new_label(); |
1897 | TCGLabel *done_label = gen_new_label(); | |
d324b36a PM |
1898 | TCGv_i64 addr = tcg_temp_local_new_i64(); |
1899 | TCGv_i64 tmp; | |
1900 | ||
1901 | /* Copy input into a local temp so it is not trashed when the | |
1902 | * basic block ends at the branch insn. | |
1903 | */ | |
1904 | tcg_gen_mov_i64(addr, inaddr); | |
1905 | tcg_gen_brcond_i64(TCG_COND_NE, addr, cpu_exclusive_addr, fail_label); | |
1906 | ||
1907 | tmp = tcg_temp_new_i64(); | |
d324b36a | 1908 | if (is_pair) { |
1dd089d0 EC |
1909 | if (size == 2) { |
1910 | TCGv_i64 val = tcg_temp_new_i64(); | |
1911 | tcg_gen_concat32_i64(tmp, cpu_reg(s, rt), cpu_reg(s, rt2)); | |
1912 | tcg_gen_concat32_i64(val, cpu_exclusive_val, cpu_exclusive_high); | |
1913 | tcg_gen_atomic_cmpxchg_i64(tmp, addr, val, tmp, | |
1914 | get_mem_index(s), | |
1915 | size | MO_ALIGN | s->be_data); | |
1916 | tcg_gen_setcond_i64(TCG_COND_NE, tmp, tmp, val); | |
1917 | tcg_temp_free_i64(val); | |
1918 | } else if (s->be_data == MO_LE) { | |
1919 | gen_helper_paired_cmpxchg64_le(tmp, cpu_env, addr, cpu_reg(s, rt), | |
1920 | cpu_reg(s, rt2)); | |
1921 | } else { | |
1922 | gen_helper_paired_cmpxchg64_be(tmp, cpu_env, addr, cpu_reg(s, rt), | |
1923 | cpu_reg(s, rt2)); | |
1924 | } | |
1925 | } else { | |
1926 | TCGv_i64 val = cpu_reg(s, rt); | |
1927 | tcg_gen_atomic_cmpxchg_i64(tmp, addr, cpu_exclusive_val, val, | |
1928 | get_mem_index(s), | |
1929 | size | MO_ALIGN | s->be_data); | |
1930 | tcg_gen_setcond_i64(TCG_COND_NE, tmp, tmp, cpu_exclusive_val); | |
d324b36a PM |
1931 | } |
1932 | ||
1933 | tcg_temp_free_i64(addr); | |
1934 | ||
1dd089d0 EC |
1935 | tcg_gen_mov_i64(cpu_reg(s, rd), tmp); |
1936 | tcg_temp_free_i64(tmp); | |
d324b36a | 1937 | tcg_gen_br(done_label); |
1dd089d0 | 1938 | |
d324b36a PM |
1939 | gen_set_label(fail_label); |
1940 | tcg_gen_movi_i64(cpu_reg(s, rd), 1); | |
1941 | gen_set_label(done_label); | |
1942 | tcg_gen_movi_i64(cpu_exclusive_addr, -1); | |
fa2ef212 | 1943 | } |
fa2ef212 | 1944 | |
aaa1f954 EI |
1945 | /* Update the Sixty-Four bit (SF) registersize. This logic is derived |
1946 | * from the ARMv8 specs for LDR (Shared decode for all encodings). | |
1947 | */ | |
1948 | static bool disas_ldst_compute_iss_sf(int size, bool is_signed, int opc) | |
1949 | { | |
1950 | int opc0 = extract32(opc, 0, 1); | |
1951 | int regsize; | |
1952 | ||
1953 | if (is_signed) { | |
1954 | regsize = opc0 ? 32 : 64; | |
1955 | } else { | |
1956 | regsize = size == 3 ? 64 : 32; | |
1957 | } | |
1958 | return regsize == 64; | |
1959 | } | |
1960 | ||
fa2ef212 MM |
1961 | /* C3.3.6 Load/store exclusive |
1962 | * | |
1963 | * 31 30 29 24 23 22 21 20 16 15 14 10 9 5 4 0 | |
1964 | * +-----+-------------+----+---+----+------+----+-------+------+------+ | |
1965 | * | sz | 0 0 1 0 0 0 | o2 | L | o1 | Rs | o0 | Rt2 | Rn | Rt | | |
1966 | * +-----+-------------+----+---+----+------+----+-------+------+------+ | |
1967 | * | |
1968 | * sz: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64 bit | |
1969 | * L: 0 -> store, 1 -> load | |
1970 | * o2: 0 -> exclusive, 1 -> not | |
1971 | * o1: 0 -> single register, 1 -> register pair | |
1972 | * o0: 1 -> load-acquire/store-release, 0 -> not | |
fa2ef212 | 1973 | */ |
ad7ee8a2 CF |
1974 | static void disas_ldst_excl(DisasContext *s, uint32_t insn) |
1975 | { | |
fa2ef212 MM |
1976 | int rt = extract32(insn, 0, 5); |
1977 | int rn = extract32(insn, 5, 5); | |
1978 | int rt2 = extract32(insn, 10, 5); | |
1979 | int is_lasr = extract32(insn, 15, 1); | |
1980 | int rs = extract32(insn, 16, 5); | |
1981 | int is_pair = extract32(insn, 21, 1); | |
1982 | int is_store = !extract32(insn, 22, 1); | |
1983 | int is_excl = !extract32(insn, 23, 1); | |
1984 | int size = extract32(insn, 30, 2); | |
1985 | TCGv_i64 tcg_addr; | |
1986 | ||
e14f0eb1 PM |
1987 | if ((!is_excl && !is_pair && !is_lasr) || |
1988 | (!is_excl && is_pair) || | |
fa2ef212 MM |
1989 | (is_pair && size < 2)) { |
1990 | unallocated_encoding(s); | |
1991 | return; | |
1992 | } | |
1993 | ||
1994 | if (rn == 31) { | |
1995 | gen_check_sp_alignment(s); | |
1996 | } | |
1997 | tcg_addr = read_cpu_reg_sp(s, rn, 1); | |
1998 | ||
1999 | /* Note that since TCG is single threaded load-acquire/store-release | |
2000 | * semantics require no extra if (is_lasr) { ... } handling. | |
2001 | */ | |
2002 | ||
2003 | if (is_excl) { | |
2004 | if (!is_store) { | |
7ea47fe7 | 2005 | s->is_ldex = true; |
fa2ef212 | 2006 | gen_load_exclusive(s, rt, rt2, tcg_addr, size, is_pair); |
ce1bd93f PK |
2007 | if (is_lasr) { |
2008 | tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); | |
2009 | } | |
fa2ef212 | 2010 | } else { |
ce1bd93f PK |
2011 | if (is_lasr) { |
2012 | tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); | |
2013 | } | |
fa2ef212 MM |
2014 | gen_store_exclusive(s, rs, rt, rt2, tcg_addr, size, is_pair); |
2015 | } | |
2016 | } else { | |
2017 | TCGv_i64 tcg_rt = cpu_reg(s, rt); | |
aaa1f954 EI |
2018 | bool iss_sf = disas_ldst_compute_iss_sf(size, false, 0); |
2019 | ||
2020 | /* Generate ISS for non-exclusive accesses including LASR. */ | |
fa2ef212 | 2021 | if (is_store) { |
ce1bd93f PK |
2022 | if (is_lasr) { |
2023 | tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); | |
2024 | } | |
aaa1f954 EI |
2025 | do_gpr_st(s, tcg_rt, tcg_addr, size, |
2026 | true, rt, iss_sf, is_lasr); | |
fa2ef212 | 2027 | } else { |
aaa1f954 EI |
2028 | do_gpr_ld(s, tcg_rt, tcg_addr, size, false, false, |
2029 | true, rt, iss_sf, is_lasr); | |
ce1bd93f PK |
2030 | if (is_lasr) { |
2031 | tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); | |
2032 | } | |
fa2ef212 | 2033 | } |
fa2ef212 | 2034 | } |
ad7ee8a2 CF |
2035 | } |
2036 | ||
32b64e86 AG |
2037 | /* |
2038 | * C3.3.5 Load register (literal) | |
2039 | * | |
2040 | * 31 30 29 27 26 25 24 23 5 4 0 | |
2041 | * +-----+-------+---+-----+-------------------+-------+ | |
2042 | * | opc | 0 1 1 | V | 0 0 | imm19 | Rt | | |
2043 | * +-----+-------+---+-----+-------------------+-------+ | |
2044 | * | |
2045 | * V: 1 -> vector (simd/fp) | |
2046 | * opc (non-vector): 00 -> 32 bit, 01 -> 64 bit, | |
2047 | * 10-> 32 bit signed, 11 -> prefetch | |
2048 | * opc (vector): 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit (11 unallocated) | |
2049 | */ | |
ad7ee8a2 CF |
2050 | static void disas_ld_lit(DisasContext *s, uint32_t insn) |
2051 | { | |
32b64e86 AG |
2052 | int rt = extract32(insn, 0, 5); |
2053 | int64_t imm = sextract32(insn, 5, 19) << 2; | |
2054 | bool is_vector = extract32(insn, 26, 1); | |
2055 | int opc = extract32(insn, 30, 2); | |
2056 | bool is_signed = false; | |
2057 | int size = 2; | |
2058 | TCGv_i64 tcg_rt, tcg_addr; | |
2059 | ||
2060 | if (is_vector) { | |
2061 | if (opc == 3) { | |
2062 | unallocated_encoding(s); | |
2063 | return; | |
2064 | } | |
2065 | size = 2 + opc; | |
8c6afa6a PM |
2066 | if (!fp_access_check(s)) { |
2067 | return; | |
2068 | } | |
32b64e86 AG |
2069 | } else { |
2070 | if (opc == 3) { | |
2071 | /* PRFM (literal) : prefetch */ | |
2072 | return; | |
2073 | } | |
2074 | size = 2 + extract32(opc, 0, 1); | |
2075 | is_signed = extract32(opc, 1, 1); | |
2076 | } | |
2077 | ||
2078 | tcg_rt = cpu_reg(s, rt); | |
2079 | ||
2080 | tcg_addr = tcg_const_i64((s->pc - 4) + imm); | |
2081 | if (is_vector) { | |
2082 | do_fp_ld(s, rt, tcg_addr, size); | |
2083 | } else { | |
aaa1f954 | 2084 | /* Only unsigned 32bit loads target 32bit registers. */ |
173ff585 | 2085 | bool iss_sf = opc != 0; |
aaa1f954 EI |
2086 | |
2087 | do_gpr_ld(s, tcg_rt, tcg_addr, size, is_signed, false, | |
2088 | true, rt, iss_sf, false); | |
32b64e86 AG |
2089 | } |
2090 | tcg_temp_free_i64(tcg_addr); | |
ad7ee8a2 CF |
2091 | } |
2092 | ||
4a08d475 PM |
2093 | /* |
2094 | * C5.6.80 LDNP (Load Pair - non-temporal hint) | |
2095 | * C5.6.81 LDP (Load Pair - non vector) | |
2096 | * C5.6.82 LDPSW (Load Pair Signed Word - non vector) | |
2097 | * C5.6.176 STNP (Store Pair - non-temporal hint) | |
2098 | * C5.6.177 STP (Store Pair - non vector) | |
2099 | * C6.3.165 LDNP (Load Pair of SIMD&FP - non-temporal hint) | |
2100 | * C6.3.165 LDP (Load Pair of SIMD&FP) | |
2101 | * C6.3.284 STNP (Store Pair of SIMD&FP - non-temporal hint) | |
2102 | * C6.3.284 STP (Store Pair of SIMD&FP) | |
2103 | * | |
2104 | * 31 30 29 27 26 25 24 23 22 21 15 14 10 9 5 4 0 | |
2105 | * +-----+-------+---+---+-------+---+-----------------------------+ | |
2106 | * | opc | 1 0 1 | V | 0 | index | L | imm7 | Rt2 | Rn | Rt | | |
2107 | * +-----+-------+---+---+-------+---+-------+-------+------+------+ | |
2108 | * | |
2109 | * opc: LDP/STP/LDNP/STNP 00 -> 32 bit, 10 -> 64 bit | |
2110 | * LDPSW 01 | |
2111 | * LDP/STP/LDNP/STNP (SIMD) 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit | |
2112 | * V: 0 -> GPR, 1 -> Vector | |
2113 | * idx: 00 -> signed offset with non-temporal hint, 01 -> post-index, | |
2114 | * 10 -> signed offset, 11 -> pre-index | |
2115 | * L: 0 -> Store 1 -> Load | |
2116 | * | |
2117 | * Rt, Rt2 = GPR or SIMD registers to be stored | |
2118 | * Rn = general purpose register containing address | |
2119 | * imm7 = signed offset (multiple of 4 or 8 depending on size) | |
2120 | */ | |
ad7ee8a2 CF |
2121 | static void disas_ldst_pair(DisasContext *s, uint32_t insn) |
2122 | { | |
4a08d475 PM |
2123 | int rt = extract32(insn, 0, 5); |
2124 | int rn = extract32(insn, 5, 5); | |
2125 | int rt2 = extract32(insn, 10, 5); | |
c2ebd862 | 2126 | uint64_t offset = sextract64(insn, 15, 7); |
4a08d475 PM |
2127 | int index = extract32(insn, 23, 2); |
2128 | bool is_vector = extract32(insn, 26, 1); | |
2129 | bool is_load = extract32(insn, 22, 1); | |
2130 | int opc = extract32(insn, 30, 2); | |
2131 | ||
2132 | bool is_signed = false; | |
2133 | bool postindex = false; | |
2134 | bool wback = false; | |
2135 | ||
2136 | TCGv_i64 tcg_addr; /* calculated address */ | |
2137 | int size; | |
2138 | ||
2139 | if (opc == 3) { | |
2140 | unallocated_encoding(s); | |
2141 | return; | |
2142 | } | |
2143 | ||
2144 | if (is_vector) { | |
2145 | size = 2 + opc; | |
2146 | } else { | |
2147 | size = 2 + extract32(opc, 1, 1); | |
2148 | is_signed = extract32(opc, 0, 1); | |
2149 | if (!is_load && is_signed) { | |
2150 | unallocated_encoding(s); | |
2151 | return; | |
2152 | } | |
2153 | } | |
2154 | ||
2155 | switch (index) { | |
2156 | case 1: /* post-index */ | |
2157 | postindex = true; | |
2158 | wback = true; | |
2159 | break; | |
2160 | case 0: | |
2161 | /* signed offset with "non-temporal" hint. Since we don't emulate | |
2162 | * caches we don't care about hints to the cache system about | |
2163 | * data access patterns, and handle this identically to plain | |
2164 | * signed offset. | |
2165 | */ | |
2166 | if (is_signed) { | |
2167 | /* There is no non-temporal-hint version of LDPSW */ | |
2168 | unallocated_encoding(s); | |
2169 | return; | |
2170 | } | |
2171 | postindex = false; | |
2172 | break; | |
2173 | case 2: /* signed offset, rn not updated */ | |
2174 | postindex = false; | |
2175 | break; | |
2176 | case 3: /* pre-index */ | |
2177 | postindex = false; | |
2178 | wback = true; | |
2179 | break; | |
2180 | } | |
2181 | ||
8c6afa6a PM |
2182 | if (is_vector && !fp_access_check(s)) { |
2183 | return; | |
2184 | } | |
2185 | ||
4a08d475 PM |
2186 | offset <<= size; |
2187 | ||
2188 | if (rn == 31) { | |
2189 | gen_check_sp_alignment(s); | |
2190 | } | |
2191 | ||
2192 | tcg_addr = read_cpu_reg_sp(s, rn, 1); | |
2193 | ||
2194 | if (!postindex) { | |
2195 | tcg_gen_addi_i64(tcg_addr, tcg_addr, offset); | |
2196 | } | |
2197 | ||
2198 | if (is_vector) { | |
2199 | if (is_load) { | |
2200 | do_fp_ld(s, rt, tcg_addr, size); | |
2201 | } else { | |
2202 | do_fp_st(s, rt, tcg_addr, size); | |
2203 | } | |
2204 | } else { | |
2205 | TCGv_i64 tcg_rt = cpu_reg(s, rt); | |
2206 | if (is_load) { | |
aaa1f954 EI |
2207 | do_gpr_ld(s, tcg_rt, tcg_addr, size, is_signed, false, |
2208 | false, 0, false, false); | |
4a08d475 | 2209 | } else { |
aaa1f954 EI |
2210 | do_gpr_st(s, tcg_rt, tcg_addr, size, |
2211 | false, 0, false, false); | |
4a08d475 PM |
2212 | } |
2213 | } | |
2214 | tcg_gen_addi_i64(tcg_addr, tcg_addr, 1 << size); | |
2215 | if (is_vector) { | |
2216 | if (is_load) { | |
2217 | do_fp_ld(s, rt2, tcg_addr, size); | |
2218 | } else { | |
2219 | do_fp_st(s, rt2, tcg_addr, size); | |
2220 | } | |
2221 | } else { | |
2222 | TCGv_i64 tcg_rt2 = cpu_reg(s, rt2); | |
2223 | if (is_load) { | |
aaa1f954 EI |
2224 | do_gpr_ld(s, tcg_rt2, tcg_addr, size, is_signed, false, |
2225 | false, 0, false, false); | |
4a08d475 | 2226 | } else { |
aaa1f954 EI |
2227 | do_gpr_st(s, tcg_rt2, tcg_addr, size, |
2228 | false, 0, false, false); | |
4a08d475 PM |
2229 | } |
2230 | } | |
2231 | ||
2232 | if (wback) { | |
2233 | if (postindex) { | |
2234 | tcg_gen_addi_i64(tcg_addr, tcg_addr, offset - (1 << size)); | |
2235 | } else { | |
2236 | tcg_gen_subi_i64(tcg_addr, tcg_addr, 1 << size); | |
2237 | } | |
2238 | tcg_gen_mov_i64(cpu_reg_sp(s, rn), tcg_addr); | |
2239 | } | |
ad7ee8a2 CF |
2240 | } |
2241 | ||
a5e94a9d AB |
2242 | /* |
2243 | * C3.3.8 Load/store (immediate post-indexed) | |
2244 | * C3.3.9 Load/store (immediate pre-indexed) | |
2245 | * C3.3.12 Load/store (unscaled immediate) | |
2246 | * | |
2247 | * 31 30 29 27 26 25 24 23 22 21 20 12 11 10 9 5 4 0 | |
2248 | * +----+-------+---+-----+-----+---+--------+-----+------+------+ | |
2249 | * |size| 1 1 1 | V | 0 0 | opc | 0 | imm9 | idx | Rn | Rt | | |
2250 | * +----+-------+---+-----+-----+---+--------+-----+------+------+ | |
2251 | * | |
2252 | * idx = 01 -> post-indexed, 11 pre-indexed, 00 unscaled imm. (no writeback) | |
60510aed | 2253 | 10 -> unprivileged |
a5e94a9d AB |
2254 | * V = 0 -> non-vector |
2255 | * size: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64bit | |
2256 | * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32 | |
2257 | */ | |
cd694521 EI |
2258 | static void disas_ldst_reg_imm9(DisasContext *s, uint32_t insn, |
2259 | int opc, | |
2260 | int size, | |
2261 | int rt, | |
2262 | bool is_vector) | |
a5e94a9d | 2263 | { |
a5e94a9d AB |
2264 | int rn = extract32(insn, 5, 5); |
2265 | int imm9 = sextract32(insn, 12, 9); | |
a5e94a9d AB |
2266 | int idx = extract32(insn, 10, 2); |
2267 | bool is_signed = false; | |
2268 | bool is_store = false; | |
2269 | bool is_extended = false; | |
60510aed | 2270 | bool is_unpriv = (idx == 2); |
aaa1f954 | 2271 | bool iss_valid = !is_vector; |
a5e94a9d AB |
2272 | bool post_index; |
2273 | bool writeback; | |
2274 | ||
2275 | TCGv_i64 tcg_addr; | |
2276 | ||
2277 | if (is_vector) { | |
2278 | size |= (opc & 2) << 1; | |
60510aed | 2279 | if (size > 4 || is_unpriv) { |
a5e94a9d AB |
2280 | unallocated_encoding(s); |
2281 | return; | |
2282 | } | |
2283 | is_store = ((opc & 1) == 0); | |
8c6afa6a PM |
2284 | if (!fp_access_check(s)) { |
2285 | return; | |
2286 | } | |
a5e94a9d AB |
2287 | } else { |
2288 | if (size == 3 && opc == 2) { | |
2289 | /* PRFM - prefetch */ | |
60510aed PM |
2290 | if (is_unpriv) { |
2291 | unallocated_encoding(s); | |
2292 | return; | |
2293 | } | |
a5e94a9d AB |
2294 | return; |
2295 | } | |
2296 | if (opc == 3 && size > 1) { | |
2297 | unallocated_encoding(s); | |
2298 | return; | |
2299 | } | |
2300 | is_store = (opc == 0); | |
026a19c3 EI |
2301 | is_signed = extract32(opc, 1, 1); |
2302 | is_extended = (size < 3) && extract32(opc, 0, 1); | |
a5e94a9d AB |
2303 | } |
2304 | ||
2305 | switch (idx) { | |
2306 | case 0: | |
60510aed | 2307 | case 2: |
a5e94a9d AB |
2308 | post_index = false; |
2309 | writeback = false; | |
2310 | break; | |
2311 | case 1: | |
2312 | post_index = true; | |
2313 | writeback = true; | |
2314 | break; | |
2315 | case 3: | |
2316 | post_index = false; | |
2317 | writeback = true; | |
2318 | break; | |
a5e94a9d AB |
2319 | } |
2320 | ||
2321 | if (rn == 31) { | |
2322 | gen_check_sp_alignment(s); | |
2323 | } | |
2324 | tcg_addr = read_cpu_reg_sp(s, rn, 1); | |
2325 | ||
2326 | if (!post_index) { | |
2327 | tcg_gen_addi_i64(tcg_addr, tcg_addr, imm9); | |
2328 | } | |
2329 | ||
2330 | if (is_vector) { | |
2331 | if (is_store) { | |
2332 | do_fp_st(s, rt, tcg_addr, size); | |
2333 | } else { | |
2334 | do_fp_ld(s, rt, tcg_addr, size); | |
2335 | } | |
2336 | } else { | |
2337 | TCGv_i64 tcg_rt = cpu_reg(s, rt); | |
579d21cc | 2338 | int memidx = is_unpriv ? get_a64_user_mem_index(s) : get_mem_index(s); |
aaa1f954 | 2339 | bool iss_sf = disas_ldst_compute_iss_sf(size, is_signed, opc); |
60510aed | 2340 | |
a5e94a9d | 2341 | if (is_store) { |
aaa1f954 EI |
2342 | do_gpr_st_memidx(s, tcg_rt, tcg_addr, size, memidx, |
2343 | iss_valid, rt, iss_sf, false); | |
a5e94a9d | 2344 | } else { |
60510aed | 2345 | do_gpr_ld_memidx(s, tcg_rt, tcg_addr, size, |
aaa1f954 EI |
2346 | is_signed, is_extended, memidx, |
2347 | iss_valid, rt, iss_sf, false); | |
a5e94a9d AB |
2348 | } |
2349 | } | |
2350 | ||
2351 | if (writeback) { | |
2352 | TCGv_i64 tcg_rn = cpu_reg_sp(s, rn); | |
2353 | if (post_index) { | |
2354 | tcg_gen_addi_i64(tcg_addr, tcg_addr, imm9); | |
2355 | } | |
2356 | tcg_gen_mov_i64(tcg_rn, tcg_addr); | |
2357 | } | |
2358 | } | |
2359 | ||
229b7a05 AB |
2360 | /* |
2361 | * C3.3.10 Load/store (register offset) | |
2362 | * | |
2363 | * 31 30 29 27 26 25 24 23 22 21 20 16 15 13 12 11 10 9 5 4 0 | |
2364 | * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+ | |
2365 | * |size| 1 1 1 | V | 0 0 | opc | 1 | Rm | opt | S| 1 0 | Rn | Rt | | |
2366 | * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+ | |
2367 | * | |
2368 | * For non-vector: | |
2369 | * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit | |
2370 | * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32 | |
2371 | * For vector: | |
2372 | * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated | |
2373 | * opc<0>: 0 -> store, 1 -> load | |
2374 | * V: 1 -> vector/simd | |
2375 | * opt: extend encoding (see DecodeRegExtend) | |
2376 | * S: if S=1 then scale (essentially index by sizeof(size)) | |
2377 | * Rt: register to transfer into/out of | |
2378 | * Rn: address register or SP for base | |
2379 | * Rm: offset register or ZR for offset | |
2380 | */ | |
cd694521 EI |
2381 | static void disas_ldst_reg_roffset(DisasContext *s, uint32_t insn, |
2382 | int opc, | |
2383 | int size, | |
2384 | int rt, | |
2385 | bool is_vector) | |
229b7a05 | 2386 | { |
229b7a05 AB |
2387 | int rn = extract32(insn, 5, 5); |
2388 | int shift = extract32(insn, 12, 1); | |
2389 | int rm = extract32(insn, 16, 5); | |
229b7a05 | 2390 | int opt = extract32(insn, 13, 3); |
229b7a05 AB |
2391 | bool is_signed = false; |
2392 | bool is_store = false; | |
2393 | bool is_extended = false; | |
229b7a05 AB |
2394 | |
2395 | TCGv_i64 tcg_rm; | |
2396 | TCGv_i64 tcg_addr; | |
2397 | ||
2398 | if (extract32(opt, 1, 1) == 0) { | |
2399 | unallocated_encoding(s); | |
2400 | return; | |
2401 | } | |
2402 | ||
2403 | if (is_vector) { | |
2404 | size |= (opc & 2) << 1; | |
2405 | if (size > 4) { | |
2406 | unallocated_encoding(s); | |
2407 | return; | |
2408 | } | |
2409 | is_store = !extract32(opc, 0, 1); | |
8c6afa6a PM |
2410 | if (!fp_access_check(s)) { |
2411 | return; | |
2412 | } | |
229b7a05 AB |
2413 | } else { |
2414 | if (size == 3 && opc == 2) { | |
2415 | /* PRFM - prefetch */ | |
2416 | return; | |
2417 | } | |
2418 | if (opc == 3 && size > 1) { | |
2419 | unallocated_encoding(s); | |
2420 | return; | |
2421 | } | |
2422 | is_store = (opc == 0); | |
2423 | is_signed = extract32(opc, 1, 1); | |
2424 | is_extended = (size < 3) && extract32(opc, 0, 1); | |
2425 | } | |
2426 | ||
2427 | if (rn == 31) { | |
2428 | gen_check_sp_alignment(s); | |
2429 | } | |
2430 | tcg_addr = read_cpu_reg_sp(s, rn, 1); | |
2431 | ||
2432 | tcg_rm = read_cpu_reg(s, rm, 1); | |
2433 | ext_and_shift_reg(tcg_rm, tcg_rm, opt, shift ? size : 0); | |
2434 | ||
2435 | tcg_gen_add_i64(tcg_addr, tcg_addr, tcg_rm); | |
2436 | ||
2437 | if (is_vector) { | |
2438 | if (is_store) { | |
2439 | do_fp_st(s, rt, tcg_addr, size); | |
2440 | } else { | |
2441 | do_fp_ld(s, rt, tcg_addr, size); | |
2442 | } | |
2443 | } else { | |
2444 | TCGv_i64 tcg_rt = cpu_reg(s, rt); | |
aaa1f954 | 2445 | bool iss_sf = disas_ldst_compute_iss_sf(size, is_signed, opc); |
229b7a05 | 2446 | if (is_store) { |
aaa1f954 EI |
2447 | do_gpr_st(s, tcg_rt, tcg_addr, size, |
2448 | true, rt, iss_sf, false); | |
229b7a05 | 2449 | } else { |
aaa1f954 EI |
2450 | do_gpr_ld(s, tcg_rt, tcg_addr, size, |
2451 | is_signed, is_extended, | |
2452 | true, rt, iss_sf, false); | |
229b7a05 AB |
2453 | } |
2454 | } | |
2455 | } | |
2456 | ||
d5612f10 AB |
2457 | /* |
2458 | * C3.3.13 Load/store (unsigned immediate) | |
2459 | * | |
2460 | * 31 30 29 27 26 25 24 23 22 21 10 9 5 | |
2461 | * +----+-------+---+-----+-----+------------+-------+------+ | |
2462 | * |size| 1 1 1 | V | 0 1 | opc | imm12 | Rn | Rt | | |
2463 | * +----+-------+---+-----+-----+------------+-------+------+ | |
2464 | * | |
2465 | * For non-vector: | |
2466 | * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit | |
2467 | * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32 | |
2468 | * For vector: | |
2469 | * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated | |
2470 | * opc<0>: 0 -> store, 1 -> load | |
2471 | * Rn: base address register (inc SP) | |
2472 | * Rt: target register | |
2473 | */ | |
cd694521 EI |
2474 | static void disas_ldst_reg_unsigned_imm(DisasContext *s, uint32_t insn, |
2475 | int opc, | |
2476 | int size, | |
2477 | int rt, | |
2478 | bool is_vector) | |
d5612f10 | 2479 | { |
d5612f10 AB |
2480 | int rn = extract32(insn, 5, 5); |
2481 | unsigned int imm12 = extract32(insn, 10, 12); | |
d5612f10 AB |
2482 | unsigned int offset; |
2483 | ||
2484 | TCGv_i64 tcg_addr; | |
2485 | ||
2486 | bool is_store; | |
2487 | bool is_signed = false; | |
2488 | bool is_extended = false; | |
2489 | ||
2490 | if (is_vector) { | |
2491 | size |= (opc & 2) << 1; | |
2492 | if (size > 4) { | |
2493 | unallocated_encoding(s); | |
2494 | return; | |
2495 | } | |
2496 | is_store = !extract32(opc, 0, 1); | |
8c6afa6a PM |
2497 | if (!fp_access_check(s)) { |
2498 | return; | |
2499 | } | |
d5612f10 AB |
2500 | } else { |
2501 | if (size == 3 && opc == 2) { | |
2502 | /* PRFM - prefetch */ | |
2503 | return; | |
2504 | } | |
2505 | if (opc == 3 && size > 1) { | |
2506 | unallocated_encoding(s); | |
2507 | return; | |
2508 | } | |
2509 | is_store = (opc == 0); | |
2510 | is_signed = extract32(opc, 1, 1); | |
2511 | is_extended = (size < 3) && extract32(opc, 0, 1); | |
2512 | } | |
2513 | ||
2514 | if (rn == 31) { | |
2515 | gen_check_sp_alignment(s); | |
2516 | } | |
2517 | tcg_addr = read_cpu_reg_sp(s, rn, 1); | |
2518 | offset = imm12 << size; | |
2519 | tcg_gen_addi_i64(tcg_addr, tcg_addr, offset); | |
2520 | ||
2521 | if (is_vector) { | |
2522 | if (is_store) { | |
2523 | do_fp_st(s, rt, tcg_addr, size); | |
2524 | } else { | |
2525 | do_fp_ld(s, rt, tcg_addr, size); | |
2526 | } | |
2527 | } else { | |
2528 | TCGv_i64 tcg_rt = cpu_reg(s, rt); | |
aaa1f954 | 2529 | bool iss_sf = disas_ldst_compute_iss_sf(size, is_signed, opc); |
d5612f10 | 2530 | if (is_store) { |
aaa1f954 EI |
2531 | do_gpr_st(s, tcg_rt, tcg_addr, size, |
2532 | true, rt, iss_sf, false); | |
d5612f10 | 2533 | } else { |
aaa1f954 EI |
2534 | do_gpr_ld(s, tcg_rt, tcg_addr, size, is_signed, is_extended, |
2535 | true, rt, iss_sf, false); | |
d5612f10 AB |
2536 | } |
2537 | } | |
2538 | } | |
2539 | ||
ad7ee8a2 CF |
2540 | /* Load/store register (all forms) */ |
2541 | static void disas_ldst_reg(DisasContext *s, uint32_t insn) | |
2542 | { | |
cd694521 EI |
2543 | int rt = extract32(insn, 0, 5); |
2544 | int opc = extract32(insn, 22, 2); | |
2545 | bool is_vector = extract32(insn, 26, 1); | |
2546 | int size = extract32(insn, 30, 2); | |
2547 | ||
d5612f10 AB |
2548 | switch (extract32(insn, 24, 2)) { |
2549 | case 0: | |
229b7a05 | 2550 | if (extract32(insn, 21, 1) == 1 && extract32(insn, 10, 2) == 2) { |
cd694521 | 2551 | disas_ldst_reg_roffset(s, insn, opc, size, rt, is_vector); |
229b7a05 | 2552 | } else { |
60510aed PM |
2553 | /* Load/store register (unscaled immediate) |
2554 | * Load/store immediate pre/post-indexed | |
2555 | * Load/store register unprivileged | |
2556 | */ | |
cd694521 | 2557 | disas_ldst_reg_imm9(s, insn, opc, size, rt, is_vector); |
229b7a05 | 2558 | } |
d5612f10 AB |
2559 | break; |
2560 | case 1: | |
cd694521 | 2561 | disas_ldst_reg_unsigned_imm(s, insn, opc, size, rt, is_vector); |
d5612f10 AB |
2562 | break; |
2563 | default: | |
2564 | unallocated_encoding(s); | |
2565 | break; | |
2566 | } | |
ad7ee8a2 CF |
2567 | } |
2568 | ||
72430bf5 AB |
2569 | /* C3.3.1 AdvSIMD load/store multiple structures |
2570 | * | |
2571 | * 31 30 29 23 22 21 16 15 12 11 10 9 5 4 0 | |
2572 | * +---+---+---------------+---+-------------+--------+------+------+------+ | |
2573 | * | 0 | Q | 0 0 1 1 0 0 0 | L | 0 0 0 0 0 0 | opcode | size | Rn | Rt | | |
2574 | * +---+---+---------------+---+-------------+--------+------+------+------+ | |
2575 | * | |
2576 | * C3.3.2 AdvSIMD load/store multiple structures (post-indexed) | |
2577 | * | |
2578 | * 31 30 29 23 22 21 20 16 15 12 11 10 9 5 4 0 | |
2579 | * +---+---+---------------+---+---+---------+--------+------+------+------+ | |
2580 | * | 0 | Q | 0 0 1 1 0 0 1 | L | 0 | Rm | opcode | size | Rn | Rt | | |
2581 | * +---+---+---------------+---+---+---------+--------+------+------+------+ | |
2582 | * | |
2583 | * Rt: first (or only) SIMD&FP register to be transferred | |
2584 | * Rn: base address or SP | |
2585 | * Rm (post-index only): post-index register (when !31) or size dependent #imm | |
2586 | */ | |
ad7ee8a2 CF |
2587 | static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn) |
2588 | { | |
72430bf5 AB |
2589 | int rt = extract32(insn, 0, 5); |
2590 | int rn = extract32(insn, 5, 5); | |
2591 | int size = extract32(insn, 10, 2); | |
2592 | int opcode = extract32(insn, 12, 4); | |
2593 | bool is_store = !extract32(insn, 22, 1); | |
2594 | bool is_postidx = extract32(insn, 23, 1); | |
2595 | bool is_q = extract32(insn, 30, 1); | |
2596 | TCGv_i64 tcg_addr, tcg_rn; | |
2597 | ||
2598 | int ebytes = 1 << size; | |
2599 | int elements = (is_q ? 128 : 64) / (8 << size); | |
2600 | int rpt; /* num iterations */ | |
2601 | int selem; /* structure elements */ | |
2602 | int r; | |
2603 | ||
2604 | if (extract32(insn, 31, 1) || extract32(insn, 21, 1)) { | |
2605 | unallocated_encoding(s); | |
2606 | return; | |
2607 | } | |
2608 | ||
2609 | /* From the shared decode logic */ | |
2610 | switch (opcode) { | |
2611 | case 0x0: | |
2612 | rpt = 1; | |
2613 | selem = 4; | |
2614 | break; | |
2615 | case 0x2: | |
2616 | rpt = 4; | |
2617 | selem = 1; | |
2618 | break; | |
2619 | case 0x4: | |
2620 | rpt = 1; | |
2621 | selem = 3; | |
2622 | break; | |
2623 | case 0x6: | |
2624 | rpt = 3; | |
2625 | selem = 1; | |
2626 | break; | |
2627 | case 0x7: | |
2628 | rpt = 1; | |
2629 | selem = 1; | |
2630 | break; | |
2631 | case 0x8: | |
2632 | rpt = 1; | |
2633 | selem = 2; | |
2634 | break; | |
2635 | case 0xa: | |
2636 | rpt = 2; | |
2637 | selem = 1; | |
2638 | break; | |
2639 | default: | |
2640 | unallocated_encoding(s); | |
2641 | return; | |
2642 | } | |
2643 | ||
2644 | if (size == 3 && !is_q && selem != 1) { | |
2645 | /* reserved */ | |
2646 | unallocated_encoding(s); | |
2647 | return; | |
2648 | } | |
2649 | ||
8c6afa6a PM |
2650 | if (!fp_access_check(s)) { |
2651 | return; | |
2652 | } | |
2653 | ||
72430bf5 AB |
2654 | if (rn == 31) { |
2655 | gen_check_sp_alignment(s); | |
2656 | } | |
2657 | ||
2658 | tcg_rn = cpu_reg_sp(s, rn); | |
2659 | tcg_addr = tcg_temp_new_i64(); | |
2660 | tcg_gen_mov_i64(tcg_addr, tcg_rn); | |
2661 | ||
2662 | for (r = 0; r < rpt; r++) { | |
2663 | int e; | |
2664 | for (e = 0; e < elements; e++) { | |
2665 | int tt = (rt + r) % 32; | |
2666 | int xs; | |
2667 | for (xs = 0; xs < selem; xs++) { | |
2668 | if (is_store) { | |
2669 | do_vec_st(s, tt, e, tcg_addr, size); | |
2670 | } else { | |
2671 | do_vec_ld(s, tt, e, tcg_addr, size); | |
2672 | ||
2673 | /* For non-quad operations, setting a slice of the low | |
2674 | * 64 bits of the register clears the high 64 bits (in | |
2675 | * the ARM ARM pseudocode this is implicit in the fact | |
2676 | * that 'rval' is a 64 bit wide variable). We optimize | |
2677 | * by noticing that we only need to do this the first | |
2678 | * time we touch a register. | |
2679 | */ | |
2680 | if (!is_q && e == 0 && (r == 0 || xs == selem - 1)) { | |
2681 | clear_vec_high(s, tt); | |
2682 | } | |
2683 | } | |
2684 | tcg_gen_addi_i64(tcg_addr, tcg_addr, ebytes); | |
2685 | tt = (tt + 1) % 32; | |
2686 | } | |
2687 | } | |
2688 | } | |
2689 | ||
2690 | if (is_postidx) { | |
2691 | int rm = extract32(insn, 16, 5); | |
2692 | if (rm == 31) { | |
2693 | tcg_gen_mov_i64(tcg_rn, tcg_addr); | |
2694 | } else { | |
2695 | tcg_gen_add_i64(tcg_rn, tcg_rn, cpu_reg(s, rm)); | |
2696 | } | |
2697 | } | |
2698 | tcg_temp_free_i64(tcg_addr); | |
ad7ee8a2 CF |
2699 | } |
2700 | ||
df54e47d PM |
2701 | /* C3.3.3 AdvSIMD load/store single structure |
2702 | * | |
2703 | * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0 | |
2704 | * +---+---+---------------+-----+-----------+-----+---+------+------+------+ | |
2705 | * | 0 | Q | 0 0 1 1 0 1 0 | L R | 0 0 0 0 0 | opc | S | size | Rn | Rt | | |
2706 | * +---+---+---------------+-----+-----------+-----+---+------+------+------+ | |
2707 | * | |
2708 | * C3.3.4 AdvSIMD load/store single structure (post-indexed) | |
2709 | * | |
2710 | * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0 | |
2711 | * +---+---+---------------+-----+-----------+-----+---+------+------+------+ | |
2712 | * | 0 | Q | 0 0 1 1 0 1 1 | L R | Rm | opc | S | size | Rn | Rt | | |
2713 | * +---+---+---------------+-----+-----------+-----+---+------+------+------+ | |
2714 | * | |
2715 | * Rt: first (or only) SIMD&FP register to be transferred | |
2716 | * Rn: base address or SP | |
2717 | * Rm (post-index only): post-index register (when !31) or size dependent #imm | |
2718 | * index = encoded in Q:S:size dependent on size | |
2719 | * | |
2720 | * lane_size = encoded in R, opc | |
2721 | * transfer width = encoded in opc, S, size | |
2722 | */ | |
ad7ee8a2 CF |
2723 | static void disas_ldst_single_struct(DisasContext *s, uint32_t insn) |
2724 | { | |
df54e47d PM |
2725 | int rt = extract32(insn, 0, 5); |
2726 | int rn = extract32(insn, 5, 5); | |
2727 | int size = extract32(insn, 10, 2); | |
2728 | int S = extract32(insn, 12, 1); | |
2729 | int opc = extract32(insn, 13, 3); | |
2730 | int R = extract32(insn, 21, 1); | |
2731 | int is_load = extract32(insn, 22, 1); | |
2732 | int is_postidx = extract32(insn, 23, 1); | |
2733 | int is_q = extract32(insn, 30, 1); | |
2734 | ||
2735 | int scale = extract32(opc, 1, 2); | |
2736 | int selem = (extract32(opc, 0, 1) << 1 | R) + 1; | |
2737 | bool replicate = false; | |
2738 | int index = is_q << 3 | S << 2 | size; | |
2739 | int ebytes, xs; | |
2740 | TCGv_i64 tcg_addr, tcg_rn; | |
2741 | ||
2742 | switch (scale) { | |
2743 | case 3: | |
2744 | if (!is_load || S) { | |
2745 | unallocated_encoding(s); | |
2746 | return; | |
2747 | } | |
2748 | scale = size; | |
2749 | replicate = true; | |
2750 | break; | |
2751 | case 0: | |
2752 | break; | |
2753 | case 1: | |
2754 | if (extract32(size, 0, 1)) { | |
2755 | unallocated_encoding(s); | |
2756 | return; | |
2757 | } | |
2758 | index >>= 1; | |
2759 | break; | |
2760 | case 2: | |
2761 | if (extract32(size, 1, 1)) { | |
2762 | unallocated_encoding(s); | |
2763 | return; | |
2764 | } | |
2765 | if (!extract32(size, 0, 1)) { | |
2766 | index >>= 2; | |
2767 | } else { | |
2768 | if (S) { | |
2769 | unallocated_encoding(s); | |
2770 | return; | |
2771 | } | |
2772 | index >>= 3; | |
2773 | scale = 3; | |
2774 | } | |
2775 | break; | |
2776 | default: | |
2777 | g_assert_not_reached(); | |
2778 | } | |
2779 | ||
8c6afa6a PM |
2780 | if (!fp_access_check(s)) { |
2781 | return; | |
2782 | } | |
2783 | ||
df54e47d PM |
2784 | ebytes = 1 << scale; |
2785 | ||
2786 | if (rn == 31) { | |
2787 | gen_check_sp_alignment(s); | |
2788 | } | |
2789 | ||
2790 | tcg_rn = cpu_reg_sp(s, rn); | |
2791 | tcg_addr = tcg_temp_new_i64(); | |
2792 | tcg_gen_mov_i64(tcg_addr, tcg_rn); | |
2793 | ||
2794 | for (xs = 0; xs < selem; xs++) { | |
2795 | if (replicate) { | |
2796 | /* Load and replicate to all elements */ | |
2797 | uint64_t mulconst; | |
2798 | TCGv_i64 tcg_tmp = tcg_temp_new_i64(); | |
2799 | ||
2800 | tcg_gen_qemu_ld_i64(tcg_tmp, tcg_addr, | |
aa6489da | 2801 | get_mem_index(s), s->be_data + scale); |
df54e47d PM |
2802 | switch (scale) { |
2803 | case 0: | |
2804 | mulconst = 0x0101010101010101ULL; | |
2805 | break; | |
2806 | case 1: | |
2807 | mulconst = 0x0001000100010001ULL; | |
2808 | break; | |
2809 | case 2: | |
2810 | mulconst = 0x0000000100000001ULL; | |
2811 | break; | |
2812 | case 3: | |
2813 | mulconst = 0; | |
2814 | break; | |
2815 | default: | |
2816 | g_assert_not_reached(); | |
2817 | } | |
2818 | if (mulconst) { | |
2819 | tcg_gen_muli_i64(tcg_tmp, tcg_tmp, mulconst); | |
2820 | } | |
2821 | write_vec_element(s, tcg_tmp, rt, 0, MO_64); | |
2822 | if (is_q) { | |
2823 | write_vec_element(s, tcg_tmp, rt, 1, MO_64); | |
2824 | } else { | |
2825 | clear_vec_high(s, rt); | |
2826 | } | |
2827 | tcg_temp_free_i64(tcg_tmp); | |
2828 | } else { | |
2829 | /* Load/store one element per register */ | |
2830 | if (is_load) { | |
0a97c40f | 2831 | do_vec_ld(s, rt, index, tcg_addr, scale); |
df54e47d | 2832 | } else { |
0a97c40f | 2833 | do_vec_st(s, rt, index, tcg_addr, scale); |
df54e47d PM |
2834 | } |
2835 | } | |
2836 | tcg_gen_addi_i64(tcg_addr, tcg_addr, ebytes); | |
2837 | rt = (rt + 1) % 32; | |
2838 | } | |
2839 | ||
2840 | if (is_postidx) { | |
2841 | int rm = extract32(insn, 16, 5); | |
2842 | if (rm == 31) { | |
2843 | tcg_gen_mov_i64(tcg_rn, tcg_addr); | |
2844 | } else { | |
2845 | tcg_gen_add_i64(tcg_rn, tcg_rn, cpu_reg(s, rm)); | |
2846 | } | |
2847 | } | |
2848 | tcg_temp_free_i64(tcg_addr); | |
ad7ee8a2 CF |
2849 | } |
2850 | ||
2851 | /* C3.3 Loads and stores */ | |
2852 | static void disas_ldst(DisasContext *s, uint32_t insn) | |
2853 | { | |
2854 | switch (extract32(insn, 24, 6)) { | |
2855 | case 0x08: /* Load/store exclusive */ | |
2856 | disas_ldst_excl(s, insn); | |
2857 | break; | |
2858 | case 0x18: case 0x1c: /* Load register (literal) */ | |
2859 | disas_ld_lit(s, insn); | |
2860 | break; | |
2861 | case 0x28: case 0x29: | |
2862 | case 0x2c: case 0x2d: /* Load/store pair (all forms) */ | |
2863 | disas_ldst_pair(s, insn); | |
2864 | break; | |
2865 | case 0x38: case 0x39: | |
2866 | case 0x3c: case 0x3d: /* Load/store register (all forms) */ | |
2867 | disas_ldst_reg(s, insn); | |
2868 | break; | |
2869 | case 0x0c: /* AdvSIMD load/store multiple structures */ | |
2870 | disas_ldst_multiple_struct(s, insn); | |
2871 | break; | |
2872 | case 0x0d: /* AdvSIMD load/store single structure */ | |
2873 | disas_ldst_single_struct(s, insn); | |
2874 | break; | |
2875 | default: | |
2876 | unallocated_encoding(s); | |
2877 | break; | |
2878 | } | |
2879 | } | |
2880 | ||
15bfe8b6 AG |
2881 | /* C3.4.6 PC-rel. addressing |
2882 | * 31 30 29 28 24 23 5 4 0 | |
2883 | * +----+-------+-----------+-------------------+------+ | |
2884 | * | op | immlo | 1 0 0 0 0 | immhi | Rd | | |
2885 | * +----+-------+-----------+-------------------+------+ | |
2886 | */ | |
ad7ee8a2 CF |
2887 | static void disas_pc_rel_adr(DisasContext *s, uint32_t insn) |
2888 | { | |
15bfe8b6 AG |
2889 | unsigned int page, rd; |
2890 | uint64_t base; | |
037e1d00 | 2891 | uint64_t offset; |
15bfe8b6 AG |
2892 | |
2893 | page = extract32(insn, 31, 1); | |
2894 | /* SignExtend(immhi:immlo) -> offset */ | |
037e1d00 PM |
2895 | offset = sextract64(insn, 5, 19); |
2896 | offset = offset << 2 | extract32(insn, 29, 2); | |
15bfe8b6 AG |
2897 | rd = extract32(insn, 0, 5); |
2898 | base = s->pc - 4; | |
2899 | ||
2900 | if (page) { | |
2901 | /* ADRP (page based) */ | |
2902 | base &= ~0xfff; | |
2903 | offset <<= 12; | |
2904 | } | |
2905 | ||
2906 | tcg_gen_movi_i64(cpu_reg(s, rd), base + offset); | |
ad7ee8a2 CF |
2907 | } |
2908 | ||
b0ff21b4 AB |
2909 | /* |
2910 | * C3.4.1 Add/subtract (immediate) | |
2911 | * | |
2912 | * 31 30 29 28 24 23 22 21 10 9 5 4 0 | |
2913 | * +--+--+--+-----------+-----+-------------+-----+-----+ | |
2914 | * |sf|op| S| 1 0 0 0 1 |shift| imm12 | Rn | Rd | | |
2915 | * +--+--+--+-----------+-----+-------------+-----+-----+ | |
2916 | * | |
2917 | * sf: 0 -> 32bit, 1 -> 64bit | |
2918 | * op: 0 -> add , 1 -> sub | |
2919 | * S: 1 -> set flags | |
2920 | * shift: 00 -> LSL imm by 0, 01 -> LSL imm by 12 | |
2921 | */ | |
ad7ee8a2 CF |
2922 | static void disas_add_sub_imm(DisasContext *s, uint32_t insn) |
2923 | { | |
b0ff21b4 AB |
2924 | int rd = extract32(insn, 0, 5); |
2925 | int rn = extract32(insn, 5, 5); | |
2926 | uint64_t imm = extract32(insn, 10, 12); | |
2927 | int shift = extract32(insn, 22, 2); | |
2928 | bool setflags = extract32(insn, 29, 1); | |
2929 | bool sub_op = extract32(insn, 30, 1); | |
2930 | bool is_64bit = extract32(insn, 31, 1); | |
2931 | ||
2932 | TCGv_i64 tcg_rn = cpu_reg_sp(s, rn); | |
2933 | TCGv_i64 tcg_rd = setflags ? cpu_reg(s, rd) : cpu_reg_sp(s, rd); | |
2934 | TCGv_i64 tcg_result; | |
2935 | ||
2936 | switch (shift) { | |
2937 | case 0x0: | |
2938 | break; | |
2939 | case 0x1: | |
2940 | imm <<= 12; | |
2941 | break; | |
2942 | default: | |
2943 | unallocated_encoding(s); | |
2944 | return; | |
2945 | } | |
2946 | ||
2947 | tcg_result = tcg_temp_new_i64(); | |
2948 | if (!setflags) { | |
2949 | if (sub_op) { | |
2950 | tcg_gen_subi_i64(tcg_result, tcg_rn, imm); | |
2951 | } else { | |
2952 | tcg_gen_addi_i64(tcg_result, tcg_rn, imm); | |
2953 | } | |
2954 | } else { | |
2955 | TCGv_i64 tcg_imm = tcg_const_i64(imm); | |
2956 | if (sub_op) { | |
2957 | gen_sub_CC(is_64bit, tcg_result, tcg_rn, tcg_imm); | |
2958 | } else { | |
2959 | gen_add_CC(is_64bit, tcg_result, tcg_rn, tcg_imm); | |
2960 | } | |
2961 | tcg_temp_free_i64(tcg_imm); | |
2962 | } | |
2963 | ||
2964 | if (is_64bit) { | |
2965 | tcg_gen_mov_i64(tcg_rd, tcg_result); | |
2966 | } else { | |
2967 | tcg_gen_ext32u_i64(tcg_rd, tcg_result); | |
2968 | } | |
2969 | ||
2970 | tcg_temp_free_i64(tcg_result); | |
ad7ee8a2 CF |
2971 | } |
2972 | ||
71b46089 AG |
2973 | /* The input should be a value in the bottom e bits (with higher |
2974 | * bits zero); returns that value replicated into every element | |
2975 | * of size e in a 64 bit integer. | |
2976 | */ | |
2977 | static uint64_t bitfield_replicate(uint64_t mask, unsigned int e) | |
2978 | { | |
2979 | assert(e != 0); | |
2980 | while (e < 64) { | |
2981 | mask |= mask << e; | |
2982 | e *= 2; | |
2983 | } | |
2984 | return mask; | |
2985 | } | |
2986 | ||
2987 | /* Return a value with the bottom len bits set (where 0 < len <= 64) */ | |
2988 | static inline uint64_t bitmask64(unsigned int length) | |
2989 | { | |
2990 | assert(length > 0 && length <= 64); | |
2991 | return ~0ULL >> (64 - length); | |
2992 | } | |
2993 | ||
2994 | /* Simplified variant of pseudocode DecodeBitMasks() for the case where we | |
2995 | * only require the wmask. Returns false if the imms/immr/immn are a reserved | |
2996 | * value (ie should cause a guest UNDEF exception), and true if they are | |
2997 | * valid, in which case the decoded bit pattern is written to result. | |
2998 | */ | |
2999 | static bool logic_imm_decode_wmask(uint64_t *result, unsigned int immn, | |
3000 | unsigned int imms, unsigned int immr) | |
3001 | { | |
3002 | uint64_t mask; | |
3003 | unsigned e, levels, s, r; | |
3004 | int len; | |
3005 | ||
3006 | assert(immn < 2 && imms < 64 && immr < 64); | |
3007 | ||
3008 | /* The bit patterns we create here are 64 bit patterns which | |
3009 | * are vectors of identical elements of size e = 2, 4, 8, 16, 32 or | |
3010 | * 64 bits each. Each element contains the same value: a run | |
3011 | * of between 1 and e-1 non-zero bits, rotated within the | |
3012 | * element by between 0 and e-1 bits. | |
3013 | * | |
3014 | * The element size and run length are encoded into immn (1 bit) | |
3015 | * and imms (6 bits) as follows: | |
3016 | * 64 bit elements: immn = 1, imms = <length of run - 1> | |
3017 | * 32 bit elements: immn = 0, imms = 0 : <length of run - 1> | |
3018 | * 16 bit elements: immn = 0, imms = 10 : <length of run - 1> | |
3019 | * 8 bit elements: immn = 0, imms = 110 : <length of run - 1> | |
3020 | * 4 bit elements: immn = 0, imms = 1110 : <length of run - 1> | |
3021 | * 2 bit elements: immn = 0, imms = 11110 : <length of run - 1> | |
3022 | * Notice that immn = 0, imms = 11111x is the only combination | |
3023 | * not covered by one of the above options; this is reserved. | |
3024 | * Further, <length of run - 1> all-ones is a reserved pattern. | |
3025 | * | |
3026 | * In all cases the rotation is by immr % e (and immr is 6 bits). | |
3027 | */ | |
3028 | ||
3029 | /* First determine the element size */ | |
3030 | len = 31 - clz32((immn << 6) | (~imms & 0x3f)); | |
3031 | if (len < 1) { | |
3032 | /* This is the immn == 0, imms == 0x11111x case */ | |
3033 | return false; | |
3034 | } | |
3035 | e = 1 << len; | |
3036 | ||
3037 | levels = e - 1; | |
3038 | s = imms & levels; | |
3039 | r = immr & levels; | |
3040 | ||
3041 | if (s == levels) { | |
3042 | /* <length of run - 1> mustn't be all-ones. */ | |
3043 | return false; | |
3044 | } | |
3045 | ||
3046 | /* Create the value of one element: s+1 set bits rotated | |
3047 | * by r within the element (which is e bits wide)... | |
3048 | */ | |
3049 | mask = bitmask64(s + 1); | |
e167adc9 PM |
3050 | if (r) { |
3051 | mask = (mask >> r) | (mask << (e - r)); | |
3052 | mask &= bitmask64(e); | |
3053 | } | |
71b46089 AG |
3054 | /* ...then replicate the element over the whole 64 bit value */ |
3055 | mask = bitfield_replicate(mask, e); | |
3056 | *result = mask; | |
3057 | return true; | |
3058 | } | |
3059 | ||
3060 | /* C3.4.4 Logical (immediate) | |
3061 | * 31 30 29 28 23 22 21 16 15 10 9 5 4 0 | |
3062 | * +----+-----+-------------+---+------+------+------+------+ | |
3063 | * | sf | opc | 1 0 0 1 0 0 | N | immr | imms | Rn | Rd | | |
3064 | * +----+-----+-------------+---+------+------+------+------+ | |
3065 | */ | |
ad7ee8a2 CF |
3066 | static void disas_logic_imm(DisasContext *s, uint32_t insn) |
3067 | { | |
71b46089 AG |
3068 | unsigned int sf, opc, is_n, immr, imms, rn, rd; |
3069 | TCGv_i64 tcg_rd, tcg_rn; | |
3070 | uint64_t wmask; | |
3071 | bool is_and = false; | |
3072 | ||
3073 | sf = extract32(insn, 31, 1); | |
3074 | opc = extract32(insn, 29, 2); | |
3075 | is_n = extract32(insn, 22, 1); | |
3076 | immr = extract32(insn, 16, 6); | |
3077 | imms = extract32(insn, 10, 6); | |
3078 | rn = extract32(insn, 5, 5); | |
3079 | rd = extract32(insn, 0, 5); | |
3080 | ||
3081 | if (!sf && is_n) { | |
3082 | unallocated_encoding(s); | |
3083 | return; | |
3084 | } | |
3085 | ||
3086 | if (opc == 0x3) { /* ANDS */ | |
3087 | tcg_rd = cpu_reg(s, rd); | |
3088 | } else { | |
3089 | tcg_rd = cpu_reg_sp(s, rd); | |
3090 | } | |
3091 | tcg_rn = cpu_reg(s, rn); | |
3092 | ||
3093 | if (!logic_imm_decode_wmask(&wmask, is_n, imms, immr)) { | |
3094 | /* some immediate field values are reserved */ | |
3095 | unallocated_encoding(s); | |
3096 | return; | |
3097 | } | |
3098 | ||
3099 | if (!sf) { | |
3100 | wmask &= 0xffffffff; | |
3101 | } | |
3102 | ||
3103 | switch (opc) { | |
3104 | case 0x3: /* ANDS */ | |
3105 | case 0x0: /* AND */ | |
3106 | tcg_gen_andi_i64(tcg_rd, tcg_rn, wmask); | |
3107 | is_and = true; | |
3108 | break; | |
3109 | case 0x1: /* ORR */ | |
3110 | tcg_gen_ori_i64(tcg_rd, tcg_rn, wmask); | |
3111 | break; | |
3112 | case 0x2: /* EOR */ | |
3113 | tcg_gen_xori_i64(tcg_rd, tcg_rn, wmask); | |
3114 | break; | |
3115 | default: | |
3116 | assert(FALSE); /* must handle all above */ | |
3117 | break; | |
3118 | } | |
3119 | ||
3120 | if (!sf && !is_and) { | |
3121 | /* zero extend final result; we know we can skip this for AND | |
3122 | * since the immediate had the high 32 bits clear. | |
3123 | */ | |
3124 | tcg_gen_ext32u_i64(tcg_rd, tcg_rd); | |
3125 | } | |
3126 | ||
3127 | if (opc == 3) { /* ANDS */ | |
3128 | gen_logic_CC(sf, tcg_rd); | |
3129 | } | |
ad7ee8a2 CF |
3130 | } |
3131 | ||
ed6ec679 AB |
3132 | /* |
3133 | * C3.4.5 Move wide (immediate) | |
3134 | * | |
3135 | * 31 30 29 28 23 22 21 20 5 4 0 | |
3136 | * +--+-----+-------------+-----+----------------+------+ | |
3137 | * |sf| opc | 1 0 0 1 0 1 | hw | imm16 | Rd | | |
3138 | * +--+-----+-------------+-----+----------------+------+ | |
3139 | * | |
3140 | * sf: 0 -> 32 bit, 1 -> 64 bit | |
3141 | * opc: 00 -> N, 10 -> Z, 11 -> K | |
3142 | * hw: shift/16 (0,16, and sf only 32, 48) | |
3143 | */ | |
ad7ee8a2 CF |
3144 | static void disas_movw_imm(DisasContext *s, uint32_t insn) |
3145 | { | |
ed6ec679 AB |
3146 | int rd = extract32(insn, 0, 5); |
3147 | uint64_t imm = extract32(insn, 5, 16); | |
3148 | int sf = extract32(insn, 31, 1); | |
3149 | int opc = extract32(insn, 29, 2); | |
3150 | int pos = extract32(insn, 21, 2) << 4; | |
3151 | TCGv_i64 tcg_rd = cpu_reg(s, rd); | |
3152 | TCGv_i64 tcg_imm; | |
3153 | ||
3154 | if (!sf && (pos >= 32)) { | |
3155 | unallocated_encoding(s); | |
3156 | return; | |
3157 | } | |
3158 | ||
3159 | switch (opc) { | |
3160 | case 0: /* MOVN */ | |
3161 | case 2: /* MOVZ */ | |
3162 | imm <<= pos; | |
3163 | if (opc == 0) { | |
3164 | imm = ~imm; | |
3165 | } | |
3166 | if (!sf) { | |
3167 | imm &= 0xffffffffu; | |
3168 | } | |
3169 | tcg_gen_movi_i64(tcg_rd, imm); | |
3170 | break; | |
3171 | case 3: /* MOVK */ | |
3172 | tcg_imm = tcg_const_i64(imm); | |
3173 | tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_imm, pos, 16); | |
3174 | tcg_temp_free_i64(tcg_imm); | |
3175 | if (!sf) { | |
3176 | tcg_gen_ext32u_i64(tcg_rd, tcg_rd); | |
3177 | } | |
3178 | break; | |
3179 | default: | |
3180 | unallocated_encoding(s); | |
3181 | break; | |
3182 | } | |
ad7ee8a2 CF |
3183 | } |
3184 | ||
88077742 CF |
3185 | /* C3.4.2 Bitfield |
3186 | * 31 30 29 28 23 22 21 16 15 10 9 5 4 0 | |
3187 | * +----+-----+-------------+---+------+------+------+------+ | |
3188 | * | sf | opc | 1 0 0 1 1 0 | N | immr | imms | Rn | Rd | | |
3189 | * +----+-----+-------------+---+------+------+------+------+ | |
3190 | */ | |
ad7ee8a2 CF |
3191 | static void disas_bitfield(DisasContext *s, uint32_t insn) |
3192 | { | |
88077742 CF |
3193 | unsigned int sf, n, opc, ri, si, rn, rd, bitsize, pos, len; |
3194 | TCGv_i64 tcg_rd, tcg_tmp; | |
3195 | ||
3196 | sf = extract32(insn, 31, 1); | |
3197 | opc = extract32(insn, 29, 2); | |
3198 | n = extract32(insn, 22, 1); | |
3199 | ri = extract32(insn, 16, 6); | |
3200 | si = extract32(insn, 10, 6); | |
3201 | rn = extract32(insn, 5, 5); | |
3202 | rd = extract32(insn, 0, 5); | |
3203 | bitsize = sf ? 64 : 32; | |
3204 | ||
3205 | if (sf != n || ri >= bitsize || si >= bitsize || opc > 2) { | |
3206 | unallocated_encoding(s); | |
3207 | return; | |
3208 | } | |
3209 | ||
3210 | tcg_rd = cpu_reg(s, rd); | |
d3a77b42 RH |
3211 | |
3212 | /* Suppress the zero-extend for !sf. Since RI and SI are constrained | |
3213 | to be smaller than bitsize, we'll never reference data outside the | |
3214 | low 32-bits anyway. */ | |
3215 | tcg_tmp = read_cpu_reg(s, rn, 1); | |
88077742 | 3216 | |
59a71b4c | 3217 | /* Recognize simple(r) extractions. */ |
86c9ab27 | 3218 | if (si >= ri) { |
59a71b4c RH |
3219 | /* Wd<s-r:0> = Wn<s:r> */ |
3220 | len = (si - ri) + 1; | |
3221 | if (opc == 0) { /* SBFM: ASR, SBFX, SXTB, SXTH, SXTW */ | |
3222 | tcg_gen_sextract_i64(tcg_rd, tcg_tmp, ri, len); | |
ef60151b | 3223 | goto done; |
59a71b4c RH |
3224 | } else if (opc == 2) { /* UBFM: UBFX, LSR, UXTB, UXTH */ |
3225 | tcg_gen_extract_i64(tcg_rd, tcg_tmp, ri, len); | |
9924e858 RH |
3226 | return; |
3227 | } | |
59a71b4c RH |
3228 | /* opc == 1, BXFIL fall through to deposit */ |
3229 | tcg_gen_extract_i64(tcg_tmp, tcg_tmp, ri, len); | |
88077742 | 3230 | pos = 0; |
88077742 | 3231 | } else { |
59a71b4c RH |
3232 | /* Handle the ri > si case with a deposit |
3233 | * Wd<32+s-r,32-r> = Wn<s:0> | |
3234 | */ | |
88077742 | 3235 | len = si + 1; |
59a71b4c | 3236 | pos = (bitsize - ri) & (bitsize - 1); |
88077742 CF |
3237 | } |
3238 | ||
59a71b4c RH |
3239 | if (opc == 0 && len < ri) { |
3240 | /* SBFM: sign extend the destination field from len to fill | |
3241 | the balance of the word. Let the deposit below insert all | |
3242 | of those sign bits. */ | |
3243 | tcg_gen_sextract_i64(tcg_tmp, tcg_tmp, 0, len); | |
3244 | len = ri; | |
3245 | } | |
88077742 | 3246 | |
59a71b4c RH |
3247 | if (opc == 1) { /* BFM, BXFIL */ |
3248 | tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_tmp, pos, len); | |
3249 | } else { | |
3250 | /* SBFM or UBFM: We start with zero, and we haven't modified | |
3251 | any bits outside bitsize, therefore the zero-extension | |
3252 | below is unneeded. */ | |
3253 | tcg_gen_deposit_z_i64(tcg_rd, tcg_tmp, pos, len); | |
3254 | return; | |
88077742 CF |
3255 | } |
3256 | ||
ef60151b | 3257 | done: |
88077742 CF |
3258 | if (!sf) { /* zero extend final result */ |
3259 | tcg_gen_ext32u_i64(tcg_rd, tcg_rd); | |
3260 | } | |
ad7ee8a2 CF |
3261 | } |
3262 | ||
e801de93 AG |
3263 | /* C3.4.3 Extract |
3264 | * 31 30 29 28 23 22 21 20 16 15 10 9 5 4 0 | |
3265 | * +----+------+-------------+---+----+------+--------+------+------+ | |
3266 | * | sf | op21 | 1 0 0 1 1 1 | N | o0 | Rm | imms | Rn | Rd | | |
3267 | * +----+------+-------------+---+----+------+--------+------+------+ | |
3268 | */ | |
ad7ee8a2 CF |
3269 | static void disas_extract(DisasContext *s, uint32_t insn) |
3270 | { | |
e801de93 AG |
3271 | unsigned int sf, n, rm, imm, rn, rd, bitsize, op21, op0; |
3272 | ||
3273 | sf = extract32(insn, 31, 1); | |
3274 | n = extract32(insn, 22, 1); | |
3275 | rm = extract32(insn, 16, 5); | |
3276 | imm = extract32(insn, 10, 6); | |
3277 | rn = extract32(insn, 5, 5); | |
3278 | rd = extract32(insn, 0, 5); | |
3279 | op21 = extract32(insn, 29, 2); | |
3280 | op0 = extract32(insn, 21, 1); | |
3281 | bitsize = sf ? 64 : 32; | |
3282 | ||
3283 | if (sf != n || op21 || op0 || imm >= bitsize) { | |
3284 | unallocated_encoding(s); | |
3285 | } else { | |
3286 | TCGv_i64 tcg_rd, tcg_rm, tcg_rn; | |
3287 | ||
3288 | tcg_rd = cpu_reg(s, rd); | |
3289 | ||
8fb0ad8e | 3290 | if (unlikely(imm == 0)) { |
e801de93 AG |
3291 | /* tcg shl_i32/shl_i64 is undefined for 32/64 bit shifts, |
3292 | * so an extract from bit 0 is a special case. | |
3293 | */ | |
3294 | if (sf) { | |
3295 | tcg_gen_mov_i64(tcg_rd, cpu_reg(s, rm)); | |
3296 | } else { | |
3297 | tcg_gen_ext32u_i64(tcg_rd, cpu_reg(s, rm)); | |
3298 | } | |
8fb0ad8e RH |
3299 | } else if (rm == rn) { /* ROR */ |
3300 | tcg_rm = cpu_reg(s, rm); | |
3301 | if (sf) { | |
3302 | tcg_gen_rotri_i64(tcg_rd, tcg_rm, imm); | |
3303 | } else { | |
3304 | TCGv_i32 tmp = tcg_temp_new_i32(); | |
3305 | tcg_gen_extrl_i64_i32(tmp, tcg_rm); | |
3306 | tcg_gen_rotri_i32(tmp, tmp, imm); | |
3307 | tcg_gen_extu_i32_i64(tcg_rd, tmp); | |
3308 | tcg_temp_free_i32(tmp); | |
3309 | } | |
3310 | } else { | |
3311 | tcg_rm = read_cpu_reg(s, rm, sf); | |
3312 | tcg_rn = read_cpu_reg(s, rn, sf); | |
3313 | tcg_gen_shri_i64(tcg_rm, tcg_rm, imm); | |
3314 | tcg_gen_shli_i64(tcg_rn, tcg_rn, bitsize - imm); | |
3315 | tcg_gen_or_i64(tcg_rd, tcg_rm, tcg_rn); | |
3316 | if (!sf) { | |
3317 | tcg_gen_ext32u_i64(tcg_rd, tcg_rd); | |
3318 | } | |
e801de93 | 3319 | } |
e801de93 | 3320 | } |
ad7ee8a2 CF |
3321 | } |
3322 | ||
3323 | /* C3.4 Data processing - immediate */ | |
3324 | static void disas_data_proc_imm(DisasContext *s, uint32_t insn) | |
3325 | { | |
3326 | switch (extract32(insn, 23, 6)) { | |
3327 | case 0x20: case 0x21: /* PC-rel. addressing */ | |
3328 | disas_pc_rel_adr(s, insn); | |
3329 | break; | |
3330 | case 0x22: case 0x23: /* Add/subtract (immediate) */ | |
3331 | disas_add_sub_imm(s, insn); | |
3332 | break; | |
3333 | case 0x24: /* Logical (immediate) */ | |
3334 | disas_logic_imm(s, insn); | |
3335 | break; | |
3336 | case 0x25: /* Move wide (immediate) */ | |
3337 | disas_movw_imm(s, insn); | |
3338 | break; | |
3339 | case 0x26: /* Bitfield */ | |
3340 | disas_bitfield(s, insn); | |
3341 | break; | |
3342 | case 0x27: /* Extract */ | |
3343 | disas_extract(s, insn); | |
3344 | break; | |
3345 | default: | |
3346 | unallocated_encoding(s); | |
3347 | break; | |
3348 | } | |
3349 | } | |
3350 | ||
832ffa1c AG |
3351 | /* Shift a TCGv src by TCGv shift_amount, put result in dst. |
3352 | * Note that it is the caller's responsibility to ensure that the | |
3353 | * shift amount is in range (ie 0..31 or 0..63) and provide the ARM | |
3354 | * mandated semantics for out of range shifts. | |
3355 | */ | |
3356 | static void shift_reg(TCGv_i64 dst, TCGv_i64 src, int sf, | |
3357 | enum a64_shift_type shift_type, TCGv_i64 shift_amount) | |
3358 | { | |
3359 | switch (shift_type) { | |
3360 | case A64_SHIFT_TYPE_LSL: | |
3361 | tcg_gen_shl_i64(dst, src, shift_amount); | |
3362 | break; | |
3363 | case A64_SHIFT_TYPE_LSR: | |
3364 | tcg_gen_shr_i64(dst, src, shift_amount); | |
3365 | break; | |
3366 | case A64_SHIFT_TYPE_ASR: | |
3367 | if (!sf) { | |
3368 | tcg_gen_ext32s_i64(dst, src); | |
3369 | } | |
3370 | tcg_gen_sar_i64(dst, sf ? src : dst, shift_amount); | |
3371 | break; | |
3372 | case A64_SHIFT_TYPE_ROR: | |
3373 | if (sf) { | |
3374 | tcg_gen_rotr_i64(dst, src, shift_amount); | |
3375 | } else { | |
3376 | TCGv_i32 t0, t1; | |
3377 | t0 = tcg_temp_new_i32(); | |
3378 | t1 = tcg_temp_new_i32(); | |
ecc7b3aa RH |
3379 | tcg_gen_extrl_i64_i32(t0, src); |
3380 | tcg_gen_extrl_i64_i32(t1, shift_amount); | |
832ffa1c AG |
3381 | tcg_gen_rotr_i32(t0, t0, t1); |
3382 | tcg_gen_extu_i32_i64(dst, t0); | |
3383 | tcg_temp_free_i32(t0); | |
3384 | tcg_temp_free_i32(t1); | |
3385 | } | |
3386 | break; | |
3387 | default: | |
3388 | assert(FALSE); /* all shift types should be handled */ | |
3389 | break; | |
3390 | } | |
3391 | ||
3392 | if (!sf) { /* zero extend final result */ | |
3393 | tcg_gen_ext32u_i64(dst, dst); | |
3394 | } | |
3395 | } | |
3396 | ||
3397 | /* Shift a TCGv src by immediate, put result in dst. | |
3398 | * The shift amount must be in range (this should always be true as the | |
3399 | * relevant instructions will UNDEF on bad shift immediates). | |
3400 | */ | |
3401 | static void shift_reg_imm(TCGv_i64 dst, TCGv_i64 src, int sf, | |
3402 | enum a64_shift_type shift_type, unsigned int shift_i) | |
3403 | { | |
3404 | assert(shift_i < (sf ? 64 : 32)); | |
3405 | ||
3406 | if (shift_i == 0) { | |
3407 | tcg_gen_mov_i64(dst, src); | |
3408 | } else { | |
3409 | TCGv_i64 shift_const; | |
3410 | ||
3411 | shift_const = tcg_const_i64(shift_i); | |
3412 | shift_reg(dst, src, sf, shift_type, shift_const); | |
3413 | tcg_temp_free_i64(shift_const); | |
3414 | } | |
3415 | } | |
3416 | ||
3417 | /* C3.5.10 Logical (shifted register) | |
3418 | * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0 | |
3419 | * +----+-----+-----------+-------+---+------+--------+------+------+ | |
3420 | * | sf | opc | 0 1 0 1 0 | shift | N | Rm | imm6 | Rn | Rd | | |
3421 | * +----+-----+-----------+-------+---+------+--------+------+------+ | |
3422 | */ | |
ad7ee8a2 CF |
3423 | static void disas_logic_reg(DisasContext *s, uint32_t insn) |
3424 | { | |
832ffa1c AG |
3425 | TCGv_i64 tcg_rd, tcg_rn, tcg_rm; |
3426 | unsigned int sf, opc, shift_type, invert, rm, shift_amount, rn, rd; | |
3427 | ||
3428 | sf = extract32(insn, 31, 1); | |
3429 | opc = extract32(insn, 29, 2); | |
3430 | shift_type = extract32(insn, 22, 2); | |
3431 | invert = extract32(insn, 21, 1); | |
3432 | rm = extract32(insn, 16, 5); | |
3433 | shift_amount = extract32(insn, 10, 6); | |
3434 | rn = extract32(insn, 5, 5); | |
3435 | rd = extract32(insn, 0, 5); | |
3436 | ||
3437 | if (!sf && (shift_amount & (1 << 5))) { | |
3438 | unallocated_encoding(s); | |
3439 | return; | |
3440 | } | |
3441 | ||
3442 | tcg_rd = cpu_reg(s, rd); | |
3443 | ||
3444 | if (opc == 1 && shift_amount == 0 && shift_type == 0 && rn == 31) { | |
3445 | /* Unshifted ORR and ORN with WZR/XZR is the standard encoding for | |
3446 | * register-register MOV and MVN, so it is worth special casing. | |
3447 | */ | |
3448 | tcg_rm = cpu_reg(s, rm); | |
3449 | if (invert) { | |
3450 | tcg_gen_not_i64(tcg_rd, tcg_rm); | |
3451 | if (!sf) { | |
3452 | tcg_gen_ext32u_i64(tcg_rd, tcg_rd); | |
3453 | } | |
3454 | } else { | |
3455 | if (sf) { | |
3456 | tcg_gen_mov_i64(tcg_rd, tcg_rm); | |
3457 | } else { | |
3458 | tcg_gen_ext32u_i64(tcg_rd, tcg_rm); | |
3459 | } | |
3460 | } | |
3461 | return; | |
3462 | } | |
3463 | ||
3464 | tcg_rm = read_cpu_reg(s, rm, sf); | |
3465 | ||
3466 | if (shift_amount) { | |
3467 | shift_reg_imm(tcg_rm, tcg_rm, sf, shift_type, shift_amount); | |
3468 | } | |
3469 | ||
3470 | tcg_rn = cpu_reg(s, rn); | |
3471 | ||
3472 | switch (opc | (invert << 2)) { | |
3473 | case 0: /* AND */ | |
3474 | case 3: /* ANDS */ | |
3475 | tcg_gen_and_i64(tcg_rd, tcg_rn, tcg_rm); | |
3476 | break; | |
3477 | case 1: /* ORR */ | |
3478 | tcg_gen_or_i64(tcg_rd, tcg_rn, tcg_rm); | |
3479 | break; | |
3480 | case 2: /* EOR */ | |
3481 | tcg_gen_xor_i64(tcg_rd, tcg_rn, tcg_rm); | |
3482 | break; | |
3483 | case 4: /* BIC */ | |
3484 | case 7: /* BICS */ | |
3485 | tcg_gen_andc_i64(tcg_rd, tcg_rn, tcg_rm); | |
3486 | break; | |
3487 | case 5: /* ORN */ | |
3488 | tcg_gen_orc_i64(tcg_rd, tcg_rn, tcg_rm); | |
3489 | break; | |
3490 | case 6: /* EON */ | |
3491 | tcg_gen_eqv_i64(tcg_rd, tcg_rn, tcg_rm); | |
3492 | break; | |
3493 | default: | |
3494 | assert(FALSE); | |
3495 | break; | |
3496 | } | |
3497 | ||
3498 | if (!sf) { | |
3499 | tcg_gen_ext32u_i64(tcg_rd, tcg_rd); | |
3500 | } | |
3501 | ||
3502 | if (opc == 3) { | |
3503 | gen_logic_CC(sf, tcg_rd); | |
3504 | } | |
ad7ee8a2 CF |
3505 | } |
3506 | ||
b0ff21b4 AB |
3507 | /* |
3508 | * C3.5.1 Add/subtract (extended register) | |
3509 | * | |
3510 | * 31|30|29|28 24|23 22|21|20 16|15 13|12 10|9 5|4 0| | |
3511 | * +--+--+--+-----------+-----+--+-------+------+------+----+----+ | |
3512 | * |sf|op| S| 0 1 0 1 1 | opt | 1| Rm |option| imm3 | Rn | Rd | | |
3513 | * +--+--+--+-----------+-----+--+-------+------+------+----+----+ | |
3514 | * | |
3515 | * sf: 0 -> 32bit, 1 -> 64bit | |
3516 | * op: 0 -> add , 1 -> sub | |
3517 | * S: 1 -> set flags | |
3518 | * opt: 00 | |
3519 | * option: extension type (see DecodeRegExtend) | |
3520 | * imm3: optional shift to Rm | |
3521 | * | |
3522 | * Rd = Rn + LSL(extend(Rm), amount) | |
3523 | */ | |
ad7ee8a2 CF |
3524 | static void disas_add_sub_ext_reg(DisasContext *s, uint32_t insn) |
3525 | { | |
b0ff21b4 AB |
3526 | int rd = extract32(insn, 0, 5); |
3527 | int rn = extract32(insn, 5, 5); | |
3528 | int imm3 = extract32(insn, 10, 3); | |
3529 | int option = extract32(insn, 13, 3); | |
3530 | int rm = extract32(insn, 16, 5); | |
3531 | bool setflags = extract32(insn, 29, 1); | |
3532 | bool sub_op = extract32(insn, 30, 1); | |
3533 | bool sf = extract32(insn, 31, 1); | |
3534 | ||
3535 | TCGv_i64 tcg_rm, tcg_rn; /* temps */ | |
3536 | TCGv_i64 tcg_rd; | |
3537 | TCGv_i64 tcg_result; | |
3538 | ||
3539 | if (imm3 > 4) { | |
3540 | unallocated_encoding(s); | |
3541 | return; | |
3542 | } | |
3543 | ||
3544 | /* non-flag setting ops may use SP */ | |
3545 | if (!setflags) { | |
b0ff21b4 AB |
3546 | tcg_rd = cpu_reg_sp(s, rd); |
3547 | } else { | |
b0ff21b4 AB |
3548 | tcg_rd = cpu_reg(s, rd); |
3549 | } | |
cf4ab1af | 3550 | tcg_rn = read_cpu_reg_sp(s, rn, sf); |
b0ff21b4 AB |
3551 | |
3552 | tcg_rm = read_cpu_reg(s, rm, sf); | |
3553 | ext_and_shift_reg(tcg_rm, tcg_rm, option, imm3); | |
3554 | ||
3555 | tcg_result = tcg_temp_new_i64(); | |
3556 | ||
3557 | if (!setflags) { | |
3558 | if (sub_op) { | |
3559 | tcg_gen_sub_i64(tcg_result, tcg_rn, tcg_rm); | |
3560 | } else { | |
3561 | tcg_gen_add_i64(tcg_result, tcg_rn, tcg_rm); | |
3562 | } | |
3563 | } else { | |
3564 | if (sub_op) { | |
3565 | gen_sub_CC(sf, tcg_result, tcg_rn, tcg_rm); | |
3566 | } else { | |
3567 | gen_add_CC(sf, tcg_result, tcg_rn, tcg_rm); | |
3568 | } | |
3569 | } | |
3570 | ||
3571 | if (sf) { | |
3572 | tcg_gen_mov_i64(tcg_rd, tcg_result); | |
3573 | } else { | |
3574 | tcg_gen_ext32u_i64(tcg_rd, tcg_result); | |
3575 | } | |
3576 | ||
3577 | tcg_temp_free_i64(tcg_result); | |
ad7ee8a2 CF |
3578 | } |
3579 | ||
b0ff21b4 AB |
3580 | /* |
3581 | * C3.5.2 Add/subtract (shifted register) | |
3582 | * | |
3583 | * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0 | |
3584 | * +--+--+--+-----------+-----+--+-------+---------+------+------+ | |
3585 | * |sf|op| S| 0 1 0 1 1 |shift| 0| Rm | imm6 | Rn | Rd | | |
3586 | * +--+--+--+-----------+-----+--+-------+---------+------+------+ | |
3587 | * | |
3588 | * sf: 0 -> 32bit, 1 -> 64bit | |
3589 | * op: 0 -> add , 1 -> sub | |
3590 | * S: 1 -> set flags | |
3591 | * shift: 00 -> LSL, 01 -> LSR, 10 -> ASR, 11 -> RESERVED | |
3592 | * imm6: Shift amount to apply to Rm before the add/sub | |
3593 | */ | |
ad7ee8a2 CF |
3594 | static void disas_add_sub_reg(DisasContext *s, uint32_t insn) |
3595 | { | |
b0ff21b4 AB |
3596 | int rd = extract32(insn, 0, 5); |
3597 | int rn = extract32(insn, 5, 5); | |
3598 | int imm6 = extract32(insn, 10, 6); | |
3599 | int rm = extract32(insn, 16, 5); | |
3600 | int shift_type = extract32(insn, 22, 2); | |
3601 | bool setflags = extract32(insn, 29, 1); | |
3602 | bool sub_op = extract32(insn, 30, 1); | |
3603 | bool sf = extract32(insn, 31, 1); | |
3604 | ||
3605 | TCGv_i64 tcg_rd = cpu_reg(s, rd); | |
3606 | TCGv_i64 tcg_rn, tcg_rm; | |
3607 | TCGv_i64 tcg_result; | |
3608 | ||
3609 | if ((shift_type == 3) || (!sf && (imm6 > 31))) { | |
3610 | unallocated_encoding(s); | |
3611 | return; | |
3612 | } | |
3613 | ||
3614 | tcg_rn = read_cpu_reg(s, rn, sf); | |
3615 | tcg_rm = read_cpu_reg(s, rm, sf); | |
3616 | ||
3617 | shift_reg_imm(tcg_rm, tcg_rm, sf, shift_type, imm6); | |
3618 | ||
3619 | tcg_result = tcg_temp_new_i64(); | |
3620 | ||
3621 | if (!setflags) { | |
3622 | if (sub_op) { | |
3623 | tcg_gen_sub_i64(tcg_result, tcg_rn, tcg_rm); | |
3624 | } else { | |
3625 | tcg_gen_add_i64(tcg_result, tcg_rn, tcg_rm); | |
3626 | } | |
3627 | } else { | |
3628 | if (sub_op) { | |
3629 | gen_sub_CC(sf, tcg_result, tcg_rn, tcg_rm); | |
3630 | } else { | |
3631 | gen_add_CC(sf, tcg_result, tcg_rn, tcg_rm); | |
3632 | } | |
3633 | } | |
3634 | ||
3635 | if (sf) { | |
3636 | tcg_gen_mov_i64(tcg_rd, tcg_result); | |
3637 | } else { | |
3638 | tcg_gen_ext32u_i64(tcg_rd, tcg_result); | |
3639 | } | |
3640 | ||
3641 | tcg_temp_free_i64(tcg_result); | |
ad7ee8a2 CF |
3642 | } |
3643 | ||
52c8b9af AG |
3644 | /* C3.5.9 Data-processing (3 source) |
3645 | ||
3646 | 31 30 29 28 24 23 21 20 16 15 14 10 9 5 4 0 | |
3647 | +--+------+-----------+------+------+----+------+------+------+ | |
3648 | |sf| op54 | 1 1 0 1 1 | op31 | Rm | o0 | Ra | Rn | Rd | | |
3649 | +--+------+-----------+------+------+----+------+------+------+ | |
3650 | ||
3651 | */ | |
ad7ee8a2 CF |
3652 | static void disas_data_proc_3src(DisasContext *s, uint32_t insn) |
3653 | { | |
52c8b9af AG |
3654 | int rd = extract32(insn, 0, 5); |
3655 | int rn = extract32(insn, 5, 5); | |
3656 | int ra = extract32(insn, 10, 5); | |
3657 | int rm = extract32(insn, 16, 5); | |
3658 | int op_id = (extract32(insn, 29, 3) << 4) | | |
3659 | (extract32(insn, 21, 3) << 1) | | |
3660 | extract32(insn, 15, 1); | |
3661 | bool sf = extract32(insn, 31, 1); | |
3662 | bool is_sub = extract32(op_id, 0, 1); | |
3663 | bool is_high = extract32(op_id, 2, 1); | |
3664 | bool is_signed = false; | |
3665 | TCGv_i64 tcg_op1; | |
3666 | TCGv_i64 tcg_op2; | |
3667 | TCGv_i64 tcg_tmp; | |
3668 | ||
3669 | /* Note that op_id is sf:op54:op31:o0 so it includes the 32/64 size flag */ | |
3670 | switch (op_id) { | |
3671 | case 0x42: /* SMADDL */ | |
3672 | case 0x43: /* SMSUBL */ | |
3673 | case 0x44: /* SMULH */ | |
3674 | is_signed = true; | |
3675 | break; | |
3676 | case 0x0: /* MADD (32bit) */ | |
3677 | case 0x1: /* MSUB (32bit) */ | |
3678 | case 0x40: /* MADD (64bit) */ | |
3679 | case 0x41: /* MSUB (64bit) */ | |
3680 | case 0x4a: /* UMADDL */ | |
3681 | case 0x4b: /* UMSUBL */ | |
3682 | case 0x4c: /* UMULH */ | |
3683 | break; | |
3684 | default: | |
3685 | unallocated_encoding(s); | |
3686 | return; | |
3687 | } | |
3688 | ||
3689 | if (is_high) { | |
3690 | TCGv_i64 low_bits = tcg_temp_new_i64(); /* low bits discarded */ | |
3691 | TCGv_i64 tcg_rd = cpu_reg(s, rd); | |
3692 | TCGv_i64 tcg_rn = cpu_reg(s, rn); | |
3693 | TCGv_i64 tcg_rm = cpu_reg(s, rm); | |
3694 | ||
3695 | if (is_signed) { | |
3696 | tcg_gen_muls2_i64(low_bits, tcg_rd, tcg_rn, tcg_rm); | |
3697 | } else { | |
3698 | tcg_gen_mulu2_i64(low_bits, tcg_rd, tcg_rn, tcg_rm); | |
3699 | } | |
3700 | ||
3701 | tcg_temp_free_i64(low_bits); | |
3702 | return; | |
3703 | } | |
3704 | ||
3705 | tcg_op1 = tcg_temp_new_i64(); | |
3706 | tcg_op2 = tcg_temp_new_i64(); | |
3707 | tcg_tmp = tcg_temp_new_i64(); | |
3708 | ||
3709 | if (op_id < 0x42) { | |
3710 | tcg_gen_mov_i64(tcg_op1, cpu_reg(s, rn)); | |
3711 | tcg_gen_mov_i64(tcg_op2, cpu_reg(s, rm)); | |
3712 | } else { | |
3713 | if (is_signed) { | |
3714 | tcg_gen_ext32s_i64(tcg_op1, cpu_reg(s, rn)); | |
3715 | tcg_gen_ext32s_i64(tcg_op2, cpu_reg(s, rm)); | |
3716 | } else { | |
3717 | tcg_gen_ext32u_i64(tcg_op1, cpu_reg(s, rn)); | |
3718 | tcg_gen_ext32u_i64(tcg_op2, cpu_reg(s, rm)); | |
3719 | } | |
3720 | } | |
3721 | ||
3722 | if (ra == 31 && !is_sub) { | |
3723 | /* Special-case MADD with rA == XZR; it is the standard MUL alias */ | |
3724 | tcg_gen_mul_i64(cpu_reg(s, rd), tcg_op1, tcg_op2); | |
3725 | } else { | |
3726 | tcg_gen_mul_i64(tcg_tmp, tcg_op1, tcg_op2); | |
3727 | if (is_sub) { | |
3728 | tcg_gen_sub_i64(cpu_reg(s, rd), cpu_reg(s, ra), tcg_tmp); | |
3729 | } else { | |
3730 | tcg_gen_add_i64(cpu_reg(s, rd), cpu_reg(s, ra), tcg_tmp); | |
3731 | } | |
3732 | } | |
3733 | ||
3734 | if (!sf) { | |
3735 | tcg_gen_ext32u_i64(cpu_reg(s, rd), cpu_reg(s, rd)); | |
3736 | } | |
3737 | ||
3738 | tcg_temp_free_i64(tcg_op1); | |
3739 | tcg_temp_free_i64(tcg_op2); | |
3740 | tcg_temp_free_i64(tcg_tmp); | |
ad7ee8a2 CF |
3741 | } |
3742 | ||
643dbb07 CF |
3743 | /* C3.5.3 - Add/subtract (with carry) |
3744 | * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 10 9 5 4 0 | |
3745 | * +--+--+--+------------------------+------+---------+------+-----+ | |
3746 | * |sf|op| S| 1 1 0 1 0 0 0 0 | rm | opcode2 | Rn | Rd | | |
3747 | * +--+--+--+------------------------+------+---------+------+-----+ | |
3748 | * [000000] | |
3749 | */ | |
3750 | ||
ad7ee8a2 CF |
3751 | static void disas_adc_sbc(DisasContext *s, uint32_t insn) |
3752 | { | |
643dbb07 CF |
3753 | unsigned int sf, op, setflags, rm, rn, rd; |
3754 | TCGv_i64 tcg_y, tcg_rn, tcg_rd; | |
3755 | ||
3756 | if (extract32(insn, 10, 6) != 0) { | |
3757 | unallocated_encoding(s); | |
3758 | return; | |
3759 | } | |
3760 | ||
3761 | sf = extract32(insn, 31, 1); | |
3762 | op = extract32(insn, 30, 1); | |
3763 | setflags = extract32(insn, 29, 1); | |
3764 | rm = extract32(insn, 16, 5); | |
3765 | rn = extract32(insn, 5, 5); | |
3766 | rd = extract32(insn, 0, 5); | |
3767 | ||
3768 | tcg_rd = cpu_reg(s, rd); | |
3769 | tcg_rn = cpu_reg(s, rn); | |
3770 | ||
3771 | if (op) { | |
3772 | tcg_y = new_tmp_a64(s); | |
3773 | tcg_gen_not_i64(tcg_y, cpu_reg(s, rm)); | |
3774 | } else { | |
3775 | tcg_y = cpu_reg(s, rm); | |
3776 | } | |
3777 | ||
3778 | if (setflags) { | |
3779 | gen_adc_CC(sf, tcg_rd, tcg_rn, tcg_y); | |
3780 | } else { | |
3781 | gen_adc(sf, tcg_rd, tcg_rn, tcg_y); | |
3782 | } | |
ad7ee8a2 CF |
3783 | } |
3784 | ||
750813cf CF |
3785 | /* C3.5.4 - C3.5.5 Conditional compare (immediate / register) |
3786 | * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0 | |
3787 | * +--+--+--+------------------------+--------+------+----+--+------+--+-----+ | |
3788 | * |sf|op| S| 1 1 0 1 0 0 1 0 |imm5/rm | cond |i/r |o2| Rn |o3|nzcv | | |
3789 | * +--+--+--+------------------------+--------+------+----+--+------+--+-----+ | |
3790 | * [1] y [0] [0] | |
3791 | */ | |
3792 | static void disas_cc(DisasContext *s, uint32_t insn) | |
ad7ee8a2 | 3793 | { |
750813cf | 3794 | unsigned int sf, op, y, cond, rn, nzcv, is_imm; |
7dd03d77 | 3795 | TCGv_i32 tcg_t0, tcg_t1, tcg_t2; |
750813cf | 3796 | TCGv_i64 tcg_tmp, tcg_y, tcg_rn; |
7dd03d77 | 3797 | DisasCompare c; |
ad7ee8a2 | 3798 | |
750813cf CF |
3799 | if (!extract32(insn, 29, 1)) { |
3800 | unallocated_encoding(s); | |
3801 | return; | |
3802 | } | |
3803 | if (insn & (1 << 10 | 1 << 4)) { | |
3804 | unallocated_encoding(s); | |
3805 | return; | |
3806 | } | |
3807 | sf = extract32(insn, 31, 1); | |
3808 | op = extract32(insn, 30, 1); | |
3809 | is_imm = extract32(insn, 11, 1); | |
3810 | y = extract32(insn, 16, 5); /* y = rm (reg) or imm5 (imm) */ | |
3811 | cond = extract32(insn, 12, 4); | |
3812 | rn = extract32(insn, 5, 5); | |
3813 | nzcv = extract32(insn, 0, 4); | |
3814 | ||
7dd03d77 RH |
3815 | /* Set T0 = !COND. */ |
3816 | tcg_t0 = tcg_temp_new_i32(); | |
3817 | arm_test_cc(&c, cond); | |
3818 | tcg_gen_setcondi_i32(tcg_invert_cond(c.cond), tcg_t0, c.value, 0); | |
3819 | arm_free_cc(&c); | |
3820 | ||
3821 | /* Load the arguments for the new comparison. */ | |
750813cf CF |
3822 | if (is_imm) { |
3823 | tcg_y = new_tmp_a64(s); | |
3824 | tcg_gen_movi_i64(tcg_y, y); | |
3825 | } else { | |
3826 | tcg_y = cpu_reg(s, y); | |
3827 | } | |
3828 | tcg_rn = cpu_reg(s, rn); | |
3829 | ||
7dd03d77 | 3830 | /* Set the flags for the new comparison. */ |
750813cf CF |
3831 | tcg_tmp = tcg_temp_new_i64(); |
3832 | if (op) { | |
3833 | gen_sub_CC(sf, tcg_tmp, tcg_rn, tcg_y); | |
3834 | } else { | |
3835 | gen_add_CC(sf, tcg_tmp, tcg_rn, tcg_y); | |
3836 | } | |
3837 | tcg_temp_free_i64(tcg_tmp); | |
3838 | ||
7dd03d77 RH |
3839 | /* If COND was false, force the flags to #nzcv. Compute two masks |
3840 | * to help with this: T1 = (COND ? 0 : -1), T2 = (COND ? -1 : 0). | |
3841 | * For tcg hosts that support ANDC, we can make do with just T1. | |
3842 | * In either case, allow the tcg optimizer to delete any unused mask. | |
3843 | */ | |
3844 | tcg_t1 = tcg_temp_new_i32(); | |
3845 | tcg_t2 = tcg_temp_new_i32(); | |
3846 | tcg_gen_neg_i32(tcg_t1, tcg_t0); | |
3847 | tcg_gen_subi_i32(tcg_t2, tcg_t0, 1); | |
3848 | ||
3849 | if (nzcv & 8) { /* N */ | |
3850 | tcg_gen_or_i32(cpu_NF, cpu_NF, tcg_t1); | |
3851 | } else { | |
3852 | if (TCG_TARGET_HAS_andc_i32) { | |
3853 | tcg_gen_andc_i32(cpu_NF, cpu_NF, tcg_t1); | |
3854 | } else { | |
3855 | tcg_gen_and_i32(cpu_NF, cpu_NF, tcg_t2); | |
3856 | } | |
3857 | } | |
3858 | if (nzcv & 4) { /* Z */ | |
3859 | if (TCG_TARGET_HAS_andc_i32) { | |
3860 | tcg_gen_andc_i32(cpu_ZF, cpu_ZF, tcg_t1); | |
3861 | } else { | |
3862 | tcg_gen_and_i32(cpu_ZF, cpu_ZF, tcg_t2); | |
3863 | } | |
3864 | } else { | |
3865 | tcg_gen_or_i32(cpu_ZF, cpu_ZF, tcg_t0); | |
3866 | } | |
3867 | if (nzcv & 2) { /* C */ | |
3868 | tcg_gen_or_i32(cpu_CF, cpu_CF, tcg_t0); | |
3869 | } else { | |
3870 | if (TCG_TARGET_HAS_andc_i32) { | |
3871 | tcg_gen_andc_i32(cpu_CF, cpu_CF, tcg_t1); | |
3872 | } else { | |
3873 | tcg_gen_and_i32(cpu_CF, cpu_CF, tcg_t2); | |
3874 | } | |
3875 | } | |
3876 | if (nzcv & 1) { /* V */ | |
3877 | tcg_gen_or_i32(cpu_VF, cpu_VF, tcg_t1); | |
3878 | } else { | |
3879 | if (TCG_TARGET_HAS_andc_i32) { | |
3880 | tcg_gen_andc_i32(cpu_VF, cpu_VF, tcg_t1); | |
3881 | } else { | |
3882 | tcg_gen_and_i32(cpu_VF, cpu_VF, tcg_t2); | |
3883 | } | |
750813cf | 3884 | } |
7dd03d77 RH |
3885 | tcg_temp_free_i32(tcg_t0); |
3886 | tcg_temp_free_i32(tcg_t1); | |
3887 | tcg_temp_free_i32(tcg_t2); | |
ad7ee8a2 CF |
3888 | } |
3889 | ||
e952d8c7 CF |
3890 | /* C3.5.6 Conditional select |
3891 | * 31 30 29 28 21 20 16 15 12 11 10 9 5 4 0 | |
3892 | * +----+----+---+-----------------+------+------+-----+------+------+ | |
3893 | * | sf | op | S | 1 1 0 1 0 1 0 0 | Rm | cond | op2 | Rn | Rd | | |
3894 | * +----+----+---+-----------------+------+------+-----+------+------+ | |
3895 | */ | |
ad7ee8a2 CF |
3896 | static void disas_cond_select(DisasContext *s, uint32_t insn) |
3897 | { | |
e952d8c7 | 3898 | unsigned int sf, else_inv, rm, cond, else_inc, rn, rd; |
259cb684 RH |
3899 | TCGv_i64 tcg_rd, zero; |
3900 | DisasCompare64 c; | |
e952d8c7 CF |
3901 | |
3902 | if (extract32(insn, 29, 1) || extract32(insn, 11, 1)) { | |
3903 | /* S == 1 or op2<1> == 1 */ | |
3904 | unallocated_encoding(s); | |
3905 | return; | |
3906 | } | |
3907 | sf = extract32(insn, 31, 1); | |
3908 | else_inv = extract32(insn, 30, 1); | |
3909 | rm = extract32(insn, 16, 5); | |
3910 | cond = extract32(insn, 12, 4); | |
3911 | else_inc = extract32(insn, 10, 1); | |
3912 | rn = extract32(insn, 5, 5); | |
3913 | rd = extract32(insn, 0, 5); | |
3914 | ||
e952d8c7 CF |
3915 | tcg_rd = cpu_reg(s, rd); |
3916 | ||
259cb684 RH |
3917 | a64_test_cc(&c, cond); |
3918 | zero = tcg_const_i64(0); | |
e952d8c7 | 3919 | |
259cb684 RH |
3920 | if (rn == 31 && rm == 31 && (else_inc ^ else_inv)) { |
3921 | /* CSET & CSETM. */ | |
3922 | tcg_gen_setcond_i64(tcg_invert_cond(c.cond), tcg_rd, c.value, zero); | |
3923 | if (else_inv) { | |
3924 | tcg_gen_neg_i64(tcg_rd, tcg_rd); | |
3925 | } | |
3926 | } else { | |
3927 | TCGv_i64 t_true = cpu_reg(s, rn); | |
3928 | TCGv_i64 t_false = read_cpu_reg(s, rm, 1); | |
e952d8c7 | 3929 | if (else_inv && else_inc) { |
259cb684 | 3930 | tcg_gen_neg_i64(t_false, t_false); |
e952d8c7 | 3931 | } else if (else_inv) { |
259cb684 | 3932 | tcg_gen_not_i64(t_false, t_false); |
e952d8c7 | 3933 | } else if (else_inc) { |
259cb684 | 3934 | tcg_gen_addi_i64(t_false, t_false, 1); |
e952d8c7 | 3935 | } |
259cb684 RH |
3936 | tcg_gen_movcond_i64(c.cond, tcg_rd, c.value, zero, t_true, t_false); |
3937 | } | |
3938 | ||
3939 | tcg_temp_free_i64(zero); | |
3940 | a64_free_cc(&c); | |
3941 | ||
3942 | if (!sf) { | |
3943 | tcg_gen_ext32u_i64(tcg_rd, tcg_rd); | |
e952d8c7 | 3944 | } |
ad7ee8a2 CF |
3945 | } |
3946 | ||
680ead21 CF |
3947 | static void handle_clz(DisasContext *s, unsigned int sf, |
3948 | unsigned int rn, unsigned int rd) | |
3949 | { | |
3950 | TCGv_i64 tcg_rd, tcg_rn; | |
3951 | tcg_rd = cpu_reg(s, rd); | |
3952 | tcg_rn = cpu_reg(s, rn); | |
3953 | ||
3954 | if (sf) { | |
7539a012 | 3955 | tcg_gen_clzi_i64(tcg_rd, tcg_rn, 64); |
680ead21 CF |
3956 | } else { |
3957 | TCGv_i32 tcg_tmp32 = tcg_temp_new_i32(); | |
ecc7b3aa | 3958 | tcg_gen_extrl_i64_i32(tcg_tmp32, tcg_rn); |
7539a012 | 3959 | tcg_gen_clzi_i32(tcg_tmp32, tcg_tmp32, 32); |
680ead21 CF |
3960 | tcg_gen_extu_i32_i64(tcg_rd, tcg_tmp32); |
3961 | tcg_temp_free_i32(tcg_tmp32); | |
3962 | } | |
3963 | } | |
3964 | ||
e80c5020 CF |
3965 | static void handle_cls(DisasContext *s, unsigned int sf, |
3966 | unsigned int rn, unsigned int rd) | |
3967 | { | |
3968 | TCGv_i64 tcg_rd, tcg_rn; | |
3969 | tcg_rd = cpu_reg(s, rd); | |
3970 | tcg_rn = cpu_reg(s, rn); | |
3971 | ||
3972 | if (sf) { | |
bc21dbcc | 3973 | tcg_gen_clrsb_i64(tcg_rd, tcg_rn); |
e80c5020 CF |
3974 | } else { |
3975 | TCGv_i32 tcg_tmp32 = tcg_temp_new_i32(); | |
ecc7b3aa | 3976 | tcg_gen_extrl_i64_i32(tcg_tmp32, tcg_rn); |
bc21dbcc | 3977 | tcg_gen_clrsb_i32(tcg_tmp32, tcg_tmp32); |
e80c5020 CF |
3978 | tcg_gen_extu_i32_i64(tcg_rd, tcg_tmp32); |
3979 | tcg_temp_free_i32(tcg_tmp32); | |
3980 | } | |
3981 | } | |
3982 | ||
82e14b02 AG |
3983 | static void handle_rbit(DisasContext *s, unsigned int sf, |
3984 | unsigned int rn, unsigned int rd) | |
3985 | { | |
3986 | TCGv_i64 tcg_rd, tcg_rn; | |
3987 | tcg_rd = cpu_reg(s, rd); | |
3988 | tcg_rn = cpu_reg(s, rn); | |
3989 | ||
3990 | if (sf) { | |
3991 | gen_helper_rbit64(tcg_rd, tcg_rn); | |
3992 | } else { | |
3993 | TCGv_i32 tcg_tmp32 = tcg_temp_new_i32(); | |
ecc7b3aa | 3994 | tcg_gen_extrl_i64_i32(tcg_tmp32, tcg_rn); |
82e14b02 AG |
3995 | gen_helper_rbit(tcg_tmp32, tcg_tmp32); |
3996 | tcg_gen_extu_i32_i64(tcg_rd, tcg_tmp32); | |
3997 | tcg_temp_free_i32(tcg_tmp32); | |
3998 | } | |
3999 | } | |
4000 | ||
45323209 CF |
4001 | /* C5.6.149 REV with sf==1, opcode==3 ("REV64") */ |
4002 | static void handle_rev64(DisasContext *s, unsigned int sf, | |
4003 | unsigned int rn, unsigned int rd) | |
4004 | { | |
4005 | if (!sf) { | |
4006 | unallocated_encoding(s); | |
4007 | return; | |
4008 | } | |
4009 | tcg_gen_bswap64_i64(cpu_reg(s, rd), cpu_reg(s, rn)); | |
4010 | } | |
4011 | ||
4012 | /* C5.6.149 REV with sf==0, opcode==2 | |
4013 | * C5.6.151 REV32 (sf==1, opcode==2) | |
4014 | */ | |
4015 | static void handle_rev32(DisasContext *s, unsigned int sf, | |
4016 | unsigned int rn, unsigned int rd) | |
4017 | { | |
4018 | TCGv_i64 tcg_rd = cpu_reg(s, rd); | |
4019 | ||
4020 | if (sf) { | |
4021 | TCGv_i64 tcg_tmp = tcg_temp_new_i64(); | |
4022 | TCGv_i64 tcg_rn = read_cpu_reg(s, rn, sf); | |
4023 | ||
4024 | /* bswap32_i64 requires zero high word */ | |
4025 | tcg_gen_ext32u_i64(tcg_tmp, tcg_rn); | |
4026 | tcg_gen_bswap32_i64(tcg_rd, tcg_tmp); | |
4027 | tcg_gen_shri_i64(tcg_tmp, tcg_rn, 32); | |
4028 | tcg_gen_bswap32_i64(tcg_tmp, tcg_tmp); | |
4029 | tcg_gen_concat32_i64(tcg_rd, tcg_rd, tcg_tmp); | |
4030 | ||
4031 | tcg_temp_free_i64(tcg_tmp); | |
4032 | } else { | |
4033 | tcg_gen_ext32u_i64(tcg_rd, cpu_reg(s, rn)); | |
4034 | tcg_gen_bswap32_i64(tcg_rd, tcg_rd); | |
4035 | } | |
4036 | } | |
4037 | ||
4038 | /* C5.6.150 REV16 (opcode==1) */ | |
4039 | static void handle_rev16(DisasContext *s, unsigned int sf, | |
4040 | unsigned int rn, unsigned int rd) | |
4041 | { | |
4042 | TCGv_i64 tcg_rd = cpu_reg(s, rd); | |
4043 | TCGv_i64 tcg_tmp = tcg_temp_new_i64(); | |
4044 | TCGv_i64 tcg_rn = read_cpu_reg(s, rn, sf); | |
4045 | ||
4046 | tcg_gen_andi_i64(tcg_tmp, tcg_rn, 0xffff); | |
4047 | tcg_gen_bswap16_i64(tcg_rd, tcg_tmp); | |
4048 | ||
4049 | tcg_gen_shri_i64(tcg_tmp, tcg_rn, 16); | |
4050 | tcg_gen_andi_i64(tcg_tmp, tcg_tmp, 0xffff); | |
4051 | tcg_gen_bswap16_i64(tcg_tmp, tcg_tmp); | |
4052 | tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_tmp, 16, 16); | |
4053 | ||
4054 | if (sf) { | |
4055 | tcg_gen_shri_i64(tcg_tmp, tcg_rn, 32); | |
4056 | tcg_gen_andi_i64(tcg_tmp, tcg_tmp, 0xffff); | |
4057 | tcg_gen_bswap16_i64(tcg_tmp, tcg_tmp); | |
4058 | tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_tmp, 32, 16); | |
4059 | ||
4060 | tcg_gen_shri_i64(tcg_tmp, tcg_rn, 48); | |
4061 | tcg_gen_bswap16_i64(tcg_tmp, tcg_tmp); | |
4062 | tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_tmp, 48, 16); | |
4063 | } | |
4064 | ||
4065 | tcg_temp_free_i64(tcg_tmp); | |
4066 | } | |
4067 | ||
680ead21 CF |
4068 | /* C3.5.7 Data-processing (1 source) |
4069 | * 31 30 29 28 21 20 16 15 10 9 5 4 0 | |
4070 | * +----+---+---+-----------------+---------+--------+------+------+ | |
4071 | * | sf | 1 | S | 1 1 0 1 0 1 1 0 | opcode2 | opcode | Rn | Rd | | |
4072 | * +----+---+---+-----------------+---------+--------+------+------+ | |
4073 | */ | |
ad7ee8a2 CF |
4074 | static void disas_data_proc_1src(DisasContext *s, uint32_t insn) |
4075 | { | |
680ead21 CF |
4076 | unsigned int sf, opcode, rn, rd; |
4077 | ||
4078 | if (extract32(insn, 29, 1) || extract32(insn, 16, 5)) { | |
4079 | unallocated_encoding(s); | |
4080 | return; | |
4081 | } | |
4082 | ||
4083 | sf = extract32(insn, 31, 1); | |
4084 | opcode = extract32(insn, 10, 6); | |
4085 | rn = extract32(insn, 5, 5); | |
4086 | rd = extract32(insn, 0, 5); | |
4087 | ||
4088 | switch (opcode) { | |
4089 | case 0: /* RBIT */ | |
82e14b02 AG |
4090 | handle_rbit(s, sf, rn, rd); |
4091 | break; | |
680ead21 | 4092 | case 1: /* REV16 */ |
45323209 CF |
4093 | handle_rev16(s, sf, rn, rd); |
4094 | break; | |
680ead21 | 4095 | case 2: /* REV32 */ |
45323209 CF |
4096 | handle_rev32(s, sf, rn, rd); |
4097 | break; | |
680ead21 | 4098 | case 3: /* REV64 */ |
45323209 | 4099 | handle_rev64(s, sf, rn, rd); |
680ead21 CF |
4100 | break; |
4101 | case 4: /* CLZ */ | |
4102 | handle_clz(s, sf, rn, rd); | |
4103 | break; | |
4104 | case 5: /* CLS */ | |
e80c5020 | 4105 | handle_cls(s, sf, rn, rd); |
680ead21 CF |
4106 | break; |
4107 | } | |
ad7ee8a2 CF |
4108 | } |
4109 | ||
8220e911 AG |
4110 | static void handle_div(DisasContext *s, bool is_signed, unsigned int sf, |
4111 | unsigned int rm, unsigned int rn, unsigned int rd) | |
4112 | { | |
4113 | TCGv_i64 tcg_n, tcg_m, tcg_rd; | |
4114 | tcg_rd = cpu_reg(s, rd); | |
4115 | ||
4116 | if (!sf && is_signed) { | |
4117 | tcg_n = new_tmp_a64(s); | |
4118 | tcg_m = new_tmp_a64(s); | |
4119 | tcg_gen_ext32s_i64(tcg_n, cpu_reg(s, rn)); | |
4120 | tcg_gen_ext32s_i64(tcg_m, cpu_reg(s, rm)); | |
4121 | } else { | |
4122 | tcg_n = read_cpu_reg(s, rn, sf); | |
4123 | tcg_m = read_cpu_reg(s, rm, sf); | |
4124 | } | |
4125 | ||
4126 | if (is_signed) { | |
4127 | gen_helper_sdiv64(tcg_rd, tcg_n, tcg_m); | |
4128 | } else { | |
4129 | gen_helper_udiv64(tcg_rd, tcg_n, tcg_m); | |
4130 | } | |
4131 | ||
4132 | if (!sf) { /* zero extend final result */ | |
4133 | tcg_gen_ext32u_i64(tcg_rd, tcg_rd); | |
4134 | } | |
4135 | } | |
4136 | ||
6c1adc91 AG |
4137 | /* C5.6.115 LSLV, C5.6.118 LSRV, C5.6.17 ASRV, C5.6.154 RORV */ |
4138 | static void handle_shift_reg(DisasContext *s, | |
4139 | enum a64_shift_type shift_type, unsigned int sf, | |
4140 | unsigned int rm, unsigned int rn, unsigned int rd) | |
4141 | { | |
4142 | TCGv_i64 tcg_shift = tcg_temp_new_i64(); | |
4143 | TCGv_i64 tcg_rd = cpu_reg(s, rd); | |
4144 | TCGv_i64 tcg_rn = read_cpu_reg(s, rn, sf); | |
4145 | ||
4146 | tcg_gen_andi_i64(tcg_shift, cpu_reg(s, rm), sf ? 63 : 31); | |
4147 | shift_reg(tcg_rd, tcg_rn, sf, shift_type, tcg_shift); | |
4148 | tcg_temp_free_i64(tcg_shift); | |
4149 | } | |
4150 | ||
130f2e7d PM |
4151 | /* CRC32[BHWX], CRC32C[BHWX] */ |
4152 | static void handle_crc32(DisasContext *s, | |
4153 | unsigned int sf, unsigned int sz, bool crc32c, | |
4154 | unsigned int rm, unsigned int rn, unsigned int rd) | |
4155 | { | |
4156 | TCGv_i64 tcg_acc, tcg_val; | |
4157 | TCGv_i32 tcg_bytes; | |
4158 | ||
4159 | if (!arm_dc_feature(s, ARM_FEATURE_CRC) | |
4160 | || (sf == 1 && sz != 3) | |
4161 | || (sf == 0 && sz == 3)) { | |
4162 | unallocated_encoding(s); | |
4163 | return; | |
4164 | } | |
4165 | ||
4166 | if (sz == 3) { | |
4167 | tcg_val = cpu_reg(s, rm); | |
4168 | } else { | |
4169 | uint64_t mask; | |
4170 | switch (sz) { | |
4171 | case 0: | |
4172 | mask = 0xFF; | |
4173 | break; | |
4174 | case 1: | |
4175 | mask = 0xFFFF; | |
4176 | break; | |
4177 | case 2: | |
4178 | mask = 0xFFFFFFFF; | |
4179 | break; | |
4180 | default: | |
4181 | g_assert_not_reached(); | |
4182 | } | |
4183 | tcg_val = new_tmp_a64(s); | |
4184 | tcg_gen_andi_i64(tcg_val, cpu_reg(s, rm), mask); | |
4185 | } | |
4186 | ||
4187 | tcg_acc = cpu_reg(s, rn); | |
4188 | tcg_bytes = tcg_const_i32(1 << sz); | |
4189 | ||
4190 | if (crc32c) { | |
4191 | gen_helper_crc32c_64(cpu_reg(s, rd), tcg_acc, tcg_val, tcg_bytes); | |
4192 | } else { | |
4193 | gen_helper_crc32_64(cpu_reg(s, rd), tcg_acc, tcg_val, tcg_bytes); | |
4194 | } | |
4195 | ||
4196 | tcg_temp_free_i32(tcg_bytes); | |
4197 | } | |
4198 | ||
8220e911 AG |
4199 | /* C3.5.8 Data-processing (2 source) |
4200 | * 31 30 29 28 21 20 16 15 10 9 5 4 0 | |
4201 | * +----+---+---+-----------------+------+--------+------+------+ | |
4202 | * | sf | 0 | S | 1 1 0 1 0 1 1 0 | Rm | opcode | Rn | Rd | | |
4203 | * +----+---+---+-----------------+------+--------+------+------+ | |
4204 | */ | |
ad7ee8a2 CF |
4205 | static void disas_data_proc_2src(DisasContext *s, uint32_t insn) |
4206 | { | |
8220e911 AG |
4207 | unsigned int sf, rm, opcode, rn, rd; |
4208 | sf = extract32(insn, 31, 1); | |
4209 | rm = extract32(insn, 16, 5); | |
4210 | opcode = extract32(insn, 10, 6); | |
4211 | rn = extract32(insn, 5, 5); | |
4212 | rd = extract32(insn, 0, 5); | |
4213 | ||
4214 | if (extract32(insn, 29, 1)) { | |
4215 | unallocated_encoding(s); | |
4216 | return; | |
4217 | } | |
4218 | ||
4219 | switch (opcode) { | |
4220 | case 2: /* UDIV */ | |
4221 | handle_div(s, false, sf, rm, rn, rd); | |
4222 | break; | |
4223 | case 3: /* SDIV */ | |
4224 | handle_div(s, true, sf, rm, rn, rd); | |
4225 | break; | |
4226 | case 8: /* LSLV */ | |
6c1adc91 AG |
4227 | handle_shift_reg(s, A64_SHIFT_TYPE_LSL, sf, rm, rn, rd); |
4228 | break; | |
8220e911 | 4229 | case 9: /* LSRV */ |
6c1adc91 AG |
4230 | handle_shift_reg(s, A64_SHIFT_TYPE_LSR, sf, rm, rn, rd); |
4231 | break; | |
8220e911 | 4232 | case 10: /* ASRV */ |
6c1adc91 AG |
4233 | handle_shift_reg(s, A64_SHIFT_TYPE_ASR, sf, rm, rn, rd); |
4234 | break; | |
8220e911 | 4235 | case 11: /* RORV */ |
6c1adc91 AG |
4236 | handle_shift_reg(s, A64_SHIFT_TYPE_ROR, sf, rm, rn, rd); |
4237 | break; | |
8220e911 AG |
4238 | case 16: |
4239 | case 17: | |
4240 | case 18: | |
4241 | case 19: | |
4242 | case 20: | |
4243 | case 21: | |
4244 | case 22: | |
4245 | case 23: /* CRC32 */ | |
130f2e7d PM |
4246 | { |
4247 | int sz = extract32(opcode, 0, 2); | |
4248 | bool crc32c = extract32(opcode, 2, 1); | |
4249 | handle_crc32(s, sf, sz, crc32c, rm, rn, rd); | |
8220e911 | 4250 | break; |
130f2e7d | 4251 | } |
8220e911 AG |
4252 | default: |
4253 | unallocated_encoding(s); | |
4254 | break; | |
4255 | } | |
ad7ee8a2 CF |
4256 | } |
4257 | ||
4258 | /* C3.5 Data processing - register */ | |
4259 | static void disas_data_proc_reg(DisasContext *s, uint32_t insn) | |
4260 | { | |
4261 | switch (extract32(insn, 24, 5)) { | |
4262 | case 0x0a: /* Logical (shifted register) */ | |
4263 | disas_logic_reg(s, insn); | |
4264 | break; | |
4265 | case 0x0b: /* Add/subtract */ | |
4266 | if (insn & (1 << 21)) { /* (extended register) */ | |
4267 | disas_add_sub_ext_reg(s, insn); | |
4268 | } else { | |
4269 | disas_add_sub_reg(s, insn); | |
4270 | } | |
4271 | break; | |
4272 | case 0x1b: /* Data-processing (3 source) */ | |
4273 | disas_data_proc_3src(s, insn); | |
4274 | break; | |
4275 | case 0x1a: | |
4276 | switch (extract32(insn, 21, 3)) { | |
4277 | case 0x0: /* Add/subtract (with carry) */ | |
4278 | disas_adc_sbc(s, insn); | |
4279 | break; | |
4280 | case 0x2: /* Conditional compare */ | |
750813cf | 4281 | disas_cc(s, insn); /* both imm and reg forms */ |
ad7ee8a2 CF |
4282 | break; |
4283 | case 0x4: /* Conditional select */ | |
4284 | disas_cond_select(s, insn); | |
4285 | break; | |
4286 | case 0x6: /* Data-processing */ | |
4287 | if (insn & (1 << 30)) { /* (1 source) */ | |
4288 | disas_data_proc_1src(s, insn); | |
4289 | } else { /* (2 source) */ | |
4290 | disas_data_proc_2src(s, insn); | |
4291 | } | |
4292 | break; | |
4293 | default: | |
4294 | unallocated_encoding(s); | |
4295 | break; | |
4296 | } | |
4297 | break; | |
4298 | default: | |
4299 | unallocated_encoding(s); | |
4300 | break; | |
4301 | } | |
4302 | } | |
4303 | ||
da7dafe7 CF |
4304 | static void handle_fp_compare(DisasContext *s, bool is_double, |
4305 | unsigned int rn, unsigned int rm, | |
4306 | bool cmp_with_zero, bool signal_all_nans) | |
4307 | { | |
4308 | TCGv_i64 tcg_flags = tcg_temp_new_i64(); | |
4309 | TCGv_ptr fpst = get_fpstatus_ptr(); | |
4310 | ||
4311 | if (is_double) { | |
4312 | TCGv_i64 tcg_vn, tcg_vm; | |
4313 | ||
4314 | tcg_vn = read_fp_dreg(s, rn); | |
4315 | if (cmp_with_zero) { | |
4316 | tcg_vm = tcg_const_i64(0); | |
4317 | } else { | |
4318 | tcg_vm = read_fp_dreg(s, rm); | |
4319 | } | |
4320 | if (signal_all_nans) { | |
4321 | gen_helper_vfp_cmped_a64(tcg_flags, tcg_vn, tcg_vm, fpst); | |
4322 | } else { | |
4323 | gen_helper_vfp_cmpd_a64(tcg_flags, tcg_vn, tcg_vm, fpst); | |
4324 | } | |
4325 | tcg_temp_free_i64(tcg_vn); | |
4326 | tcg_temp_free_i64(tcg_vm); | |
4327 | } else { | |
4328 | TCGv_i32 tcg_vn, tcg_vm; | |
4329 | ||
4330 | tcg_vn = read_fp_sreg(s, rn); | |
4331 | if (cmp_with_zero) { | |
4332 | tcg_vm = tcg_const_i32(0); | |
4333 | } else { | |
4334 | tcg_vm = read_fp_sreg(s, rm); | |
4335 | } | |
4336 | if (signal_all_nans) { | |
4337 | gen_helper_vfp_cmpes_a64(tcg_flags, tcg_vn, tcg_vm, fpst); | |
4338 | } else { | |
4339 | gen_helper_vfp_cmps_a64(tcg_flags, tcg_vn, tcg_vm, fpst); | |
4340 | } | |
4341 | tcg_temp_free_i32(tcg_vn); | |
4342 | tcg_temp_free_i32(tcg_vm); | |
4343 | } | |
4344 | ||
4345 | tcg_temp_free_ptr(fpst); | |
4346 | ||
4347 | gen_set_nzcv(tcg_flags); | |
4348 | ||
4349 | tcg_temp_free_i64(tcg_flags); | |
4350 | } | |
4351 | ||
faa0ba46 PM |
4352 | /* C3.6.22 Floating point compare |
4353 | * 31 30 29 28 24 23 22 21 20 16 15 14 13 10 9 5 4 0 | |
4354 | * +---+---+---+-----------+------+---+------+-----+---------+------+-------+ | |
4355 | * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | op | 1 0 0 0 | Rn | op2 | | |
4356 | * +---+---+---+-----------+------+---+------+-----+---------+------+-------+ | |
4357 | */ | |
4358 | static void disas_fp_compare(DisasContext *s, uint32_t insn) | |
4359 | { | |
da7dafe7 CF |
4360 | unsigned int mos, type, rm, op, rn, opc, op2r; |
4361 | ||
4362 | mos = extract32(insn, 29, 3); | |
4363 | type = extract32(insn, 22, 2); /* 0 = single, 1 = double */ | |
4364 | rm = extract32(insn, 16, 5); | |
4365 | op = extract32(insn, 14, 2); | |
4366 | rn = extract32(insn, 5, 5); | |
4367 | opc = extract32(insn, 3, 2); | |
4368 | op2r = extract32(insn, 0, 3); | |
4369 | ||
4370 | if (mos || op || op2r || type > 1) { | |
4371 | unallocated_encoding(s); | |
4372 | return; | |
4373 | } | |
4374 | ||
8c6afa6a PM |
4375 | if (!fp_access_check(s)) { |
4376 | return; | |
4377 | } | |
4378 | ||
da7dafe7 | 4379 | handle_fp_compare(s, type, rn, rm, opc & 1, opc & 2); |
faa0ba46 PM |
4380 | } |
4381 | ||
4382 | /* C3.6.23 Floating point conditional compare | |
4383 | * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0 | |
4384 | * +---+---+---+-----------+------+---+------+------+-----+------+----+------+ | |
4385 | * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 0 1 | Rn | op | nzcv | | |
4386 | * +---+---+---+-----------+------+---+------+------+-----+------+----+------+ | |
4387 | */ | |
4388 | static void disas_fp_ccomp(DisasContext *s, uint32_t insn) | |
4389 | { | |
513f1d76 CF |
4390 | unsigned int mos, type, rm, cond, rn, op, nzcv; |
4391 | TCGv_i64 tcg_flags; | |
42a268c2 | 4392 | TCGLabel *label_continue = NULL; |
513f1d76 CF |
4393 | |
4394 | mos = extract32(insn, 29, 3); | |
4395 | type = extract32(insn, 22, 2); /* 0 = single, 1 = double */ | |
4396 | rm = extract32(insn, 16, 5); | |
4397 | cond = extract32(insn, 12, 4); | |
4398 | rn = extract32(insn, 5, 5); | |
4399 | op = extract32(insn, 4, 1); | |
4400 | nzcv = extract32(insn, 0, 4); | |
4401 | ||
4402 | if (mos || type > 1) { | |
4403 | unallocated_encoding(s); | |
4404 | return; | |
4405 | } | |
4406 | ||
8c6afa6a PM |
4407 | if (!fp_access_check(s)) { |
4408 | return; | |
4409 | } | |
4410 | ||
513f1d76 | 4411 | if (cond < 0x0e) { /* not always */ |
42a268c2 | 4412 | TCGLabel *label_match = gen_new_label(); |
513f1d76 CF |
4413 | label_continue = gen_new_label(); |
4414 | arm_gen_test_cc(cond, label_match); | |
4415 | /* nomatch: */ | |
4416 | tcg_flags = tcg_const_i64(nzcv << 28); | |
4417 | gen_set_nzcv(tcg_flags); | |
4418 | tcg_temp_free_i64(tcg_flags); | |
4419 | tcg_gen_br(label_continue); | |
4420 | gen_set_label(label_match); | |
4421 | } | |
4422 | ||
4423 | handle_fp_compare(s, type, rn, rm, false, op); | |
4424 | ||
4425 | if (cond < 0x0e) { | |
4426 | gen_set_label(label_continue); | |
4427 | } | |
faa0ba46 PM |
4428 | } |
4429 | ||
4430 | /* C3.6.24 Floating point conditional select | |
4431 | * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0 | |
4432 | * +---+---+---+-----------+------+---+------+------+-----+------+------+ | |
4433 | * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 1 1 | Rn | Rd | | |
4434 | * +---+---+---+-----------+------+---+------+------+-----+------+------+ | |
4435 | */ | |
4436 | static void disas_fp_csel(DisasContext *s, uint32_t insn) | |
4437 | { | |
5640ff62 | 4438 | unsigned int mos, type, rm, cond, rn, rd; |
6e061029 RH |
4439 | TCGv_i64 t_true, t_false, t_zero; |
4440 | DisasCompare64 c; | |
5640ff62 CF |
4441 | |
4442 | mos = extract32(insn, 29, 3); | |
4443 | type = extract32(insn, 22, 2); /* 0 = single, 1 = double */ | |
4444 | rm = extract32(insn, 16, 5); | |
4445 | cond = extract32(insn, 12, 4); | |
4446 | rn = extract32(insn, 5, 5); | |
4447 | rd = extract32(insn, 0, 5); | |
4448 | ||
4449 | if (mos || type > 1) { | |
4450 | unallocated_encoding(s); | |
4451 | return; | |
4452 | } | |
4453 | ||
8c6afa6a PM |
4454 | if (!fp_access_check(s)) { |
4455 | return; | |
4456 | } | |
4457 | ||
6e061029 RH |
4458 | /* Zero extend sreg inputs to 64 bits now. */ |
4459 | t_true = tcg_temp_new_i64(); | |
4460 | t_false = tcg_temp_new_i64(); | |
4461 | read_vec_element(s, t_true, rn, 0, type ? MO_64 : MO_32); | |
4462 | read_vec_element(s, t_false, rm, 0, type ? MO_64 : MO_32); | |
5640ff62 | 4463 | |
6e061029 RH |
4464 | a64_test_cc(&c, cond); |
4465 | t_zero = tcg_const_i64(0); | |
4466 | tcg_gen_movcond_i64(c.cond, t_true, c.value, t_zero, t_true, t_false); | |
4467 | tcg_temp_free_i64(t_zero); | |
4468 | tcg_temp_free_i64(t_false); | |
4469 | a64_free_cc(&c); | |
5640ff62 | 4470 | |
6e061029 RH |
4471 | /* Note that sregs write back zeros to the high bits, |
4472 | and we've already done the zero-extension. */ | |
4473 | write_fp_dreg(s, rd, t_true); | |
4474 | tcg_temp_free_i64(t_true); | |
faa0ba46 PM |
4475 | } |
4476 | ||
d9b0848d PM |
4477 | /* C3.6.25 Floating-point data-processing (1 source) - single precision */ |
4478 | static void handle_fp_1src_single(DisasContext *s, int opcode, int rd, int rn) | |
4479 | { | |
4480 | TCGv_ptr fpst; | |
4481 | TCGv_i32 tcg_op; | |
4482 | TCGv_i32 tcg_res; | |
4483 | ||
4484 | fpst = get_fpstatus_ptr(); | |
4485 | tcg_op = read_fp_sreg(s, rn); | |
4486 | tcg_res = tcg_temp_new_i32(); | |
4487 | ||
4488 | switch (opcode) { | |
4489 | case 0x0: /* FMOV */ | |
4490 | tcg_gen_mov_i32(tcg_res, tcg_op); | |
4491 | break; | |
4492 | case 0x1: /* FABS */ | |
4493 | gen_helper_vfp_abss(tcg_res, tcg_op); | |
4494 | break; | |
4495 | case 0x2: /* FNEG */ | |
4496 | gen_helper_vfp_negs(tcg_res, tcg_op); | |
4497 | break; | |
4498 | case 0x3: /* FSQRT */ | |
4499 | gen_helper_vfp_sqrts(tcg_res, tcg_op, cpu_env); | |
4500 | break; | |
4501 | case 0x8: /* FRINTN */ | |
4502 | case 0x9: /* FRINTP */ | |
4503 | case 0xa: /* FRINTM */ | |
4504 | case 0xb: /* FRINTZ */ | |
4505 | case 0xc: /* FRINTA */ | |
4506 | { | |
4507 | TCGv_i32 tcg_rmode = tcg_const_i32(arm_rmode_to_sf(opcode & 7)); | |
4508 | ||
4509 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); | |
4510 | gen_helper_rints(tcg_res, tcg_op, fpst); | |
4511 | ||
4512 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); | |
4513 | tcg_temp_free_i32(tcg_rmode); | |
4514 | break; | |
4515 | } | |
4516 | case 0xe: /* FRINTX */ | |
4517 | gen_helper_rints_exact(tcg_res, tcg_op, fpst); | |
4518 | break; | |
4519 | case 0xf: /* FRINTI */ | |
4520 | gen_helper_rints(tcg_res, tcg_op, fpst); | |
4521 | break; | |
4522 | default: | |
4523 | abort(); | |
4524 | } | |
4525 | ||
4526 | write_fp_sreg(s, rd, tcg_res); | |
4527 | ||
4528 | tcg_temp_free_ptr(fpst); | |
4529 | tcg_temp_free_i32(tcg_op); | |
4530 | tcg_temp_free_i32(tcg_res); | |
4531 | } | |
4532 | ||
4533 | /* C3.6.25 Floating-point data-processing (1 source) - double precision */ | |
4534 | static void handle_fp_1src_double(DisasContext *s, int opcode, int rd, int rn) | |
4535 | { | |
4536 | TCGv_ptr fpst; | |
4537 | TCGv_i64 tcg_op; | |
4538 | TCGv_i64 tcg_res; | |
4539 | ||
4540 | fpst = get_fpstatus_ptr(); | |
4541 | tcg_op = read_fp_dreg(s, rn); | |
4542 | tcg_res = tcg_temp_new_i64(); | |
4543 | ||
4544 | switch (opcode) { | |
4545 | case 0x0: /* FMOV */ | |
4546 | tcg_gen_mov_i64(tcg_res, tcg_op); | |
4547 | break; | |
4548 | case 0x1: /* FABS */ | |
4549 | gen_helper_vfp_absd(tcg_res, tcg_op); | |
4550 | break; | |
4551 | case 0x2: /* FNEG */ | |
4552 | gen_helper_vfp_negd(tcg_res, tcg_op); | |
4553 | break; | |
4554 | case 0x3: /* FSQRT */ | |
4555 | gen_helper_vfp_sqrtd(tcg_res, tcg_op, cpu_env); | |
4556 | break; | |
4557 | case 0x8: /* FRINTN */ | |
4558 | case 0x9: /* FRINTP */ | |
4559 | case 0xa: /* FRINTM */ | |
4560 | case 0xb: /* FRINTZ */ | |
4561 | case 0xc: /* FRINTA */ | |
4562 | { | |
4563 | TCGv_i32 tcg_rmode = tcg_const_i32(arm_rmode_to_sf(opcode & 7)); | |
4564 | ||
4565 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); | |
4566 | gen_helper_rintd(tcg_res, tcg_op, fpst); | |
4567 | ||
4568 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); | |
4569 | tcg_temp_free_i32(tcg_rmode); | |
4570 | break; | |
4571 | } | |
4572 | case 0xe: /* FRINTX */ | |
4573 | gen_helper_rintd_exact(tcg_res, tcg_op, fpst); | |
4574 | break; | |
4575 | case 0xf: /* FRINTI */ | |
4576 | gen_helper_rintd(tcg_res, tcg_op, fpst); | |
4577 | break; | |
4578 | default: | |
4579 | abort(); | |
4580 | } | |
4581 | ||
4582 | write_fp_dreg(s, rd, tcg_res); | |
4583 | ||
4584 | tcg_temp_free_ptr(fpst); | |
4585 | tcg_temp_free_i64(tcg_op); | |
4586 | tcg_temp_free_i64(tcg_res); | |
4587 | } | |
4588 | ||
8900aad2 PM |
4589 | static void handle_fp_fcvt(DisasContext *s, int opcode, |
4590 | int rd, int rn, int dtype, int ntype) | |
4591 | { | |
4592 | switch (ntype) { | |
4593 | case 0x0: | |
4594 | { | |
4595 | TCGv_i32 tcg_rn = read_fp_sreg(s, rn); | |
4596 | if (dtype == 1) { | |
4597 | /* Single to double */ | |
4598 | TCGv_i64 tcg_rd = tcg_temp_new_i64(); | |
4599 | gen_helper_vfp_fcvtds(tcg_rd, tcg_rn, cpu_env); | |
4600 | write_fp_dreg(s, rd, tcg_rd); | |
4601 | tcg_temp_free_i64(tcg_rd); | |
4602 | } else { | |
4603 | /* Single to half */ | |
4604 | TCGv_i32 tcg_rd = tcg_temp_new_i32(); | |
4605 | gen_helper_vfp_fcvt_f32_to_f16(tcg_rd, tcg_rn, cpu_env); | |
4606 | /* write_fp_sreg is OK here because top half of tcg_rd is zero */ | |
4607 | write_fp_sreg(s, rd, tcg_rd); | |
4608 | tcg_temp_free_i32(tcg_rd); | |
4609 | } | |
4610 | tcg_temp_free_i32(tcg_rn); | |
4611 | break; | |
4612 | } | |
4613 | case 0x1: | |
4614 | { | |
4615 | TCGv_i64 tcg_rn = read_fp_dreg(s, rn); | |
4616 | TCGv_i32 tcg_rd = tcg_temp_new_i32(); | |
4617 | if (dtype == 0) { | |
4618 | /* Double to single */ | |
4619 | gen_helper_vfp_fcvtsd(tcg_rd, tcg_rn, cpu_env); | |
4620 | } else { | |
4621 | /* Double to half */ | |
4622 | gen_helper_vfp_fcvt_f64_to_f16(tcg_rd, tcg_rn, cpu_env); | |
4623 | /* write_fp_sreg is OK here because top half of tcg_rd is zero */ | |
4624 | } | |
4625 | write_fp_sreg(s, rd, tcg_rd); | |
4626 | tcg_temp_free_i32(tcg_rd); | |
4627 | tcg_temp_free_i64(tcg_rn); | |
4628 | break; | |
4629 | } | |
4630 | case 0x3: | |
4631 | { | |
4632 | TCGv_i32 tcg_rn = read_fp_sreg(s, rn); | |
4633 | tcg_gen_ext16u_i32(tcg_rn, tcg_rn); | |
4634 | if (dtype == 0) { | |
4635 | /* Half to single */ | |
4636 | TCGv_i32 tcg_rd = tcg_temp_new_i32(); | |
4637 | gen_helper_vfp_fcvt_f16_to_f32(tcg_rd, tcg_rn, cpu_env); | |
4638 | write_fp_sreg(s, rd, tcg_rd); | |
4639 | tcg_temp_free_i32(tcg_rd); | |
4640 | } else { | |
4641 | /* Half to double */ | |
4642 | TCGv_i64 tcg_rd = tcg_temp_new_i64(); | |
4643 | gen_helper_vfp_fcvt_f16_to_f64(tcg_rd, tcg_rn, cpu_env); | |
4644 | write_fp_dreg(s, rd, tcg_rd); | |
4645 | tcg_temp_free_i64(tcg_rd); | |
4646 | } | |
4647 | tcg_temp_free_i32(tcg_rn); | |
4648 | break; | |
4649 | } | |
4650 | default: | |
4651 | abort(); | |
4652 | } | |
4653 | } | |
4654 | ||
faa0ba46 PM |
4655 | /* C3.6.25 Floating point data-processing (1 source) |
4656 | * 31 30 29 28 24 23 22 21 20 15 14 10 9 5 4 0 | |
4657 | * +---+---+---+-----------+------+---+--------+-----------+------+------+ | |
4658 | * | M | 0 | S | 1 1 1 1 0 | type | 1 | opcode | 1 0 0 0 0 | Rn | Rd | | |
4659 | * +---+---+---+-----------+------+---+--------+-----------+------+------+ | |
4660 | */ | |
4661 | static void disas_fp_1src(DisasContext *s, uint32_t insn) | |
4662 | { | |
d9b0848d PM |
4663 | int type = extract32(insn, 22, 2); |
4664 | int opcode = extract32(insn, 15, 6); | |
4665 | int rn = extract32(insn, 5, 5); | |
4666 | int rd = extract32(insn, 0, 5); | |
4667 | ||
4668 | switch (opcode) { | |
4669 | case 0x4: case 0x5: case 0x7: | |
8900aad2 | 4670 | { |
d9b0848d | 4671 | /* FCVT between half, single and double precision */ |
8900aad2 PM |
4672 | int dtype = extract32(opcode, 0, 2); |
4673 | if (type == 2 || dtype == type) { | |
4674 | unallocated_encoding(s); | |
4675 | return; | |
4676 | } | |
8c6afa6a PM |
4677 | if (!fp_access_check(s)) { |
4678 | return; | |
4679 | } | |
4680 | ||
8900aad2 | 4681 | handle_fp_fcvt(s, opcode, rd, rn, dtype, type); |
d9b0848d | 4682 | break; |
8900aad2 | 4683 | } |
d9b0848d PM |
4684 | case 0x0 ... 0x3: |
4685 | case 0x8 ... 0xc: | |
4686 | case 0xe ... 0xf: | |
4687 | /* 32-to-32 and 64-to-64 ops */ | |
4688 | switch (type) { | |
4689 | case 0: | |
8c6afa6a PM |
4690 | if (!fp_access_check(s)) { |
4691 | return; | |
4692 | } | |
4693 | ||
d9b0848d PM |
4694 | handle_fp_1src_single(s, opcode, rd, rn); |
4695 | break; | |
4696 | case 1: | |
8c6afa6a PM |
4697 | if (!fp_access_check(s)) { |
4698 | return; | |
4699 | } | |
4700 | ||
d9b0848d PM |
4701 | handle_fp_1src_double(s, opcode, rd, rn); |
4702 | break; | |
4703 | default: | |
4704 | unallocated_encoding(s); | |
4705 | } | |
4706 | break; | |
4707 | default: | |
4708 | unallocated_encoding(s); | |
4709 | break; | |
4710 | } | |
faa0ba46 PM |
4711 | } |
4712 | ||
ec73d2e0 AG |
4713 | /* C3.6.26 Floating-point data-processing (2 source) - single precision */ |
4714 | static void handle_fp_2src_single(DisasContext *s, int opcode, | |
4715 | int rd, int rn, int rm) | |
4716 | { | |
4717 | TCGv_i32 tcg_op1; | |
4718 | TCGv_i32 tcg_op2; | |
4719 | TCGv_i32 tcg_res; | |
4720 | TCGv_ptr fpst; | |
4721 | ||
4722 | tcg_res = tcg_temp_new_i32(); | |
4723 | fpst = get_fpstatus_ptr(); | |
4724 | tcg_op1 = read_fp_sreg(s, rn); | |
4725 | tcg_op2 = read_fp_sreg(s, rm); | |
4726 | ||
4727 | switch (opcode) { | |
4728 | case 0x0: /* FMUL */ | |
4729 | gen_helper_vfp_muls(tcg_res, tcg_op1, tcg_op2, fpst); | |
4730 | break; | |
4731 | case 0x1: /* FDIV */ | |
4732 | gen_helper_vfp_divs(tcg_res, tcg_op1, tcg_op2, fpst); | |
4733 | break; | |
4734 | case 0x2: /* FADD */ | |
4735 | gen_helper_vfp_adds(tcg_res, tcg_op1, tcg_op2, fpst); | |
4736 | break; | |
4737 | case 0x3: /* FSUB */ | |
4738 | gen_helper_vfp_subs(tcg_res, tcg_op1, tcg_op2, fpst); | |
4739 | break; | |
4740 | case 0x4: /* FMAX */ | |
4741 | gen_helper_vfp_maxs(tcg_res, tcg_op1, tcg_op2, fpst); | |
4742 | break; | |
4743 | case 0x5: /* FMIN */ | |
4744 | gen_helper_vfp_mins(tcg_res, tcg_op1, tcg_op2, fpst); | |
4745 | break; | |
4746 | case 0x6: /* FMAXNM */ | |
4747 | gen_helper_vfp_maxnums(tcg_res, tcg_op1, tcg_op2, fpst); | |
4748 | break; | |
4749 | case 0x7: /* FMINNM */ | |
4750 | gen_helper_vfp_minnums(tcg_res, tcg_op1, tcg_op2, fpst); | |
4751 | break; | |
4752 | case 0x8: /* FNMUL */ | |
4753 | gen_helper_vfp_muls(tcg_res, tcg_op1, tcg_op2, fpst); | |
4754 | gen_helper_vfp_negs(tcg_res, tcg_res); | |
4755 | break; | |
4756 | } | |
4757 | ||
4758 | write_fp_sreg(s, rd, tcg_res); | |
4759 | ||
4760 | tcg_temp_free_ptr(fpst); | |
4761 | tcg_temp_free_i32(tcg_op1); | |
4762 | tcg_temp_free_i32(tcg_op2); | |
4763 | tcg_temp_free_i32(tcg_res); | |
4764 | } | |
4765 | ||
4766 | /* C3.6.26 Floating-point data-processing (2 source) - double precision */ | |
4767 | static void handle_fp_2src_double(DisasContext *s, int opcode, | |
4768 | int rd, int rn, int rm) | |
4769 | { | |
4770 | TCGv_i64 tcg_op1; | |
4771 | TCGv_i64 tcg_op2; | |
4772 | TCGv_i64 tcg_res; | |
4773 | TCGv_ptr fpst; | |
4774 | ||
4775 | tcg_res = tcg_temp_new_i64(); | |
4776 | fpst = get_fpstatus_ptr(); | |
4777 | tcg_op1 = read_fp_dreg(s, rn); | |
4778 | tcg_op2 = read_fp_dreg(s, rm); | |
4779 | ||
4780 | switch (opcode) { | |
4781 | case 0x0: /* FMUL */ | |
4782 | gen_helper_vfp_muld(tcg_res, tcg_op1, tcg_op2, fpst); | |
4783 | break; | |
4784 | case 0x1: /* FDIV */ | |
4785 | gen_helper_vfp_divd(tcg_res, tcg_op1, tcg_op2, fpst); | |
4786 | break; | |
4787 | case 0x2: /* FADD */ | |
4788 | gen_helper_vfp_addd(tcg_res, tcg_op1, tcg_op2, fpst); | |
4789 | break; | |
4790 | case 0x3: /* FSUB */ | |
4791 | gen_helper_vfp_subd(tcg_res, tcg_op1, tcg_op2, fpst); | |
4792 | break; | |
4793 | case 0x4: /* FMAX */ | |
4794 | gen_helper_vfp_maxd(tcg_res, tcg_op1, tcg_op2, fpst); | |
4795 | break; | |
4796 | case 0x5: /* FMIN */ | |
4797 | gen_helper_vfp_mind(tcg_res, tcg_op1, tcg_op2, fpst); | |
4798 | break; | |
4799 | case 0x6: /* FMAXNM */ | |
4800 | gen_helper_vfp_maxnumd(tcg_res, tcg_op1, tcg_op2, fpst); | |
4801 | break; | |
4802 | case 0x7: /* FMINNM */ | |
4803 | gen_helper_vfp_minnumd(tcg_res, tcg_op1, tcg_op2, fpst); | |
4804 | break; | |
4805 | case 0x8: /* FNMUL */ | |
4806 | gen_helper_vfp_muld(tcg_res, tcg_op1, tcg_op2, fpst); | |
4807 | gen_helper_vfp_negd(tcg_res, tcg_res); | |
4808 | break; | |
4809 | } | |
4810 | ||
4811 | write_fp_dreg(s, rd, tcg_res); | |
4812 | ||
4813 | tcg_temp_free_ptr(fpst); | |
4814 | tcg_temp_free_i64(tcg_op1); | |
4815 | tcg_temp_free_i64(tcg_op2); | |
4816 | tcg_temp_free_i64(tcg_res); | |
4817 | } | |
4818 | ||
faa0ba46 PM |
4819 | /* C3.6.26 Floating point data-processing (2 source) |
4820 | * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0 | |
4821 | * +---+---+---+-----------+------+---+------+--------+-----+------+------+ | |
4822 | * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | opcode | 1 0 | Rn | Rd | | |
4823 | * +---+---+---+-----------+------+---+------+--------+-----+------+------+ | |
4824 | */ | |
4825 | static void disas_fp_2src(DisasContext *s, uint32_t insn) | |
4826 | { | |
ec73d2e0 AG |
4827 | int type = extract32(insn, 22, 2); |
4828 | int rd = extract32(insn, 0, 5); | |
4829 | int rn = extract32(insn, 5, 5); | |
4830 | int rm = extract32(insn, 16, 5); | |
4831 | int opcode = extract32(insn, 12, 4); | |
4832 | ||
4833 | if (opcode > 8) { | |
4834 | unallocated_encoding(s); | |
4835 | return; | |
4836 | } | |
4837 | ||
4838 | switch (type) { | |
4839 | case 0: | |
8c6afa6a PM |
4840 | if (!fp_access_check(s)) { |
4841 | return; | |
4842 | } | |
ec73d2e0 AG |
4843 | handle_fp_2src_single(s, opcode, rd, rn, rm); |
4844 | break; | |
4845 | case 1: | |
8c6afa6a PM |
4846 | if (!fp_access_check(s)) { |
4847 | return; | |
4848 | } | |
ec73d2e0 AG |
4849 | handle_fp_2src_double(s, opcode, rd, rn, rm); |
4850 | break; | |
4851 | default: | |
4852 | unallocated_encoding(s); | |
4853 | } | |
faa0ba46 PM |
4854 | } |
4855 | ||
6a30667f AG |
4856 | /* C3.6.27 Floating-point data-processing (3 source) - single precision */ |
4857 | static void handle_fp_3src_single(DisasContext *s, bool o0, bool o1, | |
4858 | int rd, int rn, int rm, int ra) | |
4859 | { | |
4860 | TCGv_i32 tcg_op1, tcg_op2, tcg_op3; | |
4861 | TCGv_i32 tcg_res = tcg_temp_new_i32(); | |
4862 | TCGv_ptr fpst = get_fpstatus_ptr(); | |
4863 | ||
4864 | tcg_op1 = read_fp_sreg(s, rn); | |
4865 | tcg_op2 = read_fp_sreg(s, rm); | |
4866 | tcg_op3 = read_fp_sreg(s, ra); | |
4867 | ||
4868 | /* These are fused multiply-add, and must be done as one | |
4869 | * floating point operation with no rounding between the | |
4870 | * multiplication and addition steps. | |
4871 | * NB that doing the negations here as separate steps is | |
4872 | * correct : an input NaN should come out with its sign bit | |
4873 | * flipped if it is a negated-input. | |
4874 | */ | |
4875 | if (o1 == true) { | |
4876 | gen_helper_vfp_negs(tcg_op3, tcg_op3); | |
4877 | } | |
4878 | ||
4879 | if (o0 != o1) { | |
4880 | gen_helper_vfp_negs(tcg_op1, tcg_op1); | |
4881 | } | |
4882 | ||
4883 | gen_helper_vfp_muladds(tcg_res, tcg_op1, tcg_op2, tcg_op3, fpst); | |
4884 | ||
4885 | write_fp_sreg(s, rd, tcg_res); | |
4886 | ||
4887 | tcg_temp_free_ptr(fpst); | |
4888 | tcg_temp_free_i32(tcg_op1); | |
4889 | tcg_temp_free_i32(tcg_op2); | |
4890 | tcg_temp_free_i32(tcg_op3); | |
4891 | tcg_temp_free_i32(tcg_res); | |
4892 | } | |
4893 | ||
4894 | /* C3.6.27 Floating-point data-processing (3 source) - double precision */ | |
4895 | static void handle_fp_3src_double(DisasContext *s, bool o0, bool o1, | |
4896 | int rd, int rn, int rm, int ra) | |
4897 | { | |
4898 | TCGv_i64 tcg_op1, tcg_op2, tcg_op3; | |
4899 | TCGv_i64 tcg_res = tcg_temp_new_i64(); | |
4900 | TCGv_ptr fpst = get_fpstatus_ptr(); | |
4901 | ||
4902 | tcg_op1 = read_fp_dreg(s, rn); | |
4903 | tcg_op2 = read_fp_dreg(s, rm); | |
4904 | tcg_op3 = read_fp_dreg(s, ra); | |
4905 | ||
4906 | /* These are fused multiply-add, and must be done as one | |
4907 | * floating point operation with no rounding between the | |
4908 | * multiplication and addition steps. | |
4909 | * NB that doing the negations here as separate steps is | |
4910 | * correct : an input NaN should come out with its sign bit | |
4911 | * flipped if it is a negated-input. | |
4912 | */ | |
4913 | if (o1 == true) { | |
4914 | gen_helper_vfp_negd(tcg_op3, tcg_op3); | |
4915 | } | |
4916 | ||
4917 | if (o0 != o1) { | |
4918 | gen_helper_vfp_negd(tcg_op1, tcg_op1); | |
4919 | } | |
4920 | ||
4921 | gen_helper_vfp_muladdd(tcg_res, tcg_op1, tcg_op2, tcg_op3, fpst); | |
4922 | ||
4923 | write_fp_dreg(s, rd, tcg_res); | |
4924 | ||
4925 | tcg_temp_free_ptr(fpst); | |
4926 | tcg_temp_free_i64(tcg_op1); | |
4927 | tcg_temp_free_i64(tcg_op2); | |
4928 | tcg_temp_free_i64(tcg_op3); | |
4929 | tcg_temp_free_i64(tcg_res); | |
4930 | } | |
4931 | ||
faa0ba46 PM |
4932 | /* C3.6.27 Floating point data-processing (3 source) |
4933 | * 31 30 29 28 24 23 22 21 20 16 15 14 10 9 5 4 0 | |
4934 | * +---+---+---+-----------+------+----+------+----+------+------+------+ | |
4935 | * | M | 0 | S | 1 1 1 1 1 | type | o1 | Rm | o0 | Ra | Rn | Rd | | |
4936 | * +---+---+---+-----------+------+----+------+----+------+------+------+ | |
4937 | */ | |
4938 | static void disas_fp_3src(DisasContext *s, uint32_t insn) | |
4939 | { | |
6a30667f AG |
4940 | int type = extract32(insn, 22, 2); |
4941 | int rd = extract32(insn, 0, 5); | |
4942 | int rn = extract32(insn, 5, 5); | |
4943 | int ra = extract32(insn, 10, 5); | |
4944 | int rm = extract32(insn, 16, 5); | |
4945 | bool o0 = extract32(insn, 15, 1); | |
4946 | bool o1 = extract32(insn, 21, 1); | |
4947 | ||
4948 | switch (type) { | |
4949 | case 0: | |
8c6afa6a PM |
4950 | if (!fp_access_check(s)) { |
4951 | return; | |
4952 | } | |
6a30667f AG |
4953 | handle_fp_3src_single(s, o0, o1, rd, rn, rm, ra); |
4954 | break; | |
4955 | case 1: | |
8c6afa6a PM |
4956 | if (!fp_access_check(s)) { |
4957 | return; | |
4958 | } | |
6a30667f AG |
4959 | handle_fp_3src_double(s, o0, o1, rd, rn, rm, ra); |
4960 | break; | |
4961 | default: | |
4962 | unallocated_encoding(s); | |
4963 | } | |
faa0ba46 PM |
4964 | } |
4965 | ||
4966 | /* C3.6.28 Floating point immediate | |
4967 | * 31 30 29 28 24 23 22 21 20 13 12 10 9 5 4 0 | |
4968 | * +---+---+---+-----------+------+---+------------+-------+------+------+ | |
4969 | * | M | 0 | S | 1 1 1 1 0 | type | 1 | imm8 | 1 0 0 | imm5 | Rd | | |
4970 | * +---+---+---+-----------+------+---+------------+-------+------+------+ | |
4971 | */ | |
4972 | static void disas_fp_imm(DisasContext *s, uint32_t insn) | |
4973 | { | |
6163f868 AG |
4974 | int rd = extract32(insn, 0, 5); |
4975 | int imm8 = extract32(insn, 13, 8); | |
4976 | int is_double = extract32(insn, 22, 2); | |
4977 | uint64_t imm; | |
4978 | TCGv_i64 tcg_res; | |
4979 | ||
4980 | if (is_double > 1) { | |
4981 | unallocated_encoding(s); | |
4982 | return; | |
4983 | } | |
4984 | ||
8c6afa6a PM |
4985 | if (!fp_access_check(s)) { |
4986 | return; | |
4987 | } | |
4988 | ||
6163f868 AG |
4989 | /* The imm8 encodes the sign bit, enough bits to represent |
4990 | * an exponent in the range 01....1xx to 10....0xx, | |
4991 | * and the most significant 4 bits of the mantissa; see | |
4992 | * VFPExpandImm() in the v8 ARM ARM. | |
4993 | */ | |
4994 | if (is_double) { | |
4995 | imm = (extract32(imm8, 7, 1) ? 0x8000 : 0) | | |
4996 | (extract32(imm8, 6, 1) ? 0x3fc0 : 0x4000) | | |
4997 | extract32(imm8, 0, 6); | |
4998 | imm <<= 48; | |
4999 | } else { | |
5000 | imm = (extract32(imm8, 7, 1) ? 0x8000 : 0) | | |
5001 | (extract32(imm8, 6, 1) ? 0x3e00 : 0x4000) | | |
5002 | (extract32(imm8, 0, 6) << 3); | |
5003 | imm <<= 16; | |
5004 | } | |
5005 | ||
5006 | tcg_res = tcg_const_i64(imm); | |
5007 | write_fp_dreg(s, rd, tcg_res); | |
5008 | tcg_temp_free_i64(tcg_res); | |
faa0ba46 PM |
5009 | } |
5010 | ||
52a1f6a3 AG |
5011 | /* Handle floating point <=> fixed point conversions. Note that we can |
5012 | * also deal with fp <=> integer conversions as a special case (scale == 64) | |
5013 | * OPTME: consider handling that special case specially or at least skipping | |
5014 | * the call to scalbn in the helpers for zero shifts. | |
5015 | */ | |
5016 | static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode, | |
5017 | bool itof, int rmode, int scale, int sf, int type) | |
5018 | { | |
5019 | bool is_signed = !(opcode & 1); | |
5020 | bool is_double = type; | |
5021 | TCGv_ptr tcg_fpstatus; | |
5022 | TCGv_i32 tcg_shift; | |
5023 | ||
5024 | tcg_fpstatus = get_fpstatus_ptr(); | |
5025 | ||
5026 | tcg_shift = tcg_const_i32(64 - scale); | |
5027 | ||
5028 | if (itof) { | |
5029 | TCGv_i64 tcg_int = cpu_reg(s, rn); | |
5030 | if (!sf) { | |
5031 | TCGv_i64 tcg_extend = new_tmp_a64(s); | |
5032 | ||
5033 | if (is_signed) { | |
5034 | tcg_gen_ext32s_i64(tcg_extend, tcg_int); | |
5035 | } else { | |
5036 | tcg_gen_ext32u_i64(tcg_extend, tcg_int); | |
5037 | } | |
5038 | ||
5039 | tcg_int = tcg_extend; | |
5040 | } | |
5041 | ||
5042 | if (is_double) { | |
5043 | TCGv_i64 tcg_double = tcg_temp_new_i64(); | |
5044 | if (is_signed) { | |
5045 | gen_helper_vfp_sqtod(tcg_double, tcg_int, | |
5046 | tcg_shift, tcg_fpstatus); | |
5047 | } else { | |
5048 | gen_helper_vfp_uqtod(tcg_double, tcg_int, | |
5049 | tcg_shift, tcg_fpstatus); | |
5050 | } | |
5051 | write_fp_dreg(s, rd, tcg_double); | |
5052 | tcg_temp_free_i64(tcg_double); | |
5053 | } else { | |
5054 | TCGv_i32 tcg_single = tcg_temp_new_i32(); | |
5055 | if (is_signed) { | |
5056 | gen_helper_vfp_sqtos(tcg_single, tcg_int, | |
5057 | tcg_shift, tcg_fpstatus); | |
5058 | } else { | |
5059 | gen_helper_vfp_uqtos(tcg_single, tcg_int, | |
5060 | tcg_shift, tcg_fpstatus); | |
5061 | } | |
5062 | write_fp_sreg(s, rd, tcg_single); | |
5063 | tcg_temp_free_i32(tcg_single); | |
5064 | } | |
5065 | } else { | |
5066 | TCGv_i64 tcg_int = cpu_reg(s, rd); | |
5067 | TCGv_i32 tcg_rmode; | |
5068 | ||
5069 | if (extract32(opcode, 2, 1)) { | |
5070 | /* There are too many rounding modes to all fit into rmode, | |
5071 | * so FCVTA[US] is a special case. | |
5072 | */ | |
5073 | rmode = FPROUNDING_TIEAWAY; | |
5074 | } | |
5075 | ||
5076 | tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode)); | |
5077 | ||
5078 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); | |
5079 | ||
5080 | if (is_double) { | |
5081 | TCGv_i64 tcg_double = read_fp_dreg(s, rn); | |
5082 | if (is_signed) { | |
5083 | if (!sf) { | |
5084 | gen_helper_vfp_tosld(tcg_int, tcg_double, | |
5085 | tcg_shift, tcg_fpstatus); | |
5086 | } else { | |
5087 | gen_helper_vfp_tosqd(tcg_int, tcg_double, | |
5088 | tcg_shift, tcg_fpstatus); | |
5089 | } | |
5090 | } else { | |
5091 | if (!sf) { | |
5092 | gen_helper_vfp_tould(tcg_int, tcg_double, | |
5093 | tcg_shift, tcg_fpstatus); | |
5094 | } else { | |
5095 | gen_helper_vfp_touqd(tcg_int, tcg_double, | |
5096 | tcg_shift, tcg_fpstatus); | |
5097 | } | |
5098 | } | |
5099 | tcg_temp_free_i64(tcg_double); | |
5100 | } else { | |
5101 | TCGv_i32 tcg_single = read_fp_sreg(s, rn); | |
5102 | if (sf) { | |
5103 | if (is_signed) { | |
5104 | gen_helper_vfp_tosqs(tcg_int, tcg_single, | |
5105 | tcg_shift, tcg_fpstatus); | |
5106 | } else { | |
5107 | gen_helper_vfp_touqs(tcg_int, tcg_single, | |
5108 | tcg_shift, tcg_fpstatus); | |
5109 | } | |
5110 | } else { | |
5111 | TCGv_i32 tcg_dest = tcg_temp_new_i32(); | |
5112 | if (is_signed) { | |
5113 | gen_helper_vfp_tosls(tcg_dest, tcg_single, | |
5114 | tcg_shift, tcg_fpstatus); | |
5115 | } else { | |
5116 | gen_helper_vfp_touls(tcg_dest, tcg_single, | |
5117 | tcg_shift, tcg_fpstatus); | |
5118 | } | |
5119 | tcg_gen_extu_i32_i64(tcg_int, tcg_dest); | |
5120 | tcg_temp_free_i32(tcg_dest); | |
5121 | } | |
5122 | tcg_temp_free_i32(tcg_single); | |
5123 | } | |
5124 | ||
5125 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); | |
5126 | tcg_temp_free_i32(tcg_rmode); | |
5127 | ||
5128 | if (!sf) { | |
5129 | tcg_gen_ext32u_i64(tcg_int, tcg_int); | |
5130 | } | |
5131 | } | |
5132 | ||
5133 | tcg_temp_free_ptr(tcg_fpstatus); | |
5134 | tcg_temp_free_i32(tcg_shift); | |
5135 | } | |
5136 | ||
faa0ba46 PM |
5137 | /* C3.6.29 Floating point <-> fixed point conversions |
5138 | * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0 | |
5139 | * +----+---+---+-----------+------+---+-------+--------+-------+------+------+ | |
5140 | * | sf | 0 | S | 1 1 1 1 0 | type | 0 | rmode | opcode | scale | Rn | Rd | | |
5141 | * +----+---+---+-----------+------+---+-------+--------+-------+------+------+ | |
5142 | */ | |
5143 | static void disas_fp_fixed_conv(DisasContext *s, uint32_t insn) | |
5144 | { | |
52a1f6a3 AG |
5145 | int rd = extract32(insn, 0, 5); |
5146 | int rn = extract32(insn, 5, 5); | |
5147 | int scale = extract32(insn, 10, 6); | |
5148 | int opcode = extract32(insn, 16, 3); | |
5149 | int rmode = extract32(insn, 19, 2); | |
5150 | int type = extract32(insn, 22, 2); | |
5151 | bool sbit = extract32(insn, 29, 1); | |
5152 | bool sf = extract32(insn, 31, 1); | |
5153 | bool itof; | |
5154 | ||
5155 | if (sbit || (type > 1) | |
5156 | || (!sf && scale < 32)) { | |
5157 | unallocated_encoding(s); | |
5158 | return; | |
5159 | } | |
5160 | ||
5161 | switch ((rmode << 3) | opcode) { | |
5162 | case 0x2: /* SCVTF */ | |
5163 | case 0x3: /* UCVTF */ | |
5164 | itof = true; | |
5165 | break; | |
5166 | case 0x18: /* FCVTZS */ | |
5167 | case 0x19: /* FCVTZU */ | |
5168 | itof = false; | |
5169 | break; | |
5170 | default: | |
5171 | unallocated_encoding(s); | |
5172 | return; | |
5173 | } | |
5174 | ||
8c6afa6a PM |
5175 | if (!fp_access_check(s)) { |
5176 | return; | |
5177 | } | |
5178 | ||
52a1f6a3 | 5179 | handle_fpfpcvt(s, rd, rn, opcode, itof, FPROUNDING_ZERO, scale, sf, type); |
faa0ba46 PM |
5180 | } |
5181 | ||
ce5458e8 PM |
5182 | static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof) |
5183 | { | |
5184 | /* FMOV: gpr to or from float, double, or top half of quad fp reg, | |
5185 | * without conversion. | |
5186 | */ | |
5187 | ||
5188 | if (itof) { | |
ce5458e8 PM |
5189 | TCGv_i64 tcg_rn = cpu_reg(s, rn); |
5190 | ||
5191 | switch (type) { | |
5192 | case 0: | |
5193 | { | |
5194 | /* 32 bit */ | |
5195 | TCGv_i64 tmp = tcg_temp_new_i64(); | |
5196 | tcg_gen_ext32u_i64(tmp, tcg_rn); | |
90e49638 | 5197 | tcg_gen_st_i64(tmp, cpu_env, fp_reg_offset(s, rd, MO_64)); |
ce5458e8 | 5198 | tcg_gen_movi_i64(tmp, 0); |
90e49638 | 5199 | tcg_gen_st_i64(tmp, cpu_env, fp_reg_hi_offset(s, rd)); |
ce5458e8 PM |
5200 | tcg_temp_free_i64(tmp); |
5201 | break; | |
5202 | } | |
5203 | case 1: | |
5204 | { | |
5205 | /* 64 bit */ | |
5206 | TCGv_i64 tmp = tcg_const_i64(0); | |
90e49638 PM |
5207 | tcg_gen_st_i64(tcg_rn, cpu_env, fp_reg_offset(s, rd, MO_64)); |
5208 | tcg_gen_st_i64(tmp, cpu_env, fp_reg_hi_offset(s, rd)); | |
ce5458e8 PM |
5209 | tcg_temp_free_i64(tmp); |
5210 | break; | |
5211 | } | |
5212 | case 2: | |
5213 | /* 64 bit to top half. */ | |
90e49638 | 5214 | tcg_gen_st_i64(tcg_rn, cpu_env, fp_reg_hi_offset(s, rd)); |
ce5458e8 PM |
5215 | break; |
5216 | } | |
5217 | } else { | |
ce5458e8 PM |
5218 | TCGv_i64 tcg_rd = cpu_reg(s, rd); |
5219 | ||
5220 | switch (type) { | |
5221 | case 0: | |
5222 | /* 32 bit */ | |
90e49638 | 5223 | tcg_gen_ld32u_i64(tcg_rd, cpu_env, fp_reg_offset(s, rn, MO_32)); |
ce5458e8 | 5224 | break; |
ce5458e8 PM |
5225 | case 1: |
5226 | /* 64 bit */ | |
90e49638 | 5227 | tcg_gen_ld_i64(tcg_rd, cpu_env, fp_reg_offset(s, rn, MO_64)); |
e2f90565 PM |
5228 | break; |
5229 | case 2: | |
5230 | /* 64 bits from top half */ | |
90e49638 | 5231 | tcg_gen_ld_i64(tcg_rd, cpu_env, fp_reg_hi_offset(s, rn)); |
ce5458e8 PM |
5232 | break; |
5233 | } | |
5234 | } | |
5235 | } | |
5236 | ||
faa0ba46 PM |
5237 | /* C3.6.30 Floating point <-> integer conversions |
5238 | * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0 | |
5239 | * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+ | |
c436d406 | 5240 | * | sf | 0 | S | 1 1 1 1 0 | type | 1 | rmode | opc | 0 0 0 0 0 0 | Rn | Rd | |
faa0ba46 PM |
5241 | * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+ |
5242 | */ | |
5243 | static void disas_fp_int_conv(DisasContext *s, uint32_t insn) | |
5244 | { | |
ce5458e8 PM |
5245 | int rd = extract32(insn, 0, 5); |
5246 | int rn = extract32(insn, 5, 5); | |
5247 | int opcode = extract32(insn, 16, 3); | |
5248 | int rmode = extract32(insn, 19, 2); | |
5249 | int type = extract32(insn, 22, 2); | |
5250 | bool sbit = extract32(insn, 29, 1); | |
5251 | bool sf = extract32(insn, 31, 1); | |
5252 | ||
c436d406 WN |
5253 | if (sbit) { |
5254 | unallocated_encoding(s); | |
5255 | return; | |
5256 | } | |
5257 | ||
5258 | if (opcode > 5) { | |
ce5458e8 PM |
5259 | /* FMOV */ |
5260 | bool itof = opcode & 1; | |
5261 | ||
c436d406 WN |
5262 | if (rmode >= 2) { |
5263 | unallocated_encoding(s); | |
5264 | return; | |
5265 | } | |
5266 | ||
ce5458e8 PM |
5267 | switch (sf << 3 | type << 1 | rmode) { |
5268 | case 0x0: /* 32 bit */ | |
5269 | case 0xa: /* 64 bit */ | |
5270 | case 0xd: /* 64 bit to top half of quad */ | |
5271 | break; | |
5272 | default: | |
5273 | /* all other sf/type/rmode combinations are invalid */ | |
5274 | unallocated_encoding(s); | |
5275 | break; | |
5276 | } | |
5277 | ||
8c6afa6a PM |
5278 | if (!fp_access_check(s)) { |
5279 | return; | |
5280 | } | |
ce5458e8 PM |
5281 | handle_fmov(s, rd, rn, type, itof); |
5282 | } else { | |
5283 | /* actual FP conversions */ | |
c436d406 WN |
5284 | bool itof = extract32(opcode, 1, 1); |
5285 | ||
5286 | if (type > 1 || (rmode != 0 && opcode > 1)) { | |
5287 | unallocated_encoding(s); | |
5288 | return; | |
5289 | } | |
5290 | ||
8c6afa6a PM |
5291 | if (!fp_access_check(s)) { |
5292 | return; | |
5293 | } | |
c436d406 | 5294 | handle_fpfpcvt(s, rd, rn, opcode, itof, rmode, 64, sf, type); |
ce5458e8 | 5295 | } |
faa0ba46 PM |
5296 | } |
5297 | ||
5298 | /* FP-specific subcases of table C3-6 (SIMD and FP data processing) | |
5299 | * 31 30 29 28 25 24 0 | |
5300 | * +---+---+---+---------+-----------------------------+ | |
5301 | * | | 0 | | 1 1 1 1 | | | |
5302 | * +---+---+---+---------+-----------------------------+ | |
5303 | */ | |
5304 | static void disas_data_proc_fp(DisasContext *s, uint32_t insn) | |
5305 | { | |
5306 | if (extract32(insn, 24, 1)) { | |
5307 | /* Floating point data-processing (3 source) */ | |
5308 | disas_fp_3src(s, insn); | |
5309 | } else if (extract32(insn, 21, 1) == 0) { | |
5310 | /* Floating point to fixed point conversions */ | |
5311 | disas_fp_fixed_conv(s, insn); | |
5312 | } else { | |
5313 | switch (extract32(insn, 10, 2)) { | |
5314 | case 1: | |
5315 | /* Floating point conditional compare */ | |
5316 | disas_fp_ccomp(s, insn); | |
5317 | break; | |
5318 | case 2: | |
5319 | /* Floating point data-processing (2 source) */ | |
5320 | disas_fp_2src(s, insn); | |
5321 | break; | |
5322 | case 3: | |
5323 | /* Floating point conditional select */ | |
5324 | disas_fp_csel(s, insn); | |
5325 | break; | |
5326 | case 0: | |
5327 | switch (ctz32(extract32(insn, 12, 4))) { | |
5328 | case 0: /* [15:12] == xxx1 */ | |
5329 | /* Floating point immediate */ | |
5330 | disas_fp_imm(s, insn); | |
5331 | break; | |
5332 | case 1: /* [15:12] == xx10 */ | |
5333 | /* Floating point compare */ | |
5334 | disas_fp_compare(s, insn); | |
5335 | break; | |
5336 | case 2: /* [15:12] == x100 */ | |
5337 | /* Floating point data-processing (1 source) */ | |
5338 | disas_fp_1src(s, insn); | |
5339 | break; | |
5340 | case 3: /* [15:12] == 1000 */ | |
5341 | unallocated_encoding(s); | |
5342 | break; | |
5343 | default: /* [15:12] == 0000 */ | |
5344 | /* Floating point <-> integer conversions */ | |
5345 | disas_fp_int_conv(s, insn); | |
5346 | break; | |
5347 | } | |
5348 | break; | |
5349 | } | |
5350 | } | |
5351 | } | |
5352 | ||
5c73747f PM |
5353 | static void do_ext64(DisasContext *s, TCGv_i64 tcg_left, TCGv_i64 tcg_right, |
5354 | int pos) | |
5355 | { | |
5356 | /* Extract 64 bits from the middle of two concatenated 64 bit | |
5357 | * vector register slices left:right. The extracted bits start | |
5358 | * at 'pos' bits into the right (least significant) side. | |
5359 | * We return the result in tcg_right, and guarantee not to | |
5360 | * trash tcg_left. | |
5361 | */ | |
5362 | TCGv_i64 tcg_tmp = tcg_temp_new_i64(); | |
5363 | assert(pos > 0 && pos < 64); | |
5364 | ||
5365 | tcg_gen_shri_i64(tcg_right, tcg_right, pos); | |
5366 | tcg_gen_shli_i64(tcg_tmp, tcg_left, 64 - pos); | |
5367 | tcg_gen_or_i64(tcg_right, tcg_right, tcg_tmp); | |
5368 | ||
5369 | tcg_temp_free_i64(tcg_tmp); | |
5370 | } | |
5371 | ||
384b26fb AB |
5372 | /* C3.6.1 EXT |
5373 | * 31 30 29 24 23 22 21 20 16 15 14 11 10 9 5 4 0 | |
5374 | * +---+---+-------------+-----+---+------+---+------+---+------+------+ | |
5375 | * | 0 | Q | 1 0 1 1 1 0 | op2 | 0 | Rm | 0 | imm4 | 0 | Rn | Rd | | |
5376 | * +---+---+-------------+-----+---+------+---+------+---+------+------+ | |
5377 | */ | |
5378 | static void disas_simd_ext(DisasContext *s, uint32_t insn) | |
5379 | { | |
5c73747f PM |
5380 | int is_q = extract32(insn, 30, 1); |
5381 | int op2 = extract32(insn, 22, 2); | |
5382 | int imm4 = extract32(insn, 11, 4); | |
5383 | int rm = extract32(insn, 16, 5); | |
5384 | int rn = extract32(insn, 5, 5); | |
5385 | int rd = extract32(insn, 0, 5); | |
5386 | int pos = imm4 << 3; | |
5387 | TCGv_i64 tcg_resl, tcg_resh; | |
5388 | ||
5389 | if (op2 != 0 || (!is_q && extract32(imm4, 3, 1))) { | |
5390 | unallocated_encoding(s); | |
5391 | return; | |
5392 | } | |
5393 | ||
8c6afa6a PM |
5394 | if (!fp_access_check(s)) { |
5395 | return; | |
5396 | } | |
5397 | ||
5c73747f PM |
5398 | tcg_resh = tcg_temp_new_i64(); |
5399 | tcg_resl = tcg_temp_new_i64(); | |
5400 | ||
5401 | /* Vd gets bits starting at pos bits into Vm:Vn. This is | |
5402 | * either extracting 128 bits from a 128:128 concatenation, or | |
5403 | * extracting 64 bits from a 64:64 concatenation. | |
5404 | */ | |
5405 | if (!is_q) { | |
5406 | read_vec_element(s, tcg_resl, rn, 0, MO_64); | |
5407 | if (pos != 0) { | |
5408 | read_vec_element(s, tcg_resh, rm, 0, MO_64); | |
5409 | do_ext64(s, tcg_resh, tcg_resl, pos); | |
5410 | } | |
5411 | tcg_gen_movi_i64(tcg_resh, 0); | |
5412 | } else { | |
5413 | TCGv_i64 tcg_hh; | |
5414 | typedef struct { | |
5415 | int reg; | |
5416 | int elt; | |
5417 | } EltPosns; | |
5418 | EltPosns eltposns[] = { {rn, 0}, {rn, 1}, {rm, 0}, {rm, 1} }; | |
5419 | EltPosns *elt = eltposns; | |
5420 | ||
5421 | if (pos >= 64) { | |
5422 | elt++; | |
5423 | pos -= 64; | |
5424 | } | |
5425 | ||
5426 | read_vec_element(s, tcg_resl, elt->reg, elt->elt, MO_64); | |
5427 | elt++; | |
5428 | read_vec_element(s, tcg_resh, elt->reg, elt->elt, MO_64); | |
5429 | elt++; | |
5430 | if (pos != 0) { | |
5431 | do_ext64(s, tcg_resh, tcg_resl, pos); | |
5432 | tcg_hh = tcg_temp_new_i64(); | |
5433 | read_vec_element(s, tcg_hh, elt->reg, elt->elt, MO_64); | |
5434 | do_ext64(s, tcg_hh, tcg_resh, pos); | |
5435 | tcg_temp_free_i64(tcg_hh); | |
5436 | } | |
5437 | } | |
5438 | ||
5439 | write_vec_element(s, tcg_resl, rd, 0, MO_64); | |
5440 | tcg_temp_free_i64(tcg_resl); | |
5441 | write_vec_element(s, tcg_resh, rd, 1, MO_64); | |
5442 | tcg_temp_free_i64(tcg_resh); | |
384b26fb AB |
5443 | } |
5444 | ||
5445 | /* C3.6.2 TBL/TBX | |
5446 | * 31 30 29 24 23 22 21 20 16 15 14 13 12 11 10 9 5 4 0 | |
5447 | * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+ | |
5448 | * | 0 | Q | 0 0 1 1 1 0 | op2 | 0 | Rm | 0 | len | op | 0 0 | Rn | Rd | | |
5449 | * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+ | |
5450 | */ | |
5451 | static void disas_simd_tb(DisasContext *s, uint32_t insn) | |
5452 | { | |
7c51048f MM |
5453 | int op2 = extract32(insn, 22, 2); |
5454 | int is_q = extract32(insn, 30, 1); | |
5455 | int rm = extract32(insn, 16, 5); | |
5456 | int rn = extract32(insn, 5, 5); | |
5457 | int rd = extract32(insn, 0, 5); | |
5458 | int is_tblx = extract32(insn, 12, 1); | |
5459 | int len = extract32(insn, 13, 2); | |
5460 | TCGv_i64 tcg_resl, tcg_resh, tcg_idx; | |
5461 | TCGv_i32 tcg_regno, tcg_numregs; | |
5462 | ||
5463 | if (op2 != 0) { | |
5464 | unallocated_encoding(s); | |
5465 | return; | |
5466 | } | |
5467 | ||
8c6afa6a PM |
5468 | if (!fp_access_check(s)) { |
5469 | return; | |
5470 | } | |
5471 | ||
7c51048f MM |
5472 | /* This does a table lookup: for every byte element in the input |
5473 | * we index into a table formed from up to four vector registers, | |
5474 | * and then the output is the result of the lookups. Our helper | |
5475 | * function does the lookup operation for a single 64 bit part of | |
5476 | * the input. | |
5477 | */ | |
5478 | tcg_resl = tcg_temp_new_i64(); | |
5479 | tcg_resh = tcg_temp_new_i64(); | |
5480 | ||
5481 | if (is_tblx) { | |
5482 | read_vec_element(s, tcg_resl, rd, 0, MO_64); | |
5483 | } else { | |
5484 | tcg_gen_movi_i64(tcg_resl, 0); | |
5485 | } | |
5486 | if (is_tblx && is_q) { | |
5487 | read_vec_element(s, tcg_resh, rd, 1, MO_64); | |
5488 | } else { | |
5489 | tcg_gen_movi_i64(tcg_resh, 0); | |
5490 | } | |
5491 | ||
5492 | tcg_idx = tcg_temp_new_i64(); | |
5493 | tcg_regno = tcg_const_i32(rn); | |
5494 | tcg_numregs = tcg_const_i32(len + 1); | |
5495 | read_vec_element(s, tcg_idx, rm, 0, MO_64); | |
5496 | gen_helper_simd_tbl(tcg_resl, cpu_env, tcg_resl, tcg_idx, | |
5497 | tcg_regno, tcg_numregs); | |
5498 | if (is_q) { | |
5499 | read_vec_element(s, tcg_idx, rm, 1, MO_64); | |
5500 | gen_helper_simd_tbl(tcg_resh, cpu_env, tcg_resh, tcg_idx, | |
5501 | tcg_regno, tcg_numregs); | |
5502 | } | |
5503 | tcg_temp_free_i64(tcg_idx); | |
5504 | tcg_temp_free_i32(tcg_regno); | |
5505 | tcg_temp_free_i32(tcg_numregs); | |
5506 | ||
5507 | write_vec_element(s, tcg_resl, rd, 0, MO_64); | |
5508 | tcg_temp_free_i64(tcg_resl); | |
5509 | write_vec_element(s, tcg_resh, rd, 1, MO_64); | |
5510 | tcg_temp_free_i64(tcg_resh); | |
384b26fb AB |
5511 | } |
5512 | ||
5513 | /* C3.6.3 ZIP/UZP/TRN | |
5514 | * 31 30 29 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0 | |
5515 | * +---+---+-------------+------+---+------+---+------------------+------+ | |
5516 | * | 0 | Q | 0 0 1 1 1 0 | size | 0 | Rm | 0 | opc | 1 0 | Rn | Rd | | |
5517 | * +---+---+-------------+------+---+------+---+------------------+------+ | |
5518 | */ | |
5519 | static void disas_simd_zip_trn(DisasContext *s, uint32_t insn) | |
5520 | { | |
5fa5469c MM |
5521 | int rd = extract32(insn, 0, 5); |
5522 | int rn = extract32(insn, 5, 5); | |
5523 | int rm = extract32(insn, 16, 5); | |
5524 | int size = extract32(insn, 22, 2); | |
5525 | /* opc field bits [1:0] indicate ZIP/UZP/TRN; | |
5526 | * bit 2 indicates 1 vs 2 variant of the insn. | |
5527 | */ | |
5528 | int opcode = extract32(insn, 12, 2); | |
5529 | bool part = extract32(insn, 14, 1); | |
5530 | bool is_q = extract32(insn, 30, 1); | |
5531 | int esize = 8 << size; | |
5532 | int i, ofs; | |
5533 | int datasize = is_q ? 128 : 64; | |
5534 | int elements = datasize / esize; | |
5535 | TCGv_i64 tcg_res, tcg_resl, tcg_resh; | |
5536 | ||
5537 | if (opcode == 0 || (size == 3 && !is_q)) { | |
5538 | unallocated_encoding(s); | |
5539 | return; | |
5540 | } | |
5541 | ||
8c6afa6a PM |
5542 | if (!fp_access_check(s)) { |
5543 | return; | |
5544 | } | |
5545 | ||
5fa5469c MM |
5546 | tcg_resl = tcg_const_i64(0); |
5547 | tcg_resh = tcg_const_i64(0); | |
5548 | tcg_res = tcg_temp_new_i64(); | |
5549 | ||
5550 | for (i = 0; i < elements; i++) { | |
5551 | switch (opcode) { | |
5552 | case 1: /* UZP1/2 */ | |
5553 | { | |
5554 | int midpoint = elements / 2; | |
5555 | if (i < midpoint) { | |
5556 | read_vec_element(s, tcg_res, rn, 2 * i + part, size); | |
5557 | } else { | |
5558 | read_vec_element(s, tcg_res, rm, | |
5559 | 2 * (i - midpoint) + part, size); | |
5560 | } | |
5561 | break; | |
5562 | } | |
5563 | case 2: /* TRN1/2 */ | |
5564 | if (i & 1) { | |
5565 | read_vec_element(s, tcg_res, rm, (i & ~1) + part, size); | |
5566 | } else { | |
5567 | read_vec_element(s, tcg_res, rn, (i & ~1) + part, size); | |
5568 | } | |
5569 | break; | |
5570 | case 3: /* ZIP1/2 */ | |
5571 | { | |
5572 | int base = part * elements / 2; | |
5573 | if (i & 1) { | |
5574 | read_vec_element(s, tcg_res, rm, base + (i >> 1), size); | |
5575 | } else { | |
5576 | read_vec_element(s, tcg_res, rn, base + (i >> 1), size); | |
5577 | } | |
5578 | break; | |
5579 | } | |
5580 | default: | |
5581 | g_assert_not_reached(); | |
5582 | } | |
5583 | ||
5584 | ofs = i * esize; | |
5585 | if (ofs < 64) { | |
5586 | tcg_gen_shli_i64(tcg_res, tcg_res, ofs); | |
5587 | tcg_gen_or_i64(tcg_resl, tcg_resl, tcg_res); | |
5588 | } else { | |
5589 | tcg_gen_shli_i64(tcg_res, tcg_res, ofs - 64); | |
5590 | tcg_gen_or_i64(tcg_resh, tcg_resh, tcg_res); | |
5591 | } | |
5592 | } | |
5593 | ||
5594 | tcg_temp_free_i64(tcg_res); | |
5595 | ||
5596 | write_vec_element(s, tcg_resl, rd, 0, MO_64); | |
5597 | tcg_temp_free_i64(tcg_resl); | |
5598 | write_vec_element(s, tcg_resh, rd, 1, MO_64); | |
5599 | tcg_temp_free_i64(tcg_resh); | |
384b26fb AB |
5600 | } |
5601 | ||
4a0ff1ce MM |
5602 | static void do_minmaxop(DisasContext *s, TCGv_i32 tcg_elt1, TCGv_i32 tcg_elt2, |
5603 | int opc, bool is_min, TCGv_ptr fpst) | |
5604 | { | |
5605 | /* Helper function for disas_simd_across_lanes: do a single precision | |
5606 | * min/max operation on the specified two inputs, | |
5607 | * and return the result in tcg_elt1. | |
5608 | */ | |
5609 | if (opc == 0xc) { | |
5610 | if (is_min) { | |
5611 | gen_helper_vfp_minnums(tcg_elt1, tcg_elt1, tcg_elt2, fpst); | |
5612 | } else { | |
5613 | gen_helper_vfp_maxnums(tcg_elt1, tcg_elt1, tcg_elt2, fpst); | |
5614 | } | |
5615 | } else { | |
5616 | assert(opc == 0xf); | |
5617 | if (is_min) { | |
5618 | gen_helper_vfp_mins(tcg_elt1, tcg_elt1, tcg_elt2, fpst); | |
5619 | } else { | |
5620 | gen_helper_vfp_maxs(tcg_elt1, tcg_elt1, tcg_elt2, fpst); | |
5621 | } | |
5622 | } | |
5623 | } | |
5624 | ||
384b26fb AB |
5625 | /* C3.6.4 AdvSIMD across lanes |
5626 | * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0 | |
5627 | * +---+---+---+-----------+------+-----------+--------+-----+------+------+ | |
5628 | * | 0 | Q | U | 0 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd | | |
5629 | * +---+---+---+-----------+------+-----------+--------+-----+------+------+ | |
5630 | */ | |
5631 | static void disas_simd_across_lanes(DisasContext *s, uint32_t insn) | |
5632 | { | |
4a0ff1ce MM |
5633 | int rd = extract32(insn, 0, 5); |
5634 | int rn = extract32(insn, 5, 5); | |
5635 | int size = extract32(insn, 22, 2); | |
5636 | int opcode = extract32(insn, 12, 5); | |
5637 | bool is_q = extract32(insn, 30, 1); | |
5638 | bool is_u = extract32(insn, 29, 1); | |
5639 | bool is_fp = false; | |
5640 | bool is_min = false; | |
5641 | int esize; | |
5642 | int elements; | |
5643 | int i; | |
5644 | TCGv_i64 tcg_res, tcg_elt; | |
5645 | ||
5646 | switch (opcode) { | |
5647 | case 0x1b: /* ADDV */ | |
5648 | if (is_u) { | |
5649 | unallocated_encoding(s); | |
5650 | return; | |
5651 | } | |
5652 | /* fall through */ | |
5653 | case 0x3: /* SADDLV, UADDLV */ | |
5654 | case 0xa: /* SMAXV, UMAXV */ | |
5655 | case 0x1a: /* SMINV, UMINV */ | |
5656 | if (size == 3 || (size == 2 && !is_q)) { | |
5657 | unallocated_encoding(s); | |
5658 | return; | |
5659 | } | |
5660 | break; | |
5661 | case 0xc: /* FMAXNMV, FMINNMV */ | |
5662 | case 0xf: /* FMAXV, FMINV */ | |
5663 | if (!is_u || !is_q || extract32(size, 0, 1)) { | |
5664 | unallocated_encoding(s); | |
5665 | return; | |
5666 | } | |
5667 | /* Bit 1 of size field encodes min vs max, and actual size is always | |
5668 | * 32 bits: adjust the size variable so following code can rely on it | |
5669 | */ | |
5670 | is_min = extract32(size, 1, 1); | |
5671 | is_fp = true; | |
5672 | size = 2; | |
5673 | break; | |
5674 | default: | |
5675 | unallocated_encoding(s); | |
5676 | return; | |
5677 | } | |
5678 | ||
8c6afa6a PM |
5679 | if (!fp_access_check(s)) { |
5680 | return; | |
5681 | } | |
5682 | ||
4a0ff1ce MM |
5683 | esize = 8 << size; |
5684 | elements = (is_q ? 128 : 64) / esize; | |
5685 | ||
5686 | tcg_res = tcg_temp_new_i64(); | |
5687 | tcg_elt = tcg_temp_new_i64(); | |
5688 | ||
5689 | /* These instructions operate across all lanes of a vector | |
5690 | * to produce a single result. We can guarantee that a 64 | |
5691 | * bit intermediate is sufficient: | |
5692 | * + for [US]ADDLV the maximum element size is 32 bits, and | |
5693 | * the result type is 64 bits | |
5694 | * + for FMAX*V, FMIN*V, ADDV the intermediate type is the | |
5695 | * same as the element size, which is 32 bits at most | |
5696 | * For the integer operations we can choose to work at 64 | |
5697 | * or 32 bits and truncate at the end; for simplicity | |
5698 | * we use 64 bits always. The floating point | |
5699 | * ops do require 32 bit intermediates, though. | |
5700 | */ | |
5701 | if (!is_fp) { | |
5702 | read_vec_element(s, tcg_res, rn, 0, size | (is_u ? 0 : MO_SIGN)); | |
5703 | ||
5704 | for (i = 1; i < elements; i++) { | |
5705 | read_vec_element(s, tcg_elt, rn, i, size | (is_u ? 0 : MO_SIGN)); | |
5706 | ||
5707 | switch (opcode) { | |
5708 | case 0x03: /* SADDLV / UADDLV */ | |
5709 | case 0x1b: /* ADDV */ | |
5710 | tcg_gen_add_i64(tcg_res, tcg_res, tcg_elt); | |
5711 | break; | |
5712 | case 0x0a: /* SMAXV / UMAXV */ | |
5713 | tcg_gen_movcond_i64(is_u ? TCG_COND_GEU : TCG_COND_GE, | |
5714 | tcg_res, | |
5715 | tcg_res, tcg_elt, tcg_res, tcg_elt); | |
5716 | break; | |
5717 | case 0x1a: /* SMINV / UMINV */ | |
5718 | tcg_gen_movcond_i64(is_u ? TCG_COND_LEU : TCG_COND_LE, | |
5719 | tcg_res, | |
5720 | tcg_res, tcg_elt, tcg_res, tcg_elt); | |
5721 | break; | |
5722 | break; | |
5723 | default: | |
5724 | g_assert_not_reached(); | |
5725 | } | |
5726 | ||
5727 | } | |
5728 | } else { | |
5729 | /* Floating point ops which work on 32 bit (single) intermediates. | |
5730 | * Note that correct NaN propagation requires that we do these | |
5731 | * operations in exactly the order specified by the pseudocode. | |
5732 | */ | |
5733 | TCGv_i32 tcg_elt1 = tcg_temp_new_i32(); | |
5734 | TCGv_i32 tcg_elt2 = tcg_temp_new_i32(); | |
5735 | TCGv_i32 tcg_elt3 = tcg_temp_new_i32(); | |
5736 | TCGv_ptr fpst = get_fpstatus_ptr(); | |
5737 | ||
5738 | assert(esize == 32); | |
5739 | assert(elements == 4); | |
5740 | ||
5741 | read_vec_element(s, tcg_elt, rn, 0, MO_32); | |
ecc7b3aa | 5742 | tcg_gen_extrl_i64_i32(tcg_elt1, tcg_elt); |
4a0ff1ce | 5743 | read_vec_element(s, tcg_elt, rn, 1, MO_32); |
ecc7b3aa | 5744 | tcg_gen_extrl_i64_i32(tcg_elt2, tcg_elt); |
4a0ff1ce MM |
5745 | |
5746 | do_minmaxop(s, tcg_elt1, tcg_elt2, opcode, is_min, fpst); | |
5747 | ||
5748 | read_vec_element(s, tcg_elt, rn, 2, MO_32); | |
ecc7b3aa | 5749 | tcg_gen_extrl_i64_i32(tcg_elt2, tcg_elt); |
4a0ff1ce | 5750 | read_vec_element(s, tcg_elt, rn, 3, MO_32); |
ecc7b3aa | 5751 | tcg_gen_extrl_i64_i32(tcg_elt3, tcg_elt); |
4a0ff1ce MM |
5752 | |
5753 | do_minmaxop(s, tcg_elt2, tcg_elt3, opcode, is_min, fpst); | |
5754 | ||
5755 | do_minmaxop(s, tcg_elt1, tcg_elt2, opcode, is_min, fpst); | |
5756 | ||
5757 | tcg_gen_extu_i32_i64(tcg_res, tcg_elt1); | |
5758 | tcg_temp_free_i32(tcg_elt1); | |
5759 | tcg_temp_free_i32(tcg_elt2); | |
5760 | tcg_temp_free_i32(tcg_elt3); | |
5761 | tcg_temp_free_ptr(fpst); | |
5762 | } | |
5763 | ||
5764 | tcg_temp_free_i64(tcg_elt); | |
5765 | ||
5766 | /* Now truncate the result to the width required for the final output */ | |
5767 | if (opcode == 0x03) { | |
5768 | /* SADDLV, UADDLV: result is 2*esize */ | |
5769 | size++; | |
5770 | } | |
5771 | ||
5772 | switch (size) { | |
5773 | case 0: | |
5774 | tcg_gen_ext8u_i64(tcg_res, tcg_res); | |
5775 | break; | |
5776 | case 1: | |
5777 | tcg_gen_ext16u_i64(tcg_res, tcg_res); | |
5778 | break; | |
5779 | case 2: | |
5780 | tcg_gen_ext32u_i64(tcg_res, tcg_res); | |
5781 | break; | |
5782 | case 3: | |
5783 | break; | |
5784 | default: | |
5785 | g_assert_not_reached(); | |
5786 | } | |
5787 | ||
5788 | write_fp_dreg(s, rd, tcg_res); | |
5789 | tcg_temp_free_i64(tcg_res); | |
384b26fb AB |
5790 | } |
5791 | ||
67bb9389 AB |
5792 | /* C6.3.31 DUP (Element, Vector) |
5793 | * | |
5794 | * 31 30 29 21 20 16 15 10 9 5 4 0 | |
5795 | * +---+---+-------------------+--------+-------------+------+------+ | |
5796 | * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd | | |
5797 | * +---+---+-------------------+--------+-------------+------+------+ | |
5798 | * | |
5799 | * size: encoded in imm5 (see ARM ARM LowestSetBit()) | |
5800 | */ | |
5801 | static void handle_simd_dupe(DisasContext *s, int is_q, int rd, int rn, | |
5802 | int imm5) | |
5803 | { | |
5804 | int size = ctz32(imm5); | |
5805 | int esize = 8 << size; | |
5806 | int elements = (is_q ? 128 : 64) / esize; | |
5807 | int index, i; | |
5808 | TCGv_i64 tmp; | |
5809 | ||
5810 | if (size > 3 || (size == 3 && !is_q)) { | |
5811 | unallocated_encoding(s); | |
5812 | return; | |
5813 | } | |
5814 | ||
8c6afa6a PM |
5815 | if (!fp_access_check(s)) { |
5816 | return; | |
5817 | } | |
5818 | ||
67bb9389 AB |
5819 | index = imm5 >> (size + 1); |
5820 | ||
5821 | tmp = tcg_temp_new_i64(); | |
5822 | read_vec_element(s, tmp, rn, index, size); | |
5823 | ||
5824 | for (i = 0; i < elements; i++) { | |
5825 | write_vec_element(s, tmp, rd, i, size); | |
5826 | } | |
5827 | ||
5828 | if (!is_q) { | |
5829 | clear_vec_high(s, rd); | |
5830 | } | |
5831 | ||
5832 | tcg_temp_free_i64(tmp); | |
5833 | } | |
5834 | ||
360a6f2d PM |
5835 | /* C6.3.31 DUP (element, scalar) |
5836 | * 31 21 20 16 15 10 9 5 4 0 | |
5837 | * +-----------------------+--------+-------------+------+------+ | |
5838 | * | 0 1 0 1 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd | | |
5839 | * +-----------------------+--------+-------------+------+------+ | |
5840 | */ | |
5841 | static void handle_simd_dupes(DisasContext *s, int rd, int rn, | |
5842 | int imm5) | |
5843 | { | |
5844 | int size = ctz32(imm5); | |
5845 | int index; | |
5846 | TCGv_i64 tmp; | |
5847 | ||
5848 | if (size > 3) { | |
5849 | unallocated_encoding(s); | |
5850 | return; | |
5851 | } | |
5852 | ||
8c6afa6a PM |
5853 | if (!fp_access_check(s)) { |
5854 | return; | |
5855 | } | |
5856 | ||
360a6f2d PM |
5857 | index = imm5 >> (size + 1); |
5858 | ||
5859 | /* This instruction just extracts the specified element and | |
5860 | * zero-extends it into the bottom of the destination register. | |
5861 | */ | |
5862 | tmp = tcg_temp_new_i64(); | |
5863 | read_vec_element(s, tmp, rn, index, size); | |
5864 | write_fp_dreg(s, rd, tmp); | |
5865 | tcg_temp_free_i64(tmp); | |
5866 | } | |
5867 | ||
67bb9389 AB |
5868 | /* C6.3.32 DUP (General) |
5869 | * | |
5870 | * 31 30 29 21 20 16 15 10 9 5 4 0 | |
5871 | * +---+---+-------------------+--------+-------------+------+------+ | |
5872 | * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 1 1 | Rn | Rd | | |
5873 | * +---+---+-------------------+--------+-------------+------+------+ | |
5874 | * | |
5875 | * size: encoded in imm5 (see ARM ARM LowestSetBit()) | |
5876 | */ | |
5877 | static void handle_simd_dupg(DisasContext *s, int is_q, int rd, int rn, | |
5878 | int imm5) | |
5879 | { | |
5880 | int size = ctz32(imm5); | |
5881 | int esize = 8 << size; | |
5882 | int elements = (is_q ? 128 : 64)/esize; | |
5883 | int i = 0; | |
5884 | ||
5885 | if (size > 3 || ((size == 3) && !is_q)) { | |
5886 | unallocated_encoding(s); | |
5887 | return; | |
5888 | } | |
8c6afa6a PM |
5889 | |
5890 | if (!fp_access_check(s)) { | |
5891 | return; | |
5892 | } | |
5893 | ||
67bb9389 AB |
5894 | for (i = 0; i < elements; i++) { |
5895 | write_vec_element(s, cpu_reg(s, rn), rd, i, size); | |
5896 | } | |
5897 | if (!is_q) { | |
5898 | clear_vec_high(s, rd); | |
5899 | } | |
5900 | } | |
5901 | ||
5902 | /* C6.3.150 INS (Element) | |
5903 | * | |
5904 | * 31 21 20 16 15 14 11 10 9 5 4 0 | |
5905 | * +-----------------------+--------+------------+---+------+------+ | |
5906 | * | 0 1 1 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd | | |
5907 | * +-----------------------+--------+------------+---+------+------+ | |
5908 | * | |
5909 | * size: encoded in imm5 (see ARM ARM LowestSetBit()) | |
5910 | * index: encoded in imm5<4:size+1> | |
5911 | */ | |
5912 | static void handle_simd_inse(DisasContext *s, int rd, int rn, | |
5913 | int imm4, int imm5) | |
5914 | { | |
5915 | int size = ctz32(imm5); | |
5916 | int src_index, dst_index; | |
5917 | TCGv_i64 tmp; | |
5918 | ||
5919 | if (size > 3) { | |
5920 | unallocated_encoding(s); | |
5921 | return; | |
5922 | } | |
8c6afa6a PM |
5923 | |
5924 | if (!fp_access_check(s)) { | |
5925 | return; | |
5926 | } | |
5927 | ||
67bb9389 AB |
5928 | dst_index = extract32(imm5, 1+size, 5); |
5929 | src_index = extract32(imm4, size, 4); | |
5930 | ||
5931 | tmp = tcg_temp_new_i64(); | |
5932 | ||
5933 | read_vec_element(s, tmp, rn, src_index, size); | |
5934 | write_vec_element(s, tmp, rd, dst_index, size); | |
5935 | ||
5936 | tcg_temp_free_i64(tmp); | |
5937 | } | |
5938 | ||
5939 | ||
5940 | /* C6.3.151 INS (General) | |
5941 | * | |
5942 | * 31 21 20 16 15 10 9 5 4 0 | |
5943 | * +-----------------------+--------+-------------+------+------+ | |
5944 | * | 0 1 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 1 1 1 | Rn | Rd | | |
5945 | * +-----------------------+--------+-------------+------+------+ | |
5946 | * | |
5947 | * size: encoded in imm5 (see ARM ARM LowestSetBit()) | |
5948 | * index: encoded in imm5<4:size+1> | |
5949 | */ | |
5950 | static void handle_simd_insg(DisasContext *s, int rd, int rn, int imm5) | |
5951 | { | |
5952 | int size = ctz32(imm5); | |
5953 | int idx; | |
5954 | ||
5955 | if (size > 3) { | |
5956 | unallocated_encoding(s); | |
5957 | return; | |
5958 | } | |
5959 | ||
8c6afa6a PM |
5960 | if (!fp_access_check(s)) { |
5961 | return; | |
5962 | } | |
5963 | ||
67bb9389 AB |
5964 | idx = extract32(imm5, 1 + size, 4 - size); |
5965 | write_vec_element(s, cpu_reg(s, rn), rd, idx, size); | |
5966 | } | |
5967 | ||
5968 | /* | |
5969 | * C6.3.321 UMOV (General) | |
5970 | * C6.3.237 SMOV (General) | |
5971 | * | |
5972 | * 31 30 29 21 20 16 15 12 10 9 5 4 0 | |
5973 | * +---+---+-------------------+--------+-------------+------+------+ | |
5974 | * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 1 U 1 1 | Rn | Rd | | |
5975 | * +---+---+-------------------+--------+-------------+------+------+ | |
5976 | * | |
5977 | * U: unsigned when set | |
5978 | * size: encoded in imm5 (see ARM ARM LowestSetBit()) | |
5979 | */ | |
5980 | static void handle_simd_umov_smov(DisasContext *s, int is_q, int is_signed, | |
5981 | int rn, int rd, int imm5) | |
5982 | { | |
5983 | int size = ctz32(imm5); | |
5984 | int element; | |
5985 | TCGv_i64 tcg_rd; | |
5986 | ||
5987 | /* Check for UnallocatedEncodings */ | |
5988 | if (is_signed) { | |
5989 | if (size > 2 || (size == 2 && !is_q)) { | |
5990 | unallocated_encoding(s); | |
5991 | return; | |
5992 | } | |
5993 | } else { | |
5994 | if (size > 3 | |
5995 | || (size < 3 && is_q) | |
5996 | || (size == 3 && !is_q)) { | |
5997 | unallocated_encoding(s); | |
5998 | return; | |
5999 | } | |
6000 | } | |
8c6afa6a PM |
6001 | |
6002 | if (!fp_access_check(s)) { | |
6003 | return; | |
6004 | } | |
6005 | ||
67bb9389 AB |
6006 | element = extract32(imm5, 1+size, 4); |
6007 | ||
6008 | tcg_rd = cpu_reg(s, rd); | |
6009 | read_vec_element(s, tcg_rd, rn, element, size | (is_signed ? MO_SIGN : 0)); | |
6010 | if (is_signed && !is_q) { | |
6011 | tcg_gen_ext32u_i64(tcg_rd, tcg_rd); | |
6012 | } | |
6013 | } | |
6014 | ||
384b26fb AB |
6015 | /* C3.6.5 AdvSIMD copy |
6016 | * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0 | |
6017 | * +---+---+----+-----------------+------+---+------+---+------+------+ | |
6018 | * | 0 | Q | op | 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd | | |
6019 | * +---+---+----+-----------------+------+---+------+---+------+------+ | |
6020 | */ | |
6021 | static void disas_simd_copy(DisasContext *s, uint32_t insn) | |
6022 | { | |
67bb9389 AB |
6023 | int rd = extract32(insn, 0, 5); |
6024 | int rn = extract32(insn, 5, 5); | |
6025 | int imm4 = extract32(insn, 11, 4); | |
6026 | int op = extract32(insn, 29, 1); | |
6027 | int is_q = extract32(insn, 30, 1); | |
6028 | int imm5 = extract32(insn, 16, 5); | |
6029 | ||
6030 | if (op) { | |
6031 | if (is_q) { | |
6032 | /* INS (element) */ | |
6033 | handle_simd_inse(s, rd, rn, imm4, imm5); | |
6034 | } else { | |
6035 | unallocated_encoding(s); | |
6036 | } | |
6037 | } else { | |
6038 | switch (imm4) { | |
6039 | case 0: | |
6040 | /* DUP (element - vector) */ | |
6041 | handle_simd_dupe(s, is_q, rd, rn, imm5); | |
6042 | break; | |
6043 | case 1: | |
6044 | /* DUP (general) */ | |
6045 | handle_simd_dupg(s, is_q, rd, rn, imm5); | |
6046 | break; | |
6047 | case 3: | |
6048 | if (is_q) { | |
6049 | /* INS (general) */ | |
6050 | handle_simd_insg(s, rd, rn, imm5); | |
6051 | } else { | |
6052 | unallocated_encoding(s); | |
6053 | } | |
6054 | break; | |
6055 | case 5: | |
6056 | case 7: | |
6057 | /* UMOV/SMOV (is_q indicates 32/64; imm4 indicates signedness) */ | |
6058 | handle_simd_umov_smov(s, is_q, (imm4 == 5), rn, rd, imm5); | |
6059 | break; | |
6060 | default: | |
6061 | unallocated_encoding(s); | |
6062 | break; | |
6063 | } | |
6064 | } | |
384b26fb AB |
6065 | } |
6066 | ||
6067 | /* C3.6.6 AdvSIMD modified immediate | |
6068 | * 31 30 29 28 19 18 16 15 12 11 10 9 5 4 0 | |
6069 | * +---+---+----+---------------------+-----+-------+----+---+-------+------+ | |
6070 | * | 0 | Q | op | 0 1 1 1 1 0 0 0 0 0 | abc | cmode | o2 | 1 | defgh | Rd | | |
6071 | * +---+---+----+---------------------+-----+-------+----+---+-------+------+ | |
f3f8c4f4 AB |
6072 | * |
6073 | * There are a number of operations that can be carried out here: | |
6074 | * MOVI - move (shifted) imm into register | |
6075 | * MVNI - move inverted (shifted) imm into register | |
6076 | * ORR - bitwise OR of (shifted) imm with register | |
6077 | * BIC - bitwise clear of (shifted) imm with register | |
384b26fb AB |
6078 | */ |
6079 | static void disas_simd_mod_imm(DisasContext *s, uint32_t insn) | |
6080 | { | |
f3f8c4f4 AB |
6081 | int rd = extract32(insn, 0, 5); |
6082 | int cmode = extract32(insn, 12, 4); | |
6083 | int cmode_3_1 = extract32(cmode, 1, 3); | |
6084 | int cmode_0 = extract32(cmode, 0, 1); | |
6085 | int o2 = extract32(insn, 11, 1); | |
6086 | uint64_t abcdefgh = extract32(insn, 5, 5) | (extract32(insn, 16, 3) << 5); | |
6087 | bool is_neg = extract32(insn, 29, 1); | |
6088 | bool is_q = extract32(insn, 30, 1); | |
6089 | uint64_t imm = 0; | |
6090 | TCGv_i64 tcg_rd, tcg_imm; | |
6091 | int i; | |
6092 | ||
6093 | if (o2 != 0 || ((cmode == 0xf) && is_neg && !is_q)) { | |
6094 | unallocated_encoding(s); | |
6095 | return; | |
6096 | } | |
6097 | ||
8c6afa6a PM |
6098 | if (!fp_access_check(s)) { |
6099 | return; | |
6100 | } | |
6101 | ||
f3f8c4f4 AB |
6102 | /* See AdvSIMDExpandImm() in ARM ARM */ |
6103 | switch (cmode_3_1) { | |
6104 | case 0: /* Replicate(Zeros(24):imm8, 2) */ | |
6105 | case 1: /* Replicate(Zeros(16):imm8:Zeros(8), 2) */ | |
6106 | case 2: /* Replicate(Zeros(8):imm8:Zeros(16), 2) */ | |
6107 | case 3: /* Replicate(imm8:Zeros(24), 2) */ | |
6108 | { | |
6109 | int shift = cmode_3_1 * 8; | |
6110 | imm = bitfield_replicate(abcdefgh << shift, 32); | |
6111 | break; | |
6112 | } | |
6113 | case 4: /* Replicate(Zeros(8):imm8, 4) */ | |
6114 | case 5: /* Replicate(imm8:Zeros(8), 4) */ | |
6115 | { | |
6116 | int shift = (cmode_3_1 & 0x1) * 8; | |
6117 | imm = bitfield_replicate(abcdefgh << shift, 16); | |
6118 | break; | |
6119 | } | |
6120 | case 6: | |
6121 | if (cmode_0) { | |
6122 | /* Replicate(Zeros(8):imm8:Ones(16), 2) */ | |
6123 | imm = (abcdefgh << 16) | 0xffff; | |
6124 | } else { | |
6125 | /* Replicate(Zeros(16):imm8:Ones(8), 2) */ | |
6126 | imm = (abcdefgh << 8) | 0xff; | |
6127 | } | |
6128 | imm = bitfield_replicate(imm, 32); | |
6129 | break; | |
6130 | case 7: | |
6131 | if (!cmode_0 && !is_neg) { | |
6132 | imm = bitfield_replicate(abcdefgh, 8); | |
6133 | } else if (!cmode_0 && is_neg) { | |
6134 | int i; | |
6135 | imm = 0; | |
6136 | for (i = 0; i < 8; i++) { | |
6137 | if ((abcdefgh) & (1 << i)) { | |
6138 | imm |= 0xffULL << (i * 8); | |
6139 | } | |
6140 | } | |
6141 | } else if (cmode_0) { | |
6142 | if (is_neg) { | |
6143 | imm = (abcdefgh & 0x3f) << 48; | |
6144 | if (abcdefgh & 0x80) { | |
6145 | imm |= 0x8000000000000000ULL; | |
6146 | } | |
6147 | if (abcdefgh & 0x40) { | |
6148 | imm |= 0x3fc0000000000000ULL; | |
6149 | } else { | |
6150 | imm |= 0x4000000000000000ULL; | |
6151 | } | |
6152 | } else { | |
6153 | imm = (abcdefgh & 0x3f) << 19; | |
6154 | if (abcdefgh & 0x80) { | |
6155 | imm |= 0x80000000; | |
6156 | } | |
6157 | if (abcdefgh & 0x40) { | |
6158 | imm |= 0x3e000000; | |
6159 | } else { | |
6160 | imm |= 0x40000000; | |
6161 | } | |
6162 | imm |= (imm << 32); | |
6163 | } | |
6164 | } | |
6165 | break; | |
6166 | } | |
6167 | ||
6168 | if (cmode_3_1 != 7 && is_neg) { | |
6169 | imm = ~imm; | |
6170 | } | |
6171 | ||
6172 | tcg_imm = tcg_const_i64(imm); | |
6173 | tcg_rd = new_tmp_a64(s); | |
6174 | ||
6175 | for (i = 0; i < 2; i++) { | |
90e49638 | 6176 | int foffs = i ? fp_reg_hi_offset(s, rd) : fp_reg_offset(s, rd, MO_64); |
f3f8c4f4 AB |
6177 | |
6178 | if (i == 1 && !is_q) { | |
6179 | /* non-quad ops clear high half of vector */ | |
6180 | tcg_gen_movi_i64(tcg_rd, 0); | |
6181 | } else if ((cmode & 0x9) == 0x1 || (cmode & 0xd) == 0x9) { | |
6182 | tcg_gen_ld_i64(tcg_rd, cpu_env, foffs); | |
6183 | if (is_neg) { | |
6184 | /* AND (BIC) */ | |
6185 | tcg_gen_and_i64(tcg_rd, tcg_rd, tcg_imm); | |
6186 | } else { | |
6187 | /* ORR */ | |
6188 | tcg_gen_or_i64(tcg_rd, tcg_rd, tcg_imm); | |
6189 | } | |
6190 | } else { | |
6191 | /* MOVI */ | |
6192 | tcg_gen_mov_i64(tcg_rd, tcg_imm); | |
6193 | } | |
6194 | tcg_gen_st_i64(tcg_rd, cpu_env, foffs); | |
6195 | } | |
6196 | ||
6197 | tcg_temp_free_i64(tcg_imm); | |
384b26fb AB |
6198 | } |
6199 | ||
6200 | /* C3.6.7 AdvSIMD scalar copy | |
6201 | * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0 | |
6202 | * +-----+----+-----------------+------+---+------+---+------+------+ | |
6203 | * | 0 1 | op | 1 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd | | |
6204 | * +-----+----+-----------------+------+---+------+---+------+------+ | |
6205 | */ | |
6206 | static void disas_simd_scalar_copy(DisasContext *s, uint32_t insn) | |
6207 | { | |
360a6f2d PM |
6208 | int rd = extract32(insn, 0, 5); |
6209 | int rn = extract32(insn, 5, 5); | |
6210 | int imm4 = extract32(insn, 11, 4); | |
6211 | int imm5 = extract32(insn, 16, 5); | |
6212 | int op = extract32(insn, 29, 1); | |
6213 | ||
6214 | if (op != 0 || imm4 != 0) { | |
6215 | unallocated_encoding(s); | |
6216 | return; | |
6217 | } | |
6218 | ||
6219 | /* DUP (element, scalar) */ | |
6220 | handle_simd_dupes(s, rd, rn, imm5); | |
384b26fb AB |
6221 | } |
6222 | ||
6223 | /* C3.6.8 AdvSIMD scalar pairwise | |
6224 | * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0 | |
6225 | * +-----+---+-----------+------+-----------+--------+-----+------+------+ | |
6226 | * | 0 1 | U | 1 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd | | |
6227 | * +-----+---+-----------+------+-----------+--------+-----+------+------+ | |
6228 | */ | |
6229 | static void disas_simd_scalar_pairwise(DisasContext *s, uint32_t insn) | |
6230 | { | |
3720a7ea PM |
6231 | int u = extract32(insn, 29, 1); |
6232 | int size = extract32(insn, 22, 2); | |
6233 | int opcode = extract32(insn, 12, 5); | |
6234 | int rn = extract32(insn, 5, 5); | |
6235 | int rd = extract32(insn, 0, 5); | |
6236 | TCGv_ptr fpst; | |
6237 | ||
6238 | /* For some ops (the FP ones), size[1] is part of the encoding. | |
6239 | * For ADDP strictly it is not but size[1] is always 1 for valid | |
6240 | * encodings. | |
6241 | */ | |
6242 | opcode |= (extract32(size, 1, 1) << 5); | |
6243 | ||
6244 | switch (opcode) { | |
6245 | case 0x3b: /* ADDP */ | |
6246 | if (u || size != 3) { | |
6247 | unallocated_encoding(s); | |
6248 | return; | |
6249 | } | |
8c6afa6a PM |
6250 | if (!fp_access_check(s)) { |
6251 | return; | |
6252 | } | |
6253 | ||
3720a7ea PM |
6254 | TCGV_UNUSED_PTR(fpst); |
6255 | break; | |
6256 | case 0xc: /* FMAXNMP */ | |
6257 | case 0xd: /* FADDP */ | |
6258 | case 0xf: /* FMAXP */ | |
6259 | case 0x2c: /* FMINNMP */ | |
6260 | case 0x2f: /* FMINP */ | |
6261 | /* FP op, size[0] is 32 or 64 bit */ | |
6262 | if (!u) { | |
6263 | unallocated_encoding(s); | |
6264 | return; | |
6265 | } | |
8c6afa6a PM |
6266 | if (!fp_access_check(s)) { |
6267 | return; | |
6268 | } | |
6269 | ||
3720a7ea PM |
6270 | size = extract32(size, 0, 1) ? 3 : 2; |
6271 | fpst = get_fpstatus_ptr(); | |
6272 | break; | |
6273 | default: | |
6274 | unallocated_encoding(s); | |
6275 | return; | |
6276 | } | |
6277 | ||
6278 | if (size == 3) { | |
6279 | TCGv_i64 tcg_op1 = tcg_temp_new_i64(); | |
6280 | TCGv_i64 tcg_op2 = tcg_temp_new_i64(); | |
6281 | TCGv_i64 tcg_res = tcg_temp_new_i64(); | |
6282 | ||
6283 | read_vec_element(s, tcg_op1, rn, 0, MO_64); | |
6284 | read_vec_element(s, tcg_op2, rn, 1, MO_64); | |
6285 | ||
6286 | switch (opcode) { | |
6287 | case 0x3b: /* ADDP */ | |
6288 | tcg_gen_add_i64(tcg_res, tcg_op1, tcg_op2); | |
6289 | break; | |
6290 | case 0xc: /* FMAXNMP */ | |
6291 | gen_helper_vfp_maxnumd(tcg_res, tcg_op1, tcg_op2, fpst); | |
6292 | break; | |
6293 | case 0xd: /* FADDP */ | |
6294 | gen_helper_vfp_addd(tcg_res, tcg_op1, tcg_op2, fpst); | |
6295 | break; | |
6296 | case 0xf: /* FMAXP */ | |
6297 | gen_helper_vfp_maxd(tcg_res, tcg_op1, tcg_op2, fpst); | |
6298 | break; | |
6299 | case 0x2c: /* FMINNMP */ | |
6300 | gen_helper_vfp_minnumd(tcg_res, tcg_op1, tcg_op2, fpst); | |
6301 | break; | |
6302 | case 0x2f: /* FMINP */ | |
6303 | gen_helper_vfp_mind(tcg_res, tcg_op1, tcg_op2, fpst); | |
6304 | break; | |
6305 | default: | |
6306 | g_assert_not_reached(); | |
6307 | } | |
6308 | ||
6309 | write_fp_dreg(s, rd, tcg_res); | |
6310 | ||
6311 | tcg_temp_free_i64(tcg_op1); | |
6312 | tcg_temp_free_i64(tcg_op2); | |
6313 | tcg_temp_free_i64(tcg_res); | |
6314 | } else { | |
6315 | TCGv_i32 tcg_op1 = tcg_temp_new_i32(); | |
6316 | TCGv_i32 tcg_op2 = tcg_temp_new_i32(); | |
6317 | TCGv_i32 tcg_res = tcg_temp_new_i32(); | |
6318 | ||
6319 | read_vec_element_i32(s, tcg_op1, rn, 0, MO_32); | |
6320 | read_vec_element_i32(s, tcg_op2, rn, 1, MO_32); | |
6321 | ||
6322 | switch (opcode) { | |
6323 | case 0xc: /* FMAXNMP */ | |
6324 | gen_helper_vfp_maxnums(tcg_res, tcg_op1, tcg_op2, fpst); | |
6325 | break; | |
6326 | case 0xd: /* FADDP */ | |
6327 | gen_helper_vfp_adds(tcg_res, tcg_op1, tcg_op2, fpst); | |
6328 | break; | |
6329 | case 0xf: /* FMAXP */ | |
6330 | gen_helper_vfp_maxs(tcg_res, tcg_op1, tcg_op2, fpst); | |
6331 | break; | |
6332 | case 0x2c: /* FMINNMP */ | |
6333 | gen_helper_vfp_minnums(tcg_res, tcg_op1, tcg_op2, fpst); | |
6334 | break; | |
6335 | case 0x2f: /* FMINP */ | |
6336 | gen_helper_vfp_mins(tcg_res, tcg_op1, tcg_op2, fpst); | |
6337 | break; | |
6338 | default: | |
6339 | g_assert_not_reached(); | |
6340 | } | |
6341 | ||
6342 | write_fp_sreg(s, rd, tcg_res); | |
6343 | ||
6344 | tcg_temp_free_i32(tcg_op1); | |
6345 | tcg_temp_free_i32(tcg_op2); | |
6346 | tcg_temp_free_i32(tcg_res); | |
6347 | } | |
6348 | ||
6349 | if (!TCGV_IS_UNUSED_PTR(fpst)) { | |
6350 | tcg_temp_free_ptr(fpst); | |
6351 | } | |
384b26fb AB |
6352 | } |
6353 | ||
4d1cef84 AB |
6354 | /* |
6355 | * Common SSHR[RA]/USHR[RA] - Shift right (optional rounding/accumulate) | |
6356 | * | |
6357 | * This code is handles the common shifting code and is used by both | |
6358 | * the vector and scalar code. | |
6359 | */ | |
6360 | static void handle_shri_with_rndacc(TCGv_i64 tcg_res, TCGv_i64 tcg_src, | |
6361 | TCGv_i64 tcg_rnd, bool accumulate, | |
6362 | bool is_u, int size, int shift) | |
6363 | { | |
6364 | bool extended_result = false; | |
6365 | bool round = !TCGV_IS_UNUSED_I64(tcg_rnd); | |
6366 | int ext_lshift = 0; | |
6367 | TCGv_i64 tcg_src_hi; | |
6368 | ||
6369 | if (round && size == 3) { | |
6370 | extended_result = true; | |
6371 | ext_lshift = 64 - shift; | |
6372 | tcg_src_hi = tcg_temp_new_i64(); | |
6373 | } else if (shift == 64) { | |
6374 | if (!accumulate && is_u) { | |
6375 | /* result is zero */ | |
6376 | tcg_gen_movi_i64(tcg_res, 0); | |
6377 | return; | |
6378 | } | |
6379 | } | |
6380 | ||
6381 | /* Deal with the rounding step */ | |
6382 | if (round) { | |
6383 | if (extended_result) { | |
6384 | TCGv_i64 tcg_zero = tcg_const_i64(0); | |
6385 | if (!is_u) { | |
6386 | /* take care of sign extending tcg_res */ | |
6387 | tcg_gen_sari_i64(tcg_src_hi, tcg_src, 63); | |
6388 | tcg_gen_add2_i64(tcg_src, tcg_src_hi, | |
6389 | tcg_src, tcg_src_hi, | |
6390 | tcg_rnd, tcg_zero); | |
6391 | } else { | |
6392 | tcg_gen_add2_i64(tcg_src, tcg_src_hi, | |
6393 | tcg_src, tcg_zero, | |
6394 | tcg_rnd, tcg_zero); | |
6395 | } | |
6396 | tcg_temp_free_i64(tcg_zero); | |
6397 | } else { | |
6398 | tcg_gen_add_i64(tcg_src, tcg_src, tcg_rnd); | |
6399 | } | |
6400 | } | |
6401 | ||
6402 | /* Now do the shift right */ | |
6403 | if (round && extended_result) { | |
6404 | /* extended case, >64 bit precision required */ | |
6405 | if (ext_lshift == 0) { | |
6406 | /* special case, only high bits matter */ | |
6407 | tcg_gen_mov_i64(tcg_src, tcg_src_hi); | |
6408 | } else { | |
6409 | tcg_gen_shri_i64(tcg_src, tcg_src, shift); | |
6410 | tcg_gen_shli_i64(tcg_src_hi, tcg_src_hi, ext_lshift); | |
6411 | tcg_gen_or_i64(tcg_src, tcg_src, tcg_src_hi); | |
6412 | } | |
6413 | } else { | |
6414 | if (is_u) { | |
6415 | if (shift == 64) { | |
6416 | /* essentially shifting in 64 zeros */ | |
6417 | tcg_gen_movi_i64(tcg_src, 0); | |
6418 | } else { | |
6419 | tcg_gen_shri_i64(tcg_src, tcg_src, shift); | |
6420 | } | |
6421 | } else { | |
6422 | if (shift == 64) { | |
6423 | /* effectively extending the sign-bit */ | |
6424 | tcg_gen_sari_i64(tcg_src, tcg_src, 63); | |
6425 | } else { | |
6426 | tcg_gen_sari_i64(tcg_src, tcg_src, shift); | |
6427 | } | |
6428 | } | |
6429 | } | |
6430 | ||
6431 | if (accumulate) { | |
6432 | tcg_gen_add_i64(tcg_res, tcg_res, tcg_src); | |
6433 | } else { | |
6434 | tcg_gen_mov_i64(tcg_res, tcg_src); | |
6435 | } | |
6436 | ||
6437 | if (extended_result) { | |
6438 | tcg_temp_free_i64(tcg_src_hi); | |
6439 | } | |
6440 | } | |
6441 | ||
6442 | /* Common SHL/SLI - Shift left with an optional insert */ | |
6443 | static void handle_shli_with_ins(TCGv_i64 tcg_res, TCGv_i64 tcg_src, | |
6444 | bool insert, int shift) | |
6445 | { | |
6446 | if (insert) { /* SLI */ | |
6447 | tcg_gen_deposit_i64(tcg_res, tcg_res, tcg_src, shift, 64 - shift); | |
6448 | } else { /* SHL */ | |
6449 | tcg_gen_shli_i64(tcg_res, tcg_src, shift); | |
6450 | } | |
6451 | } | |
6452 | ||
37a706ad PM |
6453 | /* SRI: shift right with insert */ |
6454 | static void handle_shri_with_ins(TCGv_i64 tcg_res, TCGv_i64 tcg_src, | |
6455 | int size, int shift) | |
6456 | { | |
6457 | int esize = 8 << size; | |
6458 | ||
6459 | /* shift count same as element size is valid but does nothing; | |
6460 | * special case to avoid potential shift by 64. | |
6461 | */ | |
6462 | if (shift != esize) { | |
6463 | tcg_gen_shri_i64(tcg_src, tcg_src, shift); | |
6464 | tcg_gen_deposit_i64(tcg_res, tcg_res, tcg_src, 0, esize - shift); | |
6465 | } | |
6466 | } | |
6467 | ||
4d1cef84 AB |
6468 | /* SSHR[RA]/USHR[RA] - Scalar shift right (optional rounding/accumulate) */ |
6469 | static void handle_scalar_simd_shri(DisasContext *s, | |
6470 | bool is_u, int immh, int immb, | |
6471 | int opcode, int rn, int rd) | |
6472 | { | |
6473 | const int size = 3; | |
6474 | int immhb = immh << 3 | immb; | |
6475 | int shift = 2 * (8 << size) - immhb; | |
6476 | bool accumulate = false; | |
6477 | bool round = false; | |
37a706ad | 6478 | bool insert = false; |
4d1cef84 AB |
6479 | TCGv_i64 tcg_rn; |
6480 | TCGv_i64 tcg_rd; | |
6481 | TCGv_i64 tcg_round; | |
6482 | ||
6483 | if (!extract32(immh, 3, 1)) { | |
6484 | unallocated_encoding(s); | |
6485 | return; | |
6486 | } | |
6487 | ||
8c6afa6a PM |
6488 | if (!fp_access_check(s)) { |
6489 | return; | |
6490 | } | |
6491 | ||
4d1cef84 AB |
6492 | switch (opcode) { |
6493 | case 0x02: /* SSRA / USRA (accumulate) */ | |
6494 | accumulate = true; | |
6495 | break; | |
6496 | case 0x04: /* SRSHR / URSHR (rounding) */ | |
6497 | round = true; | |
6498 | break; | |
6499 | case 0x06: /* SRSRA / URSRA (accum + rounding) */ | |
6500 | accumulate = round = true; | |
6501 | break; | |
37a706ad PM |
6502 | case 0x08: /* SRI */ |
6503 | insert = true; | |
6504 | break; | |
4d1cef84 AB |
6505 | } |
6506 | ||
6507 | if (round) { | |
6508 | uint64_t round_const = 1ULL << (shift - 1); | |
6509 | tcg_round = tcg_const_i64(round_const); | |
6510 | } else { | |
6511 | TCGV_UNUSED_I64(tcg_round); | |
6512 | } | |
6513 | ||
6514 | tcg_rn = read_fp_dreg(s, rn); | |
37a706ad | 6515 | tcg_rd = (accumulate || insert) ? read_fp_dreg(s, rd) : tcg_temp_new_i64(); |
4d1cef84 | 6516 | |
37a706ad PM |
6517 | if (insert) { |
6518 | handle_shri_with_ins(tcg_rd, tcg_rn, size, shift); | |
6519 | } else { | |
6520 | handle_shri_with_rndacc(tcg_rd, tcg_rn, tcg_round, | |
6521 | accumulate, is_u, size, shift); | |
6522 | } | |
4d1cef84 AB |
6523 | |
6524 | write_fp_dreg(s, rd, tcg_rd); | |
6525 | ||
6526 | tcg_temp_free_i64(tcg_rn); | |
6527 | tcg_temp_free_i64(tcg_rd); | |
6528 | if (round) { | |
6529 | tcg_temp_free_i64(tcg_round); | |
6530 | } | |
6531 | } | |
6532 | ||
6533 | /* SHL/SLI - Scalar shift left */ | |
6534 | static void handle_scalar_simd_shli(DisasContext *s, bool insert, | |
6535 | int immh, int immb, int opcode, | |
6536 | int rn, int rd) | |
6537 | { | |
6538 | int size = 32 - clz32(immh) - 1; | |
6539 | int immhb = immh << 3 | immb; | |
6540 | int shift = immhb - (8 << size); | |
6541 | TCGv_i64 tcg_rn = new_tmp_a64(s); | |
6542 | TCGv_i64 tcg_rd = new_tmp_a64(s); | |
6543 | ||
6544 | if (!extract32(immh, 3, 1)) { | |
6545 | unallocated_encoding(s); | |
6546 | return; | |
6547 | } | |
6548 | ||
8c6afa6a PM |
6549 | if (!fp_access_check(s)) { |
6550 | return; | |
6551 | } | |
6552 | ||
4d1cef84 AB |
6553 | tcg_rn = read_fp_dreg(s, rn); |
6554 | tcg_rd = insert ? read_fp_dreg(s, rd) : tcg_temp_new_i64(); | |
6555 | ||
6556 | handle_shli_with_ins(tcg_rd, tcg_rn, insert, shift); | |
6557 | ||
6558 | write_fp_dreg(s, rd, tcg_rd); | |
6559 | ||
6560 | tcg_temp_free_i64(tcg_rn); | |
6561 | tcg_temp_free_i64(tcg_rd); | |
6562 | } | |
6563 | ||
c1b876b2 AB |
6564 | /* SQSHRN/SQSHRUN - Saturating (signed/unsigned) shift right with |
6565 | * (signed/unsigned) narrowing */ | |
6566 | static void handle_vec_simd_sqshrn(DisasContext *s, bool is_scalar, bool is_q, | |
6567 | bool is_u_shift, bool is_u_narrow, | |
6568 | int immh, int immb, int opcode, | |
6569 | int rn, int rd) | |
6570 | { | |
6571 | int immhb = immh << 3 | immb; | |
6572 | int size = 32 - clz32(immh) - 1; | |
6573 | int esize = 8 << size; | |
6574 | int shift = (2 * esize) - immhb; | |
6575 | int elements = is_scalar ? 1 : (64 / esize); | |
6576 | bool round = extract32(opcode, 0, 1); | |
6577 | TCGMemOp ldop = (size + 1) | (is_u_shift ? 0 : MO_SIGN); | |
6578 | TCGv_i64 tcg_rn, tcg_rd, tcg_round; | |
6579 | TCGv_i32 tcg_rd_narrowed; | |
6580 | TCGv_i64 tcg_final; | |
6581 | ||
6582 | static NeonGenNarrowEnvFn * const signed_narrow_fns[4][2] = { | |
6583 | { gen_helper_neon_narrow_sat_s8, | |
6584 | gen_helper_neon_unarrow_sat8 }, | |
6585 | { gen_helper_neon_narrow_sat_s16, | |
6586 | gen_helper_neon_unarrow_sat16 }, | |
6587 | { gen_helper_neon_narrow_sat_s32, | |
6588 | gen_helper_neon_unarrow_sat32 }, | |
6589 | { NULL, NULL }, | |
6590 | }; | |
6591 | static NeonGenNarrowEnvFn * const unsigned_narrow_fns[4] = { | |
6592 | gen_helper_neon_narrow_sat_u8, | |
6593 | gen_helper_neon_narrow_sat_u16, | |
6594 | gen_helper_neon_narrow_sat_u32, | |
6595 | NULL | |
6596 | }; | |
6597 | NeonGenNarrowEnvFn *narrowfn; | |
6598 | ||
6599 | int i; | |
6600 | ||
6601 | assert(size < 4); | |
6602 | ||
6603 | if (extract32(immh, 3, 1)) { | |
6604 | unallocated_encoding(s); | |
6605 | return; | |
6606 | } | |
6607 | ||
8c6afa6a PM |
6608 | if (!fp_access_check(s)) { |
6609 | return; | |
6610 | } | |
6611 | ||
c1b876b2 AB |
6612 | if (is_u_shift) { |
6613 | narrowfn = unsigned_narrow_fns[size]; | |
6614 | } else { | |
6615 | narrowfn = signed_narrow_fns[size][is_u_narrow ? 1 : 0]; | |
6616 | } | |
6617 | ||
6618 | tcg_rn = tcg_temp_new_i64(); | |
6619 | tcg_rd = tcg_temp_new_i64(); | |
6620 | tcg_rd_narrowed = tcg_temp_new_i32(); | |
6621 | tcg_final = tcg_const_i64(0); | |
6622 | ||
6623 | if (round) { | |
6624 | uint64_t round_const = 1ULL << (shift - 1); | |
6625 | tcg_round = tcg_const_i64(round_const); | |
6626 | } else { | |
6627 | TCGV_UNUSED_I64(tcg_round); | |
6628 | } | |
6629 | ||
6630 | for (i = 0; i < elements; i++) { | |
6631 | read_vec_element(s, tcg_rn, rn, i, ldop); | |
6632 | handle_shri_with_rndacc(tcg_rd, tcg_rn, tcg_round, | |
6633 | false, is_u_shift, size+1, shift); | |
6634 | narrowfn(tcg_rd_narrowed, cpu_env, tcg_rd); | |
6635 | tcg_gen_extu_i32_i64(tcg_rd, tcg_rd_narrowed); | |
6636 | tcg_gen_deposit_i64(tcg_final, tcg_final, tcg_rd, esize * i, esize); | |
6637 | } | |
6638 | ||
6639 | if (!is_q) { | |
6640 | clear_vec_high(s, rd); | |
6641 | write_vec_element(s, tcg_final, rd, 0, MO_64); | |
6642 | } else { | |
6643 | write_vec_element(s, tcg_final, rd, 1, MO_64); | |
6644 | } | |
6645 | ||
6646 | if (round) { | |
6647 | tcg_temp_free_i64(tcg_round); | |
6648 | } | |
6649 | tcg_temp_free_i64(tcg_rn); | |
6650 | tcg_temp_free_i64(tcg_rd); | |
6651 | tcg_temp_free_i32(tcg_rd_narrowed); | |
6652 | tcg_temp_free_i64(tcg_final); | |
6653 | return; | |
6654 | } | |
6655 | ||
a847f32c PM |
6656 | /* SQSHLU, UQSHL, SQSHL: saturating left shifts */ |
6657 | static void handle_simd_qshl(DisasContext *s, bool scalar, bool is_q, | |
6658 | bool src_unsigned, bool dst_unsigned, | |
6659 | int immh, int immb, int rn, int rd) | |
6660 | { | |
6661 | int immhb = immh << 3 | immb; | |
6662 | int size = 32 - clz32(immh) - 1; | |
6663 | int shift = immhb - (8 << size); | |
6664 | int pass; | |
6665 | ||
6666 | assert(immh != 0); | |
6667 | assert(!(scalar && is_q)); | |
6668 | ||
6669 | if (!scalar) { | |
6670 | if (!is_q && extract32(immh, 3, 1)) { | |
6671 | unallocated_encoding(s); | |
6672 | return; | |
6673 | } | |
6674 | ||
6675 | /* Since we use the variable-shift helpers we must | |
6676 | * replicate the shift count into each element of | |
6677 | * the tcg_shift value. | |
6678 | */ | |
6679 | switch (size) { | |
6680 | case 0: | |
6681 | shift |= shift << 8; | |
6682 | /* fall through */ | |
6683 | case 1: | |
6684 | shift |= shift << 16; | |
6685 | break; | |
6686 | case 2: | |
6687 | case 3: | |
6688 | break; | |
6689 | default: | |
6690 | g_assert_not_reached(); | |
6691 | } | |
6692 | } | |
6693 | ||
8c6afa6a PM |
6694 | if (!fp_access_check(s)) { |
6695 | return; | |
6696 | } | |
6697 | ||
a847f32c PM |
6698 | if (size == 3) { |
6699 | TCGv_i64 tcg_shift = tcg_const_i64(shift); | |
6700 | static NeonGenTwo64OpEnvFn * const fns[2][2] = { | |
6701 | { gen_helper_neon_qshl_s64, gen_helper_neon_qshlu_s64 }, | |
6702 | { NULL, gen_helper_neon_qshl_u64 }, | |
6703 | }; | |
6704 | NeonGenTwo64OpEnvFn *genfn = fns[src_unsigned][dst_unsigned]; | |
6705 | int maxpass = is_q ? 2 : 1; | |
6706 | ||
6707 | for (pass = 0; pass < maxpass; pass++) { | |
6708 | TCGv_i64 tcg_op = tcg_temp_new_i64(); | |
6709 | ||
6710 | read_vec_element(s, tcg_op, rn, pass, MO_64); | |
6711 | genfn(tcg_op, cpu_env, tcg_op, tcg_shift); | |
6712 | write_vec_element(s, tcg_op, rd, pass, MO_64); | |
6713 | ||
6714 | tcg_temp_free_i64(tcg_op); | |
6715 | } | |
6716 | tcg_temp_free_i64(tcg_shift); | |
6717 | ||
6718 | if (!is_q) { | |
6719 | clear_vec_high(s, rd); | |
6720 | } | |
6721 | } else { | |
6722 | TCGv_i32 tcg_shift = tcg_const_i32(shift); | |
6723 | static NeonGenTwoOpEnvFn * const fns[2][2][3] = { | |
6724 | { | |
6725 | { gen_helper_neon_qshl_s8, | |
6726 | gen_helper_neon_qshl_s16, | |
6727 | gen_helper_neon_qshl_s32 }, | |
6728 | { gen_helper_neon_qshlu_s8, | |
6729 | gen_helper_neon_qshlu_s16, | |
6730 | gen_helper_neon_qshlu_s32 } | |
6731 | }, { | |
6732 | { NULL, NULL, NULL }, | |
6733 | { gen_helper_neon_qshl_u8, | |
6734 | gen_helper_neon_qshl_u16, | |
6735 | gen_helper_neon_qshl_u32 } | |
6736 | } | |
6737 | }; | |
6738 | NeonGenTwoOpEnvFn *genfn = fns[src_unsigned][dst_unsigned][size]; | |
6739 | TCGMemOp memop = scalar ? size : MO_32; | |
6740 | int maxpass = scalar ? 1 : is_q ? 4 : 2; | |
6741 | ||
6742 | for (pass = 0; pass < maxpass; pass++) { | |
6743 | TCGv_i32 tcg_op = tcg_temp_new_i32(); | |
6744 | ||
6745 | read_vec_element_i32(s, tcg_op, rn, pass, memop); | |
6746 | genfn(tcg_op, cpu_env, tcg_op, tcg_shift); | |
6747 | if (scalar) { | |
6748 | switch (size) { | |
6749 | case 0: | |
6750 | tcg_gen_ext8u_i32(tcg_op, tcg_op); | |
6751 | break; | |
6752 | case 1: | |
6753 | tcg_gen_ext16u_i32(tcg_op, tcg_op); | |
6754 | break; | |
6755 | case 2: | |
6756 | break; | |
6757 | default: | |
6758 | g_assert_not_reached(); | |
6759 | } | |
6760 | write_fp_sreg(s, rd, tcg_op); | |
6761 | } else { | |
6762 | write_vec_element_i32(s, tcg_op, rd, pass, MO_32); | |
6763 | } | |
6764 | ||
6765 | tcg_temp_free_i32(tcg_op); | |
6766 | } | |
6767 | tcg_temp_free_i32(tcg_shift); | |
6768 | ||
6769 | if (!is_q && !scalar) { | |
6770 | clear_vec_high(s, rd); | |
6771 | } | |
6772 | } | |
6773 | } | |
6774 | ||
10113b69 AB |
6775 | /* Common vector code for handling integer to FP conversion */ |
6776 | static void handle_simd_intfp_conv(DisasContext *s, int rd, int rn, | |
6777 | int elements, int is_signed, | |
6778 | int fracbits, int size) | |
6779 | { | |
6780 | bool is_double = size == 3 ? true : false; | |
6781 | TCGv_ptr tcg_fpst = get_fpstatus_ptr(); | |
6782 | TCGv_i32 tcg_shift = tcg_const_i32(fracbits); | |
6783 | TCGv_i64 tcg_int = tcg_temp_new_i64(); | |
6784 | TCGMemOp mop = size | (is_signed ? MO_SIGN : 0); | |
6785 | int pass; | |
6786 | ||
6787 | for (pass = 0; pass < elements; pass++) { | |
6788 | read_vec_element(s, tcg_int, rn, pass, mop); | |
6789 | ||
6790 | if (is_double) { | |
6791 | TCGv_i64 tcg_double = tcg_temp_new_i64(); | |
6792 | if (is_signed) { | |
6793 | gen_helper_vfp_sqtod(tcg_double, tcg_int, | |
6794 | tcg_shift, tcg_fpst); | |
6795 | } else { | |
6796 | gen_helper_vfp_uqtod(tcg_double, tcg_int, | |
6797 | tcg_shift, tcg_fpst); | |
6798 | } | |
6799 | if (elements == 1) { | |
6800 | write_fp_dreg(s, rd, tcg_double); | |
6801 | } else { | |
6802 | write_vec_element(s, tcg_double, rd, pass, MO_64); | |
6803 | } | |
6804 | tcg_temp_free_i64(tcg_double); | |
6805 | } else { | |
6806 | TCGv_i32 tcg_single = tcg_temp_new_i32(); | |
6807 | if (is_signed) { | |
6808 | gen_helper_vfp_sqtos(tcg_single, tcg_int, | |
6809 | tcg_shift, tcg_fpst); | |
6810 | } else { | |
6811 | gen_helper_vfp_uqtos(tcg_single, tcg_int, | |
6812 | tcg_shift, tcg_fpst); | |
6813 | } | |
6814 | if (elements == 1) { | |
6815 | write_fp_sreg(s, rd, tcg_single); | |
6816 | } else { | |
6817 | write_vec_element_i32(s, tcg_single, rd, pass, MO_32); | |
6818 | } | |
6819 | tcg_temp_free_i32(tcg_single); | |
6820 | } | |
6821 | } | |
6822 | ||
6823 | if (!is_double && elements == 2) { | |
6824 | clear_vec_high(s, rd); | |
6825 | } | |
6826 | ||
6827 | tcg_temp_free_i64(tcg_int); | |
6828 | tcg_temp_free_ptr(tcg_fpst); | |
6829 | tcg_temp_free_i32(tcg_shift); | |
6830 | } | |
6831 | ||
6832 | /* UCVTF/SCVTF - Integer to FP conversion */ | |
6833 | static void handle_simd_shift_intfp_conv(DisasContext *s, bool is_scalar, | |
6834 | bool is_q, bool is_u, | |
6835 | int immh, int immb, int opcode, | |
6836 | int rn, int rd) | |
6837 | { | |
6838 | bool is_double = extract32(immh, 3, 1); | |
6839 | int size = is_double ? MO_64 : MO_32; | |
6840 | int elements; | |
6841 | int immhb = immh << 3 | immb; | |
6842 | int fracbits = (is_double ? 128 : 64) - immhb; | |
6843 | ||
6844 | if (!extract32(immh, 2, 2)) { | |
6845 | unallocated_encoding(s); | |
6846 | return; | |
6847 | } | |
6848 | ||
6849 | if (is_scalar) { | |
6850 | elements = 1; | |
6851 | } else { | |
6852 | elements = is_double ? 2 : is_q ? 4 : 2; | |
6853 | if (is_double && !is_q) { | |
6854 | unallocated_encoding(s); | |
6855 | return; | |
6856 | } | |
6857 | } | |
8c6afa6a PM |
6858 | |
6859 | if (!fp_access_check(s)) { | |
6860 | return; | |
6861 | } | |
6862 | ||
10113b69 AB |
6863 | /* immh == 0 would be a failure of the decode logic */ |
6864 | g_assert(immh); | |
6865 | ||
6866 | handle_simd_intfp_conv(s, rd, rn, elements, !is_u, fracbits, size); | |
6867 | } | |
6868 | ||
2ed3ea11 PM |
6869 | /* FCVTZS, FVCVTZU - FP to fixedpoint conversion */ |
6870 | static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar, | |
6871 | bool is_q, bool is_u, | |
6872 | int immh, int immb, int rn, int rd) | |
6873 | { | |
6874 | bool is_double = extract32(immh, 3, 1); | |
6875 | int immhb = immh << 3 | immb; | |
6876 | int fracbits = (is_double ? 128 : 64) - immhb; | |
6877 | int pass; | |
6878 | TCGv_ptr tcg_fpstatus; | |
6879 | TCGv_i32 tcg_rmode, tcg_shift; | |
6880 | ||
6881 | if (!extract32(immh, 2, 2)) { | |
6882 | unallocated_encoding(s); | |
6883 | return; | |
6884 | } | |
6885 | ||
6886 | if (!is_scalar && !is_q && is_double) { | |
6887 | unallocated_encoding(s); | |
6888 | return; | |
6889 | } | |
6890 | ||
8c6afa6a PM |
6891 | if (!fp_access_check(s)) { |
6892 | return; | |
6893 | } | |
6894 | ||
2ed3ea11 PM |
6895 | assert(!(is_scalar && is_q)); |
6896 | ||
6897 | tcg_rmode = tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO)); | |
6898 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); | |
6899 | tcg_fpstatus = get_fpstatus_ptr(); | |
6900 | tcg_shift = tcg_const_i32(fracbits); | |
6901 | ||
6902 | if (is_double) { | |
4063452e | 6903 | int maxpass = is_scalar ? 1 : 2; |
2ed3ea11 PM |
6904 | |
6905 | for (pass = 0; pass < maxpass; pass++) { | |
6906 | TCGv_i64 tcg_op = tcg_temp_new_i64(); | |
6907 | ||
6908 | read_vec_element(s, tcg_op, rn, pass, MO_64); | |
6909 | if (is_u) { | |
6910 | gen_helper_vfp_touqd(tcg_op, tcg_op, tcg_shift, tcg_fpstatus); | |
6911 | } else { | |
6912 | gen_helper_vfp_tosqd(tcg_op, tcg_op, tcg_shift, tcg_fpstatus); | |
6913 | } | |
6914 | write_vec_element(s, tcg_op, rd, pass, MO_64); | |
6915 | tcg_temp_free_i64(tcg_op); | |
6916 | } | |
6917 | if (!is_q) { | |
6918 | clear_vec_high(s, rd); | |
6919 | } | |
6920 | } else { | |
6921 | int maxpass = is_scalar ? 1 : is_q ? 4 : 2; | |
6922 | for (pass = 0; pass < maxpass; pass++) { | |
6923 | TCGv_i32 tcg_op = tcg_temp_new_i32(); | |
6924 | ||
6925 | read_vec_element_i32(s, tcg_op, rn, pass, MO_32); | |
6926 | if (is_u) { | |
6927 | gen_helper_vfp_touls(tcg_op, tcg_op, tcg_shift, tcg_fpstatus); | |
6928 | } else { | |
6929 | gen_helper_vfp_tosls(tcg_op, tcg_op, tcg_shift, tcg_fpstatus); | |
6930 | } | |
6931 | if (is_scalar) { | |
6932 | write_fp_sreg(s, rd, tcg_op); | |
6933 | } else { | |
6934 | write_vec_element_i32(s, tcg_op, rd, pass, MO_32); | |
6935 | } | |
6936 | tcg_temp_free_i32(tcg_op); | |
6937 | } | |
6938 | if (!is_q && !is_scalar) { | |
6939 | clear_vec_high(s, rd); | |
6940 | } | |
6941 | } | |
6942 | ||
6943 | tcg_temp_free_ptr(tcg_fpstatus); | |
6944 | tcg_temp_free_i32(tcg_shift); | |
6945 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); | |
6946 | tcg_temp_free_i32(tcg_rmode); | |
6947 | } | |
6948 | ||
384b26fb AB |
6949 | /* C3.6.9 AdvSIMD scalar shift by immediate |
6950 | * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0 | |
6951 | * +-----+---+-------------+------+------+--------+---+------+------+ | |
6952 | * | 0 1 | U | 1 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd | | |
6953 | * +-----+---+-------------+------+------+--------+---+------+------+ | |
4d1cef84 AB |
6954 | * |
6955 | * This is the scalar version so it works on a fixed sized registers | |
384b26fb AB |
6956 | */ |
6957 | static void disas_simd_scalar_shift_imm(DisasContext *s, uint32_t insn) | |
6958 | { | |
4d1cef84 AB |
6959 | int rd = extract32(insn, 0, 5); |
6960 | int rn = extract32(insn, 5, 5); | |
6961 | int opcode = extract32(insn, 11, 5); | |
6962 | int immb = extract32(insn, 16, 3); | |
6963 | int immh = extract32(insn, 19, 4); | |
6964 | bool is_u = extract32(insn, 29, 1); | |
6965 | ||
c1b876b2 AB |
6966 | if (immh == 0) { |
6967 | unallocated_encoding(s); | |
6968 | return; | |
6969 | } | |
6970 | ||
4d1cef84 | 6971 | switch (opcode) { |
37a706ad PM |
6972 | case 0x08: /* SRI */ |
6973 | if (!is_u) { | |
6974 | unallocated_encoding(s); | |
6975 | return; | |
6976 | } | |
6977 | /* fall through */ | |
4d1cef84 AB |
6978 | case 0x00: /* SSHR / USHR */ |
6979 | case 0x02: /* SSRA / USRA */ | |
6980 | case 0x04: /* SRSHR / URSHR */ | |
6981 | case 0x06: /* SRSRA / URSRA */ | |
6982 | handle_scalar_simd_shri(s, is_u, immh, immb, opcode, rn, rd); | |
6983 | break; | |
6984 | case 0x0a: /* SHL / SLI */ | |
6985 | handle_scalar_simd_shli(s, is_u, immh, immb, opcode, rn, rd); | |
6986 | break; | |
10113b69 AB |
6987 | case 0x1c: /* SCVTF, UCVTF */ |
6988 | handle_simd_shift_intfp_conv(s, true, false, is_u, immh, immb, | |
6989 | opcode, rn, rd); | |
6990 | break; | |
c1b876b2 AB |
6991 | case 0x10: /* SQSHRUN, SQSHRUN2 */ |
6992 | case 0x11: /* SQRSHRUN, SQRSHRUN2 */ | |
6993 | if (!is_u) { | |
6994 | unallocated_encoding(s); | |
6995 | return; | |
6996 | } | |
6997 | handle_vec_simd_sqshrn(s, true, false, false, true, | |
6998 | immh, immb, opcode, rn, rd); | |
6999 | break; | |
7000 | case 0x12: /* SQSHRN, SQSHRN2, UQSHRN */ | |
7001 | case 0x13: /* SQRSHRN, SQRSHRN2, UQRSHRN, UQRSHRN2 */ | |
7002 | handle_vec_simd_sqshrn(s, true, false, is_u, is_u, | |
7003 | immh, immb, opcode, rn, rd); | |
7004 | break; | |
a566da1b | 7005 | case 0xc: /* SQSHLU */ |
a847f32c PM |
7006 | if (!is_u) { |
7007 | unallocated_encoding(s); | |
7008 | return; | |
7009 | } | |
7010 | handle_simd_qshl(s, true, false, false, true, immh, immb, rn, rd); | |
7011 | break; | |
a566da1b | 7012 | case 0xe: /* SQSHL, UQSHL */ |
a847f32c PM |
7013 | handle_simd_qshl(s, true, false, is_u, is_u, immh, immb, rn, rd); |
7014 | break; | |
a566da1b | 7015 | case 0x1f: /* FCVTZS, FCVTZU */ |
2ed3ea11 | 7016 | handle_simd_shift_fpint_conv(s, true, false, is_u, immh, immb, rn, rd); |
4d1cef84 | 7017 | break; |
a566da1b PM |
7018 | default: |
7019 | unallocated_encoding(s); | |
7020 | break; | |
4d1cef84 | 7021 | } |
384b26fb AB |
7022 | } |
7023 | ||
7024 | /* C3.6.10 AdvSIMD scalar three different | |
7025 | * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0 | |
7026 | * +-----+---+-----------+------+---+------+--------+-----+------+------+ | |
7027 | * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd | | |
7028 | * +-----+---+-----------+------+---+------+--------+-----+------+------+ | |
7029 | */ | |
7030 | static void disas_simd_scalar_three_reg_diff(DisasContext *s, uint32_t insn) | |
7031 | { | |
b033cd3d PM |
7032 | bool is_u = extract32(insn, 29, 1); |
7033 | int size = extract32(insn, 22, 2); | |
7034 | int opcode = extract32(insn, 12, 4); | |
7035 | int rm = extract32(insn, 16, 5); | |
7036 | int rn = extract32(insn, 5, 5); | |
7037 | int rd = extract32(insn, 0, 5); | |
7038 | ||
7039 | if (is_u) { | |
7040 | unallocated_encoding(s); | |
7041 | return; | |
7042 | } | |
7043 | ||
7044 | switch (opcode) { | |
7045 | case 0x9: /* SQDMLAL, SQDMLAL2 */ | |
7046 | case 0xb: /* SQDMLSL, SQDMLSL2 */ | |
7047 | case 0xd: /* SQDMULL, SQDMULL2 */ | |
7048 | if (size == 0 || size == 3) { | |
7049 | unallocated_encoding(s); | |
7050 | return; | |
7051 | } | |
7052 | break; | |
7053 | default: | |
7054 | unallocated_encoding(s); | |
7055 | return; | |
7056 | } | |
7057 | ||
8c6afa6a PM |
7058 | if (!fp_access_check(s)) { |
7059 | return; | |
7060 | } | |
7061 | ||
b033cd3d PM |
7062 | if (size == 2) { |
7063 | TCGv_i64 tcg_op1 = tcg_temp_new_i64(); | |
7064 | TCGv_i64 tcg_op2 = tcg_temp_new_i64(); | |
7065 | TCGv_i64 tcg_res = tcg_temp_new_i64(); | |
7066 | ||
7067 | read_vec_element(s, tcg_op1, rn, 0, MO_32 | MO_SIGN); | |
7068 | read_vec_element(s, tcg_op2, rm, 0, MO_32 | MO_SIGN); | |
7069 | ||
7070 | tcg_gen_mul_i64(tcg_res, tcg_op1, tcg_op2); | |
7071 | gen_helper_neon_addl_saturate_s64(tcg_res, cpu_env, tcg_res, tcg_res); | |
7072 | ||
7073 | switch (opcode) { | |
7074 | case 0xd: /* SQDMULL, SQDMULL2 */ | |
7075 | break; | |
7076 | case 0xb: /* SQDMLSL, SQDMLSL2 */ | |
7077 | tcg_gen_neg_i64(tcg_res, tcg_res); | |
7078 | /* fall through */ | |
7079 | case 0x9: /* SQDMLAL, SQDMLAL2 */ | |
7080 | read_vec_element(s, tcg_op1, rd, 0, MO_64); | |
7081 | gen_helper_neon_addl_saturate_s64(tcg_res, cpu_env, | |
7082 | tcg_res, tcg_op1); | |
7083 | break; | |
7084 | default: | |
7085 | g_assert_not_reached(); | |
7086 | } | |
7087 | ||
7088 | write_fp_dreg(s, rd, tcg_res); | |
7089 | ||
7090 | tcg_temp_free_i64(tcg_op1); | |
7091 | tcg_temp_free_i64(tcg_op2); | |
7092 | tcg_temp_free_i64(tcg_res); | |
7093 | } else { | |
7094 | TCGv_i32 tcg_op1 = tcg_temp_new_i32(); | |
7095 | TCGv_i32 tcg_op2 = tcg_temp_new_i32(); | |
7096 | TCGv_i64 tcg_res = tcg_temp_new_i64(); | |
7097 | ||
7098 | read_vec_element_i32(s, tcg_op1, rn, 0, MO_16); | |
7099 | read_vec_element_i32(s, tcg_op2, rm, 0, MO_16); | |
7100 | ||
7101 | gen_helper_neon_mull_s16(tcg_res, tcg_op1, tcg_op2); | |
7102 | gen_helper_neon_addl_saturate_s32(tcg_res, cpu_env, tcg_res, tcg_res); | |
7103 | ||
7104 | switch (opcode) { | |
7105 | case 0xd: /* SQDMULL, SQDMULL2 */ | |
7106 | break; | |
7107 | case 0xb: /* SQDMLSL, SQDMLSL2 */ | |
7108 | gen_helper_neon_negl_u32(tcg_res, tcg_res); | |
7109 | /* fall through */ | |
7110 | case 0x9: /* SQDMLAL, SQDMLAL2 */ | |
7111 | { | |
7112 | TCGv_i64 tcg_op3 = tcg_temp_new_i64(); | |
7113 | read_vec_element(s, tcg_op3, rd, 0, MO_32); | |
7114 | gen_helper_neon_addl_saturate_s32(tcg_res, cpu_env, | |
7115 | tcg_res, tcg_op3); | |
7116 | tcg_temp_free_i64(tcg_op3); | |
7117 | break; | |
7118 | } | |
7119 | default: | |
7120 | g_assert_not_reached(); | |
7121 | } | |
7122 | ||
7123 | tcg_gen_ext32u_i64(tcg_res, tcg_res); | |
7124 | write_fp_dreg(s, rd, tcg_res); | |
7125 | ||
7126 | tcg_temp_free_i32(tcg_op1); | |
7127 | tcg_temp_free_i32(tcg_op2); | |
7128 | tcg_temp_free_i64(tcg_res); | |
7129 | } | |
384b26fb AB |
7130 | } |
7131 | ||
b305dba6 PM |
7132 | static void handle_3same_64(DisasContext *s, int opcode, bool u, |
7133 | TCGv_i64 tcg_rd, TCGv_i64 tcg_rn, TCGv_i64 tcg_rm) | |
7134 | { | |
7135 | /* Handle 64x64->64 opcodes which are shared between the scalar | |
7136 | * and vector 3-same groups. We cover every opcode where size == 3 | |
7137 | * is valid in either the three-reg-same (integer, not pairwise) | |
7138 | * or scalar-three-reg-same groups. (Some opcodes are not yet | |
7139 | * implemented.) | |
7140 | */ | |
7141 | TCGCond cond; | |
7142 | ||
7143 | switch (opcode) { | |
6d9571f7 PM |
7144 | case 0x1: /* SQADD */ |
7145 | if (u) { | |
7146 | gen_helper_neon_qadd_u64(tcg_rd, cpu_env, tcg_rn, tcg_rm); | |
7147 | } else { | |
7148 | gen_helper_neon_qadd_s64(tcg_rd, cpu_env, tcg_rn, tcg_rm); | |
7149 | } | |
7150 | break; | |
7151 | case 0x5: /* SQSUB */ | |
7152 | if (u) { | |
7153 | gen_helper_neon_qsub_u64(tcg_rd, cpu_env, tcg_rn, tcg_rm); | |
7154 | } else { | |
7155 | gen_helper_neon_qsub_s64(tcg_rd, cpu_env, tcg_rn, tcg_rm); | |
7156 | } | |
7157 | break; | |
b305dba6 PM |
7158 | case 0x6: /* CMGT, CMHI */ |
7159 | /* 64 bit integer comparison, result = test ? (2^64 - 1) : 0. | |
7160 | * We implement this using setcond (test) and then negating. | |
7161 | */ | |
7162 | cond = u ? TCG_COND_GTU : TCG_COND_GT; | |
7163 | do_cmop: | |
7164 | tcg_gen_setcond_i64(cond, tcg_rd, tcg_rn, tcg_rm); | |
7165 | tcg_gen_neg_i64(tcg_rd, tcg_rd); | |
7166 | break; | |
7167 | case 0x7: /* CMGE, CMHS */ | |
7168 | cond = u ? TCG_COND_GEU : TCG_COND_GE; | |
7169 | goto do_cmop; | |
7170 | case 0x11: /* CMTST, CMEQ */ | |
7171 | if (u) { | |
7172 | cond = TCG_COND_EQ; | |
7173 | goto do_cmop; | |
7174 | } | |
7175 | /* CMTST : test is "if (X & Y != 0)". */ | |
7176 | tcg_gen_and_i64(tcg_rd, tcg_rn, tcg_rm); | |
7177 | tcg_gen_setcondi_i64(TCG_COND_NE, tcg_rd, tcg_rd, 0); | |
7178 | tcg_gen_neg_i64(tcg_rd, tcg_rd); | |
7179 | break; | |
6d9571f7 | 7180 | case 0x8: /* SSHL, USHL */ |
b305dba6 | 7181 | if (u) { |
6d9571f7 | 7182 | gen_helper_neon_shl_u64(tcg_rd, tcg_rn, tcg_rm); |
b305dba6 | 7183 | } else { |
6d9571f7 | 7184 | gen_helper_neon_shl_s64(tcg_rd, tcg_rn, tcg_rm); |
b305dba6 PM |
7185 | } |
7186 | break; | |
b305dba6 | 7187 | case 0x9: /* SQSHL, UQSHL */ |
6d9571f7 PM |
7188 | if (u) { |
7189 | gen_helper_neon_qshl_u64(tcg_rd, cpu_env, tcg_rn, tcg_rm); | |
7190 | } else { | |
7191 | gen_helper_neon_qshl_s64(tcg_rd, cpu_env, tcg_rn, tcg_rm); | |
7192 | } | |
7193 | break; | |
b305dba6 | 7194 | case 0xa: /* SRSHL, URSHL */ |
6d9571f7 PM |
7195 | if (u) { |
7196 | gen_helper_neon_rshl_u64(tcg_rd, tcg_rn, tcg_rm); | |
7197 | } else { | |
7198 | gen_helper_neon_rshl_s64(tcg_rd, tcg_rn, tcg_rm); | |
7199 | } | |
7200 | break; | |
b305dba6 | 7201 | case 0xb: /* SQRSHL, UQRSHL */ |
6d9571f7 PM |
7202 | if (u) { |
7203 | gen_helper_neon_qrshl_u64(tcg_rd, cpu_env, tcg_rn, tcg_rm); | |
7204 | } else { | |
7205 | gen_helper_neon_qrshl_s64(tcg_rd, cpu_env, tcg_rn, tcg_rm); | |
7206 | } | |
7207 | break; | |
7208 | case 0x10: /* ADD, SUB */ | |
7209 | if (u) { | |
7210 | tcg_gen_sub_i64(tcg_rd, tcg_rn, tcg_rm); | |
7211 | } else { | |
7212 | tcg_gen_add_i64(tcg_rd, tcg_rn, tcg_rm); | |
7213 | } | |
7214 | break; | |
b305dba6 PM |
7215 | default: |
7216 | g_assert_not_reached(); | |
7217 | } | |
7218 | } | |
7219 | ||
845ea09a PM |
7220 | /* Handle the 3-same-operands float operations; shared by the scalar |
7221 | * and vector encodings. The caller must filter out any encodings | |
7222 | * not allocated for the encoding it is dealing with. | |
7223 | */ | |
7224 | static void handle_3same_float(DisasContext *s, int size, int elements, | |
7225 | int fpopcode, int rd, int rn, int rm) | |
7226 | { | |
7227 | int pass; | |
7228 | TCGv_ptr fpst = get_fpstatus_ptr(); | |
7229 | ||
7230 | for (pass = 0; pass < elements; pass++) { | |
7231 | if (size) { | |
7232 | /* Double */ | |
7233 | TCGv_i64 tcg_op1 = tcg_temp_new_i64(); | |
7234 | TCGv_i64 tcg_op2 = tcg_temp_new_i64(); | |
7235 | TCGv_i64 tcg_res = tcg_temp_new_i64(); | |
7236 | ||
7237 | read_vec_element(s, tcg_op1, rn, pass, MO_64); | |
7238 | read_vec_element(s, tcg_op2, rm, pass, MO_64); | |
7239 | ||
7240 | switch (fpopcode) { | |
057d5f62 PM |
7241 | case 0x39: /* FMLS */ |
7242 | /* As usual for ARM, separate negation for fused multiply-add */ | |
7243 | gen_helper_vfp_negd(tcg_op1, tcg_op1); | |
7244 | /* fall through */ | |
7245 | case 0x19: /* FMLA */ | |
7246 | read_vec_element(s, tcg_res, rd, pass, MO_64); | |
7247 | gen_helper_vfp_muladdd(tcg_res, tcg_op1, tcg_op2, | |
7248 | tcg_res, fpst); | |
7249 | break; | |
845ea09a PM |
7250 | case 0x18: /* FMAXNM */ |
7251 | gen_helper_vfp_maxnumd(tcg_res, tcg_op1, tcg_op2, fpst); | |
7252 | break; | |
7253 | case 0x1a: /* FADD */ | |
7254 | gen_helper_vfp_addd(tcg_res, tcg_op1, tcg_op2, fpst); | |
7255 | break; | |
057d5f62 PM |
7256 | case 0x1b: /* FMULX */ |
7257 | gen_helper_vfp_mulxd(tcg_res, tcg_op1, tcg_op2, fpst); | |
7258 | break; | |
8908f4d1 AB |
7259 | case 0x1c: /* FCMEQ */ |
7260 | gen_helper_neon_ceq_f64(tcg_res, tcg_op1, tcg_op2, fpst); | |
7261 | break; | |
845ea09a PM |
7262 | case 0x1e: /* FMAX */ |
7263 | gen_helper_vfp_maxd(tcg_res, tcg_op1, tcg_op2, fpst); | |
7264 | break; | |
057d5f62 PM |
7265 | case 0x1f: /* FRECPS */ |
7266 | gen_helper_recpsf_f64(tcg_res, tcg_op1, tcg_op2, fpst); | |
7267 | break; | |
845ea09a PM |
7268 | case 0x38: /* FMINNM */ |
7269 | gen_helper_vfp_minnumd(tcg_res, tcg_op1, tcg_op2, fpst); | |
7270 | break; | |
7271 | case 0x3a: /* FSUB */ | |
7272 | gen_helper_vfp_subd(tcg_res, tcg_op1, tcg_op2, fpst); | |
7273 | break; | |
7274 | case 0x3e: /* FMIN */ | |
7275 | gen_helper_vfp_mind(tcg_res, tcg_op1, tcg_op2, fpst); | |
7276 | break; | |
057d5f62 PM |
7277 | case 0x3f: /* FRSQRTS */ |
7278 | gen_helper_rsqrtsf_f64(tcg_res, tcg_op1, tcg_op2, fpst); | |
7279 | break; | |
845ea09a PM |
7280 | case 0x5b: /* FMUL */ |
7281 | gen_helper_vfp_muld(tcg_res, tcg_op1, tcg_op2, fpst); | |
7282 | break; | |
8908f4d1 AB |
7283 | case 0x5c: /* FCMGE */ |
7284 | gen_helper_neon_cge_f64(tcg_res, tcg_op1, tcg_op2, fpst); | |
7285 | break; | |
057d5f62 PM |
7286 | case 0x5d: /* FACGE */ |
7287 | gen_helper_neon_acge_f64(tcg_res, tcg_op1, tcg_op2, fpst); | |
7288 | break; | |
845ea09a PM |
7289 | case 0x5f: /* FDIV */ |
7290 | gen_helper_vfp_divd(tcg_res, tcg_op1, tcg_op2, fpst); | |
7291 | break; | |
7292 | case 0x7a: /* FABD */ | |
7293 | gen_helper_vfp_subd(tcg_res, tcg_op1, tcg_op2, fpst); | |
7294 | gen_helper_vfp_absd(tcg_res, tcg_res); | |
7295 | break; | |
8908f4d1 AB |
7296 | case 0x7c: /* FCMGT */ |
7297 | gen_helper_neon_cgt_f64(tcg_res, tcg_op1, tcg_op2, fpst); | |
7298 | break; | |
057d5f62 PM |
7299 | case 0x7d: /* FACGT */ |
7300 | gen_helper_neon_acgt_f64(tcg_res, tcg_op1, tcg_op2, fpst); | |
7301 | break; | |
845ea09a PM |
7302 | default: |
7303 | g_assert_not_reached(); | |
7304 | } | |
7305 | ||
7306 | write_vec_element(s, tcg_res, rd, pass, MO_64); | |
7307 | ||
7308 | tcg_temp_free_i64(tcg_res); | |
7309 | tcg_temp_free_i64(tcg_op1); | |
7310 | tcg_temp_free_i64(tcg_op2); | |
7311 | } else { | |
7312 | /* Single */ | |
7313 | TCGv_i32 tcg_op1 = tcg_temp_new_i32(); | |
7314 | TCGv_i32 tcg_op2 = tcg_temp_new_i32(); | |
7315 | TCGv_i32 tcg_res = tcg_temp_new_i32(); | |
7316 | ||
7317 | read_vec_element_i32(s, tcg_op1, rn, pass, MO_32); | |
7318 | read_vec_element_i32(s, tcg_op2, rm, pass, MO_32); | |
7319 | ||
7320 | switch (fpopcode) { | |
057d5f62 PM |
7321 | case 0x39: /* FMLS */ |
7322 | /* As usual for ARM, separate negation for fused multiply-add */ | |
7323 | gen_helper_vfp_negs(tcg_op1, tcg_op1); | |
7324 | /* fall through */ | |
7325 | case 0x19: /* FMLA */ | |
7326 | read_vec_element_i32(s, tcg_res, rd, pass, MO_32); | |
7327 | gen_helper_vfp_muladds(tcg_res, tcg_op1, tcg_op2, | |
7328 | tcg_res, fpst); | |
7329 | break; | |
845ea09a PM |
7330 | case 0x1a: /* FADD */ |
7331 | gen_helper_vfp_adds(tcg_res, tcg_op1, tcg_op2, fpst); | |
7332 | break; | |
057d5f62 PM |
7333 | case 0x1b: /* FMULX */ |
7334 | gen_helper_vfp_mulxs(tcg_res, tcg_op1, tcg_op2, fpst); | |
7335 | break; | |
8908f4d1 AB |
7336 | case 0x1c: /* FCMEQ */ |
7337 | gen_helper_neon_ceq_f32(tcg_res, tcg_op1, tcg_op2, fpst); | |
7338 | break; | |
845ea09a PM |
7339 | case 0x1e: /* FMAX */ |
7340 | gen_helper_vfp_maxs(tcg_res, tcg_op1, tcg_op2, fpst); | |
7341 | break; | |
057d5f62 PM |
7342 | case 0x1f: /* FRECPS */ |
7343 | gen_helper_recpsf_f32(tcg_res, tcg_op1, tcg_op2, fpst); | |
7344 | break; | |
845ea09a PM |
7345 | case 0x18: /* FMAXNM */ |
7346 | gen_helper_vfp_maxnums(tcg_res, tcg_op1, tcg_op2, fpst); | |
7347 | break; | |
7348 | case 0x38: /* FMINNM */ | |
7349 | gen_helper_vfp_minnums(tcg_res, tcg_op1, tcg_op2, fpst); | |
7350 | break; | |
7351 | case 0x3a: /* FSUB */ | |
7352 | gen_helper_vfp_subs(tcg_res, tcg_op1, tcg_op2, fpst); | |
7353 | break; | |
7354 | case 0x3e: /* FMIN */ | |
7355 | gen_helper_vfp_mins(tcg_res, tcg_op1, tcg_op2, fpst); | |
7356 | break; | |
057d5f62 PM |
7357 | case 0x3f: /* FRSQRTS */ |
7358 | gen_helper_rsqrtsf_f32(tcg_res, tcg_op1, tcg_op2, fpst); | |
7359 | break; | |
845ea09a PM |
7360 | case 0x5b: /* FMUL */ |
7361 | gen_helper_vfp_muls(tcg_res, tcg_op1, tcg_op2, fpst); | |
7362 | break; | |
8908f4d1 AB |
7363 | case 0x5c: /* FCMGE */ |
7364 | gen_helper_neon_cge_f32(tcg_res, tcg_op1, tcg_op2, fpst); | |
7365 | break; | |
057d5f62 PM |
7366 | case 0x5d: /* FACGE */ |
7367 | gen_helper_neon_acge_f32(tcg_res, tcg_op1, tcg_op2, fpst); | |
7368 | break; | |
845ea09a PM |
7369 | case 0x5f: /* FDIV */ |
7370 | gen_helper_vfp_divs(tcg_res, tcg_op1, tcg_op2, fpst); | |
7371 | break; | |
7372 | case 0x7a: /* FABD */ | |
7373 | gen_helper_vfp_subs(tcg_res, tcg_op1, tcg_op2, fpst); | |
7374 | gen_helper_vfp_abss(tcg_res, tcg_res); | |
7375 | break; | |
8908f4d1 AB |
7376 | case 0x7c: /* FCMGT */ |
7377 | gen_helper_neon_cgt_f32(tcg_res, tcg_op1, tcg_op2, fpst); | |
7378 | break; | |
057d5f62 PM |
7379 | case 0x7d: /* FACGT */ |
7380 | gen_helper_neon_acgt_f32(tcg_res, tcg_op1, tcg_op2, fpst); | |
7381 | break; | |
845ea09a PM |
7382 | default: |
7383 | g_assert_not_reached(); | |
7384 | } | |
7385 | ||
7386 | if (elements == 1) { | |
7387 | /* scalar single so clear high part */ | |
7388 | TCGv_i64 tcg_tmp = tcg_temp_new_i64(); | |
7389 | ||
7390 | tcg_gen_extu_i32_i64(tcg_tmp, tcg_res); | |
7391 | write_vec_element(s, tcg_tmp, rd, pass, MO_64); | |
7392 | tcg_temp_free_i64(tcg_tmp); | |
7393 | } else { | |
7394 | write_vec_element_i32(s, tcg_res, rd, pass, MO_32); | |
7395 | } | |
7396 | ||
7397 | tcg_temp_free_i32(tcg_res); | |
7398 | tcg_temp_free_i32(tcg_op1); | |
7399 | tcg_temp_free_i32(tcg_op2); | |
7400 | } | |
7401 | } | |
7402 | ||
7403 | tcg_temp_free_ptr(fpst); | |
7404 | ||
7405 | if ((elements << size) < 4) { | |
7406 | /* scalar, or non-quad vector op */ | |
7407 | clear_vec_high(s, rd); | |
7408 | } | |
7409 | } | |
7410 | ||
384b26fb AB |
7411 | /* C3.6.11 AdvSIMD scalar three same |
7412 | * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0 | |
7413 | * +-----+---+-----------+------+---+------+--------+---+------+------+ | |
7414 | * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd | | |
7415 | * +-----+---+-----------+------+---+------+--------+---+------+------+ | |
7416 | */ | |
7417 | static void disas_simd_scalar_three_reg_same(DisasContext *s, uint32_t insn) | |
7418 | { | |
b305dba6 PM |
7419 | int rd = extract32(insn, 0, 5); |
7420 | int rn = extract32(insn, 5, 5); | |
7421 | int opcode = extract32(insn, 11, 5); | |
7422 | int rm = extract32(insn, 16, 5); | |
7423 | int size = extract32(insn, 22, 2); | |
7424 | bool u = extract32(insn, 29, 1); | |
b305dba6 PM |
7425 | TCGv_i64 tcg_rd; |
7426 | ||
7427 | if (opcode >= 0x18) { | |
7428 | /* Floating point: U, size[1] and opcode indicate operation */ | |
7429 | int fpopcode = opcode | (extract32(size, 1, 1) << 5) | (u << 6); | |
7430 | switch (fpopcode) { | |
7431 | case 0x1b: /* FMULX */ | |
b305dba6 PM |
7432 | case 0x1f: /* FRECPS */ |
7433 | case 0x3f: /* FRSQRTS */ | |
b305dba6 | 7434 | case 0x5d: /* FACGE */ |
b305dba6 | 7435 | case 0x7d: /* FACGT */ |
8908f4d1 AB |
7436 | case 0x1c: /* FCMEQ */ |
7437 | case 0x5c: /* FCMGE */ | |
7438 | case 0x7c: /* FCMGT */ | |
845ea09a PM |
7439 | case 0x7a: /* FABD */ |
7440 | break; | |
b305dba6 PM |
7441 | default: |
7442 | unallocated_encoding(s); | |
7443 | return; | |
7444 | } | |
845ea09a | 7445 | |
8c6afa6a PM |
7446 | if (!fp_access_check(s)) { |
7447 | return; | |
7448 | } | |
7449 | ||
845ea09a PM |
7450 | handle_3same_float(s, extract32(size, 0, 1), 1, fpopcode, rd, rn, rm); |
7451 | return; | |
b305dba6 PM |
7452 | } |
7453 | ||
7454 | switch (opcode) { | |
7455 | case 0x1: /* SQADD, UQADD */ | |
7456 | case 0x5: /* SQSUB, UQSUB */ | |
c0b2b5fa PM |
7457 | case 0x9: /* SQSHL, UQSHL */ |
7458 | case 0xb: /* SQRSHL, UQRSHL */ | |
7459 | break; | |
6d9571f7 PM |
7460 | case 0x8: /* SSHL, USHL */ |
7461 | case 0xa: /* SRSHL, URSHL */ | |
b305dba6 PM |
7462 | case 0x6: /* CMGT, CMHI */ |
7463 | case 0x7: /* CMGE, CMHS */ | |
7464 | case 0x11: /* CMTST, CMEQ */ | |
7465 | case 0x10: /* ADD, SUB (vector) */ | |
7466 | if (size != 3) { | |
7467 | unallocated_encoding(s); | |
7468 | return; | |
7469 | } | |
7470 | break; | |
b305dba6 PM |
7471 | case 0x16: /* SQDMULH, SQRDMULH (vector) */ |
7472 | if (size != 1 && size != 2) { | |
7473 | unallocated_encoding(s); | |
7474 | return; | |
7475 | } | |
c0b2b5fa | 7476 | break; |
b305dba6 PM |
7477 | default: |
7478 | unallocated_encoding(s); | |
7479 | return; | |
7480 | } | |
7481 | ||
8c6afa6a PM |
7482 | if (!fp_access_check(s)) { |
7483 | return; | |
7484 | } | |
7485 | ||
b305dba6 PM |
7486 | tcg_rd = tcg_temp_new_i64(); |
7487 | ||
c0b2b5fa PM |
7488 | if (size == 3) { |
7489 | TCGv_i64 tcg_rn = read_fp_dreg(s, rn); | |
7490 | TCGv_i64 tcg_rm = read_fp_dreg(s, rm); | |
7491 | ||
7492 | handle_3same_64(s, opcode, u, tcg_rd, tcg_rn, tcg_rm); | |
7493 | tcg_temp_free_i64(tcg_rn); | |
7494 | tcg_temp_free_i64(tcg_rm); | |
7495 | } else { | |
7496 | /* Do a single operation on the lowest element in the vector. | |
7497 | * We use the standard Neon helpers and rely on 0 OP 0 == 0 with | |
7498 | * no side effects for all these operations. | |
7499 | * OPTME: special-purpose helpers would avoid doing some | |
7500 | * unnecessary work in the helper for the 8 and 16 bit cases. | |
7501 | */ | |
7502 | NeonGenTwoOpEnvFn *genenvfn; | |
7503 | TCGv_i32 tcg_rn = tcg_temp_new_i32(); | |
7504 | TCGv_i32 tcg_rm = tcg_temp_new_i32(); | |
7505 | TCGv_i32 tcg_rd32 = tcg_temp_new_i32(); | |
7506 | ||
7507 | read_vec_element_i32(s, tcg_rn, rn, 0, size); | |
7508 | read_vec_element_i32(s, tcg_rm, rm, 0, size); | |
7509 | ||
7510 | switch (opcode) { | |
7511 | case 0x1: /* SQADD, UQADD */ | |
7512 | { | |
7513 | static NeonGenTwoOpEnvFn * const fns[3][2] = { | |
7514 | { gen_helper_neon_qadd_s8, gen_helper_neon_qadd_u8 }, | |
7515 | { gen_helper_neon_qadd_s16, gen_helper_neon_qadd_u16 }, | |
7516 | { gen_helper_neon_qadd_s32, gen_helper_neon_qadd_u32 }, | |
7517 | }; | |
7518 | genenvfn = fns[size][u]; | |
7519 | break; | |
7520 | } | |
7521 | case 0x5: /* SQSUB, UQSUB */ | |
7522 | { | |
7523 | static NeonGenTwoOpEnvFn * const fns[3][2] = { | |
7524 | { gen_helper_neon_qsub_s8, gen_helper_neon_qsub_u8 }, | |
7525 | { gen_helper_neon_qsub_s16, gen_helper_neon_qsub_u16 }, | |
7526 | { gen_helper_neon_qsub_s32, gen_helper_neon_qsub_u32 }, | |
7527 | }; | |
7528 | genenvfn = fns[size][u]; | |
7529 | break; | |
7530 | } | |
7531 | case 0x9: /* SQSHL, UQSHL */ | |
7532 | { | |
7533 | static NeonGenTwoOpEnvFn * const fns[3][2] = { | |
7534 | { gen_helper_neon_qshl_s8, gen_helper_neon_qshl_u8 }, | |
7535 | { gen_helper_neon_qshl_s16, gen_helper_neon_qshl_u16 }, | |
7536 | { gen_helper_neon_qshl_s32, gen_helper_neon_qshl_u32 }, | |
7537 | }; | |
7538 | genenvfn = fns[size][u]; | |
7539 | break; | |
7540 | } | |
7541 | case 0xb: /* SQRSHL, UQRSHL */ | |
7542 | { | |
7543 | static NeonGenTwoOpEnvFn * const fns[3][2] = { | |
7544 | { gen_helper_neon_qrshl_s8, gen_helper_neon_qrshl_u8 }, | |
7545 | { gen_helper_neon_qrshl_s16, gen_helper_neon_qrshl_u16 }, | |
7546 | { gen_helper_neon_qrshl_s32, gen_helper_neon_qrshl_u32 }, | |
7547 | }; | |
7548 | genenvfn = fns[size][u]; | |
7549 | break; | |
7550 | } | |
7551 | case 0x16: /* SQDMULH, SQRDMULH */ | |
7552 | { | |
7553 | static NeonGenTwoOpEnvFn * const fns[2][2] = { | |
7554 | { gen_helper_neon_qdmulh_s16, gen_helper_neon_qrdmulh_s16 }, | |
7555 | { gen_helper_neon_qdmulh_s32, gen_helper_neon_qrdmulh_s32 }, | |
7556 | }; | |
7557 | assert(size == 1 || size == 2); | |
7558 | genenvfn = fns[size - 1][u]; | |
7559 | break; | |
7560 | } | |
7561 | default: | |
7562 | g_assert_not_reached(); | |
7563 | } | |
7564 | ||
7565 | genenvfn(tcg_rd32, cpu_env, tcg_rn, tcg_rm); | |
7566 | tcg_gen_extu_i32_i64(tcg_rd, tcg_rd32); | |
7567 | tcg_temp_free_i32(tcg_rd32); | |
7568 | tcg_temp_free_i32(tcg_rn); | |
7569 | tcg_temp_free_i32(tcg_rm); | |
7570 | } | |
b305dba6 PM |
7571 | |
7572 | write_fp_dreg(s, rd, tcg_rd); | |
7573 | ||
b305dba6 | 7574 | tcg_temp_free_i64(tcg_rd); |
384b26fb AB |
7575 | } |
7576 | ||
effa8e06 | 7577 | static void handle_2misc_64(DisasContext *s, int opcode, bool u, |
04c7c6c2 PM |
7578 | TCGv_i64 tcg_rd, TCGv_i64 tcg_rn, |
7579 | TCGv_i32 tcg_rmode, TCGv_ptr tcg_fpstatus) | |
effa8e06 PM |
7580 | { |
7581 | /* Handle 64->64 opcodes which are shared between the scalar and | |
7582 | * vector 2-reg-misc groups. We cover every integer opcode where size == 3 | |
f93d0138 | 7583 | * is valid in either group and also the double-precision fp ops. |
04c7c6c2 PM |
7584 | * The caller only need provide tcg_rmode and tcg_fpstatus if the op |
7585 | * requires them. | |
effa8e06 PM |
7586 | */ |
7587 | TCGCond cond; | |
7588 | ||
7589 | switch (opcode) { | |
b05c3068 AB |
7590 | case 0x4: /* CLS, CLZ */ |
7591 | if (u) { | |
7539a012 | 7592 | tcg_gen_clzi_i64(tcg_rd, tcg_rn, 64); |
b05c3068 | 7593 | } else { |
bc21dbcc | 7594 | tcg_gen_clrsb_i64(tcg_rd, tcg_rn); |
b05c3068 AB |
7595 | } |
7596 | break; | |
86cbc418 PM |
7597 | case 0x5: /* NOT */ |
7598 | /* This opcode is shared with CNT and RBIT but we have earlier | |
7599 | * enforced that size == 3 if and only if this is the NOT insn. | |
7600 | */ | |
7601 | tcg_gen_not_i64(tcg_rd, tcg_rn); | |
7602 | break; | |
0a79bc87 AB |
7603 | case 0x7: /* SQABS, SQNEG */ |
7604 | if (u) { | |
7605 | gen_helper_neon_qneg_s64(tcg_rd, cpu_env, tcg_rn); | |
7606 | } else { | |
7607 | gen_helper_neon_qabs_s64(tcg_rd, cpu_env, tcg_rn); | |
7608 | } | |
7609 | break; | |
effa8e06 PM |
7610 | case 0xa: /* CMLT */ |
7611 | /* 64 bit integer comparison against zero, result is | |
7612 | * test ? (2^64 - 1) : 0. We implement via setcond(!test) and | |
7613 | * subtracting 1. | |
7614 | */ | |
7615 | cond = TCG_COND_LT; | |
7616 | do_cmop: | |
7617 | tcg_gen_setcondi_i64(cond, tcg_rd, tcg_rn, 0); | |
7618 | tcg_gen_neg_i64(tcg_rd, tcg_rd); | |
7619 | break; | |
7620 | case 0x8: /* CMGT, CMGE */ | |
7621 | cond = u ? TCG_COND_GE : TCG_COND_GT; | |
7622 | goto do_cmop; | |
7623 | case 0x9: /* CMEQ, CMLE */ | |
7624 | cond = u ? TCG_COND_LE : TCG_COND_EQ; | |
7625 | goto do_cmop; | |
7626 | case 0xb: /* ABS, NEG */ | |
7627 | if (u) { | |
7628 | tcg_gen_neg_i64(tcg_rd, tcg_rn); | |
7629 | } else { | |
7630 | TCGv_i64 tcg_zero = tcg_const_i64(0); | |
7631 | tcg_gen_neg_i64(tcg_rd, tcg_rn); | |
7632 | tcg_gen_movcond_i64(TCG_COND_GT, tcg_rd, tcg_rn, tcg_zero, | |
7633 | tcg_rn, tcg_rd); | |
7634 | tcg_temp_free_i64(tcg_zero); | |
7635 | } | |
7636 | break; | |
f93d0138 PM |
7637 | case 0x2f: /* FABS */ |
7638 | gen_helper_vfp_absd(tcg_rd, tcg_rn); | |
7639 | break; | |
7640 | case 0x6f: /* FNEG */ | |
7641 | gen_helper_vfp_negd(tcg_rd, tcg_rn); | |
7642 | break; | |
f612537e AB |
7643 | case 0x7f: /* FSQRT */ |
7644 | gen_helper_vfp_sqrtd(tcg_rd, tcg_rn, cpu_env); | |
7645 | break; | |
04c7c6c2 PM |
7646 | case 0x1a: /* FCVTNS */ |
7647 | case 0x1b: /* FCVTMS */ | |
7648 | case 0x1c: /* FCVTAS */ | |
7649 | case 0x3a: /* FCVTPS */ | |
7650 | case 0x3b: /* FCVTZS */ | |
7651 | { | |
7652 | TCGv_i32 tcg_shift = tcg_const_i32(0); | |
7653 | gen_helper_vfp_tosqd(tcg_rd, tcg_rn, tcg_shift, tcg_fpstatus); | |
7654 | tcg_temp_free_i32(tcg_shift); | |
7655 | break; | |
7656 | } | |
7657 | case 0x5a: /* FCVTNU */ | |
7658 | case 0x5b: /* FCVTMU */ | |
7659 | case 0x5c: /* FCVTAU */ | |
7660 | case 0x7a: /* FCVTPU */ | |
7661 | case 0x7b: /* FCVTZU */ | |
7662 | { | |
7663 | TCGv_i32 tcg_shift = tcg_const_i32(0); | |
7664 | gen_helper_vfp_touqd(tcg_rd, tcg_rn, tcg_shift, tcg_fpstatus); | |
7665 | tcg_temp_free_i32(tcg_shift); | |
7666 | break; | |
7667 | } | |
03df01ed PM |
7668 | case 0x18: /* FRINTN */ |
7669 | case 0x19: /* FRINTM */ | |
7670 | case 0x38: /* FRINTP */ | |
7671 | case 0x39: /* FRINTZ */ | |
7672 | case 0x58: /* FRINTA */ | |
7673 | case 0x79: /* FRINTI */ | |
7674 | gen_helper_rintd(tcg_rd, tcg_rn, tcg_fpstatus); | |
7675 | break; | |
7676 | case 0x59: /* FRINTX */ | |
7677 | gen_helper_rintd_exact(tcg_rd, tcg_rn, tcg_fpstatus); | |
7678 | break; | |
effa8e06 PM |
7679 | default: |
7680 | g_assert_not_reached(); | |
7681 | } | |
7682 | } | |
7683 | ||
8908f4d1 AB |
7684 | static void handle_2misc_fcmp_zero(DisasContext *s, int opcode, |
7685 | bool is_scalar, bool is_u, bool is_q, | |
7686 | int size, int rn, int rd) | |
7687 | { | |
7688 | bool is_double = (size == 3); | |
8c6afa6a PM |
7689 | TCGv_ptr fpst; |
7690 | ||
7691 | if (!fp_access_check(s)) { | |
7692 | return; | |
7693 | } | |
7694 | ||
7695 | fpst = get_fpstatus_ptr(); | |
8908f4d1 AB |
7696 | |
7697 | if (is_double) { | |
7698 | TCGv_i64 tcg_op = tcg_temp_new_i64(); | |
7699 | TCGv_i64 tcg_zero = tcg_const_i64(0); | |
7700 | TCGv_i64 tcg_res = tcg_temp_new_i64(); | |
7701 | NeonGenTwoDoubleOPFn *genfn; | |
7702 | bool swap = false; | |
7703 | int pass; | |
7704 | ||
7705 | switch (opcode) { | |
7706 | case 0x2e: /* FCMLT (zero) */ | |
7707 | swap = true; | |
7708 | /* fallthrough */ | |
7709 | case 0x2c: /* FCMGT (zero) */ | |
7710 | genfn = gen_helper_neon_cgt_f64; | |
7711 | break; | |
7712 | case 0x2d: /* FCMEQ (zero) */ | |
7713 | genfn = gen_helper_neon_ceq_f64; | |
7714 | break; | |
7715 | case 0x6d: /* FCMLE (zero) */ | |
7716 | swap = true; | |
7717 | /* fall through */ | |
7718 | case 0x6c: /* FCMGE (zero) */ | |
7719 | genfn = gen_helper_neon_cge_f64; | |
7720 | break; | |
7721 | default: | |
7722 | g_assert_not_reached(); | |
7723 | } | |
7724 | ||
7725 | for (pass = 0; pass < (is_scalar ? 1 : 2); pass++) { | |
7726 | read_vec_element(s, tcg_op, rn, pass, MO_64); | |
7727 | if (swap) { | |
7728 | genfn(tcg_res, tcg_zero, tcg_op, fpst); | |
7729 | } else { | |
7730 | genfn(tcg_res, tcg_op, tcg_zero, fpst); | |
7731 | } | |
7732 | write_vec_element(s, tcg_res, rd, pass, MO_64); | |
7733 | } | |
7734 | if (is_scalar) { | |
7735 | clear_vec_high(s, rd); | |
7736 | } | |
7737 | ||
7738 | tcg_temp_free_i64(tcg_res); | |
7739 | tcg_temp_free_i64(tcg_zero); | |
7740 | tcg_temp_free_i64(tcg_op); | |
7741 | } else { | |
7742 | TCGv_i32 tcg_op = tcg_temp_new_i32(); | |
7743 | TCGv_i32 tcg_zero = tcg_const_i32(0); | |
7744 | TCGv_i32 tcg_res = tcg_temp_new_i32(); | |
7745 | NeonGenTwoSingleOPFn *genfn; | |
7746 | bool swap = false; | |
7747 | int pass, maxpasses; | |
7748 | ||
7749 | switch (opcode) { | |
7750 | case 0x2e: /* FCMLT (zero) */ | |
7751 | swap = true; | |
7752 | /* fall through */ | |
7753 | case 0x2c: /* FCMGT (zero) */ | |
7754 | genfn = gen_helper_neon_cgt_f32; | |
7755 | break; | |
7756 | case 0x2d: /* FCMEQ (zero) */ | |
7757 | genfn = gen_helper_neon_ceq_f32; | |
7758 | break; | |
7759 | case 0x6d: /* FCMLE (zero) */ | |
7760 | swap = true; | |
7761 | /* fall through */ | |
7762 | case 0x6c: /* FCMGE (zero) */ | |
7763 | genfn = gen_helper_neon_cge_f32; | |
7764 | break; | |
7765 | default: | |
7766 | g_assert_not_reached(); | |
7767 | } | |
7768 | ||
7769 | if (is_scalar) { | |
7770 | maxpasses = 1; | |
7771 | } else { | |
7772 | maxpasses = is_q ? 4 : 2; | |
7773 | } | |
7774 | ||
7775 | for (pass = 0; pass < maxpasses; pass++) { | |
7776 | read_vec_element_i32(s, tcg_op, rn, pass, MO_32); | |
7777 | if (swap) { | |
7778 | genfn(tcg_res, tcg_zero, tcg_op, fpst); | |
7779 | } else { | |
7780 | genfn(tcg_res, tcg_op, tcg_zero, fpst); | |
7781 | } | |
7782 | if (is_scalar) { | |
7783 | write_fp_sreg(s, rd, tcg_res); | |
7784 | } else { | |
7785 | write_vec_element_i32(s, tcg_res, rd, pass, MO_32); | |
7786 | } | |
7787 | } | |
7788 | tcg_temp_free_i32(tcg_res); | |
7789 | tcg_temp_free_i32(tcg_zero); | |
7790 | tcg_temp_free_i32(tcg_op); | |
7791 | if (!is_q && !is_scalar) { | |
7792 | clear_vec_high(s, rd); | |
7793 | } | |
7794 | } | |
7795 | ||
7796 | tcg_temp_free_ptr(fpst); | |
7797 | } | |
7798 | ||
8f0c6758 AB |
7799 | static void handle_2misc_reciprocal(DisasContext *s, int opcode, |
7800 | bool is_scalar, bool is_u, bool is_q, | |
7801 | int size, int rn, int rd) | |
7802 | { | |
7803 | bool is_double = (size == 3); | |
7804 | TCGv_ptr fpst = get_fpstatus_ptr(); | |
7805 | ||
7806 | if (is_double) { | |
7807 | TCGv_i64 tcg_op = tcg_temp_new_i64(); | |
7808 | TCGv_i64 tcg_res = tcg_temp_new_i64(); | |
7809 | int pass; | |
7810 | ||
7811 | for (pass = 0; pass < (is_scalar ? 1 : 2); pass++) { | |
7812 | read_vec_element(s, tcg_op, rn, pass, MO_64); | |
7813 | switch (opcode) { | |
b6d4443a AB |
7814 | case 0x3d: /* FRECPE */ |
7815 | gen_helper_recpe_f64(tcg_res, tcg_op, fpst); | |
7816 | break; | |
8f0c6758 AB |
7817 | case 0x3f: /* FRECPX */ |
7818 | gen_helper_frecpx_f64(tcg_res, tcg_op, fpst); | |
7819 | break; | |
c2fb418e AB |
7820 | case 0x7d: /* FRSQRTE */ |
7821 | gen_helper_rsqrte_f64(tcg_res, tcg_op, fpst); | |
7822 | break; | |
8f0c6758 AB |
7823 | default: |
7824 | g_assert_not_reached(); | |
7825 | } | |
7826 | write_vec_element(s, tcg_res, rd, pass, MO_64); | |
7827 | } | |
7828 | if (is_scalar) { | |
7829 | clear_vec_high(s, rd); | |
7830 | } | |
7831 | ||
7832 | tcg_temp_free_i64(tcg_res); | |
7833 | tcg_temp_free_i64(tcg_op); | |
7834 | } else { | |
7835 | TCGv_i32 tcg_op = tcg_temp_new_i32(); | |
7836 | TCGv_i32 tcg_res = tcg_temp_new_i32(); | |
7837 | int pass, maxpasses; | |
7838 | ||
7839 | if (is_scalar) { | |
7840 | maxpasses = 1; | |
7841 | } else { | |
7842 | maxpasses = is_q ? 4 : 2; | |
7843 | } | |
7844 | ||
7845 | for (pass = 0; pass < maxpasses; pass++) { | |
7846 | read_vec_element_i32(s, tcg_op, rn, pass, MO_32); | |
7847 | ||
7848 | switch (opcode) { | |
b6d4443a AB |
7849 | case 0x3c: /* URECPE */ |
7850 | gen_helper_recpe_u32(tcg_res, tcg_op, fpst); | |
7851 | break; | |
7852 | case 0x3d: /* FRECPE */ | |
7853 | gen_helper_recpe_f32(tcg_res, tcg_op, fpst); | |
7854 | break; | |
8f0c6758 AB |
7855 | case 0x3f: /* FRECPX */ |
7856 | gen_helper_frecpx_f32(tcg_res, tcg_op, fpst); | |
7857 | break; | |
c2fb418e AB |
7858 | case 0x7d: /* FRSQRTE */ |
7859 | gen_helper_rsqrte_f32(tcg_res, tcg_op, fpst); | |
7860 | break; | |
8f0c6758 AB |
7861 | default: |
7862 | g_assert_not_reached(); | |
7863 | } | |
7864 | ||
7865 | if (is_scalar) { | |
7866 | write_fp_sreg(s, rd, tcg_res); | |
7867 | } else { | |
7868 | write_vec_element_i32(s, tcg_res, rd, pass, MO_32); | |
7869 | } | |
7870 | } | |
7871 | tcg_temp_free_i32(tcg_res); | |
7872 | tcg_temp_free_i32(tcg_op); | |
7873 | if (!is_q && !is_scalar) { | |
7874 | clear_vec_high(s, rd); | |
7875 | } | |
7876 | } | |
7877 | tcg_temp_free_ptr(fpst); | |
7878 | } | |
7879 | ||
5201c136 AB |
7880 | static void handle_2misc_narrow(DisasContext *s, bool scalar, |
7881 | int opcode, bool u, bool is_q, | |
8b092ca9 AB |
7882 | int size, int rn, int rd) |
7883 | { | |
7884 | /* Handle 2-reg-misc ops which are narrowing (so each 2*size element | |
7885 | * in the source becomes a size element in the destination). | |
7886 | */ | |
7887 | int pass; | |
7888 | TCGv_i32 tcg_res[2]; | |
7889 | int destelt = is_q ? 2 : 0; | |
5201c136 | 7890 | int passes = scalar ? 1 : 2; |
8b092ca9 | 7891 | |
5201c136 AB |
7892 | if (scalar) { |
7893 | tcg_res[1] = tcg_const_i32(0); | |
7894 | } | |
7895 | ||
7896 | for (pass = 0; pass < passes; pass++) { | |
8b092ca9 AB |
7897 | TCGv_i64 tcg_op = tcg_temp_new_i64(); |
7898 | NeonGenNarrowFn *genfn = NULL; | |
7899 | NeonGenNarrowEnvFn *genenvfn = NULL; | |
7900 | ||
5201c136 AB |
7901 | if (scalar) { |
7902 | read_vec_element(s, tcg_op, rn, pass, size + 1); | |
7903 | } else { | |
7904 | read_vec_element(s, tcg_op, rn, pass, MO_64); | |
7905 | } | |
8b092ca9 AB |
7906 | tcg_res[pass] = tcg_temp_new_i32(); |
7907 | ||
7908 | switch (opcode) { | |
7909 | case 0x12: /* XTN, SQXTUN */ | |
7910 | { | |
7911 | static NeonGenNarrowFn * const xtnfns[3] = { | |
7912 | gen_helper_neon_narrow_u8, | |
7913 | gen_helper_neon_narrow_u16, | |
ecc7b3aa | 7914 | tcg_gen_extrl_i64_i32, |
8b092ca9 AB |
7915 | }; |
7916 | static NeonGenNarrowEnvFn * const sqxtunfns[3] = { | |
7917 | gen_helper_neon_unarrow_sat8, | |
7918 | gen_helper_neon_unarrow_sat16, | |
7919 | gen_helper_neon_unarrow_sat32, | |
7920 | }; | |
7921 | if (u) { | |
7922 | genenvfn = sqxtunfns[size]; | |
7923 | } else { | |
7924 | genfn = xtnfns[size]; | |
7925 | } | |
7926 | break; | |
7927 | } | |
7928 | case 0x14: /* SQXTN, UQXTN */ | |
7929 | { | |
7930 | static NeonGenNarrowEnvFn * const fns[3][2] = { | |
7931 | { gen_helper_neon_narrow_sat_s8, | |
7932 | gen_helper_neon_narrow_sat_u8 }, | |
7933 | { gen_helper_neon_narrow_sat_s16, | |
7934 | gen_helper_neon_narrow_sat_u16 }, | |
7935 | { gen_helper_neon_narrow_sat_s32, | |
7936 | gen_helper_neon_narrow_sat_u32 }, | |
7937 | }; | |
7938 | genenvfn = fns[size][u]; | |
7939 | break; | |
7940 | } | |
7941 | case 0x16: /* FCVTN, FCVTN2 */ | |
7942 | /* 32 bit to 16 bit or 64 bit to 32 bit float conversion */ | |
7943 | if (size == 2) { | |
7944 | gen_helper_vfp_fcvtsd(tcg_res[pass], tcg_op, cpu_env); | |
7945 | } else { | |
7946 | TCGv_i32 tcg_lo = tcg_temp_new_i32(); | |
7947 | TCGv_i32 tcg_hi = tcg_temp_new_i32(); | |
7cb36e18 | 7948 | tcg_gen_extr_i64_i32(tcg_lo, tcg_hi, tcg_op); |
8b092ca9 | 7949 | gen_helper_vfp_fcvt_f32_to_f16(tcg_lo, tcg_lo, cpu_env); |
8b092ca9 AB |
7950 | gen_helper_vfp_fcvt_f32_to_f16(tcg_hi, tcg_hi, cpu_env); |
7951 | tcg_gen_deposit_i32(tcg_res[pass], tcg_lo, tcg_hi, 16, 16); | |
7952 | tcg_temp_free_i32(tcg_lo); | |
7953 | tcg_temp_free_i32(tcg_hi); | |
7954 | } | |
7955 | break; | |
5553955e PM |
7956 | case 0x56: /* FCVTXN, FCVTXN2 */ |
7957 | /* 64 bit to 32 bit float conversion | |
7958 | * with von Neumann rounding (round to odd) | |
7959 | */ | |
7960 | assert(size == 2); | |
7961 | gen_helper_fcvtx_f64_to_f32(tcg_res[pass], tcg_op, cpu_env); | |
7962 | break; | |
8b092ca9 AB |
7963 | default: |
7964 | g_assert_not_reached(); | |
7965 | } | |
7966 | ||
7967 | if (genfn) { | |
7968 | genfn(tcg_res[pass], tcg_op); | |
7969 | } else if (genenvfn) { | |
7970 | genenvfn(tcg_res[pass], cpu_env, tcg_op); | |
7971 | } | |
7972 | ||
7973 | tcg_temp_free_i64(tcg_op); | |
7974 | } | |
7975 | ||
7976 | for (pass = 0; pass < 2; pass++) { | |
7977 | write_vec_element_i32(s, tcg_res[pass], rd, destelt + pass, MO_32); | |
7978 | tcg_temp_free_i32(tcg_res[pass]); | |
7979 | } | |
7980 | if (!is_q) { | |
7981 | clear_vec_high(s, rd); | |
7982 | } | |
7983 | } | |
7984 | ||
09e03735 AB |
7985 | /* Remaining saturating accumulating ops */ |
7986 | static void handle_2misc_satacc(DisasContext *s, bool is_scalar, bool is_u, | |
7987 | bool is_q, int size, int rn, int rd) | |
7988 | { | |
7989 | bool is_double = (size == 3); | |
7990 | ||
7991 | if (is_double) { | |
7992 | TCGv_i64 tcg_rn = tcg_temp_new_i64(); | |
7993 | TCGv_i64 tcg_rd = tcg_temp_new_i64(); | |
7994 | int pass; | |
7995 | ||
7996 | for (pass = 0; pass < (is_scalar ? 1 : 2); pass++) { | |
7997 | read_vec_element(s, tcg_rn, rn, pass, MO_64); | |
7998 | read_vec_element(s, tcg_rd, rd, pass, MO_64); | |
7999 | ||
8000 | if (is_u) { /* USQADD */ | |
8001 | gen_helper_neon_uqadd_s64(tcg_rd, cpu_env, tcg_rn, tcg_rd); | |
8002 | } else { /* SUQADD */ | |
8003 | gen_helper_neon_sqadd_u64(tcg_rd, cpu_env, tcg_rn, tcg_rd); | |
8004 | } | |
8005 | write_vec_element(s, tcg_rd, rd, pass, MO_64); | |
8006 | } | |
8007 | if (is_scalar) { | |
8008 | clear_vec_high(s, rd); | |
8009 | } | |
8010 | ||
8011 | tcg_temp_free_i64(tcg_rd); | |
8012 | tcg_temp_free_i64(tcg_rn); | |
8013 | } else { | |
8014 | TCGv_i32 tcg_rn = tcg_temp_new_i32(); | |
8015 | TCGv_i32 tcg_rd = tcg_temp_new_i32(); | |
8016 | int pass, maxpasses; | |
8017 | ||
8018 | if (is_scalar) { | |
8019 | maxpasses = 1; | |
8020 | } else { | |
8021 | maxpasses = is_q ? 4 : 2; | |
8022 | } | |
8023 | ||
8024 | for (pass = 0; pass < maxpasses; pass++) { | |
8025 | if (is_scalar) { | |
8026 | read_vec_element_i32(s, tcg_rn, rn, pass, size); | |
8027 | read_vec_element_i32(s, tcg_rd, rd, pass, size); | |
8028 | } else { | |
8029 | read_vec_element_i32(s, tcg_rn, rn, pass, MO_32); | |
8030 | read_vec_element_i32(s, tcg_rd, rd, pass, MO_32); | |
8031 | } | |
8032 | ||
8033 | if (is_u) { /* USQADD */ | |
8034 | switch (size) { | |
8035 | case 0: | |
8036 | gen_helper_neon_uqadd_s8(tcg_rd, cpu_env, tcg_rn, tcg_rd); | |
8037 | break; | |
8038 | case 1: | |
8039 | gen_helper_neon_uqadd_s16(tcg_rd, cpu_env, tcg_rn, tcg_rd); | |
8040 | break; | |
8041 | case 2: | |
8042 | gen_helper_neon_uqadd_s32(tcg_rd, cpu_env, tcg_rn, tcg_rd); | |
8043 | break; | |
8044 | default: | |
8045 | g_assert_not_reached(); | |
8046 | } | |
8047 | } else { /* SUQADD */ | |
8048 | switch (size) { | |
8049 | case 0: | |
8050 | gen_helper_neon_sqadd_u8(tcg_rd, cpu_env, tcg_rn, tcg_rd); | |
8051 | break; | |
8052 | case 1: | |
8053 | gen_helper_neon_sqadd_u16(tcg_rd, cpu_env, tcg_rn, tcg_rd); | |
8054 | break; | |
8055 | case 2: | |
8056 | gen_helper_neon_sqadd_u32(tcg_rd, cpu_env, tcg_rn, tcg_rd); | |
8057 | break; | |
8058 | default: | |
8059 | g_assert_not_reached(); | |
8060 | } | |
8061 | } | |
8062 | ||
8063 | if (is_scalar) { | |
8064 | TCGv_i64 tcg_zero = tcg_const_i64(0); | |
8065 | write_vec_element(s, tcg_zero, rd, 0, MO_64); | |
8066 | tcg_temp_free_i64(tcg_zero); | |
8067 | } | |
8068 | write_vec_element_i32(s, tcg_rd, rd, pass, MO_32); | |
8069 | } | |
8070 | ||
8071 | if (!is_q) { | |
8072 | clear_vec_high(s, rd); | |
8073 | } | |
8074 | ||
8075 | tcg_temp_free_i32(tcg_rd); | |
8076 | tcg_temp_free_i32(tcg_rn); | |
8077 | } | |
8078 | } | |
8079 | ||
384b26fb AB |
8080 | /* C3.6.12 AdvSIMD scalar two reg misc |
8081 | * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0 | |
8082 | * +-----+---+-----------+------+-----------+--------+-----+------+------+ | |
8083 | * | 0 1 | U | 1 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd | | |
8084 | * +-----+---+-----------+------+-----------+--------+-----+------+------+ | |
8085 | */ | |
8086 | static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn) | |
8087 | { | |
effa8e06 PM |
8088 | int rd = extract32(insn, 0, 5); |
8089 | int rn = extract32(insn, 5, 5); | |
8090 | int opcode = extract32(insn, 12, 5); | |
8091 | int size = extract32(insn, 22, 2); | |
8092 | bool u = extract32(insn, 29, 1); | |
04c7c6c2 PM |
8093 | bool is_fcvt = false; |
8094 | int rmode; | |
8095 | TCGv_i32 tcg_rmode; | |
8096 | TCGv_ptr tcg_fpstatus; | |
effa8e06 PM |
8097 | |
8098 | switch (opcode) { | |
09e03735 | 8099 | case 0x3: /* USQADD / SUQADD*/ |
8c6afa6a PM |
8100 | if (!fp_access_check(s)) { |
8101 | return; | |
8102 | } | |
09e03735 AB |
8103 | handle_2misc_satacc(s, true, u, false, size, rn, rd); |
8104 | return; | |
0a79bc87 AB |
8105 | case 0x7: /* SQABS / SQNEG */ |
8106 | break; | |
effa8e06 PM |
8107 | case 0xa: /* CMLT */ |
8108 | if (u) { | |
8109 | unallocated_encoding(s); | |
8110 | return; | |
8111 | } | |
8112 | /* fall through */ | |
8113 | case 0x8: /* CMGT, CMGE */ | |
8114 | case 0x9: /* CMEQ, CMLE */ | |
8115 | case 0xb: /* ABS, NEG */ | |
8116 | if (size != 3) { | |
8117 | unallocated_encoding(s); | |
8118 | return; | |
8119 | } | |
8120 | break; | |
5201c136 | 8121 | case 0x12: /* SQXTUN */ |
e44a90c5 | 8122 | if (!u) { |
5201c136 AB |
8123 | unallocated_encoding(s); |
8124 | return; | |
8125 | } | |
8126 | /* fall through */ | |
8127 | case 0x14: /* SQXTN, UQXTN */ | |
8128 | if (size == 3) { | |
8129 | unallocated_encoding(s); | |
8130 | return; | |
8131 | } | |
8c6afa6a PM |
8132 | if (!fp_access_check(s)) { |
8133 | return; | |
8134 | } | |
5201c136 AB |
8135 | handle_2misc_narrow(s, true, opcode, u, false, size, rn, rd); |
8136 | return; | |
8908f4d1 AB |
8137 | case 0xc ... 0xf: |
8138 | case 0x16 ... 0x1d: | |
8139 | case 0x1f: | |
8140 | /* Floating point: U, size[1] and opcode indicate operation; | |
8141 | * size[0] indicates single or double precision. | |
8142 | */ | |
8143 | opcode |= (extract32(size, 1, 1) << 5) | (u << 6); | |
8144 | size = extract32(size, 0, 1) ? 3 : 2; | |
8145 | switch (opcode) { | |
8146 | case 0x2c: /* FCMGT (zero) */ | |
8147 | case 0x2d: /* FCMEQ (zero) */ | |
8148 | case 0x2e: /* FCMLT (zero) */ | |
8149 | case 0x6c: /* FCMGE (zero) */ | |
8150 | case 0x6d: /* FCMLE (zero) */ | |
8151 | handle_2misc_fcmp_zero(s, opcode, true, u, true, size, rn, rd); | |
8152 | return; | |
10113b69 AB |
8153 | case 0x1d: /* SCVTF */ |
8154 | case 0x5d: /* UCVTF */ | |
8155 | { | |
8156 | bool is_signed = (opcode == 0x1d); | |
8c6afa6a PM |
8157 | if (!fp_access_check(s)) { |
8158 | return; | |
8159 | } | |
10113b69 AB |
8160 | handle_simd_intfp_conv(s, rd, rn, 1, is_signed, 0, size); |
8161 | return; | |
8162 | } | |
b6d4443a | 8163 | case 0x3d: /* FRECPE */ |
8f0c6758 | 8164 | case 0x3f: /* FRECPX */ |
c2fb418e | 8165 | case 0x7d: /* FRSQRTE */ |
8c6afa6a PM |
8166 | if (!fp_access_check(s)) { |
8167 | return; | |
8168 | } | |
8f0c6758 AB |
8169 | handle_2misc_reciprocal(s, opcode, true, u, true, size, rn, rd); |
8170 | return; | |
8908f4d1 AB |
8171 | case 0x1a: /* FCVTNS */ |
8172 | case 0x1b: /* FCVTMS */ | |
8908f4d1 AB |
8173 | case 0x3a: /* FCVTPS */ |
8174 | case 0x3b: /* FCVTZS */ | |
8908f4d1 AB |
8175 | case 0x5a: /* FCVTNU */ |
8176 | case 0x5b: /* FCVTMU */ | |
8908f4d1 AB |
8177 | case 0x7a: /* FCVTPU */ |
8178 | case 0x7b: /* FCVTZU */ | |
04c7c6c2 PM |
8179 | is_fcvt = true; |
8180 | rmode = extract32(opcode, 5, 1) | (extract32(opcode, 0, 1) << 1); | |
8181 | break; | |
8182 | case 0x1c: /* FCVTAS */ | |
8183 | case 0x5c: /* FCVTAU */ | |
8184 | /* TIEAWAY doesn't fit in the usual rounding mode encoding */ | |
8185 | is_fcvt = true; | |
8186 | rmode = FPROUNDING_TIEAWAY; | |
8187 | break; | |
04c7c6c2 | 8188 | case 0x56: /* FCVTXN, FCVTXN2 */ |
5553955e PM |
8189 | if (size == 2) { |
8190 | unallocated_encoding(s); | |
8191 | return; | |
8192 | } | |
8c6afa6a PM |
8193 | if (!fp_access_check(s)) { |
8194 | return; | |
8195 | } | |
5553955e PM |
8196 | handle_2misc_narrow(s, true, opcode, u, false, size - 1, rn, rd); |
8197 | return; | |
8908f4d1 AB |
8198 | default: |
8199 | unallocated_encoding(s); | |
8200 | return; | |
8201 | } | |
8202 | break; | |
effa8e06 | 8203 | default: |
09e03735 | 8204 | unallocated_encoding(s); |
effa8e06 PM |
8205 | return; |
8206 | } | |
8207 | ||
8c6afa6a PM |
8208 | if (!fp_access_check(s)) { |
8209 | return; | |
8210 | } | |
8211 | ||
04c7c6c2 PM |
8212 | if (is_fcvt) { |
8213 | tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode)); | |
8214 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); | |
8215 | tcg_fpstatus = get_fpstatus_ptr(); | |
8216 | } else { | |
8217 | TCGV_UNUSED_I32(tcg_rmode); | |
8218 | TCGV_UNUSED_PTR(tcg_fpstatus); | |
8219 | } | |
8220 | ||
effa8e06 PM |
8221 | if (size == 3) { |
8222 | TCGv_i64 tcg_rn = read_fp_dreg(s, rn); | |
8223 | TCGv_i64 tcg_rd = tcg_temp_new_i64(); | |
8224 | ||
04c7c6c2 | 8225 | handle_2misc_64(s, opcode, u, tcg_rd, tcg_rn, tcg_rmode, tcg_fpstatus); |
effa8e06 PM |
8226 | write_fp_dreg(s, rd, tcg_rd); |
8227 | tcg_temp_free_i64(tcg_rd); | |
8228 | tcg_temp_free_i64(tcg_rn); | |
0a79bc87 AB |
8229 | } else { |
8230 | TCGv_i32 tcg_rn = tcg_temp_new_i32(); | |
04c7c6c2 PM |
8231 | TCGv_i32 tcg_rd = tcg_temp_new_i32(); |
8232 | ||
0a79bc87 AB |
8233 | read_vec_element_i32(s, tcg_rn, rn, 0, size); |
8234 | ||
04c7c6c2 | 8235 | switch (opcode) { |
0a79bc87 AB |
8236 | case 0x7: /* SQABS, SQNEG */ |
8237 | { | |
8238 | NeonGenOneOpEnvFn *genfn; | |
8239 | static NeonGenOneOpEnvFn * const fns[3][2] = { | |
8240 | { gen_helper_neon_qabs_s8, gen_helper_neon_qneg_s8 }, | |
8241 | { gen_helper_neon_qabs_s16, gen_helper_neon_qneg_s16 }, | |
8242 | { gen_helper_neon_qabs_s32, gen_helper_neon_qneg_s32 }, | |
8243 | }; | |
8244 | genfn = fns[size][u]; | |
8245 | genfn(tcg_rd, cpu_env, tcg_rn); | |
8246 | break; | |
8247 | } | |
04c7c6c2 PM |
8248 | case 0x1a: /* FCVTNS */ |
8249 | case 0x1b: /* FCVTMS */ | |
8250 | case 0x1c: /* FCVTAS */ | |
8251 | case 0x3a: /* FCVTPS */ | |
8252 | case 0x3b: /* FCVTZS */ | |
8253 | { | |
8254 | TCGv_i32 tcg_shift = tcg_const_i32(0); | |
8255 | gen_helper_vfp_tosls(tcg_rd, tcg_rn, tcg_shift, tcg_fpstatus); | |
8256 | tcg_temp_free_i32(tcg_shift); | |
8257 | break; | |
8258 | } | |
8259 | case 0x5a: /* FCVTNU */ | |
8260 | case 0x5b: /* FCVTMU */ | |
8261 | case 0x5c: /* FCVTAU */ | |
8262 | case 0x7a: /* FCVTPU */ | |
8263 | case 0x7b: /* FCVTZU */ | |
8264 | { | |
8265 | TCGv_i32 tcg_shift = tcg_const_i32(0); | |
8266 | gen_helper_vfp_touls(tcg_rd, tcg_rn, tcg_shift, tcg_fpstatus); | |
8267 | tcg_temp_free_i32(tcg_shift); | |
8268 | break; | |
8269 | } | |
8270 | default: | |
8271 | g_assert_not_reached(); | |
8272 | } | |
8273 | ||
8274 | write_fp_sreg(s, rd, tcg_rd); | |
8275 | tcg_temp_free_i32(tcg_rd); | |
8276 | tcg_temp_free_i32(tcg_rn); | |
effa8e06 | 8277 | } |
04c7c6c2 PM |
8278 | |
8279 | if (is_fcvt) { | |
8280 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); | |
8281 | tcg_temp_free_i32(tcg_rmode); | |
8282 | tcg_temp_free_ptr(tcg_fpstatus); | |
8283 | } | |
384b26fb AB |
8284 | } |
8285 | ||
4d1cef84 AB |
8286 | /* SSHR[RA]/USHR[RA] - Vector shift right (optional rounding/accumulate) */ |
8287 | static void handle_vec_simd_shri(DisasContext *s, bool is_q, bool is_u, | |
8288 | int immh, int immb, int opcode, int rn, int rd) | |
8289 | { | |
8290 | int size = 32 - clz32(immh) - 1; | |
8291 | int immhb = immh << 3 | immb; | |
8292 | int shift = 2 * (8 << size) - immhb; | |
8293 | bool accumulate = false; | |
8294 | bool round = false; | |
37a706ad | 8295 | bool insert = false; |
4d1cef84 AB |
8296 | int dsize = is_q ? 128 : 64; |
8297 | int esize = 8 << size; | |
8298 | int elements = dsize/esize; | |
8299 | TCGMemOp memop = size | (is_u ? 0 : MO_SIGN); | |
8300 | TCGv_i64 tcg_rn = new_tmp_a64(s); | |
8301 | TCGv_i64 tcg_rd = new_tmp_a64(s); | |
8302 | TCGv_i64 tcg_round; | |
8303 | int i; | |
8304 | ||
8305 | if (extract32(immh, 3, 1) && !is_q) { | |
8306 | unallocated_encoding(s); | |
8307 | return; | |
8308 | } | |
8309 | ||
8310 | if (size > 3 && !is_q) { | |
8311 | unallocated_encoding(s); | |
8312 | return; | |
8313 | } | |
8314 | ||
8c6afa6a PM |
8315 | if (!fp_access_check(s)) { |
8316 | return; | |
8317 | } | |
8318 | ||
4d1cef84 AB |
8319 | switch (opcode) { |
8320 | case 0x02: /* SSRA / USRA (accumulate) */ | |
8321 | accumulate = true; | |
8322 | break; | |
8323 | case 0x04: /* SRSHR / URSHR (rounding) */ | |
8324 | round = true; | |
8325 | break; | |
8326 | case 0x06: /* SRSRA / URSRA (accum + rounding) */ | |
8327 | accumulate = round = true; | |
8328 | break; | |
37a706ad PM |
8329 | case 0x08: /* SRI */ |
8330 | insert = true; | |
8331 | break; | |
4d1cef84 AB |
8332 | } |
8333 | ||
8334 | if (round) { | |
8335 | uint64_t round_const = 1ULL << (shift - 1); | |
8336 | tcg_round = tcg_const_i64(round_const); | |
8337 | } else { | |
8338 | TCGV_UNUSED_I64(tcg_round); | |
8339 | } | |
8340 | ||
8341 | for (i = 0; i < elements; i++) { | |
8342 | read_vec_element(s, tcg_rn, rn, i, memop); | |
37a706ad | 8343 | if (accumulate || insert) { |
4d1cef84 AB |
8344 | read_vec_element(s, tcg_rd, rd, i, memop); |
8345 | } | |
8346 | ||
37a706ad PM |
8347 | if (insert) { |
8348 | handle_shri_with_ins(tcg_rd, tcg_rn, size, shift); | |
8349 | } else { | |
8350 | handle_shri_with_rndacc(tcg_rd, tcg_rn, tcg_round, | |
8351 | accumulate, is_u, size, shift); | |
8352 | } | |
4d1cef84 AB |
8353 | |
8354 | write_vec_element(s, tcg_rd, rd, i, size); | |
8355 | } | |
8356 | ||
8357 | if (!is_q) { | |
8358 | clear_vec_high(s, rd); | |
8359 | } | |
8360 | ||
8361 | if (round) { | |
8362 | tcg_temp_free_i64(tcg_round); | |
8363 | } | |
8364 | } | |
8365 | ||
8366 | /* SHL/SLI - Vector shift left */ | |
8367 | static void handle_vec_simd_shli(DisasContext *s, bool is_q, bool insert, | |
8368 | int immh, int immb, int opcode, int rn, int rd) | |
8369 | { | |
8370 | int size = 32 - clz32(immh) - 1; | |
8371 | int immhb = immh << 3 | immb; | |
8372 | int shift = immhb - (8 << size); | |
8373 | int dsize = is_q ? 128 : 64; | |
8374 | int esize = 8 << size; | |
8375 | int elements = dsize/esize; | |
8376 | TCGv_i64 tcg_rn = new_tmp_a64(s); | |
8377 | TCGv_i64 tcg_rd = new_tmp_a64(s); | |
8378 | int i; | |
8379 | ||
8380 | if (extract32(immh, 3, 1) && !is_q) { | |
8381 | unallocated_encoding(s); | |
8382 | return; | |
8383 | } | |
8384 | ||
8385 | if (size > 3 && !is_q) { | |
8386 | unallocated_encoding(s); | |
8387 | return; | |
8388 | } | |
8389 | ||
8c6afa6a PM |
8390 | if (!fp_access_check(s)) { |
8391 | return; | |
8392 | } | |
8393 | ||
4d1cef84 AB |
8394 | for (i = 0; i < elements; i++) { |
8395 | read_vec_element(s, tcg_rn, rn, i, size); | |
8396 | if (insert) { | |
8397 | read_vec_element(s, tcg_rd, rd, i, size); | |
8398 | } | |
8399 | ||
8400 | handle_shli_with_ins(tcg_rd, tcg_rn, insert, shift); | |
8401 | ||
8402 | write_vec_element(s, tcg_rd, rd, i, size); | |
8403 | } | |
8404 | ||
8405 | if (!is_q) { | |
8406 | clear_vec_high(s, rd); | |
8407 | } | |
8408 | } | |
8409 | ||
8410 | /* USHLL/SHLL - Vector shift left with widening */ | |
8411 | static void handle_vec_simd_wshli(DisasContext *s, bool is_q, bool is_u, | |
8412 | int immh, int immb, int opcode, int rn, int rd) | |
8413 | { | |
8414 | int size = 32 - clz32(immh) - 1; | |
8415 | int immhb = immh << 3 | immb; | |
8416 | int shift = immhb - (8 << size); | |
8417 | int dsize = 64; | |
8418 | int esize = 8 << size; | |
8419 | int elements = dsize/esize; | |
8420 | TCGv_i64 tcg_rn = new_tmp_a64(s); | |
8421 | TCGv_i64 tcg_rd = new_tmp_a64(s); | |
8422 | int i; | |
8423 | ||
8424 | if (size >= 3) { | |
8425 | unallocated_encoding(s); | |
8426 | return; | |
8427 | } | |
8428 | ||
8c6afa6a PM |
8429 | if (!fp_access_check(s)) { |
8430 | return; | |
8431 | } | |
8432 | ||
4d1cef84 AB |
8433 | /* For the LL variants the store is larger than the load, |
8434 | * so if rd == rn we would overwrite parts of our input. | |
8435 | * So load everything right now and use shifts in the main loop. | |
8436 | */ | |
8437 | read_vec_element(s, tcg_rn, rn, is_q ? 1 : 0, MO_64); | |
8438 | ||
8439 | for (i = 0; i < elements; i++) { | |
8440 | tcg_gen_shri_i64(tcg_rd, tcg_rn, i * esize); | |
8441 | ext_and_shift_reg(tcg_rd, tcg_rd, size | (!is_u << 2), 0); | |
8442 | tcg_gen_shli_i64(tcg_rd, tcg_rd, shift); | |
8443 | write_vec_element(s, tcg_rd, rd, i, size + 1); | |
8444 | } | |
8445 | } | |
8446 | ||
c1b876b2 AB |
8447 | /* SHRN/RSHRN - Shift right with narrowing (and potential rounding) */ |
8448 | static void handle_vec_simd_shrn(DisasContext *s, bool is_q, | |
8449 | int immh, int immb, int opcode, int rn, int rd) | |
8450 | { | |
8451 | int immhb = immh << 3 | immb; | |
8452 | int size = 32 - clz32(immh) - 1; | |
8453 | int dsize = 64; | |
8454 | int esize = 8 << size; | |
8455 | int elements = dsize/esize; | |
8456 | int shift = (2 * esize) - immhb; | |
8457 | bool round = extract32(opcode, 0, 1); | |
8458 | TCGv_i64 tcg_rn, tcg_rd, tcg_final; | |
8459 | TCGv_i64 tcg_round; | |
8460 | int i; | |
8461 | ||
8462 | if (extract32(immh, 3, 1)) { | |
8463 | unallocated_encoding(s); | |
8464 | return; | |
8465 | } | |
8466 | ||
8c6afa6a PM |
8467 | if (!fp_access_check(s)) { |
8468 | return; | |
8469 | } | |
8470 | ||
c1b876b2 AB |
8471 | tcg_rn = tcg_temp_new_i64(); |
8472 | tcg_rd = tcg_temp_new_i64(); | |
8473 | tcg_final = tcg_temp_new_i64(); | |
8474 | read_vec_element(s, tcg_final, rd, is_q ? 1 : 0, MO_64); | |
8475 | ||
8476 | if (round) { | |
8477 | uint64_t round_const = 1ULL << (shift - 1); | |
8478 | tcg_round = tcg_const_i64(round_const); | |
8479 | } else { | |
8480 | TCGV_UNUSED_I64(tcg_round); | |
8481 | } | |
8482 | ||
8483 | for (i = 0; i < elements; i++) { | |
8484 | read_vec_element(s, tcg_rn, rn, i, size+1); | |
8485 | handle_shri_with_rndacc(tcg_rd, tcg_rn, tcg_round, | |
8486 | false, true, size+1, shift); | |
8487 | ||
8488 | tcg_gen_deposit_i64(tcg_final, tcg_final, tcg_rd, esize * i, esize); | |
8489 | } | |
8490 | ||
8491 | if (!is_q) { | |
8492 | clear_vec_high(s, rd); | |
8493 | write_vec_element(s, tcg_final, rd, 0, MO_64); | |
8494 | } else { | |
8495 | write_vec_element(s, tcg_final, rd, 1, MO_64); | |
8496 | } | |
8497 | ||
8498 | if (round) { | |
8499 | tcg_temp_free_i64(tcg_round); | |
8500 | } | |
8501 | tcg_temp_free_i64(tcg_rn); | |
8502 | tcg_temp_free_i64(tcg_rd); | |
8503 | tcg_temp_free_i64(tcg_final); | |
8504 | return; | |
8505 | } | |
8506 | ||
8507 | ||
384b26fb AB |
8508 | /* C3.6.14 AdvSIMD shift by immediate |
8509 | * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0 | |
8510 | * +---+---+---+-------------+------+------+--------+---+------+------+ | |
8511 | * | 0 | Q | U | 0 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd | | |
8512 | * +---+---+---+-------------+------+------+--------+---+------+------+ | |
8513 | */ | |
8514 | static void disas_simd_shift_imm(DisasContext *s, uint32_t insn) | |
8515 | { | |
4d1cef84 AB |
8516 | int rd = extract32(insn, 0, 5); |
8517 | int rn = extract32(insn, 5, 5); | |
8518 | int opcode = extract32(insn, 11, 5); | |
8519 | int immb = extract32(insn, 16, 3); | |
8520 | int immh = extract32(insn, 19, 4); | |
8521 | bool is_u = extract32(insn, 29, 1); | |
8522 | bool is_q = extract32(insn, 30, 1); | |
8523 | ||
8524 | switch (opcode) { | |
37a706ad PM |
8525 | case 0x08: /* SRI */ |
8526 | if (!is_u) { | |
8527 | unallocated_encoding(s); | |
8528 | return; | |
8529 | } | |
8530 | /* fall through */ | |
4d1cef84 AB |
8531 | case 0x00: /* SSHR / USHR */ |
8532 | case 0x02: /* SSRA / USRA (accumulate) */ | |
8533 | case 0x04: /* SRSHR / URSHR (rounding) */ | |
8534 | case 0x06: /* SRSRA / URSRA (accum + rounding) */ | |
8535 | handle_vec_simd_shri(s, is_q, is_u, immh, immb, opcode, rn, rd); | |
8536 | break; | |
8537 | case 0x0a: /* SHL / SLI */ | |
8538 | handle_vec_simd_shli(s, is_q, is_u, immh, immb, opcode, rn, rd); | |
8539 | break; | |
c1b876b2 AB |
8540 | case 0x10: /* SHRN */ |
8541 | case 0x11: /* RSHRN / SQRSHRUN */ | |
8542 | if (is_u) { | |
8543 | handle_vec_simd_sqshrn(s, false, is_q, false, true, immh, immb, | |
8544 | opcode, rn, rd); | |
8545 | } else { | |
8546 | handle_vec_simd_shrn(s, is_q, immh, immb, opcode, rn, rd); | |
8547 | } | |
8548 | break; | |
8549 | case 0x12: /* SQSHRN / UQSHRN */ | |
8550 | case 0x13: /* SQRSHRN / UQRSHRN */ | |
8551 | handle_vec_simd_sqshrn(s, false, is_q, is_u, is_u, immh, immb, | |
8552 | opcode, rn, rd); | |
8553 | break; | |
4d1cef84 AB |
8554 | case 0x14: /* SSHLL / USHLL */ |
8555 | handle_vec_simd_wshli(s, is_q, is_u, immh, immb, opcode, rn, rd); | |
8556 | break; | |
10113b69 AB |
8557 | case 0x1c: /* SCVTF / UCVTF */ |
8558 | handle_simd_shift_intfp_conv(s, false, is_q, is_u, immh, immb, | |
8559 | opcode, rn, rd); | |
8560 | break; | |
a566da1b | 8561 | case 0xc: /* SQSHLU */ |
a847f32c PM |
8562 | if (!is_u) { |
8563 | unallocated_encoding(s); | |
8564 | return; | |
8565 | } | |
8566 | handle_simd_qshl(s, false, is_q, false, true, immh, immb, rn, rd); | |
8567 | break; | |
a566da1b | 8568 | case 0xe: /* SQSHL, UQSHL */ |
a847f32c PM |
8569 | handle_simd_qshl(s, false, is_q, is_u, is_u, immh, immb, rn, rd); |
8570 | break; | |
10113b69 | 8571 | case 0x1f: /* FCVTZS/ FCVTZU */ |
2ed3ea11 | 8572 | handle_simd_shift_fpint_conv(s, false, is_q, is_u, immh, immb, rn, rd); |
10113b69 | 8573 | return; |
4d1cef84 | 8574 | default: |
a566da1b | 8575 | unallocated_encoding(s); |
4d1cef84 AB |
8576 | return; |
8577 | } | |
384b26fb AB |
8578 | } |
8579 | ||
70d7f984 PM |
8580 | /* Generate code to do a "long" addition or subtraction, ie one done in |
8581 | * TCGv_i64 on vector lanes twice the width specified by size. | |
8582 | */ | |
8583 | static void gen_neon_addl(int size, bool is_sub, TCGv_i64 tcg_res, | |
8584 | TCGv_i64 tcg_op1, TCGv_i64 tcg_op2) | |
8585 | { | |
8586 | static NeonGenTwo64OpFn * const fns[3][2] = { | |
8587 | { gen_helper_neon_addl_u16, gen_helper_neon_subl_u16 }, | |
8588 | { gen_helper_neon_addl_u32, gen_helper_neon_subl_u32 }, | |
8589 | { tcg_gen_add_i64, tcg_gen_sub_i64 }, | |
8590 | }; | |
8591 | NeonGenTwo64OpFn *genfn; | |
8592 | assert(size < 3); | |
8593 | ||
8594 | genfn = fns[size][is_sub]; | |
8595 | genfn(tcg_res, tcg_op1, tcg_op2); | |
8596 | } | |
8597 | ||
a08582f4 PM |
8598 | static void handle_3rd_widening(DisasContext *s, int is_q, int is_u, int size, |
8599 | int opcode, int rd, int rn, int rm) | |
8600 | { | |
8601 | /* 3-reg-different widening insns: 64 x 64 -> 128 */ | |
8602 | TCGv_i64 tcg_res[2]; | |
8603 | int pass, accop; | |
8604 | ||
8605 | tcg_res[0] = tcg_temp_new_i64(); | |
8606 | tcg_res[1] = tcg_temp_new_i64(); | |
8607 | ||
8608 | /* Does this op do an adding accumulate, a subtracting accumulate, | |
8609 | * or no accumulate at all? | |
8610 | */ | |
8611 | switch (opcode) { | |
8612 | case 5: | |
8613 | case 8: | |
8614 | case 9: | |
8615 | accop = 1; | |
8616 | break; | |
8617 | case 10: | |
8618 | case 11: | |
8619 | accop = -1; | |
8620 | break; | |
8621 | default: | |
8622 | accop = 0; | |
8623 | break; | |
8624 | } | |
8625 | ||
8626 | if (accop != 0) { | |
8627 | read_vec_element(s, tcg_res[0], rd, 0, MO_64); | |
8628 | read_vec_element(s, tcg_res[1], rd, 1, MO_64); | |
8629 | } | |
8630 | ||
8631 | /* size == 2 means two 32x32->64 operations; this is worth special | |
8632 | * casing because we can generally handle it inline. | |
8633 | */ | |
8634 | if (size == 2) { | |
8635 | for (pass = 0; pass < 2; pass++) { | |
8636 | TCGv_i64 tcg_op1 = tcg_temp_new_i64(); | |
8637 | TCGv_i64 tcg_op2 = tcg_temp_new_i64(); | |
8638 | TCGv_i64 tcg_passres; | |
8639 | TCGMemOp memop = MO_32 | (is_u ? 0 : MO_SIGN); | |
8640 | ||
8641 | int elt = pass + is_q * 2; | |
8642 | ||
8643 | read_vec_element(s, tcg_op1, rn, elt, memop); | |
8644 | read_vec_element(s, tcg_op2, rm, elt, memop); | |
8645 | ||
8646 | if (accop == 0) { | |
8647 | tcg_passres = tcg_res[pass]; | |
8648 | } else { | |
8649 | tcg_passres = tcg_temp_new_i64(); | |
8650 | } | |
8651 | ||
8652 | switch (opcode) { | |
70d7f984 PM |
8653 | case 0: /* SADDL, SADDL2, UADDL, UADDL2 */ |
8654 | tcg_gen_add_i64(tcg_passres, tcg_op1, tcg_op2); | |
8655 | break; | |
8656 | case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */ | |
8657 | tcg_gen_sub_i64(tcg_passres, tcg_op1, tcg_op2); | |
8658 | break; | |
0ae39320 PM |
8659 | case 5: /* SABAL, SABAL2, UABAL, UABAL2 */ |
8660 | case 7: /* SABDL, SABDL2, UABDL, UABDL2 */ | |
8661 | { | |
8662 | TCGv_i64 tcg_tmp1 = tcg_temp_new_i64(); | |
8663 | TCGv_i64 tcg_tmp2 = tcg_temp_new_i64(); | |
8664 | ||
8665 | tcg_gen_sub_i64(tcg_tmp1, tcg_op1, tcg_op2); | |
8666 | tcg_gen_sub_i64(tcg_tmp2, tcg_op2, tcg_op1); | |
8667 | tcg_gen_movcond_i64(is_u ? TCG_COND_GEU : TCG_COND_GE, | |
8668 | tcg_passres, | |
8669 | tcg_op1, tcg_op2, tcg_tmp1, tcg_tmp2); | |
8670 | tcg_temp_free_i64(tcg_tmp1); | |
8671 | tcg_temp_free_i64(tcg_tmp2); | |
8672 | break; | |
8673 | } | |
a08582f4 PM |
8674 | case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */ |
8675 | case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */ | |
8676 | case 12: /* UMULL, UMULL2, SMULL, SMULL2 */ | |
8677 | tcg_gen_mul_i64(tcg_passres, tcg_op1, tcg_op2); | |
8678 | break; | |
70d7f984 PM |
8679 | case 9: /* SQDMLAL, SQDMLAL2 */ |
8680 | case 11: /* SQDMLSL, SQDMLSL2 */ | |
8681 | case 13: /* SQDMULL, SQDMULL2 */ | |
8682 | tcg_gen_mul_i64(tcg_passres, tcg_op1, tcg_op2); | |
8683 | gen_helper_neon_addl_saturate_s64(tcg_passres, cpu_env, | |
8684 | tcg_passres, tcg_passres); | |
8685 | break; | |
a08582f4 PM |
8686 | default: |
8687 | g_assert_not_reached(); | |
8688 | } | |
8689 | ||
70d7f984 PM |
8690 | if (opcode == 9 || opcode == 11) { |
8691 | /* saturating accumulate ops */ | |
8692 | if (accop < 0) { | |
8693 | tcg_gen_neg_i64(tcg_passres, tcg_passres); | |
8694 | } | |
8695 | gen_helper_neon_addl_saturate_s64(tcg_res[pass], cpu_env, | |
8696 | tcg_res[pass], tcg_passres); | |
8697 | } else if (accop > 0) { | |
a08582f4 | 8698 | tcg_gen_add_i64(tcg_res[pass], tcg_res[pass], tcg_passres); |
a08582f4 PM |
8699 | } else if (accop < 0) { |
8700 | tcg_gen_sub_i64(tcg_res[pass], tcg_res[pass], tcg_passres); | |
70d7f984 PM |
8701 | } |
8702 | ||
8703 | if (accop != 0) { | |
a08582f4 PM |
8704 | tcg_temp_free_i64(tcg_passres); |
8705 | } | |
8706 | ||
8707 | tcg_temp_free_i64(tcg_op1); | |
8708 | tcg_temp_free_i64(tcg_op2); | |
8709 | } | |
8710 | } else { | |
8711 | /* size 0 or 1, generally helper functions */ | |
8712 | for (pass = 0; pass < 2; pass++) { | |
8713 | TCGv_i32 tcg_op1 = tcg_temp_new_i32(); | |
8714 | TCGv_i32 tcg_op2 = tcg_temp_new_i32(); | |
8715 | TCGv_i64 tcg_passres; | |
8716 | int elt = pass + is_q * 2; | |
8717 | ||
8718 | read_vec_element_i32(s, tcg_op1, rn, elt, MO_32); | |
8719 | read_vec_element_i32(s, tcg_op2, rm, elt, MO_32); | |
8720 | ||
8721 | if (accop == 0) { | |
8722 | tcg_passres = tcg_res[pass]; | |
8723 | } else { | |
8724 | tcg_passres = tcg_temp_new_i64(); | |
8725 | } | |
8726 | ||
8727 | switch (opcode) { | |
70d7f984 PM |
8728 | case 0: /* SADDL, SADDL2, UADDL, UADDL2 */ |
8729 | case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */ | |
8730 | { | |
8731 | TCGv_i64 tcg_op2_64 = tcg_temp_new_i64(); | |
8732 | static NeonGenWidenFn * const widenfns[2][2] = { | |
8733 | { gen_helper_neon_widen_s8, gen_helper_neon_widen_u8 }, | |
8734 | { gen_helper_neon_widen_s16, gen_helper_neon_widen_u16 }, | |
8735 | }; | |
8736 | NeonGenWidenFn *widenfn = widenfns[size][is_u]; | |
8737 | ||
8738 | widenfn(tcg_op2_64, tcg_op2); | |
8739 | widenfn(tcg_passres, tcg_op1); | |
8740 | gen_neon_addl(size, (opcode == 2), tcg_passres, | |
8741 | tcg_passres, tcg_op2_64); | |
8742 | tcg_temp_free_i64(tcg_op2_64); | |
8743 | break; | |
8744 | } | |
0ae39320 PM |
8745 | case 5: /* SABAL, SABAL2, UABAL, UABAL2 */ |
8746 | case 7: /* SABDL, SABDL2, UABDL, UABDL2 */ | |
8747 | if (size == 0) { | |
8748 | if (is_u) { | |
8749 | gen_helper_neon_abdl_u16(tcg_passres, tcg_op1, tcg_op2); | |
8750 | } else { | |
8751 | gen_helper_neon_abdl_s16(tcg_passres, tcg_op1, tcg_op2); | |
8752 | } | |
8753 | } else { | |
8754 | if (is_u) { | |
8755 | gen_helper_neon_abdl_u32(tcg_passres, tcg_op1, tcg_op2); | |
8756 | } else { | |
8757 | gen_helper_neon_abdl_s32(tcg_passres, tcg_op1, tcg_op2); | |
8758 | } | |
8759 | } | |
8760 | break; | |
a08582f4 PM |
8761 | case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */ |
8762 | case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */ | |
8763 | case 12: /* UMULL, UMULL2, SMULL, SMULL2 */ | |
8764 | if (size == 0) { | |
8765 | if (is_u) { | |
8766 | gen_helper_neon_mull_u8(tcg_passres, tcg_op1, tcg_op2); | |
8767 | } else { | |
8768 | gen_helper_neon_mull_s8(tcg_passres, tcg_op1, tcg_op2); | |
8769 | } | |
8770 | } else { | |
8771 | if (is_u) { | |
8772 | gen_helper_neon_mull_u16(tcg_passres, tcg_op1, tcg_op2); | |
8773 | } else { | |
8774 | gen_helper_neon_mull_s16(tcg_passres, tcg_op1, tcg_op2); | |
8775 | } | |
8776 | } | |
8777 | break; | |
70d7f984 PM |
8778 | case 9: /* SQDMLAL, SQDMLAL2 */ |
8779 | case 11: /* SQDMLSL, SQDMLSL2 */ | |
8780 | case 13: /* SQDMULL, SQDMULL2 */ | |
8781 | assert(size == 1); | |
8782 | gen_helper_neon_mull_s16(tcg_passres, tcg_op1, tcg_op2); | |
8783 | gen_helper_neon_addl_saturate_s32(tcg_passres, cpu_env, | |
8784 | tcg_passres, tcg_passres); | |
8785 | break; | |
a984e42c PM |
8786 | case 14: /* PMULL */ |
8787 | assert(size == 0); | |
8788 | gen_helper_neon_mull_p8(tcg_passres, tcg_op1, tcg_op2); | |
8789 | break; | |
a08582f4 PM |
8790 | default: |
8791 | g_assert_not_reached(); | |
8792 | } | |
8793 | tcg_temp_free_i32(tcg_op1); | |
8794 | tcg_temp_free_i32(tcg_op2); | |
8795 | ||
70d7f984 PM |
8796 | if (accop != 0) { |
8797 | if (opcode == 9 || opcode == 11) { | |
8798 | /* saturating accumulate ops */ | |
8799 | if (accop < 0) { | |
8800 | gen_helper_neon_negl_u32(tcg_passres, tcg_passres); | |
8801 | } | |
8802 | gen_helper_neon_addl_saturate_s32(tcg_res[pass], cpu_env, | |
8803 | tcg_res[pass], | |
8804 | tcg_passres); | |
a08582f4 | 8805 | } else { |
70d7f984 PM |
8806 | gen_neon_addl(size, (accop < 0), tcg_res[pass], |
8807 | tcg_res[pass], tcg_passres); | |
a08582f4 PM |
8808 | } |
8809 | tcg_temp_free_i64(tcg_passres); | |
8810 | } | |
8811 | } | |
8812 | } | |
8813 | ||
8814 | write_vec_element(s, tcg_res[0], rd, 0, MO_64); | |
8815 | write_vec_element(s, tcg_res[1], rd, 1, MO_64); | |
8816 | tcg_temp_free_i64(tcg_res[0]); | |
8817 | tcg_temp_free_i64(tcg_res[1]); | |
8818 | } | |
8819 | ||
dfc15c7c PM |
8820 | static void handle_3rd_wide(DisasContext *s, int is_q, int is_u, int size, |
8821 | int opcode, int rd, int rn, int rm) | |
8822 | { | |
8823 | TCGv_i64 tcg_res[2]; | |
8824 | int part = is_q ? 2 : 0; | |
8825 | int pass; | |
8826 | ||
8827 | for (pass = 0; pass < 2; pass++) { | |
8828 | TCGv_i64 tcg_op1 = tcg_temp_new_i64(); | |
8829 | TCGv_i32 tcg_op2 = tcg_temp_new_i32(); | |
8830 | TCGv_i64 tcg_op2_wide = tcg_temp_new_i64(); | |
8831 | static NeonGenWidenFn * const widenfns[3][2] = { | |
8832 | { gen_helper_neon_widen_s8, gen_helper_neon_widen_u8 }, | |
8833 | { gen_helper_neon_widen_s16, gen_helper_neon_widen_u16 }, | |
8834 | { tcg_gen_ext_i32_i64, tcg_gen_extu_i32_i64 }, | |
8835 | }; | |
8836 | NeonGenWidenFn *widenfn = widenfns[size][is_u]; | |
8837 | ||
8838 | read_vec_element(s, tcg_op1, rn, pass, MO_64); | |
8839 | read_vec_element_i32(s, tcg_op2, rm, part + pass, MO_32); | |
8840 | widenfn(tcg_op2_wide, tcg_op2); | |
8841 | tcg_temp_free_i32(tcg_op2); | |
8842 | tcg_res[pass] = tcg_temp_new_i64(); | |
8843 | gen_neon_addl(size, (opcode == 3), | |
8844 | tcg_res[pass], tcg_op1, tcg_op2_wide); | |
8845 | tcg_temp_free_i64(tcg_op1); | |
8846 | tcg_temp_free_i64(tcg_op2_wide); | |
8847 | } | |
8848 | ||
8849 | for (pass = 0; pass < 2; pass++) { | |
8850 | write_vec_element(s, tcg_res[pass], rd, pass, MO_64); | |
8851 | tcg_temp_free_i64(tcg_res[pass]); | |
8852 | } | |
8853 | } | |
8854 | ||
e4b998d4 PM |
8855 | static void do_narrow_round_high_u32(TCGv_i32 res, TCGv_i64 in) |
8856 | { | |
8857 | tcg_gen_addi_i64(in, in, 1U << 31); | |
7cb36e18 | 8858 | tcg_gen_extrh_i64_i32(res, in); |
e4b998d4 PM |
8859 | } |
8860 | ||
8861 | static void handle_3rd_narrowing(DisasContext *s, int is_q, int is_u, int size, | |
8862 | int opcode, int rd, int rn, int rm) | |
8863 | { | |
8864 | TCGv_i32 tcg_res[2]; | |
8865 | int part = is_q ? 2 : 0; | |
8866 | int pass; | |
8867 | ||
8868 | for (pass = 0; pass < 2; pass++) { | |
8869 | TCGv_i64 tcg_op1 = tcg_temp_new_i64(); | |
8870 | TCGv_i64 tcg_op2 = tcg_temp_new_i64(); | |
8871 | TCGv_i64 tcg_wideres = tcg_temp_new_i64(); | |
8872 | static NeonGenNarrowFn * const narrowfns[3][2] = { | |
8873 | { gen_helper_neon_narrow_high_u8, | |
8874 | gen_helper_neon_narrow_round_high_u8 }, | |
8875 | { gen_helper_neon_narrow_high_u16, | |
8876 | gen_helper_neon_narrow_round_high_u16 }, | |
7cb36e18 | 8877 | { tcg_gen_extrh_i64_i32, do_narrow_round_high_u32 }, |
e4b998d4 PM |
8878 | }; |
8879 | NeonGenNarrowFn *gennarrow = narrowfns[size][is_u]; | |
8880 | ||
8881 | read_vec_element(s, tcg_op1, rn, pass, MO_64); | |
8882 | read_vec_element(s, tcg_op2, rm, pass, MO_64); | |
8883 | ||
8884 | gen_neon_addl(size, (opcode == 6), tcg_wideres, tcg_op1, tcg_op2); | |
8885 | ||
8886 | tcg_temp_free_i64(tcg_op1); | |
8887 | tcg_temp_free_i64(tcg_op2); | |
8888 | ||
8889 | tcg_res[pass] = tcg_temp_new_i32(); | |
8890 | gennarrow(tcg_res[pass], tcg_wideres); | |
8891 | tcg_temp_free_i64(tcg_wideres); | |
8892 | } | |
8893 | ||
8894 | for (pass = 0; pass < 2; pass++) { | |
8895 | write_vec_element_i32(s, tcg_res[pass], rd, pass + part, MO_32); | |
8896 | tcg_temp_free_i32(tcg_res[pass]); | |
8897 | } | |
8898 | if (!is_q) { | |
8899 | clear_vec_high(s, rd); | |
8900 | } | |
8901 | } | |
8902 | ||
a984e42c PM |
8903 | static void handle_pmull_64(DisasContext *s, int is_q, int rd, int rn, int rm) |
8904 | { | |
8905 | /* PMULL of 64 x 64 -> 128 is an odd special case because it | |
8906 | * is the only three-reg-diff instruction which produces a | |
8907 | * 128-bit wide result from a single operation. However since | |
8908 | * it's possible to calculate the two halves more or less | |
8909 | * separately we just use two helper calls. | |
8910 | */ | |
8911 | TCGv_i64 tcg_op1 = tcg_temp_new_i64(); | |
8912 | TCGv_i64 tcg_op2 = tcg_temp_new_i64(); | |
8913 | TCGv_i64 tcg_res = tcg_temp_new_i64(); | |
8914 | ||
8915 | read_vec_element(s, tcg_op1, rn, is_q, MO_64); | |
8916 | read_vec_element(s, tcg_op2, rm, is_q, MO_64); | |
8917 | gen_helper_neon_pmull_64_lo(tcg_res, tcg_op1, tcg_op2); | |
8918 | write_vec_element(s, tcg_res, rd, 0, MO_64); | |
8919 | gen_helper_neon_pmull_64_hi(tcg_res, tcg_op1, tcg_op2); | |
8920 | write_vec_element(s, tcg_res, rd, 1, MO_64); | |
8921 | ||
8922 | tcg_temp_free_i64(tcg_op1); | |
8923 | tcg_temp_free_i64(tcg_op2); | |
8924 | tcg_temp_free_i64(tcg_res); | |
8925 | } | |
8926 | ||
384b26fb AB |
8927 | /* C3.6.15 AdvSIMD three different |
8928 | * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0 | |
8929 | * +---+---+---+-----------+------+---+------+--------+-----+------+------+ | |
8930 | * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd | | |
8931 | * +---+---+---+-----------+------+---+------+--------+-----+------+------+ | |
8932 | */ | |
8933 | static void disas_simd_three_reg_diff(DisasContext *s, uint32_t insn) | |
8934 | { | |
a08582f4 PM |
8935 | /* Instructions in this group fall into three basic classes |
8936 | * (in each case with the operation working on each element in | |
8937 | * the input vectors): | |
8938 | * (1) widening 64 x 64 -> 128 (with possibly Vd as an extra | |
8939 | * 128 bit input) | |
8940 | * (2) wide 64 x 128 -> 128 | |
8941 | * (3) narrowing 128 x 128 -> 64 | |
8942 | * Here we do initial decode, catch unallocated cases and | |
8943 | * dispatch to separate functions for each class. | |
8944 | */ | |
8945 | int is_q = extract32(insn, 30, 1); | |
8946 | int is_u = extract32(insn, 29, 1); | |
8947 | int size = extract32(insn, 22, 2); | |
8948 | int opcode = extract32(insn, 12, 4); | |
8949 | int rm = extract32(insn, 16, 5); | |
8950 | int rn = extract32(insn, 5, 5); | |
8951 | int rd = extract32(insn, 0, 5); | |
8952 | ||
8953 | switch (opcode) { | |
8954 | case 1: /* SADDW, SADDW2, UADDW, UADDW2 */ | |
8955 | case 3: /* SSUBW, SSUBW2, USUBW, USUBW2 */ | |
8956 | /* 64 x 128 -> 128 */ | |
dfc15c7c PM |
8957 | if (size == 3) { |
8958 | unallocated_encoding(s); | |
8959 | return; | |
8960 | } | |
8c6afa6a PM |
8961 | if (!fp_access_check(s)) { |
8962 | return; | |
8963 | } | |
dfc15c7c | 8964 | handle_3rd_wide(s, is_q, is_u, size, opcode, rd, rn, rm); |
a08582f4 PM |
8965 | break; |
8966 | case 4: /* ADDHN, ADDHN2, RADDHN, RADDHN2 */ | |
8967 | case 6: /* SUBHN, SUBHN2, RSUBHN, RSUBHN2 */ | |
8968 | /* 128 x 128 -> 64 */ | |
e4b998d4 PM |
8969 | if (size == 3) { |
8970 | unallocated_encoding(s); | |
8971 | return; | |
8972 | } | |
8c6afa6a PM |
8973 | if (!fp_access_check(s)) { |
8974 | return; | |
8975 | } | |
e4b998d4 | 8976 | handle_3rd_narrowing(s, is_q, is_u, size, opcode, rd, rn, rm); |
a08582f4 | 8977 | break; |
70d7f984 PM |
8978 | case 14: /* PMULL, PMULL2 */ |
8979 | if (is_u || size == 1 || size == 2) { | |
8980 | unallocated_encoding(s); | |
8981 | return; | |
8982 | } | |
a984e42c | 8983 | if (size == 3) { |
411bdc78 | 8984 | if (!arm_dc_feature(s, ARM_FEATURE_V8_PMULL)) { |
a984e42c PM |
8985 | unallocated_encoding(s); |
8986 | return; | |
8987 | } | |
8c6afa6a PM |
8988 | if (!fp_access_check(s)) { |
8989 | return; | |
8990 | } | |
a984e42c PM |
8991 | handle_pmull_64(s, is_q, rd, rn, rm); |
8992 | return; | |
8993 | } | |
8994 | goto is_widening; | |
13caf1fd PM |
8995 | case 9: /* SQDMLAL, SQDMLAL2 */ |
8996 | case 11: /* SQDMLSL, SQDMLSL2 */ | |
8997 | case 13: /* SQDMULL, SQDMULL2 */ | |
70d7f984 | 8998 | if (is_u || size == 0) { |
a08582f4 PM |
8999 | unallocated_encoding(s); |
9000 | return; | |
9001 | } | |
9002 | /* fall through */ | |
13caf1fd PM |
9003 | case 0: /* SADDL, SADDL2, UADDL, UADDL2 */ |
9004 | case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */ | |
13caf1fd PM |
9005 | case 5: /* SABAL, SABAL2, UABAL, UABAL2 */ |
9006 | case 7: /* SABDL, SABDL2, UABDL, UABDL2 */ | |
9007 | case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */ | |
9008 | case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */ | |
9009 | case 12: /* SMULL, SMULL2, UMULL, UMULL2 */ | |
a08582f4 PM |
9010 | /* 64 x 64 -> 128 */ |
9011 | if (size == 3) { | |
9012 | unallocated_encoding(s); | |
9013 | return; | |
9014 | } | |
a984e42c | 9015 | is_widening: |
8c6afa6a PM |
9016 | if (!fp_access_check(s)) { |
9017 | return; | |
9018 | } | |
9019 | ||
a08582f4 PM |
9020 | handle_3rd_widening(s, is_q, is_u, size, opcode, rd, rn, rm); |
9021 | break; | |
9022 | default: | |
9023 | /* opcode 15 not allocated */ | |
9024 | unallocated_encoding(s); | |
9025 | break; | |
9026 | } | |
384b26fb AB |
9027 | } |
9028 | ||
e1cea114 PM |
9029 | /* Logic op (opcode == 3) subgroup of C3.6.16. */ |
9030 | static void disas_simd_3same_logic(DisasContext *s, uint32_t insn) | |
9031 | { | |
956d272e PM |
9032 | int rd = extract32(insn, 0, 5); |
9033 | int rn = extract32(insn, 5, 5); | |
9034 | int rm = extract32(insn, 16, 5); | |
9035 | int size = extract32(insn, 22, 2); | |
9036 | bool is_u = extract32(insn, 29, 1); | |
9037 | bool is_q = extract32(insn, 30, 1); | |
8c6afa6a | 9038 | TCGv_i64 tcg_op1, tcg_op2, tcg_res[2]; |
956d272e PM |
9039 | int pass; |
9040 | ||
8c6afa6a PM |
9041 | if (!fp_access_check(s)) { |
9042 | return; | |
9043 | } | |
9044 | ||
9045 | tcg_op1 = tcg_temp_new_i64(); | |
9046 | tcg_op2 = tcg_temp_new_i64(); | |
956d272e PM |
9047 | tcg_res[0] = tcg_temp_new_i64(); |
9048 | tcg_res[1] = tcg_temp_new_i64(); | |
9049 | ||
9050 | for (pass = 0; pass < (is_q ? 2 : 1); pass++) { | |
9051 | read_vec_element(s, tcg_op1, rn, pass, MO_64); | |
9052 | read_vec_element(s, tcg_op2, rm, pass, MO_64); | |
9053 | ||
9054 | if (!is_u) { | |
9055 | switch (size) { | |
9056 | case 0: /* AND */ | |
9057 | tcg_gen_and_i64(tcg_res[pass], tcg_op1, tcg_op2); | |
9058 | break; | |
9059 | case 1: /* BIC */ | |
9060 | tcg_gen_andc_i64(tcg_res[pass], tcg_op1, tcg_op2); | |
9061 | break; | |
9062 | case 2: /* ORR */ | |
9063 | tcg_gen_or_i64(tcg_res[pass], tcg_op1, tcg_op2); | |
9064 | break; | |
9065 | case 3: /* ORN */ | |
9066 | tcg_gen_orc_i64(tcg_res[pass], tcg_op1, tcg_op2); | |
9067 | break; | |
9068 | } | |
9069 | } else { | |
9070 | if (size != 0) { | |
9071 | /* B* ops need res loaded to operate on */ | |
9072 | read_vec_element(s, tcg_res[pass], rd, pass, MO_64); | |
9073 | } | |
9074 | ||
9075 | switch (size) { | |
9076 | case 0: /* EOR */ | |
9077 | tcg_gen_xor_i64(tcg_res[pass], tcg_op1, tcg_op2); | |
9078 | break; | |
9079 | case 1: /* BSL bitwise select */ | |
9080 | tcg_gen_xor_i64(tcg_op1, tcg_op1, tcg_op2); | |
9081 | tcg_gen_and_i64(tcg_op1, tcg_op1, tcg_res[pass]); | |
9082 | tcg_gen_xor_i64(tcg_res[pass], tcg_op2, tcg_op1); | |
9083 | break; | |
9084 | case 2: /* BIT, bitwise insert if true */ | |
9085 | tcg_gen_xor_i64(tcg_op1, tcg_op1, tcg_res[pass]); | |
9086 | tcg_gen_and_i64(tcg_op1, tcg_op1, tcg_op2); | |
9087 | tcg_gen_xor_i64(tcg_res[pass], tcg_res[pass], tcg_op1); | |
9088 | break; | |
9089 | case 3: /* BIF, bitwise insert if false */ | |
9090 | tcg_gen_xor_i64(tcg_op1, tcg_op1, tcg_res[pass]); | |
9091 | tcg_gen_andc_i64(tcg_op1, tcg_op1, tcg_op2); | |
9092 | tcg_gen_xor_i64(tcg_res[pass], tcg_res[pass], tcg_op1); | |
9093 | break; | |
9094 | } | |
9095 | } | |
9096 | } | |
9097 | ||
9098 | write_vec_element(s, tcg_res[0], rd, 0, MO_64); | |
9099 | if (!is_q) { | |
9100 | tcg_gen_movi_i64(tcg_res[1], 0); | |
9101 | } | |
9102 | write_vec_element(s, tcg_res[1], rd, 1, MO_64); | |
9103 | ||
9104 | tcg_temp_free_i64(tcg_op1); | |
9105 | tcg_temp_free_i64(tcg_op2); | |
9106 | tcg_temp_free_i64(tcg_res[0]); | |
9107 | tcg_temp_free_i64(tcg_res[1]); | |
e1cea114 PM |
9108 | } |
9109 | ||
8b12a0cf PM |
9110 | /* Helper functions for 32 bit comparisons */ |
9111 | static void gen_max_s32(TCGv_i32 res, TCGv_i32 op1, TCGv_i32 op2) | |
9112 | { | |
9113 | tcg_gen_movcond_i32(TCG_COND_GE, res, op1, op2, op1, op2); | |
9114 | } | |
9115 | ||
9116 | static void gen_max_u32(TCGv_i32 res, TCGv_i32 op1, TCGv_i32 op2) | |
9117 | { | |
9118 | tcg_gen_movcond_i32(TCG_COND_GEU, res, op1, op2, op1, op2); | |
9119 | } | |
9120 | ||
9121 | static void gen_min_s32(TCGv_i32 res, TCGv_i32 op1, TCGv_i32 op2) | |
9122 | { | |
9123 | tcg_gen_movcond_i32(TCG_COND_LE, res, op1, op2, op1, op2); | |
9124 | } | |
9125 | ||
9126 | static void gen_min_u32(TCGv_i32 res, TCGv_i32 op1, TCGv_i32 op2) | |
9127 | { | |
9128 | tcg_gen_movcond_i32(TCG_COND_LEU, res, op1, op2, op1, op2); | |
9129 | } | |
9130 | ||
bc242f9b AB |
9131 | /* Pairwise op subgroup of C3.6.16. |
9132 | * | |
9133 | * This is called directly or via the handle_3same_float for float pairwise | |
9134 | * operations where the opcode and size are calculated differently. | |
9135 | */ | |
9136 | static void handle_simd_3same_pair(DisasContext *s, int is_q, int u, int opcode, | |
9137 | int size, int rn, int rm, int rd) | |
e1cea114 | 9138 | { |
bc242f9b | 9139 | TCGv_ptr fpst; |
0173a005 PM |
9140 | int pass; |
9141 | ||
bc242f9b AB |
9142 | /* Floating point operations need fpst */ |
9143 | if (opcode >= 0x58) { | |
9144 | fpst = get_fpstatus_ptr(); | |
9145 | } else { | |
9146 | TCGV_UNUSED_PTR(fpst); | |
0173a005 PM |
9147 | } |
9148 | ||
8c6afa6a PM |
9149 | if (!fp_access_check(s)) { |
9150 | return; | |
9151 | } | |
9152 | ||
0173a005 PM |
9153 | /* These operations work on the concatenated rm:rn, with each pair of |
9154 | * adjacent elements being operated on to produce an element in the result. | |
9155 | */ | |
9156 | if (size == 3) { | |
9157 | TCGv_i64 tcg_res[2]; | |
9158 | ||
9159 | for (pass = 0; pass < 2; pass++) { | |
9160 | TCGv_i64 tcg_op1 = tcg_temp_new_i64(); | |
9161 | TCGv_i64 tcg_op2 = tcg_temp_new_i64(); | |
9162 | int passreg = (pass == 0) ? rn : rm; | |
9163 | ||
9164 | read_vec_element(s, tcg_op1, passreg, 0, MO_64); | |
9165 | read_vec_element(s, tcg_op2, passreg, 1, MO_64); | |
9166 | tcg_res[pass] = tcg_temp_new_i64(); | |
9167 | ||
bc242f9b AB |
9168 | switch (opcode) { |
9169 | case 0x17: /* ADDP */ | |
9170 | tcg_gen_add_i64(tcg_res[pass], tcg_op1, tcg_op2); | |
9171 | break; | |
9172 | case 0x58: /* FMAXNMP */ | |
9173 | gen_helper_vfp_maxnumd(tcg_res[pass], tcg_op1, tcg_op2, fpst); | |
9174 | break; | |
9175 | case 0x5a: /* FADDP */ | |
9176 | gen_helper_vfp_addd(tcg_res[pass], tcg_op1, tcg_op2, fpst); | |
9177 | break; | |
9178 | case 0x5e: /* FMAXP */ | |
9179 | gen_helper_vfp_maxd(tcg_res[pass], tcg_op1, tcg_op2, fpst); | |
9180 | break; | |
9181 | case 0x78: /* FMINNMP */ | |
9182 | gen_helper_vfp_minnumd(tcg_res[pass], tcg_op1, tcg_op2, fpst); | |
9183 | break; | |
9184 | case 0x7e: /* FMINP */ | |
9185 | gen_helper_vfp_mind(tcg_res[pass], tcg_op1, tcg_op2, fpst); | |
9186 | break; | |
9187 | default: | |
9188 | g_assert_not_reached(); | |
9189 | } | |
0173a005 PM |
9190 | |
9191 | tcg_temp_free_i64(tcg_op1); | |
9192 | tcg_temp_free_i64(tcg_op2); | |
9193 | } | |
9194 | ||
9195 | for (pass = 0; pass < 2; pass++) { | |
9196 | write_vec_element(s, tcg_res[pass], rd, pass, MO_64); | |
9197 | tcg_temp_free_i64(tcg_res[pass]); | |
9198 | } | |
9199 | } else { | |
9200 | int maxpass = is_q ? 4 : 2; | |
9201 | TCGv_i32 tcg_res[4]; | |
9202 | ||
9203 | for (pass = 0; pass < maxpass; pass++) { | |
9204 | TCGv_i32 tcg_op1 = tcg_temp_new_i32(); | |
9205 | TCGv_i32 tcg_op2 = tcg_temp_new_i32(); | |
bc242f9b | 9206 | NeonGenTwoOpFn *genfn = NULL; |
0173a005 PM |
9207 | int passreg = pass < (maxpass / 2) ? rn : rm; |
9208 | int passelt = (is_q && (pass & 1)) ? 2 : 0; | |
9209 | ||
9210 | read_vec_element_i32(s, tcg_op1, passreg, passelt, MO_32); | |
9211 | read_vec_element_i32(s, tcg_op2, passreg, passelt + 1, MO_32); | |
9212 | tcg_res[pass] = tcg_temp_new_i32(); | |
9213 | ||
9214 | switch (opcode) { | |
9215 | case 0x17: /* ADDP */ | |
9216 | { | |
9217 | static NeonGenTwoOpFn * const fns[3] = { | |
9218 | gen_helper_neon_padd_u8, | |
9219 | gen_helper_neon_padd_u16, | |
9220 | tcg_gen_add_i32, | |
9221 | }; | |
9222 | genfn = fns[size]; | |
9223 | break; | |
9224 | } | |
9225 | case 0x14: /* SMAXP, UMAXP */ | |
9226 | { | |
9227 | static NeonGenTwoOpFn * const fns[3][2] = { | |
9228 | { gen_helper_neon_pmax_s8, gen_helper_neon_pmax_u8 }, | |
9229 | { gen_helper_neon_pmax_s16, gen_helper_neon_pmax_u16 }, | |
9230 | { gen_max_s32, gen_max_u32 }, | |
9231 | }; | |
9232 | genfn = fns[size][u]; | |
9233 | break; | |
9234 | } | |
9235 | case 0x15: /* SMINP, UMINP */ | |
9236 | { | |
9237 | static NeonGenTwoOpFn * const fns[3][2] = { | |
9238 | { gen_helper_neon_pmin_s8, gen_helper_neon_pmin_u8 }, | |
9239 | { gen_helper_neon_pmin_s16, gen_helper_neon_pmin_u16 }, | |
9240 | { gen_min_s32, gen_min_u32 }, | |
9241 | }; | |
9242 | genfn = fns[size][u]; | |
9243 | break; | |
9244 | } | |
bc242f9b AB |
9245 | /* The FP operations are all on single floats (32 bit) */ |
9246 | case 0x58: /* FMAXNMP */ | |
9247 | gen_helper_vfp_maxnums(tcg_res[pass], tcg_op1, tcg_op2, fpst); | |
9248 | break; | |
9249 | case 0x5a: /* FADDP */ | |
9250 | gen_helper_vfp_adds(tcg_res[pass], tcg_op1, tcg_op2, fpst); | |
9251 | break; | |
9252 | case 0x5e: /* FMAXP */ | |
9253 | gen_helper_vfp_maxs(tcg_res[pass], tcg_op1, tcg_op2, fpst); | |
9254 | break; | |
9255 | case 0x78: /* FMINNMP */ | |
9256 | gen_helper_vfp_minnums(tcg_res[pass], tcg_op1, tcg_op2, fpst); | |
9257 | break; | |
9258 | case 0x7e: /* FMINP */ | |
9259 | gen_helper_vfp_mins(tcg_res[pass], tcg_op1, tcg_op2, fpst); | |
9260 | break; | |
0173a005 PM |
9261 | default: |
9262 | g_assert_not_reached(); | |
9263 | } | |
9264 | ||
bc242f9b AB |
9265 | /* FP ops called directly, otherwise call now */ |
9266 | if (genfn) { | |
9267 | genfn(tcg_res[pass], tcg_op1, tcg_op2); | |
9268 | } | |
0173a005 PM |
9269 | |
9270 | tcg_temp_free_i32(tcg_op1); | |
9271 | tcg_temp_free_i32(tcg_op2); | |
9272 | } | |
9273 | ||
9274 | for (pass = 0; pass < maxpass; pass++) { | |
9275 | write_vec_element_i32(s, tcg_res[pass], rd, pass, MO_32); | |
9276 | tcg_temp_free_i32(tcg_res[pass]); | |
9277 | } | |
9278 | if (!is_q) { | |
9279 | clear_vec_high(s, rd); | |
9280 | } | |
9281 | } | |
bc242f9b AB |
9282 | |
9283 | if (!TCGV_IS_UNUSED_PTR(fpst)) { | |
9284 | tcg_temp_free_ptr(fpst); | |
9285 | } | |
e1cea114 PM |
9286 | } |
9287 | ||
9288 | /* Floating point op subgroup of C3.6.16. */ | |
9289 | static void disas_simd_3same_float(DisasContext *s, uint32_t insn) | |
9290 | { | |
845ea09a PM |
9291 | /* For floating point ops, the U, size[1] and opcode bits |
9292 | * together indicate the operation. size[0] indicates single | |
9293 | * or double. | |
9294 | */ | |
9295 | int fpopcode = extract32(insn, 11, 5) | |
9296 | | (extract32(insn, 23, 1) << 5) | |
9297 | | (extract32(insn, 29, 1) << 6); | |
9298 | int is_q = extract32(insn, 30, 1); | |
9299 | int size = extract32(insn, 22, 1); | |
9300 | int rm = extract32(insn, 16, 5); | |
9301 | int rn = extract32(insn, 5, 5); | |
9302 | int rd = extract32(insn, 0, 5); | |
9303 | ||
9304 | int datasize = is_q ? 128 : 64; | |
9305 | int esize = 32 << size; | |
9306 | int elements = datasize / esize; | |
9307 | ||
9308 | if (size == 1 && !is_q) { | |
9309 | unallocated_encoding(s); | |
9310 | return; | |
9311 | } | |
9312 | ||
9313 | switch (fpopcode) { | |
9314 | case 0x58: /* FMAXNMP */ | |
9315 | case 0x5a: /* FADDP */ | |
9316 | case 0x5e: /* FMAXP */ | |
9317 | case 0x78: /* FMINNMP */ | |
9318 | case 0x7e: /* FMINP */ | |
bc242f9b AB |
9319 | if (size && !is_q) { |
9320 | unallocated_encoding(s); | |
9321 | return; | |
9322 | } | |
9323 | handle_simd_3same_pair(s, is_q, 0, fpopcode, size ? MO_64 : MO_32, | |
9324 | rn, rm, rd); | |
845ea09a PM |
9325 | return; |
9326 | case 0x1b: /* FMULX */ | |
845ea09a PM |
9327 | case 0x1f: /* FRECPS */ |
9328 | case 0x3f: /* FRSQRTS */ | |
845ea09a | 9329 | case 0x5d: /* FACGE */ |
845ea09a PM |
9330 | case 0x7d: /* FACGT */ |
9331 | case 0x19: /* FMLA */ | |
9332 | case 0x39: /* FMLS */ | |
845ea09a PM |
9333 | case 0x18: /* FMAXNM */ |
9334 | case 0x1a: /* FADD */ | |
8908f4d1 | 9335 | case 0x1c: /* FCMEQ */ |
845ea09a PM |
9336 | case 0x1e: /* FMAX */ |
9337 | case 0x38: /* FMINNM */ | |
9338 | case 0x3a: /* FSUB */ | |
9339 | case 0x3e: /* FMIN */ | |
9340 | case 0x5b: /* FMUL */ | |
8908f4d1 | 9341 | case 0x5c: /* FCMGE */ |
845ea09a PM |
9342 | case 0x5f: /* FDIV */ |
9343 | case 0x7a: /* FABD */ | |
8908f4d1 | 9344 | case 0x7c: /* FCMGT */ |
8c6afa6a PM |
9345 | if (!fp_access_check(s)) { |
9346 | return; | |
9347 | } | |
9348 | ||
845ea09a PM |
9349 | handle_3same_float(s, size, elements, fpopcode, rd, rn, rm); |
9350 | return; | |
9351 | default: | |
9352 | unallocated_encoding(s); | |
9353 | return; | |
9354 | } | |
e1cea114 PM |
9355 | } |
9356 | ||
9357 | /* Integer op subgroup of C3.6.16. */ | |
9358 | static void disas_simd_3same_int(DisasContext *s, uint32_t insn) | |
9359 | { | |
1f8a73af PM |
9360 | int is_q = extract32(insn, 30, 1); |
9361 | int u = extract32(insn, 29, 1); | |
9362 | int size = extract32(insn, 22, 2); | |
9363 | int opcode = extract32(insn, 11, 5); | |
9364 | int rm = extract32(insn, 16, 5); | |
9365 | int rn = extract32(insn, 5, 5); | |
9366 | int rd = extract32(insn, 0, 5); | |
9367 | int pass; | |
9368 | ||
9369 | switch (opcode) { | |
9370 | case 0x13: /* MUL, PMUL */ | |
9371 | if (u && size != 0) { | |
9372 | unallocated_encoding(s); | |
9373 | return; | |
9374 | } | |
9375 | /* fall through */ | |
9376 | case 0x0: /* SHADD, UHADD */ | |
9377 | case 0x2: /* SRHADD, URHADD */ | |
9378 | case 0x4: /* SHSUB, UHSUB */ | |
9379 | case 0xc: /* SMAX, UMAX */ | |
9380 | case 0xd: /* SMIN, UMIN */ | |
9381 | case 0xe: /* SABD, UABD */ | |
9382 | case 0xf: /* SABA, UABA */ | |
9383 | case 0x12: /* MLA, MLS */ | |
9384 | if (size == 3) { | |
9385 | unallocated_encoding(s); | |
9386 | return; | |
9387 | } | |
8b12a0cf | 9388 | break; |
1f8a73af PM |
9389 | case 0x16: /* SQDMULH, SQRDMULH */ |
9390 | if (size == 0 || size == 3) { | |
9391 | unallocated_encoding(s); | |
9392 | return; | |
9393 | } | |
8b12a0cf | 9394 | break; |
1f8a73af PM |
9395 | default: |
9396 | if (size == 3 && !is_q) { | |
9397 | unallocated_encoding(s); | |
9398 | return; | |
9399 | } | |
9400 | break; | |
9401 | } | |
9402 | ||
8c6afa6a PM |
9403 | if (!fp_access_check(s)) { |
9404 | return; | |
9405 | } | |
9406 | ||
1f8a73af | 9407 | if (size == 3) { |
220ad4ca PM |
9408 | assert(is_q); |
9409 | for (pass = 0; pass < 2; pass++) { | |
1f8a73af PM |
9410 | TCGv_i64 tcg_op1 = tcg_temp_new_i64(); |
9411 | TCGv_i64 tcg_op2 = tcg_temp_new_i64(); | |
9412 | TCGv_i64 tcg_res = tcg_temp_new_i64(); | |
9413 | ||
9414 | read_vec_element(s, tcg_op1, rn, pass, MO_64); | |
9415 | read_vec_element(s, tcg_op2, rm, pass, MO_64); | |
9416 | ||
9417 | handle_3same_64(s, opcode, u, tcg_res, tcg_op1, tcg_op2); | |
9418 | ||
9419 | write_vec_element(s, tcg_res, rd, pass, MO_64); | |
9420 | ||
9421 | tcg_temp_free_i64(tcg_res); | |
9422 | tcg_temp_free_i64(tcg_op1); | |
9423 | tcg_temp_free_i64(tcg_op2); | |
9424 | } | |
9425 | } else { | |
9426 | for (pass = 0; pass < (is_q ? 4 : 2); pass++) { | |
9427 | TCGv_i32 tcg_op1 = tcg_temp_new_i32(); | |
9428 | TCGv_i32 tcg_op2 = tcg_temp_new_i32(); | |
9429 | TCGv_i32 tcg_res = tcg_temp_new_i32(); | |
6d9571f7 PM |
9430 | NeonGenTwoOpFn *genfn = NULL; |
9431 | NeonGenTwoOpEnvFn *genenvfn = NULL; | |
1f8a73af PM |
9432 | |
9433 | read_vec_element_i32(s, tcg_op1, rn, pass, MO_32); | |
9434 | read_vec_element_i32(s, tcg_op2, rm, pass, MO_32); | |
9435 | ||
9436 | switch (opcode) { | |
8b12a0cf PM |
9437 | case 0x0: /* SHADD, UHADD */ |
9438 | { | |
9439 | static NeonGenTwoOpFn * const fns[3][2] = { | |
9440 | { gen_helper_neon_hadd_s8, gen_helper_neon_hadd_u8 }, | |
9441 | { gen_helper_neon_hadd_s16, gen_helper_neon_hadd_u16 }, | |
9442 | { gen_helper_neon_hadd_s32, gen_helper_neon_hadd_u32 }, | |
9443 | }; | |
9444 | genfn = fns[size][u]; | |
9445 | break; | |
9446 | } | |
6d9571f7 PM |
9447 | case 0x1: /* SQADD, UQADD */ |
9448 | { | |
9449 | static NeonGenTwoOpEnvFn * const fns[3][2] = { | |
9450 | { gen_helper_neon_qadd_s8, gen_helper_neon_qadd_u8 }, | |
9451 | { gen_helper_neon_qadd_s16, gen_helper_neon_qadd_u16 }, | |
9452 | { gen_helper_neon_qadd_s32, gen_helper_neon_qadd_u32 }, | |
9453 | }; | |
9454 | genenvfn = fns[size][u]; | |
9455 | break; | |
9456 | } | |
8b12a0cf PM |
9457 | case 0x2: /* SRHADD, URHADD */ |
9458 | { | |
9459 | static NeonGenTwoOpFn * const fns[3][2] = { | |
9460 | { gen_helper_neon_rhadd_s8, gen_helper_neon_rhadd_u8 }, | |
9461 | { gen_helper_neon_rhadd_s16, gen_helper_neon_rhadd_u16 }, | |
9462 | { gen_helper_neon_rhadd_s32, gen_helper_neon_rhadd_u32 }, | |
9463 | }; | |
9464 | genfn = fns[size][u]; | |
9465 | break; | |
9466 | } | |
9467 | case 0x4: /* SHSUB, UHSUB */ | |
9468 | { | |
9469 | static NeonGenTwoOpFn * const fns[3][2] = { | |
9470 | { gen_helper_neon_hsub_s8, gen_helper_neon_hsub_u8 }, | |
9471 | { gen_helper_neon_hsub_s16, gen_helper_neon_hsub_u16 }, | |
9472 | { gen_helper_neon_hsub_s32, gen_helper_neon_hsub_u32 }, | |
9473 | }; | |
9474 | genfn = fns[size][u]; | |
9475 | break; | |
9476 | } | |
6d9571f7 PM |
9477 | case 0x5: /* SQSUB, UQSUB */ |
9478 | { | |
9479 | static NeonGenTwoOpEnvFn * const fns[3][2] = { | |
9480 | { gen_helper_neon_qsub_s8, gen_helper_neon_qsub_u8 }, | |
9481 | { gen_helper_neon_qsub_s16, gen_helper_neon_qsub_u16 }, | |
9482 | { gen_helper_neon_qsub_s32, gen_helper_neon_qsub_u32 }, | |
9483 | }; | |
9484 | genenvfn = fns[size][u]; | |
9485 | break; | |
9486 | } | |
1f8a73af PM |
9487 | case 0x6: /* CMGT, CMHI */ |
9488 | { | |
9489 | static NeonGenTwoOpFn * const fns[3][2] = { | |
9490 | { gen_helper_neon_cgt_s8, gen_helper_neon_cgt_u8 }, | |
9491 | { gen_helper_neon_cgt_s16, gen_helper_neon_cgt_u16 }, | |
9492 | { gen_helper_neon_cgt_s32, gen_helper_neon_cgt_u32 }, | |
9493 | }; | |
9494 | genfn = fns[size][u]; | |
9495 | break; | |
9496 | } | |
9497 | case 0x7: /* CMGE, CMHS */ | |
9498 | { | |
9499 | static NeonGenTwoOpFn * const fns[3][2] = { | |
9500 | { gen_helper_neon_cge_s8, gen_helper_neon_cge_u8 }, | |
9501 | { gen_helper_neon_cge_s16, gen_helper_neon_cge_u16 }, | |
9502 | { gen_helper_neon_cge_s32, gen_helper_neon_cge_u32 }, | |
9503 | }; | |
9504 | genfn = fns[size][u]; | |
9505 | break; | |
9506 | } | |
6d9571f7 PM |
9507 | case 0x8: /* SSHL, USHL */ |
9508 | { | |
9509 | static NeonGenTwoOpFn * const fns[3][2] = { | |
9510 | { gen_helper_neon_shl_s8, gen_helper_neon_shl_u8 }, | |
9511 | { gen_helper_neon_shl_s16, gen_helper_neon_shl_u16 }, | |
9512 | { gen_helper_neon_shl_s32, gen_helper_neon_shl_u32 }, | |
9513 | }; | |
9514 | genfn = fns[size][u]; | |
9515 | break; | |
9516 | } | |
9517 | case 0x9: /* SQSHL, UQSHL */ | |
9518 | { | |
9519 | static NeonGenTwoOpEnvFn * const fns[3][2] = { | |
9520 | { gen_helper_neon_qshl_s8, gen_helper_neon_qshl_u8 }, | |
9521 | { gen_helper_neon_qshl_s16, gen_helper_neon_qshl_u16 }, | |
9522 | { gen_helper_neon_qshl_s32, gen_helper_neon_qshl_u32 }, | |
9523 | }; | |
9524 | genenvfn = fns[size][u]; | |
9525 | break; | |
9526 | } | |
9527 | case 0xa: /* SRSHL, URSHL */ | |
9528 | { | |
9529 | static NeonGenTwoOpFn * const fns[3][2] = { | |
9530 | { gen_helper_neon_rshl_s8, gen_helper_neon_rshl_u8 }, | |
9531 | { gen_helper_neon_rshl_s16, gen_helper_neon_rshl_u16 }, | |
9532 | { gen_helper_neon_rshl_s32, gen_helper_neon_rshl_u32 }, | |
9533 | }; | |
9534 | genfn = fns[size][u]; | |
9535 | break; | |
9536 | } | |
9537 | case 0xb: /* SQRSHL, UQRSHL */ | |
9538 | { | |
9539 | static NeonGenTwoOpEnvFn * const fns[3][2] = { | |
9540 | { gen_helper_neon_qrshl_s8, gen_helper_neon_qrshl_u8 }, | |
9541 | { gen_helper_neon_qrshl_s16, gen_helper_neon_qrshl_u16 }, | |
9542 | { gen_helper_neon_qrshl_s32, gen_helper_neon_qrshl_u32 }, | |
9543 | }; | |
9544 | genenvfn = fns[size][u]; | |
9545 | break; | |
9546 | } | |
8b12a0cf PM |
9547 | case 0xc: /* SMAX, UMAX */ |
9548 | { | |
9549 | static NeonGenTwoOpFn * const fns[3][2] = { | |
9550 | { gen_helper_neon_max_s8, gen_helper_neon_max_u8 }, | |
9551 | { gen_helper_neon_max_s16, gen_helper_neon_max_u16 }, | |
9552 | { gen_max_s32, gen_max_u32 }, | |
9553 | }; | |
9554 | genfn = fns[size][u]; | |
9555 | break; | |
9556 | } | |
9557 | ||
9558 | case 0xd: /* SMIN, UMIN */ | |
9559 | { | |
9560 | static NeonGenTwoOpFn * const fns[3][2] = { | |
9561 | { gen_helper_neon_min_s8, gen_helper_neon_min_u8 }, | |
9562 | { gen_helper_neon_min_s16, gen_helper_neon_min_u16 }, | |
9563 | { gen_min_s32, gen_min_u32 }, | |
9564 | }; | |
9565 | genfn = fns[size][u]; | |
9566 | break; | |
9567 | } | |
9568 | case 0xe: /* SABD, UABD */ | |
9569 | case 0xf: /* SABA, UABA */ | |
9570 | { | |
9571 | static NeonGenTwoOpFn * const fns[3][2] = { | |
9572 | { gen_helper_neon_abd_s8, gen_helper_neon_abd_u8 }, | |
9573 | { gen_helper_neon_abd_s16, gen_helper_neon_abd_u16 }, | |
9574 | { gen_helper_neon_abd_s32, gen_helper_neon_abd_u32 }, | |
9575 | }; | |
9576 | genfn = fns[size][u]; | |
9577 | break; | |
9578 | } | |
1f8a73af PM |
9579 | case 0x10: /* ADD, SUB */ |
9580 | { | |
9581 | static NeonGenTwoOpFn * const fns[3][2] = { | |
9582 | { gen_helper_neon_add_u8, gen_helper_neon_sub_u8 }, | |
9583 | { gen_helper_neon_add_u16, gen_helper_neon_sub_u16 }, | |
9584 | { tcg_gen_add_i32, tcg_gen_sub_i32 }, | |
9585 | }; | |
9586 | genfn = fns[size][u]; | |
9587 | break; | |
9588 | } | |
9589 | case 0x11: /* CMTST, CMEQ */ | |
9590 | { | |
9591 | static NeonGenTwoOpFn * const fns[3][2] = { | |
9592 | { gen_helper_neon_tst_u8, gen_helper_neon_ceq_u8 }, | |
9593 | { gen_helper_neon_tst_u16, gen_helper_neon_ceq_u16 }, | |
9594 | { gen_helper_neon_tst_u32, gen_helper_neon_ceq_u32 }, | |
9595 | }; | |
9596 | genfn = fns[size][u]; | |
9597 | break; | |
9598 | } | |
8b12a0cf PM |
9599 | case 0x13: /* MUL, PMUL */ |
9600 | if (u) { | |
9601 | /* PMUL */ | |
9602 | assert(size == 0); | |
9603 | genfn = gen_helper_neon_mul_p8; | |
9604 | break; | |
9605 | } | |
9606 | /* fall through : MUL */ | |
9607 | case 0x12: /* MLA, MLS */ | |
9608 | { | |
9609 | static NeonGenTwoOpFn * const fns[3] = { | |
9610 | gen_helper_neon_mul_u8, | |
9611 | gen_helper_neon_mul_u16, | |
9612 | tcg_gen_mul_i32, | |
9613 | }; | |
9614 | genfn = fns[size]; | |
9615 | break; | |
9616 | } | |
9617 | case 0x16: /* SQDMULH, SQRDMULH */ | |
9618 | { | |
9619 | static NeonGenTwoOpEnvFn * const fns[2][2] = { | |
9620 | { gen_helper_neon_qdmulh_s16, gen_helper_neon_qrdmulh_s16 }, | |
9621 | { gen_helper_neon_qdmulh_s32, gen_helper_neon_qrdmulh_s32 }, | |
9622 | }; | |
9623 | assert(size == 1 || size == 2); | |
9624 | genenvfn = fns[size - 1][u]; | |
9625 | break; | |
9626 | } | |
1f8a73af PM |
9627 | default: |
9628 | g_assert_not_reached(); | |
9629 | } | |
9630 | ||
6d9571f7 PM |
9631 | if (genenvfn) { |
9632 | genenvfn(tcg_res, cpu_env, tcg_op1, tcg_op2); | |
9633 | } else { | |
9634 | genfn(tcg_res, tcg_op1, tcg_op2); | |
9635 | } | |
1f8a73af | 9636 | |
8b12a0cf PM |
9637 | if (opcode == 0xf || opcode == 0x12) { |
9638 | /* SABA, UABA, MLA, MLS: accumulating ops */ | |
9639 | static NeonGenTwoOpFn * const fns[3][2] = { | |
9640 | { gen_helper_neon_add_u8, gen_helper_neon_sub_u8 }, | |
9641 | { gen_helper_neon_add_u16, gen_helper_neon_sub_u16 }, | |
9642 | { tcg_gen_add_i32, tcg_gen_sub_i32 }, | |
9643 | }; | |
9644 | bool is_sub = (opcode == 0x12 && u); /* MLS */ | |
9645 | ||
9646 | genfn = fns[size][is_sub]; | |
9647 | read_vec_element_i32(s, tcg_op1, rd, pass, MO_32); | |
d108609b | 9648 | genfn(tcg_res, tcg_op1, tcg_res); |
8b12a0cf PM |
9649 | } |
9650 | ||
1f8a73af PM |
9651 | write_vec_element_i32(s, tcg_res, rd, pass, MO_32); |
9652 | ||
9653 | tcg_temp_free_i32(tcg_res); | |
9654 | tcg_temp_free_i32(tcg_op1); | |
9655 | tcg_temp_free_i32(tcg_op2); | |
9656 | } | |
9657 | } | |
9658 | ||
9659 | if (!is_q) { | |
9660 | clear_vec_high(s, rd); | |
9661 | } | |
e1cea114 PM |
9662 | } |
9663 | ||
384b26fb AB |
9664 | /* C3.6.16 AdvSIMD three same |
9665 | * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0 | |
9666 | * +---+---+---+-----------+------+---+------+--------+---+------+------+ | |
9667 | * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd | | |
9668 | * +---+---+---+-----------+------+---+------+--------+---+------+------+ | |
9669 | */ | |
9670 | static void disas_simd_three_reg_same(DisasContext *s, uint32_t insn) | |
9671 | { | |
e1cea114 PM |
9672 | int opcode = extract32(insn, 11, 5); |
9673 | ||
9674 | switch (opcode) { | |
9675 | case 0x3: /* logic ops */ | |
9676 | disas_simd_3same_logic(s, insn); | |
9677 | break; | |
9678 | case 0x17: /* ADDP */ | |
9679 | case 0x14: /* SMAXP, UMAXP */ | |
9680 | case 0x15: /* SMINP, UMINP */ | |
bc242f9b | 9681 | { |
e1cea114 | 9682 | /* Pairwise operations */ |
bc242f9b AB |
9683 | int is_q = extract32(insn, 30, 1); |
9684 | int u = extract32(insn, 29, 1); | |
9685 | int size = extract32(insn, 22, 2); | |
9686 | int rm = extract32(insn, 16, 5); | |
9687 | int rn = extract32(insn, 5, 5); | |
9688 | int rd = extract32(insn, 0, 5); | |
9689 | if (opcode == 0x17) { | |
9690 | if (u || (size == 3 && !is_q)) { | |
9691 | unallocated_encoding(s); | |
9692 | return; | |
9693 | } | |
9694 | } else { | |
9695 | if (size == 3) { | |
9696 | unallocated_encoding(s); | |
9697 | return; | |
9698 | } | |
9699 | } | |
9700 | handle_simd_3same_pair(s, is_q, u, opcode, size, rn, rm, rd); | |
e1cea114 | 9701 | break; |
bc242f9b | 9702 | } |
e1cea114 PM |
9703 | case 0x18 ... 0x31: |
9704 | /* floating point ops, sz[1] and U are part of opcode */ | |
9705 | disas_simd_3same_float(s, insn); | |
9706 | break; | |
9707 | default: | |
9708 | disas_simd_3same_int(s, insn); | |
9709 | break; | |
9710 | } | |
384b26fb AB |
9711 | } |
9712 | ||
931c8cc2 PM |
9713 | static void handle_2misc_widening(DisasContext *s, int opcode, bool is_q, |
9714 | int size, int rn, int rd) | |
9715 | { | |
9716 | /* Handle 2-reg-misc ops which are widening (so each size element | |
9717 | * in the source becomes a 2*size element in the destination. | |
9718 | * The only instruction like this is FCVTL. | |
9719 | */ | |
9720 | int pass; | |
9721 | ||
9722 | if (size == 3) { | |
9723 | /* 32 -> 64 bit fp conversion */ | |
9724 | TCGv_i64 tcg_res[2]; | |
9725 | int srcelt = is_q ? 2 : 0; | |
9726 | ||
9727 | for (pass = 0; pass < 2; pass++) { | |
9728 | TCGv_i32 tcg_op = tcg_temp_new_i32(); | |
9729 | tcg_res[pass] = tcg_temp_new_i64(); | |
9730 | ||
9731 | read_vec_element_i32(s, tcg_op, rn, srcelt + pass, MO_32); | |
9732 | gen_helper_vfp_fcvtds(tcg_res[pass], tcg_op, cpu_env); | |
9733 | tcg_temp_free_i32(tcg_op); | |
9734 | } | |
9735 | for (pass = 0; pass < 2; pass++) { | |
9736 | write_vec_element(s, tcg_res[pass], rd, pass, MO_64); | |
9737 | tcg_temp_free_i64(tcg_res[pass]); | |
9738 | } | |
9739 | } else { | |
9740 | /* 16 -> 32 bit fp conversion */ | |
9741 | int srcelt = is_q ? 4 : 0; | |
9742 | TCGv_i32 tcg_res[4]; | |
9743 | ||
9744 | for (pass = 0; pass < 4; pass++) { | |
9745 | tcg_res[pass] = tcg_temp_new_i32(); | |
9746 | ||
9747 | read_vec_element_i32(s, tcg_res[pass], rn, srcelt + pass, MO_16); | |
9748 | gen_helper_vfp_fcvt_f16_to_f32(tcg_res[pass], tcg_res[pass], | |
9749 | cpu_env); | |
9750 | } | |
9751 | for (pass = 0; pass < 4; pass++) { | |
9752 | write_vec_element_i32(s, tcg_res[pass], rd, pass, MO_32); | |
9753 | tcg_temp_free_i32(tcg_res[pass]); | |
9754 | } | |
9755 | } | |
9756 | } | |
9757 | ||
39d82118 AB |
9758 | static void handle_rev(DisasContext *s, int opcode, bool u, |
9759 | bool is_q, int size, int rn, int rd) | |
9760 | { | |
9761 | int op = (opcode << 1) | u; | |
9762 | int opsz = op + size; | |
9763 | int grp_size = 3 - opsz; | |
9764 | int dsize = is_q ? 128 : 64; | |
9765 | int i; | |
9766 | ||
9767 | if (opsz >= 3) { | |
9768 | unallocated_encoding(s); | |
9769 | return; | |
9770 | } | |
9771 | ||
8c6afa6a PM |
9772 | if (!fp_access_check(s)) { |
9773 | return; | |
9774 | } | |
9775 | ||
39d82118 AB |
9776 | if (size == 0) { |
9777 | /* Special case bytes, use bswap op on each group of elements */ | |
9778 | int groups = dsize / (8 << grp_size); | |
9779 | ||
9780 | for (i = 0; i < groups; i++) { | |
9781 | TCGv_i64 tcg_tmp = tcg_temp_new_i64(); | |
9782 | ||
9783 | read_vec_element(s, tcg_tmp, rn, i, grp_size); | |
9784 | switch (grp_size) { | |
9785 | case MO_16: | |
9786 | tcg_gen_bswap16_i64(tcg_tmp, tcg_tmp); | |
9787 | break; | |
9788 | case MO_32: | |
9789 | tcg_gen_bswap32_i64(tcg_tmp, tcg_tmp); | |
9790 | break; | |
9791 | case MO_64: | |
9792 | tcg_gen_bswap64_i64(tcg_tmp, tcg_tmp); | |
9793 | break; | |
9794 | default: | |
9795 | g_assert_not_reached(); | |
9796 | } | |
9797 | write_vec_element(s, tcg_tmp, rd, i, grp_size); | |
9798 | tcg_temp_free_i64(tcg_tmp); | |
9799 | } | |
9800 | if (!is_q) { | |
9801 | clear_vec_high(s, rd); | |
9802 | } | |
9803 | } else { | |
9804 | int revmask = (1 << grp_size) - 1; | |
9805 | int esize = 8 << size; | |
9806 | int elements = dsize / esize; | |
9807 | TCGv_i64 tcg_rn = tcg_temp_new_i64(); | |
9808 | TCGv_i64 tcg_rd = tcg_const_i64(0); | |
9809 | TCGv_i64 tcg_rd_hi = tcg_const_i64(0); | |
9810 | ||
9811 | for (i = 0; i < elements; i++) { | |
9812 | int e_rev = (i & 0xf) ^ revmask; | |
9813 | int off = e_rev * esize; | |
9814 | read_vec_element(s, tcg_rn, rn, i, size); | |
9815 | if (off >= 64) { | |
9816 | tcg_gen_deposit_i64(tcg_rd_hi, tcg_rd_hi, | |
9817 | tcg_rn, off - 64, esize); | |
9818 | } else { | |
9819 | tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_rn, off, esize); | |
9820 | } | |
9821 | } | |
9822 | write_vec_element(s, tcg_rd, rd, 0, MO_64); | |
9823 | write_vec_element(s, tcg_rd_hi, rd, 1, MO_64); | |
9824 | ||
9825 | tcg_temp_free_i64(tcg_rd_hi); | |
9826 | tcg_temp_free_i64(tcg_rd); | |
9827 | tcg_temp_free_i64(tcg_rn); | |
9828 | } | |
9829 | } | |
9830 | ||
6781fa11 PM |
9831 | static void handle_2misc_pairwise(DisasContext *s, int opcode, bool u, |
9832 | bool is_q, int size, int rn, int rd) | |
9833 | { | |
9834 | /* Implement the pairwise operations from 2-misc: | |
9835 | * SADDLP, UADDLP, SADALP, UADALP. | |
9836 | * These all add pairs of elements in the input to produce a | |
9837 | * double-width result element in the output (possibly accumulating). | |
9838 | */ | |
9839 | bool accum = (opcode == 0x6); | |
9840 | int maxpass = is_q ? 2 : 1; | |
9841 | int pass; | |
9842 | TCGv_i64 tcg_res[2]; | |
9843 | ||
9844 | if (size == 2) { | |
9845 | /* 32 + 32 -> 64 op */ | |
9846 | TCGMemOp memop = size + (u ? 0 : MO_SIGN); | |
9847 | ||
9848 | for (pass = 0; pass < maxpass; pass++) { | |
9849 | TCGv_i64 tcg_op1 = tcg_temp_new_i64(); | |
9850 | TCGv_i64 tcg_op2 = tcg_temp_new_i64(); | |
9851 | ||
9852 | tcg_res[pass] = tcg_temp_new_i64(); | |
9853 | ||
9854 | read_vec_element(s, tcg_op1, rn, pass * 2, memop); | |
9855 | read_vec_element(s, tcg_op2, rn, pass * 2 + 1, memop); | |
9856 | tcg_gen_add_i64(tcg_res[pass], tcg_op1, tcg_op2); | |
9857 | if (accum) { | |
9858 | read_vec_element(s, tcg_op1, rd, pass, MO_64); | |
9859 | tcg_gen_add_i64(tcg_res[pass], tcg_res[pass], tcg_op1); | |
9860 | } | |
9861 | ||
9862 | tcg_temp_free_i64(tcg_op1); | |
9863 | tcg_temp_free_i64(tcg_op2); | |
9864 | } | |
9865 | } else { | |
9866 | for (pass = 0; pass < maxpass; pass++) { | |
9867 | TCGv_i64 tcg_op = tcg_temp_new_i64(); | |
9868 | NeonGenOneOpFn *genfn; | |
9869 | static NeonGenOneOpFn * const fns[2][2] = { | |
9870 | { gen_helper_neon_addlp_s8, gen_helper_neon_addlp_u8 }, | |
9871 | { gen_helper_neon_addlp_s16, gen_helper_neon_addlp_u16 }, | |
9872 | }; | |
9873 | ||
9874 | genfn = fns[size][u]; | |
9875 | ||
9876 | tcg_res[pass] = tcg_temp_new_i64(); | |
9877 | ||
9878 | read_vec_element(s, tcg_op, rn, pass, MO_64); | |
9879 | genfn(tcg_res[pass], tcg_op); | |
9880 | ||
9881 | if (accum) { | |
9882 | read_vec_element(s, tcg_op, rd, pass, MO_64); | |
9883 | if (size == 0) { | |
9884 | gen_helper_neon_addl_u16(tcg_res[pass], | |
9885 | tcg_res[pass], tcg_op); | |
9886 | } else { | |
9887 | gen_helper_neon_addl_u32(tcg_res[pass], | |
9888 | tcg_res[pass], tcg_op); | |
9889 | } | |
9890 | } | |
9891 | tcg_temp_free_i64(tcg_op); | |
9892 | } | |
9893 | } | |
9894 | if (!is_q) { | |
9895 | tcg_res[1] = tcg_const_i64(0); | |
9896 | } | |
9897 | for (pass = 0; pass < 2; pass++) { | |
9898 | write_vec_element(s, tcg_res[pass], rd, pass, MO_64); | |
9899 | tcg_temp_free_i64(tcg_res[pass]); | |
9900 | } | |
9901 | } | |
9902 | ||
73a81d10 PM |
9903 | static void handle_shll(DisasContext *s, bool is_q, int size, int rn, int rd) |
9904 | { | |
9905 | /* Implement SHLL and SHLL2 */ | |
9906 | int pass; | |
9907 | int part = is_q ? 2 : 0; | |
9908 | TCGv_i64 tcg_res[2]; | |
9909 | ||
9910 | for (pass = 0; pass < 2; pass++) { | |
9911 | static NeonGenWidenFn * const widenfns[3] = { | |
9912 | gen_helper_neon_widen_u8, | |
9913 | gen_helper_neon_widen_u16, | |
9914 | tcg_gen_extu_i32_i64, | |
9915 | }; | |
9916 | NeonGenWidenFn *widenfn = widenfns[size]; | |
9917 | TCGv_i32 tcg_op = tcg_temp_new_i32(); | |
9918 | ||
9919 | read_vec_element_i32(s, tcg_op, rn, part + pass, MO_32); | |
9920 | tcg_res[pass] = tcg_temp_new_i64(); | |
9921 | widenfn(tcg_res[pass], tcg_op); | |
9922 | tcg_gen_shli_i64(tcg_res[pass], tcg_res[pass], 8 << size); | |
9923 | ||
9924 | tcg_temp_free_i32(tcg_op); | |
9925 | } | |
9926 | ||
9927 | for (pass = 0; pass < 2; pass++) { | |
9928 | write_vec_element(s, tcg_res[pass], rd, pass, MO_64); | |
9929 | tcg_temp_free_i64(tcg_res[pass]); | |
9930 | } | |
9931 | } | |
9932 | ||
384b26fb AB |
9933 | /* C3.6.17 AdvSIMD two reg misc |
9934 | * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0 | |
9935 | * +---+---+---+-----------+------+-----------+--------+-----+------+------+ | |
9936 | * | 0 | Q | U | 0 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd | | |
9937 | * +---+---+---+-----------+------+-----------+--------+-----+------+------+ | |
9938 | */ | |
9939 | static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn) | |
9940 | { | |
45aecc6d PM |
9941 | int size = extract32(insn, 22, 2); |
9942 | int opcode = extract32(insn, 12, 5); | |
9943 | bool u = extract32(insn, 29, 1); | |
9944 | bool is_q = extract32(insn, 30, 1); | |
94b6c911 PM |
9945 | int rn = extract32(insn, 5, 5); |
9946 | int rd = extract32(insn, 0, 5); | |
04c7c6c2 PM |
9947 | bool need_fpstatus = false; |
9948 | bool need_rmode = false; | |
9949 | int rmode = -1; | |
9950 | TCGv_i32 tcg_rmode; | |
9951 | TCGv_ptr tcg_fpstatus; | |
45aecc6d PM |
9952 | |
9953 | switch (opcode) { | |
9954 | case 0x0: /* REV64, REV32 */ | |
9955 | case 0x1: /* REV16 */ | |
39d82118 | 9956 | handle_rev(s, opcode, u, is_q, size, rn, rd); |
45aecc6d | 9957 | return; |
86cbc418 PM |
9958 | case 0x5: /* CNT, NOT, RBIT */ |
9959 | if (u && size == 0) { | |
9960 | /* NOT: adjust size so we can use the 64-bits-at-a-time loop. */ | |
9961 | size = 3; | |
9962 | break; | |
9963 | } else if (u && size == 1) { | |
9964 | /* RBIT */ | |
9965 | break; | |
9966 | } else if (!u && size == 0) { | |
9967 | /* CNT */ | |
9968 | break; | |
45aecc6d | 9969 | } |
86cbc418 | 9970 | unallocated_encoding(s); |
45aecc6d | 9971 | return; |
d980fd59 PM |
9972 | case 0x12: /* XTN, XTN2, SQXTUN, SQXTUN2 */ |
9973 | case 0x14: /* SQXTN, SQXTN2, UQXTN, UQXTN2 */ | |
9974 | if (size == 3) { | |
9975 | unallocated_encoding(s); | |
9976 | return; | |
9977 | } | |
8c6afa6a PM |
9978 | if (!fp_access_check(s)) { |
9979 | return; | |
9980 | } | |
9981 | ||
5201c136 | 9982 | handle_2misc_narrow(s, false, opcode, u, is_q, size, rn, rd); |
d980fd59 | 9983 | return; |
45aecc6d | 9984 | case 0x4: /* CLS, CLZ */ |
b05c3068 AB |
9985 | if (size == 3) { |
9986 | unallocated_encoding(s); | |
9987 | return; | |
9988 | } | |
9989 | break; | |
9990 | case 0x2: /* SADDLP, UADDLP */ | |
45aecc6d | 9991 | case 0x6: /* SADALP, UADALP */ |
45aecc6d PM |
9992 | if (size == 3) { |
9993 | unallocated_encoding(s); | |
9994 | return; | |
9995 | } | |
8c6afa6a PM |
9996 | if (!fp_access_check(s)) { |
9997 | return; | |
9998 | } | |
6781fa11 | 9999 | handle_2misc_pairwise(s, opcode, u, is_q, size, rn, rd); |
45aecc6d PM |
10000 | return; |
10001 | case 0x13: /* SHLL, SHLL2 */ | |
10002 | if (u == 0 || size == 3) { | |
10003 | unallocated_encoding(s); | |
10004 | return; | |
10005 | } | |
8c6afa6a PM |
10006 | if (!fp_access_check(s)) { |
10007 | return; | |
10008 | } | |
73a81d10 | 10009 | handle_shll(s, is_q, size, rn, rd); |
45aecc6d PM |
10010 | return; |
10011 | case 0xa: /* CMLT */ | |
10012 | if (u == 1) { | |
10013 | unallocated_encoding(s); | |
10014 | return; | |
10015 | } | |
10016 | /* fall through */ | |
45aecc6d PM |
10017 | case 0x8: /* CMGT, CMGE */ |
10018 | case 0x9: /* CMEQ, CMLE */ | |
10019 | case 0xb: /* ABS, NEG */ | |
94b6c911 PM |
10020 | if (size == 3 && !is_q) { |
10021 | unallocated_encoding(s); | |
10022 | return; | |
10023 | } | |
10024 | break; | |
10025 | case 0x3: /* SUQADD, USQADD */ | |
09e03735 AB |
10026 | if (size == 3 && !is_q) { |
10027 | unallocated_encoding(s); | |
10028 | return; | |
10029 | } | |
8c6afa6a PM |
10030 | if (!fp_access_check(s)) { |
10031 | return; | |
10032 | } | |
09e03735 AB |
10033 | handle_2misc_satacc(s, false, u, is_q, size, rn, rd); |
10034 | return; | |
94b6c911 | 10035 | case 0x7: /* SQABS, SQNEG */ |
45aecc6d PM |
10036 | if (size == 3 && !is_q) { |
10037 | unallocated_encoding(s); | |
10038 | return; | |
10039 | } | |
0a79bc87 | 10040 | break; |
45aecc6d PM |
10041 | case 0xc ... 0xf: |
10042 | case 0x16 ... 0x1d: | |
10043 | case 0x1f: | |
10044 | { | |
10045 | /* Floating point: U, size[1] and opcode indicate operation; | |
10046 | * size[0] indicates single or double precision. | |
10047 | */ | |
10113b69 | 10048 | int is_double = extract32(size, 0, 1); |
45aecc6d | 10049 | opcode |= (extract32(size, 1, 1) << 5) | (u << 6); |
10113b69 | 10050 | size = is_double ? 3 : 2; |
45aecc6d | 10051 | switch (opcode) { |
f93d0138 PM |
10052 | case 0x2f: /* FABS */ |
10053 | case 0x6f: /* FNEG */ | |
10054 | if (size == 3 && !is_q) { | |
10055 | unallocated_encoding(s); | |
10056 | return; | |
10057 | } | |
10058 | break; | |
10113b69 AB |
10059 | case 0x1d: /* SCVTF */ |
10060 | case 0x5d: /* UCVTF */ | |
10061 | { | |
10062 | bool is_signed = (opcode == 0x1d) ? true : false; | |
10063 | int elements = is_double ? 2 : is_q ? 4 : 2; | |
10064 | if (is_double && !is_q) { | |
10065 | unallocated_encoding(s); | |
10066 | return; | |
10067 | } | |
8c6afa6a PM |
10068 | if (!fp_access_check(s)) { |
10069 | return; | |
10070 | } | |
10113b69 AB |
10071 | handle_simd_intfp_conv(s, rd, rn, elements, is_signed, 0, size); |
10072 | return; | |
10073 | } | |
8908f4d1 AB |
10074 | case 0x2c: /* FCMGT (zero) */ |
10075 | case 0x2d: /* FCMEQ (zero) */ | |
10076 | case 0x2e: /* FCMLT (zero) */ | |
10077 | case 0x6c: /* FCMGE (zero) */ | |
10078 | case 0x6d: /* FCMLE (zero) */ | |
10079 | if (size == 3 && !is_q) { | |
10080 | unallocated_encoding(s); | |
10081 | return; | |
10082 | } | |
10083 | handle_2misc_fcmp_zero(s, opcode, false, u, is_q, size, rn, rd); | |
10084 | return; | |
f612537e AB |
10085 | case 0x7f: /* FSQRT */ |
10086 | if (size == 3 && !is_q) { | |
10087 | unallocated_encoding(s); | |
10088 | return; | |
10089 | } | |
10090 | break; | |
04c7c6c2 PM |
10091 | case 0x1a: /* FCVTNS */ |
10092 | case 0x1b: /* FCVTMS */ | |
10093 | case 0x3a: /* FCVTPS */ | |
10094 | case 0x3b: /* FCVTZS */ | |
10095 | case 0x5a: /* FCVTNU */ | |
10096 | case 0x5b: /* FCVTMU */ | |
10097 | case 0x7a: /* FCVTPU */ | |
10098 | case 0x7b: /* FCVTZU */ | |
10099 | need_fpstatus = true; | |
10100 | need_rmode = true; | |
10101 | rmode = extract32(opcode, 5, 1) | (extract32(opcode, 0, 1) << 1); | |
10102 | if (size == 3 && !is_q) { | |
10103 | unallocated_encoding(s); | |
10104 | return; | |
10105 | } | |
10106 | break; | |
10107 | case 0x5c: /* FCVTAU */ | |
10108 | case 0x1c: /* FCVTAS */ | |
10109 | need_fpstatus = true; | |
10110 | need_rmode = true; | |
10111 | rmode = FPROUNDING_TIEAWAY; | |
10112 | if (size == 3 && !is_q) { | |
10113 | unallocated_encoding(s); | |
10114 | return; | |
10115 | } | |
10116 | break; | |
b6d4443a AB |
10117 | case 0x3c: /* URECPE */ |
10118 | if (size == 3) { | |
10119 | unallocated_encoding(s); | |
10120 | return; | |
10121 | } | |
10122 | /* fall through */ | |
10123 | case 0x3d: /* FRECPE */ | |
c2fb418e AB |
10124 | case 0x7d: /* FRSQRTE */ |
10125 | if (size == 3 && !is_q) { | |
10126 | unallocated_encoding(s); | |
10127 | return; | |
10128 | } | |
8c6afa6a PM |
10129 | if (!fp_access_check(s)) { |
10130 | return; | |
10131 | } | |
b6d4443a AB |
10132 | handle_2misc_reciprocal(s, opcode, false, u, is_q, size, rn, rd); |
10133 | return; | |
5553955e PM |
10134 | case 0x56: /* FCVTXN, FCVTXN2 */ |
10135 | if (size == 2) { | |
10136 | unallocated_encoding(s); | |
10137 | return; | |
10138 | } | |
10139 | /* fall through */ | |
45aecc6d | 10140 | case 0x16: /* FCVTN, FCVTN2 */ |
261a5b4d PM |
10141 | /* handle_2misc_narrow does a 2*size -> size operation, but these |
10142 | * instructions encode the source size rather than dest size. | |
10143 | */ | |
8c6afa6a PM |
10144 | if (!fp_access_check(s)) { |
10145 | return; | |
10146 | } | |
5201c136 | 10147 | handle_2misc_narrow(s, false, opcode, 0, is_q, size - 1, rn, rd); |
261a5b4d | 10148 | return; |
45aecc6d | 10149 | case 0x17: /* FCVTL, FCVTL2 */ |
8c6afa6a PM |
10150 | if (!fp_access_check(s)) { |
10151 | return; | |
10152 | } | |
931c8cc2 PM |
10153 | handle_2misc_widening(s, opcode, is_q, size, rn, rd); |
10154 | return; | |
45aecc6d PM |
10155 | case 0x18: /* FRINTN */ |
10156 | case 0x19: /* FRINTM */ | |
45aecc6d PM |
10157 | case 0x38: /* FRINTP */ |
10158 | case 0x39: /* FRINTZ */ | |
03df01ed PM |
10159 | need_rmode = true; |
10160 | rmode = extract32(opcode, 5, 1) | (extract32(opcode, 0, 1) << 1); | |
10161 | /* fall through */ | |
10162 | case 0x59: /* FRINTX */ | |
10163 | case 0x79: /* FRINTI */ | |
10164 | need_fpstatus = true; | |
10165 | if (size == 3 && !is_q) { | |
10166 | unallocated_encoding(s); | |
10167 | return; | |
10168 | } | |
10169 | break; | |
10170 | case 0x58: /* FRINTA */ | |
10171 | need_rmode = true; | |
10172 | rmode = FPROUNDING_TIEAWAY; | |
10173 | need_fpstatus = true; | |
10174 | if (size == 3 && !is_q) { | |
10175 | unallocated_encoding(s); | |
10176 | return; | |
10177 | } | |
10178 | break; | |
45aecc6d | 10179 | case 0x7c: /* URSQRTE */ |
c2fb418e AB |
10180 | if (size == 3) { |
10181 | unallocated_encoding(s); | |
10182 | return; | |
10183 | } | |
10184 | need_fpstatus = true; | |
10185 | break; | |
45aecc6d PM |
10186 | default: |
10187 | unallocated_encoding(s); | |
10188 | return; | |
10189 | } | |
10190 | break; | |
10191 | } | |
10192 | default: | |
10193 | unallocated_encoding(s); | |
10194 | return; | |
10195 | } | |
94b6c911 | 10196 | |
8c6afa6a PM |
10197 | if (!fp_access_check(s)) { |
10198 | return; | |
10199 | } | |
10200 | ||
04c7c6c2 PM |
10201 | if (need_fpstatus) { |
10202 | tcg_fpstatus = get_fpstatus_ptr(); | |
10203 | } else { | |
10204 | TCGV_UNUSED_PTR(tcg_fpstatus); | |
10205 | } | |
10206 | if (need_rmode) { | |
10207 | tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode)); | |
10208 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); | |
10209 | } else { | |
10210 | TCGV_UNUSED_I32(tcg_rmode); | |
10211 | } | |
10212 | ||
94b6c911 PM |
10213 | if (size == 3) { |
10214 | /* All 64-bit element operations can be shared with scalar 2misc */ | |
10215 | int pass; | |
10216 | ||
10217 | for (pass = 0; pass < (is_q ? 2 : 1); pass++) { | |
10218 | TCGv_i64 tcg_op = tcg_temp_new_i64(); | |
10219 | TCGv_i64 tcg_res = tcg_temp_new_i64(); | |
10220 | ||
10221 | read_vec_element(s, tcg_op, rn, pass, MO_64); | |
10222 | ||
04c7c6c2 PM |
10223 | handle_2misc_64(s, opcode, u, tcg_res, tcg_op, |
10224 | tcg_rmode, tcg_fpstatus); | |
94b6c911 PM |
10225 | |
10226 | write_vec_element(s, tcg_res, rd, pass, MO_64); | |
10227 | ||
10228 | tcg_temp_free_i64(tcg_res); | |
10229 | tcg_temp_free_i64(tcg_op); | |
10230 | } | |
10231 | } else { | |
10232 | int pass; | |
10233 | ||
10234 | for (pass = 0; pass < (is_q ? 4 : 2); pass++) { | |
10235 | TCGv_i32 tcg_op = tcg_temp_new_i32(); | |
10236 | TCGv_i32 tcg_res = tcg_temp_new_i32(); | |
10237 | TCGCond cond; | |
10238 | ||
10239 | read_vec_element_i32(s, tcg_op, rn, pass, MO_32); | |
10240 | ||
10241 | if (size == 2) { | |
10242 | /* Special cases for 32 bit elements */ | |
10243 | switch (opcode) { | |
10244 | case 0xa: /* CMLT */ | |
10245 | /* 32 bit integer comparison against zero, result is | |
10246 | * test ? (2^32 - 1) : 0. We implement via setcond(test) | |
10247 | * and inverting. | |
10248 | */ | |
10249 | cond = TCG_COND_LT; | |
10250 | do_cmop: | |
10251 | tcg_gen_setcondi_i32(cond, tcg_res, tcg_op, 0); | |
10252 | tcg_gen_neg_i32(tcg_res, tcg_res); | |
10253 | break; | |
10254 | case 0x8: /* CMGT, CMGE */ | |
10255 | cond = u ? TCG_COND_GE : TCG_COND_GT; | |
10256 | goto do_cmop; | |
10257 | case 0x9: /* CMEQ, CMLE */ | |
10258 | cond = u ? TCG_COND_LE : TCG_COND_EQ; | |
10259 | goto do_cmop; | |
b05c3068 AB |
10260 | case 0x4: /* CLS */ |
10261 | if (u) { | |
7539a012 | 10262 | tcg_gen_clzi_i32(tcg_res, tcg_op, 32); |
b05c3068 | 10263 | } else { |
bc21dbcc | 10264 | tcg_gen_clrsb_i32(tcg_res, tcg_op); |
b05c3068 AB |
10265 | } |
10266 | break; | |
0a79bc87 AB |
10267 | case 0x7: /* SQABS, SQNEG */ |
10268 | if (u) { | |
10269 | gen_helper_neon_qneg_s32(tcg_res, cpu_env, tcg_op); | |
10270 | } else { | |
10271 | gen_helper_neon_qabs_s32(tcg_res, cpu_env, tcg_op); | |
10272 | } | |
10273 | break; | |
94b6c911 PM |
10274 | case 0xb: /* ABS, NEG */ |
10275 | if (u) { | |
10276 | tcg_gen_neg_i32(tcg_res, tcg_op); | |
10277 | } else { | |
10278 | TCGv_i32 tcg_zero = tcg_const_i32(0); | |
10279 | tcg_gen_neg_i32(tcg_res, tcg_op); | |
10280 | tcg_gen_movcond_i32(TCG_COND_GT, tcg_res, tcg_op, | |
10281 | tcg_zero, tcg_op, tcg_res); | |
10282 | tcg_temp_free_i32(tcg_zero); | |
10283 | } | |
10284 | break; | |
f93d0138 PM |
10285 | case 0x2f: /* FABS */ |
10286 | gen_helper_vfp_abss(tcg_res, tcg_op); | |
10287 | break; | |
10288 | case 0x6f: /* FNEG */ | |
10289 | gen_helper_vfp_negs(tcg_res, tcg_op); | |
10290 | break; | |
f612537e AB |
10291 | case 0x7f: /* FSQRT */ |
10292 | gen_helper_vfp_sqrts(tcg_res, tcg_op, cpu_env); | |
10293 | break; | |
04c7c6c2 PM |
10294 | case 0x1a: /* FCVTNS */ |
10295 | case 0x1b: /* FCVTMS */ | |
10296 | case 0x1c: /* FCVTAS */ | |
10297 | case 0x3a: /* FCVTPS */ | |
10298 | case 0x3b: /* FCVTZS */ | |
10299 | { | |
10300 | TCGv_i32 tcg_shift = tcg_const_i32(0); | |
10301 | gen_helper_vfp_tosls(tcg_res, tcg_op, | |
10302 | tcg_shift, tcg_fpstatus); | |
10303 | tcg_temp_free_i32(tcg_shift); | |
10304 | break; | |
10305 | } | |
10306 | case 0x5a: /* FCVTNU */ | |
10307 | case 0x5b: /* FCVTMU */ | |
10308 | case 0x5c: /* FCVTAU */ | |
10309 | case 0x7a: /* FCVTPU */ | |
10310 | case 0x7b: /* FCVTZU */ | |
10311 | { | |
10312 | TCGv_i32 tcg_shift = tcg_const_i32(0); | |
10313 | gen_helper_vfp_touls(tcg_res, tcg_op, | |
10314 | tcg_shift, tcg_fpstatus); | |
10315 | tcg_temp_free_i32(tcg_shift); | |
10316 | break; | |
10317 | } | |
03df01ed PM |
10318 | case 0x18: /* FRINTN */ |
10319 | case 0x19: /* FRINTM */ | |
10320 | case 0x38: /* FRINTP */ | |
10321 | case 0x39: /* FRINTZ */ | |
10322 | case 0x58: /* FRINTA */ | |
10323 | case 0x79: /* FRINTI */ | |
10324 | gen_helper_rints(tcg_res, tcg_op, tcg_fpstatus); | |
10325 | break; | |
10326 | case 0x59: /* FRINTX */ | |
10327 | gen_helper_rints_exact(tcg_res, tcg_op, tcg_fpstatus); | |
10328 | break; | |
c2fb418e AB |
10329 | case 0x7c: /* URSQRTE */ |
10330 | gen_helper_rsqrte_u32(tcg_res, tcg_op, tcg_fpstatus); | |
10331 | break; | |
94b6c911 PM |
10332 | default: |
10333 | g_assert_not_reached(); | |
10334 | } | |
10335 | } else { | |
10336 | /* Use helpers for 8 and 16 bit elements */ | |
10337 | switch (opcode) { | |
86cbc418 PM |
10338 | case 0x5: /* CNT, RBIT */ |
10339 | /* For these two insns size is part of the opcode specifier | |
10340 | * (handled earlier); they always operate on byte elements. | |
10341 | */ | |
10342 | if (u) { | |
10343 | gen_helper_neon_rbit_u8(tcg_res, tcg_op); | |
10344 | } else { | |
10345 | gen_helper_neon_cnt_u8(tcg_res, tcg_op); | |
10346 | } | |
10347 | break; | |
0a79bc87 AB |
10348 | case 0x7: /* SQABS, SQNEG */ |
10349 | { | |
10350 | NeonGenOneOpEnvFn *genfn; | |
10351 | static NeonGenOneOpEnvFn * const fns[2][2] = { | |
10352 | { gen_helper_neon_qabs_s8, gen_helper_neon_qneg_s8 }, | |
10353 | { gen_helper_neon_qabs_s16, gen_helper_neon_qneg_s16 }, | |
10354 | }; | |
10355 | genfn = fns[size][u]; | |
10356 | genfn(tcg_res, cpu_env, tcg_op); | |
10357 | break; | |
10358 | } | |
94b6c911 PM |
10359 | case 0x8: /* CMGT, CMGE */ |
10360 | case 0x9: /* CMEQ, CMLE */ | |
10361 | case 0xa: /* CMLT */ | |
10362 | { | |
10363 | static NeonGenTwoOpFn * const fns[3][2] = { | |
10364 | { gen_helper_neon_cgt_s8, gen_helper_neon_cgt_s16 }, | |
10365 | { gen_helper_neon_cge_s8, gen_helper_neon_cge_s16 }, | |
10366 | { gen_helper_neon_ceq_u8, gen_helper_neon_ceq_u16 }, | |
10367 | }; | |
10368 | NeonGenTwoOpFn *genfn; | |
10369 | int comp; | |
10370 | bool reverse; | |
10371 | TCGv_i32 tcg_zero = tcg_const_i32(0); | |
10372 | ||
10373 | /* comp = index into [CMGT, CMGE, CMEQ, CMLE, CMLT] */ | |
10374 | comp = (opcode - 0x8) * 2 + u; | |
10375 | /* ...but LE, LT are implemented as reverse GE, GT */ | |
10376 | reverse = (comp > 2); | |
10377 | if (reverse) { | |
10378 | comp = 4 - comp; | |
10379 | } | |
10380 | genfn = fns[comp][size]; | |
10381 | if (reverse) { | |
10382 | genfn(tcg_res, tcg_zero, tcg_op); | |
10383 | } else { | |
10384 | genfn(tcg_res, tcg_op, tcg_zero); | |
10385 | } | |
10386 | tcg_temp_free_i32(tcg_zero); | |
10387 | break; | |
10388 | } | |
10389 | case 0xb: /* ABS, NEG */ | |
10390 | if (u) { | |
10391 | TCGv_i32 tcg_zero = tcg_const_i32(0); | |
10392 | if (size) { | |
10393 | gen_helper_neon_sub_u16(tcg_res, tcg_zero, tcg_op); | |
10394 | } else { | |
10395 | gen_helper_neon_sub_u8(tcg_res, tcg_zero, tcg_op); | |
10396 | } | |
10397 | tcg_temp_free_i32(tcg_zero); | |
10398 | } else { | |
10399 | if (size) { | |
10400 | gen_helper_neon_abs_s16(tcg_res, tcg_op); | |
10401 | } else { | |
10402 | gen_helper_neon_abs_s8(tcg_res, tcg_op); | |
10403 | } | |
10404 | } | |
10405 | break; | |
b05c3068 AB |
10406 | case 0x4: /* CLS, CLZ */ |
10407 | if (u) { | |
10408 | if (size == 0) { | |
10409 | gen_helper_neon_clz_u8(tcg_res, tcg_op); | |
10410 | } else { | |
10411 | gen_helper_neon_clz_u16(tcg_res, tcg_op); | |
10412 | } | |
10413 | } else { | |
10414 | if (size == 0) { | |
10415 | gen_helper_neon_cls_s8(tcg_res, tcg_op); | |
10416 | } else { | |
10417 | gen_helper_neon_cls_s16(tcg_res, tcg_op); | |
10418 | } | |
10419 | } | |
10420 | break; | |
94b6c911 PM |
10421 | default: |
10422 | g_assert_not_reached(); | |
10423 | } | |
10424 | } | |
10425 | ||
10426 | write_vec_element_i32(s, tcg_res, rd, pass, MO_32); | |
10427 | ||
10428 | tcg_temp_free_i32(tcg_res); | |
10429 | tcg_temp_free_i32(tcg_op); | |
10430 | } | |
10431 | } | |
10432 | if (!is_q) { | |
10433 | clear_vec_high(s, rd); | |
10434 | } | |
04c7c6c2 PM |
10435 | |
10436 | if (need_rmode) { | |
10437 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); | |
10438 | tcg_temp_free_i32(tcg_rmode); | |
10439 | } | |
10440 | if (need_fpstatus) { | |
10441 | tcg_temp_free_ptr(tcg_fpstatus); | |
10442 | } | |
384b26fb AB |
10443 | } |
10444 | ||
9f82e0ff PM |
10445 | /* C3.6.13 AdvSIMD scalar x indexed element |
10446 | * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0 | |
10447 | * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+ | |
10448 | * | 0 1 | U | 1 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd | | |
10449 | * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+ | |
10450 | * C3.6.18 AdvSIMD vector x indexed element | |
384b26fb AB |
10451 | * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0 |
10452 | * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+ | |
10453 | * | 0 | Q | U | 0 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd | | |
10454 | * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+ | |
10455 | */ | |
9f82e0ff | 10456 | static void disas_simd_indexed(DisasContext *s, uint32_t insn) |
384b26fb | 10457 | { |
f5e51e7f PM |
10458 | /* This encoding has two kinds of instruction: |
10459 | * normal, where we perform elt x idxelt => elt for each | |
10460 | * element in the vector | |
10461 | * long, where we perform elt x idxelt and generate a result of | |
10462 | * double the width of the input element | |
10463 | * The long ops have a 'part' specifier (ie come in INSN, INSN2 pairs). | |
10464 | */ | |
9f82e0ff | 10465 | bool is_scalar = extract32(insn, 28, 1); |
f5e51e7f PM |
10466 | bool is_q = extract32(insn, 30, 1); |
10467 | bool u = extract32(insn, 29, 1); | |
10468 | int size = extract32(insn, 22, 2); | |
10469 | int l = extract32(insn, 21, 1); | |
10470 | int m = extract32(insn, 20, 1); | |
10471 | /* Note that the Rm field here is only 4 bits, not 5 as it usually is */ | |
10472 | int rm = extract32(insn, 16, 4); | |
10473 | int opcode = extract32(insn, 12, 4); | |
10474 | int h = extract32(insn, 11, 1); | |
10475 | int rn = extract32(insn, 5, 5); | |
10476 | int rd = extract32(insn, 0, 5); | |
10477 | bool is_long = false; | |
10478 | bool is_fp = false; | |
10479 | int index; | |
10480 | TCGv_ptr fpst; | |
10481 | ||
10482 | switch (opcode) { | |
10483 | case 0x0: /* MLA */ | |
10484 | case 0x4: /* MLS */ | |
9f82e0ff | 10485 | if (!u || is_scalar) { |
f5e51e7f PM |
10486 | unallocated_encoding(s); |
10487 | return; | |
10488 | } | |
10489 | break; | |
10490 | case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */ | |
10491 | case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */ | |
10492 | case 0xa: /* SMULL, SMULL2, UMULL, UMULL2 */ | |
9f82e0ff PM |
10493 | if (is_scalar) { |
10494 | unallocated_encoding(s); | |
10495 | return; | |
10496 | } | |
f5e51e7f PM |
10497 | is_long = true; |
10498 | break; | |
10499 | case 0x3: /* SQDMLAL, SQDMLAL2 */ | |
10500 | case 0x7: /* SQDMLSL, SQDMLSL2 */ | |
10501 | case 0xb: /* SQDMULL, SQDMULL2 */ | |
10502 | is_long = true; | |
10503 | /* fall through */ | |
10504 | case 0xc: /* SQDMULH */ | |
10505 | case 0xd: /* SQRDMULH */ | |
f5e51e7f PM |
10506 | if (u) { |
10507 | unallocated_encoding(s); | |
10508 | return; | |
10509 | } | |
10510 | break; | |
9f82e0ff PM |
10511 | case 0x8: /* MUL */ |
10512 | if (u || is_scalar) { | |
10513 | unallocated_encoding(s); | |
10514 | return; | |
10515 | } | |
10516 | break; | |
f5e51e7f PM |
10517 | case 0x1: /* FMLA */ |
10518 | case 0x5: /* FMLS */ | |
10519 | if (u) { | |
10520 | unallocated_encoding(s); | |
10521 | return; | |
10522 | } | |
10523 | /* fall through */ | |
10524 | case 0x9: /* FMUL, FMULX */ | |
10525 | if (!extract32(size, 1, 1)) { | |
10526 | unallocated_encoding(s); | |
10527 | return; | |
10528 | } | |
10529 | is_fp = true; | |
10530 | break; | |
10531 | default: | |
10532 | unallocated_encoding(s); | |
10533 | return; | |
10534 | } | |
10535 | ||
10536 | if (is_fp) { | |
10537 | /* low bit of size indicates single/double */ | |
10538 | size = extract32(size, 0, 1) ? 3 : 2; | |
10539 | if (size == 2) { | |
10540 | index = h << 1 | l; | |
10541 | } else { | |
10542 | if (l || !is_q) { | |
10543 | unallocated_encoding(s); | |
10544 | return; | |
10545 | } | |
10546 | index = h; | |
10547 | } | |
10548 | rm |= (m << 4); | |
10549 | } else { | |
10550 | switch (size) { | |
10551 | case 1: | |
10552 | index = h << 2 | l << 1 | m; | |
10553 | break; | |
10554 | case 2: | |
10555 | index = h << 1 | l; | |
10556 | rm |= (m << 4); | |
10557 | break; | |
10558 | default: | |
10559 | unallocated_encoding(s); | |
10560 | return; | |
10561 | } | |
10562 | } | |
10563 | ||
8c6afa6a PM |
10564 | if (!fp_access_check(s)) { |
10565 | return; | |
10566 | } | |
10567 | ||
f5e51e7f PM |
10568 | if (is_fp) { |
10569 | fpst = get_fpstatus_ptr(); | |
10570 | } else { | |
10571 | TCGV_UNUSED_PTR(fpst); | |
10572 | } | |
10573 | ||
10574 | if (size == 3) { | |
10575 | TCGv_i64 tcg_idx = tcg_temp_new_i64(); | |
10576 | int pass; | |
10577 | ||
10578 | assert(is_fp && is_q && !is_long); | |
10579 | ||
10580 | read_vec_element(s, tcg_idx, rm, index, MO_64); | |
10581 | ||
9f82e0ff | 10582 | for (pass = 0; pass < (is_scalar ? 1 : 2); pass++) { |
f5e51e7f PM |
10583 | TCGv_i64 tcg_op = tcg_temp_new_i64(); |
10584 | TCGv_i64 tcg_res = tcg_temp_new_i64(); | |
10585 | ||
10586 | read_vec_element(s, tcg_op, rn, pass, MO_64); | |
10587 | ||
10588 | switch (opcode) { | |
10589 | case 0x5: /* FMLS */ | |
10590 | /* As usual for ARM, separate negation for fused multiply-add */ | |
10591 | gen_helper_vfp_negd(tcg_op, tcg_op); | |
10592 | /* fall through */ | |
10593 | case 0x1: /* FMLA */ | |
10594 | read_vec_element(s, tcg_res, rd, pass, MO_64); | |
10595 | gen_helper_vfp_muladdd(tcg_res, tcg_op, tcg_idx, tcg_res, fpst); | |
10596 | break; | |
10597 | case 0x9: /* FMUL, FMULX */ | |
10598 | if (u) { | |
10599 | gen_helper_vfp_mulxd(tcg_res, tcg_op, tcg_idx, fpst); | |
10600 | } else { | |
10601 | gen_helper_vfp_muld(tcg_res, tcg_op, tcg_idx, fpst); | |
10602 | } | |
10603 | break; | |
10604 | default: | |
10605 | g_assert_not_reached(); | |
10606 | } | |
10607 | ||
10608 | write_vec_element(s, tcg_res, rd, pass, MO_64); | |
10609 | tcg_temp_free_i64(tcg_op); | |
10610 | tcg_temp_free_i64(tcg_res); | |
10611 | } | |
10612 | ||
9f82e0ff PM |
10613 | if (is_scalar) { |
10614 | clear_vec_high(s, rd); | |
10615 | } | |
10616 | ||
f5e51e7f PM |
10617 | tcg_temp_free_i64(tcg_idx); |
10618 | } else if (!is_long) { | |
9f82e0ff PM |
10619 | /* 32 bit floating point, or 16 or 32 bit integer. |
10620 | * For the 16 bit scalar case we use the usual Neon helpers and | |
10621 | * rely on the fact that 0 op 0 == 0 with no side effects. | |
10622 | */ | |
f5e51e7f | 10623 | TCGv_i32 tcg_idx = tcg_temp_new_i32(); |
9f82e0ff PM |
10624 | int pass, maxpasses; |
10625 | ||
10626 | if (is_scalar) { | |
10627 | maxpasses = 1; | |
10628 | } else { | |
10629 | maxpasses = is_q ? 4 : 2; | |
10630 | } | |
f5e51e7f PM |
10631 | |
10632 | read_vec_element_i32(s, tcg_idx, rm, index, size); | |
10633 | ||
9f82e0ff | 10634 | if (size == 1 && !is_scalar) { |
f5e51e7f PM |
10635 | /* The simplest way to handle the 16x16 indexed ops is to duplicate |
10636 | * the index into both halves of the 32 bit tcg_idx and then use | |
10637 | * the usual Neon helpers. | |
10638 | */ | |
10639 | tcg_gen_deposit_i32(tcg_idx, tcg_idx, tcg_idx, 16, 16); | |
10640 | } | |
10641 | ||
9f82e0ff | 10642 | for (pass = 0; pass < maxpasses; pass++) { |
f5e51e7f PM |
10643 | TCGv_i32 tcg_op = tcg_temp_new_i32(); |
10644 | TCGv_i32 tcg_res = tcg_temp_new_i32(); | |
10645 | ||
9f82e0ff | 10646 | read_vec_element_i32(s, tcg_op, rn, pass, is_scalar ? size : MO_32); |
f5e51e7f PM |
10647 | |
10648 | switch (opcode) { | |
10649 | case 0x0: /* MLA */ | |
10650 | case 0x4: /* MLS */ | |
10651 | case 0x8: /* MUL */ | |
10652 | { | |
10653 | static NeonGenTwoOpFn * const fns[2][2] = { | |
10654 | { gen_helper_neon_add_u16, gen_helper_neon_sub_u16 }, | |
10655 | { tcg_gen_add_i32, tcg_gen_sub_i32 }, | |
10656 | }; | |
10657 | NeonGenTwoOpFn *genfn; | |
10658 | bool is_sub = opcode == 0x4; | |
10659 | ||
10660 | if (size == 1) { | |
10661 | gen_helper_neon_mul_u16(tcg_res, tcg_op, tcg_idx); | |
10662 | } else { | |
10663 | tcg_gen_mul_i32(tcg_res, tcg_op, tcg_idx); | |
10664 | } | |
10665 | if (opcode == 0x8) { | |
10666 | break; | |
10667 | } | |
10668 | read_vec_element_i32(s, tcg_op, rd, pass, MO_32); | |
10669 | genfn = fns[size - 1][is_sub]; | |
10670 | genfn(tcg_res, tcg_op, tcg_res); | |
10671 | break; | |
10672 | } | |
10673 | case 0x5: /* FMLS */ | |
10674 | /* As usual for ARM, separate negation for fused multiply-add */ | |
10675 | gen_helper_vfp_negs(tcg_op, tcg_op); | |
10676 | /* fall through */ | |
10677 | case 0x1: /* FMLA */ | |
10678 | read_vec_element_i32(s, tcg_res, rd, pass, MO_32); | |
10679 | gen_helper_vfp_muladds(tcg_res, tcg_op, tcg_idx, tcg_res, fpst); | |
10680 | break; | |
10681 | case 0x9: /* FMUL, FMULX */ | |
10682 | if (u) { | |
10683 | gen_helper_vfp_mulxs(tcg_res, tcg_op, tcg_idx, fpst); | |
10684 | } else { | |
10685 | gen_helper_vfp_muls(tcg_res, tcg_op, tcg_idx, fpst); | |
10686 | } | |
10687 | break; | |
10688 | case 0xc: /* SQDMULH */ | |
10689 | if (size == 1) { | |
10690 | gen_helper_neon_qdmulh_s16(tcg_res, cpu_env, | |
10691 | tcg_op, tcg_idx); | |
10692 | } else { | |
10693 | gen_helper_neon_qdmulh_s32(tcg_res, cpu_env, | |
10694 | tcg_op, tcg_idx); | |
10695 | } | |
10696 | break; | |
10697 | case 0xd: /* SQRDMULH */ | |
10698 | if (size == 1) { | |
10699 | gen_helper_neon_qrdmulh_s16(tcg_res, cpu_env, | |
10700 | tcg_op, tcg_idx); | |
10701 | } else { | |
10702 | gen_helper_neon_qrdmulh_s32(tcg_res, cpu_env, | |
10703 | tcg_op, tcg_idx); | |
10704 | } | |
10705 | break; | |
10706 | default: | |
10707 | g_assert_not_reached(); | |
10708 | } | |
10709 | ||
9f82e0ff PM |
10710 | if (is_scalar) { |
10711 | write_fp_sreg(s, rd, tcg_res); | |
10712 | } else { | |
10713 | write_vec_element_i32(s, tcg_res, rd, pass, MO_32); | |
10714 | } | |
10715 | ||
f5e51e7f PM |
10716 | tcg_temp_free_i32(tcg_op); |
10717 | tcg_temp_free_i32(tcg_res); | |
10718 | } | |
10719 | ||
10720 | tcg_temp_free_i32(tcg_idx); | |
10721 | ||
10722 | if (!is_q) { | |
10723 | clear_vec_high(s, rd); | |
10724 | } | |
10725 | } else { | |
10726 | /* long ops: 16x16->32 or 32x32->64 */ | |
c44ad1fd PM |
10727 | TCGv_i64 tcg_res[2]; |
10728 | int pass; | |
10729 | bool satop = extract32(opcode, 0, 1); | |
10730 | TCGMemOp memop = MO_32; | |
10731 | ||
10732 | if (satop || !u) { | |
10733 | memop |= MO_SIGN; | |
10734 | } | |
10735 | ||
10736 | if (size == 2) { | |
10737 | TCGv_i64 tcg_idx = tcg_temp_new_i64(); | |
10738 | ||
10739 | read_vec_element(s, tcg_idx, rm, index, memop); | |
10740 | ||
9f82e0ff | 10741 | for (pass = 0; pass < (is_scalar ? 1 : 2); pass++) { |
c44ad1fd PM |
10742 | TCGv_i64 tcg_op = tcg_temp_new_i64(); |
10743 | TCGv_i64 tcg_passres; | |
9f82e0ff | 10744 | int passelt; |
c44ad1fd | 10745 | |
9f82e0ff PM |
10746 | if (is_scalar) { |
10747 | passelt = 0; | |
10748 | } else { | |
10749 | passelt = pass + (is_q * 2); | |
10750 | } | |
10751 | ||
10752 | read_vec_element(s, tcg_op, rn, passelt, memop); | |
c44ad1fd PM |
10753 | |
10754 | tcg_res[pass] = tcg_temp_new_i64(); | |
10755 | ||
10756 | if (opcode == 0xa || opcode == 0xb) { | |
10757 | /* Non-accumulating ops */ | |
10758 | tcg_passres = tcg_res[pass]; | |
10759 | } else { | |
10760 | tcg_passres = tcg_temp_new_i64(); | |
10761 | } | |
10762 | ||
10763 | tcg_gen_mul_i64(tcg_passres, tcg_op, tcg_idx); | |
10764 | tcg_temp_free_i64(tcg_op); | |
10765 | ||
10766 | if (satop) { | |
10767 | /* saturating, doubling */ | |
10768 | gen_helper_neon_addl_saturate_s64(tcg_passres, cpu_env, | |
10769 | tcg_passres, tcg_passres); | |
10770 | } | |
10771 | ||
10772 | if (opcode == 0xa || opcode == 0xb) { | |
10773 | continue; | |
10774 | } | |
10775 | ||
10776 | /* Accumulating op: handle accumulate step */ | |
10777 | read_vec_element(s, tcg_res[pass], rd, pass, MO_64); | |
10778 | ||
10779 | switch (opcode) { | |
10780 | case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */ | |
10781 | tcg_gen_add_i64(tcg_res[pass], tcg_res[pass], tcg_passres); | |
10782 | break; | |
10783 | case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */ | |
10784 | tcg_gen_sub_i64(tcg_res[pass], tcg_res[pass], tcg_passres); | |
10785 | break; | |
10786 | case 0x7: /* SQDMLSL, SQDMLSL2 */ | |
10787 | tcg_gen_neg_i64(tcg_passres, tcg_passres); | |
10788 | /* fall through */ | |
10789 | case 0x3: /* SQDMLAL, SQDMLAL2 */ | |
10790 | gen_helper_neon_addl_saturate_s64(tcg_res[pass], cpu_env, | |
10791 | tcg_res[pass], | |
10792 | tcg_passres); | |
10793 | break; | |
10794 | default: | |
10795 | g_assert_not_reached(); | |
10796 | } | |
10797 | tcg_temp_free_i64(tcg_passres); | |
10798 | } | |
10799 | tcg_temp_free_i64(tcg_idx); | |
9f82e0ff PM |
10800 | |
10801 | if (is_scalar) { | |
10802 | clear_vec_high(s, rd); | |
10803 | } | |
c44ad1fd PM |
10804 | } else { |
10805 | TCGv_i32 tcg_idx = tcg_temp_new_i32(); | |
10806 | ||
10807 | assert(size == 1); | |
10808 | read_vec_element_i32(s, tcg_idx, rm, index, size); | |
10809 | ||
9f82e0ff PM |
10810 | if (!is_scalar) { |
10811 | /* The simplest way to handle the 16x16 indexed ops is to | |
10812 | * duplicate the index into both halves of the 32 bit tcg_idx | |
10813 | * and then use the usual Neon helpers. | |
10814 | */ | |
10815 | tcg_gen_deposit_i32(tcg_idx, tcg_idx, tcg_idx, 16, 16); | |
10816 | } | |
c44ad1fd | 10817 | |
9f82e0ff | 10818 | for (pass = 0; pass < (is_scalar ? 1 : 2); pass++) { |
c44ad1fd PM |
10819 | TCGv_i32 tcg_op = tcg_temp_new_i32(); |
10820 | TCGv_i64 tcg_passres; | |
10821 | ||
9f82e0ff PM |
10822 | if (is_scalar) { |
10823 | read_vec_element_i32(s, tcg_op, rn, pass, size); | |
10824 | } else { | |
10825 | read_vec_element_i32(s, tcg_op, rn, | |
10826 | pass + (is_q * 2), MO_32); | |
10827 | } | |
10828 | ||
c44ad1fd PM |
10829 | tcg_res[pass] = tcg_temp_new_i64(); |
10830 | ||
10831 | if (opcode == 0xa || opcode == 0xb) { | |
10832 | /* Non-accumulating ops */ | |
10833 | tcg_passres = tcg_res[pass]; | |
10834 | } else { | |
10835 | tcg_passres = tcg_temp_new_i64(); | |
10836 | } | |
10837 | ||
10838 | if (memop & MO_SIGN) { | |
10839 | gen_helper_neon_mull_s16(tcg_passres, tcg_op, tcg_idx); | |
10840 | } else { | |
10841 | gen_helper_neon_mull_u16(tcg_passres, tcg_op, tcg_idx); | |
10842 | } | |
10843 | if (satop) { | |
10844 | gen_helper_neon_addl_saturate_s32(tcg_passres, cpu_env, | |
10845 | tcg_passres, tcg_passres); | |
10846 | } | |
10847 | tcg_temp_free_i32(tcg_op); | |
10848 | ||
10849 | if (opcode == 0xa || opcode == 0xb) { | |
10850 | continue; | |
10851 | } | |
10852 | ||
10853 | /* Accumulating op: handle accumulate step */ | |
10854 | read_vec_element(s, tcg_res[pass], rd, pass, MO_64); | |
10855 | ||
10856 | switch (opcode) { | |
10857 | case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */ | |
10858 | gen_helper_neon_addl_u32(tcg_res[pass], tcg_res[pass], | |
10859 | tcg_passres); | |
10860 | break; | |
10861 | case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */ | |
10862 | gen_helper_neon_subl_u32(tcg_res[pass], tcg_res[pass], | |
10863 | tcg_passres); | |
10864 | break; | |
10865 | case 0x7: /* SQDMLSL, SQDMLSL2 */ | |
10866 | gen_helper_neon_negl_u32(tcg_passres, tcg_passres); | |
10867 | /* fall through */ | |
10868 | case 0x3: /* SQDMLAL, SQDMLAL2 */ | |
10869 | gen_helper_neon_addl_saturate_s32(tcg_res[pass], cpu_env, | |
10870 | tcg_res[pass], | |
10871 | tcg_passres); | |
10872 | break; | |
10873 | default: | |
10874 | g_assert_not_reached(); | |
10875 | } | |
10876 | tcg_temp_free_i64(tcg_passres); | |
10877 | } | |
10878 | tcg_temp_free_i32(tcg_idx); | |
9f82e0ff PM |
10879 | |
10880 | if (is_scalar) { | |
10881 | tcg_gen_ext32u_i64(tcg_res[0], tcg_res[0]); | |
10882 | } | |
10883 | } | |
10884 | ||
10885 | if (is_scalar) { | |
10886 | tcg_res[1] = tcg_const_i64(0); | |
c44ad1fd PM |
10887 | } |
10888 | ||
10889 | for (pass = 0; pass < 2; pass++) { | |
10890 | write_vec_element(s, tcg_res[pass], rd, pass, MO_64); | |
10891 | tcg_temp_free_i64(tcg_res[pass]); | |
10892 | } | |
f5e51e7f PM |
10893 | } |
10894 | ||
10895 | if (!TCGV_IS_UNUSED_PTR(fpst)) { | |
10896 | tcg_temp_free_ptr(fpst); | |
10897 | } | |
384b26fb AB |
10898 | } |
10899 | ||
10900 | /* C3.6.19 Crypto AES | |
10901 | * 31 24 23 22 21 17 16 12 11 10 9 5 4 0 | |
10902 | * +-----------------+------+-----------+--------+-----+------+------+ | |
10903 | * | 0 1 0 0 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd | | |
10904 | * +-----------------+------+-----------+--------+-----+------+------+ | |
10905 | */ | |
10906 | static void disas_crypto_aes(DisasContext *s, uint32_t insn) | |
10907 | { | |
5acc765c PM |
10908 | int size = extract32(insn, 22, 2); |
10909 | int opcode = extract32(insn, 12, 5); | |
10910 | int rn = extract32(insn, 5, 5); | |
10911 | int rd = extract32(insn, 0, 5); | |
10912 | int decrypt; | |
10913 | TCGv_i32 tcg_rd_regno, tcg_rn_regno, tcg_decrypt; | |
10914 | CryptoThreeOpEnvFn *genfn; | |
10915 | ||
10916 | if (!arm_dc_feature(s, ARM_FEATURE_V8_AES) | |
10917 | || size != 0) { | |
10918 | unallocated_encoding(s); | |
10919 | return; | |
10920 | } | |
10921 | ||
10922 | switch (opcode) { | |
10923 | case 0x4: /* AESE */ | |
10924 | decrypt = 0; | |
10925 | genfn = gen_helper_crypto_aese; | |
10926 | break; | |
10927 | case 0x6: /* AESMC */ | |
10928 | decrypt = 0; | |
10929 | genfn = gen_helper_crypto_aesmc; | |
10930 | break; | |
10931 | case 0x5: /* AESD */ | |
10932 | decrypt = 1; | |
10933 | genfn = gen_helper_crypto_aese; | |
10934 | break; | |
10935 | case 0x7: /* AESIMC */ | |
10936 | decrypt = 1; | |
10937 | genfn = gen_helper_crypto_aesmc; | |
10938 | break; | |
10939 | default: | |
10940 | unallocated_encoding(s); | |
10941 | return; | |
10942 | } | |
10943 | ||
a4f5c5b7 NR |
10944 | if (!fp_access_check(s)) { |
10945 | return; | |
10946 | } | |
10947 | ||
5acc765c PM |
10948 | /* Note that we convert the Vx register indexes into the |
10949 | * index within the vfp.regs[] array, so we can share the | |
10950 | * helper with the AArch32 instructions. | |
10951 | */ | |
10952 | tcg_rd_regno = tcg_const_i32(rd << 1); | |
10953 | tcg_rn_regno = tcg_const_i32(rn << 1); | |
10954 | tcg_decrypt = tcg_const_i32(decrypt); | |
10955 | ||
10956 | genfn(cpu_env, tcg_rd_regno, tcg_rn_regno, tcg_decrypt); | |
10957 | ||
10958 | tcg_temp_free_i32(tcg_rd_regno); | |
10959 | tcg_temp_free_i32(tcg_rn_regno); | |
10960 | tcg_temp_free_i32(tcg_decrypt); | |
384b26fb AB |
10961 | } |
10962 | ||
10963 | /* C3.6.20 Crypto three-reg SHA | |
10964 | * 31 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0 | |
10965 | * +-----------------+------+---+------+---+--------+-----+------+------+ | |
10966 | * | 0 1 0 1 1 1 1 0 | size | 0 | Rm | 0 | opcode | 0 0 | Rn | Rd | | |
10967 | * +-----------------+------+---+------+---+--------+-----+------+------+ | |
10968 | */ | |
10969 | static void disas_crypto_three_reg_sha(DisasContext *s, uint32_t insn) | |
10970 | { | |
be56f04e PM |
10971 | int size = extract32(insn, 22, 2); |
10972 | int opcode = extract32(insn, 12, 3); | |
10973 | int rm = extract32(insn, 16, 5); | |
10974 | int rn = extract32(insn, 5, 5); | |
10975 | int rd = extract32(insn, 0, 5); | |
10976 | CryptoThreeOpEnvFn *genfn; | |
10977 | TCGv_i32 tcg_rd_regno, tcg_rn_regno, tcg_rm_regno; | |
10978 | int feature = ARM_FEATURE_V8_SHA256; | |
10979 | ||
10980 | if (size != 0) { | |
10981 | unallocated_encoding(s); | |
10982 | return; | |
10983 | } | |
10984 | ||
10985 | switch (opcode) { | |
10986 | case 0: /* SHA1C */ | |
10987 | case 1: /* SHA1P */ | |
10988 | case 2: /* SHA1M */ | |
10989 | case 3: /* SHA1SU0 */ | |
10990 | genfn = NULL; | |
10991 | feature = ARM_FEATURE_V8_SHA1; | |
10992 | break; | |
10993 | case 4: /* SHA256H */ | |
10994 | genfn = gen_helper_crypto_sha256h; | |
10995 | break; | |
10996 | case 5: /* SHA256H2 */ | |
10997 | genfn = gen_helper_crypto_sha256h2; | |
10998 | break; | |
10999 | case 6: /* SHA256SU1 */ | |
11000 | genfn = gen_helper_crypto_sha256su1; | |
11001 | break; | |
11002 | default: | |
11003 | unallocated_encoding(s); | |
11004 | return; | |
11005 | } | |
11006 | ||
11007 | if (!arm_dc_feature(s, feature)) { | |
11008 | unallocated_encoding(s); | |
11009 | return; | |
11010 | } | |
11011 | ||
a4f5c5b7 NR |
11012 | if (!fp_access_check(s)) { |
11013 | return; | |
11014 | } | |
11015 | ||
be56f04e PM |
11016 | tcg_rd_regno = tcg_const_i32(rd << 1); |
11017 | tcg_rn_regno = tcg_const_i32(rn << 1); | |
11018 | tcg_rm_regno = tcg_const_i32(rm << 1); | |
11019 | ||
11020 | if (genfn) { | |
11021 | genfn(cpu_env, tcg_rd_regno, tcg_rn_regno, tcg_rm_regno); | |
11022 | } else { | |
11023 | TCGv_i32 tcg_opcode = tcg_const_i32(opcode); | |
11024 | ||
11025 | gen_helper_crypto_sha1_3reg(cpu_env, tcg_rd_regno, | |
11026 | tcg_rn_regno, tcg_rm_regno, tcg_opcode); | |
11027 | tcg_temp_free_i32(tcg_opcode); | |
11028 | } | |
11029 | ||
11030 | tcg_temp_free_i32(tcg_rd_regno); | |
11031 | tcg_temp_free_i32(tcg_rn_regno); | |
11032 | tcg_temp_free_i32(tcg_rm_regno); | |
384b26fb AB |
11033 | } |
11034 | ||
11035 | /* C3.6.21 Crypto two-reg SHA | |
11036 | * 31 24 23 22 21 17 16 12 11 10 9 5 4 0 | |
11037 | * +-----------------+------+-----------+--------+-----+------+------+ | |
11038 | * | 0 1 0 1 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd | | |
11039 | * +-----------------+------+-----------+--------+-----+------+------+ | |
11040 | */ | |
11041 | static void disas_crypto_two_reg_sha(DisasContext *s, uint32_t insn) | |
11042 | { | |
f6fe04d5 PM |
11043 | int size = extract32(insn, 22, 2); |
11044 | int opcode = extract32(insn, 12, 5); | |
11045 | int rn = extract32(insn, 5, 5); | |
11046 | int rd = extract32(insn, 0, 5); | |
11047 | CryptoTwoOpEnvFn *genfn; | |
11048 | int feature; | |
11049 | TCGv_i32 tcg_rd_regno, tcg_rn_regno; | |
11050 | ||
11051 | if (size != 0) { | |
11052 | unallocated_encoding(s); | |
11053 | return; | |
11054 | } | |
11055 | ||
11056 | switch (opcode) { | |
11057 | case 0: /* SHA1H */ | |
11058 | feature = ARM_FEATURE_V8_SHA1; | |
11059 | genfn = gen_helper_crypto_sha1h; | |
11060 | break; | |
11061 | case 1: /* SHA1SU1 */ | |
11062 | feature = ARM_FEATURE_V8_SHA1; | |
11063 | genfn = gen_helper_crypto_sha1su1; | |
11064 | break; | |
11065 | case 2: /* SHA256SU0 */ | |
11066 | feature = ARM_FEATURE_V8_SHA256; | |
11067 | genfn = gen_helper_crypto_sha256su0; | |
11068 | break; | |
11069 | default: | |
11070 | unallocated_encoding(s); | |
11071 | return; | |
11072 | } | |
11073 | ||
11074 | if (!arm_dc_feature(s, feature)) { | |
11075 | unallocated_encoding(s); | |
11076 | return; | |
11077 | } | |
11078 | ||
a4f5c5b7 NR |
11079 | if (!fp_access_check(s)) { |
11080 | return; | |
11081 | } | |
11082 | ||
f6fe04d5 PM |
11083 | tcg_rd_regno = tcg_const_i32(rd << 1); |
11084 | tcg_rn_regno = tcg_const_i32(rn << 1); | |
11085 | ||
11086 | genfn(cpu_env, tcg_rd_regno, tcg_rn_regno); | |
11087 | ||
11088 | tcg_temp_free_i32(tcg_rd_regno); | |
11089 | tcg_temp_free_i32(tcg_rn_regno); | |
384b26fb AB |
11090 | } |
11091 | ||
11092 | /* C3.6 Data processing - SIMD, inc Crypto | |
11093 | * | |
11094 | * As the decode gets a little complex we are using a table based | |
11095 | * approach for this part of the decode. | |
11096 | */ | |
11097 | static const AArch64DecodeTable data_proc_simd[] = { | |
11098 | /* pattern , mask , fn */ | |
11099 | { 0x0e200400, 0x9f200400, disas_simd_three_reg_same }, | |
11100 | { 0x0e200000, 0x9f200c00, disas_simd_three_reg_diff }, | |
11101 | { 0x0e200800, 0x9f3e0c00, disas_simd_two_reg_misc }, | |
11102 | { 0x0e300800, 0x9f3e0c00, disas_simd_across_lanes }, | |
11103 | { 0x0e000400, 0x9fe08400, disas_simd_copy }, | |
9f82e0ff | 11104 | { 0x0f000000, 0x9f000400, disas_simd_indexed }, /* vector indexed */ |
384b26fb AB |
11105 | /* simd_mod_imm decode is a subset of simd_shift_imm, so must precede it */ |
11106 | { 0x0f000400, 0x9ff80400, disas_simd_mod_imm }, | |
11107 | { 0x0f000400, 0x9f800400, disas_simd_shift_imm }, | |
11108 | { 0x0e000000, 0xbf208c00, disas_simd_tb }, | |
11109 | { 0x0e000800, 0xbf208c00, disas_simd_zip_trn }, | |
11110 | { 0x2e000000, 0xbf208400, disas_simd_ext }, | |
11111 | { 0x5e200400, 0xdf200400, disas_simd_scalar_three_reg_same }, | |
11112 | { 0x5e200000, 0xdf200c00, disas_simd_scalar_three_reg_diff }, | |
11113 | { 0x5e200800, 0xdf3e0c00, disas_simd_scalar_two_reg_misc }, | |
11114 | { 0x5e300800, 0xdf3e0c00, disas_simd_scalar_pairwise }, | |
11115 | { 0x5e000400, 0xdfe08400, disas_simd_scalar_copy }, | |
9f82e0ff | 11116 | { 0x5f000000, 0xdf000400, disas_simd_indexed }, /* scalar indexed */ |
384b26fb AB |
11117 | { 0x5f000400, 0xdf800400, disas_simd_scalar_shift_imm }, |
11118 | { 0x4e280800, 0xff3e0c00, disas_crypto_aes }, | |
11119 | { 0x5e000000, 0xff208c00, disas_crypto_three_reg_sha }, | |
11120 | { 0x5e280800, 0xff3e0c00, disas_crypto_two_reg_sha }, | |
11121 | { 0x00000000, 0x00000000, NULL } | |
11122 | }; | |
11123 | ||
faa0ba46 PM |
11124 | static void disas_data_proc_simd(DisasContext *s, uint32_t insn) |
11125 | { | |
11126 | /* Note that this is called with all non-FP cases from | |
11127 | * table C3-6 so it must UNDEF for entries not specifically | |
11128 | * allocated to instructions in that table. | |
11129 | */ | |
384b26fb AB |
11130 | AArch64DecodeFn *fn = lookup_disas_fn(&data_proc_simd[0], insn); |
11131 | if (fn) { | |
11132 | fn(s, insn); | |
11133 | } else { | |
11134 | unallocated_encoding(s); | |
11135 | } | |
faa0ba46 PM |
11136 | } |
11137 | ||
ad7ee8a2 CF |
11138 | /* C3.6 Data processing - SIMD and floating point */ |
11139 | static void disas_data_proc_simd_fp(DisasContext *s, uint32_t insn) | |
11140 | { | |
faa0ba46 PM |
11141 | if (extract32(insn, 28, 1) == 1 && extract32(insn, 30, 1) == 0) { |
11142 | disas_data_proc_fp(s, insn); | |
11143 | } else { | |
11144 | /* SIMD, including crypto */ | |
11145 | disas_data_proc_simd(s, insn); | |
11146 | } | |
ad7ee8a2 CF |
11147 | } |
11148 | ||
11149 | /* C3.1 A64 instruction index by encoding */ | |
40f860cd | 11150 | static void disas_a64_insn(CPUARMState *env, DisasContext *s) |
14ade10f AG |
11151 | { |
11152 | uint32_t insn; | |
11153 | ||
f9fd40eb | 11154 | insn = arm_ldl_code(env, s->pc, s->sctlr_b); |
14ade10f AG |
11155 | s->insn = insn; |
11156 | s->pc += 4; | |
11157 | ||
90e49638 PM |
11158 | s->fp_access_checked = false; |
11159 | ||
ad7ee8a2 CF |
11160 | switch (extract32(insn, 25, 4)) { |
11161 | case 0x0: case 0x1: case 0x2: case 0x3: /* UNALLOCATED */ | |
14ade10f AG |
11162 | unallocated_encoding(s); |
11163 | break; | |
ad7ee8a2 CF |
11164 | case 0x8: case 0x9: /* Data processing - immediate */ |
11165 | disas_data_proc_imm(s, insn); | |
11166 | break; | |
11167 | case 0xa: case 0xb: /* Branch, exception generation and system insns */ | |
11168 | disas_b_exc_sys(s, insn); | |
11169 | break; | |
11170 | case 0x4: | |
11171 | case 0x6: | |
11172 | case 0xc: | |
11173 | case 0xe: /* Loads and stores */ | |
11174 | disas_ldst(s, insn); | |
11175 | break; | |
11176 | case 0x5: | |
11177 | case 0xd: /* Data processing - register */ | |
11178 | disas_data_proc_reg(s, insn); | |
11179 | break; | |
11180 | case 0x7: | |
11181 | case 0xf: /* Data processing - SIMD and floating point */ | |
11182 | disas_data_proc_simd_fp(s, insn); | |
11183 | break; | |
11184 | default: | |
11185 | assert(FALSE); /* all 15 cases should be handled above */ | |
11186 | break; | |
14ade10f | 11187 | } |
11e169de AG |
11188 | |
11189 | /* if we allocated any temporaries, free them here */ | |
11190 | free_tmp_a64(s); | |
40f860cd | 11191 | } |
14ade10f | 11192 | |
4e5e1215 | 11193 | void gen_intermediate_code_a64(ARMCPU *cpu, TranslationBlock *tb) |
40f860cd PM |
11194 | { |
11195 | CPUState *cs = CPU(cpu); | |
11196 | CPUARMState *env = &cpu->env; | |
11197 | DisasContext dc1, *dc = &dc1; | |
40f860cd PM |
11198 | target_ulong pc_start; |
11199 | target_ulong next_page_start; | |
11200 | int num_insns; | |
11201 | int max_insns; | |
11202 | ||
11203 | pc_start = tb->pc; | |
11204 | ||
11205 | dc->tb = tb; | |
11206 | ||
40f860cd PM |
11207 | dc->is_jmp = DISAS_NEXT; |
11208 | dc->pc = pc_start; | |
11209 | dc->singlestep_enabled = cs->singlestep_enabled; | |
11210 | dc->condjmp = 0; | |
11211 | ||
11212 | dc->aarch64 = 1; | |
cef9ee70 SS |
11213 | /* If we are coming from secure EL0 in a system with a 32-bit EL3, then |
11214 | * there is no secure EL1, so we route exceptions to EL3. | |
11215 | */ | |
11216 | dc->secure_routed_to_el3 = arm_feature(env, ARM_FEATURE_EL3) && | |
11217 | !arm_el_is_aa64(env, 3); | |
40f860cd | 11218 | dc->thumb = 0; |
f9fd40eb | 11219 | dc->sctlr_b = 0; |
91cca2cd | 11220 | dc->be_data = ARM_TBFLAG_BE_DATA(tb->flags) ? MO_BE : MO_LE; |
40f860cd PM |
11221 | dc->condexec_mask = 0; |
11222 | dc->condexec_cond = 0; | |
8bd5c820 | 11223 | dc->mmu_idx = core_to_arm_mmu_idx(env, ARM_TBFLAG_MMUIDX(tb->flags)); |
86fb3fa4 TH |
11224 | dc->tbi0 = ARM_TBFLAG_TBI0(tb->flags); |
11225 | dc->tbi1 = ARM_TBFLAG_TBI1(tb->flags); | |
c1e37810 | 11226 | dc->current_el = arm_mmu_idx_to_el(dc->mmu_idx); |
40f860cd | 11227 | #if !defined(CONFIG_USER_ONLY) |
c1e37810 | 11228 | dc->user = (dc->current_el == 0); |
40f860cd | 11229 | #endif |
9dbbc748 | 11230 | dc->fp_excp_el = ARM_TBFLAG_FPEXC_EL(tb->flags); |
40f860cd PM |
11231 | dc->vec_len = 0; |
11232 | dc->vec_stride = 0; | |
60322b39 | 11233 | dc->cp_regs = cpu->cp_regs; |
a984e42c | 11234 | dc->features = env->features; |
40f860cd | 11235 | |
7ea47fe7 PM |
11236 | /* Single step state. The code-generation logic here is: |
11237 | * SS_ACTIVE == 0: | |
11238 | * generate code with no special handling for single-stepping (except | |
11239 | * that anything that can make us go to SS_ACTIVE == 1 must end the TB; | |
11240 | * this happens anyway because those changes are all system register or | |
11241 | * PSTATE writes). | |
11242 | * SS_ACTIVE == 1, PSTATE.SS == 1: (active-not-pending) | |
11243 | * emit code for one insn | |
11244 | * emit code to clear PSTATE.SS | |
11245 | * emit code to generate software step exception for completed step | |
11246 | * end TB (as usual for having generated an exception) | |
11247 | * SS_ACTIVE == 1, PSTATE.SS == 0: (active-pending) | |
11248 | * emit code to generate a software step exception | |
11249 | * end the TB | |
11250 | */ | |
3cf6a0fc PM |
11251 | dc->ss_active = ARM_TBFLAG_SS_ACTIVE(tb->flags); |
11252 | dc->pstate_ss = ARM_TBFLAG_PSTATE_SS(tb->flags); | |
7ea47fe7 | 11253 | dc->is_ldex = false; |
dcbff19b | 11254 | dc->ss_same_el = (arm_debug_target_el(env) == dc->current_el); |
7ea47fe7 | 11255 | |
11e169de AG |
11256 | init_tmp_a64_array(dc); |
11257 | ||
40f860cd | 11258 | next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; |
40f860cd PM |
11259 | num_insns = 0; |
11260 | max_insns = tb->cflags & CF_COUNT_MASK; | |
11261 | if (max_insns == 0) { | |
11262 | max_insns = CF_COUNT_MASK; | |
11263 | } | |
190ce7fb RH |
11264 | if (max_insns > TCG_MAX_INSNS) { |
11265 | max_insns = TCG_MAX_INSNS; | |
11266 | } | |
40f860cd | 11267 | |
cd42d5b2 | 11268 | gen_tb_start(tb); |
40f860cd PM |
11269 | |
11270 | tcg_clear_temp_count(); | |
11271 | ||
11272 | do { | |
aaa1f954 EI |
11273 | dc->insn_start_idx = tcg_op_buf_count(); |
11274 | tcg_gen_insn_start(dc->pc, 0, 0); | |
959082fc | 11275 | num_insns++; |
40f860cd | 11276 | |
b933066a RH |
11277 | if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { |
11278 | CPUBreakpoint *bp; | |
11279 | QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { | |
11280 | if (bp->pc == dc->pc) { | |
5d98bf8f | 11281 | if (bp->flags & BP_CPU) { |
ed6c6448 | 11282 | gen_a64_set_pc_im(dc->pc); |
5d98bf8f SF |
11283 | gen_helper_check_breakpoints(cpu_env); |
11284 | /* End the TB early; it likely won't be executed */ | |
11285 | dc->is_jmp = DISAS_UPDATE; | |
11286 | } else { | |
11287 | gen_exception_internal_insn(dc, 0, EXCP_DEBUG); | |
522a0d4e RH |
11288 | /* The address covered by the breakpoint must be |
11289 | included in [tb->pc, tb->pc + tb->size) in order | |
11290 | to for it to be properly cleared -- thus we | |
11291 | increment the PC here so that the logic setting | |
11292 | tb->size below does the right thing. */ | |
5d98bf8f SF |
11293 | dc->pc += 4; |
11294 | goto done_generating; | |
11295 | } | |
11296 | break; | |
b933066a RH |
11297 | } |
11298 | } | |
11299 | } | |
11300 | ||
959082fc | 11301 | if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) { |
40f860cd PM |
11302 | gen_io_start(); |
11303 | } | |
11304 | ||
7ea47fe7 PM |
11305 | if (dc->ss_active && !dc->pstate_ss) { |
11306 | /* Singlestep state is Active-pending. | |
11307 | * If we're in this state at the start of a TB then either | |
11308 | * a) we just took an exception to an EL which is being debugged | |
11309 | * and this is the first insn in the exception handler | |
11310 | * b) debug exceptions were masked and we just unmasked them | |
11311 | * without changing EL (eg by clearing PSTATE.D) | |
11312 | * In either case we're going to take a swstep exception in the | |
11313 | * "did not step an insn" case, and so the syndrome ISV and EX | |
11314 | * bits should be zero. | |
11315 | */ | |
959082fc | 11316 | assert(num_insns == 1); |
73710361 GB |
11317 | gen_exception(EXCP_UDEF, syn_swstep(dc->ss_same_el, 0, 0), |
11318 | default_exception_el(dc)); | |
7ea47fe7 PM |
11319 | dc->is_jmp = DISAS_EXC; |
11320 | break; | |
11321 | } | |
11322 | ||
40f860cd PM |
11323 | disas_a64_insn(env, dc); |
11324 | ||
11325 | if (tcg_check_temp_count()) { | |
11326 | fprintf(stderr, "TCG temporary leak before "TARGET_FMT_lx"\n", | |
11327 | dc->pc); | |
11328 | } | |
11329 | ||
11330 | /* Translation stops when a conditional branch is encountered. | |
11331 | * Otherwise the subsequent code could get translated several times. | |
11332 | * Also stop translation when a page boundary is reached. This | |
11333 | * ensures prefetch aborts occur at the right place. | |
11334 | */ | |
fe700adb | 11335 | } while (!dc->is_jmp && !tcg_op_buf_full() && |
40f860cd PM |
11336 | !cs->singlestep_enabled && |
11337 | !singlestep && | |
7ea47fe7 | 11338 | !dc->ss_active && |
40f860cd PM |
11339 | dc->pc < next_page_start && |
11340 | num_insns < max_insns); | |
11341 | ||
11342 | if (tb->cflags & CF_LAST_IO) { | |
11343 | gen_io_end(); | |
11344 | } | |
11345 | ||
7ea47fe7 PM |
11346 | if (unlikely(cs->singlestep_enabled || dc->ss_active) |
11347 | && dc->is_jmp != DISAS_EXC) { | |
40f860cd PM |
11348 | /* Note that this means single stepping WFI doesn't halt the CPU. |
11349 | * For conditional branch insns this is harmless unreachable code as | |
11350 | * gen_goto_tb() has already handled emitting the debug exception | |
11351 | * (and thus a tb-jump is not possible when singlestepping). | |
11352 | */ | |
11353 | assert(dc->is_jmp != DISAS_TB_JUMP); | |
11354 | if (dc->is_jmp != DISAS_JUMP) { | |
11355 | gen_a64_set_pc_im(dc->pc); | |
11356 | } | |
7ea47fe7 PM |
11357 | if (cs->singlestep_enabled) { |
11358 | gen_exception_internal(EXCP_DEBUG); | |
11359 | } else { | |
11360 | gen_step_complete_exception(dc); | |
11361 | } | |
40f860cd PM |
11362 | } else { |
11363 | switch (dc->is_jmp) { | |
11364 | case DISAS_NEXT: | |
11365 | gen_goto_tb(dc, 1, dc->pc); | |
11366 | break; | |
11367 | default: | |
40f860cd | 11368 | case DISAS_UPDATE: |
fea50522 PM |
11369 | gen_a64_set_pc_im(dc->pc); |
11370 | /* fall through */ | |
11371 | case DISAS_JUMP: | |
e75449a3 | 11372 | tcg_gen_lookup_and_goto_ptr(cpu_pc); |
40f860cd | 11373 | break; |
8da54b25 RH |
11374 | case DISAS_EXIT: |
11375 | tcg_gen_exit_tb(0); | |
11376 | break; | |
40f860cd PM |
11377 | case DISAS_TB_JUMP: |
11378 | case DISAS_EXC: | |
11379 | case DISAS_SWI: | |
11380 | break; | |
252ec405 RH |
11381 | case DISAS_WFE: |
11382 | gen_a64_set_pc_im(dc->pc); | |
11383 | gen_helper_wfe(cpu_env); | |
11384 | break; | |
049e24a1 PM |
11385 | case DISAS_YIELD: |
11386 | gen_a64_set_pc_im(dc->pc); | |
11387 | gen_helper_yield(cpu_env); | |
11388 | break; | |
40f860cd PM |
11389 | case DISAS_WFI: |
11390 | /* This is a special case because we don't want to just halt the CPU | |
11391 | * if trying to debug across a WFI. | |
11392 | */ | |
1ed69e82 | 11393 | gen_a64_set_pc_im(dc->pc); |
40f860cd | 11394 | gen_helper_wfi(cpu_env); |
84549b6d PM |
11395 | /* The helper doesn't necessarily throw an exception, but we |
11396 | * must go back to the main loop to check for interrupts anyway. | |
11397 | */ | |
11398 | tcg_gen_exit_tb(0); | |
40f860cd PM |
11399 | break; |
11400 | } | |
11401 | } | |
11402 | ||
11403 | done_generating: | |
11404 | gen_tb_end(tb, num_insns); | |
40f860cd PM |
11405 | |
11406 | #ifdef DEBUG_DISAS | |
06486077 AB |
11407 | if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) && |
11408 | qemu_log_in_addr_range(pc_start)) { | |
1ee73216 | 11409 | qemu_log_lock(); |
40f860cd PM |
11410 | qemu_log("----------------\n"); |
11411 | qemu_log("IN: %s\n", lookup_symbol(pc_start)); | |
d49190c4 | 11412 | log_target_disas(cs, pc_start, dc->pc - pc_start, |
f9fd40eb | 11413 | 4 | (bswap_code(dc->sctlr_b) ? 2 : 0)); |
40f860cd | 11414 | qemu_log("\n"); |
1ee73216 | 11415 | qemu_log_unlock(); |
40f860cd PM |
11416 | } |
11417 | #endif | |
4e5e1215 RH |
11418 | tb->size = dc->pc - pc_start; |
11419 | tb->icount = num_insns; | |
14ade10f | 11420 | } |