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14ade10f AG |
1 | /* |
2 | * AArch64 translation | |
3 | * | |
4 | * Copyright (c) 2013 Alexander Graf <agraf@suse.de> | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
74c21bd0 | 19 | #include "qemu/osdep.h" |
14ade10f AG |
20 | |
21 | #include "cpu.h" | |
63c91552 | 22 | #include "exec/exec-all.h" |
dcb32f1d PMD |
23 | #include "tcg/tcg-op.h" |
24 | #include "tcg/tcg-op-gvec.h" | |
14ade10f | 25 | #include "qemu/log.h" |
1d854765 | 26 | #include "arm_ldst.h" |
14ade10f | 27 | #include "translate.h" |
ccd38087 | 28 | #include "internals.h" |
14ade10f AG |
29 | #include "qemu/host-utils.h" |
30 | ||
f1672e6f | 31 | #include "hw/semihosting/semihost.h" |
40f860cd PM |
32 | #include "exec/gen-icount.h" |
33 | ||
2ef6175a RH |
34 | #include "exec/helper-proto.h" |
35 | #include "exec/helper-gen.h" | |
508127e2 | 36 | #include "exec/log.h" |
14ade10f | 37 | |
a7e30d84 | 38 | #include "trace-tcg.h" |
8c71baed | 39 | #include "translate-a64.h" |
62823083 | 40 | #include "qemu/atomic128.h" |
a7e30d84 | 41 | |
14ade10f AG |
42 | static TCGv_i64 cpu_X[32]; |
43 | static TCGv_i64 cpu_pc; | |
14ade10f | 44 | |
fa2ef212 | 45 | /* Load/store exclusive handling */ |
fa2ef212 | 46 | static TCGv_i64 cpu_exclusive_high; |
fa2ef212 | 47 | |
14ade10f AG |
48 | static const char *regnames[] = { |
49 | "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", | |
50 | "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", | |
51 | "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", | |
52 | "x24", "x25", "x26", "x27", "x28", "x29", "lr", "sp" | |
53 | }; | |
54 | ||
832ffa1c AG |
55 | enum a64_shift_type { |
56 | A64_SHIFT_TYPE_LSL = 0, | |
57 | A64_SHIFT_TYPE_LSR = 1, | |
58 | A64_SHIFT_TYPE_ASR = 2, | |
59 | A64_SHIFT_TYPE_ROR = 3 | |
60 | }; | |
61 | ||
384b26fb AB |
62 | /* Table based decoder typedefs - used when the relevant bits for decode |
63 | * are too awkwardly scattered across the instruction (eg SIMD). | |
64 | */ | |
65 | typedef void AArch64DecodeFn(DisasContext *s, uint32_t insn); | |
66 | ||
67 | typedef struct AArch64DecodeTable { | |
68 | uint32_t pattern; | |
69 | uint32_t mask; | |
70 | AArch64DecodeFn *disas_fn; | |
71 | } AArch64DecodeTable; | |
72 | ||
14ade10f AG |
73 | /* initialize TCG globals. */ |
74 | void a64_translate_init(void) | |
75 | { | |
76 | int i; | |
77 | ||
e1ccc054 | 78 | cpu_pc = tcg_global_mem_new_i64(cpu_env, |
14ade10f AG |
79 | offsetof(CPUARMState, pc), |
80 | "pc"); | |
81 | for (i = 0; i < 32; i++) { | |
e1ccc054 | 82 | cpu_X[i] = tcg_global_mem_new_i64(cpu_env, |
14ade10f AG |
83 | offsetof(CPUARMState, xregs[i]), |
84 | regnames[i]); | |
85 | } | |
86 | ||
e1ccc054 | 87 | cpu_exclusive_high = tcg_global_mem_new_i64(cpu_env, |
fa2ef212 | 88 | offsetof(CPUARMState, exclusive_high), "exclusive_high"); |
14ade10f AG |
89 | } |
90 | ||
cc28fc30 RH |
91 | /* |
92 | * Return the core mmu_idx to use for A64 "unprivileged load/store" insns | |
93 | */ | |
94 | static int get_a64_user_mem_index(DisasContext *s) | |
579d21cc | 95 | { |
cc28fc30 RH |
96 | /* |
97 | * If AccType_UNPRIV is not used, the insn uses AccType_NORMAL, | |
98 | * which is the usual mmu_idx for this cpu state. | |
579d21cc | 99 | */ |
cc28fc30 | 100 | ARMMMUIdx useridx = s->mmu_idx; |
8bd5c820 | 101 | |
cc28fc30 RH |
102 | if (s->unpriv) { |
103 | /* | |
104 | * We have pre-computed the condition for AccType_UNPRIV. | |
105 | * Therefore we should never get here with a mmu_idx for | |
106 | * which we do not know the corresponding user mmu_idx. | |
107 | */ | |
108 | switch (useridx) { | |
109 | case ARMMMUIdx_E10_1: | |
452ef8cb | 110 | case ARMMMUIdx_E10_1_PAN: |
cc28fc30 RH |
111 | useridx = ARMMMUIdx_E10_0; |
112 | break; | |
113 | case ARMMMUIdx_E20_2: | |
452ef8cb | 114 | case ARMMMUIdx_E20_2_PAN: |
cc28fc30 RH |
115 | useridx = ARMMMUIdx_E20_0; |
116 | break; | |
117 | case ARMMMUIdx_SE10_1: | |
452ef8cb | 118 | case ARMMMUIdx_SE10_1_PAN: |
cc28fc30 RH |
119 | useridx = ARMMMUIdx_SE10_0; |
120 | break; | |
121 | default: | |
122 | g_assert_not_reached(); | |
123 | } | |
579d21cc | 124 | } |
8bd5c820 | 125 | return arm_to_core_mmu_idx(useridx); |
579d21cc PM |
126 | } |
127 | ||
51bf0d7a RH |
128 | static void reset_btype(DisasContext *s) |
129 | { | |
130 | if (s->btype != 0) { | |
131 | TCGv_i32 zero = tcg_const_i32(0); | |
132 | tcg_gen_st_i32(zero, cpu_env, offsetof(CPUARMState, btype)); | |
133 | tcg_temp_free_i32(zero); | |
134 | s->btype = 0; | |
135 | } | |
136 | } | |
137 | ||
001d47b6 RH |
138 | static void set_btype(DisasContext *s, int val) |
139 | { | |
140 | TCGv_i32 tcg_val; | |
141 | ||
142 | /* BTYPE is a 2-bit field, and 0 should be done with reset_btype. */ | |
143 | tcg_debug_assert(val >= 1 && val <= 3); | |
144 | ||
145 | tcg_val = tcg_const_i32(val); | |
146 | tcg_gen_st_i32(tcg_val, cpu_env, offsetof(CPUARMState, btype)); | |
147 | tcg_temp_free_i32(tcg_val); | |
148 | s->btype = -1; | |
149 | } | |
150 | ||
14ade10f AG |
151 | void gen_a64_set_pc_im(uint64_t val) |
152 | { | |
153 | tcg_gen_movi_i64(cpu_pc, val); | |
154 | } | |
155 | ||
4a9ee99d RH |
156 | /* |
157 | * Handle Top Byte Ignore (TBI) bits. | |
6feecb8b | 158 | * |
4a9ee99d | 159 | * If address tagging is enabled via the TCR TBI bits: |
6feecb8b TH |
160 | * + for EL2 and EL3 there is only one TBI bit, and if it is set |
161 | * then the address is zero-extended, clearing bits [63:56] | |
162 | * + for EL0 and EL1, TBI0 controls addresses with bit 55 == 0 | |
163 | * and TBI1 controls addressses with bit 55 == 1. | |
164 | * If the appropriate TBI bit is set for the address then | |
165 | * the address is sign-extended from bit 55 into bits [63:56] | |
166 | * | |
4a9ee99d | 167 | * Here We have concatenated TBI{1,0} into tbi. |
6feecb8b | 168 | */ |
4a9ee99d RH |
169 | static void gen_top_byte_ignore(DisasContext *s, TCGv_i64 dst, |
170 | TCGv_i64 src, int tbi) | |
6feecb8b | 171 | { |
4a9ee99d RH |
172 | if (tbi == 0) { |
173 | /* Load unmodified address */ | |
174 | tcg_gen_mov_i64(dst, src); | |
339370b9 | 175 | } else if (!regime_has_2_ranges(s->mmu_idx)) { |
4a9ee99d RH |
176 | /* Force tag byte to all zero */ |
177 | tcg_gen_extract_i64(dst, src, 0, 56); | |
178 | } else { | |
179 | /* Sign-extend from bit 55. */ | |
180 | tcg_gen_sextract_i64(dst, src, 0, 56); | |
6feecb8b | 181 | |
4a9ee99d RH |
182 | if (tbi != 3) { |
183 | TCGv_i64 tcg_zero = tcg_const_i64(0); | |
6feecb8b | 184 | |
4a9ee99d RH |
185 | /* |
186 | * The two TBI bits differ. | |
187 | * If tbi0, then !tbi1: only use the extension if positive. | |
188 | * if !tbi0, then tbi1: only use the extension if negative. | |
189 | */ | |
190 | tcg_gen_movcond_i64(tbi == 1 ? TCG_COND_GE : TCG_COND_LT, | |
191 | dst, dst, tcg_zero, dst, src); | |
192 | tcg_temp_free_i64(tcg_zero); | |
6feecb8b TH |
193 | } |
194 | } | |
4a9ee99d | 195 | } |
8733d762 | 196 | |
4a9ee99d RH |
197 | static void gen_a64_set_pc(DisasContext *s, TCGv_i64 src) |
198 | { | |
199 | /* | |
200 | * If address tagging is enabled for instructions via the TCR TBI bits, | |
201 | * then loading an address into the PC will clear out any tag. | |
202 | */ | |
203 | gen_top_byte_ignore(s, cpu_pc, src, s->tbii); | |
6feecb8b TH |
204 | } |
205 | ||
3a471103 RH |
206 | /* |
207 | * Return a "clean" address for ADDR according to TBID. | |
208 | * This is always a fresh temporary, as we need to be able to | |
209 | * increment this independently of a dirty write-back address. | |
210 | */ | |
211 | static TCGv_i64 clean_data_tbi(DisasContext *s, TCGv_i64 addr) | |
212 | { | |
213 | TCGv_i64 clean = new_tmp_a64(s); | |
38d93168 RH |
214 | /* |
215 | * In order to get the correct value in the FAR_ELx register, | |
216 | * we must present the memory subsystem with the "dirty" address | |
217 | * including the TBI. In system mode we can make this work via | |
218 | * the TLB, dropping the TBI during translation. But for user-only | |
219 | * mode we don't have that option, and must remove the top byte now. | |
220 | */ | |
221 | #ifdef CONFIG_USER_ONLY | |
3a471103 | 222 | gen_top_byte_ignore(s, clean, addr, s->tbid); |
38d93168 RH |
223 | #else |
224 | tcg_gen_mov_i64(clean, addr); | |
225 | #endif | |
3a471103 RH |
226 | return clean; |
227 | } | |
228 | ||
259cb684 RH |
229 | typedef struct DisasCompare64 { |
230 | TCGCond cond; | |
231 | TCGv_i64 value; | |
232 | } DisasCompare64; | |
233 | ||
234 | static void a64_test_cc(DisasCompare64 *c64, int cc) | |
235 | { | |
236 | DisasCompare c32; | |
237 | ||
238 | arm_test_cc(&c32, cc); | |
239 | ||
240 | /* Sign-extend the 32-bit value so that the GE/LT comparisons work | |
241 | * properly. The NE/EQ comparisons are also fine with this choice. */ | |
242 | c64->cond = c32.cond; | |
243 | c64->value = tcg_temp_new_i64(); | |
244 | tcg_gen_ext_i32_i64(c64->value, c32.value); | |
245 | ||
246 | arm_free_cc(&c32); | |
247 | } | |
248 | ||
249 | static void a64_free_cc(DisasCompare64 *c64) | |
250 | { | |
251 | tcg_temp_free_i64(c64->value); | |
252 | } | |
253 | ||
d4a2dc67 | 254 | static void gen_exception_internal(int excp) |
14ade10f | 255 | { |
d4a2dc67 PM |
256 | TCGv_i32 tcg_excp = tcg_const_i32(excp); |
257 | ||
258 | assert(excp_is_internal(excp)); | |
259 | gen_helper_exception_internal(cpu_env, tcg_excp); | |
260 | tcg_temp_free_i32(tcg_excp); | |
261 | } | |
262 | ||
aee828e7 | 263 | static void gen_exception_internal_insn(DisasContext *s, uint64_t pc, int excp) |
d4a2dc67 | 264 | { |
aee828e7 | 265 | gen_a64_set_pc_im(pc); |
d4a2dc67 | 266 | gen_exception_internal(excp); |
dcba3a8d | 267 | s->base.is_jmp = DISAS_NORETURN; |
14ade10f AG |
268 | } |
269 | ||
a767fac8 | 270 | static void gen_exception_insn(DisasContext *s, uint64_t pc, int excp, |
73710361 | 271 | uint32_t syndrome, uint32_t target_el) |
14ade10f | 272 | { |
a767fac8 | 273 | gen_a64_set_pc_im(pc); |
73710361 | 274 | gen_exception(excp, syndrome, target_el); |
dcba3a8d | 275 | s->base.is_jmp = DISAS_NORETURN; |
40f860cd PM |
276 | } |
277 | ||
06bcbda3 | 278 | static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syndrome) |
c900a2e6 PM |
279 | { |
280 | TCGv_i32 tcg_syn; | |
281 | ||
06bcbda3 | 282 | gen_a64_set_pc_im(s->pc_curr); |
c900a2e6 PM |
283 | tcg_syn = tcg_const_i32(syndrome); |
284 | gen_helper_exception_bkpt_insn(cpu_env, tcg_syn); | |
285 | tcg_temp_free_i32(tcg_syn); | |
286 | s->base.is_jmp = DISAS_NORETURN; | |
287 | } | |
288 | ||
7ea47fe7 PM |
289 | static void gen_step_complete_exception(DisasContext *s) |
290 | { | |
291 | /* We just completed step of an insn. Move from Active-not-pending | |
292 | * to Active-pending, and then also take the swstep exception. | |
293 | * This corresponds to making the (IMPDEF) choice to prioritize | |
294 | * swstep exceptions over asynchronous exceptions taken to an exception | |
295 | * level where debug is disabled. This choice has the advantage that | |
296 | * we do not need to maintain internal state corresponding to the | |
297 | * ISV/EX syndrome bits between completion of the step and generation | |
298 | * of the exception, and our syndrome information is always correct. | |
299 | */ | |
300 | gen_ss_advance(s); | |
c1d5f50f | 301 | gen_swstep_exception(s, 1, s->is_ldex); |
dcba3a8d | 302 | s->base.is_jmp = DISAS_NORETURN; |
7ea47fe7 PM |
303 | } |
304 | ||
40f860cd PM |
305 | static inline bool use_goto_tb(DisasContext *s, int n, uint64_t dest) |
306 | { | |
7ea47fe7 PM |
307 | /* No direct tb linking with singlestep (either QEMU's or the ARM |
308 | * debug architecture kind) or deterministic io | |
309 | */ | |
c5a49c63 EC |
310 | if (s->base.singlestep_enabled || s->ss_active || |
311 | (tb_cflags(s->base.tb) & CF_LAST_IO)) { | |
40f860cd PM |
312 | return false; |
313 | } | |
314 | ||
90aa39a1 | 315 | #ifndef CONFIG_USER_ONLY |
40f860cd | 316 | /* Only link tbs from inside the same guest page */ |
dcba3a8d | 317 | if ((s->base.tb->pc & TARGET_PAGE_MASK) != (dest & TARGET_PAGE_MASK)) { |
40f860cd PM |
318 | return false; |
319 | } | |
90aa39a1 | 320 | #endif |
40f860cd PM |
321 | |
322 | return true; | |
323 | } | |
324 | ||
325 | static inline void gen_goto_tb(DisasContext *s, int n, uint64_t dest) | |
326 | { | |
327 | TranslationBlock *tb; | |
328 | ||
dcba3a8d | 329 | tb = s->base.tb; |
40f860cd PM |
330 | if (use_goto_tb(s, n, dest)) { |
331 | tcg_gen_goto_tb(n); | |
332 | gen_a64_set_pc_im(dest); | |
07ea28b4 | 333 | tcg_gen_exit_tb(tb, n); |
dcba3a8d | 334 | s->base.is_jmp = DISAS_NORETURN; |
40f860cd PM |
335 | } else { |
336 | gen_a64_set_pc_im(dest); | |
7ea47fe7 PM |
337 | if (s->ss_active) { |
338 | gen_step_complete_exception(s); | |
dcba3a8d | 339 | } else if (s->base.singlestep_enabled) { |
d4a2dc67 | 340 | gen_exception_internal(EXCP_DEBUG); |
cc9c1ed1 | 341 | } else { |
7f11636d | 342 | tcg_gen_lookup_and_goto_ptr(); |
dcba3a8d | 343 | s->base.is_jmp = DISAS_NORETURN; |
40f860cd | 344 | } |
40f860cd | 345 | } |
14ade10f AG |
346 | } |
347 | ||
429a71d6 RH |
348 | void unallocated_encoding(DisasContext *s) |
349 | { | |
350 | /* Unallocated and reserved encodings are uncategorized */ | |
351 | gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(), | |
352 | default_exception_el(s)); | |
353 | } | |
354 | ||
11e169de AG |
355 | static void init_tmp_a64_array(DisasContext *s) |
356 | { | |
357 | #ifdef CONFIG_DEBUG_TCG | |
f764718d | 358 | memset(s->tmp_a64, 0, sizeof(s->tmp_a64)); |
11e169de AG |
359 | #endif |
360 | s->tmp_a64_count = 0; | |
361 | } | |
362 | ||
363 | static void free_tmp_a64(DisasContext *s) | |
364 | { | |
365 | int i; | |
366 | for (i = 0; i < s->tmp_a64_count; i++) { | |
367 | tcg_temp_free_i64(s->tmp_a64[i]); | |
368 | } | |
369 | init_tmp_a64_array(s); | |
370 | } | |
371 | ||
8c71baed | 372 | TCGv_i64 new_tmp_a64(DisasContext *s) |
11e169de AG |
373 | { |
374 | assert(s->tmp_a64_count < TMP_A64_MAX); | |
375 | return s->tmp_a64[s->tmp_a64_count++] = tcg_temp_new_i64(); | |
376 | } | |
377 | ||
8c71baed | 378 | TCGv_i64 new_tmp_a64_zero(DisasContext *s) |
11e169de AG |
379 | { |
380 | TCGv_i64 t = new_tmp_a64(s); | |
381 | tcg_gen_movi_i64(t, 0); | |
382 | return t; | |
383 | } | |
384 | ||
71b46089 AG |
385 | /* |
386 | * Register access functions | |
387 | * | |
388 | * These functions are used for directly accessing a register in where | |
389 | * changes to the final register value are likely to be made. If you | |
390 | * need to use a register for temporary calculation (e.g. index type | |
391 | * operations) use the read_* form. | |
392 | * | |
393 | * B1.2.1 Register mappings | |
394 | * | |
395 | * In instruction register encoding 31 can refer to ZR (zero register) or | |
396 | * the SP (stack pointer) depending on context. In QEMU's case we map SP | |
397 | * to cpu_X[31] and ZR accesses to a temporary which can be discarded. | |
398 | * This is the point of the _sp forms. | |
399 | */ | |
8c71baed | 400 | TCGv_i64 cpu_reg(DisasContext *s, int reg) |
11e169de AG |
401 | { |
402 | if (reg == 31) { | |
403 | return new_tmp_a64_zero(s); | |
404 | } else { | |
405 | return cpu_X[reg]; | |
406 | } | |
407 | } | |
408 | ||
71b46089 | 409 | /* register access for when 31 == SP */ |
8c71baed | 410 | TCGv_i64 cpu_reg_sp(DisasContext *s, int reg) |
71b46089 AG |
411 | { |
412 | return cpu_X[reg]; | |
413 | } | |
414 | ||
60e53388 AG |
415 | /* read a cpu register in 32bit/64bit mode. Returns a TCGv_i64 |
416 | * representing the register contents. This TCGv is an auto-freed | |
417 | * temporary so it need not be explicitly freed, and may be modified. | |
418 | */ | |
8c71baed | 419 | TCGv_i64 read_cpu_reg(DisasContext *s, int reg, int sf) |
60e53388 AG |
420 | { |
421 | TCGv_i64 v = new_tmp_a64(s); | |
422 | if (reg != 31) { | |
423 | if (sf) { | |
424 | tcg_gen_mov_i64(v, cpu_X[reg]); | |
425 | } else { | |
426 | tcg_gen_ext32u_i64(v, cpu_X[reg]); | |
427 | } | |
428 | } else { | |
429 | tcg_gen_movi_i64(v, 0); | |
430 | } | |
431 | return v; | |
432 | } | |
433 | ||
8c71baed | 434 | TCGv_i64 read_cpu_reg_sp(DisasContext *s, int reg, int sf) |
4a08d475 PM |
435 | { |
436 | TCGv_i64 v = new_tmp_a64(s); | |
437 | if (sf) { | |
438 | tcg_gen_mov_i64(v, cpu_X[reg]); | |
439 | } else { | |
440 | tcg_gen_ext32u_i64(v, cpu_X[reg]); | |
441 | } | |
442 | return v; | |
443 | } | |
444 | ||
e2f90565 PM |
445 | /* Return the offset into CPUARMState of a slice (from |
446 | * the least significant end) of FP register Qn (ie | |
447 | * Dn, Sn, Hn or Bn). | |
448 | * (Note that this is not the same mapping as for A32; see cpu.h) | |
449 | */ | |
14776ab5 | 450 | static inline int fp_reg_offset(DisasContext *s, int regno, MemOp size) |
e2f90565 | 451 | { |
9a2b5256 | 452 | return vec_reg_offset(s, regno, 0, size); |
e2f90565 PM |
453 | } |
454 | ||
455 | /* Offset of the high half of the 128 bit vector Qn */ | |
90e49638 | 456 | static inline int fp_reg_hi_offset(DisasContext *s, int regno) |
e2f90565 | 457 | { |
9a2b5256 | 458 | return vec_reg_offset(s, regno, 1, MO_64); |
e2f90565 PM |
459 | } |
460 | ||
ec73d2e0 AG |
461 | /* Convenience accessors for reading and writing single and double |
462 | * FP registers. Writing clears the upper parts of the associated | |
463 | * 128 bit vector register, as required by the architecture. | |
464 | * Note that unlike the GP register accessors, the values returned | |
465 | * by the read functions must be manually freed. | |
466 | */ | |
467 | static TCGv_i64 read_fp_dreg(DisasContext *s, int reg) | |
468 | { | |
469 | TCGv_i64 v = tcg_temp_new_i64(); | |
470 | ||
90e49638 | 471 | tcg_gen_ld_i64(v, cpu_env, fp_reg_offset(s, reg, MO_64)); |
ec73d2e0 AG |
472 | return v; |
473 | } | |
474 | ||
475 | static TCGv_i32 read_fp_sreg(DisasContext *s, int reg) | |
476 | { | |
477 | TCGv_i32 v = tcg_temp_new_i32(); | |
478 | ||
90e49638 | 479 | tcg_gen_ld_i32(v, cpu_env, fp_reg_offset(s, reg, MO_32)); |
ec73d2e0 AG |
480 | return v; |
481 | } | |
482 | ||
3d99d931 RH |
483 | static TCGv_i32 read_fp_hreg(DisasContext *s, int reg) |
484 | { | |
485 | TCGv_i32 v = tcg_temp_new_i32(); | |
486 | ||
487 | tcg_gen_ld16u_i32(v, cpu_env, fp_reg_offset(s, reg, MO_16)); | |
488 | return v; | |
489 | } | |
490 | ||
4ff55bcb RH |
491 | /* Clear the bits above an N-bit vector, for N = (is_q ? 128 : 64). |
492 | * If SVE is not enabled, then there are only 128 bits in the vector. | |
493 | */ | |
494 | static void clear_vec_high(DisasContext *s, bool is_q, int rd) | |
495 | { | |
496 | unsigned ofs = fp_reg_offset(s, rd, MO_64); | |
497 | unsigned vsz = vec_full_reg_size(s); | |
498 | ||
5c27392d RH |
499 | /* Nop move, with side effect of clearing the tail. */ |
500 | tcg_gen_gvec_mov(MO_64, ofs, ofs, is_q ? 16 : 8, vsz); | |
4ff55bcb RH |
501 | } |
502 | ||
8c71baed | 503 | void write_fp_dreg(DisasContext *s, int reg, TCGv_i64 v) |
ec73d2e0 | 504 | { |
4ff55bcb | 505 | unsigned ofs = fp_reg_offset(s, reg, MO_64); |
ec73d2e0 | 506 | |
4ff55bcb RH |
507 | tcg_gen_st_i64(v, cpu_env, ofs); |
508 | clear_vec_high(s, false, reg); | |
ec73d2e0 AG |
509 | } |
510 | ||
511 | static void write_fp_sreg(DisasContext *s, int reg, TCGv_i32 v) | |
512 | { | |
513 | TCGv_i64 tmp = tcg_temp_new_i64(); | |
514 | ||
515 | tcg_gen_extu_i32_i64(tmp, v); | |
516 | write_fp_dreg(s, reg, tmp); | |
517 | tcg_temp_free_i64(tmp); | |
518 | } | |
519 | ||
8c71baed | 520 | TCGv_ptr get_fpstatus_ptr(bool is_f16) |
ec73d2e0 AG |
521 | { |
522 | TCGv_ptr statusptr = tcg_temp_new_ptr(); | |
523 | int offset; | |
524 | ||
d81ce0ef AB |
525 | /* In A64 all instructions (both FP and Neon) use the FPCR; there |
526 | * is no equivalent of the A32 Neon "standard FPSCR value". | |
527 | * However half-precision operations operate under a different | |
528 | * FZ16 flag and use vfp.fp_status_f16 instead of vfp.fp_status. | |
ec73d2e0 | 529 | */ |
d81ce0ef AB |
530 | if (is_f16) { |
531 | offset = offsetof(CPUARMState, vfp.fp_status_f16); | |
532 | } else { | |
533 | offset = offsetof(CPUARMState, vfp.fp_status); | |
534 | } | |
ec73d2e0 AG |
535 | tcg_gen_addi_ptr(statusptr, cpu_env, offset); |
536 | return statusptr; | |
537 | } | |
538 | ||
377ef731 RH |
539 | /* Expand a 2-operand AdvSIMD vector operation using an expander function. */ |
540 | static void gen_gvec_fn2(DisasContext *s, bool is_q, int rd, int rn, | |
541 | GVecGen2Fn *gvec_fn, int vece) | |
542 | { | |
543 | gvec_fn(vece, vec_full_reg_offset(s, rd), vec_full_reg_offset(s, rn), | |
544 | is_q ? 16 : 8, vec_full_reg_size(s)); | |
545 | } | |
546 | ||
cdb45a60 RH |
547 | /* Expand a 2-operand + immediate AdvSIMD vector operation using |
548 | * an expander function. | |
549 | */ | |
550 | static void gen_gvec_fn2i(DisasContext *s, bool is_q, int rd, int rn, | |
551 | int64_t imm, GVecGen2iFn *gvec_fn, int vece) | |
552 | { | |
553 | gvec_fn(vece, vec_full_reg_offset(s, rd), vec_full_reg_offset(s, rn), | |
554 | imm, is_q ? 16 : 8, vec_full_reg_size(s)); | |
555 | } | |
556 | ||
bc48092f RH |
557 | /* Expand a 3-operand AdvSIMD vector operation using an expander function. */ |
558 | static void gen_gvec_fn3(DisasContext *s, bool is_q, int rd, int rn, int rm, | |
559 | GVecGen3Fn *gvec_fn, int vece) | |
560 | { | |
561 | gvec_fn(vece, vec_full_reg_offset(s, rd), vec_full_reg_offset(s, rn), | |
562 | vec_full_reg_offset(s, rm), is_q ? 16 : 8, vec_full_reg_size(s)); | |
563 | } | |
564 | ||
3a7a2b4e RH |
565 | /* Expand a 4-operand AdvSIMD vector operation using an expander function. */ |
566 | static void gen_gvec_fn4(DisasContext *s, bool is_q, int rd, int rn, int rm, | |
567 | int rx, GVecGen4Fn *gvec_fn, int vece) | |
568 | { | |
569 | gvec_fn(vece, vec_full_reg_offset(s, rd), vec_full_reg_offset(s, rn), | |
570 | vec_full_reg_offset(s, rm), vec_full_reg_offset(s, rx), | |
571 | is_q ? 16 : 8, vec_full_reg_size(s)); | |
572 | } | |
573 | ||
a04b68e1 RH |
574 | /* Expand a 2-operand operation using an out-of-line helper. */ |
575 | static void gen_gvec_op2_ool(DisasContext *s, bool is_q, int rd, | |
576 | int rn, int data, gen_helper_gvec_2 *fn) | |
577 | { | |
578 | tcg_gen_gvec_2_ool(vec_full_reg_offset(s, rd), | |
579 | vec_full_reg_offset(s, rn), | |
580 | is_q ? 16 : 8, vec_full_reg_size(s), data, fn); | |
581 | } | |
582 | ||
26c470a7 RH |
583 | /* Expand a 3-operand operation using an out-of-line helper. */ |
584 | static void gen_gvec_op3_ool(DisasContext *s, bool is_q, int rd, | |
585 | int rn, int rm, int data, gen_helper_gvec_3 *fn) | |
586 | { | |
587 | tcg_gen_gvec_3_ool(vec_full_reg_offset(s, rd), | |
588 | vec_full_reg_offset(s, rn), | |
589 | vec_full_reg_offset(s, rm), | |
590 | is_q ? 16 : 8, vec_full_reg_size(s), data, fn); | |
591 | } | |
592 | ||
1695cd61 RH |
593 | /* Expand a 3-operand + fpstatus pointer + simd data value operation using |
594 | * an out-of-line helper. | |
595 | */ | |
596 | static void gen_gvec_op3_fpst(DisasContext *s, bool is_q, int rd, int rn, | |
597 | int rm, bool is_fp16, int data, | |
598 | gen_helper_gvec_3_ptr *fn) | |
599 | { | |
600 | TCGv_ptr fpst = get_fpstatus_ptr(is_fp16); | |
601 | tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd), | |
602 | vec_full_reg_offset(s, rn), | |
603 | vec_full_reg_offset(s, rm), fpst, | |
604 | is_q ? 16 : 8, vec_full_reg_size(s), data, fn); | |
605 | tcg_temp_free_ptr(fpst); | |
606 | } | |
607 | ||
832ffa1c AG |
608 | /* Set ZF and NF based on a 64 bit result. This is alas fiddlier |
609 | * than the 32 bit equivalent. | |
610 | */ | |
611 | static inline void gen_set_NZ64(TCGv_i64 result) | |
612 | { | |
7cb36e18 RH |
613 | tcg_gen_extr_i64_i32(cpu_ZF, cpu_NF, result); |
614 | tcg_gen_or_i32(cpu_ZF, cpu_ZF, cpu_NF); | |
832ffa1c AG |
615 | } |
616 | ||
617 | /* Set NZCV as for a logical operation: NZ as per result, CV cleared. */ | |
618 | static inline void gen_logic_CC(int sf, TCGv_i64 result) | |
619 | { | |
620 | if (sf) { | |
621 | gen_set_NZ64(result); | |
622 | } else { | |
ecc7b3aa | 623 | tcg_gen_extrl_i64_i32(cpu_ZF, result); |
7cb36e18 | 624 | tcg_gen_mov_i32(cpu_NF, cpu_ZF); |
832ffa1c AG |
625 | } |
626 | tcg_gen_movi_i32(cpu_CF, 0); | |
627 | tcg_gen_movi_i32(cpu_VF, 0); | |
628 | } | |
629 | ||
b0ff21b4 AB |
630 | /* dest = T0 + T1; compute C, N, V and Z flags */ |
631 | static void gen_add_CC(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1) | |
632 | { | |
633 | if (sf) { | |
634 | TCGv_i64 result, flag, tmp; | |
635 | result = tcg_temp_new_i64(); | |
636 | flag = tcg_temp_new_i64(); | |
637 | tmp = tcg_temp_new_i64(); | |
638 | ||
639 | tcg_gen_movi_i64(tmp, 0); | |
640 | tcg_gen_add2_i64(result, flag, t0, tmp, t1, tmp); | |
641 | ||
ecc7b3aa | 642 | tcg_gen_extrl_i64_i32(cpu_CF, flag); |
b0ff21b4 AB |
643 | |
644 | gen_set_NZ64(result); | |
645 | ||
646 | tcg_gen_xor_i64(flag, result, t0); | |
647 | tcg_gen_xor_i64(tmp, t0, t1); | |
648 | tcg_gen_andc_i64(flag, flag, tmp); | |
649 | tcg_temp_free_i64(tmp); | |
7cb36e18 | 650 | tcg_gen_extrh_i64_i32(cpu_VF, flag); |
b0ff21b4 AB |
651 | |
652 | tcg_gen_mov_i64(dest, result); | |
653 | tcg_temp_free_i64(result); | |
654 | tcg_temp_free_i64(flag); | |
655 | } else { | |
656 | /* 32 bit arithmetic */ | |
657 | TCGv_i32 t0_32 = tcg_temp_new_i32(); | |
658 | TCGv_i32 t1_32 = tcg_temp_new_i32(); | |
659 | TCGv_i32 tmp = tcg_temp_new_i32(); | |
660 | ||
661 | tcg_gen_movi_i32(tmp, 0); | |
ecc7b3aa RH |
662 | tcg_gen_extrl_i64_i32(t0_32, t0); |
663 | tcg_gen_extrl_i64_i32(t1_32, t1); | |
b0ff21b4 AB |
664 | tcg_gen_add2_i32(cpu_NF, cpu_CF, t0_32, tmp, t1_32, tmp); |
665 | tcg_gen_mov_i32(cpu_ZF, cpu_NF); | |
666 | tcg_gen_xor_i32(cpu_VF, cpu_NF, t0_32); | |
667 | tcg_gen_xor_i32(tmp, t0_32, t1_32); | |
668 | tcg_gen_andc_i32(cpu_VF, cpu_VF, tmp); | |
669 | tcg_gen_extu_i32_i64(dest, cpu_NF); | |
670 | ||
671 | tcg_temp_free_i32(tmp); | |
672 | tcg_temp_free_i32(t0_32); | |
673 | tcg_temp_free_i32(t1_32); | |
674 | } | |
675 | } | |
676 | ||
677 | /* dest = T0 - T1; compute C, N, V and Z flags */ | |
678 | static void gen_sub_CC(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1) | |
679 | { | |
680 | if (sf) { | |
681 | /* 64 bit arithmetic */ | |
682 | TCGv_i64 result, flag, tmp; | |
683 | ||
684 | result = tcg_temp_new_i64(); | |
685 | flag = tcg_temp_new_i64(); | |
686 | tcg_gen_sub_i64(result, t0, t1); | |
687 | ||
688 | gen_set_NZ64(result); | |
689 | ||
690 | tcg_gen_setcond_i64(TCG_COND_GEU, flag, t0, t1); | |
ecc7b3aa | 691 | tcg_gen_extrl_i64_i32(cpu_CF, flag); |
b0ff21b4 AB |
692 | |
693 | tcg_gen_xor_i64(flag, result, t0); | |
694 | tmp = tcg_temp_new_i64(); | |
695 | tcg_gen_xor_i64(tmp, t0, t1); | |
696 | tcg_gen_and_i64(flag, flag, tmp); | |
697 | tcg_temp_free_i64(tmp); | |
7cb36e18 | 698 | tcg_gen_extrh_i64_i32(cpu_VF, flag); |
b0ff21b4 AB |
699 | tcg_gen_mov_i64(dest, result); |
700 | tcg_temp_free_i64(flag); | |
701 | tcg_temp_free_i64(result); | |
702 | } else { | |
703 | /* 32 bit arithmetic */ | |
704 | TCGv_i32 t0_32 = tcg_temp_new_i32(); | |
705 | TCGv_i32 t1_32 = tcg_temp_new_i32(); | |
706 | TCGv_i32 tmp; | |
707 | ||
ecc7b3aa RH |
708 | tcg_gen_extrl_i64_i32(t0_32, t0); |
709 | tcg_gen_extrl_i64_i32(t1_32, t1); | |
b0ff21b4 AB |
710 | tcg_gen_sub_i32(cpu_NF, t0_32, t1_32); |
711 | tcg_gen_mov_i32(cpu_ZF, cpu_NF); | |
712 | tcg_gen_setcond_i32(TCG_COND_GEU, cpu_CF, t0_32, t1_32); | |
713 | tcg_gen_xor_i32(cpu_VF, cpu_NF, t0_32); | |
714 | tmp = tcg_temp_new_i32(); | |
715 | tcg_gen_xor_i32(tmp, t0_32, t1_32); | |
716 | tcg_temp_free_i32(t0_32); | |
717 | tcg_temp_free_i32(t1_32); | |
718 | tcg_gen_and_i32(cpu_VF, cpu_VF, tmp); | |
719 | tcg_temp_free_i32(tmp); | |
720 | tcg_gen_extu_i32_i64(dest, cpu_NF); | |
721 | } | |
722 | } | |
723 | ||
643dbb07 CF |
724 | /* dest = T0 + T1 + CF; do not compute flags. */ |
725 | static void gen_adc(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1) | |
726 | { | |
727 | TCGv_i64 flag = tcg_temp_new_i64(); | |
728 | tcg_gen_extu_i32_i64(flag, cpu_CF); | |
729 | tcg_gen_add_i64(dest, t0, t1); | |
730 | tcg_gen_add_i64(dest, dest, flag); | |
731 | tcg_temp_free_i64(flag); | |
732 | ||
733 | if (!sf) { | |
734 | tcg_gen_ext32u_i64(dest, dest); | |
735 | } | |
736 | } | |
737 | ||
738 | /* dest = T0 + T1 + CF; compute C, N, V and Z flags. */ | |
739 | static void gen_adc_CC(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1) | |
740 | { | |
741 | if (sf) { | |
742 | TCGv_i64 result, cf_64, vf_64, tmp; | |
743 | result = tcg_temp_new_i64(); | |
744 | cf_64 = tcg_temp_new_i64(); | |
745 | vf_64 = tcg_temp_new_i64(); | |
746 | tmp = tcg_const_i64(0); | |
747 | ||
748 | tcg_gen_extu_i32_i64(cf_64, cpu_CF); | |
749 | tcg_gen_add2_i64(result, cf_64, t0, tmp, cf_64, tmp); | |
750 | tcg_gen_add2_i64(result, cf_64, result, cf_64, t1, tmp); | |
ecc7b3aa | 751 | tcg_gen_extrl_i64_i32(cpu_CF, cf_64); |
643dbb07 CF |
752 | gen_set_NZ64(result); |
753 | ||
754 | tcg_gen_xor_i64(vf_64, result, t0); | |
755 | tcg_gen_xor_i64(tmp, t0, t1); | |
756 | tcg_gen_andc_i64(vf_64, vf_64, tmp); | |
7cb36e18 | 757 | tcg_gen_extrh_i64_i32(cpu_VF, vf_64); |
643dbb07 CF |
758 | |
759 | tcg_gen_mov_i64(dest, result); | |
760 | ||
761 | tcg_temp_free_i64(tmp); | |
762 | tcg_temp_free_i64(vf_64); | |
763 | tcg_temp_free_i64(cf_64); | |
764 | tcg_temp_free_i64(result); | |
765 | } else { | |
766 | TCGv_i32 t0_32, t1_32, tmp; | |
767 | t0_32 = tcg_temp_new_i32(); | |
768 | t1_32 = tcg_temp_new_i32(); | |
769 | tmp = tcg_const_i32(0); | |
770 | ||
ecc7b3aa RH |
771 | tcg_gen_extrl_i64_i32(t0_32, t0); |
772 | tcg_gen_extrl_i64_i32(t1_32, t1); | |
643dbb07 CF |
773 | tcg_gen_add2_i32(cpu_NF, cpu_CF, t0_32, tmp, cpu_CF, tmp); |
774 | tcg_gen_add2_i32(cpu_NF, cpu_CF, cpu_NF, cpu_CF, t1_32, tmp); | |
775 | ||
776 | tcg_gen_mov_i32(cpu_ZF, cpu_NF); | |
777 | tcg_gen_xor_i32(cpu_VF, cpu_NF, t0_32); | |
778 | tcg_gen_xor_i32(tmp, t0_32, t1_32); | |
779 | tcg_gen_andc_i32(cpu_VF, cpu_VF, tmp); | |
780 | tcg_gen_extu_i32_i64(dest, cpu_NF); | |
781 | ||
782 | tcg_temp_free_i32(tmp); | |
783 | tcg_temp_free_i32(t1_32); | |
784 | tcg_temp_free_i32(t0_32); | |
785 | } | |
786 | } | |
787 | ||
4a08d475 PM |
788 | /* |
789 | * Load/Store generators | |
790 | */ | |
791 | ||
792 | /* | |
60510aed | 793 | * Store from GPR register to memory. |
4a08d475 | 794 | */ |
60510aed | 795 | static void do_gpr_st_memidx(DisasContext *s, TCGv_i64 source, |
aaa1f954 EI |
796 | TCGv_i64 tcg_addr, int size, int memidx, |
797 | bool iss_valid, | |
798 | unsigned int iss_srt, | |
799 | bool iss_sf, bool iss_ar) | |
60510aed PM |
800 | { |
801 | g_assert(size <= 3); | |
aa6489da | 802 | tcg_gen_qemu_st_i64(source, tcg_addr, memidx, s->be_data + size); |
aaa1f954 EI |
803 | |
804 | if (iss_valid) { | |
805 | uint32_t syn; | |
806 | ||
807 | syn = syn_data_abort_with_iss(0, | |
808 | size, | |
809 | false, | |
810 | iss_srt, | |
811 | iss_sf, | |
812 | iss_ar, | |
813 | 0, 0, 0, 0, 0, false); | |
814 | disas_set_insn_syndrome(s, syn); | |
815 | } | |
60510aed PM |
816 | } |
817 | ||
4a08d475 | 818 | static void do_gpr_st(DisasContext *s, TCGv_i64 source, |
aaa1f954 EI |
819 | TCGv_i64 tcg_addr, int size, |
820 | bool iss_valid, | |
821 | unsigned int iss_srt, | |
822 | bool iss_sf, bool iss_ar) | |
4a08d475 | 823 | { |
aaa1f954 EI |
824 | do_gpr_st_memidx(s, source, tcg_addr, size, get_mem_index(s), |
825 | iss_valid, iss_srt, iss_sf, iss_ar); | |
4a08d475 PM |
826 | } |
827 | ||
828 | /* | |
829 | * Load from memory to GPR register | |
830 | */ | |
aaa1f954 EI |
831 | static void do_gpr_ld_memidx(DisasContext *s, |
832 | TCGv_i64 dest, TCGv_i64 tcg_addr, | |
833 | int size, bool is_signed, | |
834 | bool extend, int memidx, | |
835 | bool iss_valid, unsigned int iss_srt, | |
836 | bool iss_sf, bool iss_ar) | |
4a08d475 | 837 | { |
14776ab5 | 838 | MemOp memop = s->be_data + size; |
4a08d475 PM |
839 | |
840 | g_assert(size <= 3); | |
841 | ||
842 | if (is_signed) { | |
843 | memop += MO_SIGN; | |
844 | } | |
845 | ||
60510aed | 846 | tcg_gen_qemu_ld_i64(dest, tcg_addr, memidx, memop); |
4a08d475 PM |
847 | |
848 | if (extend && is_signed) { | |
849 | g_assert(size < 3); | |
850 | tcg_gen_ext32u_i64(dest, dest); | |
851 | } | |
aaa1f954 EI |
852 | |
853 | if (iss_valid) { | |
854 | uint32_t syn; | |
855 | ||
856 | syn = syn_data_abort_with_iss(0, | |
857 | size, | |
858 | is_signed, | |
859 | iss_srt, | |
860 | iss_sf, | |
861 | iss_ar, | |
862 | 0, 0, 0, 0, 0, false); | |
863 | disas_set_insn_syndrome(s, syn); | |
864 | } | |
4a08d475 PM |
865 | } |
866 | ||
aaa1f954 EI |
867 | static void do_gpr_ld(DisasContext *s, |
868 | TCGv_i64 dest, TCGv_i64 tcg_addr, | |
869 | int size, bool is_signed, bool extend, | |
870 | bool iss_valid, unsigned int iss_srt, | |
871 | bool iss_sf, bool iss_ar) | |
60510aed PM |
872 | { |
873 | do_gpr_ld_memidx(s, dest, tcg_addr, size, is_signed, extend, | |
aaa1f954 EI |
874 | get_mem_index(s), |
875 | iss_valid, iss_srt, iss_sf, iss_ar); | |
60510aed PM |
876 | } |
877 | ||
4a08d475 PM |
878 | /* |
879 | * Store from FP register to memory | |
880 | */ | |
881 | static void do_fp_st(DisasContext *s, int srcidx, TCGv_i64 tcg_addr, int size) | |
882 | { | |
883 | /* This writes the bottom N bits of a 128 bit wide vector to memory */ | |
4a08d475 | 884 | TCGv_i64 tmp = tcg_temp_new_i64(); |
90e49638 | 885 | tcg_gen_ld_i64(tmp, cpu_env, fp_reg_offset(s, srcidx, MO_64)); |
4a08d475 | 886 | if (size < 4) { |
aa6489da PC |
887 | tcg_gen_qemu_st_i64(tmp, tcg_addr, get_mem_index(s), |
888 | s->be_data + size); | |
4a08d475 | 889 | } else { |
aa6489da | 890 | bool be = s->be_data == MO_BE; |
4a08d475 | 891 | TCGv_i64 tcg_hiaddr = tcg_temp_new_i64(); |
aa6489da | 892 | |
4a08d475 | 893 | tcg_gen_addi_i64(tcg_hiaddr, tcg_addr, 8); |
aa6489da PC |
894 | tcg_gen_qemu_st_i64(tmp, be ? tcg_hiaddr : tcg_addr, get_mem_index(s), |
895 | s->be_data | MO_Q); | |
896 | tcg_gen_ld_i64(tmp, cpu_env, fp_reg_hi_offset(s, srcidx)); | |
897 | tcg_gen_qemu_st_i64(tmp, be ? tcg_addr : tcg_hiaddr, get_mem_index(s), | |
898 | s->be_data | MO_Q); | |
4a08d475 PM |
899 | tcg_temp_free_i64(tcg_hiaddr); |
900 | } | |
901 | ||
902 | tcg_temp_free_i64(tmp); | |
903 | } | |
904 | ||
905 | /* | |
906 | * Load from memory to FP register | |
907 | */ | |
908 | static void do_fp_ld(DisasContext *s, int destidx, TCGv_i64 tcg_addr, int size) | |
909 | { | |
910 | /* This always zero-extends and writes to a full 128 bit wide vector */ | |
4a08d475 | 911 | TCGv_i64 tmplo = tcg_temp_new_i64(); |
e1f77859 | 912 | TCGv_i64 tmphi = NULL; |
4a08d475 PM |
913 | |
914 | if (size < 4) { | |
14776ab5 | 915 | MemOp memop = s->be_data + size; |
4a08d475 PM |
916 | tcg_gen_qemu_ld_i64(tmplo, tcg_addr, get_mem_index(s), memop); |
917 | } else { | |
aa6489da | 918 | bool be = s->be_data == MO_BE; |
4a08d475 | 919 | TCGv_i64 tcg_hiaddr; |
aa6489da | 920 | |
4a08d475 PM |
921 | tmphi = tcg_temp_new_i64(); |
922 | tcg_hiaddr = tcg_temp_new_i64(); | |
923 | ||
4a08d475 | 924 | tcg_gen_addi_i64(tcg_hiaddr, tcg_addr, 8); |
aa6489da PC |
925 | tcg_gen_qemu_ld_i64(tmplo, be ? tcg_hiaddr : tcg_addr, get_mem_index(s), |
926 | s->be_data | MO_Q); | |
927 | tcg_gen_qemu_ld_i64(tmphi, be ? tcg_addr : tcg_hiaddr, get_mem_index(s), | |
928 | s->be_data | MO_Q); | |
4a08d475 PM |
929 | tcg_temp_free_i64(tcg_hiaddr); |
930 | } | |
931 | ||
90e49638 | 932 | tcg_gen_st_i64(tmplo, cpu_env, fp_reg_offset(s, destidx, MO_64)); |
4a08d475 | 933 | tcg_temp_free_i64(tmplo); |
4ff55bcb | 934 | |
e1f77859 RH |
935 | if (tmphi) { |
936 | tcg_gen_st_i64(tmphi, cpu_env, fp_reg_hi_offset(s, destidx)); | |
937 | tcg_temp_free_i64(tmphi); | |
938 | } | |
939 | clear_vec_high(s, tmphi != NULL, destidx); | |
4a08d475 PM |
940 | } |
941 | ||
72430bf5 AB |
942 | /* |
943 | * Vector load/store helpers. | |
944 | * | |
945 | * The principal difference between this and a FP load is that we don't | |
946 | * zero extend as we are filling a partial chunk of the vector register. | |
947 | * These functions don't support 128 bit loads/stores, which would be | |
948 | * normal load/store operations. | |
a08582f4 PM |
949 | * |
950 | * The _i32 versions are useful when operating on 32 bit quantities | |
951 | * (eg for floating point single or using Neon helper functions). | |
72430bf5 AB |
952 | */ |
953 | ||
954 | /* Get value of an element within a vector register */ | |
955 | static void read_vec_element(DisasContext *s, TCGv_i64 tcg_dest, int srcidx, | |
14776ab5 | 956 | int element, MemOp memop) |
72430bf5 | 957 | { |
90e49638 | 958 | int vect_off = vec_reg_offset(s, srcidx, element, memop & MO_SIZE); |
72430bf5 AB |
959 | switch (memop) { |
960 | case MO_8: | |
961 | tcg_gen_ld8u_i64(tcg_dest, cpu_env, vect_off); | |
962 | break; | |
963 | case MO_16: | |
964 | tcg_gen_ld16u_i64(tcg_dest, cpu_env, vect_off); | |
965 | break; | |
966 | case MO_32: | |
967 | tcg_gen_ld32u_i64(tcg_dest, cpu_env, vect_off); | |
968 | break; | |
969 | case MO_8|MO_SIGN: | |
970 | tcg_gen_ld8s_i64(tcg_dest, cpu_env, vect_off); | |
971 | break; | |
972 | case MO_16|MO_SIGN: | |
973 | tcg_gen_ld16s_i64(tcg_dest, cpu_env, vect_off); | |
974 | break; | |
975 | case MO_32|MO_SIGN: | |
976 | tcg_gen_ld32s_i64(tcg_dest, cpu_env, vect_off); | |
977 | break; | |
978 | case MO_64: | |
979 | case MO_64|MO_SIGN: | |
980 | tcg_gen_ld_i64(tcg_dest, cpu_env, vect_off); | |
981 | break; | |
982 | default: | |
983 | g_assert_not_reached(); | |
984 | } | |
985 | } | |
986 | ||
a08582f4 | 987 | static void read_vec_element_i32(DisasContext *s, TCGv_i32 tcg_dest, int srcidx, |
14776ab5 | 988 | int element, MemOp memop) |
a08582f4 | 989 | { |
90e49638 | 990 | int vect_off = vec_reg_offset(s, srcidx, element, memop & MO_SIZE); |
a08582f4 PM |
991 | switch (memop) { |
992 | case MO_8: | |
993 | tcg_gen_ld8u_i32(tcg_dest, cpu_env, vect_off); | |
994 | break; | |
995 | case MO_16: | |
996 | tcg_gen_ld16u_i32(tcg_dest, cpu_env, vect_off); | |
997 | break; | |
998 | case MO_8|MO_SIGN: | |
999 | tcg_gen_ld8s_i32(tcg_dest, cpu_env, vect_off); | |
1000 | break; | |
1001 | case MO_16|MO_SIGN: | |
1002 | tcg_gen_ld16s_i32(tcg_dest, cpu_env, vect_off); | |
1003 | break; | |
1004 | case MO_32: | |
1005 | case MO_32|MO_SIGN: | |
1006 | tcg_gen_ld_i32(tcg_dest, cpu_env, vect_off); | |
1007 | break; | |
1008 | default: | |
1009 | g_assert_not_reached(); | |
1010 | } | |
1011 | } | |
1012 | ||
72430bf5 AB |
1013 | /* Set value of an element within a vector register */ |
1014 | static void write_vec_element(DisasContext *s, TCGv_i64 tcg_src, int destidx, | |
14776ab5 | 1015 | int element, MemOp memop) |
72430bf5 | 1016 | { |
90e49638 | 1017 | int vect_off = vec_reg_offset(s, destidx, element, memop & MO_SIZE); |
72430bf5 AB |
1018 | switch (memop) { |
1019 | case MO_8: | |
1020 | tcg_gen_st8_i64(tcg_src, cpu_env, vect_off); | |
1021 | break; | |
1022 | case MO_16: | |
1023 | tcg_gen_st16_i64(tcg_src, cpu_env, vect_off); | |
1024 | break; | |
1025 | case MO_32: | |
1026 | tcg_gen_st32_i64(tcg_src, cpu_env, vect_off); | |
1027 | break; | |
1028 | case MO_64: | |
1029 | tcg_gen_st_i64(tcg_src, cpu_env, vect_off); | |
1030 | break; | |
1031 | default: | |
1032 | g_assert_not_reached(); | |
1033 | } | |
1034 | } | |
1035 | ||
1f8a73af | 1036 | static void write_vec_element_i32(DisasContext *s, TCGv_i32 tcg_src, |
14776ab5 | 1037 | int destidx, int element, MemOp memop) |
1f8a73af | 1038 | { |
90e49638 | 1039 | int vect_off = vec_reg_offset(s, destidx, element, memop & MO_SIZE); |
1f8a73af PM |
1040 | switch (memop) { |
1041 | case MO_8: | |
1042 | tcg_gen_st8_i32(tcg_src, cpu_env, vect_off); | |
1043 | break; | |
1044 | case MO_16: | |
1045 | tcg_gen_st16_i32(tcg_src, cpu_env, vect_off); | |
1046 | break; | |
1047 | case MO_32: | |
1048 | tcg_gen_st_i32(tcg_src, cpu_env, vect_off); | |
1049 | break; | |
1050 | default: | |
1051 | g_assert_not_reached(); | |
1052 | } | |
1053 | } | |
1054 | ||
72430bf5 AB |
1055 | /* Store from vector register to memory */ |
1056 | static void do_vec_st(DisasContext *s, int srcidx, int element, | |
14776ab5 | 1057 | TCGv_i64 tcg_addr, int size, MemOp endian) |
72430bf5 | 1058 | { |
72430bf5 AB |
1059 | TCGv_i64 tcg_tmp = tcg_temp_new_i64(); |
1060 | ||
1061 | read_vec_element(s, tcg_tmp, srcidx, element, size); | |
87f9a7f0 | 1062 | tcg_gen_qemu_st_i64(tcg_tmp, tcg_addr, get_mem_index(s), endian | size); |
72430bf5 AB |
1063 | |
1064 | tcg_temp_free_i64(tcg_tmp); | |
1065 | } | |
1066 | ||
1067 | /* Load from memory to vector register */ | |
1068 | static void do_vec_ld(DisasContext *s, int destidx, int element, | |
14776ab5 | 1069 | TCGv_i64 tcg_addr, int size, MemOp endian) |
72430bf5 | 1070 | { |
72430bf5 AB |
1071 | TCGv_i64 tcg_tmp = tcg_temp_new_i64(); |
1072 | ||
87f9a7f0 | 1073 | tcg_gen_qemu_ld_i64(tcg_tmp, tcg_addr, get_mem_index(s), endian | size); |
72430bf5 AB |
1074 | write_vec_element(s, tcg_tmp, destidx, element, size); |
1075 | ||
1076 | tcg_temp_free_i64(tcg_tmp); | |
1077 | } | |
1078 | ||
8c6afa6a PM |
1079 | /* Check that FP/Neon access is enabled. If it is, return |
1080 | * true. If not, emit code to generate an appropriate exception, | |
1081 | * and return false; the caller should not emit any code for | |
1082 | * the instruction. Note that this check must happen after all | |
1083 | * unallocated-encoding checks (otherwise the syndrome information | |
1084 | * for the resulting exception will be incorrect). | |
1085 | */ | |
1086 | static inline bool fp_access_check(DisasContext *s) | |
1087 | { | |
90e49638 PM |
1088 | assert(!s->fp_access_checked); |
1089 | s->fp_access_checked = true; | |
1090 | ||
9dbbc748 | 1091 | if (!s->fp_excp_el) { |
8c6afa6a PM |
1092 | return true; |
1093 | } | |
1094 | ||
a767fac8 RH |
1095 | gen_exception_insn(s, s->pc_curr, EXCP_UDEF, |
1096 | syn_fp_access_trap(1, 0xe, false), s->fp_excp_el); | |
8c6afa6a PM |
1097 | return false; |
1098 | } | |
1099 | ||
490aa7f1 RH |
1100 | /* Check that SVE access is enabled. If it is, return true. |
1101 | * If not, emit code to generate an appropriate exception and return false. | |
1102 | */ | |
8c71baed | 1103 | bool sve_access_check(DisasContext *s) |
490aa7f1 RH |
1104 | { |
1105 | if (s->sve_excp_el) { | |
a767fac8 | 1106 | gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_sve_access_trap(), |
490aa7f1 RH |
1107 | s->sve_excp_el); |
1108 | return false; | |
1109 | } | |
8c71baed | 1110 | return fp_access_check(s); |
490aa7f1 RH |
1111 | } |
1112 | ||
229b7a05 AB |
1113 | /* |
1114 | * This utility function is for doing register extension with an | |
1115 | * optional shift. You will likely want to pass a temporary for the | |
1116 | * destination register. See DecodeRegExtend() in the ARM ARM. | |
1117 | */ | |
1118 | static void ext_and_shift_reg(TCGv_i64 tcg_out, TCGv_i64 tcg_in, | |
1119 | int option, unsigned int shift) | |
1120 | { | |
1121 | int extsize = extract32(option, 0, 2); | |
1122 | bool is_signed = extract32(option, 2, 1); | |
1123 | ||
1124 | if (is_signed) { | |
1125 | switch (extsize) { | |
1126 | case 0: | |
1127 | tcg_gen_ext8s_i64(tcg_out, tcg_in); | |
1128 | break; | |
1129 | case 1: | |
1130 | tcg_gen_ext16s_i64(tcg_out, tcg_in); | |
1131 | break; | |
1132 | case 2: | |
1133 | tcg_gen_ext32s_i64(tcg_out, tcg_in); | |
1134 | break; | |
1135 | case 3: | |
1136 | tcg_gen_mov_i64(tcg_out, tcg_in); | |
1137 | break; | |
1138 | } | |
1139 | } else { | |
1140 | switch (extsize) { | |
1141 | case 0: | |
1142 | tcg_gen_ext8u_i64(tcg_out, tcg_in); | |
1143 | break; | |
1144 | case 1: | |
1145 | tcg_gen_ext16u_i64(tcg_out, tcg_in); | |
1146 | break; | |
1147 | case 2: | |
1148 | tcg_gen_ext32u_i64(tcg_out, tcg_in); | |
1149 | break; | |
1150 | case 3: | |
1151 | tcg_gen_mov_i64(tcg_out, tcg_in); | |
1152 | break; | |
1153 | } | |
1154 | } | |
1155 | ||
1156 | if (shift) { | |
1157 | tcg_gen_shli_i64(tcg_out, tcg_out, shift); | |
1158 | } | |
1159 | } | |
1160 | ||
4a08d475 PM |
1161 | static inline void gen_check_sp_alignment(DisasContext *s) |
1162 | { | |
1163 | /* The AArch64 architecture mandates that (if enabled via PSTATE | |
1164 | * or SCTLR bits) there is a check that SP is 16-aligned on every | |
1165 | * SP-relative load or store (with an exception generated if it is not). | |
1166 | * In line with general QEMU practice regarding misaligned accesses, | |
1167 | * we omit these checks for the sake of guest program performance. | |
1168 | * This function is provided as a hook so we can more easily add these | |
1169 | * checks in future (possibly as a "favour catching guest program bugs | |
1170 | * over speed" user selectable option). | |
1171 | */ | |
1172 | } | |
1173 | ||
384b26fb AB |
1174 | /* |
1175 | * This provides a simple table based table lookup decoder. It is | |
1176 | * intended to be used when the relevant bits for decode are too | |
1177 | * awkwardly placed and switch/if based logic would be confusing and | |
1178 | * deeply nested. Since it's a linear search through the table, tables | |
1179 | * should be kept small. | |
1180 | * | |
1181 | * It returns the first handler where insn & mask == pattern, or | |
1182 | * NULL if there is no match. | |
1183 | * The table is terminated by an empty mask (i.e. 0) | |
1184 | */ | |
1185 | static inline AArch64DecodeFn *lookup_disas_fn(const AArch64DecodeTable *table, | |
1186 | uint32_t insn) | |
1187 | { | |
1188 | const AArch64DecodeTable *tptr = table; | |
1189 | ||
1190 | while (tptr->mask) { | |
1191 | if ((insn & tptr->mask) == tptr->pattern) { | |
1192 | return tptr->disas_fn; | |
1193 | } | |
1194 | tptr++; | |
1195 | } | |
1196 | return NULL; | |
1197 | } | |
1198 | ||
ad7ee8a2 | 1199 | /* |
4ce31af4 PM |
1200 | * The instruction disassembly implemented here matches |
1201 | * the instruction encoding classifications in chapter C4 | |
1202 | * of the ARM Architecture Reference Manual (DDI0487B_a); | |
1203 | * classification names and decode diagrams here should generally | |
1204 | * match up with those in the manual. | |
ad7ee8a2 CF |
1205 | */ |
1206 | ||
4ce31af4 | 1207 | /* Unconditional branch (immediate) |
11e169de AG |
1208 | * 31 30 26 25 0 |
1209 | * +----+-----------+-------------------------------------+ | |
1210 | * | op | 0 0 1 0 1 | imm26 | | |
1211 | * +----+-----------+-------------------------------------+ | |
1212 | */ | |
ad7ee8a2 CF |
1213 | static void disas_uncond_b_imm(DisasContext *s, uint32_t insn) |
1214 | { | |
43722a6d | 1215 | uint64_t addr = s->pc_curr + sextract32(insn, 0, 26) * 4; |
11e169de | 1216 | |
1743d55c | 1217 | if (insn & (1U << 31)) { |
4ce31af4 | 1218 | /* BL Branch with link */ |
a0415916 | 1219 | tcg_gen_movi_i64(cpu_reg(s, 30), s->base.pc_next); |
11e169de AG |
1220 | } |
1221 | ||
4ce31af4 | 1222 | /* B Branch / BL Branch with link */ |
35862270 | 1223 | reset_btype(s); |
11e169de | 1224 | gen_goto_tb(s, 0, addr); |
ad7ee8a2 CF |
1225 | } |
1226 | ||
4ce31af4 | 1227 | /* Compare and branch (immediate) |
60e53388 AG |
1228 | * 31 30 25 24 23 5 4 0 |
1229 | * +----+-------------+----+---------------------+--------+ | |
1230 | * | sf | 0 1 1 0 1 0 | op | imm19 | Rt | | |
1231 | * +----+-------------+----+---------------------+--------+ | |
1232 | */ | |
ad7ee8a2 CF |
1233 | static void disas_comp_b_imm(DisasContext *s, uint32_t insn) |
1234 | { | |
60e53388 AG |
1235 | unsigned int sf, op, rt; |
1236 | uint64_t addr; | |
42a268c2 | 1237 | TCGLabel *label_match; |
60e53388 AG |
1238 | TCGv_i64 tcg_cmp; |
1239 | ||
1240 | sf = extract32(insn, 31, 1); | |
1241 | op = extract32(insn, 24, 1); /* 0: CBZ; 1: CBNZ */ | |
1242 | rt = extract32(insn, 0, 5); | |
43722a6d | 1243 | addr = s->pc_curr + sextract32(insn, 5, 19) * 4; |
60e53388 AG |
1244 | |
1245 | tcg_cmp = read_cpu_reg(s, rt, sf); | |
1246 | label_match = gen_new_label(); | |
1247 | ||
35862270 | 1248 | reset_btype(s); |
60e53388 AG |
1249 | tcg_gen_brcondi_i64(op ? TCG_COND_NE : TCG_COND_EQ, |
1250 | tcg_cmp, 0, label_match); | |
1251 | ||
a0415916 | 1252 | gen_goto_tb(s, 0, s->base.pc_next); |
60e53388 AG |
1253 | gen_set_label(label_match); |
1254 | gen_goto_tb(s, 1, addr); | |
ad7ee8a2 CF |
1255 | } |
1256 | ||
4ce31af4 | 1257 | /* Test and branch (immediate) |
db0f7958 AG |
1258 | * 31 30 25 24 23 19 18 5 4 0 |
1259 | * +----+-------------+----+-------+-------------+------+ | |
1260 | * | b5 | 0 1 1 0 1 1 | op | b40 | imm14 | Rt | | |
1261 | * +----+-------------+----+-------+-------------+------+ | |
1262 | */ | |
ad7ee8a2 CF |
1263 | static void disas_test_b_imm(DisasContext *s, uint32_t insn) |
1264 | { | |
db0f7958 AG |
1265 | unsigned int bit_pos, op, rt; |
1266 | uint64_t addr; | |
42a268c2 | 1267 | TCGLabel *label_match; |
db0f7958 AG |
1268 | TCGv_i64 tcg_cmp; |
1269 | ||
1270 | bit_pos = (extract32(insn, 31, 1) << 5) | extract32(insn, 19, 5); | |
1271 | op = extract32(insn, 24, 1); /* 0: TBZ; 1: TBNZ */ | |
43722a6d | 1272 | addr = s->pc_curr + sextract32(insn, 5, 14) * 4; |
db0f7958 AG |
1273 | rt = extract32(insn, 0, 5); |
1274 | ||
1275 | tcg_cmp = tcg_temp_new_i64(); | |
1276 | tcg_gen_andi_i64(tcg_cmp, cpu_reg(s, rt), (1ULL << bit_pos)); | |
1277 | label_match = gen_new_label(); | |
35862270 RH |
1278 | |
1279 | reset_btype(s); | |
db0f7958 AG |
1280 | tcg_gen_brcondi_i64(op ? TCG_COND_NE : TCG_COND_EQ, |
1281 | tcg_cmp, 0, label_match); | |
1282 | tcg_temp_free_i64(tcg_cmp); | |
a0415916 | 1283 | gen_goto_tb(s, 0, s->base.pc_next); |
db0f7958 AG |
1284 | gen_set_label(label_match); |
1285 | gen_goto_tb(s, 1, addr); | |
ad7ee8a2 CF |
1286 | } |
1287 | ||
4ce31af4 | 1288 | /* Conditional branch (immediate) |
39fb730a AG |
1289 | * 31 25 24 23 5 4 3 0 |
1290 | * +---------------+----+---------------------+----+------+ | |
1291 | * | 0 1 0 1 0 1 0 | o1 | imm19 | o0 | cond | | |
1292 | * +---------------+----+---------------------+----+------+ | |
1293 | */ | |
ad7ee8a2 CF |
1294 | static void disas_cond_b_imm(DisasContext *s, uint32_t insn) |
1295 | { | |
39fb730a AG |
1296 | unsigned int cond; |
1297 | uint64_t addr; | |
1298 | ||
1299 | if ((insn & (1 << 4)) || (insn & (1 << 24))) { | |
1300 | unallocated_encoding(s); | |
1301 | return; | |
1302 | } | |
43722a6d | 1303 | addr = s->pc_curr + sextract32(insn, 5, 19) * 4; |
39fb730a AG |
1304 | cond = extract32(insn, 0, 4); |
1305 | ||
35862270 | 1306 | reset_btype(s); |
39fb730a AG |
1307 | if (cond < 0x0e) { |
1308 | /* genuinely conditional branches */ | |
42a268c2 | 1309 | TCGLabel *label_match = gen_new_label(); |
39fb730a | 1310 | arm_gen_test_cc(cond, label_match); |
a0415916 | 1311 | gen_goto_tb(s, 0, s->base.pc_next); |
39fb730a AG |
1312 | gen_set_label(label_match); |
1313 | gen_goto_tb(s, 1, addr); | |
1314 | } else { | |
1315 | /* 0xe and 0xf are both "always" conditions */ | |
1316 | gen_goto_tb(s, 0, addr); | |
1317 | } | |
ad7ee8a2 CF |
1318 | } |
1319 | ||
4ce31af4 | 1320 | /* HINT instruction group, including various allocated HINTs */ |
87462e0f CF |
1321 | static void handle_hint(DisasContext *s, uint32_t insn, |
1322 | unsigned int op1, unsigned int op2, unsigned int crm) | |
1323 | { | |
1324 | unsigned int selector = crm << 3 | op2; | |
1325 | ||
1326 | if (op1 != 3) { | |
1327 | unallocated_encoding(s); | |
1328 | return; | |
1329 | } | |
1330 | ||
1331 | switch (selector) { | |
7c94c834 RH |
1332 | case 0b00000: /* NOP */ |
1333 | break; | |
1334 | case 0b00011: /* WFI */ | |
dcba3a8d | 1335 | s->base.is_jmp = DISAS_WFI; |
7c94c834 RH |
1336 | break; |
1337 | case 0b00001: /* YIELD */ | |
2399d4e7 EC |
1338 | /* When running in MTTCG we don't generate jumps to the yield and |
1339 | * WFE helpers as it won't affect the scheduling of other vCPUs. | |
1340 | * If we wanted to more completely model WFE/SEV so we don't busy | |
1341 | * spin unnecessarily we would need to do something more involved. | |
1342 | */ | |
2399d4e7 | 1343 | if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) { |
dcba3a8d | 1344 | s->base.is_jmp = DISAS_YIELD; |
c22edfeb | 1345 | } |
7c94c834 RH |
1346 | break; |
1347 | case 0b00010: /* WFE */ | |
2399d4e7 | 1348 | if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) { |
dcba3a8d | 1349 | s->base.is_jmp = DISAS_WFE; |
c22edfeb | 1350 | } |
7c94c834 RH |
1351 | break; |
1352 | case 0b00100: /* SEV */ | |
1353 | case 0b00101: /* SEVL */ | |
87462e0f | 1354 | /* we treat all as NOP at least for now */ |
7c94c834 RH |
1355 | break; |
1356 | case 0b00111: /* XPACLRI */ | |
1357 | if (s->pauth_active) { | |
1358 | gen_helper_xpaci(cpu_X[30], cpu_env, cpu_X[30]); | |
1359 | } | |
1360 | break; | |
1361 | case 0b01000: /* PACIA1716 */ | |
1362 | if (s->pauth_active) { | |
1363 | gen_helper_pacia(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]); | |
1364 | } | |
1365 | break; | |
1366 | case 0b01010: /* PACIB1716 */ | |
1367 | if (s->pauth_active) { | |
1368 | gen_helper_pacib(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]); | |
1369 | } | |
1370 | break; | |
1371 | case 0b01100: /* AUTIA1716 */ | |
1372 | if (s->pauth_active) { | |
1373 | gen_helper_autia(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]); | |
1374 | } | |
1375 | break; | |
1376 | case 0b01110: /* AUTIB1716 */ | |
1377 | if (s->pauth_active) { | |
1378 | gen_helper_autib(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]); | |
1379 | } | |
1380 | break; | |
1381 | case 0b11000: /* PACIAZ */ | |
1382 | if (s->pauth_active) { | |
1383 | gen_helper_pacia(cpu_X[30], cpu_env, cpu_X[30], | |
1384 | new_tmp_a64_zero(s)); | |
1385 | } | |
1386 | break; | |
1387 | case 0b11001: /* PACIASP */ | |
1388 | if (s->pauth_active) { | |
1389 | gen_helper_pacia(cpu_X[30], cpu_env, cpu_X[30], cpu_X[31]); | |
1390 | } | |
1391 | break; | |
1392 | case 0b11010: /* PACIBZ */ | |
1393 | if (s->pauth_active) { | |
1394 | gen_helper_pacib(cpu_X[30], cpu_env, cpu_X[30], | |
1395 | new_tmp_a64_zero(s)); | |
1396 | } | |
1397 | break; | |
1398 | case 0b11011: /* PACIBSP */ | |
1399 | if (s->pauth_active) { | |
1400 | gen_helper_pacib(cpu_X[30], cpu_env, cpu_X[30], cpu_X[31]); | |
1401 | } | |
1402 | break; | |
1403 | case 0b11100: /* AUTIAZ */ | |
1404 | if (s->pauth_active) { | |
1405 | gen_helper_autia(cpu_X[30], cpu_env, cpu_X[30], | |
1406 | new_tmp_a64_zero(s)); | |
1407 | } | |
1408 | break; | |
1409 | case 0b11101: /* AUTIASP */ | |
1410 | if (s->pauth_active) { | |
1411 | gen_helper_autia(cpu_X[30], cpu_env, cpu_X[30], cpu_X[31]); | |
1412 | } | |
1413 | break; | |
1414 | case 0b11110: /* AUTIBZ */ | |
1415 | if (s->pauth_active) { | |
1416 | gen_helper_autib(cpu_X[30], cpu_env, cpu_X[30], | |
1417 | new_tmp_a64_zero(s)); | |
1418 | } | |
1419 | break; | |
1420 | case 0b11111: /* AUTIBSP */ | |
1421 | if (s->pauth_active) { | |
1422 | gen_helper_autib(cpu_X[30], cpu_env, cpu_X[30], cpu_X[31]); | |
1423 | } | |
1424 | break; | |
87462e0f CF |
1425 | default: |
1426 | /* default specified as NOP equivalent */ | |
7c94c834 | 1427 | break; |
87462e0f CF |
1428 | } |
1429 | } | |
1430 | ||
fa2ef212 MM |
1431 | static void gen_clrex(DisasContext *s, uint32_t insn) |
1432 | { | |
1433 | tcg_gen_movi_i64(cpu_exclusive_addr, -1); | |
1434 | } | |
1435 | ||
87462e0f CF |
1436 | /* CLREX, DSB, DMB, ISB */ |
1437 | static void handle_sync(DisasContext *s, uint32_t insn, | |
1438 | unsigned int op1, unsigned int op2, unsigned int crm) | |
1439 | { | |
ce1bd93f PK |
1440 | TCGBar bar; |
1441 | ||
87462e0f CF |
1442 | if (op1 != 3) { |
1443 | unallocated_encoding(s); | |
1444 | return; | |
1445 | } | |
1446 | ||
1447 | switch (op2) { | |
1448 | case 2: /* CLREX */ | |
fa2ef212 | 1449 | gen_clrex(s, insn); |
87462e0f CF |
1450 | return; |
1451 | case 4: /* DSB */ | |
1452 | case 5: /* DMB */ | |
ce1bd93f PK |
1453 | switch (crm & 3) { |
1454 | case 1: /* MBReqTypes_Reads */ | |
1455 | bar = TCG_BAR_SC | TCG_MO_LD_LD | TCG_MO_LD_ST; | |
1456 | break; | |
1457 | case 2: /* MBReqTypes_Writes */ | |
1458 | bar = TCG_BAR_SC | TCG_MO_ST_ST; | |
1459 | break; | |
1460 | default: /* MBReqTypes_All */ | |
1461 | bar = TCG_BAR_SC | TCG_MO_ALL; | |
1462 | break; | |
1463 | } | |
1464 | tcg_gen_mb(bar); | |
87462e0f | 1465 | return; |
6df99dec SS |
1466 | case 6: /* ISB */ |
1467 | /* We need to break the TB after this insn to execute | |
1468 | * a self-modified code correctly and also to take | |
1469 | * any pending interrupts immediately. | |
1470 | */ | |
35862270 | 1471 | reset_btype(s); |
a0415916 | 1472 | gen_goto_tb(s, 0, s->base.pc_next); |
6df99dec | 1473 | return; |
9888bd1e RH |
1474 | |
1475 | case 7: /* SB */ | |
1476 | if (crm != 0 || !dc_isar_feature(aa64_sb, s)) { | |
1477 | goto do_unallocated; | |
1478 | } | |
1479 | /* | |
1480 | * TODO: There is no speculation barrier opcode for TCG; | |
1481 | * MB and end the TB instead. | |
1482 | */ | |
1483 | tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); | |
a0415916 | 1484 | gen_goto_tb(s, 0, s->base.pc_next); |
9888bd1e RH |
1485 | return; |
1486 | ||
87462e0f | 1487 | default: |
9888bd1e | 1488 | do_unallocated: |
87462e0f CF |
1489 | unallocated_encoding(s); |
1490 | return; | |
1491 | } | |
1492 | } | |
1493 | ||
5ef84f11 RH |
1494 | static void gen_xaflag(void) |
1495 | { | |
1496 | TCGv_i32 z = tcg_temp_new_i32(); | |
1497 | ||
1498 | tcg_gen_setcondi_i32(TCG_COND_EQ, z, cpu_ZF, 0); | |
1499 | ||
1500 | /* | |
1501 | * (!C & !Z) << 31 | |
1502 | * (!(C | Z)) << 31 | |
1503 | * ~((C | Z) << 31) | |
1504 | * ~-(C | Z) | |
1505 | * (C | Z) - 1 | |
1506 | */ | |
1507 | tcg_gen_or_i32(cpu_NF, cpu_CF, z); | |
1508 | tcg_gen_subi_i32(cpu_NF, cpu_NF, 1); | |
1509 | ||
1510 | /* !(Z & C) */ | |
1511 | tcg_gen_and_i32(cpu_ZF, z, cpu_CF); | |
1512 | tcg_gen_xori_i32(cpu_ZF, cpu_ZF, 1); | |
1513 | ||
1514 | /* (!C & Z) << 31 -> -(Z & ~C) */ | |
1515 | tcg_gen_andc_i32(cpu_VF, z, cpu_CF); | |
1516 | tcg_gen_neg_i32(cpu_VF, cpu_VF); | |
1517 | ||
1518 | /* C | Z */ | |
1519 | tcg_gen_or_i32(cpu_CF, cpu_CF, z); | |
1520 | ||
1521 | tcg_temp_free_i32(z); | |
1522 | } | |
1523 | ||
1524 | static void gen_axflag(void) | |
1525 | { | |
1526 | tcg_gen_sari_i32(cpu_VF, cpu_VF, 31); /* V ? -1 : 0 */ | |
1527 | tcg_gen_andc_i32(cpu_CF, cpu_CF, cpu_VF); /* C & !V */ | |
1528 | ||
1529 | /* !(Z | V) -> !(!ZF | V) -> ZF & !V -> ZF & ~VF */ | |
1530 | tcg_gen_andc_i32(cpu_ZF, cpu_ZF, cpu_VF); | |
1531 | ||
1532 | tcg_gen_movi_i32(cpu_NF, 0); | |
1533 | tcg_gen_movi_i32(cpu_VF, 0); | |
1534 | } | |
1535 | ||
4ce31af4 | 1536 | /* MSR (immediate) - move immediate to processor state field */ |
87462e0f CF |
1537 | static void handle_msr_i(DisasContext *s, uint32_t insn, |
1538 | unsigned int op1, unsigned int op2, unsigned int crm) | |
1539 | { | |
ff730e96 | 1540 | TCGv_i32 t1; |
9cfa0b4e | 1541 | int op = op1 << 3 | op2; |
ff730e96 RH |
1542 | |
1543 | /* End the TB by default, chaining is ok. */ | |
1544 | s->base.is_jmp = DISAS_TOO_MANY; | |
1545 | ||
9cfa0b4e | 1546 | switch (op) { |
b89d9c98 RH |
1547 | case 0x00: /* CFINV */ |
1548 | if (crm != 0 || !dc_isar_feature(aa64_condm_4, s)) { | |
1549 | goto do_unallocated; | |
1550 | } | |
1551 | tcg_gen_xori_i32(cpu_CF, cpu_CF, 1); | |
1552 | s->base.is_jmp = DISAS_NEXT; | |
1553 | break; | |
1554 | ||
5ef84f11 RH |
1555 | case 0x01: /* XAFlag */ |
1556 | if (crm != 0 || !dc_isar_feature(aa64_condm_5, s)) { | |
1557 | goto do_unallocated; | |
1558 | } | |
1559 | gen_xaflag(); | |
1560 | s->base.is_jmp = DISAS_NEXT; | |
1561 | break; | |
1562 | ||
1563 | case 0x02: /* AXFlag */ | |
1564 | if (crm != 0 || !dc_isar_feature(aa64_condm_5, s)) { | |
1565 | goto do_unallocated; | |
1566 | } | |
1567 | gen_axflag(); | |
1568 | s->base.is_jmp = DISAS_NEXT; | |
1569 | break; | |
1570 | ||
9eeb7a1c RH |
1571 | case 0x03: /* UAO */ |
1572 | if (!dc_isar_feature(aa64_uao, s) || s->current_el == 0) { | |
1573 | goto do_unallocated; | |
1574 | } | |
1575 | if (crm & 1) { | |
1576 | set_pstate_bits(PSTATE_UAO); | |
1577 | } else { | |
1578 | clear_pstate_bits(PSTATE_UAO); | |
1579 | } | |
1580 | t1 = tcg_const_i32(s->current_el); | |
1581 | gen_helper_rebuild_hflags_a64(cpu_env, t1); | |
1582 | tcg_temp_free_i32(t1); | |
1583 | break; | |
1584 | ||
220f508f RH |
1585 | case 0x04: /* PAN */ |
1586 | if (!dc_isar_feature(aa64_pan, s) || s->current_el == 0) { | |
1587 | goto do_unallocated; | |
1588 | } | |
1589 | if (crm & 1) { | |
1590 | set_pstate_bits(PSTATE_PAN); | |
1591 | } else { | |
1592 | clear_pstate_bits(PSTATE_PAN); | |
1593 | } | |
1594 | t1 = tcg_const_i32(s->current_el); | |
1595 | gen_helper_rebuild_hflags_a64(cpu_env, t1); | |
1596 | tcg_temp_free_i32(t1); | |
1597 | break; | |
1598 | ||
9cfa0b4e | 1599 | case 0x05: /* SPSel */ |
dcbff19b | 1600 | if (s->current_el == 0) { |
ff730e96 | 1601 | goto do_unallocated; |
9cfa0b4e | 1602 | } |
ff730e96 RH |
1603 | t1 = tcg_const_i32(crm & PSTATE_SP); |
1604 | gen_helper_msr_i_spsel(cpu_env, t1); | |
1605 | tcg_temp_free_i32(t1); | |
1606 | break; | |
1607 | ||
9cfa0b4e | 1608 | case 0x1e: /* DAIFSet */ |
ff730e96 RH |
1609 | t1 = tcg_const_i32(crm); |
1610 | gen_helper_msr_i_daifset(cpu_env, t1); | |
1611 | tcg_temp_free_i32(t1); | |
1612 | break; | |
1613 | ||
9cfa0b4e | 1614 | case 0x1f: /* DAIFClear */ |
ff730e96 RH |
1615 | t1 = tcg_const_i32(crm); |
1616 | gen_helper_msr_i_daifclear(cpu_env, t1); | |
1617 | tcg_temp_free_i32(t1); | |
8da54b25 | 1618 | /* For DAIFClear, exit the cpu loop to re-evaluate pending IRQs. */ |
ff730e96 | 1619 | s->base.is_jmp = DISAS_UPDATE; |
9cfa0b4e | 1620 | break; |
ff730e96 | 1621 | |
9cfa0b4e | 1622 | default: |
ff730e96 | 1623 | do_unallocated: |
9cfa0b4e PM |
1624 | unallocated_encoding(s); |
1625 | return; | |
1626 | } | |
87462e0f CF |
1627 | } |
1628 | ||
b0d2b7d0 PM |
1629 | static void gen_get_nzcv(TCGv_i64 tcg_rt) |
1630 | { | |
1631 | TCGv_i32 tmp = tcg_temp_new_i32(); | |
1632 | TCGv_i32 nzcv = tcg_temp_new_i32(); | |
1633 | ||
1634 | /* build bit 31, N */ | |
1743d55c | 1635 | tcg_gen_andi_i32(nzcv, cpu_NF, (1U << 31)); |
b0d2b7d0 PM |
1636 | /* build bit 30, Z */ |
1637 | tcg_gen_setcondi_i32(TCG_COND_EQ, tmp, cpu_ZF, 0); | |
1638 | tcg_gen_deposit_i32(nzcv, nzcv, tmp, 30, 1); | |
1639 | /* build bit 29, C */ | |
1640 | tcg_gen_deposit_i32(nzcv, nzcv, cpu_CF, 29, 1); | |
1641 | /* build bit 28, V */ | |
1642 | tcg_gen_shri_i32(tmp, cpu_VF, 31); | |
1643 | tcg_gen_deposit_i32(nzcv, nzcv, tmp, 28, 1); | |
1644 | /* generate result */ | |
1645 | tcg_gen_extu_i32_i64(tcg_rt, nzcv); | |
1646 | ||
1647 | tcg_temp_free_i32(nzcv); | |
1648 | tcg_temp_free_i32(tmp); | |
1649 | } | |
1650 | ||
1651 | static void gen_set_nzcv(TCGv_i64 tcg_rt) | |
b0d2b7d0 PM |
1652 | { |
1653 | TCGv_i32 nzcv = tcg_temp_new_i32(); | |
1654 | ||
1655 | /* take NZCV from R[t] */ | |
ecc7b3aa | 1656 | tcg_gen_extrl_i64_i32(nzcv, tcg_rt); |
b0d2b7d0 PM |
1657 | |
1658 | /* bit 31, N */ | |
1743d55c | 1659 | tcg_gen_andi_i32(cpu_NF, nzcv, (1U << 31)); |
b0d2b7d0 PM |
1660 | /* bit 30, Z */ |
1661 | tcg_gen_andi_i32(cpu_ZF, nzcv, (1 << 30)); | |
1662 | tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_ZF, cpu_ZF, 0); | |
1663 | /* bit 29, C */ | |
1664 | tcg_gen_andi_i32(cpu_CF, nzcv, (1 << 29)); | |
1665 | tcg_gen_shri_i32(cpu_CF, cpu_CF, 29); | |
1666 | /* bit 28, V */ | |
1667 | tcg_gen_andi_i32(cpu_VF, nzcv, (1 << 28)); | |
1668 | tcg_gen_shli_i32(cpu_VF, cpu_VF, 3); | |
1669 | tcg_temp_free_i32(nzcv); | |
1670 | } | |
1671 | ||
4ce31af4 PM |
1672 | /* MRS - move from system register |
1673 | * MSR (register) - move to system register | |
1674 | * SYS | |
1675 | * SYSL | |
fea50522 PM |
1676 | * These are all essentially the same insn in 'read' and 'write' |
1677 | * versions, with varying op0 fields. | |
1678 | */ | |
1679 | static void handle_sys(DisasContext *s, uint32_t insn, bool isread, | |
1680 | unsigned int op0, unsigned int op1, unsigned int op2, | |
87462e0f CF |
1681 | unsigned int crn, unsigned int crm, unsigned int rt) |
1682 | { | |
fea50522 PM |
1683 | const ARMCPRegInfo *ri; |
1684 | TCGv_i64 tcg_rt; | |
87462e0f | 1685 | |
fea50522 PM |
1686 | ri = get_arm_cp_reginfo(s->cp_regs, |
1687 | ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, | |
1688 | crn, crm, op0, op1, op2)); | |
87462e0f | 1689 | |
fea50522 | 1690 | if (!ri) { |
626187d8 PM |
1691 | /* Unknown register; this might be a guest error or a QEMU |
1692 | * unimplemented feature. | |
1693 | */ | |
1694 | qemu_log_mask(LOG_UNIMP, "%s access to unsupported AArch64 " | |
1695 | "system register op0:%d op1:%d crn:%d crm:%d op2:%d\n", | |
1696 | isread ? "read" : "write", op0, op1, crn, crm, op2); | |
fea50522 PM |
1697 | unallocated_encoding(s); |
1698 | return; | |
1699 | } | |
1700 | ||
1701 | /* Check access permissions */ | |
dcbff19b | 1702 | if (!cp_access_ok(s->current_el, ri, isread)) { |
fea50522 PM |
1703 | unallocated_encoding(s); |
1704 | return; | |
1705 | } | |
1706 | ||
f59df3f2 PM |
1707 | if (ri->accessfn) { |
1708 | /* Emit code to perform further access permissions checks at | |
1709 | * runtime; this may result in an exception. | |
1710 | */ | |
1711 | TCGv_ptr tmpptr; | |
3f208fd7 | 1712 | TCGv_i32 tcg_syn, tcg_isread; |
8bcbf37c PM |
1713 | uint32_t syndrome; |
1714 | ||
43722a6d | 1715 | gen_a64_set_pc_im(s->pc_curr); |
f59df3f2 | 1716 | tmpptr = tcg_const_ptr(ri); |
8bcbf37c PM |
1717 | syndrome = syn_aa64_sysregtrap(op0, op1, op2, crn, crm, rt, isread); |
1718 | tcg_syn = tcg_const_i32(syndrome); | |
3f208fd7 PM |
1719 | tcg_isread = tcg_const_i32(isread); |
1720 | gen_helper_access_check_cp_reg(cpu_env, tmpptr, tcg_syn, tcg_isread); | |
f59df3f2 | 1721 | tcg_temp_free_ptr(tmpptr); |
8bcbf37c | 1722 | tcg_temp_free_i32(tcg_syn); |
3f208fd7 | 1723 | tcg_temp_free_i32(tcg_isread); |
37ff584c PM |
1724 | } else if (ri->type & ARM_CP_RAISES_EXC) { |
1725 | /* | |
1726 | * The readfn or writefn might raise an exception; | |
1727 | * synchronize the CPU state in case it does. | |
1728 | */ | |
1729 | gen_a64_set_pc_im(s->pc_curr); | |
f59df3f2 PM |
1730 | } |
1731 | ||
fea50522 PM |
1732 | /* Handle special cases first */ |
1733 | switch (ri->type & ~(ARM_CP_FLAG_MASK & ~ARM_CP_SPECIAL)) { | |
1734 | case ARM_CP_NOP: | |
1735 | return; | |
b0d2b7d0 PM |
1736 | case ARM_CP_NZCV: |
1737 | tcg_rt = cpu_reg(s, rt); | |
1738 | if (isread) { | |
1739 | gen_get_nzcv(tcg_rt); | |
1740 | } else { | |
1741 | gen_set_nzcv(tcg_rt); | |
1742 | } | |
1743 | return; | |
0eef9d98 PM |
1744 | case ARM_CP_CURRENTEL: |
1745 | /* Reads as current EL value from pstate, which is | |
1746 | * guaranteed to be constant by the tb flags. | |
1747 | */ | |
1748 | tcg_rt = cpu_reg(s, rt); | |
dcbff19b | 1749 | tcg_gen_movi_i64(tcg_rt, s->current_el << 2); |
0eef9d98 | 1750 | return; |
aca3f40b PM |
1751 | case ARM_CP_DC_ZVA: |
1752 | /* Writes clear the aligned block of memory which rt points into. */ | |
597d61a3 | 1753 | tcg_rt = clean_data_tbi(s, cpu_reg(s, rt)); |
aca3f40b PM |
1754 | gen_helper_dc_zva(cpu_env, tcg_rt); |
1755 | return; | |
fea50522 PM |
1756 | default: |
1757 | break; | |
1758 | } | |
fe03d45f RH |
1759 | if ((ri->type & ARM_CP_FPU) && !fp_access_check(s)) { |
1760 | return; | |
11d7870b RH |
1761 | } else if ((ri->type & ARM_CP_SVE) && !sve_access_check(s)) { |
1762 | return; | |
fe03d45f | 1763 | } |
fea50522 | 1764 | |
c5a49c63 | 1765 | if ((tb_cflags(s->base.tb) & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) { |
fea50522 PM |
1766 | gen_io_start(); |
1767 | } | |
1768 | ||
1769 | tcg_rt = cpu_reg(s, rt); | |
1770 | ||
1771 | if (isread) { | |
1772 | if (ri->type & ARM_CP_CONST) { | |
1773 | tcg_gen_movi_i64(tcg_rt, ri->resetvalue); | |
1774 | } else if (ri->readfn) { | |
1775 | TCGv_ptr tmpptr; | |
fea50522 PM |
1776 | tmpptr = tcg_const_ptr(ri); |
1777 | gen_helper_get_cp_reg64(tcg_rt, cpu_env, tmpptr); | |
1778 | tcg_temp_free_ptr(tmpptr); | |
1779 | } else { | |
1780 | tcg_gen_ld_i64(tcg_rt, cpu_env, ri->fieldoffset); | |
1781 | } | |
1782 | } else { | |
1783 | if (ri->type & ARM_CP_CONST) { | |
1784 | /* If not forbidden by access permissions, treat as WI */ | |
1785 | return; | |
1786 | } else if (ri->writefn) { | |
1787 | TCGv_ptr tmpptr; | |
fea50522 PM |
1788 | tmpptr = tcg_const_ptr(ri); |
1789 | gen_helper_set_cp_reg64(cpu_env, tmpptr, tcg_rt); | |
1790 | tcg_temp_free_ptr(tmpptr); | |
1791 | } else { | |
1792 | tcg_gen_st_i64(tcg_rt, cpu_env, ri->fieldoffset); | |
1793 | } | |
1794 | } | |
1795 | ||
c5a49c63 | 1796 | if ((tb_cflags(s->base.tb) & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) { |
fea50522 | 1797 | /* I/O operations must end the TB here (whether read or write) */ |
dcba3a8d | 1798 | s->base.is_jmp = DISAS_UPDATE; |
69d66864 RH |
1799 | } |
1800 | if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) { | |
1801 | /* | |
1802 | * A write to any coprocessor regiser that ends a TB | |
1803 | * must rebuild the hflags for the next TB. | |
1804 | */ | |
1805 | TCGv_i32 tcg_el = tcg_const_i32(s->current_el); | |
1806 | gen_helper_rebuild_hflags_a64(cpu_env, tcg_el); | |
1807 | tcg_temp_free_i32(tcg_el); | |
1808 | /* | |
1809 | * We default to ending the TB on a coprocessor register write, | |
fea50522 PM |
1810 | * but allow this to be suppressed by the register definition |
1811 | * (usually only necessary to work around guest bugs). | |
1812 | */ | |
dcba3a8d | 1813 | s->base.is_jmp = DISAS_UPDATE; |
fea50522 | 1814 | } |
ad7ee8a2 CF |
1815 | } |
1816 | ||
4ce31af4 | 1817 | /* System |
87462e0f CF |
1818 | * 31 22 21 20 19 18 16 15 12 11 8 7 5 4 0 |
1819 | * +---------------------+---+-----+-----+-------+-------+-----+------+ | |
1820 | * | 1 1 0 1 0 1 0 1 0 0 | L | op0 | op1 | CRn | CRm | op2 | Rt | | |
1821 | * +---------------------+---+-----+-----+-------+-------+-----+------+ | |
1822 | */ | |
1823 | static void disas_system(DisasContext *s, uint32_t insn) | |
1824 | { | |
1825 | unsigned int l, op0, op1, crn, crm, op2, rt; | |
1826 | l = extract32(insn, 21, 1); | |
1827 | op0 = extract32(insn, 19, 2); | |
1828 | op1 = extract32(insn, 16, 3); | |
1829 | crn = extract32(insn, 12, 4); | |
1830 | crm = extract32(insn, 8, 4); | |
1831 | op2 = extract32(insn, 5, 3); | |
1832 | rt = extract32(insn, 0, 5); | |
1833 | ||
1834 | if (op0 == 0) { | |
1835 | if (l || rt != 31) { | |
1836 | unallocated_encoding(s); | |
1837 | return; | |
1838 | } | |
1839 | switch (crn) { | |
4ce31af4 | 1840 | case 2: /* HINT (including allocated hints like NOP, YIELD, etc) */ |
87462e0f CF |
1841 | handle_hint(s, insn, op1, op2, crm); |
1842 | break; | |
1843 | case 3: /* CLREX, DSB, DMB, ISB */ | |
1844 | handle_sync(s, insn, op1, op2, crm); | |
1845 | break; | |
4ce31af4 | 1846 | case 4: /* MSR (immediate) */ |
87462e0f CF |
1847 | handle_msr_i(s, insn, op1, op2, crm); |
1848 | break; | |
1849 | default: | |
1850 | unallocated_encoding(s); | |
1851 | break; | |
1852 | } | |
1853 | return; | |
1854 | } | |
fea50522 | 1855 | handle_sys(s, insn, l, op0, op1, op2, crn, crm, rt); |
87462e0f CF |
1856 | } |
1857 | ||
4ce31af4 | 1858 | /* Exception generation |
9618e809 AG |
1859 | * |
1860 | * 31 24 23 21 20 5 4 2 1 0 | |
1861 | * +-----------------+-----+------------------------+-----+----+ | |
1862 | * | 1 1 0 1 0 1 0 0 | opc | imm16 | op2 | LL | | |
1863 | * +-----------------------+------------------------+----------+ | |
1864 | */ | |
ad7ee8a2 CF |
1865 | static void disas_exc(DisasContext *s, uint32_t insn) |
1866 | { | |
9618e809 AG |
1867 | int opc = extract32(insn, 21, 3); |
1868 | int op2_ll = extract32(insn, 0, 5); | |
d4a2dc67 | 1869 | int imm16 = extract32(insn, 5, 16); |
e0d6e6a5 | 1870 | TCGv_i32 tmp; |
9618e809 AG |
1871 | |
1872 | switch (opc) { | |
1873 | case 0: | |
7ea47fe7 PM |
1874 | /* For SVC, HVC and SMC we advance the single-step state |
1875 | * machine before taking the exception. This is architecturally | |
1876 | * mandated, to ensure that single-stepping a system call | |
1877 | * instruction works properly. | |
1878 | */ | |
35979d71 | 1879 | switch (op2_ll) { |
957956b3 | 1880 | case 1: /* SVC */ |
35979d71 | 1881 | gen_ss_advance(s); |
a767fac8 RH |
1882 | gen_exception_insn(s, s->base.pc_next, EXCP_SWI, |
1883 | syn_aa64_svc(imm16), default_exception_el(s)); | |
35979d71 | 1884 | break; |
957956b3 | 1885 | case 2: /* HVC */ |
dcbff19b | 1886 | if (s->current_el == 0) { |
35979d71 EI |
1887 | unallocated_encoding(s); |
1888 | break; | |
1889 | } | |
1890 | /* The pre HVC helper handles cases when HVC gets trapped | |
1891 | * as an undefined insn by runtime configuration. | |
1892 | */ | |
43722a6d | 1893 | gen_a64_set_pc_im(s->pc_curr); |
35979d71 EI |
1894 | gen_helper_pre_hvc(cpu_env); |
1895 | gen_ss_advance(s); | |
a767fac8 RH |
1896 | gen_exception_insn(s, s->base.pc_next, EXCP_HVC, |
1897 | syn_aa64_hvc(imm16), 2); | |
35979d71 | 1898 | break; |
957956b3 | 1899 | case 3: /* SMC */ |
dcbff19b | 1900 | if (s->current_el == 0) { |
e0d6e6a5 EI |
1901 | unallocated_encoding(s); |
1902 | break; | |
1903 | } | |
43722a6d | 1904 | gen_a64_set_pc_im(s->pc_curr); |
e0d6e6a5 EI |
1905 | tmp = tcg_const_i32(syn_aa64_smc(imm16)); |
1906 | gen_helper_pre_smc(cpu_env, tmp); | |
1907 | tcg_temp_free_i32(tmp); | |
1908 | gen_ss_advance(s); | |
a767fac8 RH |
1909 | gen_exception_insn(s, s->base.pc_next, EXCP_SMC, |
1910 | syn_aa64_smc(imm16), 3); | |
e0d6e6a5 | 1911 | break; |
35979d71 EI |
1912 | default: |
1913 | unallocated_encoding(s); | |
1914 | break; | |
1915 | } | |
9618e809 AG |
1916 | break; |
1917 | case 1: | |
1918 | if (op2_ll != 0) { | |
1919 | unallocated_encoding(s); | |
1920 | break; | |
1921 | } | |
1922 | /* BRK */ | |
06bcbda3 | 1923 | gen_exception_bkpt_insn(s, syn_aa64_bkpt(imm16)); |
9618e809 AG |
1924 | break; |
1925 | case 2: | |
1926 | if (op2_ll != 0) { | |
1927 | unallocated_encoding(s); | |
1928 | break; | |
1929 | } | |
8012c84f PM |
1930 | /* HLT. This has two purposes. |
1931 | * Architecturally, it is an external halting debug instruction. | |
1932 | * Since QEMU doesn't implement external debug, we treat this as | |
1933 | * it is required for halting debug disabled: it will UNDEF. | |
1934 | * Secondly, "HLT 0xf000" is the A64 semihosting syscall instruction. | |
1935 | */ | |
1936 | if (semihosting_enabled() && imm16 == 0xf000) { | |
1937 | #ifndef CONFIG_USER_ONLY | |
1938 | /* In system mode, don't allow userspace access to semihosting, | |
1939 | * to provide some semblance of security (and for consistency | |
1940 | * with our 32-bit semihosting). | |
1941 | */ | |
1942 | if (s->current_el == 0) { | |
1943 | unsupported_encoding(s, insn); | |
1944 | break; | |
1945 | } | |
1946 | #endif | |
4ff5ef9e | 1947 | gen_exception_internal_insn(s, s->pc_curr, EXCP_SEMIHOST); |
8012c84f PM |
1948 | } else { |
1949 | unsupported_encoding(s, insn); | |
1950 | } | |
9618e809 AG |
1951 | break; |
1952 | case 5: | |
1953 | if (op2_ll < 1 || op2_ll > 3) { | |
1954 | unallocated_encoding(s); | |
1955 | break; | |
1956 | } | |
1957 | /* DCPS1, DCPS2, DCPS3 */ | |
1958 | unsupported_encoding(s, insn); | |
1959 | break; | |
1960 | default: | |
1961 | unallocated_encoding(s); | |
1962 | break; | |
1963 | } | |
ad7ee8a2 CF |
1964 | } |
1965 | ||
4ce31af4 | 1966 | /* Unconditional branch (register) |
b001c8c3 AG |
1967 | * 31 25 24 21 20 16 15 10 9 5 4 0 |
1968 | * +---------------+-------+-------+-------+------+-------+ | |
1969 | * | 1 1 0 1 0 1 1 | opc | op2 | op3 | Rn | op4 | | |
1970 | * +---------------+-------+-------+-------+------+-------+ | |
1971 | */ | |
ad7ee8a2 CF |
1972 | static void disas_uncond_b_reg(DisasContext *s, uint32_t insn) |
1973 | { | |
b001c8c3 | 1974 | unsigned int opc, op2, op3, rn, op4; |
001d47b6 | 1975 | unsigned btype_mod = 2; /* 0: BR, 1: BLR, 2: other */ |
d9f482a0 | 1976 | TCGv_i64 dst; |
561c0a33 | 1977 | TCGv_i64 modifier; |
b001c8c3 AG |
1978 | |
1979 | opc = extract32(insn, 21, 4); | |
1980 | op2 = extract32(insn, 16, 5); | |
1981 | op3 = extract32(insn, 10, 6); | |
1982 | rn = extract32(insn, 5, 5); | |
1983 | op4 = extract32(insn, 0, 5); | |
1984 | ||
f7cf3bfc RH |
1985 | if (op2 != 0x1f) { |
1986 | goto do_unallocated; | |
b001c8c3 AG |
1987 | } |
1988 | ||
1989 | switch (opc) { | |
1990 | case 0: /* BR */ | |
b001c8c3 | 1991 | case 1: /* BLR */ |
6feecb8b | 1992 | case 2: /* RET */ |
001d47b6 | 1993 | btype_mod = opc; |
f7cf3bfc RH |
1994 | switch (op3) { |
1995 | case 0: | |
561c0a33 | 1996 | /* BR, BLR, RET */ |
f7cf3bfc RH |
1997 | if (op4 != 0) { |
1998 | goto do_unallocated; | |
1999 | } | |
2000 | dst = cpu_reg(s, rn); | |
2001 | break; | |
2002 | ||
561c0a33 RH |
2003 | case 2: |
2004 | case 3: | |
2005 | if (!dc_isar_feature(aa64_pauth, s)) { | |
2006 | goto do_unallocated; | |
2007 | } | |
2008 | if (opc == 2) { | |
2009 | /* RETAA, RETAB */ | |
2010 | if (rn != 0x1f || op4 != 0x1f) { | |
2011 | goto do_unallocated; | |
2012 | } | |
2013 | rn = 30; | |
2014 | modifier = cpu_X[31]; | |
2015 | } else { | |
2016 | /* BRAAZ, BRABZ, BLRAAZ, BLRABZ */ | |
2017 | if (op4 != 0x1f) { | |
2018 | goto do_unallocated; | |
2019 | } | |
2020 | modifier = new_tmp_a64_zero(s); | |
2021 | } | |
2022 | if (s->pauth_active) { | |
2023 | dst = new_tmp_a64(s); | |
2024 | if (op3 == 2) { | |
2025 | gen_helper_autia(dst, cpu_env, cpu_reg(s, rn), modifier); | |
2026 | } else { | |
2027 | gen_helper_autib(dst, cpu_env, cpu_reg(s, rn), modifier); | |
2028 | } | |
2029 | } else { | |
2030 | dst = cpu_reg(s, rn); | |
2031 | } | |
2032 | break; | |
2033 | ||
f7cf3bfc RH |
2034 | default: |
2035 | goto do_unallocated; | |
2036 | } | |
f7cf3bfc | 2037 | gen_a64_set_pc(s, dst); |
6feecb8b TH |
2038 | /* BLR also needs to load return address */ |
2039 | if (opc == 1) { | |
a0415916 | 2040 | tcg_gen_movi_i64(cpu_reg(s, 30), s->base.pc_next); |
6feecb8b | 2041 | } |
b001c8c3 | 2042 | break; |
f7cf3bfc | 2043 | |
561c0a33 RH |
2044 | case 8: /* BRAA */ |
2045 | case 9: /* BLRAA */ | |
2046 | if (!dc_isar_feature(aa64_pauth, s)) { | |
2047 | goto do_unallocated; | |
2048 | } | |
1cf86a86 | 2049 | if ((op3 & ~1) != 2) { |
561c0a33 RH |
2050 | goto do_unallocated; |
2051 | } | |
001d47b6 | 2052 | btype_mod = opc & 1; |
561c0a33 RH |
2053 | if (s->pauth_active) { |
2054 | dst = new_tmp_a64(s); | |
2055 | modifier = cpu_reg_sp(s, op4); | |
2056 | if (op3 == 2) { | |
2057 | gen_helper_autia(dst, cpu_env, cpu_reg(s, rn), modifier); | |
2058 | } else { | |
2059 | gen_helper_autib(dst, cpu_env, cpu_reg(s, rn), modifier); | |
2060 | } | |
2061 | } else { | |
2062 | dst = cpu_reg(s, rn); | |
2063 | } | |
2064 | gen_a64_set_pc(s, dst); | |
2065 | /* BLRAA also needs to load return address */ | |
2066 | if (opc == 9) { | |
a0415916 | 2067 | tcg_gen_movi_i64(cpu_reg(s, 30), s->base.pc_next); |
561c0a33 RH |
2068 | } |
2069 | break; | |
2070 | ||
b001c8c3 | 2071 | case 4: /* ERET */ |
dcbff19b | 2072 | if (s->current_el == 0) { |
f7cf3bfc RH |
2073 | goto do_unallocated; |
2074 | } | |
2075 | switch (op3) { | |
561c0a33 | 2076 | case 0: /* ERET */ |
f7cf3bfc RH |
2077 | if (op4 != 0) { |
2078 | goto do_unallocated; | |
2079 | } | |
2080 | dst = tcg_temp_new_i64(); | |
2081 | tcg_gen_ld_i64(dst, cpu_env, | |
2082 | offsetof(CPUARMState, elr_el[s->current_el])); | |
2083 | break; | |
2084 | ||
561c0a33 RH |
2085 | case 2: /* ERETAA */ |
2086 | case 3: /* ERETAB */ | |
2087 | if (!dc_isar_feature(aa64_pauth, s)) { | |
2088 | goto do_unallocated; | |
2089 | } | |
2090 | if (rn != 0x1f || op4 != 0x1f) { | |
2091 | goto do_unallocated; | |
2092 | } | |
2093 | dst = tcg_temp_new_i64(); | |
2094 | tcg_gen_ld_i64(dst, cpu_env, | |
2095 | offsetof(CPUARMState, elr_el[s->current_el])); | |
2096 | if (s->pauth_active) { | |
2097 | modifier = cpu_X[31]; | |
2098 | if (op3 == 2) { | |
2099 | gen_helper_autia(dst, cpu_env, dst, modifier); | |
2100 | } else { | |
2101 | gen_helper_autib(dst, cpu_env, dst, modifier); | |
2102 | } | |
2103 | } | |
2104 | break; | |
2105 | ||
f7cf3bfc RH |
2106 | default: |
2107 | goto do_unallocated; | |
14c521d4 | 2108 | } |
e69ad9df AL |
2109 | if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { |
2110 | gen_io_start(); | |
2111 | } | |
f7cf3bfc | 2112 | |
d9f482a0 RH |
2113 | gen_helper_exception_return(cpu_env, dst); |
2114 | tcg_temp_free_i64(dst); | |
b29fd33d | 2115 | /* Must exit loop to check un-masked IRQs */ |
dcba3a8d | 2116 | s->base.is_jmp = DISAS_EXIT; |
52e60cdd | 2117 | return; |
f7cf3bfc | 2118 | |
b001c8c3 | 2119 | case 5: /* DRPS */ |
f7cf3bfc RH |
2120 | if (op3 != 0 || op4 != 0 || rn != 0x1f) { |
2121 | goto do_unallocated; | |
b001c8c3 AG |
2122 | } else { |
2123 | unsupported_encoding(s, insn); | |
2124 | } | |
2125 | return; | |
f7cf3bfc | 2126 | |
b001c8c3 | 2127 | default: |
f7cf3bfc | 2128 | do_unallocated: |
b001c8c3 AG |
2129 | unallocated_encoding(s); |
2130 | return; | |
2131 | } | |
2132 | ||
001d47b6 RH |
2133 | switch (btype_mod) { |
2134 | case 0: /* BR */ | |
2135 | if (dc_isar_feature(aa64_bti, s)) { | |
2136 | /* BR to {x16,x17} or !guard -> 1, else 3. */ | |
2137 | set_btype(s, rn == 16 || rn == 17 || !s->guarded_page ? 1 : 3); | |
2138 | } | |
2139 | break; | |
2140 | ||
2141 | case 1: /* BLR */ | |
2142 | if (dc_isar_feature(aa64_bti, s)) { | |
2143 | /* BLR sets BTYPE to 2, regardless of source guarded page. */ | |
2144 | set_btype(s, 2); | |
2145 | } | |
2146 | break; | |
2147 | ||
2148 | default: /* RET or none of the above. */ | |
2149 | /* BTYPE will be set to 0 by normal end-of-insn processing. */ | |
2150 | break; | |
2151 | } | |
2152 | ||
dcba3a8d | 2153 | s->base.is_jmp = DISAS_JUMP; |
ad7ee8a2 CF |
2154 | } |
2155 | ||
4ce31af4 | 2156 | /* Branches, exception generating and system instructions */ |
ad7ee8a2 CF |
2157 | static void disas_b_exc_sys(DisasContext *s, uint32_t insn) |
2158 | { | |
2159 | switch (extract32(insn, 25, 7)) { | |
2160 | case 0x0a: case 0x0b: | |
2161 | case 0x4a: case 0x4b: /* Unconditional branch (immediate) */ | |
2162 | disas_uncond_b_imm(s, insn); | |
2163 | break; | |
2164 | case 0x1a: case 0x5a: /* Compare & branch (immediate) */ | |
2165 | disas_comp_b_imm(s, insn); | |
2166 | break; | |
2167 | case 0x1b: case 0x5b: /* Test & branch (immediate) */ | |
2168 | disas_test_b_imm(s, insn); | |
2169 | break; | |
2170 | case 0x2a: /* Conditional branch (immediate) */ | |
2171 | disas_cond_b_imm(s, insn); | |
2172 | break; | |
2173 | case 0x6a: /* Exception generation / System */ | |
2174 | if (insn & (1 << 24)) { | |
08d5e3bd PM |
2175 | if (extract32(insn, 22, 2) == 0) { |
2176 | disas_system(s, insn); | |
2177 | } else { | |
2178 | unallocated_encoding(s); | |
2179 | } | |
ad7ee8a2 CF |
2180 | } else { |
2181 | disas_exc(s, insn); | |
2182 | } | |
2183 | break; | |
2184 | case 0x6b: /* Unconditional branch (register) */ | |
2185 | disas_uncond_b_reg(s, insn); | |
2186 | break; | |
2187 | default: | |
2188 | unallocated_encoding(s); | |
2189 | break; | |
2190 | } | |
2191 | } | |
2192 | ||
5460da50 AB |
2193 | /* |
2194 | * Load/Store exclusive instructions are implemented by remembering | |
2195 | * the value/address loaded, and seeing if these are the same | |
2196 | * when the store is performed. This is not actually the architecturally | |
2197 | * mandated semantics, but it works for typical guest code sequences | |
2198 | * and avoids having to monitor regular stores. | |
2199 | * | |
2200 | * The store exclusive uses the atomic cmpxchg primitives to avoid | |
2201 | * races in multi-threaded linux-user and when MTTCG softmmu is | |
2202 | * enabled. | |
2203 | */ | |
fa2ef212 MM |
2204 | static void gen_load_exclusive(DisasContext *s, int rt, int rt2, |
2205 | TCGv_i64 addr, int size, bool is_pair) | |
2206 | { | |
19514cde | 2207 | int idx = get_mem_index(s); |
14776ab5 | 2208 | MemOp memop = s->be_data; |
fa2ef212 MM |
2209 | |
2210 | g_assert(size <= 3); | |
fa2ef212 | 2211 | if (is_pair) { |
5460da50 | 2212 | g_assert(size >= 2); |
19514cde RH |
2213 | if (size == 2) { |
2214 | /* The pair must be single-copy atomic for the doubleword. */ | |
4a2fdb78 | 2215 | memop |= MO_64 | MO_ALIGN; |
19514cde RH |
2216 | tcg_gen_qemu_ld_i64(cpu_exclusive_val, addr, idx, memop); |
2217 | if (s->be_data == MO_LE) { | |
2218 | tcg_gen_extract_i64(cpu_reg(s, rt), cpu_exclusive_val, 0, 32); | |
2219 | tcg_gen_extract_i64(cpu_reg(s, rt2), cpu_exclusive_val, 32, 32); | |
2220 | } else { | |
2221 | tcg_gen_extract_i64(cpu_reg(s, rt), cpu_exclusive_val, 32, 32); | |
2222 | tcg_gen_extract_i64(cpu_reg(s, rt2), cpu_exclusive_val, 0, 32); | |
2223 | } | |
2224 | } else { | |
4a2fdb78 AF |
2225 | /* The pair must be single-copy atomic for *each* doubleword, not |
2226 | the entire quadword, however it must be quadword aligned. */ | |
19514cde | 2227 | memop |= MO_64; |
4a2fdb78 AF |
2228 | tcg_gen_qemu_ld_i64(cpu_exclusive_val, addr, idx, |
2229 | memop | MO_ALIGN_16); | |
19514cde RH |
2230 | |
2231 | TCGv_i64 addr2 = tcg_temp_new_i64(); | |
2232 | tcg_gen_addi_i64(addr2, addr, 8); | |
2233 | tcg_gen_qemu_ld_i64(cpu_exclusive_high, addr2, idx, memop); | |
2234 | tcg_temp_free_i64(addr2); | |
2235 | ||
2236 | tcg_gen_mov_i64(cpu_reg(s, rt), cpu_exclusive_val); | |
2237 | tcg_gen_mov_i64(cpu_reg(s, rt2), cpu_exclusive_high); | |
2238 | } | |
2239 | } else { | |
4a2fdb78 | 2240 | memop |= size | MO_ALIGN; |
19514cde RH |
2241 | tcg_gen_qemu_ld_i64(cpu_exclusive_val, addr, idx, memop); |
2242 | tcg_gen_mov_i64(cpu_reg(s, rt), cpu_exclusive_val); | |
fa2ef212 | 2243 | } |
fa2ef212 MM |
2244 | tcg_gen_mov_i64(cpu_exclusive_addr, addr); |
2245 | } | |
2246 | ||
fa2ef212 | 2247 | static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2, |
37e29a64 | 2248 | TCGv_i64 addr, int size, int is_pair) |
fa2ef212 | 2249 | { |
d324b36a PM |
2250 | /* if (env->exclusive_addr == addr && env->exclusive_val == [addr] |
2251 | * && (!is_pair || env->exclusive_high == [addr + datasize])) { | |
2252 | * [addr] = {Rt}; | |
2253 | * if (is_pair) { | |
2254 | * [addr + datasize] = {Rt2}; | |
2255 | * } | |
2256 | * {Rd} = 0; | |
2257 | * } else { | |
2258 | * {Rd} = 1; | |
2259 | * } | |
2260 | * env->exclusive_addr = -1; | |
2261 | */ | |
42a268c2 RH |
2262 | TCGLabel *fail_label = gen_new_label(); |
2263 | TCGLabel *done_label = gen_new_label(); | |
d324b36a PM |
2264 | TCGv_i64 tmp; |
2265 | ||
d324b36a PM |
2266 | tcg_gen_brcond_i64(TCG_COND_NE, addr, cpu_exclusive_addr, fail_label); |
2267 | ||
2268 | tmp = tcg_temp_new_i64(); | |
d324b36a | 2269 | if (is_pair) { |
1dd089d0 | 2270 | if (size == 2) { |
19514cde RH |
2271 | if (s->be_data == MO_LE) { |
2272 | tcg_gen_concat32_i64(tmp, cpu_reg(s, rt), cpu_reg(s, rt2)); | |
2273 | } else { | |
2274 | tcg_gen_concat32_i64(tmp, cpu_reg(s, rt2), cpu_reg(s, rt)); | |
2275 | } | |
37e29a64 RH |
2276 | tcg_gen_atomic_cmpxchg_i64(tmp, cpu_exclusive_addr, |
2277 | cpu_exclusive_val, tmp, | |
1dd089d0 | 2278 | get_mem_index(s), |
955fd0ad | 2279 | MO_64 | MO_ALIGN | s->be_data); |
19514cde | 2280 | tcg_gen_setcond_i64(TCG_COND_NE, tmp, tmp, cpu_exclusive_val); |
62823083 RH |
2281 | } else if (tb_cflags(s->base.tb) & CF_PARALLEL) { |
2282 | if (!HAVE_CMPXCHG128) { | |
2283 | gen_helper_exit_atomic(cpu_env); | |
2284 | s->base.is_jmp = DISAS_NORETURN; | |
2285 | } else if (s->be_data == MO_LE) { | |
2399d4e7 EC |
2286 | gen_helper_paired_cmpxchg64_le_parallel(tmp, cpu_env, |
2287 | cpu_exclusive_addr, | |
2288 | cpu_reg(s, rt), | |
2289 | cpu_reg(s, rt2)); | |
2290 | } else { | |
2399d4e7 EC |
2291 | gen_helper_paired_cmpxchg64_be_parallel(tmp, cpu_env, |
2292 | cpu_exclusive_addr, | |
2293 | cpu_reg(s, rt), | |
2294 | cpu_reg(s, rt2)); | |
2399d4e7 | 2295 | } |
62823083 RH |
2296 | } else if (s->be_data == MO_LE) { |
2297 | gen_helper_paired_cmpxchg64_le(tmp, cpu_env, cpu_exclusive_addr, | |
2298 | cpu_reg(s, rt), cpu_reg(s, rt2)); | |
2299 | } else { | |
2300 | gen_helper_paired_cmpxchg64_be(tmp, cpu_env, cpu_exclusive_addr, | |
2301 | cpu_reg(s, rt), cpu_reg(s, rt2)); | |
1dd089d0 EC |
2302 | } |
2303 | } else { | |
37e29a64 RH |
2304 | tcg_gen_atomic_cmpxchg_i64(tmp, cpu_exclusive_addr, cpu_exclusive_val, |
2305 | cpu_reg(s, rt), get_mem_index(s), | |
1dd089d0 EC |
2306 | size | MO_ALIGN | s->be_data); |
2307 | tcg_gen_setcond_i64(TCG_COND_NE, tmp, tmp, cpu_exclusive_val); | |
d324b36a | 2308 | } |
1dd089d0 EC |
2309 | tcg_gen_mov_i64(cpu_reg(s, rd), tmp); |
2310 | tcg_temp_free_i64(tmp); | |
d324b36a | 2311 | tcg_gen_br(done_label); |
1dd089d0 | 2312 | |
d324b36a PM |
2313 | gen_set_label(fail_label); |
2314 | tcg_gen_movi_i64(cpu_reg(s, rd), 1); | |
2315 | gen_set_label(done_label); | |
2316 | tcg_gen_movi_i64(cpu_exclusive_addr, -1); | |
fa2ef212 | 2317 | } |
fa2ef212 | 2318 | |
44ac14b0 RH |
2319 | static void gen_compare_and_swap(DisasContext *s, int rs, int rt, |
2320 | int rn, int size) | |
2321 | { | |
2322 | TCGv_i64 tcg_rs = cpu_reg(s, rs); | |
2323 | TCGv_i64 tcg_rt = cpu_reg(s, rt); | |
2324 | int memidx = get_mem_index(s); | |
3a471103 | 2325 | TCGv_i64 clean_addr; |
44ac14b0 RH |
2326 | |
2327 | if (rn == 31) { | |
2328 | gen_check_sp_alignment(s); | |
2329 | } | |
3a471103 RH |
2330 | clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn)); |
2331 | tcg_gen_atomic_cmpxchg_i64(tcg_rs, clean_addr, tcg_rs, tcg_rt, memidx, | |
44ac14b0 RH |
2332 | size | MO_ALIGN | s->be_data); |
2333 | } | |
2334 | ||
2335 | static void gen_compare_and_swap_pair(DisasContext *s, int rs, int rt, | |
2336 | int rn, int size) | |
2337 | { | |
2338 | TCGv_i64 s1 = cpu_reg(s, rs); | |
2339 | TCGv_i64 s2 = cpu_reg(s, rs + 1); | |
2340 | TCGv_i64 t1 = cpu_reg(s, rt); | |
2341 | TCGv_i64 t2 = cpu_reg(s, rt + 1); | |
3a471103 | 2342 | TCGv_i64 clean_addr; |
44ac14b0 RH |
2343 | int memidx = get_mem_index(s); |
2344 | ||
2345 | if (rn == 31) { | |
2346 | gen_check_sp_alignment(s); | |
2347 | } | |
3a471103 | 2348 | clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn)); |
44ac14b0 RH |
2349 | |
2350 | if (size == 2) { | |
2351 | TCGv_i64 cmp = tcg_temp_new_i64(); | |
2352 | TCGv_i64 val = tcg_temp_new_i64(); | |
2353 | ||
2354 | if (s->be_data == MO_LE) { | |
2355 | tcg_gen_concat32_i64(val, t1, t2); | |
2356 | tcg_gen_concat32_i64(cmp, s1, s2); | |
2357 | } else { | |
2358 | tcg_gen_concat32_i64(val, t2, t1); | |
2359 | tcg_gen_concat32_i64(cmp, s2, s1); | |
2360 | } | |
2361 | ||
3a471103 | 2362 | tcg_gen_atomic_cmpxchg_i64(cmp, clean_addr, cmp, val, memidx, |
44ac14b0 RH |
2363 | MO_64 | MO_ALIGN | s->be_data); |
2364 | tcg_temp_free_i64(val); | |
2365 | ||
2366 | if (s->be_data == MO_LE) { | |
2367 | tcg_gen_extr32_i64(s1, s2, cmp); | |
2368 | } else { | |
2369 | tcg_gen_extr32_i64(s2, s1, cmp); | |
2370 | } | |
2371 | tcg_temp_free_i64(cmp); | |
2372 | } else if (tb_cflags(s->base.tb) & CF_PARALLEL) { | |
62823083 RH |
2373 | if (HAVE_CMPXCHG128) { |
2374 | TCGv_i32 tcg_rs = tcg_const_i32(rs); | |
2375 | if (s->be_data == MO_LE) { | |
3a471103 RH |
2376 | gen_helper_casp_le_parallel(cpu_env, tcg_rs, |
2377 | clean_addr, t1, t2); | |
62823083 | 2378 | } else { |
3a471103 RH |
2379 | gen_helper_casp_be_parallel(cpu_env, tcg_rs, |
2380 | clean_addr, t1, t2); | |
62823083 RH |
2381 | } |
2382 | tcg_temp_free_i32(tcg_rs); | |
44ac14b0 | 2383 | } else { |
62823083 RH |
2384 | gen_helper_exit_atomic(cpu_env); |
2385 | s->base.is_jmp = DISAS_NORETURN; | |
44ac14b0 | 2386 | } |
44ac14b0 RH |
2387 | } else { |
2388 | TCGv_i64 d1 = tcg_temp_new_i64(); | |
2389 | TCGv_i64 d2 = tcg_temp_new_i64(); | |
2390 | TCGv_i64 a2 = tcg_temp_new_i64(); | |
2391 | TCGv_i64 c1 = tcg_temp_new_i64(); | |
2392 | TCGv_i64 c2 = tcg_temp_new_i64(); | |
2393 | TCGv_i64 zero = tcg_const_i64(0); | |
2394 | ||
2395 | /* Load the two words, in memory order. */ | |
3a471103 | 2396 | tcg_gen_qemu_ld_i64(d1, clean_addr, memidx, |
44ac14b0 | 2397 | MO_64 | MO_ALIGN_16 | s->be_data); |
3a471103 | 2398 | tcg_gen_addi_i64(a2, clean_addr, 8); |
a036f530 | 2399 | tcg_gen_qemu_ld_i64(d2, a2, memidx, MO_64 | s->be_data); |
44ac14b0 RH |
2400 | |
2401 | /* Compare the two words, also in memory order. */ | |
2402 | tcg_gen_setcond_i64(TCG_COND_EQ, c1, d1, s1); | |
2403 | tcg_gen_setcond_i64(TCG_COND_EQ, c2, d2, s2); | |
2404 | tcg_gen_and_i64(c2, c2, c1); | |
2405 | ||
2406 | /* If compare equal, write back new data, else write back old data. */ | |
2407 | tcg_gen_movcond_i64(TCG_COND_NE, c1, c2, zero, t1, d1); | |
2408 | tcg_gen_movcond_i64(TCG_COND_NE, c2, c2, zero, t2, d2); | |
3a471103 | 2409 | tcg_gen_qemu_st_i64(c1, clean_addr, memidx, MO_64 | s->be_data); |
44ac14b0 RH |
2410 | tcg_gen_qemu_st_i64(c2, a2, memidx, MO_64 | s->be_data); |
2411 | tcg_temp_free_i64(a2); | |
2412 | tcg_temp_free_i64(c1); | |
2413 | tcg_temp_free_i64(c2); | |
2414 | tcg_temp_free_i64(zero); | |
2415 | ||
2416 | /* Write back the data from memory to Rs. */ | |
2417 | tcg_gen_mov_i64(s1, d1); | |
2418 | tcg_gen_mov_i64(s2, d2); | |
2419 | tcg_temp_free_i64(d1); | |
2420 | tcg_temp_free_i64(d2); | |
2421 | } | |
2422 | } | |
2423 | ||
aaa1f954 EI |
2424 | /* Update the Sixty-Four bit (SF) registersize. This logic is derived |
2425 | * from the ARMv8 specs for LDR (Shared decode for all encodings). | |
2426 | */ | |
2427 | static bool disas_ldst_compute_iss_sf(int size, bool is_signed, int opc) | |
2428 | { | |
2429 | int opc0 = extract32(opc, 0, 1); | |
2430 | int regsize; | |
2431 | ||
2432 | if (is_signed) { | |
2433 | regsize = opc0 ? 32 : 64; | |
2434 | } else { | |
2435 | regsize = size == 3 ? 64 : 32; | |
2436 | } | |
2437 | return regsize == 64; | |
2438 | } | |
2439 | ||
4ce31af4 | 2440 | /* Load/store exclusive |
fa2ef212 MM |
2441 | * |
2442 | * 31 30 29 24 23 22 21 20 16 15 14 10 9 5 4 0 | |
2443 | * +-----+-------------+----+---+----+------+----+-------+------+------+ | |
2444 | * | sz | 0 0 1 0 0 0 | o2 | L | o1 | Rs | o0 | Rt2 | Rn | Rt | | |
2445 | * +-----+-------------+----+---+----+------+----+-------+------+------+ | |
2446 | * | |
2447 | * sz: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64 bit | |
2448 | * L: 0 -> store, 1 -> load | |
2449 | * o2: 0 -> exclusive, 1 -> not | |
2450 | * o1: 0 -> single register, 1 -> register pair | |
2451 | * o0: 1 -> load-acquire/store-release, 0 -> not | |
fa2ef212 | 2452 | */ |
ad7ee8a2 CF |
2453 | static void disas_ldst_excl(DisasContext *s, uint32_t insn) |
2454 | { | |
fa2ef212 MM |
2455 | int rt = extract32(insn, 0, 5); |
2456 | int rn = extract32(insn, 5, 5); | |
2457 | int rt2 = extract32(insn, 10, 5); | |
fa2ef212 | 2458 | int rs = extract32(insn, 16, 5); |
68412d2e RH |
2459 | int is_lasr = extract32(insn, 15, 1); |
2460 | int o2_L_o1_o0 = extract32(insn, 21, 3) * 2 | is_lasr; | |
fa2ef212 | 2461 | int size = extract32(insn, 30, 2); |
3a471103 | 2462 | TCGv_i64 clean_addr; |
fa2ef212 | 2463 | |
68412d2e RH |
2464 | switch (o2_L_o1_o0) { |
2465 | case 0x0: /* STXR */ | |
2466 | case 0x1: /* STLXR */ | |
2467 | if (rn == 31) { | |
2468 | gen_check_sp_alignment(s); | |
2469 | } | |
2470 | if (is_lasr) { | |
2471 | tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); | |
2472 | } | |
3a471103 RH |
2473 | clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn)); |
2474 | gen_store_exclusive(s, rs, rt, rt2, clean_addr, size, false); | |
fa2ef212 | 2475 | return; |
fa2ef212 | 2476 | |
68412d2e RH |
2477 | case 0x4: /* LDXR */ |
2478 | case 0x5: /* LDAXR */ | |
2479 | if (rn == 31) { | |
2480 | gen_check_sp_alignment(s); | |
2481 | } | |
3a471103 | 2482 | clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn)); |
68412d2e | 2483 | s->is_ldex = true; |
3a471103 | 2484 | gen_load_exclusive(s, rt, rt2, clean_addr, size, false); |
68412d2e RH |
2485 | if (is_lasr) { |
2486 | tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); | |
2487 | } | |
2488 | return; | |
fa2ef212 | 2489 | |
2d7137c1 RH |
2490 | case 0x8: /* STLLR */ |
2491 | if (!dc_isar_feature(aa64_lor, s)) { | |
2492 | break; | |
2493 | } | |
2494 | /* StoreLORelease is the same as Store-Release for QEMU. */ | |
2495 | /* fall through */ | |
68412d2e RH |
2496 | case 0x9: /* STLR */ |
2497 | /* Generate ISS for non-exclusive accesses including LASR. */ | |
2498 | if (rn == 31) { | |
2499 | gen_check_sp_alignment(s); | |
2500 | } | |
2501 | tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); | |
3a471103 RH |
2502 | clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn)); |
2503 | do_gpr_st(s, cpu_reg(s, rt), clean_addr, size, true, rt, | |
68412d2e RH |
2504 | disas_ldst_compute_iss_sf(size, false, 0), is_lasr); |
2505 | return; | |
fa2ef212 | 2506 | |
2d7137c1 RH |
2507 | case 0xc: /* LDLAR */ |
2508 | if (!dc_isar_feature(aa64_lor, s)) { | |
2509 | break; | |
2510 | } | |
2511 | /* LoadLOAcquire is the same as Load-Acquire for QEMU. */ | |
2512 | /* fall through */ | |
68412d2e RH |
2513 | case 0xd: /* LDAR */ |
2514 | /* Generate ISS for non-exclusive accesses including LASR. */ | |
2515 | if (rn == 31) { | |
2516 | gen_check_sp_alignment(s); | |
2517 | } | |
3a471103 RH |
2518 | clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn)); |
2519 | do_gpr_ld(s, cpu_reg(s, rt), clean_addr, size, false, false, true, rt, | |
68412d2e RH |
2520 | disas_ldst_compute_iss_sf(size, false, 0), is_lasr); |
2521 | tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); | |
2522 | return; | |
2523 | ||
2524 | case 0x2: case 0x3: /* CASP / STXP */ | |
2525 | if (size & 2) { /* STXP / STLXP */ | |
2526 | if (rn == 31) { | |
2527 | gen_check_sp_alignment(s); | |
ce1bd93f | 2528 | } |
ce1bd93f PK |
2529 | if (is_lasr) { |
2530 | tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); | |
2531 | } | |
3a471103 RH |
2532 | clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn)); |
2533 | gen_store_exclusive(s, rs, rt, rt2, clean_addr, size, true); | |
68412d2e | 2534 | return; |
fa2ef212 | 2535 | } |
44ac14b0 RH |
2536 | if (rt2 == 31 |
2537 | && ((rt | rs) & 1) == 0 | |
962fcbf2 | 2538 | && dc_isar_feature(aa64_atomics, s)) { |
44ac14b0 RH |
2539 | /* CASP / CASPL */ |
2540 | gen_compare_and_swap_pair(s, rs, rt, rn, size | 2); | |
2541 | return; | |
2542 | } | |
68412d2e | 2543 | break; |
aaa1f954 | 2544 | |
44ac14b0 | 2545 | case 0x6: case 0x7: /* CASPA / LDXP */ |
68412d2e RH |
2546 | if (size & 2) { /* LDXP / LDAXP */ |
2547 | if (rn == 31) { | |
2548 | gen_check_sp_alignment(s); | |
ce1bd93f | 2549 | } |
3a471103 | 2550 | clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn)); |
68412d2e | 2551 | s->is_ldex = true; |
3a471103 | 2552 | gen_load_exclusive(s, rt, rt2, clean_addr, size, true); |
ce1bd93f PK |
2553 | if (is_lasr) { |
2554 | tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); | |
2555 | } | |
68412d2e | 2556 | return; |
fa2ef212 | 2557 | } |
44ac14b0 RH |
2558 | if (rt2 == 31 |
2559 | && ((rt | rs) & 1) == 0 | |
962fcbf2 | 2560 | && dc_isar_feature(aa64_atomics, s)) { |
44ac14b0 RH |
2561 | /* CASPA / CASPAL */ |
2562 | gen_compare_and_swap_pair(s, rs, rt, rn, size | 2); | |
2563 | return; | |
fa2ef212 | 2564 | } |
68412d2e RH |
2565 | break; |
2566 | ||
2567 | case 0xa: /* CAS */ | |
2568 | case 0xb: /* CASL */ | |
2569 | case 0xe: /* CASA */ | |
2570 | case 0xf: /* CASAL */ | |
962fcbf2 | 2571 | if (rt2 == 31 && dc_isar_feature(aa64_atomics, s)) { |
44ac14b0 RH |
2572 | gen_compare_and_swap(s, rs, rt, rn, size); |
2573 | return; | |
2574 | } | |
68412d2e | 2575 | break; |
fa2ef212 | 2576 | } |
68412d2e | 2577 | unallocated_encoding(s); |
ad7ee8a2 CF |
2578 | } |
2579 | ||
32b64e86 | 2580 | /* |
4ce31af4 | 2581 | * Load register (literal) |
32b64e86 AG |
2582 | * |
2583 | * 31 30 29 27 26 25 24 23 5 4 0 | |
2584 | * +-----+-------+---+-----+-------------------+-------+ | |
2585 | * | opc | 0 1 1 | V | 0 0 | imm19 | Rt | | |
2586 | * +-----+-------+---+-----+-------------------+-------+ | |
2587 | * | |
2588 | * V: 1 -> vector (simd/fp) | |
2589 | * opc (non-vector): 00 -> 32 bit, 01 -> 64 bit, | |
2590 | * 10-> 32 bit signed, 11 -> prefetch | |
2591 | * opc (vector): 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit (11 unallocated) | |
2592 | */ | |
ad7ee8a2 CF |
2593 | static void disas_ld_lit(DisasContext *s, uint32_t insn) |
2594 | { | |
32b64e86 AG |
2595 | int rt = extract32(insn, 0, 5); |
2596 | int64_t imm = sextract32(insn, 5, 19) << 2; | |
2597 | bool is_vector = extract32(insn, 26, 1); | |
2598 | int opc = extract32(insn, 30, 2); | |
2599 | bool is_signed = false; | |
2600 | int size = 2; | |
3a471103 | 2601 | TCGv_i64 tcg_rt, clean_addr; |
32b64e86 AG |
2602 | |
2603 | if (is_vector) { | |
2604 | if (opc == 3) { | |
2605 | unallocated_encoding(s); | |
2606 | return; | |
2607 | } | |
2608 | size = 2 + opc; | |
8c6afa6a PM |
2609 | if (!fp_access_check(s)) { |
2610 | return; | |
2611 | } | |
32b64e86 AG |
2612 | } else { |
2613 | if (opc == 3) { | |
2614 | /* PRFM (literal) : prefetch */ | |
2615 | return; | |
2616 | } | |
2617 | size = 2 + extract32(opc, 0, 1); | |
2618 | is_signed = extract32(opc, 1, 1); | |
2619 | } | |
2620 | ||
2621 | tcg_rt = cpu_reg(s, rt); | |
2622 | ||
43722a6d | 2623 | clean_addr = tcg_const_i64(s->pc_curr + imm); |
32b64e86 | 2624 | if (is_vector) { |
3a471103 | 2625 | do_fp_ld(s, rt, clean_addr, size); |
32b64e86 | 2626 | } else { |
aaa1f954 | 2627 | /* Only unsigned 32bit loads target 32bit registers. */ |
173ff585 | 2628 | bool iss_sf = opc != 0; |
aaa1f954 | 2629 | |
3a471103 | 2630 | do_gpr_ld(s, tcg_rt, clean_addr, size, is_signed, false, |
aaa1f954 | 2631 | true, rt, iss_sf, false); |
32b64e86 | 2632 | } |
3a471103 | 2633 | tcg_temp_free_i64(clean_addr); |
ad7ee8a2 CF |
2634 | } |
2635 | ||
4a08d475 | 2636 | /* |
4ce31af4 PM |
2637 | * LDNP (Load Pair - non-temporal hint) |
2638 | * LDP (Load Pair - non vector) | |
2639 | * LDPSW (Load Pair Signed Word - non vector) | |
2640 | * STNP (Store Pair - non-temporal hint) | |
2641 | * STP (Store Pair - non vector) | |
2642 | * LDNP (Load Pair of SIMD&FP - non-temporal hint) | |
2643 | * LDP (Load Pair of SIMD&FP) | |
2644 | * STNP (Store Pair of SIMD&FP - non-temporal hint) | |
2645 | * STP (Store Pair of SIMD&FP) | |
4a08d475 PM |
2646 | * |
2647 | * 31 30 29 27 26 25 24 23 22 21 15 14 10 9 5 4 0 | |
2648 | * +-----+-------+---+---+-------+---+-----------------------------+ | |
2649 | * | opc | 1 0 1 | V | 0 | index | L | imm7 | Rt2 | Rn | Rt | | |
2650 | * +-----+-------+---+---+-------+---+-------+-------+------+------+ | |
2651 | * | |
2652 | * opc: LDP/STP/LDNP/STNP 00 -> 32 bit, 10 -> 64 bit | |
2653 | * LDPSW 01 | |
2654 | * LDP/STP/LDNP/STNP (SIMD) 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit | |
2655 | * V: 0 -> GPR, 1 -> Vector | |
2656 | * idx: 00 -> signed offset with non-temporal hint, 01 -> post-index, | |
2657 | * 10 -> signed offset, 11 -> pre-index | |
2658 | * L: 0 -> Store 1 -> Load | |
2659 | * | |
2660 | * Rt, Rt2 = GPR or SIMD registers to be stored | |
2661 | * Rn = general purpose register containing address | |
2662 | * imm7 = signed offset (multiple of 4 or 8 depending on size) | |
2663 | */ | |
ad7ee8a2 CF |
2664 | static void disas_ldst_pair(DisasContext *s, uint32_t insn) |
2665 | { | |
4a08d475 PM |
2666 | int rt = extract32(insn, 0, 5); |
2667 | int rn = extract32(insn, 5, 5); | |
2668 | int rt2 = extract32(insn, 10, 5); | |
c2ebd862 | 2669 | uint64_t offset = sextract64(insn, 15, 7); |
4a08d475 PM |
2670 | int index = extract32(insn, 23, 2); |
2671 | bool is_vector = extract32(insn, 26, 1); | |
2672 | bool is_load = extract32(insn, 22, 1); | |
2673 | int opc = extract32(insn, 30, 2); | |
2674 | ||
2675 | bool is_signed = false; | |
2676 | bool postindex = false; | |
2677 | bool wback = false; | |
2678 | ||
3a471103 RH |
2679 | TCGv_i64 clean_addr, dirty_addr; |
2680 | ||
4a08d475 PM |
2681 | int size; |
2682 | ||
2683 | if (opc == 3) { | |
2684 | unallocated_encoding(s); | |
2685 | return; | |
2686 | } | |
2687 | ||
2688 | if (is_vector) { | |
2689 | size = 2 + opc; | |
2690 | } else { | |
2691 | size = 2 + extract32(opc, 1, 1); | |
2692 | is_signed = extract32(opc, 0, 1); | |
2693 | if (!is_load && is_signed) { | |
2694 | unallocated_encoding(s); | |
2695 | return; | |
2696 | } | |
2697 | } | |
2698 | ||
2699 | switch (index) { | |
2700 | case 1: /* post-index */ | |
2701 | postindex = true; | |
2702 | wback = true; | |
2703 | break; | |
2704 | case 0: | |
2705 | /* signed offset with "non-temporal" hint. Since we don't emulate | |
2706 | * caches we don't care about hints to the cache system about | |
2707 | * data access patterns, and handle this identically to plain | |
2708 | * signed offset. | |
2709 | */ | |
2710 | if (is_signed) { | |
2711 | /* There is no non-temporal-hint version of LDPSW */ | |
2712 | unallocated_encoding(s); | |
2713 | return; | |
2714 | } | |
2715 | postindex = false; | |
2716 | break; | |
2717 | case 2: /* signed offset, rn not updated */ | |
2718 | postindex = false; | |
2719 | break; | |
2720 | case 3: /* pre-index */ | |
2721 | postindex = false; | |
2722 | wback = true; | |
2723 | break; | |
2724 | } | |
2725 | ||
8c6afa6a PM |
2726 | if (is_vector && !fp_access_check(s)) { |
2727 | return; | |
2728 | } | |
2729 | ||
4a08d475 PM |
2730 | offset <<= size; |
2731 | ||
2732 | if (rn == 31) { | |
2733 | gen_check_sp_alignment(s); | |
2734 | } | |
2735 | ||
3a471103 | 2736 | dirty_addr = read_cpu_reg_sp(s, rn, 1); |
4a08d475 | 2737 | if (!postindex) { |
3a471103 | 2738 | tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); |
4a08d475 | 2739 | } |
3a471103 | 2740 | clean_addr = clean_data_tbi(s, dirty_addr); |
4a08d475 PM |
2741 | |
2742 | if (is_vector) { | |
2743 | if (is_load) { | |
3a471103 | 2744 | do_fp_ld(s, rt, clean_addr, size); |
4a08d475 | 2745 | } else { |
3a471103 | 2746 | do_fp_st(s, rt, clean_addr, size); |
4a08d475 | 2747 | } |
3a471103 | 2748 | tcg_gen_addi_i64(clean_addr, clean_addr, 1 << size); |
4a08d475 | 2749 | if (is_load) { |
3a471103 | 2750 | do_fp_ld(s, rt2, clean_addr, size); |
4a08d475 | 2751 | } else { |
3a471103 | 2752 | do_fp_st(s, rt2, clean_addr, size); |
4a08d475 PM |
2753 | } |
2754 | } else { | |
3e4d91b9 | 2755 | TCGv_i64 tcg_rt = cpu_reg(s, rt); |
4a08d475 | 2756 | TCGv_i64 tcg_rt2 = cpu_reg(s, rt2); |
3e4d91b9 | 2757 | |
4a08d475 | 2758 | if (is_load) { |
3e4d91b9 RH |
2759 | TCGv_i64 tmp = tcg_temp_new_i64(); |
2760 | ||
2761 | /* Do not modify tcg_rt before recognizing any exception | |
2762 | * from the second load. | |
2763 | */ | |
3a471103 | 2764 | do_gpr_ld(s, tmp, clean_addr, size, is_signed, false, |
3e4d91b9 | 2765 | false, 0, false, false); |
3a471103 RH |
2766 | tcg_gen_addi_i64(clean_addr, clean_addr, 1 << size); |
2767 | do_gpr_ld(s, tcg_rt2, clean_addr, size, is_signed, false, | |
aaa1f954 | 2768 | false, 0, false, false); |
3e4d91b9 RH |
2769 | |
2770 | tcg_gen_mov_i64(tcg_rt, tmp); | |
2771 | tcg_temp_free_i64(tmp); | |
4a08d475 | 2772 | } else { |
3a471103 | 2773 | do_gpr_st(s, tcg_rt, clean_addr, size, |
3e4d91b9 | 2774 | false, 0, false, false); |
3a471103 RH |
2775 | tcg_gen_addi_i64(clean_addr, clean_addr, 1 << size); |
2776 | do_gpr_st(s, tcg_rt2, clean_addr, size, | |
aaa1f954 | 2777 | false, 0, false, false); |
4a08d475 PM |
2778 | } |
2779 | } | |
2780 | ||
2781 | if (wback) { | |
2782 | if (postindex) { | |
3a471103 | 2783 | tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); |
4a08d475 | 2784 | } |
3a471103 | 2785 | tcg_gen_mov_i64(cpu_reg_sp(s, rn), dirty_addr); |
4a08d475 | 2786 | } |
ad7ee8a2 CF |
2787 | } |
2788 | ||
a5e94a9d | 2789 | /* |
4ce31af4 PM |
2790 | * Load/store (immediate post-indexed) |
2791 | * Load/store (immediate pre-indexed) | |
2792 | * Load/store (unscaled immediate) | |
a5e94a9d AB |
2793 | * |
2794 | * 31 30 29 27 26 25 24 23 22 21 20 12 11 10 9 5 4 0 | |
2795 | * +----+-------+---+-----+-----+---+--------+-----+------+------+ | |
2796 | * |size| 1 1 1 | V | 0 0 | opc | 0 | imm9 | idx | Rn | Rt | | |
2797 | * +----+-------+---+-----+-----+---+--------+-----+------+------+ | |
2798 | * | |
2799 | * idx = 01 -> post-indexed, 11 pre-indexed, 00 unscaled imm. (no writeback) | |
60510aed | 2800 | 10 -> unprivileged |
a5e94a9d AB |
2801 | * V = 0 -> non-vector |
2802 | * size: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64bit | |
2803 | * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32 | |
2804 | */ | |
cd694521 EI |
2805 | static void disas_ldst_reg_imm9(DisasContext *s, uint32_t insn, |
2806 | int opc, | |
2807 | int size, | |
2808 | int rt, | |
2809 | bool is_vector) | |
a5e94a9d | 2810 | { |
a5e94a9d AB |
2811 | int rn = extract32(insn, 5, 5); |
2812 | int imm9 = sextract32(insn, 12, 9); | |
a5e94a9d AB |
2813 | int idx = extract32(insn, 10, 2); |
2814 | bool is_signed = false; | |
2815 | bool is_store = false; | |
2816 | bool is_extended = false; | |
60510aed | 2817 | bool is_unpriv = (idx == 2); |
aaa1f954 | 2818 | bool iss_valid = !is_vector; |
a5e94a9d AB |
2819 | bool post_index; |
2820 | bool writeback; | |
2821 | ||
3a471103 | 2822 | TCGv_i64 clean_addr, dirty_addr; |
a5e94a9d AB |
2823 | |
2824 | if (is_vector) { | |
2825 | size |= (opc & 2) << 1; | |
60510aed | 2826 | if (size > 4 || is_unpriv) { |
a5e94a9d AB |
2827 | unallocated_encoding(s); |
2828 | return; | |
2829 | } | |
2830 | is_store = ((opc & 1) == 0); | |
8c6afa6a PM |
2831 | if (!fp_access_check(s)) { |
2832 | return; | |
2833 | } | |
a5e94a9d AB |
2834 | } else { |
2835 | if (size == 3 && opc == 2) { | |
2836 | /* PRFM - prefetch */ | |
a80c4256 | 2837 | if (idx != 0) { |
60510aed PM |
2838 | unallocated_encoding(s); |
2839 | return; | |
2840 | } | |
a5e94a9d AB |
2841 | return; |
2842 | } | |
2843 | if (opc == 3 && size > 1) { | |
2844 | unallocated_encoding(s); | |
2845 | return; | |
2846 | } | |
2847 | is_store = (opc == 0); | |
026a19c3 EI |
2848 | is_signed = extract32(opc, 1, 1); |
2849 | is_extended = (size < 3) && extract32(opc, 0, 1); | |
a5e94a9d AB |
2850 | } |
2851 | ||
2852 | switch (idx) { | |
2853 | case 0: | |
60510aed | 2854 | case 2: |
a5e94a9d AB |
2855 | post_index = false; |
2856 | writeback = false; | |
2857 | break; | |
2858 | case 1: | |
2859 | post_index = true; | |
2860 | writeback = true; | |
2861 | break; | |
2862 | case 3: | |
2863 | post_index = false; | |
2864 | writeback = true; | |
2865 | break; | |
5ca66278 EC |
2866 | default: |
2867 | g_assert_not_reached(); | |
a5e94a9d AB |
2868 | } |
2869 | ||
2870 | if (rn == 31) { | |
2871 | gen_check_sp_alignment(s); | |
2872 | } | |
a5e94a9d | 2873 | |
3a471103 | 2874 | dirty_addr = read_cpu_reg_sp(s, rn, 1); |
a5e94a9d | 2875 | if (!post_index) { |
3a471103 | 2876 | tcg_gen_addi_i64(dirty_addr, dirty_addr, imm9); |
a5e94a9d | 2877 | } |
3a471103 | 2878 | clean_addr = clean_data_tbi(s, dirty_addr); |
a5e94a9d AB |
2879 | |
2880 | if (is_vector) { | |
2881 | if (is_store) { | |
3a471103 | 2882 | do_fp_st(s, rt, clean_addr, size); |
a5e94a9d | 2883 | } else { |
3a471103 | 2884 | do_fp_ld(s, rt, clean_addr, size); |
a5e94a9d AB |
2885 | } |
2886 | } else { | |
2887 | TCGv_i64 tcg_rt = cpu_reg(s, rt); | |
579d21cc | 2888 | int memidx = is_unpriv ? get_a64_user_mem_index(s) : get_mem_index(s); |
aaa1f954 | 2889 | bool iss_sf = disas_ldst_compute_iss_sf(size, is_signed, opc); |
60510aed | 2890 | |
a5e94a9d | 2891 | if (is_store) { |
3a471103 | 2892 | do_gpr_st_memidx(s, tcg_rt, clean_addr, size, memidx, |
aaa1f954 | 2893 | iss_valid, rt, iss_sf, false); |
a5e94a9d | 2894 | } else { |
3a471103 | 2895 | do_gpr_ld_memidx(s, tcg_rt, clean_addr, size, |
aaa1f954 EI |
2896 | is_signed, is_extended, memidx, |
2897 | iss_valid, rt, iss_sf, false); | |
a5e94a9d AB |
2898 | } |
2899 | } | |
2900 | ||
2901 | if (writeback) { | |
2902 | TCGv_i64 tcg_rn = cpu_reg_sp(s, rn); | |
2903 | if (post_index) { | |
3a471103 | 2904 | tcg_gen_addi_i64(dirty_addr, dirty_addr, imm9); |
a5e94a9d | 2905 | } |
3a471103 | 2906 | tcg_gen_mov_i64(tcg_rn, dirty_addr); |
a5e94a9d AB |
2907 | } |
2908 | } | |
2909 | ||
229b7a05 | 2910 | /* |
4ce31af4 | 2911 | * Load/store (register offset) |
229b7a05 AB |
2912 | * |
2913 | * 31 30 29 27 26 25 24 23 22 21 20 16 15 13 12 11 10 9 5 4 0 | |
2914 | * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+ | |
2915 | * |size| 1 1 1 | V | 0 0 | opc | 1 | Rm | opt | S| 1 0 | Rn | Rt | | |
2916 | * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+ | |
2917 | * | |
2918 | * For non-vector: | |
2919 | * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit | |
2920 | * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32 | |
2921 | * For vector: | |
2922 | * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated | |
2923 | * opc<0>: 0 -> store, 1 -> load | |
2924 | * V: 1 -> vector/simd | |
2925 | * opt: extend encoding (see DecodeRegExtend) | |
2926 | * S: if S=1 then scale (essentially index by sizeof(size)) | |
2927 | * Rt: register to transfer into/out of | |
2928 | * Rn: address register or SP for base | |
2929 | * Rm: offset register or ZR for offset | |
2930 | */ | |
cd694521 EI |
2931 | static void disas_ldst_reg_roffset(DisasContext *s, uint32_t insn, |
2932 | int opc, | |
2933 | int size, | |
2934 | int rt, | |
2935 | bool is_vector) | |
229b7a05 | 2936 | { |
229b7a05 AB |
2937 | int rn = extract32(insn, 5, 5); |
2938 | int shift = extract32(insn, 12, 1); | |
2939 | int rm = extract32(insn, 16, 5); | |
229b7a05 | 2940 | int opt = extract32(insn, 13, 3); |
229b7a05 AB |
2941 | bool is_signed = false; |
2942 | bool is_store = false; | |
2943 | bool is_extended = false; | |
229b7a05 | 2944 | |
3a471103 | 2945 | TCGv_i64 tcg_rm, clean_addr, dirty_addr; |
229b7a05 AB |
2946 | |
2947 | if (extract32(opt, 1, 1) == 0) { | |
2948 | unallocated_encoding(s); | |
2949 | return; | |
2950 | } | |
2951 | ||
2952 | if (is_vector) { | |
2953 | size |= (opc & 2) << 1; | |
2954 | if (size > 4) { | |
2955 | unallocated_encoding(s); | |
2956 | return; | |
2957 | } | |
2958 | is_store = !extract32(opc, 0, 1); | |
8c6afa6a PM |
2959 | if (!fp_access_check(s)) { |
2960 | return; | |
2961 | } | |
229b7a05 AB |
2962 | } else { |
2963 | if (size == 3 && opc == 2) { | |
2964 | /* PRFM - prefetch */ | |
2965 | return; | |
2966 | } | |
2967 | if (opc == 3 && size > 1) { | |
2968 | unallocated_encoding(s); | |
2969 | return; | |
2970 | } | |
2971 | is_store = (opc == 0); | |
2972 | is_signed = extract32(opc, 1, 1); | |
2973 | is_extended = (size < 3) && extract32(opc, 0, 1); | |
2974 | } | |
2975 | ||
2976 | if (rn == 31) { | |
2977 | gen_check_sp_alignment(s); | |
2978 | } | |
3a471103 | 2979 | dirty_addr = read_cpu_reg_sp(s, rn, 1); |
229b7a05 AB |
2980 | |
2981 | tcg_rm = read_cpu_reg(s, rm, 1); | |
2982 | ext_and_shift_reg(tcg_rm, tcg_rm, opt, shift ? size : 0); | |
2983 | ||
3a471103 RH |
2984 | tcg_gen_add_i64(dirty_addr, dirty_addr, tcg_rm); |
2985 | clean_addr = clean_data_tbi(s, dirty_addr); | |
229b7a05 AB |
2986 | |
2987 | if (is_vector) { | |
2988 | if (is_store) { | |
3a471103 | 2989 | do_fp_st(s, rt, clean_addr, size); |
229b7a05 | 2990 | } else { |
3a471103 | 2991 | do_fp_ld(s, rt, clean_addr, size); |
229b7a05 AB |
2992 | } |
2993 | } else { | |
2994 | TCGv_i64 tcg_rt = cpu_reg(s, rt); | |
aaa1f954 | 2995 | bool iss_sf = disas_ldst_compute_iss_sf(size, is_signed, opc); |
229b7a05 | 2996 | if (is_store) { |
3a471103 | 2997 | do_gpr_st(s, tcg_rt, clean_addr, size, |
aaa1f954 | 2998 | true, rt, iss_sf, false); |
229b7a05 | 2999 | } else { |
3a471103 | 3000 | do_gpr_ld(s, tcg_rt, clean_addr, size, |
aaa1f954 EI |
3001 | is_signed, is_extended, |
3002 | true, rt, iss_sf, false); | |
229b7a05 AB |
3003 | } |
3004 | } | |
3005 | } | |
3006 | ||
d5612f10 | 3007 | /* |
4ce31af4 | 3008 | * Load/store (unsigned immediate) |
d5612f10 AB |
3009 | * |
3010 | * 31 30 29 27 26 25 24 23 22 21 10 9 5 | |
3011 | * +----+-------+---+-----+-----+------------+-------+------+ | |
3012 | * |size| 1 1 1 | V | 0 1 | opc | imm12 | Rn | Rt | | |
3013 | * +----+-------+---+-----+-----+------------+-------+------+ | |
3014 | * | |
3015 | * For non-vector: | |
3016 | * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit | |
3017 | * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32 | |
3018 | * For vector: | |
3019 | * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated | |
3020 | * opc<0>: 0 -> store, 1 -> load | |
3021 | * Rn: base address register (inc SP) | |
3022 | * Rt: target register | |
3023 | */ | |
cd694521 EI |
3024 | static void disas_ldst_reg_unsigned_imm(DisasContext *s, uint32_t insn, |
3025 | int opc, | |
3026 | int size, | |
3027 | int rt, | |
3028 | bool is_vector) | |
d5612f10 | 3029 | { |
d5612f10 AB |
3030 | int rn = extract32(insn, 5, 5); |
3031 | unsigned int imm12 = extract32(insn, 10, 12); | |
d5612f10 AB |
3032 | unsigned int offset; |
3033 | ||
3a471103 | 3034 | TCGv_i64 clean_addr, dirty_addr; |
d5612f10 AB |
3035 | |
3036 | bool is_store; | |
3037 | bool is_signed = false; | |
3038 | bool is_extended = false; | |
3039 | ||
3040 | if (is_vector) { | |
3041 | size |= (opc & 2) << 1; | |
3042 | if (size > 4) { | |
3043 | unallocated_encoding(s); | |
3044 | return; | |
3045 | } | |
3046 | is_store = !extract32(opc, 0, 1); | |
8c6afa6a PM |
3047 | if (!fp_access_check(s)) { |
3048 | return; | |
3049 | } | |
d5612f10 AB |
3050 | } else { |
3051 | if (size == 3 && opc == 2) { | |
3052 | /* PRFM - prefetch */ | |
3053 | return; | |
3054 | } | |
3055 | if (opc == 3 && size > 1) { | |
3056 | unallocated_encoding(s); | |
3057 | return; | |
3058 | } | |
3059 | is_store = (opc == 0); | |
3060 | is_signed = extract32(opc, 1, 1); | |
3061 | is_extended = (size < 3) && extract32(opc, 0, 1); | |
3062 | } | |
3063 | ||
3064 | if (rn == 31) { | |
3065 | gen_check_sp_alignment(s); | |
3066 | } | |
3a471103 | 3067 | dirty_addr = read_cpu_reg_sp(s, rn, 1); |
d5612f10 | 3068 | offset = imm12 << size; |
3a471103 RH |
3069 | tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); |
3070 | clean_addr = clean_data_tbi(s, dirty_addr); | |
d5612f10 AB |
3071 | |
3072 | if (is_vector) { | |
3073 | if (is_store) { | |
3a471103 | 3074 | do_fp_st(s, rt, clean_addr, size); |
d5612f10 | 3075 | } else { |
3a471103 | 3076 | do_fp_ld(s, rt, clean_addr, size); |
d5612f10 AB |
3077 | } |
3078 | } else { | |
3079 | TCGv_i64 tcg_rt = cpu_reg(s, rt); | |
aaa1f954 | 3080 | bool iss_sf = disas_ldst_compute_iss_sf(size, is_signed, opc); |
d5612f10 | 3081 | if (is_store) { |
3a471103 | 3082 | do_gpr_st(s, tcg_rt, clean_addr, size, |
aaa1f954 | 3083 | true, rt, iss_sf, false); |
d5612f10 | 3084 | } else { |
3a471103 | 3085 | do_gpr_ld(s, tcg_rt, clean_addr, size, is_signed, is_extended, |
aaa1f954 | 3086 | true, rt, iss_sf, false); |
d5612f10 AB |
3087 | } |
3088 | } | |
3089 | } | |
3090 | ||
68412d2e RH |
3091 | /* Atomic memory operations |
3092 | * | |
3093 | * 31 30 27 26 24 22 21 16 15 12 10 5 0 | |
3094 | * +------+-------+---+-----+-----+---+----+----+-----+-----+----+-----+ | |
3095 | * | size | 1 1 1 | V | 0 0 | A R | 1 | Rs | o3 | opc | 0 0 | Rn | Rt | | |
3096 | * +------+-------+---+-----+-----+--------+----+-----+-----+----+-----+ | |
3097 | * | |
3098 | * Rt: the result register | |
3099 | * Rn: base address or SP | |
3100 | * Rs: the source register for the operation | |
3101 | * V: vector flag (always 0 as of v8.3) | |
3102 | * A: acquire flag | |
3103 | * R: release flag | |
3104 | */ | |
3105 | static void disas_ldst_atomic(DisasContext *s, uint32_t insn, | |
3106 | int size, int rt, bool is_vector) | |
3107 | { | |
3108 | int rs = extract32(insn, 16, 5); | |
3109 | int rn = extract32(insn, 5, 5); | |
3110 | int o3_opc = extract32(insn, 12, 4); | |
2677cf9f PM |
3111 | bool r = extract32(insn, 22, 1); |
3112 | bool a = extract32(insn, 23, 1); | |
3a471103 | 3113 | TCGv_i64 tcg_rs, clean_addr; |
74608ea4 | 3114 | AtomicThreeOpFn *fn; |
68412d2e | 3115 | |
962fcbf2 | 3116 | if (is_vector || !dc_isar_feature(aa64_atomics, s)) { |
68412d2e RH |
3117 | unallocated_encoding(s); |
3118 | return; | |
3119 | } | |
3120 | switch (o3_opc) { | |
3121 | case 000: /* LDADD */ | |
74608ea4 RH |
3122 | fn = tcg_gen_atomic_fetch_add_i64; |
3123 | break; | |
68412d2e | 3124 | case 001: /* LDCLR */ |
74608ea4 RH |
3125 | fn = tcg_gen_atomic_fetch_and_i64; |
3126 | break; | |
68412d2e | 3127 | case 002: /* LDEOR */ |
74608ea4 RH |
3128 | fn = tcg_gen_atomic_fetch_xor_i64; |
3129 | break; | |
68412d2e | 3130 | case 003: /* LDSET */ |
74608ea4 RH |
3131 | fn = tcg_gen_atomic_fetch_or_i64; |
3132 | break; | |
68412d2e | 3133 | case 004: /* LDSMAX */ |
74608ea4 RH |
3134 | fn = tcg_gen_atomic_fetch_smax_i64; |
3135 | break; | |
68412d2e | 3136 | case 005: /* LDSMIN */ |
74608ea4 RH |
3137 | fn = tcg_gen_atomic_fetch_smin_i64; |
3138 | break; | |
68412d2e | 3139 | case 006: /* LDUMAX */ |
74608ea4 RH |
3140 | fn = tcg_gen_atomic_fetch_umax_i64; |
3141 | break; | |
68412d2e | 3142 | case 007: /* LDUMIN */ |
74608ea4 RH |
3143 | fn = tcg_gen_atomic_fetch_umin_i64; |
3144 | break; | |
68412d2e | 3145 | case 010: /* SWP */ |
74608ea4 RH |
3146 | fn = tcg_gen_atomic_xchg_i64; |
3147 | break; | |
2677cf9f PM |
3148 | case 014: /* LDAPR, LDAPRH, LDAPRB */ |
3149 | if (!dc_isar_feature(aa64_rcpc_8_3, s) || | |
3150 | rs != 31 || a != 1 || r != 0) { | |
3151 | unallocated_encoding(s); | |
3152 | return; | |
3153 | } | |
3154 | break; | |
68412d2e RH |
3155 | default: |
3156 | unallocated_encoding(s); | |
3157 | return; | |
3158 | } | |
68412d2e | 3159 | |
74608ea4 RH |
3160 | if (rn == 31) { |
3161 | gen_check_sp_alignment(s); | |
3162 | } | |
3a471103 | 3163 | clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn)); |
2677cf9f PM |
3164 | |
3165 | if (o3_opc == 014) { | |
3166 | /* | |
3167 | * LDAPR* are a special case because they are a simple load, not a | |
3168 | * fetch-and-do-something op. | |
3169 | * The architectural consistency requirements here are weaker than | |
3170 | * full load-acquire (we only need "load-acquire processor consistent"), | |
3171 | * but we choose to implement them as full LDAQ. | |
3172 | */ | |
3173 | do_gpr_ld(s, cpu_reg(s, rt), clean_addr, size, false, false, | |
3174 | true, rt, disas_ldst_compute_iss_sf(size, false, 0), true); | |
3175 | tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); | |
3176 | return; | |
3177 | } | |
3178 | ||
74608ea4 RH |
3179 | tcg_rs = read_cpu_reg(s, rs, true); |
3180 | ||
3181 | if (o3_opc == 1) { /* LDCLR */ | |
3182 | tcg_gen_not_i64(tcg_rs, tcg_rs); | |
3183 | } | |
3184 | ||
3185 | /* The tcg atomic primitives are all full barriers. Therefore we | |
3186 | * can ignore the Acquire and Release bits of this instruction. | |
3187 | */ | |
3a471103 | 3188 | fn(cpu_reg(s, rt), clean_addr, tcg_rs, get_mem_index(s), |
74608ea4 | 3189 | s->be_data | size | MO_ALIGN); |
68412d2e RH |
3190 | } |
3191 | ||
bd889f48 RH |
3192 | /* |
3193 | * PAC memory operations | |
3194 | * | |
3195 | * 31 30 27 26 24 22 21 12 11 10 5 0 | |
3196 | * +------+-------+---+-----+-----+---+--------+---+---+----+-----+ | |
3197 | * | size | 1 1 1 | V | 0 0 | M S | 1 | imm9 | W | 1 | Rn | Rt | | |
3198 | * +------+-------+---+-----+-----+---+--------+---+---+----+-----+ | |
3199 | * | |
3200 | * Rt: the result register | |
3201 | * Rn: base address or SP | |
3202 | * V: vector flag (always 0 as of v8.3) | |
3203 | * M: clear for key DA, set for key DB | |
3204 | * W: pre-indexing flag | |
3205 | * S: sign for imm9. | |
3206 | */ | |
3207 | static void disas_ldst_pac(DisasContext *s, uint32_t insn, | |
3208 | int size, int rt, bool is_vector) | |
3209 | { | |
3210 | int rn = extract32(insn, 5, 5); | |
3211 | bool is_wback = extract32(insn, 11, 1); | |
3212 | bool use_key_a = !extract32(insn, 23, 1); | |
3213 | int offset; | |
3a471103 | 3214 | TCGv_i64 clean_addr, dirty_addr, tcg_rt; |
bd889f48 RH |
3215 | |
3216 | if (size != 3 || is_vector || !dc_isar_feature(aa64_pauth, s)) { | |
3217 | unallocated_encoding(s); | |
3218 | return; | |
3219 | } | |
3220 | ||
3221 | if (rn == 31) { | |
3222 | gen_check_sp_alignment(s); | |
3223 | } | |
3a471103 | 3224 | dirty_addr = read_cpu_reg_sp(s, rn, 1); |
bd889f48 RH |
3225 | |
3226 | if (s->pauth_active) { | |
3227 | if (use_key_a) { | |
3a471103 | 3228 | gen_helper_autda(dirty_addr, cpu_env, dirty_addr, cpu_X[31]); |
bd889f48 | 3229 | } else { |
3a471103 | 3230 | gen_helper_autdb(dirty_addr, cpu_env, dirty_addr, cpu_X[31]); |
bd889f48 RH |
3231 | } |
3232 | } | |
3233 | ||
3234 | /* Form the 10-bit signed, scaled offset. */ | |
3235 | offset = (extract32(insn, 22, 1) << 9) | extract32(insn, 12, 9); | |
3236 | offset = sextract32(offset << size, 0, 10 + size); | |
3a471103 | 3237 | tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); |
bd889f48 | 3238 | |
3a471103 RH |
3239 | /* Note that "clean" and "dirty" here refer to TBI not PAC. */ |
3240 | clean_addr = clean_data_tbi(s, dirty_addr); | |
bd889f48 | 3241 | |
3a471103 RH |
3242 | tcg_rt = cpu_reg(s, rt); |
3243 | do_gpr_ld(s, tcg_rt, clean_addr, size, /* is_signed */ false, | |
bd889f48 RH |
3244 | /* extend */ false, /* iss_valid */ !is_wback, |
3245 | /* iss_srt */ rt, /* iss_sf */ true, /* iss_ar */ false); | |
3246 | ||
3247 | if (is_wback) { | |
3a471103 | 3248 | tcg_gen_mov_i64(cpu_reg_sp(s, rn), dirty_addr); |
bd889f48 RH |
3249 | } |
3250 | } | |
3251 | ||
a1229109 PM |
3252 | /* |
3253 | * LDAPR/STLR (unscaled immediate) | |
3254 | * | |
3255 | * 31 30 24 22 21 12 10 5 0 | |
3256 | * +------+-------------+-----+---+--------+-----+----+-----+ | |
3257 | * | size | 0 1 1 0 0 1 | opc | 0 | imm9 | 0 0 | Rn | Rt | | |
3258 | * +------+-------------+-----+---+--------+-----+----+-----+ | |
3259 | * | |
3260 | * Rt: source or destination register | |
3261 | * Rn: base register | |
3262 | * imm9: unscaled immediate offset | |
3263 | * opc: 00: STLUR*, 01/10/11: various LDAPUR* | |
3264 | * size: size of load/store | |
3265 | */ | |
3266 | static void disas_ldst_ldapr_stlr(DisasContext *s, uint32_t insn) | |
3267 | { | |
3268 | int rt = extract32(insn, 0, 5); | |
3269 | int rn = extract32(insn, 5, 5); | |
3270 | int offset = sextract32(insn, 12, 9); | |
3271 | int opc = extract32(insn, 22, 2); | |
3272 | int size = extract32(insn, 30, 2); | |
3273 | TCGv_i64 clean_addr, dirty_addr; | |
3274 | bool is_store = false; | |
3275 | bool is_signed = false; | |
3276 | bool extend = false; | |
3277 | bool iss_sf; | |
3278 | ||
3279 | if (!dc_isar_feature(aa64_rcpc_8_4, s)) { | |
3280 | unallocated_encoding(s); | |
3281 | return; | |
3282 | } | |
3283 | ||
3284 | switch (opc) { | |
3285 | case 0: /* STLURB */ | |
3286 | is_store = true; | |
3287 | break; | |
3288 | case 1: /* LDAPUR* */ | |
3289 | break; | |
3290 | case 2: /* LDAPURS* 64-bit variant */ | |
3291 | if (size == 3) { | |
3292 | unallocated_encoding(s); | |
3293 | return; | |
3294 | } | |
3295 | is_signed = true; | |
3296 | break; | |
3297 | case 3: /* LDAPURS* 32-bit variant */ | |
3298 | if (size > 1) { | |
3299 | unallocated_encoding(s); | |
3300 | return; | |
3301 | } | |
3302 | is_signed = true; | |
3303 | extend = true; /* zero-extend 32->64 after signed load */ | |
3304 | break; | |
3305 | default: | |
3306 | g_assert_not_reached(); | |
3307 | } | |
3308 | ||
3309 | iss_sf = disas_ldst_compute_iss_sf(size, is_signed, opc); | |
3310 | ||
3311 | if (rn == 31) { | |
3312 | gen_check_sp_alignment(s); | |
3313 | } | |
3314 | ||
3315 | dirty_addr = read_cpu_reg_sp(s, rn, 1); | |
3316 | tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); | |
3317 | clean_addr = clean_data_tbi(s, dirty_addr); | |
3318 | ||
3319 | if (is_store) { | |
3320 | /* Store-Release semantics */ | |
3321 | tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); | |
3322 | do_gpr_st(s, cpu_reg(s, rt), clean_addr, size, true, rt, iss_sf, true); | |
3323 | } else { | |
3324 | /* | |
3325 | * Load-AcquirePC semantics; we implement as the slightly more | |
3326 | * restrictive Load-Acquire. | |
3327 | */ | |
3328 | do_gpr_ld(s, cpu_reg(s, rt), clean_addr, size, is_signed, extend, | |
3329 | true, rt, iss_sf, true); | |
3330 | tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); | |
3331 | } | |
3332 | } | |
3333 | ||
ad7ee8a2 CF |
3334 | /* Load/store register (all forms) */ |
3335 | static void disas_ldst_reg(DisasContext *s, uint32_t insn) | |
3336 | { | |
cd694521 EI |
3337 | int rt = extract32(insn, 0, 5); |
3338 | int opc = extract32(insn, 22, 2); | |
3339 | bool is_vector = extract32(insn, 26, 1); | |
3340 | int size = extract32(insn, 30, 2); | |
3341 | ||
d5612f10 AB |
3342 | switch (extract32(insn, 24, 2)) { |
3343 | case 0: | |
68412d2e | 3344 | if (extract32(insn, 21, 1) == 0) { |
60510aed PM |
3345 | /* Load/store register (unscaled immediate) |
3346 | * Load/store immediate pre/post-indexed | |
3347 | * Load/store register unprivileged | |
3348 | */ | |
cd694521 | 3349 | disas_ldst_reg_imm9(s, insn, opc, size, rt, is_vector); |
68412d2e RH |
3350 | return; |
3351 | } | |
3352 | switch (extract32(insn, 10, 2)) { | |
3353 | case 0: | |
3354 | disas_ldst_atomic(s, insn, size, rt, is_vector); | |
3355 | return; | |
3356 | case 2: | |
3357 | disas_ldst_reg_roffset(s, insn, opc, size, rt, is_vector); | |
3358 | return; | |
bd889f48 RH |
3359 | default: |
3360 | disas_ldst_pac(s, insn, size, rt, is_vector); | |
3361 | return; | |
229b7a05 | 3362 | } |
d5612f10 AB |
3363 | break; |
3364 | case 1: | |
cd694521 | 3365 | disas_ldst_reg_unsigned_imm(s, insn, opc, size, rt, is_vector); |
68412d2e | 3366 | return; |
d5612f10 | 3367 | } |
68412d2e | 3368 | unallocated_encoding(s); |
ad7ee8a2 CF |
3369 | } |
3370 | ||
4ce31af4 | 3371 | /* AdvSIMD load/store multiple structures |
72430bf5 AB |
3372 | * |
3373 | * 31 30 29 23 22 21 16 15 12 11 10 9 5 4 0 | |
3374 | * +---+---+---------------+---+-------------+--------+------+------+------+ | |
3375 | * | 0 | Q | 0 0 1 1 0 0 0 | L | 0 0 0 0 0 0 | opcode | size | Rn | Rt | | |
3376 | * +---+---+---------------+---+-------------+--------+------+------+------+ | |
3377 | * | |
4ce31af4 | 3378 | * AdvSIMD load/store multiple structures (post-indexed) |
72430bf5 AB |
3379 | * |
3380 | * 31 30 29 23 22 21 20 16 15 12 11 10 9 5 4 0 | |
3381 | * +---+---+---------------+---+---+---------+--------+------+------+------+ | |
3382 | * | 0 | Q | 0 0 1 1 0 0 1 | L | 0 | Rm | opcode | size | Rn | Rt | | |
3383 | * +---+---+---------------+---+---+---------+--------+------+------+------+ | |
3384 | * | |
3385 | * Rt: first (or only) SIMD&FP register to be transferred | |
3386 | * Rn: base address or SP | |
3387 | * Rm (post-index only): post-index register (when !31) or size dependent #imm | |
3388 | */ | |
ad7ee8a2 CF |
3389 | static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn) |
3390 | { | |
72430bf5 AB |
3391 | int rt = extract32(insn, 0, 5); |
3392 | int rn = extract32(insn, 5, 5); | |
e1f22081 | 3393 | int rm = extract32(insn, 16, 5); |
72430bf5 AB |
3394 | int size = extract32(insn, 10, 2); |
3395 | int opcode = extract32(insn, 12, 4); | |
3396 | bool is_store = !extract32(insn, 22, 1); | |
3397 | bool is_postidx = extract32(insn, 23, 1); | |
3398 | bool is_q = extract32(insn, 30, 1); | |
3a471103 | 3399 | TCGv_i64 clean_addr, tcg_rn, tcg_ebytes; |
14776ab5 | 3400 | MemOp endian = s->be_data; |
72430bf5 | 3401 | |
87f9a7f0 RH |
3402 | int ebytes; /* bytes per element */ |
3403 | int elements; /* elements per vector */ | |
72430bf5 AB |
3404 | int rpt; /* num iterations */ |
3405 | int selem; /* structure elements */ | |
3406 | int r; | |
3407 | ||
3408 | if (extract32(insn, 31, 1) || extract32(insn, 21, 1)) { | |
3409 | unallocated_encoding(s); | |
3410 | return; | |
3411 | } | |
3412 | ||
e1f22081 PM |
3413 | if (!is_postidx && rm != 0) { |
3414 | unallocated_encoding(s); | |
3415 | return; | |
3416 | } | |
3417 | ||
72430bf5 AB |
3418 | /* From the shared decode logic */ |
3419 | switch (opcode) { | |
3420 | case 0x0: | |
3421 | rpt = 1; | |
3422 | selem = 4; | |
3423 | break; | |
3424 | case 0x2: | |
3425 | rpt = 4; | |
3426 | selem = 1; | |
3427 | break; | |
3428 | case 0x4: | |
3429 | rpt = 1; | |
3430 | selem = 3; | |
3431 | break; | |
3432 | case 0x6: | |
3433 | rpt = 3; | |
3434 | selem = 1; | |
3435 | break; | |
3436 | case 0x7: | |
3437 | rpt = 1; | |
3438 | selem = 1; | |
3439 | break; | |
3440 | case 0x8: | |
3441 | rpt = 1; | |
3442 | selem = 2; | |
3443 | break; | |
3444 | case 0xa: | |
3445 | rpt = 2; | |
3446 | selem = 1; | |
3447 | break; | |
3448 | default: | |
3449 | unallocated_encoding(s); | |
3450 | return; | |
3451 | } | |
3452 | ||
3453 | if (size == 3 && !is_q && selem != 1) { | |
3454 | /* reserved */ | |
3455 | unallocated_encoding(s); | |
3456 | return; | |
3457 | } | |
3458 | ||
8c6afa6a PM |
3459 | if (!fp_access_check(s)) { |
3460 | return; | |
3461 | } | |
3462 | ||
72430bf5 AB |
3463 | if (rn == 31) { |
3464 | gen_check_sp_alignment(s); | |
3465 | } | |
3466 | ||
87f9a7f0 RH |
3467 | /* For our purposes, bytes are always little-endian. */ |
3468 | if (size == 0) { | |
3469 | endian = MO_LE; | |
3470 | } | |
3471 | ||
3472 | /* Consecutive little-endian elements from a single register | |
3473 | * can be promoted to a larger little-endian operation. | |
3474 | */ | |
3475 | if (selem == 1 && endian == MO_LE) { | |
3476 | size = 3; | |
3477 | } | |
3478 | ebytes = 1 << size; | |
3479 | elements = (is_q ? 16 : 8) / ebytes; | |
3480 | ||
72430bf5 | 3481 | tcg_rn = cpu_reg_sp(s, rn); |
3a471103 | 3482 | clean_addr = clean_data_tbi(s, tcg_rn); |
a7d8143a | 3483 | tcg_ebytes = tcg_const_i64(ebytes); |
72430bf5 AB |
3484 | |
3485 | for (r = 0; r < rpt; r++) { | |
3486 | int e; | |
3487 | for (e = 0; e < elements; e++) { | |
72430bf5 AB |
3488 | int xs; |
3489 | for (xs = 0; xs < selem; xs++) { | |
87f9a7f0 | 3490 | int tt = (rt + r + xs) % 32; |
72430bf5 | 3491 | if (is_store) { |
3a471103 | 3492 | do_vec_st(s, tt, e, clean_addr, size, endian); |
72430bf5 | 3493 | } else { |
3a471103 | 3494 | do_vec_ld(s, tt, e, clean_addr, size, endian); |
72430bf5 | 3495 | } |
3a471103 | 3496 | tcg_gen_add_i64(clean_addr, clean_addr, tcg_ebytes); |
72430bf5 AB |
3497 | } |
3498 | } | |
3499 | } | |
3a471103 | 3500 | tcg_temp_free_i64(tcg_ebytes); |
72430bf5 | 3501 | |
87f9a7f0 RH |
3502 | if (!is_store) { |
3503 | /* For non-quad operations, setting a slice of the low | |
3504 | * 64 bits of the register clears the high 64 bits (in | |
3505 | * the ARM ARM pseudocode this is implicit in the fact | |
3506 | * that 'rval' is a 64 bit wide variable). | |
3507 | * For quad operations, we might still need to zero the | |
3508 | * high bits of SVE. | |
3509 | */ | |
3510 | for (r = 0; r < rpt * selem; r++) { | |
3511 | int tt = (rt + r) % 32; | |
3512 | clear_vec_high(s, is_q, tt); | |
3513 | } | |
3514 | } | |
3515 | ||
72430bf5 | 3516 | if (is_postidx) { |
72430bf5 | 3517 | if (rm == 31) { |
3a471103 | 3518 | tcg_gen_addi_i64(tcg_rn, tcg_rn, rpt * elements * selem * ebytes); |
72430bf5 AB |
3519 | } else { |
3520 | tcg_gen_add_i64(tcg_rn, tcg_rn, cpu_reg(s, rm)); | |
3521 | } | |
3522 | } | |
ad7ee8a2 CF |
3523 | } |
3524 | ||
4ce31af4 | 3525 | /* AdvSIMD load/store single structure |
df54e47d PM |
3526 | * |
3527 | * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0 | |
3528 | * +---+---+---------------+-----+-----------+-----+---+------+------+------+ | |
3529 | * | 0 | Q | 0 0 1 1 0 1 0 | L R | 0 0 0 0 0 | opc | S | size | Rn | Rt | | |
3530 | * +---+---+---------------+-----+-----------+-----+---+------+------+------+ | |
3531 | * | |
4ce31af4 | 3532 | * AdvSIMD load/store single structure (post-indexed) |
df54e47d PM |
3533 | * |
3534 | * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0 | |
3535 | * +---+---+---------------+-----+-----------+-----+---+------+------+------+ | |
3536 | * | 0 | Q | 0 0 1 1 0 1 1 | L R | Rm | opc | S | size | Rn | Rt | | |
3537 | * +---+---+---------------+-----+-----------+-----+---+------+------+------+ | |
3538 | * | |
3539 | * Rt: first (or only) SIMD&FP register to be transferred | |
3540 | * Rn: base address or SP | |
3541 | * Rm (post-index only): post-index register (when !31) or size dependent #imm | |
3542 | * index = encoded in Q:S:size dependent on size | |
3543 | * | |
3544 | * lane_size = encoded in R, opc | |
3545 | * transfer width = encoded in opc, S, size | |
3546 | */ | |
ad7ee8a2 CF |
3547 | static void disas_ldst_single_struct(DisasContext *s, uint32_t insn) |
3548 | { | |
df54e47d PM |
3549 | int rt = extract32(insn, 0, 5); |
3550 | int rn = extract32(insn, 5, 5); | |
9c72b68a | 3551 | int rm = extract32(insn, 16, 5); |
df54e47d PM |
3552 | int size = extract32(insn, 10, 2); |
3553 | int S = extract32(insn, 12, 1); | |
3554 | int opc = extract32(insn, 13, 3); | |
3555 | int R = extract32(insn, 21, 1); | |
3556 | int is_load = extract32(insn, 22, 1); | |
3557 | int is_postidx = extract32(insn, 23, 1); | |
3558 | int is_q = extract32(insn, 30, 1); | |
3559 | ||
3560 | int scale = extract32(opc, 1, 2); | |
3561 | int selem = (extract32(opc, 0, 1) << 1 | R) + 1; | |
3562 | bool replicate = false; | |
3563 | int index = is_q << 3 | S << 2 | size; | |
3564 | int ebytes, xs; | |
3a471103 | 3565 | TCGv_i64 clean_addr, tcg_rn, tcg_ebytes; |
df54e47d | 3566 | |
9c72b68a PM |
3567 | if (extract32(insn, 31, 1)) { |
3568 | unallocated_encoding(s); | |
3569 | return; | |
3570 | } | |
3571 | if (!is_postidx && rm != 0) { | |
3572 | unallocated_encoding(s); | |
3573 | return; | |
3574 | } | |
3575 | ||
df54e47d PM |
3576 | switch (scale) { |
3577 | case 3: | |
3578 | if (!is_load || S) { | |
3579 | unallocated_encoding(s); | |
3580 | return; | |
3581 | } | |
3582 | scale = size; | |
3583 | replicate = true; | |
3584 | break; | |
3585 | case 0: | |
3586 | break; | |
3587 | case 1: | |
3588 | if (extract32(size, 0, 1)) { | |
3589 | unallocated_encoding(s); | |
3590 | return; | |
3591 | } | |
3592 | index >>= 1; | |
3593 | break; | |
3594 | case 2: | |
3595 | if (extract32(size, 1, 1)) { | |
3596 | unallocated_encoding(s); | |
3597 | return; | |
3598 | } | |
3599 | if (!extract32(size, 0, 1)) { | |
3600 | index >>= 2; | |
3601 | } else { | |
3602 | if (S) { | |
3603 | unallocated_encoding(s); | |
3604 | return; | |
3605 | } | |
3606 | index >>= 3; | |
3607 | scale = 3; | |
3608 | } | |
3609 | break; | |
3610 | default: | |
3611 | g_assert_not_reached(); | |
3612 | } | |
3613 | ||
8c6afa6a PM |
3614 | if (!fp_access_check(s)) { |
3615 | return; | |
3616 | } | |
3617 | ||
df54e47d PM |
3618 | ebytes = 1 << scale; |
3619 | ||
3620 | if (rn == 31) { | |
3621 | gen_check_sp_alignment(s); | |
3622 | } | |
3623 | ||
3624 | tcg_rn = cpu_reg_sp(s, rn); | |
3a471103 | 3625 | clean_addr = clean_data_tbi(s, tcg_rn); |
a7d8143a | 3626 | tcg_ebytes = tcg_const_i64(ebytes); |
df54e47d PM |
3627 | |
3628 | for (xs = 0; xs < selem; xs++) { | |
3629 | if (replicate) { | |
3630 | /* Load and replicate to all elements */ | |
df54e47d PM |
3631 | TCGv_i64 tcg_tmp = tcg_temp_new_i64(); |
3632 | ||
3a471103 | 3633 | tcg_gen_qemu_ld_i64(tcg_tmp, clean_addr, |
aa6489da | 3634 | get_mem_index(s), s->be_data + scale); |
10e0b33c RH |
3635 | tcg_gen_gvec_dup_i64(scale, vec_full_reg_offset(s, rt), |
3636 | (is_q + 1) * 8, vec_full_reg_size(s), | |
3637 | tcg_tmp); | |
df54e47d PM |
3638 | tcg_temp_free_i64(tcg_tmp); |
3639 | } else { | |
3640 | /* Load/store one element per register */ | |
3641 | if (is_load) { | |
3a471103 | 3642 | do_vec_ld(s, rt, index, clean_addr, scale, s->be_data); |
df54e47d | 3643 | } else { |
3a471103 | 3644 | do_vec_st(s, rt, index, clean_addr, scale, s->be_data); |
df54e47d PM |
3645 | } |
3646 | } | |
3a471103 | 3647 | tcg_gen_add_i64(clean_addr, clean_addr, tcg_ebytes); |
df54e47d PM |
3648 | rt = (rt + 1) % 32; |
3649 | } | |
3a471103 | 3650 | tcg_temp_free_i64(tcg_ebytes); |
df54e47d PM |
3651 | |
3652 | if (is_postidx) { | |
df54e47d | 3653 | if (rm == 31) { |
3a471103 | 3654 | tcg_gen_addi_i64(tcg_rn, tcg_rn, selem * ebytes); |
df54e47d PM |
3655 | } else { |
3656 | tcg_gen_add_i64(tcg_rn, tcg_rn, cpu_reg(s, rm)); | |
3657 | } | |
3658 | } | |
ad7ee8a2 CF |
3659 | } |
3660 | ||
4ce31af4 | 3661 | /* Loads and stores */ |
ad7ee8a2 CF |
3662 | static void disas_ldst(DisasContext *s, uint32_t insn) |
3663 | { | |
3664 | switch (extract32(insn, 24, 6)) { | |
3665 | case 0x08: /* Load/store exclusive */ | |
3666 | disas_ldst_excl(s, insn); | |
3667 | break; | |
3668 | case 0x18: case 0x1c: /* Load register (literal) */ | |
3669 | disas_ld_lit(s, insn); | |
3670 | break; | |
3671 | case 0x28: case 0x29: | |
3672 | case 0x2c: case 0x2d: /* Load/store pair (all forms) */ | |
3673 | disas_ldst_pair(s, insn); | |
3674 | break; | |
3675 | case 0x38: case 0x39: | |
3676 | case 0x3c: case 0x3d: /* Load/store register (all forms) */ | |
3677 | disas_ldst_reg(s, insn); | |
3678 | break; | |
3679 | case 0x0c: /* AdvSIMD load/store multiple structures */ | |
3680 | disas_ldst_multiple_struct(s, insn); | |
3681 | break; | |
3682 | case 0x0d: /* AdvSIMD load/store single structure */ | |
3683 | disas_ldst_single_struct(s, insn); | |
3684 | break; | |
a1229109 PM |
3685 | case 0x19: /* LDAPR/STLR (unscaled immediate) */ |
3686 | if (extract32(insn, 10, 2) != 0 || | |
3687 | extract32(insn, 21, 1) != 0) { | |
3688 | unallocated_encoding(s); | |
3689 | break; | |
3690 | } | |
3691 | disas_ldst_ldapr_stlr(s, insn); | |
3692 | break; | |
ad7ee8a2 CF |
3693 | default: |
3694 | unallocated_encoding(s); | |
3695 | break; | |
3696 | } | |
3697 | } | |
3698 | ||
4ce31af4 | 3699 | /* PC-rel. addressing |
15bfe8b6 AG |
3700 | * 31 30 29 28 24 23 5 4 0 |
3701 | * +----+-------+-----------+-------------------+------+ | |
3702 | * | op | immlo | 1 0 0 0 0 | immhi | Rd | | |
3703 | * +----+-------+-----------+-------------------+------+ | |
3704 | */ | |
ad7ee8a2 CF |
3705 | static void disas_pc_rel_adr(DisasContext *s, uint32_t insn) |
3706 | { | |
15bfe8b6 AG |
3707 | unsigned int page, rd; |
3708 | uint64_t base; | |
037e1d00 | 3709 | uint64_t offset; |
15bfe8b6 AG |
3710 | |
3711 | page = extract32(insn, 31, 1); | |
3712 | /* SignExtend(immhi:immlo) -> offset */ | |
037e1d00 PM |
3713 | offset = sextract64(insn, 5, 19); |
3714 | offset = offset << 2 | extract32(insn, 29, 2); | |
15bfe8b6 | 3715 | rd = extract32(insn, 0, 5); |
43722a6d | 3716 | base = s->pc_curr; |
15bfe8b6 AG |
3717 | |
3718 | if (page) { | |
3719 | /* ADRP (page based) */ | |
3720 | base &= ~0xfff; | |
3721 | offset <<= 12; | |
3722 | } | |
3723 | ||
3724 | tcg_gen_movi_i64(cpu_reg(s, rd), base + offset); | |
ad7ee8a2 CF |
3725 | } |
3726 | ||
b0ff21b4 | 3727 | /* |
4ce31af4 | 3728 | * Add/subtract (immediate) |
b0ff21b4 AB |
3729 | * |
3730 | * 31 30 29 28 24 23 22 21 10 9 5 4 0 | |
3731 | * +--+--+--+-----------+-----+-------------+-----+-----+ | |
3732 | * |sf|op| S| 1 0 0 0 1 |shift| imm12 | Rn | Rd | | |
3733 | * +--+--+--+-----------+-----+-------------+-----+-----+ | |
3734 | * | |
3735 | * sf: 0 -> 32bit, 1 -> 64bit | |
3736 | * op: 0 -> add , 1 -> sub | |
3737 | * S: 1 -> set flags | |
3738 | * shift: 00 -> LSL imm by 0, 01 -> LSL imm by 12 | |
3739 | */ | |
ad7ee8a2 CF |
3740 | static void disas_add_sub_imm(DisasContext *s, uint32_t insn) |
3741 | { | |
b0ff21b4 AB |
3742 | int rd = extract32(insn, 0, 5); |
3743 | int rn = extract32(insn, 5, 5); | |
3744 | uint64_t imm = extract32(insn, 10, 12); | |
3745 | int shift = extract32(insn, 22, 2); | |
3746 | bool setflags = extract32(insn, 29, 1); | |
3747 | bool sub_op = extract32(insn, 30, 1); | |
3748 | bool is_64bit = extract32(insn, 31, 1); | |
3749 | ||
3750 | TCGv_i64 tcg_rn = cpu_reg_sp(s, rn); | |
3751 | TCGv_i64 tcg_rd = setflags ? cpu_reg(s, rd) : cpu_reg_sp(s, rd); | |
3752 | TCGv_i64 tcg_result; | |
3753 | ||
3754 | switch (shift) { | |
3755 | case 0x0: | |
3756 | break; | |
3757 | case 0x1: | |
3758 | imm <<= 12; | |
3759 | break; | |
3760 | default: | |
3761 | unallocated_encoding(s); | |
3762 | return; | |
3763 | } | |
3764 | ||
3765 | tcg_result = tcg_temp_new_i64(); | |
3766 | if (!setflags) { | |
3767 | if (sub_op) { | |
3768 | tcg_gen_subi_i64(tcg_result, tcg_rn, imm); | |
3769 | } else { | |
3770 | tcg_gen_addi_i64(tcg_result, tcg_rn, imm); | |
3771 | } | |
3772 | } else { | |
3773 | TCGv_i64 tcg_imm = tcg_const_i64(imm); | |
3774 | if (sub_op) { | |
3775 | gen_sub_CC(is_64bit, tcg_result, tcg_rn, tcg_imm); | |
3776 | } else { | |
3777 | gen_add_CC(is_64bit, tcg_result, tcg_rn, tcg_imm); | |
3778 | } | |
3779 | tcg_temp_free_i64(tcg_imm); | |
3780 | } | |
3781 | ||
3782 | if (is_64bit) { | |
3783 | tcg_gen_mov_i64(tcg_rd, tcg_result); | |
3784 | } else { | |
3785 | tcg_gen_ext32u_i64(tcg_rd, tcg_result); | |
3786 | } | |
3787 | ||
3788 | tcg_temp_free_i64(tcg_result); | |
ad7ee8a2 CF |
3789 | } |
3790 | ||
71b46089 AG |
3791 | /* The input should be a value in the bottom e bits (with higher |
3792 | * bits zero); returns that value replicated into every element | |
3793 | * of size e in a 64 bit integer. | |
3794 | */ | |
3795 | static uint64_t bitfield_replicate(uint64_t mask, unsigned int e) | |
3796 | { | |
3797 | assert(e != 0); | |
3798 | while (e < 64) { | |
3799 | mask |= mask << e; | |
3800 | e *= 2; | |
3801 | } | |
3802 | return mask; | |
3803 | } | |
3804 | ||
3805 | /* Return a value with the bottom len bits set (where 0 < len <= 64) */ | |
3806 | static inline uint64_t bitmask64(unsigned int length) | |
3807 | { | |
3808 | assert(length > 0 && length <= 64); | |
3809 | return ~0ULL >> (64 - length); | |
3810 | } | |
3811 | ||
3812 | /* Simplified variant of pseudocode DecodeBitMasks() for the case where we | |
3813 | * only require the wmask. Returns false if the imms/immr/immn are a reserved | |
3814 | * value (ie should cause a guest UNDEF exception), and true if they are | |
3815 | * valid, in which case the decoded bit pattern is written to result. | |
3816 | */ | |
8c71baed RH |
3817 | bool logic_imm_decode_wmask(uint64_t *result, unsigned int immn, |
3818 | unsigned int imms, unsigned int immr) | |
71b46089 AG |
3819 | { |
3820 | uint64_t mask; | |
3821 | unsigned e, levels, s, r; | |
3822 | int len; | |
3823 | ||
3824 | assert(immn < 2 && imms < 64 && immr < 64); | |
3825 | ||
3826 | /* The bit patterns we create here are 64 bit patterns which | |
3827 | * are vectors of identical elements of size e = 2, 4, 8, 16, 32 or | |
3828 | * 64 bits each. Each element contains the same value: a run | |
3829 | * of between 1 and e-1 non-zero bits, rotated within the | |
3830 | * element by between 0 and e-1 bits. | |
3831 | * | |
3832 | * The element size and run length are encoded into immn (1 bit) | |
3833 | * and imms (6 bits) as follows: | |
3834 | * 64 bit elements: immn = 1, imms = <length of run - 1> | |
3835 | * 32 bit elements: immn = 0, imms = 0 : <length of run - 1> | |
3836 | * 16 bit elements: immn = 0, imms = 10 : <length of run - 1> | |
3837 | * 8 bit elements: immn = 0, imms = 110 : <length of run - 1> | |
3838 | * 4 bit elements: immn = 0, imms = 1110 : <length of run - 1> | |
3839 | * 2 bit elements: immn = 0, imms = 11110 : <length of run - 1> | |
3840 | * Notice that immn = 0, imms = 11111x is the only combination | |
3841 | * not covered by one of the above options; this is reserved. | |
3842 | * Further, <length of run - 1> all-ones is a reserved pattern. | |
3843 | * | |
3844 | * In all cases the rotation is by immr % e (and immr is 6 bits). | |
3845 | */ | |
3846 | ||
3847 | /* First determine the element size */ | |
3848 | len = 31 - clz32((immn << 6) | (~imms & 0x3f)); | |
3849 | if (len < 1) { | |
3850 | /* This is the immn == 0, imms == 0x11111x case */ | |
3851 | return false; | |
3852 | } | |
3853 | e = 1 << len; | |
3854 | ||
3855 | levels = e - 1; | |
3856 | s = imms & levels; | |
3857 | r = immr & levels; | |
3858 | ||
3859 | if (s == levels) { | |
3860 | /* <length of run - 1> mustn't be all-ones. */ | |
3861 | return false; | |
3862 | } | |
3863 | ||
3864 | /* Create the value of one element: s+1 set bits rotated | |
3865 | * by r within the element (which is e bits wide)... | |
3866 | */ | |
3867 | mask = bitmask64(s + 1); | |
e167adc9 PM |
3868 | if (r) { |
3869 | mask = (mask >> r) | (mask << (e - r)); | |
3870 | mask &= bitmask64(e); | |
3871 | } | |
71b46089 AG |
3872 | /* ...then replicate the element over the whole 64 bit value */ |
3873 | mask = bitfield_replicate(mask, e); | |
3874 | *result = mask; | |
3875 | return true; | |
3876 | } | |
3877 | ||
4ce31af4 | 3878 | /* Logical (immediate) |
71b46089 AG |
3879 | * 31 30 29 28 23 22 21 16 15 10 9 5 4 0 |
3880 | * +----+-----+-------------+---+------+------+------+------+ | |
3881 | * | sf | opc | 1 0 0 1 0 0 | N | immr | imms | Rn | Rd | | |
3882 | * +----+-----+-------------+---+------+------+------+------+ | |
3883 | */ | |
ad7ee8a2 CF |
3884 | static void disas_logic_imm(DisasContext *s, uint32_t insn) |
3885 | { | |
71b46089 AG |
3886 | unsigned int sf, opc, is_n, immr, imms, rn, rd; |
3887 | TCGv_i64 tcg_rd, tcg_rn; | |
3888 | uint64_t wmask; | |
3889 | bool is_and = false; | |
3890 | ||
3891 | sf = extract32(insn, 31, 1); | |
3892 | opc = extract32(insn, 29, 2); | |
3893 | is_n = extract32(insn, 22, 1); | |
3894 | immr = extract32(insn, 16, 6); | |
3895 | imms = extract32(insn, 10, 6); | |
3896 | rn = extract32(insn, 5, 5); | |
3897 | rd = extract32(insn, 0, 5); | |
3898 | ||
3899 | if (!sf && is_n) { | |
3900 | unallocated_encoding(s); | |
3901 | return; | |
3902 | } | |
3903 | ||
3904 | if (opc == 0x3) { /* ANDS */ | |
3905 | tcg_rd = cpu_reg(s, rd); | |
3906 | } else { | |
3907 | tcg_rd = cpu_reg_sp(s, rd); | |
3908 | } | |
3909 | tcg_rn = cpu_reg(s, rn); | |
3910 | ||
3911 | if (!logic_imm_decode_wmask(&wmask, is_n, imms, immr)) { | |
3912 | /* some immediate field values are reserved */ | |
3913 | unallocated_encoding(s); | |
3914 | return; | |
3915 | } | |
3916 | ||
3917 | if (!sf) { | |
3918 | wmask &= 0xffffffff; | |
3919 | } | |
3920 | ||
3921 | switch (opc) { | |
3922 | case 0x3: /* ANDS */ | |
3923 | case 0x0: /* AND */ | |
3924 | tcg_gen_andi_i64(tcg_rd, tcg_rn, wmask); | |
3925 | is_and = true; | |
3926 | break; | |
3927 | case 0x1: /* ORR */ | |
3928 | tcg_gen_ori_i64(tcg_rd, tcg_rn, wmask); | |
3929 | break; | |
3930 | case 0x2: /* EOR */ | |
3931 | tcg_gen_xori_i64(tcg_rd, tcg_rn, wmask); | |
3932 | break; | |
3933 | default: | |
3934 | assert(FALSE); /* must handle all above */ | |
3935 | break; | |
3936 | } | |
3937 | ||
3938 | if (!sf && !is_and) { | |
3939 | /* zero extend final result; we know we can skip this for AND | |
3940 | * since the immediate had the high 32 bits clear. | |
3941 | */ | |
3942 | tcg_gen_ext32u_i64(tcg_rd, tcg_rd); | |
3943 | } | |
3944 | ||
3945 | if (opc == 3) { /* ANDS */ | |
3946 | gen_logic_CC(sf, tcg_rd); | |
3947 | } | |
ad7ee8a2 CF |
3948 | } |
3949 | ||
ed6ec679 | 3950 | /* |
4ce31af4 | 3951 | * Move wide (immediate) |
ed6ec679 AB |
3952 | * |
3953 | * 31 30 29 28 23 22 21 20 5 4 0 | |
3954 | * +--+-----+-------------+-----+----------------+------+ | |
3955 | * |sf| opc | 1 0 0 1 0 1 | hw | imm16 | Rd | | |
3956 | * +--+-----+-------------+-----+----------------+------+ | |
3957 | * | |
3958 | * sf: 0 -> 32 bit, 1 -> 64 bit | |
3959 | * opc: 00 -> N, 10 -> Z, 11 -> K | |
3960 | * hw: shift/16 (0,16, and sf only 32, 48) | |
3961 | */ | |
ad7ee8a2 CF |
3962 | static void disas_movw_imm(DisasContext *s, uint32_t insn) |
3963 | { | |
ed6ec679 AB |
3964 | int rd = extract32(insn, 0, 5); |
3965 | uint64_t imm = extract32(insn, 5, 16); | |
3966 | int sf = extract32(insn, 31, 1); | |
3967 | int opc = extract32(insn, 29, 2); | |
3968 | int pos = extract32(insn, 21, 2) << 4; | |
3969 | TCGv_i64 tcg_rd = cpu_reg(s, rd); | |
3970 | TCGv_i64 tcg_imm; | |
3971 | ||
3972 | if (!sf && (pos >= 32)) { | |
3973 | unallocated_encoding(s); | |
3974 | return; | |
3975 | } | |
3976 | ||
3977 | switch (opc) { | |
3978 | case 0: /* MOVN */ | |
3979 | case 2: /* MOVZ */ | |
3980 | imm <<= pos; | |
3981 | if (opc == 0) { | |
3982 | imm = ~imm; | |
3983 | } | |
3984 | if (!sf) { | |
3985 | imm &= 0xffffffffu; | |
3986 | } | |
3987 | tcg_gen_movi_i64(tcg_rd, imm); | |
3988 | break; | |
3989 | case 3: /* MOVK */ | |
3990 | tcg_imm = tcg_const_i64(imm); | |
3991 | tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_imm, pos, 16); | |
3992 | tcg_temp_free_i64(tcg_imm); | |
3993 | if (!sf) { | |
3994 | tcg_gen_ext32u_i64(tcg_rd, tcg_rd); | |
3995 | } | |
3996 | break; | |
3997 | default: | |
3998 | unallocated_encoding(s); | |
3999 | break; | |
4000 | } | |
ad7ee8a2 CF |
4001 | } |
4002 | ||
4ce31af4 | 4003 | /* Bitfield |
88077742 CF |
4004 | * 31 30 29 28 23 22 21 16 15 10 9 5 4 0 |
4005 | * +----+-----+-------------+---+------+------+------+------+ | |
4006 | * | sf | opc | 1 0 0 1 1 0 | N | immr | imms | Rn | Rd | | |
4007 | * +----+-----+-------------+---+------+------+------+------+ | |
4008 | */ | |
ad7ee8a2 CF |
4009 | static void disas_bitfield(DisasContext *s, uint32_t insn) |
4010 | { | |
88077742 CF |
4011 | unsigned int sf, n, opc, ri, si, rn, rd, bitsize, pos, len; |
4012 | TCGv_i64 tcg_rd, tcg_tmp; | |
4013 | ||
4014 | sf = extract32(insn, 31, 1); | |
4015 | opc = extract32(insn, 29, 2); | |
4016 | n = extract32(insn, 22, 1); | |
4017 | ri = extract32(insn, 16, 6); | |
4018 | si = extract32(insn, 10, 6); | |
4019 | rn = extract32(insn, 5, 5); | |
4020 | rd = extract32(insn, 0, 5); | |
4021 | bitsize = sf ? 64 : 32; | |
4022 | ||
4023 | if (sf != n || ri >= bitsize || si >= bitsize || opc > 2) { | |
4024 | unallocated_encoding(s); | |
4025 | return; | |
4026 | } | |
4027 | ||
4028 | tcg_rd = cpu_reg(s, rd); | |
d3a77b42 RH |
4029 | |
4030 | /* Suppress the zero-extend for !sf. Since RI and SI are constrained | |
4031 | to be smaller than bitsize, we'll never reference data outside the | |
4032 | low 32-bits anyway. */ | |
4033 | tcg_tmp = read_cpu_reg(s, rn, 1); | |
88077742 | 4034 | |
59a71b4c | 4035 | /* Recognize simple(r) extractions. */ |
86c9ab27 | 4036 | if (si >= ri) { |
59a71b4c RH |
4037 | /* Wd<s-r:0> = Wn<s:r> */ |
4038 | len = (si - ri) + 1; | |
4039 | if (opc == 0) { /* SBFM: ASR, SBFX, SXTB, SXTH, SXTW */ | |
4040 | tcg_gen_sextract_i64(tcg_rd, tcg_tmp, ri, len); | |
ef60151b | 4041 | goto done; |
59a71b4c RH |
4042 | } else if (opc == 2) { /* UBFM: UBFX, LSR, UXTB, UXTH */ |
4043 | tcg_gen_extract_i64(tcg_rd, tcg_tmp, ri, len); | |
9924e858 RH |
4044 | return; |
4045 | } | |
87eb65a3 RH |
4046 | /* opc == 1, BFXIL fall through to deposit */ |
4047 | tcg_gen_shri_i64(tcg_tmp, tcg_tmp, ri); | |
88077742 | 4048 | pos = 0; |
88077742 | 4049 | } else { |
59a71b4c RH |
4050 | /* Handle the ri > si case with a deposit |
4051 | * Wd<32+s-r,32-r> = Wn<s:0> | |
4052 | */ | |
88077742 | 4053 | len = si + 1; |
59a71b4c | 4054 | pos = (bitsize - ri) & (bitsize - 1); |
88077742 CF |
4055 | } |
4056 | ||
59a71b4c RH |
4057 | if (opc == 0 && len < ri) { |
4058 | /* SBFM: sign extend the destination field from len to fill | |
4059 | the balance of the word. Let the deposit below insert all | |
4060 | of those sign bits. */ | |
4061 | tcg_gen_sextract_i64(tcg_tmp, tcg_tmp, 0, len); | |
4062 | len = ri; | |
4063 | } | |
88077742 | 4064 | |
87eb65a3 | 4065 | if (opc == 1) { /* BFM, BFXIL */ |
59a71b4c RH |
4066 | tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_tmp, pos, len); |
4067 | } else { | |
4068 | /* SBFM or UBFM: We start with zero, and we haven't modified | |
4069 | any bits outside bitsize, therefore the zero-extension | |
4070 | below is unneeded. */ | |
4071 | tcg_gen_deposit_z_i64(tcg_rd, tcg_tmp, pos, len); | |
4072 | return; | |
88077742 CF |
4073 | } |
4074 | ||
ef60151b | 4075 | done: |
88077742 CF |
4076 | if (!sf) { /* zero extend final result */ |
4077 | tcg_gen_ext32u_i64(tcg_rd, tcg_rd); | |
4078 | } | |
ad7ee8a2 CF |
4079 | } |
4080 | ||
4ce31af4 | 4081 | /* Extract |
e801de93 AG |
4082 | * 31 30 29 28 23 22 21 20 16 15 10 9 5 4 0 |
4083 | * +----+------+-------------+---+----+------+--------+------+------+ | |
4084 | * | sf | op21 | 1 0 0 1 1 1 | N | o0 | Rm | imms | Rn | Rd | | |
4085 | * +----+------+-------------+---+----+------+--------+------+------+ | |
4086 | */ | |
ad7ee8a2 CF |
4087 | static void disas_extract(DisasContext *s, uint32_t insn) |
4088 | { | |
e801de93 AG |
4089 | unsigned int sf, n, rm, imm, rn, rd, bitsize, op21, op0; |
4090 | ||
4091 | sf = extract32(insn, 31, 1); | |
4092 | n = extract32(insn, 22, 1); | |
4093 | rm = extract32(insn, 16, 5); | |
4094 | imm = extract32(insn, 10, 6); | |
4095 | rn = extract32(insn, 5, 5); | |
4096 | rd = extract32(insn, 0, 5); | |
4097 | op21 = extract32(insn, 29, 2); | |
4098 | op0 = extract32(insn, 21, 1); | |
4099 | bitsize = sf ? 64 : 32; | |
4100 | ||
4101 | if (sf != n || op21 || op0 || imm >= bitsize) { | |
4102 | unallocated_encoding(s); | |
4103 | } else { | |
4104 | TCGv_i64 tcg_rd, tcg_rm, tcg_rn; | |
4105 | ||
4106 | tcg_rd = cpu_reg(s, rd); | |
4107 | ||
8fb0ad8e | 4108 | if (unlikely(imm == 0)) { |
e801de93 AG |
4109 | /* tcg shl_i32/shl_i64 is undefined for 32/64 bit shifts, |
4110 | * so an extract from bit 0 is a special case. | |
4111 | */ | |
4112 | if (sf) { | |
4113 | tcg_gen_mov_i64(tcg_rd, cpu_reg(s, rm)); | |
4114 | } else { | |
4115 | tcg_gen_ext32u_i64(tcg_rd, cpu_reg(s, rm)); | |
4116 | } | |
80ac954c | 4117 | } else { |
8fb0ad8e | 4118 | tcg_rm = cpu_reg(s, rm); |
80ac954c RH |
4119 | tcg_rn = cpu_reg(s, rn); |
4120 | ||
8fb0ad8e | 4121 | if (sf) { |
80ac954c RH |
4122 | /* Specialization to ROR happens in EXTRACT2. */ |
4123 | tcg_gen_extract2_i64(tcg_rd, tcg_rm, tcg_rn, imm); | |
8fb0ad8e | 4124 | } else { |
80ac954c RH |
4125 | TCGv_i32 t0 = tcg_temp_new_i32(); |
4126 | ||
4127 | tcg_gen_extrl_i64_i32(t0, tcg_rm); | |
4128 | if (rm == rn) { | |
4129 | tcg_gen_rotri_i32(t0, t0, imm); | |
4130 | } else { | |
4131 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
4132 | tcg_gen_extrl_i64_i32(t1, tcg_rn); | |
4133 | tcg_gen_extract2_i32(t0, t0, t1, imm); | |
4134 | tcg_temp_free_i32(t1); | |
4135 | } | |
4136 | tcg_gen_extu_i32_i64(tcg_rd, t0); | |
4137 | tcg_temp_free_i32(t0); | |
8fb0ad8e | 4138 | } |
e801de93 | 4139 | } |
e801de93 | 4140 | } |
ad7ee8a2 CF |
4141 | } |
4142 | ||
4ce31af4 | 4143 | /* Data processing - immediate */ |
ad7ee8a2 CF |
4144 | static void disas_data_proc_imm(DisasContext *s, uint32_t insn) |
4145 | { | |
4146 | switch (extract32(insn, 23, 6)) { | |
4147 | case 0x20: case 0x21: /* PC-rel. addressing */ | |
4148 | disas_pc_rel_adr(s, insn); | |
4149 | break; | |
4150 | case 0x22: case 0x23: /* Add/subtract (immediate) */ | |
4151 | disas_add_sub_imm(s, insn); | |
4152 | break; | |
4153 | case 0x24: /* Logical (immediate) */ | |
4154 | disas_logic_imm(s, insn); | |
4155 | break; | |
4156 | case 0x25: /* Move wide (immediate) */ | |
4157 | disas_movw_imm(s, insn); | |
4158 | break; | |
4159 | case 0x26: /* Bitfield */ | |
4160 | disas_bitfield(s, insn); | |
4161 | break; | |
4162 | case 0x27: /* Extract */ | |
4163 | disas_extract(s, insn); | |
4164 | break; | |
4165 | default: | |
4166 | unallocated_encoding(s); | |
4167 | break; | |
4168 | } | |
4169 | } | |
4170 | ||
832ffa1c AG |
4171 | /* Shift a TCGv src by TCGv shift_amount, put result in dst. |
4172 | * Note that it is the caller's responsibility to ensure that the | |
4173 | * shift amount is in range (ie 0..31 or 0..63) and provide the ARM | |
4174 | * mandated semantics for out of range shifts. | |
4175 | */ | |
4176 | static void shift_reg(TCGv_i64 dst, TCGv_i64 src, int sf, | |
4177 | enum a64_shift_type shift_type, TCGv_i64 shift_amount) | |
4178 | { | |
4179 | switch (shift_type) { | |
4180 | case A64_SHIFT_TYPE_LSL: | |
4181 | tcg_gen_shl_i64(dst, src, shift_amount); | |
4182 | break; | |
4183 | case A64_SHIFT_TYPE_LSR: | |
4184 | tcg_gen_shr_i64(dst, src, shift_amount); | |
4185 | break; | |
4186 | case A64_SHIFT_TYPE_ASR: | |
4187 | if (!sf) { | |
4188 | tcg_gen_ext32s_i64(dst, src); | |
4189 | } | |
4190 | tcg_gen_sar_i64(dst, sf ? src : dst, shift_amount); | |
4191 | break; | |
4192 | case A64_SHIFT_TYPE_ROR: | |
4193 | if (sf) { | |
4194 | tcg_gen_rotr_i64(dst, src, shift_amount); | |
4195 | } else { | |
4196 | TCGv_i32 t0, t1; | |
4197 | t0 = tcg_temp_new_i32(); | |
4198 | t1 = tcg_temp_new_i32(); | |
ecc7b3aa RH |
4199 | tcg_gen_extrl_i64_i32(t0, src); |
4200 | tcg_gen_extrl_i64_i32(t1, shift_amount); | |
832ffa1c AG |
4201 | tcg_gen_rotr_i32(t0, t0, t1); |
4202 | tcg_gen_extu_i32_i64(dst, t0); | |
4203 | tcg_temp_free_i32(t0); | |
4204 | tcg_temp_free_i32(t1); | |
4205 | } | |
4206 | break; | |
4207 | default: | |
4208 | assert(FALSE); /* all shift types should be handled */ | |
4209 | break; | |
4210 | } | |
4211 | ||
4212 | if (!sf) { /* zero extend final result */ | |
4213 | tcg_gen_ext32u_i64(dst, dst); | |
4214 | } | |
4215 | } | |
4216 | ||
4217 | /* Shift a TCGv src by immediate, put result in dst. | |
4218 | * The shift amount must be in range (this should always be true as the | |
4219 | * relevant instructions will UNDEF on bad shift immediates). | |
4220 | */ | |
4221 | static void shift_reg_imm(TCGv_i64 dst, TCGv_i64 src, int sf, | |
4222 | enum a64_shift_type shift_type, unsigned int shift_i) | |
4223 | { | |
4224 | assert(shift_i < (sf ? 64 : 32)); | |
4225 | ||
4226 | if (shift_i == 0) { | |
4227 | tcg_gen_mov_i64(dst, src); | |
4228 | } else { | |
4229 | TCGv_i64 shift_const; | |
4230 | ||
4231 | shift_const = tcg_const_i64(shift_i); | |
4232 | shift_reg(dst, src, sf, shift_type, shift_const); | |
4233 | tcg_temp_free_i64(shift_const); | |
4234 | } | |
4235 | } | |
4236 | ||
4ce31af4 | 4237 | /* Logical (shifted register) |
832ffa1c AG |
4238 | * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0 |
4239 | * +----+-----+-----------+-------+---+------+--------+------+------+ | |
4240 | * | sf | opc | 0 1 0 1 0 | shift | N | Rm | imm6 | Rn | Rd | | |
4241 | * +----+-----+-----------+-------+---+------+--------+------+------+ | |
4242 | */ | |
ad7ee8a2 CF |
4243 | static void disas_logic_reg(DisasContext *s, uint32_t insn) |
4244 | { | |
832ffa1c AG |
4245 | TCGv_i64 tcg_rd, tcg_rn, tcg_rm; |
4246 | unsigned int sf, opc, shift_type, invert, rm, shift_amount, rn, rd; | |
4247 | ||
4248 | sf = extract32(insn, 31, 1); | |
4249 | opc = extract32(insn, 29, 2); | |
4250 | shift_type = extract32(insn, 22, 2); | |
4251 | invert = extract32(insn, 21, 1); | |
4252 | rm = extract32(insn, 16, 5); | |
4253 | shift_amount = extract32(insn, 10, 6); | |
4254 | rn = extract32(insn, 5, 5); | |
4255 | rd = extract32(insn, 0, 5); | |
4256 | ||
4257 | if (!sf && (shift_amount & (1 << 5))) { | |
4258 | unallocated_encoding(s); | |
4259 | return; | |
4260 | } | |
4261 | ||
4262 | tcg_rd = cpu_reg(s, rd); | |
4263 | ||
4264 | if (opc == 1 && shift_amount == 0 && shift_type == 0 && rn == 31) { | |
4265 | /* Unshifted ORR and ORN with WZR/XZR is the standard encoding for | |
4266 | * register-register MOV and MVN, so it is worth special casing. | |
4267 | */ | |
4268 | tcg_rm = cpu_reg(s, rm); | |
4269 | if (invert) { | |
4270 | tcg_gen_not_i64(tcg_rd, tcg_rm); | |
4271 | if (!sf) { | |
4272 | tcg_gen_ext32u_i64(tcg_rd, tcg_rd); | |
4273 | } | |
4274 | } else { | |
4275 | if (sf) { | |
4276 | tcg_gen_mov_i64(tcg_rd, tcg_rm); | |
4277 | } else { | |
4278 | tcg_gen_ext32u_i64(tcg_rd, tcg_rm); | |
4279 | } | |
4280 | } | |
4281 | return; | |
4282 | } | |
4283 | ||
4284 | tcg_rm = read_cpu_reg(s, rm, sf); | |
4285 | ||
4286 | if (shift_amount) { | |
4287 | shift_reg_imm(tcg_rm, tcg_rm, sf, shift_type, shift_amount); | |
4288 | } | |
4289 | ||
4290 | tcg_rn = cpu_reg(s, rn); | |
4291 | ||
4292 | switch (opc | (invert << 2)) { | |
4293 | case 0: /* AND */ | |
4294 | case 3: /* ANDS */ | |
4295 | tcg_gen_and_i64(tcg_rd, tcg_rn, tcg_rm); | |
4296 | break; | |
4297 | case 1: /* ORR */ | |
4298 | tcg_gen_or_i64(tcg_rd, tcg_rn, tcg_rm); | |
4299 | break; | |
4300 | case 2: /* EOR */ | |
4301 | tcg_gen_xor_i64(tcg_rd, tcg_rn, tcg_rm); | |
4302 | break; | |
4303 | case 4: /* BIC */ | |
4304 | case 7: /* BICS */ | |
4305 | tcg_gen_andc_i64(tcg_rd, tcg_rn, tcg_rm); | |
4306 | break; | |
4307 | case 5: /* ORN */ | |
4308 | tcg_gen_orc_i64(tcg_rd, tcg_rn, tcg_rm); | |
4309 | break; | |
4310 | case 6: /* EON */ | |
4311 | tcg_gen_eqv_i64(tcg_rd, tcg_rn, tcg_rm); | |
4312 | break; | |
4313 | default: | |
4314 | assert(FALSE); | |
4315 | break; | |
4316 | } | |
4317 | ||
4318 | if (!sf) { | |
4319 | tcg_gen_ext32u_i64(tcg_rd, tcg_rd); | |
4320 | } | |
4321 | ||
4322 | if (opc == 3) { | |
4323 | gen_logic_CC(sf, tcg_rd); | |
4324 | } | |
ad7ee8a2 CF |
4325 | } |
4326 | ||
b0ff21b4 | 4327 | /* |
4ce31af4 | 4328 | * Add/subtract (extended register) |
b0ff21b4 AB |
4329 | * |
4330 | * 31|30|29|28 24|23 22|21|20 16|15 13|12 10|9 5|4 0| | |
4331 | * +--+--+--+-----------+-----+--+-------+------+------+----+----+ | |
4332 | * |sf|op| S| 0 1 0 1 1 | opt | 1| Rm |option| imm3 | Rn | Rd | | |
4333 | * +--+--+--+-----------+-----+--+-------+------+------+----+----+ | |
4334 | * | |
4335 | * sf: 0 -> 32bit, 1 -> 64bit | |
4336 | * op: 0 -> add , 1 -> sub | |
4337 | * S: 1 -> set flags | |
4338 | * opt: 00 | |
4339 | * option: extension type (see DecodeRegExtend) | |
4340 | * imm3: optional shift to Rm | |
4341 | * | |
4342 | * Rd = Rn + LSL(extend(Rm), amount) | |
4343 | */ | |
ad7ee8a2 CF |
4344 | static void disas_add_sub_ext_reg(DisasContext *s, uint32_t insn) |
4345 | { | |
b0ff21b4 AB |
4346 | int rd = extract32(insn, 0, 5); |
4347 | int rn = extract32(insn, 5, 5); | |
4348 | int imm3 = extract32(insn, 10, 3); | |
4349 | int option = extract32(insn, 13, 3); | |
4350 | int rm = extract32(insn, 16, 5); | |
4f611066 | 4351 | int opt = extract32(insn, 22, 2); |
b0ff21b4 AB |
4352 | bool setflags = extract32(insn, 29, 1); |
4353 | bool sub_op = extract32(insn, 30, 1); | |
4354 | bool sf = extract32(insn, 31, 1); | |
4355 | ||
4356 | TCGv_i64 tcg_rm, tcg_rn; /* temps */ | |
4357 | TCGv_i64 tcg_rd; | |
4358 | TCGv_i64 tcg_result; | |
4359 | ||
4f611066 | 4360 | if (imm3 > 4 || opt != 0) { |
b0ff21b4 AB |
4361 | unallocated_encoding(s); |
4362 | return; | |
4363 | } | |
4364 | ||
4365 | /* non-flag setting ops may use SP */ | |
4366 | if (!setflags) { | |
b0ff21b4 AB |
4367 | tcg_rd = cpu_reg_sp(s, rd); |
4368 | } else { | |
b0ff21b4 AB |
4369 | tcg_rd = cpu_reg(s, rd); |
4370 | } | |
cf4ab1af | 4371 | tcg_rn = read_cpu_reg_sp(s, rn, sf); |
b0ff21b4 AB |
4372 | |
4373 | tcg_rm = read_cpu_reg(s, rm, sf); | |
4374 | ext_and_shift_reg(tcg_rm, tcg_rm, option, imm3); | |
4375 | ||
4376 | tcg_result = tcg_temp_new_i64(); | |
4377 | ||
4378 | if (!setflags) { | |
4379 | if (sub_op) { | |
4380 | tcg_gen_sub_i64(tcg_result, tcg_rn, tcg_rm); | |
4381 | } else { | |
4382 | tcg_gen_add_i64(tcg_result, tcg_rn, tcg_rm); | |
4383 | } | |
4384 | } else { | |
4385 | if (sub_op) { | |
4386 | gen_sub_CC(sf, tcg_result, tcg_rn, tcg_rm); | |
4387 | } else { | |
4388 | gen_add_CC(sf, tcg_result, tcg_rn, tcg_rm); | |
4389 | } | |
4390 | } | |
4391 | ||
4392 | if (sf) { | |
4393 | tcg_gen_mov_i64(tcg_rd, tcg_result); | |
4394 | } else { | |
4395 | tcg_gen_ext32u_i64(tcg_rd, tcg_result); | |
4396 | } | |
4397 | ||
4398 | tcg_temp_free_i64(tcg_result); | |
ad7ee8a2 CF |
4399 | } |
4400 | ||
b0ff21b4 | 4401 | /* |
4ce31af4 | 4402 | * Add/subtract (shifted register) |
b0ff21b4 AB |
4403 | * |
4404 | * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0 | |
4405 | * +--+--+--+-----------+-----+--+-------+---------+------+------+ | |
4406 | * |sf|op| S| 0 1 0 1 1 |shift| 0| Rm | imm6 | Rn | Rd | | |
4407 | * +--+--+--+-----------+-----+--+-------+---------+------+------+ | |
4408 | * | |
4409 | * sf: 0 -> 32bit, 1 -> 64bit | |
4410 | * op: 0 -> add , 1 -> sub | |
4411 | * S: 1 -> set flags | |
4412 | * shift: 00 -> LSL, 01 -> LSR, 10 -> ASR, 11 -> RESERVED | |
4413 | * imm6: Shift amount to apply to Rm before the add/sub | |
4414 | */ | |
ad7ee8a2 CF |
4415 | static void disas_add_sub_reg(DisasContext *s, uint32_t insn) |
4416 | { | |
b0ff21b4 AB |
4417 | int rd = extract32(insn, 0, 5); |
4418 | int rn = extract32(insn, 5, 5); | |
4419 | int imm6 = extract32(insn, 10, 6); | |
4420 | int rm = extract32(insn, 16, 5); | |
4421 | int shift_type = extract32(insn, 22, 2); | |
4422 | bool setflags = extract32(insn, 29, 1); | |
4423 | bool sub_op = extract32(insn, 30, 1); | |
4424 | bool sf = extract32(insn, 31, 1); | |
4425 | ||
4426 | TCGv_i64 tcg_rd = cpu_reg(s, rd); | |
4427 | TCGv_i64 tcg_rn, tcg_rm; | |
4428 | TCGv_i64 tcg_result; | |
4429 | ||
4430 | if ((shift_type == 3) || (!sf && (imm6 > 31))) { | |
4431 | unallocated_encoding(s); | |
4432 | return; | |
4433 | } | |
4434 | ||
4435 | tcg_rn = read_cpu_reg(s, rn, sf); | |
4436 | tcg_rm = read_cpu_reg(s, rm, sf); | |
4437 | ||
4438 | shift_reg_imm(tcg_rm, tcg_rm, sf, shift_type, imm6); | |
4439 | ||
4440 | tcg_result = tcg_temp_new_i64(); | |
4441 | ||
4442 | if (!setflags) { | |
4443 | if (sub_op) { | |
4444 | tcg_gen_sub_i64(tcg_result, tcg_rn, tcg_rm); | |
4445 | } else { | |
4446 | tcg_gen_add_i64(tcg_result, tcg_rn, tcg_rm); | |
4447 | } | |
4448 | } else { | |
4449 | if (sub_op) { | |
4450 | gen_sub_CC(sf, tcg_result, tcg_rn, tcg_rm); | |
4451 | } else { | |
4452 | gen_add_CC(sf, tcg_result, tcg_rn, tcg_rm); | |
4453 | } | |
4454 | } | |
4455 | ||
4456 | if (sf) { | |
4457 | tcg_gen_mov_i64(tcg_rd, tcg_result); | |
4458 | } else { | |
4459 | tcg_gen_ext32u_i64(tcg_rd, tcg_result); | |
4460 | } | |
4461 | ||
4462 | tcg_temp_free_i64(tcg_result); | |
ad7ee8a2 CF |
4463 | } |
4464 | ||
4ce31af4 PM |
4465 | /* Data-processing (3 source) |
4466 | * | |
4467 | * 31 30 29 28 24 23 21 20 16 15 14 10 9 5 4 0 | |
4468 | * +--+------+-----------+------+------+----+------+------+------+ | |
4469 | * |sf| op54 | 1 1 0 1 1 | op31 | Rm | o0 | Ra | Rn | Rd | | |
4470 | * +--+------+-----------+------+------+----+------+------+------+ | |
52c8b9af | 4471 | */ |
ad7ee8a2 CF |
4472 | static void disas_data_proc_3src(DisasContext *s, uint32_t insn) |
4473 | { | |
52c8b9af AG |
4474 | int rd = extract32(insn, 0, 5); |
4475 | int rn = extract32(insn, 5, 5); | |
4476 | int ra = extract32(insn, 10, 5); | |
4477 | int rm = extract32(insn, 16, 5); | |
4478 | int op_id = (extract32(insn, 29, 3) << 4) | | |
4479 | (extract32(insn, 21, 3) << 1) | | |
4480 | extract32(insn, 15, 1); | |
4481 | bool sf = extract32(insn, 31, 1); | |
4482 | bool is_sub = extract32(op_id, 0, 1); | |
4483 | bool is_high = extract32(op_id, 2, 1); | |
4484 | bool is_signed = false; | |
4485 | TCGv_i64 tcg_op1; | |
4486 | TCGv_i64 tcg_op2; | |
4487 | TCGv_i64 tcg_tmp; | |
4488 | ||
4489 | /* Note that op_id is sf:op54:op31:o0 so it includes the 32/64 size flag */ | |
4490 | switch (op_id) { | |
4491 | case 0x42: /* SMADDL */ | |
4492 | case 0x43: /* SMSUBL */ | |
4493 | case 0x44: /* SMULH */ | |
4494 | is_signed = true; | |
4495 | break; | |
4496 | case 0x0: /* MADD (32bit) */ | |
4497 | case 0x1: /* MSUB (32bit) */ | |
4498 | case 0x40: /* MADD (64bit) */ | |
4499 | case 0x41: /* MSUB (64bit) */ | |
4500 | case 0x4a: /* UMADDL */ | |
4501 | case 0x4b: /* UMSUBL */ | |
4502 | case 0x4c: /* UMULH */ | |
4503 | break; | |
4504 | default: | |
4505 | unallocated_encoding(s); | |
4506 | return; | |
4507 | } | |
4508 | ||
4509 | if (is_high) { | |
4510 | TCGv_i64 low_bits = tcg_temp_new_i64(); /* low bits discarded */ | |
4511 | TCGv_i64 tcg_rd = cpu_reg(s, rd); | |
4512 | TCGv_i64 tcg_rn = cpu_reg(s, rn); | |
4513 | TCGv_i64 tcg_rm = cpu_reg(s, rm); | |
4514 | ||
4515 | if (is_signed) { | |
4516 | tcg_gen_muls2_i64(low_bits, tcg_rd, tcg_rn, tcg_rm); | |
4517 | } else { | |
4518 | tcg_gen_mulu2_i64(low_bits, tcg_rd, tcg_rn, tcg_rm); | |
4519 | } | |
4520 | ||
4521 | tcg_temp_free_i64(low_bits); | |
4522 | return; | |
4523 | } | |
4524 | ||
4525 | tcg_op1 = tcg_temp_new_i64(); | |
4526 | tcg_op2 = tcg_temp_new_i64(); | |
4527 | tcg_tmp = tcg_temp_new_i64(); | |
4528 | ||
4529 | if (op_id < 0x42) { | |
4530 | tcg_gen_mov_i64(tcg_op1, cpu_reg(s, rn)); | |
4531 | tcg_gen_mov_i64(tcg_op2, cpu_reg(s, rm)); | |
4532 | } else { | |
4533 | if (is_signed) { | |
4534 | tcg_gen_ext32s_i64(tcg_op1, cpu_reg(s, rn)); | |
4535 | tcg_gen_ext32s_i64(tcg_op2, cpu_reg(s, rm)); | |
4536 | } else { | |
4537 | tcg_gen_ext32u_i64(tcg_op1, cpu_reg(s, rn)); | |
4538 | tcg_gen_ext32u_i64(tcg_op2, cpu_reg(s, rm)); | |
4539 | } | |
4540 | } | |
4541 | ||
4542 | if (ra == 31 && !is_sub) { | |
4543 | /* Special-case MADD with rA == XZR; it is the standard MUL alias */ | |
4544 | tcg_gen_mul_i64(cpu_reg(s, rd), tcg_op1, tcg_op2); | |
4545 | } else { | |
4546 | tcg_gen_mul_i64(tcg_tmp, tcg_op1, tcg_op2); | |
4547 | if (is_sub) { | |
4548 | tcg_gen_sub_i64(cpu_reg(s, rd), cpu_reg(s, ra), tcg_tmp); | |
4549 | } else { | |
4550 | tcg_gen_add_i64(cpu_reg(s, rd), cpu_reg(s, ra), tcg_tmp); | |
4551 | } | |
4552 | } | |
4553 | ||
4554 | if (!sf) { | |
4555 | tcg_gen_ext32u_i64(cpu_reg(s, rd), cpu_reg(s, rd)); | |
4556 | } | |
4557 | ||
4558 | tcg_temp_free_i64(tcg_op1); | |
4559 | tcg_temp_free_i64(tcg_op2); | |
4560 | tcg_temp_free_i64(tcg_tmp); | |
ad7ee8a2 CF |
4561 | } |
4562 | ||
4ce31af4 | 4563 | /* Add/subtract (with carry) |
2fba34f7 RH |
4564 | * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 10 9 5 4 0 |
4565 | * +--+--+--+------------------------+------+-------------+------+-----+ | |
4566 | * |sf|op| S| 1 1 0 1 0 0 0 0 | rm | 0 0 0 0 0 0 | Rn | Rd | | |
4567 | * +--+--+--+------------------------+------+-------------+------+-----+ | |
643dbb07 CF |
4568 | */ |
4569 | ||
ad7ee8a2 CF |
4570 | static void disas_adc_sbc(DisasContext *s, uint32_t insn) |
4571 | { | |
643dbb07 CF |
4572 | unsigned int sf, op, setflags, rm, rn, rd; |
4573 | TCGv_i64 tcg_y, tcg_rn, tcg_rd; | |
4574 | ||
643dbb07 CF |
4575 | sf = extract32(insn, 31, 1); |
4576 | op = extract32(insn, 30, 1); | |
4577 | setflags = extract32(insn, 29, 1); | |
4578 | rm = extract32(insn, 16, 5); | |
4579 | rn = extract32(insn, 5, 5); | |
4580 | rd = extract32(insn, 0, 5); | |
4581 | ||
4582 | tcg_rd = cpu_reg(s, rd); | |
4583 | tcg_rn = cpu_reg(s, rn); | |
4584 | ||
4585 | if (op) { | |
4586 | tcg_y = new_tmp_a64(s); | |
4587 | tcg_gen_not_i64(tcg_y, cpu_reg(s, rm)); | |
4588 | } else { | |
4589 | tcg_y = cpu_reg(s, rm); | |
4590 | } | |
4591 | ||
4592 | if (setflags) { | |
4593 | gen_adc_CC(sf, tcg_rd, tcg_rn, tcg_y); | |
4594 | } else { | |
4595 | gen_adc(sf, tcg_rd, tcg_rn, tcg_y); | |
4596 | } | |
ad7ee8a2 CF |
4597 | } |
4598 | ||
b89d9c98 RH |
4599 | /* |
4600 | * Rotate right into flags | |
4601 | * 31 30 29 21 15 10 5 4 0 | |
4602 | * +--+--+--+-----------------+--------+-----------+------+--+------+ | |
4603 | * |sf|op| S| 1 1 0 1 0 0 0 0 | imm6 | 0 0 0 0 1 | Rn |o2| mask | | |
4604 | * +--+--+--+-----------------+--------+-----------+------+--+------+ | |
4605 | */ | |
4606 | static void disas_rotate_right_into_flags(DisasContext *s, uint32_t insn) | |
4607 | { | |
4608 | int mask = extract32(insn, 0, 4); | |
4609 | int o2 = extract32(insn, 4, 1); | |
4610 | int rn = extract32(insn, 5, 5); | |
4611 | int imm6 = extract32(insn, 15, 6); | |
4612 | int sf_op_s = extract32(insn, 29, 3); | |
4613 | TCGv_i64 tcg_rn; | |
4614 | TCGv_i32 nzcv; | |
4615 | ||
4616 | if (sf_op_s != 5 || o2 != 0 || !dc_isar_feature(aa64_condm_4, s)) { | |
4617 | unallocated_encoding(s); | |
4618 | return; | |
4619 | } | |
4620 | ||
4621 | tcg_rn = read_cpu_reg(s, rn, 1); | |
4622 | tcg_gen_rotri_i64(tcg_rn, tcg_rn, imm6); | |
4623 | ||
4624 | nzcv = tcg_temp_new_i32(); | |
4625 | tcg_gen_extrl_i64_i32(nzcv, tcg_rn); | |
4626 | ||
4627 | if (mask & 8) { /* N */ | |
4628 | tcg_gen_shli_i32(cpu_NF, nzcv, 31 - 3); | |
4629 | } | |
4630 | if (mask & 4) { /* Z */ | |
4631 | tcg_gen_not_i32(cpu_ZF, nzcv); | |
4632 | tcg_gen_andi_i32(cpu_ZF, cpu_ZF, 4); | |
4633 | } | |
4634 | if (mask & 2) { /* C */ | |
4635 | tcg_gen_extract_i32(cpu_CF, nzcv, 1, 1); | |
4636 | } | |
4637 | if (mask & 1) { /* V */ | |
4638 | tcg_gen_shli_i32(cpu_VF, nzcv, 31 - 0); | |
4639 | } | |
4640 | ||
4641 | tcg_temp_free_i32(nzcv); | |
4642 | } | |
4643 | ||
4644 | /* | |
4645 | * Evaluate into flags | |
4646 | * 31 30 29 21 15 14 10 5 4 0 | |
4647 | * +--+--+--+-----------------+---------+----+---------+------+--+------+ | |
4648 | * |sf|op| S| 1 1 0 1 0 0 0 0 | opcode2 | sz | 0 0 1 0 | Rn |o3| mask | | |
4649 | * +--+--+--+-----------------+---------+----+---------+------+--+------+ | |
4650 | */ | |
4651 | static void disas_evaluate_into_flags(DisasContext *s, uint32_t insn) | |
4652 | { | |
4653 | int o3_mask = extract32(insn, 0, 5); | |
4654 | int rn = extract32(insn, 5, 5); | |
4655 | int o2 = extract32(insn, 15, 6); | |
4656 | int sz = extract32(insn, 14, 1); | |
4657 | int sf_op_s = extract32(insn, 29, 3); | |
4658 | TCGv_i32 tmp; | |
4659 | int shift; | |
4660 | ||
4661 | if (sf_op_s != 1 || o2 != 0 || o3_mask != 0xd || | |
4662 | !dc_isar_feature(aa64_condm_4, s)) { | |
4663 | unallocated_encoding(s); | |
4664 | return; | |
4665 | } | |
4666 | shift = sz ? 16 : 24; /* SETF16 or SETF8 */ | |
4667 | ||
4668 | tmp = tcg_temp_new_i32(); | |
4669 | tcg_gen_extrl_i64_i32(tmp, cpu_reg(s, rn)); | |
4670 | tcg_gen_shli_i32(cpu_NF, tmp, shift); | |
4671 | tcg_gen_shli_i32(cpu_VF, tmp, shift - 1); | |
4672 | tcg_gen_mov_i32(cpu_ZF, cpu_NF); | |
4673 | tcg_gen_xor_i32(cpu_VF, cpu_VF, cpu_NF); | |
4674 | tcg_temp_free_i32(tmp); | |
4675 | } | |
4676 | ||
4ce31af4 | 4677 | /* Conditional compare (immediate / register) |
750813cf CF |
4678 | * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0 |
4679 | * +--+--+--+------------------------+--------+------+----+--+------+--+-----+ | |
4680 | * |sf|op| S| 1 1 0 1 0 0 1 0 |imm5/rm | cond |i/r |o2| Rn |o3|nzcv | | |
4681 | * +--+--+--+------------------------+--------+------+----+--+------+--+-----+ | |
4682 | * [1] y [0] [0] | |
4683 | */ | |
4684 | static void disas_cc(DisasContext *s, uint32_t insn) | |
ad7ee8a2 | 4685 | { |
750813cf | 4686 | unsigned int sf, op, y, cond, rn, nzcv, is_imm; |
7dd03d77 | 4687 | TCGv_i32 tcg_t0, tcg_t1, tcg_t2; |
750813cf | 4688 | TCGv_i64 tcg_tmp, tcg_y, tcg_rn; |
7dd03d77 | 4689 | DisasCompare c; |
ad7ee8a2 | 4690 | |
750813cf CF |
4691 | if (!extract32(insn, 29, 1)) { |
4692 | unallocated_encoding(s); | |
4693 | return; | |
4694 | } | |
4695 | if (insn & (1 << 10 | 1 << 4)) { | |
4696 | unallocated_encoding(s); | |
4697 | return; | |
4698 | } | |
4699 | sf = extract32(insn, 31, 1); | |
4700 | op = extract32(insn, 30, 1); | |
4701 | is_imm = extract32(insn, 11, 1); | |
4702 | y = extract32(insn, 16, 5); /* y = rm (reg) or imm5 (imm) */ | |
4703 | cond = extract32(insn, 12, 4); | |
4704 | rn = extract32(insn, 5, 5); | |
4705 | nzcv = extract32(insn, 0, 4); | |
4706 | ||
7dd03d77 RH |
4707 | /* Set T0 = !COND. */ |
4708 | tcg_t0 = tcg_temp_new_i32(); | |
4709 | arm_test_cc(&c, cond); | |
4710 | tcg_gen_setcondi_i32(tcg_invert_cond(c.cond), tcg_t0, c.value, 0); | |
4711 | arm_free_cc(&c); | |
4712 | ||
4713 | /* Load the arguments for the new comparison. */ | |
750813cf CF |
4714 | if (is_imm) { |
4715 | tcg_y = new_tmp_a64(s); | |
4716 | tcg_gen_movi_i64(tcg_y, y); | |
4717 | } else { | |
4718 | tcg_y = cpu_reg(s, y); | |
4719 | } | |
4720 | tcg_rn = cpu_reg(s, rn); | |
4721 | ||
7dd03d77 | 4722 | /* Set the flags for the new comparison. */ |
750813cf CF |
4723 | tcg_tmp = tcg_temp_new_i64(); |
4724 | if (op) { | |
4725 | gen_sub_CC(sf, tcg_tmp, tcg_rn, tcg_y); | |
4726 | } else { | |
4727 | gen_add_CC(sf, tcg_tmp, tcg_rn, tcg_y); | |
4728 | } | |
4729 | tcg_temp_free_i64(tcg_tmp); | |
4730 | ||
7dd03d77 RH |
4731 | /* If COND was false, force the flags to #nzcv. Compute two masks |
4732 | * to help with this: T1 = (COND ? 0 : -1), T2 = (COND ? -1 : 0). | |
4733 | * For tcg hosts that support ANDC, we can make do with just T1. | |
4734 | * In either case, allow the tcg optimizer to delete any unused mask. | |
4735 | */ | |
4736 | tcg_t1 = tcg_temp_new_i32(); | |
4737 | tcg_t2 = tcg_temp_new_i32(); | |
4738 | tcg_gen_neg_i32(tcg_t1, tcg_t0); | |
4739 | tcg_gen_subi_i32(tcg_t2, tcg_t0, 1); | |
4740 | ||
4741 | if (nzcv & 8) { /* N */ | |
4742 | tcg_gen_or_i32(cpu_NF, cpu_NF, tcg_t1); | |
4743 | } else { | |
4744 | if (TCG_TARGET_HAS_andc_i32) { | |
4745 | tcg_gen_andc_i32(cpu_NF, cpu_NF, tcg_t1); | |
4746 | } else { | |
4747 | tcg_gen_and_i32(cpu_NF, cpu_NF, tcg_t2); | |
4748 | } | |
4749 | } | |
4750 | if (nzcv & 4) { /* Z */ | |
4751 | if (TCG_TARGET_HAS_andc_i32) { | |
4752 | tcg_gen_andc_i32(cpu_ZF, cpu_ZF, tcg_t1); | |
4753 | } else { | |
4754 | tcg_gen_and_i32(cpu_ZF, cpu_ZF, tcg_t2); | |
4755 | } | |
4756 | } else { | |
4757 | tcg_gen_or_i32(cpu_ZF, cpu_ZF, tcg_t0); | |
4758 | } | |
4759 | if (nzcv & 2) { /* C */ | |
4760 | tcg_gen_or_i32(cpu_CF, cpu_CF, tcg_t0); | |
4761 | } else { | |
4762 | if (TCG_TARGET_HAS_andc_i32) { | |
4763 | tcg_gen_andc_i32(cpu_CF, cpu_CF, tcg_t1); | |
4764 | } else { | |
4765 | tcg_gen_and_i32(cpu_CF, cpu_CF, tcg_t2); | |
4766 | } | |
4767 | } | |
4768 | if (nzcv & 1) { /* V */ | |
4769 | tcg_gen_or_i32(cpu_VF, cpu_VF, tcg_t1); | |
4770 | } else { | |
4771 | if (TCG_TARGET_HAS_andc_i32) { | |
4772 | tcg_gen_andc_i32(cpu_VF, cpu_VF, tcg_t1); | |
4773 | } else { | |
4774 | tcg_gen_and_i32(cpu_VF, cpu_VF, tcg_t2); | |
4775 | } | |
750813cf | 4776 | } |
7dd03d77 RH |
4777 | tcg_temp_free_i32(tcg_t0); |
4778 | tcg_temp_free_i32(tcg_t1); | |
4779 | tcg_temp_free_i32(tcg_t2); | |
ad7ee8a2 CF |
4780 | } |
4781 | ||
4ce31af4 | 4782 | /* Conditional select |
e952d8c7 CF |
4783 | * 31 30 29 28 21 20 16 15 12 11 10 9 5 4 0 |
4784 | * +----+----+---+-----------------+------+------+-----+------+------+ | |
4785 | * | sf | op | S | 1 1 0 1 0 1 0 0 | Rm | cond | op2 | Rn | Rd | | |
4786 | * +----+----+---+-----------------+------+------+-----+------+------+ | |
4787 | */ | |
ad7ee8a2 CF |
4788 | static void disas_cond_select(DisasContext *s, uint32_t insn) |
4789 | { | |
e952d8c7 | 4790 | unsigned int sf, else_inv, rm, cond, else_inc, rn, rd; |
259cb684 RH |
4791 | TCGv_i64 tcg_rd, zero; |
4792 | DisasCompare64 c; | |
e952d8c7 CF |
4793 | |
4794 | if (extract32(insn, 29, 1) || extract32(insn, 11, 1)) { | |
4795 | /* S == 1 or op2<1> == 1 */ | |
4796 | unallocated_encoding(s); | |
4797 | return; | |
4798 | } | |
4799 | sf = extract32(insn, 31, 1); | |
4800 | else_inv = extract32(insn, 30, 1); | |
4801 | rm = extract32(insn, 16, 5); | |
4802 | cond = extract32(insn, 12, 4); | |
4803 | else_inc = extract32(insn, 10, 1); | |
4804 | rn = extract32(insn, 5, 5); | |
4805 | rd = extract32(insn, 0, 5); | |
4806 | ||
e952d8c7 CF |
4807 | tcg_rd = cpu_reg(s, rd); |
4808 | ||
259cb684 RH |
4809 | a64_test_cc(&c, cond); |
4810 | zero = tcg_const_i64(0); | |
e952d8c7 | 4811 | |
259cb684 RH |
4812 | if (rn == 31 && rm == 31 && (else_inc ^ else_inv)) { |
4813 | /* CSET & CSETM. */ | |
4814 | tcg_gen_setcond_i64(tcg_invert_cond(c.cond), tcg_rd, c.value, zero); | |
4815 | if (else_inv) { | |
4816 | tcg_gen_neg_i64(tcg_rd, tcg_rd); | |
4817 | } | |
4818 | } else { | |
4819 | TCGv_i64 t_true = cpu_reg(s, rn); | |
4820 | TCGv_i64 t_false = read_cpu_reg(s, rm, 1); | |
e952d8c7 | 4821 | if (else_inv && else_inc) { |
259cb684 | 4822 | tcg_gen_neg_i64(t_false, t_false); |
e952d8c7 | 4823 | } else if (else_inv) { |
259cb684 | 4824 | tcg_gen_not_i64(t_false, t_false); |
e952d8c7 | 4825 | } else if (else_inc) { |
259cb684 | 4826 | tcg_gen_addi_i64(t_false, t_false, 1); |
e952d8c7 | 4827 | } |
259cb684 RH |
4828 | tcg_gen_movcond_i64(c.cond, tcg_rd, c.value, zero, t_true, t_false); |
4829 | } | |
4830 | ||
4831 | tcg_temp_free_i64(zero); | |
4832 | a64_free_cc(&c); | |
4833 | ||
4834 | if (!sf) { | |
4835 | tcg_gen_ext32u_i64(tcg_rd, tcg_rd); | |
e952d8c7 | 4836 | } |
ad7ee8a2 CF |
4837 | } |
4838 | ||
680ead21 CF |
4839 | static void handle_clz(DisasContext *s, unsigned int sf, |
4840 | unsigned int rn, unsigned int rd) | |
4841 | { | |
4842 | TCGv_i64 tcg_rd, tcg_rn; | |
4843 | tcg_rd = cpu_reg(s, rd); | |
4844 | tcg_rn = cpu_reg(s, rn); | |
4845 | ||
4846 | if (sf) { | |
7539a012 | 4847 | tcg_gen_clzi_i64(tcg_rd, tcg_rn, 64); |
680ead21 CF |
4848 | } else { |
4849 | TCGv_i32 tcg_tmp32 = tcg_temp_new_i32(); | |
ecc7b3aa | 4850 | tcg_gen_extrl_i64_i32(tcg_tmp32, tcg_rn); |
7539a012 | 4851 | tcg_gen_clzi_i32(tcg_tmp32, tcg_tmp32, 32); |
680ead21 CF |
4852 | tcg_gen_extu_i32_i64(tcg_rd, tcg_tmp32); |
4853 | tcg_temp_free_i32(tcg_tmp32); | |
4854 | } | |
4855 | } | |
4856 | ||
e80c5020 CF |
4857 | static void handle_cls(DisasContext *s, unsigned int sf, |
4858 | unsigned int rn, unsigned int rd) | |
4859 | { | |
4860 | TCGv_i64 tcg_rd, tcg_rn; | |
4861 | tcg_rd = cpu_reg(s, rd); | |
4862 | tcg_rn = cpu_reg(s, rn); | |
4863 | ||
4864 | if (sf) { | |
bc21dbcc | 4865 | tcg_gen_clrsb_i64(tcg_rd, tcg_rn); |
e80c5020 CF |
4866 | } else { |
4867 | TCGv_i32 tcg_tmp32 = tcg_temp_new_i32(); | |
ecc7b3aa | 4868 | tcg_gen_extrl_i64_i32(tcg_tmp32, tcg_rn); |
bc21dbcc | 4869 | tcg_gen_clrsb_i32(tcg_tmp32, tcg_tmp32); |
e80c5020 CF |
4870 | tcg_gen_extu_i32_i64(tcg_rd, tcg_tmp32); |
4871 | tcg_temp_free_i32(tcg_tmp32); | |
4872 | } | |
4873 | } | |
4874 | ||
82e14b02 AG |
4875 | static void handle_rbit(DisasContext *s, unsigned int sf, |
4876 | unsigned int rn, unsigned int rd) | |
4877 | { | |
4878 | TCGv_i64 tcg_rd, tcg_rn; | |
4879 | tcg_rd = cpu_reg(s, rd); | |
4880 | tcg_rn = cpu_reg(s, rn); | |
4881 | ||
4882 | if (sf) { | |
4883 | gen_helper_rbit64(tcg_rd, tcg_rn); | |
4884 | } else { | |
4885 | TCGv_i32 tcg_tmp32 = tcg_temp_new_i32(); | |
ecc7b3aa | 4886 | tcg_gen_extrl_i64_i32(tcg_tmp32, tcg_rn); |
82e14b02 AG |
4887 | gen_helper_rbit(tcg_tmp32, tcg_tmp32); |
4888 | tcg_gen_extu_i32_i64(tcg_rd, tcg_tmp32); | |
4889 | tcg_temp_free_i32(tcg_tmp32); | |
4890 | } | |
4891 | } | |
4892 | ||
4ce31af4 | 4893 | /* REV with sf==1, opcode==3 ("REV64") */ |
45323209 CF |
4894 | static void handle_rev64(DisasContext *s, unsigned int sf, |
4895 | unsigned int rn, unsigned int rd) | |
4896 | { | |
4897 | if (!sf) { | |
4898 | unallocated_encoding(s); | |
4899 | return; | |
4900 | } | |
4901 | tcg_gen_bswap64_i64(cpu_reg(s, rd), cpu_reg(s, rn)); | |
4902 | } | |
4903 | ||
4ce31af4 PM |
4904 | /* REV with sf==0, opcode==2 |
4905 | * REV32 (sf==1, opcode==2) | |
45323209 CF |
4906 | */ |
4907 | static void handle_rev32(DisasContext *s, unsigned int sf, | |
4908 | unsigned int rn, unsigned int rd) | |
4909 | { | |
4910 | TCGv_i64 tcg_rd = cpu_reg(s, rd); | |
4911 | ||
4912 | if (sf) { | |
4913 | TCGv_i64 tcg_tmp = tcg_temp_new_i64(); | |
4914 | TCGv_i64 tcg_rn = read_cpu_reg(s, rn, sf); | |
4915 | ||
4916 | /* bswap32_i64 requires zero high word */ | |
4917 | tcg_gen_ext32u_i64(tcg_tmp, tcg_rn); | |
4918 | tcg_gen_bswap32_i64(tcg_rd, tcg_tmp); | |
4919 | tcg_gen_shri_i64(tcg_tmp, tcg_rn, 32); | |
4920 | tcg_gen_bswap32_i64(tcg_tmp, tcg_tmp); | |
4921 | tcg_gen_concat32_i64(tcg_rd, tcg_rd, tcg_tmp); | |
4922 | ||
4923 | tcg_temp_free_i64(tcg_tmp); | |
4924 | } else { | |
4925 | tcg_gen_ext32u_i64(tcg_rd, cpu_reg(s, rn)); | |
4926 | tcg_gen_bswap32_i64(tcg_rd, tcg_rd); | |
4927 | } | |
4928 | } | |
4929 | ||
4ce31af4 | 4930 | /* REV16 (opcode==1) */ |
45323209 CF |
4931 | static void handle_rev16(DisasContext *s, unsigned int sf, |
4932 | unsigned int rn, unsigned int rd) | |
4933 | { | |
4934 | TCGv_i64 tcg_rd = cpu_reg(s, rd); | |
4935 | TCGv_i64 tcg_tmp = tcg_temp_new_i64(); | |
4936 | TCGv_i64 tcg_rn = read_cpu_reg(s, rn, sf); | |
abb1066d | 4937 | TCGv_i64 mask = tcg_const_i64(sf ? 0x00ff00ff00ff00ffull : 0x00ff00ff); |
45323209 | 4938 | |
abb1066d RH |
4939 | tcg_gen_shri_i64(tcg_tmp, tcg_rn, 8); |
4940 | tcg_gen_and_i64(tcg_rd, tcg_rn, mask); | |
4941 | tcg_gen_and_i64(tcg_tmp, tcg_tmp, mask); | |
4942 | tcg_gen_shli_i64(tcg_rd, tcg_rd, 8); | |
4943 | tcg_gen_or_i64(tcg_rd, tcg_rd, tcg_tmp); | |
45323209 | 4944 | |
e4256c3c | 4945 | tcg_temp_free_i64(mask); |
45323209 CF |
4946 | tcg_temp_free_i64(tcg_tmp); |
4947 | } | |
4948 | ||
4ce31af4 | 4949 | /* Data-processing (1 source) |
680ead21 CF |
4950 | * 31 30 29 28 21 20 16 15 10 9 5 4 0 |
4951 | * +----+---+---+-----------------+---------+--------+------+------+ | |
4952 | * | sf | 1 | S | 1 1 0 1 0 1 1 0 | opcode2 | opcode | Rn | Rd | | |
4953 | * +----+---+---+-----------------+---------+--------+------+------+ | |
4954 | */ | |
ad7ee8a2 CF |
4955 | static void disas_data_proc_1src(DisasContext *s, uint32_t insn) |
4956 | { | |
18de2813 | 4957 | unsigned int sf, opcode, opcode2, rn, rd; |
95ebd99d | 4958 | TCGv_i64 tcg_rd; |
680ead21 | 4959 | |
18de2813 | 4960 | if (extract32(insn, 29, 1)) { |
680ead21 CF |
4961 | unallocated_encoding(s); |
4962 | return; | |
4963 | } | |
4964 | ||
4965 | sf = extract32(insn, 31, 1); | |
4966 | opcode = extract32(insn, 10, 6); | |
18de2813 | 4967 | opcode2 = extract32(insn, 16, 5); |
680ead21 CF |
4968 | rn = extract32(insn, 5, 5); |
4969 | rd = extract32(insn, 0, 5); | |
4970 | ||
18de2813 RH |
4971 | #define MAP(SF, O2, O1) ((SF) | (O1 << 1) | (O2 << 7)) |
4972 | ||
4973 | switch (MAP(sf, opcode2, opcode)) { | |
4974 | case MAP(0, 0x00, 0x00): /* RBIT */ | |
4975 | case MAP(1, 0x00, 0x00): | |
82e14b02 AG |
4976 | handle_rbit(s, sf, rn, rd); |
4977 | break; | |
18de2813 RH |
4978 | case MAP(0, 0x00, 0x01): /* REV16 */ |
4979 | case MAP(1, 0x00, 0x01): | |
45323209 CF |
4980 | handle_rev16(s, sf, rn, rd); |
4981 | break; | |
18de2813 RH |
4982 | case MAP(0, 0x00, 0x02): /* REV/REV32 */ |
4983 | case MAP(1, 0x00, 0x02): | |
45323209 CF |
4984 | handle_rev32(s, sf, rn, rd); |
4985 | break; | |
18de2813 | 4986 | case MAP(1, 0x00, 0x03): /* REV64 */ |
45323209 | 4987 | handle_rev64(s, sf, rn, rd); |
680ead21 | 4988 | break; |
18de2813 RH |
4989 | case MAP(0, 0x00, 0x04): /* CLZ */ |
4990 | case MAP(1, 0x00, 0x04): | |
680ead21 CF |
4991 | handle_clz(s, sf, rn, rd); |
4992 | break; | |
18de2813 RH |
4993 | case MAP(0, 0x00, 0x05): /* CLS */ |
4994 | case MAP(1, 0x00, 0x05): | |
e80c5020 | 4995 | handle_cls(s, sf, rn, rd); |
680ead21 | 4996 | break; |
95ebd99d RH |
4997 | case MAP(1, 0x01, 0x00): /* PACIA */ |
4998 | if (s->pauth_active) { | |
4999 | tcg_rd = cpu_reg(s, rd); | |
5000 | gen_helper_pacia(tcg_rd, cpu_env, tcg_rd, cpu_reg_sp(s, rn)); | |
5001 | } else if (!dc_isar_feature(aa64_pauth, s)) { | |
5002 | goto do_unallocated; | |
5003 | } | |
5004 | break; | |
5005 | case MAP(1, 0x01, 0x01): /* PACIB */ | |
5006 | if (s->pauth_active) { | |
5007 | tcg_rd = cpu_reg(s, rd); | |
5008 | gen_helper_pacib(tcg_rd, cpu_env, tcg_rd, cpu_reg_sp(s, rn)); | |
5009 | } else if (!dc_isar_feature(aa64_pauth, s)) { | |
5010 | goto do_unallocated; | |
5011 | } | |
5012 | break; | |
5013 | case MAP(1, 0x01, 0x02): /* PACDA */ | |
5014 | if (s->pauth_active) { | |
5015 | tcg_rd = cpu_reg(s, rd); | |
5016 | gen_helper_pacda(tcg_rd, cpu_env, tcg_rd, cpu_reg_sp(s, rn)); | |
5017 | } else if (!dc_isar_feature(aa64_pauth, s)) { | |
5018 | goto do_unallocated; | |
5019 | } | |
5020 | break; | |
5021 | case MAP(1, 0x01, 0x03): /* PACDB */ | |
5022 | if (s->pauth_active) { | |
5023 | tcg_rd = cpu_reg(s, rd); | |
5024 | gen_helper_pacdb(tcg_rd, cpu_env, tcg_rd, cpu_reg_sp(s, rn)); | |
5025 | } else if (!dc_isar_feature(aa64_pauth, s)) { | |
5026 | goto do_unallocated; | |
5027 | } | |
5028 | break; | |
5029 | case MAP(1, 0x01, 0x04): /* AUTIA */ | |
5030 | if (s->pauth_active) { | |
5031 | tcg_rd = cpu_reg(s, rd); | |
5032 | gen_helper_autia(tcg_rd, cpu_env, tcg_rd, cpu_reg_sp(s, rn)); | |
5033 | } else if (!dc_isar_feature(aa64_pauth, s)) { | |
5034 | goto do_unallocated; | |
5035 | } | |
5036 | break; | |
5037 | case MAP(1, 0x01, 0x05): /* AUTIB */ | |
5038 | if (s->pauth_active) { | |
5039 | tcg_rd = cpu_reg(s, rd); | |
5040 | gen_helper_autib(tcg_rd, cpu_env, tcg_rd, cpu_reg_sp(s, rn)); | |
5041 | } else if (!dc_isar_feature(aa64_pauth, s)) { | |
5042 | goto do_unallocated; | |
5043 | } | |
5044 | break; | |
5045 | case MAP(1, 0x01, 0x06): /* AUTDA */ | |
5046 | if (s->pauth_active) { | |
5047 | tcg_rd = cpu_reg(s, rd); | |
5048 | gen_helper_autda(tcg_rd, cpu_env, tcg_rd, cpu_reg_sp(s, rn)); | |
5049 | } else if (!dc_isar_feature(aa64_pauth, s)) { | |
5050 | goto do_unallocated; | |
5051 | } | |
5052 | break; | |
5053 | case MAP(1, 0x01, 0x07): /* AUTDB */ | |
5054 | if (s->pauth_active) { | |
5055 | tcg_rd = cpu_reg(s, rd); | |
5056 | gen_helper_autdb(tcg_rd, cpu_env, tcg_rd, cpu_reg_sp(s, rn)); | |
5057 | } else if (!dc_isar_feature(aa64_pauth, s)) { | |
5058 | goto do_unallocated; | |
5059 | } | |
5060 | break; | |
5061 | case MAP(1, 0x01, 0x08): /* PACIZA */ | |
5062 | if (!dc_isar_feature(aa64_pauth, s) || rn != 31) { | |
5063 | goto do_unallocated; | |
5064 | } else if (s->pauth_active) { | |
5065 | tcg_rd = cpu_reg(s, rd); | |
5066 | gen_helper_pacia(tcg_rd, cpu_env, tcg_rd, new_tmp_a64_zero(s)); | |
5067 | } | |
5068 | break; | |
5069 | case MAP(1, 0x01, 0x09): /* PACIZB */ | |
5070 | if (!dc_isar_feature(aa64_pauth, s) || rn != 31) { | |
5071 | goto do_unallocated; | |
5072 | } else if (s->pauth_active) { | |
5073 | tcg_rd = cpu_reg(s, rd); | |
5074 | gen_helper_pacib(tcg_rd, cpu_env, tcg_rd, new_tmp_a64_zero(s)); | |
5075 | } | |
5076 | break; | |
5077 | case MAP(1, 0x01, 0x0a): /* PACDZA */ | |
5078 | if (!dc_isar_feature(aa64_pauth, s) || rn != 31) { | |
5079 | goto do_unallocated; | |
5080 | } else if (s->pauth_active) { | |
5081 | tcg_rd = cpu_reg(s, rd); | |
5082 | gen_helper_pacda(tcg_rd, cpu_env, tcg_rd, new_tmp_a64_zero(s)); | |
5083 | } | |
5084 | break; | |
5085 | case MAP(1, 0x01, 0x0b): /* PACDZB */ | |
5086 | if (!dc_isar_feature(aa64_pauth, s) || rn != 31) { | |
5087 | goto do_unallocated; | |
5088 | } else if (s->pauth_active) { | |
5089 | tcg_rd = cpu_reg(s, rd); | |
5090 | gen_helper_pacdb(tcg_rd, cpu_env, tcg_rd, new_tmp_a64_zero(s)); | |
5091 | } | |
5092 | break; | |
5093 | case MAP(1, 0x01, 0x0c): /* AUTIZA */ | |
5094 | if (!dc_isar_feature(aa64_pauth, s) || rn != 31) { | |
5095 | goto do_unallocated; | |
5096 | } else if (s->pauth_active) { | |
5097 | tcg_rd = cpu_reg(s, rd); | |
5098 | gen_helper_autia(tcg_rd, cpu_env, tcg_rd, new_tmp_a64_zero(s)); | |
5099 | } | |
5100 | break; | |
5101 | case MAP(1, 0x01, 0x0d): /* AUTIZB */ | |
5102 | if (!dc_isar_feature(aa64_pauth, s) || rn != 31) { | |
5103 | goto do_unallocated; | |
5104 | } else if (s->pauth_active) { | |
5105 | tcg_rd = cpu_reg(s, rd); | |
5106 | gen_helper_autib(tcg_rd, cpu_env, tcg_rd, new_tmp_a64_zero(s)); | |
5107 | } | |
5108 | break; | |
5109 | case MAP(1, 0x01, 0x0e): /* AUTDZA */ | |
5110 | if (!dc_isar_feature(aa64_pauth, s) || rn != 31) { | |
5111 | goto do_unallocated; | |
5112 | } else if (s->pauth_active) { | |
5113 | tcg_rd = cpu_reg(s, rd); | |
5114 | gen_helper_autda(tcg_rd, cpu_env, tcg_rd, new_tmp_a64_zero(s)); | |
5115 | } | |
5116 | break; | |
5117 | case MAP(1, 0x01, 0x0f): /* AUTDZB */ | |
5118 | if (!dc_isar_feature(aa64_pauth, s) || rn != 31) { | |
5119 | goto do_unallocated; | |
5120 | } else if (s->pauth_active) { | |
5121 | tcg_rd = cpu_reg(s, rd); | |
5122 | gen_helper_autdb(tcg_rd, cpu_env, tcg_rd, new_tmp_a64_zero(s)); | |
5123 | } | |
5124 | break; | |
5125 | case MAP(1, 0x01, 0x10): /* XPACI */ | |
5126 | if (!dc_isar_feature(aa64_pauth, s) || rn != 31) { | |
5127 | goto do_unallocated; | |
5128 | } else if (s->pauth_active) { | |
5129 | tcg_rd = cpu_reg(s, rd); | |
5130 | gen_helper_xpaci(tcg_rd, cpu_env, tcg_rd); | |
5131 | } | |
5132 | break; | |
5133 | case MAP(1, 0x01, 0x11): /* XPACD */ | |
5134 | if (!dc_isar_feature(aa64_pauth, s) || rn != 31) { | |
5135 | goto do_unallocated; | |
5136 | } else if (s->pauth_active) { | |
5137 | tcg_rd = cpu_reg(s, rd); | |
5138 | gen_helper_xpacd(tcg_rd, cpu_env, tcg_rd); | |
5139 | } | |
5140 | break; | |
18de2813 | 5141 | default: |
95ebd99d | 5142 | do_unallocated: |
18de2813 RH |
5143 | unallocated_encoding(s); |
5144 | break; | |
680ead21 | 5145 | } |
18de2813 RH |
5146 | |
5147 | #undef MAP | |
ad7ee8a2 CF |
5148 | } |
5149 | ||
8220e911 AG |
5150 | static void handle_div(DisasContext *s, bool is_signed, unsigned int sf, |
5151 | unsigned int rm, unsigned int rn, unsigned int rd) | |
5152 | { | |
5153 | TCGv_i64 tcg_n, tcg_m, tcg_rd; | |
5154 | tcg_rd = cpu_reg(s, rd); | |
5155 | ||
5156 | if (!sf && is_signed) { | |
5157 | tcg_n = new_tmp_a64(s); | |
5158 | tcg_m = new_tmp_a64(s); | |
5159 | tcg_gen_ext32s_i64(tcg_n, cpu_reg(s, rn)); | |
5160 | tcg_gen_ext32s_i64(tcg_m, cpu_reg(s, rm)); | |
5161 | } else { | |
5162 | tcg_n = read_cpu_reg(s, rn, sf); | |
5163 | tcg_m = read_cpu_reg(s, rm, sf); | |
5164 | } | |
5165 | ||
5166 | if (is_signed) { | |
5167 | gen_helper_sdiv64(tcg_rd, tcg_n, tcg_m); | |
5168 | } else { | |
5169 | gen_helper_udiv64(tcg_rd, tcg_n, tcg_m); | |
5170 | } | |
5171 | ||
5172 | if (!sf) { /* zero extend final result */ | |
5173 | tcg_gen_ext32u_i64(tcg_rd, tcg_rd); | |
5174 | } | |
5175 | } | |
5176 | ||
4ce31af4 | 5177 | /* LSLV, LSRV, ASRV, RORV */ |
6c1adc91 AG |
5178 | static void handle_shift_reg(DisasContext *s, |
5179 | enum a64_shift_type shift_type, unsigned int sf, | |
5180 | unsigned int rm, unsigned int rn, unsigned int rd) | |
5181 | { | |
5182 | TCGv_i64 tcg_shift = tcg_temp_new_i64(); | |
5183 | TCGv_i64 tcg_rd = cpu_reg(s, rd); | |
5184 | TCGv_i64 tcg_rn = read_cpu_reg(s, rn, sf); | |
5185 | ||
5186 | tcg_gen_andi_i64(tcg_shift, cpu_reg(s, rm), sf ? 63 : 31); | |
5187 | shift_reg(tcg_rd, tcg_rn, sf, shift_type, tcg_shift); | |
5188 | tcg_temp_free_i64(tcg_shift); | |
5189 | } | |
5190 | ||
130f2e7d PM |
5191 | /* CRC32[BHWX], CRC32C[BHWX] */ |
5192 | static void handle_crc32(DisasContext *s, | |
5193 | unsigned int sf, unsigned int sz, bool crc32c, | |
5194 | unsigned int rm, unsigned int rn, unsigned int rd) | |
5195 | { | |
5196 | TCGv_i64 tcg_acc, tcg_val; | |
5197 | TCGv_i32 tcg_bytes; | |
5198 | ||
962fcbf2 | 5199 | if (!dc_isar_feature(aa64_crc32, s) |
130f2e7d PM |
5200 | || (sf == 1 && sz != 3) |
5201 | || (sf == 0 && sz == 3)) { | |
5202 | unallocated_encoding(s); | |
5203 | return; | |
5204 | } | |
5205 | ||
5206 | if (sz == 3) { | |
5207 | tcg_val = cpu_reg(s, rm); | |
5208 | } else { | |
5209 | uint64_t mask; | |
5210 | switch (sz) { | |
5211 | case 0: | |
5212 | mask = 0xFF; | |
5213 | break; | |
5214 | case 1: | |
5215 | mask = 0xFFFF; | |
5216 | break; | |
5217 | case 2: | |
5218 | mask = 0xFFFFFFFF; | |
5219 | break; | |
5220 | default: | |
5221 | g_assert_not_reached(); | |
5222 | } | |
5223 | tcg_val = new_tmp_a64(s); | |
5224 | tcg_gen_andi_i64(tcg_val, cpu_reg(s, rm), mask); | |
5225 | } | |
5226 | ||
5227 | tcg_acc = cpu_reg(s, rn); | |
5228 | tcg_bytes = tcg_const_i32(1 << sz); | |
5229 | ||
5230 | if (crc32c) { | |
5231 | gen_helper_crc32c_64(cpu_reg(s, rd), tcg_acc, tcg_val, tcg_bytes); | |
5232 | } else { | |
5233 | gen_helper_crc32_64(cpu_reg(s, rd), tcg_acc, tcg_val, tcg_bytes); | |
5234 | } | |
5235 | ||
5236 | tcg_temp_free_i32(tcg_bytes); | |
5237 | } | |
5238 | ||
4ce31af4 | 5239 | /* Data-processing (2 source) |
8220e911 AG |
5240 | * 31 30 29 28 21 20 16 15 10 9 5 4 0 |
5241 | * +----+---+---+-----------------+------+--------+------+------+ | |
5242 | * | sf | 0 | S | 1 1 0 1 0 1 1 0 | Rm | opcode | Rn | Rd | | |
5243 | * +----+---+---+-----------------+------+--------+------+------+ | |
5244 | */ | |
ad7ee8a2 CF |
5245 | static void disas_data_proc_2src(DisasContext *s, uint32_t insn) |
5246 | { | |
8220e911 AG |
5247 | unsigned int sf, rm, opcode, rn, rd; |
5248 | sf = extract32(insn, 31, 1); | |
5249 | rm = extract32(insn, 16, 5); | |
5250 | opcode = extract32(insn, 10, 6); | |
5251 | rn = extract32(insn, 5, 5); | |
5252 | rd = extract32(insn, 0, 5); | |
5253 | ||
5254 | if (extract32(insn, 29, 1)) { | |
5255 | unallocated_encoding(s); | |
5256 | return; | |
5257 | } | |
5258 | ||
5259 | switch (opcode) { | |
5260 | case 2: /* UDIV */ | |
5261 | handle_div(s, false, sf, rm, rn, rd); | |
5262 | break; | |
5263 | case 3: /* SDIV */ | |
5264 | handle_div(s, true, sf, rm, rn, rd); | |
5265 | break; | |
5266 | case 8: /* LSLV */ | |
6c1adc91 AG |
5267 | handle_shift_reg(s, A64_SHIFT_TYPE_LSL, sf, rm, rn, rd); |
5268 | break; | |
8220e911 | 5269 | case 9: /* LSRV */ |
6c1adc91 AG |
5270 | handle_shift_reg(s, A64_SHIFT_TYPE_LSR, sf, rm, rn, rd); |
5271 | break; | |
8220e911 | 5272 | case 10: /* ASRV */ |
6c1adc91 AG |
5273 | handle_shift_reg(s, A64_SHIFT_TYPE_ASR, sf, rm, rn, rd); |
5274 | break; | |
8220e911 | 5275 | case 11: /* RORV */ |
6c1adc91 AG |
5276 | handle_shift_reg(s, A64_SHIFT_TYPE_ROR, sf, rm, rn, rd); |
5277 | break; | |
b6342a9f RH |
5278 | case 12: /* PACGA */ |
5279 | if (sf == 0 || !dc_isar_feature(aa64_pauth, s)) { | |
5280 | goto do_unallocated; | |
5281 | } | |
5282 | gen_helper_pacga(cpu_reg(s, rd), cpu_env, | |
5283 | cpu_reg(s, rn), cpu_reg_sp(s, rm)); | |
5284 | break; | |
8220e911 AG |
5285 | case 16: |
5286 | case 17: | |
5287 | case 18: | |
5288 | case 19: | |
5289 | case 20: | |
5290 | case 21: | |
5291 | case 22: | |
5292 | case 23: /* CRC32 */ | |
130f2e7d PM |
5293 | { |
5294 | int sz = extract32(opcode, 0, 2); | |
5295 | bool crc32c = extract32(opcode, 2, 1); | |
5296 | handle_crc32(s, sf, sz, crc32c, rm, rn, rd); | |
8220e911 | 5297 | break; |
130f2e7d | 5298 | } |
8220e911 | 5299 | default: |
b6342a9f | 5300 | do_unallocated: |
8220e911 AG |
5301 | unallocated_encoding(s); |
5302 | break; | |
5303 | } | |
ad7ee8a2 CF |
5304 | } |
5305 | ||
2fba34f7 RH |
5306 | /* |
5307 | * Data processing - register | |
5308 | * 31 30 29 28 25 21 20 16 10 0 | |
5309 | * +--+---+--+---+-------+-----+-------+-------+---------+ | |
5310 | * | |op0| |op1| 1 0 1 | op2 | | op3 | | | |
5311 | * +--+---+--+---+-------+-----+-------+-------+---------+ | |
5312 | */ | |
ad7ee8a2 CF |
5313 | static void disas_data_proc_reg(DisasContext *s, uint32_t insn) |
5314 | { | |
2fba34f7 RH |
5315 | int op0 = extract32(insn, 30, 1); |
5316 | int op1 = extract32(insn, 28, 1); | |
5317 | int op2 = extract32(insn, 21, 4); | |
5318 | int op3 = extract32(insn, 10, 6); | |
5319 | ||
5320 | if (!op1) { | |
5321 | if (op2 & 8) { | |
5322 | if (op2 & 1) { | |
5323 | /* Add/sub (extended register) */ | |
5324 | disas_add_sub_ext_reg(s, insn); | |
5325 | } else { | |
5326 | /* Add/sub (shifted register) */ | |
5327 | disas_add_sub_reg(s, insn); | |
5328 | } | |
ad7ee8a2 | 5329 | } else { |
2fba34f7 RH |
5330 | /* Logical (shifted register) */ |
5331 | disas_logic_reg(s, insn); | |
ad7ee8a2 | 5332 | } |
2fba34f7 RH |
5333 | return; |
5334 | } | |
5335 | ||
5336 | switch (op2) { | |
5337 | case 0x0: | |
5338 | switch (op3) { | |
5339 | case 0x00: /* Add/subtract (with carry) */ | |
ad7ee8a2 CF |
5340 | disas_adc_sbc(s, insn); |
5341 | break; | |
2fba34f7 | 5342 | |
b89d9c98 RH |
5343 | case 0x01: /* Rotate right into flags */ |
5344 | case 0x21: | |
5345 | disas_rotate_right_into_flags(s, insn); | |
5346 | break; | |
5347 | ||
5348 | case 0x02: /* Evaluate into flags */ | |
5349 | case 0x12: | |
5350 | case 0x22: | |
5351 | case 0x32: | |
5352 | disas_evaluate_into_flags(s, insn); | |
5353 | break; | |
5354 | ||
ad7ee8a2 | 5355 | default: |
2fba34f7 | 5356 | goto do_unallocated; |
ad7ee8a2 CF |
5357 | } |
5358 | break; | |
2fba34f7 RH |
5359 | |
5360 | case 0x2: /* Conditional compare */ | |
5361 | disas_cc(s, insn); /* both imm and reg forms */ | |
5362 | break; | |
5363 | ||
5364 | case 0x4: /* Conditional select */ | |
5365 | disas_cond_select(s, insn); | |
5366 | break; | |
5367 | ||
5368 | case 0x6: /* Data-processing */ | |
5369 | if (op0) { /* (1 source) */ | |
5370 | disas_data_proc_1src(s, insn); | |
5371 | } else { /* (2 source) */ | |
5372 | disas_data_proc_2src(s, insn); | |
5373 | } | |
5374 | break; | |
5375 | case 0x8 ... 0xf: /* (3 source) */ | |
5376 | disas_data_proc_3src(s, insn); | |
5377 | break; | |
5378 | ||
ad7ee8a2 | 5379 | default: |
2fba34f7 | 5380 | do_unallocated: |
ad7ee8a2 CF |
5381 | unallocated_encoding(s); |
5382 | break; | |
5383 | } | |
5384 | } | |
5385 | ||
7a192925 | 5386 | static void handle_fp_compare(DisasContext *s, int size, |
da7dafe7 CF |
5387 | unsigned int rn, unsigned int rm, |
5388 | bool cmp_with_zero, bool signal_all_nans) | |
5389 | { | |
5390 | TCGv_i64 tcg_flags = tcg_temp_new_i64(); | |
7a192925 | 5391 | TCGv_ptr fpst = get_fpstatus_ptr(size == MO_16); |
da7dafe7 | 5392 | |
7a192925 | 5393 | if (size == MO_64) { |
da7dafe7 CF |
5394 | TCGv_i64 tcg_vn, tcg_vm; |
5395 | ||
5396 | tcg_vn = read_fp_dreg(s, rn); | |
5397 | if (cmp_with_zero) { | |
5398 | tcg_vm = tcg_const_i64(0); | |
5399 | } else { | |
5400 | tcg_vm = read_fp_dreg(s, rm); | |
5401 | } | |
5402 | if (signal_all_nans) { | |
5403 | gen_helper_vfp_cmped_a64(tcg_flags, tcg_vn, tcg_vm, fpst); | |
5404 | } else { | |
5405 | gen_helper_vfp_cmpd_a64(tcg_flags, tcg_vn, tcg_vm, fpst); | |
5406 | } | |
5407 | tcg_temp_free_i64(tcg_vn); | |
5408 | tcg_temp_free_i64(tcg_vm); | |
5409 | } else { | |
7a192925 AB |
5410 | TCGv_i32 tcg_vn = tcg_temp_new_i32(); |
5411 | TCGv_i32 tcg_vm = tcg_temp_new_i32(); | |
da7dafe7 | 5412 | |
7a192925 | 5413 | read_vec_element_i32(s, tcg_vn, rn, 0, size); |
da7dafe7 | 5414 | if (cmp_with_zero) { |
7a192925 | 5415 | tcg_gen_movi_i32(tcg_vm, 0); |
da7dafe7 | 5416 | } else { |
7a192925 | 5417 | read_vec_element_i32(s, tcg_vm, rm, 0, size); |
da7dafe7 | 5418 | } |
7a192925 AB |
5419 | |
5420 | switch (size) { | |
5421 | case MO_32: | |
5422 | if (signal_all_nans) { | |
5423 | gen_helper_vfp_cmpes_a64(tcg_flags, tcg_vn, tcg_vm, fpst); | |
5424 | } else { | |
5425 | gen_helper_vfp_cmps_a64(tcg_flags, tcg_vn, tcg_vm, fpst); | |
5426 | } | |
5427 | break; | |
5428 | case MO_16: | |
5429 | if (signal_all_nans) { | |
5430 | gen_helper_vfp_cmpeh_a64(tcg_flags, tcg_vn, tcg_vm, fpst); | |
5431 | } else { | |
5432 | gen_helper_vfp_cmph_a64(tcg_flags, tcg_vn, tcg_vm, fpst); | |
5433 | } | |
5434 | break; | |
5435 | default: | |
5436 | g_assert_not_reached(); | |
da7dafe7 | 5437 | } |
7a192925 | 5438 | |
da7dafe7 CF |
5439 | tcg_temp_free_i32(tcg_vn); |
5440 | tcg_temp_free_i32(tcg_vm); | |
5441 | } | |
5442 | ||
5443 | tcg_temp_free_ptr(fpst); | |
5444 | ||
5445 | gen_set_nzcv(tcg_flags); | |
5446 | ||
5447 | tcg_temp_free_i64(tcg_flags); | |
5448 | } | |
5449 | ||
4ce31af4 | 5450 | /* Floating point compare |
faa0ba46 PM |
5451 | * 31 30 29 28 24 23 22 21 20 16 15 14 13 10 9 5 4 0 |
5452 | * +---+---+---+-----------+------+---+------+-----+---------+------+-------+ | |
5453 | * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | op | 1 0 0 0 | Rn | op2 | | |
5454 | * +---+---+---+-----------+------+---+------+-----+---------+------+-------+ | |
5455 | */ | |
5456 | static void disas_fp_compare(DisasContext *s, uint32_t insn) | |
5457 | { | |
da7dafe7 | 5458 | unsigned int mos, type, rm, op, rn, opc, op2r; |
7a192925 | 5459 | int size; |
da7dafe7 CF |
5460 | |
5461 | mos = extract32(insn, 29, 3); | |
7a192925 | 5462 | type = extract32(insn, 22, 2); |
da7dafe7 CF |
5463 | rm = extract32(insn, 16, 5); |
5464 | op = extract32(insn, 14, 2); | |
5465 | rn = extract32(insn, 5, 5); | |
5466 | opc = extract32(insn, 3, 2); | |
5467 | op2r = extract32(insn, 0, 3); | |
5468 | ||
7a192925 AB |
5469 | if (mos || op || op2r) { |
5470 | unallocated_encoding(s); | |
5471 | return; | |
5472 | } | |
5473 | ||
5474 | switch (type) { | |
5475 | case 0: | |
5476 | size = MO_32; | |
5477 | break; | |
5478 | case 1: | |
5479 | size = MO_64; | |
5480 | break; | |
5481 | case 3: | |
5482 | size = MO_16; | |
5763190f | 5483 | if (dc_isar_feature(aa64_fp16, s)) { |
7a192925 AB |
5484 | break; |
5485 | } | |
5486 | /* fallthru */ | |
5487 | default: | |
da7dafe7 CF |
5488 | unallocated_encoding(s); |
5489 | return; | |
5490 | } | |
5491 | ||
8c6afa6a PM |
5492 | if (!fp_access_check(s)) { |
5493 | return; | |
5494 | } | |
5495 | ||
7a192925 | 5496 | handle_fp_compare(s, size, rn, rm, opc & 1, opc & 2); |
faa0ba46 PM |
5497 | } |
5498 | ||
4ce31af4 | 5499 | /* Floating point conditional compare |
faa0ba46 PM |
5500 | * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0 |
5501 | * +---+---+---+-----------+------+---+------+------+-----+------+----+------+ | |
5502 | * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 0 1 | Rn | op | nzcv | | |
5503 | * +---+---+---+-----------+------+---+------+------+-----+------+----+------+ | |
5504 | */ | |
5505 | static void disas_fp_ccomp(DisasContext *s, uint32_t insn) | |
5506 | { | |
513f1d76 CF |
5507 | unsigned int mos, type, rm, cond, rn, op, nzcv; |
5508 | TCGv_i64 tcg_flags; | |
42a268c2 | 5509 | TCGLabel *label_continue = NULL; |
7a192925 | 5510 | int size; |
513f1d76 CF |
5511 | |
5512 | mos = extract32(insn, 29, 3); | |
7a192925 | 5513 | type = extract32(insn, 22, 2); |
513f1d76 CF |
5514 | rm = extract32(insn, 16, 5); |
5515 | cond = extract32(insn, 12, 4); | |
5516 | rn = extract32(insn, 5, 5); | |
5517 | op = extract32(insn, 4, 1); | |
5518 | nzcv = extract32(insn, 0, 4); | |
5519 | ||
7a192925 AB |
5520 | if (mos) { |
5521 | unallocated_encoding(s); | |
5522 | return; | |
5523 | } | |
5524 | ||
5525 | switch (type) { | |
5526 | case 0: | |
5527 | size = MO_32; | |
5528 | break; | |
5529 | case 1: | |
5530 | size = MO_64; | |
5531 | break; | |
5532 | case 3: | |
5533 | size = MO_16; | |
5763190f | 5534 | if (dc_isar_feature(aa64_fp16, s)) { |
7a192925 AB |
5535 | break; |
5536 | } | |
5537 | /* fallthru */ | |
5538 | default: | |
513f1d76 CF |
5539 | unallocated_encoding(s); |
5540 | return; | |
5541 | } | |
5542 | ||
8c6afa6a PM |
5543 | if (!fp_access_check(s)) { |
5544 | return; | |
5545 | } | |
5546 | ||
513f1d76 | 5547 | if (cond < 0x0e) { /* not always */ |
42a268c2 | 5548 | TCGLabel *label_match = gen_new_label(); |
513f1d76 CF |
5549 | label_continue = gen_new_label(); |
5550 | arm_gen_test_cc(cond, label_match); | |
5551 | /* nomatch: */ | |
5552 | tcg_flags = tcg_const_i64(nzcv << 28); | |
5553 | gen_set_nzcv(tcg_flags); | |
5554 | tcg_temp_free_i64(tcg_flags); | |
5555 | tcg_gen_br(label_continue); | |
5556 | gen_set_label(label_match); | |
5557 | } | |
5558 | ||
7a192925 | 5559 | handle_fp_compare(s, size, rn, rm, false, op); |
513f1d76 CF |
5560 | |
5561 | if (cond < 0x0e) { | |
5562 | gen_set_label(label_continue); | |
5563 | } | |
faa0ba46 PM |
5564 | } |
5565 | ||
4ce31af4 | 5566 | /* Floating point conditional select |
faa0ba46 PM |
5567 | * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0 |
5568 | * +---+---+---+-----------+------+---+------+------+-----+------+------+ | |
5569 | * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 1 1 | Rn | Rd | | |
5570 | * +---+---+---+-----------+------+---+------+------+-----+------+------+ | |
5571 | */ | |
5572 | static void disas_fp_csel(DisasContext *s, uint32_t insn) | |
5573 | { | |
5640ff62 | 5574 | unsigned int mos, type, rm, cond, rn, rd; |
6e061029 RH |
5575 | TCGv_i64 t_true, t_false, t_zero; |
5576 | DisasCompare64 c; | |
14776ab5 | 5577 | MemOp sz; |
5640ff62 CF |
5578 | |
5579 | mos = extract32(insn, 29, 3); | |
ace97fee | 5580 | type = extract32(insn, 22, 2); |
5640ff62 CF |
5581 | rm = extract32(insn, 16, 5); |
5582 | cond = extract32(insn, 12, 4); | |
5583 | rn = extract32(insn, 5, 5); | |
5584 | rd = extract32(insn, 0, 5); | |
5585 | ||
ace97fee AB |
5586 | if (mos) { |
5587 | unallocated_encoding(s); | |
5588 | return; | |
5589 | } | |
5590 | ||
5591 | switch (type) { | |
5592 | case 0: | |
5593 | sz = MO_32; | |
5594 | break; | |
5595 | case 1: | |
5596 | sz = MO_64; | |
5597 | break; | |
5598 | case 3: | |
5599 | sz = MO_16; | |
5763190f | 5600 | if (dc_isar_feature(aa64_fp16, s)) { |
ace97fee AB |
5601 | break; |
5602 | } | |
5603 | /* fallthru */ | |
5604 | default: | |
5640ff62 CF |
5605 | unallocated_encoding(s); |
5606 | return; | |
5607 | } | |
5608 | ||
8c6afa6a PM |
5609 | if (!fp_access_check(s)) { |
5610 | return; | |
5611 | } | |
5612 | ||
ace97fee | 5613 | /* Zero extend sreg & hreg inputs to 64 bits now. */ |
6e061029 RH |
5614 | t_true = tcg_temp_new_i64(); |
5615 | t_false = tcg_temp_new_i64(); | |
ace97fee AB |
5616 | read_vec_element(s, t_true, rn, 0, sz); |
5617 | read_vec_element(s, t_false, rm, 0, sz); | |
5640ff62 | 5618 | |
6e061029 RH |
5619 | a64_test_cc(&c, cond); |
5620 | t_zero = tcg_const_i64(0); | |
5621 | tcg_gen_movcond_i64(c.cond, t_true, c.value, t_zero, t_true, t_false); | |
5622 | tcg_temp_free_i64(t_zero); | |
5623 | tcg_temp_free_i64(t_false); | |
5624 | a64_free_cc(&c); | |
5640ff62 | 5625 | |
ace97fee | 5626 | /* Note that sregs & hregs write back zeros to the high bits, |
6e061029 RH |
5627 | and we've already done the zero-extension. */ |
5628 | write_fp_dreg(s, rd, t_true); | |
5629 | tcg_temp_free_i64(t_true); | |
faa0ba46 PM |
5630 | } |
5631 | ||
c2c08713 AB |
5632 | /* Floating-point data-processing (1 source) - half precision */ |
5633 | static void handle_fp_1src_half(DisasContext *s, int opcode, int rd, int rn) | |
5634 | { | |
5635 | TCGv_ptr fpst = NULL; | |
3d99d931 | 5636 | TCGv_i32 tcg_op = read_fp_hreg(s, rn); |
c2c08713 AB |
5637 | TCGv_i32 tcg_res = tcg_temp_new_i32(); |
5638 | ||
c2c08713 AB |
5639 | switch (opcode) { |
5640 | case 0x0: /* FMOV */ | |
5641 | tcg_gen_mov_i32(tcg_res, tcg_op); | |
5642 | break; | |
5643 | case 0x1: /* FABS */ | |
5644 | tcg_gen_andi_i32(tcg_res, tcg_op, 0x7fff); | |
5645 | break; | |
5646 | case 0x2: /* FNEG */ | |
5647 | tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000); | |
5648 | break; | |
5649 | case 0x3: /* FSQRT */ | |
905edee9 AB |
5650 | fpst = get_fpstatus_ptr(true); |
5651 | gen_helper_sqrt_f16(tcg_res, tcg_op, fpst); | |
c2c08713 AB |
5652 | break; |
5653 | case 0x8: /* FRINTN */ | |
5654 | case 0x9: /* FRINTP */ | |
5655 | case 0xa: /* FRINTM */ | |
5656 | case 0xb: /* FRINTZ */ | |
5657 | case 0xc: /* FRINTA */ | |
5658 | { | |
5659 | TCGv_i32 tcg_rmode = tcg_const_i32(arm_rmode_to_sf(opcode & 7)); | |
5660 | fpst = get_fpstatus_ptr(true); | |
5661 | ||
5662 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); | |
5663 | gen_helper_advsimd_rinth(tcg_res, tcg_op, fpst); | |
5664 | ||
5665 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); | |
5666 | tcg_temp_free_i32(tcg_rmode); | |
5667 | break; | |
5668 | } | |
5669 | case 0xe: /* FRINTX */ | |
5670 | fpst = get_fpstatus_ptr(true); | |
5671 | gen_helper_advsimd_rinth_exact(tcg_res, tcg_op, fpst); | |
5672 | break; | |
5673 | case 0xf: /* FRINTI */ | |
5674 | fpst = get_fpstatus_ptr(true); | |
5675 | gen_helper_advsimd_rinth(tcg_res, tcg_op, fpst); | |
5676 | break; | |
5677 | default: | |
5678 | abort(); | |
5679 | } | |
5680 | ||
5681 | write_fp_sreg(s, rd, tcg_res); | |
5682 | ||
5683 | if (fpst) { | |
5684 | tcg_temp_free_ptr(fpst); | |
5685 | } | |
5686 | tcg_temp_free_i32(tcg_op); | |
5687 | tcg_temp_free_i32(tcg_res); | |
5688 | } | |
5689 | ||
4ce31af4 | 5690 | /* Floating-point data-processing (1 source) - single precision */ |
d9b0848d PM |
5691 | static void handle_fp_1src_single(DisasContext *s, int opcode, int rd, int rn) |
5692 | { | |
0e4db23d RH |
5693 | void (*gen_fpst)(TCGv_i32, TCGv_i32, TCGv_ptr); |
5694 | TCGv_i32 tcg_op, tcg_res; | |
d9b0848d | 5695 | TCGv_ptr fpst; |
0e4db23d | 5696 | int rmode = -1; |
d9b0848d | 5697 | |
d9b0848d PM |
5698 | tcg_op = read_fp_sreg(s, rn); |
5699 | tcg_res = tcg_temp_new_i32(); | |
5700 | ||
5701 | switch (opcode) { | |
5702 | case 0x0: /* FMOV */ | |
5703 | tcg_gen_mov_i32(tcg_res, tcg_op); | |
0e4db23d | 5704 | goto done; |
d9b0848d PM |
5705 | case 0x1: /* FABS */ |
5706 | gen_helper_vfp_abss(tcg_res, tcg_op); | |
0e4db23d | 5707 | goto done; |
d9b0848d PM |
5708 | case 0x2: /* FNEG */ |
5709 | gen_helper_vfp_negs(tcg_res, tcg_op); | |
0e4db23d | 5710 | goto done; |
d9b0848d PM |
5711 | case 0x3: /* FSQRT */ |
5712 | gen_helper_vfp_sqrts(tcg_res, tcg_op, cpu_env); | |
0e4db23d | 5713 | goto done; |
d9b0848d PM |
5714 | case 0x8: /* FRINTN */ |
5715 | case 0x9: /* FRINTP */ | |
5716 | case 0xa: /* FRINTM */ | |
5717 | case 0xb: /* FRINTZ */ | |
5718 | case 0xc: /* FRINTA */ | |
0e4db23d RH |
5719 | rmode = arm_rmode_to_sf(opcode & 7); |
5720 | gen_fpst = gen_helper_rints; | |
d9b0848d | 5721 | break; |
d9b0848d | 5722 | case 0xe: /* FRINTX */ |
0e4db23d | 5723 | gen_fpst = gen_helper_rints_exact; |
d9b0848d PM |
5724 | break; |
5725 | case 0xf: /* FRINTI */ | |
0e4db23d | 5726 | gen_fpst = gen_helper_rints; |
d9b0848d | 5727 | break; |
6bea2563 RH |
5728 | case 0x10: /* FRINT32Z */ |
5729 | rmode = float_round_to_zero; | |
5730 | gen_fpst = gen_helper_frint32_s; | |
5731 | break; | |
5732 | case 0x11: /* FRINT32X */ | |
5733 | gen_fpst = gen_helper_frint32_s; | |
5734 | break; | |
5735 | case 0x12: /* FRINT64Z */ | |
5736 | rmode = float_round_to_zero; | |
5737 | gen_fpst = gen_helper_frint64_s; | |
5738 | break; | |
5739 | case 0x13: /* FRINT64X */ | |
5740 | gen_fpst = gen_helper_frint64_s; | |
5741 | break; | |
d9b0848d | 5742 | default: |
0e4db23d | 5743 | g_assert_not_reached(); |
d9b0848d PM |
5744 | } |
5745 | ||
0e4db23d RH |
5746 | fpst = get_fpstatus_ptr(false); |
5747 | if (rmode >= 0) { | |
5748 | TCGv_i32 tcg_rmode = tcg_const_i32(rmode); | |
5749 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); | |
5750 | gen_fpst(tcg_res, tcg_op, fpst); | |
5751 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); | |
5752 | tcg_temp_free_i32(tcg_rmode); | |
5753 | } else { | |
5754 | gen_fpst(tcg_res, tcg_op, fpst); | |
5755 | } | |
d9b0848d | 5756 | tcg_temp_free_ptr(fpst); |
0e4db23d RH |
5757 | |
5758 | done: | |
5759 | write_fp_sreg(s, rd, tcg_res); | |
d9b0848d PM |
5760 | tcg_temp_free_i32(tcg_op); |
5761 | tcg_temp_free_i32(tcg_res); | |
5762 | } | |
5763 | ||
4ce31af4 | 5764 | /* Floating-point data-processing (1 source) - double precision */ |
d9b0848d PM |
5765 | static void handle_fp_1src_double(DisasContext *s, int opcode, int rd, int rn) |
5766 | { | |
0e4db23d RH |
5767 | void (*gen_fpst)(TCGv_i64, TCGv_i64, TCGv_ptr); |
5768 | TCGv_i64 tcg_op, tcg_res; | |
d9b0848d | 5769 | TCGv_ptr fpst; |
0e4db23d | 5770 | int rmode = -1; |
d9b0848d | 5771 | |
377ef731 RH |
5772 | switch (opcode) { |
5773 | case 0x0: /* FMOV */ | |
5774 | gen_gvec_fn2(s, false, rd, rn, tcg_gen_gvec_mov, 0); | |
5775 | return; | |
5776 | } | |
5777 | ||
d9b0848d PM |
5778 | tcg_op = read_fp_dreg(s, rn); |
5779 | tcg_res = tcg_temp_new_i64(); | |
5780 | ||
5781 | switch (opcode) { | |
d9b0848d PM |
5782 | case 0x1: /* FABS */ |
5783 | gen_helper_vfp_absd(tcg_res, tcg_op); | |
0e4db23d | 5784 | goto done; |
d9b0848d PM |
5785 | case 0x2: /* FNEG */ |
5786 | gen_helper_vfp_negd(tcg_res, tcg_op); | |
0e4db23d | 5787 | goto done; |
d9b0848d PM |
5788 | case 0x3: /* FSQRT */ |
5789 | gen_helper_vfp_sqrtd(tcg_res, tcg_op, cpu_env); | |
0e4db23d | 5790 | goto done; |
d9b0848d PM |
5791 | case 0x8: /* FRINTN */ |
5792 | case 0x9: /* FRINTP */ | |
5793 | case 0xa: /* FRINTM */ | |
5794 | case 0xb: /* FRINTZ */ | |
5795 | case 0xc: /* FRINTA */ | |
0e4db23d RH |
5796 | rmode = arm_rmode_to_sf(opcode & 7); |
5797 | gen_fpst = gen_helper_rintd; | |
d9b0848d | 5798 | break; |
d9b0848d | 5799 | case 0xe: /* FRINTX */ |
0e4db23d | 5800 | gen_fpst = gen_helper_rintd_exact; |
d9b0848d PM |
5801 | break; |
5802 | case 0xf: /* FRINTI */ | |
0e4db23d | 5803 | gen_fpst = gen_helper_rintd; |
d9b0848d | 5804 | break; |
6bea2563 RH |
5805 | case 0x10: /* FRINT32Z */ |
5806 | rmode = float_round_to_zero; | |
5807 | gen_fpst = gen_helper_frint32_d; | |
5808 | break; | |
5809 | case 0x11: /* FRINT32X */ | |
5810 | gen_fpst = gen_helper_frint32_d; | |
5811 | break; | |
5812 | case 0x12: /* FRINT64Z */ | |
5813 | rmode = float_round_to_zero; | |
5814 | gen_fpst = gen_helper_frint64_d; | |
5815 | break; | |
5816 | case 0x13: /* FRINT64X */ | |
5817 | gen_fpst = gen_helper_frint64_d; | |
5818 | break; | |
d9b0848d | 5819 | default: |
0e4db23d | 5820 | g_assert_not_reached(); |
d9b0848d PM |
5821 | } |
5822 | ||
0e4db23d RH |
5823 | fpst = get_fpstatus_ptr(false); |
5824 | if (rmode >= 0) { | |
5825 | TCGv_i32 tcg_rmode = tcg_const_i32(rmode); | |
5826 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); | |
5827 | gen_fpst(tcg_res, tcg_op, fpst); | |
5828 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); | |
5829 | tcg_temp_free_i32(tcg_rmode); | |
5830 | } else { | |
5831 | gen_fpst(tcg_res, tcg_op, fpst); | |
5832 | } | |
d9b0848d | 5833 | tcg_temp_free_ptr(fpst); |
0e4db23d RH |
5834 | |
5835 | done: | |
5836 | write_fp_dreg(s, rd, tcg_res); | |
d9b0848d PM |
5837 | tcg_temp_free_i64(tcg_op); |
5838 | tcg_temp_free_i64(tcg_res); | |
5839 | } | |
5840 | ||
8900aad2 PM |
5841 | static void handle_fp_fcvt(DisasContext *s, int opcode, |
5842 | int rd, int rn, int dtype, int ntype) | |
5843 | { | |
5844 | switch (ntype) { | |
5845 | case 0x0: | |
5846 | { | |
5847 | TCGv_i32 tcg_rn = read_fp_sreg(s, rn); | |
5848 | if (dtype == 1) { | |
5849 | /* Single to double */ | |
5850 | TCGv_i64 tcg_rd = tcg_temp_new_i64(); | |
5851 | gen_helper_vfp_fcvtds(tcg_rd, tcg_rn, cpu_env); | |
5852 | write_fp_dreg(s, rd, tcg_rd); | |
5853 | tcg_temp_free_i64(tcg_rd); | |
5854 | } else { | |
5855 | /* Single to half */ | |
5856 | TCGv_i32 tcg_rd = tcg_temp_new_i32(); | |
486624fc AB |
5857 | TCGv_i32 ahp = get_ahp_flag(); |
5858 | TCGv_ptr fpst = get_fpstatus_ptr(false); | |
5859 | ||
5860 | gen_helper_vfp_fcvt_f32_to_f16(tcg_rd, tcg_rn, fpst, ahp); | |
8900aad2 PM |
5861 | /* write_fp_sreg is OK here because top half of tcg_rd is zero */ |
5862 | write_fp_sreg(s, rd, tcg_rd); | |
5863 | tcg_temp_free_i32(tcg_rd); | |
486624fc AB |
5864 | tcg_temp_free_i32(ahp); |
5865 | tcg_temp_free_ptr(fpst); | |
8900aad2 PM |
5866 | } |
5867 | tcg_temp_free_i32(tcg_rn); | |
5868 | break; | |
5869 | } | |
5870 | case 0x1: | |
5871 | { | |
5872 | TCGv_i64 tcg_rn = read_fp_dreg(s, rn); | |
5873 | TCGv_i32 tcg_rd = tcg_temp_new_i32(); | |
5874 | if (dtype == 0) { | |
5875 | /* Double to single */ | |
5876 | gen_helper_vfp_fcvtsd(tcg_rd, tcg_rn, cpu_env); | |
5877 | } else { | |
486624fc AB |
5878 | TCGv_ptr fpst = get_fpstatus_ptr(false); |
5879 | TCGv_i32 ahp = get_ahp_flag(); | |
8900aad2 | 5880 | /* Double to half */ |
486624fc | 5881 | gen_helper_vfp_fcvt_f64_to_f16(tcg_rd, tcg_rn, fpst, ahp); |
8900aad2 | 5882 | /* write_fp_sreg is OK here because top half of tcg_rd is zero */ |
486624fc AB |
5883 | tcg_temp_free_ptr(fpst); |
5884 | tcg_temp_free_i32(ahp); | |
8900aad2 PM |
5885 | } |
5886 | write_fp_sreg(s, rd, tcg_rd); | |
5887 | tcg_temp_free_i32(tcg_rd); | |
5888 | tcg_temp_free_i64(tcg_rn); | |
5889 | break; | |
5890 | } | |
5891 | case 0x3: | |
5892 | { | |
5893 | TCGv_i32 tcg_rn = read_fp_sreg(s, rn); | |
486624fc AB |
5894 | TCGv_ptr tcg_fpst = get_fpstatus_ptr(false); |
5895 | TCGv_i32 tcg_ahp = get_ahp_flag(); | |
8900aad2 PM |
5896 | tcg_gen_ext16u_i32(tcg_rn, tcg_rn); |
5897 | if (dtype == 0) { | |
5898 | /* Half to single */ | |
5899 | TCGv_i32 tcg_rd = tcg_temp_new_i32(); | |
486624fc | 5900 | gen_helper_vfp_fcvt_f16_to_f32(tcg_rd, tcg_rn, tcg_fpst, tcg_ahp); |
8900aad2 PM |
5901 | write_fp_sreg(s, rd, tcg_rd); |
5902 | tcg_temp_free_i32(tcg_rd); | |
5903 | } else { | |
5904 | /* Half to double */ | |
5905 | TCGv_i64 tcg_rd = tcg_temp_new_i64(); | |
486624fc | 5906 | gen_helper_vfp_fcvt_f16_to_f64(tcg_rd, tcg_rn, tcg_fpst, tcg_ahp); |
8900aad2 PM |
5907 | write_fp_dreg(s, rd, tcg_rd); |
5908 | tcg_temp_free_i64(tcg_rd); | |
5909 | } | |
5910 | tcg_temp_free_i32(tcg_rn); | |
aeab8e5e AB |
5911 | tcg_temp_free_ptr(tcg_fpst); |
5912 | tcg_temp_free_i32(tcg_ahp); | |
8900aad2 PM |
5913 | break; |
5914 | } | |
5915 | default: | |
5916 | abort(); | |
5917 | } | |
5918 | } | |
5919 | ||
4ce31af4 | 5920 | /* Floating point data-processing (1 source) |
faa0ba46 PM |
5921 | * 31 30 29 28 24 23 22 21 20 15 14 10 9 5 4 0 |
5922 | * +---+---+---+-----------+------+---+--------+-----------+------+------+ | |
5923 | * | M | 0 | S | 1 1 1 1 0 | type | 1 | opcode | 1 0 0 0 0 | Rn | Rd | | |
5924 | * +---+---+---+-----------+------+---+--------+-----------+------+------+ | |
5925 | */ | |
5926 | static void disas_fp_1src(DisasContext *s, uint32_t insn) | |
5927 | { | |
c1e20801 | 5928 | int mos = extract32(insn, 29, 3); |
d9b0848d PM |
5929 | int type = extract32(insn, 22, 2); |
5930 | int opcode = extract32(insn, 15, 6); | |
5931 | int rn = extract32(insn, 5, 5); | |
5932 | int rd = extract32(insn, 0, 5); | |
5933 | ||
c1e20801 PM |
5934 | if (mos) { |
5935 | unallocated_encoding(s); | |
5936 | return; | |
5937 | } | |
5938 | ||
d9b0848d PM |
5939 | switch (opcode) { |
5940 | case 0x4: case 0x5: case 0x7: | |
8900aad2 | 5941 | { |
d9b0848d | 5942 | /* FCVT between half, single and double precision */ |
8900aad2 PM |
5943 | int dtype = extract32(opcode, 0, 2); |
5944 | if (type == 2 || dtype == type) { | |
5945 | unallocated_encoding(s); | |
5946 | return; | |
5947 | } | |
8c6afa6a PM |
5948 | if (!fp_access_check(s)) { |
5949 | return; | |
5950 | } | |
5951 | ||
8900aad2 | 5952 | handle_fp_fcvt(s, opcode, rd, rn, dtype, type); |
d9b0848d | 5953 | break; |
8900aad2 | 5954 | } |
6bea2563 RH |
5955 | |
5956 | case 0x10 ... 0x13: /* FRINT{32,64}{X,Z} */ | |
5957 | if (type > 1 || !dc_isar_feature(aa64_frint, s)) { | |
5958 | unallocated_encoding(s); | |
5959 | return; | |
5960 | } | |
5961 | /* fall through */ | |
d9b0848d PM |
5962 | case 0x0 ... 0x3: |
5963 | case 0x8 ... 0xc: | |
5964 | case 0xe ... 0xf: | |
5965 | /* 32-to-32 and 64-to-64 ops */ | |
5966 | switch (type) { | |
5967 | case 0: | |
8c6afa6a PM |
5968 | if (!fp_access_check(s)) { |
5969 | return; | |
5970 | } | |
d9b0848d PM |
5971 | handle_fp_1src_single(s, opcode, rd, rn); |
5972 | break; | |
5973 | case 1: | |
8c6afa6a PM |
5974 | if (!fp_access_check(s)) { |
5975 | return; | |
5976 | } | |
d9b0848d PM |
5977 | handle_fp_1src_double(s, opcode, rd, rn); |
5978 | break; | |
c2c08713 | 5979 | case 3: |
5763190f | 5980 | if (!dc_isar_feature(aa64_fp16, s)) { |
c2c08713 AB |
5981 | unallocated_encoding(s); |
5982 | return; | |
5983 | } | |
5984 | ||
5985 | if (!fp_access_check(s)) { | |
5986 | return; | |
5987 | } | |
c2c08713 AB |
5988 | handle_fp_1src_half(s, opcode, rd, rn); |
5989 | break; | |
d9b0848d PM |
5990 | default: |
5991 | unallocated_encoding(s); | |
5992 | } | |
5993 | break; | |
6bea2563 | 5994 | |
d9b0848d PM |
5995 | default: |
5996 | unallocated_encoding(s); | |
5997 | break; | |
5998 | } | |
faa0ba46 PM |
5999 | } |
6000 | ||
4ce31af4 | 6001 | /* Floating-point data-processing (2 source) - single precision */ |
ec73d2e0 AG |
6002 | static void handle_fp_2src_single(DisasContext *s, int opcode, |
6003 | int rd, int rn, int rm) | |
6004 | { | |
6005 | TCGv_i32 tcg_op1; | |
6006 | TCGv_i32 tcg_op2; | |
6007 | TCGv_i32 tcg_res; | |
6008 | TCGv_ptr fpst; | |
6009 | ||
6010 | tcg_res = tcg_temp_new_i32(); | |
d81ce0ef | 6011 | fpst = get_fpstatus_ptr(false); |
ec73d2e0 AG |
6012 | tcg_op1 = read_fp_sreg(s, rn); |
6013 | tcg_op2 = read_fp_sreg(s, rm); | |
6014 | ||
6015 | switch (opcode) { | |
6016 | case 0x0: /* FMUL */ | |
6017 | gen_helper_vfp_muls(tcg_res, tcg_op1, tcg_op2, fpst); | |
6018 | break; | |
6019 | case 0x1: /* FDIV */ | |
6020 | gen_helper_vfp_divs(tcg_res, tcg_op1, tcg_op2, fpst); | |
6021 | break; | |
6022 | case 0x2: /* FADD */ | |
6023 | gen_helper_vfp_adds(tcg_res, tcg_op1, tcg_op2, fpst); | |
6024 | break; | |
6025 | case 0x3: /* FSUB */ | |
6026 | gen_helper_vfp_subs(tcg_res, tcg_op1, tcg_op2, fpst); | |
6027 | break; | |
6028 | case 0x4: /* FMAX */ | |
6029 | gen_helper_vfp_maxs(tcg_res, tcg_op1, tcg_op2, fpst); | |
6030 | break; | |
6031 | case 0x5: /* FMIN */ | |
6032 | gen_helper_vfp_mins(tcg_res, tcg_op1, tcg_op2, fpst); | |
6033 | break; | |
6034 | case 0x6: /* FMAXNM */ | |
6035 | gen_helper_vfp_maxnums(tcg_res, tcg_op1, tcg_op2, fpst); | |
6036 | break; | |
6037 | case 0x7: /* FMINNM */ | |
6038 | gen_helper_vfp_minnums(tcg_res, tcg_op1, tcg_op2, fpst); | |
6039 | break; | |
6040 | case 0x8: /* FNMUL */ | |
6041 | gen_helper_vfp_muls(tcg_res, tcg_op1, tcg_op2, fpst); | |
6042 | gen_helper_vfp_negs(tcg_res, tcg_res); | |
6043 | break; | |
6044 | } | |
6045 | ||
6046 | write_fp_sreg(s, rd, tcg_res); | |
6047 | ||
6048 | tcg_temp_free_ptr(fpst); | |
6049 | tcg_temp_free_i32(tcg_op1); | |
6050 | tcg_temp_free_i32(tcg_op2); | |
6051 | tcg_temp_free_i32(tcg_res); | |
6052 | } | |
6053 | ||
4ce31af4 | 6054 | /* Floating-point data-processing (2 source) - double precision */ |
ec73d2e0 AG |
6055 | static void handle_fp_2src_double(DisasContext *s, int opcode, |
6056 | int rd, int rn, int rm) | |
6057 | { | |
6058 | TCGv_i64 tcg_op1; | |
6059 | TCGv_i64 tcg_op2; | |
6060 | TCGv_i64 tcg_res; | |
6061 | TCGv_ptr fpst; | |
6062 | ||
6063 | tcg_res = tcg_temp_new_i64(); | |
d81ce0ef | 6064 | fpst = get_fpstatus_ptr(false); |
ec73d2e0 AG |
6065 | tcg_op1 = read_fp_dreg(s, rn); |
6066 | tcg_op2 = read_fp_dreg(s, rm); | |
6067 | ||
6068 | switch (opcode) { | |
6069 | case 0x0: /* FMUL */ | |
6070 | gen_helper_vfp_muld(tcg_res, tcg_op1, tcg_op2, fpst); | |
6071 | break; | |
6072 | case 0x1: /* FDIV */ | |
6073 | gen_helper_vfp_divd(tcg_res, tcg_op1, tcg_op2, fpst); | |
6074 | break; | |
6075 | case 0x2: /* FADD */ | |
6076 | gen_helper_vfp_addd(tcg_res, tcg_op1, tcg_op2, fpst); | |
6077 | break; | |
6078 | case 0x3: /* FSUB */ | |
6079 | gen_helper_vfp_subd(tcg_res, tcg_op1, tcg_op2, fpst); | |
6080 | break; | |
6081 | case 0x4: /* FMAX */ | |
6082 | gen_helper_vfp_maxd(tcg_res, tcg_op1, tcg_op2, fpst); | |
6083 | break; | |
6084 | case 0x5: /* FMIN */ | |
6085 | gen_helper_vfp_mind(tcg_res, tcg_op1, tcg_op2, fpst); | |
6086 | break; | |
6087 | case 0x6: /* FMAXNM */ | |
6088 | gen_helper_vfp_maxnumd(tcg_res, tcg_op1, tcg_op2, fpst); | |
6089 | break; | |
6090 | case 0x7: /* FMINNM */ | |
6091 | gen_helper_vfp_minnumd(tcg_res, tcg_op1, tcg_op2, fpst); | |
6092 | break; | |
6093 | case 0x8: /* FNMUL */ | |
6094 | gen_helper_vfp_muld(tcg_res, tcg_op1, tcg_op2, fpst); | |
6095 | gen_helper_vfp_negd(tcg_res, tcg_res); | |
6096 | break; | |
6097 | } | |
6098 | ||
6099 | write_fp_dreg(s, rd, tcg_res); | |
6100 | ||
6101 | tcg_temp_free_ptr(fpst); | |
6102 | tcg_temp_free_i64(tcg_op1); | |
6103 | tcg_temp_free_i64(tcg_op2); | |
6104 | tcg_temp_free_i64(tcg_res); | |
6105 | } | |
6106 | ||
b8f5171c RH |
6107 | /* Floating-point data-processing (2 source) - half precision */ |
6108 | static void handle_fp_2src_half(DisasContext *s, int opcode, | |
6109 | int rd, int rn, int rm) | |
6110 | { | |
6111 | TCGv_i32 tcg_op1; | |
6112 | TCGv_i32 tcg_op2; | |
6113 | TCGv_i32 tcg_res; | |
6114 | TCGv_ptr fpst; | |
6115 | ||
6116 | tcg_res = tcg_temp_new_i32(); | |
6117 | fpst = get_fpstatus_ptr(true); | |
6118 | tcg_op1 = read_fp_hreg(s, rn); | |
6119 | tcg_op2 = read_fp_hreg(s, rm); | |
6120 | ||
6121 | switch (opcode) { | |
6122 | case 0x0: /* FMUL */ | |
6123 | gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst); | |
6124 | break; | |
6125 | case 0x1: /* FDIV */ | |
6126 | gen_helper_advsimd_divh(tcg_res, tcg_op1, tcg_op2, fpst); | |
6127 | break; | |
6128 | case 0x2: /* FADD */ | |
6129 | gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst); | |
6130 | break; | |
6131 | case 0x3: /* FSUB */ | |
6132 | gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst); | |
6133 | break; | |
6134 | case 0x4: /* FMAX */ | |
6135 | gen_helper_advsimd_maxh(tcg_res, tcg_op1, tcg_op2, fpst); | |
6136 | break; | |
6137 | case 0x5: /* FMIN */ | |
6138 | gen_helper_advsimd_minh(tcg_res, tcg_op1, tcg_op2, fpst); | |
6139 | break; | |
6140 | case 0x6: /* FMAXNM */ | |
6141 | gen_helper_advsimd_maxnumh(tcg_res, tcg_op1, tcg_op2, fpst); | |
6142 | break; | |
6143 | case 0x7: /* FMINNM */ | |
6144 | gen_helper_advsimd_minnumh(tcg_res, tcg_op1, tcg_op2, fpst); | |
6145 | break; | |
6146 | case 0x8: /* FNMUL */ | |
6147 | gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst); | |
6148 | tcg_gen_xori_i32(tcg_res, tcg_res, 0x8000); | |
6149 | break; | |
6150 | default: | |
6151 | g_assert_not_reached(); | |
6152 | } | |
6153 | ||
6154 | write_fp_sreg(s, rd, tcg_res); | |
6155 | ||
6156 | tcg_temp_free_ptr(fpst); | |
6157 | tcg_temp_free_i32(tcg_op1); | |
6158 | tcg_temp_free_i32(tcg_op2); | |
6159 | tcg_temp_free_i32(tcg_res); | |
6160 | } | |
6161 | ||
4ce31af4 | 6162 | /* Floating point data-processing (2 source) |
faa0ba46 PM |
6163 | * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0 |
6164 | * +---+---+---+-----------+------+---+------+--------+-----+------+------+ | |
6165 | * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | opcode | 1 0 | Rn | Rd | | |
6166 | * +---+---+---+-----------+------+---+------+--------+-----+------+------+ | |
6167 | */ | |
6168 | static void disas_fp_2src(DisasContext *s, uint32_t insn) | |
6169 | { | |
c1e20801 | 6170 | int mos = extract32(insn, 29, 3); |
ec73d2e0 AG |
6171 | int type = extract32(insn, 22, 2); |
6172 | int rd = extract32(insn, 0, 5); | |
6173 | int rn = extract32(insn, 5, 5); | |
6174 | int rm = extract32(insn, 16, 5); | |
6175 | int opcode = extract32(insn, 12, 4); | |
6176 | ||
c1e20801 | 6177 | if (opcode > 8 || mos) { |
ec73d2e0 AG |
6178 | unallocated_encoding(s); |
6179 | return; | |
6180 | } | |
6181 | ||
6182 | switch (type) { | |
6183 | case 0: | |
8c6afa6a PM |
6184 | if (!fp_access_check(s)) { |
6185 | return; | |
6186 | } | |
ec73d2e0 AG |
6187 | handle_fp_2src_single(s, opcode, rd, rn, rm); |
6188 | break; | |
6189 | case 1: | |
8c6afa6a PM |
6190 | if (!fp_access_check(s)) { |
6191 | return; | |
6192 | } | |
ec73d2e0 AG |
6193 | handle_fp_2src_double(s, opcode, rd, rn, rm); |
6194 | break; | |
b8f5171c | 6195 | case 3: |
5763190f | 6196 | if (!dc_isar_feature(aa64_fp16, s)) { |
b8f5171c RH |
6197 | unallocated_encoding(s); |
6198 | return; | |
6199 | } | |
6200 | if (!fp_access_check(s)) { | |
6201 | return; | |
6202 | } | |
6203 | handle_fp_2src_half(s, opcode, rd, rn, rm); | |
6204 | break; | |
ec73d2e0 AG |
6205 | default: |
6206 | unallocated_encoding(s); | |
6207 | } | |
faa0ba46 PM |
6208 | } |
6209 | ||
4ce31af4 | 6210 | /* Floating-point data-processing (3 source) - single precision */ |
6a30667f AG |
6211 | static void handle_fp_3src_single(DisasContext *s, bool o0, bool o1, |
6212 | int rd, int rn, int rm, int ra) | |
6213 | { | |
6214 | TCGv_i32 tcg_op1, tcg_op2, tcg_op3; | |
6215 | TCGv_i32 tcg_res = tcg_temp_new_i32(); | |
d81ce0ef | 6216 | TCGv_ptr fpst = get_fpstatus_ptr(false); |
6a30667f AG |
6217 | |
6218 | tcg_op1 = read_fp_sreg(s, rn); | |
6219 | tcg_op2 = read_fp_sreg(s, rm); | |
6220 | tcg_op3 = read_fp_sreg(s, ra); | |
6221 | ||
6222 | /* These are fused multiply-add, and must be done as one | |
6223 | * floating point operation with no rounding between the | |
6224 | * multiplication and addition steps. | |
6225 | * NB that doing the negations here as separate steps is | |
6226 | * correct : an input NaN should come out with its sign bit | |
6227 | * flipped if it is a negated-input. | |
6228 | */ | |
6229 | if (o1 == true) { | |
6230 | gen_helper_vfp_negs(tcg_op3, tcg_op3); | |
6231 | } | |
6232 | ||
6233 | if (o0 != o1) { | |
6234 | gen_helper_vfp_negs(tcg_op1, tcg_op1); | |
6235 | } | |
6236 | ||
6237 | gen_helper_vfp_muladds(tcg_res, tcg_op1, tcg_op2, tcg_op3, fpst); | |
6238 | ||
6239 | write_fp_sreg(s, rd, tcg_res); | |
6240 | ||
6241 | tcg_temp_free_ptr(fpst); | |
6242 | tcg_temp_free_i32(tcg_op1); | |
6243 | tcg_temp_free_i32(tcg_op2); | |
6244 | tcg_temp_free_i32(tcg_op3); | |
6245 | tcg_temp_free_i32(tcg_res); | |
6246 | } | |
6247 | ||
4ce31af4 | 6248 | /* Floating-point data-processing (3 source) - double precision */ |
6a30667f AG |
6249 | static void handle_fp_3src_double(DisasContext *s, bool o0, bool o1, |
6250 | int rd, int rn, int rm, int ra) | |
6251 | { | |
6252 | TCGv_i64 tcg_op1, tcg_op2, tcg_op3; | |
6253 | TCGv_i64 tcg_res = tcg_temp_new_i64(); | |
d81ce0ef | 6254 | TCGv_ptr fpst = get_fpstatus_ptr(false); |
6a30667f AG |
6255 | |
6256 | tcg_op1 = read_fp_dreg(s, rn); | |
6257 | tcg_op2 = read_fp_dreg(s, rm); | |
6258 | tcg_op3 = read_fp_dreg(s, ra); | |
6259 | ||
6260 | /* These are fused multiply-add, and must be done as one | |
6261 | * floating point operation with no rounding between the | |
6262 | * multiplication and addition steps. | |
6263 | * NB that doing the negations here as separate steps is | |
6264 | * correct : an input NaN should come out with its sign bit | |
6265 | * flipped if it is a negated-input. | |
6266 | */ | |
6267 | if (o1 == true) { | |
6268 | gen_helper_vfp_negd(tcg_op3, tcg_op3); | |
6269 | } | |
6270 | ||
6271 | if (o0 != o1) { | |
6272 | gen_helper_vfp_negd(tcg_op1, tcg_op1); | |
6273 | } | |
6274 | ||
6275 | gen_helper_vfp_muladdd(tcg_res, tcg_op1, tcg_op2, tcg_op3, fpst); | |
6276 | ||
6277 | write_fp_dreg(s, rd, tcg_res); | |
6278 | ||
6279 | tcg_temp_free_ptr(fpst); | |
6280 | tcg_temp_free_i64(tcg_op1); | |
6281 | tcg_temp_free_i64(tcg_op2); | |
6282 | tcg_temp_free_i64(tcg_op3); | |
6283 | tcg_temp_free_i64(tcg_res); | |
6284 | } | |
6285 | ||
95f9864f RH |
6286 | /* Floating-point data-processing (3 source) - half precision */ |
6287 | static void handle_fp_3src_half(DisasContext *s, bool o0, bool o1, | |
6288 | int rd, int rn, int rm, int ra) | |
6289 | { | |
6290 | TCGv_i32 tcg_op1, tcg_op2, tcg_op3; | |
6291 | TCGv_i32 tcg_res = tcg_temp_new_i32(); | |
6292 | TCGv_ptr fpst = get_fpstatus_ptr(true); | |
6293 | ||
6294 | tcg_op1 = read_fp_hreg(s, rn); | |
6295 | tcg_op2 = read_fp_hreg(s, rm); | |
6296 | tcg_op3 = read_fp_hreg(s, ra); | |
6297 | ||
6298 | /* These are fused multiply-add, and must be done as one | |
6299 | * floating point operation with no rounding between the | |
6300 | * multiplication and addition steps. | |
6301 | * NB that doing the negations here as separate steps is | |
6302 | * correct : an input NaN should come out with its sign bit | |
6303 | * flipped if it is a negated-input. | |
6304 | */ | |
6305 | if (o1 == true) { | |
6306 | tcg_gen_xori_i32(tcg_op3, tcg_op3, 0x8000); | |
6307 | } | |
6308 | ||
6309 | if (o0 != o1) { | |
6310 | tcg_gen_xori_i32(tcg_op1, tcg_op1, 0x8000); | |
6311 | } | |
6312 | ||
6313 | gen_helper_advsimd_muladdh(tcg_res, tcg_op1, tcg_op2, tcg_op3, fpst); | |
6314 | ||
6315 | write_fp_sreg(s, rd, tcg_res); | |
6316 | ||
6317 | tcg_temp_free_ptr(fpst); | |
6318 | tcg_temp_free_i32(tcg_op1); | |
6319 | tcg_temp_free_i32(tcg_op2); | |
6320 | tcg_temp_free_i32(tcg_op3); | |
6321 | tcg_temp_free_i32(tcg_res); | |
6322 | } | |
6323 | ||
4ce31af4 | 6324 | /* Floating point data-processing (3 source) |
faa0ba46 PM |
6325 | * 31 30 29 28 24 23 22 21 20 16 15 14 10 9 5 4 0 |
6326 | * +---+---+---+-----------+------+----+------+----+------+------+------+ | |
6327 | * | M | 0 | S | 1 1 1 1 1 | type | o1 | Rm | o0 | Ra | Rn | Rd | | |
6328 | * +---+---+---+-----------+------+----+------+----+------+------+------+ | |
6329 | */ | |
6330 | static void disas_fp_3src(DisasContext *s, uint32_t insn) | |
6331 | { | |
c1e20801 | 6332 | int mos = extract32(insn, 29, 3); |
6a30667f AG |
6333 | int type = extract32(insn, 22, 2); |
6334 | int rd = extract32(insn, 0, 5); | |
6335 | int rn = extract32(insn, 5, 5); | |
6336 | int ra = extract32(insn, 10, 5); | |
6337 | int rm = extract32(insn, 16, 5); | |
6338 | bool o0 = extract32(insn, 15, 1); | |
6339 | bool o1 = extract32(insn, 21, 1); | |
6340 | ||
c1e20801 PM |
6341 | if (mos) { |
6342 | unallocated_encoding(s); | |
6343 | return; | |
6344 | } | |
6345 | ||
6a30667f AG |
6346 | switch (type) { |
6347 | case 0: | |
8c6afa6a PM |
6348 | if (!fp_access_check(s)) { |
6349 | return; | |
6350 | } | |
6a30667f AG |
6351 | handle_fp_3src_single(s, o0, o1, rd, rn, rm, ra); |
6352 | break; | |
6353 | case 1: | |
8c6afa6a PM |
6354 | if (!fp_access_check(s)) { |
6355 | return; | |
6356 | } | |
6a30667f AG |
6357 | handle_fp_3src_double(s, o0, o1, rd, rn, rm, ra); |
6358 | break; | |
95f9864f | 6359 | case 3: |
5763190f | 6360 | if (!dc_isar_feature(aa64_fp16, s)) { |
95f9864f RH |
6361 | unallocated_encoding(s); |
6362 | return; | |
6363 | } | |
6364 | if (!fp_access_check(s)) { | |
6365 | return; | |
6366 | } | |
6367 | handle_fp_3src_half(s, o0, o1, rd, rn, rm, ra); | |
6368 | break; | |
6a30667f AG |
6369 | default: |
6370 | unallocated_encoding(s); | |
6371 | } | |
faa0ba46 PM |
6372 | } |
6373 | ||
4ce31af4 | 6374 | /* Floating point immediate |
faa0ba46 PM |
6375 | * 31 30 29 28 24 23 22 21 20 13 12 10 9 5 4 0 |
6376 | * +---+---+---+-----------+------+---+------------+-------+------+------+ | |
6377 | * | M | 0 | S | 1 1 1 1 0 | type | 1 | imm8 | 1 0 0 | imm5 | Rd | | |
6378 | * +---+---+---+-----------+------+---+------------+-------+------+------+ | |
6379 | */ | |
6380 | static void disas_fp_imm(DisasContext *s, uint32_t insn) | |
6381 | { | |
6163f868 | 6382 | int rd = extract32(insn, 0, 5); |
c1e20801 | 6383 | int imm5 = extract32(insn, 5, 5); |
6163f868 | 6384 | int imm8 = extract32(insn, 13, 8); |
6ba28ddb | 6385 | int type = extract32(insn, 22, 2); |
c1e20801 | 6386 | int mos = extract32(insn, 29, 3); |
6163f868 AG |
6387 | uint64_t imm; |
6388 | TCGv_i64 tcg_res; | |
14776ab5 | 6389 | MemOp sz; |
6163f868 | 6390 | |
c1e20801 PM |
6391 | if (mos || imm5) { |
6392 | unallocated_encoding(s); | |
6393 | return; | |
6394 | } | |
6395 | ||
6ba28ddb AB |
6396 | switch (type) { |
6397 | case 0: | |
6398 | sz = MO_32; | |
6399 | break; | |
6400 | case 1: | |
6401 | sz = MO_64; | |
6402 | break; | |
6403 | case 3: | |
6404 | sz = MO_16; | |
5763190f | 6405 | if (dc_isar_feature(aa64_fp16, s)) { |
6ba28ddb AB |
6406 | break; |
6407 | } | |
6408 | /* fallthru */ | |
6409 | default: | |
6163f868 AG |
6410 | unallocated_encoding(s); |
6411 | return; | |
6412 | } | |
6413 | ||
8c6afa6a PM |
6414 | if (!fp_access_check(s)) { |
6415 | return; | |
6416 | } | |
6417 | ||
6ba28ddb | 6418 | imm = vfp_expand_imm(sz, imm8); |
6163f868 AG |
6419 | |
6420 | tcg_res = tcg_const_i64(imm); | |
6421 | write_fp_dreg(s, rd, tcg_res); | |
6422 | tcg_temp_free_i64(tcg_res); | |
faa0ba46 PM |
6423 | } |
6424 | ||
52a1f6a3 AG |
6425 | /* Handle floating point <=> fixed point conversions. Note that we can |
6426 | * also deal with fp <=> integer conversions as a special case (scale == 64) | |
6427 | * OPTME: consider handling that special case specially or at least skipping | |
6428 | * the call to scalbn in the helpers for zero shifts. | |
6429 | */ | |
6430 | static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode, | |
6431 | bool itof, int rmode, int scale, int sf, int type) | |
6432 | { | |
6433 | bool is_signed = !(opcode & 1); | |
52a1f6a3 | 6434 | TCGv_ptr tcg_fpstatus; |
564a0632 RH |
6435 | TCGv_i32 tcg_shift, tcg_single; |
6436 | TCGv_i64 tcg_double; | |
52a1f6a3 | 6437 | |
564a0632 | 6438 | tcg_fpstatus = get_fpstatus_ptr(type == 3); |
52a1f6a3 AG |
6439 | |
6440 | tcg_shift = tcg_const_i32(64 - scale); | |
6441 | ||
6442 | if (itof) { | |
6443 | TCGv_i64 tcg_int = cpu_reg(s, rn); | |
6444 | if (!sf) { | |
6445 | TCGv_i64 tcg_extend = new_tmp_a64(s); | |
6446 | ||
6447 | if (is_signed) { | |
6448 | tcg_gen_ext32s_i64(tcg_extend, tcg_int); | |
6449 | } else { | |
6450 | tcg_gen_ext32u_i64(tcg_extend, tcg_int); | |
6451 | } | |
6452 | ||
6453 | tcg_int = tcg_extend; | |
6454 | } | |
6455 | ||
564a0632 RH |
6456 | switch (type) { |
6457 | case 1: /* float64 */ | |
6458 | tcg_double = tcg_temp_new_i64(); | |
52a1f6a3 AG |
6459 | if (is_signed) { |
6460 | gen_helper_vfp_sqtod(tcg_double, tcg_int, | |
6461 | tcg_shift, tcg_fpstatus); | |
6462 | } else { | |
6463 | gen_helper_vfp_uqtod(tcg_double, tcg_int, | |
6464 | tcg_shift, tcg_fpstatus); | |
6465 | } | |
6466 | write_fp_dreg(s, rd, tcg_double); | |
6467 | tcg_temp_free_i64(tcg_double); | |
564a0632 RH |
6468 | break; |
6469 | ||
6470 | case 0: /* float32 */ | |
6471 | tcg_single = tcg_temp_new_i32(); | |
52a1f6a3 AG |
6472 | if (is_signed) { |
6473 | gen_helper_vfp_sqtos(tcg_single, tcg_int, | |
6474 | tcg_shift, tcg_fpstatus); | |
6475 | } else { | |
6476 | gen_helper_vfp_uqtos(tcg_single, tcg_int, | |
6477 | tcg_shift, tcg_fpstatus); | |
6478 | } | |
6479 | write_fp_sreg(s, rd, tcg_single); | |
6480 | tcg_temp_free_i32(tcg_single); | |
564a0632 RH |
6481 | break; |
6482 | ||
6483 | case 3: /* float16 */ | |
6484 | tcg_single = tcg_temp_new_i32(); | |
6485 | if (is_signed) { | |
6486 | gen_helper_vfp_sqtoh(tcg_single, tcg_int, | |
6487 | tcg_shift, tcg_fpstatus); | |
6488 | } else { | |
6489 | gen_helper_vfp_uqtoh(tcg_single, tcg_int, | |
6490 | tcg_shift, tcg_fpstatus); | |
6491 | } | |
6492 | write_fp_sreg(s, rd, tcg_single); | |
6493 | tcg_temp_free_i32(tcg_single); | |
6494 | break; | |
6495 | ||
6496 | default: | |
6497 | g_assert_not_reached(); | |
52a1f6a3 AG |
6498 | } |
6499 | } else { | |
6500 | TCGv_i64 tcg_int = cpu_reg(s, rd); | |
6501 | TCGv_i32 tcg_rmode; | |
6502 | ||
6503 | if (extract32(opcode, 2, 1)) { | |
6504 | /* There are too many rounding modes to all fit into rmode, | |
6505 | * so FCVTA[US] is a special case. | |
6506 | */ | |
6507 | rmode = FPROUNDING_TIEAWAY; | |
6508 | } | |
6509 | ||
6510 | tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode)); | |
6511 | ||
9b049916 | 6512 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); |
52a1f6a3 | 6513 | |
564a0632 RH |
6514 | switch (type) { |
6515 | case 1: /* float64 */ | |
6516 | tcg_double = read_fp_dreg(s, rn); | |
52a1f6a3 AG |
6517 | if (is_signed) { |
6518 | if (!sf) { | |
6519 | gen_helper_vfp_tosld(tcg_int, tcg_double, | |
6520 | tcg_shift, tcg_fpstatus); | |
6521 | } else { | |
6522 | gen_helper_vfp_tosqd(tcg_int, tcg_double, | |
6523 | tcg_shift, tcg_fpstatus); | |
6524 | } | |
6525 | } else { | |
6526 | if (!sf) { | |
6527 | gen_helper_vfp_tould(tcg_int, tcg_double, | |
6528 | tcg_shift, tcg_fpstatus); | |
6529 | } else { | |
6530 | gen_helper_vfp_touqd(tcg_int, tcg_double, | |
6531 | tcg_shift, tcg_fpstatus); | |
6532 | } | |
6533 | } | |
564a0632 RH |
6534 | if (!sf) { |
6535 | tcg_gen_ext32u_i64(tcg_int, tcg_int); | |
6536 | } | |
52a1f6a3 | 6537 | tcg_temp_free_i64(tcg_double); |
564a0632 RH |
6538 | break; |
6539 | ||
6540 | case 0: /* float32 */ | |
6541 | tcg_single = read_fp_sreg(s, rn); | |
52a1f6a3 AG |
6542 | if (sf) { |
6543 | if (is_signed) { | |
6544 | gen_helper_vfp_tosqs(tcg_int, tcg_single, | |
6545 | tcg_shift, tcg_fpstatus); | |
6546 | } else { | |
6547 | gen_helper_vfp_touqs(tcg_int, tcg_single, | |
6548 | tcg_shift, tcg_fpstatus); | |
6549 | } | |
6550 | } else { | |
6551 | TCGv_i32 tcg_dest = tcg_temp_new_i32(); | |
6552 | if (is_signed) { | |
6553 | gen_helper_vfp_tosls(tcg_dest, tcg_single, | |
6554 | tcg_shift, tcg_fpstatus); | |
6555 | } else { | |
6556 | gen_helper_vfp_touls(tcg_dest, tcg_single, | |
6557 | tcg_shift, tcg_fpstatus); | |
6558 | } | |
6559 | tcg_gen_extu_i32_i64(tcg_int, tcg_dest); | |
6560 | tcg_temp_free_i32(tcg_dest); | |
6561 | } | |
6562 | tcg_temp_free_i32(tcg_single); | |
564a0632 RH |
6563 | break; |
6564 | ||
6565 | case 3: /* float16 */ | |
6566 | tcg_single = read_fp_sreg(s, rn); | |
6567 | if (sf) { | |
6568 | if (is_signed) { | |
6569 | gen_helper_vfp_tosqh(tcg_int, tcg_single, | |
6570 | tcg_shift, tcg_fpstatus); | |
6571 | } else { | |
6572 | gen_helper_vfp_touqh(tcg_int, tcg_single, | |
6573 | tcg_shift, tcg_fpstatus); | |
6574 | } | |
6575 | } else { | |
6576 | TCGv_i32 tcg_dest = tcg_temp_new_i32(); | |
6577 | if (is_signed) { | |
6578 | gen_helper_vfp_toslh(tcg_dest, tcg_single, | |
6579 | tcg_shift, tcg_fpstatus); | |
6580 | } else { | |
6581 | gen_helper_vfp_toulh(tcg_dest, tcg_single, | |
6582 | tcg_shift, tcg_fpstatus); | |
6583 | } | |
6584 | tcg_gen_extu_i32_i64(tcg_int, tcg_dest); | |
6585 | tcg_temp_free_i32(tcg_dest); | |
6586 | } | |
6587 | tcg_temp_free_i32(tcg_single); | |
6588 | break; | |
6589 | ||
6590 | default: | |
6591 | g_assert_not_reached(); | |
52a1f6a3 AG |
6592 | } |
6593 | ||
9b049916 | 6594 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); |
52a1f6a3 | 6595 | tcg_temp_free_i32(tcg_rmode); |
52a1f6a3 AG |
6596 | } |
6597 | ||
6598 | tcg_temp_free_ptr(tcg_fpstatus); | |
6599 | tcg_temp_free_i32(tcg_shift); | |
6600 | } | |
6601 | ||
4ce31af4 | 6602 | /* Floating point <-> fixed point conversions |
faa0ba46 PM |
6603 | * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0 |
6604 | * +----+---+---+-----------+------+---+-------+--------+-------+------+------+ | |
6605 | * | sf | 0 | S | 1 1 1 1 0 | type | 0 | rmode | opcode | scale | Rn | Rd | | |
6606 | * +----+---+---+-----------+------+---+-------+--------+-------+------+------+ | |
6607 | */ | |
6608 | static void disas_fp_fixed_conv(DisasContext *s, uint32_t insn) | |
6609 | { | |
52a1f6a3 AG |
6610 | int rd = extract32(insn, 0, 5); |
6611 | int rn = extract32(insn, 5, 5); | |
6612 | int scale = extract32(insn, 10, 6); | |
6613 | int opcode = extract32(insn, 16, 3); | |
6614 | int rmode = extract32(insn, 19, 2); | |
6615 | int type = extract32(insn, 22, 2); | |
6616 | bool sbit = extract32(insn, 29, 1); | |
6617 | bool sf = extract32(insn, 31, 1); | |
6618 | bool itof; | |
6619 | ||
27527280 RH |
6620 | if (sbit || (!sf && scale < 32)) { |
6621 | unallocated_encoding(s); | |
6622 | return; | |
6623 | } | |
6624 | ||
6625 | switch (type) { | |
6626 | case 0: /* float32 */ | |
6627 | case 1: /* float64 */ | |
6628 | break; | |
6629 | case 3: /* float16 */ | |
5763190f | 6630 | if (dc_isar_feature(aa64_fp16, s)) { |
27527280 RH |
6631 | break; |
6632 | } | |
6633 | /* fallthru */ | |
6634 | default: | |
52a1f6a3 AG |
6635 | unallocated_encoding(s); |
6636 | return; | |
6637 | } | |
6638 | ||
6639 | switch ((rmode << 3) | opcode) { | |
6640 | case 0x2: /* SCVTF */ | |
6641 | case 0x3: /* UCVTF */ | |
6642 | itof = true; | |
6643 | break; | |
6644 | case 0x18: /* FCVTZS */ | |
6645 | case 0x19: /* FCVTZU */ | |
6646 | itof = false; | |
6647 | break; | |
6648 | default: | |
6649 | unallocated_encoding(s); | |
6650 | return; | |
6651 | } | |
6652 | ||
8c6afa6a PM |
6653 | if (!fp_access_check(s)) { |
6654 | return; | |
6655 | } | |
6656 | ||
52a1f6a3 | 6657 | handle_fpfpcvt(s, rd, rn, opcode, itof, FPROUNDING_ZERO, scale, sf, type); |
faa0ba46 PM |
6658 | } |
6659 | ||
ce5458e8 PM |
6660 | static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof) |
6661 | { | |
6662 | /* FMOV: gpr to or from float, double, or top half of quad fp reg, | |
6663 | * without conversion. | |
6664 | */ | |
6665 | ||
6666 | if (itof) { | |
ce5458e8 | 6667 | TCGv_i64 tcg_rn = cpu_reg(s, rn); |
9a9f1f59 | 6668 | TCGv_i64 tmp; |
ce5458e8 PM |
6669 | |
6670 | switch (type) { | |
6671 | case 0: | |
ce5458e8 | 6672 | /* 32 bit */ |
9a9f1f59 | 6673 | tmp = tcg_temp_new_i64(); |
ce5458e8 | 6674 | tcg_gen_ext32u_i64(tmp, tcg_rn); |
9a9f1f59 | 6675 | write_fp_dreg(s, rd, tmp); |
ce5458e8 PM |
6676 | tcg_temp_free_i64(tmp); |
6677 | break; | |
ce5458e8 | 6678 | case 1: |
ce5458e8 | 6679 | /* 64 bit */ |
9a9f1f59 | 6680 | write_fp_dreg(s, rd, tcg_rn); |
ce5458e8 | 6681 | break; |
ce5458e8 PM |
6682 | case 2: |
6683 | /* 64 bit to top half. */ | |
90e49638 | 6684 | tcg_gen_st_i64(tcg_rn, cpu_env, fp_reg_hi_offset(s, rd)); |
9a9f1f59 | 6685 | clear_vec_high(s, true, rd); |
ce5458e8 | 6686 | break; |
68130236 RH |
6687 | case 3: |
6688 | /* 16 bit */ | |
6689 | tmp = tcg_temp_new_i64(); | |
6690 | tcg_gen_ext16u_i64(tmp, tcg_rn); | |
6691 | write_fp_dreg(s, rd, tmp); | |
6692 | tcg_temp_free_i64(tmp); | |
6693 | break; | |
6694 | default: | |
6695 | g_assert_not_reached(); | |
ce5458e8 PM |
6696 | } |
6697 | } else { | |
ce5458e8 PM |
6698 | TCGv_i64 tcg_rd = cpu_reg(s, rd); |
6699 | ||
6700 | switch (type) { | |
6701 | case 0: | |
6702 | /* 32 bit */ | |
90e49638 | 6703 | tcg_gen_ld32u_i64(tcg_rd, cpu_env, fp_reg_offset(s, rn, MO_32)); |
ce5458e8 | 6704 | break; |
ce5458e8 PM |
6705 | case 1: |
6706 | /* 64 bit */ | |
90e49638 | 6707 | tcg_gen_ld_i64(tcg_rd, cpu_env, fp_reg_offset(s, rn, MO_64)); |
e2f90565 PM |
6708 | break; |
6709 | case 2: | |
6710 | /* 64 bits from top half */ | |
90e49638 | 6711 | tcg_gen_ld_i64(tcg_rd, cpu_env, fp_reg_hi_offset(s, rn)); |
ce5458e8 | 6712 | break; |
68130236 RH |
6713 | case 3: |
6714 | /* 16 bit */ | |
6715 | tcg_gen_ld16u_i64(tcg_rd, cpu_env, fp_reg_offset(s, rn, MO_16)); | |
6716 | break; | |
6717 | default: | |
6718 | g_assert_not_reached(); | |
ce5458e8 PM |
6719 | } |
6720 | } | |
6721 | } | |
6722 | ||
6c1f6f27 RH |
6723 | static void handle_fjcvtzs(DisasContext *s, int rd, int rn) |
6724 | { | |
6725 | TCGv_i64 t = read_fp_dreg(s, rn); | |
6726 | TCGv_ptr fpstatus = get_fpstatus_ptr(false); | |
6727 | ||
6728 | gen_helper_fjcvtzs(t, t, fpstatus); | |
6729 | ||
6730 | tcg_temp_free_ptr(fpstatus); | |
6731 | ||
6732 | tcg_gen_ext32u_i64(cpu_reg(s, rd), t); | |
6733 | tcg_gen_extrh_i64_i32(cpu_ZF, t); | |
6734 | tcg_gen_movi_i32(cpu_CF, 0); | |
6735 | tcg_gen_movi_i32(cpu_NF, 0); | |
6736 | tcg_gen_movi_i32(cpu_VF, 0); | |
6737 | ||
6738 | tcg_temp_free_i64(t); | |
6739 | } | |
6740 | ||
4ce31af4 | 6741 | /* Floating point <-> integer conversions |
faa0ba46 PM |
6742 | * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0 |
6743 | * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+ | |
c436d406 | 6744 | * | sf | 0 | S | 1 1 1 1 0 | type | 1 | rmode | opc | 0 0 0 0 0 0 | Rn | Rd | |
faa0ba46 PM |
6745 | * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+ |
6746 | */ | |
6747 | static void disas_fp_int_conv(DisasContext *s, uint32_t insn) | |
6748 | { | |
ce5458e8 PM |
6749 | int rd = extract32(insn, 0, 5); |
6750 | int rn = extract32(insn, 5, 5); | |
6751 | int opcode = extract32(insn, 16, 3); | |
6752 | int rmode = extract32(insn, 19, 2); | |
6753 | int type = extract32(insn, 22, 2); | |
6754 | bool sbit = extract32(insn, 29, 1); | |
6755 | bool sf = extract32(insn, 31, 1); | |
3c3ff684 | 6756 | bool itof = false; |
ce5458e8 | 6757 | |
c436d406 | 6758 | if (sbit) { |
3c3ff684 | 6759 | goto do_unallocated; |
c436d406 WN |
6760 | } |
6761 | ||
3c3ff684 RH |
6762 | switch (opcode) { |
6763 | case 2: /* SCVTF */ | |
6764 | case 3: /* UCVTF */ | |
6765 | itof = true; | |
6766 | /* fallthru */ | |
6767 | case 4: /* FCVTAS */ | |
6768 | case 5: /* FCVTAU */ | |
6769 | if (rmode != 0) { | |
6770 | goto do_unallocated; | |
c436d406 | 6771 | } |
3c3ff684 RH |
6772 | /* fallthru */ |
6773 | case 0: /* FCVT[NPMZ]S */ | |
6774 | case 1: /* FCVT[NPMZ]U */ | |
6775 | switch (type) { | |
6776 | case 0: /* float32 */ | |
6777 | case 1: /* float64 */ | |
ce5458e8 | 6778 | break; |
3c3ff684 RH |
6779 | case 3: /* float16 */ |
6780 | if (!dc_isar_feature(aa64_fp16, s)) { | |
6781 | goto do_unallocated; | |
68130236 | 6782 | } |
3c3ff684 | 6783 | break; |
ce5458e8 | 6784 | default: |
3c3ff684 | 6785 | goto do_unallocated; |
ce5458e8 | 6786 | } |
8c6afa6a PM |
6787 | if (!fp_access_check(s)) { |
6788 | return; | |
6789 | } | |
3c3ff684 RH |
6790 | handle_fpfpcvt(s, rd, rn, opcode, itof, rmode, 64, sf, type); |
6791 | break; | |
c436d406 | 6792 | |
3c3ff684 RH |
6793 | default: |
6794 | switch (sf << 7 | type << 5 | rmode << 3 | opcode) { | |
6795 | case 0b01100110: /* FMOV half <-> 32-bit int */ | |
6796 | case 0b01100111: | |
6797 | case 0b11100110: /* FMOV half <-> 64-bit int */ | |
6798 | case 0b11100111: | |
6799 | if (!dc_isar_feature(aa64_fp16, s)) { | |
6800 | goto do_unallocated; | |
564a0632 RH |
6801 | } |
6802 | /* fallthru */ | |
3c3ff684 RH |
6803 | case 0b00000110: /* FMOV 32-bit */ |
6804 | case 0b00000111: | |
6805 | case 0b10100110: /* FMOV 64-bit */ | |
6806 | case 0b10100111: | |
6807 | case 0b11001110: /* FMOV top half of 128-bit */ | |
6808 | case 0b11001111: | |
6809 | if (!fp_access_check(s)) { | |
6810 | return; | |
6811 | } | |
6812 | itof = opcode & 1; | |
6813 | handle_fmov(s, rd, rn, type, itof); | |
6814 | break; | |
6815 | ||
6c1f6f27 RH |
6816 | case 0b00111110: /* FJCVTZS */ |
6817 | if (!dc_isar_feature(aa64_jscvt, s)) { | |
6818 | goto do_unallocated; | |
6819 | } else if (fp_access_check(s)) { | |
6820 | handle_fjcvtzs(s, rd, rn); | |
6821 | } | |
6822 | break; | |
6823 | ||
564a0632 | 6824 | default: |
3c3ff684 | 6825 | do_unallocated: |
c436d406 WN |
6826 | unallocated_encoding(s); |
6827 | return; | |
6828 | } | |
3c3ff684 | 6829 | break; |
ce5458e8 | 6830 | } |
faa0ba46 PM |
6831 | } |
6832 | ||
6833 | /* FP-specific subcases of table C3-6 (SIMD and FP data processing) | |
6834 | * 31 30 29 28 25 24 0 | |
6835 | * +---+---+---+---------+-----------------------------+ | |
6836 | * | | 0 | | 1 1 1 1 | | | |
6837 | * +---+---+---+---------+-----------------------------+ | |
6838 | */ | |
6839 | static void disas_data_proc_fp(DisasContext *s, uint32_t insn) | |
6840 | { | |
6841 | if (extract32(insn, 24, 1)) { | |
6842 | /* Floating point data-processing (3 source) */ | |
6843 | disas_fp_3src(s, insn); | |
6844 | } else if (extract32(insn, 21, 1) == 0) { | |
6845 | /* Floating point to fixed point conversions */ | |
6846 | disas_fp_fixed_conv(s, insn); | |
6847 | } else { | |
6848 | switch (extract32(insn, 10, 2)) { | |
6849 | case 1: | |
6850 | /* Floating point conditional compare */ | |
6851 | disas_fp_ccomp(s, insn); | |
6852 | break; | |
6853 | case 2: | |
6854 | /* Floating point data-processing (2 source) */ | |
6855 | disas_fp_2src(s, insn); | |
6856 | break; | |
6857 | case 3: | |
6858 | /* Floating point conditional select */ | |
6859 | disas_fp_csel(s, insn); | |
6860 | break; | |
6861 | case 0: | |
6862 | switch (ctz32(extract32(insn, 12, 4))) { | |
6863 | case 0: /* [15:12] == xxx1 */ | |
6864 | /* Floating point immediate */ | |
6865 | disas_fp_imm(s, insn); | |
6866 | break; | |
6867 | case 1: /* [15:12] == xx10 */ | |
6868 | /* Floating point compare */ | |
6869 | disas_fp_compare(s, insn); | |
6870 | break; | |
6871 | case 2: /* [15:12] == x100 */ | |
6872 | /* Floating point data-processing (1 source) */ | |
6873 | disas_fp_1src(s, insn); | |
6874 | break; | |
6875 | case 3: /* [15:12] == 1000 */ | |
6876 | unallocated_encoding(s); | |
6877 | break; | |
6878 | default: /* [15:12] == 0000 */ | |
6879 | /* Floating point <-> integer conversions */ | |
6880 | disas_fp_int_conv(s, insn); | |
6881 | break; | |
6882 | } | |
6883 | break; | |
6884 | } | |
6885 | } | |
6886 | } | |
6887 | ||
5c73747f PM |
6888 | static void do_ext64(DisasContext *s, TCGv_i64 tcg_left, TCGv_i64 tcg_right, |
6889 | int pos) | |
6890 | { | |
6891 | /* Extract 64 bits from the middle of two concatenated 64 bit | |
6892 | * vector register slices left:right. The extracted bits start | |
6893 | * at 'pos' bits into the right (least significant) side. | |
6894 | * We return the result in tcg_right, and guarantee not to | |
6895 | * trash tcg_left. | |
6896 | */ | |
6897 | TCGv_i64 tcg_tmp = tcg_temp_new_i64(); | |
6898 | assert(pos > 0 && pos < 64); | |
6899 | ||
6900 | tcg_gen_shri_i64(tcg_right, tcg_right, pos); | |
6901 | tcg_gen_shli_i64(tcg_tmp, tcg_left, 64 - pos); | |
6902 | tcg_gen_or_i64(tcg_right, tcg_right, tcg_tmp); | |
6903 | ||
6904 | tcg_temp_free_i64(tcg_tmp); | |
6905 | } | |
6906 | ||
4ce31af4 | 6907 | /* EXT |
384b26fb AB |
6908 | * 31 30 29 24 23 22 21 20 16 15 14 11 10 9 5 4 0 |
6909 | * +---+---+-------------+-----+---+------+---+------+---+------+------+ | |
6910 | * | 0 | Q | 1 0 1 1 1 0 | op2 | 0 | Rm | 0 | imm4 | 0 | Rn | Rd | | |
6911 | * +---+---+-------------+-----+---+------+---+------+---+------+------+ | |
6912 | */ | |
6913 | static void disas_simd_ext(DisasContext *s, uint32_t insn) | |
6914 | { | |
5c73747f PM |
6915 | int is_q = extract32(insn, 30, 1); |
6916 | int op2 = extract32(insn, 22, 2); | |
6917 | int imm4 = extract32(insn, 11, 4); | |
6918 | int rm = extract32(insn, 16, 5); | |
6919 | int rn = extract32(insn, 5, 5); | |
6920 | int rd = extract32(insn, 0, 5); | |
6921 | int pos = imm4 << 3; | |
6922 | TCGv_i64 tcg_resl, tcg_resh; | |
6923 | ||
6924 | if (op2 != 0 || (!is_q && extract32(imm4, 3, 1))) { | |
6925 | unallocated_encoding(s); | |
6926 | return; | |
6927 | } | |
6928 | ||
8c6afa6a PM |
6929 | if (!fp_access_check(s)) { |
6930 | return; | |
6931 | } | |
6932 | ||
5c73747f PM |
6933 | tcg_resh = tcg_temp_new_i64(); |
6934 | tcg_resl = tcg_temp_new_i64(); | |
6935 | ||
6936 | /* Vd gets bits starting at pos bits into Vm:Vn. This is | |
6937 | * either extracting 128 bits from a 128:128 concatenation, or | |
6938 | * extracting 64 bits from a 64:64 concatenation. | |
6939 | */ | |
6940 | if (!is_q) { | |
6941 | read_vec_element(s, tcg_resl, rn, 0, MO_64); | |
6942 | if (pos != 0) { | |
6943 | read_vec_element(s, tcg_resh, rm, 0, MO_64); | |
6944 | do_ext64(s, tcg_resh, tcg_resl, pos); | |
6945 | } | |
5c73747f PM |
6946 | } else { |
6947 | TCGv_i64 tcg_hh; | |
6948 | typedef struct { | |
6949 | int reg; | |
6950 | int elt; | |
6951 | } EltPosns; | |
6952 | EltPosns eltposns[] = { {rn, 0}, {rn, 1}, {rm, 0}, {rm, 1} }; | |
6953 | EltPosns *elt = eltposns; | |
6954 | ||
6955 | if (pos >= 64) { | |
6956 | elt++; | |
6957 | pos -= 64; | |
6958 | } | |
6959 | ||
6960 | read_vec_element(s, tcg_resl, elt->reg, elt->elt, MO_64); | |
6961 | elt++; | |
6962 | read_vec_element(s, tcg_resh, elt->reg, elt->elt, MO_64); | |
6963 | elt++; | |
6964 | if (pos != 0) { | |
6965 | do_ext64(s, tcg_resh, tcg_resl, pos); | |
6966 | tcg_hh = tcg_temp_new_i64(); | |
6967 | read_vec_element(s, tcg_hh, elt->reg, elt->elt, MO_64); | |
6968 | do_ext64(s, tcg_hh, tcg_resh, pos); | |
6969 | tcg_temp_free_i64(tcg_hh); | |
6970 | } | |
6971 | } | |
6972 | ||
6973 | write_vec_element(s, tcg_resl, rd, 0, MO_64); | |
6974 | tcg_temp_free_i64(tcg_resl); | |
e1f77859 RH |
6975 | if (is_q) { |
6976 | write_vec_element(s, tcg_resh, rd, 1, MO_64); | |
6977 | } | |
5c73747f | 6978 | tcg_temp_free_i64(tcg_resh); |
e1f77859 | 6979 | clear_vec_high(s, is_q, rd); |
384b26fb AB |
6980 | } |
6981 | ||
4ce31af4 | 6982 | /* TBL/TBX |
384b26fb AB |
6983 | * 31 30 29 24 23 22 21 20 16 15 14 13 12 11 10 9 5 4 0 |
6984 | * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+ | |
6985 | * | 0 | Q | 0 0 1 1 1 0 | op2 | 0 | Rm | 0 | len | op | 0 0 | Rn | Rd | | |
6986 | * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+ | |
6987 | */ | |
6988 | static void disas_simd_tb(DisasContext *s, uint32_t insn) | |
6989 | { | |
7c51048f MM |
6990 | int op2 = extract32(insn, 22, 2); |
6991 | int is_q = extract32(insn, 30, 1); | |
6992 | int rm = extract32(insn, 16, 5); | |
6993 | int rn = extract32(insn, 5, 5); | |
6994 | int rd = extract32(insn, 0, 5); | |
6995 | int is_tblx = extract32(insn, 12, 1); | |
6996 | int len = extract32(insn, 13, 2); | |
6997 | TCGv_i64 tcg_resl, tcg_resh, tcg_idx; | |
6998 | TCGv_i32 tcg_regno, tcg_numregs; | |
6999 | ||
7000 | if (op2 != 0) { | |
7001 | unallocated_encoding(s); | |
7002 | return; | |
7003 | } | |
7004 | ||
8c6afa6a PM |
7005 | if (!fp_access_check(s)) { |
7006 | return; | |
7007 | } | |
7008 | ||
7c51048f MM |
7009 | /* This does a table lookup: for every byte element in the input |
7010 | * we index into a table formed from up to four vector registers, | |
7011 | * and then the output is the result of the lookups. Our helper | |
7012 | * function does the lookup operation for a single 64 bit part of | |
7013 | * the input. | |
7014 | */ | |
7015 | tcg_resl = tcg_temp_new_i64(); | |
e1f77859 | 7016 | tcg_resh = NULL; |
7c51048f MM |
7017 | |
7018 | if (is_tblx) { | |
7019 | read_vec_element(s, tcg_resl, rd, 0, MO_64); | |
7020 | } else { | |
7021 | tcg_gen_movi_i64(tcg_resl, 0); | |
7022 | } | |
e1f77859 RH |
7023 | |
7024 | if (is_q) { | |
7025 | tcg_resh = tcg_temp_new_i64(); | |
7026 | if (is_tblx) { | |
7027 | read_vec_element(s, tcg_resh, rd, 1, MO_64); | |
7028 | } else { | |
7029 | tcg_gen_movi_i64(tcg_resh, 0); | |
7030 | } | |
7c51048f MM |
7031 | } |
7032 | ||
7033 | tcg_idx = tcg_temp_new_i64(); | |
7034 | tcg_regno = tcg_const_i32(rn); | |
7035 | tcg_numregs = tcg_const_i32(len + 1); | |
7036 | read_vec_element(s, tcg_idx, rm, 0, MO_64); | |
7037 | gen_helper_simd_tbl(tcg_resl, cpu_env, tcg_resl, tcg_idx, | |
7038 | tcg_regno, tcg_numregs); | |
7039 | if (is_q) { | |
7040 | read_vec_element(s, tcg_idx, rm, 1, MO_64); | |
7041 | gen_helper_simd_tbl(tcg_resh, cpu_env, tcg_resh, tcg_idx, | |
7042 | tcg_regno, tcg_numregs); | |
7043 | } | |
7044 | tcg_temp_free_i64(tcg_idx); | |
7045 | tcg_temp_free_i32(tcg_regno); | |
7046 | tcg_temp_free_i32(tcg_numregs); | |
7047 | ||
7048 | write_vec_element(s, tcg_resl, rd, 0, MO_64); | |
7049 | tcg_temp_free_i64(tcg_resl); | |
e1f77859 RH |
7050 | |
7051 | if (is_q) { | |
7052 | write_vec_element(s, tcg_resh, rd, 1, MO_64); | |
7053 | tcg_temp_free_i64(tcg_resh); | |
7054 | } | |
7055 | clear_vec_high(s, is_q, rd); | |
384b26fb AB |
7056 | } |
7057 | ||
4ce31af4 | 7058 | /* ZIP/UZP/TRN |
384b26fb AB |
7059 | * 31 30 29 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0 |
7060 | * +---+---+-------------+------+---+------+---+------------------+------+ | |
7061 | * | 0 | Q | 0 0 1 1 1 0 | size | 0 | Rm | 0 | opc | 1 0 | Rn | Rd | | |
7062 | * +---+---+-------------+------+---+------+---+------------------+------+ | |
7063 | */ | |
7064 | static void disas_simd_zip_trn(DisasContext *s, uint32_t insn) | |
7065 | { | |
5fa5469c MM |
7066 | int rd = extract32(insn, 0, 5); |
7067 | int rn = extract32(insn, 5, 5); | |
7068 | int rm = extract32(insn, 16, 5); | |
7069 | int size = extract32(insn, 22, 2); | |
7070 | /* opc field bits [1:0] indicate ZIP/UZP/TRN; | |
7071 | * bit 2 indicates 1 vs 2 variant of the insn. | |
7072 | */ | |
7073 | int opcode = extract32(insn, 12, 2); | |
7074 | bool part = extract32(insn, 14, 1); | |
7075 | bool is_q = extract32(insn, 30, 1); | |
7076 | int esize = 8 << size; | |
7077 | int i, ofs; | |
7078 | int datasize = is_q ? 128 : 64; | |
7079 | int elements = datasize / esize; | |
7080 | TCGv_i64 tcg_res, tcg_resl, tcg_resh; | |
7081 | ||
7082 | if (opcode == 0 || (size == 3 && !is_q)) { | |
7083 | unallocated_encoding(s); | |
7084 | return; | |
7085 | } | |
7086 | ||
8c6afa6a PM |
7087 | if (!fp_access_check(s)) { |
7088 | return; | |
7089 | } | |
7090 | ||
5fa5469c | 7091 | tcg_resl = tcg_const_i64(0); |
e1f77859 | 7092 | tcg_resh = is_q ? tcg_const_i64(0) : NULL; |
5fa5469c MM |
7093 | tcg_res = tcg_temp_new_i64(); |
7094 | ||
7095 | for (i = 0; i < elements; i++) { | |
7096 | switch (opcode) { | |
7097 | case 1: /* UZP1/2 */ | |
7098 | { | |
7099 | int midpoint = elements / 2; | |
7100 | if (i < midpoint) { | |
7101 | read_vec_element(s, tcg_res, rn, 2 * i + part, size); | |
7102 | } else { | |
7103 | read_vec_element(s, tcg_res, rm, | |
7104 | 2 * (i - midpoint) + part, size); | |
7105 | } | |
7106 | break; | |
7107 | } | |
7108 | case 2: /* TRN1/2 */ | |
7109 | if (i & 1) { | |
7110 | read_vec_element(s, tcg_res, rm, (i & ~1) + part, size); | |
7111 | } else { | |
7112 | read_vec_element(s, tcg_res, rn, (i & ~1) + part, size); | |
7113 | } | |
7114 | break; | |
7115 | case 3: /* ZIP1/2 */ | |
7116 | { | |
7117 | int base = part * elements / 2; | |
7118 | if (i & 1) { | |
7119 | read_vec_element(s, tcg_res, rm, base + (i >> 1), size); | |
7120 | } else { | |
7121 | read_vec_element(s, tcg_res, rn, base + (i >> 1), size); | |
7122 | } | |
7123 | break; | |
7124 | } | |
7125 | default: | |
7126 | g_assert_not_reached(); | |
7127 | } | |
7128 | ||
7129 | ofs = i * esize; | |
7130 | if (ofs < 64) { | |
7131 | tcg_gen_shli_i64(tcg_res, tcg_res, ofs); | |
7132 | tcg_gen_or_i64(tcg_resl, tcg_resl, tcg_res); | |
7133 | } else { | |
7134 | tcg_gen_shli_i64(tcg_res, tcg_res, ofs - 64); | |
7135 | tcg_gen_or_i64(tcg_resh, tcg_resh, tcg_res); | |
7136 | } | |
7137 | } | |
7138 | ||
7139 | tcg_temp_free_i64(tcg_res); | |
7140 | ||
7141 | write_vec_element(s, tcg_resl, rd, 0, MO_64); | |
7142 | tcg_temp_free_i64(tcg_resl); | |
e1f77859 RH |
7143 | |
7144 | if (is_q) { | |
7145 | write_vec_element(s, tcg_resh, rd, 1, MO_64); | |
7146 | tcg_temp_free_i64(tcg_resh); | |
7147 | } | |
7148 | clear_vec_high(s, is_q, rd); | |
384b26fb AB |
7149 | } |
7150 | ||
807cdd50 AB |
7151 | /* |
7152 | * do_reduction_op helper | |
7153 | * | |
7154 | * This mirrors the Reduce() pseudocode in the ARM ARM. It is | |
7155 | * important for correct NaN propagation that we do these | |
7156 | * operations in exactly the order specified by the pseudocode. | |
7157 | * | |
7158 | * This is a recursive function, TCG temps should be freed by the | |
7159 | * calling function once it is done with the values. | |
7160 | */ | |
7161 | static TCGv_i32 do_reduction_op(DisasContext *s, int fpopcode, int rn, | |
7162 | int esize, int size, int vmap, TCGv_ptr fpst) | |
7163 | { | |
7164 | if (esize == size) { | |
7165 | int element; | |
14776ab5 | 7166 | MemOp msize = esize == 16 ? MO_16 : MO_32; |
807cdd50 AB |
7167 | TCGv_i32 tcg_elem; |
7168 | ||
7169 | /* We should have one register left here */ | |
7170 | assert(ctpop8(vmap) == 1); | |
7171 | element = ctz32(vmap); | |
7172 | assert(element < 8); | |
7173 | ||
7174 | tcg_elem = tcg_temp_new_i32(); | |
7175 | read_vec_element_i32(s, tcg_elem, rn, element, msize); | |
7176 | return tcg_elem; | |
4a0ff1ce | 7177 | } else { |
807cdd50 AB |
7178 | int bits = size / 2; |
7179 | int shift = ctpop8(vmap) / 2; | |
7180 | int vmap_lo = (vmap >> shift) & vmap; | |
7181 | int vmap_hi = (vmap & ~vmap_lo); | |
7182 | TCGv_i32 tcg_hi, tcg_lo, tcg_res; | |
7183 | ||
7184 | tcg_hi = do_reduction_op(s, fpopcode, rn, esize, bits, vmap_hi, fpst); | |
7185 | tcg_lo = do_reduction_op(s, fpopcode, rn, esize, bits, vmap_lo, fpst); | |
7186 | tcg_res = tcg_temp_new_i32(); | |
7187 | ||
7188 | switch (fpopcode) { | |
7189 | case 0x0c: /* fmaxnmv half-precision */ | |
7190 | gen_helper_advsimd_maxnumh(tcg_res, tcg_lo, tcg_hi, fpst); | |
7191 | break; | |
7192 | case 0x0f: /* fmaxv half-precision */ | |
7193 | gen_helper_advsimd_maxh(tcg_res, tcg_lo, tcg_hi, fpst); | |
7194 | break; | |
7195 | case 0x1c: /* fminnmv half-precision */ | |
7196 | gen_helper_advsimd_minnumh(tcg_res, tcg_lo, tcg_hi, fpst); | |
7197 | break; | |
7198 | case 0x1f: /* fminv half-precision */ | |
7199 | gen_helper_advsimd_minh(tcg_res, tcg_lo, tcg_hi, fpst); | |
7200 | break; | |
7201 | case 0x2c: /* fmaxnmv */ | |
7202 | gen_helper_vfp_maxnums(tcg_res, tcg_lo, tcg_hi, fpst); | |
7203 | break; | |
7204 | case 0x2f: /* fmaxv */ | |
7205 | gen_helper_vfp_maxs(tcg_res, tcg_lo, tcg_hi, fpst); | |
7206 | break; | |
7207 | case 0x3c: /* fminnmv */ | |
7208 | gen_helper_vfp_minnums(tcg_res, tcg_lo, tcg_hi, fpst); | |
7209 | break; | |
7210 | case 0x3f: /* fminv */ | |
7211 | gen_helper_vfp_mins(tcg_res, tcg_lo, tcg_hi, fpst); | |
7212 | break; | |
7213 | default: | |
7214 | g_assert_not_reached(); | |
4a0ff1ce | 7215 | } |
807cdd50 AB |
7216 | |
7217 | tcg_temp_free_i32(tcg_hi); | |
7218 | tcg_temp_free_i32(tcg_lo); | |
7219 | return tcg_res; | |
4a0ff1ce MM |
7220 | } |
7221 | } | |
7222 | ||
4ce31af4 | 7223 | /* AdvSIMD across lanes |
384b26fb AB |
7224 | * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0 |
7225 | * +---+---+---+-----------+------+-----------+--------+-----+------+------+ | |
7226 | * | 0 | Q | U | 0 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd | | |
7227 | * +---+---+---+-----------+------+-----------+--------+-----+------+------+ | |
7228 | */ | |
7229 | static void disas_simd_across_lanes(DisasContext *s, uint32_t insn) | |
7230 | { | |
4a0ff1ce MM |
7231 | int rd = extract32(insn, 0, 5); |
7232 | int rn = extract32(insn, 5, 5); | |
7233 | int size = extract32(insn, 22, 2); | |
7234 | int opcode = extract32(insn, 12, 5); | |
7235 | bool is_q = extract32(insn, 30, 1); | |
7236 | bool is_u = extract32(insn, 29, 1); | |
7237 | bool is_fp = false; | |
7238 | bool is_min = false; | |
7239 | int esize; | |
7240 | int elements; | |
7241 | int i; | |
7242 | TCGv_i64 tcg_res, tcg_elt; | |
7243 | ||
7244 | switch (opcode) { | |
7245 | case 0x1b: /* ADDV */ | |
7246 | if (is_u) { | |
7247 | unallocated_encoding(s); | |
7248 | return; | |
7249 | } | |
7250 | /* fall through */ | |
7251 | case 0x3: /* SADDLV, UADDLV */ | |
7252 | case 0xa: /* SMAXV, UMAXV */ | |
7253 | case 0x1a: /* SMINV, UMINV */ | |
7254 | if (size == 3 || (size == 2 && !is_q)) { | |
7255 | unallocated_encoding(s); | |
7256 | return; | |
7257 | } | |
7258 | break; | |
7259 | case 0xc: /* FMAXNMV, FMINNMV */ | |
7260 | case 0xf: /* FMAXV, FMINV */ | |
807cdd50 AB |
7261 | /* Bit 1 of size field encodes min vs max and the actual size |
7262 | * depends on the encoding of the U bit. If not set (and FP16 | |
7263 | * enabled) then we do half-precision float instead of single | |
7264 | * precision. | |
4a0ff1ce MM |
7265 | */ |
7266 | is_min = extract32(size, 1, 1); | |
7267 | is_fp = true; | |
5763190f | 7268 | if (!is_u && dc_isar_feature(aa64_fp16, s)) { |
807cdd50 AB |
7269 | size = 1; |
7270 | } else if (!is_u || !is_q || extract32(size, 0, 1)) { | |
7271 | unallocated_encoding(s); | |
7272 | return; | |
7273 | } else { | |
7274 | size = 2; | |
7275 | } | |
4a0ff1ce MM |
7276 | break; |
7277 | default: | |
7278 | unallocated_encoding(s); | |
7279 | return; | |
7280 | } | |
7281 | ||
8c6afa6a PM |
7282 | if (!fp_access_check(s)) { |
7283 | return; | |
7284 | } | |
7285 | ||
4a0ff1ce MM |
7286 | esize = 8 << size; |
7287 | elements = (is_q ? 128 : 64) / esize; | |
7288 | ||
7289 | tcg_res = tcg_temp_new_i64(); | |
7290 | tcg_elt = tcg_temp_new_i64(); | |
7291 | ||
7292 | /* These instructions operate across all lanes of a vector | |
7293 | * to produce a single result. We can guarantee that a 64 | |
7294 | * bit intermediate is sufficient: | |
7295 | * + for [US]ADDLV the maximum element size is 32 bits, and | |
7296 | * the result type is 64 bits | |
7297 | * + for FMAX*V, FMIN*V, ADDV the intermediate type is the | |
7298 | * same as the element size, which is 32 bits at most | |
7299 | * For the integer operations we can choose to work at 64 | |
7300 | * or 32 bits and truncate at the end; for simplicity | |
7301 | * we use 64 bits always. The floating point | |
7302 | * ops do require 32 bit intermediates, though. | |
7303 | */ | |
7304 | if (!is_fp) { | |
7305 | read_vec_element(s, tcg_res, rn, 0, size | (is_u ? 0 : MO_SIGN)); | |
7306 | ||
7307 | for (i = 1; i < elements; i++) { | |
7308 | read_vec_element(s, tcg_elt, rn, i, size | (is_u ? 0 : MO_SIGN)); | |
7309 | ||
7310 | switch (opcode) { | |
7311 | case 0x03: /* SADDLV / UADDLV */ | |
7312 | case 0x1b: /* ADDV */ | |
7313 | tcg_gen_add_i64(tcg_res, tcg_res, tcg_elt); | |
7314 | break; | |
7315 | case 0x0a: /* SMAXV / UMAXV */ | |
ecb8ab8d RH |
7316 | if (is_u) { |
7317 | tcg_gen_umax_i64(tcg_res, tcg_res, tcg_elt); | |
7318 | } else { | |
7319 | tcg_gen_smax_i64(tcg_res, tcg_res, tcg_elt); | |
7320 | } | |
4a0ff1ce MM |
7321 | break; |
7322 | case 0x1a: /* SMINV / UMINV */ | |
ecb8ab8d RH |
7323 | if (is_u) { |
7324 | tcg_gen_umin_i64(tcg_res, tcg_res, tcg_elt); | |
7325 | } else { | |
7326 | tcg_gen_smin_i64(tcg_res, tcg_res, tcg_elt); | |
7327 | } | |
4a0ff1ce MM |
7328 | break; |
7329 | default: | |
7330 | g_assert_not_reached(); | |
7331 | } | |
7332 | ||
7333 | } | |
7334 | } else { | |
807cdd50 AB |
7335 | /* Floating point vector reduction ops which work across 32 |
7336 | * bit (single) or 16 bit (half-precision) intermediates. | |
4a0ff1ce MM |
7337 | * Note that correct NaN propagation requires that we do these |
7338 | * operations in exactly the order specified by the pseudocode. | |
7339 | */ | |
807cdd50 AB |
7340 | TCGv_ptr fpst = get_fpstatus_ptr(size == MO_16); |
7341 | int fpopcode = opcode | is_min << 4 | is_u << 5; | |
7342 | int vmap = (1 << elements) - 1; | |
7343 | TCGv_i32 tcg_res32 = do_reduction_op(s, fpopcode, rn, esize, | |
7344 | (is_q ? 128 : 64), vmap, fpst); | |
7345 | tcg_gen_extu_i32_i64(tcg_res, tcg_res32); | |
7346 | tcg_temp_free_i32(tcg_res32); | |
4a0ff1ce MM |
7347 | tcg_temp_free_ptr(fpst); |
7348 | } | |
7349 | ||
7350 | tcg_temp_free_i64(tcg_elt); | |
7351 | ||
7352 | /* Now truncate the result to the width required for the final output */ | |
7353 | if (opcode == 0x03) { | |
7354 | /* SADDLV, UADDLV: result is 2*esize */ | |
7355 | size++; | |
7356 | } | |
7357 | ||
7358 | switch (size) { | |
7359 | case 0: | |
7360 | tcg_gen_ext8u_i64(tcg_res, tcg_res); | |
7361 | break; | |
7362 | case 1: | |
7363 | tcg_gen_ext16u_i64(tcg_res, tcg_res); | |
7364 | break; | |
7365 | case 2: | |
7366 | tcg_gen_ext32u_i64(tcg_res, tcg_res); | |
7367 | break; | |
7368 | case 3: | |
7369 | break; | |
7370 | default: | |
7371 | g_assert_not_reached(); | |
7372 | } | |
7373 | ||
7374 | write_fp_dreg(s, rd, tcg_res); | |
7375 | tcg_temp_free_i64(tcg_res); | |
384b26fb AB |
7376 | } |
7377 | ||
4ce31af4 | 7378 | /* DUP (Element, Vector) |
67bb9389 AB |
7379 | * |
7380 | * 31 30 29 21 20 16 15 10 9 5 4 0 | |
7381 | * +---+---+-------------------+--------+-------------+------+------+ | |
7382 | * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd | | |
7383 | * +---+---+-------------------+--------+-------------+------+------+ | |
7384 | * | |
7385 | * size: encoded in imm5 (see ARM ARM LowestSetBit()) | |
7386 | */ | |
7387 | static void handle_simd_dupe(DisasContext *s, int is_q, int rd, int rn, | |
7388 | int imm5) | |
7389 | { | |
7390 | int size = ctz32(imm5); | |
550a0489 | 7391 | int index; |
67bb9389 AB |
7392 | |
7393 | if (size > 3 || (size == 3 && !is_q)) { | |
7394 | unallocated_encoding(s); | |
7395 | return; | |
7396 | } | |
7397 | ||
8c6afa6a PM |
7398 | if (!fp_access_check(s)) { |
7399 | return; | |
7400 | } | |
7401 | ||
550a0489 | 7402 | index = imm5 >> (size + 1); |
861a1ded RH |
7403 | tcg_gen_gvec_dup_mem(size, vec_full_reg_offset(s, rd), |
7404 | vec_reg_offset(s, rn, index, size), | |
7405 | is_q ? 16 : 8, vec_full_reg_size(s)); | |
67bb9389 AB |
7406 | } |
7407 | ||
4ce31af4 | 7408 | /* DUP (element, scalar) |
360a6f2d PM |
7409 | * 31 21 20 16 15 10 9 5 4 0 |
7410 | * +-----------------------+--------+-------------+------+------+ | |
7411 | * | 0 1 0 1 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd | | |
7412 | * +-----------------------+--------+-------------+------+------+ | |
7413 | */ | |
7414 | static void handle_simd_dupes(DisasContext *s, int rd, int rn, | |
7415 | int imm5) | |
7416 | { | |
7417 | int size = ctz32(imm5); | |
7418 | int index; | |
7419 | TCGv_i64 tmp; | |
7420 | ||
7421 | if (size > 3) { | |
7422 | unallocated_encoding(s); | |
7423 | return; | |
7424 | } | |
7425 | ||
8c6afa6a PM |
7426 | if (!fp_access_check(s)) { |
7427 | return; | |
7428 | } | |
7429 | ||
360a6f2d PM |
7430 | index = imm5 >> (size + 1); |
7431 | ||
7432 | /* This instruction just extracts the specified element and | |
7433 | * zero-extends it into the bottom of the destination register. | |
7434 | */ | |
7435 | tmp = tcg_temp_new_i64(); | |
7436 | read_vec_element(s, tmp, rn, index, size); | |
7437 | write_fp_dreg(s, rd, tmp); | |
7438 | tcg_temp_free_i64(tmp); | |
7439 | } | |
7440 | ||
4ce31af4 | 7441 | /* DUP (General) |
67bb9389 AB |
7442 | * |
7443 | * 31 30 29 21 20 16 15 10 9 5 4 0 | |
7444 | * +---+---+-------------------+--------+-------------+------+------+ | |
7445 | * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 1 1 | Rn | Rd | | |
7446 | * +---+---+-------------------+--------+-------------+------+------+ | |
7447 | * | |
7448 | * size: encoded in imm5 (see ARM ARM LowestSetBit()) | |
7449 | */ | |
7450 | static void handle_simd_dupg(DisasContext *s, int is_q, int rd, int rn, | |
7451 | int imm5) | |
7452 | { | |
7453 | int size = ctz32(imm5); | |
861a1ded | 7454 | uint32_t dofs, oprsz, maxsz; |
67bb9389 AB |
7455 | |
7456 | if (size > 3 || ((size == 3) && !is_q)) { | |
7457 | unallocated_encoding(s); | |
7458 | return; | |
7459 | } | |
8c6afa6a PM |
7460 | |
7461 | if (!fp_access_check(s)) { | |
7462 | return; | |
7463 | } | |
7464 | ||
861a1ded RH |
7465 | dofs = vec_full_reg_offset(s, rd); |
7466 | oprsz = is_q ? 16 : 8; | |
7467 | maxsz = vec_full_reg_size(s); | |
7468 | ||
7469 | tcg_gen_gvec_dup_i64(size, dofs, oprsz, maxsz, cpu_reg(s, rn)); | |
67bb9389 AB |
7470 | } |
7471 | ||
4ce31af4 | 7472 | /* INS (Element) |
67bb9389 AB |
7473 | * |
7474 | * 31 21 20 16 15 14 11 10 9 5 4 0 | |
7475 | * +-----------------------+--------+------------+---+------+------+ | |
7476 | * | 0 1 1 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd | | |
7477 | * +-----------------------+--------+------------+---+------+------+ | |
7478 | * | |
7479 | * size: encoded in imm5 (see ARM ARM LowestSetBit()) | |
7480 | * index: encoded in imm5<4:size+1> | |
7481 | */ | |
7482 | static void handle_simd_inse(DisasContext *s, int rd, int rn, | |
7483 | int imm4, int imm5) | |
7484 | { | |
7485 | int size = ctz32(imm5); | |
7486 | int src_index, dst_index; | |
7487 | TCGv_i64 tmp; | |
7488 | ||
7489 | if (size > 3) { | |
7490 | unallocated_encoding(s); | |
7491 | return; | |
7492 | } | |
8c6afa6a PM |
7493 | |
7494 | if (!fp_access_check(s)) { | |
7495 | return; | |
7496 | } | |
7497 | ||
67bb9389 AB |
7498 | dst_index = extract32(imm5, 1+size, 5); |
7499 | src_index = extract32(imm4, size, 4); | |
7500 | ||
7501 | tmp = tcg_temp_new_i64(); | |
7502 | ||
7503 | read_vec_element(s, tmp, rn, src_index, size); | |
7504 | write_vec_element(s, tmp, rd, dst_index, size); | |
7505 | ||
7506 | tcg_temp_free_i64(tmp); | |
528dc354 RH |
7507 | |
7508 | /* INS is considered a 128-bit write for SVE. */ | |
7509 | clear_vec_high(s, true, rd); | |
67bb9389 AB |
7510 | } |
7511 | ||
7512 | ||
4ce31af4 | 7513 | /* INS (General) |
67bb9389 AB |
7514 | * |
7515 | * 31 21 20 16 15 10 9 5 4 0 | |
7516 | * +-----------------------+--------+-------------+------+------+ | |
7517 | * | 0 1 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 1 1 1 | Rn | Rd | | |
7518 | * +-----------------------+--------+-------------+------+------+ | |
7519 | * | |
7520 | * size: encoded in imm5 (see ARM ARM LowestSetBit()) | |
7521 | * index: encoded in imm5<4:size+1> | |
7522 | */ | |
7523 | static void handle_simd_insg(DisasContext *s, int rd, int rn, int imm5) | |
7524 | { | |
7525 | int size = ctz32(imm5); | |
7526 | int idx; | |
7527 | ||
7528 | if (size > 3) { | |
7529 | unallocated_encoding(s); | |
7530 | return; | |
7531 | } | |
7532 | ||
8c6afa6a PM |
7533 | if (!fp_access_check(s)) { |
7534 | return; | |
7535 | } | |
7536 | ||
67bb9389 AB |
7537 | idx = extract32(imm5, 1 + size, 4 - size); |
7538 | write_vec_element(s, cpu_reg(s, rn), rd, idx, size); | |
528dc354 RH |
7539 | |
7540 | /* INS is considered a 128-bit write for SVE. */ | |
7541 | clear_vec_high(s, true, rd); | |
67bb9389 AB |
7542 | } |
7543 | ||
7544 | /* | |
4ce31af4 PM |
7545 | * UMOV (General) |
7546 | * SMOV (General) | |
67bb9389 AB |
7547 | * |
7548 | * 31 30 29 21 20 16 15 12 10 9 5 4 0 | |
7549 | * +---+---+-------------------+--------+-------------+------+------+ | |
7550 | * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 1 U 1 1 | Rn | Rd | | |
7551 | * +---+---+-------------------+--------+-------------+------+------+ | |
7552 | * | |
7553 | * U: unsigned when set | |
7554 | * size: encoded in imm5 (see ARM ARM LowestSetBit()) | |
7555 | */ | |
7556 | static void handle_simd_umov_smov(DisasContext *s, int is_q, int is_signed, | |
7557 | int rn, int rd, int imm5) | |
7558 | { | |
7559 | int size = ctz32(imm5); | |
7560 | int element; | |
7561 | TCGv_i64 tcg_rd; | |
7562 | ||
7563 | /* Check for UnallocatedEncodings */ | |
7564 | if (is_signed) { | |
7565 | if (size > 2 || (size == 2 && !is_q)) { | |
7566 | unallocated_encoding(s); | |
7567 | return; | |
7568 | } | |
7569 | } else { | |
7570 | if (size > 3 | |
7571 | || (size < 3 && is_q) | |
7572 | || (size == 3 && !is_q)) { | |
7573 | unallocated_encoding(s); | |
7574 | return; | |
7575 | } | |
7576 | } | |
8c6afa6a PM |
7577 | |
7578 | if (!fp_access_check(s)) { | |
7579 | return; | |
7580 | } | |
7581 | ||
67bb9389 AB |
7582 | element = extract32(imm5, 1+size, 4); |
7583 | ||
7584 | tcg_rd = cpu_reg(s, rd); | |
7585 | read_vec_element(s, tcg_rd, rn, element, size | (is_signed ? MO_SIGN : 0)); | |
7586 | if (is_signed && !is_q) { | |
7587 | tcg_gen_ext32u_i64(tcg_rd, tcg_rd); | |
7588 | } | |
7589 | } | |
7590 | ||
4ce31af4 | 7591 | /* AdvSIMD copy |
384b26fb AB |
7592 | * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0 |
7593 | * +---+---+----+-----------------+------+---+------+---+------+------+ | |
7594 | * | 0 | Q | op | 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd | | |
7595 | * +---+---+----+-----------------+------+---+------+---+------+------+ | |
7596 | */ | |
7597 | static void disas_simd_copy(DisasContext *s, uint32_t insn) | |
7598 | { | |
67bb9389 AB |
7599 | int rd = extract32(insn, 0, 5); |
7600 | int rn = extract32(insn, 5, 5); | |
7601 | int imm4 = extract32(insn, 11, 4); | |
7602 | int op = extract32(insn, 29, 1); | |
7603 | int is_q = extract32(insn, 30, 1); | |
7604 | int imm5 = extract32(insn, 16, 5); | |
7605 | ||
7606 | if (op) { | |
7607 | if (is_q) { | |
7608 | /* INS (element) */ | |
7609 | handle_simd_inse(s, rd, rn, imm4, imm5); | |
7610 | } else { | |
7611 | unallocated_encoding(s); | |
7612 | } | |
7613 | } else { | |
7614 | switch (imm4) { | |
7615 | case 0: | |
7616 | /* DUP (element - vector) */ | |
7617 | handle_simd_dupe(s, is_q, rd, rn, imm5); | |
7618 | break; | |
7619 | case 1: | |
7620 | /* DUP (general) */ | |
7621 | handle_simd_dupg(s, is_q, rd, rn, imm5); | |
7622 | break; | |
7623 | case 3: | |
7624 | if (is_q) { | |
7625 | /* INS (general) */ | |
7626 | handle_simd_insg(s, rd, rn, imm5); | |
7627 | } else { | |
7628 | unallocated_encoding(s); | |
7629 | } | |
7630 | break; | |
7631 | case 5: | |
7632 | case 7: | |
7633 | /* UMOV/SMOV (is_q indicates 32/64; imm4 indicates signedness) */ | |
7634 | handle_simd_umov_smov(s, is_q, (imm4 == 5), rn, rd, imm5); | |
7635 | break; | |
7636 | default: | |
7637 | unallocated_encoding(s); | |
7638 | break; | |
7639 | } | |
7640 | } | |
384b26fb AB |
7641 | } |
7642 | ||
4ce31af4 | 7643 | /* AdvSIMD modified immediate |
384b26fb AB |
7644 | * 31 30 29 28 19 18 16 15 12 11 10 9 5 4 0 |
7645 | * +---+---+----+---------------------+-----+-------+----+---+-------+------+ | |
7646 | * | 0 | Q | op | 0 1 1 1 1 0 0 0 0 0 | abc | cmode | o2 | 1 | defgh | Rd | | |
7647 | * +---+---+----+---------------------+-----+-------+----+---+-------+------+ | |
f3f8c4f4 AB |
7648 | * |
7649 | * There are a number of operations that can be carried out here: | |
7650 | * MOVI - move (shifted) imm into register | |
7651 | * MVNI - move inverted (shifted) imm into register | |
7652 | * ORR - bitwise OR of (shifted) imm with register | |
7653 | * BIC - bitwise clear of (shifted) imm with register | |
70b4e6a4 AB |
7654 | * With ARMv8.2 we also have: |
7655 | * FMOV half-precision | |
384b26fb AB |
7656 | */ |
7657 | static void disas_simd_mod_imm(DisasContext *s, uint32_t insn) | |
7658 | { | |
f3f8c4f4 AB |
7659 | int rd = extract32(insn, 0, 5); |
7660 | int cmode = extract32(insn, 12, 4); | |
7661 | int cmode_3_1 = extract32(cmode, 1, 3); | |
7662 | int cmode_0 = extract32(cmode, 0, 1); | |
7663 | int o2 = extract32(insn, 11, 1); | |
7664 | uint64_t abcdefgh = extract32(insn, 5, 5) | (extract32(insn, 16, 3) << 5); | |
7665 | bool is_neg = extract32(insn, 29, 1); | |
7666 | bool is_q = extract32(insn, 30, 1); | |
7667 | uint64_t imm = 0; | |
f3f8c4f4 AB |
7668 | |
7669 | if (o2 != 0 || ((cmode == 0xf) && is_neg && !is_q)) { | |
70b4e6a4 | 7670 | /* Check for FMOV (vector, immediate) - half-precision */ |
5763190f | 7671 | if (!(dc_isar_feature(aa64_fp16, s) && o2 && cmode == 0xf)) { |
70b4e6a4 AB |
7672 | unallocated_encoding(s); |
7673 | return; | |
7674 | } | |
f3f8c4f4 AB |
7675 | } |
7676 | ||
8c6afa6a PM |
7677 | if (!fp_access_check(s)) { |
7678 | return; | |
7679 | } | |
7680 | ||
f3f8c4f4 AB |
7681 | /* See AdvSIMDExpandImm() in ARM ARM */ |
7682 | switch (cmode_3_1) { | |
7683 | case 0: /* Replicate(Zeros(24):imm8, 2) */ | |
7684 | case 1: /* Replicate(Zeros(16):imm8:Zeros(8), 2) */ | |
7685 | case 2: /* Replicate(Zeros(8):imm8:Zeros(16), 2) */ | |
7686 | case 3: /* Replicate(imm8:Zeros(24), 2) */ | |
7687 | { | |
7688 | int shift = cmode_3_1 * 8; | |
7689 | imm = bitfield_replicate(abcdefgh << shift, 32); | |
7690 | break; | |
7691 | } | |
7692 | case 4: /* Replicate(Zeros(8):imm8, 4) */ | |
7693 | case 5: /* Replicate(imm8:Zeros(8), 4) */ | |
7694 | { | |
7695 | int shift = (cmode_3_1 & 0x1) * 8; | |
7696 | imm = bitfield_replicate(abcdefgh << shift, 16); | |
7697 | break; | |
7698 | } | |
7699 | case 6: | |
7700 | if (cmode_0) { | |
7701 | /* Replicate(Zeros(8):imm8:Ones(16), 2) */ | |
7702 | imm = (abcdefgh << 16) | 0xffff; | |
7703 | } else { | |
7704 | /* Replicate(Zeros(16):imm8:Ones(8), 2) */ | |
7705 | imm = (abcdefgh << 8) | 0xff; | |
7706 | } | |
7707 | imm = bitfield_replicate(imm, 32); | |
7708 | break; | |
7709 | case 7: | |
7710 | if (!cmode_0 && !is_neg) { | |
7711 | imm = bitfield_replicate(abcdefgh, 8); | |
7712 | } else if (!cmode_0 && is_neg) { | |
7713 | int i; | |
7714 | imm = 0; | |
7715 | for (i = 0; i < 8; i++) { | |
7716 | if ((abcdefgh) & (1 << i)) { | |
7717 | imm |= 0xffULL << (i * 8); | |
7718 | } | |
7719 | } | |
7720 | } else if (cmode_0) { | |
7721 | if (is_neg) { | |
7722 | imm = (abcdefgh & 0x3f) << 48; | |
7723 | if (abcdefgh & 0x80) { | |
7724 | imm |= 0x8000000000000000ULL; | |
7725 | } | |
7726 | if (abcdefgh & 0x40) { | |
7727 | imm |= 0x3fc0000000000000ULL; | |
7728 | } else { | |
7729 | imm |= 0x4000000000000000ULL; | |
7730 | } | |
7731 | } else { | |
70b4e6a4 AB |
7732 | if (o2) { |
7733 | /* FMOV (vector, immediate) - half-precision */ | |
7734 | imm = vfp_expand_imm(MO_16, abcdefgh); | |
7735 | /* now duplicate across the lanes */ | |
7736 | imm = bitfield_replicate(imm, 16); | |
f3f8c4f4 | 7737 | } else { |
70b4e6a4 AB |
7738 | imm = (abcdefgh & 0x3f) << 19; |
7739 | if (abcdefgh & 0x80) { | |
7740 | imm |= 0x80000000; | |
7741 | } | |
7742 | if (abcdefgh & 0x40) { | |
7743 | imm |= 0x3e000000; | |
7744 | } else { | |
7745 | imm |= 0x40000000; | |
7746 | } | |
7747 | imm |= (imm << 32); | |
f3f8c4f4 | 7748 | } |
f3f8c4f4 AB |
7749 | } |
7750 | } | |
7751 | break; | |
70b4e6a4 AB |
7752 | default: |
7753 | fprintf(stderr, "%s: cmode_3_1: %x\n", __func__, cmode_3_1); | |
7754 | g_assert_not_reached(); | |
f3f8c4f4 AB |
7755 | } |
7756 | ||
7757 | if (cmode_3_1 != 7 && is_neg) { | |
7758 | imm = ~imm; | |
7759 | } | |
7760 | ||
861a1ded RH |
7761 | if (!((cmode & 0x9) == 0x1 || (cmode & 0xd) == 0x9)) { |
7762 | /* MOVI or MVNI, with MVNI negation handled above. */ | |
8711e71f RH |
7763 | tcg_gen_gvec_dup_imm(MO_64, vec_full_reg_offset(s, rd), is_q ? 16 : 8, |
7764 | vec_full_reg_size(s), imm); | |
861a1ded | 7765 | } else { |
064e265d RH |
7766 | /* ORR or BIC, with BIC negation to AND handled above. */ |
7767 | if (is_neg) { | |
7768 | gen_gvec_fn2i(s, is_q, rd, rd, imm, tcg_gen_gvec_andi, MO_64); | |
7769 | } else { | |
7770 | gen_gvec_fn2i(s, is_q, rd, rd, imm, tcg_gen_gvec_ori, MO_64); | |
f3f8c4f4 | 7771 | } |
861a1ded | 7772 | } |
384b26fb AB |
7773 | } |
7774 | ||
4ce31af4 | 7775 | /* AdvSIMD scalar copy |
384b26fb AB |
7776 | * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0 |
7777 | * +-----+----+-----------------+------+---+------+---+------+------+ | |
7778 | * | 0 1 | op | 1 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd | | |
7779 | * +-----+----+-----------------+------+---+------+---+------+------+ | |
7780 | */ | |
7781 | static void disas_simd_scalar_copy(DisasContext *s, uint32_t insn) | |
7782 | { | |
360a6f2d PM |
7783 | int rd = extract32(insn, 0, 5); |
7784 | int rn = extract32(insn, 5, 5); | |
7785 | int imm4 = extract32(insn, 11, 4); | |
7786 | int imm5 = extract32(insn, 16, 5); | |
7787 | int op = extract32(insn, 29, 1); | |
7788 | ||
7789 | if (op != 0 || imm4 != 0) { | |
7790 | unallocated_encoding(s); | |
7791 | return; | |
7792 | } | |
7793 | ||
7794 | /* DUP (element, scalar) */ | |
7795 | handle_simd_dupes(s, rd, rn, imm5); | |
384b26fb AB |
7796 | } |
7797 | ||
4ce31af4 | 7798 | /* AdvSIMD scalar pairwise |
384b26fb AB |
7799 | * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0 |
7800 | * +-----+---+-----------+------+-----------+--------+-----+------+------+ | |
7801 | * | 0 1 | U | 1 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd | | |
7802 | * +-----+---+-----------+------+-----------+--------+-----+------+------+ | |
7803 | */ | |
7804 | static void disas_simd_scalar_pairwise(DisasContext *s, uint32_t insn) | |
7805 | { | |
3720a7ea PM |
7806 | int u = extract32(insn, 29, 1); |
7807 | int size = extract32(insn, 22, 2); | |
7808 | int opcode = extract32(insn, 12, 5); | |
7809 | int rn = extract32(insn, 5, 5); | |
7810 | int rd = extract32(insn, 0, 5); | |
7811 | TCGv_ptr fpst; | |
7812 | ||
7813 | /* For some ops (the FP ones), size[1] is part of the encoding. | |
7814 | * For ADDP strictly it is not but size[1] is always 1 for valid | |
7815 | * encodings. | |
7816 | */ | |
7817 | opcode |= (extract32(size, 1, 1) << 5); | |
7818 | ||
7819 | switch (opcode) { | |
7820 | case 0x3b: /* ADDP */ | |
7821 | if (u || size != 3) { | |
7822 | unallocated_encoding(s); | |
7823 | return; | |
7824 | } | |
8c6afa6a PM |
7825 | if (!fp_access_check(s)) { |
7826 | return; | |
7827 | } | |
7828 | ||
f764718d | 7829 | fpst = NULL; |
3720a7ea PM |
7830 | break; |
7831 | case 0xc: /* FMAXNMP */ | |
7832 | case 0xd: /* FADDP */ | |
7833 | case 0xf: /* FMAXP */ | |
7834 | case 0x2c: /* FMINNMP */ | |
7835 | case 0x2f: /* FMINP */ | |
5c36d895 | 7836 | /* FP op, size[0] is 32 or 64 bit*/ |
3720a7ea | 7837 | if (!u) { |
5763190f | 7838 | if (!dc_isar_feature(aa64_fp16, s)) { |
5c36d895 AB |
7839 | unallocated_encoding(s); |
7840 | return; | |
7841 | } else { | |
7842 | size = MO_16; | |
7843 | } | |
7844 | } else { | |
7845 | size = extract32(size, 0, 1) ? MO_64 : MO_32; | |
3720a7ea | 7846 | } |
5c36d895 | 7847 | |
8c6afa6a PM |
7848 | if (!fp_access_check(s)) { |
7849 | return; | |
7850 | } | |
7851 | ||
5c36d895 | 7852 | fpst = get_fpstatus_ptr(size == MO_16); |
3720a7ea PM |
7853 | break; |
7854 | default: | |
7855 | unallocated_encoding(s); | |
7856 | return; | |
7857 | } | |
7858 | ||
5c36d895 | 7859 | if (size == MO_64) { |
3720a7ea PM |
7860 | TCGv_i64 tcg_op1 = tcg_temp_new_i64(); |
7861 | TCGv_i64 tcg_op2 = tcg_temp_new_i64(); | |
7862 | TCGv_i64 tcg_res = tcg_temp_new_i64(); | |
7863 | ||
7864 | read_vec_element(s, tcg_op1, rn, 0, MO_64); | |
7865 | read_vec_element(s, tcg_op2, rn, 1, MO_64); | |
7866 | ||
7867 | switch (opcode) { | |
7868 | case 0x3b: /* ADDP */ | |
7869 | tcg_gen_add_i64(tcg_res, tcg_op1, tcg_op2); | |
7870 | break; | |
7871 | case 0xc: /* FMAXNMP */ | |
7872 | gen_helper_vfp_maxnumd(tcg_res, tcg_op1, tcg_op2, fpst); | |
7873 | break; | |
7874 | case 0xd: /* FADDP */ | |
7875 | gen_helper_vfp_addd(tcg_res, tcg_op1, tcg_op2, fpst); | |
7876 | break; | |
7877 | case 0xf: /* FMAXP */ | |
7878 | gen_helper_vfp_maxd(tcg_res, tcg_op1, tcg_op2, fpst); | |
7879 | break; | |
7880 | case 0x2c: /* FMINNMP */ | |
7881 | gen_helper_vfp_minnumd(tcg_res, tcg_op1, tcg_op2, fpst); | |
7882 | break; | |
7883 | case 0x2f: /* FMINP */ | |
7884 | gen_helper_vfp_mind(tcg_res, tcg_op1, tcg_op2, fpst); | |
7885 | break; | |
7886 | default: | |
7887 | g_assert_not_reached(); | |
7888 | } | |
7889 | ||
7890 | write_fp_dreg(s, rd, tcg_res); | |
7891 | ||
7892 | tcg_temp_free_i64(tcg_op1); | |
7893 | tcg_temp_free_i64(tcg_op2); | |
7894 | tcg_temp_free_i64(tcg_res); | |
7895 | } else { | |
7896 | TCGv_i32 tcg_op1 = tcg_temp_new_i32(); | |
7897 | TCGv_i32 tcg_op2 = tcg_temp_new_i32(); | |
7898 | TCGv_i32 tcg_res = tcg_temp_new_i32(); | |
7899 | ||
5c36d895 AB |
7900 | read_vec_element_i32(s, tcg_op1, rn, 0, size); |
7901 | read_vec_element_i32(s, tcg_op2, rn, 1, size); | |
3720a7ea | 7902 | |
5c36d895 AB |
7903 | if (size == MO_16) { |
7904 | switch (opcode) { | |
7905 | case 0xc: /* FMAXNMP */ | |
7906 | gen_helper_advsimd_maxnumh(tcg_res, tcg_op1, tcg_op2, fpst); | |
7907 | break; | |
7908 | case 0xd: /* FADDP */ | |
7909 | gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst); | |
7910 | break; | |
7911 | case 0xf: /* FMAXP */ | |
7912 | gen_helper_advsimd_maxh(tcg_res, tcg_op1, tcg_op2, fpst); | |
7913 | break; | |
7914 | case 0x2c: /* FMINNMP */ | |
7915 | gen_helper_advsimd_minnumh(tcg_res, tcg_op1, tcg_op2, fpst); | |
7916 | break; | |
7917 | case 0x2f: /* FMINP */ | |
7918 | gen_helper_advsimd_minh(tcg_res, tcg_op1, tcg_op2, fpst); | |
7919 | break; | |
7920 | default: | |
7921 | g_assert_not_reached(); | |
7922 | } | |
7923 | } else { | |
7924 | switch (opcode) { | |
7925 | case 0xc: /* FMAXNMP */ | |
7926 | gen_helper_vfp_maxnums(tcg_res, tcg_op1, tcg_op2, fpst); | |
7927 | break; | |
7928 | case 0xd: /* FADDP */ | |
7929 | gen_helper_vfp_adds(tcg_res, tcg_op1, tcg_op2, fpst); | |
7930 | break; | |
7931 | case 0xf: /* FMAXP */ | |
7932 | gen_helper_vfp_maxs(tcg_res, tcg_op1, tcg_op2, fpst); | |
7933 | break; | |
7934 | case 0x2c: /* FMINNMP */ | |
7935 | gen_helper_vfp_minnums(tcg_res, tcg_op1, tcg_op2, fpst); | |
7936 | break; | |
7937 | case 0x2f: /* FMINP */ | |
7938 | gen_helper_vfp_mins(tcg_res, tcg_op1, tcg_op2, fpst); | |
7939 | break; | |
7940 | default: | |
7941 | g_assert_not_reached(); | |
7942 | } | |
3720a7ea PM |
7943 | } |
7944 | ||
7945 | write_fp_sreg(s, rd, tcg_res); | |
7946 | ||
7947 | tcg_temp_free_i32(tcg_op1); | |
7948 | tcg_temp_free_i32(tcg_op2); | |
7949 | tcg_temp_free_i32(tcg_res); | |
7950 | } | |
7951 | ||
f764718d | 7952 | if (fpst) { |
3720a7ea PM |
7953 | tcg_temp_free_ptr(fpst); |
7954 | } | |
384b26fb AB |
7955 | } |
7956 | ||
4d1cef84 AB |
7957 | /* |
7958 | * Common SSHR[RA]/USHR[RA] - Shift right (optional rounding/accumulate) | |
7959 | * | |
7960 | * This code is handles the common shifting code and is used by both | |
7961 | * the vector and scalar code. | |
7962 | */ | |
7963 | static void handle_shri_with_rndacc(TCGv_i64 tcg_res, TCGv_i64 tcg_src, | |
7964 | TCGv_i64 tcg_rnd, bool accumulate, | |
7965 | bool is_u, int size, int shift) | |
7966 | { | |
7967 | bool extended_result = false; | |
f764718d | 7968 | bool round = tcg_rnd != NULL; |
4d1cef84 AB |
7969 | int ext_lshift = 0; |
7970 | TCGv_i64 tcg_src_hi; | |
7971 | ||
7972 | if (round && size == 3) { | |
7973 | extended_result = true; | |
7974 | ext_lshift = 64 - shift; | |
7975 | tcg_src_hi = tcg_temp_new_i64(); | |
7976 | } else if (shift == 64) { | |
7977 | if (!accumulate && is_u) { | |
7978 | /* result is zero */ | |
7979 | tcg_gen_movi_i64(tcg_res, 0); | |
7980 | return; | |
7981 | } | |
7982 | } | |
7983 | ||
7984 | /* Deal with the rounding step */ | |
7985 | if (round) { | |
7986 | if (extended_result) { | |
7987 | TCGv_i64 tcg_zero = tcg_const_i64(0); | |
7988 | if (!is_u) { | |
7989 | /* take care of sign extending tcg_res */ | |
7990 | tcg_gen_sari_i64(tcg_src_hi, tcg_src, 63); | |
7991 | tcg_gen_add2_i64(tcg_src, tcg_src_hi, | |
7992 | tcg_src, tcg_src_hi, | |
7993 | tcg_rnd, tcg_zero); | |
7994 | } else { | |
7995 | tcg_gen_add2_i64(tcg_src, tcg_src_hi, | |
7996 | tcg_src, tcg_zero, | |
7997 | tcg_rnd, tcg_zero); | |
7998 | } | |
7999 | tcg_temp_free_i64(tcg_zero); | |
8000 | } else { | |
8001 | tcg_gen_add_i64(tcg_src, tcg_src, tcg_rnd); | |
8002 | } | |
8003 | } | |
8004 | ||
8005 | /* Now do the shift right */ | |
8006 | if (round && extended_result) { | |
8007 | /* extended case, >64 bit precision required */ | |
8008 | if (ext_lshift == 0) { | |
8009 | /* special case, only high bits matter */ | |
8010 | tcg_gen_mov_i64(tcg_src, tcg_src_hi); | |
8011 | } else { | |
8012 | tcg_gen_shri_i64(tcg_src, tcg_src, shift); | |
8013 | tcg_gen_shli_i64(tcg_src_hi, tcg_src_hi, ext_lshift); | |
8014 | tcg_gen_or_i64(tcg_src, tcg_src, tcg_src_hi); | |
8015 | } | |
8016 | } else { | |
8017 | if (is_u) { | |
8018 | if (shift == 64) { | |
8019 | /* essentially shifting in 64 zeros */ | |
8020 | tcg_gen_movi_i64(tcg_src, 0); | |
8021 | } else { | |
8022 | tcg_gen_shri_i64(tcg_src, tcg_src, shift); | |
8023 | } | |
8024 | } else { | |
8025 | if (shift == 64) { | |
8026 | /* effectively extending the sign-bit */ | |
8027 | tcg_gen_sari_i64(tcg_src, tcg_src, 63); | |
8028 | } else { | |
8029 | tcg_gen_sari_i64(tcg_src, tcg_src, shift); | |
8030 | } | |
8031 | } | |
8032 | } | |
8033 | ||
8034 | if (accumulate) { | |
8035 | tcg_gen_add_i64(tcg_res, tcg_res, tcg_src); | |
8036 | } else { | |
8037 | tcg_gen_mov_i64(tcg_res, tcg_src); | |
8038 | } | |
8039 | ||
8040 | if (extended_result) { | |
8041 | tcg_temp_free_i64(tcg_src_hi); | |
8042 | } | |
8043 | } | |
8044 | ||
4d1cef84 AB |
8045 | /* SSHR[RA]/USHR[RA] - Scalar shift right (optional rounding/accumulate) */ |
8046 | static void handle_scalar_simd_shri(DisasContext *s, | |
8047 | bool is_u, int immh, int immb, | |
8048 | int opcode, int rn, int rd) | |
8049 | { | |
8050 | const int size = 3; | |
8051 | int immhb = immh << 3 | immb; | |
8052 | int shift = 2 * (8 << size) - immhb; | |
8053 | bool accumulate = false; | |
8054 | bool round = false; | |
37a706ad | 8055 | bool insert = false; |
4d1cef84 AB |
8056 | TCGv_i64 tcg_rn; |
8057 | TCGv_i64 tcg_rd; | |
8058 | TCGv_i64 tcg_round; | |
8059 | ||
8060 | if (!extract32(immh, 3, 1)) { | |
8061 | unallocated_encoding(s); | |
8062 | return; | |
8063 | } | |
8064 | ||
8c6afa6a PM |
8065 | if (!fp_access_check(s)) { |
8066 | return; | |
8067 | } | |
8068 | ||
4d1cef84 AB |
8069 | switch (opcode) { |
8070 | case 0x02: /* SSRA / USRA (accumulate) */ | |
8071 | accumulate = true; | |
8072 | break; | |
8073 | case 0x04: /* SRSHR / URSHR (rounding) */ | |
8074 | round = true; | |
8075 | break; | |
8076 | case 0x06: /* SRSRA / URSRA (accum + rounding) */ | |
8077 | accumulate = round = true; | |
8078 | break; | |
37a706ad PM |
8079 | case 0x08: /* SRI */ |
8080 | insert = true; | |
8081 | break; | |
4d1cef84 AB |
8082 | } |
8083 | ||
8084 | if (round) { | |
8085 | uint64_t round_const = 1ULL << (shift - 1); | |
8086 | tcg_round = tcg_const_i64(round_const); | |
8087 | } else { | |
f764718d | 8088 | tcg_round = NULL; |
4d1cef84 AB |
8089 | } |
8090 | ||
8091 | tcg_rn = read_fp_dreg(s, rn); | |
37a706ad | 8092 | tcg_rd = (accumulate || insert) ? read_fp_dreg(s, rd) : tcg_temp_new_i64(); |
4d1cef84 | 8093 | |
37a706ad | 8094 | if (insert) { |
cdb45a60 RH |
8095 | /* shift count same as element size is valid but does nothing; |
8096 | * special case to avoid potential shift by 64. | |
8097 | */ | |
8098 | int esize = 8 << size; | |
8099 | if (shift != esize) { | |
8100 | tcg_gen_shri_i64(tcg_rn, tcg_rn, shift); | |
8101 | tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_rn, 0, esize - shift); | |
8102 | } | |
37a706ad PM |
8103 | } else { |
8104 | handle_shri_with_rndacc(tcg_rd, tcg_rn, tcg_round, | |
8105 | accumulate, is_u, size, shift); | |
8106 | } | |
4d1cef84 AB |
8107 | |
8108 | write_fp_dreg(s, rd, tcg_rd); | |
8109 | ||
8110 | tcg_temp_free_i64(tcg_rn); | |
8111 | tcg_temp_free_i64(tcg_rd); | |
8112 | if (round) { | |
8113 | tcg_temp_free_i64(tcg_round); | |
8114 | } | |
8115 | } | |
8116 | ||
8117 | /* SHL/SLI - Scalar shift left */ | |
8118 | static void handle_scalar_simd_shli(DisasContext *s, bool insert, | |
8119 | int immh, int immb, int opcode, | |
8120 | int rn, int rd) | |
8121 | { | |
8122 | int size = 32 - clz32(immh) - 1; | |
8123 | int immhb = immh << 3 | immb; | |
8124 | int shift = immhb - (8 << size); | |
8125 | TCGv_i64 tcg_rn = new_tmp_a64(s); | |
8126 | TCGv_i64 tcg_rd = new_tmp_a64(s); | |
8127 | ||
8128 | if (!extract32(immh, 3, 1)) { | |
8129 | unallocated_encoding(s); | |
8130 | return; | |
8131 | } | |
8132 | ||
8c6afa6a PM |
8133 | if (!fp_access_check(s)) { |
8134 | return; | |
8135 | } | |
8136 | ||
4d1cef84 AB |
8137 | tcg_rn = read_fp_dreg(s, rn); |
8138 | tcg_rd = insert ? read_fp_dreg(s, rd) : tcg_temp_new_i64(); | |
8139 | ||
cdb45a60 RH |
8140 | if (insert) { |
8141 | tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_rn, shift, 64 - shift); | |
8142 | } else { | |
8143 | tcg_gen_shli_i64(tcg_rd, tcg_rn, shift); | |
8144 | } | |
4d1cef84 AB |
8145 | |
8146 | write_fp_dreg(s, rd, tcg_rd); | |
8147 | ||
8148 | tcg_temp_free_i64(tcg_rn); | |
8149 | tcg_temp_free_i64(tcg_rd); | |
8150 | } | |
8151 | ||
c1b876b2 AB |
8152 | /* SQSHRN/SQSHRUN - Saturating (signed/unsigned) shift right with |
8153 | * (signed/unsigned) narrowing */ | |
8154 | static void handle_vec_simd_sqshrn(DisasContext *s, bool is_scalar, bool is_q, | |
8155 | bool is_u_shift, bool is_u_narrow, | |
8156 | int immh, int immb, int opcode, | |
8157 | int rn, int rd) | |
8158 | { | |
8159 | int immhb = immh << 3 | immb; | |
8160 | int size = 32 - clz32(immh) - 1; | |
8161 | int esize = 8 << size; | |
8162 | int shift = (2 * esize) - immhb; | |
8163 | int elements = is_scalar ? 1 : (64 / esize); | |
8164 | bool round = extract32(opcode, 0, 1); | |
14776ab5 | 8165 | MemOp ldop = (size + 1) | (is_u_shift ? 0 : MO_SIGN); |
c1b876b2 AB |
8166 | TCGv_i64 tcg_rn, tcg_rd, tcg_round; |
8167 | TCGv_i32 tcg_rd_narrowed; | |
8168 | TCGv_i64 tcg_final; | |
8169 | ||
8170 | static NeonGenNarrowEnvFn * const signed_narrow_fns[4][2] = { | |
8171 | { gen_helper_neon_narrow_sat_s8, | |
8172 | gen_helper_neon_unarrow_sat8 }, | |
8173 | { gen_helper_neon_narrow_sat_s16, | |
8174 | gen_helper_neon_unarrow_sat16 }, | |
8175 | { gen_helper_neon_narrow_sat_s32, | |
8176 | gen_helper_neon_unarrow_sat32 }, | |
8177 | { NULL, NULL }, | |
8178 | }; | |
8179 | static NeonGenNarrowEnvFn * const unsigned_narrow_fns[4] = { | |
8180 | gen_helper_neon_narrow_sat_u8, | |
8181 | gen_helper_neon_narrow_sat_u16, | |
8182 | gen_helper_neon_narrow_sat_u32, | |
8183 | NULL | |
8184 | }; | |
8185 | NeonGenNarrowEnvFn *narrowfn; | |
8186 | ||
8187 | int i; | |
8188 | ||
8189 | assert(size < 4); | |
8190 | ||
8191 | if (extract32(immh, 3, 1)) { | |
8192 | unallocated_encoding(s); | |
8193 | return; | |
8194 | } | |
8195 | ||
8c6afa6a PM |
8196 | if (!fp_access_check(s)) { |
8197 | return; | |
8198 | } | |
8199 | ||
c1b876b2 AB |
8200 | if (is_u_shift) { |
8201 | narrowfn = unsigned_narrow_fns[size]; | |
8202 | } else { | |
8203 | narrowfn = signed_narrow_fns[size][is_u_narrow ? 1 : 0]; | |
8204 | } | |
8205 | ||
8206 | tcg_rn = tcg_temp_new_i64(); | |
8207 | tcg_rd = tcg_temp_new_i64(); | |
8208 | tcg_rd_narrowed = tcg_temp_new_i32(); | |
8209 | tcg_final = tcg_const_i64(0); | |
8210 | ||
8211 | if (round) { | |
8212 | uint64_t round_const = 1ULL << (shift - 1); | |
8213 | tcg_round = tcg_const_i64(round_const); | |
8214 | } else { | |
f764718d | 8215 | tcg_round = NULL; |
c1b876b2 AB |
8216 | } |
8217 | ||
8218 | for (i = 0; i < elements; i++) { | |
8219 | read_vec_element(s, tcg_rn, rn, i, ldop); | |
8220 | handle_shri_with_rndacc(tcg_rd, tcg_rn, tcg_round, | |
8221 | false, is_u_shift, size+1, shift); | |
8222 | narrowfn(tcg_rd_narrowed, cpu_env, tcg_rd); | |
8223 | tcg_gen_extu_i32_i64(tcg_rd, tcg_rd_narrowed); | |
8224 | tcg_gen_deposit_i64(tcg_final, tcg_final, tcg_rd, esize * i, esize); | |
8225 | } | |
8226 | ||
8227 | if (!is_q) { | |
c1b876b2 AB |
8228 | write_vec_element(s, tcg_final, rd, 0, MO_64); |
8229 | } else { | |
8230 | write_vec_element(s, tcg_final, rd, 1, MO_64); | |
8231 | } | |
8232 | ||
8233 | if (round) { | |
8234 | tcg_temp_free_i64(tcg_round); | |
8235 | } | |
8236 | tcg_temp_free_i64(tcg_rn); | |
8237 | tcg_temp_free_i64(tcg_rd); | |
8238 | tcg_temp_free_i32(tcg_rd_narrowed); | |
8239 | tcg_temp_free_i64(tcg_final); | |
4ff55bcb RH |
8240 | |
8241 | clear_vec_high(s, is_q, rd); | |
c1b876b2 AB |
8242 | } |
8243 | ||
a847f32c PM |
8244 | /* SQSHLU, UQSHL, SQSHL: saturating left shifts */ |
8245 | static void handle_simd_qshl(DisasContext *s, bool scalar, bool is_q, | |
8246 | bool src_unsigned, bool dst_unsigned, | |
8247 | int immh, int immb, int rn, int rd) | |
8248 | { | |
8249 | int immhb = immh << 3 | immb; | |
8250 | int size = 32 - clz32(immh) - 1; | |
8251 | int shift = immhb - (8 << size); | |
8252 | int pass; | |
8253 | ||
8254 | assert(immh != 0); | |
8255 | assert(!(scalar && is_q)); | |
8256 | ||
8257 | if (!scalar) { | |
8258 | if (!is_q && extract32(immh, 3, 1)) { | |
8259 | unallocated_encoding(s); | |
8260 | return; | |
8261 | } | |
8262 | ||
8263 | /* Since we use the variable-shift helpers we must | |
8264 | * replicate the shift count into each element of | |
8265 | * the tcg_shift value. | |
8266 | */ | |
8267 | switch (size) { | |
8268 | case 0: | |
8269 | shift |= shift << 8; | |
8270 | /* fall through */ | |
8271 | case 1: | |
8272 | shift |= shift << 16; | |
8273 | break; | |
8274 | case 2: | |
8275 | case 3: | |
8276 | break; | |
8277 | default: | |
8278 | g_assert_not_reached(); | |
8279 | } | |
8280 | } | |
8281 | ||
8c6afa6a PM |
8282 | if (!fp_access_check(s)) { |
8283 | return; | |
8284 | } | |
8285 | ||
a847f32c PM |
8286 | if (size == 3) { |
8287 | TCGv_i64 tcg_shift = tcg_const_i64(shift); | |
8288 | static NeonGenTwo64OpEnvFn * const fns[2][2] = { | |
8289 | { gen_helper_neon_qshl_s64, gen_helper_neon_qshlu_s64 }, | |
8290 | { NULL, gen_helper_neon_qshl_u64 }, | |
8291 | }; | |
8292 | NeonGenTwo64OpEnvFn *genfn = fns[src_unsigned][dst_unsigned]; | |
8293 | int maxpass = is_q ? 2 : 1; | |
8294 | ||
8295 | for (pass = 0; pass < maxpass; pass++) { | |
8296 | TCGv_i64 tcg_op = tcg_temp_new_i64(); | |
8297 | ||
8298 | read_vec_element(s, tcg_op, rn, pass, MO_64); | |
8299 | genfn(tcg_op, cpu_env, tcg_op, tcg_shift); | |
8300 | write_vec_element(s, tcg_op, rd, pass, MO_64); | |
8301 | ||
8302 | tcg_temp_free_i64(tcg_op); | |
8303 | } | |
8304 | tcg_temp_free_i64(tcg_shift); | |
4ff55bcb | 8305 | clear_vec_high(s, is_q, rd); |
a847f32c PM |
8306 | } else { |
8307 | TCGv_i32 tcg_shift = tcg_const_i32(shift); | |
8308 | static NeonGenTwoOpEnvFn * const fns[2][2][3] = { | |
8309 | { | |
8310 | { gen_helper_neon_qshl_s8, | |
8311 | gen_helper_neon_qshl_s16, | |
8312 | gen_helper_neon_qshl_s32 }, | |
8313 | { gen_helper_neon_qshlu_s8, | |
8314 | gen_helper_neon_qshlu_s16, | |
8315 | gen_helper_neon_qshlu_s32 } | |
8316 | }, { | |
8317 | { NULL, NULL, NULL }, | |
8318 | { gen_helper_neon_qshl_u8, | |
8319 | gen_helper_neon_qshl_u16, | |
8320 | gen_helper_neon_qshl_u32 } | |
8321 | } | |
8322 | }; | |
8323 | NeonGenTwoOpEnvFn *genfn = fns[src_unsigned][dst_unsigned][size]; | |
14776ab5 | 8324 | MemOp memop = scalar ? size : MO_32; |
a847f32c PM |
8325 | int maxpass = scalar ? 1 : is_q ? 4 : 2; |
8326 | ||
8327 | for (pass = 0; pass < maxpass; pass++) { | |
8328 | TCGv_i32 tcg_op = tcg_temp_new_i32(); | |
8329 | ||
8330 | read_vec_element_i32(s, tcg_op, rn, pass, memop); | |
8331 | genfn(tcg_op, cpu_env, tcg_op, tcg_shift); | |
8332 | if (scalar) { | |
8333 | switch (size) { | |
8334 | case 0: | |
8335 | tcg_gen_ext8u_i32(tcg_op, tcg_op); | |
8336 | break; | |
8337 | case 1: | |
8338 | tcg_gen_ext16u_i32(tcg_op, tcg_op); | |
8339 | break; | |
8340 | case 2: | |
8341 | break; | |
8342 | default: | |
8343 | g_assert_not_reached(); | |
8344 | } | |
8345 | write_fp_sreg(s, rd, tcg_op); | |
8346 | } else { | |
8347 | write_vec_element_i32(s, tcg_op, rd, pass, MO_32); | |
8348 | } | |
8349 | ||
8350 | tcg_temp_free_i32(tcg_op); | |
8351 | } | |
8352 | tcg_temp_free_i32(tcg_shift); | |
8353 | ||
4ff55bcb RH |
8354 | if (!scalar) { |
8355 | clear_vec_high(s, is_q, rd); | |
a847f32c PM |
8356 | } |
8357 | } | |
8358 | } | |
8359 | ||
10113b69 AB |
8360 | /* Common vector code for handling integer to FP conversion */ |
8361 | static void handle_simd_intfp_conv(DisasContext *s, int rd, int rn, | |
8362 | int elements, int is_signed, | |
8363 | int fracbits, int size) | |
8364 | { | |
93193190 AB |
8365 | TCGv_ptr tcg_fpst = get_fpstatus_ptr(size == MO_16); |
8366 | TCGv_i32 tcg_shift = NULL; | |
8367 | ||
14776ab5 | 8368 | MemOp mop = size | (is_signed ? MO_SIGN : 0); |
10113b69 AB |
8369 | int pass; |
8370 | ||
93193190 AB |
8371 | if (fracbits || size == MO_64) { |
8372 | tcg_shift = tcg_const_i32(fracbits); | |
8373 | } | |
8374 | ||
8375 | if (size == MO_64) { | |
8376 | TCGv_i64 tcg_int64 = tcg_temp_new_i64(); | |
8377 | TCGv_i64 tcg_double = tcg_temp_new_i64(); | |
8378 | ||
8379 | for (pass = 0; pass < elements; pass++) { | |
8380 | read_vec_element(s, tcg_int64, rn, pass, mop); | |
10113b69 | 8381 | |
10113b69 | 8382 | if (is_signed) { |
93193190 | 8383 | gen_helper_vfp_sqtod(tcg_double, tcg_int64, |
10113b69 AB |
8384 | tcg_shift, tcg_fpst); |
8385 | } else { | |
93193190 | 8386 | gen_helper_vfp_uqtod(tcg_double, tcg_int64, |
10113b69 AB |
8387 | tcg_shift, tcg_fpst); |
8388 | } | |
8389 | if (elements == 1) { | |
8390 | write_fp_dreg(s, rd, tcg_double); | |
8391 | } else { | |
8392 | write_vec_element(s, tcg_double, rd, pass, MO_64); | |
8393 | } | |
93193190 AB |
8394 | } |
8395 | ||
8396 | tcg_temp_free_i64(tcg_int64); | |
8397 | tcg_temp_free_i64(tcg_double); | |
8398 | ||
8399 | } else { | |
8400 | TCGv_i32 tcg_int32 = tcg_temp_new_i32(); | |
8401 | TCGv_i32 tcg_float = tcg_temp_new_i32(); | |
8402 | ||
8403 | for (pass = 0; pass < elements; pass++) { | |
8404 | read_vec_element_i32(s, tcg_int32, rn, pass, mop); | |
8405 | ||
8406 | switch (size) { | |
8407 | case MO_32: | |
8408 | if (fracbits) { | |
8409 | if (is_signed) { | |
8410 | gen_helper_vfp_sltos(tcg_float, tcg_int32, | |
8411 | tcg_shift, tcg_fpst); | |
8412 | } else { | |
8413 | gen_helper_vfp_ultos(tcg_float, tcg_int32, | |
8414 | tcg_shift, tcg_fpst); | |
8415 | } | |
8416 | } else { | |
8417 | if (is_signed) { | |
8418 | gen_helper_vfp_sitos(tcg_float, tcg_int32, tcg_fpst); | |
8419 | } else { | |
8420 | gen_helper_vfp_uitos(tcg_float, tcg_int32, tcg_fpst); | |
8421 | } | |
8422 | } | |
8423 | break; | |
8424 | case MO_16: | |
8425 | if (fracbits) { | |
8426 | if (is_signed) { | |
8427 | gen_helper_vfp_sltoh(tcg_float, tcg_int32, | |
8428 | tcg_shift, tcg_fpst); | |
8429 | } else { | |
8430 | gen_helper_vfp_ultoh(tcg_float, tcg_int32, | |
8431 | tcg_shift, tcg_fpst); | |
8432 | } | |
8433 | } else { | |
8434 | if (is_signed) { | |
8435 | gen_helper_vfp_sitoh(tcg_float, tcg_int32, tcg_fpst); | |
8436 | } else { | |
8437 | gen_helper_vfp_uitoh(tcg_float, tcg_int32, tcg_fpst); | |
8438 | } | |
8439 | } | |
8440 | break; | |
8441 | default: | |
8442 | g_assert_not_reached(); | |
10113b69 | 8443 | } |
93193190 | 8444 | |
10113b69 | 8445 | if (elements == 1) { |
93193190 | 8446 | write_fp_sreg(s, rd, tcg_float); |
10113b69 | 8447 | } else { |
93193190 | 8448 | write_vec_element_i32(s, tcg_float, rd, pass, size); |
10113b69 | 8449 | } |
10113b69 | 8450 | } |
93193190 AB |
8451 | |
8452 | tcg_temp_free_i32(tcg_int32); | |
8453 | tcg_temp_free_i32(tcg_float); | |
10113b69 AB |
8454 | } |
8455 | ||
10113b69 | 8456 | tcg_temp_free_ptr(tcg_fpst); |
93193190 AB |
8457 | if (tcg_shift) { |
8458 | tcg_temp_free_i32(tcg_shift); | |
8459 | } | |
4ff55bcb RH |
8460 | |
8461 | clear_vec_high(s, elements << size == 16, rd); | |
10113b69 AB |
8462 | } |
8463 | ||
8464 | /* UCVTF/SCVTF - Integer to FP conversion */ | |
8465 | static void handle_simd_shift_intfp_conv(DisasContext *s, bool is_scalar, | |
8466 | bool is_q, bool is_u, | |
8467 | int immh, int immb, int opcode, | |
8468 | int rn, int rd) | |
8469 | { | |
a6117fae | 8470 | int size, elements, fracbits; |
10113b69 | 8471 | int immhb = immh << 3 | immb; |
10113b69 | 8472 | |
a6117fae RH |
8473 | if (immh & 8) { |
8474 | size = MO_64; | |
8475 | if (!is_scalar && !is_q) { | |
8476 | unallocated_encoding(s); | |
8477 | return; | |
8478 | } | |
8479 | } else if (immh & 4) { | |
8480 | size = MO_32; | |
8481 | } else if (immh & 2) { | |
8482 | size = MO_16; | |
5763190f | 8483 | if (!dc_isar_feature(aa64_fp16, s)) { |
a6117fae RH |
8484 | unallocated_encoding(s); |
8485 | return; | |
8486 | } | |
8487 | } else { | |
8488 | /* immh == 0 would be a failure of the decode logic */ | |
8489 | g_assert(immh == 1); | |
10113b69 AB |
8490 | unallocated_encoding(s); |
8491 | return; | |
8492 | } | |
8493 | ||
8494 | if (is_scalar) { | |
8495 | elements = 1; | |
8496 | } else { | |
a6117fae | 8497 | elements = (8 << is_q) >> size; |
10113b69 | 8498 | } |
a6117fae | 8499 | fracbits = (16 << size) - immhb; |
8c6afa6a PM |
8500 | |
8501 | if (!fp_access_check(s)) { | |
8502 | return; | |
8503 | } | |
8504 | ||
10113b69 AB |
8505 | handle_simd_intfp_conv(s, rd, rn, elements, !is_u, fracbits, size); |
8506 | } | |
8507 | ||
2ed3ea11 PM |
8508 | /* FCVTZS, FVCVTZU - FP to fixedpoint conversion */ |
8509 | static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar, | |
8510 | bool is_q, bool is_u, | |
8511 | int immh, int immb, int rn, int rd) | |
8512 | { | |
2ed3ea11 | 8513 | int immhb = immh << 3 | immb; |
d0ba8e74 | 8514 | int pass, size, fracbits; |
2ed3ea11 PM |
8515 | TCGv_ptr tcg_fpstatus; |
8516 | TCGv_i32 tcg_rmode, tcg_shift; | |
8517 | ||
d0ba8e74 RH |
8518 | if (immh & 0x8) { |
8519 | size = MO_64; | |
8520 | if (!is_scalar && !is_q) { | |
8521 | unallocated_encoding(s); | |
8522 | return; | |
8523 | } | |
8524 | } else if (immh & 0x4) { | |
8525 | size = MO_32; | |
8526 | } else if (immh & 0x2) { | |
8527 | size = MO_16; | |
5763190f | 8528 | if (!dc_isar_feature(aa64_fp16, s)) { |
d0ba8e74 RH |
8529 | unallocated_encoding(s); |
8530 | return; | |
8531 | } | |
8532 | } else { | |
8533 | /* Should have split out AdvSIMD modified immediate earlier. */ | |
8534 | assert(immh == 1); | |
2ed3ea11 PM |
8535 | unallocated_encoding(s); |
8536 | return; | |
8537 | } | |
8538 | ||
8c6afa6a PM |
8539 | if (!fp_access_check(s)) { |
8540 | return; | |
8541 | } | |
8542 | ||
2ed3ea11 PM |
8543 | assert(!(is_scalar && is_q)); |
8544 | ||
8545 | tcg_rmode = tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO)); | |
d0ba8e74 | 8546 | tcg_fpstatus = get_fpstatus_ptr(size == MO_16); |
9b049916 | 8547 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); |
d0ba8e74 | 8548 | fracbits = (16 << size) - immhb; |
2ed3ea11 PM |
8549 | tcg_shift = tcg_const_i32(fracbits); |
8550 | ||
d0ba8e74 | 8551 | if (size == MO_64) { |
4063452e | 8552 | int maxpass = is_scalar ? 1 : 2; |
2ed3ea11 PM |
8553 | |
8554 | for (pass = 0; pass < maxpass; pass++) { | |
8555 | TCGv_i64 tcg_op = tcg_temp_new_i64(); | |
8556 | ||
8557 | read_vec_element(s, tcg_op, rn, pass, MO_64); | |
8558 | if (is_u) { | |
8559 | gen_helper_vfp_touqd(tcg_op, tcg_op, tcg_shift, tcg_fpstatus); | |
8560 | } else { | |
8561 | gen_helper_vfp_tosqd(tcg_op, tcg_op, tcg_shift, tcg_fpstatus); | |
8562 | } | |
8563 | write_vec_element(s, tcg_op, rd, pass, MO_64); | |
8564 | tcg_temp_free_i64(tcg_op); | |
8565 | } | |
4ff55bcb | 8566 | clear_vec_high(s, is_q, rd); |
2ed3ea11 | 8567 | } else { |
d0ba8e74 RH |
8568 | void (*fn)(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_ptr); |
8569 | int maxpass = is_scalar ? 1 : ((8 << is_q) >> size); | |
2ed3ea11 | 8570 | |
d0ba8e74 RH |
8571 | switch (size) { |
8572 | case MO_16: | |
2ed3ea11 | 8573 | if (is_u) { |
88808a02 | 8574 | fn = gen_helper_vfp_touhh; |
2ed3ea11 | 8575 | } else { |
88808a02 | 8576 | fn = gen_helper_vfp_toshh; |
2ed3ea11 | 8577 | } |
d0ba8e74 RH |
8578 | break; |
8579 | case MO_32: | |
2ed3ea11 | 8580 | if (is_u) { |
d0ba8e74 | 8581 | fn = gen_helper_vfp_touls; |
2ed3ea11 | 8582 | } else { |
d0ba8e74 | 8583 | fn = gen_helper_vfp_tosls; |
2ed3ea11 | 8584 | } |
d0ba8e74 RH |
8585 | break; |
8586 | default: | |
8587 | g_assert_not_reached(); | |
8588 | } | |
8589 | ||
8590 | for (pass = 0; pass < maxpass; pass++) { | |
8591 | TCGv_i32 tcg_op = tcg_temp_new_i32(); | |
8592 | ||
8593 | read_vec_element_i32(s, tcg_op, rn, pass, size); | |
8594 | fn(tcg_op, tcg_op, tcg_shift, tcg_fpstatus); | |
2ed3ea11 PM |
8595 | if (is_scalar) { |
8596 | write_fp_sreg(s, rd, tcg_op); | |
8597 | } else { | |
d0ba8e74 | 8598 | write_vec_element_i32(s, tcg_op, rd, pass, size); |
2ed3ea11 PM |
8599 | } |
8600 | tcg_temp_free_i32(tcg_op); | |
8601 | } | |
4ff55bcb RH |
8602 | if (!is_scalar) { |
8603 | clear_vec_high(s, is_q, rd); | |
2ed3ea11 PM |
8604 | } |
8605 | } | |
8606 | ||
8607 | tcg_temp_free_ptr(tcg_fpstatus); | |
8608 | tcg_temp_free_i32(tcg_shift); | |
9b049916 | 8609 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); |
2ed3ea11 PM |
8610 | tcg_temp_free_i32(tcg_rmode); |
8611 | } | |
8612 | ||
4ce31af4 | 8613 | /* AdvSIMD scalar shift by immediate |
384b26fb AB |
8614 | * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0 |
8615 | * +-----+---+-------------+------+------+--------+---+------+------+ | |
8616 | * | 0 1 | U | 1 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd | | |
8617 | * +-----+---+-------------+------+------+--------+---+------+------+ | |
4d1cef84 AB |
8618 | * |
8619 | * This is the scalar version so it works on a fixed sized registers | |
384b26fb AB |
8620 | */ |
8621 | static void disas_simd_scalar_shift_imm(DisasContext *s, uint32_t insn) | |
8622 | { | |
4d1cef84 AB |
8623 | int rd = extract32(insn, 0, 5); |
8624 | int rn = extract32(insn, 5, 5); | |
8625 | int opcode = extract32(insn, 11, 5); | |
8626 | int immb = extract32(insn, 16, 3); | |
8627 | int immh = extract32(insn, 19, 4); | |
8628 | bool is_u = extract32(insn, 29, 1); | |
8629 | ||
c1b876b2 AB |
8630 | if (immh == 0) { |
8631 | unallocated_encoding(s); | |
8632 | return; | |
8633 | } | |
8634 | ||
4d1cef84 | 8635 | switch (opcode) { |
37a706ad PM |
8636 | case 0x08: /* SRI */ |
8637 | if (!is_u) { | |
8638 | unallocated_encoding(s); | |
8639 | return; | |
8640 | } | |
8641 | /* fall through */ | |
4d1cef84 AB |
8642 | case 0x00: /* SSHR / USHR */ |
8643 | case 0x02: /* SSRA / USRA */ | |
8644 | case 0x04: /* SRSHR / URSHR */ | |
8645 | case 0x06: /* SRSRA / URSRA */ | |
8646 | handle_scalar_simd_shri(s, is_u, immh, immb, opcode, rn, rd); | |
8647 | break; | |
8648 | case 0x0a: /* SHL / SLI */ | |
8649 | handle_scalar_simd_shli(s, is_u, immh, immb, opcode, rn, rd); | |
8650 | break; | |
10113b69 AB |
8651 | case 0x1c: /* SCVTF, UCVTF */ |
8652 | handle_simd_shift_intfp_conv(s, true, false, is_u, immh, immb, | |
8653 | opcode, rn, rd); | |
8654 | break; | |
c1b876b2 AB |
8655 | case 0x10: /* SQSHRUN, SQSHRUN2 */ |
8656 | case 0x11: /* SQRSHRUN, SQRSHRUN2 */ | |
8657 | if (!is_u) { | |
8658 | unallocated_encoding(s); | |
8659 | return; | |
8660 | } | |
8661 | handle_vec_simd_sqshrn(s, true, false, false, true, | |
8662 | immh, immb, opcode, rn, rd); | |
8663 | break; | |
8664 | case 0x12: /* SQSHRN, SQSHRN2, UQSHRN */ | |
8665 | case 0x13: /* SQRSHRN, SQRSHRN2, UQRSHRN, UQRSHRN2 */ | |
8666 | handle_vec_simd_sqshrn(s, true, false, is_u, is_u, | |
8667 | immh, immb, opcode, rn, rd); | |
8668 | break; | |
a566da1b | 8669 | case 0xc: /* SQSHLU */ |
a847f32c PM |
8670 | if (!is_u) { |
8671 | unallocated_encoding(s); | |
8672 | return; | |
8673 | } | |
8674 | handle_simd_qshl(s, true, false, false, true, immh, immb, rn, rd); | |
8675 | break; | |
a566da1b | 8676 | case 0xe: /* SQSHL, UQSHL */ |
a847f32c PM |
8677 | handle_simd_qshl(s, true, false, is_u, is_u, immh, immb, rn, rd); |
8678 | break; | |
a566da1b | 8679 | case 0x1f: /* FCVTZS, FCVTZU */ |
2ed3ea11 | 8680 | handle_simd_shift_fpint_conv(s, true, false, is_u, immh, immb, rn, rd); |
4d1cef84 | 8681 | break; |
a566da1b PM |
8682 | default: |
8683 | unallocated_encoding(s); | |
8684 | break; | |
4d1cef84 | 8685 | } |
384b26fb AB |
8686 | } |
8687 | ||
4ce31af4 | 8688 | /* AdvSIMD scalar three different |
384b26fb AB |
8689 | * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0 |
8690 | * +-----+---+-----------+------+---+------+--------+-----+------+------+ | |
8691 | * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd | | |
8692 | * +-----+---+-----------+------+---+------+--------+-----+------+------+ | |
8693 | */ | |
8694 | static void disas_simd_scalar_three_reg_diff(DisasContext *s, uint32_t insn) | |
8695 | { | |
b033cd3d PM |
8696 | bool is_u = extract32(insn, 29, 1); |
8697 | int size = extract32(insn, 22, 2); | |
8698 | int opcode = extract32(insn, 12, 4); | |
8699 | int rm = extract32(insn, 16, 5); | |
8700 | int rn = extract32(insn, 5, 5); | |
8701 | int rd = extract32(insn, 0, 5); | |
8702 | ||
8703 | if (is_u) { | |
8704 | unallocated_encoding(s); | |
8705 | return; | |
8706 | } | |
8707 | ||
8708 | switch (opcode) { | |
8709 | case 0x9: /* SQDMLAL, SQDMLAL2 */ | |
8710 | case 0xb: /* SQDMLSL, SQDMLSL2 */ | |
8711 | case 0xd: /* SQDMULL, SQDMULL2 */ | |
8712 | if (size == 0 || size == 3) { | |
8713 | unallocated_encoding(s); | |
8714 | return; | |
8715 | } | |
8716 | break; | |
8717 | default: | |
8718 | unallocated_encoding(s); | |
8719 | return; | |
8720 | } | |
8721 | ||
8c6afa6a PM |
8722 | if (!fp_access_check(s)) { |
8723 | return; | |
8724 | } | |
8725 | ||
b033cd3d PM |
8726 | if (size == 2) { |
8727 | TCGv_i64 tcg_op1 = tcg_temp_new_i64(); | |
8728 | TCGv_i64 tcg_op2 = tcg_temp_new_i64(); | |
8729 | TCGv_i64 tcg_res = tcg_temp_new_i64(); | |
8730 | ||
8731 | read_vec_element(s, tcg_op1, rn, 0, MO_32 | MO_SIGN); | |
8732 | read_vec_element(s, tcg_op2, rm, 0, MO_32 | MO_SIGN); | |
8733 | ||
8734 | tcg_gen_mul_i64(tcg_res, tcg_op1, tcg_op2); | |
8735 | gen_helper_neon_addl_saturate_s64(tcg_res, cpu_env, tcg_res, tcg_res); | |
8736 | ||
8737 | switch (opcode) { | |
8738 | case 0xd: /* SQDMULL, SQDMULL2 */ | |
8739 | break; | |
8740 | case 0xb: /* SQDMLSL, SQDMLSL2 */ | |
8741 | tcg_gen_neg_i64(tcg_res, tcg_res); | |
8742 | /* fall through */ | |
8743 | case 0x9: /* SQDMLAL, SQDMLAL2 */ | |
8744 | read_vec_element(s, tcg_op1, rd, 0, MO_64); | |
8745 | gen_helper_neon_addl_saturate_s64(tcg_res, cpu_env, | |
8746 | tcg_res, tcg_op1); | |
8747 | break; | |
8748 | default: | |
8749 | g_assert_not_reached(); | |
8750 | } | |
8751 | ||
8752 | write_fp_dreg(s, rd, tcg_res); | |
8753 | ||
8754 | tcg_temp_free_i64(tcg_op1); | |
8755 | tcg_temp_free_i64(tcg_op2); | |
8756 | tcg_temp_free_i64(tcg_res); | |
8757 | } else { | |
3d99d931 RH |
8758 | TCGv_i32 tcg_op1 = read_fp_hreg(s, rn); |
8759 | TCGv_i32 tcg_op2 = read_fp_hreg(s, rm); | |
b033cd3d PM |
8760 | TCGv_i64 tcg_res = tcg_temp_new_i64(); |
8761 | ||
b033cd3d PM |
8762 | gen_helper_neon_mull_s16(tcg_res, tcg_op1, tcg_op2); |
8763 | gen_helper_neon_addl_saturate_s32(tcg_res, cpu_env, tcg_res, tcg_res); | |
8764 | ||
8765 | switch (opcode) { | |
8766 | case 0xd: /* SQDMULL, SQDMULL2 */ | |
8767 | break; | |
8768 | case 0xb: /* SQDMLSL, SQDMLSL2 */ | |
8769 | gen_helper_neon_negl_u32(tcg_res, tcg_res); | |
8770 | /* fall through */ | |
8771 | case 0x9: /* SQDMLAL, SQDMLAL2 */ | |
8772 | { | |
8773 | TCGv_i64 tcg_op3 = tcg_temp_new_i64(); | |
8774 | read_vec_element(s, tcg_op3, rd, 0, MO_32); | |
8775 | gen_helper_neon_addl_saturate_s32(tcg_res, cpu_env, | |
8776 | tcg_res, tcg_op3); | |
8777 | tcg_temp_free_i64(tcg_op3); | |
8778 | break; | |
8779 | } | |
8780 | default: | |
8781 | g_assert_not_reached(); | |
8782 | } | |
8783 | ||
8784 | tcg_gen_ext32u_i64(tcg_res, tcg_res); | |
8785 | write_fp_dreg(s, rd, tcg_res); | |
8786 | ||
8787 | tcg_temp_free_i32(tcg_op1); | |
8788 | tcg_temp_free_i32(tcg_op2); | |
8789 | tcg_temp_free_i64(tcg_res); | |
8790 | } | |
384b26fb AB |
8791 | } |
8792 | ||
b305dba6 PM |
8793 | static void handle_3same_64(DisasContext *s, int opcode, bool u, |
8794 | TCGv_i64 tcg_rd, TCGv_i64 tcg_rn, TCGv_i64 tcg_rm) | |
8795 | { | |
8796 | /* Handle 64x64->64 opcodes which are shared between the scalar | |
8797 | * and vector 3-same groups. We cover every opcode where size == 3 | |
8798 | * is valid in either the three-reg-same (integer, not pairwise) | |
3840d219 | 8799 | * or scalar-three-reg-same groups. |
b305dba6 PM |
8800 | */ |
8801 | TCGCond cond; | |
8802 | ||
8803 | switch (opcode) { | |
6d9571f7 PM |
8804 | case 0x1: /* SQADD */ |
8805 | if (u) { | |
8806 | gen_helper_neon_qadd_u64(tcg_rd, cpu_env, tcg_rn, tcg_rm); | |
8807 | } else { | |
8808 | gen_helper_neon_qadd_s64(tcg_rd, cpu_env, tcg_rn, tcg_rm); | |
8809 | } | |
8810 | break; | |
8811 | case 0x5: /* SQSUB */ | |
8812 | if (u) { | |
8813 | gen_helper_neon_qsub_u64(tcg_rd, cpu_env, tcg_rn, tcg_rm); | |
8814 | } else { | |
8815 | gen_helper_neon_qsub_s64(tcg_rd, cpu_env, tcg_rn, tcg_rm); | |
8816 | } | |
8817 | break; | |
b305dba6 PM |
8818 | case 0x6: /* CMGT, CMHI */ |
8819 | /* 64 bit integer comparison, result = test ? (2^64 - 1) : 0. | |
8820 | * We implement this using setcond (test) and then negating. | |
8821 | */ | |
8822 | cond = u ? TCG_COND_GTU : TCG_COND_GT; | |
8823 | do_cmop: | |
8824 | tcg_gen_setcond_i64(cond, tcg_rd, tcg_rn, tcg_rm); | |
8825 | tcg_gen_neg_i64(tcg_rd, tcg_rd); | |
8826 | break; | |
8827 | case 0x7: /* CMGE, CMHS */ | |
8828 | cond = u ? TCG_COND_GEU : TCG_COND_GE; | |
8829 | goto do_cmop; | |
8830 | case 0x11: /* CMTST, CMEQ */ | |
8831 | if (u) { | |
8832 | cond = TCG_COND_EQ; | |
8833 | goto do_cmop; | |
8834 | } | |
79d61de6 | 8835 | gen_cmtst_i64(tcg_rd, tcg_rn, tcg_rm); |
b305dba6 | 8836 | break; |
6d9571f7 | 8837 | case 0x8: /* SSHL, USHL */ |
b305dba6 | 8838 | if (u) { |
87b74e8b | 8839 | gen_ushl_i64(tcg_rd, tcg_rn, tcg_rm); |
b305dba6 | 8840 | } else { |
87b74e8b | 8841 | gen_sshl_i64(tcg_rd, tcg_rn, tcg_rm); |
b305dba6 PM |
8842 | } |
8843 | break; | |
b305dba6 | 8844 | case 0x9: /* SQSHL, UQSHL */ |
6d9571f7 PM |
8845 | if (u) { |
8846 | gen_helper_neon_qshl_u64(tcg_rd, cpu_env, tcg_rn, tcg_rm); | |
8847 | } else { | |
8848 | gen_helper_neon_qshl_s64(tcg_rd, cpu_env, tcg_rn, tcg_rm); | |
8849 | } | |
8850 | break; | |
b305dba6 | 8851 | case 0xa: /* SRSHL, URSHL */ |
6d9571f7 PM |
8852 | if (u) { |
8853 | gen_helper_neon_rshl_u64(tcg_rd, tcg_rn, tcg_rm); | |
8854 | } else { | |
8855 | gen_helper_neon_rshl_s64(tcg_rd, tcg_rn, tcg_rm); | |
8856 | } | |
8857 | break; | |
b305dba6 | 8858 | case 0xb: /* SQRSHL, UQRSHL */ |
6d9571f7 PM |
8859 | if (u) { |
8860 | gen_helper_neon_qrshl_u64(tcg_rd, cpu_env, tcg_rn, tcg_rm); | |
8861 | } else { | |
8862 | gen_helper_neon_qrshl_s64(tcg_rd, cpu_env, tcg_rn, tcg_rm); | |
8863 | } | |
8864 | break; | |
8865 | case 0x10: /* ADD, SUB */ | |
8866 | if (u) { | |
8867 | tcg_gen_sub_i64(tcg_rd, tcg_rn, tcg_rm); | |
8868 | } else { | |
8869 | tcg_gen_add_i64(tcg_rd, tcg_rn, tcg_rm); | |
8870 | } | |
8871 | break; | |
b305dba6 PM |
8872 | default: |
8873 | g_assert_not_reached(); | |
8874 | } | |
8875 | } | |
8876 | ||
845ea09a PM |
8877 | /* Handle the 3-same-operands float operations; shared by the scalar |
8878 | * and vector encodings. The caller must filter out any encodings | |
8879 | * not allocated for the encoding it is dealing with. | |
8880 | */ | |
8881 | static void handle_3same_float(DisasContext *s, int size, int elements, | |
8882 | int fpopcode, int rd, int rn, int rm) | |
8883 | { | |
8884 | int pass; | |
d81ce0ef | 8885 | TCGv_ptr fpst = get_fpstatus_ptr(false); |
845ea09a PM |
8886 | |
8887 | for (pass = 0; pass < elements; pass++) { | |
8888 | if (size) { | |
8889 | /* Double */ | |
8890 | TCGv_i64 tcg_op1 = tcg_temp_new_i64(); | |
8891 | TCGv_i64 tcg_op2 = tcg_temp_new_i64(); | |
8892 | TCGv_i64 tcg_res = tcg_temp_new_i64(); | |
8893 | ||
8894 | read_vec_element(s, tcg_op1, rn, pass, MO_64); | |
8895 | read_vec_element(s, tcg_op2, rm, pass, MO_64); | |
8896 | ||
8897 | switch (fpopcode) { | |
057d5f62 PM |
8898 | case 0x39: /* FMLS */ |
8899 | /* As usual for ARM, separate negation for fused multiply-add */ | |
8900 | gen_helper_vfp_negd(tcg_op1, tcg_op1); | |
8901 | /* fall through */ | |
8902 | case 0x19: /* FMLA */ | |
8903 | read_vec_element(s, tcg_res, rd, pass, MO_64); | |
8904 | gen_helper_vfp_muladdd(tcg_res, tcg_op1, tcg_op2, | |
8905 | tcg_res, fpst); | |
8906 | break; | |
845ea09a PM |
8907 | case 0x18: /* FMAXNM */ |
8908 | gen_helper_vfp_maxnumd(tcg_res, tcg_op1, tcg_op2, fpst); | |
8909 | break; | |
8910 | case 0x1a: /* FADD */ | |
8911 | gen_helper_vfp_addd(tcg_res, tcg_op1, tcg_op2, fpst); | |
8912 | break; | |
057d5f62 PM |
8913 | case 0x1b: /* FMULX */ |
8914 | gen_helper_vfp_mulxd(tcg_res, tcg_op1, tcg_op2, fpst); | |
8915 | break; | |
8908f4d1 AB |
8916 | case 0x1c: /* FCMEQ */ |
8917 | gen_helper_neon_ceq_f64(tcg_res, tcg_op1, tcg_op2, fpst); | |
8918 | break; | |
845ea09a PM |
8919 | case 0x1e: /* FMAX */ |
8920 | gen_helper_vfp_maxd(tcg_res, tcg_op1, tcg_op2, fpst); | |
8921 | break; | |
057d5f62 PM |
8922 | case 0x1f: /* FRECPS */ |
8923 | gen_helper_recpsf_f64(tcg_res, tcg_op1, tcg_op2, fpst); | |
8924 | break; | |
845ea09a PM |
8925 | case 0x38: /* FMINNM */ |
8926 | gen_helper_vfp_minnumd(tcg_res, tcg_op1, tcg_op2, fpst); | |
8927 | break; | |
8928 | case 0x3a: /* FSUB */ | |
8929 | gen_helper_vfp_subd(tcg_res, tcg_op1, tcg_op2, fpst); | |
8930 | break; | |
8931 | case 0x3e: /* FMIN */ | |
8932 | gen_helper_vfp_mind(tcg_res, tcg_op1, tcg_op2, fpst); | |
8933 | break; | |
057d5f62 PM |
8934 | case 0x3f: /* FRSQRTS */ |
8935 | gen_helper_rsqrtsf_f64(tcg_res, tcg_op1, tcg_op2, fpst); | |
8936 | break; | |
845ea09a PM |
8937 | case 0x5b: /* FMUL */ |
8938 | gen_helper_vfp_muld(tcg_res, tcg_op1, tcg_op2, fpst); | |
8939 | break; | |
8908f4d1 AB |
8940 | case 0x5c: /* FCMGE */ |
8941 | gen_helper_neon_cge_f64(tcg_res, tcg_op1, tcg_op2, fpst); | |
8942 | break; | |
057d5f62 PM |
8943 | case 0x5d: /* FACGE */ |
8944 | gen_helper_neon_acge_f64(tcg_res, tcg_op1, tcg_op2, fpst); | |
8945 | break; | |
845ea09a PM |
8946 | case 0x5f: /* FDIV */ |
8947 | gen_helper_vfp_divd(tcg_res, tcg_op1, tcg_op2, fpst); | |
8948 | break; | |
8949 | case 0x7a: /* FABD */ | |
8950 | gen_helper_vfp_subd(tcg_res, tcg_op1, tcg_op2, fpst); | |
8951 | gen_helper_vfp_absd(tcg_res, tcg_res); | |
8952 | break; | |
8908f4d1 AB |
8953 | case 0x7c: /* FCMGT */ |
8954 | gen_helper_neon_cgt_f64(tcg_res, tcg_op1, tcg_op2, fpst); | |
8955 | break; | |
057d5f62 PM |
8956 | case 0x7d: /* FACGT */ |
8957 | gen_helper_neon_acgt_f64(tcg_res, tcg_op1, tcg_op2, fpst); | |
8958 | break; | |
845ea09a PM |
8959 | default: |
8960 | g_assert_not_reached(); | |
8961 | } | |
8962 | ||
8963 | write_vec_element(s, tcg_res, rd, pass, MO_64); | |
8964 | ||
8965 | tcg_temp_free_i64(tcg_res); | |
8966 | tcg_temp_free_i64(tcg_op1); | |
8967 | tcg_temp_free_i64(tcg_op2); | |
8968 | } else { | |
8969 | /* Single */ | |
8970 | TCGv_i32 tcg_op1 = tcg_temp_new_i32(); | |
8971 | TCGv_i32 tcg_op2 = tcg_temp_new_i32(); | |
8972 | TCGv_i32 tcg_res = tcg_temp_new_i32(); | |
8973 | ||
8974 | read_vec_element_i32(s, tcg_op1, rn, pass, MO_32); | |
8975 | read_vec_element_i32(s, tcg_op2, rm, pass, MO_32); | |
8976 | ||
8977 | switch (fpopcode) { | |
057d5f62 PM |
8978 | case 0x39: /* FMLS */ |
8979 | /* As usual for ARM, separate negation for fused multiply-add */ | |
8980 | gen_helper_vfp_negs(tcg_op1, tcg_op1); | |
8981 | /* fall through */ | |
8982 | case 0x19: /* FMLA */ | |
8983 | read_vec_element_i32(s, tcg_res, rd, pass, MO_32); | |
8984 | gen_helper_vfp_muladds(tcg_res, tcg_op1, tcg_op2, | |
8985 | tcg_res, fpst); | |
8986 | break; | |
845ea09a PM |
8987 | case 0x1a: /* FADD */ |
8988 | gen_helper_vfp_adds(tcg_res, tcg_op1, tcg_op2, fpst); | |
8989 | break; | |
057d5f62 PM |
8990 | case 0x1b: /* FMULX */ |
8991 | gen_helper_vfp_mulxs(tcg_res, tcg_op1, tcg_op2, fpst); | |
8992 | break; | |
8908f4d1 AB |
8993 | case 0x1c: /* FCMEQ */ |
8994 | gen_helper_neon_ceq_f32(tcg_res, tcg_op1, tcg_op2, fpst); | |
8995 | break; | |
845ea09a PM |
8996 | case 0x1e: /* FMAX */ |
8997 | gen_helper_vfp_maxs(tcg_res, tcg_op1, tcg_op2, fpst); | |
8998 | break; | |
057d5f62 PM |
8999 | case 0x1f: /* FRECPS */ |
9000 | gen_helper_recpsf_f32(tcg_res, tcg_op1, tcg_op2, fpst); | |
9001 | break; | |
845ea09a PM |
9002 | case 0x18: /* FMAXNM */ |
9003 | gen_helper_vfp_maxnums(tcg_res, tcg_op1, tcg_op2, fpst); | |
9004 | break; | |
9005 | case 0x38: /* FMINNM */ | |
9006 | gen_helper_vfp_minnums(tcg_res, tcg_op1, tcg_op2, fpst); | |
9007 | break; | |
9008 | case 0x3a: /* FSUB */ | |
9009 | gen_helper_vfp_subs(tcg_res, tcg_op1, tcg_op2, fpst); | |
9010 | break; | |
9011 | case 0x3e: /* FMIN */ | |
9012 | gen_helper_vfp_mins(tcg_res, tcg_op1, tcg_op2, fpst); | |
9013 | break; | |
057d5f62 PM |
9014 | case 0x3f: /* FRSQRTS */ |
9015 | gen_helper_rsqrtsf_f32(tcg_res, tcg_op1, tcg_op2, fpst); | |
9016 | break; | |
845ea09a PM |
9017 | case 0x5b: /* FMUL */ |
9018 | gen_helper_vfp_muls(tcg_res, tcg_op1, tcg_op2, fpst); | |
9019 | break; | |
8908f4d1 AB |
9020 | case 0x5c: /* FCMGE */ |
9021 | gen_helper_neon_cge_f32(tcg_res, tcg_op1, tcg_op2, fpst); | |
9022 | break; | |
057d5f62 PM |
9023 | case 0x5d: /* FACGE */ |
9024 | gen_helper_neon_acge_f32(tcg_res, tcg_op1, tcg_op2, fpst); | |
9025 | break; | |
845ea09a PM |
9026 | case 0x5f: /* FDIV */ |
9027 | gen_helper_vfp_divs(tcg_res, tcg_op1, tcg_op2, fpst); | |
9028 | break; | |
9029 | case 0x7a: /* FABD */ | |
9030 | gen_helper_vfp_subs(tcg_res, tcg_op1, tcg_op2, fpst); | |
9031 | gen_helper_vfp_abss(tcg_res, tcg_res); | |
9032 | break; | |
8908f4d1 AB |
9033 | case 0x7c: /* FCMGT */ |
9034 | gen_helper_neon_cgt_f32(tcg_res, tcg_op1, tcg_op2, fpst); | |
9035 | break; | |
057d5f62 PM |
9036 | case 0x7d: /* FACGT */ |
9037 | gen_helper_neon_acgt_f32(tcg_res, tcg_op1, tcg_op2, fpst); | |
9038 | break; | |
845ea09a PM |
9039 | default: |
9040 | g_assert_not_reached(); | |
9041 | } | |
9042 | ||
9043 | if (elements == 1) { | |
9044 | /* scalar single so clear high part */ | |
9045 | TCGv_i64 tcg_tmp = tcg_temp_new_i64(); | |
9046 | ||
9047 | tcg_gen_extu_i32_i64(tcg_tmp, tcg_res); | |
9048 | write_vec_element(s, tcg_tmp, rd, pass, MO_64); | |
9049 | tcg_temp_free_i64(tcg_tmp); | |
9050 | } else { | |
9051 | write_vec_element_i32(s, tcg_res, rd, pass, MO_32); | |
9052 | } | |
9053 | ||
9054 | tcg_temp_free_i32(tcg_res); | |
9055 | tcg_temp_free_i32(tcg_op1); | |
9056 | tcg_temp_free_i32(tcg_op2); | |
9057 | } | |
9058 | } | |
9059 | ||
9060 | tcg_temp_free_ptr(fpst); | |
9061 | ||
4ff55bcb | 9062 | clear_vec_high(s, elements * (size ? 8 : 4) > 8, rd); |
845ea09a PM |
9063 | } |
9064 | ||
4ce31af4 | 9065 | /* AdvSIMD scalar three same |
384b26fb AB |
9066 | * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0 |
9067 | * +-----+---+-----------+------+---+------+--------+---+------+------+ | |
9068 | * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd | | |
9069 | * +-----+---+-----------+------+---+------+--------+---+------+------+ | |
9070 | */ | |
9071 | static void disas_simd_scalar_three_reg_same(DisasContext *s, uint32_t insn) | |
9072 | { | |
b305dba6 PM |
9073 | int rd = extract32(insn, 0, 5); |
9074 | int rn = extract32(insn, 5, 5); | |
9075 | int opcode = extract32(insn, 11, 5); | |
9076 | int rm = extract32(insn, 16, 5); | |
9077 | int size = extract32(insn, 22, 2); | |
9078 | bool u = extract32(insn, 29, 1); | |
b305dba6 PM |
9079 | TCGv_i64 tcg_rd; |
9080 | ||
9081 | if (opcode >= 0x18) { | |
9082 | /* Floating point: U, size[1] and opcode indicate operation */ | |
9083 | int fpopcode = opcode | (extract32(size, 1, 1) << 5) | (u << 6); | |
9084 | switch (fpopcode) { | |
9085 | case 0x1b: /* FMULX */ | |
b305dba6 PM |
9086 | case 0x1f: /* FRECPS */ |
9087 | case 0x3f: /* FRSQRTS */ | |
b305dba6 | 9088 | case 0x5d: /* FACGE */ |
b305dba6 | 9089 | case 0x7d: /* FACGT */ |
8908f4d1 AB |
9090 | case 0x1c: /* FCMEQ */ |
9091 | case 0x5c: /* FCMGE */ | |
9092 | case 0x7c: /* FCMGT */ | |
845ea09a PM |
9093 | case 0x7a: /* FABD */ |
9094 | break; | |
b305dba6 PM |
9095 | default: |
9096 | unallocated_encoding(s); | |
9097 | return; | |
9098 | } | |
845ea09a | 9099 | |
8c6afa6a PM |
9100 | if (!fp_access_check(s)) { |
9101 | return; | |
9102 | } | |
9103 | ||
845ea09a PM |
9104 | handle_3same_float(s, extract32(size, 0, 1), 1, fpopcode, rd, rn, rm); |
9105 | return; | |
b305dba6 PM |
9106 | } |
9107 | ||
9108 | switch (opcode) { | |
9109 | case 0x1: /* SQADD, UQADD */ | |
9110 | case 0x5: /* SQSUB, UQSUB */ | |
c0b2b5fa PM |
9111 | case 0x9: /* SQSHL, UQSHL */ |
9112 | case 0xb: /* SQRSHL, UQRSHL */ | |
9113 | break; | |
6d9571f7 PM |
9114 | case 0x8: /* SSHL, USHL */ |
9115 | case 0xa: /* SRSHL, URSHL */ | |
b305dba6 PM |
9116 | case 0x6: /* CMGT, CMHI */ |
9117 | case 0x7: /* CMGE, CMHS */ | |
9118 | case 0x11: /* CMTST, CMEQ */ | |
9119 | case 0x10: /* ADD, SUB (vector) */ | |
9120 | if (size != 3) { | |
9121 | unallocated_encoding(s); | |
9122 | return; | |
9123 | } | |
9124 | break; | |
b305dba6 PM |
9125 | case 0x16: /* SQDMULH, SQRDMULH (vector) */ |
9126 | if (size != 1 && size != 2) { | |
9127 | unallocated_encoding(s); | |
9128 | return; | |
9129 | } | |
c0b2b5fa | 9130 | break; |
b305dba6 PM |
9131 | default: |
9132 | unallocated_encoding(s); | |
9133 | return; | |
9134 | } | |
9135 | ||
8c6afa6a PM |
9136 | if (!fp_access_check(s)) { |
9137 | return; | |
9138 | } | |
9139 | ||
b305dba6 PM |
9140 | tcg_rd = tcg_temp_new_i64(); |
9141 | ||
c0b2b5fa PM |
9142 | if (size == 3) { |
9143 | TCGv_i64 tcg_rn = read_fp_dreg(s, rn); | |
9144 | TCGv_i64 tcg_rm = read_fp_dreg(s, rm); | |
9145 | ||
9146 | handle_3same_64(s, opcode, u, tcg_rd, tcg_rn, tcg_rm); | |
9147 | tcg_temp_free_i64(tcg_rn); | |
9148 | tcg_temp_free_i64(tcg_rm); | |
9149 | } else { | |
9150 | /* Do a single operation on the lowest element in the vector. | |
9151 | * We use the standard Neon helpers and rely on 0 OP 0 == 0 with | |
9152 | * no side effects for all these operations. | |
9153 | * OPTME: special-purpose helpers would avoid doing some | |
9154 | * unnecessary work in the helper for the 8 and 16 bit cases. | |
9155 | */ | |
9156 | NeonGenTwoOpEnvFn *genenvfn; | |
9157 | TCGv_i32 tcg_rn = tcg_temp_new_i32(); | |
9158 | TCGv_i32 tcg_rm = tcg_temp_new_i32(); | |
9159 | TCGv_i32 tcg_rd32 = tcg_temp_new_i32(); | |
9160 | ||
9161 | read_vec_element_i32(s, tcg_rn, rn, 0, size); | |
9162 | read_vec_element_i32(s, tcg_rm, rm, 0, size); | |
9163 | ||
9164 | switch (opcode) { | |
9165 | case 0x1: /* SQADD, UQADD */ | |
9166 | { | |
9167 | static NeonGenTwoOpEnvFn * const fns[3][2] = { | |
9168 | { gen_helper_neon_qadd_s8, gen_helper_neon_qadd_u8 }, | |
9169 | { gen_helper_neon_qadd_s16, gen_helper_neon_qadd_u16 }, | |
9170 | { gen_helper_neon_qadd_s32, gen_helper_neon_qadd_u32 }, | |
9171 | }; | |
9172 | genenvfn = fns[size][u]; | |
9173 | break; | |
9174 | } | |
9175 | case 0x5: /* SQSUB, UQSUB */ | |
9176 | { | |
9177 | static NeonGenTwoOpEnvFn * const fns[3][2] = { | |
9178 | { gen_helper_neon_qsub_s8, gen_helper_neon_qsub_u8 }, | |
9179 | { gen_helper_neon_qsub_s16, gen_helper_neon_qsub_u16 }, | |
9180 | { gen_helper_neon_qsub_s32, gen_helper_neon_qsub_u32 }, | |
9181 | }; | |
9182 | genenvfn = fns[size][u]; | |
9183 | break; | |
9184 | } | |
9185 | case 0x9: /* SQSHL, UQSHL */ | |
9186 | { | |
9187 | static NeonGenTwoOpEnvFn * const fns[3][2] = { | |
9188 | { gen_helper_neon_qshl_s8, gen_helper_neon_qshl_u8 }, | |
9189 | { gen_helper_neon_qshl_s16, gen_helper_neon_qshl_u16 }, | |
9190 | { gen_helper_neon_qshl_s32, gen_helper_neon_qshl_u32 }, | |
9191 | }; | |
9192 | genenvfn = fns[size][u]; | |
9193 | break; | |
9194 | } | |
9195 | case 0xb: /* SQRSHL, UQRSHL */ | |
9196 | { | |
9197 | static NeonGenTwoOpEnvFn * const fns[3][2] = { | |
9198 | { gen_helper_neon_qrshl_s8, gen_helper_neon_qrshl_u8 }, | |
9199 | { gen_helper_neon_qrshl_s16, gen_helper_neon_qrshl_u16 }, | |
9200 | { gen_helper_neon_qrshl_s32, gen_helper_neon_qrshl_u32 }, | |
9201 | }; | |
9202 | genenvfn = fns[size][u]; | |
9203 | break; | |
9204 | } | |
9205 | case 0x16: /* SQDMULH, SQRDMULH */ | |
9206 | { | |
9207 | static NeonGenTwoOpEnvFn * const fns[2][2] = { | |
9208 | { gen_helper_neon_qdmulh_s16, gen_helper_neon_qrdmulh_s16 }, | |
9209 | { gen_helper_neon_qdmulh_s32, gen_helper_neon_qrdmulh_s32 }, | |
9210 | }; | |
9211 | assert(size == 1 || size == 2); | |
9212 | genenvfn = fns[size - 1][u]; | |
9213 | break; | |
9214 | } | |
9215 | default: | |
9216 | g_assert_not_reached(); | |
9217 | } | |
9218 | ||
9219 | genenvfn(tcg_rd32, cpu_env, tcg_rn, tcg_rm); | |
9220 | tcg_gen_extu_i32_i64(tcg_rd, tcg_rd32); | |
9221 | tcg_temp_free_i32(tcg_rd32); | |
9222 | tcg_temp_free_i32(tcg_rn); | |
9223 | tcg_temp_free_i32(tcg_rm); | |
9224 | } | |
b305dba6 PM |
9225 | |
9226 | write_fp_dreg(s, rd, tcg_rd); | |
9227 | ||
b305dba6 | 9228 | tcg_temp_free_i64(tcg_rd); |
384b26fb AB |
9229 | } |
9230 | ||
7c93b774 AB |
9231 | /* AdvSIMD scalar three same FP16 |
9232 | * 31 30 29 28 24 23 22 21 20 16 15 14 13 11 10 9 5 4 0 | |
9233 | * +-----+---+-----------+---+-----+------+-----+--------+---+----+----+ | |
9234 | * | 0 1 | U | 1 1 1 1 0 | a | 1 0 | Rm | 0 0 | opcode | 1 | Rn | Rd | | |
9235 | * +-----+---+-----------+---+-----+------+-----+--------+---+----+----+ | |
9236 | * v: 0101 1110 0100 0000 0000 0100 0000 0000 => 5e400400 | |
9237 | * m: 1101 1111 0110 0000 1100 0100 0000 0000 => df60c400 | |
9238 | */ | |
9239 | static void disas_simd_scalar_three_reg_same_fp16(DisasContext *s, | |
9240 | uint32_t insn) | |
9241 | { | |
9242 | int rd = extract32(insn, 0, 5); | |
9243 | int rn = extract32(insn, 5, 5); | |
9244 | int opcode = extract32(insn, 11, 3); | |
9245 | int rm = extract32(insn, 16, 5); | |
9246 | bool u = extract32(insn, 29, 1); | |
9247 | bool a = extract32(insn, 23, 1); | |
9248 | int fpopcode = opcode | (a << 3) | (u << 4); | |
9249 | TCGv_ptr fpst; | |
9250 | TCGv_i32 tcg_op1; | |
9251 | TCGv_i32 tcg_op2; | |
9252 | TCGv_i32 tcg_res; | |
9253 | ||
9254 | switch (fpopcode) { | |
9255 | case 0x03: /* FMULX */ | |
9256 | case 0x04: /* FCMEQ (reg) */ | |
9257 | case 0x07: /* FRECPS */ | |
9258 | case 0x0f: /* FRSQRTS */ | |
9259 | case 0x14: /* FCMGE (reg) */ | |
9260 | case 0x15: /* FACGE */ | |
9261 | case 0x1a: /* FABD */ | |
9262 | case 0x1c: /* FCMGT (reg) */ | |
9263 | case 0x1d: /* FACGT */ | |
9264 | break; | |
9265 | default: | |
9266 | unallocated_encoding(s); | |
9267 | return; | |
9268 | } | |
9269 | ||
5763190f | 9270 | if (!dc_isar_feature(aa64_fp16, s)) { |
7c93b774 AB |
9271 | unallocated_encoding(s); |
9272 | } | |
9273 | ||
9274 | if (!fp_access_check(s)) { | |
9275 | return; | |
9276 | } | |
9277 | ||
9278 | fpst = get_fpstatus_ptr(true); | |
9279 | ||
3d99d931 RH |
9280 | tcg_op1 = read_fp_hreg(s, rn); |
9281 | tcg_op2 = read_fp_hreg(s, rm); | |
7c93b774 AB |
9282 | tcg_res = tcg_temp_new_i32(); |
9283 | ||
7c93b774 AB |
9284 | switch (fpopcode) { |
9285 | case 0x03: /* FMULX */ | |
9286 | gen_helper_advsimd_mulxh(tcg_res, tcg_op1, tcg_op2, fpst); | |
9287 | break; | |
9288 | case 0x04: /* FCMEQ (reg) */ | |
9289 | gen_helper_advsimd_ceq_f16(tcg_res, tcg_op1, tcg_op2, fpst); | |
9290 | break; | |
9291 | case 0x07: /* FRECPS */ | |
9292 | gen_helper_recpsf_f16(tcg_res, tcg_op1, tcg_op2, fpst); | |
9293 | break; | |
9294 | case 0x0f: /* FRSQRTS */ | |
9295 | gen_helper_rsqrtsf_f16(tcg_res, tcg_op1, tcg_op2, fpst); | |
9296 | break; | |
9297 | case 0x14: /* FCMGE (reg) */ | |
9298 | gen_helper_advsimd_cge_f16(tcg_res, tcg_op1, tcg_op2, fpst); | |
9299 | break; | |
9300 | case 0x15: /* FACGE */ | |
9301 | gen_helper_advsimd_acge_f16(tcg_res, tcg_op1, tcg_op2, fpst); | |
9302 | break; | |
9303 | case 0x1a: /* FABD */ | |
9304 | gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst); | |
9305 | tcg_gen_andi_i32(tcg_res, tcg_res, 0x7fff); | |
9306 | break; | |
9307 | case 0x1c: /* FCMGT (reg) */ | |
9308 | gen_helper_advsimd_cgt_f16(tcg_res, tcg_op1, tcg_op2, fpst); | |
9309 | break; | |
9310 | case 0x1d: /* FACGT */ | |
9311 | gen_helper_advsimd_acgt_f16(tcg_res, tcg_op1, tcg_op2, fpst); | |
9312 | break; | |
9313 | default: | |
9314 | g_assert_not_reached(); | |
9315 | } | |
9316 | ||
9317 | write_fp_sreg(s, rd, tcg_res); | |
9318 | ||
9319 | ||
9320 | tcg_temp_free_i32(tcg_res); | |
9321 | tcg_temp_free_i32(tcg_op1); | |
9322 | tcg_temp_free_i32(tcg_op2); | |
9323 | tcg_temp_free_ptr(fpst); | |
9324 | } | |
9325 | ||
d9061ec3 RH |
9326 | /* AdvSIMD scalar three same extra |
9327 | * 31 30 29 28 24 23 22 21 20 16 15 14 11 10 9 5 4 0 | |
9328 | * +-----+---+-----------+------+---+------+---+--------+---+----+----+ | |
9329 | * | 0 1 | U | 1 1 1 1 0 | size | 0 | Rm | 1 | opcode | 1 | Rn | Rd | | |
9330 | * +-----+---+-----------+------+---+------+---+--------+---+----+----+ | |
9331 | */ | |
9332 | static void disas_simd_scalar_three_reg_same_extra(DisasContext *s, | |
9333 | uint32_t insn) | |
9334 | { | |
9335 | int rd = extract32(insn, 0, 5); | |
9336 | int rn = extract32(insn, 5, 5); | |
9337 | int opcode = extract32(insn, 11, 4); | |
9338 | int rm = extract32(insn, 16, 5); | |
9339 | int size = extract32(insn, 22, 2); | |
9340 | bool u = extract32(insn, 29, 1); | |
9341 | TCGv_i32 ele1, ele2, ele3; | |
9342 | TCGv_i64 res; | |
962fcbf2 | 9343 | bool feature; |
d9061ec3 RH |
9344 | |
9345 | switch (u * 16 + opcode) { | |
9346 | case 0x10: /* SQRDMLAH (vector) */ | |
9347 | case 0x11: /* SQRDMLSH (vector) */ | |
9348 | if (size != 1 && size != 2) { | |
9349 | unallocated_encoding(s); | |
9350 | return; | |
9351 | } | |
962fcbf2 | 9352 | feature = dc_isar_feature(aa64_rdm, s); |
d9061ec3 RH |
9353 | break; |
9354 | default: | |
9355 | unallocated_encoding(s); | |
9356 | return; | |
9357 | } | |
962fcbf2 | 9358 | if (!feature) { |
d9061ec3 RH |
9359 | unallocated_encoding(s); |
9360 | return; | |
9361 | } | |
9362 | if (!fp_access_check(s)) { | |
9363 | return; | |
9364 | } | |
9365 | ||
9366 | /* Do a single operation on the lowest element in the vector. | |
9367 | * We use the standard Neon helpers and rely on 0 OP 0 == 0 | |
9368 | * with no side effects for all these operations. | |
9369 | * OPTME: special-purpose helpers would avoid doing some | |
9370 | * unnecessary work in the helper for the 16 bit cases. | |
9371 | */ | |
9372 | ele1 = tcg_temp_new_i32(); | |
9373 | ele2 = tcg_temp_new_i32(); | |
9374 | ele3 = tcg_temp_new_i32(); | |
9375 | ||
9376 | read_vec_element_i32(s, ele1, rn, 0, size); | |
9377 | read_vec_element_i32(s, ele2, rm, 0, size); | |
9378 | read_vec_element_i32(s, ele3, rd, 0, size); | |
9379 | ||
9380 | switch (opcode) { | |
9381 | case 0x0: /* SQRDMLAH */ | |
9382 | if (size == 1) { | |
9383 | gen_helper_neon_qrdmlah_s16(ele3, cpu_env, ele1, ele2, ele3); | |
9384 | } else { | |
9385 | gen_helper_neon_qrdmlah_s32(ele3, cpu_env, ele1, ele2, ele3); | |
9386 | } | |
9387 | break; | |
9388 | case 0x1: /* SQRDMLSH */ | |
9389 | if (size == 1) { | |
9390 | gen_helper_neon_qrdmlsh_s16(ele3, cpu_env, ele1, ele2, ele3); | |
9391 | } else { | |
9392 | gen_helper_neon_qrdmlsh_s32(ele3, cpu_env, ele1, ele2, ele3); | |
9393 | } | |
9394 | break; | |
9395 | default: | |
9396 | g_assert_not_reached(); | |
9397 | } | |
9398 | tcg_temp_free_i32(ele1); | |
9399 | tcg_temp_free_i32(ele2); | |
9400 | ||
9401 | res = tcg_temp_new_i64(); | |
9402 | tcg_gen_extu_i32_i64(res, ele3); | |
9403 | tcg_temp_free_i32(ele3); | |
9404 | ||
9405 | write_fp_dreg(s, rd, res); | |
9406 | tcg_temp_free_i64(res); | |
9407 | } | |
9408 | ||
effa8e06 | 9409 | static void handle_2misc_64(DisasContext *s, int opcode, bool u, |
04c7c6c2 PM |
9410 | TCGv_i64 tcg_rd, TCGv_i64 tcg_rn, |
9411 | TCGv_i32 tcg_rmode, TCGv_ptr tcg_fpstatus) | |
effa8e06 PM |
9412 | { |
9413 | /* Handle 64->64 opcodes which are shared between the scalar and | |
9414 | * vector 2-reg-misc groups. We cover every integer opcode where size == 3 | |
f93d0138 | 9415 | * is valid in either group and also the double-precision fp ops. |
04c7c6c2 PM |
9416 | * The caller only need provide tcg_rmode and tcg_fpstatus if the op |
9417 | * requires them. | |
effa8e06 PM |
9418 | */ |
9419 | TCGCond cond; | |
9420 | ||
9421 | switch (opcode) { | |
b05c3068 AB |
9422 | case 0x4: /* CLS, CLZ */ |
9423 | if (u) { | |
7539a012 | 9424 | tcg_gen_clzi_i64(tcg_rd, tcg_rn, 64); |
b05c3068 | 9425 | } else { |
bc21dbcc | 9426 | tcg_gen_clrsb_i64(tcg_rd, tcg_rn); |
b05c3068 AB |
9427 | } |
9428 | break; | |
86cbc418 PM |
9429 | case 0x5: /* NOT */ |
9430 | /* This opcode is shared with CNT and RBIT but we have earlier | |
9431 | * enforced that size == 3 if and only if this is the NOT insn. | |
9432 | */ | |
9433 | tcg_gen_not_i64(tcg_rd, tcg_rn); | |
9434 | break; | |
0a79bc87 AB |
9435 | case 0x7: /* SQABS, SQNEG */ |
9436 | if (u) { | |
9437 | gen_helper_neon_qneg_s64(tcg_rd, cpu_env, tcg_rn); | |
9438 | } else { | |
9439 | gen_helper_neon_qabs_s64(tcg_rd, cpu_env, tcg_rn); | |
9440 | } | |
9441 | break; | |
effa8e06 PM |
9442 | case 0xa: /* CMLT */ |
9443 | /* 64 bit integer comparison against zero, result is | |
9444 | * test ? (2^64 - 1) : 0. We implement via setcond(!test) and | |
9445 | * subtracting 1. | |
9446 | */ | |
9447 | cond = TCG_COND_LT; | |
9448 | do_cmop: | |
9449 | tcg_gen_setcondi_i64(cond, tcg_rd, tcg_rn, 0); | |
9450 | tcg_gen_neg_i64(tcg_rd, tcg_rd); | |
9451 | break; | |
9452 | case 0x8: /* CMGT, CMGE */ | |
9453 | cond = u ? TCG_COND_GE : TCG_COND_GT; | |
9454 | goto do_cmop; | |
9455 | case 0x9: /* CMEQ, CMLE */ | |
9456 | cond = u ? TCG_COND_LE : TCG_COND_EQ; | |
9457 | goto do_cmop; | |
9458 | case 0xb: /* ABS, NEG */ | |
9459 | if (u) { | |
9460 | tcg_gen_neg_i64(tcg_rd, tcg_rn); | |
9461 | } else { | |
4e027a71 | 9462 | tcg_gen_abs_i64(tcg_rd, tcg_rn); |
effa8e06 PM |
9463 | } |
9464 | break; | |
f93d0138 PM |
9465 | case 0x2f: /* FABS */ |
9466 | gen_helper_vfp_absd(tcg_rd, tcg_rn); | |
9467 | break; | |
9468 | case 0x6f: /* FNEG */ | |
9469 | gen_helper_vfp_negd(tcg_rd, tcg_rn); | |
9470 | break; | |
f612537e AB |
9471 | case 0x7f: /* FSQRT */ |
9472 | gen_helper_vfp_sqrtd(tcg_rd, tcg_rn, cpu_env); | |
9473 | break; | |
04c7c6c2 PM |
9474 | case 0x1a: /* FCVTNS */ |
9475 | case 0x1b: /* FCVTMS */ | |
9476 | case 0x1c: /* FCVTAS */ | |
9477 | case 0x3a: /* FCVTPS */ | |
9478 | case 0x3b: /* FCVTZS */ | |
9479 | { | |
9480 | TCGv_i32 tcg_shift = tcg_const_i32(0); | |
9481 | gen_helper_vfp_tosqd(tcg_rd, tcg_rn, tcg_shift, tcg_fpstatus); | |
9482 | tcg_temp_free_i32(tcg_shift); | |
9483 | break; | |
9484 | } | |
9485 | case 0x5a: /* FCVTNU */ | |
9486 | case 0x5b: /* FCVTMU */ | |
9487 | case 0x5c: /* FCVTAU */ | |
9488 | case 0x7a: /* FCVTPU */ | |
9489 | case 0x7b: /* FCVTZU */ | |
9490 | { | |
9491 | TCGv_i32 tcg_shift = tcg_const_i32(0); | |
9492 | gen_helper_vfp_touqd(tcg_rd, tcg_rn, tcg_shift, tcg_fpstatus); | |
9493 | tcg_temp_free_i32(tcg_shift); | |
9494 | break; | |
9495 | } | |
03df01ed PM |
9496 | case 0x18: /* FRINTN */ |
9497 | case 0x19: /* FRINTM */ | |
9498 | case 0x38: /* FRINTP */ | |
9499 | case 0x39: /* FRINTZ */ | |
9500 | case 0x58: /* FRINTA */ | |
9501 | case 0x79: /* FRINTI */ | |
9502 | gen_helper_rintd(tcg_rd, tcg_rn, tcg_fpstatus); | |
9503 | break; | |
9504 | case 0x59: /* FRINTX */ | |
9505 | gen_helper_rintd_exact(tcg_rd, tcg_rn, tcg_fpstatus); | |
9506 | break; | |
6bea2563 RH |
9507 | case 0x1e: /* FRINT32Z */ |
9508 | case 0x5e: /* FRINT32X */ | |
9509 | gen_helper_frint32_d(tcg_rd, tcg_rn, tcg_fpstatus); | |
9510 | break; | |
9511 | case 0x1f: /* FRINT64Z */ | |
9512 | case 0x5f: /* FRINT64X */ | |
9513 | gen_helper_frint64_d(tcg_rd, tcg_rn, tcg_fpstatus); | |
9514 | break; | |
effa8e06 PM |
9515 | default: |
9516 | g_assert_not_reached(); | |
9517 | } | |
9518 | } | |
9519 | ||
8908f4d1 AB |
9520 | static void handle_2misc_fcmp_zero(DisasContext *s, int opcode, |
9521 | bool is_scalar, bool is_u, bool is_q, | |
9522 | int size, int rn, int rd) | |
9523 | { | |
7d4dd1a7 | 9524 | bool is_double = (size == MO_64); |
8c6afa6a PM |
9525 | TCGv_ptr fpst; |
9526 | ||
9527 | if (!fp_access_check(s)) { | |
9528 | return; | |
9529 | } | |
9530 | ||
7d4dd1a7 | 9531 | fpst = get_fpstatus_ptr(size == MO_16); |
8908f4d1 AB |
9532 | |
9533 | if (is_double) { | |
9534 | TCGv_i64 tcg_op = tcg_temp_new_i64(); | |
9535 | TCGv_i64 tcg_zero = tcg_const_i64(0); | |
9536 | TCGv_i64 tcg_res = tcg_temp_new_i64(); | |
5de3fd04 | 9537 | NeonGenTwoDoubleOpFn *genfn; |
8908f4d1 AB |
9538 | bool swap = false; |
9539 | int pass; | |
9540 | ||
9541 | switch (opcode) { | |
9542 | case 0x2e: /* FCMLT (zero) */ | |
9543 | swap = true; | |
9544 | /* fallthrough */ | |
9545 | case 0x2c: /* FCMGT (zero) */ | |
9546 | genfn = gen_helper_neon_cgt_f64; | |
9547 | break; | |
9548 | case 0x2d: /* FCMEQ (zero) */ | |
9549 | genfn = gen_helper_neon_ceq_f64; | |
9550 | break; | |
9551 | case 0x6d: /* FCMLE (zero) */ | |
9552 | swap = true; | |
9553 | /* fall through */ | |
9554 | case 0x6c: /* FCMGE (zero) */ | |
9555 | genfn = gen_helper_neon_cge_f64; | |
9556 | break; | |
9557 | default: | |
9558 | g_assert_not_reached(); | |
9559 | } | |
9560 | ||
9561 | for (pass = 0; pass < (is_scalar ? 1 : 2); pass++) { | |
9562 | read_vec_element(s, tcg_op, rn, pass, MO_64); | |
9563 | if (swap) { | |
9564 | genfn(tcg_res, tcg_zero, tcg_op, fpst); | |
9565 | } else { | |
9566 | genfn(tcg_res, tcg_op, tcg_zero, fpst); | |
9567 | } | |
9568 | write_vec_element(s, tcg_res, rd, pass, MO_64); | |
9569 | } | |
8908f4d1 AB |
9570 | tcg_temp_free_i64(tcg_res); |
9571 | tcg_temp_free_i64(tcg_zero); | |
9572 | tcg_temp_free_i64(tcg_op); | |
4ff55bcb RH |
9573 | |
9574 | clear_vec_high(s, !is_scalar, rd); | |
8908f4d1 AB |
9575 | } else { |
9576 | TCGv_i32 tcg_op = tcg_temp_new_i32(); | |
9577 | TCGv_i32 tcg_zero = tcg_const_i32(0); | |
9578 | TCGv_i32 tcg_res = tcg_temp_new_i32(); | |
5de3fd04 | 9579 | NeonGenTwoSingleOpFn *genfn; |
8908f4d1 AB |
9580 | bool swap = false; |
9581 | int pass, maxpasses; | |
9582 | ||
7d4dd1a7 AB |
9583 | if (size == MO_16) { |
9584 | switch (opcode) { | |
9585 | case 0x2e: /* FCMLT (zero) */ | |
9586 | swap = true; | |
9587 | /* fall through */ | |
9588 | case 0x2c: /* FCMGT (zero) */ | |
9589 | genfn = gen_helper_advsimd_cgt_f16; | |
9590 | break; | |
9591 | case 0x2d: /* FCMEQ (zero) */ | |
9592 | genfn = gen_helper_advsimd_ceq_f16; | |
9593 | break; | |
9594 | case 0x6d: /* FCMLE (zero) */ | |
9595 | swap = true; | |
9596 | /* fall through */ | |
9597 | case 0x6c: /* FCMGE (zero) */ | |
9598 | genfn = gen_helper_advsimd_cge_f16; | |
9599 | break; | |
9600 | default: | |
9601 | g_assert_not_reached(); | |
9602 | } | |
9603 | } else { | |
9604 | switch (opcode) { | |
9605 | case 0x2e: /* FCMLT (zero) */ | |
9606 | swap = true; | |
9607 | /* fall through */ | |
9608 | case 0x2c: /* FCMGT (zero) */ | |
9609 | genfn = gen_helper_neon_cgt_f32; | |
9610 | break; | |
9611 | case 0x2d: /* FCMEQ (zero) */ | |
9612 | genfn = gen_helper_neon_ceq_f32; | |
9613 | break; | |
9614 | case 0x6d: /* FCMLE (zero) */ | |
9615 | swap = true; | |
9616 | /* fall through */ | |
9617 | case 0x6c: /* FCMGE (zero) */ | |
9618 | genfn = gen_helper_neon_cge_f32; | |
9619 | break; | |
9620 | default: | |
9621 | g_assert_not_reached(); | |
9622 | } | |
8908f4d1 AB |
9623 | } |
9624 | ||
9625 | if (is_scalar) { | |
9626 | maxpasses = 1; | |
9627 | } else { | |
7d4dd1a7 AB |
9628 | int vector_size = 8 << is_q; |
9629 | maxpasses = vector_size >> size; | |
8908f4d1 AB |
9630 | } |
9631 | ||
9632 | for (pass = 0; pass < maxpasses; pass++) { | |
7d4dd1a7 | 9633 | read_vec_element_i32(s, tcg_op, rn, pass, size); |
8908f4d1 AB |
9634 | if (swap) { |
9635 | genfn(tcg_res, tcg_zero, tcg_op, fpst); | |
9636 | } else { | |
9637 | genfn(tcg_res, tcg_op, tcg_zero, fpst); | |
9638 | } | |
9639 | if (is_scalar) { | |
9640 | write_fp_sreg(s, rd, tcg_res); | |
9641 | } else { | |
7d4dd1a7 | 9642 | write_vec_element_i32(s, tcg_res, rd, pass, size); |
8908f4d1 AB |
9643 | } |
9644 | } | |
9645 | tcg_temp_free_i32(tcg_res); | |
9646 | tcg_temp_free_i32(tcg_zero); | |
9647 | tcg_temp_free_i32(tcg_op); | |
4ff55bcb RH |
9648 | if (!is_scalar) { |
9649 | clear_vec_high(s, is_q, rd); | |
8908f4d1 AB |
9650 | } |
9651 | } | |
9652 | ||
9653 | tcg_temp_free_ptr(fpst); | |
9654 | } | |
9655 | ||
8f0c6758 AB |
9656 | static void handle_2misc_reciprocal(DisasContext *s, int opcode, |
9657 | bool is_scalar, bool is_u, bool is_q, | |
9658 | int size, int rn, int rd) | |
9659 | { | |
9660 | bool is_double = (size == 3); | |
d81ce0ef | 9661 | TCGv_ptr fpst = get_fpstatus_ptr(false); |
8f0c6758 AB |
9662 | |
9663 | if (is_double) { | |
9664 | TCGv_i64 tcg_op = tcg_temp_new_i64(); | |
9665 | TCGv_i64 tcg_res = tcg_temp_new_i64(); | |
9666 | int pass; | |
9667 | ||
9668 | for (pass = 0; pass < (is_scalar ? 1 : 2); pass++) { | |
9669 | read_vec_element(s, tcg_op, rn, pass, MO_64); | |
9670 | switch (opcode) { | |
b6d4443a AB |
9671 | case 0x3d: /* FRECPE */ |
9672 | gen_helper_recpe_f64(tcg_res, tcg_op, fpst); | |
9673 | break; | |
8f0c6758 AB |
9674 | case 0x3f: /* FRECPX */ |
9675 | gen_helper_frecpx_f64(tcg_res, tcg_op, fpst); | |
9676 | break; | |
c2fb418e AB |
9677 | case 0x7d: /* FRSQRTE */ |
9678 | gen_helper_rsqrte_f64(tcg_res, tcg_op, fpst); | |
9679 | break; | |
8f0c6758 AB |
9680 | default: |
9681 | g_assert_not_reached(); | |
9682 | } | |
9683 | write_vec_element(s, tcg_res, rd, pass, MO_64); | |
9684 | } | |
8f0c6758 AB |
9685 | tcg_temp_free_i64(tcg_res); |
9686 | tcg_temp_free_i64(tcg_op); | |
4ff55bcb | 9687 | clear_vec_high(s, !is_scalar, rd); |
8f0c6758 AB |
9688 | } else { |
9689 | TCGv_i32 tcg_op = tcg_temp_new_i32(); | |
9690 | TCGv_i32 tcg_res = tcg_temp_new_i32(); | |
9691 | int pass, maxpasses; | |
9692 | ||
9693 | if (is_scalar) { | |
9694 | maxpasses = 1; | |
9695 | } else { | |
9696 | maxpasses = is_q ? 4 : 2; | |
9697 | } | |
9698 | ||
9699 | for (pass = 0; pass < maxpasses; pass++) { | |
9700 | read_vec_element_i32(s, tcg_op, rn, pass, MO_32); | |
9701 | ||
9702 | switch (opcode) { | |
b6d4443a | 9703 | case 0x3c: /* URECPE */ |
fe6fb4be | 9704 | gen_helper_recpe_u32(tcg_res, tcg_op); |
b6d4443a AB |
9705 | break; |
9706 | case 0x3d: /* FRECPE */ | |
9707 | gen_helper_recpe_f32(tcg_res, tcg_op, fpst); | |
9708 | break; | |
8f0c6758 AB |
9709 | case 0x3f: /* FRECPX */ |
9710 | gen_helper_frecpx_f32(tcg_res, tcg_op, fpst); | |
9711 | break; | |
c2fb418e AB |
9712 | case 0x7d: /* FRSQRTE */ |
9713 | gen_helper_rsqrte_f32(tcg_res, tcg_op, fpst); | |
9714 | break; | |
8f0c6758 AB |
9715 | default: |
9716 | g_assert_not_reached(); | |
9717 | } | |
9718 | ||
9719 | if (is_scalar) { | |
9720 | write_fp_sreg(s, rd, tcg_res); | |
9721 | } else { | |
9722 | write_vec_element_i32(s, tcg_res, rd, pass, MO_32); | |
9723 | } | |
9724 | } | |
9725 | tcg_temp_free_i32(tcg_res); | |
9726 | tcg_temp_free_i32(tcg_op); | |
4ff55bcb RH |
9727 | if (!is_scalar) { |
9728 | clear_vec_high(s, is_q, rd); | |
8f0c6758 AB |
9729 | } |
9730 | } | |
9731 | tcg_temp_free_ptr(fpst); | |
9732 | } | |
9733 | ||
5201c136 AB |
9734 | static void handle_2misc_narrow(DisasContext *s, bool scalar, |
9735 | int opcode, bool u, bool is_q, | |
8b092ca9 AB |
9736 | int size, int rn, int rd) |
9737 | { | |
9738 | /* Handle 2-reg-misc ops which are narrowing (so each 2*size element | |
9739 | * in the source becomes a size element in the destination). | |
9740 | */ | |
9741 | int pass; | |
9742 | TCGv_i32 tcg_res[2]; | |
9743 | int destelt = is_q ? 2 : 0; | |
5201c136 | 9744 | int passes = scalar ? 1 : 2; |
8b092ca9 | 9745 | |
5201c136 AB |
9746 | if (scalar) { |
9747 | tcg_res[1] = tcg_const_i32(0); | |
9748 | } | |
9749 | ||
9750 | for (pass = 0; pass < passes; pass++) { | |
8b092ca9 AB |
9751 | TCGv_i64 tcg_op = tcg_temp_new_i64(); |
9752 | NeonGenNarrowFn *genfn = NULL; | |
9753 | NeonGenNarrowEnvFn *genenvfn = NULL; | |
9754 | ||
5201c136 AB |
9755 | if (scalar) { |
9756 | read_vec_element(s, tcg_op, rn, pass, size + 1); | |
9757 | } else { | |
9758 | read_vec_element(s, tcg_op, rn, pass, MO_64); | |
9759 | } | |
8b092ca9 AB |
9760 | tcg_res[pass] = tcg_temp_new_i32(); |
9761 | ||
9762 | switch (opcode) { | |
9763 | case 0x12: /* XTN, SQXTUN */ | |
9764 | { | |
9765 | static NeonGenNarrowFn * const xtnfns[3] = { | |
9766 | gen_helper_neon_narrow_u8, | |
9767 | gen_helper_neon_narrow_u16, | |
ecc7b3aa | 9768 | tcg_gen_extrl_i64_i32, |
8b092ca9 AB |
9769 | }; |
9770 | static NeonGenNarrowEnvFn * const sqxtunfns[3] = { | |
9771 | gen_helper_neon_unarrow_sat8, | |
9772 | gen_helper_neon_unarrow_sat16, | |
9773 | gen_helper_neon_unarrow_sat32, | |
9774 | }; | |
9775 | if (u) { | |
9776 | genenvfn = sqxtunfns[size]; | |
9777 | } else { | |
9778 | genfn = xtnfns[size]; | |
9779 | } | |
9780 | break; | |
9781 | } | |
9782 | case 0x14: /* SQXTN, UQXTN */ | |
9783 | { | |
9784 | static NeonGenNarrowEnvFn * const fns[3][2] = { | |
9785 | { gen_helper_neon_narrow_sat_s8, | |
9786 | gen_helper_neon_narrow_sat_u8 }, | |
9787 | { gen_helper_neon_narrow_sat_s16, | |
9788 | gen_helper_neon_narrow_sat_u16 }, | |
9789 | { gen_helper_neon_narrow_sat_s32, | |
9790 | gen_helper_neon_narrow_sat_u32 }, | |
9791 | }; | |
9792 | genenvfn = fns[size][u]; | |
9793 | break; | |
9794 | } | |
9795 | case 0x16: /* FCVTN, FCVTN2 */ | |
9796 | /* 32 bit to 16 bit or 64 bit to 32 bit float conversion */ | |
9797 | if (size == 2) { | |
9798 | gen_helper_vfp_fcvtsd(tcg_res[pass], tcg_op, cpu_env); | |
9799 | } else { | |
9800 | TCGv_i32 tcg_lo = tcg_temp_new_i32(); | |
9801 | TCGv_i32 tcg_hi = tcg_temp_new_i32(); | |
486624fc AB |
9802 | TCGv_ptr fpst = get_fpstatus_ptr(false); |
9803 | TCGv_i32 ahp = get_ahp_flag(); | |
9804 | ||
7cb36e18 | 9805 | tcg_gen_extr_i64_i32(tcg_lo, tcg_hi, tcg_op); |
486624fc AB |
9806 | gen_helper_vfp_fcvt_f32_to_f16(tcg_lo, tcg_lo, fpst, ahp); |
9807 | gen_helper_vfp_fcvt_f32_to_f16(tcg_hi, tcg_hi, fpst, ahp); | |
8b092ca9 AB |
9808 | tcg_gen_deposit_i32(tcg_res[pass], tcg_lo, tcg_hi, 16, 16); |
9809 | tcg_temp_free_i32(tcg_lo); | |
9810 | tcg_temp_free_i32(tcg_hi); | |
486624fc AB |
9811 | tcg_temp_free_ptr(fpst); |
9812 | tcg_temp_free_i32(ahp); | |
8b092ca9 AB |
9813 | } |
9814 | break; | |
5553955e PM |
9815 | case 0x56: /* FCVTXN, FCVTXN2 */ |
9816 | /* 64 bit to 32 bit float conversion | |
9817 | * with von Neumann rounding (round to odd) | |
9818 | */ | |
9819 | assert(size == 2); | |
9820 | gen_helper_fcvtx_f64_to_f32(tcg_res[pass], tcg_op, cpu_env); | |
9821 | break; | |
8b092ca9 AB |
9822 | default: |
9823 | g_assert_not_reached(); | |
9824 | } | |
9825 | ||
9826 | if (genfn) { | |
9827 | genfn(tcg_res[pass], tcg_op); | |
9828 | } else if (genenvfn) { | |
9829 | genenvfn(tcg_res[pass], cpu_env, tcg_op); | |
9830 | } | |
9831 | ||
9832 | tcg_temp_free_i64(tcg_op); | |
9833 | } | |
9834 | ||
9835 | for (pass = 0; pass < 2; pass++) { | |
9836 | write_vec_element_i32(s, tcg_res[pass], rd, destelt + pass, MO_32); | |
9837 | tcg_temp_free_i32(tcg_res[pass]); | |
9838 | } | |
4ff55bcb | 9839 | clear_vec_high(s, is_q, rd); |
8b092ca9 AB |
9840 | } |
9841 | ||
09e03735 AB |
9842 | /* Remaining saturating accumulating ops */ |
9843 | static void handle_2misc_satacc(DisasContext *s, bool is_scalar, bool is_u, | |
9844 | bool is_q, int size, int rn, int rd) | |
9845 | { | |
9846 | bool is_double = (size == 3); | |
9847 | ||
9848 | if (is_double) { | |
9849 | TCGv_i64 tcg_rn = tcg_temp_new_i64(); | |
9850 | TCGv_i64 tcg_rd = tcg_temp_new_i64(); | |
9851 | int pass; | |
9852 | ||
9853 | for (pass = 0; pass < (is_scalar ? 1 : 2); pass++) { | |
9854 | read_vec_element(s, tcg_rn, rn, pass, MO_64); | |
9855 | read_vec_element(s, tcg_rd, rd, pass, MO_64); | |
9856 | ||
9857 | if (is_u) { /* USQADD */ | |
9858 | gen_helper_neon_uqadd_s64(tcg_rd, cpu_env, tcg_rn, tcg_rd); | |
9859 | } else { /* SUQADD */ | |
9860 | gen_helper_neon_sqadd_u64(tcg_rd, cpu_env, tcg_rn, tcg_rd); | |
9861 | } | |
9862 | write_vec_element(s, tcg_rd, rd, pass, MO_64); | |
9863 | } | |
09e03735 AB |
9864 | tcg_temp_free_i64(tcg_rd); |
9865 | tcg_temp_free_i64(tcg_rn); | |
4ff55bcb | 9866 | clear_vec_high(s, !is_scalar, rd); |
09e03735 AB |
9867 | } else { |
9868 | TCGv_i32 tcg_rn = tcg_temp_new_i32(); | |
9869 | TCGv_i32 tcg_rd = tcg_temp_new_i32(); | |
9870 | int pass, maxpasses; | |
9871 | ||
9872 | if (is_scalar) { | |
9873 | maxpasses = 1; | |
9874 | } else { | |
9875 | maxpasses = is_q ? 4 : 2; | |
9876 | } | |
9877 | ||
9878 | for (pass = 0; pass < maxpasses; pass++) { | |
9879 | if (is_scalar) { | |
9880 | read_vec_element_i32(s, tcg_rn, rn, pass, size); | |
9881 | read_vec_element_i32(s, tcg_rd, rd, pass, size); | |
9882 | } else { | |
9883 | read_vec_element_i32(s, tcg_rn, rn, pass, MO_32); | |
9884 | read_vec_element_i32(s, tcg_rd, rd, pass, MO_32); | |
9885 | } | |
9886 | ||
9887 | if (is_u) { /* USQADD */ | |
9888 | switch (size) { | |
9889 | case 0: | |
9890 | gen_helper_neon_uqadd_s8(tcg_rd, cpu_env, tcg_rn, tcg_rd); | |
9891 | break; | |
9892 | case 1: | |
9893 | gen_helper_neon_uqadd_s16(tcg_rd, cpu_env, tcg_rn, tcg_rd); | |
9894 | break; | |
9895 | case 2: | |
9896 | gen_helper_neon_uqadd_s32(tcg_rd, cpu_env, tcg_rn, tcg_rd); | |
9897 | break; | |
9898 | default: | |
9899 | g_assert_not_reached(); | |
9900 | } | |
9901 | } else { /* SUQADD */ | |
9902 | switch (size) { | |
9903 | case 0: | |
9904 | gen_helper_neon_sqadd_u8(tcg_rd, cpu_env, tcg_rn, tcg_rd); | |
9905 | break; | |
9906 | case 1: | |
9907 | gen_helper_neon_sqadd_u16(tcg_rd, cpu_env, tcg_rn, tcg_rd); | |
9908 | break; | |
9909 | case 2: | |
9910 | gen_helper_neon_sqadd_u32(tcg_rd, cpu_env, tcg_rn, tcg_rd); | |
9911 | break; | |
9912 | default: | |
9913 | g_assert_not_reached(); | |
9914 | } | |
9915 | } | |
9916 | ||
9917 | if (is_scalar) { | |
9918 | TCGv_i64 tcg_zero = tcg_const_i64(0); | |
9919 | write_vec_element(s, tcg_zero, rd, 0, MO_64); | |
9920 | tcg_temp_free_i64(tcg_zero); | |
9921 | } | |
9922 | write_vec_element_i32(s, tcg_rd, rd, pass, MO_32); | |
9923 | } | |
09e03735 AB |
9924 | tcg_temp_free_i32(tcg_rd); |
9925 | tcg_temp_free_i32(tcg_rn); | |
4ff55bcb | 9926 | clear_vec_high(s, is_q, rd); |
09e03735 AB |
9927 | } |
9928 | } | |
9929 | ||
4ce31af4 | 9930 | /* AdvSIMD scalar two reg misc |
384b26fb AB |
9931 | * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0 |
9932 | * +-----+---+-----------+------+-----------+--------+-----+------+------+ | |
9933 | * | 0 1 | U | 1 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd | | |
9934 | * +-----+---+-----------+------+-----------+--------+-----+------+------+ | |
9935 | */ | |
9936 | static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn) | |
9937 | { | |
effa8e06 PM |
9938 | int rd = extract32(insn, 0, 5); |
9939 | int rn = extract32(insn, 5, 5); | |
9940 | int opcode = extract32(insn, 12, 5); | |
9941 | int size = extract32(insn, 22, 2); | |
9942 | bool u = extract32(insn, 29, 1); | |
04c7c6c2 PM |
9943 | bool is_fcvt = false; |
9944 | int rmode; | |
9945 | TCGv_i32 tcg_rmode; | |
9946 | TCGv_ptr tcg_fpstatus; | |
effa8e06 PM |
9947 | |
9948 | switch (opcode) { | |
09e03735 | 9949 | case 0x3: /* USQADD / SUQADD*/ |
8c6afa6a PM |
9950 | if (!fp_access_check(s)) { |
9951 | return; | |
9952 | } | |
09e03735 AB |
9953 | handle_2misc_satacc(s, true, u, false, size, rn, rd); |
9954 | return; | |
0a79bc87 AB |
9955 | case 0x7: /* SQABS / SQNEG */ |
9956 | break; | |
effa8e06 PM |
9957 | case 0xa: /* CMLT */ |
9958 | if (u) { | |
9959 | unallocated_encoding(s); | |
9960 | return; | |
9961 | } | |
9962 | /* fall through */ | |
9963 | case 0x8: /* CMGT, CMGE */ | |
9964 | case 0x9: /* CMEQ, CMLE */ | |
9965 | case 0xb: /* ABS, NEG */ | |
9966 | if (size != 3) { | |
9967 | unallocated_encoding(s); | |
9968 | return; | |
9969 | } | |
9970 | break; | |
5201c136 | 9971 | case 0x12: /* SQXTUN */ |
e44a90c5 | 9972 | if (!u) { |
5201c136 AB |
9973 | unallocated_encoding(s); |
9974 | return; | |
9975 | } | |
9976 | /* fall through */ | |
9977 | case 0x14: /* SQXTN, UQXTN */ | |
9978 | if (size == 3) { | |
9979 | unallocated_encoding(s); | |
9980 | return; | |
9981 | } | |
8c6afa6a PM |
9982 | if (!fp_access_check(s)) { |
9983 | return; | |
9984 | } | |
5201c136 AB |
9985 | handle_2misc_narrow(s, true, opcode, u, false, size, rn, rd); |
9986 | return; | |
8908f4d1 AB |
9987 | case 0xc ... 0xf: |
9988 | case 0x16 ... 0x1d: | |
9989 | case 0x1f: | |
9990 | /* Floating point: U, size[1] and opcode indicate operation; | |
9991 | * size[0] indicates single or double precision. | |
9992 | */ | |
9993 | opcode |= (extract32(size, 1, 1) << 5) | (u << 6); | |
9994 | size = extract32(size, 0, 1) ? 3 : 2; | |
9995 | switch (opcode) { | |
9996 | case 0x2c: /* FCMGT (zero) */ | |
9997 | case 0x2d: /* FCMEQ (zero) */ | |
9998 | case 0x2e: /* FCMLT (zero) */ | |
9999 | case 0x6c: /* FCMGE (zero) */ | |
10000 | case 0x6d: /* FCMLE (zero) */ | |
10001 | handle_2misc_fcmp_zero(s, opcode, true, u, true, size, rn, rd); | |
10002 | return; | |
10113b69 AB |
10003 | case 0x1d: /* SCVTF */ |
10004 | case 0x5d: /* UCVTF */ | |
10005 | { | |
10006 | bool is_signed = (opcode == 0x1d); | |
8c6afa6a PM |
10007 | if (!fp_access_check(s)) { |
10008 | return; | |
10009 | } | |
10113b69 AB |
10010 | handle_simd_intfp_conv(s, rd, rn, 1, is_signed, 0, size); |
10011 | return; | |
10012 | } | |
b6d4443a | 10013 | case 0x3d: /* FRECPE */ |
8f0c6758 | 10014 | case 0x3f: /* FRECPX */ |
c2fb418e | 10015 | case 0x7d: /* FRSQRTE */ |
8c6afa6a PM |
10016 | if (!fp_access_check(s)) { |
10017 | return; | |
10018 | } | |
8f0c6758 AB |
10019 | handle_2misc_reciprocal(s, opcode, true, u, true, size, rn, rd); |
10020 | return; | |
8908f4d1 AB |
10021 | case 0x1a: /* FCVTNS */ |
10022 | case 0x1b: /* FCVTMS */ | |
8908f4d1 AB |
10023 | case 0x3a: /* FCVTPS */ |
10024 | case 0x3b: /* FCVTZS */ | |
8908f4d1 AB |
10025 | case 0x5a: /* FCVTNU */ |
10026 | case 0x5b: /* FCVTMU */ | |
8908f4d1 AB |
10027 | case 0x7a: /* FCVTPU */ |
10028 | case 0x7b: /* FCVTZU */ | |
04c7c6c2 PM |
10029 | is_fcvt = true; |
10030 | rmode = extract32(opcode, 5, 1) | (extract32(opcode, 0, 1) << 1); | |
10031 | break; | |
10032 | case 0x1c: /* FCVTAS */ | |
10033 | case 0x5c: /* FCVTAU */ | |
10034 | /* TIEAWAY doesn't fit in the usual rounding mode encoding */ | |
10035 | is_fcvt = true; | |
10036 | rmode = FPROUNDING_TIEAWAY; | |
10037 | break; | |
04c7c6c2 | 10038 | case 0x56: /* FCVTXN, FCVTXN2 */ |
5553955e PM |
10039 | if (size == 2) { |
10040 | unallocated_encoding(s); | |
10041 | return; | |
10042 | } | |
8c6afa6a PM |
10043 | if (!fp_access_check(s)) { |
10044 | return; | |
10045 | } | |
5553955e PM |
10046 | handle_2misc_narrow(s, true, opcode, u, false, size - 1, rn, rd); |
10047 | return; | |
8908f4d1 AB |
10048 | default: |
10049 | unallocated_encoding(s); | |
10050 | return; | |
10051 | } | |
10052 | break; | |
effa8e06 | 10053 | default: |
09e03735 | 10054 | unallocated_encoding(s); |
effa8e06 PM |
10055 | return; |
10056 | } | |
10057 | ||
8c6afa6a PM |
10058 | if (!fp_access_check(s)) { |
10059 | return; | |
10060 | } | |
10061 | ||
04c7c6c2 PM |
10062 | if (is_fcvt) { |
10063 | tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode)); | |
d81ce0ef | 10064 | tcg_fpstatus = get_fpstatus_ptr(false); |
9b049916 | 10065 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); |
04c7c6c2 | 10066 | } else { |
f764718d RH |
10067 | tcg_rmode = NULL; |
10068 | tcg_fpstatus = NULL; | |
04c7c6c2 PM |
10069 | } |
10070 | ||
effa8e06 PM |
10071 | if (size == 3) { |
10072 | TCGv_i64 tcg_rn = read_fp_dreg(s, rn); | |
10073 | TCGv_i64 tcg_rd = tcg_temp_new_i64(); | |
10074 | ||
04c7c6c2 | 10075 | handle_2misc_64(s, opcode, u, tcg_rd, tcg_rn, tcg_rmode, tcg_fpstatus); |
effa8e06 PM |
10076 | write_fp_dreg(s, rd, tcg_rd); |
10077 | tcg_temp_free_i64(tcg_rd); | |
10078 | tcg_temp_free_i64(tcg_rn); | |
0a79bc87 AB |
10079 | } else { |
10080 | TCGv_i32 tcg_rn = tcg_temp_new_i32(); | |
04c7c6c2 PM |
10081 | TCGv_i32 tcg_rd = tcg_temp_new_i32(); |
10082 | ||
0a79bc87 AB |
10083 | read_vec_element_i32(s, tcg_rn, rn, 0, size); |
10084 | ||
04c7c6c2 | 10085 | switch (opcode) { |
0a79bc87 AB |
10086 | case 0x7: /* SQABS, SQNEG */ |
10087 | { | |
10088 | NeonGenOneOpEnvFn *genfn; | |
10089 | static NeonGenOneOpEnvFn * const fns[3][2] = { | |
10090 | { gen_helper_neon_qabs_s8, gen_helper_neon_qneg_s8 }, | |
10091 | { gen_helper_neon_qabs_s16, gen_helper_neon_qneg_s16 }, | |
10092 | { gen_helper_neon_qabs_s32, gen_helper_neon_qneg_s32 }, | |
10093 | }; | |
10094 | genfn = fns[size][u]; | |
10095 | genfn(tcg_rd, cpu_env, tcg_rn); | |
10096 | break; | |
10097 | } | |
04c7c6c2 PM |
10098 | case 0x1a: /* FCVTNS */ |
10099 | case 0x1b: /* FCVTMS */ | |
10100 | case 0x1c: /* FCVTAS */ | |
10101 | case 0x3a: /* FCVTPS */ | |
10102 | case 0x3b: /* FCVTZS */ | |
10103 | { | |
10104 | TCGv_i32 tcg_shift = tcg_const_i32(0); | |
10105 | gen_helper_vfp_tosls(tcg_rd, tcg_rn, tcg_shift, tcg_fpstatus); | |
10106 | tcg_temp_free_i32(tcg_shift); | |
10107 | break; | |
10108 | } | |
10109 | case 0x5a: /* FCVTNU */ | |
10110 | case 0x5b: /* FCVTMU */ | |
10111 | case 0x5c: /* FCVTAU */ | |
10112 | case 0x7a: /* FCVTPU */ | |
10113 | case 0x7b: /* FCVTZU */ | |
10114 | { | |
10115 | TCGv_i32 tcg_shift = tcg_const_i32(0); | |
10116 | gen_helper_vfp_touls(tcg_rd, tcg_rn, tcg_shift, tcg_fpstatus); | |
10117 | tcg_temp_free_i32(tcg_shift); | |
10118 | break; | |
10119 | } | |
10120 | default: | |
10121 | g_assert_not_reached(); | |
10122 | } | |
10123 | ||
10124 | write_fp_sreg(s, rd, tcg_rd); | |
10125 | tcg_temp_free_i32(tcg_rd); | |
10126 | tcg_temp_free_i32(tcg_rn); | |
effa8e06 | 10127 | } |
04c7c6c2 PM |
10128 | |
10129 | if (is_fcvt) { | |
9b049916 | 10130 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); |
04c7c6c2 PM |
10131 | tcg_temp_free_i32(tcg_rmode); |
10132 | tcg_temp_free_ptr(tcg_fpstatus); | |
10133 | } | |
384b26fb AB |
10134 | } |
10135 | ||
4d1cef84 AB |
10136 | /* SSHR[RA]/USHR[RA] - Vector shift right (optional rounding/accumulate) */ |
10137 | static void handle_vec_simd_shri(DisasContext *s, bool is_q, bool is_u, | |
10138 | int immh, int immb, int opcode, int rn, int rd) | |
10139 | { | |
10140 | int size = 32 - clz32(immh) - 1; | |
10141 | int immhb = immh << 3 | immb; | |
10142 | int shift = 2 * (8 << size) - immhb; | |
3f08f0bc | 10143 | GVecGen2iFn *gvec_fn; |
4d1cef84 AB |
10144 | |
10145 | if (extract32(immh, 3, 1) && !is_q) { | |
10146 | unallocated_encoding(s); | |
10147 | return; | |
10148 | } | |
8dae4697 | 10149 | tcg_debug_assert(size <= 3); |
4d1cef84 | 10150 | |
8c6afa6a PM |
10151 | if (!fp_access_check(s)) { |
10152 | return; | |
10153 | } | |
10154 | ||
4d1cef84 AB |
10155 | switch (opcode) { |
10156 | case 0x02: /* SSRA / USRA (accumulate) */ | |
3f08f0bc RH |
10157 | gvec_fn = is_u ? gen_gvec_usra : gen_gvec_ssra; |
10158 | break; | |
893ab054 | 10159 | |
cdb45a60 | 10160 | case 0x08: /* SRI */ |
3f08f0bc RH |
10161 | gvec_fn = gen_gvec_sri; |
10162 | break; | |
cdb45a60 RH |
10163 | |
10164 | case 0x00: /* SSHR / USHR */ | |
10165 | if (is_u) { | |
10166 | if (shift == 8 << size) { | |
10167 | /* Shift count the same size as element size produces zero. */ | |
8711e71f RH |
10168 | tcg_gen_gvec_dup_imm(size, vec_full_reg_offset(s, rd), |
10169 | is_q ? 16 : 8, vec_full_reg_size(s), 0); | |
3f08f0bc | 10170 | return; |
cdb45a60 | 10171 | } |
3f08f0bc | 10172 | gvec_fn = tcg_gen_gvec_shri; |
cdb45a60 RH |
10173 | } else { |
10174 | /* Shift count the same size as element size produces all sign. */ | |
10175 | if (shift == 8 << size) { | |
10176 | shift -= 1; | |
10177 | } | |
3f08f0bc | 10178 | gvec_fn = tcg_gen_gvec_sari; |
cdb45a60 | 10179 | } |
3f08f0bc | 10180 | break; |
cdb45a60 | 10181 | |
4d1cef84 | 10182 | case 0x04: /* SRSHR / URSHR (rounding) */ |
3f08f0bc RH |
10183 | gvec_fn = is_u ? gen_gvec_urshr : gen_gvec_srshr; |
10184 | break; | |
6ccd48d4 | 10185 | |
4d1cef84 | 10186 | case 0x06: /* SRSRA / URSRA (accum + rounding) */ |
3f08f0bc RH |
10187 | gvec_fn = is_u ? gen_gvec_ursra : gen_gvec_srsra; |
10188 | break; | |
6ccd48d4 | 10189 | |
cdb45a60 RH |
10190 | default: |
10191 | g_assert_not_reached(); | |
4d1cef84 AB |
10192 | } |
10193 | ||
3f08f0bc | 10194 | gen_gvec_fn2i(s, is_q, rd, rn, shift, gvec_fn, size); |
cdb45a60 | 10195 | } |
4d1cef84 | 10196 | |
4d1cef84 AB |
10197 | /* SHL/SLI - Vector shift left */ |
10198 | static void handle_vec_simd_shli(DisasContext *s, bool is_q, bool insert, | |
cdb45a60 | 10199 | int immh, int immb, int opcode, int rn, int rd) |
4d1cef84 AB |
10200 | { |
10201 | int size = 32 - clz32(immh) - 1; | |
10202 | int immhb = immh << 3 | immb; | |
10203 | int shift = immhb - (8 << size); | |
4d1cef84 | 10204 | |
f6c98f91 PM |
10205 | /* Range of size is limited by decode: immh is a non-zero 4 bit field */ |
10206 | assert(size >= 0 && size <= 3); | |
4d1cef84 | 10207 | |
f6c98f91 | 10208 | if (extract32(immh, 3, 1) && !is_q) { |
4d1cef84 AB |
10209 | unallocated_encoding(s); |
10210 | return; | |
10211 | } | |
10212 | ||
8c6afa6a PM |
10213 | if (!fp_access_check(s)) { |
10214 | return; | |
10215 | } | |
10216 | ||
cdb45a60 | 10217 | if (insert) { |
893ab054 | 10218 | gen_gvec_fn2i(s, is_q, rd, rn, shift, gen_gvec_sli, size); |
cdb45a60 RH |
10219 | } else { |
10220 | gen_gvec_fn2i(s, is_q, rd, rn, shift, tcg_gen_gvec_shli, size); | |
4d1cef84 AB |
10221 | } |
10222 | } | |
10223 | ||
10224 | /* USHLL/SHLL - Vector shift left with widening */ | |
10225 | static void handle_vec_simd_wshli(DisasContext *s, bool is_q, bool is_u, | |
10226 | int immh, int immb, int opcode, int rn, int rd) | |
10227 | { | |
10228 | int size = 32 - clz32(immh) - 1; | |
10229 | int immhb = immh << 3 | immb; | |
10230 | int shift = immhb - (8 << size); | |
10231 | int dsize = 64; | |
10232 | int esize = 8 << size; | |
10233 | int elements = dsize/esize; | |
10234 | TCGv_i64 tcg_rn = new_tmp_a64(s); | |
10235 | TCGv_i64 tcg_rd = new_tmp_a64(s); | |
10236 | int i; | |
10237 | ||
10238 | if (size >= 3) { | |
10239 | unallocated_encoding(s); | |
10240 | return; | |
10241 | } | |
10242 | ||
8c6afa6a PM |
10243 | if (!fp_access_check(s)) { |
10244 | return; | |
10245 | } | |
10246 | ||
4d1cef84 AB |
10247 | /* For the LL variants the store is larger than the load, |
10248 | * so if rd == rn we would overwrite parts of our input. | |
10249 | * So load everything right now and use shifts in the main loop. | |
10250 | */ | |
10251 | read_vec_element(s, tcg_rn, rn, is_q ? 1 : 0, MO_64); | |
10252 | ||
10253 | for (i = 0; i < elements; i++) { | |
10254 | tcg_gen_shri_i64(tcg_rd, tcg_rn, i * esize); | |
10255 | ext_and_shift_reg(tcg_rd, tcg_rd, size | (!is_u << 2), 0); | |
10256 | tcg_gen_shli_i64(tcg_rd, tcg_rd, shift); | |
10257 | write_vec_element(s, tcg_rd, rd, i, size + 1); | |
10258 | } | |
10259 | } | |
10260 | ||
c1b876b2 AB |
10261 | /* SHRN/RSHRN - Shift right with narrowing (and potential rounding) */ |
10262 | static void handle_vec_simd_shrn(DisasContext *s, bool is_q, | |
10263 | int immh, int immb, int opcode, int rn, int rd) | |
10264 | { | |
10265 | int immhb = immh << 3 | immb; | |
10266 | int size = 32 - clz32(immh) - 1; | |
10267 | int dsize = 64; | |
10268 | int esize = 8 << size; | |
10269 | int elements = dsize/esize; | |
10270 | int shift = (2 * esize) - immhb; | |
10271 | bool round = extract32(opcode, 0, 1); | |
10272 | TCGv_i64 tcg_rn, tcg_rd, tcg_final; | |
10273 | TCGv_i64 tcg_round; | |
10274 | int i; | |
10275 | ||
10276 | if (extract32(immh, 3, 1)) { | |
10277 | unallocated_encoding(s); | |
10278 | return; | |
10279 | } | |
10280 | ||
8c6afa6a PM |
10281 | if (!fp_access_check(s)) { |
10282 | return; | |
10283 | } | |
10284 | ||
c1b876b2 AB |
10285 | tcg_rn = tcg_temp_new_i64(); |
10286 | tcg_rd = tcg_temp_new_i64(); | |
10287 | tcg_final = tcg_temp_new_i64(); | |
10288 | read_vec_element(s, tcg_final, rd, is_q ? 1 : 0, MO_64); | |
10289 | ||
10290 | if (round) { | |
10291 | uint64_t round_const = 1ULL << (shift - 1); | |
10292 | tcg_round = tcg_const_i64(round_const); | |
10293 | } else { | |
f764718d | 10294 | tcg_round = NULL; |
c1b876b2 AB |
10295 | } |
10296 | ||
10297 | for (i = 0; i < elements; i++) { | |
10298 | read_vec_element(s, tcg_rn, rn, i, size+1); | |
10299 | handle_shri_with_rndacc(tcg_rd, tcg_rn, tcg_round, | |
10300 | false, true, size+1, shift); | |
10301 | ||
10302 | tcg_gen_deposit_i64(tcg_final, tcg_final, tcg_rd, esize * i, esize); | |
10303 | } | |
10304 | ||
10305 | if (!is_q) { | |
c1b876b2 AB |
10306 | write_vec_element(s, tcg_final, rd, 0, MO_64); |
10307 | } else { | |
10308 | write_vec_element(s, tcg_final, rd, 1, MO_64); | |
10309 | } | |
c1b876b2 AB |
10310 | if (round) { |
10311 | tcg_temp_free_i64(tcg_round); | |
10312 | } | |
10313 | tcg_temp_free_i64(tcg_rn); | |
10314 | tcg_temp_free_i64(tcg_rd); | |
10315 | tcg_temp_free_i64(tcg_final); | |
4ff55bcb RH |
10316 | |
10317 | clear_vec_high(s, is_q, rd); | |
c1b876b2 AB |
10318 | } |
10319 | ||
10320 | ||
4ce31af4 | 10321 | /* AdvSIMD shift by immediate |
384b26fb AB |
10322 | * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0 |
10323 | * +---+---+---+-------------+------+------+--------+---+------+------+ | |
10324 | * | 0 | Q | U | 0 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd | | |
10325 | * +---+---+---+-------------+------+------+--------+---+------+------+ | |
10326 | */ | |
10327 | static void disas_simd_shift_imm(DisasContext *s, uint32_t insn) | |
10328 | { | |
4d1cef84 AB |
10329 | int rd = extract32(insn, 0, 5); |
10330 | int rn = extract32(insn, 5, 5); | |
10331 | int opcode = extract32(insn, 11, 5); | |
10332 | int immb = extract32(insn, 16, 3); | |
10333 | int immh = extract32(insn, 19, 4); | |
10334 | bool is_u = extract32(insn, 29, 1); | |
10335 | bool is_q = extract32(insn, 30, 1); | |
10336 | ||
3944d58d RH |
10337 | /* data_proc_simd[] has sent immh == 0 to disas_simd_mod_imm. */ |
10338 | assert(immh != 0); | |
10339 | ||
4d1cef84 | 10340 | switch (opcode) { |
37a706ad PM |
10341 | case 0x08: /* SRI */ |
10342 | if (!is_u) { | |
10343 | unallocated_encoding(s); | |
10344 | return; | |
10345 | } | |
10346 | /* fall through */ | |
4d1cef84 AB |
10347 | case 0x00: /* SSHR / USHR */ |
10348 | case 0x02: /* SSRA / USRA (accumulate) */ | |
10349 | case 0x04: /* SRSHR / URSHR (rounding) */ | |
10350 | case 0x06: /* SRSRA / URSRA (accum + rounding) */ | |
10351 | handle_vec_simd_shri(s, is_q, is_u, immh, immb, opcode, rn, rd); | |
10352 | break; | |
10353 | case 0x0a: /* SHL / SLI */ | |
10354 | handle_vec_simd_shli(s, is_q, is_u, immh, immb, opcode, rn, rd); | |
10355 | break; | |
c1b876b2 AB |
10356 | case 0x10: /* SHRN */ |
10357 | case 0x11: /* RSHRN / SQRSHRUN */ | |
10358 | if (is_u) { | |
10359 | handle_vec_simd_sqshrn(s, false, is_q, false, true, immh, immb, | |
10360 | opcode, rn, rd); | |
10361 | } else { | |
10362 | handle_vec_simd_shrn(s, is_q, immh, immb, opcode, rn, rd); | |
10363 | } | |
10364 | break; | |
10365 | case 0x12: /* SQSHRN / UQSHRN */ | |
10366 | case 0x13: /* SQRSHRN / UQRSHRN */ | |
10367 | handle_vec_simd_sqshrn(s, false, is_q, is_u, is_u, immh, immb, | |
10368 | opcode, rn, rd); | |
10369 | break; | |
4d1cef84 AB |
10370 | case 0x14: /* SSHLL / USHLL */ |
10371 | handle_vec_simd_wshli(s, is_q, is_u, immh, immb, opcode, rn, rd); | |
10372 | break; | |
10113b69 AB |
10373 | case 0x1c: /* SCVTF / UCVTF */ |
10374 | handle_simd_shift_intfp_conv(s, false, is_q, is_u, immh, immb, | |
10375 | opcode, rn, rd); | |
10376 | break; | |
a566da1b | 10377 | case 0xc: /* SQSHLU */ |
a847f32c PM |
10378 | if (!is_u) { |
10379 | unallocated_encoding(s); | |
10380 | return; | |
10381 | } | |
10382 | handle_simd_qshl(s, false, is_q, false, true, immh, immb, rn, rd); | |
10383 | break; | |
a566da1b | 10384 | case 0xe: /* SQSHL, UQSHL */ |
a847f32c PM |
10385 | handle_simd_qshl(s, false, is_q, is_u, is_u, immh, immb, rn, rd); |
10386 | break; | |
10113b69 | 10387 | case 0x1f: /* FCVTZS/ FCVTZU */ |
2ed3ea11 | 10388 | handle_simd_shift_fpint_conv(s, false, is_q, is_u, immh, immb, rn, rd); |
10113b69 | 10389 | return; |
4d1cef84 | 10390 | default: |
a566da1b | 10391 | unallocated_encoding(s); |
4d1cef84 AB |
10392 | return; |
10393 | } | |
384b26fb AB |
10394 | } |
10395 | ||
70d7f984 PM |
10396 | /* Generate code to do a "long" addition or subtraction, ie one done in |
10397 | * TCGv_i64 on vector lanes twice the width specified by size. | |
10398 | */ | |
10399 | static void gen_neon_addl(int size, bool is_sub, TCGv_i64 tcg_res, | |
10400 | TCGv_i64 tcg_op1, TCGv_i64 tcg_op2) | |
10401 | { | |
10402 | static NeonGenTwo64OpFn * const fns[3][2] = { | |
10403 | { gen_helper_neon_addl_u16, gen_helper_neon_subl_u16 }, | |
10404 | { gen_helper_neon_addl_u32, gen_helper_neon_subl_u32 }, | |
10405 | { tcg_gen_add_i64, tcg_gen_sub_i64 }, | |
10406 | }; | |
10407 | NeonGenTwo64OpFn *genfn; | |
10408 | assert(size < 3); | |
10409 | ||
10410 | genfn = fns[size][is_sub]; | |
10411 | genfn(tcg_res, tcg_op1, tcg_op2); | |
10412 | } | |
10413 | ||
a08582f4 PM |
10414 | static void handle_3rd_widening(DisasContext *s, int is_q, int is_u, int size, |
10415 | int opcode, int rd, int rn, int rm) | |
10416 | { | |
10417 | /* 3-reg-different widening insns: 64 x 64 -> 128 */ | |
10418 | TCGv_i64 tcg_res[2]; | |
10419 | int pass, accop; | |
10420 | ||
10421 | tcg_res[0] = tcg_temp_new_i64(); | |
10422 | tcg_res[1] = tcg_temp_new_i64(); | |
10423 | ||
10424 | /* Does this op do an adding accumulate, a subtracting accumulate, | |
10425 | * or no accumulate at all? | |
10426 | */ | |
10427 | switch (opcode) { | |
10428 | case 5: | |
10429 | case 8: | |
10430 | case 9: | |
10431 | accop = 1; | |
10432 | break; | |
10433 | case 10: | |
10434 | case 11: | |
10435 | accop = -1; | |
10436 | break; | |
10437 | default: | |
10438 | accop = 0; | |
10439 | break; | |
10440 | } | |
10441 | ||
10442 | if (accop != 0) { | |
10443 | read_vec_element(s, tcg_res[0], rd, 0, MO_64); | |
10444 | read_vec_element(s, tcg_res[1], rd, 1, MO_64); | |
10445 | } | |
10446 | ||
10447 | /* size == 2 means two 32x32->64 operations; this is worth special | |
10448 | * casing because we can generally handle it inline. | |
10449 | */ | |
10450 | if (size == 2) { | |
10451 | for (pass = 0; pass < 2; pass++) { | |
10452 | TCGv_i64 tcg_op1 = tcg_temp_new_i64(); | |
10453 | TCGv_i64 tcg_op2 = tcg_temp_new_i64(); | |
10454 | TCGv_i64 tcg_passres; | |
14776ab5 | 10455 | MemOp memop = MO_32 | (is_u ? 0 : MO_SIGN); |
a08582f4 PM |
10456 | |
10457 | int elt = pass + is_q * 2; | |
10458 | ||
10459 | read_vec_element(s, tcg_op1, rn, elt, memop); | |
10460 | read_vec_element(s, tcg_op2, rm, elt, memop); | |
10461 | ||
10462 | if (accop == 0) { | |
10463 | tcg_passres = tcg_res[pass]; | |
10464 | } else { | |
10465 | tcg_passres = tcg_temp_new_i64(); | |
10466 | } | |
10467 | ||
10468 | switch (opcode) { | |
70d7f984 PM |
10469 | case 0: /* SADDL, SADDL2, UADDL, UADDL2 */ |
10470 | tcg_gen_add_i64(tcg_passres, tcg_op1, tcg_op2); | |
10471 | break; | |
10472 | case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */ | |
10473 | tcg_gen_sub_i64(tcg_passres, tcg_op1, tcg_op2); | |
10474 | break; | |
0ae39320 PM |
10475 | case 5: /* SABAL, SABAL2, UABAL, UABAL2 */ |
10476 | case 7: /* SABDL, SABDL2, UABDL, UABDL2 */ | |
10477 | { | |
10478 | TCGv_i64 tcg_tmp1 = tcg_temp_new_i64(); | |
10479 | TCGv_i64 tcg_tmp2 = tcg_temp_new_i64(); | |
10480 | ||
10481 | tcg_gen_sub_i64(tcg_tmp1, tcg_op1, tcg_op2); | |
10482 | tcg_gen_sub_i64(tcg_tmp2, tcg_op2, tcg_op1); | |
10483 | tcg_gen_movcond_i64(is_u ? TCG_COND_GEU : TCG_COND_GE, | |
10484 | tcg_passres, | |
10485 | tcg_op1, tcg_op2, tcg_tmp1, tcg_tmp2); | |
10486 | tcg_temp_free_i64(tcg_tmp1); | |
10487 | tcg_temp_free_i64(tcg_tmp2); | |
10488 | break; | |
10489 | } | |
a08582f4 PM |
10490 | case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */ |
10491 | case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */ | |
10492 | case 12: /* UMULL, UMULL2, SMULL, SMULL2 */ | |
10493 | tcg_gen_mul_i64(tcg_passres, tcg_op1, tcg_op2); | |
10494 | break; | |
70d7f984 PM |
10495 | case 9: /* SQDMLAL, SQDMLAL2 */ |
10496 | case 11: /* SQDMLSL, SQDMLSL2 */ | |
10497 | case 13: /* SQDMULL, SQDMULL2 */ | |
10498 | tcg_gen_mul_i64(tcg_passres, tcg_op1, tcg_op2); | |
10499 | gen_helper_neon_addl_saturate_s64(tcg_passres, cpu_env, | |
10500 | tcg_passres, tcg_passres); | |
10501 | break; | |
a08582f4 PM |
10502 | default: |
10503 | g_assert_not_reached(); | |
10504 | } | |
10505 | ||
70d7f984 PM |
10506 | if (opcode == 9 || opcode == 11) { |
10507 | /* saturating accumulate ops */ | |
10508 | if (accop < 0) { | |
10509 | tcg_gen_neg_i64(tcg_passres, tcg_passres); | |
10510 | } | |
10511 | gen_helper_neon_addl_saturate_s64(tcg_res[pass], cpu_env, | |
10512 | tcg_res[pass], tcg_passres); | |
10513 | } else if (accop > 0) { | |
a08582f4 | 10514 | tcg_gen_add_i64(tcg_res[pass], tcg_res[pass], tcg_passres); |
a08582f4 PM |
10515 | } else if (accop < 0) { |
10516 | tcg_gen_sub_i64(tcg_res[pass], tcg_res[pass], tcg_passres); | |
70d7f984 PM |
10517 | } |
10518 | ||
10519 | if (accop != 0) { | |
a08582f4 PM |
10520 | tcg_temp_free_i64(tcg_passres); |
10521 | } | |
10522 | ||
10523 | tcg_temp_free_i64(tcg_op1); | |
10524 | tcg_temp_free_i64(tcg_op2); | |
10525 | } | |
10526 | } else { | |
10527 | /* size 0 or 1, generally helper functions */ | |
10528 | for (pass = 0; pass < 2; pass++) { | |
10529 | TCGv_i32 tcg_op1 = tcg_temp_new_i32(); | |
10530 | TCGv_i32 tcg_op2 = tcg_temp_new_i32(); | |
10531 | TCGv_i64 tcg_passres; | |
10532 | int elt = pass + is_q * 2; | |
10533 | ||
10534 | read_vec_element_i32(s, tcg_op1, rn, elt, MO_32); | |
10535 | read_vec_element_i32(s, tcg_op2, rm, elt, MO_32); | |
10536 | ||
10537 | if (accop == 0) { | |
10538 | tcg_passres = tcg_res[pass]; | |
10539 | } else { | |
10540 | tcg_passres = tcg_temp_new_i64(); | |
10541 | } | |
10542 | ||
10543 | switch (opcode) { | |
70d7f984 PM |
10544 | case 0: /* SADDL, SADDL2, UADDL, UADDL2 */ |
10545 | case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */ | |
10546 | { | |
10547 | TCGv_i64 tcg_op2_64 = tcg_temp_new_i64(); | |
10548 | static NeonGenWidenFn * const widenfns[2][2] = { | |
10549 | { gen_helper_neon_widen_s8, gen_helper_neon_widen_u8 }, | |
10550 | { gen_helper_neon_widen_s16, gen_helper_neon_widen_u16 }, | |
10551 | }; | |
10552 | NeonGenWidenFn *widenfn = widenfns[size][is_u]; | |
10553 | ||
10554 | widenfn(tcg_op2_64, tcg_op2); | |
10555 | widenfn(tcg_passres, tcg_op1); | |
10556 | gen_neon_addl(size, (opcode == 2), tcg_passres, | |
10557 | tcg_passres, tcg_op2_64); | |
10558 | tcg_temp_free_i64(tcg_op2_64); | |
10559 | break; | |
10560 | } | |
0ae39320 PM |
10561 | case 5: /* SABAL, SABAL2, UABAL, UABAL2 */ |
10562 | case 7: /* SABDL, SABDL2, UABDL, UABDL2 */ | |
10563 | if (size == 0) { | |
10564 | if (is_u) { | |
10565 | gen_helper_neon_abdl_u16(tcg_passres, tcg_op1, tcg_op2); | |
10566 | } else { | |
10567 | gen_helper_neon_abdl_s16(tcg_passres, tcg_op1, tcg_op2); | |
10568 | } | |
10569 | } else { | |
10570 | if (is_u) { | |
10571 | gen_helper_neon_abdl_u32(tcg_passres, tcg_op1, tcg_op2); | |
10572 | } else { | |
10573 | gen_helper_neon_abdl_s32(tcg_passres, tcg_op1, tcg_op2); | |
10574 | } | |
10575 | } | |
10576 | break; | |
a08582f4 PM |
10577 | case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */ |
10578 | case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */ | |
10579 | case 12: /* UMULL, UMULL2, SMULL, SMULL2 */ | |
10580 | if (size == 0) { | |
10581 | if (is_u) { | |
10582 | gen_helper_neon_mull_u8(tcg_passres, tcg_op1, tcg_op2); | |
10583 | } else { | |
10584 | gen_helper_neon_mull_s8(tcg_passres, tcg_op1, tcg_op2); | |
10585 | } | |
10586 | } else { | |
10587 | if (is_u) { | |
10588 | gen_helper_neon_mull_u16(tcg_passres, tcg_op1, tcg_op2); | |
10589 | } else { | |
10590 | gen_helper_neon_mull_s16(tcg_passres, tcg_op1, tcg_op2); | |
10591 | } | |
10592 | } | |
10593 | break; | |
70d7f984 PM |
10594 | case 9: /* SQDMLAL, SQDMLAL2 */ |
10595 | case 11: /* SQDMLSL, SQDMLSL2 */ | |
10596 | case 13: /* SQDMULL, SQDMULL2 */ | |
10597 | assert(size == 1); | |
10598 | gen_helper_neon_mull_s16(tcg_passres, tcg_op1, tcg_op2); | |
10599 | gen_helper_neon_addl_saturate_s32(tcg_passres, cpu_env, | |
10600 | tcg_passres, tcg_passres); | |
10601 | break; | |
a08582f4 PM |
10602 | default: |
10603 | g_assert_not_reached(); | |
10604 | } | |
10605 | tcg_temp_free_i32(tcg_op1); | |
10606 | tcg_temp_free_i32(tcg_op2); | |
10607 | ||
70d7f984 PM |
10608 | if (accop != 0) { |
10609 | if (opcode == 9 || opcode == 11) { | |
10610 | /* saturating accumulate ops */ | |
10611 | if (accop < 0) { | |
10612 | gen_helper_neon_negl_u32(tcg_passres, tcg_passres); | |
10613 | } | |
10614 | gen_helper_neon_addl_saturate_s32(tcg_res[pass], cpu_env, | |
10615 | tcg_res[pass], | |
10616 | tcg_passres); | |
a08582f4 | 10617 | } else { |
70d7f984 PM |
10618 | gen_neon_addl(size, (accop < 0), tcg_res[pass], |
10619 | tcg_res[pass], tcg_passres); | |
a08582f4 PM |
10620 | } |
10621 | tcg_temp_free_i64(tcg_passres); | |
10622 | } | |
10623 | } | |
10624 | } | |
10625 | ||
10626 | write_vec_element(s, tcg_res[0], rd, 0, MO_64); | |
10627 | write_vec_element(s, tcg_res[1], rd, 1, MO_64); | |
10628 | tcg_temp_free_i64(tcg_res[0]); | |
10629 | tcg_temp_free_i64(tcg_res[1]); | |
10630 | } | |
10631 | ||
dfc15c7c PM |
10632 | static void handle_3rd_wide(DisasContext *s, int is_q, int is_u, int size, |
10633 | int opcode, int rd, int rn, int rm) | |
10634 | { | |
10635 | TCGv_i64 tcg_res[2]; | |
10636 | int part = is_q ? 2 : 0; | |
10637 | int pass; | |
10638 | ||
10639 | for (pass = 0; pass < 2; pass++) { | |
10640 | TCGv_i64 tcg_op1 = tcg_temp_new_i64(); | |
10641 | TCGv_i32 tcg_op2 = tcg_temp_new_i32(); | |
10642 | TCGv_i64 tcg_op2_wide = tcg_temp_new_i64(); | |
10643 | static NeonGenWidenFn * const widenfns[3][2] = { | |
10644 | { gen_helper_neon_widen_s8, gen_helper_neon_widen_u8 }, | |
10645 | { gen_helper_neon_widen_s16, gen_helper_neon_widen_u16 }, | |
10646 | { tcg_gen_ext_i32_i64, tcg_gen_extu_i32_i64 }, | |
10647 | }; | |
10648 | NeonGenWidenFn *widenfn = widenfns[size][is_u]; | |
10649 | ||
10650 | read_vec_element(s, tcg_op1, rn, pass, MO_64); | |
10651 | read_vec_element_i32(s, tcg_op2, rm, part + pass, MO_32); | |
10652 | widenfn(tcg_op2_wide, tcg_op2); | |
10653 | tcg_temp_free_i32(tcg_op2); | |
10654 | tcg_res[pass] = tcg_temp_new_i64(); | |
10655 | gen_neon_addl(size, (opcode == 3), | |
10656 | tcg_res[pass], tcg_op1, tcg_op2_wide); | |
10657 | tcg_temp_free_i64(tcg_op1); | |
10658 | tcg_temp_free_i64(tcg_op2_wide); | |
10659 | } | |
10660 | ||
10661 | for (pass = 0; pass < 2; pass++) { | |
10662 | write_vec_element(s, tcg_res[pass], rd, pass, MO_64); | |
10663 | tcg_temp_free_i64(tcg_res[pass]); | |
10664 | } | |
10665 | } | |
10666 | ||
e4b998d4 PM |
10667 | static void do_narrow_round_high_u32(TCGv_i32 res, TCGv_i64 in) |
10668 | { | |
10669 | tcg_gen_addi_i64(in, in, 1U << 31); | |
7cb36e18 | 10670 | tcg_gen_extrh_i64_i32(res, in); |
e4b998d4 PM |
10671 | } |
10672 | ||
10673 | static void handle_3rd_narrowing(DisasContext *s, int is_q, int is_u, int size, | |
10674 | int opcode, int rd, int rn, int rm) | |
10675 | { | |
10676 | TCGv_i32 tcg_res[2]; | |
10677 | int part = is_q ? 2 : 0; | |
10678 | int pass; | |
10679 | ||
10680 | for (pass = 0; pass < 2; pass++) { | |
10681 | TCGv_i64 tcg_op1 = tcg_temp_new_i64(); | |
10682 | TCGv_i64 tcg_op2 = tcg_temp_new_i64(); | |
10683 | TCGv_i64 tcg_wideres = tcg_temp_new_i64(); | |
10684 | static NeonGenNarrowFn * const narrowfns[3][2] = { | |
10685 | { gen_helper_neon_narrow_high_u8, | |
10686 | gen_helper_neon_narrow_round_high_u8 }, | |
10687 | { gen_helper_neon_narrow_high_u16, | |
10688 | gen_helper_neon_narrow_round_high_u16 }, | |
7cb36e18 | 10689 | { tcg_gen_extrh_i64_i32, do_narrow_round_high_u32 }, |
e4b998d4 PM |
10690 | }; |
10691 | NeonGenNarrowFn *gennarrow = narrowfns[size][is_u]; | |
10692 | ||
10693 | read_vec_element(s, tcg_op1, rn, pass, MO_64); | |
10694 | read_vec_element(s, tcg_op2, rm, pass, MO_64); | |
10695 | ||
10696 | gen_neon_addl(size, (opcode == 6), tcg_wideres, tcg_op1, tcg_op2); | |
10697 | ||
10698 | tcg_temp_free_i64(tcg_op1); | |
10699 | tcg_temp_free_i64(tcg_op2); | |
10700 | ||
10701 | tcg_res[pass] = tcg_temp_new_i32(); | |
10702 | gennarrow(tcg_res[pass], tcg_wideres); | |
10703 | tcg_temp_free_i64(tcg_wideres); | |
10704 | } | |
10705 | ||
10706 | for (pass = 0; pass < 2; pass++) { | |
10707 | write_vec_element_i32(s, tcg_res[pass], rd, pass + part, MO_32); | |
10708 | tcg_temp_free_i32(tcg_res[pass]); | |
10709 | } | |
4ff55bcb | 10710 | clear_vec_high(s, is_q, rd); |
e4b998d4 PM |
10711 | } |
10712 | ||
4ce31af4 | 10713 | /* AdvSIMD three different |
384b26fb AB |
10714 | * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0 |
10715 | * +---+---+---+-----------+------+---+------+--------+-----+------+------+ | |
10716 | * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd | | |
10717 | * +---+---+---+-----------+------+---+------+--------+-----+------+------+ | |
10718 | */ | |
10719 | static void disas_simd_three_reg_diff(DisasContext *s, uint32_t insn) | |
10720 | { | |
a08582f4 PM |
10721 | /* Instructions in this group fall into three basic classes |
10722 | * (in each case with the operation working on each element in | |
10723 | * the input vectors): | |
10724 | * (1) widening 64 x 64 -> 128 (with possibly Vd as an extra | |
10725 | * 128 bit input) | |
10726 | * (2) wide 64 x 128 -> 128 | |
10727 | * (3) narrowing 128 x 128 -> 64 | |
10728 | * Here we do initial decode, catch unallocated cases and | |
10729 | * dispatch to separate functions for each class. | |
10730 | */ | |
10731 | int is_q = extract32(insn, 30, 1); | |
10732 | int is_u = extract32(insn, 29, 1); | |
10733 | int size = extract32(insn, 22, 2); | |
10734 | int opcode = extract32(insn, 12, 4); | |
10735 | int rm = extract32(insn, 16, 5); | |
10736 | int rn = extract32(insn, 5, 5); | |
10737 | int rd = extract32(insn, 0, 5); | |
10738 | ||
10739 | switch (opcode) { | |
10740 | case 1: /* SADDW, SADDW2, UADDW, UADDW2 */ | |
10741 | case 3: /* SSUBW, SSUBW2, USUBW, USUBW2 */ | |
10742 | /* 64 x 128 -> 128 */ | |
dfc15c7c PM |
10743 | if (size == 3) { |
10744 | unallocated_encoding(s); | |
10745 | return; | |
10746 | } | |
8c6afa6a PM |
10747 | if (!fp_access_check(s)) { |
10748 | return; | |
10749 | } | |
dfc15c7c | 10750 | handle_3rd_wide(s, is_q, is_u, size, opcode, rd, rn, rm); |
a08582f4 PM |
10751 | break; |
10752 | case 4: /* ADDHN, ADDHN2, RADDHN, RADDHN2 */ | |
10753 | case 6: /* SUBHN, SUBHN2, RSUBHN, RSUBHN2 */ | |
10754 | /* 128 x 128 -> 64 */ | |
e4b998d4 PM |
10755 | if (size == 3) { |
10756 | unallocated_encoding(s); | |
10757 | return; | |
10758 | } | |
8c6afa6a PM |
10759 | if (!fp_access_check(s)) { |
10760 | return; | |
10761 | } | |
e4b998d4 | 10762 | handle_3rd_narrowing(s, is_q, is_u, size, opcode, rd, rn, rm); |
a08582f4 | 10763 | break; |
70d7f984 | 10764 | case 14: /* PMULL, PMULL2 */ |
e7e96fc5 | 10765 | if (is_u) { |
70d7f984 PM |
10766 | unallocated_encoding(s); |
10767 | return; | |
10768 | } | |
e7e96fc5 RH |
10769 | switch (size) { |
10770 | case 0: /* PMULL.P8 */ | |
10771 | if (!fp_access_check(s)) { | |
10772 | return; | |
10773 | } | |
10774 | /* The Q field specifies lo/hi half input for this insn. */ | |
10775 | gen_gvec_op3_ool(s, true, rd, rn, rm, is_q, | |
10776 | gen_helper_neon_pmull_h); | |
10777 | break; | |
10778 | ||
10779 | case 3: /* PMULL.P64 */ | |
962fcbf2 | 10780 | if (!dc_isar_feature(aa64_pmull, s)) { |
a984e42c PM |
10781 | unallocated_encoding(s); |
10782 | return; | |
10783 | } | |
8c6afa6a PM |
10784 | if (!fp_access_check(s)) { |
10785 | return; | |
10786 | } | |
b9ed510e RH |
10787 | /* The Q field specifies lo/hi half input for this insn. */ |
10788 | gen_gvec_op3_ool(s, true, rd, rn, rm, is_q, | |
10789 | gen_helper_gvec_pmull_q); | |
e7e96fc5 RH |
10790 | break; |
10791 | ||
10792 | default: | |
10793 | unallocated_encoding(s); | |
10794 | break; | |
a984e42c | 10795 | } |
e7e96fc5 | 10796 | return; |
13caf1fd PM |
10797 | case 9: /* SQDMLAL, SQDMLAL2 */ |
10798 | case 11: /* SQDMLSL, SQDMLSL2 */ | |
10799 | case 13: /* SQDMULL, SQDMULL2 */ | |
70d7f984 | 10800 | if (is_u || size == 0) { |
a08582f4 PM |
10801 | unallocated_encoding(s); |
10802 | return; | |
10803 | } | |
10804 | /* fall through */ | |
13caf1fd PM |
10805 | case 0: /* SADDL, SADDL2, UADDL, UADDL2 */ |
10806 | case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */ | |
13caf1fd PM |
10807 | case 5: /* SABAL, SABAL2, UABAL, UABAL2 */ |
10808 | case 7: /* SABDL, SABDL2, UABDL, UABDL2 */ | |
10809 | case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */ | |
10810 | case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */ | |
10811 | case 12: /* SMULL, SMULL2, UMULL, UMULL2 */ | |
a08582f4 PM |
10812 | /* 64 x 64 -> 128 */ |
10813 | if (size == 3) { | |
10814 | unallocated_encoding(s); | |
10815 | return; | |
10816 | } | |
8c6afa6a PM |
10817 | if (!fp_access_check(s)) { |
10818 | return; | |
10819 | } | |
10820 | ||
a08582f4 PM |
10821 | handle_3rd_widening(s, is_q, is_u, size, opcode, rd, rn, rm); |
10822 | break; | |
10823 | default: | |
10824 | /* opcode 15 not allocated */ | |
10825 | unallocated_encoding(s); | |
10826 | break; | |
10827 | } | |
384b26fb AB |
10828 | } |
10829 | ||
e1cea114 PM |
10830 | /* Logic op (opcode == 3) subgroup of C3.6.16. */ |
10831 | static void disas_simd_3same_logic(DisasContext *s, uint32_t insn) | |
10832 | { | |
956d272e PM |
10833 | int rd = extract32(insn, 0, 5); |
10834 | int rn = extract32(insn, 5, 5); | |
10835 | int rm = extract32(insn, 16, 5); | |
10836 | int size = extract32(insn, 22, 2); | |
10837 | bool is_u = extract32(insn, 29, 1); | |
10838 | bool is_q = extract32(insn, 30, 1); | |
956d272e | 10839 | |
8c6afa6a PM |
10840 | if (!fp_access_check(s)) { |
10841 | return; | |
10842 | } | |
10843 | ||
bc48092f RH |
10844 | switch (size + 4 * is_u) { |
10845 | case 0: /* AND */ | |
10846 | gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_and, 0); | |
10847 | return; | |
10848 | case 1: /* BIC */ | |
10849 | gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_andc, 0); | |
10850 | return; | |
10851 | case 2: /* ORR */ | |
2900847f | 10852 | gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_or, 0); |
bc48092f RH |
10853 | return; |
10854 | case 3: /* ORN */ | |
10855 | gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_orc, 0); | |
10856 | return; | |
10857 | case 4: /* EOR */ | |
10858 | gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_xor, 0); | |
10859 | return; | |
956d272e | 10860 | |
bc48092f | 10861 | case 5: /* BSL bitwise select */ |
3a7a2b4e | 10862 | gen_gvec_fn4(s, is_q, rd, rd, rn, rm, tcg_gen_gvec_bitsel, 0); |
bc48092f RH |
10863 | return; |
10864 | case 6: /* BIT, bitwise insert if true */ | |
3a7a2b4e | 10865 | gen_gvec_fn4(s, is_q, rd, rm, rn, rd, tcg_gen_gvec_bitsel, 0); |
bc48092f RH |
10866 | return; |
10867 | case 7: /* BIF, bitwise insert if false */ | |
3a7a2b4e | 10868 | gen_gvec_fn4(s, is_q, rd, rm, rd, rn, tcg_gen_gvec_bitsel, 0); |
bc48092f | 10869 | return; |
956d272e | 10870 | |
bc48092f RH |
10871 | default: |
10872 | g_assert_not_reached(); | |
956d272e | 10873 | } |
e1cea114 PM |
10874 | } |
10875 | ||
bc242f9b AB |
10876 | /* Pairwise op subgroup of C3.6.16. |
10877 | * | |
10878 | * This is called directly or via the handle_3same_float for float pairwise | |
10879 | * operations where the opcode and size are calculated differently. | |
10880 | */ | |
10881 | static void handle_simd_3same_pair(DisasContext *s, int is_q, int u, int opcode, | |
10882 | int size, int rn, int rm, int rd) | |
e1cea114 | 10883 | { |
bc242f9b | 10884 | TCGv_ptr fpst; |
0173a005 PM |
10885 | int pass; |
10886 | ||
bc242f9b AB |
10887 | /* Floating point operations need fpst */ |
10888 | if (opcode >= 0x58) { | |
d81ce0ef | 10889 | fpst = get_fpstatus_ptr(false); |
bc242f9b | 10890 | } else { |
f764718d | 10891 | fpst = NULL; |
0173a005 PM |
10892 | } |
10893 | ||
8c6afa6a PM |
10894 | if (!fp_access_check(s)) { |
10895 | return; | |
10896 | } | |
10897 | ||
0173a005 PM |
10898 | /* These operations work on the concatenated rm:rn, with each pair of |
10899 | * adjacent elements being operated on to produce an element in the result. | |
10900 | */ | |
10901 | if (size == 3) { | |
10902 | TCGv_i64 tcg_res[2]; | |
10903 | ||
10904 | for (pass = 0; pass < 2; pass++) { | |
10905 | TCGv_i64 tcg_op1 = tcg_temp_new_i64(); | |
10906 | TCGv_i64 tcg_op2 = tcg_temp_new_i64(); | |
10907 | int passreg = (pass == 0) ? rn : rm; | |
10908 | ||
10909 | read_vec_element(s, tcg_op1, passreg, 0, MO_64); | |
10910 | read_vec_element(s, tcg_op2, passreg, 1, MO_64); | |
10911 | tcg_res[pass] = tcg_temp_new_i64(); | |
10912 | ||
bc242f9b AB |
10913 | switch (opcode) { |
10914 | case 0x17: /* ADDP */ | |
10915 | tcg_gen_add_i64(tcg_res[pass], tcg_op1, tcg_op2); | |
10916 | break; | |
10917 | case 0x58: /* FMAXNMP */ | |
10918 | gen_helper_vfp_maxnumd(tcg_res[pass], tcg_op1, tcg_op2, fpst); | |
10919 | break; | |
10920 | case 0x5a: /* FADDP */ | |
10921 | gen_helper_vfp_addd(tcg_res[pass], tcg_op1, tcg_op2, fpst); | |
10922 | break; | |
10923 | case 0x5e: /* FMAXP */ | |
10924 | gen_helper_vfp_maxd(tcg_res[pass], tcg_op1, tcg_op2, fpst); | |
10925 | break; | |
10926 | case 0x78: /* FMINNMP */ | |
10927 | gen_helper_vfp_minnumd(tcg_res[pass], tcg_op1, tcg_op2, fpst); | |
10928 | break; | |
10929 | case 0x7e: /* FMINP */ | |
10930 | gen_helper_vfp_mind(tcg_res[pass], tcg_op1, tcg_op2, fpst); | |
10931 | break; | |
10932 | default: | |
10933 | g_assert_not_reached(); | |
10934 | } | |
0173a005 PM |
10935 | |
10936 | tcg_temp_free_i64(tcg_op1); | |
10937 | tcg_temp_free_i64(tcg_op2); | |
10938 | } | |
10939 | ||
10940 | for (pass = 0; pass < 2; pass++) { | |
10941 | write_vec_element(s, tcg_res[pass], rd, pass, MO_64); | |
10942 | tcg_temp_free_i64(tcg_res[pass]); | |
10943 | } | |
10944 | } else { | |
10945 | int maxpass = is_q ? 4 : 2; | |
10946 | TCGv_i32 tcg_res[4]; | |
10947 | ||
10948 | for (pass = 0; pass < maxpass; pass++) { | |
10949 | TCGv_i32 tcg_op1 = tcg_temp_new_i32(); | |
10950 | TCGv_i32 tcg_op2 = tcg_temp_new_i32(); | |
bc242f9b | 10951 | NeonGenTwoOpFn *genfn = NULL; |
0173a005 PM |
10952 | int passreg = pass < (maxpass / 2) ? rn : rm; |
10953 | int passelt = (is_q && (pass & 1)) ? 2 : 0; | |
10954 | ||
10955 | read_vec_element_i32(s, tcg_op1, passreg, passelt, MO_32); | |
10956 | read_vec_element_i32(s, tcg_op2, passreg, passelt + 1, MO_32); | |
10957 | tcg_res[pass] = tcg_temp_new_i32(); | |
10958 | ||
10959 | switch (opcode) { | |
10960 | case 0x17: /* ADDP */ | |
10961 | { | |
10962 | static NeonGenTwoOpFn * const fns[3] = { | |
10963 | gen_helper_neon_padd_u8, | |
10964 | gen_helper_neon_padd_u16, | |
10965 | tcg_gen_add_i32, | |
10966 | }; | |
10967 | genfn = fns[size]; | |
10968 | break; | |
10969 | } | |
10970 | case 0x14: /* SMAXP, UMAXP */ | |
10971 | { | |
10972 | static NeonGenTwoOpFn * const fns[3][2] = { | |
10973 | { gen_helper_neon_pmax_s8, gen_helper_neon_pmax_u8 }, | |
10974 | { gen_helper_neon_pmax_s16, gen_helper_neon_pmax_u16 }, | |
ecb8ab8d | 10975 | { tcg_gen_smax_i32, tcg_gen_umax_i32 }, |
0173a005 PM |
10976 | }; |
10977 | genfn = fns[size][u]; | |
10978 | break; | |
10979 | } | |
10980 | case 0x15: /* SMINP, UMINP */ | |
10981 | { | |
10982 | static NeonGenTwoOpFn * const fns[3][2] = { | |
10983 | { gen_helper_neon_pmin_s8, gen_helper_neon_pmin_u8 }, | |
10984 | { gen_helper_neon_pmin_s16, gen_helper_neon_pmin_u16 }, | |
ecb8ab8d | 10985 | { tcg_gen_smin_i32, tcg_gen_umin_i32 }, |
0173a005 PM |
10986 | }; |
10987 | genfn = fns[size][u]; | |
10988 | break; | |
10989 | } | |
bc242f9b AB |
10990 | /* The FP operations are all on single floats (32 bit) */ |
10991 | case 0x58: /* FMAXNMP */ | |
10992 | gen_helper_vfp_maxnums(tcg_res[pass], tcg_op1, tcg_op2, fpst); | |
10993 | break; | |
10994 | case 0x5a: /* FADDP */ | |
10995 | gen_helper_vfp_adds(tcg_res[pass], tcg_op1, tcg_op2, fpst); | |
10996 | break; | |
10997 | case 0x5e: /* FMAXP */ | |
10998 | gen_helper_vfp_maxs(tcg_res[pass], tcg_op1, tcg_op2, fpst); | |
10999 | break; | |
11000 | case 0x78: /* FMINNMP */ | |
11001 | gen_helper_vfp_minnums(tcg_res[pass], tcg_op1, tcg_op2, fpst); | |
11002 | break; | |
11003 | case 0x7e: /* FMINP */ | |
11004 | gen_helper_vfp_mins(tcg_res[pass], tcg_op1, tcg_op2, fpst); | |
11005 | break; | |
0173a005 PM |
11006 | default: |
11007 | g_assert_not_reached(); | |
11008 | } | |
11009 | ||
bc242f9b AB |
11010 | /* FP ops called directly, otherwise call now */ |
11011 | if (genfn) { | |
11012 | genfn(tcg_res[pass], tcg_op1, tcg_op2); | |
11013 | } | |
0173a005 PM |
11014 | |
11015 | tcg_temp_free_i32(tcg_op1); | |
11016 | tcg_temp_free_i32(tcg_op2); | |
11017 | } | |
11018 | ||
11019 | for (pass = 0; pass < maxpass; pass++) { | |
11020 | write_vec_element_i32(s, tcg_res[pass], rd, pass, MO_32); | |
11021 | tcg_temp_free_i32(tcg_res[pass]); | |
11022 | } | |
4ff55bcb | 11023 | clear_vec_high(s, is_q, rd); |
0173a005 | 11024 | } |
bc242f9b | 11025 | |
f764718d | 11026 | if (fpst) { |
bc242f9b AB |
11027 | tcg_temp_free_ptr(fpst); |
11028 | } | |
e1cea114 PM |
11029 | } |
11030 | ||
11031 | /* Floating point op subgroup of C3.6.16. */ | |
11032 | static void disas_simd_3same_float(DisasContext *s, uint32_t insn) | |
11033 | { | |
845ea09a PM |
11034 | /* For floating point ops, the U, size[1] and opcode bits |
11035 | * together indicate the operation. size[0] indicates single | |
11036 | * or double. | |
11037 | */ | |
11038 | int fpopcode = extract32(insn, 11, 5) | |
11039 | | (extract32(insn, 23, 1) << 5) | |
11040 | | (extract32(insn, 29, 1) << 6); | |
11041 | int is_q = extract32(insn, 30, 1); | |
11042 | int size = extract32(insn, 22, 1); | |
11043 | int rm = extract32(insn, 16, 5); | |
11044 | int rn = extract32(insn, 5, 5); | |
11045 | int rd = extract32(insn, 0, 5); | |
11046 | ||
11047 | int datasize = is_q ? 128 : 64; | |
11048 | int esize = 32 << size; | |
11049 | int elements = datasize / esize; | |
11050 | ||
11051 | if (size == 1 && !is_q) { | |
11052 | unallocated_encoding(s); | |
11053 | return; | |
11054 | } | |
11055 | ||
11056 | switch (fpopcode) { | |
11057 | case 0x58: /* FMAXNMP */ | |
11058 | case 0x5a: /* FADDP */ | |
11059 | case 0x5e: /* FMAXP */ | |
11060 | case 0x78: /* FMINNMP */ | |
11061 | case 0x7e: /* FMINP */ | |
bc242f9b AB |
11062 | if (size && !is_q) { |
11063 | unallocated_encoding(s); | |
11064 | return; | |
11065 | } | |
11066 | handle_simd_3same_pair(s, is_q, 0, fpopcode, size ? MO_64 : MO_32, | |
11067 | rn, rm, rd); | |
845ea09a PM |
11068 | return; |
11069 | case 0x1b: /* FMULX */ | |
845ea09a PM |
11070 | case 0x1f: /* FRECPS */ |
11071 | case 0x3f: /* FRSQRTS */ | |
845ea09a | 11072 | case 0x5d: /* FACGE */ |
845ea09a PM |
11073 | case 0x7d: /* FACGT */ |
11074 | case 0x19: /* FMLA */ | |
11075 | case 0x39: /* FMLS */ | |
845ea09a PM |
11076 | case 0x18: /* FMAXNM */ |
11077 | case 0x1a: /* FADD */ | |
8908f4d1 | 11078 | case 0x1c: /* FCMEQ */ |
845ea09a PM |
11079 | case 0x1e: /* FMAX */ |
11080 | case 0x38: /* FMINNM */ | |
11081 | case 0x3a: /* FSUB */ | |
11082 | case 0x3e: /* FMIN */ | |
11083 | case 0x5b: /* FMUL */ | |
8908f4d1 | 11084 | case 0x5c: /* FCMGE */ |
845ea09a PM |
11085 | case 0x5f: /* FDIV */ |
11086 | case 0x7a: /* FABD */ | |
8908f4d1 | 11087 | case 0x7c: /* FCMGT */ |
8c6afa6a PM |
11088 | if (!fp_access_check(s)) { |
11089 | return; | |
11090 | } | |
845ea09a PM |
11091 | handle_3same_float(s, size, elements, fpopcode, rd, rn, rm); |
11092 | return; | |
0caa5af8 RH |
11093 | |
11094 | case 0x1d: /* FMLAL */ | |
11095 | case 0x3d: /* FMLSL */ | |
11096 | case 0x59: /* FMLAL2 */ | |
11097 | case 0x79: /* FMLSL2 */ | |
11098 | if (size & 1 || !dc_isar_feature(aa64_fhm, s)) { | |
11099 | unallocated_encoding(s); | |
11100 | return; | |
11101 | } | |
11102 | if (fp_access_check(s)) { | |
11103 | int is_s = extract32(insn, 23, 1); | |
11104 | int is_2 = extract32(insn, 29, 1); | |
11105 | int data = (is_2 << 1) | is_s; | |
11106 | tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd), | |
11107 | vec_full_reg_offset(s, rn), | |
11108 | vec_full_reg_offset(s, rm), cpu_env, | |
11109 | is_q ? 16 : 8, vec_full_reg_size(s), | |
11110 | data, gen_helper_gvec_fmlal_a64); | |
11111 | } | |
11112 | return; | |
11113 | ||
845ea09a PM |
11114 | default: |
11115 | unallocated_encoding(s); | |
11116 | return; | |
11117 | } | |
e1cea114 PM |
11118 | } |
11119 | ||
11120 | /* Integer op subgroup of C3.6.16. */ | |
11121 | static void disas_simd_3same_int(DisasContext *s, uint32_t insn) | |
11122 | { | |
1f8a73af PM |
11123 | int is_q = extract32(insn, 30, 1); |
11124 | int u = extract32(insn, 29, 1); | |
11125 | int size = extract32(insn, 22, 2); | |
11126 | int opcode = extract32(insn, 11, 5); | |
11127 | int rm = extract32(insn, 16, 5); | |
11128 | int rn = extract32(insn, 5, 5); | |
11129 | int rd = extract32(insn, 0, 5); | |
11130 | int pass; | |
79d61de6 | 11131 | TCGCond cond; |
1f8a73af PM |
11132 | |
11133 | switch (opcode) { | |
11134 | case 0x13: /* MUL, PMUL */ | |
11135 | if (u && size != 0) { | |
11136 | unallocated_encoding(s); | |
11137 | return; | |
11138 | } | |
11139 | /* fall through */ | |
11140 | case 0x0: /* SHADD, UHADD */ | |
11141 | case 0x2: /* SRHADD, URHADD */ | |
11142 | case 0x4: /* SHSUB, UHSUB */ | |
11143 | case 0xc: /* SMAX, UMAX */ | |
11144 | case 0xd: /* SMIN, UMIN */ | |
11145 | case 0xe: /* SABD, UABD */ | |
11146 | case 0xf: /* SABA, UABA */ | |
11147 | case 0x12: /* MLA, MLS */ | |
11148 | if (size == 3) { | |
11149 | unallocated_encoding(s); | |
11150 | return; | |
11151 | } | |
8b12a0cf | 11152 | break; |
1f8a73af PM |
11153 | case 0x16: /* SQDMULH, SQRDMULH */ |
11154 | if (size == 0 || size == 3) { | |
11155 | unallocated_encoding(s); | |
11156 | return; | |
11157 | } | |
8b12a0cf | 11158 | break; |
1f8a73af PM |
11159 | default: |
11160 | if (size == 3 && !is_q) { | |
11161 | unallocated_encoding(s); | |
11162 | return; | |
11163 | } | |
11164 | break; | |
11165 | } | |
11166 | ||
8c6afa6a PM |
11167 | if (!fp_access_check(s)) { |
11168 | return; | |
11169 | } | |
11170 | ||
bc48092f | 11171 | switch (opcode) { |
89e68b57 | 11172 | case 0x01: /* SQADD, UQADD */ |
c7715b6b RH |
11173 | if (u) { |
11174 | gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_uqadd_qc, size); | |
11175 | } else { | |
11176 | gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_sqadd_qc, size); | |
11177 | } | |
89e68b57 RH |
11178 | return; |
11179 | case 0x05: /* SQSUB, UQSUB */ | |
c7715b6b RH |
11180 | if (u) { |
11181 | gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_uqsub_qc, size); | |
11182 | } else { | |
11183 | gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_sqsub_qc, size); | |
11184 | } | |
89e68b57 | 11185 | return; |
87b74e8b | 11186 | case 0x08: /* SSHL, USHL */ |
8161b753 RH |
11187 | if (u) { |
11188 | gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_ushl, size); | |
11189 | } else { | |
11190 | gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_sshl, size); | |
11191 | } | |
87b74e8b | 11192 | return; |
264d2a48 RH |
11193 | case 0x0c: /* SMAX, UMAX */ |
11194 | if (u) { | |
11195 | gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_umax, size); | |
11196 | } else { | |
11197 | gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_smax, size); | |
11198 | } | |
11199 | return; | |
11200 | case 0x0d: /* SMIN, UMIN */ | |
11201 | if (u) { | |
11202 | gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_umin, size); | |
11203 | } else { | |
11204 | gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_smin, size); | |
11205 | } | |
11206 | return; | |
50c160d4 RH |
11207 | case 0xe: /* SABD, UABD */ |
11208 | if (u) { | |
11209 | gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_uabd, size); | |
11210 | } else { | |
11211 | gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_sabd, size); | |
11212 | } | |
11213 | return; | |
cfdb2c0c RH |
11214 | case 0xf: /* SABA, UABA */ |
11215 | if (u) { | |
11216 | gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_uaba, size); | |
11217 | } else { | |
11218 | gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_saba, size); | |
11219 | } | |
11220 | return; | |
bc48092f RH |
11221 | case 0x10: /* ADD, SUB */ |
11222 | if (u) { | |
11223 | gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_sub, size); | |
11224 | } else { | |
11225 | gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_add, size); | |
11226 | } | |
11227 | return; | |
0c7c55c4 RH |
11228 | case 0x13: /* MUL, PMUL */ |
11229 | if (!u) { /* MUL */ | |
11230 | gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_mul, size); | |
a21bb78e RH |
11231 | } else { /* PMUL */ |
11232 | gen_gvec_op3_ool(s, is_q, rd, rn, rm, 0, gen_helper_gvec_pmul_b); | |
0c7c55c4 | 11233 | } |
a21bb78e | 11234 | return; |
0c7c55c4 RH |
11235 | case 0x12: /* MLA, MLS */ |
11236 | if (u) { | |
27106320 | 11237 | gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_mls, size); |
0c7c55c4 | 11238 | } else { |
27106320 | 11239 | gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_mla, size); |
0c7c55c4 RH |
11240 | } |
11241 | return; | |
79d61de6 RH |
11242 | case 0x11: |
11243 | if (!u) { /* CMTST */ | |
8161b753 | 11244 | gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_cmtst, size); |
79d61de6 RH |
11245 | return; |
11246 | } | |
11247 | /* else CMEQ */ | |
11248 | cond = TCG_COND_EQ; | |
11249 | goto do_gvec_cmp; | |
11250 | case 0x06: /* CMGT, CMHI */ | |
11251 | cond = u ? TCG_COND_GTU : TCG_COND_GT; | |
11252 | goto do_gvec_cmp; | |
11253 | case 0x07: /* CMGE, CMHS */ | |
11254 | cond = u ? TCG_COND_GEU : TCG_COND_GE; | |
11255 | do_gvec_cmp: | |
11256 | tcg_gen_gvec_cmp(cond, size, vec_full_reg_offset(s, rd), | |
11257 | vec_full_reg_offset(s, rn), | |
11258 | vec_full_reg_offset(s, rm), | |
11259 | is_q ? 16 : 8, vec_full_reg_size(s)); | |
11260 | return; | |
bc48092f RH |
11261 | } |
11262 | ||
1f8a73af | 11263 | if (size == 3) { |
220ad4ca PM |
11264 | assert(is_q); |
11265 | for (pass = 0; pass < 2; pass++) { | |
1f8a73af PM |
11266 | TCGv_i64 tcg_op1 = tcg_temp_new_i64(); |
11267 | TCGv_i64 tcg_op2 = tcg_temp_new_i64(); | |
11268 | TCGv_i64 tcg_res = tcg_temp_new_i64(); | |
11269 | ||
11270 | read_vec_element(s, tcg_op1, rn, pass, MO_64); | |
11271 | read_vec_element(s, tcg_op2, rm, pass, MO_64); | |
11272 | ||
11273 | handle_3same_64(s, opcode, u, tcg_res, tcg_op1, tcg_op2); | |
11274 | ||
11275 | write_vec_element(s, tcg_res, rd, pass, MO_64); | |
11276 | ||
11277 | tcg_temp_free_i64(tcg_res); | |
11278 | tcg_temp_free_i64(tcg_op1); | |
11279 | tcg_temp_free_i64(tcg_op2); | |
11280 | } | |
11281 | } else { | |
11282 | for (pass = 0; pass < (is_q ? 4 : 2); pass++) { | |
11283 | TCGv_i32 tcg_op1 = tcg_temp_new_i32(); | |
11284 | TCGv_i32 tcg_op2 = tcg_temp_new_i32(); | |
11285 | TCGv_i32 tcg_res = tcg_temp_new_i32(); | |
6d9571f7 PM |
11286 | NeonGenTwoOpFn *genfn = NULL; |
11287 | NeonGenTwoOpEnvFn *genenvfn = NULL; | |
1f8a73af PM |
11288 | |
11289 | read_vec_element_i32(s, tcg_op1, rn, pass, MO_32); | |
11290 | read_vec_element_i32(s, tcg_op2, rm, pass, MO_32); | |
11291 | ||
11292 | switch (opcode) { | |
8b12a0cf PM |
11293 | case 0x0: /* SHADD, UHADD */ |
11294 | { | |
11295 | static NeonGenTwoOpFn * const fns[3][2] = { | |
11296 | { gen_helper_neon_hadd_s8, gen_helper_neon_hadd_u8 }, | |
11297 | { gen_helper_neon_hadd_s16, gen_helper_neon_hadd_u16 }, | |
11298 | { gen_helper_neon_hadd_s32, gen_helper_neon_hadd_u32 }, | |
11299 | }; | |
11300 | genfn = fns[size][u]; | |
11301 | break; | |
11302 | } | |
8b12a0cf PM |
11303 | case 0x2: /* SRHADD, URHADD */ |
11304 | { | |
11305 | static NeonGenTwoOpFn * const fns[3][2] = { | |
11306 | { gen_helper_neon_rhadd_s8, gen_helper_neon_rhadd_u8 }, | |
11307 | { gen_helper_neon_rhadd_s16, gen_helper_neon_rhadd_u16 }, | |
11308 | { gen_helper_neon_rhadd_s32, gen_helper_neon_rhadd_u32 }, | |
11309 | }; | |
11310 | genfn = fns[size][u]; | |
11311 | break; | |
11312 | } | |
11313 | case 0x4: /* SHSUB, UHSUB */ | |
11314 | { | |
11315 | static NeonGenTwoOpFn * const fns[3][2] = { | |
11316 | { gen_helper_neon_hsub_s8, gen_helper_neon_hsub_u8 }, | |
11317 | { gen_helper_neon_hsub_s16, gen_helper_neon_hsub_u16 }, | |
11318 | { gen_helper_neon_hsub_s32, gen_helper_neon_hsub_u32 }, | |
11319 | }; | |
11320 | genfn = fns[size][u]; | |
11321 | break; | |
11322 | } | |
6d9571f7 PM |
11323 | case 0x9: /* SQSHL, UQSHL */ |
11324 | { | |
11325 | static NeonGenTwoOpEnvFn * const fns[3][2] = { | |
11326 | { gen_helper_neon_qshl_s8, gen_helper_neon_qshl_u8 }, | |
11327 | { gen_helper_neon_qshl_s16, gen_helper_neon_qshl_u16 }, | |
11328 | { gen_helper_neon_qshl_s32, gen_helper_neon_qshl_u32 }, | |
11329 | }; | |
11330 | genenvfn = fns[size][u]; | |
11331 | break; | |
11332 | } | |
11333 | case 0xa: /* SRSHL, URSHL */ | |
11334 | { | |
11335 | static NeonGenTwoOpFn * const fns[3][2] = { | |
11336 | { gen_helper_neon_rshl_s8, gen_helper_neon_rshl_u8 }, | |
11337 | { gen_helper_neon_rshl_s16, gen_helper_neon_rshl_u16 }, | |
11338 | { gen_helper_neon_rshl_s32, gen_helper_neon_rshl_u32 }, | |
11339 | }; | |
11340 | genfn = fns[size][u]; | |
11341 | break; | |
11342 | } | |
11343 | case 0xb: /* SQRSHL, UQRSHL */ | |
11344 | { | |
11345 | static NeonGenTwoOpEnvFn * const fns[3][2] = { | |
11346 | { gen_helper_neon_qrshl_s8, gen_helper_neon_qrshl_u8 }, | |
11347 | { gen_helper_neon_qrshl_s16, gen_helper_neon_qrshl_u16 }, | |
11348 | { gen_helper_neon_qrshl_s32, gen_helper_neon_qrshl_u32 }, | |
11349 | }; | |
11350 | genenvfn = fns[size][u]; | |
11351 | break; | |
11352 | } | |
8b12a0cf PM |
11353 | case 0x16: /* SQDMULH, SQRDMULH */ |
11354 | { | |
11355 | static NeonGenTwoOpEnvFn * const fns[2][2] = { | |
11356 | { gen_helper_neon_qdmulh_s16, gen_helper_neon_qrdmulh_s16 }, | |
11357 | { gen_helper_neon_qdmulh_s32, gen_helper_neon_qrdmulh_s32 }, | |
11358 | }; | |
11359 | assert(size == 1 || size == 2); | |
11360 | genenvfn = fns[size - 1][u]; | |
11361 | break; | |
11362 | } | |
1f8a73af PM |
11363 | default: |
11364 | g_assert_not_reached(); | |
11365 | } | |
11366 | ||
6d9571f7 PM |
11367 | if (genenvfn) { |
11368 | genenvfn(tcg_res, cpu_env, tcg_op1, tcg_op2); | |
11369 | } else { | |
11370 | genfn(tcg_res, tcg_op1, tcg_op2); | |
11371 | } | |
1f8a73af PM |
11372 | |
11373 | write_vec_element_i32(s, tcg_res, rd, pass, MO_32); | |
11374 | ||
11375 | tcg_temp_free_i32(tcg_res); | |
11376 | tcg_temp_free_i32(tcg_op1); | |
11377 | tcg_temp_free_i32(tcg_op2); | |
11378 | } | |
11379 | } | |
4ff55bcb | 11380 | clear_vec_high(s, is_q, rd); |
e1cea114 PM |
11381 | } |
11382 | ||
4ce31af4 | 11383 | /* AdvSIMD three same |
384b26fb AB |
11384 | * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0 |
11385 | * +---+---+---+-----------+------+---+------+--------+---+------+------+ | |
11386 | * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd | | |
11387 | * +---+---+---+-----------+------+---+------+--------+---+------+------+ | |
11388 | */ | |
11389 | static void disas_simd_three_reg_same(DisasContext *s, uint32_t insn) | |
11390 | { | |
e1cea114 PM |
11391 | int opcode = extract32(insn, 11, 5); |
11392 | ||
11393 | switch (opcode) { | |
11394 | case 0x3: /* logic ops */ | |
11395 | disas_simd_3same_logic(s, insn); | |
11396 | break; | |
11397 | case 0x17: /* ADDP */ | |
11398 | case 0x14: /* SMAXP, UMAXP */ | |
11399 | case 0x15: /* SMINP, UMINP */ | |
bc242f9b | 11400 | { |
e1cea114 | 11401 | /* Pairwise operations */ |
bc242f9b AB |
11402 | int is_q = extract32(insn, 30, 1); |
11403 | int u = extract32(insn, 29, 1); | |
11404 | int size = extract32(insn, 22, 2); | |
11405 | int rm = extract32(insn, 16, 5); | |
11406 | int rn = extract32(insn, 5, 5); | |
11407 | int rd = extract32(insn, 0, 5); | |
11408 | if (opcode == 0x17) { | |
11409 | if (u || (size == 3 && !is_q)) { | |
11410 | unallocated_encoding(s); | |
11411 | return; | |
11412 | } | |
11413 | } else { | |
11414 | if (size == 3) { | |
11415 | unallocated_encoding(s); | |
11416 | return; | |
11417 | } | |
11418 | } | |
11419 | handle_simd_3same_pair(s, is_q, u, opcode, size, rn, rm, rd); | |
e1cea114 | 11420 | break; |
bc242f9b | 11421 | } |
e1cea114 PM |
11422 | case 0x18 ... 0x31: |
11423 | /* floating point ops, sz[1] and U are part of opcode */ | |
11424 | disas_simd_3same_float(s, insn); | |
11425 | break; | |
11426 | default: | |
11427 | disas_simd_3same_int(s, insn); | |
11428 | break; | |
11429 | } | |
384b26fb AB |
11430 | } |
11431 | ||
376e8d6c AB |
11432 | /* |
11433 | * Advanced SIMD three same (ARMv8.2 FP16 variants) | |
11434 | * | |
11435 | * 31 30 29 28 24 23 22 21 20 16 15 14 13 11 10 9 5 4 0 | |
11436 | * +---+---+---+-----------+---------+------+-----+--------+---+------+------+ | |
11437 | * | 0 | Q | U | 0 1 1 1 0 | a | 1 0 | Rm | 0 0 | opcode | 1 | Rn | Rd | | |
11438 | * +---+---+---+-----------+---------+------+-----+--------+---+------+------+ | |
11439 | * | |
11440 | * This includes FMULX, FCMEQ (register), FRECPS, FRSQRTS, FCMGE | |
11441 | * (register), FACGE, FABD, FCMGT (register) and FACGT. | |
11442 | * | |
11443 | */ | |
11444 | static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn) | |
11445 | { | |
11446 | int opcode, fpopcode; | |
11447 | int is_q, u, a, rm, rn, rd; | |
11448 | int datasize, elements; | |
11449 | int pass; | |
11450 | TCGv_ptr fpst; | |
7a2c6e61 | 11451 | bool pairwise = false; |
376e8d6c | 11452 | |
5763190f | 11453 | if (!dc_isar_feature(aa64_fp16, s)) { |
376e8d6c AB |
11454 | unallocated_encoding(s); |
11455 | return; | |
11456 | } | |
11457 | ||
11458 | if (!fp_access_check(s)) { | |
11459 | return; | |
11460 | } | |
11461 | ||
11462 | /* For these floating point ops, the U, a and opcode bits | |
11463 | * together indicate the operation. | |
11464 | */ | |
11465 | opcode = extract32(insn, 11, 3); | |
11466 | u = extract32(insn, 29, 1); | |
11467 | a = extract32(insn, 23, 1); | |
11468 | is_q = extract32(insn, 30, 1); | |
11469 | rm = extract32(insn, 16, 5); | |
11470 | rn = extract32(insn, 5, 5); | |
11471 | rd = extract32(insn, 0, 5); | |
11472 | ||
11473 | fpopcode = opcode | (a << 3) | (u << 4); | |
11474 | datasize = is_q ? 128 : 64; | |
11475 | elements = datasize / 16; | |
11476 | ||
7a2c6e61 AB |
11477 | switch (fpopcode) { |
11478 | case 0x10: /* FMAXNMP */ | |
11479 | case 0x12: /* FADDP */ | |
11480 | case 0x16: /* FMAXP */ | |
11481 | case 0x18: /* FMINNMP */ | |
11482 | case 0x1e: /* FMINP */ | |
11483 | pairwise = true; | |
11484 | break; | |
11485 | } | |
11486 | ||
376e8d6c AB |
11487 | fpst = get_fpstatus_ptr(true); |
11488 | ||
7a2c6e61 AB |
11489 | if (pairwise) { |
11490 | int maxpass = is_q ? 8 : 4; | |
376e8d6c AB |
11491 | TCGv_i32 tcg_op1 = tcg_temp_new_i32(); |
11492 | TCGv_i32 tcg_op2 = tcg_temp_new_i32(); | |
7a2c6e61 | 11493 | TCGv_i32 tcg_res[8]; |
376e8d6c | 11494 | |
7a2c6e61 AB |
11495 | for (pass = 0; pass < maxpass; pass++) { |
11496 | int passreg = pass < (maxpass / 2) ? rn : rm; | |
11497 | int passelt = (pass << 1) & (maxpass - 1); | |
376e8d6c | 11498 | |
7a2c6e61 AB |
11499 | read_vec_element_i32(s, tcg_op1, passreg, passelt, MO_16); |
11500 | read_vec_element_i32(s, tcg_op2, passreg, passelt + 1, MO_16); | |
11501 | tcg_res[pass] = tcg_temp_new_i32(); | |
11502 | ||
11503 | switch (fpopcode) { | |
11504 | case 0x10: /* FMAXNMP */ | |
11505 | gen_helper_advsimd_maxnumh(tcg_res[pass], tcg_op1, tcg_op2, | |
11506 | fpst); | |
11507 | break; | |
11508 | case 0x12: /* FADDP */ | |
11509 | gen_helper_advsimd_addh(tcg_res[pass], tcg_op1, tcg_op2, fpst); | |
11510 | break; | |
11511 | case 0x16: /* FMAXP */ | |
11512 | gen_helper_advsimd_maxh(tcg_res[pass], tcg_op1, tcg_op2, fpst); | |
11513 | break; | |
11514 | case 0x18: /* FMINNMP */ | |
11515 | gen_helper_advsimd_minnumh(tcg_res[pass], tcg_op1, tcg_op2, | |
11516 | fpst); | |
11517 | break; | |
11518 | case 0x1e: /* FMINP */ | |
11519 | gen_helper_advsimd_minh(tcg_res[pass], tcg_op1, tcg_op2, fpst); | |
11520 | break; | |
11521 | default: | |
11522 | g_assert_not_reached(); | |
11523 | } | |
11524 | } | |
11525 | ||
11526 | for (pass = 0; pass < maxpass; pass++) { | |
11527 | write_vec_element_i32(s, tcg_res[pass], rd, pass, MO_16); | |
11528 | tcg_temp_free_i32(tcg_res[pass]); | |
376e8d6c AB |
11529 | } |
11530 | ||
376e8d6c AB |
11531 | tcg_temp_free_i32(tcg_op1); |
11532 | tcg_temp_free_i32(tcg_op2); | |
7a2c6e61 AB |
11533 | |
11534 | } else { | |
11535 | for (pass = 0; pass < elements; pass++) { | |
11536 | TCGv_i32 tcg_op1 = tcg_temp_new_i32(); | |
11537 | TCGv_i32 tcg_op2 = tcg_temp_new_i32(); | |
11538 | TCGv_i32 tcg_res = tcg_temp_new_i32(); | |
11539 | ||
11540 | read_vec_element_i32(s, tcg_op1, rn, pass, MO_16); | |
11541 | read_vec_element_i32(s, tcg_op2, rm, pass, MO_16); | |
11542 | ||
11543 | switch (fpopcode) { | |
11544 | case 0x0: /* FMAXNM */ | |
11545 | gen_helper_advsimd_maxnumh(tcg_res, tcg_op1, tcg_op2, fpst); | |
11546 | break; | |
11547 | case 0x1: /* FMLA */ | |
11548 | read_vec_element_i32(s, tcg_res, rd, pass, MO_16); | |
11549 | gen_helper_advsimd_muladdh(tcg_res, tcg_op1, tcg_op2, tcg_res, | |
11550 | fpst); | |
11551 | break; | |
11552 | case 0x2: /* FADD */ | |
11553 | gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst); | |
11554 | break; | |
11555 | case 0x3: /* FMULX */ | |
11556 | gen_helper_advsimd_mulxh(tcg_res, tcg_op1, tcg_op2, fpst); | |
11557 | break; | |
11558 | case 0x4: /* FCMEQ */ | |
11559 | gen_helper_advsimd_ceq_f16(tcg_res, tcg_op1, tcg_op2, fpst); | |
11560 | break; | |
11561 | case 0x6: /* FMAX */ | |
11562 | gen_helper_advsimd_maxh(tcg_res, tcg_op1, tcg_op2, fpst); | |
11563 | break; | |
11564 | case 0x7: /* FRECPS */ | |
11565 | gen_helper_recpsf_f16(tcg_res, tcg_op1, tcg_op2, fpst); | |
11566 | break; | |
11567 | case 0x8: /* FMINNM */ | |
11568 | gen_helper_advsimd_minnumh(tcg_res, tcg_op1, tcg_op2, fpst); | |
11569 | break; | |
11570 | case 0x9: /* FMLS */ | |
11571 | /* As usual for ARM, separate negation for fused multiply-add */ | |
11572 | tcg_gen_xori_i32(tcg_op1, tcg_op1, 0x8000); | |
11573 | read_vec_element_i32(s, tcg_res, rd, pass, MO_16); | |
11574 | gen_helper_advsimd_muladdh(tcg_res, tcg_op1, tcg_op2, tcg_res, | |
11575 | fpst); | |
11576 | break; | |
11577 | case 0xa: /* FSUB */ | |
11578 | gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst); | |
11579 | break; | |
11580 | case 0xe: /* FMIN */ | |
11581 | gen_helper_advsimd_minh(tcg_res, tcg_op1, tcg_op2, fpst); | |
11582 | break; | |
11583 | case 0xf: /* FRSQRTS */ | |
11584 | gen_helper_rsqrtsf_f16(tcg_res, tcg_op1, tcg_op2, fpst); | |
11585 | break; | |
11586 | case 0x13: /* FMUL */ | |
11587 | gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst); | |
11588 | break; | |
11589 | case 0x14: /* FCMGE */ | |
11590 | gen_helper_advsimd_cge_f16(tcg_res, tcg_op1, tcg_op2, fpst); | |
11591 | break; | |
11592 | case 0x15: /* FACGE */ | |
11593 | gen_helper_advsimd_acge_f16(tcg_res, tcg_op1, tcg_op2, fpst); | |
11594 | break; | |
11595 | case 0x17: /* FDIV */ | |
11596 | gen_helper_advsimd_divh(tcg_res, tcg_op1, tcg_op2, fpst); | |
11597 | break; | |
11598 | case 0x1a: /* FABD */ | |
11599 | gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst); | |
11600 | tcg_gen_andi_i32(tcg_res, tcg_res, 0x7fff); | |
11601 | break; | |
11602 | case 0x1c: /* FCMGT */ | |
11603 | gen_helper_advsimd_cgt_f16(tcg_res, tcg_op1, tcg_op2, fpst); | |
11604 | break; | |
11605 | case 0x1d: /* FACGT */ | |
11606 | gen_helper_advsimd_acgt_f16(tcg_res, tcg_op1, tcg_op2, fpst); | |
11607 | break; | |
11608 | default: | |
11609 | fprintf(stderr, "%s: insn %#04x, fpop %#2x @ %#" PRIx64 "\n", | |
43722a6d | 11610 | __func__, insn, fpopcode, s->pc_curr); |
7a2c6e61 AB |
11611 | g_assert_not_reached(); |
11612 | } | |
11613 | ||
11614 | write_vec_element_i32(s, tcg_res, rd, pass, MO_16); | |
11615 | tcg_temp_free_i32(tcg_res); | |
11616 | tcg_temp_free_i32(tcg_op1); | |
11617 | tcg_temp_free_i32(tcg_op2); | |
11618 | } | |
376e8d6c AB |
11619 | } |
11620 | ||
11621 | tcg_temp_free_ptr(fpst); | |
11622 | ||
11623 | clear_vec_high(s, is_q, rd); | |
11624 | } | |
11625 | ||
e7186d82 RH |
11626 | /* AdvSIMD three same extra |
11627 | * 31 30 29 28 24 23 22 21 20 16 15 14 11 10 9 5 4 0 | |
11628 | * +---+---+---+-----------+------+---+------+---+--------+---+----+----+ | |
11629 | * | 0 | Q | U | 0 1 1 1 0 | size | 0 | Rm | 1 | opcode | 1 | Rn | Rd | | |
11630 | * +---+---+---+-----------+------+---+------+---+--------+---+----+----+ | |
11631 | */ | |
11632 | static void disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn) | |
11633 | { | |
11634 | int rd = extract32(insn, 0, 5); | |
11635 | int rn = extract32(insn, 5, 5); | |
11636 | int opcode = extract32(insn, 11, 4); | |
11637 | int rm = extract32(insn, 16, 5); | |
11638 | int size = extract32(insn, 22, 2); | |
11639 | bool u = extract32(insn, 29, 1); | |
11640 | bool is_q = extract32(insn, 30, 1); | |
962fcbf2 RH |
11641 | bool feature; |
11642 | int rot; | |
e7186d82 RH |
11643 | |
11644 | switch (u * 16 + opcode) { | |
11645 | case 0x10: /* SQRDMLAH (vector) */ | |
11646 | case 0x11: /* SQRDMLSH (vector) */ | |
11647 | if (size != 1 && size != 2) { | |
11648 | unallocated_encoding(s); | |
11649 | return; | |
11650 | } | |
962fcbf2 | 11651 | feature = dc_isar_feature(aa64_rdm, s); |
e7186d82 | 11652 | break; |
26c470a7 RH |
11653 | case 0x02: /* SDOT (vector) */ |
11654 | case 0x12: /* UDOT (vector) */ | |
11655 | if (size != MO_32) { | |
11656 | unallocated_encoding(s); | |
11657 | return; | |
11658 | } | |
962fcbf2 | 11659 | feature = dc_isar_feature(aa64_dp, s); |
26c470a7 | 11660 | break; |
b8a4a96d RH |
11661 | case 0x18: /* FCMLA, #0 */ |
11662 | case 0x19: /* FCMLA, #90 */ | |
11663 | case 0x1a: /* FCMLA, #180 */ | |
11664 | case 0x1b: /* FCMLA, #270 */ | |
11665 | case 0x1c: /* FCADD, #90 */ | |
11666 | case 0x1e: /* FCADD, #270 */ | |
1695cd61 | 11667 | if (size == 0 |
5763190f | 11668 | || (size == 1 && !dc_isar_feature(aa64_fp16, s)) |
1695cd61 RH |
11669 | || (size == 3 && !is_q)) { |
11670 | unallocated_encoding(s); | |
11671 | return; | |
11672 | } | |
962fcbf2 | 11673 | feature = dc_isar_feature(aa64_fcma, s); |
1695cd61 | 11674 | break; |
e7186d82 RH |
11675 | default: |
11676 | unallocated_encoding(s); | |
11677 | return; | |
11678 | } | |
962fcbf2 | 11679 | if (!feature) { |
e7186d82 RH |
11680 | unallocated_encoding(s); |
11681 | return; | |
11682 | } | |
11683 | if (!fp_access_check(s)) { | |
11684 | return; | |
11685 | } | |
11686 | ||
11687 | switch (opcode) { | |
11688 | case 0x0: /* SQRDMLAH (vector) */ | |
146aa66c | 11689 | gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_sqrdmlah_qc, size); |
e7186d82 RH |
11690 | return; |
11691 | ||
11692 | case 0x1: /* SQRDMLSH (vector) */ | |
146aa66c | 11693 | gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_sqrdmlsh_qc, size); |
e7186d82 RH |
11694 | return; |
11695 | ||
26c470a7 RH |
11696 | case 0x2: /* SDOT / UDOT */ |
11697 | gen_gvec_op3_ool(s, is_q, rd, rn, rm, 0, | |
11698 | u ? gen_helper_gvec_udot_b : gen_helper_gvec_sdot_b); | |
11699 | return; | |
11700 | ||
d17b7cdc RH |
11701 | case 0x8: /* FCMLA, #0 */ |
11702 | case 0x9: /* FCMLA, #90 */ | |
11703 | case 0xa: /* FCMLA, #180 */ | |
11704 | case 0xb: /* FCMLA, #270 */ | |
11705 | rot = extract32(opcode, 0, 2); | |
11706 | switch (size) { | |
11707 | case 1: | |
11708 | gen_gvec_op3_fpst(s, is_q, rd, rn, rm, true, rot, | |
11709 | gen_helper_gvec_fcmlah); | |
11710 | break; | |
11711 | case 2: | |
11712 | gen_gvec_op3_fpst(s, is_q, rd, rn, rm, false, rot, | |
11713 | gen_helper_gvec_fcmlas); | |
11714 | break; | |
11715 | case 3: | |
11716 | gen_gvec_op3_fpst(s, is_q, rd, rn, rm, false, rot, | |
11717 | gen_helper_gvec_fcmlad); | |
11718 | break; | |
11719 | default: | |
11720 | g_assert_not_reached(); | |
11721 | } | |
11722 | return; | |
11723 | ||
1695cd61 RH |
11724 | case 0xc: /* FCADD, #90 */ |
11725 | case 0xe: /* FCADD, #270 */ | |
11726 | rot = extract32(opcode, 1, 1); | |
11727 | switch (size) { | |
11728 | case 1: | |
11729 | gen_gvec_op3_fpst(s, is_q, rd, rn, rm, size == 1, rot, | |
11730 | gen_helper_gvec_fcaddh); | |
11731 | break; | |
11732 | case 2: | |
11733 | gen_gvec_op3_fpst(s, is_q, rd, rn, rm, size == 1, rot, | |
11734 | gen_helper_gvec_fcadds); | |
11735 | break; | |
11736 | case 3: | |
11737 | gen_gvec_op3_fpst(s, is_q, rd, rn, rm, size == 1, rot, | |
11738 | gen_helper_gvec_fcaddd); | |
11739 | break; | |
11740 | default: | |
11741 | g_assert_not_reached(); | |
11742 | } | |
11743 | return; | |
11744 | ||
e7186d82 RH |
11745 | default: |
11746 | g_assert_not_reached(); | |
11747 | } | |
11748 | } | |
11749 | ||
931c8cc2 PM |
11750 | static void handle_2misc_widening(DisasContext *s, int opcode, bool is_q, |
11751 | int size, int rn, int rd) | |
11752 | { | |
11753 | /* Handle 2-reg-misc ops which are widening (so each size element | |
11754 | * in the source becomes a 2*size element in the destination. | |
11755 | * The only instruction like this is FCVTL. | |
11756 | */ | |
11757 | int pass; | |
11758 | ||
11759 | if (size == 3) { | |
11760 | /* 32 -> 64 bit fp conversion */ | |
11761 | TCGv_i64 tcg_res[2]; | |
11762 | int srcelt = is_q ? 2 : 0; | |
11763 | ||
11764 | for (pass = 0; pass < 2; pass++) { | |
11765 | TCGv_i32 tcg_op = tcg_temp_new_i32(); | |
11766 | tcg_res[pass] = tcg_temp_new_i64(); | |
11767 | ||
11768 | read_vec_element_i32(s, tcg_op, rn, srcelt + pass, MO_32); | |
11769 | gen_helper_vfp_fcvtds(tcg_res[pass], tcg_op, cpu_env); | |
11770 | tcg_temp_free_i32(tcg_op); | |
11771 | } | |
11772 | for (pass = 0; pass < 2; pass++) { | |
11773 | write_vec_element(s, tcg_res[pass], rd, pass, MO_64); | |
11774 | tcg_temp_free_i64(tcg_res[pass]); | |
11775 | } | |
11776 | } else { | |
11777 | /* 16 -> 32 bit fp conversion */ | |
11778 | int srcelt = is_q ? 4 : 0; | |
11779 | TCGv_i32 tcg_res[4]; | |
486624fc AB |
11780 | TCGv_ptr fpst = get_fpstatus_ptr(false); |
11781 | TCGv_i32 ahp = get_ahp_flag(); | |
931c8cc2 PM |
11782 | |
11783 | for (pass = 0; pass < 4; pass++) { | |
11784 | tcg_res[pass] = tcg_temp_new_i32(); | |
11785 | ||
11786 | read_vec_element_i32(s, tcg_res[pass], rn, srcelt + pass, MO_16); | |
11787 | gen_helper_vfp_fcvt_f16_to_f32(tcg_res[pass], tcg_res[pass], | |
486624fc | 11788 | fpst, ahp); |
931c8cc2 PM |
11789 | } |
11790 | for (pass = 0; pass < 4; pass++) { | |
11791 | write_vec_element_i32(s, tcg_res[pass], rd, pass, MO_32); | |
11792 | tcg_temp_free_i32(tcg_res[pass]); | |
11793 | } | |
486624fc AB |
11794 | |
11795 | tcg_temp_free_ptr(fpst); | |
11796 | tcg_temp_free_i32(ahp); | |
931c8cc2 PM |
11797 | } |
11798 | } | |
11799 | ||
39d82118 AB |
11800 | static void handle_rev(DisasContext *s, int opcode, bool u, |
11801 | bool is_q, int size, int rn, int rd) | |
11802 | { | |
11803 | int op = (opcode << 1) | u; | |
11804 | int opsz = op + size; | |
11805 | int grp_size = 3 - opsz; | |
11806 | int dsize = is_q ? 128 : 64; | |
11807 | int i; | |
11808 | ||
11809 | if (opsz >= 3) { | |
11810 | unallocated_encoding(s); | |
11811 | return; | |
11812 | } | |
11813 | ||
8c6afa6a PM |
11814 | if (!fp_access_check(s)) { |
11815 | return; | |
11816 | } | |
11817 | ||
39d82118 AB |
11818 | if (size == 0) { |
11819 | /* Special case bytes, use bswap op on each group of elements */ | |
11820 | int groups = dsize / (8 << grp_size); | |
11821 | ||
11822 | for (i = 0; i < groups; i++) { | |
11823 | TCGv_i64 tcg_tmp = tcg_temp_new_i64(); | |
11824 | ||
11825 | read_vec_element(s, tcg_tmp, rn, i, grp_size); | |
11826 | switch (grp_size) { | |
11827 | case MO_16: | |
11828 | tcg_gen_bswap16_i64(tcg_tmp, tcg_tmp); | |
11829 | break; | |
11830 | case MO_32: | |
11831 | tcg_gen_bswap32_i64(tcg_tmp, tcg_tmp); | |
11832 | break; | |
11833 | case MO_64: | |
11834 | tcg_gen_bswap64_i64(tcg_tmp, tcg_tmp); | |
11835 | break; | |
11836 | default: | |
11837 | g_assert_not_reached(); | |
11838 | } | |
11839 | write_vec_element(s, tcg_tmp, rd, i, grp_size); | |
11840 | tcg_temp_free_i64(tcg_tmp); | |
11841 | } | |
4ff55bcb | 11842 | clear_vec_high(s, is_q, rd); |
39d82118 AB |
11843 | } else { |
11844 | int revmask = (1 << grp_size) - 1; | |
11845 | int esize = 8 << size; | |
11846 | int elements = dsize / esize; | |
11847 | TCGv_i64 tcg_rn = tcg_temp_new_i64(); | |
11848 | TCGv_i64 tcg_rd = tcg_const_i64(0); | |
11849 | TCGv_i64 tcg_rd_hi = tcg_const_i64(0); | |
11850 | ||
11851 | for (i = 0; i < elements; i++) { | |
11852 | int e_rev = (i & 0xf) ^ revmask; | |
11853 | int off = e_rev * esize; | |
11854 | read_vec_element(s, tcg_rn, rn, i, size); | |
11855 | if (off >= 64) { | |
11856 | tcg_gen_deposit_i64(tcg_rd_hi, tcg_rd_hi, | |
11857 | tcg_rn, off - 64, esize); | |
11858 | } else { | |
11859 | tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_rn, off, esize); | |
11860 | } | |
11861 | } | |
11862 | write_vec_element(s, tcg_rd, rd, 0, MO_64); | |
11863 | write_vec_element(s, tcg_rd_hi, rd, 1, MO_64); | |
11864 | ||
11865 | tcg_temp_free_i64(tcg_rd_hi); | |
11866 | tcg_temp_free_i64(tcg_rd); | |
11867 | tcg_temp_free_i64(tcg_rn); | |
11868 | } | |
11869 | } | |
11870 | ||
6781fa11 PM |
11871 | static void handle_2misc_pairwise(DisasContext *s, int opcode, bool u, |
11872 | bool is_q, int size, int rn, int rd) | |
11873 | { | |
11874 | /* Implement the pairwise operations from 2-misc: | |
11875 | * SADDLP, UADDLP, SADALP, UADALP. | |
11876 | * These all add pairs of elements in the input to produce a | |
11877 | * double-width result element in the output (possibly accumulating). | |
11878 | */ | |
11879 | bool accum = (opcode == 0x6); | |
11880 | int maxpass = is_q ? 2 : 1; | |
11881 | int pass; | |
11882 | TCGv_i64 tcg_res[2]; | |
11883 | ||
11884 | if (size == 2) { | |
11885 | /* 32 + 32 -> 64 op */ | |
14776ab5 | 11886 | MemOp memop = size + (u ? 0 : MO_SIGN); |
6781fa11 PM |
11887 | |
11888 | for (pass = 0; pass < maxpass; pass++) { | |
11889 | TCGv_i64 tcg_op1 = tcg_temp_new_i64(); | |
11890 | TCGv_i64 tcg_op2 = tcg_temp_new_i64(); | |
11891 | ||
11892 | tcg_res[pass] = tcg_temp_new_i64(); | |
11893 | ||
11894 | read_vec_element(s, tcg_op1, rn, pass * 2, memop); | |
11895 | read_vec_element(s, tcg_op2, rn, pass * 2 + 1, memop); | |
11896 | tcg_gen_add_i64(tcg_res[pass], tcg_op1, tcg_op2); | |
11897 | if (accum) { | |
11898 | read_vec_element(s, tcg_op1, rd, pass, MO_64); | |
11899 | tcg_gen_add_i64(tcg_res[pass], tcg_res[pass], tcg_op1); | |
11900 | } | |
11901 | ||
11902 | tcg_temp_free_i64(tcg_op1); | |
11903 | tcg_temp_free_i64(tcg_op2); | |
11904 | } | |
11905 | } else { | |
11906 | for (pass = 0; pass < maxpass; pass++) { | |
11907 | TCGv_i64 tcg_op = tcg_temp_new_i64(); | |
039f4e80 PM |
11908 | NeonGenOne64OpFn *genfn; |
11909 | static NeonGenOne64OpFn * const fns[2][2] = { | |
6781fa11 PM |
11910 | { gen_helper_neon_addlp_s8, gen_helper_neon_addlp_u8 }, |
11911 | { gen_helper_neon_addlp_s16, gen_helper_neon_addlp_u16 }, | |
11912 | }; | |
11913 | ||
11914 | genfn = fns[size][u]; | |
11915 | ||
11916 | tcg_res[pass] = tcg_temp_new_i64(); | |
11917 | ||
11918 | read_vec_element(s, tcg_op, rn, pass, MO_64); | |
11919 | genfn(tcg_res[pass], tcg_op); | |
11920 | ||
11921 | if (accum) { | |
11922 | read_vec_element(s, tcg_op, rd, pass, MO_64); | |
11923 | if (size == 0) { | |
11924 | gen_helper_neon_addl_u16(tcg_res[pass], | |
11925 | tcg_res[pass], tcg_op); | |
11926 | } else { | |
11927 | gen_helper_neon_addl_u32(tcg_res[pass], | |
11928 | tcg_res[pass], tcg_op); | |
11929 | } | |
11930 | } | |
11931 | tcg_temp_free_i64(tcg_op); | |
11932 | } | |
11933 | } | |
11934 | if (!is_q) { | |
11935 | tcg_res[1] = tcg_const_i64(0); | |
11936 | } | |
11937 | for (pass = 0; pass < 2; pass++) { | |
11938 | write_vec_element(s, tcg_res[pass], rd, pass, MO_64); | |
11939 | tcg_temp_free_i64(tcg_res[pass]); | |
11940 | } | |
11941 | } | |
11942 | ||
73a81d10 PM |
11943 | static void handle_shll(DisasContext *s, bool is_q, int size, int rn, int rd) |
11944 | { | |
11945 | /* Implement SHLL and SHLL2 */ | |
11946 | int pass; | |
11947 | int part = is_q ? 2 : 0; | |
11948 | TCGv_i64 tcg_res[2]; | |
11949 | ||
11950 | for (pass = 0; pass < 2; pass++) { | |
11951 | static NeonGenWidenFn * const widenfns[3] = { | |
11952 | gen_helper_neon_widen_u8, | |
11953 | gen_helper_neon_widen_u16, | |
11954 | tcg_gen_extu_i32_i64, | |
11955 | }; | |
11956 | NeonGenWidenFn *widenfn = widenfns[size]; | |
11957 | TCGv_i32 tcg_op = tcg_temp_new_i32(); | |
11958 | ||
11959 | read_vec_element_i32(s, tcg_op, rn, part + pass, MO_32); | |
11960 | tcg_res[pass] = tcg_temp_new_i64(); | |
11961 | widenfn(tcg_res[pass], tcg_op); | |
11962 | tcg_gen_shli_i64(tcg_res[pass], tcg_res[pass], 8 << size); | |
11963 | ||
11964 | tcg_temp_free_i32(tcg_op); | |
11965 | } | |
11966 | ||
11967 | for (pass = 0; pass < 2; pass++) { | |
11968 | write_vec_element(s, tcg_res[pass], rd, pass, MO_64); | |
11969 | tcg_temp_free_i64(tcg_res[pass]); | |
11970 | } | |
11971 | } | |
11972 | ||
4ce31af4 | 11973 | /* AdvSIMD two reg misc |
384b26fb AB |
11974 | * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0 |
11975 | * +---+---+---+-----------+------+-----------+--------+-----+------+------+ | |
11976 | * | 0 | Q | U | 0 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd | | |
11977 | * +---+---+---+-----------+------+-----------+--------+-----+------+------+ | |
11978 | */ | |
11979 | static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn) | |
11980 | { | |
45aecc6d PM |
11981 | int size = extract32(insn, 22, 2); |
11982 | int opcode = extract32(insn, 12, 5); | |
11983 | bool u = extract32(insn, 29, 1); | |
11984 | bool is_q = extract32(insn, 30, 1); | |
94b6c911 PM |
11985 | int rn = extract32(insn, 5, 5); |
11986 | int rd = extract32(insn, 0, 5); | |
04c7c6c2 PM |
11987 | bool need_fpstatus = false; |
11988 | bool need_rmode = false; | |
11989 | int rmode = -1; | |
11990 | TCGv_i32 tcg_rmode; | |
11991 | TCGv_ptr tcg_fpstatus; | |
45aecc6d PM |
11992 | |
11993 | switch (opcode) { | |
11994 | case 0x0: /* REV64, REV32 */ | |
11995 | case 0x1: /* REV16 */ | |
39d82118 | 11996 | handle_rev(s, opcode, u, is_q, size, rn, rd); |
45aecc6d | 11997 | return; |
86cbc418 PM |
11998 | case 0x5: /* CNT, NOT, RBIT */ |
11999 | if (u && size == 0) { | |
377ef731 | 12000 | /* NOT */ |
86cbc418 PM |
12001 | break; |
12002 | } else if (u && size == 1) { | |
12003 | /* RBIT */ | |
12004 | break; | |
12005 | } else if (!u && size == 0) { | |
12006 | /* CNT */ | |
12007 | break; | |
45aecc6d | 12008 | } |
86cbc418 | 12009 | unallocated_encoding(s); |
45aecc6d | 12010 | return; |
d980fd59 PM |
12011 | case 0x12: /* XTN, XTN2, SQXTUN, SQXTUN2 */ |
12012 | case 0x14: /* SQXTN, SQXTN2, UQXTN, UQXTN2 */ | |
12013 | if (size == 3) { | |
12014 | unallocated_encoding(s); | |
12015 | return; | |
12016 | } | |
8c6afa6a PM |
12017 | if (!fp_access_check(s)) { |
12018 | return; | |
12019 | } | |
12020 | ||
5201c136 | 12021 | handle_2misc_narrow(s, false, opcode, u, is_q, size, rn, rd); |
d980fd59 | 12022 | return; |
45aecc6d | 12023 | case 0x4: /* CLS, CLZ */ |
b05c3068 AB |
12024 | if (size == 3) { |
12025 | unallocated_encoding(s); | |
12026 | return; | |
12027 | } | |
12028 | break; | |
12029 | case 0x2: /* SADDLP, UADDLP */ | |
45aecc6d | 12030 | case 0x6: /* SADALP, UADALP */ |
45aecc6d PM |
12031 | if (size == 3) { |
12032 | unallocated_encoding(s); | |
12033 | return; | |
12034 | } | |
8c6afa6a PM |
12035 | if (!fp_access_check(s)) { |
12036 | return; | |
12037 | } | |
6781fa11 | 12038 | handle_2misc_pairwise(s, opcode, u, is_q, size, rn, rd); |
45aecc6d PM |
12039 | return; |
12040 | case 0x13: /* SHLL, SHLL2 */ | |
12041 | if (u == 0 || size == 3) { | |
12042 | unallocated_encoding(s); | |
12043 | return; | |
12044 | } | |
8c6afa6a PM |
12045 | if (!fp_access_check(s)) { |
12046 | return; | |
12047 | } | |
73a81d10 | 12048 | handle_shll(s, is_q, size, rn, rd); |
45aecc6d PM |
12049 | return; |
12050 | case 0xa: /* CMLT */ | |
12051 | if (u == 1) { | |
12052 | unallocated_encoding(s); | |
12053 | return; | |
12054 | } | |
12055 | /* fall through */ | |
45aecc6d PM |
12056 | case 0x8: /* CMGT, CMGE */ |
12057 | case 0x9: /* CMEQ, CMLE */ | |
12058 | case 0xb: /* ABS, NEG */ | |
94b6c911 PM |
12059 | if (size == 3 && !is_q) { |
12060 | unallocated_encoding(s); | |
12061 | return; | |
12062 | } | |
12063 | break; | |
12064 | case 0x3: /* SUQADD, USQADD */ | |
09e03735 AB |
12065 | if (size == 3 && !is_q) { |
12066 | unallocated_encoding(s); | |
12067 | return; | |
12068 | } | |
8c6afa6a PM |
12069 | if (!fp_access_check(s)) { |
12070 | return; | |
12071 | } | |
09e03735 AB |
12072 | handle_2misc_satacc(s, false, u, is_q, size, rn, rd); |
12073 | return; | |
94b6c911 | 12074 | case 0x7: /* SQABS, SQNEG */ |
45aecc6d PM |
12075 | if (size == 3 && !is_q) { |
12076 | unallocated_encoding(s); | |
12077 | return; | |
12078 | } | |
0a79bc87 | 12079 | break; |
45aecc6d | 12080 | case 0xc ... 0xf: |
6bea2563 | 12081 | case 0x16 ... 0x1f: |
45aecc6d PM |
12082 | { |
12083 | /* Floating point: U, size[1] and opcode indicate operation; | |
12084 | * size[0] indicates single or double precision. | |
12085 | */ | |
10113b69 | 12086 | int is_double = extract32(size, 0, 1); |
45aecc6d | 12087 | opcode |= (extract32(size, 1, 1) << 5) | (u << 6); |
10113b69 | 12088 | size = is_double ? 3 : 2; |
45aecc6d | 12089 | switch (opcode) { |
f93d0138 PM |
12090 | case 0x2f: /* FABS */ |
12091 | case 0x6f: /* FNEG */ | |
12092 | if (size == 3 && !is_q) { | |
12093 | unallocated_encoding(s); | |
12094 | return; | |
12095 | } | |
12096 | break; | |
10113b69 AB |
12097 | case 0x1d: /* SCVTF */ |
12098 | case 0x5d: /* UCVTF */ | |
12099 | { | |
12100 | bool is_signed = (opcode == 0x1d) ? true : false; | |
12101 | int elements = is_double ? 2 : is_q ? 4 : 2; | |
12102 | if (is_double && !is_q) { | |
12103 | unallocated_encoding(s); | |
12104 | return; | |
12105 | } | |
8c6afa6a PM |
12106 | if (!fp_access_check(s)) { |
12107 | return; | |
12108 | } | |
10113b69 AB |
12109 | handle_simd_intfp_conv(s, rd, rn, elements, is_signed, 0, size); |
12110 | return; | |
12111 | } | |
8908f4d1 AB |
12112 | case 0x2c: /* FCMGT (zero) */ |
12113 | case 0x2d: /* FCMEQ (zero) */ | |
12114 | case 0x2e: /* FCMLT (zero) */ | |
12115 | case 0x6c: /* FCMGE (zero) */ | |
12116 | case 0x6d: /* FCMLE (zero) */ | |
12117 | if (size == 3 && !is_q) { | |
12118 | unallocated_encoding(s); | |
12119 | return; | |
12120 | } | |
12121 | handle_2misc_fcmp_zero(s, opcode, false, u, is_q, size, rn, rd); | |
12122 | return; | |
f612537e AB |
12123 | case 0x7f: /* FSQRT */ |
12124 | if (size == 3 && !is_q) { | |
12125 | unallocated_encoding(s); | |
12126 | return; | |
12127 | } | |
12128 | break; | |
04c7c6c2 PM |
12129 | case 0x1a: /* FCVTNS */ |
12130 | case 0x1b: /* FCVTMS */ | |
12131 | case 0x3a: /* FCVTPS */ | |
12132 | case 0x3b: /* FCVTZS */ | |
12133 | case 0x5a: /* FCVTNU */ | |
12134 | case 0x5b: /* FCVTMU */ | |
12135 | case 0x7a: /* FCVTPU */ | |
12136 | case 0x7b: /* FCVTZU */ | |
12137 | need_fpstatus = true; | |
12138 | need_rmode = true; | |
12139 | rmode = extract32(opcode, 5, 1) | (extract32(opcode, 0, 1) << 1); | |
12140 | if (size == 3 && !is_q) { | |
12141 | unallocated_encoding(s); | |
12142 | return; | |
12143 | } | |
12144 | break; | |
12145 | case 0x5c: /* FCVTAU */ | |
12146 | case 0x1c: /* FCVTAS */ | |
12147 | need_fpstatus = true; | |
12148 | need_rmode = true; | |
12149 | rmode = FPROUNDING_TIEAWAY; | |
12150 | if (size == 3 && !is_q) { | |
12151 | unallocated_encoding(s); | |
12152 | return; | |
12153 | } | |
12154 | break; | |
b6d4443a AB |
12155 | case 0x3c: /* URECPE */ |
12156 | if (size == 3) { | |
12157 | unallocated_encoding(s); | |
12158 | return; | |
12159 | } | |
12160 | /* fall through */ | |
12161 | case 0x3d: /* FRECPE */ | |
c2fb418e AB |
12162 | case 0x7d: /* FRSQRTE */ |
12163 | if (size == 3 && !is_q) { | |
12164 | unallocated_encoding(s); | |
12165 | return; | |
12166 | } | |
8c6afa6a PM |
12167 | if (!fp_access_check(s)) { |
12168 | return; | |
12169 | } | |
b6d4443a AB |
12170 | handle_2misc_reciprocal(s, opcode, false, u, is_q, size, rn, rd); |
12171 | return; | |
5553955e PM |
12172 | case 0x56: /* FCVTXN, FCVTXN2 */ |
12173 | if (size == 2) { | |
12174 | unallocated_encoding(s); | |
12175 | return; | |
12176 | } | |
12177 | /* fall through */ | |
45aecc6d | 12178 | case 0x16: /* FCVTN, FCVTN2 */ |
261a5b4d PM |
12179 | /* handle_2misc_narrow does a 2*size -> size operation, but these |
12180 | * instructions encode the source size rather than dest size. | |
12181 | */ | |
8c6afa6a PM |
12182 | if (!fp_access_check(s)) { |
12183 | return; | |
12184 | } | |
5201c136 | 12185 | handle_2misc_narrow(s, false, opcode, 0, is_q, size - 1, rn, rd); |
261a5b4d | 12186 | return; |
45aecc6d | 12187 | case 0x17: /* FCVTL, FCVTL2 */ |
8c6afa6a PM |
12188 | if (!fp_access_check(s)) { |
12189 | return; | |
12190 | } | |
931c8cc2 PM |
12191 | handle_2misc_widening(s, opcode, is_q, size, rn, rd); |
12192 | return; | |
45aecc6d PM |
12193 | case 0x18: /* FRINTN */ |
12194 | case 0x19: /* FRINTM */ | |
45aecc6d PM |
12195 | case 0x38: /* FRINTP */ |
12196 | case 0x39: /* FRINTZ */ | |
03df01ed PM |
12197 | need_rmode = true; |
12198 | rmode = extract32(opcode, 5, 1) | (extract32(opcode, 0, 1) << 1); | |
12199 | /* fall through */ | |
12200 | case 0x59: /* FRINTX */ | |
12201 | case 0x79: /* FRINTI */ | |
12202 | need_fpstatus = true; | |
12203 | if (size == 3 && !is_q) { | |
12204 | unallocated_encoding(s); | |
12205 | return; | |
12206 | } | |
12207 | break; | |
12208 | case 0x58: /* FRINTA */ | |
12209 | need_rmode = true; | |
12210 | rmode = FPROUNDING_TIEAWAY; | |
12211 | need_fpstatus = true; | |
12212 | if (size == 3 && !is_q) { | |
12213 | unallocated_encoding(s); | |
12214 | return; | |
12215 | } | |
12216 | break; | |
45aecc6d | 12217 | case 0x7c: /* URSQRTE */ |
c2fb418e AB |
12218 | if (size == 3) { |
12219 | unallocated_encoding(s); | |
12220 | return; | |
12221 | } | |
c2fb418e | 12222 | break; |
6bea2563 RH |
12223 | case 0x1e: /* FRINT32Z */ |
12224 | case 0x1f: /* FRINT64Z */ | |
12225 | need_rmode = true; | |
12226 | rmode = FPROUNDING_ZERO; | |
12227 | /* fall through */ | |
12228 | case 0x5e: /* FRINT32X */ | |
12229 | case 0x5f: /* FRINT64X */ | |
12230 | need_fpstatus = true; | |
12231 | if ((size == 3 && !is_q) || !dc_isar_feature(aa64_frint, s)) { | |
12232 | unallocated_encoding(s); | |
12233 | return; | |
12234 | } | |
12235 | break; | |
45aecc6d PM |
12236 | default: |
12237 | unallocated_encoding(s); | |
12238 | return; | |
12239 | } | |
12240 | break; | |
12241 | } | |
12242 | default: | |
12243 | unallocated_encoding(s); | |
12244 | return; | |
12245 | } | |
94b6c911 | 12246 | |
8c6afa6a PM |
12247 | if (!fp_access_check(s)) { |
12248 | return; | |
12249 | } | |
12250 | ||
9b049916 | 12251 | if (need_fpstatus || need_rmode) { |
d81ce0ef | 12252 | tcg_fpstatus = get_fpstatus_ptr(false); |
04c7c6c2 | 12253 | } else { |
f764718d | 12254 | tcg_fpstatus = NULL; |
04c7c6c2 PM |
12255 | } |
12256 | if (need_rmode) { | |
12257 | tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode)); | |
9b049916 | 12258 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); |
04c7c6c2 | 12259 | } else { |
f764718d | 12260 | tcg_rmode = NULL; |
04c7c6c2 PM |
12261 | } |
12262 | ||
377ef731 RH |
12263 | switch (opcode) { |
12264 | case 0x5: | |
12265 | if (u && size == 0) { /* NOT */ | |
12266 | gen_gvec_fn2(s, is_q, rd, rn, tcg_gen_gvec_not, 0); | |
12267 | return; | |
12268 | } | |
12269 | break; | |
6b375d35 | 12270 | case 0x8: /* CMGT, CMGE */ |
69d5e2bf RH |
12271 | if (u) { |
12272 | gen_gvec_fn2(s, is_q, rd, rn, gen_gvec_cge0, size); | |
12273 | } else { | |
12274 | gen_gvec_fn2(s, is_q, rd, rn, gen_gvec_cgt0, size); | |
12275 | } | |
6b375d35 RH |
12276 | return; |
12277 | case 0x9: /* CMEQ, CMLE */ | |
69d5e2bf RH |
12278 | if (u) { |
12279 | gen_gvec_fn2(s, is_q, rd, rn, gen_gvec_cle0, size); | |
12280 | } else { | |
12281 | gen_gvec_fn2(s, is_q, rd, rn, gen_gvec_ceq0, size); | |
12282 | } | |
6b375d35 RH |
12283 | return; |
12284 | case 0xa: /* CMLT */ | |
69d5e2bf | 12285 | gen_gvec_fn2(s, is_q, rd, rn, gen_gvec_clt0, size); |
6b375d35 | 12286 | return; |
377ef731 | 12287 | case 0xb: |
4e027a71 | 12288 | if (u) { /* ABS, NEG */ |
377ef731 | 12289 | gen_gvec_fn2(s, is_q, rd, rn, tcg_gen_gvec_neg, size); |
4e027a71 RH |
12290 | } else { |
12291 | gen_gvec_fn2(s, is_q, rd, rn, tcg_gen_gvec_abs, size); | |
377ef731 | 12292 | } |
4e027a71 | 12293 | return; |
377ef731 RH |
12294 | } |
12295 | ||
94b6c911 PM |
12296 | if (size == 3) { |
12297 | /* All 64-bit element operations can be shared with scalar 2misc */ | |
12298 | int pass; | |
12299 | ||
a8766e31 RH |
12300 | /* Coverity claims (size == 3 && !is_q) has been eliminated |
12301 | * from all paths leading to here. | |
12302 | */ | |
12303 | tcg_debug_assert(is_q); | |
12304 | for (pass = 0; pass < 2; pass++) { | |
94b6c911 PM |
12305 | TCGv_i64 tcg_op = tcg_temp_new_i64(); |
12306 | TCGv_i64 tcg_res = tcg_temp_new_i64(); | |
12307 | ||
12308 | read_vec_element(s, tcg_op, rn, pass, MO_64); | |
12309 | ||
04c7c6c2 PM |
12310 | handle_2misc_64(s, opcode, u, tcg_res, tcg_op, |
12311 | tcg_rmode, tcg_fpstatus); | |
94b6c911 PM |
12312 | |
12313 | write_vec_element(s, tcg_res, rd, pass, MO_64); | |
12314 | ||
12315 | tcg_temp_free_i64(tcg_res); | |
12316 | tcg_temp_free_i64(tcg_op); | |
12317 | } | |
12318 | } else { | |
12319 | int pass; | |
12320 | ||
12321 | for (pass = 0; pass < (is_q ? 4 : 2); pass++) { | |
12322 | TCGv_i32 tcg_op = tcg_temp_new_i32(); | |
12323 | TCGv_i32 tcg_res = tcg_temp_new_i32(); | |
94b6c911 PM |
12324 | |
12325 | read_vec_element_i32(s, tcg_op, rn, pass, MO_32); | |
12326 | ||
12327 | if (size == 2) { | |
12328 | /* Special cases for 32 bit elements */ | |
12329 | switch (opcode) { | |
b05c3068 AB |
12330 | case 0x4: /* CLS */ |
12331 | if (u) { | |
7539a012 | 12332 | tcg_gen_clzi_i32(tcg_res, tcg_op, 32); |
b05c3068 | 12333 | } else { |
bc21dbcc | 12334 | tcg_gen_clrsb_i32(tcg_res, tcg_op); |
b05c3068 AB |
12335 | } |
12336 | break; | |
0a79bc87 AB |
12337 | case 0x7: /* SQABS, SQNEG */ |
12338 | if (u) { | |
12339 | gen_helper_neon_qneg_s32(tcg_res, cpu_env, tcg_op); | |
12340 | } else { | |
12341 | gen_helper_neon_qabs_s32(tcg_res, cpu_env, tcg_op); | |
12342 | } | |
12343 | break; | |
f93d0138 PM |
12344 | case 0x2f: /* FABS */ |
12345 | gen_helper_vfp_abss(tcg_res, tcg_op); | |
12346 | break; | |
12347 | case 0x6f: /* FNEG */ | |
12348 | gen_helper_vfp_negs(tcg_res, tcg_op); | |
12349 | break; | |
f612537e AB |
12350 | case 0x7f: /* FSQRT */ |
12351 | gen_helper_vfp_sqrts(tcg_res, tcg_op, cpu_env); | |
12352 | break; | |
04c7c6c2 PM |
12353 | case 0x1a: /* FCVTNS */ |
12354 | case 0x1b: /* FCVTMS */ | |
12355 | case 0x1c: /* FCVTAS */ | |
12356 | case 0x3a: /* FCVTPS */ | |
12357 | case 0x3b: /* FCVTZS */ | |
12358 | { | |
12359 | TCGv_i32 tcg_shift = tcg_const_i32(0); | |
12360 | gen_helper_vfp_tosls(tcg_res, tcg_op, | |
12361 | tcg_shift, tcg_fpstatus); | |
12362 | tcg_temp_free_i32(tcg_shift); | |
12363 | break; | |
12364 | } | |
12365 | case 0x5a: /* FCVTNU */ | |
12366 | case 0x5b: /* FCVTMU */ | |
12367 | case 0x5c: /* FCVTAU */ | |
12368 | case 0x7a: /* FCVTPU */ | |
12369 | case 0x7b: /* FCVTZU */ | |
12370 | { | |
12371 | TCGv_i32 tcg_shift = tcg_const_i32(0); | |
12372 | gen_helper_vfp_touls(tcg_res, tcg_op, | |
12373 | tcg_shift, tcg_fpstatus); | |
12374 | tcg_temp_free_i32(tcg_shift); | |
12375 | break; | |
12376 | } | |
03df01ed PM |
12377 | case 0x18: /* FRINTN */ |
12378 | case 0x19: /* FRINTM */ | |
12379 | case 0x38: /* FRINTP */ | |
12380 | case 0x39: /* FRINTZ */ | |
12381 | case 0x58: /* FRINTA */ | |
12382 | case 0x79: /* FRINTI */ | |
12383 | gen_helper_rints(tcg_res, tcg_op, tcg_fpstatus); | |
12384 | break; | |
12385 | case 0x59: /* FRINTX */ | |
12386 | gen_helper_rints_exact(tcg_res, tcg_op, tcg_fpstatus); | |
12387 | break; | |
c2fb418e | 12388 | case 0x7c: /* URSQRTE */ |
fe6fb4be | 12389 | gen_helper_rsqrte_u32(tcg_res, tcg_op); |
c2fb418e | 12390 | break; |
6bea2563 RH |
12391 | case 0x1e: /* FRINT32Z */ |
12392 | case 0x5e: /* FRINT32X */ | |
12393 | gen_helper_frint32_s(tcg_res, tcg_op, tcg_fpstatus); | |
12394 | break; | |
12395 | case 0x1f: /* FRINT64Z */ | |
12396 | case 0x5f: /* FRINT64X */ | |
12397 | gen_helper_frint64_s(tcg_res, tcg_op, tcg_fpstatus); | |
12398 | break; | |
94b6c911 PM |
12399 | default: |
12400 | g_assert_not_reached(); | |
12401 | } | |
12402 | } else { | |
12403 | /* Use helpers for 8 and 16 bit elements */ | |
12404 | switch (opcode) { | |
86cbc418 PM |
12405 | case 0x5: /* CNT, RBIT */ |
12406 | /* For these two insns size is part of the opcode specifier | |
12407 | * (handled earlier); they always operate on byte elements. | |
12408 | */ | |
12409 | if (u) { | |
12410 | gen_helper_neon_rbit_u8(tcg_res, tcg_op); | |
12411 | } else { | |
12412 | gen_helper_neon_cnt_u8(tcg_res, tcg_op); | |
12413 | } | |
12414 | break; | |
0a79bc87 AB |
12415 | case 0x7: /* SQABS, SQNEG */ |
12416 | { | |
12417 | NeonGenOneOpEnvFn *genfn; | |
12418 | static NeonGenOneOpEnvFn * const fns[2][2] = { | |
12419 | { gen_helper_neon_qabs_s8, gen_helper_neon_qneg_s8 }, | |
12420 | { gen_helper_neon_qabs_s16, gen_helper_neon_qneg_s16 }, | |
12421 | }; | |
12422 | genfn = fns[size][u]; | |
12423 | genfn(tcg_res, cpu_env, tcg_op); | |
12424 | break; | |
12425 | } | |
b05c3068 AB |
12426 | case 0x4: /* CLS, CLZ */ |
12427 | if (u) { | |
12428 | if (size == 0) { | |
12429 | gen_helper_neon_clz_u8(tcg_res, tcg_op); | |
12430 | } else { | |
12431 | gen_helper_neon_clz_u16(tcg_res, tcg_op); | |
12432 | } | |
12433 | } else { | |
12434 | if (size == 0) { | |
12435 | gen_helper_neon_cls_s8(tcg_res, tcg_op); | |
12436 | } else { | |
12437 | gen_helper_neon_cls_s16(tcg_res, tcg_op); | |
12438 | } | |
12439 | } | |
12440 | break; | |
94b6c911 PM |
12441 | default: |
12442 | g_assert_not_reached(); | |
12443 | } | |
12444 | } | |
12445 | ||
12446 | write_vec_element_i32(s, tcg_res, rd, pass, MO_32); | |
12447 | ||
12448 | tcg_temp_free_i32(tcg_res); | |
12449 | tcg_temp_free_i32(tcg_op); | |
12450 | } | |
12451 | } | |
4ff55bcb | 12452 | clear_vec_high(s, is_q, rd); |
04c7c6c2 PM |
12453 | |
12454 | if (need_rmode) { | |
9b049916 | 12455 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); |
04c7c6c2 PM |
12456 | tcg_temp_free_i32(tcg_rmode); |
12457 | } | |
12458 | if (need_fpstatus) { | |
12459 | tcg_temp_free_ptr(tcg_fpstatus); | |
12460 | } | |
384b26fb AB |
12461 | } |
12462 | ||
5d432be6 AB |
12463 | /* AdvSIMD [scalar] two register miscellaneous (FP16) |
12464 | * | |
12465 | * 31 30 29 28 27 24 23 22 21 17 16 12 11 10 9 5 4 0 | |
12466 | * +---+---+---+---+---------+---+-------------+--------+-----+------+------+ | |
12467 | * | 0 | Q | U | S | 1 1 1 0 | a | 1 1 1 1 0 0 | opcode | 1 0 | Rn | Rd | | |
12468 | * +---+---+---+---+---------+---+-------------+--------+-----+------+------+ | |
12469 | * mask: 1000 1111 0111 1110 0000 1100 0000 0000 0x8f7e 0c00 | |
12470 | * val: 0000 1110 0111 1000 0000 1000 0000 0000 0x0e78 0800 | |
12471 | * | |
12472 | * This actually covers two groups where scalar access is governed by | |
12473 | * bit 28. A bunch of the instructions (float to integral) only exist | |
12474 | * in the vector form and are un-allocated for the scalar decode. Also | |
12475 | * in the scalar decode Q is always 1. | |
12476 | */ | |
12477 | static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn) | |
12478 | { | |
6109aea2 AB |
12479 | int fpop, opcode, a, u; |
12480 | int rn, rd; | |
12481 | bool is_q; | |
12482 | bool is_scalar; | |
12483 | bool only_in_vector = false; | |
12484 | ||
12485 | int pass; | |
12486 | TCGv_i32 tcg_rmode = NULL; | |
12487 | TCGv_ptr tcg_fpstatus = NULL; | |
12488 | bool need_rmode = false; | |
15f8a233 | 12489 | bool need_fpst = true; |
6109aea2 | 12490 | int rmode; |
5d432be6 | 12491 | |
5763190f | 12492 | if (!dc_isar_feature(aa64_fp16, s)) { |
5d432be6 AB |
12493 | unallocated_encoding(s); |
12494 | return; | |
12495 | } | |
12496 | ||
6109aea2 AB |
12497 | rd = extract32(insn, 0, 5); |
12498 | rn = extract32(insn, 5, 5); | |
5d432be6 | 12499 | |
5d432be6 | 12500 | a = extract32(insn, 23, 1); |
6109aea2 AB |
12501 | u = extract32(insn, 29, 1); |
12502 | is_scalar = extract32(insn, 28, 1); | |
12503 | is_q = extract32(insn, 30, 1); | |
12504 | ||
12505 | opcode = extract32(insn, 12, 5); | |
5d432be6 | 12506 | fpop = deposit32(opcode, 5, 1, a); |
6109aea2 | 12507 | fpop = deposit32(fpop, 6, 1, u); |
5d432be6 | 12508 | |
7d4dd1a7 AB |
12509 | rd = extract32(insn, 0, 5); |
12510 | rn = extract32(insn, 5, 5); | |
12511 | ||
5d432be6 | 12512 | switch (fpop) { |
93193190 AB |
12513 | case 0x1d: /* SCVTF */ |
12514 | case 0x5d: /* UCVTF */ | |
12515 | { | |
12516 | int elements; | |
12517 | ||
12518 | if (is_scalar) { | |
12519 | elements = 1; | |
12520 | } else { | |
12521 | elements = (is_q ? 8 : 4); | |
12522 | } | |
12523 | ||
12524 | if (!fp_access_check(s)) { | |
12525 | return; | |
12526 | } | |
12527 | handle_simd_intfp_conv(s, rd, rn, elements, !u, 0, MO_16); | |
12528 | return; | |
12529 | } | |
7d4dd1a7 AB |
12530 | break; |
12531 | case 0x2c: /* FCMGT (zero) */ | |
12532 | case 0x2d: /* FCMEQ (zero) */ | |
12533 | case 0x2e: /* FCMLT (zero) */ | |
12534 | case 0x6c: /* FCMGE (zero) */ | |
12535 | case 0x6d: /* FCMLE (zero) */ | |
12536 | handle_2misc_fcmp_zero(s, fpop, is_scalar, 0, is_q, MO_16, rn, rd); | |
12537 | return; | |
fbd06e1e | 12538 | case 0x3d: /* FRECPE */ |
98695028 | 12539 | case 0x3f: /* FRECPX */ |
fbd06e1e | 12540 | break; |
6109aea2 AB |
12541 | case 0x18: /* FRINTN */ |
12542 | need_rmode = true; | |
12543 | only_in_vector = true; | |
12544 | rmode = FPROUNDING_TIEEVEN; | |
12545 | break; | |
12546 | case 0x19: /* FRINTM */ | |
12547 | need_rmode = true; | |
12548 | only_in_vector = true; | |
12549 | rmode = FPROUNDING_NEGINF; | |
12550 | break; | |
12551 | case 0x38: /* FRINTP */ | |
12552 | need_rmode = true; | |
12553 | only_in_vector = true; | |
12554 | rmode = FPROUNDING_POSINF; | |
12555 | break; | |
12556 | case 0x39: /* FRINTZ */ | |
12557 | need_rmode = true; | |
12558 | only_in_vector = true; | |
12559 | rmode = FPROUNDING_ZERO; | |
12560 | break; | |
12561 | case 0x58: /* FRINTA */ | |
12562 | need_rmode = true; | |
12563 | only_in_vector = true; | |
12564 | rmode = FPROUNDING_TIEAWAY; | |
12565 | break; | |
12566 | case 0x59: /* FRINTX */ | |
12567 | case 0x79: /* FRINTI */ | |
12568 | only_in_vector = true; | |
12569 | /* current rounding mode */ | |
12570 | break; | |
2df58130 AB |
12571 | case 0x1a: /* FCVTNS */ |
12572 | need_rmode = true; | |
12573 | rmode = FPROUNDING_TIEEVEN; | |
12574 | break; | |
12575 | case 0x1b: /* FCVTMS */ | |
12576 | need_rmode = true; | |
12577 | rmode = FPROUNDING_NEGINF; | |
12578 | break; | |
12579 | case 0x1c: /* FCVTAS */ | |
12580 | need_rmode = true; | |
12581 | rmode = FPROUNDING_TIEAWAY; | |
12582 | break; | |
12583 | case 0x3a: /* FCVTPS */ | |
12584 | need_rmode = true; | |
12585 | rmode = FPROUNDING_POSINF; | |
12586 | break; | |
12587 | case 0x3b: /* FCVTZS */ | |
12588 | need_rmode = true; | |
12589 | rmode = FPROUNDING_ZERO; | |
12590 | break; | |
12591 | case 0x5a: /* FCVTNU */ | |
12592 | need_rmode = true; | |
12593 | rmode = FPROUNDING_TIEEVEN; | |
12594 | break; | |
12595 | case 0x5b: /* FCVTMU */ | |
12596 | need_rmode = true; | |
12597 | rmode = FPROUNDING_NEGINF; | |
12598 | break; | |
12599 | case 0x5c: /* FCVTAU */ | |
12600 | need_rmode = true; | |
12601 | rmode = FPROUNDING_TIEAWAY; | |
12602 | break; | |
12603 | case 0x7a: /* FCVTPU */ | |
12604 | need_rmode = true; | |
12605 | rmode = FPROUNDING_POSINF; | |
12606 | break; | |
12607 | case 0x7b: /* FCVTZU */ | |
12608 | need_rmode = true; | |
12609 | rmode = FPROUNDING_ZERO; | |
12610 | break; | |
15f8a233 AB |
12611 | case 0x2f: /* FABS */ |
12612 | case 0x6f: /* FNEG */ | |
12613 | need_fpst = false; | |
12614 | break; | |
c625ff95 | 12615 | case 0x7d: /* FRSQRTE */ |
b96a54c7 AB |
12616 | case 0x7f: /* FSQRT (vector) */ |
12617 | break; | |
5d432be6 AB |
12618 | default: |
12619 | fprintf(stderr, "%s: insn %#04x fpop %#2x\n", __func__, insn, fpop); | |
12620 | g_assert_not_reached(); | |
12621 | } | |
12622 | ||
6109aea2 AB |
12623 | |
12624 | /* Check additional constraints for the scalar encoding */ | |
12625 | if (is_scalar) { | |
12626 | if (!is_q) { | |
12627 | unallocated_encoding(s); | |
12628 | return; | |
12629 | } | |
12630 | /* FRINTxx is only in the vector form */ | |
12631 | if (only_in_vector) { | |
12632 | unallocated_encoding(s); | |
12633 | return; | |
12634 | } | |
12635 | } | |
12636 | ||
12637 | if (!fp_access_check(s)) { | |
12638 | return; | |
12639 | } | |
12640 | ||
15f8a233 | 12641 | if (need_rmode || need_fpst) { |
6109aea2 AB |
12642 | tcg_fpstatus = get_fpstatus_ptr(true); |
12643 | } | |
12644 | ||
12645 | if (need_rmode) { | |
12646 | tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode)); | |
12647 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); | |
12648 | } | |
12649 | ||
12650 | if (is_scalar) { | |
3d99d931 | 12651 | TCGv_i32 tcg_op = read_fp_hreg(s, rn); |
2df58130 AB |
12652 | TCGv_i32 tcg_res = tcg_temp_new_i32(); |
12653 | ||
2df58130 AB |
12654 | switch (fpop) { |
12655 | case 0x1a: /* FCVTNS */ | |
12656 | case 0x1b: /* FCVTMS */ | |
12657 | case 0x1c: /* FCVTAS */ | |
12658 | case 0x3a: /* FCVTPS */ | |
12659 | case 0x3b: /* FCVTZS */ | |
12660 | gen_helper_advsimd_f16tosinth(tcg_res, tcg_op, tcg_fpstatus); | |
12661 | break; | |
fbd06e1e AB |
12662 | case 0x3d: /* FRECPE */ |
12663 | gen_helper_recpe_f16(tcg_res, tcg_op, tcg_fpstatus); | |
12664 | break; | |
98695028 AB |
12665 | case 0x3f: /* FRECPX */ |
12666 | gen_helper_frecpx_f16(tcg_res, tcg_op, tcg_fpstatus); | |
12667 | break; | |
2df58130 AB |
12668 | case 0x5a: /* FCVTNU */ |
12669 | case 0x5b: /* FCVTMU */ | |
12670 | case 0x5c: /* FCVTAU */ | |
12671 | case 0x7a: /* FCVTPU */ | |
12672 | case 0x7b: /* FCVTZU */ | |
12673 | gen_helper_advsimd_f16touinth(tcg_res, tcg_op, tcg_fpstatus); | |
12674 | break; | |
15f8a233 AB |
12675 | case 0x6f: /* FNEG */ |
12676 | tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000); | |
12677 | break; | |
c625ff95 AB |
12678 | case 0x7d: /* FRSQRTE */ |
12679 | gen_helper_rsqrte_f16(tcg_res, tcg_op, tcg_fpstatus); | |
12680 | break; | |
2df58130 AB |
12681 | default: |
12682 | g_assert_not_reached(); | |
12683 | } | |
12684 | ||
12685 | /* limit any sign extension going on */ | |
12686 | tcg_gen_andi_i32(tcg_res, tcg_res, 0xffff); | |
12687 | write_fp_sreg(s, rd, tcg_res); | |
12688 | ||
12689 | tcg_temp_free_i32(tcg_res); | |
12690 | tcg_temp_free_i32(tcg_op); | |
6109aea2 AB |
12691 | } else { |
12692 | for (pass = 0; pass < (is_q ? 8 : 4); pass++) { | |
12693 | TCGv_i32 tcg_op = tcg_temp_new_i32(); | |
12694 | TCGv_i32 tcg_res = tcg_temp_new_i32(); | |
12695 | ||
12696 | read_vec_element_i32(s, tcg_op, rn, pass, MO_16); | |
12697 | ||
12698 | switch (fpop) { | |
2df58130 AB |
12699 | case 0x1a: /* FCVTNS */ |
12700 | case 0x1b: /* FCVTMS */ | |
12701 | case 0x1c: /* FCVTAS */ | |
12702 | case 0x3a: /* FCVTPS */ | |
12703 | case 0x3b: /* FCVTZS */ | |
12704 | gen_helper_advsimd_f16tosinth(tcg_res, tcg_op, tcg_fpstatus); | |
12705 | break; | |
fbd06e1e AB |
12706 | case 0x3d: /* FRECPE */ |
12707 | gen_helper_recpe_f16(tcg_res, tcg_op, tcg_fpstatus); | |
12708 | break; | |
2df58130 AB |
12709 | case 0x5a: /* FCVTNU */ |
12710 | case 0x5b: /* FCVTMU */ | |
12711 | case 0x5c: /* FCVTAU */ | |
12712 | case 0x7a: /* FCVTPU */ | |
12713 | case 0x7b: /* FCVTZU */ | |
12714 | gen_helper_advsimd_f16touinth(tcg_res, tcg_op, tcg_fpstatus); | |
12715 | break; | |
6109aea2 AB |
12716 | case 0x18: /* FRINTN */ |
12717 | case 0x19: /* FRINTM */ | |
12718 | case 0x38: /* FRINTP */ | |
12719 | case 0x39: /* FRINTZ */ | |
12720 | case 0x58: /* FRINTA */ | |
12721 | case 0x79: /* FRINTI */ | |
12722 | gen_helper_advsimd_rinth(tcg_res, tcg_op, tcg_fpstatus); | |
12723 | break; | |
12724 | case 0x59: /* FRINTX */ | |
12725 | gen_helper_advsimd_rinth_exact(tcg_res, tcg_op, tcg_fpstatus); | |
12726 | break; | |
15f8a233 AB |
12727 | case 0x2f: /* FABS */ |
12728 | tcg_gen_andi_i32(tcg_res, tcg_op, 0x7fff); | |
12729 | break; | |
12730 | case 0x6f: /* FNEG */ | |
12731 | tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000); | |
12732 | break; | |
c625ff95 AB |
12733 | case 0x7d: /* FRSQRTE */ |
12734 | gen_helper_rsqrte_f16(tcg_res, tcg_op, tcg_fpstatus); | |
12735 | break; | |
b96a54c7 AB |
12736 | case 0x7f: /* FSQRT */ |
12737 | gen_helper_sqrt_f16(tcg_res, tcg_op, tcg_fpstatus); | |
12738 | break; | |
6109aea2 AB |
12739 | default: |
12740 | g_assert_not_reached(); | |
12741 | } | |
12742 | ||
12743 | write_vec_element_i32(s, tcg_res, rd, pass, MO_16); | |
12744 | ||
12745 | tcg_temp_free_i32(tcg_res); | |
12746 | tcg_temp_free_i32(tcg_op); | |
12747 | } | |
12748 | ||
12749 | clear_vec_high(s, is_q, rd); | |
12750 | } | |
12751 | ||
12752 | if (tcg_rmode) { | |
12753 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); | |
12754 | tcg_temp_free_i32(tcg_rmode); | |
12755 | } | |
12756 | ||
12757 | if (tcg_fpstatus) { | |
12758 | tcg_temp_free_ptr(tcg_fpstatus); | |
12759 | } | |
5d432be6 AB |
12760 | } |
12761 | ||
4ce31af4 | 12762 | /* AdvSIMD scalar x indexed element |
9f82e0ff PM |
12763 | * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0 |
12764 | * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+ | |
12765 | * | 0 1 | U | 1 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd | | |
12766 | * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+ | |
4ce31af4 | 12767 | * AdvSIMD vector x indexed element |
384b26fb AB |
12768 | * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0 |
12769 | * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+ | |
12770 | * | 0 | Q | U | 0 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd | | |
12771 | * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+ | |
12772 | */ | |
9f82e0ff | 12773 | static void disas_simd_indexed(DisasContext *s, uint32_t insn) |
384b26fb | 12774 | { |
f5e51e7f PM |
12775 | /* This encoding has two kinds of instruction: |
12776 | * normal, where we perform elt x idxelt => elt for each | |
12777 | * element in the vector | |
12778 | * long, where we perform elt x idxelt and generate a result of | |
12779 | * double the width of the input element | |
12780 | * The long ops have a 'part' specifier (ie come in INSN, INSN2 pairs). | |
12781 | */ | |
9f82e0ff | 12782 | bool is_scalar = extract32(insn, 28, 1); |
f5e51e7f PM |
12783 | bool is_q = extract32(insn, 30, 1); |
12784 | bool u = extract32(insn, 29, 1); | |
12785 | int size = extract32(insn, 22, 2); | |
12786 | int l = extract32(insn, 21, 1); | |
12787 | int m = extract32(insn, 20, 1); | |
12788 | /* Note that the Rm field here is only 4 bits, not 5 as it usually is */ | |
12789 | int rm = extract32(insn, 16, 4); | |
12790 | int opcode = extract32(insn, 12, 4); | |
12791 | int h = extract32(insn, 11, 1); | |
12792 | int rn = extract32(insn, 5, 5); | |
12793 | int rd = extract32(insn, 0, 5); | |
12794 | bool is_long = false; | |
d17b7cdc | 12795 | int is_fp = 0; |
5d265064 | 12796 | bool is_fp16 = false; |
f5e51e7f PM |
12797 | int index; |
12798 | TCGv_ptr fpst; | |
12799 | ||
5f81b1de RH |
12800 | switch (16 * u + opcode) { |
12801 | case 0x08: /* MUL */ | |
12802 | case 0x10: /* MLA */ | |
12803 | case 0x14: /* MLS */ | |
12804 | if (is_scalar) { | |
f5e51e7f PM |
12805 | unallocated_encoding(s); |
12806 | return; | |
12807 | } | |
12808 | break; | |
5f81b1de RH |
12809 | case 0x02: /* SMLAL, SMLAL2 */ |
12810 | case 0x12: /* UMLAL, UMLAL2 */ | |
12811 | case 0x06: /* SMLSL, SMLSL2 */ | |
12812 | case 0x16: /* UMLSL, UMLSL2 */ | |
12813 | case 0x0a: /* SMULL, SMULL2 */ | |
12814 | case 0x1a: /* UMULL, UMULL2 */ | |
9f82e0ff PM |
12815 | if (is_scalar) { |
12816 | unallocated_encoding(s); | |
12817 | return; | |
12818 | } | |
f5e51e7f PM |
12819 | is_long = true; |
12820 | break; | |
5f81b1de RH |
12821 | case 0x03: /* SQDMLAL, SQDMLAL2 */ |
12822 | case 0x07: /* SQDMLSL, SQDMLSL2 */ | |
12823 | case 0x0b: /* SQDMULL, SQDMULL2 */ | |
f5e51e7f | 12824 | is_long = true; |
f5e51e7f | 12825 | break; |
5f81b1de RH |
12826 | case 0x0c: /* SQDMULH */ |
12827 | case 0x0d: /* SQRDMULH */ | |
9f82e0ff | 12828 | break; |
5f81b1de RH |
12829 | case 0x01: /* FMLA */ |
12830 | case 0x05: /* FMLS */ | |
12831 | case 0x09: /* FMUL */ | |
12832 | case 0x19: /* FMULX */ | |
d17b7cdc | 12833 | is_fp = 1; |
f5e51e7f | 12834 | break; |
d345df7a RH |
12835 | case 0x1d: /* SQRDMLAH */ |
12836 | case 0x1f: /* SQRDMLSH */ | |
962fcbf2 | 12837 | if (!dc_isar_feature(aa64_rdm, s)) { |
d345df7a RH |
12838 | unallocated_encoding(s); |
12839 | return; | |
12840 | } | |
12841 | break; | |
26c470a7 RH |
12842 | case 0x0e: /* SDOT */ |
12843 | case 0x1e: /* UDOT */ | |
4977986c | 12844 | if (is_scalar || size != MO_32 || !dc_isar_feature(aa64_dp, s)) { |
26c470a7 RH |
12845 | unallocated_encoding(s); |
12846 | return; | |
12847 | } | |
12848 | break; | |
d17b7cdc RH |
12849 | case 0x11: /* FCMLA #0 */ |
12850 | case 0x13: /* FCMLA #90 */ | |
12851 | case 0x15: /* FCMLA #180 */ | |
12852 | case 0x17: /* FCMLA #270 */ | |
4dfabb6d | 12853 | if (is_scalar || !dc_isar_feature(aa64_fcma, s)) { |
d17b7cdc RH |
12854 | unallocated_encoding(s); |
12855 | return; | |
12856 | } | |
12857 | is_fp = 2; | |
12858 | break; | |
0caa5af8 RH |
12859 | case 0x00: /* FMLAL */ |
12860 | case 0x04: /* FMLSL */ | |
12861 | case 0x18: /* FMLAL2 */ | |
12862 | case 0x1c: /* FMLSL2 */ | |
12863 | if (is_scalar || size != MO_32 || !dc_isar_feature(aa64_fhm, s)) { | |
12864 | unallocated_encoding(s); | |
12865 | return; | |
12866 | } | |
12867 | size = MO_16; | |
12868 | /* is_fp, but we pass cpu_env not fp_status. */ | |
12869 | break; | |
f5e51e7f PM |
12870 | default: |
12871 | unallocated_encoding(s); | |
12872 | return; | |
12873 | } | |
12874 | ||
d17b7cdc RH |
12875 | switch (is_fp) { |
12876 | case 1: /* normal fp */ | |
14776ab5 | 12877 | /* convert insn encoded size to MemOp size */ |
5d265064 | 12878 | switch (size) { |
449f264b | 12879 | case 0: /* half-precision */ |
5d265064 | 12880 | size = MO_16; |
d17b7cdc | 12881 | is_fp16 = true; |
449f264b RH |
12882 | break; |
12883 | case MO_32: /* single precision */ | |
12884 | case MO_64: /* double precision */ | |
12885 | break; | |
12886 | default: | |
5d265064 AB |
12887 | unallocated_encoding(s); |
12888 | return; | |
f5e51e7f | 12889 | } |
d17b7cdc RH |
12890 | break; |
12891 | ||
12892 | case 2: /* complex fp */ | |
12893 | /* Each indexable element is a complex pair. */ | |
eaefb97a | 12894 | size += 1; |
d17b7cdc RH |
12895 | switch (size) { |
12896 | case MO_32: | |
12897 | if (h && !is_q) { | |
12898 | unallocated_encoding(s); | |
12899 | return; | |
12900 | } | |
12901 | is_fp16 = true; | |
12902 | break; | |
12903 | case MO_64: | |
12904 | break; | |
12905 | default: | |
12906 | unallocated_encoding(s); | |
12907 | return; | |
12908 | } | |
12909 | break; | |
12910 | ||
12911 | default: /* integer */ | |
f5e51e7f | 12912 | switch (size) { |
449f264b RH |
12913 | case MO_8: |
12914 | case MO_64: | |
f5e51e7f PM |
12915 | unallocated_encoding(s); |
12916 | return; | |
12917 | } | |
d17b7cdc RH |
12918 | break; |
12919 | } | |
5763190f | 12920 | if (is_fp16 && !dc_isar_feature(aa64_fp16, s)) { |
d17b7cdc RH |
12921 | unallocated_encoding(s); |
12922 | return; | |
f5e51e7f PM |
12923 | } |
12924 | ||
14776ab5 | 12925 | /* Given MemOp size, adjust register and indexing. */ |
449f264b RH |
12926 | switch (size) { |
12927 | case MO_16: | |
12928 | index = h << 2 | l << 1 | m; | |
12929 | break; | |
12930 | case MO_32: | |
12931 | index = h << 1 | l; | |
12932 | rm |= m << 4; | |
12933 | break; | |
12934 | case MO_64: | |
12935 | if (l || !is_q) { | |
12936 | unallocated_encoding(s); | |
12937 | return; | |
12938 | } | |
12939 | index = h; | |
12940 | rm |= m << 4; | |
12941 | break; | |
12942 | default: | |
12943 | g_assert_not_reached(); | |
12944 | } | |
12945 | ||
8c6afa6a PM |
12946 | if (!fp_access_check(s)) { |
12947 | return; | |
12948 | } | |
12949 | ||
f5e51e7f | 12950 | if (is_fp) { |
5d265064 | 12951 | fpst = get_fpstatus_ptr(is_fp16); |
f5e51e7f | 12952 | } else { |
f764718d | 12953 | fpst = NULL; |
f5e51e7f PM |
12954 | } |
12955 | ||
d17b7cdc | 12956 | switch (16 * u + opcode) { |
26c470a7 RH |
12957 | case 0x0e: /* SDOT */ |
12958 | case 0x1e: /* UDOT */ | |
12959 | gen_gvec_op3_ool(s, is_q, rd, rn, rm, index, | |
12960 | u ? gen_helper_gvec_udot_idx_b | |
12961 | : gen_helper_gvec_sdot_idx_b); | |
12962 | return; | |
d17b7cdc RH |
12963 | case 0x11: /* FCMLA #0 */ |
12964 | case 0x13: /* FCMLA #90 */ | |
12965 | case 0x15: /* FCMLA #180 */ | |
12966 | case 0x17: /* FCMLA #270 */ | |
2cc99919 RH |
12967 | { |
12968 | int rot = extract32(insn, 13, 2); | |
12969 | int data = (index << 2) | rot; | |
12970 | tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd), | |
12971 | vec_full_reg_offset(s, rn), | |
12972 | vec_full_reg_offset(s, rm), fpst, | |
12973 | is_q ? 16 : 8, vec_full_reg_size(s), data, | |
12974 | size == MO_64 | |
12975 | ? gen_helper_gvec_fcmlas_idx | |
12976 | : gen_helper_gvec_fcmlah_idx); | |
12977 | tcg_temp_free_ptr(fpst); | |
12978 | } | |
d17b7cdc | 12979 | return; |
0caa5af8 RH |
12980 | |
12981 | case 0x00: /* FMLAL */ | |
12982 | case 0x04: /* FMLSL */ | |
12983 | case 0x18: /* FMLAL2 */ | |
12984 | case 0x1c: /* FMLSL2 */ | |
12985 | { | |
12986 | int is_s = extract32(opcode, 2, 1); | |
12987 | int is_2 = u; | |
12988 | int data = (index << 2) | (is_2 << 1) | is_s; | |
12989 | tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd), | |
12990 | vec_full_reg_offset(s, rn), | |
12991 | vec_full_reg_offset(s, rm), cpu_env, | |
12992 | is_q ? 16 : 8, vec_full_reg_size(s), | |
12993 | data, gen_helper_gvec_fmlal_idx_a64); | |
12994 | } | |
12995 | return; | |
d17b7cdc RH |
12996 | } |
12997 | ||
f5e51e7f PM |
12998 | if (size == 3) { |
12999 | TCGv_i64 tcg_idx = tcg_temp_new_i64(); | |
13000 | int pass; | |
13001 | ||
13002 | assert(is_fp && is_q && !is_long); | |
13003 | ||
13004 | read_vec_element(s, tcg_idx, rm, index, MO_64); | |
13005 | ||
9f82e0ff | 13006 | for (pass = 0; pass < (is_scalar ? 1 : 2); pass++) { |
f5e51e7f PM |
13007 | TCGv_i64 tcg_op = tcg_temp_new_i64(); |
13008 | TCGv_i64 tcg_res = tcg_temp_new_i64(); | |
13009 | ||
13010 | read_vec_element(s, tcg_op, rn, pass, MO_64); | |
13011 | ||
5f81b1de RH |
13012 | switch (16 * u + opcode) { |
13013 | case 0x05: /* FMLS */ | |
f5e51e7f PM |
13014 | /* As usual for ARM, separate negation for fused multiply-add */ |
13015 | gen_helper_vfp_negd(tcg_op, tcg_op); | |
13016 | /* fall through */ | |
5f81b1de | 13017 | case 0x01: /* FMLA */ |
f5e51e7f PM |
13018 | read_vec_element(s, tcg_res, rd, pass, MO_64); |
13019 | gen_helper_vfp_muladdd(tcg_res, tcg_op, tcg_idx, tcg_res, fpst); | |
13020 | break; | |
5f81b1de RH |
13021 | case 0x09: /* FMUL */ |
13022 | gen_helper_vfp_muld(tcg_res, tcg_op, tcg_idx, fpst); | |
13023 | break; | |
13024 | case 0x19: /* FMULX */ | |
13025 | gen_helper_vfp_mulxd(tcg_res, tcg_op, tcg_idx, fpst); | |
f5e51e7f PM |
13026 | break; |
13027 | default: | |
13028 | g_assert_not_reached(); | |
13029 | } | |
13030 | ||
13031 | write_vec_element(s, tcg_res, rd, pass, MO_64); | |
13032 | tcg_temp_free_i64(tcg_op); | |
13033 | tcg_temp_free_i64(tcg_res); | |
13034 | } | |
13035 | ||
13036 | tcg_temp_free_i64(tcg_idx); | |
4ff55bcb | 13037 | clear_vec_high(s, !is_scalar, rd); |
f5e51e7f | 13038 | } else if (!is_long) { |
9f82e0ff PM |
13039 | /* 32 bit floating point, or 16 or 32 bit integer. |
13040 | * For the 16 bit scalar case we use the usual Neon helpers and | |
13041 | * rely on the fact that 0 op 0 == 0 with no side effects. | |
13042 | */ | |
f5e51e7f | 13043 | TCGv_i32 tcg_idx = tcg_temp_new_i32(); |
9f82e0ff PM |
13044 | int pass, maxpasses; |
13045 | ||
13046 | if (is_scalar) { | |
13047 | maxpasses = 1; | |
13048 | } else { | |
13049 | maxpasses = is_q ? 4 : 2; | |
13050 | } | |
f5e51e7f PM |
13051 | |
13052 | read_vec_element_i32(s, tcg_idx, rm, index, size); | |
13053 | ||
9f82e0ff | 13054 | if (size == 1 && !is_scalar) { |
f5e51e7f PM |
13055 | /* The simplest way to handle the 16x16 indexed ops is to duplicate |
13056 | * the index into both halves of the 32 bit tcg_idx and then use | |
13057 | * the usual Neon helpers. | |
13058 | */ | |
13059 | tcg_gen_deposit_i32(tcg_idx, tcg_idx, tcg_idx, 16, 16); | |
13060 | } | |
13061 | ||
9f82e0ff | 13062 | for (pass = 0; pass < maxpasses; pass++) { |
f5e51e7f PM |
13063 | TCGv_i32 tcg_op = tcg_temp_new_i32(); |
13064 | TCGv_i32 tcg_res = tcg_temp_new_i32(); | |
13065 | ||
9f82e0ff | 13066 | read_vec_element_i32(s, tcg_op, rn, pass, is_scalar ? size : MO_32); |
f5e51e7f | 13067 | |
5f81b1de RH |
13068 | switch (16 * u + opcode) { |
13069 | case 0x08: /* MUL */ | |
13070 | case 0x10: /* MLA */ | |
13071 | case 0x14: /* MLS */ | |
f5e51e7f PM |
13072 | { |
13073 | static NeonGenTwoOpFn * const fns[2][2] = { | |
13074 | { gen_helper_neon_add_u16, gen_helper_neon_sub_u16 }, | |
13075 | { tcg_gen_add_i32, tcg_gen_sub_i32 }, | |
13076 | }; | |
13077 | NeonGenTwoOpFn *genfn; | |
13078 | bool is_sub = opcode == 0x4; | |
13079 | ||
13080 | if (size == 1) { | |
13081 | gen_helper_neon_mul_u16(tcg_res, tcg_op, tcg_idx); | |
13082 | } else { | |
13083 | tcg_gen_mul_i32(tcg_res, tcg_op, tcg_idx); | |
13084 | } | |
13085 | if (opcode == 0x8) { | |
13086 | break; | |
13087 | } | |
13088 | read_vec_element_i32(s, tcg_op, rd, pass, MO_32); | |
13089 | genfn = fns[size - 1][is_sub]; | |
13090 | genfn(tcg_res, tcg_op, tcg_res); | |
13091 | break; | |
13092 | } | |
5f81b1de RH |
13093 | case 0x05: /* FMLS */ |
13094 | case 0x01: /* FMLA */ | |
5d265064 AB |
13095 | read_vec_element_i32(s, tcg_res, rd, pass, |
13096 | is_scalar ? size : MO_32); | |
13097 | switch (size) { | |
13098 | case 1: | |
13099 | if (opcode == 0x5) { | |
13100 | /* As usual for ARM, separate negation for fused | |
13101 | * multiply-add */ | |
13102 | tcg_gen_xori_i32(tcg_op, tcg_op, 0x80008000); | |
13103 | } | |
6089030c AB |
13104 | if (is_scalar) { |
13105 | gen_helper_advsimd_muladdh(tcg_res, tcg_op, tcg_idx, | |
13106 | tcg_res, fpst); | |
13107 | } else { | |
13108 | gen_helper_advsimd_muladd2h(tcg_res, tcg_op, tcg_idx, | |
13109 | tcg_res, fpst); | |
13110 | } | |
5d265064 AB |
13111 | break; |
13112 | case 2: | |
13113 | if (opcode == 0x5) { | |
13114 | /* As usual for ARM, separate negation for | |
13115 | * fused multiply-add */ | |
13116 | tcg_gen_xori_i32(tcg_op, tcg_op, 0x80000000); | |
13117 | } | |
13118 | gen_helper_vfp_muladds(tcg_res, tcg_op, tcg_idx, | |
13119 | tcg_res, fpst); | |
13120 | break; | |
13121 | default: | |
13122 | g_assert_not_reached(); | |
13123 | } | |
f5e51e7f | 13124 | break; |
5f81b1de | 13125 | case 0x09: /* FMUL */ |
5d265064 AB |
13126 | switch (size) { |
13127 | case 1: | |
5f81b1de RH |
13128 | if (is_scalar) { |
13129 | gen_helper_advsimd_mulh(tcg_res, tcg_op, | |
13130 | tcg_idx, fpst); | |
5d265064 | 13131 | } else { |
5f81b1de RH |
13132 | gen_helper_advsimd_mul2h(tcg_res, tcg_op, |
13133 | tcg_idx, fpst); | |
5d265064 AB |
13134 | } |
13135 | break; | |
13136 | case 2: | |
5f81b1de RH |
13137 | gen_helper_vfp_muls(tcg_res, tcg_op, tcg_idx, fpst); |
13138 | break; | |
13139 | default: | |
13140 | g_assert_not_reached(); | |
13141 | } | |
13142 | break; | |
13143 | case 0x19: /* FMULX */ | |
13144 | switch (size) { | |
13145 | case 1: | |
13146 | if (is_scalar) { | |
13147 | gen_helper_advsimd_mulxh(tcg_res, tcg_op, | |
13148 | tcg_idx, fpst); | |
5d265064 | 13149 | } else { |
5f81b1de RH |
13150 | gen_helper_advsimd_mulx2h(tcg_res, tcg_op, |
13151 | tcg_idx, fpst); | |
5d265064 AB |
13152 | } |
13153 | break; | |
5f81b1de RH |
13154 | case 2: |
13155 | gen_helper_vfp_mulxs(tcg_res, tcg_op, tcg_idx, fpst); | |
13156 | break; | |
5d265064 AB |
13157 | default: |
13158 | g_assert_not_reached(); | |
f5e51e7f PM |
13159 | } |
13160 | break; | |
5f81b1de | 13161 | case 0x0c: /* SQDMULH */ |
f5e51e7f PM |
13162 | if (size == 1) { |
13163 | gen_helper_neon_qdmulh_s16(tcg_res, cpu_env, | |
13164 | tcg_op, tcg_idx); | |
13165 | } else { | |
13166 | gen_helper_neon_qdmulh_s32(tcg_res, cpu_env, | |
13167 | tcg_op, tcg_idx); | |
13168 | } | |
13169 | break; | |
5f81b1de | 13170 | case 0x0d: /* SQRDMULH */ |
f5e51e7f PM |
13171 | if (size == 1) { |
13172 | gen_helper_neon_qrdmulh_s16(tcg_res, cpu_env, | |
13173 | tcg_op, tcg_idx); | |
13174 | } else { | |
13175 | gen_helper_neon_qrdmulh_s32(tcg_res, cpu_env, | |
13176 | tcg_op, tcg_idx); | |
13177 | } | |
13178 | break; | |
d345df7a RH |
13179 | case 0x1d: /* SQRDMLAH */ |
13180 | read_vec_element_i32(s, tcg_res, rd, pass, | |
13181 | is_scalar ? size : MO_32); | |
13182 | if (size == 1) { | |
13183 | gen_helper_neon_qrdmlah_s16(tcg_res, cpu_env, | |
13184 | tcg_op, tcg_idx, tcg_res); | |
13185 | } else { | |
13186 | gen_helper_neon_qrdmlah_s32(tcg_res, cpu_env, | |
13187 | tcg_op, tcg_idx, tcg_res); | |
13188 | } | |
13189 | break; | |
13190 | case 0x1f: /* SQRDMLSH */ | |
13191 | read_vec_element_i32(s, tcg_res, rd, pass, | |
13192 | is_scalar ? size : MO_32); | |
13193 | if (size == 1) { | |
13194 | gen_helper_neon_qrdmlsh_s16(tcg_res, cpu_env, | |
13195 | tcg_op, tcg_idx, tcg_res); | |
13196 | } else { | |
13197 | gen_helper_neon_qrdmlsh_s32(tcg_res, cpu_env, | |
13198 | tcg_op, tcg_idx, tcg_res); | |
13199 | } | |
13200 | break; | |
f5e51e7f PM |
13201 | default: |
13202 | g_assert_not_reached(); | |
13203 | } | |
13204 | ||
9f82e0ff PM |
13205 | if (is_scalar) { |
13206 | write_fp_sreg(s, rd, tcg_res); | |
13207 | } else { | |
13208 | write_vec_element_i32(s, tcg_res, rd, pass, MO_32); | |
13209 | } | |
13210 | ||
f5e51e7f PM |
13211 | tcg_temp_free_i32(tcg_op); |
13212 | tcg_temp_free_i32(tcg_res); | |
13213 | } | |
13214 | ||
13215 | tcg_temp_free_i32(tcg_idx); | |
4ff55bcb | 13216 | clear_vec_high(s, is_q, rd); |
f5e51e7f PM |
13217 | } else { |
13218 | /* long ops: 16x16->32 or 32x32->64 */ | |
c44ad1fd PM |
13219 | TCGv_i64 tcg_res[2]; |
13220 | int pass; | |
13221 | bool satop = extract32(opcode, 0, 1); | |
14776ab5 | 13222 | MemOp memop = MO_32; |
c44ad1fd PM |
13223 | |
13224 | if (satop || !u) { | |
13225 | memop |= MO_SIGN; | |
13226 | } | |
13227 | ||
13228 | if (size == 2) { | |
13229 | TCGv_i64 tcg_idx = tcg_temp_new_i64(); | |
13230 | ||
13231 | read_vec_element(s, tcg_idx, rm, index, memop); | |
13232 | ||
9f82e0ff | 13233 | for (pass = 0; pass < (is_scalar ? 1 : 2); pass++) { |
c44ad1fd PM |
13234 | TCGv_i64 tcg_op = tcg_temp_new_i64(); |
13235 | TCGv_i64 tcg_passres; | |
9f82e0ff | 13236 | int passelt; |
c44ad1fd | 13237 | |
9f82e0ff PM |
13238 | if (is_scalar) { |
13239 | passelt = 0; | |
13240 | } else { | |
13241 | passelt = pass + (is_q * 2); | |
13242 | } | |
13243 | ||
13244 | read_vec_element(s, tcg_op, rn, passelt, memop); | |
c44ad1fd PM |
13245 | |
13246 | tcg_res[pass] = tcg_temp_new_i64(); | |
13247 | ||
13248 | if (opcode == 0xa || opcode == 0xb) { | |
13249 | /* Non-accumulating ops */ | |
13250 | tcg_passres = tcg_res[pass]; | |
13251 | } else { | |
13252 | tcg_passres = tcg_temp_new_i64(); | |
13253 | } | |
13254 | ||
13255 | tcg_gen_mul_i64(tcg_passres, tcg_op, tcg_idx); | |
13256 | tcg_temp_free_i64(tcg_op); | |
13257 | ||
13258 | if (satop) { | |
13259 | /* saturating, doubling */ | |
13260 | gen_helper_neon_addl_saturate_s64(tcg_passres, cpu_env, | |
13261 | tcg_passres, tcg_passres); | |
13262 | } | |
13263 | ||
13264 | if (opcode == 0xa || opcode == 0xb) { | |
13265 | continue; | |
13266 | } | |
13267 | ||
13268 | /* Accumulating op: handle accumulate step */ | |
13269 | read_vec_element(s, tcg_res[pass], rd, pass, MO_64); | |
13270 | ||
13271 | switch (opcode) { | |
13272 | case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */ | |
13273 | tcg_gen_add_i64(tcg_res[pass], tcg_res[pass], tcg_passres); | |
13274 | break; | |
13275 | case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */ | |
13276 | tcg_gen_sub_i64(tcg_res[pass], tcg_res[pass], tcg_passres); | |
13277 | break; | |
13278 | case 0x7: /* SQDMLSL, SQDMLSL2 */ | |
13279 | tcg_gen_neg_i64(tcg_passres, tcg_passres); | |
13280 | /* fall through */ | |
13281 | case 0x3: /* SQDMLAL, SQDMLAL2 */ | |
13282 | gen_helper_neon_addl_saturate_s64(tcg_res[pass], cpu_env, | |
13283 | tcg_res[pass], | |
13284 | tcg_passres); | |
13285 | break; | |
13286 | default: | |
13287 | g_assert_not_reached(); | |
13288 | } | |
13289 | tcg_temp_free_i64(tcg_passres); | |
13290 | } | |
13291 | tcg_temp_free_i64(tcg_idx); | |
9f82e0ff | 13292 | |
4ff55bcb | 13293 | clear_vec_high(s, !is_scalar, rd); |
c44ad1fd PM |
13294 | } else { |
13295 | TCGv_i32 tcg_idx = tcg_temp_new_i32(); | |
13296 | ||
13297 | assert(size == 1); | |
13298 | read_vec_element_i32(s, tcg_idx, rm, index, size); | |
13299 | ||
9f82e0ff PM |
13300 | if (!is_scalar) { |
13301 | /* The simplest way to handle the 16x16 indexed ops is to | |
13302 | * duplicate the index into both halves of the 32 bit tcg_idx | |
13303 | * and then use the usual Neon helpers. | |
13304 | */ | |
13305 | tcg_gen_deposit_i32(tcg_idx, tcg_idx, tcg_idx, 16, 16); | |
13306 | } | |
c44ad1fd | 13307 | |
9f82e0ff | 13308 | for (pass = 0; pass < (is_scalar ? 1 : 2); pass++) { |
c44ad1fd PM |
13309 | TCGv_i32 tcg_op = tcg_temp_new_i32(); |
13310 | TCGv_i64 tcg_passres; | |
13311 | ||
9f82e0ff PM |
13312 | if (is_scalar) { |
13313 | read_vec_element_i32(s, tcg_op, rn, pass, size); | |
13314 | } else { | |
13315 | read_vec_element_i32(s, tcg_op, rn, | |
13316 | pass + (is_q * 2), MO_32); | |
13317 | } | |
13318 | ||
c44ad1fd PM |
13319 | tcg_res[pass] = tcg_temp_new_i64(); |
13320 | ||
13321 | if (opcode == 0xa || opcode == 0xb) { | |
13322 | /* Non-accumulating ops */ | |
13323 | tcg_passres = tcg_res[pass]; | |
13324 | } else { | |
13325 | tcg_passres = tcg_temp_new_i64(); | |
13326 | } | |
13327 | ||
13328 | if (memop & MO_SIGN) { | |
13329 | gen_helper_neon_mull_s16(tcg_passres, tcg_op, tcg_idx); | |
13330 | } else { | |
13331 | gen_helper_neon_mull_u16(tcg_passres, tcg_op, tcg_idx); | |
13332 | } | |
13333 | if (satop) { | |
13334 | gen_helper_neon_addl_saturate_s32(tcg_passres, cpu_env, | |
13335 | tcg_passres, tcg_passres); | |
13336 | } | |
13337 | tcg_temp_free_i32(tcg_op); | |
13338 | ||
13339 | if (opcode == 0xa || opcode == 0xb) { | |
13340 | continue; | |
13341 | } | |
13342 | ||
13343 | /* Accumulating op: handle accumulate step */ | |
13344 | read_vec_element(s, tcg_res[pass], rd, pass, MO_64); | |
13345 | ||
13346 | switch (opcode) { | |
13347 | case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */ | |
13348 | gen_helper_neon_addl_u32(tcg_res[pass], tcg_res[pass], | |
13349 | tcg_passres); | |
13350 | break; | |
13351 | case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */ | |
13352 | gen_helper_neon_subl_u32(tcg_res[pass], tcg_res[pass], | |
13353 | tcg_passres); | |
13354 | break; | |
13355 | case 0x7: /* SQDMLSL, SQDMLSL2 */ | |
13356 | gen_helper_neon_negl_u32(tcg_passres, tcg_passres); | |
13357 | /* fall through */ | |
13358 | case 0x3: /* SQDMLAL, SQDMLAL2 */ | |
13359 | gen_helper_neon_addl_saturate_s32(tcg_res[pass], cpu_env, | |
13360 | tcg_res[pass], | |
13361 | tcg_passres); | |
13362 | break; | |
13363 | default: | |
13364 | g_assert_not_reached(); | |
13365 | } | |
13366 | tcg_temp_free_i64(tcg_passres); | |
13367 | } | |
13368 | tcg_temp_free_i32(tcg_idx); | |
9f82e0ff PM |
13369 | |
13370 | if (is_scalar) { | |
13371 | tcg_gen_ext32u_i64(tcg_res[0], tcg_res[0]); | |
13372 | } | |
13373 | } | |
13374 | ||
13375 | if (is_scalar) { | |
13376 | tcg_res[1] = tcg_const_i64(0); | |
c44ad1fd PM |
13377 | } |
13378 | ||
13379 | for (pass = 0; pass < 2; pass++) { | |
13380 | write_vec_element(s, tcg_res[pass], rd, pass, MO_64); | |
13381 | tcg_temp_free_i64(tcg_res[pass]); | |
13382 | } | |
f5e51e7f PM |
13383 | } |
13384 | ||
f764718d | 13385 | if (fpst) { |
f5e51e7f PM |
13386 | tcg_temp_free_ptr(fpst); |
13387 | } | |
384b26fb AB |
13388 | } |
13389 | ||
4ce31af4 | 13390 | /* Crypto AES |
384b26fb AB |
13391 | * 31 24 23 22 21 17 16 12 11 10 9 5 4 0 |
13392 | * +-----------------+------+-----------+--------+-----+------+------+ | |
13393 | * | 0 1 0 0 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd | | |
13394 | * +-----------------+------+-----------+--------+-----+------+------+ | |
13395 | */ | |
13396 | static void disas_crypto_aes(DisasContext *s, uint32_t insn) | |
13397 | { | |
5acc765c PM |
13398 | int size = extract32(insn, 22, 2); |
13399 | int opcode = extract32(insn, 12, 5); | |
13400 | int rn = extract32(insn, 5, 5); | |
13401 | int rd = extract32(insn, 0, 5); | |
13402 | int decrypt; | |
a04b68e1 RH |
13403 | gen_helper_gvec_2 *genfn2 = NULL; |
13404 | gen_helper_gvec_3 *genfn3 = NULL; | |
5acc765c | 13405 | |
962fcbf2 | 13406 | if (!dc_isar_feature(aa64_aes, s) || size != 0) { |
5acc765c PM |
13407 | unallocated_encoding(s); |
13408 | return; | |
13409 | } | |
13410 | ||
13411 | switch (opcode) { | |
13412 | case 0x4: /* AESE */ | |
13413 | decrypt = 0; | |
a04b68e1 | 13414 | genfn3 = gen_helper_crypto_aese; |
5acc765c PM |
13415 | break; |
13416 | case 0x6: /* AESMC */ | |
13417 | decrypt = 0; | |
a04b68e1 | 13418 | genfn2 = gen_helper_crypto_aesmc; |
5acc765c PM |
13419 | break; |
13420 | case 0x5: /* AESD */ | |
13421 | decrypt = 1; | |
a04b68e1 | 13422 | genfn3 = gen_helper_crypto_aese; |
5acc765c PM |
13423 | break; |
13424 | case 0x7: /* AESIMC */ | |
13425 | decrypt = 1; | |
a04b68e1 | 13426 | genfn2 = gen_helper_crypto_aesmc; |
5acc765c PM |
13427 | break; |
13428 | default: | |
13429 | unallocated_encoding(s); | |
13430 | return; | |
13431 | } | |
13432 | ||
a4f5c5b7 NR |
13433 | if (!fp_access_check(s)) { |
13434 | return; | |
13435 | } | |
a04b68e1 RH |
13436 | if (genfn2) { |
13437 | gen_gvec_op2_ool(s, true, rd, rn, decrypt, genfn2); | |
13438 | } else { | |
13439 | gen_gvec_op3_ool(s, true, rd, rd, rn, decrypt, genfn3); | |
13440 | } | |
384b26fb AB |
13441 | } |
13442 | ||
4ce31af4 | 13443 | /* Crypto three-reg SHA |
384b26fb AB |
13444 | * 31 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0 |
13445 | * +-----------------+------+---+------+---+--------+-----+------+------+ | |
13446 | * | 0 1 0 1 1 1 1 0 | size | 0 | Rm | 0 | opcode | 0 0 | Rn | Rd | | |
13447 | * +-----------------+------+---+------+---+--------+-----+------+------+ | |
13448 | */ | |
13449 | static void disas_crypto_three_reg_sha(DisasContext *s, uint32_t insn) | |
13450 | { | |
be56f04e PM |
13451 | int size = extract32(insn, 22, 2); |
13452 | int opcode = extract32(insn, 12, 3); | |
13453 | int rm = extract32(insn, 16, 5); | |
13454 | int rn = extract32(insn, 5, 5); | |
13455 | int rd = extract32(insn, 0, 5); | |
effa992f | 13456 | gen_helper_gvec_3 *genfn; |
962fcbf2 | 13457 | bool feature; |
be56f04e PM |
13458 | |
13459 | if (size != 0) { | |
13460 | unallocated_encoding(s); | |
13461 | return; | |
13462 | } | |
13463 | ||
13464 | switch (opcode) { | |
13465 | case 0: /* SHA1C */ | |
afc8b7d3 RH |
13466 | genfn = gen_helper_crypto_sha1c; |
13467 | feature = dc_isar_feature(aa64_sha1, s); | |
13468 | break; | |
be56f04e | 13469 | case 1: /* SHA1P */ |
afc8b7d3 RH |
13470 | genfn = gen_helper_crypto_sha1p; |
13471 | feature = dc_isar_feature(aa64_sha1, s); | |
13472 | break; | |
be56f04e | 13473 | case 2: /* SHA1M */ |
afc8b7d3 RH |
13474 | genfn = gen_helper_crypto_sha1m; |
13475 | feature = dc_isar_feature(aa64_sha1, s); | |
13476 | break; | |
be56f04e | 13477 | case 3: /* SHA1SU0 */ |
afc8b7d3 | 13478 | genfn = gen_helper_crypto_sha1su0; |
962fcbf2 | 13479 | feature = dc_isar_feature(aa64_sha1, s); |
be56f04e PM |
13480 | break; |
13481 | case 4: /* SHA256H */ | |
13482 | genfn = gen_helper_crypto_sha256h; | |
962fcbf2 | 13483 | feature = dc_isar_feature(aa64_sha256, s); |
be56f04e PM |
13484 | break; |
13485 | case 5: /* SHA256H2 */ | |
13486 | genfn = gen_helper_crypto_sha256h2; | |
962fcbf2 | 13487 | feature = dc_isar_feature(aa64_sha256, s); |
be56f04e PM |
13488 | break; |
13489 | case 6: /* SHA256SU1 */ | |
13490 | genfn = gen_helper_crypto_sha256su1; | |
962fcbf2 | 13491 | feature = dc_isar_feature(aa64_sha256, s); |
be56f04e PM |
13492 | break; |
13493 | default: | |
13494 | unallocated_encoding(s); | |
13495 | return; | |
13496 | } | |
13497 | ||
962fcbf2 | 13498 | if (!feature) { |
be56f04e PM |
13499 | unallocated_encoding(s); |
13500 | return; | |
13501 | } | |
13502 | ||
a4f5c5b7 NR |
13503 | if (!fp_access_check(s)) { |
13504 | return; | |
13505 | } | |
afc8b7d3 | 13506 | gen_gvec_op3_ool(s, true, rd, rn, rm, 0, genfn); |
384b26fb AB |
13507 | } |
13508 | ||
4ce31af4 | 13509 | /* Crypto two-reg SHA |
384b26fb AB |
13510 | * 31 24 23 22 21 17 16 12 11 10 9 5 4 0 |
13511 | * +-----------------+------+-----------+--------+-----+------+------+ | |
13512 | * | 0 1 0 1 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd | | |
13513 | * +-----------------+------+-----------+--------+-----+------+------+ | |
13514 | */ | |
13515 | static void disas_crypto_two_reg_sha(DisasContext *s, uint32_t insn) | |
13516 | { | |
f6fe04d5 PM |
13517 | int size = extract32(insn, 22, 2); |
13518 | int opcode = extract32(insn, 12, 5); | |
13519 | int rn = extract32(insn, 5, 5); | |
13520 | int rd = extract32(insn, 0, 5); | |
effa992f | 13521 | gen_helper_gvec_2 *genfn; |
962fcbf2 | 13522 | bool feature; |
f6fe04d5 PM |
13523 | |
13524 | if (size != 0) { | |
13525 | unallocated_encoding(s); | |
13526 | return; | |
13527 | } | |
13528 | ||
13529 | switch (opcode) { | |
13530 | case 0: /* SHA1H */ | |
962fcbf2 | 13531 | feature = dc_isar_feature(aa64_sha1, s); |
f6fe04d5 PM |
13532 | genfn = gen_helper_crypto_sha1h; |
13533 | break; | |
13534 | case 1: /* SHA1SU1 */ | |
962fcbf2 | 13535 | feature = dc_isar_feature(aa64_sha1, s); |
f6fe04d5 PM |
13536 | genfn = gen_helper_crypto_sha1su1; |
13537 | break; | |
13538 | case 2: /* SHA256SU0 */ | |
962fcbf2 | 13539 | feature = dc_isar_feature(aa64_sha256, s); |
f6fe04d5 PM |
13540 | genfn = gen_helper_crypto_sha256su0; |
13541 | break; | |
13542 | default: | |
13543 | unallocated_encoding(s); | |
13544 | return; | |
13545 | } | |
13546 | ||
962fcbf2 | 13547 | if (!feature) { |
f6fe04d5 PM |
13548 | unallocated_encoding(s); |
13549 | return; | |
13550 | } | |
13551 | ||
a4f5c5b7 NR |
13552 | if (!fp_access_check(s)) { |
13553 | return; | |
13554 | } | |
effa992f | 13555 | gen_gvec_op2_ool(s, true, rd, rn, 0, genfn); |
384b26fb AB |
13556 | } |
13557 | ||
1738860d RH |
13558 | static void gen_rax1_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m) |
13559 | { | |
13560 | tcg_gen_rotli_i64(d, m, 1); | |
13561 | tcg_gen_xor_i64(d, d, n); | |
13562 | } | |
13563 | ||
13564 | static void gen_rax1_vec(unsigned vece, TCGv_vec d, TCGv_vec n, TCGv_vec m) | |
13565 | { | |
13566 | tcg_gen_rotli_vec(vece, d, m, 1); | |
13567 | tcg_gen_xor_vec(vece, d, d, n); | |
13568 | } | |
13569 | ||
13570 | void gen_gvec_rax1(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, | |
13571 | uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz) | |
13572 | { | |
13573 | static const TCGOpcode vecop_list[] = { INDEX_op_rotli_vec, 0 }; | |
13574 | static const GVecGen3 op = { | |
13575 | .fni8 = gen_rax1_i64, | |
13576 | .fniv = gen_rax1_vec, | |
13577 | .opt_opc = vecop_list, | |
13578 | .fno = gen_helper_crypto_rax1, | |
13579 | .vece = MO_64, | |
13580 | }; | |
13581 | tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, opr_sz, max_sz, &op); | |
13582 | } | |
13583 | ||
90b827d1 AB |
13584 | /* Crypto three-reg SHA512 |
13585 | * 31 21 20 16 15 14 13 12 11 10 9 5 4 0 | |
13586 | * +-----------------------+------+---+---+-----+--------+------+------+ | |
13587 | * | 1 1 0 0 1 1 1 0 0 1 1 | Rm | 1 | O | 0 0 | opcode | Rn | Rd | | |
13588 | * +-----------------------+------+---+---+-----+--------+------+------+ | |
13589 | */ | |
13590 | static void disas_crypto_three_reg_sha512(DisasContext *s, uint32_t insn) | |
13591 | { | |
13592 | int opcode = extract32(insn, 10, 2); | |
13593 | int o = extract32(insn, 14, 1); | |
13594 | int rm = extract32(insn, 16, 5); | |
13595 | int rn = extract32(insn, 5, 5); | |
13596 | int rd = extract32(insn, 0, 5); | |
962fcbf2 | 13597 | bool feature; |
a04b68e1 | 13598 | gen_helper_gvec_3 *oolfn = NULL; |
1738860d | 13599 | GVecGen3Fn *gvecfn = NULL; |
90b827d1 AB |
13600 | |
13601 | if (o == 0) { | |
13602 | switch (opcode) { | |
13603 | case 0: /* SHA512H */ | |
962fcbf2 | 13604 | feature = dc_isar_feature(aa64_sha512, s); |
aaffebd6 | 13605 | oolfn = gen_helper_crypto_sha512h; |
90b827d1 AB |
13606 | break; |
13607 | case 1: /* SHA512H2 */ | |
962fcbf2 | 13608 | feature = dc_isar_feature(aa64_sha512, s); |
aaffebd6 | 13609 | oolfn = gen_helper_crypto_sha512h2; |
90b827d1 AB |
13610 | break; |
13611 | case 2: /* SHA512SU1 */ | |
962fcbf2 | 13612 | feature = dc_isar_feature(aa64_sha512, s); |
aaffebd6 | 13613 | oolfn = gen_helper_crypto_sha512su1; |
90b827d1 | 13614 | break; |
cd270ade | 13615 | case 3: /* RAX1 */ |
962fcbf2 | 13616 | feature = dc_isar_feature(aa64_sha3, s); |
1738860d | 13617 | gvecfn = gen_gvec_rax1; |
cd270ade | 13618 | break; |
c7a5e791 PN |
13619 | default: |
13620 | g_assert_not_reached(); | |
90b827d1 AB |
13621 | } |
13622 | } else { | |
80d6f4c6 AB |
13623 | switch (opcode) { |
13624 | case 0: /* SM3PARTW1 */ | |
962fcbf2 | 13625 | feature = dc_isar_feature(aa64_sm3, s); |
aaffebd6 | 13626 | oolfn = gen_helper_crypto_sm3partw1; |
80d6f4c6 AB |
13627 | break; |
13628 | case 1: /* SM3PARTW2 */ | |
962fcbf2 | 13629 | feature = dc_isar_feature(aa64_sm3, s); |
aaffebd6 | 13630 | oolfn = gen_helper_crypto_sm3partw2; |
80d6f4c6 | 13631 | break; |
b6577bcd | 13632 | case 2: /* SM4EKEY */ |
962fcbf2 | 13633 | feature = dc_isar_feature(aa64_sm4, s); |
a04b68e1 | 13634 | oolfn = gen_helper_crypto_sm4ekey; |
b6577bcd | 13635 | break; |
80d6f4c6 AB |
13636 | default: |
13637 | unallocated_encoding(s); | |
13638 | return; | |
13639 | } | |
90b827d1 AB |
13640 | } |
13641 | ||
962fcbf2 | 13642 | if (!feature) { |
90b827d1 AB |
13643 | unallocated_encoding(s); |
13644 | return; | |
13645 | } | |
13646 | ||
13647 | if (!fp_access_check(s)) { | |
13648 | return; | |
13649 | } | |
13650 | ||
a04b68e1 RH |
13651 | if (oolfn) { |
13652 | gen_gvec_op3_ool(s, true, rd, rn, rm, 0, oolfn); | |
1738860d | 13653 | } else { |
aaffebd6 | 13654 | gen_gvec_fn3(s, true, rd, rn, rm, gvecfn, MO_64); |
90b827d1 AB |
13655 | } |
13656 | } | |
13657 | ||
13658 | /* Crypto two-reg SHA512 | |
13659 | * 31 12 11 10 9 5 4 0 | |
13660 | * +-----------------------------------------+--------+------+------+ | |
13661 | * | 1 1 0 0 1 1 1 0 1 1 0 0 0 0 0 0 1 0 0 0 | opcode | Rn | Rd | | |
13662 | * +-----------------------------------------+--------+------+------+ | |
13663 | */ | |
13664 | static void disas_crypto_two_reg_sha512(DisasContext *s, uint32_t insn) | |
13665 | { | |
13666 | int opcode = extract32(insn, 10, 2); | |
13667 | int rn = extract32(insn, 5, 5); | |
13668 | int rd = extract32(insn, 0, 5); | |
962fcbf2 | 13669 | bool feature; |
90b827d1 AB |
13670 | |
13671 | switch (opcode) { | |
13672 | case 0: /* SHA512SU0 */ | |
962fcbf2 | 13673 | feature = dc_isar_feature(aa64_sha512, s); |
90b827d1 | 13674 | break; |
b6577bcd | 13675 | case 1: /* SM4E */ |
962fcbf2 | 13676 | feature = dc_isar_feature(aa64_sm4, s); |
b6577bcd | 13677 | break; |
90b827d1 AB |
13678 | default: |
13679 | unallocated_encoding(s); | |
13680 | return; | |
13681 | } | |
13682 | ||
962fcbf2 | 13683 | if (!feature) { |
90b827d1 AB |
13684 | unallocated_encoding(s); |
13685 | return; | |
13686 | } | |
13687 | ||
13688 | if (!fp_access_check(s)) { | |
13689 | return; | |
13690 | } | |
13691 | ||
aaffebd6 RH |
13692 | switch (opcode) { |
13693 | case 0: /* SHA512SU0 */ | |
13694 | gen_gvec_op2_ool(s, true, rd, rn, 0, gen_helper_crypto_sha512su0); | |
13695 | break; | |
13696 | case 1: /* SM4E */ | |
13697 | gen_gvec_op3_ool(s, true, rd, rd, rn, 0, gen_helper_crypto_sm4e); | |
13698 | break; | |
13699 | default: | |
13700 | g_assert_not_reached(); | |
a04b68e1 | 13701 | } |
90b827d1 AB |
13702 | } |
13703 | ||
cd270ade AB |
13704 | /* Crypto four-register |
13705 | * 31 23 22 21 20 16 15 14 10 9 5 4 0 | |
13706 | * +-------------------+-----+------+---+------+------+------+ | |
13707 | * | 1 1 0 0 1 1 1 0 0 | Op0 | Rm | 0 | Ra | Rn | Rd | | |
13708 | * +-------------------+-----+------+---+------+------+------+ | |
13709 | */ | |
13710 | static void disas_crypto_four_reg(DisasContext *s, uint32_t insn) | |
13711 | { | |
13712 | int op0 = extract32(insn, 21, 2); | |
13713 | int rm = extract32(insn, 16, 5); | |
13714 | int ra = extract32(insn, 10, 5); | |
13715 | int rn = extract32(insn, 5, 5); | |
13716 | int rd = extract32(insn, 0, 5); | |
962fcbf2 | 13717 | bool feature; |
cd270ade AB |
13718 | |
13719 | switch (op0) { | |
13720 | case 0: /* EOR3 */ | |
13721 | case 1: /* BCAX */ | |
962fcbf2 | 13722 | feature = dc_isar_feature(aa64_sha3, s); |
cd270ade | 13723 | break; |
80d6f4c6 | 13724 | case 2: /* SM3SS1 */ |
962fcbf2 | 13725 | feature = dc_isar_feature(aa64_sm3, s); |
80d6f4c6 | 13726 | break; |
cd270ade AB |
13727 | default: |
13728 | unallocated_encoding(s); | |
13729 | return; | |
13730 | } | |
13731 | ||
962fcbf2 | 13732 | if (!feature) { |
cd270ade AB |
13733 | unallocated_encoding(s); |
13734 | return; | |
13735 | } | |
13736 | ||
13737 | if (!fp_access_check(s)) { | |
13738 | return; | |
13739 | } | |
13740 | ||
13741 | if (op0 < 2) { | |
13742 | TCGv_i64 tcg_op1, tcg_op2, tcg_op3, tcg_res[2]; | |
13743 | int pass; | |
13744 | ||
13745 | tcg_op1 = tcg_temp_new_i64(); | |
13746 | tcg_op2 = tcg_temp_new_i64(); | |
13747 | tcg_op3 = tcg_temp_new_i64(); | |
13748 | tcg_res[0] = tcg_temp_new_i64(); | |
13749 | tcg_res[1] = tcg_temp_new_i64(); | |
13750 | ||
13751 | for (pass = 0; pass < 2; pass++) { | |
13752 | read_vec_element(s, tcg_op1, rn, pass, MO_64); | |
13753 | read_vec_element(s, tcg_op2, rm, pass, MO_64); | |
13754 | read_vec_element(s, tcg_op3, ra, pass, MO_64); | |
13755 | ||
13756 | if (op0 == 0) { | |
13757 | /* EOR3 */ | |
13758 | tcg_gen_xor_i64(tcg_res[pass], tcg_op2, tcg_op3); | |
13759 | } else { | |
13760 | /* BCAX */ | |
13761 | tcg_gen_andc_i64(tcg_res[pass], tcg_op2, tcg_op3); | |
13762 | } | |
13763 | tcg_gen_xor_i64(tcg_res[pass], tcg_res[pass], tcg_op1); | |
13764 | } | |
13765 | write_vec_element(s, tcg_res[0], rd, 0, MO_64); | |
13766 | write_vec_element(s, tcg_res[1], rd, 1, MO_64); | |
13767 | ||
13768 | tcg_temp_free_i64(tcg_op1); | |
13769 | tcg_temp_free_i64(tcg_op2); | |
13770 | tcg_temp_free_i64(tcg_op3); | |
13771 | tcg_temp_free_i64(tcg_res[0]); | |
13772 | tcg_temp_free_i64(tcg_res[1]); | |
13773 | } else { | |
80d6f4c6 AB |
13774 | TCGv_i32 tcg_op1, tcg_op2, tcg_op3, tcg_res, tcg_zero; |
13775 | ||
13776 | tcg_op1 = tcg_temp_new_i32(); | |
13777 | tcg_op2 = tcg_temp_new_i32(); | |
13778 | tcg_op3 = tcg_temp_new_i32(); | |
13779 | tcg_res = tcg_temp_new_i32(); | |
13780 | tcg_zero = tcg_const_i32(0); | |
13781 | ||
13782 | read_vec_element_i32(s, tcg_op1, rn, 3, MO_32); | |
13783 | read_vec_element_i32(s, tcg_op2, rm, 3, MO_32); | |
13784 | read_vec_element_i32(s, tcg_op3, ra, 3, MO_32); | |
13785 | ||
13786 | tcg_gen_rotri_i32(tcg_res, tcg_op1, 20); | |
13787 | tcg_gen_add_i32(tcg_res, tcg_res, tcg_op2); | |
13788 | tcg_gen_add_i32(tcg_res, tcg_res, tcg_op3); | |
13789 | tcg_gen_rotri_i32(tcg_res, tcg_res, 25); | |
13790 | ||
13791 | write_vec_element_i32(s, tcg_zero, rd, 0, MO_32); | |
13792 | write_vec_element_i32(s, tcg_zero, rd, 1, MO_32); | |
13793 | write_vec_element_i32(s, tcg_zero, rd, 2, MO_32); | |
13794 | write_vec_element_i32(s, tcg_res, rd, 3, MO_32); | |
13795 | ||
13796 | tcg_temp_free_i32(tcg_op1); | |
13797 | tcg_temp_free_i32(tcg_op2); | |
13798 | tcg_temp_free_i32(tcg_op3); | |
13799 | tcg_temp_free_i32(tcg_res); | |
13800 | tcg_temp_free_i32(tcg_zero); | |
cd270ade AB |
13801 | } |
13802 | } | |
13803 | ||
13804 | /* Crypto XAR | |
13805 | * 31 21 20 16 15 10 9 5 4 0 | |
13806 | * +-----------------------+------+--------+------+------+ | |
13807 | * | 1 1 0 0 1 1 1 0 1 0 0 | Rm | imm6 | Rn | Rd | | |
13808 | * +-----------------------+------+--------+------+------+ | |
13809 | */ | |
13810 | static void disas_crypto_xar(DisasContext *s, uint32_t insn) | |
13811 | { | |
13812 | int rm = extract32(insn, 16, 5); | |
13813 | int imm6 = extract32(insn, 10, 6); | |
13814 | int rn = extract32(insn, 5, 5); | |
13815 | int rd = extract32(insn, 0, 5); | |
13816 | TCGv_i64 tcg_op1, tcg_op2, tcg_res[2]; | |
13817 | int pass; | |
13818 | ||
962fcbf2 | 13819 | if (!dc_isar_feature(aa64_sha3, s)) { |
cd270ade AB |
13820 | unallocated_encoding(s); |
13821 | return; | |
13822 | } | |
13823 | ||
13824 | if (!fp_access_check(s)) { | |
13825 | return; | |
13826 | } | |
13827 | ||
13828 | tcg_op1 = tcg_temp_new_i64(); | |
13829 | tcg_op2 = tcg_temp_new_i64(); | |
13830 | tcg_res[0] = tcg_temp_new_i64(); | |
13831 | tcg_res[1] = tcg_temp_new_i64(); | |
13832 | ||
13833 | for (pass = 0; pass < 2; pass++) { | |
13834 | read_vec_element(s, tcg_op1, rn, pass, MO_64); | |
13835 | read_vec_element(s, tcg_op2, rm, pass, MO_64); | |
13836 | ||
13837 | tcg_gen_xor_i64(tcg_res[pass], tcg_op1, tcg_op2); | |
13838 | tcg_gen_rotri_i64(tcg_res[pass], tcg_res[pass], imm6); | |
13839 | } | |
13840 | write_vec_element(s, tcg_res[0], rd, 0, MO_64); | |
13841 | write_vec_element(s, tcg_res[1], rd, 1, MO_64); | |
13842 | ||
13843 | tcg_temp_free_i64(tcg_op1); | |
13844 | tcg_temp_free_i64(tcg_op2); | |
13845 | tcg_temp_free_i64(tcg_res[0]); | |
13846 | tcg_temp_free_i64(tcg_res[1]); | |
13847 | } | |
13848 | ||
80d6f4c6 AB |
13849 | /* Crypto three-reg imm2 |
13850 | * 31 21 20 16 15 14 13 12 11 10 9 5 4 0 | |
13851 | * +-----------------------+------+-----+------+--------+------+------+ | |
13852 | * | 1 1 0 0 1 1 1 0 0 1 0 | Rm | 1 0 | imm2 | opcode | Rn | Rd | | |
13853 | * +-----------------------+------+-----+------+--------+------+------+ | |
13854 | */ | |
13855 | static void disas_crypto_three_reg_imm2(DisasContext *s, uint32_t insn) | |
13856 | { | |
43fa36c9 RH |
13857 | static gen_helper_gvec_3 * const fns[4] = { |
13858 | gen_helper_crypto_sm3tt1a, gen_helper_crypto_sm3tt1b, | |
13859 | gen_helper_crypto_sm3tt2a, gen_helper_crypto_sm3tt2b, | |
13860 | }; | |
80d6f4c6 AB |
13861 | int opcode = extract32(insn, 10, 2); |
13862 | int imm2 = extract32(insn, 12, 2); | |
13863 | int rm = extract32(insn, 16, 5); | |
13864 | int rn = extract32(insn, 5, 5); | |
13865 | int rd = extract32(insn, 0, 5); | |
80d6f4c6 | 13866 | |
962fcbf2 | 13867 | if (!dc_isar_feature(aa64_sm3, s)) { |
80d6f4c6 AB |
13868 | unallocated_encoding(s); |
13869 | return; | |
13870 | } | |
13871 | ||
13872 | if (!fp_access_check(s)) { | |
13873 | return; | |
13874 | } | |
13875 | ||
43fa36c9 | 13876 | gen_gvec_op3_ool(s, true, rd, rn, rm, imm2, fns[opcode]); |
80d6f4c6 AB |
13877 | } |
13878 | ||
384b26fb AB |
13879 | /* C3.6 Data processing - SIMD, inc Crypto |
13880 | * | |
13881 | * As the decode gets a little complex we are using a table based | |
13882 | * approach for this part of the decode. | |
13883 | */ | |
13884 | static const AArch64DecodeTable data_proc_simd[] = { | |
13885 | /* pattern , mask , fn */ | |
13886 | { 0x0e200400, 0x9f200400, disas_simd_three_reg_same }, | |
e7186d82 | 13887 | { 0x0e008400, 0x9f208400, disas_simd_three_reg_same_extra }, |
384b26fb AB |
13888 | { 0x0e200000, 0x9f200c00, disas_simd_three_reg_diff }, |
13889 | { 0x0e200800, 0x9f3e0c00, disas_simd_two_reg_misc }, | |
13890 | { 0x0e300800, 0x9f3e0c00, disas_simd_across_lanes }, | |
13891 | { 0x0e000400, 0x9fe08400, disas_simd_copy }, | |
9f82e0ff | 13892 | { 0x0f000000, 0x9f000400, disas_simd_indexed }, /* vector indexed */ |
384b26fb AB |
13893 | /* simd_mod_imm decode is a subset of simd_shift_imm, so must precede it */ |
13894 | { 0x0f000400, 0x9ff80400, disas_simd_mod_imm }, | |
13895 | { 0x0f000400, 0x9f800400, disas_simd_shift_imm }, | |
13896 | { 0x0e000000, 0xbf208c00, disas_simd_tb }, | |
13897 | { 0x0e000800, 0xbf208c00, disas_simd_zip_trn }, | |
13898 | { 0x2e000000, 0xbf208400, disas_simd_ext }, | |
13899 | { 0x5e200400, 0xdf200400, disas_simd_scalar_three_reg_same }, | |
d9061ec3 | 13900 | { 0x5e008400, 0xdf208400, disas_simd_scalar_three_reg_same_extra }, |
384b26fb AB |
13901 | { 0x5e200000, 0xdf200c00, disas_simd_scalar_three_reg_diff }, |
13902 | { 0x5e200800, 0xdf3e0c00, disas_simd_scalar_two_reg_misc }, | |
13903 | { 0x5e300800, 0xdf3e0c00, disas_simd_scalar_pairwise }, | |
13904 | { 0x5e000400, 0xdfe08400, disas_simd_scalar_copy }, | |
9f82e0ff | 13905 | { 0x5f000000, 0xdf000400, disas_simd_indexed }, /* scalar indexed */ |
384b26fb AB |
13906 | { 0x5f000400, 0xdf800400, disas_simd_scalar_shift_imm }, |
13907 | { 0x4e280800, 0xff3e0c00, disas_crypto_aes }, | |
13908 | { 0x5e000000, 0xff208c00, disas_crypto_three_reg_sha }, | |
13909 | { 0x5e280800, 0xff3e0c00, disas_crypto_two_reg_sha }, | |
90b827d1 AB |
13910 | { 0xce608000, 0xffe0b000, disas_crypto_three_reg_sha512 }, |
13911 | { 0xcec08000, 0xfffff000, disas_crypto_two_reg_sha512 }, | |
cd270ade AB |
13912 | { 0xce000000, 0xff808000, disas_crypto_four_reg }, |
13913 | { 0xce800000, 0xffe00000, disas_crypto_xar }, | |
80d6f4c6 | 13914 | { 0xce408000, 0xffe0c000, disas_crypto_three_reg_imm2 }, |
376e8d6c | 13915 | { 0x0e400400, 0x9f60c400, disas_simd_three_reg_same_fp16 }, |
5d432be6 | 13916 | { 0x0e780800, 0x8f7e0c00, disas_simd_two_reg_misc_fp16 }, |
7c93b774 | 13917 | { 0x5e400400, 0xdf60c400, disas_simd_scalar_three_reg_same_fp16 }, |
384b26fb AB |
13918 | { 0x00000000, 0x00000000, NULL } |
13919 | }; | |
13920 | ||
faa0ba46 PM |
13921 | static void disas_data_proc_simd(DisasContext *s, uint32_t insn) |
13922 | { | |
13923 | /* Note that this is called with all non-FP cases from | |
13924 | * table C3-6 so it must UNDEF for entries not specifically | |
13925 | * allocated to instructions in that table. | |
13926 | */ | |
384b26fb AB |
13927 | AArch64DecodeFn *fn = lookup_disas_fn(&data_proc_simd[0], insn); |
13928 | if (fn) { | |
13929 | fn(s, insn); | |
13930 | } else { | |
13931 | unallocated_encoding(s); | |
13932 | } | |
faa0ba46 PM |
13933 | } |
13934 | ||
ad7ee8a2 CF |
13935 | /* C3.6 Data processing - SIMD and floating point */ |
13936 | static void disas_data_proc_simd_fp(DisasContext *s, uint32_t insn) | |
13937 | { | |
faa0ba46 PM |
13938 | if (extract32(insn, 28, 1) == 1 && extract32(insn, 30, 1) == 0) { |
13939 | disas_data_proc_fp(s, insn); | |
13940 | } else { | |
13941 | /* SIMD, including crypto */ | |
13942 | disas_data_proc_simd(s, insn); | |
13943 | } | |
ad7ee8a2 CF |
13944 | } |
13945 | ||
51bf0d7a RH |
13946 | /** |
13947 | * is_guarded_page: | |
13948 | * @env: The cpu environment | |
13949 | * @s: The DisasContext | |
13950 | * | |
13951 | * Return true if the page is guarded. | |
13952 | */ | |
13953 | static bool is_guarded_page(CPUARMState *env, DisasContext *s) | |
13954 | { | |
13955 | #ifdef CONFIG_USER_ONLY | |
13956 | return false; /* FIXME */ | |
13957 | #else | |
13958 | uint64_t addr = s->base.pc_first; | |
13959 | int mmu_idx = arm_to_core_mmu_idx(s->mmu_idx); | |
13960 | unsigned int index = tlb_index(env, mmu_idx, addr); | |
13961 | CPUTLBEntry *entry = tlb_entry(env, mmu_idx, addr); | |
13962 | ||
13963 | /* | |
13964 | * We test this immediately after reading an insn, which means | |
13965 | * that any normal page must be in the TLB. The only exception | |
13966 | * would be for executing from flash or device memory, which | |
13967 | * does not retain the TLB entry. | |
13968 | * | |
13969 | * FIXME: Assume false for those, for now. We could use | |
13970 | * arm_cpu_get_phys_page_attrs_debug to re-read the page | |
13971 | * table entry even for that case. | |
13972 | */ | |
13973 | return (tlb_hit(entry->addr_code, addr) && | |
a40ec84e | 13974 | env_tlb(env)->d[mmu_idx].iotlb[index].attrs.target_tlb_bit0); |
51bf0d7a RH |
13975 | #endif |
13976 | } | |
13977 | ||
13978 | /** | |
13979 | * btype_destination_ok: | |
13980 | * @insn: The instruction at the branch destination | |
13981 | * @bt: SCTLR_ELx.BT | |
13982 | * @btype: PSTATE.BTYPE, and is non-zero | |
13983 | * | |
13984 | * On a guarded page, there are a limited number of insns | |
13985 | * that may be present at the branch target: | |
13986 | * - branch target identifiers, | |
13987 | * - paciasp, pacibsp, | |
13988 | * - BRK insn | |
13989 | * - HLT insn | |
13990 | * Anything else causes a Branch Target Exception. | |
13991 | * | |
13992 | * Return true if the branch is compatible, false to raise BTITRAP. | |
13993 | */ | |
13994 | static bool btype_destination_ok(uint32_t insn, bool bt, int btype) | |
13995 | { | |
13996 | if ((insn & 0xfffff01fu) == 0xd503201fu) { | |
13997 | /* HINT space */ | |
13998 | switch (extract32(insn, 5, 7)) { | |
13999 | case 0b011001: /* PACIASP */ | |
14000 | case 0b011011: /* PACIBSP */ | |
14001 | /* | |
14002 | * If SCTLR_ELx.BT, then PACI*SP are not compatible | |
14003 | * with btype == 3. Otherwise all btype are ok. | |
14004 | */ | |
14005 | return !bt || btype != 3; | |
14006 | case 0b100000: /* BTI */ | |
14007 | /* Not compatible with any btype. */ | |
14008 | return false; | |
14009 | case 0b100010: /* BTI c */ | |
14010 | /* Not compatible with btype == 3 */ | |
14011 | return btype != 3; | |
14012 | case 0b100100: /* BTI j */ | |
14013 | /* Not compatible with btype == 2 */ | |
14014 | return btype != 2; | |
14015 | case 0b100110: /* BTI jc */ | |
14016 | /* Compatible with any btype. */ | |
14017 | return true; | |
14018 | } | |
14019 | } else { | |
14020 | switch (insn & 0xffe0001fu) { | |
14021 | case 0xd4200000u: /* BRK */ | |
14022 | case 0xd4400000u: /* HLT */ | |
14023 | /* Give priority to the breakpoint exception. */ | |
14024 | return true; | |
14025 | } | |
14026 | } | |
14027 | return false; | |
14028 | } | |
14029 | ||
ad7ee8a2 | 14030 | /* C3.1 A64 instruction index by encoding */ |
40f860cd | 14031 | static void disas_a64_insn(CPUARMState *env, DisasContext *s) |
14ade10f AG |
14032 | { |
14033 | uint32_t insn; | |
14034 | ||
a0415916 RH |
14035 | s->pc_curr = s->base.pc_next; |
14036 | insn = arm_ldl_code(env, s->base.pc_next, s->sctlr_b); | |
14ade10f | 14037 | s->insn = insn; |
a0415916 | 14038 | s->base.pc_next += 4; |
14ade10f | 14039 | |
90e49638 PM |
14040 | s->fp_access_checked = false; |
14041 | ||
51bf0d7a RH |
14042 | if (dc_isar_feature(aa64_bti, s)) { |
14043 | if (s->base.num_insns == 1) { | |
14044 | /* | |
14045 | * At the first insn of the TB, compute s->guarded_page. | |
14046 | * We delayed computing this until successfully reading | |
14047 | * the first insn of the TB, above. This (mostly) ensures | |
14048 | * that the softmmu tlb entry has been populated, and the | |
14049 | * page table GP bit is available. | |
14050 | * | |
14051 | * Note that we need to compute this even if btype == 0, | |
14052 | * because this value is used for BR instructions later | |
14053 | * where ENV is not available. | |
14054 | */ | |
14055 | s->guarded_page = is_guarded_page(env, s); | |
14056 | ||
14057 | /* First insn can have btype set to non-zero. */ | |
14058 | tcg_debug_assert(s->btype >= 0); | |
14059 | ||
14060 | /* | |
14061 | * Note that the Branch Target Exception has fairly high | |
14062 | * priority -- below debugging exceptions but above most | |
14063 | * everything else. This allows us to handle this now | |
14064 | * instead of waiting until the insn is otherwise decoded. | |
14065 | */ | |
14066 | if (s->btype != 0 | |
14067 | && s->guarded_page | |
14068 | && !btype_destination_ok(insn, s->bt, s->btype)) { | |
a767fac8 RH |
14069 | gen_exception_insn(s, s->pc_curr, EXCP_UDEF, |
14070 | syn_btitrap(s->btype), | |
51bf0d7a RH |
14071 | default_exception_el(s)); |
14072 | return; | |
14073 | } | |
14074 | } else { | |
14075 | /* Not the first insn: btype must be 0. */ | |
14076 | tcg_debug_assert(s->btype == 0); | |
14077 | } | |
14078 | } | |
14079 | ||
ad7ee8a2 | 14080 | switch (extract32(insn, 25, 4)) { |
38388f7e | 14081 | case 0x0: case 0x1: case 0x3: /* UNALLOCATED */ |
14ade10f AG |
14082 | unallocated_encoding(s); |
14083 | break; | |
38388f7e | 14084 | case 0x2: |
cd208a1c | 14085 | if (!dc_isar_feature(aa64_sve, s) || !disas_sve(s, insn)) { |
38388f7e RH |
14086 | unallocated_encoding(s); |
14087 | } | |
14088 | break; | |
ad7ee8a2 CF |
14089 | case 0x8: case 0x9: /* Data processing - immediate */ |
14090 | disas_data_proc_imm(s, insn); | |
14091 | break; | |
14092 | case 0xa: case 0xb: /* Branch, exception generation and system insns */ | |
14093 | disas_b_exc_sys(s, insn); | |
14094 | break; | |
14095 | case 0x4: | |
14096 | case 0x6: | |
14097 | case 0xc: | |
14098 | case 0xe: /* Loads and stores */ | |
14099 | disas_ldst(s, insn); | |
14100 | break; | |
14101 | case 0x5: | |
14102 | case 0xd: /* Data processing - register */ | |
14103 | disas_data_proc_reg(s, insn); | |
14104 | break; | |
14105 | case 0x7: | |
14106 | case 0xf: /* Data processing - SIMD and floating point */ | |
14107 | disas_data_proc_simd_fp(s, insn); | |
14108 | break; | |
14109 | default: | |
14110 | assert(FALSE); /* all 15 cases should be handled above */ | |
14111 | break; | |
14ade10f | 14112 | } |
11e169de AG |
14113 | |
14114 | /* if we allocated any temporaries, free them here */ | |
14115 | free_tmp_a64(s); | |
51bf0d7a RH |
14116 | |
14117 | /* | |
14118 | * After execution of most insns, btype is reset to 0. | |
14119 | * Note that we set btype == -1 when the insn sets btype. | |
14120 | */ | |
14121 | if (s->btype > 0 && s->base.is_jmp != DISAS_NORETURN) { | |
14122 | reset_btype(s); | |
14123 | } | |
40f860cd | 14124 | } |
14ade10f | 14125 | |
b542683d EC |
14126 | static void aarch64_tr_init_disas_context(DisasContextBase *dcbase, |
14127 | CPUState *cpu) | |
40f860cd | 14128 | { |
dcba3a8d | 14129 | DisasContext *dc = container_of(dcbase, DisasContext, base); |
5c039906 | 14130 | CPUARMState *env = cpu->env_ptr; |
2fc0cc0e | 14131 | ARMCPU *arm_cpu = env_archcpu(env); |
aad821ac RH |
14132 | uint32_t tb_flags = dc->base.tb->flags; |
14133 | int bound, core_mmu_idx; | |
40f860cd | 14134 | |
962fcbf2 | 14135 | dc->isar = &arm_cpu->isar; |
40f860cd PM |
14136 | dc->condjmp = 0; |
14137 | ||
14138 | dc->aarch64 = 1; | |
cef9ee70 SS |
14139 | /* If we are coming from secure EL0 in a system with a 32-bit EL3, then |
14140 | * there is no secure EL1, so we route exceptions to EL3. | |
14141 | */ | |
14142 | dc->secure_routed_to_el3 = arm_feature(env, ARM_FEATURE_EL3) && | |
14143 | !arm_el_is_aa64(env, 3); | |
40f860cd | 14144 | dc->thumb = 0; |
f9fd40eb | 14145 | dc->sctlr_b = 0; |
aad821ac | 14146 | dc->be_data = FIELD_EX32(tb_flags, TBFLAG_ANY, BE_DATA) ? MO_BE : MO_LE; |
40f860cd PM |
14147 | dc->condexec_mask = 0; |
14148 | dc->condexec_cond = 0; | |
aad821ac | 14149 | core_mmu_idx = FIELD_EX32(tb_flags, TBFLAG_ANY, MMUIDX); |
20dc67c9 | 14150 | dc->mmu_idx = core_to_aa64_mmu_idx(core_mmu_idx); |
476a4692 | 14151 | dc->tbii = FIELD_EX32(tb_flags, TBFLAG_A64, TBII); |
4a9ee99d | 14152 | dc->tbid = FIELD_EX32(tb_flags, TBFLAG_A64, TBID); |
c1e37810 | 14153 | dc->current_el = arm_mmu_idx_to_el(dc->mmu_idx); |
40f860cd | 14154 | #if !defined(CONFIG_USER_ONLY) |
c1e37810 | 14155 | dc->user = (dc->current_el == 0); |
40f860cd | 14156 | #endif |
aad821ac RH |
14157 | dc->fp_excp_el = FIELD_EX32(tb_flags, TBFLAG_ANY, FPEXC_EL); |
14158 | dc->sve_excp_el = FIELD_EX32(tb_flags, TBFLAG_A64, SVEEXC_EL); | |
14159 | dc->sve_len = (FIELD_EX32(tb_flags, TBFLAG_A64, ZCR_LEN) + 1) * 16; | |
0816ef1b | 14160 | dc->pauth_active = FIELD_EX32(tb_flags, TBFLAG_A64, PAUTH_ACTIVE); |
08f1434a RH |
14161 | dc->bt = FIELD_EX32(tb_flags, TBFLAG_A64, BT); |
14162 | dc->btype = FIELD_EX32(tb_flags, TBFLAG_A64, BTYPE); | |
cc28fc30 | 14163 | dc->unpriv = FIELD_EX32(tb_flags, TBFLAG_A64, UNPRIV); |
40f860cd PM |
14164 | dc->vec_len = 0; |
14165 | dc->vec_stride = 0; | |
5c039906 | 14166 | dc->cp_regs = arm_cpu->cp_regs; |
a984e42c | 14167 | dc->features = env->features; |
40f860cd | 14168 | |
7ea47fe7 PM |
14169 | /* Single step state. The code-generation logic here is: |
14170 | * SS_ACTIVE == 0: | |
14171 | * generate code with no special handling for single-stepping (except | |
14172 | * that anything that can make us go to SS_ACTIVE == 1 must end the TB; | |
14173 | * this happens anyway because those changes are all system register or | |
14174 | * PSTATE writes). | |
14175 | * SS_ACTIVE == 1, PSTATE.SS == 1: (active-not-pending) | |
14176 | * emit code for one insn | |
14177 | * emit code to clear PSTATE.SS | |
14178 | * emit code to generate software step exception for completed step | |
14179 | * end TB (as usual for having generated an exception) | |
14180 | * SS_ACTIVE == 1, PSTATE.SS == 0: (active-pending) | |
14181 | * emit code to generate a software step exception | |
14182 | * end the TB | |
14183 | */ | |
aad821ac RH |
14184 | dc->ss_active = FIELD_EX32(tb_flags, TBFLAG_ANY, SS_ACTIVE); |
14185 | dc->pstate_ss = FIELD_EX32(tb_flags, TBFLAG_ANY, PSTATE_SS); | |
7ea47fe7 | 14186 | dc->is_ldex = false; |
8bd587c1 | 14187 | dc->debug_target_el = FIELD_EX32(tb_flags, TBFLAG_ANY, DEBUG_TARGET_EL); |
7ea47fe7 | 14188 | |
dcc3a212 RH |
14189 | /* Bound the number of insns to execute to those left on the page. */ |
14190 | bound = -(dc->base.pc_first | TARGET_PAGE_MASK) / 4; | |
14191 | ||
14192 | /* If architectural single step active, limit to 1. */ | |
14193 | if (dc->ss_active) { | |
14194 | bound = 1; | |
14195 | } | |
b542683d | 14196 | dc->base.max_insns = MIN(dc->base.max_insns, bound); |
24299c89 | 14197 | |
11e169de | 14198 | init_tmp_a64_array(dc); |
5c039906 LV |
14199 | } |
14200 | ||
23169224 LV |
14201 | static void aarch64_tr_tb_start(DisasContextBase *db, CPUState *cpu) |
14202 | { | |
23169224 LV |
14203 | } |
14204 | ||
a68956ad LV |
14205 | static void aarch64_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) |
14206 | { | |
14207 | DisasContext *dc = container_of(dcbase, DisasContext, base); | |
14208 | ||
a0415916 | 14209 | tcg_gen_insn_start(dc->base.pc_next, 0, 0); |
15fa08f8 | 14210 | dc->insn_start = tcg_last_op(); |
a68956ad LV |
14211 | } |
14212 | ||
0cb56b37 LV |
14213 | static bool aarch64_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu, |
14214 | const CPUBreakpoint *bp) | |
14215 | { | |
14216 | DisasContext *dc = container_of(dcbase, DisasContext, base); | |
14217 | ||
14218 | if (bp->flags & BP_CPU) { | |
a0415916 | 14219 | gen_a64_set_pc_im(dc->base.pc_next); |
0cb56b37 LV |
14220 | gen_helper_check_breakpoints(cpu_env); |
14221 | /* End the TB early; it likely won't be executed */ | |
14222 | dc->base.is_jmp = DISAS_TOO_MANY; | |
14223 | } else { | |
aee828e7 | 14224 | gen_exception_internal_insn(dc, dc->base.pc_next, EXCP_DEBUG); |
0cb56b37 LV |
14225 | /* The address covered by the breakpoint must be |
14226 | included in [tb->pc, tb->pc + tb->size) in order | |
14227 | to for it to be properly cleared -- thus we | |
14228 | increment the PC here so that the logic setting | |
14229 | tb->size below does the right thing. */ | |
a0415916 | 14230 | dc->base.pc_next += 4; |
0cb56b37 LV |
14231 | dc->base.is_jmp = DISAS_NORETURN; |
14232 | } | |
14233 | ||
14234 | return true; | |
14235 | } | |
14236 | ||
24299c89 LV |
14237 | static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) |
14238 | { | |
14239 | DisasContext *dc = container_of(dcbase, DisasContext, base); | |
14240 | CPUARMState *env = cpu->env_ptr; | |
14241 | ||
14242 | if (dc->ss_active && !dc->pstate_ss) { | |
14243 | /* Singlestep state is Active-pending. | |
14244 | * If we're in this state at the start of a TB then either | |
14245 | * a) we just took an exception to an EL which is being debugged | |
14246 | * and this is the first insn in the exception handler | |
14247 | * b) debug exceptions were masked and we just unmasked them | |
14248 | * without changing EL (eg by clearing PSTATE.D) | |
14249 | * In either case we're going to take a swstep exception in the | |
14250 | * "did not step an insn" case, and so the syndrome ISV and EX | |
14251 | * bits should be zero. | |
14252 | */ | |
14253 | assert(dc->base.num_insns == 1); | |
c1d5f50f | 14254 | gen_swstep_exception(dc, 0, 0); |
24299c89 LV |
14255 | dc->base.is_jmp = DISAS_NORETURN; |
14256 | } else { | |
14257 | disas_a64_insn(env, dc); | |
14258 | } | |
14259 | ||
23169224 | 14260 | translator_loop_temp_check(&dc->base); |
24299c89 LV |
14261 | } |
14262 | ||
be407964 LV |
14263 | static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) |
14264 | { | |
14265 | DisasContext *dc = container_of(dcbase, DisasContext, base); | |
14266 | ||
14267 | if (unlikely(dc->base.singlestep_enabled || dc->ss_active)) { | |
14268 | /* Note that this means single stepping WFI doesn't halt the CPU. | |
14269 | * For conditional branch insns this is harmless unreachable code as | |
14270 | * gen_goto_tb() has already handled emitting the debug exception | |
14271 | * (and thus a tb-jump is not possible when singlestepping). | |
14272 | */ | |
14273 | switch (dc->base.is_jmp) { | |
14274 | default: | |
a0415916 | 14275 | gen_a64_set_pc_im(dc->base.pc_next); |
be407964 | 14276 | /* fall through */ |
dddbba99 | 14277 | case DISAS_EXIT: |
be407964 LV |
14278 | case DISAS_JUMP: |
14279 | if (dc->base.singlestep_enabled) { | |
14280 | gen_exception_internal(EXCP_DEBUG); | |
14281 | } else { | |
14282 | gen_step_complete_exception(dc); | |
14283 | } | |
14284 | break; | |
14285 | case DISAS_NORETURN: | |
14286 | break; | |
14287 | } | |
14288 | } else { | |
14289 | switch (dc->base.is_jmp) { | |
14290 | case DISAS_NEXT: | |
14291 | case DISAS_TOO_MANY: | |
a0415916 | 14292 | gen_goto_tb(dc, 1, dc->base.pc_next); |
be407964 LV |
14293 | break; |
14294 | default: | |
14295 | case DISAS_UPDATE: | |
a0415916 | 14296 | gen_a64_set_pc_im(dc->base.pc_next); |
be407964 | 14297 | /* fall through */ |
be407964 | 14298 | case DISAS_EXIT: |
07ea28b4 | 14299 | tcg_gen_exit_tb(NULL, 0); |
be407964 | 14300 | break; |
a75a52d6 VK |
14301 | case DISAS_JUMP: |
14302 | tcg_gen_lookup_and_goto_ptr(); | |
14303 | break; | |
be407964 LV |
14304 | case DISAS_NORETURN: |
14305 | case DISAS_SWI: | |
14306 | break; | |
14307 | case DISAS_WFE: | |
a0415916 | 14308 | gen_a64_set_pc_im(dc->base.pc_next); |
be407964 LV |
14309 | gen_helper_wfe(cpu_env); |
14310 | break; | |
14311 | case DISAS_YIELD: | |
a0415916 | 14312 | gen_a64_set_pc_im(dc->base.pc_next); |
be407964 LV |
14313 | gen_helper_yield(cpu_env); |
14314 | break; | |
14315 | case DISAS_WFI: | |
58803318 | 14316 | { |
be407964 LV |
14317 | /* This is a special case because we don't want to just halt the CPU |
14318 | * if trying to debug across a WFI. | |
14319 | */ | |
58803318 SS |
14320 | TCGv_i32 tmp = tcg_const_i32(4); |
14321 | ||
a0415916 | 14322 | gen_a64_set_pc_im(dc->base.pc_next); |
58803318 SS |
14323 | gen_helper_wfi(cpu_env, tmp); |
14324 | tcg_temp_free_i32(tmp); | |
be407964 LV |
14325 | /* The helper doesn't necessarily throw an exception, but we |
14326 | * must go back to the main loop to check for interrupts anyway. | |
14327 | */ | |
07ea28b4 | 14328 | tcg_gen_exit_tb(NULL, 0); |
be407964 LV |
14329 | break; |
14330 | } | |
58803318 | 14331 | } |
be407964 LV |
14332 | } |
14333 | } | |
14334 | ||
58350fa4 LV |
14335 | static void aarch64_tr_disas_log(const DisasContextBase *dcbase, |
14336 | CPUState *cpu) | |
14337 | { | |
14338 | DisasContext *dc = container_of(dcbase, DisasContext, base); | |
14339 | ||
14340 | qemu_log("IN: %s\n", lookup_symbol(dc->base.pc_first)); | |
1d48474d | 14341 | log_target_disas(cpu, dc->base.pc_first, dc->base.tb->size); |
58350fa4 LV |
14342 | } |
14343 | ||
23169224 LV |
14344 | const TranslatorOps aarch64_translator_ops = { |
14345 | .init_disas_context = aarch64_tr_init_disas_context, | |
14346 | .tb_start = aarch64_tr_tb_start, | |
14347 | .insn_start = aarch64_tr_insn_start, | |
14348 | .breakpoint_check = aarch64_tr_breakpoint_check, | |
14349 | .translate_insn = aarch64_tr_translate_insn, | |
14350 | .tb_stop = aarch64_tr_tb_stop, | |
14351 | .disas_log = aarch64_tr_disas_log, | |
14352 | }; |