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14ade10f AG |
1 | /* |
2 | * AArch64 translation | |
3 | * | |
4 | * Copyright (c) 2013 Alexander Graf <agraf@suse.de> | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
74c21bd0 | 19 | #include "qemu/osdep.h" |
14ade10f AG |
20 | |
21 | #include "cpu.h" | |
63c91552 | 22 | #include "exec/exec-all.h" |
14ade10f | 23 | #include "tcg-op.h" |
bc48092f | 24 | #include "tcg-op-gvec.h" |
14ade10f | 25 | #include "qemu/log.h" |
1d854765 | 26 | #include "arm_ldst.h" |
14ade10f | 27 | #include "translate.h" |
ccd38087 | 28 | #include "internals.h" |
14ade10f AG |
29 | #include "qemu/host-utils.h" |
30 | ||
8012c84f | 31 | #include "exec/semihost.h" |
40f860cd PM |
32 | #include "exec/gen-icount.h" |
33 | ||
2ef6175a RH |
34 | #include "exec/helper-proto.h" |
35 | #include "exec/helper-gen.h" | |
508127e2 | 36 | #include "exec/log.h" |
14ade10f | 37 | |
a7e30d84 | 38 | #include "trace-tcg.h" |
8c71baed | 39 | #include "translate-a64.h" |
62823083 | 40 | #include "qemu/atomic128.h" |
a7e30d84 | 41 | |
14ade10f AG |
42 | static TCGv_i64 cpu_X[32]; |
43 | static TCGv_i64 cpu_pc; | |
14ade10f | 44 | |
fa2ef212 | 45 | /* Load/store exclusive handling */ |
fa2ef212 | 46 | static TCGv_i64 cpu_exclusive_high; |
fa2ef212 | 47 | |
14ade10f AG |
48 | static const char *regnames[] = { |
49 | "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", | |
50 | "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", | |
51 | "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", | |
52 | "x24", "x25", "x26", "x27", "x28", "x29", "lr", "sp" | |
53 | }; | |
54 | ||
832ffa1c AG |
55 | enum a64_shift_type { |
56 | A64_SHIFT_TYPE_LSL = 0, | |
57 | A64_SHIFT_TYPE_LSR = 1, | |
58 | A64_SHIFT_TYPE_ASR = 2, | |
59 | A64_SHIFT_TYPE_ROR = 3 | |
60 | }; | |
61 | ||
384b26fb AB |
62 | /* Table based decoder typedefs - used when the relevant bits for decode |
63 | * are too awkwardly scattered across the instruction (eg SIMD). | |
64 | */ | |
65 | typedef void AArch64DecodeFn(DisasContext *s, uint32_t insn); | |
66 | ||
67 | typedef struct AArch64DecodeTable { | |
68 | uint32_t pattern; | |
69 | uint32_t mask; | |
70 | AArch64DecodeFn *disas_fn; | |
71 | } AArch64DecodeTable; | |
72 | ||
1f8a73af | 73 | /* Function prototype for gen_ functions for calling Neon helpers */ |
0a79bc87 | 74 | typedef void NeonGenOneOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32); |
1f8a73af | 75 | typedef void NeonGenTwoOpFn(TCGv_i32, TCGv_i32, TCGv_i32); |
6d9571f7 | 76 | typedef void NeonGenTwoOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32); |
70d7f984 | 77 | typedef void NeonGenTwo64OpFn(TCGv_i64, TCGv_i64, TCGv_i64); |
a847f32c | 78 | typedef void NeonGenTwo64OpEnvFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i64); |
d980fd59 PM |
79 | typedef void NeonGenNarrowFn(TCGv_i32, TCGv_i64); |
80 | typedef void NeonGenNarrowEnvFn(TCGv_i32, TCGv_ptr, TCGv_i64); | |
70d7f984 | 81 | typedef void NeonGenWidenFn(TCGv_i64, TCGv_i32); |
8908f4d1 AB |
82 | typedef void NeonGenTwoSingleOPFn(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_ptr); |
83 | typedef void NeonGenTwoDoubleOPFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_ptr); | |
6781fa11 | 84 | typedef void NeonGenOneOpFn(TCGv_i64, TCGv_i64); |
1a66ac61 RH |
85 | typedef void CryptoTwoOpFn(TCGv_ptr, TCGv_ptr); |
86 | typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32); | |
87 | typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr); | |
74608ea4 | 88 | typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, TCGMemOp); |
1f8a73af | 89 | |
14ade10f AG |
90 | /* initialize TCG globals. */ |
91 | void a64_translate_init(void) | |
92 | { | |
93 | int i; | |
94 | ||
e1ccc054 | 95 | cpu_pc = tcg_global_mem_new_i64(cpu_env, |
14ade10f AG |
96 | offsetof(CPUARMState, pc), |
97 | "pc"); | |
98 | for (i = 0; i < 32; i++) { | |
e1ccc054 | 99 | cpu_X[i] = tcg_global_mem_new_i64(cpu_env, |
14ade10f AG |
100 | offsetof(CPUARMState, xregs[i]), |
101 | regnames[i]); | |
102 | } | |
103 | ||
e1ccc054 | 104 | cpu_exclusive_high = tcg_global_mem_new_i64(cpu_env, |
fa2ef212 | 105 | offsetof(CPUARMState, exclusive_high), "exclusive_high"); |
14ade10f AG |
106 | } |
107 | ||
8bd5c820 | 108 | static inline int get_a64_user_mem_index(DisasContext *s) |
579d21cc | 109 | { |
8bd5c820 | 110 | /* Return the core mmu_idx to use for A64 "unprivileged load/store" insns: |
579d21cc PM |
111 | * if EL1, access as if EL0; otherwise access at current EL |
112 | */ | |
8bd5c820 PM |
113 | ARMMMUIdx useridx; |
114 | ||
579d21cc PM |
115 | switch (s->mmu_idx) { |
116 | case ARMMMUIdx_S12NSE1: | |
8bd5c820 PM |
117 | useridx = ARMMMUIdx_S12NSE0; |
118 | break; | |
579d21cc | 119 | case ARMMMUIdx_S1SE1: |
8bd5c820 PM |
120 | useridx = ARMMMUIdx_S1SE0; |
121 | break; | |
579d21cc PM |
122 | case ARMMMUIdx_S2NS: |
123 | g_assert_not_reached(); | |
124 | default: | |
8bd5c820 PM |
125 | useridx = s->mmu_idx; |
126 | break; | |
579d21cc | 127 | } |
8bd5c820 | 128 | return arm_to_core_mmu_idx(useridx); |
579d21cc PM |
129 | } |
130 | ||
51bf0d7a RH |
131 | static void reset_btype(DisasContext *s) |
132 | { | |
133 | if (s->btype != 0) { | |
134 | TCGv_i32 zero = tcg_const_i32(0); | |
135 | tcg_gen_st_i32(zero, cpu_env, offsetof(CPUARMState, btype)); | |
136 | tcg_temp_free_i32(zero); | |
137 | s->btype = 0; | |
138 | } | |
139 | } | |
140 | ||
001d47b6 RH |
141 | static void set_btype(DisasContext *s, int val) |
142 | { | |
143 | TCGv_i32 tcg_val; | |
144 | ||
145 | /* BTYPE is a 2-bit field, and 0 should be done with reset_btype. */ | |
146 | tcg_debug_assert(val >= 1 && val <= 3); | |
147 | ||
148 | tcg_val = tcg_const_i32(val); | |
149 | tcg_gen_st_i32(tcg_val, cpu_env, offsetof(CPUARMState, btype)); | |
150 | tcg_temp_free_i32(tcg_val); | |
151 | s->btype = -1; | |
152 | } | |
153 | ||
14ade10f AG |
154 | void aarch64_cpu_dump_state(CPUState *cs, FILE *f, |
155 | fprintf_function cpu_fprintf, int flags) | |
156 | { | |
157 | ARMCPU *cpu = ARM_CPU(cs); | |
158 | CPUARMState *env = &cpu->env; | |
d356312f | 159 | uint32_t psr = pstate_read(env); |
14ade10f | 160 | int i; |
08b8e0f5 | 161 | int el = arm_current_el(env); |
06e5cf7a | 162 | const char *ns_status; |
14ade10f | 163 | |
3cb506a3 RH |
164 | cpu_fprintf(f, " PC=%016" PRIx64 " ", env->pc); |
165 | for (i = 0; i < 32; i++) { | |
166 | if (i == 31) { | |
167 | cpu_fprintf(f, " SP=%016" PRIx64 "\n", env->xregs[i]); | |
14ade10f | 168 | } else { |
3cb506a3 RH |
169 | cpu_fprintf(f, "X%02d=%016" PRIx64 "%s", i, env->xregs[i], |
170 | (i + 2) % 3 ? " " : "\n"); | |
14ade10f AG |
171 | } |
172 | } | |
06e5cf7a PM |
173 | |
174 | if (arm_feature(env, ARM_FEATURE_EL3) && el != 3) { | |
175 | ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; | |
176 | } else { | |
177 | ns_status = ""; | |
178 | } | |
2bf5f3f9 | 179 | cpu_fprintf(f, "PSTATE=%08x %c%c%c%c %sEL%d%c", |
d356312f PM |
180 | psr, |
181 | psr & PSTATE_N ? 'N' : '-', | |
182 | psr & PSTATE_Z ? 'Z' : '-', | |
183 | psr & PSTATE_C ? 'C' : '-', | |
08b8e0f5 | 184 | psr & PSTATE_V ? 'V' : '-', |
06e5cf7a | 185 | ns_status, |
08b8e0f5 PM |
186 | el, |
187 | psr & PSTATE_SP ? 'h' : 't'); | |
f6d8a314 | 188 | |
f6e52eaa RH |
189 | if (cpu_isar_feature(aa64_bti, cpu)) { |
190 | cpu_fprintf(f, " BTYPE=%d", (psr & PSTATE_BTYPE) >> 10); | |
191 | } | |
2bf5f3f9 RH |
192 | if (!(flags & CPU_DUMP_FPU)) { |
193 | cpu_fprintf(f, "\n"); | |
194 | return; | |
195 | } | |
ced31551 RH |
196 | if (fp_exception_el(env, el) != 0) { |
197 | cpu_fprintf(f, " FPU disabled\n"); | |
198 | return; | |
199 | } | |
2bf5f3f9 RH |
200 | cpu_fprintf(f, " FPCR=%08x FPSR=%08x\n", |
201 | vfp_get_fpcr(env), vfp_get_fpsr(env)); | |
202 | ||
cd208a1c | 203 | if (cpu_isar_feature(aa64_sve, cpu) && sve_exception_el(env, el) == 0) { |
ced31551 | 204 | int j, zcr_len = sve_zcr_len_for_el(env, el); |
2bf5f3f9 RH |
205 | |
206 | for (i = 0; i <= FFR_PRED_NUM; i++) { | |
207 | bool eol; | |
208 | if (i == FFR_PRED_NUM) { | |
209 | cpu_fprintf(f, "FFR="); | |
210 | /* It's last, so end the line. */ | |
211 | eol = true; | |
212 | } else { | |
213 | cpu_fprintf(f, "P%02d=", i); | |
214 | switch (zcr_len) { | |
215 | case 0: | |
216 | eol = i % 8 == 7; | |
217 | break; | |
218 | case 1: | |
219 | eol = i % 6 == 5; | |
220 | break; | |
221 | case 2: | |
222 | case 3: | |
223 | eol = i % 3 == 2; | |
224 | break; | |
225 | default: | |
226 | /* More than one quadword per predicate. */ | |
227 | eol = true; | |
228 | break; | |
229 | } | |
230 | } | |
231 | for (j = zcr_len / 4; j >= 0; j--) { | |
232 | int digits; | |
233 | if (j * 4 + 4 <= zcr_len + 1) { | |
234 | digits = 16; | |
235 | } else { | |
236 | digits = (zcr_len % 4 + 1) * 4; | |
237 | } | |
238 | cpu_fprintf(f, "%0*" PRIx64 "%s", digits, | |
239 | env->vfp.pregs[i].p[j], | |
240 | j ? ":" : eol ? "\n" : " "); | |
241 | } | |
242 | } | |
243 | ||
244 | for (i = 0; i < 32; i++) { | |
245 | if (zcr_len == 0) { | |
246 | cpu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 "%s", | |
247 | i, env->vfp.zregs[i].d[1], | |
248 | env->vfp.zregs[i].d[0], i & 1 ? "\n" : " "); | |
249 | } else if (zcr_len == 1) { | |
250 | cpu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 | |
251 | ":%016" PRIx64 ":%016" PRIx64 "\n", | |
252 | i, env->vfp.zregs[i].d[3], env->vfp.zregs[i].d[2], | |
253 | env->vfp.zregs[i].d[1], env->vfp.zregs[i].d[0]); | |
254 | } else { | |
255 | for (j = zcr_len; j >= 0; j--) { | |
256 | bool odd = (zcr_len - j) % 2 != 0; | |
257 | if (j == zcr_len) { | |
258 | cpu_fprintf(f, "Z%02d[%x-%x]=", i, j, j - 1); | |
259 | } else if (!odd) { | |
260 | if (j > 0) { | |
261 | cpu_fprintf(f, " [%x-%x]=", j, j - 1); | |
262 | } else { | |
263 | cpu_fprintf(f, " [%x]=", j); | |
264 | } | |
265 | } | |
266 | cpu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%s", | |
267 | env->vfp.zregs[i].d[j * 2 + 1], | |
268 | env->vfp.zregs[i].d[j * 2], | |
269 | odd || j == 0 ? "\n" : ":"); | |
270 | } | |
271 | } | |
272 | } | |
273 | } else { | |
274 | for (i = 0; i < 32; i++) { | |
9a2b5256 | 275 | uint64_t *q = aa64_vfp_qreg(env, i); |
2bf5f3f9 RH |
276 | cpu_fprintf(f, "Q%02d=%016" PRIx64 ":%016" PRIx64 "%s", |
277 | i, q[1], q[0], (i & 1 ? "\n" : " ")); | |
f6d8a314 | 278 | } |
f6d8a314 | 279 | } |
14ade10f AG |
280 | } |
281 | ||
282 | void gen_a64_set_pc_im(uint64_t val) | |
283 | { | |
284 | tcg_gen_movi_i64(cpu_pc, val); | |
285 | } | |
286 | ||
4a9ee99d RH |
287 | /* |
288 | * Handle Top Byte Ignore (TBI) bits. | |
6feecb8b | 289 | * |
4a9ee99d | 290 | * If address tagging is enabled via the TCR TBI bits: |
6feecb8b TH |
291 | * + for EL2 and EL3 there is only one TBI bit, and if it is set |
292 | * then the address is zero-extended, clearing bits [63:56] | |
293 | * + for EL0 and EL1, TBI0 controls addresses with bit 55 == 0 | |
294 | * and TBI1 controls addressses with bit 55 == 1. | |
295 | * If the appropriate TBI bit is set for the address then | |
296 | * the address is sign-extended from bit 55 into bits [63:56] | |
297 | * | |
4a9ee99d | 298 | * Here We have concatenated TBI{1,0} into tbi. |
6feecb8b | 299 | */ |
4a9ee99d RH |
300 | static void gen_top_byte_ignore(DisasContext *s, TCGv_i64 dst, |
301 | TCGv_i64 src, int tbi) | |
6feecb8b | 302 | { |
4a9ee99d RH |
303 | if (tbi == 0) { |
304 | /* Load unmodified address */ | |
305 | tcg_gen_mov_i64(dst, src); | |
306 | } else if (s->current_el >= 2) { | |
307 | /* FIXME: ARMv8.1-VHE S2 translation regime. */ | |
308 | /* Force tag byte to all zero */ | |
309 | tcg_gen_extract_i64(dst, src, 0, 56); | |
310 | } else { | |
311 | /* Sign-extend from bit 55. */ | |
312 | tcg_gen_sextract_i64(dst, src, 0, 56); | |
6feecb8b | 313 | |
4a9ee99d RH |
314 | if (tbi != 3) { |
315 | TCGv_i64 tcg_zero = tcg_const_i64(0); | |
6feecb8b | 316 | |
4a9ee99d RH |
317 | /* |
318 | * The two TBI bits differ. | |
319 | * If tbi0, then !tbi1: only use the extension if positive. | |
320 | * if !tbi0, then tbi1: only use the extension if negative. | |
321 | */ | |
322 | tcg_gen_movcond_i64(tbi == 1 ? TCG_COND_GE : TCG_COND_LT, | |
323 | dst, dst, tcg_zero, dst, src); | |
324 | tcg_temp_free_i64(tcg_zero); | |
6feecb8b TH |
325 | } |
326 | } | |
4a9ee99d | 327 | } |
8733d762 | 328 | |
4a9ee99d RH |
329 | static void gen_a64_set_pc(DisasContext *s, TCGv_i64 src) |
330 | { | |
331 | /* | |
332 | * If address tagging is enabled for instructions via the TCR TBI bits, | |
333 | * then loading an address into the PC will clear out any tag. | |
334 | */ | |
335 | gen_top_byte_ignore(s, cpu_pc, src, s->tbii); | |
6feecb8b TH |
336 | } |
337 | ||
3a471103 RH |
338 | /* |
339 | * Return a "clean" address for ADDR according to TBID. | |
340 | * This is always a fresh temporary, as we need to be able to | |
341 | * increment this independently of a dirty write-back address. | |
342 | */ | |
343 | static TCGv_i64 clean_data_tbi(DisasContext *s, TCGv_i64 addr) | |
344 | { | |
345 | TCGv_i64 clean = new_tmp_a64(s); | |
346 | gen_top_byte_ignore(s, clean, addr, s->tbid); | |
347 | return clean; | |
348 | } | |
349 | ||
259cb684 RH |
350 | typedef struct DisasCompare64 { |
351 | TCGCond cond; | |
352 | TCGv_i64 value; | |
353 | } DisasCompare64; | |
354 | ||
355 | static void a64_test_cc(DisasCompare64 *c64, int cc) | |
356 | { | |
357 | DisasCompare c32; | |
358 | ||
359 | arm_test_cc(&c32, cc); | |
360 | ||
361 | /* Sign-extend the 32-bit value so that the GE/LT comparisons work | |
362 | * properly. The NE/EQ comparisons are also fine with this choice. */ | |
363 | c64->cond = c32.cond; | |
364 | c64->value = tcg_temp_new_i64(); | |
365 | tcg_gen_ext_i32_i64(c64->value, c32.value); | |
366 | ||
367 | arm_free_cc(&c32); | |
368 | } | |
369 | ||
370 | static void a64_free_cc(DisasCompare64 *c64) | |
371 | { | |
372 | tcg_temp_free_i64(c64->value); | |
373 | } | |
374 | ||
d4a2dc67 | 375 | static void gen_exception_internal(int excp) |
14ade10f | 376 | { |
d4a2dc67 PM |
377 | TCGv_i32 tcg_excp = tcg_const_i32(excp); |
378 | ||
379 | assert(excp_is_internal(excp)); | |
380 | gen_helper_exception_internal(cpu_env, tcg_excp); | |
381 | tcg_temp_free_i32(tcg_excp); | |
382 | } | |
383 | ||
73710361 | 384 | static void gen_exception(int excp, uint32_t syndrome, uint32_t target_el) |
d4a2dc67 PM |
385 | { |
386 | TCGv_i32 tcg_excp = tcg_const_i32(excp); | |
387 | TCGv_i32 tcg_syn = tcg_const_i32(syndrome); | |
73710361 | 388 | TCGv_i32 tcg_el = tcg_const_i32(target_el); |
d4a2dc67 | 389 | |
73710361 GB |
390 | gen_helper_exception_with_syndrome(cpu_env, tcg_excp, |
391 | tcg_syn, tcg_el); | |
392 | tcg_temp_free_i32(tcg_el); | |
d4a2dc67 PM |
393 | tcg_temp_free_i32(tcg_syn); |
394 | tcg_temp_free_i32(tcg_excp); | |
395 | } | |
396 | ||
397 | static void gen_exception_internal_insn(DisasContext *s, int offset, int excp) | |
398 | { | |
399 | gen_a64_set_pc_im(s->pc - offset); | |
400 | gen_exception_internal(excp); | |
dcba3a8d | 401 | s->base.is_jmp = DISAS_NORETURN; |
14ade10f AG |
402 | } |
403 | ||
d4a2dc67 | 404 | static void gen_exception_insn(DisasContext *s, int offset, int excp, |
73710361 | 405 | uint32_t syndrome, uint32_t target_el) |
14ade10f AG |
406 | { |
407 | gen_a64_set_pc_im(s->pc - offset); | |
73710361 | 408 | gen_exception(excp, syndrome, target_el); |
dcba3a8d | 409 | s->base.is_jmp = DISAS_NORETURN; |
40f860cd PM |
410 | } |
411 | ||
c900a2e6 PM |
412 | static void gen_exception_bkpt_insn(DisasContext *s, int offset, |
413 | uint32_t syndrome) | |
414 | { | |
415 | TCGv_i32 tcg_syn; | |
416 | ||
417 | gen_a64_set_pc_im(s->pc - offset); | |
418 | tcg_syn = tcg_const_i32(syndrome); | |
419 | gen_helper_exception_bkpt_insn(cpu_env, tcg_syn); | |
420 | tcg_temp_free_i32(tcg_syn); | |
421 | s->base.is_jmp = DISAS_NORETURN; | |
422 | } | |
423 | ||
7ea47fe7 PM |
424 | static void gen_ss_advance(DisasContext *s) |
425 | { | |
426 | /* If the singlestep state is Active-not-pending, advance to | |
427 | * Active-pending. | |
428 | */ | |
429 | if (s->ss_active) { | |
430 | s->pstate_ss = 0; | |
431 | gen_helper_clear_pstate_ss(cpu_env); | |
432 | } | |
433 | } | |
434 | ||
435 | static void gen_step_complete_exception(DisasContext *s) | |
436 | { | |
437 | /* We just completed step of an insn. Move from Active-not-pending | |
438 | * to Active-pending, and then also take the swstep exception. | |
439 | * This corresponds to making the (IMPDEF) choice to prioritize | |
440 | * swstep exceptions over asynchronous exceptions taken to an exception | |
441 | * level where debug is disabled. This choice has the advantage that | |
442 | * we do not need to maintain internal state corresponding to the | |
443 | * ISV/EX syndrome bits between completion of the step and generation | |
444 | * of the exception, and our syndrome information is always correct. | |
445 | */ | |
446 | gen_ss_advance(s); | |
73710361 GB |
447 | gen_exception(EXCP_UDEF, syn_swstep(s->ss_same_el, 1, s->is_ldex), |
448 | default_exception_el(s)); | |
dcba3a8d | 449 | s->base.is_jmp = DISAS_NORETURN; |
7ea47fe7 PM |
450 | } |
451 | ||
40f860cd PM |
452 | static inline bool use_goto_tb(DisasContext *s, int n, uint64_t dest) |
453 | { | |
7ea47fe7 PM |
454 | /* No direct tb linking with singlestep (either QEMU's or the ARM |
455 | * debug architecture kind) or deterministic io | |
456 | */ | |
c5a49c63 EC |
457 | if (s->base.singlestep_enabled || s->ss_active || |
458 | (tb_cflags(s->base.tb) & CF_LAST_IO)) { | |
40f860cd PM |
459 | return false; |
460 | } | |
461 | ||
90aa39a1 | 462 | #ifndef CONFIG_USER_ONLY |
40f860cd | 463 | /* Only link tbs from inside the same guest page */ |
dcba3a8d | 464 | if ((s->base.tb->pc & TARGET_PAGE_MASK) != (dest & TARGET_PAGE_MASK)) { |
40f860cd PM |
465 | return false; |
466 | } | |
90aa39a1 | 467 | #endif |
40f860cd PM |
468 | |
469 | return true; | |
470 | } | |
471 | ||
472 | static inline void gen_goto_tb(DisasContext *s, int n, uint64_t dest) | |
473 | { | |
474 | TranslationBlock *tb; | |
475 | ||
dcba3a8d | 476 | tb = s->base.tb; |
40f860cd PM |
477 | if (use_goto_tb(s, n, dest)) { |
478 | tcg_gen_goto_tb(n); | |
479 | gen_a64_set_pc_im(dest); | |
07ea28b4 | 480 | tcg_gen_exit_tb(tb, n); |
dcba3a8d | 481 | s->base.is_jmp = DISAS_NORETURN; |
40f860cd PM |
482 | } else { |
483 | gen_a64_set_pc_im(dest); | |
7ea47fe7 PM |
484 | if (s->ss_active) { |
485 | gen_step_complete_exception(s); | |
dcba3a8d | 486 | } else if (s->base.singlestep_enabled) { |
d4a2dc67 | 487 | gen_exception_internal(EXCP_DEBUG); |
cc9c1ed1 | 488 | } else { |
7f11636d | 489 | tcg_gen_lookup_and_goto_ptr(); |
dcba3a8d | 490 | s->base.is_jmp = DISAS_NORETURN; |
40f860cd | 491 | } |
40f860cd | 492 | } |
14ade10f AG |
493 | } |
494 | ||
8c71baed | 495 | void unallocated_encoding(DisasContext *s) |
14ade10f | 496 | { |
d4a2dc67 | 497 | /* Unallocated and reserved encodings are uncategorized */ |
73710361 GB |
498 | gen_exception_insn(s, 4, EXCP_UDEF, syn_uncategorized(), |
499 | default_exception_el(s)); | |
14ade10f AG |
500 | } |
501 | ||
11e169de AG |
502 | static void init_tmp_a64_array(DisasContext *s) |
503 | { | |
504 | #ifdef CONFIG_DEBUG_TCG | |
f764718d | 505 | memset(s->tmp_a64, 0, sizeof(s->tmp_a64)); |
11e169de AG |
506 | #endif |
507 | s->tmp_a64_count = 0; | |
508 | } | |
509 | ||
510 | static void free_tmp_a64(DisasContext *s) | |
511 | { | |
512 | int i; | |
513 | for (i = 0; i < s->tmp_a64_count; i++) { | |
514 | tcg_temp_free_i64(s->tmp_a64[i]); | |
515 | } | |
516 | init_tmp_a64_array(s); | |
517 | } | |
518 | ||
8c71baed | 519 | TCGv_i64 new_tmp_a64(DisasContext *s) |
11e169de AG |
520 | { |
521 | assert(s->tmp_a64_count < TMP_A64_MAX); | |
522 | return s->tmp_a64[s->tmp_a64_count++] = tcg_temp_new_i64(); | |
523 | } | |
524 | ||
8c71baed | 525 | TCGv_i64 new_tmp_a64_zero(DisasContext *s) |
11e169de AG |
526 | { |
527 | TCGv_i64 t = new_tmp_a64(s); | |
528 | tcg_gen_movi_i64(t, 0); | |
529 | return t; | |
530 | } | |
531 | ||
71b46089 AG |
532 | /* |
533 | * Register access functions | |
534 | * | |
535 | * These functions are used for directly accessing a register in where | |
536 | * changes to the final register value are likely to be made. If you | |
537 | * need to use a register for temporary calculation (e.g. index type | |
538 | * operations) use the read_* form. | |
539 | * | |
540 | * B1.2.1 Register mappings | |
541 | * | |
542 | * In instruction register encoding 31 can refer to ZR (zero register) or | |
543 | * the SP (stack pointer) depending on context. In QEMU's case we map SP | |
544 | * to cpu_X[31] and ZR accesses to a temporary which can be discarded. | |
545 | * This is the point of the _sp forms. | |
546 | */ | |
8c71baed | 547 | TCGv_i64 cpu_reg(DisasContext *s, int reg) |
11e169de AG |
548 | { |
549 | if (reg == 31) { | |
550 | return new_tmp_a64_zero(s); | |
551 | } else { | |
552 | return cpu_X[reg]; | |
553 | } | |
554 | } | |
555 | ||
71b46089 | 556 | /* register access for when 31 == SP */ |
8c71baed | 557 | TCGv_i64 cpu_reg_sp(DisasContext *s, int reg) |
71b46089 AG |
558 | { |
559 | return cpu_X[reg]; | |
560 | } | |
561 | ||
60e53388 AG |
562 | /* read a cpu register in 32bit/64bit mode. Returns a TCGv_i64 |
563 | * representing the register contents. This TCGv is an auto-freed | |
564 | * temporary so it need not be explicitly freed, and may be modified. | |
565 | */ | |
8c71baed | 566 | TCGv_i64 read_cpu_reg(DisasContext *s, int reg, int sf) |
60e53388 AG |
567 | { |
568 | TCGv_i64 v = new_tmp_a64(s); | |
569 | if (reg != 31) { | |
570 | if (sf) { | |
571 | tcg_gen_mov_i64(v, cpu_X[reg]); | |
572 | } else { | |
573 | tcg_gen_ext32u_i64(v, cpu_X[reg]); | |
574 | } | |
575 | } else { | |
576 | tcg_gen_movi_i64(v, 0); | |
577 | } | |
578 | return v; | |
579 | } | |
580 | ||
8c71baed | 581 | TCGv_i64 read_cpu_reg_sp(DisasContext *s, int reg, int sf) |
4a08d475 PM |
582 | { |
583 | TCGv_i64 v = new_tmp_a64(s); | |
584 | if (sf) { | |
585 | tcg_gen_mov_i64(v, cpu_X[reg]); | |
586 | } else { | |
587 | tcg_gen_ext32u_i64(v, cpu_X[reg]); | |
588 | } | |
589 | return v; | |
590 | } | |
591 | ||
e2f90565 PM |
592 | /* Return the offset into CPUARMState of a slice (from |
593 | * the least significant end) of FP register Qn (ie | |
594 | * Dn, Sn, Hn or Bn). | |
595 | * (Note that this is not the same mapping as for A32; see cpu.h) | |
596 | */ | |
90e49638 | 597 | static inline int fp_reg_offset(DisasContext *s, int regno, TCGMemOp size) |
e2f90565 | 598 | { |
9a2b5256 | 599 | return vec_reg_offset(s, regno, 0, size); |
e2f90565 PM |
600 | } |
601 | ||
602 | /* Offset of the high half of the 128 bit vector Qn */ | |
90e49638 | 603 | static inline int fp_reg_hi_offset(DisasContext *s, int regno) |
e2f90565 | 604 | { |
9a2b5256 | 605 | return vec_reg_offset(s, regno, 1, MO_64); |
e2f90565 PM |
606 | } |
607 | ||
ec73d2e0 AG |
608 | /* Convenience accessors for reading and writing single and double |
609 | * FP registers. Writing clears the upper parts of the associated | |
610 | * 128 bit vector register, as required by the architecture. | |
611 | * Note that unlike the GP register accessors, the values returned | |
612 | * by the read functions must be manually freed. | |
613 | */ | |
614 | static TCGv_i64 read_fp_dreg(DisasContext *s, int reg) | |
615 | { | |
616 | TCGv_i64 v = tcg_temp_new_i64(); | |
617 | ||
90e49638 | 618 | tcg_gen_ld_i64(v, cpu_env, fp_reg_offset(s, reg, MO_64)); |
ec73d2e0 AG |
619 | return v; |
620 | } | |
621 | ||
622 | static TCGv_i32 read_fp_sreg(DisasContext *s, int reg) | |
623 | { | |
624 | TCGv_i32 v = tcg_temp_new_i32(); | |
625 | ||
90e49638 | 626 | tcg_gen_ld_i32(v, cpu_env, fp_reg_offset(s, reg, MO_32)); |
ec73d2e0 AG |
627 | return v; |
628 | } | |
629 | ||
3d99d931 RH |
630 | static TCGv_i32 read_fp_hreg(DisasContext *s, int reg) |
631 | { | |
632 | TCGv_i32 v = tcg_temp_new_i32(); | |
633 | ||
634 | tcg_gen_ld16u_i32(v, cpu_env, fp_reg_offset(s, reg, MO_16)); | |
635 | return v; | |
636 | } | |
637 | ||
4ff55bcb RH |
638 | /* Clear the bits above an N-bit vector, for N = (is_q ? 128 : 64). |
639 | * If SVE is not enabled, then there are only 128 bits in the vector. | |
640 | */ | |
641 | static void clear_vec_high(DisasContext *s, bool is_q, int rd) | |
642 | { | |
643 | unsigned ofs = fp_reg_offset(s, rd, MO_64); | |
644 | unsigned vsz = vec_full_reg_size(s); | |
645 | ||
646 | if (!is_q) { | |
647 | TCGv_i64 tcg_zero = tcg_const_i64(0); | |
648 | tcg_gen_st_i64(tcg_zero, cpu_env, ofs + 8); | |
649 | tcg_temp_free_i64(tcg_zero); | |
650 | } | |
651 | if (vsz > 16) { | |
652 | tcg_gen_gvec_dup8i(ofs + 16, vsz - 16, vsz - 16, 0); | |
653 | } | |
654 | } | |
655 | ||
8c71baed | 656 | void write_fp_dreg(DisasContext *s, int reg, TCGv_i64 v) |
ec73d2e0 | 657 | { |
4ff55bcb | 658 | unsigned ofs = fp_reg_offset(s, reg, MO_64); |
ec73d2e0 | 659 | |
4ff55bcb RH |
660 | tcg_gen_st_i64(v, cpu_env, ofs); |
661 | clear_vec_high(s, false, reg); | |
ec73d2e0 AG |
662 | } |
663 | ||
664 | static void write_fp_sreg(DisasContext *s, int reg, TCGv_i32 v) | |
665 | { | |
666 | TCGv_i64 tmp = tcg_temp_new_i64(); | |
667 | ||
668 | tcg_gen_extu_i32_i64(tmp, v); | |
669 | write_fp_dreg(s, reg, tmp); | |
670 | tcg_temp_free_i64(tmp); | |
671 | } | |
672 | ||
8c71baed | 673 | TCGv_ptr get_fpstatus_ptr(bool is_f16) |
ec73d2e0 AG |
674 | { |
675 | TCGv_ptr statusptr = tcg_temp_new_ptr(); | |
676 | int offset; | |
677 | ||
d81ce0ef AB |
678 | /* In A64 all instructions (both FP and Neon) use the FPCR; there |
679 | * is no equivalent of the A32 Neon "standard FPSCR value". | |
680 | * However half-precision operations operate under a different | |
681 | * FZ16 flag and use vfp.fp_status_f16 instead of vfp.fp_status. | |
ec73d2e0 | 682 | */ |
d81ce0ef AB |
683 | if (is_f16) { |
684 | offset = offsetof(CPUARMState, vfp.fp_status_f16); | |
685 | } else { | |
686 | offset = offsetof(CPUARMState, vfp.fp_status); | |
687 | } | |
ec73d2e0 AG |
688 | tcg_gen_addi_ptr(statusptr, cpu_env, offset); |
689 | return statusptr; | |
690 | } | |
691 | ||
377ef731 RH |
692 | /* Expand a 2-operand AdvSIMD vector operation using an expander function. */ |
693 | static void gen_gvec_fn2(DisasContext *s, bool is_q, int rd, int rn, | |
694 | GVecGen2Fn *gvec_fn, int vece) | |
695 | { | |
696 | gvec_fn(vece, vec_full_reg_offset(s, rd), vec_full_reg_offset(s, rn), | |
697 | is_q ? 16 : 8, vec_full_reg_size(s)); | |
698 | } | |
699 | ||
cdb45a60 RH |
700 | /* Expand a 2-operand + immediate AdvSIMD vector operation using |
701 | * an expander function. | |
702 | */ | |
703 | static void gen_gvec_fn2i(DisasContext *s, bool is_q, int rd, int rn, | |
704 | int64_t imm, GVecGen2iFn *gvec_fn, int vece) | |
705 | { | |
706 | gvec_fn(vece, vec_full_reg_offset(s, rd), vec_full_reg_offset(s, rn), | |
707 | imm, is_q ? 16 : 8, vec_full_reg_size(s)); | |
708 | } | |
709 | ||
bc48092f RH |
710 | /* Expand a 3-operand AdvSIMD vector operation using an expander function. */ |
711 | static void gen_gvec_fn3(DisasContext *s, bool is_q, int rd, int rn, int rm, | |
712 | GVecGen3Fn *gvec_fn, int vece) | |
713 | { | |
714 | gvec_fn(vece, vec_full_reg_offset(s, rd), vec_full_reg_offset(s, rn), | |
715 | vec_full_reg_offset(s, rm), is_q ? 16 : 8, vec_full_reg_size(s)); | |
716 | } | |
717 | ||
cdb45a60 RH |
718 | /* Expand a 2-operand + immediate AdvSIMD vector operation using |
719 | * an op descriptor. | |
720 | */ | |
721 | static void gen_gvec_op2i(DisasContext *s, bool is_q, int rd, | |
722 | int rn, int64_t imm, const GVecGen2i *gvec_op) | |
723 | { | |
724 | tcg_gen_gvec_2i(vec_full_reg_offset(s, rd), vec_full_reg_offset(s, rn), | |
725 | is_q ? 16 : 8, vec_full_reg_size(s), imm, gvec_op); | |
726 | } | |
727 | ||
bc48092f RH |
728 | /* Expand a 3-operand AdvSIMD vector operation using an op descriptor. */ |
729 | static void gen_gvec_op3(DisasContext *s, bool is_q, int rd, | |
730 | int rn, int rm, const GVecGen3 *gvec_op) | |
731 | { | |
732 | tcg_gen_gvec_3(vec_full_reg_offset(s, rd), vec_full_reg_offset(s, rn), | |
733 | vec_full_reg_offset(s, rm), is_q ? 16 : 8, | |
734 | vec_full_reg_size(s), gvec_op); | |
735 | } | |
736 | ||
26c470a7 RH |
737 | /* Expand a 3-operand operation using an out-of-line helper. */ |
738 | static void gen_gvec_op3_ool(DisasContext *s, bool is_q, int rd, | |
739 | int rn, int rm, int data, gen_helper_gvec_3 *fn) | |
740 | { | |
741 | tcg_gen_gvec_3_ool(vec_full_reg_offset(s, rd), | |
742 | vec_full_reg_offset(s, rn), | |
743 | vec_full_reg_offset(s, rm), | |
744 | is_q ? 16 : 8, vec_full_reg_size(s), data, fn); | |
745 | } | |
746 | ||
e7186d82 RH |
747 | /* Expand a 3-operand + env pointer operation using |
748 | * an out-of-line helper. | |
749 | */ | |
750 | static void gen_gvec_op3_env(DisasContext *s, bool is_q, int rd, | |
751 | int rn, int rm, gen_helper_gvec_3_ptr *fn) | |
752 | { | |
753 | tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd), | |
754 | vec_full_reg_offset(s, rn), | |
755 | vec_full_reg_offset(s, rm), cpu_env, | |
756 | is_q ? 16 : 8, vec_full_reg_size(s), 0, fn); | |
757 | } | |
758 | ||
1695cd61 RH |
759 | /* Expand a 3-operand + fpstatus pointer + simd data value operation using |
760 | * an out-of-line helper. | |
761 | */ | |
762 | static void gen_gvec_op3_fpst(DisasContext *s, bool is_q, int rd, int rn, | |
763 | int rm, bool is_fp16, int data, | |
764 | gen_helper_gvec_3_ptr *fn) | |
765 | { | |
766 | TCGv_ptr fpst = get_fpstatus_ptr(is_fp16); | |
767 | tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd), | |
768 | vec_full_reg_offset(s, rn), | |
769 | vec_full_reg_offset(s, rm), fpst, | |
770 | is_q ? 16 : 8, vec_full_reg_size(s), data, fn); | |
771 | tcg_temp_free_ptr(fpst); | |
772 | } | |
773 | ||
832ffa1c AG |
774 | /* Set ZF and NF based on a 64 bit result. This is alas fiddlier |
775 | * than the 32 bit equivalent. | |
776 | */ | |
777 | static inline void gen_set_NZ64(TCGv_i64 result) | |
778 | { | |
7cb36e18 RH |
779 | tcg_gen_extr_i64_i32(cpu_ZF, cpu_NF, result); |
780 | tcg_gen_or_i32(cpu_ZF, cpu_ZF, cpu_NF); | |
832ffa1c AG |
781 | } |
782 | ||
783 | /* Set NZCV as for a logical operation: NZ as per result, CV cleared. */ | |
784 | static inline void gen_logic_CC(int sf, TCGv_i64 result) | |
785 | { | |
786 | if (sf) { | |
787 | gen_set_NZ64(result); | |
788 | } else { | |
ecc7b3aa | 789 | tcg_gen_extrl_i64_i32(cpu_ZF, result); |
7cb36e18 | 790 | tcg_gen_mov_i32(cpu_NF, cpu_ZF); |
832ffa1c AG |
791 | } |
792 | tcg_gen_movi_i32(cpu_CF, 0); | |
793 | tcg_gen_movi_i32(cpu_VF, 0); | |
794 | } | |
795 | ||
b0ff21b4 AB |
796 | /* dest = T0 + T1; compute C, N, V and Z flags */ |
797 | static void gen_add_CC(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1) | |
798 | { | |
799 | if (sf) { | |
800 | TCGv_i64 result, flag, tmp; | |
801 | result = tcg_temp_new_i64(); | |
802 | flag = tcg_temp_new_i64(); | |
803 | tmp = tcg_temp_new_i64(); | |
804 | ||
805 | tcg_gen_movi_i64(tmp, 0); | |
806 | tcg_gen_add2_i64(result, flag, t0, tmp, t1, tmp); | |
807 | ||
ecc7b3aa | 808 | tcg_gen_extrl_i64_i32(cpu_CF, flag); |
b0ff21b4 AB |
809 | |
810 | gen_set_NZ64(result); | |
811 | ||
812 | tcg_gen_xor_i64(flag, result, t0); | |
813 | tcg_gen_xor_i64(tmp, t0, t1); | |
814 | tcg_gen_andc_i64(flag, flag, tmp); | |
815 | tcg_temp_free_i64(tmp); | |
7cb36e18 | 816 | tcg_gen_extrh_i64_i32(cpu_VF, flag); |
b0ff21b4 AB |
817 | |
818 | tcg_gen_mov_i64(dest, result); | |
819 | tcg_temp_free_i64(result); | |
820 | tcg_temp_free_i64(flag); | |
821 | } else { | |
822 | /* 32 bit arithmetic */ | |
823 | TCGv_i32 t0_32 = tcg_temp_new_i32(); | |
824 | TCGv_i32 t1_32 = tcg_temp_new_i32(); | |
825 | TCGv_i32 tmp = tcg_temp_new_i32(); | |
826 | ||
827 | tcg_gen_movi_i32(tmp, 0); | |
ecc7b3aa RH |
828 | tcg_gen_extrl_i64_i32(t0_32, t0); |
829 | tcg_gen_extrl_i64_i32(t1_32, t1); | |
b0ff21b4 AB |
830 | tcg_gen_add2_i32(cpu_NF, cpu_CF, t0_32, tmp, t1_32, tmp); |
831 | tcg_gen_mov_i32(cpu_ZF, cpu_NF); | |
832 | tcg_gen_xor_i32(cpu_VF, cpu_NF, t0_32); | |
833 | tcg_gen_xor_i32(tmp, t0_32, t1_32); | |
834 | tcg_gen_andc_i32(cpu_VF, cpu_VF, tmp); | |
835 | tcg_gen_extu_i32_i64(dest, cpu_NF); | |
836 | ||
837 | tcg_temp_free_i32(tmp); | |
838 | tcg_temp_free_i32(t0_32); | |
839 | tcg_temp_free_i32(t1_32); | |
840 | } | |
841 | } | |
842 | ||
843 | /* dest = T0 - T1; compute C, N, V and Z flags */ | |
844 | static void gen_sub_CC(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1) | |
845 | { | |
846 | if (sf) { | |
847 | /* 64 bit arithmetic */ | |
848 | TCGv_i64 result, flag, tmp; | |
849 | ||
850 | result = tcg_temp_new_i64(); | |
851 | flag = tcg_temp_new_i64(); | |
852 | tcg_gen_sub_i64(result, t0, t1); | |
853 | ||
854 | gen_set_NZ64(result); | |
855 | ||
856 | tcg_gen_setcond_i64(TCG_COND_GEU, flag, t0, t1); | |
ecc7b3aa | 857 | tcg_gen_extrl_i64_i32(cpu_CF, flag); |
b0ff21b4 AB |
858 | |
859 | tcg_gen_xor_i64(flag, result, t0); | |
860 | tmp = tcg_temp_new_i64(); | |
861 | tcg_gen_xor_i64(tmp, t0, t1); | |
862 | tcg_gen_and_i64(flag, flag, tmp); | |
863 | tcg_temp_free_i64(tmp); | |
7cb36e18 | 864 | tcg_gen_extrh_i64_i32(cpu_VF, flag); |
b0ff21b4 AB |
865 | tcg_gen_mov_i64(dest, result); |
866 | tcg_temp_free_i64(flag); | |
867 | tcg_temp_free_i64(result); | |
868 | } else { | |
869 | /* 32 bit arithmetic */ | |
870 | TCGv_i32 t0_32 = tcg_temp_new_i32(); | |
871 | TCGv_i32 t1_32 = tcg_temp_new_i32(); | |
872 | TCGv_i32 tmp; | |
873 | ||
ecc7b3aa RH |
874 | tcg_gen_extrl_i64_i32(t0_32, t0); |
875 | tcg_gen_extrl_i64_i32(t1_32, t1); | |
b0ff21b4 AB |
876 | tcg_gen_sub_i32(cpu_NF, t0_32, t1_32); |
877 | tcg_gen_mov_i32(cpu_ZF, cpu_NF); | |
878 | tcg_gen_setcond_i32(TCG_COND_GEU, cpu_CF, t0_32, t1_32); | |
879 | tcg_gen_xor_i32(cpu_VF, cpu_NF, t0_32); | |
880 | tmp = tcg_temp_new_i32(); | |
881 | tcg_gen_xor_i32(tmp, t0_32, t1_32); | |
882 | tcg_temp_free_i32(t0_32); | |
883 | tcg_temp_free_i32(t1_32); | |
884 | tcg_gen_and_i32(cpu_VF, cpu_VF, tmp); | |
885 | tcg_temp_free_i32(tmp); | |
886 | tcg_gen_extu_i32_i64(dest, cpu_NF); | |
887 | } | |
888 | } | |
889 | ||
643dbb07 CF |
890 | /* dest = T0 + T1 + CF; do not compute flags. */ |
891 | static void gen_adc(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1) | |
892 | { | |
893 | TCGv_i64 flag = tcg_temp_new_i64(); | |
894 | tcg_gen_extu_i32_i64(flag, cpu_CF); | |
895 | tcg_gen_add_i64(dest, t0, t1); | |
896 | tcg_gen_add_i64(dest, dest, flag); | |
897 | tcg_temp_free_i64(flag); | |
898 | ||
899 | if (!sf) { | |
900 | tcg_gen_ext32u_i64(dest, dest); | |
901 | } | |
902 | } | |
903 | ||
904 | /* dest = T0 + T1 + CF; compute C, N, V and Z flags. */ | |
905 | static void gen_adc_CC(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1) | |
906 | { | |
907 | if (sf) { | |
908 | TCGv_i64 result, cf_64, vf_64, tmp; | |
909 | result = tcg_temp_new_i64(); | |
910 | cf_64 = tcg_temp_new_i64(); | |
911 | vf_64 = tcg_temp_new_i64(); | |
912 | tmp = tcg_const_i64(0); | |
913 | ||
914 | tcg_gen_extu_i32_i64(cf_64, cpu_CF); | |
915 | tcg_gen_add2_i64(result, cf_64, t0, tmp, cf_64, tmp); | |
916 | tcg_gen_add2_i64(result, cf_64, result, cf_64, t1, tmp); | |
ecc7b3aa | 917 | tcg_gen_extrl_i64_i32(cpu_CF, cf_64); |
643dbb07 CF |
918 | gen_set_NZ64(result); |
919 | ||
920 | tcg_gen_xor_i64(vf_64, result, t0); | |
921 | tcg_gen_xor_i64(tmp, t0, t1); | |
922 | tcg_gen_andc_i64(vf_64, vf_64, tmp); | |
7cb36e18 | 923 | tcg_gen_extrh_i64_i32(cpu_VF, vf_64); |
643dbb07 CF |
924 | |
925 | tcg_gen_mov_i64(dest, result); | |
926 | ||
927 | tcg_temp_free_i64(tmp); | |
928 | tcg_temp_free_i64(vf_64); | |
929 | tcg_temp_free_i64(cf_64); | |
930 | tcg_temp_free_i64(result); | |
931 | } else { | |
932 | TCGv_i32 t0_32, t1_32, tmp; | |
933 | t0_32 = tcg_temp_new_i32(); | |
934 | t1_32 = tcg_temp_new_i32(); | |
935 | tmp = tcg_const_i32(0); | |
936 | ||
ecc7b3aa RH |
937 | tcg_gen_extrl_i64_i32(t0_32, t0); |
938 | tcg_gen_extrl_i64_i32(t1_32, t1); | |
643dbb07 CF |
939 | tcg_gen_add2_i32(cpu_NF, cpu_CF, t0_32, tmp, cpu_CF, tmp); |
940 | tcg_gen_add2_i32(cpu_NF, cpu_CF, cpu_NF, cpu_CF, t1_32, tmp); | |
941 | ||
942 | tcg_gen_mov_i32(cpu_ZF, cpu_NF); | |
943 | tcg_gen_xor_i32(cpu_VF, cpu_NF, t0_32); | |
944 | tcg_gen_xor_i32(tmp, t0_32, t1_32); | |
945 | tcg_gen_andc_i32(cpu_VF, cpu_VF, tmp); | |
946 | tcg_gen_extu_i32_i64(dest, cpu_NF); | |
947 | ||
948 | tcg_temp_free_i32(tmp); | |
949 | tcg_temp_free_i32(t1_32); | |
950 | tcg_temp_free_i32(t0_32); | |
951 | } | |
952 | } | |
953 | ||
4a08d475 PM |
954 | /* |
955 | * Load/Store generators | |
956 | */ | |
957 | ||
958 | /* | |
60510aed | 959 | * Store from GPR register to memory. |
4a08d475 | 960 | */ |
60510aed | 961 | static void do_gpr_st_memidx(DisasContext *s, TCGv_i64 source, |
aaa1f954 EI |
962 | TCGv_i64 tcg_addr, int size, int memidx, |
963 | bool iss_valid, | |
964 | unsigned int iss_srt, | |
965 | bool iss_sf, bool iss_ar) | |
60510aed PM |
966 | { |
967 | g_assert(size <= 3); | |
aa6489da | 968 | tcg_gen_qemu_st_i64(source, tcg_addr, memidx, s->be_data + size); |
aaa1f954 EI |
969 | |
970 | if (iss_valid) { | |
971 | uint32_t syn; | |
972 | ||
973 | syn = syn_data_abort_with_iss(0, | |
974 | size, | |
975 | false, | |
976 | iss_srt, | |
977 | iss_sf, | |
978 | iss_ar, | |
979 | 0, 0, 0, 0, 0, false); | |
980 | disas_set_insn_syndrome(s, syn); | |
981 | } | |
60510aed PM |
982 | } |
983 | ||
4a08d475 | 984 | static void do_gpr_st(DisasContext *s, TCGv_i64 source, |
aaa1f954 EI |
985 | TCGv_i64 tcg_addr, int size, |
986 | bool iss_valid, | |
987 | unsigned int iss_srt, | |
988 | bool iss_sf, bool iss_ar) | |
4a08d475 | 989 | { |
aaa1f954 EI |
990 | do_gpr_st_memidx(s, source, tcg_addr, size, get_mem_index(s), |
991 | iss_valid, iss_srt, iss_sf, iss_ar); | |
4a08d475 PM |
992 | } |
993 | ||
994 | /* | |
995 | * Load from memory to GPR register | |
996 | */ | |
aaa1f954 EI |
997 | static void do_gpr_ld_memidx(DisasContext *s, |
998 | TCGv_i64 dest, TCGv_i64 tcg_addr, | |
999 | int size, bool is_signed, | |
1000 | bool extend, int memidx, | |
1001 | bool iss_valid, unsigned int iss_srt, | |
1002 | bool iss_sf, bool iss_ar) | |
4a08d475 | 1003 | { |
aa6489da | 1004 | TCGMemOp memop = s->be_data + size; |
4a08d475 PM |
1005 | |
1006 | g_assert(size <= 3); | |
1007 | ||
1008 | if (is_signed) { | |
1009 | memop += MO_SIGN; | |
1010 | } | |
1011 | ||
60510aed | 1012 | tcg_gen_qemu_ld_i64(dest, tcg_addr, memidx, memop); |
4a08d475 PM |
1013 | |
1014 | if (extend && is_signed) { | |
1015 | g_assert(size < 3); | |
1016 | tcg_gen_ext32u_i64(dest, dest); | |
1017 | } | |
aaa1f954 EI |
1018 | |
1019 | if (iss_valid) { | |
1020 | uint32_t syn; | |
1021 | ||
1022 | syn = syn_data_abort_with_iss(0, | |
1023 | size, | |
1024 | is_signed, | |
1025 | iss_srt, | |
1026 | iss_sf, | |
1027 | iss_ar, | |
1028 | 0, 0, 0, 0, 0, false); | |
1029 | disas_set_insn_syndrome(s, syn); | |
1030 | } | |
4a08d475 PM |
1031 | } |
1032 | ||
aaa1f954 EI |
1033 | static void do_gpr_ld(DisasContext *s, |
1034 | TCGv_i64 dest, TCGv_i64 tcg_addr, | |
1035 | int size, bool is_signed, bool extend, | |
1036 | bool iss_valid, unsigned int iss_srt, | |
1037 | bool iss_sf, bool iss_ar) | |
60510aed PM |
1038 | { |
1039 | do_gpr_ld_memidx(s, dest, tcg_addr, size, is_signed, extend, | |
aaa1f954 EI |
1040 | get_mem_index(s), |
1041 | iss_valid, iss_srt, iss_sf, iss_ar); | |
60510aed PM |
1042 | } |
1043 | ||
4a08d475 PM |
1044 | /* |
1045 | * Store from FP register to memory | |
1046 | */ | |
1047 | static void do_fp_st(DisasContext *s, int srcidx, TCGv_i64 tcg_addr, int size) | |
1048 | { | |
1049 | /* This writes the bottom N bits of a 128 bit wide vector to memory */ | |
4a08d475 | 1050 | TCGv_i64 tmp = tcg_temp_new_i64(); |
90e49638 | 1051 | tcg_gen_ld_i64(tmp, cpu_env, fp_reg_offset(s, srcidx, MO_64)); |
4a08d475 | 1052 | if (size < 4) { |
aa6489da PC |
1053 | tcg_gen_qemu_st_i64(tmp, tcg_addr, get_mem_index(s), |
1054 | s->be_data + size); | |
4a08d475 | 1055 | } else { |
aa6489da | 1056 | bool be = s->be_data == MO_BE; |
4a08d475 | 1057 | TCGv_i64 tcg_hiaddr = tcg_temp_new_i64(); |
aa6489da | 1058 | |
4a08d475 | 1059 | tcg_gen_addi_i64(tcg_hiaddr, tcg_addr, 8); |
aa6489da PC |
1060 | tcg_gen_qemu_st_i64(tmp, be ? tcg_hiaddr : tcg_addr, get_mem_index(s), |
1061 | s->be_data | MO_Q); | |
1062 | tcg_gen_ld_i64(tmp, cpu_env, fp_reg_hi_offset(s, srcidx)); | |
1063 | tcg_gen_qemu_st_i64(tmp, be ? tcg_addr : tcg_hiaddr, get_mem_index(s), | |
1064 | s->be_data | MO_Q); | |
4a08d475 PM |
1065 | tcg_temp_free_i64(tcg_hiaddr); |
1066 | } | |
1067 | ||
1068 | tcg_temp_free_i64(tmp); | |
1069 | } | |
1070 | ||
1071 | /* | |
1072 | * Load from memory to FP register | |
1073 | */ | |
1074 | static void do_fp_ld(DisasContext *s, int destidx, TCGv_i64 tcg_addr, int size) | |
1075 | { | |
1076 | /* This always zero-extends and writes to a full 128 bit wide vector */ | |
4a08d475 PM |
1077 | TCGv_i64 tmplo = tcg_temp_new_i64(); |
1078 | TCGv_i64 tmphi; | |
1079 | ||
1080 | if (size < 4) { | |
aa6489da | 1081 | TCGMemOp memop = s->be_data + size; |
4a08d475 PM |
1082 | tmphi = tcg_const_i64(0); |
1083 | tcg_gen_qemu_ld_i64(tmplo, tcg_addr, get_mem_index(s), memop); | |
1084 | } else { | |
aa6489da | 1085 | bool be = s->be_data == MO_BE; |
4a08d475 | 1086 | TCGv_i64 tcg_hiaddr; |
aa6489da | 1087 | |
4a08d475 PM |
1088 | tmphi = tcg_temp_new_i64(); |
1089 | tcg_hiaddr = tcg_temp_new_i64(); | |
1090 | ||
4a08d475 | 1091 | tcg_gen_addi_i64(tcg_hiaddr, tcg_addr, 8); |
aa6489da PC |
1092 | tcg_gen_qemu_ld_i64(tmplo, be ? tcg_hiaddr : tcg_addr, get_mem_index(s), |
1093 | s->be_data | MO_Q); | |
1094 | tcg_gen_qemu_ld_i64(tmphi, be ? tcg_addr : tcg_hiaddr, get_mem_index(s), | |
1095 | s->be_data | MO_Q); | |
4a08d475 PM |
1096 | tcg_temp_free_i64(tcg_hiaddr); |
1097 | } | |
1098 | ||
90e49638 PM |
1099 | tcg_gen_st_i64(tmplo, cpu_env, fp_reg_offset(s, destidx, MO_64)); |
1100 | tcg_gen_st_i64(tmphi, cpu_env, fp_reg_hi_offset(s, destidx)); | |
4a08d475 PM |
1101 | |
1102 | tcg_temp_free_i64(tmplo); | |
1103 | tcg_temp_free_i64(tmphi); | |
4ff55bcb RH |
1104 | |
1105 | clear_vec_high(s, true, destidx); | |
4a08d475 PM |
1106 | } |
1107 | ||
72430bf5 AB |
1108 | /* |
1109 | * Vector load/store helpers. | |
1110 | * | |
1111 | * The principal difference between this and a FP load is that we don't | |
1112 | * zero extend as we are filling a partial chunk of the vector register. | |
1113 | * These functions don't support 128 bit loads/stores, which would be | |
1114 | * normal load/store operations. | |
a08582f4 PM |
1115 | * |
1116 | * The _i32 versions are useful when operating on 32 bit quantities | |
1117 | * (eg for floating point single or using Neon helper functions). | |
72430bf5 AB |
1118 | */ |
1119 | ||
1120 | /* Get value of an element within a vector register */ | |
1121 | static void read_vec_element(DisasContext *s, TCGv_i64 tcg_dest, int srcidx, | |
1122 | int element, TCGMemOp memop) | |
1123 | { | |
90e49638 | 1124 | int vect_off = vec_reg_offset(s, srcidx, element, memop & MO_SIZE); |
72430bf5 AB |
1125 | switch (memop) { |
1126 | case MO_8: | |
1127 | tcg_gen_ld8u_i64(tcg_dest, cpu_env, vect_off); | |
1128 | break; | |
1129 | case MO_16: | |
1130 | tcg_gen_ld16u_i64(tcg_dest, cpu_env, vect_off); | |
1131 | break; | |
1132 | case MO_32: | |
1133 | tcg_gen_ld32u_i64(tcg_dest, cpu_env, vect_off); | |
1134 | break; | |
1135 | case MO_8|MO_SIGN: | |
1136 | tcg_gen_ld8s_i64(tcg_dest, cpu_env, vect_off); | |
1137 | break; | |
1138 | case MO_16|MO_SIGN: | |
1139 | tcg_gen_ld16s_i64(tcg_dest, cpu_env, vect_off); | |
1140 | break; | |
1141 | case MO_32|MO_SIGN: | |
1142 | tcg_gen_ld32s_i64(tcg_dest, cpu_env, vect_off); | |
1143 | break; | |
1144 | case MO_64: | |
1145 | case MO_64|MO_SIGN: | |
1146 | tcg_gen_ld_i64(tcg_dest, cpu_env, vect_off); | |
1147 | break; | |
1148 | default: | |
1149 | g_assert_not_reached(); | |
1150 | } | |
1151 | } | |
1152 | ||
a08582f4 PM |
1153 | static void read_vec_element_i32(DisasContext *s, TCGv_i32 tcg_dest, int srcidx, |
1154 | int element, TCGMemOp memop) | |
1155 | { | |
90e49638 | 1156 | int vect_off = vec_reg_offset(s, srcidx, element, memop & MO_SIZE); |
a08582f4 PM |
1157 | switch (memop) { |
1158 | case MO_8: | |
1159 | tcg_gen_ld8u_i32(tcg_dest, cpu_env, vect_off); | |
1160 | break; | |
1161 | case MO_16: | |
1162 | tcg_gen_ld16u_i32(tcg_dest, cpu_env, vect_off); | |
1163 | break; | |
1164 | case MO_8|MO_SIGN: | |
1165 | tcg_gen_ld8s_i32(tcg_dest, cpu_env, vect_off); | |
1166 | break; | |
1167 | case MO_16|MO_SIGN: | |
1168 | tcg_gen_ld16s_i32(tcg_dest, cpu_env, vect_off); | |
1169 | break; | |
1170 | case MO_32: | |
1171 | case MO_32|MO_SIGN: | |
1172 | tcg_gen_ld_i32(tcg_dest, cpu_env, vect_off); | |
1173 | break; | |
1174 | default: | |
1175 | g_assert_not_reached(); | |
1176 | } | |
1177 | } | |
1178 | ||
72430bf5 AB |
1179 | /* Set value of an element within a vector register */ |
1180 | static void write_vec_element(DisasContext *s, TCGv_i64 tcg_src, int destidx, | |
1181 | int element, TCGMemOp memop) | |
1182 | { | |
90e49638 | 1183 | int vect_off = vec_reg_offset(s, destidx, element, memop & MO_SIZE); |
72430bf5 AB |
1184 | switch (memop) { |
1185 | case MO_8: | |
1186 | tcg_gen_st8_i64(tcg_src, cpu_env, vect_off); | |
1187 | break; | |
1188 | case MO_16: | |
1189 | tcg_gen_st16_i64(tcg_src, cpu_env, vect_off); | |
1190 | break; | |
1191 | case MO_32: | |
1192 | tcg_gen_st32_i64(tcg_src, cpu_env, vect_off); | |
1193 | break; | |
1194 | case MO_64: | |
1195 | tcg_gen_st_i64(tcg_src, cpu_env, vect_off); | |
1196 | break; | |
1197 | default: | |
1198 | g_assert_not_reached(); | |
1199 | } | |
1200 | } | |
1201 | ||
1f8a73af PM |
1202 | static void write_vec_element_i32(DisasContext *s, TCGv_i32 tcg_src, |
1203 | int destidx, int element, TCGMemOp memop) | |
1204 | { | |
90e49638 | 1205 | int vect_off = vec_reg_offset(s, destidx, element, memop & MO_SIZE); |
1f8a73af PM |
1206 | switch (memop) { |
1207 | case MO_8: | |
1208 | tcg_gen_st8_i32(tcg_src, cpu_env, vect_off); | |
1209 | break; | |
1210 | case MO_16: | |
1211 | tcg_gen_st16_i32(tcg_src, cpu_env, vect_off); | |
1212 | break; | |
1213 | case MO_32: | |
1214 | tcg_gen_st_i32(tcg_src, cpu_env, vect_off); | |
1215 | break; | |
1216 | default: | |
1217 | g_assert_not_reached(); | |
1218 | } | |
1219 | } | |
1220 | ||
72430bf5 AB |
1221 | /* Store from vector register to memory */ |
1222 | static void do_vec_st(DisasContext *s, int srcidx, int element, | |
87f9a7f0 | 1223 | TCGv_i64 tcg_addr, int size, TCGMemOp endian) |
72430bf5 | 1224 | { |
72430bf5 AB |
1225 | TCGv_i64 tcg_tmp = tcg_temp_new_i64(); |
1226 | ||
1227 | read_vec_element(s, tcg_tmp, srcidx, element, size); | |
87f9a7f0 | 1228 | tcg_gen_qemu_st_i64(tcg_tmp, tcg_addr, get_mem_index(s), endian | size); |
72430bf5 AB |
1229 | |
1230 | tcg_temp_free_i64(tcg_tmp); | |
1231 | } | |
1232 | ||
1233 | /* Load from memory to vector register */ | |
1234 | static void do_vec_ld(DisasContext *s, int destidx, int element, | |
87f9a7f0 | 1235 | TCGv_i64 tcg_addr, int size, TCGMemOp endian) |
72430bf5 | 1236 | { |
72430bf5 AB |
1237 | TCGv_i64 tcg_tmp = tcg_temp_new_i64(); |
1238 | ||
87f9a7f0 | 1239 | tcg_gen_qemu_ld_i64(tcg_tmp, tcg_addr, get_mem_index(s), endian | size); |
72430bf5 AB |
1240 | write_vec_element(s, tcg_tmp, destidx, element, size); |
1241 | ||
1242 | tcg_temp_free_i64(tcg_tmp); | |
1243 | } | |
1244 | ||
8c6afa6a PM |
1245 | /* Check that FP/Neon access is enabled. If it is, return |
1246 | * true. If not, emit code to generate an appropriate exception, | |
1247 | * and return false; the caller should not emit any code for | |
1248 | * the instruction. Note that this check must happen after all | |
1249 | * unallocated-encoding checks (otherwise the syndrome information | |
1250 | * for the resulting exception will be incorrect). | |
1251 | */ | |
1252 | static inline bool fp_access_check(DisasContext *s) | |
1253 | { | |
90e49638 PM |
1254 | assert(!s->fp_access_checked); |
1255 | s->fp_access_checked = true; | |
1256 | ||
9dbbc748 | 1257 | if (!s->fp_excp_el) { |
8c6afa6a PM |
1258 | return true; |
1259 | } | |
1260 | ||
73710361 | 1261 | gen_exception_insn(s, 4, EXCP_UDEF, syn_fp_access_trap(1, 0xe, false), |
9dbbc748 | 1262 | s->fp_excp_el); |
8c6afa6a PM |
1263 | return false; |
1264 | } | |
1265 | ||
490aa7f1 RH |
1266 | /* Check that SVE access is enabled. If it is, return true. |
1267 | * If not, emit code to generate an appropriate exception and return false. | |
1268 | */ | |
8c71baed | 1269 | bool sve_access_check(DisasContext *s) |
490aa7f1 RH |
1270 | { |
1271 | if (s->sve_excp_el) { | |
1272 | gen_exception_insn(s, 4, EXCP_UDEF, syn_sve_access_trap(), | |
1273 | s->sve_excp_el); | |
1274 | return false; | |
1275 | } | |
8c71baed | 1276 | return fp_access_check(s); |
490aa7f1 RH |
1277 | } |
1278 | ||
229b7a05 AB |
1279 | /* |
1280 | * This utility function is for doing register extension with an | |
1281 | * optional shift. You will likely want to pass a temporary for the | |
1282 | * destination register. See DecodeRegExtend() in the ARM ARM. | |
1283 | */ | |
1284 | static void ext_and_shift_reg(TCGv_i64 tcg_out, TCGv_i64 tcg_in, | |
1285 | int option, unsigned int shift) | |
1286 | { | |
1287 | int extsize = extract32(option, 0, 2); | |
1288 | bool is_signed = extract32(option, 2, 1); | |
1289 | ||
1290 | if (is_signed) { | |
1291 | switch (extsize) { | |
1292 | case 0: | |
1293 | tcg_gen_ext8s_i64(tcg_out, tcg_in); | |
1294 | break; | |
1295 | case 1: | |
1296 | tcg_gen_ext16s_i64(tcg_out, tcg_in); | |
1297 | break; | |
1298 | case 2: | |
1299 | tcg_gen_ext32s_i64(tcg_out, tcg_in); | |
1300 | break; | |
1301 | case 3: | |
1302 | tcg_gen_mov_i64(tcg_out, tcg_in); | |
1303 | break; | |
1304 | } | |
1305 | } else { | |
1306 | switch (extsize) { | |
1307 | case 0: | |
1308 | tcg_gen_ext8u_i64(tcg_out, tcg_in); | |
1309 | break; | |
1310 | case 1: | |
1311 | tcg_gen_ext16u_i64(tcg_out, tcg_in); | |
1312 | break; | |
1313 | case 2: | |
1314 | tcg_gen_ext32u_i64(tcg_out, tcg_in); | |
1315 | break; | |
1316 | case 3: | |
1317 | tcg_gen_mov_i64(tcg_out, tcg_in); | |
1318 | break; | |
1319 | } | |
1320 | } | |
1321 | ||
1322 | if (shift) { | |
1323 | tcg_gen_shli_i64(tcg_out, tcg_out, shift); | |
1324 | } | |
1325 | } | |
1326 | ||
4a08d475 PM |
1327 | static inline void gen_check_sp_alignment(DisasContext *s) |
1328 | { | |
1329 | /* The AArch64 architecture mandates that (if enabled via PSTATE | |
1330 | * or SCTLR bits) there is a check that SP is 16-aligned on every | |
1331 | * SP-relative load or store (with an exception generated if it is not). | |
1332 | * In line with general QEMU practice regarding misaligned accesses, | |
1333 | * we omit these checks for the sake of guest program performance. | |
1334 | * This function is provided as a hook so we can more easily add these | |
1335 | * checks in future (possibly as a "favour catching guest program bugs | |
1336 | * over speed" user selectable option). | |
1337 | */ | |
1338 | } | |
1339 | ||
384b26fb AB |
1340 | /* |
1341 | * This provides a simple table based table lookup decoder. It is | |
1342 | * intended to be used when the relevant bits for decode are too | |
1343 | * awkwardly placed and switch/if based logic would be confusing and | |
1344 | * deeply nested. Since it's a linear search through the table, tables | |
1345 | * should be kept small. | |
1346 | * | |
1347 | * It returns the first handler where insn & mask == pattern, or | |
1348 | * NULL if there is no match. | |
1349 | * The table is terminated by an empty mask (i.e. 0) | |
1350 | */ | |
1351 | static inline AArch64DecodeFn *lookup_disas_fn(const AArch64DecodeTable *table, | |
1352 | uint32_t insn) | |
1353 | { | |
1354 | const AArch64DecodeTable *tptr = table; | |
1355 | ||
1356 | while (tptr->mask) { | |
1357 | if ((insn & tptr->mask) == tptr->pattern) { | |
1358 | return tptr->disas_fn; | |
1359 | } | |
1360 | tptr++; | |
1361 | } | |
1362 | return NULL; | |
1363 | } | |
1364 | ||
ad7ee8a2 | 1365 | /* |
4ce31af4 PM |
1366 | * The instruction disassembly implemented here matches |
1367 | * the instruction encoding classifications in chapter C4 | |
1368 | * of the ARM Architecture Reference Manual (DDI0487B_a); | |
1369 | * classification names and decode diagrams here should generally | |
1370 | * match up with those in the manual. | |
ad7ee8a2 CF |
1371 | */ |
1372 | ||
4ce31af4 | 1373 | /* Unconditional branch (immediate) |
11e169de AG |
1374 | * 31 30 26 25 0 |
1375 | * +----+-----------+-------------------------------------+ | |
1376 | * | op | 0 0 1 0 1 | imm26 | | |
1377 | * +----+-----------+-------------------------------------+ | |
1378 | */ | |
ad7ee8a2 CF |
1379 | static void disas_uncond_b_imm(DisasContext *s, uint32_t insn) |
1380 | { | |
11e169de AG |
1381 | uint64_t addr = s->pc + sextract32(insn, 0, 26) * 4 - 4; |
1382 | ||
1743d55c | 1383 | if (insn & (1U << 31)) { |
4ce31af4 | 1384 | /* BL Branch with link */ |
11e169de AG |
1385 | tcg_gen_movi_i64(cpu_reg(s, 30), s->pc); |
1386 | } | |
1387 | ||
4ce31af4 | 1388 | /* B Branch / BL Branch with link */ |
35862270 | 1389 | reset_btype(s); |
11e169de | 1390 | gen_goto_tb(s, 0, addr); |
ad7ee8a2 CF |
1391 | } |
1392 | ||
4ce31af4 | 1393 | /* Compare and branch (immediate) |
60e53388 AG |
1394 | * 31 30 25 24 23 5 4 0 |
1395 | * +----+-------------+----+---------------------+--------+ | |
1396 | * | sf | 0 1 1 0 1 0 | op | imm19 | Rt | | |
1397 | * +----+-------------+----+---------------------+--------+ | |
1398 | */ | |
ad7ee8a2 CF |
1399 | static void disas_comp_b_imm(DisasContext *s, uint32_t insn) |
1400 | { | |
60e53388 AG |
1401 | unsigned int sf, op, rt; |
1402 | uint64_t addr; | |
42a268c2 | 1403 | TCGLabel *label_match; |
60e53388 AG |
1404 | TCGv_i64 tcg_cmp; |
1405 | ||
1406 | sf = extract32(insn, 31, 1); | |
1407 | op = extract32(insn, 24, 1); /* 0: CBZ; 1: CBNZ */ | |
1408 | rt = extract32(insn, 0, 5); | |
1409 | addr = s->pc + sextract32(insn, 5, 19) * 4 - 4; | |
1410 | ||
1411 | tcg_cmp = read_cpu_reg(s, rt, sf); | |
1412 | label_match = gen_new_label(); | |
1413 | ||
35862270 | 1414 | reset_btype(s); |
60e53388 AG |
1415 | tcg_gen_brcondi_i64(op ? TCG_COND_NE : TCG_COND_EQ, |
1416 | tcg_cmp, 0, label_match); | |
1417 | ||
1418 | gen_goto_tb(s, 0, s->pc); | |
1419 | gen_set_label(label_match); | |
1420 | gen_goto_tb(s, 1, addr); | |
ad7ee8a2 CF |
1421 | } |
1422 | ||
4ce31af4 | 1423 | /* Test and branch (immediate) |
db0f7958 AG |
1424 | * 31 30 25 24 23 19 18 5 4 0 |
1425 | * +----+-------------+----+-------+-------------+------+ | |
1426 | * | b5 | 0 1 1 0 1 1 | op | b40 | imm14 | Rt | | |
1427 | * +----+-------------+----+-------+-------------+------+ | |
1428 | */ | |
ad7ee8a2 CF |
1429 | static void disas_test_b_imm(DisasContext *s, uint32_t insn) |
1430 | { | |
db0f7958 AG |
1431 | unsigned int bit_pos, op, rt; |
1432 | uint64_t addr; | |
42a268c2 | 1433 | TCGLabel *label_match; |
db0f7958 AG |
1434 | TCGv_i64 tcg_cmp; |
1435 | ||
1436 | bit_pos = (extract32(insn, 31, 1) << 5) | extract32(insn, 19, 5); | |
1437 | op = extract32(insn, 24, 1); /* 0: TBZ; 1: TBNZ */ | |
1438 | addr = s->pc + sextract32(insn, 5, 14) * 4 - 4; | |
1439 | rt = extract32(insn, 0, 5); | |
1440 | ||
1441 | tcg_cmp = tcg_temp_new_i64(); | |
1442 | tcg_gen_andi_i64(tcg_cmp, cpu_reg(s, rt), (1ULL << bit_pos)); | |
1443 | label_match = gen_new_label(); | |
35862270 RH |
1444 | |
1445 | reset_btype(s); | |
db0f7958 AG |
1446 | tcg_gen_brcondi_i64(op ? TCG_COND_NE : TCG_COND_EQ, |
1447 | tcg_cmp, 0, label_match); | |
1448 | tcg_temp_free_i64(tcg_cmp); | |
1449 | gen_goto_tb(s, 0, s->pc); | |
1450 | gen_set_label(label_match); | |
1451 | gen_goto_tb(s, 1, addr); | |
ad7ee8a2 CF |
1452 | } |
1453 | ||
4ce31af4 | 1454 | /* Conditional branch (immediate) |
39fb730a AG |
1455 | * 31 25 24 23 5 4 3 0 |
1456 | * +---------------+----+---------------------+----+------+ | |
1457 | * | 0 1 0 1 0 1 0 | o1 | imm19 | o0 | cond | | |
1458 | * +---------------+----+---------------------+----+------+ | |
1459 | */ | |
ad7ee8a2 CF |
1460 | static void disas_cond_b_imm(DisasContext *s, uint32_t insn) |
1461 | { | |
39fb730a AG |
1462 | unsigned int cond; |
1463 | uint64_t addr; | |
1464 | ||
1465 | if ((insn & (1 << 4)) || (insn & (1 << 24))) { | |
1466 | unallocated_encoding(s); | |
1467 | return; | |
1468 | } | |
1469 | addr = s->pc + sextract32(insn, 5, 19) * 4 - 4; | |
1470 | cond = extract32(insn, 0, 4); | |
1471 | ||
35862270 | 1472 | reset_btype(s); |
39fb730a AG |
1473 | if (cond < 0x0e) { |
1474 | /* genuinely conditional branches */ | |
42a268c2 | 1475 | TCGLabel *label_match = gen_new_label(); |
39fb730a AG |
1476 | arm_gen_test_cc(cond, label_match); |
1477 | gen_goto_tb(s, 0, s->pc); | |
1478 | gen_set_label(label_match); | |
1479 | gen_goto_tb(s, 1, addr); | |
1480 | } else { | |
1481 | /* 0xe and 0xf are both "always" conditions */ | |
1482 | gen_goto_tb(s, 0, addr); | |
1483 | } | |
ad7ee8a2 CF |
1484 | } |
1485 | ||
4ce31af4 | 1486 | /* HINT instruction group, including various allocated HINTs */ |
87462e0f CF |
1487 | static void handle_hint(DisasContext *s, uint32_t insn, |
1488 | unsigned int op1, unsigned int op2, unsigned int crm) | |
1489 | { | |
1490 | unsigned int selector = crm << 3 | op2; | |
1491 | ||
1492 | if (op1 != 3) { | |
1493 | unallocated_encoding(s); | |
1494 | return; | |
1495 | } | |
1496 | ||
1497 | switch (selector) { | |
7c94c834 RH |
1498 | case 0b00000: /* NOP */ |
1499 | break; | |
1500 | case 0b00011: /* WFI */ | |
dcba3a8d | 1501 | s->base.is_jmp = DISAS_WFI; |
7c94c834 RH |
1502 | break; |
1503 | case 0b00001: /* YIELD */ | |
2399d4e7 EC |
1504 | /* When running in MTTCG we don't generate jumps to the yield and |
1505 | * WFE helpers as it won't affect the scheduling of other vCPUs. | |
1506 | * If we wanted to more completely model WFE/SEV so we don't busy | |
1507 | * spin unnecessarily we would need to do something more involved. | |
1508 | */ | |
2399d4e7 | 1509 | if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) { |
dcba3a8d | 1510 | s->base.is_jmp = DISAS_YIELD; |
c22edfeb | 1511 | } |
7c94c834 RH |
1512 | break; |
1513 | case 0b00010: /* WFE */ | |
2399d4e7 | 1514 | if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) { |
dcba3a8d | 1515 | s->base.is_jmp = DISAS_WFE; |
c22edfeb | 1516 | } |
7c94c834 RH |
1517 | break; |
1518 | case 0b00100: /* SEV */ | |
1519 | case 0b00101: /* SEVL */ | |
87462e0f | 1520 | /* we treat all as NOP at least for now */ |
7c94c834 RH |
1521 | break; |
1522 | case 0b00111: /* XPACLRI */ | |
1523 | if (s->pauth_active) { | |
1524 | gen_helper_xpaci(cpu_X[30], cpu_env, cpu_X[30]); | |
1525 | } | |
1526 | break; | |
1527 | case 0b01000: /* PACIA1716 */ | |
1528 | if (s->pauth_active) { | |
1529 | gen_helper_pacia(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]); | |
1530 | } | |
1531 | break; | |
1532 | case 0b01010: /* PACIB1716 */ | |
1533 | if (s->pauth_active) { | |
1534 | gen_helper_pacib(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]); | |
1535 | } | |
1536 | break; | |
1537 | case 0b01100: /* AUTIA1716 */ | |
1538 | if (s->pauth_active) { | |
1539 | gen_helper_autia(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]); | |
1540 | } | |
1541 | break; | |
1542 | case 0b01110: /* AUTIB1716 */ | |
1543 | if (s->pauth_active) { | |
1544 | gen_helper_autib(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]); | |
1545 | } | |
1546 | break; | |
1547 | case 0b11000: /* PACIAZ */ | |
1548 | if (s->pauth_active) { | |
1549 | gen_helper_pacia(cpu_X[30], cpu_env, cpu_X[30], | |
1550 | new_tmp_a64_zero(s)); | |
1551 | } | |
1552 | break; | |
1553 | case 0b11001: /* PACIASP */ | |
1554 | if (s->pauth_active) { | |
1555 | gen_helper_pacia(cpu_X[30], cpu_env, cpu_X[30], cpu_X[31]); | |
1556 | } | |
1557 | break; | |
1558 | case 0b11010: /* PACIBZ */ | |
1559 | if (s->pauth_active) { | |
1560 | gen_helper_pacib(cpu_X[30], cpu_env, cpu_X[30], | |
1561 | new_tmp_a64_zero(s)); | |
1562 | } | |
1563 | break; | |
1564 | case 0b11011: /* PACIBSP */ | |
1565 | if (s->pauth_active) { | |
1566 | gen_helper_pacib(cpu_X[30], cpu_env, cpu_X[30], cpu_X[31]); | |
1567 | } | |
1568 | break; | |
1569 | case 0b11100: /* AUTIAZ */ | |
1570 | if (s->pauth_active) { | |
1571 | gen_helper_autia(cpu_X[30], cpu_env, cpu_X[30], | |
1572 | new_tmp_a64_zero(s)); | |
1573 | } | |
1574 | break; | |
1575 | case 0b11101: /* AUTIASP */ | |
1576 | if (s->pauth_active) { | |
1577 | gen_helper_autia(cpu_X[30], cpu_env, cpu_X[30], cpu_X[31]); | |
1578 | } | |
1579 | break; | |
1580 | case 0b11110: /* AUTIBZ */ | |
1581 | if (s->pauth_active) { | |
1582 | gen_helper_autib(cpu_X[30], cpu_env, cpu_X[30], | |
1583 | new_tmp_a64_zero(s)); | |
1584 | } | |
1585 | break; | |
1586 | case 0b11111: /* AUTIBSP */ | |
1587 | if (s->pauth_active) { | |
1588 | gen_helper_autib(cpu_X[30], cpu_env, cpu_X[30], cpu_X[31]); | |
1589 | } | |
1590 | break; | |
87462e0f CF |
1591 | default: |
1592 | /* default specified as NOP equivalent */ | |
7c94c834 | 1593 | break; |
87462e0f CF |
1594 | } |
1595 | } | |
1596 | ||
fa2ef212 MM |
1597 | static void gen_clrex(DisasContext *s, uint32_t insn) |
1598 | { | |
1599 | tcg_gen_movi_i64(cpu_exclusive_addr, -1); | |
1600 | } | |
1601 | ||
87462e0f CF |
1602 | /* CLREX, DSB, DMB, ISB */ |
1603 | static void handle_sync(DisasContext *s, uint32_t insn, | |
1604 | unsigned int op1, unsigned int op2, unsigned int crm) | |
1605 | { | |
ce1bd93f PK |
1606 | TCGBar bar; |
1607 | ||
87462e0f CF |
1608 | if (op1 != 3) { |
1609 | unallocated_encoding(s); | |
1610 | return; | |
1611 | } | |
1612 | ||
1613 | switch (op2) { | |
1614 | case 2: /* CLREX */ | |
fa2ef212 | 1615 | gen_clrex(s, insn); |
87462e0f CF |
1616 | return; |
1617 | case 4: /* DSB */ | |
1618 | case 5: /* DMB */ | |
ce1bd93f PK |
1619 | switch (crm & 3) { |
1620 | case 1: /* MBReqTypes_Reads */ | |
1621 | bar = TCG_BAR_SC | TCG_MO_LD_LD | TCG_MO_LD_ST; | |
1622 | break; | |
1623 | case 2: /* MBReqTypes_Writes */ | |
1624 | bar = TCG_BAR_SC | TCG_MO_ST_ST; | |
1625 | break; | |
1626 | default: /* MBReqTypes_All */ | |
1627 | bar = TCG_BAR_SC | TCG_MO_ALL; | |
1628 | break; | |
1629 | } | |
1630 | tcg_gen_mb(bar); | |
87462e0f | 1631 | return; |
6df99dec SS |
1632 | case 6: /* ISB */ |
1633 | /* We need to break the TB after this insn to execute | |
1634 | * a self-modified code correctly and also to take | |
1635 | * any pending interrupts immediately. | |
1636 | */ | |
35862270 | 1637 | reset_btype(s); |
0b609cc1 | 1638 | gen_goto_tb(s, 0, s->pc); |
6df99dec | 1639 | return; |
87462e0f CF |
1640 | default: |
1641 | unallocated_encoding(s); | |
1642 | return; | |
1643 | } | |
1644 | } | |
1645 | ||
4ce31af4 | 1646 | /* MSR (immediate) - move immediate to processor state field */ |
87462e0f CF |
1647 | static void handle_msr_i(DisasContext *s, uint32_t insn, |
1648 | unsigned int op1, unsigned int op2, unsigned int crm) | |
1649 | { | |
9cfa0b4e PM |
1650 | int op = op1 << 3 | op2; |
1651 | switch (op) { | |
1652 | case 0x05: /* SPSel */ | |
dcbff19b | 1653 | if (s->current_el == 0) { |
9cfa0b4e PM |
1654 | unallocated_encoding(s); |
1655 | return; | |
1656 | } | |
1657 | /* fall through */ | |
1658 | case 0x1e: /* DAIFSet */ | |
1659 | case 0x1f: /* DAIFClear */ | |
1660 | { | |
1661 | TCGv_i32 tcg_imm = tcg_const_i32(crm); | |
1662 | TCGv_i32 tcg_op = tcg_const_i32(op); | |
1663 | gen_a64_set_pc_im(s->pc - 4); | |
1664 | gen_helper_msr_i_pstate(cpu_env, tcg_op, tcg_imm); | |
1665 | tcg_temp_free_i32(tcg_imm); | |
1666 | tcg_temp_free_i32(tcg_op); | |
8da54b25 RH |
1667 | /* For DAIFClear, exit the cpu loop to re-evaluate pending IRQs. */ |
1668 | gen_a64_set_pc_im(s->pc); | |
dcba3a8d | 1669 | s->base.is_jmp = (op == 0x1f ? DISAS_EXIT : DISAS_JUMP); |
9cfa0b4e PM |
1670 | break; |
1671 | } | |
1672 | default: | |
1673 | unallocated_encoding(s); | |
1674 | return; | |
1675 | } | |
87462e0f CF |
1676 | } |
1677 | ||
b0d2b7d0 PM |
1678 | static void gen_get_nzcv(TCGv_i64 tcg_rt) |
1679 | { | |
1680 | TCGv_i32 tmp = tcg_temp_new_i32(); | |
1681 | TCGv_i32 nzcv = tcg_temp_new_i32(); | |
1682 | ||
1683 | /* build bit 31, N */ | |
1743d55c | 1684 | tcg_gen_andi_i32(nzcv, cpu_NF, (1U << 31)); |
b0d2b7d0 PM |
1685 | /* build bit 30, Z */ |
1686 | tcg_gen_setcondi_i32(TCG_COND_EQ, tmp, cpu_ZF, 0); | |
1687 | tcg_gen_deposit_i32(nzcv, nzcv, tmp, 30, 1); | |
1688 | /* build bit 29, C */ | |
1689 | tcg_gen_deposit_i32(nzcv, nzcv, cpu_CF, 29, 1); | |
1690 | /* build bit 28, V */ | |
1691 | tcg_gen_shri_i32(tmp, cpu_VF, 31); | |
1692 | tcg_gen_deposit_i32(nzcv, nzcv, tmp, 28, 1); | |
1693 | /* generate result */ | |
1694 | tcg_gen_extu_i32_i64(tcg_rt, nzcv); | |
1695 | ||
1696 | tcg_temp_free_i32(nzcv); | |
1697 | tcg_temp_free_i32(tmp); | |
1698 | } | |
1699 | ||
1700 | static void gen_set_nzcv(TCGv_i64 tcg_rt) | |
1701 | ||
1702 | { | |
1703 | TCGv_i32 nzcv = tcg_temp_new_i32(); | |
1704 | ||
1705 | /* take NZCV from R[t] */ | |
ecc7b3aa | 1706 | tcg_gen_extrl_i64_i32(nzcv, tcg_rt); |
b0d2b7d0 PM |
1707 | |
1708 | /* bit 31, N */ | |
1743d55c | 1709 | tcg_gen_andi_i32(cpu_NF, nzcv, (1U << 31)); |
b0d2b7d0 PM |
1710 | /* bit 30, Z */ |
1711 | tcg_gen_andi_i32(cpu_ZF, nzcv, (1 << 30)); | |
1712 | tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_ZF, cpu_ZF, 0); | |
1713 | /* bit 29, C */ | |
1714 | tcg_gen_andi_i32(cpu_CF, nzcv, (1 << 29)); | |
1715 | tcg_gen_shri_i32(cpu_CF, cpu_CF, 29); | |
1716 | /* bit 28, V */ | |
1717 | tcg_gen_andi_i32(cpu_VF, nzcv, (1 << 28)); | |
1718 | tcg_gen_shli_i32(cpu_VF, cpu_VF, 3); | |
1719 | tcg_temp_free_i32(nzcv); | |
1720 | } | |
1721 | ||
4ce31af4 PM |
1722 | /* MRS - move from system register |
1723 | * MSR (register) - move to system register | |
1724 | * SYS | |
1725 | * SYSL | |
fea50522 PM |
1726 | * These are all essentially the same insn in 'read' and 'write' |
1727 | * versions, with varying op0 fields. | |
1728 | */ | |
1729 | static void handle_sys(DisasContext *s, uint32_t insn, bool isread, | |
1730 | unsigned int op0, unsigned int op1, unsigned int op2, | |
87462e0f CF |
1731 | unsigned int crn, unsigned int crm, unsigned int rt) |
1732 | { | |
fea50522 PM |
1733 | const ARMCPRegInfo *ri; |
1734 | TCGv_i64 tcg_rt; | |
87462e0f | 1735 | |
fea50522 PM |
1736 | ri = get_arm_cp_reginfo(s->cp_regs, |
1737 | ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, | |
1738 | crn, crm, op0, op1, op2)); | |
87462e0f | 1739 | |
fea50522 | 1740 | if (!ri) { |
626187d8 PM |
1741 | /* Unknown register; this might be a guest error or a QEMU |
1742 | * unimplemented feature. | |
1743 | */ | |
1744 | qemu_log_mask(LOG_UNIMP, "%s access to unsupported AArch64 " | |
1745 | "system register op0:%d op1:%d crn:%d crm:%d op2:%d\n", | |
1746 | isread ? "read" : "write", op0, op1, crn, crm, op2); | |
fea50522 PM |
1747 | unallocated_encoding(s); |
1748 | return; | |
1749 | } | |
1750 | ||
1751 | /* Check access permissions */ | |
dcbff19b | 1752 | if (!cp_access_ok(s->current_el, ri, isread)) { |
fea50522 PM |
1753 | unallocated_encoding(s); |
1754 | return; | |
1755 | } | |
1756 | ||
f59df3f2 PM |
1757 | if (ri->accessfn) { |
1758 | /* Emit code to perform further access permissions checks at | |
1759 | * runtime; this may result in an exception. | |
1760 | */ | |
1761 | TCGv_ptr tmpptr; | |
3f208fd7 | 1762 | TCGv_i32 tcg_syn, tcg_isread; |
8bcbf37c PM |
1763 | uint32_t syndrome; |
1764 | ||
f59df3f2 PM |
1765 | gen_a64_set_pc_im(s->pc - 4); |
1766 | tmpptr = tcg_const_ptr(ri); | |
8bcbf37c PM |
1767 | syndrome = syn_aa64_sysregtrap(op0, op1, op2, crn, crm, rt, isread); |
1768 | tcg_syn = tcg_const_i32(syndrome); | |
3f208fd7 PM |
1769 | tcg_isread = tcg_const_i32(isread); |
1770 | gen_helper_access_check_cp_reg(cpu_env, tmpptr, tcg_syn, tcg_isread); | |
f59df3f2 | 1771 | tcg_temp_free_ptr(tmpptr); |
8bcbf37c | 1772 | tcg_temp_free_i32(tcg_syn); |
3f208fd7 | 1773 | tcg_temp_free_i32(tcg_isread); |
f59df3f2 PM |
1774 | } |
1775 | ||
fea50522 PM |
1776 | /* Handle special cases first */ |
1777 | switch (ri->type & ~(ARM_CP_FLAG_MASK & ~ARM_CP_SPECIAL)) { | |
1778 | case ARM_CP_NOP: | |
1779 | return; | |
b0d2b7d0 PM |
1780 | case ARM_CP_NZCV: |
1781 | tcg_rt = cpu_reg(s, rt); | |
1782 | if (isread) { | |
1783 | gen_get_nzcv(tcg_rt); | |
1784 | } else { | |
1785 | gen_set_nzcv(tcg_rt); | |
1786 | } | |
1787 | return; | |
0eef9d98 PM |
1788 | case ARM_CP_CURRENTEL: |
1789 | /* Reads as current EL value from pstate, which is | |
1790 | * guaranteed to be constant by the tb flags. | |
1791 | */ | |
1792 | tcg_rt = cpu_reg(s, rt); | |
dcbff19b | 1793 | tcg_gen_movi_i64(tcg_rt, s->current_el << 2); |
0eef9d98 | 1794 | return; |
aca3f40b PM |
1795 | case ARM_CP_DC_ZVA: |
1796 | /* Writes clear the aligned block of memory which rt points into. */ | |
1797 | tcg_rt = cpu_reg(s, rt); | |
1798 | gen_helper_dc_zva(cpu_env, tcg_rt); | |
1799 | return; | |
fea50522 PM |
1800 | default: |
1801 | break; | |
1802 | } | |
fe03d45f RH |
1803 | if ((ri->type & ARM_CP_FPU) && !fp_access_check(s)) { |
1804 | return; | |
11d7870b RH |
1805 | } else if ((ri->type & ARM_CP_SVE) && !sve_access_check(s)) { |
1806 | return; | |
fe03d45f | 1807 | } |
fea50522 | 1808 | |
c5a49c63 | 1809 | if ((tb_cflags(s->base.tb) & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) { |
fea50522 PM |
1810 | gen_io_start(); |
1811 | } | |
1812 | ||
1813 | tcg_rt = cpu_reg(s, rt); | |
1814 | ||
1815 | if (isread) { | |
1816 | if (ri->type & ARM_CP_CONST) { | |
1817 | tcg_gen_movi_i64(tcg_rt, ri->resetvalue); | |
1818 | } else if (ri->readfn) { | |
1819 | TCGv_ptr tmpptr; | |
fea50522 PM |
1820 | tmpptr = tcg_const_ptr(ri); |
1821 | gen_helper_get_cp_reg64(tcg_rt, cpu_env, tmpptr); | |
1822 | tcg_temp_free_ptr(tmpptr); | |
1823 | } else { | |
1824 | tcg_gen_ld_i64(tcg_rt, cpu_env, ri->fieldoffset); | |
1825 | } | |
1826 | } else { | |
1827 | if (ri->type & ARM_CP_CONST) { | |
1828 | /* If not forbidden by access permissions, treat as WI */ | |
1829 | return; | |
1830 | } else if (ri->writefn) { | |
1831 | TCGv_ptr tmpptr; | |
fea50522 PM |
1832 | tmpptr = tcg_const_ptr(ri); |
1833 | gen_helper_set_cp_reg64(cpu_env, tmpptr, tcg_rt); | |
1834 | tcg_temp_free_ptr(tmpptr); | |
1835 | } else { | |
1836 | tcg_gen_st_i64(tcg_rt, cpu_env, ri->fieldoffset); | |
1837 | } | |
1838 | } | |
1839 | ||
c5a49c63 | 1840 | if ((tb_cflags(s->base.tb) & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) { |
fea50522 PM |
1841 | /* I/O operations must end the TB here (whether read or write) */ |
1842 | gen_io_end(); | |
dcba3a8d | 1843 | s->base.is_jmp = DISAS_UPDATE; |
fea50522 PM |
1844 | } else if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) { |
1845 | /* We default to ending the TB on a coprocessor register write, | |
1846 | * but allow this to be suppressed by the register definition | |
1847 | * (usually only necessary to work around guest bugs). | |
1848 | */ | |
dcba3a8d | 1849 | s->base.is_jmp = DISAS_UPDATE; |
fea50522 | 1850 | } |
ad7ee8a2 CF |
1851 | } |
1852 | ||
4ce31af4 | 1853 | /* System |
87462e0f CF |
1854 | * 31 22 21 20 19 18 16 15 12 11 8 7 5 4 0 |
1855 | * +---------------------+---+-----+-----+-------+-------+-----+------+ | |
1856 | * | 1 1 0 1 0 1 0 1 0 0 | L | op0 | op1 | CRn | CRm | op2 | Rt | | |
1857 | * +---------------------+---+-----+-----+-------+-------+-----+------+ | |
1858 | */ | |
1859 | static void disas_system(DisasContext *s, uint32_t insn) | |
1860 | { | |
1861 | unsigned int l, op0, op1, crn, crm, op2, rt; | |
1862 | l = extract32(insn, 21, 1); | |
1863 | op0 = extract32(insn, 19, 2); | |
1864 | op1 = extract32(insn, 16, 3); | |
1865 | crn = extract32(insn, 12, 4); | |
1866 | crm = extract32(insn, 8, 4); | |
1867 | op2 = extract32(insn, 5, 3); | |
1868 | rt = extract32(insn, 0, 5); | |
1869 | ||
1870 | if (op0 == 0) { | |
1871 | if (l || rt != 31) { | |
1872 | unallocated_encoding(s); | |
1873 | return; | |
1874 | } | |
1875 | switch (crn) { | |
4ce31af4 | 1876 | case 2: /* HINT (including allocated hints like NOP, YIELD, etc) */ |
87462e0f CF |
1877 | handle_hint(s, insn, op1, op2, crm); |
1878 | break; | |
1879 | case 3: /* CLREX, DSB, DMB, ISB */ | |
1880 | handle_sync(s, insn, op1, op2, crm); | |
1881 | break; | |
4ce31af4 | 1882 | case 4: /* MSR (immediate) */ |
87462e0f CF |
1883 | handle_msr_i(s, insn, op1, op2, crm); |
1884 | break; | |
1885 | default: | |
1886 | unallocated_encoding(s); | |
1887 | break; | |
1888 | } | |
1889 | return; | |
1890 | } | |
fea50522 | 1891 | handle_sys(s, insn, l, op0, op1, op2, crn, crm, rt); |
87462e0f CF |
1892 | } |
1893 | ||
4ce31af4 | 1894 | /* Exception generation |
9618e809 AG |
1895 | * |
1896 | * 31 24 23 21 20 5 4 2 1 0 | |
1897 | * +-----------------+-----+------------------------+-----+----+ | |
1898 | * | 1 1 0 1 0 1 0 0 | opc | imm16 | op2 | LL | | |
1899 | * +-----------------------+------------------------+----------+ | |
1900 | */ | |
ad7ee8a2 CF |
1901 | static void disas_exc(DisasContext *s, uint32_t insn) |
1902 | { | |
9618e809 AG |
1903 | int opc = extract32(insn, 21, 3); |
1904 | int op2_ll = extract32(insn, 0, 5); | |
d4a2dc67 | 1905 | int imm16 = extract32(insn, 5, 16); |
e0d6e6a5 | 1906 | TCGv_i32 tmp; |
9618e809 AG |
1907 | |
1908 | switch (opc) { | |
1909 | case 0: | |
7ea47fe7 PM |
1910 | /* For SVC, HVC and SMC we advance the single-step state |
1911 | * machine before taking the exception. This is architecturally | |
1912 | * mandated, to ensure that single-stepping a system call | |
1913 | * instruction works properly. | |
1914 | */ | |
35979d71 | 1915 | switch (op2_ll) { |
957956b3 | 1916 | case 1: /* SVC */ |
35979d71 | 1917 | gen_ss_advance(s); |
73710361 GB |
1918 | gen_exception_insn(s, 0, EXCP_SWI, syn_aa64_svc(imm16), |
1919 | default_exception_el(s)); | |
35979d71 | 1920 | break; |
957956b3 | 1921 | case 2: /* HVC */ |
dcbff19b | 1922 | if (s->current_el == 0) { |
35979d71 EI |
1923 | unallocated_encoding(s); |
1924 | break; | |
1925 | } | |
1926 | /* The pre HVC helper handles cases when HVC gets trapped | |
1927 | * as an undefined insn by runtime configuration. | |
1928 | */ | |
1929 | gen_a64_set_pc_im(s->pc - 4); | |
1930 | gen_helper_pre_hvc(cpu_env); | |
1931 | gen_ss_advance(s); | |
73710361 | 1932 | gen_exception_insn(s, 0, EXCP_HVC, syn_aa64_hvc(imm16), 2); |
35979d71 | 1933 | break; |
957956b3 | 1934 | case 3: /* SMC */ |
dcbff19b | 1935 | if (s->current_el == 0) { |
e0d6e6a5 EI |
1936 | unallocated_encoding(s); |
1937 | break; | |
1938 | } | |
1939 | gen_a64_set_pc_im(s->pc - 4); | |
1940 | tmp = tcg_const_i32(syn_aa64_smc(imm16)); | |
1941 | gen_helper_pre_smc(cpu_env, tmp); | |
1942 | tcg_temp_free_i32(tmp); | |
1943 | gen_ss_advance(s); | |
73710361 | 1944 | gen_exception_insn(s, 0, EXCP_SMC, syn_aa64_smc(imm16), 3); |
e0d6e6a5 | 1945 | break; |
35979d71 EI |
1946 | default: |
1947 | unallocated_encoding(s); | |
1948 | break; | |
1949 | } | |
9618e809 AG |
1950 | break; |
1951 | case 1: | |
1952 | if (op2_ll != 0) { | |
1953 | unallocated_encoding(s); | |
1954 | break; | |
1955 | } | |
1956 | /* BRK */ | |
c900a2e6 | 1957 | gen_exception_bkpt_insn(s, 4, syn_aa64_bkpt(imm16)); |
9618e809 AG |
1958 | break; |
1959 | case 2: | |
1960 | if (op2_ll != 0) { | |
1961 | unallocated_encoding(s); | |
1962 | break; | |
1963 | } | |
8012c84f PM |
1964 | /* HLT. This has two purposes. |
1965 | * Architecturally, it is an external halting debug instruction. | |
1966 | * Since QEMU doesn't implement external debug, we treat this as | |
1967 | * it is required for halting debug disabled: it will UNDEF. | |
1968 | * Secondly, "HLT 0xf000" is the A64 semihosting syscall instruction. | |
1969 | */ | |
1970 | if (semihosting_enabled() && imm16 == 0xf000) { | |
1971 | #ifndef CONFIG_USER_ONLY | |
1972 | /* In system mode, don't allow userspace access to semihosting, | |
1973 | * to provide some semblance of security (and for consistency | |
1974 | * with our 32-bit semihosting). | |
1975 | */ | |
1976 | if (s->current_el == 0) { | |
1977 | unsupported_encoding(s, insn); | |
1978 | break; | |
1979 | } | |
1980 | #endif | |
1981 | gen_exception_internal_insn(s, 0, EXCP_SEMIHOST); | |
1982 | } else { | |
1983 | unsupported_encoding(s, insn); | |
1984 | } | |
9618e809 AG |
1985 | break; |
1986 | case 5: | |
1987 | if (op2_ll < 1 || op2_ll > 3) { | |
1988 | unallocated_encoding(s); | |
1989 | break; | |
1990 | } | |
1991 | /* DCPS1, DCPS2, DCPS3 */ | |
1992 | unsupported_encoding(s, insn); | |
1993 | break; | |
1994 | default: | |
1995 | unallocated_encoding(s); | |
1996 | break; | |
1997 | } | |
ad7ee8a2 CF |
1998 | } |
1999 | ||
4ce31af4 | 2000 | /* Unconditional branch (register) |
b001c8c3 AG |
2001 | * 31 25 24 21 20 16 15 10 9 5 4 0 |
2002 | * +---------------+-------+-------+-------+------+-------+ | |
2003 | * | 1 1 0 1 0 1 1 | opc | op2 | op3 | Rn | op4 | | |
2004 | * +---------------+-------+-------+-------+------+-------+ | |
2005 | */ | |
ad7ee8a2 CF |
2006 | static void disas_uncond_b_reg(DisasContext *s, uint32_t insn) |
2007 | { | |
b001c8c3 | 2008 | unsigned int opc, op2, op3, rn, op4; |
001d47b6 | 2009 | unsigned btype_mod = 2; /* 0: BR, 1: BLR, 2: other */ |
d9f482a0 | 2010 | TCGv_i64 dst; |
561c0a33 | 2011 | TCGv_i64 modifier; |
b001c8c3 AG |
2012 | |
2013 | opc = extract32(insn, 21, 4); | |
2014 | op2 = extract32(insn, 16, 5); | |
2015 | op3 = extract32(insn, 10, 6); | |
2016 | rn = extract32(insn, 5, 5); | |
2017 | op4 = extract32(insn, 0, 5); | |
2018 | ||
f7cf3bfc RH |
2019 | if (op2 != 0x1f) { |
2020 | goto do_unallocated; | |
b001c8c3 AG |
2021 | } |
2022 | ||
2023 | switch (opc) { | |
2024 | case 0: /* BR */ | |
b001c8c3 | 2025 | case 1: /* BLR */ |
6feecb8b | 2026 | case 2: /* RET */ |
001d47b6 | 2027 | btype_mod = opc; |
f7cf3bfc RH |
2028 | switch (op3) { |
2029 | case 0: | |
561c0a33 | 2030 | /* BR, BLR, RET */ |
f7cf3bfc RH |
2031 | if (op4 != 0) { |
2032 | goto do_unallocated; | |
2033 | } | |
2034 | dst = cpu_reg(s, rn); | |
2035 | break; | |
2036 | ||
561c0a33 RH |
2037 | case 2: |
2038 | case 3: | |
2039 | if (!dc_isar_feature(aa64_pauth, s)) { | |
2040 | goto do_unallocated; | |
2041 | } | |
2042 | if (opc == 2) { | |
2043 | /* RETAA, RETAB */ | |
2044 | if (rn != 0x1f || op4 != 0x1f) { | |
2045 | goto do_unallocated; | |
2046 | } | |
2047 | rn = 30; | |
2048 | modifier = cpu_X[31]; | |
2049 | } else { | |
2050 | /* BRAAZ, BRABZ, BLRAAZ, BLRABZ */ | |
2051 | if (op4 != 0x1f) { | |
2052 | goto do_unallocated; | |
2053 | } | |
2054 | modifier = new_tmp_a64_zero(s); | |
2055 | } | |
2056 | if (s->pauth_active) { | |
2057 | dst = new_tmp_a64(s); | |
2058 | if (op3 == 2) { | |
2059 | gen_helper_autia(dst, cpu_env, cpu_reg(s, rn), modifier); | |
2060 | } else { | |
2061 | gen_helper_autib(dst, cpu_env, cpu_reg(s, rn), modifier); | |
2062 | } | |
2063 | } else { | |
2064 | dst = cpu_reg(s, rn); | |
2065 | } | |
2066 | break; | |
2067 | ||
f7cf3bfc RH |
2068 | default: |
2069 | goto do_unallocated; | |
2070 | } | |
f7cf3bfc | 2071 | gen_a64_set_pc(s, dst); |
6feecb8b TH |
2072 | /* BLR also needs to load return address */ |
2073 | if (opc == 1) { | |
2074 | tcg_gen_movi_i64(cpu_reg(s, 30), s->pc); | |
2075 | } | |
b001c8c3 | 2076 | break; |
f7cf3bfc | 2077 | |
561c0a33 RH |
2078 | case 8: /* BRAA */ |
2079 | case 9: /* BLRAA */ | |
2080 | if (!dc_isar_feature(aa64_pauth, s)) { | |
2081 | goto do_unallocated; | |
2082 | } | |
1cf86a86 | 2083 | if ((op3 & ~1) != 2) { |
561c0a33 RH |
2084 | goto do_unallocated; |
2085 | } | |
001d47b6 | 2086 | btype_mod = opc & 1; |
561c0a33 RH |
2087 | if (s->pauth_active) { |
2088 | dst = new_tmp_a64(s); | |
2089 | modifier = cpu_reg_sp(s, op4); | |
2090 | if (op3 == 2) { | |
2091 | gen_helper_autia(dst, cpu_env, cpu_reg(s, rn), modifier); | |
2092 | } else { | |
2093 | gen_helper_autib(dst, cpu_env, cpu_reg(s, rn), modifier); | |
2094 | } | |
2095 | } else { | |
2096 | dst = cpu_reg(s, rn); | |
2097 | } | |
2098 | gen_a64_set_pc(s, dst); | |
2099 | /* BLRAA also needs to load return address */ | |
2100 | if (opc == 9) { | |
2101 | tcg_gen_movi_i64(cpu_reg(s, 30), s->pc); | |
2102 | } | |
2103 | break; | |
2104 | ||
b001c8c3 | 2105 | case 4: /* ERET */ |
dcbff19b | 2106 | if (s->current_el == 0) { |
f7cf3bfc RH |
2107 | goto do_unallocated; |
2108 | } | |
2109 | switch (op3) { | |
561c0a33 | 2110 | case 0: /* ERET */ |
f7cf3bfc RH |
2111 | if (op4 != 0) { |
2112 | goto do_unallocated; | |
2113 | } | |
2114 | dst = tcg_temp_new_i64(); | |
2115 | tcg_gen_ld_i64(dst, cpu_env, | |
2116 | offsetof(CPUARMState, elr_el[s->current_el])); | |
2117 | break; | |
2118 | ||
561c0a33 RH |
2119 | case 2: /* ERETAA */ |
2120 | case 3: /* ERETAB */ | |
2121 | if (!dc_isar_feature(aa64_pauth, s)) { | |
2122 | goto do_unallocated; | |
2123 | } | |
2124 | if (rn != 0x1f || op4 != 0x1f) { | |
2125 | goto do_unallocated; | |
2126 | } | |
2127 | dst = tcg_temp_new_i64(); | |
2128 | tcg_gen_ld_i64(dst, cpu_env, | |
2129 | offsetof(CPUARMState, elr_el[s->current_el])); | |
2130 | if (s->pauth_active) { | |
2131 | modifier = cpu_X[31]; | |
2132 | if (op3 == 2) { | |
2133 | gen_helper_autia(dst, cpu_env, dst, modifier); | |
2134 | } else { | |
2135 | gen_helper_autib(dst, cpu_env, dst, modifier); | |
2136 | } | |
2137 | } | |
2138 | break; | |
2139 | ||
f7cf3bfc RH |
2140 | default: |
2141 | goto do_unallocated; | |
14c521d4 | 2142 | } |
e69ad9df AL |
2143 | if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { |
2144 | gen_io_start(); | |
2145 | } | |
f7cf3bfc | 2146 | |
d9f482a0 RH |
2147 | gen_helper_exception_return(cpu_env, dst); |
2148 | tcg_temp_free_i64(dst); | |
e69ad9df AL |
2149 | if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { |
2150 | gen_io_end(); | |
2151 | } | |
b29fd33d | 2152 | /* Must exit loop to check un-masked IRQs */ |
dcba3a8d | 2153 | s->base.is_jmp = DISAS_EXIT; |
52e60cdd | 2154 | return; |
f7cf3bfc | 2155 | |
b001c8c3 | 2156 | case 5: /* DRPS */ |
f7cf3bfc RH |
2157 | if (op3 != 0 || op4 != 0 || rn != 0x1f) { |
2158 | goto do_unallocated; | |
b001c8c3 AG |
2159 | } else { |
2160 | unsupported_encoding(s, insn); | |
2161 | } | |
2162 | return; | |
f7cf3bfc | 2163 | |
b001c8c3 | 2164 | default: |
f7cf3bfc | 2165 | do_unallocated: |
b001c8c3 AG |
2166 | unallocated_encoding(s); |
2167 | return; | |
2168 | } | |
2169 | ||
001d47b6 RH |
2170 | switch (btype_mod) { |
2171 | case 0: /* BR */ | |
2172 | if (dc_isar_feature(aa64_bti, s)) { | |
2173 | /* BR to {x16,x17} or !guard -> 1, else 3. */ | |
2174 | set_btype(s, rn == 16 || rn == 17 || !s->guarded_page ? 1 : 3); | |
2175 | } | |
2176 | break; | |
2177 | ||
2178 | case 1: /* BLR */ | |
2179 | if (dc_isar_feature(aa64_bti, s)) { | |
2180 | /* BLR sets BTYPE to 2, regardless of source guarded page. */ | |
2181 | set_btype(s, 2); | |
2182 | } | |
2183 | break; | |
2184 | ||
2185 | default: /* RET or none of the above. */ | |
2186 | /* BTYPE will be set to 0 by normal end-of-insn processing. */ | |
2187 | break; | |
2188 | } | |
2189 | ||
dcba3a8d | 2190 | s->base.is_jmp = DISAS_JUMP; |
ad7ee8a2 CF |
2191 | } |
2192 | ||
4ce31af4 | 2193 | /* Branches, exception generating and system instructions */ |
ad7ee8a2 CF |
2194 | static void disas_b_exc_sys(DisasContext *s, uint32_t insn) |
2195 | { | |
2196 | switch (extract32(insn, 25, 7)) { | |
2197 | case 0x0a: case 0x0b: | |
2198 | case 0x4a: case 0x4b: /* Unconditional branch (immediate) */ | |
2199 | disas_uncond_b_imm(s, insn); | |
2200 | break; | |
2201 | case 0x1a: case 0x5a: /* Compare & branch (immediate) */ | |
2202 | disas_comp_b_imm(s, insn); | |
2203 | break; | |
2204 | case 0x1b: case 0x5b: /* Test & branch (immediate) */ | |
2205 | disas_test_b_imm(s, insn); | |
2206 | break; | |
2207 | case 0x2a: /* Conditional branch (immediate) */ | |
2208 | disas_cond_b_imm(s, insn); | |
2209 | break; | |
2210 | case 0x6a: /* Exception generation / System */ | |
2211 | if (insn & (1 << 24)) { | |
08d5e3bd PM |
2212 | if (extract32(insn, 22, 2) == 0) { |
2213 | disas_system(s, insn); | |
2214 | } else { | |
2215 | unallocated_encoding(s); | |
2216 | } | |
ad7ee8a2 CF |
2217 | } else { |
2218 | disas_exc(s, insn); | |
2219 | } | |
2220 | break; | |
2221 | case 0x6b: /* Unconditional branch (register) */ | |
2222 | disas_uncond_b_reg(s, insn); | |
2223 | break; | |
2224 | default: | |
2225 | unallocated_encoding(s); | |
2226 | break; | |
2227 | } | |
2228 | } | |
2229 | ||
5460da50 AB |
2230 | /* |
2231 | * Load/Store exclusive instructions are implemented by remembering | |
2232 | * the value/address loaded, and seeing if these are the same | |
2233 | * when the store is performed. This is not actually the architecturally | |
2234 | * mandated semantics, but it works for typical guest code sequences | |
2235 | * and avoids having to monitor regular stores. | |
2236 | * | |
2237 | * The store exclusive uses the atomic cmpxchg primitives to avoid | |
2238 | * races in multi-threaded linux-user and when MTTCG softmmu is | |
2239 | * enabled. | |
2240 | */ | |
fa2ef212 MM |
2241 | static void gen_load_exclusive(DisasContext *s, int rt, int rt2, |
2242 | TCGv_i64 addr, int size, bool is_pair) | |
2243 | { | |
19514cde RH |
2244 | int idx = get_mem_index(s); |
2245 | TCGMemOp memop = s->be_data; | |
fa2ef212 MM |
2246 | |
2247 | g_assert(size <= 3); | |
fa2ef212 | 2248 | if (is_pair) { |
5460da50 | 2249 | g_assert(size >= 2); |
19514cde RH |
2250 | if (size == 2) { |
2251 | /* The pair must be single-copy atomic for the doubleword. */ | |
4a2fdb78 | 2252 | memop |= MO_64 | MO_ALIGN; |
19514cde RH |
2253 | tcg_gen_qemu_ld_i64(cpu_exclusive_val, addr, idx, memop); |
2254 | if (s->be_data == MO_LE) { | |
2255 | tcg_gen_extract_i64(cpu_reg(s, rt), cpu_exclusive_val, 0, 32); | |
2256 | tcg_gen_extract_i64(cpu_reg(s, rt2), cpu_exclusive_val, 32, 32); | |
2257 | } else { | |
2258 | tcg_gen_extract_i64(cpu_reg(s, rt), cpu_exclusive_val, 32, 32); | |
2259 | tcg_gen_extract_i64(cpu_reg(s, rt2), cpu_exclusive_val, 0, 32); | |
2260 | } | |
2261 | } else { | |
4a2fdb78 AF |
2262 | /* The pair must be single-copy atomic for *each* doubleword, not |
2263 | the entire quadword, however it must be quadword aligned. */ | |
19514cde | 2264 | memop |= MO_64; |
4a2fdb78 AF |
2265 | tcg_gen_qemu_ld_i64(cpu_exclusive_val, addr, idx, |
2266 | memop | MO_ALIGN_16); | |
19514cde RH |
2267 | |
2268 | TCGv_i64 addr2 = tcg_temp_new_i64(); | |
2269 | tcg_gen_addi_i64(addr2, addr, 8); | |
2270 | tcg_gen_qemu_ld_i64(cpu_exclusive_high, addr2, idx, memop); | |
2271 | tcg_temp_free_i64(addr2); | |
2272 | ||
2273 | tcg_gen_mov_i64(cpu_reg(s, rt), cpu_exclusive_val); | |
2274 | tcg_gen_mov_i64(cpu_reg(s, rt2), cpu_exclusive_high); | |
2275 | } | |
2276 | } else { | |
4a2fdb78 | 2277 | memop |= size | MO_ALIGN; |
19514cde RH |
2278 | tcg_gen_qemu_ld_i64(cpu_exclusive_val, addr, idx, memop); |
2279 | tcg_gen_mov_i64(cpu_reg(s, rt), cpu_exclusive_val); | |
fa2ef212 | 2280 | } |
fa2ef212 MM |
2281 | tcg_gen_mov_i64(cpu_exclusive_addr, addr); |
2282 | } | |
2283 | ||
fa2ef212 | 2284 | static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2, |
37e29a64 | 2285 | TCGv_i64 addr, int size, int is_pair) |
fa2ef212 | 2286 | { |
d324b36a PM |
2287 | /* if (env->exclusive_addr == addr && env->exclusive_val == [addr] |
2288 | * && (!is_pair || env->exclusive_high == [addr + datasize])) { | |
2289 | * [addr] = {Rt}; | |
2290 | * if (is_pair) { | |
2291 | * [addr + datasize] = {Rt2}; | |
2292 | * } | |
2293 | * {Rd} = 0; | |
2294 | * } else { | |
2295 | * {Rd} = 1; | |
2296 | * } | |
2297 | * env->exclusive_addr = -1; | |
2298 | */ | |
42a268c2 RH |
2299 | TCGLabel *fail_label = gen_new_label(); |
2300 | TCGLabel *done_label = gen_new_label(); | |
d324b36a PM |
2301 | TCGv_i64 tmp; |
2302 | ||
d324b36a PM |
2303 | tcg_gen_brcond_i64(TCG_COND_NE, addr, cpu_exclusive_addr, fail_label); |
2304 | ||
2305 | tmp = tcg_temp_new_i64(); | |
d324b36a | 2306 | if (is_pair) { |
1dd089d0 | 2307 | if (size == 2) { |
19514cde RH |
2308 | if (s->be_data == MO_LE) { |
2309 | tcg_gen_concat32_i64(tmp, cpu_reg(s, rt), cpu_reg(s, rt2)); | |
2310 | } else { | |
2311 | tcg_gen_concat32_i64(tmp, cpu_reg(s, rt2), cpu_reg(s, rt)); | |
2312 | } | |
37e29a64 RH |
2313 | tcg_gen_atomic_cmpxchg_i64(tmp, cpu_exclusive_addr, |
2314 | cpu_exclusive_val, tmp, | |
1dd089d0 | 2315 | get_mem_index(s), |
955fd0ad | 2316 | MO_64 | MO_ALIGN | s->be_data); |
19514cde | 2317 | tcg_gen_setcond_i64(TCG_COND_NE, tmp, tmp, cpu_exclusive_val); |
62823083 RH |
2318 | } else if (tb_cflags(s->base.tb) & CF_PARALLEL) { |
2319 | if (!HAVE_CMPXCHG128) { | |
2320 | gen_helper_exit_atomic(cpu_env); | |
2321 | s->base.is_jmp = DISAS_NORETURN; | |
2322 | } else if (s->be_data == MO_LE) { | |
2399d4e7 EC |
2323 | gen_helper_paired_cmpxchg64_le_parallel(tmp, cpu_env, |
2324 | cpu_exclusive_addr, | |
2325 | cpu_reg(s, rt), | |
2326 | cpu_reg(s, rt2)); | |
2327 | } else { | |
2399d4e7 EC |
2328 | gen_helper_paired_cmpxchg64_be_parallel(tmp, cpu_env, |
2329 | cpu_exclusive_addr, | |
2330 | cpu_reg(s, rt), | |
2331 | cpu_reg(s, rt2)); | |
2399d4e7 | 2332 | } |
62823083 RH |
2333 | } else if (s->be_data == MO_LE) { |
2334 | gen_helper_paired_cmpxchg64_le(tmp, cpu_env, cpu_exclusive_addr, | |
2335 | cpu_reg(s, rt), cpu_reg(s, rt2)); | |
2336 | } else { | |
2337 | gen_helper_paired_cmpxchg64_be(tmp, cpu_env, cpu_exclusive_addr, | |
2338 | cpu_reg(s, rt), cpu_reg(s, rt2)); | |
1dd089d0 EC |
2339 | } |
2340 | } else { | |
37e29a64 RH |
2341 | tcg_gen_atomic_cmpxchg_i64(tmp, cpu_exclusive_addr, cpu_exclusive_val, |
2342 | cpu_reg(s, rt), get_mem_index(s), | |
1dd089d0 EC |
2343 | size | MO_ALIGN | s->be_data); |
2344 | tcg_gen_setcond_i64(TCG_COND_NE, tmp, tmp, cpu_exclusive_val); | |
d324b36a | 2345 | } |
1dd089d0 EC |
2346 | tcg_gen_mov_i64(cpu_reg(s, rd), tmp); |
2347 | tcg_temp_free_i64(tmp); | |
d324b36a | 2348 | tcg_gen_br(done_label); |
1dd089d0 | 2349 | |
d324b36a PM |
2350 | gen_set_label(fail_label); |
2351 | tcg_gen_movi_i64(cpu_reg(s, rd), 1); | |
2352 | gen_set_label(done_label); | |
2353 | tcg_gen_movi_i64(cpu_exclusive_addr, -1); | |
fa2ef212 | 2354 | } |
fa2ef212 | 2355 | |
44ac14b0 RH |
2356 | static void gen_compare_and_swap(DisasContext *s, int rs, int rt, |
2357 | int rn, int size) | |
2358 | { | |
2359 | TCGv_i64 tcg_rs = cpu_reg(s, rs); | |
2360 | TCGv_i64 tcg_rt = cpu_reg(s, rt); | |
2361 | int memidx = get_mem_index(s); | |
3a471103 | 2362 | TCGv_i64 clean_addr; |
44ac14b0 RH |
2363 | |
2364 | if (rn == 31) { | |
2365 | gen_check_sp_alignment(s); | |
2366 | } | |
3a471103 RH |
2367 | clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn)); |
2368 | tcg_gen_atomic_cmpxchg_i64(tcg_rs, clean_addr, tcg_rs, tcg_rt, memidx, | |
44ac14b0 RH |
2369 | size | MO_ALIGN | s->be_data); |
2370 | } | |
2371 | ||
2372 | static void gen_compare_and_swap_pair(DisasContext *s, int rs, int rt, | |
2373 | int rn, int size) | |
2374 | { | |
2375 | TCGv_i64 s1 = cpu_reg(s, rs); | |
2376 | TCGv_i64 s2 = cpu_reg(s, rs + 1); | |
2377 | TCGv_i64 t1 = cpu_reg(s, rt); | |
2378 | TCGv_i64 t2 = cpu_reg(s, rt + 1); | |
3a471103 | 2379 | TCGv_i64 clean_addr; |
44ac14b0 RH |
2380 | int memidx = get_mem_index(s); |
2381 | ||
2382 | if (rn == 31) { | |
2383 | gen_check_sp_alignment(s); | |
2384 | } | |
3a471103 | 2385 | clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn)); |
44ac14b0 RH |
2386 | |
2387 | if (size == 2) { | |
2388 | TCGv_i64 cmp = tcg_temp_new_i64(); | |
2389 | TCGv_i64 val = tcg_temp_new_i64(); | |
2390 | ||
2391 | if (s->be_data == MO_LE) { | |
2392 | tcg_gen_concat32_i64(val, t1, t2); | |
2393 | tcg_gen_concat32_i64(cmp, s1, s2); | |
2394 | } else { | |
2395 | tcg_gen_concat32_i64(val, t2, t1); | |
2396 | tcg_gen_concat32_i64(cmp, s2, s1); | |
2397 | } | |
2398 | ||
3a471103 | 2399 | tcg_gen_atomic_cmpxchg_i64(cmp, clean_addr, cmp, val, memidx, |
44ac14b0 RH |
2400 | MO_64 | MO_ALIGN | s->be_data); |
2401 | tcg_temp_free_i64(val); | |
2402 | ||
2403 | if (s->be_data == MO_LE) { | |
2404 | tcg_gen_extr32_i64(s1, s2, cmp); | |
2405 | } else { | |
2406 | tcg_gen_extr32_i64(s2, s1, cmp); | |
2407 | } | |
2408 | tcg_temp_free_i64(cmp); | |
2409 | } else if (tb_cflags(s->base.tb) & CF_PARALLEL) { | |
62823083 RH |
2410 | if (HAVE_CMPXCHG128) { |
2411 | TCGv_i32 tcg_rs = tcg_const_i32(rs); | |
2412 | if (s->be_data == MO_LE) { | |
3a471103 RH |
2413 | gen_helper_casp_le_parallel(cpu_env, tcg_rs, |
2414 | clean_addr, t1, t2); | |
62823083 | 2415 | } else { |
3a471103 RH |
2416 | gen_helper_casp_be_parallel(cpu_env, tcg_rs, |
2417 | clean_addr, t1, t2); | |
62823083 RH |
2418 | } |
2419 | tcg_temp_free_i32(tcg_rs); | |
44ac14b0 | 2420 | } else { |
62823083 RH |
2421 | gen_helper_exit_atomic(cpu_env); |
2422 | s->base.is_jmp = DISAS_NORETURN; | |
44ac14b0 | 2423 | } |
44ac14b0 RH |
2424 | } else { |
2425 | TCGv_i64 d1 = tcg_temp_new_i64(); | |
2426 | TCGv_i64 d2 = tcg_temp_new_i64(); | |
2427 | TCGv_i64 a2 = tcg_temp_new_i64(); | |
2428 | TCGv_i64 c1 = tcg_temp_new_i64(); | |
2429 | TCGv_i64 c2 = tcg_temp_new_i64(); | |
2430 | TCGv_i64 zero = tcg_const_i64(0); | |
2431 | ||
2432 | /* Load the two words, in memory order. */ | |
3a471103 | 2433 | tcg_gen_qemu_ld_i64(d1, clean_addr, memidx, |
44ac14b0 | 2434 | MO_64 | MO_ALIGN_16 | s->be_data); |
3a471103 RH |
2435 | tcg_gen_addi_i64(a2, clean_addr, 8); |
2436 | tcg_gen_qemu_ld_i64(d2, clean_addr, memidx, MO_64 | s->be_data); | |
44ac14b0 RH |
2437 | |
2438 | /* Compare the two words, also in memory order. */ | |
2439 | tcg_gen_setcond_i64(TCG_COND_EQ, c1, d1, s1); | |
2440 | tcg_gen_setcond_i64(TCG_COND_EQ, c2, d2, s2); | |
2441 | tcg_gen_and_i64(c2, c2, c1); | |
2442 | ||
2443 | /* If compare equal, write back new data, else write back old data. */ | |
2444 | tcg_gen_movcond_i64(TCG_COND_NE, c1, c2, zero, t1, d1); | |
2445 | tcg_gen_movcond_i64(TCG_COND_NE, c2, c2, zero, t2, d2); | |
3a471103 | 2446 | tcg_gen_qemu_st_i64(c1, clean_addr, memidx, MO_64 | s->be_data); |
44ac14b0 RH |
2447 | tcg_gen_qemu_st_i64(c2, a2, memidx, MO_64 | s->be_data); |
2448 | tcg_temp_free_i64(a2); | |
2449 | tcg_temp_free_i64(c1); | |
2450 | tcg_temp_free_i64(c2); | |
2451 | tcg_temp_free_i64(zero); | |
2452 | ||
2453 | /* Write back the data from memory to Rs. */ | |
2454 | tcg_gen_mov_i64(s1, d1); | |
2455 | tcg_gen_mov_i64(s2, d2); | |
2456 | tcg_temp_free_i64(d1); | |
2457 | tcg_temp_free_i64(d2); | |
2458 | } | |
2459 | } | |
2460 | ||
aaa1f954 EI |
2461 | /* Update the Sixty-Four bit (SF) registersize. This logic is derived |
2462 | * from the ARMv8 specs for LDR (Shared decode for all encodings). | |
2463 | */ | |
2464 | static bool disas_ldst_compute_iss_sf(int size, bool is_signed, int opc) | |
2465 | { | |
2466 | int opc0 = extract32(opc, 0, 1); | |
2467 | int regsize; | |
2468 | ||
2469 | if (is_signed) { | |
2470 | regsize = opc0 ? 32 : 64; | |
2471 | } else { | |
2472 | regsize = size == 3 ? 64 : 32; | |
2473 | } | |
2474 | return regsize == 64; | |
2475 | } | |
2476 | ||
4ce31af4 | 2477 | /* Load/store exclusive |
fa2ef212 MM |
2478 | * |
2479 | * 31 30 29 24 23 22 21 20 16 15 14 10 9 5 4 0 | |
2480 | * +-----+-------------+----+---+----+------+----+-------+------+------+ | |
2481 | * | sz | 0 0 1 0 0 0 | o2 | L | o1 | Rs | o0 | Rt2 | Rn | Rt | | |
2482 | * +-----+-------------+----+---+----+------+----+-------+------+------+ | |
2483 | * | |
2484 | * sz: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64 bit | |
2485 | * L: 0 -> store, 1 -> load | |
2486 | * o2: 0 -> exclusive, 1 -> not | |
2487 | * o1: 0 -> single register, 1 -> register pair | |
2488 | * o0: 1 -> load-acquire/store-release, 0 -> not | |
fa2ef212 | 2489 | */ |
ad7ee8a2 CF |
2490 | static void disas_ldst_excl(DisasContext *s, uint32_t insn) |
2491 | { | |
fa2ef212 MM |
2492 | int rt = extract32(insn, 0, 5); |
2493 | int rn = extract32(insn, 5, 5); | |
2494 | int rt2 = extract32(insn, 10, 5); | |
fa2ef212 | 2495 | int rs = extract32(insn, 16, 5); |
68412d2e RH |
2496 | int is_lasr = extract32(insn, 15, 1); |
2497 | int o2_L_o1_o0 = extract32(insn, 21, 3) * 2 | is_lasr; | |
fa2ef212 | 2498 | int size = extract32(insn, 30, 2); |
3a471103 | 2499 | TCGv_i64 clean_addr; |
fa2ef212 | 2500 | |
68412d2e RH |
2501 | switch (o2_L_o1_o0) { |
2502 | case 0x0: /* STXR */ | |
2503 | case 0x1: /* STLXR */ | |
2504 | if (rn == 31) { | |
2505 | gen_check_sp_alignment(s); | |
2506 | } | |
2507 | if (is_lasr) { | |
2508 | tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); | |
2509 | } | |
3a471103 RH |
2510 | clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn)); |
2511 | gen_store_exclusive(s, rs, rt, rt2, clean_addr, size, false); | |
fa2ef212 | 2512 | return; |
fa2ef212 | 2513 | |
68412d2e RH |
2514 | case 0x4: /* LDXR */ |
2515 | case 0x5: /* LDAXR */ | |
2516 | if (rn == 31) { | |
2517 | gen_check_sp_alignment(s); | |
2518 | } | |
3a471103 | 2519 | clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn)); |
68412d2e | 2520 | s->is_ldex = true; |
3a471103 | 2521 | gen_load_exclusive(s, rt, rt2, clean_addr, size, false); |
68412d2e RH |
2522 | if (is_lasr) { |
2523 | tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); | |
2524 | } | |
2525 | return; | |
fa2ef212 | 2526 | |
2d7137c1 RH |
2527 | case 0x8: /* STLLR */ |
2528 | if (!dc_isar_feature(aa64_lor, s)) { | |
2529 | break; | |
2530 | } | |
2531 | /* StoreLORelease is the same as Store-Release for QEMU. */ | |
2532 | /* fall through */ | |
68412d2e RH |
2533 | case 0x9: /* STLR */ |
2534 | /* Generate ISS for non-exclusive accesses including LASR. */ | |
2535 | if (rn == 31) { | |
2536 | gen_check_sp_alignment(s); | |
2537 | } | |
2538 | tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); | |
3a471103 RH |
2539 | clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn)); |
2540 | do_gpr_st(s, cpu_reg(s, rt), clean_addr, size, true, rt, | |
68412d2e RH |
2541 | disas_ldst_compute_iss_sf(size, false, 0), is_lasr); |
2542 | return; | |
fa2ef212 | 2543 | |
2d7137c1 RH |
2544 | case 0xc: /* LDLAR */ |
2545 | if (!dc_isar_feature(aa64_lor, s)) { | |
2546 | break; | |
2547 | } | |
2548 | /* LoadLOAcquire is the same as Load-Acquire for QEMU. */ | |
2549 | /* fall through */ | |
68412d2e RH |
2550 | case 0xd: /* LDAR */ |
2551 | /* Generate ISS for non-exclusive accesses including LASR. */ | |
2552 | if (rn == 31) { | |
2553 | gen_check_sp_alignment(s); | |
2554 | } | |
3a471103 RH |
2555 | clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn)); |
2556 | do_gpr_ld(s, cpu_reg(s, rt), clean_addr, size, false, false, true, rt, | |
68412d2e RH |
2557 | disas_ldst_compute_iss_sf(size, false, 0), is_lasr); |
2558 | tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); | |
2559 | return; | |
2560 | ||
2561 | case 0x2: case 0x3: /* CASP / STXP */ | |
2562 | if (size & 2) { /* STXP / STLXP */ | |
2563 | if (rn == 31) { | |
2564 | gen_check_sp_alignment(s); | |
ce1bd93f | 2565 | } |
ce1bd93f PK |
2566 | if (is_lasr) { |
2567 | tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); | |
2568 | } | |
3a471103 RH |
2569 | clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn)); |
2570 | gen_store_exclusive(s, rs, rt, rt2, clean_addr, size, true); | |
68412d2e | 2571 | return; |
fa2ef212 | 2572 | } |
44ac14b0 RH |
2573 | if (rt2 == 31 |
2574 | && ((rt | rs) & 1) == 0 | |
962fcbf2 | 2575 | && dc_isar_feature(aa64_atomics, s)) { |
44ac14b0 RH |
2576 | /* CASP / CASPL */ |
2577 | gen_compare_and_swap_pair(s, rs, rt, rn, size | 2); | |
2578 | return; | |
2579 | } | |
68412d2e | 2580 | break; |
aaa1f954 | 2581 | |
44ac14b0 | 2582 | case 0x6: case 0x7: /* CASPA / LDXP */ |
68412d2e RH |
2583 | if (size & 2) { /* LDXP / LDAXP */ |
2584 | if (rn == 31) { | |
2585 | gen_check_sp_alignment(s); | |
ce1bd93f | 2586 | } |
3a471103 | 2587 | clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn)); |
68412d2e | 2588 | s->is_ldex = true; |
3a471103 | 2589 | gen_load_exclusive(s, rt, rt2, clean_addr, size, true); |
ce1bd93f PK |
2590 | if (is_lasr) { |
2591 | tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); | |
2592 | } | |
68412d2e | 2593 | return; |
fa2ef212 | 2594 | } |
44ac14b0 RH |
2595 | if (rt2 == 31 |
2596 | && ((rt | rs) & 1) == 0 | |
962fcbf2 | 2597 | && dc_isar_feature(aa64_atomics, s)) { |
44ac14b0 RH |
2598 | /* CASPA / CASPAL */ |
2599 | gen_compare_and_swap_pair(s, rs, rt, rn, size | 2); | |
2600 | return; | |
fa2ef212 | 2601 | } |
68412d2e RH |
2602 | break; |
2603 | ||
2604 | case 0xa: /* CAS */ | |
2605 | case 0xb: /* CASL */ | |
2606 | case 0xe: /* CASA */ | |
2607 | case 0xf: /* CASAL */ | |
962fcbf2 | 2608 | if (rt2 == 31 && dc_isar_feature(aa64_atomics, s)) { |
44ac14b0 RH |
2609 | gen_compare_and_swap(s, rs, rt, rn, size); |
2610 | return; | |
2611 | } | |
68412d2e | 2612 | break; |
fa2ef212 | 2613 | } |
68412d2e | 2614 | unallocated_encoding(s); |
ad7ee8a2 CF |
2615 | } |
2616 | ||
32b64e86 | 2617 | /* |
4ce31af4 | 2618 | * Load register (literal) |
32b64e86 AG |
2619 | * |
2620 | * 31 30 29 27 26 25 24 23 5 4 0 | |
2621 | * +-----+-------+---+-----+-------------------+-------+ | |
2622 | * | opc | 0 1 1 | V | 0 0 | imm19 | Rt | | |
2623 | * +-----+-------+---+-----+-------------------+-------+ | |
2624 | * | |
2625 | * V: 1 -> vector (simd/fp) | |
2626 | * opc (non-vector): 00 -> 32 bit, 01 -> 64 bit, | |
2627 | * 10-> 32 bit signed, 11 -> prefetch | |
2628 | * opc (vector): 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit (11 unallocated) | |
2629 | */ | |
ad7ee8a2 CF |
2630 | static void disas_ld_lit(DisasContext *s, uint32_t insn) |
2631 | { | |
32b64e86 AG |
2632 | int rt = extract32(insn, 0, 5); |
2633 | int64_t imm = sextract32(insn, 5, 19) << 2; | |
2634 | bool is_vector = extract32(insn, 26, 1); | |
2635 | int opc = extract32(insn, 30, 2); | |
2636 | bool is_signed = false; | |
2637 | int size = 2; | |
3a471103 | 2638 | TCGv_i64 tcg_rt, clean_addr; |
32b64e86 AG |
2639 | |
2640 | if (is_vector) { | |
2641 | if (opc == 3) { | |
2642 | unallocated_encoding(s); | |
2643 | return; | |
2644 | } | |
2645 | size = 2 + opc; | |
8c6afa6a PM |
2646 | if (!fp_access_check(s)) { |
2647 | return; | |
2648 | } | |
32b64e86 AG |
2649 | } else { |
2650 | if (opc == 3) { | |
2651 | /* PRFM (literal) : prefetch */ | |
2652 | return; | |
2653 | } | |
2654 | size = 2 + extract32(opc, 0, 1); | |
2655 | is_signed = extract32(opc, 1, 1); | |
2656 | } | |
2657 | ||
2658 | tcg_rt = cpu_reg(s, rt); | |
2659 | ||
3a471103 | 2660 | clean_addr = tcg_const_i64((s->pc - 4) + imm); |
32b64e86 | 2661 | if (is_vector) { |
3a471103 | 2662 | do_fp_ld(s, rt, clean_addr, size); |
32b64e86 | 2663 | } else { |
aaa1f954 | 2664 | /* Only unsigned 32bit loads target 32bit registers. */ |
173ff585 | 2665 | bool iss_sf = opc != 0; |
aaa1f954 | 2666 | |
3a471103 | 2667 | do_gpr_ld(s, tcg_rt, clean_addr, size, is_signed, false, |
aaa1f954 | 2668 | true, rt, iss_sf, false); |
32b64e86 | 2669 | } |
3a471103 | 2670 | tcg_temp_free_i64(clean_addr); |
ad7ee8a2 CF |
2671 | } |
2672 | ||
4a08d475 | 2673 | /* |
4ce31af4 PM |
2674 | * LDNP (Load Pair - non-temporal hint) |
2675 | * LDP (Load Pair - non vector) | |
2676 | * LDPSW (Load Pair Signed Word - non vector) | |
2677 | * STNP (Store Pair - non-temporal hint) | |
2678 | * STP (Store Pair - non vector) | |
2679 | * LDNP (Load Pair of SIMD&FP - non-temporal hint) | |
2680 | * LDP (Load Pair of SIMD&FP) | |
2681 | * STNP (Store Pair of SIMD&FP - non-temporal hint) | |
2682 | * STP (Store Pair of SIMD&FP) | |
4a08d475 PM |
2683 | * |
2684 | * 31 30 29 27 26 25 24 23 22 21 15 14 10 9 5 4 0 | |
2685 | * +-----+-------+---+---+-------+---+-----------------------------+ | |
2686 | * | opc | 1 0 1 | V | 0 | index | L | imm7 | Rt2 | Rn | Rt | | |
2687 | * +-----+-------+---+---+-------+---+-------+-------+------+------+ | |
2688 | * | |
2689 | * opc: LDP/STP/LDNP/STNP 00 -> 32 bit, 10 -> 64 bit | |
2690 | * LDPSW 01 | |
2691 | * LDP/STP/LDNP/STNP (SIMD) 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit | |
2692 | * V: 0 -> GPR, 1 -> Vector | |
2693 | * idx: 00 -> signed offset with non-temporal hint, 01 -> post-index, | |
2694 | * 10 -> signed offset, 11 -> pre-index | |
2695 | * L: 0 -> Store 1 -> Load | |
2696 | * | |
2697 | * Rt, Rt2 = GPR or SIMD registers to be stored | |
2698 | * Rn = general purpose register containing address | |
2699 | * imm7 = signed offset (multiple of 4 or 8 depending on size) | |
2700 | */ | |
ad7ee8a2 CF |
2701 | static void disas_ldst_pair(DisasContext *s, uint32_t insn) |
2702 | { | |
4a08d475 PM |
2703 | int rt = extract32(insn, 0, 5); |
2704 | int rn = extract32(insn, 5, 5); | |
2705 | int rt2 = extract32(insn, 10, 5); | |
c2ebd862 | 2706 | uint64_t offset = sextract64(insn, 15, 7); |
4a08d475 PM |
2707 | int index = extract32(insn, 23, 2); |
2708 | bool is_vector = extract32(insn, 26, 1); | |
2709 | bool is_load = extract32(insn, 22, 1); | |
2710 | int opc = extract32(insn, 30, 2); | |
2711 | ||
2712 | bool is_signed = false; | |
2713 | bool postindex = false; | |
2714 | bool wback = false; | |
2715 | ||
3a471103 RH |
2716 | TCGv_i64 clean_addr, dirty_addr; |
2717 | ||
4a08d475 PM |
2718 | int size; |
2719 | ||
2720 | if (opc == 3) { | |
2721 | unallocated_encoding(s); | |
2722 | return; | |
2723 | } | |
2724 | ||
2725 | if (is_vector) { | |
2726 | size = 2 + opc; | |
2727 | } else { | |
2728 | size = 2 + extract32(opc, 1, 1); | |
2729 | is_signed = extract32(opc, 0, 1); | |
2730 | if (!is_load && is_signed) { | |
2731 | unallocated_encoding(s); | |
2732 | return; | |
2733 | } | |
2734 | } | |
2735 | ||
2736 | switch (index) { | |
2737 | case 1: /* post-index */ | |
2738 | postindex = true; | |
2739 | wback = true; | |
2740 | break; | |
2741 | case 0: | |
2742 | /* signed offset with "non-temporal" hint. Since we don't emulate | |
2743 | * caches we don't care about hints to the cache system about | |
2744 | * data access patterns, and handle this identically to plain | |
2745 | * signed offset. | |
2746 | */ | |
2747 | if (is_signed) { | |
2748 | /* There is no non-temporal-hint version of LDPSW */ | |
2749 | unallocated_encoding(s); | |
2750 | return; | |
2751 | } | |
2752 | postindex = false; | |
2753 | break; | |
2754 | case 2: /* signed offset, rn not updated */ | |
2755 | postindex = false; | |
2756 | break; | |
2757 | case 3: /* pre-index */ | |
2758 | postindex = false; | |
2759 | wback = true; | |
2760 | break; | |
2761 | } | |
2762 | ||
8c6afa6a PM |
2763 | if (is_vector && !fp_access_check(s)) { |
2764 | return; | |
2765 | } | |
2766 | ||
4a08d475 PM |
2767 | offset <<= size; |
2768 | ||
2769 | if (rn == 31) { | |
2770 | gen_check_sp_alignment(s); | |
2771 | } | |
2772 | ||
3a471103 | 2773 | dirty_addr = read_cpu_reg_sp(s, rn, 1); |
4a08d475 | 2774 | if (!postindex) { |
3a471103 | 2775 | tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); |
4a08d475 | 2776 | } |
3a471103 | 2777 | clean_addr = clean_data_tbi(s, dirty_addr); |
4a08d475 PM |
2778 | |
2779 | if (is_vector) { | |
2780 | if (is_load) { | |
3a471103 | 2781 | do_fp_ld(s, rt, clean_addr, size); |
4a08d475 | 2782 | } else { |
3a471103 | 2783 | do_fp_st(s, rt, clean_addr, size); |
4a08d475 | 2784 | } |
3a471103 | 2785 | tcg_gen_addi_i64(clean_addr, clean_addr, 1 << size); |
4a08d475 | 2786 | if (is_load) { |
3a471103 | 2787 | do_fp_ld(s, rt2, clean_addr, size); |
4a08d475 | 2788 | } else { |
3a471103 | 2789 | do_fp_st(s, rt2, clean_addr, size); |
4a08d475 PM |
2790 | } |
2791 | } else { | |
3e4d91b9 | 2792 | TCGv_i64 tcg_rt = cpu_reg(s, rt); |
4a08d475 | 2793 | TCGv_i64 tcg_rt2 = cpu_reg(s, rt2); |
3e4d91b9 | 2794 | |
4a08d475 | 2795 | if (is_load) { |
3e4d91b9 RH |
2796 | TCGv_i64 tmp = tcg_temp_new_i64(); |
2797 | ||
2798 | /* Do not modify tcg_rt before recognizing any exception | |
2799 | * from the second load. | |
2800 | */ | |
3a471103 | 2801 | do_gpr_ld(s, tmp, clean_addr, size, is_signed, false, |
3e4d91b9 | 2802 | false, 0, false, false); |
3a471103 RH |
2803 | tcg_gen_addi_i64(clean_addr, clean_addr, 1 << size); |
2804 | do_gpr_ld(s, tcg_rt2, clean_addr, size, is_signed, false, | |
aaa1f954 | 2805 | false, 0, false, false); |
3e4d91b9 RH |
2806 | |
2807 | tcg_gen_mov_i64(tcg_rt, tmp); | |
2808 | tcg_temp_free_i64(tmp); | |
4a08d475 | 2809 | } else { |
3a471103 | 2810 | do_gpr_st(s, tcg_rt, clean_addr, size, |
3e4d91b9 | 2811 | false, 0, false, false); |
3a471103 RH |
2812 | tcg_gen_addi_i64(clean_addr, clean_addr, 1 << size); |
2813 | do_gpr_st(s, tcg_rt2, clean_addr, size, | |
aaa1f954 | 2814 | false, 0, false, false); |
4a08d475 PM |
2815 | } |
2816 | } | |
2817 | ||
2818 | if (wback) { | |
2819 | if (postindex) { | |
3a471103 | 2820 | tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); |
4a08d475 | 2821 | } |
3a471103 | 2822 | tcg_gen_mov_i64(cpu_reg_sp(s, rn), dirty_addr); |
4a08d475 | 2823 | } |
ad7ee8a2 CF |
2824 | } |
2825 | ||
a5e94a9d | 2826 | /* |
4ce31af4 PM |
2827 | * Load/store (immediate post-indexed) |
2828 | * Load/store (immediate pre-indexed) | |
2829 | * Load/store (unscaled immediate) | |
a5e94a9d AB |
2830 | * |
2831 | * 31 30 29 27 26 25 24 23 22 21 20 12 11 10 9 5 4 0 | |
2832 | * +----+-------+---+-----+-----+---+--------+-----+------+------+ | |
2833 | * |size| 1 1 1 | V | 0 0 | opc | 0 | imm9 | idx | Rn | Rt | | |
2834 | * +----+-------+---+-----+-----+---+--------+-----+------+------+ | |
2835 | * | |
2836 | * idx = 01 -> post-indexed, 11 pre-indexed, 00 unscaled imm. (no writeback) | |
60510aed | 2837 | 10 -> unprivileged |
a5e94a9d AB |
2838 | * V = 0 -> non-vector |
2839 | * size: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64bit | |
2840 | * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32 | |
2841 | */ | |
cd694521 EI |
2842 | static void disas_ldst_reg_imm9(DisasContext *s, uint32_t insn, |
2843 | int opc, | |
2844 | int size, | |
2845 | int rt, | |
2846 | bool is_vector) | |
a5e94a9d | 2847 | { |
a5e94a9d AB |
2848 | int rn = extract32(insn, 5, 5); |
2849 | int imm9 = sextract32(insn, 12, 9); | |
a5e94a9d AB |
2850 | int idx = extract32(insn, 10, 2); |
2851 | bool is_signed = false; | |
2852 | bool is_store = false; | |
2853 | bool is_extended = false; | |
60510aed | 2854 | bool is_unpriv = (idx == 2); |
aaa1f954 | 2855 | bool iss_valid = !is_vector; |
a5e94a9d AB |
2856 | bool post_index; |
2857 | bool writeback; | |
2858 | ||
3a471103 | 2859 | TCGv_i64 clean_addr, dirty_addr; |
a5e94a9d AB |
2860 | |
2861 | if (is_vector) { | |
2862 | size |= (opc & 2) << 1; | |
60510aed | 2863 | if (size > 4 || is_unpriv) { |
a5e94a9d AB |
2864 | unallocated_encoding(s); |
2865 | return; | |
2866 | } | |
2867 | is_store = ((opc & 1) == 0); | |
8c6afa6a PM |
2868 | if (!fp_access_check(s)) { |
2869 | return; | |
2870 | } | |
a5e94a9d AB |
2871 | } else { |
2872 | if (size == 3 && opc == 2) { | |
2873 | /* PRFM - prefetch */ | |
a80c4256 | 2874 | if (idx != 0) { |
60510aed PM |
2875 | unallocated_encoding(s); |
2876 | return; | |
2877 | } | |
a5e94a9d AB |
2878 | return; |
2879 | } | |
2880 | if (opc == 3 && size > 1) { | |
2881 | unallocated_encoding(s); | |
2882 | return; | |
2883 | } | |
2884 | is_store = (opc == 0); | |
026a19c3 EI |
2885 | is_signed = extract32(opc, 1, 1); |
2886 | is_extended = (size < 3) && extract32(opc, 0, 1); | |
a5e94a9d AB |
2887 | } |
2888 | ||
2889 | switch (idx) { | |
2890 | case 0: | |
60510aed | 2891 | case 2: |
a5e94a9d AB |
2892 | post_index = false; |
2893 | writeback = false; | |
2894 | break; | |
2895 | case 1: | |
2896 | post_index = true; | |
2897 | writeback = true; | |
2898 | break; | |
2899 | case 3: | |
2900 | post_index = false; | |
2901 | writeback = true; | |
2902 | break; | |
5ca66278 EC |
2903 | default: |
2904 | g_assert_not_reached(); | |
a5e94a9d AB |
2905 | } |
2906 | ||
2907 | if (rn == 31) { | |
2908 | gen_check_sp_alignment(s); | |
2909 | } | |
a5e94a9d | 2910 | |
3a471103 | 2911 | dirty_addr = read_cpu_reg_sp(s, rn, 1); |
a5e94a9d | 2912 | if (!post_index) { |
3a471103 | 2913 | tcg_gen_addi_i64(dirty_addr, dirty_addr, imm9); |
a5e94a9d | 2914 | } |
3a471103 | 2915 | clean_addr = clean_data_tbi(s, dirty_addr); |
a5e94a9d AB |
2916 | |
2917 | if (is_vector) { | |
2918 | if (is_store) { | |
3a471103 | 2919 | do_fp_st(s, rt, clean_addr, size); |
a5e94a9d | 2920 | } else { |
3a471103 | 2921 | do_fp_ld(s, rt, clean_addr, size); |
a5e94a9d AB |
2922 | } |
2923 | } else { | |
2924 | TCGv_i64 tcg_rt = cpu_reg(s, rt); | |
579d21cc | 2925 | int memidx = is_unpriv ? get_a64_user_mem_index(s) : get_mem_index(s); |
aaa1f954 | 2926 | bool iss_sf = disas_ldst_compute_iss_sf(size, is_signed, opc); |
60510aed | 2927 | |
a5e94a9d | 2928 | if (is_store) { |
3a471103 | 2929 | do_gpr_st_memidx(s, tcg_rt, clean_addr, size, memidx, |
aaa1f954 | 2930 | iss_valid, rt, iss_sf, false); |
a5e94a9d | 2931 | } else { |
3a471103 | 2932 | do_gpr_ld_memidx(s, tcg_rt, clean_addr, size, |
aaa1f954 EI |
2933 | is_signed, is_extended, memidx, |
2934 | iss_valid, rt, iss_sf, false); | |
a5e94a9d AB |
2935 | } |
2936 | } | |
2937 | ||
2938 | if (writeback) { | |
2939 | TCGv_i64 tcg_rn = cpu_reg_sp(s, rn); | |
2940 | if (post_index) { | |
3a471103 | 2941 | tcg_gen_addi_i64(dirty_addr, dirty_addr, imm9); |
a5e94a9d | 2942 | } |
3a471103 | 2943 | tcg_gen_mov_i64(tcg_rn, dirty_addr); |
a5e94a9d AB |
2944 | } |
2945 | } | |
2946 | ||
229b7a05 | 2947 | /* |
4ce31af4 | 2948 | * Load/store (register offset) |
229b7a05 AB |
2949 | * |
2950 | * 31 30 29 27 26 25 24 23 22 21 20 16 15 13 12 11 10 9 5 4 0 | |
2951 | * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+ | |
2952 | * |size| 1 1 1 | V | 0 0 | opc | 1 | Rm | opt | S| 1 0 | Rn | Rt | | |
2953 | * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+ | |
2954 | * | |
2955 | * For non-vector: | |
2956 | * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit | |
2957 | * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32 | |
2958 | * For vector: | |
2959 | * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated | |
2960 | * opc<0>: 0 -> store, 1 -> load | |
2961 | * V: 1 -> vector/simd | |
2962 | * opt: extend encoding (see DecodeRegExtend) | |
2963 | * S: if S=1 then scale (essentially index by sizeof(size)) | |
2964 | * Rt: register to transfer into/out of | |
2965 | * Rn: address register or SP for base | |
2966 | * Rm: offset register or ZR for offset | |
2967 | */ | |
cd694521 EI |
2968 | static void disas_ldst_reg_roffset(DisasContext *s, uint32_t insn, |
2969 | int opc, | |
2970 | int size, | |
2971 | int rt, | |
2972 | bool is_vector) | |
229b7a05 | 2973 | { |
229b7a05 AB |
2974 | int rn = extract32(insn, 5, 5); |
2975 | int shift = extract32(insn, 12, 1); | |
2976 | int rm = extract32(insn, 16, 5); | |
229b7a05 | 2977 | int opt = extract32(insn, 13, 3); |
229b7a05 AB |
2978 | bool is_signed = false; |
2979 | bool is_store = false; | |
2980 | bool is_extended = false; | |
229b7a05 | 2981 | |
3a471103 | 2982 | TCGv_i64 tcg_rm, clean_addr, dirty_addr; |
229b7a05 AB |
2983 | |
2984 | if (extract32(opt, 1, 1) == 0) { | |
2985 | unallocated_encoding(s); | |
2986 | return; | |
2987 | } | |
2988 | ||
2989 | if (is_vector) { | |
2990 | size |= (opc & 2) << 1; | |
2991 | if (size > 4) { | |
2992 | unallocated_encoding(s); | |
2993 | return; | |
2994 | } | |
2995 | is_store = !extract32(opc, 0, 1); | |
8c6afa6a PM |
2996 | if (!fp_access_check(s)) { |
2997 | return; | |
2998 | } | |
229b7a05 AB |
2999 | } else { |
3000 | if (size == 3 && opc == 2) { | |
3001 | /* PRFM - prefetch */ | |
3002 | return; | |
3003 | } | |
3004 | if (opc == 3 && size > 1) { | |
3005 | unallocated_encoding(s); | |
3006 | return; | |
3007 | } | |
3008 | is_store = (opc == 0); | |
3009 | is_signed = extract32(opc, 1, 1); | |
3010 | is_extended = (size < 3) && extract32(opc, 0, 1); | |
3011 | } | |
3012 | ||
3013 | if (rn == 31) { | |
3014 | gen_check_sp_alignment(s); | |
3015 | } | |
3a471103 | 3016 | dirty_addr = read_cpu_reg_sp(s, rn, 1); |
229b7a05 AB |
3017 | |
3018 | tcg_rm = read_cpu_reg(s, rm, 1); | |
3019 | ext_and_shift_reg(tcg_rm, tcg_rm, opt, shift ? size : 0); | |
3020 | ||
3a471103 RH |
3021 | tcg_gen_add_i64(dirty_addr, dirty_addr, tcg_rm); |
3022 | clean_addr = clean_data_tbi(s, dirty_addr); | |
229b7a05 AB |
3023 | |
3024 | if (is_vector) { | |
3025 | if (is_store) { | |
3a471103 | 3026 | do_fp_st(s, rt, clean_addr, size); |
229b7a05 | 3027 | } else { |
3a471103 | 3028 | do_fp_ld(s, rt, clean_addr, size); |
229b7a05 AB |
3029 | } |
3030 | } else { | |
3031 | TCGv_i64 tcg_rt = cpu_reg(s, rt); | |
aaa1f954 | 3032 | bool iss_sf = disas_ldst_compute_iss_sf(size, is_signed, opc); |
229b7a05 | 3033 | if (is_store) { |
3a471103 | 3034 | do_gpr_st(s, tcg_rt, clean_addr, size, |
aaa1f954 | 3035 | true, rt, iss_sf, false); |
229b7a05 | 3036 | } else { |
3a471103 | 3037 | do_gpr_ld(s, tcg_rt, clean_addr, size, |
aaa1f954 EI |
3038 | is_signed, is_extended, |
3039 | true, rt, iss_sf, false); | |
229b7a05 AB |
3040 | } |
3041 | } | |
3042 | } | |
3043 | ||
d5612f10 | 3044 | /* |
4ce31af4 | 3045 | * Load/store (unsigned immediate) |
d5612f10 AB |
3046 | * |
3047 | * 31 30 29 27 26 25 24 23 22 21 10 9 5 | |
3048 | * +----+-------+---+-----+-----+------------+-------+------+ | |
3049 | * |size| 1 1 1 | V | 0 1 | opc | imm12 | Rn | Rt | | |
3050 | * +----+-------+---+-----+-----+------------+-------+------+ | |
3051 | * | |
3052 | * For non-vector: | |
3053 | * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit | |
3054 | * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32 | |
3055 | * For vector: | |
3056 | * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated | |
3057 | * opc<0>: 0 -> store, 1 -> load | |
3058 | * Rn: base address register (inc SP) | |
3059 | * Rt: target register | |
3060 | */ | |
cd694521 EI |
3061 | static void disas_ldst_reg_unsigned_imm(DisasContext *s, uint32_t insn, |
3062 | int opc, | |
3063 | int size, | |
3064 | int rt, | |
3065 | bool is_vector) | |
d5612f10 | 3066 | { |
d5612f10 AB |
3067 | int rn = extract32(insn, 5, 5); |
3068 | unsigned int imm12 = extract32(insn, 10, 12); | |
d5612f10 AB |
3069 | unsigned int offset; |
3070 | ||
3a471103 | 3071 | TCGv_i64 clean_addr, dirty_addr; |
d5612f10 AB |
3072 | |
3073 | bool is_store; | |
3074 | bool is_signed = false; | |
3075 | bool is_extended = false; | |
3076 | ||
3077 | if (is_vector) { | |
3078 | size |= (opc & 2) << 1; | |
3079 | if (size > 4) { | |
3080 | unallocated_encoding(s); | |
3081 | return; | |
3082 | } | |
3083 | is_store = !extract32(opc, 0, 1); | |
8c6afa6a PM |
3084 | if (!fp_access_check(s)) { |
3085 | return; | |
3086 | } | |
d5612f10 AB |
3087 | } else { |
3088 | if (size == 3 && opc == 2) { | |
3089 | /* PRFM - prefetch */ | |
3090 | return; | |
3091 | } | |
3092 | if (opc == 3 && size > 1) { | |
3093 | unallocated_encoding(s); | |
3094 | return; | |
3095 | } | |
3096 | is_store = (opc == 0); | |
3097 | is_signed = extract32(opc, 1, 1); | |
3098 | is_extended = (size < 3) && extract32(opc, 0, 1); | |
3099 | } | |
3100 | ||
3101 | if (rn == 31) { | |
3102 | gen_check_sp_alignment(s); | |
3103 | } | |
3a471103 | 3104 | dirty_addr = read_cpu_reg_sp(s, rn, 1); |
d5612f10 | 3105 | offset = imm12 << size; |
3a471103 RH |
3106 | tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); |
3107 | clean_addr = clean_data_tbi(s, dirty_addr); | |
d5612f10 AB |
3108 | |
3109 | if (is_vector) { | |
3110 | if (is_store) { | |
3a471103 | 3111 | do_fp_st(s, rt, clean_addr, size); |
d5612f10 | 3112 | } else { |
3a471103 | 3113 | do_fp_ld(s, rt, clean_addr, size); |
d5612f10 AB |
3114 | } |
3115 | } else { | |
3116 | TCGv_i64 tcg_rt = cpu_reg(s, rt); | |
aaa1f954 | 3117 | bool iss_sf = disas_ldst_compute_iss_sf(size, is_signed, opc); |
d5612f10 | 3118 | if (is_store) { |
3a471103 | 3119 | do_gpr_st(s, tcg_rt, clean_addr, size, |
aaa1f954 | 3120 | true, rt, iss_sf, false); |
d5612f10 | 3121 | } else { |
3a471103 | 3122 | do_gpr_ld(s, tcg_rt, clean_addr, size, is_signed, is_extended, |
aaa1f954 | 3123 | true, rt, iss_sf, false); |
d5612f10 AB |
3124 | } |
3125 | } | |
3126 | } | |
3127 | ||
68412d2e RH |
3128 | /* Atomic memory operations |
3129 | * | |
3130 | * 31 30 27 26 24 22 21 16 15 12 10 5 0 | |
3131 | * +------+-------+---+-----+-----+---+----+----+-----+-----+----+-----+ | |
3132 | * | size | 1 1 1 | V | 0 0 | A R | 1 | Rs | o3 | opc | 0 0 | Rn | Rt | | |
3133 | * +------+-------+---+-----+-----+--------+----+-----+-----+----+-----+ | |
3134 | * | |
3135 | * Rt: the result register | |
3136 | * Rn: base address or SP | |
3137 | * Rs: the source register for the operation | |
3138 | * V: vector flag (always 0 as of v8.3) | |
3139 | * A: acquire flag | |
3140 | * R: release flag | |
3141 | */ | |
3142 | static void disas_ldst_atomic(DisasContext *s, uint32_t insn, | |
3143 | int size, int rt, bool is_vector) | |
3144 | { | |
3145 | int rs = extract32(insn, 16, 5); | |
3146 | int rn = extract32(insn, 5, 5); | |
3147 | int o3_opc = extract32(insn, 12, 4); | |
3a471103 | 3148 | TCGv_i64 tcg_rs, clean_addr; |
74608ea4 | 3149 | AtomicThreeOpFn *fn; |
68412d2e | 3150 | |
962fcbf2 | 3151 | if (is_vector || !dc_isar_feature(aa64_atomics, s)) { |
68412d2e RH |
3152 | unallocated_encoding(s); |
3153 | return; | |
3154 | } | |
3155 | switch (o3_opc) { | |
3156 | case 000: /* LDADD */ | |
74608ea4 RH |
3157 | fn = tcg_gen_atomic_fetch_add_i64; |
3158 | break; | |
68412d2e | 3159 | case 001: /* LDCLR */ |
74608ea4 RH |
3160 | fn = tcg_gen_atomic_fetch_and_i64; |
3161 | break; | |
68412d2e | 3162 | case 002: /* LDEOR */ |
74608ea4 RH |
3163 | fn = tcg_gen_atomic_fetch_xor_i64; |
3164 | break; | |
68412d2e | 3165 | case 003: /* LDSET */ |
74608ea4 RH |
3166 | fn = tcg_gen_atomic_fetch_or_i64; |
3167 | break; | |
68412d2e | 3168 | case 004: /* LDSMAX */ |
74608ea4 RH |
3169 | fn = tcg_gen_atomic_fetch_smax_i64; |
3170 | break; | |
68412d2e | 3171 | case 005: /* LDSMIN */ |
74608ea4 RH |
3172 | fn = tcg_gen_atomic_fetch_smin_i64; |
3173 | break; | |
68412d2e | 3174 | case 006: /* LDUMAX */ |
74608ea4 RH |
3175 | fn = tcg_gen_atomic_fetch_umax_i64; |
3176 | break; | |
68412d2e | 3177 | case 007: /* LDUMIN */ |
74608ea4 RH |
3178 | fn = tcg_gen_atomic_fetch_umin_i64; |
3179 | break; | |
68412d2e | 3180 | case 010: /* SWP */ |
74608ea4 RH |
3181 | fn = tcg_gen_atomic_xchg_i64; |
3182 | break; | |
68412d2e RH |
3183 | default: |
3184 | unallocated_encoding(s); | |
3185 | return; | |
3186 | } | |
68412d2e | 3187 | |
74608ea4 RH |
3188 | if (rn == 31) { |
3189 | gen_check_sp_alignment(s); | |
3190 | } | |
3a471103 | 3191 | clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn)); |
74608ea4 RH |
3192 | tcg_rs = read_cpu_reg(s, rs, true); |
3193 | ||
3194 | if (o3_opc == 1) { /* LDCLR */ | |
3195 | tcg_gen_not_i64(tcg_rs, tcg_rs); | |
3196 | } | |
3197 | ||
3198 | /* The tcg atomic primitives are all full barriers. Therefore we | |
3199 | * can ignore the Acquire and Release bits of this instruction. | |
3200 | */ | |
3a471103 | 3201 | fn(cpu_reg(s, rt), clean_addr, tcg_rs, get_mem_index(s), |
74608ea4 | 3202 | s->be_data | size | MO_ALIGN); |
68412d2e RH |
3203 | } |
3204 | ||
bd889f48 RH |
3205 | /* |
3206 | * PAC memory operations | |
3207 | * | |
3208 | * 31 30 27 26 24 22 21 12 11 10 5 0 | |
3209 | * +------+-------+---+-----+-----+---+--------+---+---+----+-----+ | |
3210 | * | size | 1 1 1 | V | 0 0 | M S | 1 | imm9 | W | 1 | Rn | Rt | | |
3211 | * +------+-------+---+-----+-----+---+--------+---+---+----+-----+ | |
3212 | * | |
3213 | * Rt: the result register | |
3214 | * Rn: base address or SP | |
3215 | * V: vector flag (always 0 as of v8.3) | |
3216 | * M: clear for key DA, set for key DB | |
3217 | * W: pre-indexing flag | |
3218 | * S: sign for imm9. | |
3219 | */ | |
3220 | static void disas_ldst_pac(DisasContext *s, uint32_t insn, | |
3221 | int size, int rt, bool is_vector) | |
3222 | { | |
3223 | int rn = extract32(insn, 5, 5); | |
3224 | bool is_wback = extract32(insn, 11, 1); | |
3225 | bool use_key_a = !extract32(insn, 23, 1); | |
3226 | int offset; | |
3a471103 | 3227 | TCGv_i64 clean_addr, dirty_addr, tcg_rt; |
bd889f48 RH |
3228 | |
3229 | if (size != 3 || is_vector || !dc_isar_feature(aa64_pauth, s)) { | |
3230 | unallocated_encoding(s); | |
3231 | return; | |
3232 | } | |
3233 | ||
3234 | if (rn == 31) { | |
3235 | gen_check_sp_alignment(s); | |
3236 | } | |
3a471103 | 3237 | dirty_addr = read_cpu_reg_sp(s, rn, 1); |
bd889f48 RH |
3238 | |
3239 | if (s->pauth_active) { | |
3240 | if (use_key_a) { | |
3a471103 | 3241 | gen_helper_autda(dirty_addr, cpu_env, dirty_addr, cpu_X[31]); |
bd889f48 | 3242 | } else { |
3a471103 | 3243 | gen_helper_autdb(dirty_addr, cpu_env, dirty_addr, cpu_X[31]); |
bd889f48 RH |
3244 | } |
3245 | } | |
3246 | ||
3247 | /* Form the 10-bit signed, scaled offset. */ | |
3248 | offset = (extract32(insn, 22, 1) << 9) | extract32(insn, 12, 9); | |
3249 | offset = sextract32(offset << size, 0, 10 + size); | |
3a471103 | 3250 | tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); |
bd889f48 | 3251 | |
3a471103 RH |
3252 | /* Note that "clean" and "dirty" here refer to TBI not PAC. */ |
3253 | clean_addr = clean_data_tbi(s, dirty_addr); | |
bd889f48 | 3254 | |
3a471103 RH |
3255 | tcg_rt = cpu_reg(s, rt); |
3256 | do_gpr_ld(s, tcg_rt, clean_addr, size, /* is_signed */ false, | |
bd889f48 RH |
3257 | /* extend */ false, /* iss_valid */ !is_wback, |
3258 | /* iss_srt */ rt, /* iss_sf */ true, /* iss_ar */ false); | |
3259 | ||
3260 | if (is_wback) { | |
3a471103 | 3261 | tcg_gen_mov_i64(cpu_reg_sp(s, rn), dirty_addr); |
bd889f48 RH |
3262 | } |
3263 | } | |
3264 | ||
ad7ee8a2 CF |
3265 | /* Load/store register (all forms) */ |
3266 | static void disas_ldst_reg(DisasContext *s, uint32_t insn) | |
3267 | { | |
cd694521 EI |
3268 | int rt = extract32(insn, 0, 5); |
3269 | int opc = extract32(insn, 22, 2); | |
3270 | bool is_vector = extract32(insn, 26, 1); | |
3271 | int size = extract32(insn, 30, 2); | |
3272 | ||
d5612f10 AB |
3273 | switch (extract32(insn, 24, 2)) { |
3274 | case 0: | |
68412d2e | 3275 | if (extract32(insn, 21, 1) == 0) { |
60510aed PM |
3276 | /* Load/store register (unscaled immediate) |
3277 | * Load/store immediate pre/post-indexed | |
3278 | * Load/store register unprivileged | |
3279 | */ | |
cd694521 | 3280 | disas_ldst_reg_imm9(s, insn, opc, size, rt, is_vector); |
68412d2e RH |
3281 | return; |
3282 | } | |
3283 | switch (extract32(insn, 10, 2)) { | |
3284 | case 0: | |
3285 | disas_ldst_atomic(s, insn, size, rt, is_vector); | |
3286 | return; | |
3287 | case 2: | |
3288 | disas_ldst_reg_roffset(s, insn, opc, size, rt, is_vector); | |
3289 | return; | |
bd889f48 RH |
3290 | default: |
3291 | disas_ldst_pac(s, insn, size, rt, is_vector); | |
3292 | return; | |
229b7a05 | 3293 | } |
d5612f10 AB |
3294 | break; |
3295 | case 1: | |
cd694521 | 3296 | disas_ldst_reg_unsigned_imm(s, insn, opc, size, rt, is_vector); |
68412d2e | 3297 | return; |
d5612f10 | 3298 | } |
68412d2e | 3299 | unallocated_encoding(s); |
ad7ee8a2 CF |
3300 | } |
3301 | ||
4ce31af4 | 3302 | /* AdvSIMD load/store multiple structures |
72430bf5 AB |
3303 | * |
3304 | * 31 30 29 23 22 21 16 15 12 11 10 9 5 4 0 | |
3305 | * +---+---+---------------+---+-------------+--------+------+------+------+ | |
3306 | * | 0 | Q | 0 0 1 1 0 0 0 | L | 0 0 0 0 0 0 | opcode | size | Rn | Rt | | |
3307 | * +---+---+---------------+---+-------------+--------+------+------+------+ | |
3308 | * | |
4ce31af4 | 3309 | * AdvSIMD load/store multiple structures (post-indexed) |
72430bf5 AB |
3310 | * |
3311 | * 31 30 29 23 22 21 20 16 15 12 11 10 9 5 4 0 | |
3312 | * +---+---+---------------+---+---+---------+--------+------+------+------+ | |
3313 | * | 0 | Q | 0 0 1 1 0 0 1 | L | 0 | Rm | opcode | size | Rn | Rt | | |
3314 | * +---+---+---------------+---+---+---------+--------+------+------+------+ | |
3315 | * | |
3316 | * Rt: first (or only) SIMD&FP register to be transferred | |
3317 | * Rn: base address or SP | |
3318 | * Rm (post-index only): post-index register (when !31) or size dependent #imm | |
3319 | */ | |
ad7ee8a2 CF |
3320 | static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn) |
3321 | { | |
72430bf5 AB |
3322 | int rt = extract32(insn, 0, 5); |
3323 | int rn = extract32(insn, 5, 5); | |
e1f22081 | 3324 | int rm = extract32(insn, 16, 5); |
72430bf5 AB |
3325 | int size = extract32(insn, 10, 2); |
3326 | int opcode = extract32(insn, 12, 4); | |
3327 | bool is_store = !extract32(insn, 22, 1); | |
3328 | bool is_postidx = extract32(insn, 23, 1); | |
3329 | bool is_q = extract32(insn, 30, 1); | |
3a471103 | 3330 | TCGv_i64 clean_addr, tcg_rn, tcg_ebytes; |
87f9a7f0 | 3331 | TCGMemOp endian = s->be_data; |
72430bf5 | 3332 | |
87f9a7f0 RH |
3333 | int ebytes; /* bytes per element */ |
3334 | int elements; /* elements per vector */ | |
72430bf5 AB |
3335 | int rpt; /* num iterations */ |
3336 | int selem; /* structure elements */ | |
3337 | int r; | |
3338 | ||
3339 | if (extract32(insn, 31, 1) || extract32(insn, 21, 1)) { | |
3340 | unallocated_encoding(s); | |
3341 | return; | |
3342 | } | |
3343 | ||
e1f22081 PM |
3344 | if (!is_postidx && rm != 0) { |
3345 | unallocated_encoding(s); | |
3346 | return; | |
3347 | } | |
3348 | ||
72430bf5 AB |
3349 | /* From the shared decode logic */ |
3350 | switch (opcode) { | |
3351 | case 0x0: | |
3352 | rpt = 1; | |
3353 | selem = 4; | |
3354 | break; | |
3355 | case 0x2: | |
3356 | rpt = 4; | |
3357 | selem = 1; | |
3358 | break; | |
3359 | case 0x4: | |
3360 | rpt = 1; | |
3361 | selem = 3; | |
3362 | break; | |
3363 | case 0x6: | |
3364 | rpt = 3; | |
3365 | selem = 1; | |
3366 | break; | |
3367 | case 0x7: | |
3368 | rpt = 1; | |
3369 | selem = 1; | |
3370 | break; | |
3371 | case 0x8: | |
3372 | rpt = 1; | |
3373 | selem = 2; | |
3374 | break; | |
3375 | case 0xa: | |
3376 | rpt = 2; | |
3377 | selem = 1; | |
3378 | break; | |
3379 | default: | |
3380 | unallocated_encoding(s); | |
3381 | return; | |
3382 | } | |
3383 | ||
3384 | if (size == 3 && !is_q && selem != 1) { | |
3385 | /* reserved */ | |
3386 | unallocated_encoding(s); | |
3387 | return; | |
3388 | } | |
3389 | ||
8c6afa6a PM |
3390 | if (!fp_access_check(s)) { |
3391 | return; | |
3392 | } | |
3393 | ||
72430bf5 AB |
3394 | if (rn == 31) { |
3395 | gen_check_sp_alignment(s); | |
3396 | } | |
3397 | ||
87f9a7f0 RH |
3398 | /* For our purposes, bytes are always little-endian. */ |
3399 | if (size == 0) { | |
3400 | endian = MO_LE; | |
3401 | } | |
3402 | ||
3403 | /* Consecutive little-endian elements from a single register | |
3404 | * can be promoted to a larger little-endian operation. | |
3405 | */ | |
3406 | if (selem == 1 && endian == MO_LE) { | |
3407 | size = 3; | |
3408 | } | |
3409 | ebytes = 1 << size; | |
3410 | elements = (is_q ? 16 : 8) / ebytes; | |
3411 | ||
72430bf5 | 3412 | tcg_rn = cpu_reg_sp(s, rn); |
3a471103 | 3413 | clean_addr = clean_data_tbi(s, tcg_rn); |
a7d8143a | 3414 | tcg_ebytes = tcg_const_i64(ebytes); |
72430bf5 AB |
3415 | |
3416 | for (r = 0; r < rpt; r++) { | |
3417 | int e; | |
3418 | for (e = 0; e < elements; e++) { | |
72430bf5 AB |
3419 | int xs; |
3420 | for (xs = 0; xs < selem; xs++) { | |
87f9a7f0 | 3421 | int tt = (rt + r + xs) % 32; |
72430bf5 | 3422 | if (is_store) { |
3a471103 | 3423 | do_vec_st(s, tt, e, clean_addr, size, endian); |
72430bf5 | 3424 | } else { |
3a471103 | 3425 | do_vec_ld(s, tt, e, clean_addr, size, endian); |
72430bf5 | 3426 | } |
3a471103 | 3427 | tcg_gen_add_i64(clean_addr, clean_addr, tcg_ebytes); |
72430bf5 AB |
3428 | } |
3429 | } | |
3430 | } | |
3a471103 | 3431 | tcg_temp_free_i64(tcg_ebytes); |
72430bf5 | 3432 | |
87f9a7f0 RH |
3433 | if (!is_store) { |
3434 | /* For non-quad operations, setting a slice of the low | |
3435 | * 64 bits of the register clears the high 64 bits (in | |
3436 | * the ARM ARM pseudocode this is implicit in the fact | |
3437 | * that 'rval' is a 64 bit wide variable). | |
3438 | * For quad operations, we might still need to zero the | |
3439 | * high bits of SVE. | |
3440 | */ | |
3441 | for (r = 0; r < rpt * selem; r++) { | |
3442 | int tt = (rt + r) % 32; | |
3443 | clear_vec_high(s, is_q, tt); | |
3444 | } | |
3445 | } | |
3446 | ||
72430bf5 | 3447 | if (is_postidx) { |
72430bf5 | 3448 | if (rm == 31) { |
3a471103 | 3449 | tcg_gen_addi_i64(tcg_rn, tcg_rn, rpt * elements * selem * ebytes); |
72430bf5 AB |
3450 | } else { |
3451 | tcg_gen_add_i64(tcg_rn, tcg_rn, cpu_reg(s, rm)); | |
3452 | } | |
3453 | } | |
ad7ee8a2 CF |
3454 | } |
3455 | ||
4ce31af4 | 3456 | /* AdvSIMD load/store single structure |
df54e47d PM |
3457 | * |
3458 | * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0 | |
3459 | * +---+---+---------------+-----+-----------+-----+---+------+------+------+ | |
3460 | * | 0 | Q | 0 0 1 1 0 1 0 | L R | 0 0 0 0 0 | opc | S | size | Rn | Rt | | |
3461 | * +---+---+---------------+-----+-----------+-----+---+------+------+------+ | |
3462 | * | |
4ce31af4 | 3463 | * AdvSIMD load/store single structure (post-indexed) |
df54e47d PM |
3464 | * |
3465 | * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0 | |
3466 | * +---+---+---------------+-----+-----------+-----+---+------+------+------+ | |
3467 | * | 0 | Q | 0 0 1 1 0 1 1 | L R | Rm | opc | S | size | Rn | Rt | | |
3468 | * +---+---+---------------+-----+-----------+-----+---+------+------+------+ | |
3469 | * | |
3470 | * Rt: first (or only) SIMD&FP register to be transferred | |
3471 | * Rn: base address or SP | |
3472 | * Rm (post-index only): post-index register (when !31) or size dependent #imm | |
3473 | * index = encoded in Q:S:size dependent on size | |
3474 | * | |
3475 | * lane_size = encoded in R, opc | |
3476 | * transfer width = encoded in opc, S, size | |
3477 | */ | |
ad7ee8a2 CF |
3478 | static void disas_ldst_single_struct(DisasContext *s, uint32_t insn) |
3479 | { | |
df54e47d PM |
3480 | int rt = extract32(insn, 0, 5); |
3481 | int rn = extract32(insn, 5, 5); | |
9c72b68a | 3482 | int rm = extract32(insn, 16, 5); |
df54e47d PM |
3483 | int size = extract32(insn, 10, 2); |
3484 | int S = extract32(insn, 12, 1); | |
3485 | int opc = extract32(insn, 13, 3); | |
3486 | int R = extract32(insn, 21, 1); | |
3487 | int is_load = extract32(insn, 22, 1); | |
3488 | int is_postidx = extract32(insn, 23, 1); | |
3489 | int is_q = extract32(insn, 30, 1); | |
3490 | ||
3491 | int scale = extract32(opc, 1, 2); | |
3492 | int selem = (extract32(opc, 0, 1) << 1 | R) + 1; | |
3493 | bool replicate = false; | |
3494 | int index = is_q << 3 | S << 2 | size; | |
3495 | int ebytes, xs; | |
3a471103 | 3496 | TCGv_i64 clean_addr, tcg_rn, tcg_ebytes; |
df54e47d | 3497 | |
9c72b68a PM |
3498 | if (extract32(insn, 31, 1)) { |
3499 | unallocated_encoding(s); | |
3500 | return; | |
3501 | } | |
3502 | if (!is_postidx && rm != 0) { | |
3503 | unallocated_encoding(s); | |
3504 | return; | |
3505 | } | |
3506 | ||
df54e47d PM |
3507 | switch (scale) { |
3508 | case 3: | |
3509 | if (!is_load || S) { | |
3510 | unallocated_encoding(s); | |
3511 | return; | |
3512 | } | |
3513 | scale = size; | |
3514 | replicate = true; | |
3515 | break; | |
3516 | case 0: | |
3517 | break; | |
3518 | case 1: | |
3519 | if (extract32(size, 0, 1)) { | |
3520 | unallocated_encoding(s); | |
3521 | return; | |
3522 | } | |
3523 | index >>= 1; | |
3524 | break; | |
3525 | case 2: | |
3526 | if (extract32(size, 1, 1)) { | |
3527 | unallocated_encoding(s); | |
3528 | return; | |
3529 | } | |
3530 | if (!extract32(size, 0, 1)) { | |
3531 | index >>= 2; | |
3532 | } else { | |
3533 | if (S) { | |
3534 | unallocated_encoding(s); | |
3535 | return; | |
3536 | } | |
3537 | index >>= 3; | |
3538 | scale = 3; | |
3539 | } | |
3540 | break; | |
3541 | default: | |
3542 | g_assert_not_reached(); | |
3543 | } | |
3544 | ||
8c6afa6a PM |
3545 | if (!fp_access_check(s)) { |
3546 | return; | |
3547 | } | |
3548 | ||
df54e47d PM |
3549 | ebytes = 1 << scale; |
3550 | ||
3551 | if (rn == 31) { | |
3552 | gen_check_sp_alignment(s); | |
3553 | } | |
3554 | ||
3555 | tcg_rn = cpu_reg_sp(s, rn); | |
3a471103 | 3556 | clean_addr = clean_data_tbi(s, tcg_rn); |
a7d8143a | 3557 | tcg_ebytes = tcg_const_i64(ebytes); |
df54e47d PM |
3558 | |
3559 | for (xs = 0; xs < selem; xs++) { | |
3560 | if (replicate) { | |
3561 | /* Load and replicate to all elements */ | |
df54e47d PM |
3562 | TCGv_i64 tcg_tmp = tcg_temp_new_i64(); |
3563 | ||
3a471103 | 3564 | tcg_gen_qemu_ld_i64(tcg_tmp, clean_addr, |
aa6489da | 3565 | get_mem_index(s), s->be_data + scale); |
10e0b33c RH |
3566 | tcg_gen_gvec_dup_i64(scale, vec_full_reg_offset(s, rt), |
3567 | (is_q + 1) * 8, vec_full_reg_size(s), | |
3568 | tcg_tmp); | |
df54e47d PM |
3569 | tcg_temp_free_i64(tcg_tmp); |
3570 | } else { | |
3571 | /* Load/store one element per register */ | |
3572 | if (is_load) { | |
3a471103 | 3573 | do_vec_ld(s, rt, index, clean_addr, scale, s->be_data); |
df54e47d | 3574 | } else { |
3a471103 | 3575 | do_vec_st(s, rt, index, clean_addr, scale, s->be_data); |
df54e47d PM |
3576 | } |
3577 | } | |
3a471103 | 3578 | tcg_gen_add_i64(clean_addr, clean_addr, tcg_ebytes); |
df54e47d PM |
3579 | rt = (rt + 1) % 32; |
3580 | } | |
3a471103 | 3581 | tcg_temp_free_i64(tcg_ebytes); |
df54e47d PM |
3582 | |
3583 | if (is_postidx) { | |
df54e47d | 3584 | if (rm == 31) { |
3a471103 | 3585 | tcg_gen_addi_i64(tcg_rn, tcg_rn, selem * ebytes); |
df54e47d PM |
3586 | } else { |
3587 | tcg_gen_add_i64(tcg_rn, tcg_rn, cpu_reg(s, rm)); | |
3588 | } | |
3589 | } | |
ad7ee8a2 CF |
3590 | } |
3591 | ||
4ce31af4 | 3592 | /* Loads and stores */ |
ad7ee8a2 CF |
3593 | static void disas_ldst(DisasContext *s, uint32_t insn) |
3594 | { | |
3595 | switch (extract32(insn, 24, 6)) { | |
3596 | case 0x08: /* Load/store exclusive */ | |
3597 | disas_ldst_excl(s, insn); | |
3598 | break; | |
3599 | case 0x18: case 0x1c: /* Load register (literal) */ | |
3600 | disas_ld_lit(s, insn); | |
3601 | break; | |
3602 | case 0x28: case 0x29: | |
3603 | case 0x2c: case 0x2d: /* Load/store pair (all forms) */ | |
3604 | disas_ldst_pair(s, insn); | |
3605 | break; | |
3606 | case 0x38: case 0x39: | |
3607 | case 0x3c: case 0x3d: /* Load/store register (all forms) */ | |
3608 | disas_ldst_reg(s, insn); | |
3609 | break; | |
3610 | case 0x0c: /* AdvSIMD load/store multiple structures */ | |
3611 | disas_ldst_multiple_struct(s, insn); | |
3612 | break; | |
3613 | case 0x0d: /* AdvSIMD load/store single structure */ | |
3614 | disas_ldst_single_struct(s, insn); | |
3615 | break; | |
3616 | default: | |
3617 | unallocated_encoding(s); | |
3618 | break; | |
3619 | } | |
3620 | } | |
3621 | ||
4ce31af4 | 3622 | /* PC-rel. addressing |
15bfe8b6 AG |
3623 | * 31 30 29 28 24 23 5 4 0 |
3624 | * +----+-------+-----------+-------------------+------+ | |
3625 | * | op | immlo | 1 0 0 0 0 | immhi | Rd | | |
3626 | * +----+-------+-----------+-------------------+------+ | |
3627 | */ | |
ad7ee8a2 CF |
3628 | static void disas_pc_rel_adr(DisasContext *s, uint32_t insn) |
3629 | { | |
15bfe8b6 AG |
3630 | unsigned int page, rd; |
3631 | uint64_t base; | |
037e1d00 | 3632 | uint64_t offset; |
15bfe8b6 AG |
3633 | |
3634 | page = extract32(insn, 31, 1); | |
3635 | /* SignExtend(immhi:immlo) -> offset */ | |
037e1d00 PM |
3636 | offset = sextract64(insn, 5, 19); |
3637 | offset = offset << 2 | extract32(insn, 29, 2); | |
15bfe8b6 AG |
3638 | rd = extract32(insn, 0, 5); |
3639 | base = s->pc - 4; | |
3640 | ||
3641 | if (page) { | |
3642 | /* ADRP (page based) */ | |
3643 | base &= ~0xfff; | |
3644 | offset <<= 12; | |
3645 | } | |
3646 | ||
3647 | tcg_gen_movi_i64(cpu_reg(s, rd), base + offset); | |
ad7ee8a2 CF |
3648 | } |
3649 | ||
b0ff21b4 | 3650 | /* |
4ce31af4 | 3651 | * Add/subtract (immediate) |
b0ff21b4 AB |
3652 | * |
3653 | * 31 30 29 28 24 23 22 21 10 9 5 4 0 | |
3654 | * +--+--+--+-----------+-----+-------------+-----+-----+ | |
3655 | * |sf|op| S| 1 0 0 0 1 |shift| imm12 | Rn | Rd | | |
3656 | * +--+--+--+-----------+-----+-------------+-----+-----+ | |
3657 | * | |
3658 | * sf: 0 -> 32bit, 1 -> 64bit | |
3659 | * op: 0 -> add , 1 -> sub | |
3660 | * S: 1 -> set flags | |
3661 | * shift: 00 -> LSL imm by 0, 01 -> LSL imm by 12 | |
3662 | */ | |
ad7ee8a2 CF |
3663 | static void disas_add_sub_imm(DisasContext *s, uint32_t insn) |
3664 | { | |
b0ff21b4 AB |
3665 | int rd = extract32(insn, 0, 5); |
3666 | int rn = extract32(insn, 5, 5); | |
3667 | uint64_t imm = extract32(insn, 10, 12); | |
3668 | int shift = extract32(insn, 22, 2); | |
3669 | bool setflags = extract32(insn, 29, 1); | |
3670 | bool sub_op = extract32(insn, 30, 1); | |
3671 | bool is_64bit = extract32(insn, 31, 1); | |
3672 | ||
3673 | TCGv_i64 tcg_rn = cpu_reg_sp(s, rn); | |
3674 | TCGv_i64 tcg_rd = setflags ? cpu_reg(s, rd) : cpu_reg_sp(s, rd); | |
3675 | TCGv_i64 tcg_result; | |
3676 | ||
3677 | switch (shift) { | |
3678 | case 0x0: | |
3679 | break; | |
3680 | case 0x1: | |
3681 | imm <<= 12; | |
3682 | break; | |
3683 | default: | |
3684 | unallocated_encoding(s); | |
3685 | return; | |
3686 | } | |
3687 | ||
3688 | tcg_result = tcg_temp_new_i64(); | |
3689 | if (!setflags) { | |
3690 | if (sub_op) { | |
3691 | tcg_gen_subi_i64(tcg_result, tcg_rn, imm); | |
3692 | } else { | |
3693 | tcg_gen_addi_i64(tcg_result, tcg_rn, imm); | |
3694 | } | |
3695 | } else { | |
3696 | TCGv_i64 tcg_imm = tcg_const_i64(imm); | |
3697 | if (sub_op) { | |
3698 | gen_sub_CC(is_64bit, tcg_result, tcg_rn, tcg_imm); | |
3699 | } else { | |
3700 | gen_add_CC(is_64bit, tcg_result, tcg_rn, tcg_imm); | |
3701 | } | |
3702 | tcg_temp_free_i64(tcg_imm); | |
3703 | } | |
3704 | ||
3705 | if (is_64bit) { | |
3706 | tcg_gen_mov_i64(tcg_rd, tcg_result); | |
3707 | } else { | |
3708 | tcg_gen_ext32u_i64(tcg_rd, tcg_result); | |
3709 | } | |
3710 | ||
3711 | tcg_temp_free_i64(tcg_result); | |
ad7ee8a2 CF |
3712 | } |
3713 | ||
71b46089 AG |
3714 | /* The input should be a value in the bottom e bits (with higher |
3715 | * bits zero); returns that value replicated into every element | |
3716 | * of size e in a 64 bit integer. | |
3717 | */ | |
3718 | static uint64_t bitfield_replicate(uint64_t mask, unsigned int e) | |
3719 | { | |
3720 | assert(e != 0); | |
3721 | while (e < 64) { | |
3722 | mask |= mask << e; | |
3723 | e *= 2; | |
3724 | } | |
3725 | return mask; | |
3726 | } | |
3727 | ||
3728 | /* Return a value with the bottom len bits set (where 0 < len <= 64) */ | |
3729 | static inline uint64_t bitmask64(unsigned int length) | |
3730 | { | |
3731 | assert(length > 0 && length <= 64); | |
3732 | return ~0ULL >> (64 - length); | |
3733 | } | |
3734 | ||
3735 | /* Simplified variant of pseudocode DecodeBitMasks() for the case where we | |
3736 | * only require the wmask. Returns false if the imms/immr/immn are a reserved | |
3737 | * value (ie should cause a guest UNDEF exception), and true if they are | |
3738 | * valid, in which case the decoded bit pattern is written to result. | |
3739 | */ | |
8c71baed RH |
3740 | bool logic_imm_decode_wmask(uint64_t *result, unsigned int immn, |
3741 | unsigned int imms, unsigned int immr) | |
71b46089 AG |
3742 | { |
3743 | uint64_t mask; | |
3744 | unsigned e, levels, s, r; | |
3745 | int len; | |
3746 | ||
3747 | assert(immn < 2 && imms < 64 && immr < 64); | |
3748 | ||
3749 | /* The bit patterns we create here are 64 bit patterns which | |
3750 | * are vectors of identical elements of size e = 2, 4, 8, 16, 32 or | |
3751 | * 64 bits each. Each element contains the same value: a run | |
3752 | * of between 1 and e-1 non-zero bits, rotated within the | |
3753 | * element by between 0 and e-1 bits. | |
3754 | * | |
3755 | * The element size and run length are encoded into immn (1 bit) | |
3756 | * and imms (6 bits) as follows: | |
3757 | * 64 bit elements: immn = 1, imms = <length of run - 1> | |
3758 | * 32 bit elements: immn = 0, imms = 0 : <length of run - 1> | |
3759 | * 16 bit elements: immn = 0, imms = 10 : <length of run - 1> | |
3760 | * 8 bit elements: immn = 0, imms = 110 : <length of run - 1> | |
3761 | * 4 bit elements: immn = 0, imms = 1110 : <length of run - 1> | |
3762 | * 2 bit elements: immn = 0, imms = 11110 : <length of run - 1> | |
3763 | * Notice that immn = 0, imms = 11111x is the only combination | |
3764 | * not covered by one of the above options; this is reserved. | |
3765 | * Further, <length of run - 1> all-ones is a reserved pattern. | |
3766 | * | |
3767 | * In all cases the rotation is by immr % e (and immr is 6 bits). | |
3768 | */ | |
3769 | ||
3770 | /* First determine the element size */ | |
3771 | len = 31 - clz32((immn << 6) | (~imms & 0x3f)); | |
3772 | if (len < 1) { | |
3773 | /* This is the immn == 0, imms == 0x11111x case */ | |
3774 | return false; | |
3775 | } | |
3776 | e = 1 << len; | |
3777 | ||
3778 | levels = e - 1; | |
3779 | s = imms & levels; | |
3780 | r = immr & levels; | |
3781 | ||
3782 | if (s == levels) { | |
3783 | /* <length of run - 1> mustn't be all-ones. */ | |
3784 | return false; | |
3785 | } | |
3786 | ||
3787 | /* Create the value of one element: s+1 set bits rotated | |
3788 | * by r within the element (which is e bits wide)... | |
3789 | */ | |
3790 | mask = bitmask64(s + 1); | |
e167adc9 PM |
3791 | if (r) { |
3792 | mask = (mask >> r) | (mask << (e - r)); | |
3793 | mask &= bitmask64(e); | |
3794 | } | |
71b46089 AG |
3795 | /* ...then replicate the element over the whole 64 bit value */ |
3796 | mask = bitfield_replicate(mask, e); | |
3797 | *result = mask; | |
3798 | return true; | |
3799 | } | |
3800 | ||
4ce31af4 | 3801 | /* Logical (immediate) |
71b46089 AG |
3802 | * 31 30 29 28 23 22 21 16 15 10 9 5 4 0 |
3803 | * +----+-----+-------------+---+------+------+------+------+ | |
3804 | * | sf | opc | 1 0 0 1 0 0 | N | immr | imms | Rn | Rd | | |
3805 | * +----+-----+-------------+---+------+------+------+------+ | |
3806 | */ | |
ad7ee8a2 CF |
3807 | static void disas_logic_imm(DisasContext *s, uint32_t insn) |
3808 | { | |
71b46089 AG |
3809 | unsigned int sf, opc, is_n, immr, imms, rn, rd; |
3810 | TCGv_i64 tcg_rd, tcg_rn; | |
3811 | uint64_t wmask; | |
3812 | bool is_and = false; | |
3813 | ||
3814 | sf = extract32(insn, 31, 1); | |
3815 | opc = extract32(insn, 29, 2); | |
3816 | is_n = extract32(insn, 22, 1); | |
3817 | immr = extract32(insn, 16, 6); | |
3818 | imms = extract32(insn, 10, 6); | |
3819 | rn = extract32(insn, 5, 5); | |
3820 | rd = extract32(insn, 0, 5); | |
3821 | ||
3822 | if (!sf && is_n) { | |
3823 | unallocated_encoding(s); | |
3824 | return; | |
3825 | } | |
3826 | ||
3827 | if (opc == 0x3) { /* ANDS */ | |
3828 | tcg_rd = cpu_reg(s, rd); | |
3829 | } else { | |
3830 | tcg_rd = cpu_reg_sp(s, rd); | |
3831 | } | |
3832 | tcg_rn = cpu_reg(s, rn); | |
3833 | ||
3834 | if (!logic_imm_decode_wmask(&wmask, is_n, imms, immr)) { | |
3835 | /* some immediate field values are reserved */ | |
3836 | unallocated_encoding(s); | |
3837 | return; | |
3838 | } | |
3839 | ||
3840 | if (!sf) { | |
3841 | wmask &= 0xffffffff; | |
3842 | } | |
3843 | ||
3844 | switch (opc) { | |
3845 | case 0x3: /* ANDS */ | |
3846 | case 0x0: /* AND */ | |
3847 | tcg_gen_andi_i64(tcg_rd, tcg_rn, wmask); | |
3848 | is_and = true; | |
3849 | break; | |
3850 | case 0x1: /* ORR */ | |
3851 | tcg_gen_ori_i64(tcg_rd, tcg_rn, wmask); | |
3852 | break; | |
3853 | case 0x2: /* EOR */ | |
3854 | tcg_gen_xori_i64(tcg_rd, tcg_rn, wmask); | |
3855 | break; | |
3856 | default: | |
3857 | assert(FALSE); /* must handle all above */ | |
3858 | break; | |
3859 | } | |
3860 | ||
3861 | if (!sf && !is_and) { | |
3862 | /* zero extend final result; we know we can skip this for AND | |
3863 | * since the immediate had the high 32 bits clear. | |
3864 | */ | |
3865 | tcg_gen_ext32u_i64(tcg_rd, tcg_rd); | |
3866 | } | |
3867 | ||
3868 | if (opc == 3) { /* ANDS */ | |
3869 | gen_logic_CC(sf, tcg_rd); | |
3870 | } | |
ad7ee8a2 CF |
3871 | } |
3872 | ||
ed6ec679 | 3873 | /* |
4ce31af4 | 3874 | * Move wide (immediate) |
ed6ec679 AB |
3875 | * |
3876 | * 31 30 29 28 23 22 21 20 5 4 0 | |
3877 | * +--+-----+-------------+-----+----------------+------+ | |
3878 | * |sf| opc | 1 0 0 1 0 1 | hw | imm16 | Rd | | |
3879 | * +--+-----+-------------+-----+----------------+------+ | |
3880 | * | |
3881 | * sf: 0 -> 32 bit, 1 -> 64 bit | |
3882 | * opc: 00 -> N, 10 -> Z, 11 -> K | |
3883 | * hw: shift/16 (0,16, and sf only 32, 48) | |
3884 | */ | |
ad7ee8a2 CF |
3885 | static void disas_movw_imm(DisasContext *s, uint32_t insn) |
3886 | { | |
ed6ec679 AB |
3887 | int rd = extract32(insn, 0, 5); |
3888 | uint64_t imm = extract32(insn, 5, 16); | |
3889 | int sf = extract32(insn, 31, 1); | |
3890 | int opc = extract32(insn, 29, 2); | |
3891 | int pos = extract32(insn, 21, 2) << 4; | |
3892 | TCGv_i64 tcg_rd = cpu_reg(s, rd); | |
3893 | TCGv_i64 tcg_imm; | |
3894 | ||
3895 | if (!sf && (pos >= 32)) { | |
3896 | unallocated_encoding(s); | |
3897 | return; | |
3898 | } | |
3899 | ||
3900 | switch (opc) { | |
3901 | case 0: /* MOVN */ | |
3902 | case 2: /* MOVZ */ | |
3903 | imm <<= pos; | |
3904 | if (opc == 0) { | |
3905 | imm = ~imm; | |
3906 | } | |
3907 | if (!sf) { | |
3908 | imm &= 0xffffffffu; | |
3909 | } | |
3910 | tcg_gen_movi_i64(tcg_rd, imm); | |
3911 | break; | |
3912 | case 3: /* MOVK */ | |
3913 | tcg_imm = tcg_const_i64(imm); | |
3914 | tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_imm, pos, 16); | |
3915 | tcg_temp_free_i64(tcg_imm); | |
3916 | if (!sf) { | |
3917 | tcg_gen_ext32u_i64(tcg_rd, tcg_rd); | |
3918 | } | |
3919 | break; | |
3920 | default: | |
3921 | unallocated_encoding(s); | |
3922 | break; | |
3923 | } | |
ad7ee8a2 CF |
3924 | } |
3925 | ||
4ce31af4 | 3926 | /* Bitfield |
88077742 CF |
3927 | * 31 30 29 28 23 22 21 16 15 10 9 5 4 0 |
3928 | * +----+-----+-------------+---+------+------+------+------+ | |
3929 | * | sf | opc | 1 0 0 1 1 0 | N | immr | imms | Rn | Rd | | |
3930 | * +----+-----+-------------+---+------+------+------+------+ | |
3931 | */ | |
ad7ee8a2 CF |
3932 | static void disas_bitfield(DisasContext *s, uint32_t insn) |
3933 | { | |
88077742 CF |
3934 | unsigned int sf, n, opc, ri, si, rn, rd, bitsize, pos, len; |
3935 | TCGv_i64 tcg_rd, tcg_tmp; | |
3936 | ||
3937 | sf = extract32(insn, 31, 1); | |
3938 | opc = extract32(insn, 29, 2); | |
3939 | n = extract32(insn, 22, 1); | |
3940 | ri = extract32(insn, 16, 6); | |
3941 | si = extract32(insn, 10, 6); | |
3942 | rn = extract32(insn, 5, 5); | |
3943 | rd = extract32(insn, 0, 5); | |
3944 | bitsize = sf ? 64 : 32; | |
3945 | ||
3946 | if (sf != n || ri >= bitsize || si >= bitsize || opc > 2) { | |
3947 | unallocated_encoding(s); | |
3948 | return; | |
3949 | } | |
3950 | ||
3951 | tcg_rd = cpu_reg(s, rd); | |
d3a77b42 RH |
3952 | |
3953 | /* Suppress the zero-extend for !sf. Since RI and SI are constrained | |
3954 | to be smaller than bitsize, we'll never reference data outside the | |
3955 | low 32-bits anyway. */ | |
3956 | tcg_tmp = read_cpu_reg(s, rn, 1); | |
88077742 | 3957 | |
59a71b4c | 3958 | /* Recognize simple(r) extractions. */ |
86c9ab27 | 3959 | if (si >= ri) { |
59a71b4c RH |
3960 | /* Wd<s-r:0> = Wn<s:r> */ |
3961 | len = (si - ri) + 1; | |
3962 | if (opc == 0) { /* SBFM: ASR, SBFX, SXTB, SXTH, SXTW */ | |
3963 | tcg_gen_sextract_i64(tcg_rd, tcg_tmp, ri, len); | |
ef60151b | 3964 | goto done; |
59a71b4c RH |
3965 | } else if (opc == 2) { /* UBFM: UBFX, LSR, UXTB, UXTH */ |
3966 | tcg_gen_extract_i64(tcg_rd, tcg_tmp, ri, len); | |
9924e858 RH |
3967 | return; |
3968 | } | |
59a71b4c RH |
3969 | /* opc == 1, BXFIL fall through to deposit */ |
3970 | tcg_gen_extract_i64(tcg_tmp, tcg_tmp, ri, len); | |
88077742 | 3971 | pos = 0; |
88077742 | 3972 | } else { |
59a71b4c RH |
3973 | /* Handle the ri > si case with a deposit |
3974 | * Wd<32+s-r,32-r> = Wn<s:0> | |
3975 | */ | |
88077742 | 3976 | len = si + 1; |
59a71b4c | 3977 | pos = (bitsize - ri) & (bitsize - 1); |
88077742 CF |
3978 | } |
3979 | ||
59a71b4c RH |
3980 | if (opc == 0 && len < ri) { |
3981 | /* SBFM: sign extend the destination field from len to fill | |
3982 | the balance of the word. Let the deposit below insert all | |
3983 | of those sign bits. */ | |
3984 | tcg_gen_sextract_i64(tcg_tmp, tcg_tmp, 0, len); | |
3985 | len = ri; | |
3986 | } | |
88077742 | 3987 | |
59a71b4c RH |
3988 | if (opc == 1) { /* BFM, BXFIL */ |
3989 | tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_tmp, pos, len); | |
3990 | } else { | |
3991 | /* SBFM or UBFM: We start with zero, and we haven't modified | |
3992 | any bits outside bitsize, therefore the zero-extension | |
3993 | below is unneeded. */ | |
3994 | tcg_gen_deposit_z_i64(tcg_rd, tcg_tmp, pos, len); | |
3995 | return; | |
88077742 CF |
3996 | } |
3997 | ||
ef60151b | 3998 | done: |
88077742 CF |
3999 | if (!sf) { /* zero extend final result */ |
4000 | tcg_gen_ext32u_i64(tcg_rd, tcg_rd); | |
4001 | } | |
ad7ee8a2 CF |
4002 | } |
4003 | ||
4ce31af4 | 4004 | /* Extract |
e801de93 AG |
4005 | * 31 30 29 28 23 22 21 20 16 15 10 9 5 4 0 |
4006 | * +----+------+-------------+---+----+------+--------+------+------+ | |
4007 | * | sf | op21 | 1 0 0 1 1 1 | N | o0 | Rm | imms | Rn | Rd | | |
4008 | * +----+------+-------------+---+----+------+--------+------+------+ | |
4009 | */ | |
ad7ee8a2 CF |
4010 | static void disas_extract(DisasContext *s, uint32_t insn) |
4011 | { | |
e801de93 AG |
4012 | unsigned int sf, n, rm, imm, rn, rd, bitsize, op21, op0; |
4013 | ||
4014 | sf = extract32(insn, 31, 1); | |
4015 | n = extract32(insn, 22, 1); | |
4016 | rm = extract32(insn, 16, 5); | |
4017 | imm = extract32(insn, 10, 6); | |
4018 | rn = extract32(insn, 5, 5); | |
4019 | rd = extract32(insn, 0, 5); | |
4020 | op21 = extract32(insn, 29, 2); | |
4021 | op0 = extract32(insn, 21, 1); | |
4022 | bitsize = sf ? 64 : 32; | |
4023 | ||
4024 | if (sf != n || op21 || op0 || imm >= bitsize) { | |
4025 | unallocated_encoding(s); | |
4026 | } else { | |
4027 | TCGv_i64 tcg_rd, tcg_rm, tcg_rn; | |
4028 | ||
4029 | tcg_rd = cpu_reg(s, rd); | |
4030 | ||
8fb0ad8e | 4031 | if (unlikely(imm == 0)) { |
e801de93 AG |
4032 | /* tcg shl_i32/shl_i64 is undefined for 32/64 bit shifts, |
4033 | * so an extract from bit 0 is a special case. | |
4034 | */ | |
4035 | if (sf) { | |
4036 | tcg_gen_mov_i64(tcg_rd, cpu_reg(s, rm)); | |
4037 | } else { | |
4038 | tcg_gen_ext32u_i64(tcg_rd, cpu_reg(s, rm)); | |
4039 | } | |
8fb0ad8e RH |
4040 | } else if (rm == rn) { /* ROR */ |
4041 | tcg_rm = cpu_reg(s, rm); | |
4042 | if (sf) { | |
4043 | tcg_gen_rotri_i64(tcg_rd, tcg_rm, imm); | |
4044 | } else { | |
4045 | TCGv_i32 tmp = tcg_temp_new_i32(); | |
4046 | tcg_gen_extrl_i64_i32(tmp, tcg_rm); | |
4047 | tcg_gen_rotri_i32(tmp, tmp, imm); | |
4048 | tcg_gen_extu_i32_i64(tcg_rd, tmp); | |
4049 | tcg_temp_free_i32(tmp); | |
4050 | } | |
4051 | } else { | |
4052 | tcg_rm = read_cpu_reg(s, rm, sf); | |
4053 | tcg_rn = read_cpu_reg(s, rn, sf); | |
4054 | tcg_gen_shri_i64(tcg_rm, tcg_rm, imm); | |
4055 | tcg_gen_shli_i64(tcg_rn, tcg_rn, bitsize - imm); | |
4056 | tcg_gen_or_i64(tcg_rd, tcg_rm, tcg_rn); | |
4057 | if (!sf) { | |
4058 | tcg_gen_ext32u_i64(tcg_rd, tcg_rd); | |
4059 | } | |
e801de93 | 4060 | } |
e801de93 | 4061 | } |
ad7ee8a2 CF |
4062 | } |
4063 | ||
4ce31af4 | 4064 | /* Data processing - immediate */ |
ad7ee8a2 CF |
4065 | static void disas_data_proc_imm(DisasContext *s, uint32_t insn) |
4066 | { | |
4067 | switch (extract32(insn, 23, 6)) { | |
4068 | case 0x20: case 0x21: /* PC-rel. addressing */ | |
4069 | disas_pc_rel_adr(s, insn); | |
4070 | break; | |
4071 | case 0x22: case 0x23: /* Add/subtract (immediate) */ | |
4072 | disas_add_sub_imm(s, insn); | |
4073 | break; | |
4074 | case 0x24: /* Logical (immediate) */ | |
4075 | disas_logic_imm(s, insn); | |
4076 | break; | |
4077 | case 0x25: /* Move wide (immediate) */ | |
4078 | disas_movw_imm(s, insn); | |
4079 | break; | |
4080 | case 0x26: /* Bitfield */ | |
4081 | disas_bitfield(s, insn); | |
4082 | break; | |
4083 | case 0x27: /* Extract */ | |
4084 | disas_extract(s, insn); | |
4085 | break; | |
4086 | default: | |
4087 | unallocated_encoding(s); | |
4088 | break; | |
4089 | } | |
4090 | } | |
4091 | ||
832ffa1c AG |
4092 | /* Shift a TCGv src by TCGv shift_amount, put result in dst. |
4093 | * Note that it is the caller's responsibility to ensure that the | |
4094 | * shift amount is in range (ie 0..31 or 0..63) and provide the ARM | |
4095 | * mandated semantics for out of range shifts. | |
4096 | */ | |
4097 | static void shift_reg(TCGv_i64 dst, TCGv_i64 src, int sf, | |
4098 | enum a64_shift_type shift_type, TCGv_i64 shift_amount) | |
4099 | { | |
4100 | switch (shift_type) { | |
4101 | case A64_SHIFT_TYPE_LSL: | |
4102 | tcg_gen_shl_i64(dst, src, shift_amount); | |
4103 | break; | |
4104 | case A64_SHIFT_TYPE_LSR: | |
4105 | tcg_gen_shr_i64(dst, src, shift_amount); | |
4106 | break; | |
4107 | case A64_SHIFT_TYPE_ASR: | |
4108 | if (!sf) { | |
4109 | tcg_gen_ext32s_i64(dst, src); | |
4110 | } | |
4111 | tcg_gen_sar_i64(dst, sf ? src : dst, shift_amount); | |
4112 | break; | |
4113 | case A64_SHIFT_TYPE_ROR: | |
4114 | if (sf) { | |
4115 | tcg_gen_rotr_i64(dst, src, shift_amount); | |
4116 | } else { | |
4117 | TCGv_i32 t0, t1; | |
4118 | t0 = tcg_temp_new_i32(); | |
4119 | t1 = tcg_temp_new_i32(); | |
ecc7b3aa RH |
4120 | tcg_gen_extrl_i64_i32(t0, src); |
4121 | tcg_gen_extrl_i64_i32(t1, shift_amount); | |
832ffa1c AG |
4122 | tcg_gen_rotr_i32(t0, t0, t1); |
4123 | tcg_gen_extu_i32_i64(dst, t0); | |
4124 | tcg_temp_free_i32(t0); | |
4125 | tcg_temp_free_i32(t1); | |
4126 | } | |
4127 | break; | |
4128 | default: | |
4129 | assert(FALSE); /* all shift types should be handled */ | |
4130 | break; | |
4131 | } | |
4132 | ||
4133 | if (!sf) { /* zero extend final result */ | |
4134 | tcg_gen_ext32u_i64(dst, dst); | |
4135 | } | |
4136 | } | |
4137 | ||
4138 | /* Shift a TCGv src by immediate, put result in dst. | |
4139 | * The shift amount must be in range (this should always be true as the | |
4140 | * relevant instructions will UNDEF on bad shift immediates). | |
4141 | */ | |
4142 | static void shift_reg_imm(TCGv_i64 dst, TCGv_i64 src, int sf, | |
4143 | enum a64_shift_type shift_type, unsigned int shift_i) | |
4144 | { | |
4145 | assert(shift_i < (sf ? 64 : 32)); | |
4146 | ||
4147 | if (shift_i == 0) { | |
4148 | tcg_gen_mov_i64(dst, src); | |
4149 | } else { | |
4150 | TCGv_i64 shift_const; | |
4151 | ||
4152 | shift_const = tcg_const_i64(shift_i); | |
4153 | shift_reg(dst, src, sf, shift_type, shift_const); | |
4154 | tcg_temp_free_i64(shift_const); | |
4155 | } | |
4156 | } | |
4157 | ||
4ce31af4 | 4158 | /* Logical (shifted register) |
832ffa1c AG |
4159 | * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0 |
4160 | * +----+-----+-----------+-------+---+------+--------+------+------+ | |
4161 | * | sf | opc | 0 1 0 1 0 | shift | N | Rm | imm6 | Rn | Rd | | |
4162 | * +----+-----+-----------+-------+---+------+--------+------+------+ | |
4163 | */ | |
ad7ee8a2 CF |
4164 | static void disas_logic_reg(DisasContext *s, uint32_t insn) |
4165 | { | |
832ffa1c AG |
4166 | TCGv_i64 tcg_rd, tcg_rn, tcg_rm; |
4167 | unsigned int sf, opc, shift_type, invert, rm, shift_amount, rn, rd; | |
4168 | ||
4169 | sf = extract32(insn, 31, 1); | |
4170 | opc = extract32(insn, 29, 2); | |
4171 | shift_type = extract32(insn, 22, 2); | |
4172 | invert = extract32(insn, 21, 1); | |
4173 | rm = extract32(insn, 16, 5); | |
4174 | shift_amount = extract32(insn, 10, 6); | |
4175 | rn = extract32(insn, 5, 5); | |
4176 | rd = extract32(insn, 0, 5); | |
4177 | ||
4178 | if (!sf && (shift_amount & (1 << 5))) { | |
4179 | unallocated_encoding(s); | |
4180 | return; | |
4181 | } | |
4182 | ||
4183 | tcg_rd = cpu_reg(s, rd); | |
4184 | ||
4185 | if (opc == 1 && shift_amount == 0 && shift_type == 0 && rn == 31) { | |
4186 | /* Unshifted ORR and ORN with WZR/XZR is the standard encoding for | |
4187 | * register-register MOV and MVN, so it is worth special casing. | |
4188 | */ | |
4189 | tcg_rm = cpu_reg(s, rm); | |
4190 | if (invert) { | |
4191 | tcg_gen_not_i64(tcg_rd, tcg_rm); | |
4192 | if (!sf) { | |
4193 | tcg_gen_ext32u_i64(tcg_rd, tcg_rd); | |
4194 | } | |
4195 | } else { | |
4196 | if (sf) { | |
4197 | tcg_gen_mov_i64(tcg_rd, tcg_rm); | |
4198 | } else { | |
4199 | tcg_gen_ext32u_i64(tcg_rd, tcg_rm); | |
4200 | } | |
4201 | } | |
4202 | return; | |
4203 | } | |
4204 | ||
4205 | tcg_rm = read_cpu_reg(s, rm, sf); | |
4206 | ||
4207 | if (shift_amount) { | |
4208 | shift_reg_imm(tcg_rm, tcg_rm, sf, shift_type, shift_amount); | |
4209 | } | |
4210 | ||
4211 | tcg_rn = cpu_reg(s, rn); | |
4212 | ||
4213 | switch (opc | (invert << 2)) { | |
4214 | case 0: /* AND */ | |
4215 | case 3: /* ANDS */ | |
4216 | tcg_gen_and_i64(tcg_rd, tcg_rn, tcg_rm); | |
4217 | break; | |
4218 | case 1: /* ORR */ | |
4219 | tcg_gen_or_i64(tcg_rd, tcg_rn, tcg_rm); | |
4220 | break; | |
4221 | case 2: /* EOR */ | |
4222 | tcg_gen_xor_i64(tcg_rd, tcg_rn, tcg_rm); | |
4223 | break; | |
4224 | case 4: /* BIC */ | |
4225 | case 7: /* BICS */ | |
4226 | tcg_gen_andc_i64(tcg_rd, tcg_rn, tcg_rm); | |
4227 | break; | |
4228 | case 5: /* ORN */ | |
4229 | tcg_gen_orc_i64(tcg_rd, tcg_rn, tcg_rm); | |
4230 | break; | |
4231 | case 6: /* EON */ | |
4232 | tcg_gen_eqv_i64(tcg_rd, tcg_rn, tcg_rm); | |
4233 | break; | |
4234 | default: | |
4235 | assert(FALSE); | |
4236 | break; | |
4237 | } | |
4238 | ||
4239 | if (!sf) { | |
4240 | tcg_gen_ext32u_i64(tcg_rd, tcg_rd); | |
4241 | } | |
4242 | ||
4243 | if (opc == 3) { | |
4244 | gen_logic_CC(sf, tcg_rd); | |
4245 | } | |
ad7ee8a2 CF |
4246 | } |
4247 | ||
b0ff21b4 | 4248 | /* |
4ce31af4 | 4249 | * Add/subtract (extended register) |
b0ff21b4 AB |
4250 | * |
4251 | * 31|30|29|28 24|23 22|21|20 16|15 13|12 10|9 5|4 0| | |
4252 | * +--+--+--+-----------+-----+--+-------+------+------+----+----+ | |
4253 | * |sf|op| S| 0 1 0 1 1 | opt | 1| Rm |option| imm3 | Rn | Rd | | |
4254 | * +--+--+--+-----------+-----+--+-------+------+------+----+----+ | |
4255 | * | |
4256 | * sf: 0 -> 32bit, 1 -> 64bit | |
4257 | * op: 0 -> add , 1 -> sub | |
4258 | * S: 1 -> set flags | |
4259 | * opt: 00 | |
4260 | * option: extension type (see DecodeRegExtend) | |
4261 | * imm3: optional shift to Rm | |
4262 | * | |
4263 | * Rd = Rn + LSL(extend(Rm), amount) | |
4264 | */ | |
ad7ee8a2 CF |
4265 | static void disas_add_sub_ext_reg(DisasContext *s, uint32_t insn) |
4266 | { | |
b0ff21b4 AB |
4267 | int rd = extract32(insn, 0, 5); |
4268 | int rn = extract32(insn, 5, 5); | |
4269 | int imm3 = extract32(insn, 10, 3); | |
4270 | int option = extract32(insn, 13, 3); | |
4271 | int rm = extract32(insn, 16, 5); | |
4f611066 | 4272 | int opt = extract32(insn, 22, 2); |
b0ff21b4 AB |
4273 | bool setflags = extract32(insn, 29, 1); |
4274 | bool sub_op = extract32(insn, 30, 1); | |
4275 | bool sf = extract32(insn, 31, 1); | |
4276 | ||
4277 | TCGv_i64 tcg_rm, tcg_rn; /* temps */ | |
4278 | TCGv_i64 tcg_rd; | |
4279 | TCGv_i64 tcg_result; | |
4280 | ||
4f611066 | 4281 | if (imm3 > 4 || opt != 0) { |
b0ff21b4 AB |
4282 | unallocated_encoding(s); |
4283 | return; | |
4284 | } | |
4285 | ||
4286 | /* non-flag setting ops may use SP */ | |
4287 | if (!setflags) { | |
b0ff21b4 AB |
4288 | tcg_rd = cpu_reg_sp(s, rd); |
4289 | } else { | |
b0ff21b4 AB |
4290 | tcg_rd = cpu_reg(s, rd); |
4291 | } | |
cf4ab1af | 4292 | tcg_rn = read_cpu_reg_sp(s, rn, sf); |
b0ff21b4 AB |
4293 | |
4294 | tcg_rm = read_cpu_reg(s, rm, sf); | |
4295 | ext_and_shift_reg(tcg_rm, tcg_rm, option, imm3); | |
4296 | ||
4297 | tcg_result = tcg_temp_new_i64(); | |
4298 | ||
4299 | if (!setflags) { | |
4300 | if (sub_op) { | |
4301 | tcg_gen_sub_i64(tcg_result, tcg_rn, tcg_rm); | |
4302 | } else { | |
4303 | tcg_gen_add_i64(tcg_result, tcg_rn, tcg_rm); | |
4304 | } | |
4305 | } else { | |
4306 | if (sub_op) { | |
4307 | gen_sub_CC(sf, tcg_result, tcg_rn, tcg_rm); | |
4308 | } else { | |
4309 | gen_add_CC(sf, tcg_result, tcg_rn, tcg_rm); | |
4310 | } | |
4311 | } | |
4312 | ||
4313 | if (sf) { | |
4314 | tcg_gen_mov_i64(tcg_rd, tcg_result); | |
4315 | } else { | |
4316 | tcg_gen_ext32u_i64(tcg_rd, tcg_result); | |
4317 | } | |
4318 | ||
4319 | tcg_temp_free_i64(tcg_result); | |
ad7ee8a2 CF |
4320 | } |
4321 | ||
b0ff21b4 | 4322 | /* |
4ce31af4 | 4323 | * Add/subtract (shifted register) |
b0ff21b4 AB |
4324 | * |
4325 | * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0 | |
4326 | * +--+--+--+-----------+-----+--+-------+---------+------+------+ | |
4327 | * |sf|op| S| 0 1 0 1 1 |shift| 0| Rm | imm6 | Rn | Rd | | |
4328 | * +--+--+--+-----------+-----+--+-------+---------+------+------+ | |
4329 | * | |
4330 | * sf: 0 -> 32bit, 1 -> 64bit | |
4331 | * op: 0 -> add , 1 -> sub | |
4332 | * S: 1 -> set flags | |
4333 | * shift: 00 -> LSL, 01 -> LSR, 10 -> ASR, 11 -> RESERVED | |
4334 | * imm6: Shift amount to apply to Rm before the add/sub | |
4335 | */ | |
ad7ee8a2 CF |
4336 | static void disas_add_sub_reg(DisasContext *s, uint32_t insn) |
4337 | { | |
b0ff21b4 AB |
4338 | int rd = extract32(insn, 0, 5); |
4339 | int rn = extract32(insn, 5, 5); | |
4340 | int imm6 = extract32(insn, 10, 6); | |
4341 | int rm = extract32(insn, 16, 5); | |
4342 | int shift_type = extract32(insn, 22, 2); | |
4343 | bool setflags = extract32(insn, 29, 1); | |
4344 | bool sub_op = extract32(insn, 30, 1); | |
4345 | bool sf = extract32(insn, 31, 1); | |
4346 | ||
4347 | TCGv_i64 tcg_rd = cpu_reg(s, rd); | |
4348 | TCGv_i64 tcg_rn, tcg_rm; | |
4349 | TCGv_i64 tcg_result; | |
4350 | ||
4351 | if ((shift_type == 3) || (!sf && (imm6 > 31))) { | |
4352 | unallocated_encoding(s); | |
4353 | return; | |
4354 | } | |
4355 | ||
4356 | tcg_rn = read_cpu_reg(s, rn, sf); | |
4357 | tcg_rm = read_cpu_reg(s, rm, sf); | |
4358 | ||
4359 | shift_reg_imm(tcg_rm, tcg_rm, sf, shift_type, imm6); | |
4360 | ||
4361 | tcg_result = tcg_temp_new_i64(); | |
4362 | ||
4363 | if (!setflags) { | |
4364 | if (sub_op) { | |
4365 | tcg_gen_sub_i64(tcg_result, tcg_rn, tcg_rm); | |
4366 | } else { | |
4367 | tcg_gen_add_i64(tcg_result, tcg_rn, tcg_rm); | |
4368 | } | |
4369 | } else { | |
4370 | if (sub_op) { | |
4371 | gen_sub_CC(sf, tcg_result, tcg_rn, tcg_rm); | |
4372 | } else { | |
4373 | gen_add_CC(sf, tcg_result, tcg_rn, tcg_rm); | |
4374 | } | |
4375 | } | |
4376 | ||
4377 | if (sf) { | |
4378 | tcg_gen_mov_i64(tcg_rd, tcg_result); | |
4379 | } else { | |
4380 | tcg_gen_ext32u_i64(tcg_rd, tcg_result); | |
4381 | } | |
4382 | ||
4383 | tcg_temp_free_i64(tcg_result); | |
ad7ee8a2 CF |
4384 | } |
4385 | ||
4ce31af4 PM |
4386 | /* Data-processing (3 source) |
4387 | * | |
4388 | * 31 30 29 28 24 23 21 20 16 15 14 10 9 5 4 0 | |
4389 | * +--+------+-----------+------+------+----+------+------+------+ | |
4390 | * |sf| op54 | 1 1 0 1 1 | op31 | Rm | o0 | Ra | Rn | Rd | | |
4391 | * +--+------+-----------+------+------+----+------+------+------+ | |
52c8b9af | 4392 | */ |
ad7ee8a2 CF |
4393 | static void disas_data_proc_3src(DisasContext *s, uint32_t insn) |
4394 | { | |
52c8b9af AG |
4395 | int rd = extract32(insn, 0, 5); |
4396 | int rn = extract32(insn, 5, 5); | |
4397 | int ra = extract32(insn, 10, 5); | |
4398 | int rm = extract32(insn, 16, 5); | |
4399 | int op_id = (extract32(insn, 29, 3) << 4) | | |
4400 | (extract32(insn, 21, 3) << 1) | | |
4401 | extract32(insn, 15, 1); | |
4402 | bool sf = extract32(insn, 31, 1); | |
4403 | bool is_sub = extract32(op_id, 0, 1); | |
4404 | bool is_high = extract32(op_id, 2, 1); | |
4405 | bool is_signed = false; | |
4406 | TCGv_i64 tcg_op1; | |
4407 | TCGv_i64 tcg_op2; | |
4408 | TCGv_i64 tcg_tmp; | |
4409 | ||
4410 | /* Note that op_id is sf:op54:op31:o0 so it includes the 32/64 size flag */ | |
4411 | switch (op_id) { | |
4412 | case 0x42: /* SMADDL */ | |
4413 | case 0x43: /* SMSUBL */ | |
4414 | case 0x44: /* SMULH */ | |
4415 | is_signed = true; | |
4416 | break; | |
4417 | case 0x0: /* MADD (32bit) */ | |
4418 | case 0x1: /* MSUB (32bit) */ | |
4419 | case 0x40: /* MADD (64bit) */ | |
4420 | case 0x41: /* MSUB (64bit) */ | |
4421 | case 0x4a: /* UMADDL */ | |
4422 | case 0x4b: /* UMSUBL */ | |
4423 | case 0x4c: /* UMULH */ | |
4424 | break; | |
4425 | default: | |
4426 | unallocated_encoding(s); | |
4427 | return; | |
4428 | } | |
4429 | ||
4430 | if (is_high) { | |
4431 | TCGv_i64 low_bits = tcg_temp_new_i64(); /* low bits discarded */ | |
4432 | TCGv_i64 tcg_rd = cpu_reg(s, rd); | |
4433 | TCGv_i64 tcg_rn = cpu_reg(s, rn); | |
4434 | TCGv_i64 tcg_rm = cpu_reg(s, rm); | |
4435 | ||
4436 | if (is_signed) { | |
4437 | tcg_gen_muls2_i64(low_bits, tcg_rd, tcg_rn, tcg_rm); | |
4438 | } else { | |
4439 | tcg_gen_mulu2_i64(low_bits, tcg_rd, tcg_rn, tcg_rm); | |
4440 | } | |
4441 | ||
4442 | tcg_temp_free_i64(low_bits); | |
4443 | return; | |
4444 | } | |
4445 | ||
4446 | tcg_op1 = tcg_temp_new_i64(); | |
4447 | tcg_op2 = tcg_temp_new_i64(); | |
4448 | tcg_tmp = tcg_temp_new_i64(); | |
4449 | ||
4450 | if (op_id < 0x42) { | |
4451 | tcg_gen_mov_i64(tcg_op1, cpu_reg(s, rn)); | |
4452 | tcg_gen_mov_i64(tcg_op2, cpu_reg(s, rm)); | |
4453 | } else { | |
4454 | if (is_signed) { | |
4455 | tcg_gen_ext32s_i64(tcg_op1, cpu_reg(s, rn)); | |
4456 | tcg_gen_ext32s_i64(tcg_op2, cpu_reg(s, rm)); | |
4457 | } else { | |
4458 | tcg_gen_ext32u_i64(tcg_op1, cpu_reg(s, rn)); | |
4459 | tcg_gen_ext32u_i64(tcg_op2, cpu_reg(s, rm)); | |
4460 | } | |
4461 | } | |
4462 | ||
4463 | if (ra == 31 && !is_sub) { | |
4464 | /* Special-case MADD with rA == XZR; it is the standard MUL alias */ | |
4465 | tcg_gen_mul_i64(cpu_reg(s, rd), tcg_op1, tcg_op2); | |
4466 | } else { | |
4467 | tcg_gen_mul_i64(tcg_tmp, tcg_op1, tcg_op2); | |
4468 | if (is_sub) { | |
4469 | tcg_gen_sub_i64(cpu_reg(s, rd), cpu_reg(s, ra), tcg_tmp); | |
4470 | } else { | |
4471 | tcg_gen_add_i64(cpu_reg(s, rd), cpu_reg(s, ra), tcg_tmp); | |
4472 | } | |
4473 | } | |
4474 | ||
4475 | if (!sf) { | |
4476 | tcg_gen_ext32u_i64(cpu_reg(s, rd), cpu_reg(s, rd)); | |
4477 | } | |
4478 | ||
4479 | tcg_temp_free_i64(tcg_op1); | |
4480 | tcg_temp_free_i64(tcg_op2); | |
4481 | tcg_temp_free_i64(tcg_tmp); | |
ad7ee8a2 CF |
4482 | } |
4483 | ||
4ce31af4 | 4484 | /* Add/subtract (with carry) |
643dbb07 CF |
4485 | * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 10 9 5 4 0 |
4486 | * +--+--+--+------------------------+------+---------+------+-----+ | |
4487 | * |sf|op| S| 1 1 0 1 0 0 0 0 | rm | opcode2 | Rn | Rd | | |
4488 | * +--+--+--+------------------------+------+---------+------+-----+ | |
4489 | * [000000] | |
4490 | */ | |
4491 | ||
ad7ee8a2 CF |
4492 | static void disas_adc_sbc(DisasContext *s, uint32_t insn) |
4493 | { | |
643dbb07 CF |
4494 | unsigned int sf, op, setflags, rm, rn, rd; |
4495 | TCGv_i64 tcg_y, tcg_rn, tcg_rd; | |
4496 | ||
4497 | if (extract32(insn, 10, 6) != 0) { | |
4498 | unallocated_encoding(s); | |
4499 | return; | |
4500 | } | |
4501 | ||
4502 | sf = extract32(insn, 31, 1); | |
4503 | op = extract32(insn, 30, 1); | |
4504 | setflags = extract32(insn, 29, 1); | |
4505 | rm = extract32(insn, 16, 5); | |
4506 | rn = extract32(insn, 5, 5); | |
4507 | rd = extract32(insn, 0, 5); | |
4508 | ||
4509 | tcg_rd = cpu_reg(s, rd); | |
4510 | tcg_rn = cpu_reg(s, rn); | |
4511 | ||
4512 | if (op) { | |
4513 | tcg_y = new_tmp_a64(s); | |
4514 | tcg_gen_not_i64(tcg_y, cpu_reg(s, rm)); | |
4515 | } else { | |
4516 | tcg_y = cpu_reg(s, rm); | |
4517 | } | |
4518 | ||
4519 | if (setflags) { | |
4520 | gen_adc_CC(sf, tcg_rd, tcg_rn, tcg_y); | |
4521 | } else { | |
4522 | gen_adc(sf, tcg_rd, tcg_rn, tcg_y); | |
4523 | } | |
ad7ee8a2 CF |
4524 | } |
4525 | ||
4ce31af4 | 4526 | /* Conditional compare (immediate / register) |
750813cf CF |
4527 | * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0 |
4528 | * +--+--+--+------------------------+--------+------+----+--+------+--+-----+ | |
4529 | * |sf|op| S| 1 1 0 1 0 0 1 0 |imm5/rm | cond |i/r |o2| Rn |o3|nzcv | | |
4530 | * +--+--+--+------------------------+--------+------+----+--+------+--+-----+ | |
4531 | * [1] y [0] [0] | |
4532 | */ | |
4533 | static void disas_cc(DisasContext *s, uint32_t insn) | |
ad7ee8a2 | 4534 | { |
750813cf | 4535 | unsigned int sf, op, y, cond, rn, nzcv, is_imm; |
7dd03d77 | 4536 | TCGv_i32 tcg_t0, tcg_t1, tcg_t2; |
750813cf | 4537 | TCGv_i64 tcg_tmp, tcg_y, tcg_rn; |
7dd03d77 | 4538 | DisasCompare c; |
ad7ee8a2 | 4539 | |
750813cf CF |
4540 | if (!extract32(insn, 29, 1)) { |
4541 | unallocated_encoding(s); | |
4542 | return; | |
4543 | } | |
4544 | if (insn & (1 << 10 | 1 << 4)) { | |
4545 | unallocated_encoding(s); | |
4546 | return; | |
4547 | } | |
4548 | sf = extract32(insn, 31, 1); | |
4549 | op = extract32(insn, 30, 1); | |
4550 | is_imm = extract32(insn, 11, 1); | |
4551 | y = extract32(insn, 16, 5); /* y = rm (reg) or imm5 (imm) */ | |
4552 | cond = extract32(insn, 12, 4); | |
4553 | rn = extract32(insn, 5, 5); | |
4554 | nzcv = extract32(insn, 0, 4); | |
4555 | ||
7dd03d77 RH |
4556 | /* Set T0 = !COND. */ |
4557 | tcg_t0 = tcg_temp_new_i32(); | |
4558 | arm_test_cc(&c, cond); | |
4559 | tcg_gen_setcondi_i32(tcg_invert_cond(c.cond), tcg_t0, c.value, 0); | |
4560 | arm_free_cc(&c); | |
4561 | ||
4562 | /* Load the arguments for the new comparison. */ | |
750813cf CF |
4563 | if (is_imm) { |
4564 | tcg_y = new_tmp_a64(s); | |
4565 | tcg_gen_movi_i64(tcg_y, y); | |
4566 | } else { | |
4567 | tcg_y = cpu_reg(s, y); | |
4568 | } | |
4569 | tcg_rn = cpu_reg(s, rn); | |
4570 | ||
7dd03d77 | 4571 | /* Set the flags for the new comparison. */ |
750813cf CF |
4572 | tcg_tmp = tcg_temp_new_i64(); |
4573 | if (op) { | |
4574 | gen_sub_CC(sf, tcg_tmp, tcg_rn, tcg_y); | |
4575 | } else { | |
4576 | gen_add_CC(sf, tcg_tmp, tcg_rn, tcg_y); | |
4577 | } | |
4578 | tcg_temp_free_i64(tcg_tmp); | |
4579 | ||
7dd03d77 RH |
4580 | /* If COND was false, force the flags to #nzcv. Compute two masks |
4581 | * to help with this: T1 = (COND ? 0 : -1), T2 = (COND ? -1 : 0). | |
4582 | * For tcg hosts that support ANDC, we can make do with just T1. | |
4583 | * In either case, allow the tcg optimizer to delete any unused mask. | |
4584 | */ | |
4585 | tcg_t1 = tcg_temp_new_i32(); | |
4586 | tcg_t2 = tcg_temp_new_i32(); | |
4587 | tcg_gen_neg_i32(tcg_t1, tcg_t0); | |
4588 | tcg_gen_subi_i32(tcg_t2, tcg_t0, 1); | |
4589 | ||
4590 | if (nzcv & 8) { /* N */ | |
4591 | tcg_gen_or_i32(cpu_NF, cpu_NF, tcg_t1); | |
4592 | } else { | |
4593 | if (TCG_TARGET_HAS_andc_i32) { | |
4594 | tcg_gen_andc_i32(cpu_NF, cpu_NF, tcg_t1); | |
4595 | } else { | |
4596 | tcg_gen_and_i32(cpu_NF, cpu_NF, tcg_t2); | |
4597 | } | |
4598 | } | |
4599 | if (nzcv & 4) { /* Z */ | |
4600 | if (TCG_TARGET_HAS_andc_i32) { | |
4601 | tcg_gen_andc_i32(cpu_ZF, cpu_ZF, tcg_t1); | |
4602 | } else { | |
4603 | tcg_gen_and_i32(cpu_ZF, cpu_ZF, tcg_t2); | |
4604 | } | |
4605 | } else { | |
4606 | tcg_gen_or_i32(cpu_ZF, cpu_ZF, tcg_t0); | |
4607 | } | |
4608 | if (nzcv & 2) { /* C */ | |
4609 | tcg_gen_or_i32(cpu_CF, cpu_CF, tcg_t0); | |
4610 | } else { | |
4611 | if (TCG_TARGET_HAS_andc_i32) { | |
4612 | tcg_gen_andc_i32(cpu_CF, cpu_CF, tcg_t1); | |
4613 | } else { | |
4614 | tcg_gen_and_i32(cpu_CF, cpu_CF, tcg_t2); | |
4615 | } | |
4616 | } | |
4617 | if (nzcv & 1) { /* V */ | |
4618 | tcg_gen_or_i32(cpu_VF, cpu_VF, tcg_t1); | |
4619 | } else { | |
4620 | if (TCG_TARGET_HAS_andc_i32) { | |
4621 | tcg_gen_andc_i32(cpu_VF, cpu_VF, tcg_t1); | |
4622 | } else { | |
4623 | tcg_gen_and_i32(cpu_VF, cpu_VF, tcg_t2); | |
4624 | } | |
750813cf | 4625 | } |
7dd03d77 RH |
4626 | tcg_temp_free_i32(tcg_t0); |
4627 | tcg_temp_free_i32(tcg_t1); | |
4628 | tcg_temp_free_i32(tcg_t2); | |
ad7ee8a2 CF |
4629 | } |
4630 | ||
4ce31af4 | 4631 | /* Conditional select |
e952d8c7 CF |
4632 | * 31 30 29 28 21 20 16 15 12 11 10 9 5 4 0 |
4633 | * +----+----+---+-----------------+------+------+-----+------+------+ | |
4634 | * | sf | op | S | 1 1 0 1 0 1 0 0 | Rm | cond | op2 | Rn | Rd | | |
4635 | * +----+----+---+-----------------+------+------+-----+------+------+ | |
4636 | */ | |
ad7ee8a2 CF |
4637 | static void disas_cond_select(DisasContext *s, uint32_t insn) |
4638 | { | |
e952d8c7 | 4639 | unsigned int sf, else_inv, rm, cond, else_inc, rn, rd; |
259cb684 RH |
4640 | TCGv_i64 tcg_rd, zero; |
4641 | DisasCompare64 c; | |
e952d8c7 CF |
4642 | |
4643 | if (extract32(insn, 29, 1) || extract32(insn, 11, 1)) { | |
4644 | /* S == 1 or op2<1> == 1 */ | |
4645 | unallocated_encoding(s); | |
4646 | return; | |
4647 | } | |
4648 | sf = extract32(insn, 31, 1); | |
4649 | else_inv = extract32(insn, 30, 1); | |
4650 | rm = extract32(insn, 16, 5); | |
4651 | cond = extract32(insn, 12, 4); | |
4652 | else_inc = extract32(insn, 10, 1); | |
4653 | rn = extract32(insn, 5, 5); | |
4654 | rd = extract32(insn, 0, 5); | |
4655 | ||
e952d8c7 CF |
4656 | tcg_rd = cpu_reg(s, rd); |
4657 | ||
259cb684 RH |
4658 | a64_test_cc(&c, cond); |
4659 | zero = tcg_const_i64(0); | |
e952d8c7 | 4660 | |
259cb684 RH |
4661 | if (rn == 31 && rm == 31 && (else_inc ^ else_inv)) { |
4662 | /* CSET & CSETM. */ | |
4663 | tcg_gen_setcond_i64(tcg_invert_cond(c.cond), tcg_rd, c.value, zero); | |
4664 | if (else_inv) { | |
4665 | tcg_gen_neg_i64(tcg_rd, tcg_rd); | |
4666 | } | |
4667 | } else { | |
4668 | TCGv_i64 t_true = cpu_reg(s, rn); | |
4669 | TCGv_i64 t_false = read_cpu_reg(s, rm, 1); | |
e952d8c7 | 4670 | if (else_inv && else_inc) { |
259cb684 | 4671 | tcg_gen_neg_i64(t_false, t_false); |
e952d8c7 | 4672 | } else if (else_inv) { |
259cb684 | 4673 | tcg_gen_not_i64(t_false, t_false); |
e952d8c7 | 4674 | } else if (else_inc) { |
259cb684 | 4675 | tcg_gen_addi_i64(t_false, t_false, 1); |
e952d8c7 | 4676 | } |
259cb684 RH |
4677 | tcg_gen_movcond_i64(c.cond, tcg_rd, c.value, zero, t_true, t_false); |
4678 | } | |
4679 | ||
4680 | tcg_temp_free_i64(zero); | |
4681 | a64_free_cc(&c); | |
4682 | ||
4683 | if (!sf) { | |
4684 | tcg_gen_ext32u_i64(tcg_rd, tcg_rd); | |
e952d8c7 | 4685 | } |
ad7ee8a2 CF |
4686 | } |
4687 | ||
680ead21 CF |
4688 | static void handle_clz(DisasContext *s, unsigned int sf, |
4689 | unsigned int rn, unsigned int rd) | |
4690 | { | |
4691 | TCGv_i64 tcg_rd, tcg_rn; | |
4692 | tcg_rd = cpu_reg(s, rd); | |
4693 | tcg_rn = cpu_reg(s, rn); | |
4694 | ||
4695 | if (sf) { | |
7539a012 | 4696 | tcg_gen_clzi_i64(tcg_rd, tcg_rn, 64); |
680ead21 CF |
4697 | } else { |
4698 | TCGv_i32 tcg_tmp32 = tcg_temp_new_i32(); | |
ecc7b3aa | 4699 | tcg_gen_extrl_i64_i32(tcg_tmp32, tcg_rn); |
7539a012 | 4700 | tcg_gen_clzi_i32(tcg_tmp32, tcg_tmp32, 32); |
680ead21 CF |
4701 | tcg_gen_extu_i32_i64(tcg_rd, tcg_tmp32); |
4702 | tcg_temp_free_i32(tcg_tmp32); | |
4703 | } | |
4704 | } | |
4705 | ||
e80c5020 CF |
4706 | static void handle_cls(DisasContext *s, unsigned int sf, |
4707 | unsigned int rn, unsigned int rd) | |
4708 | { | |
4709 | TCGv_i64 tcg_rd, tcg_rn; | |
4710 | tcg_rd = cpu_reg(s, rd); | |
4711 | tcg_rn = cpu_reg(s, rn); | |
4712 | ||
4713 | if (sf) { | |
bc21dbcc | 4714 | tcg_gen_clrsb_i64(tcg_rd, tcg_rn); |
e80c5020 CF |
4715 | } else { |
4716 | TCGv_i32 tcg_tmp32 = tcg_temp_new_i32(); | |
ecc7b3aa | 4717 | tcg_gen_extrl_i64_i32(tcg_tmp32, tcg_rn); |
bc21dbcc | 4718 | tcg_gen_clrsb_i32(tcg_tmp32, tcg_tmp32); |
e80c5020 CF |
4719 | tcg_gen_extu_i32_i64(tcg_rd, tcg_tmp32); |
4720 | tcg_temp_free_i32(tcg_tmp32); | |
4721 | } | |
4722 | } | |
4723 | ||
82e14b02 AG |
4724 | static void handle_rbit(DisasContext *s, unsigned int sf, |
4725 | unsigned int rn, unsigned int rd) | |
4726 | { | |
4727 | TCGv_i64 tcg_rd, tcg_rn; | |
4728 | tcg_rd = cpu_reg(s, rd); | |
4729 | tcg_rn = cpu_reg(s, rn); | |
4730 | ||
4731 | if (sf) { | |
4732 | gen_helper_rbit64(tcg_rd, tcg_rn); | |
4733 | } else { | |
4734 | TCGv_i32 tcg_tmp32 = tcg_temp_new_i32(); | |
ecc7b3aa | 4735 | tcg_gen_extrl_i64_i32(tcg_tmp32, tcg_rn); |
82e14b02 AG |
4736 | gen_helper_rbit(tcg_tmp32, tcg_tmp32); |
4737 | tcg_gen_extu_i32_i64(tcg_rd, tcg_tmp32); | |
4738 | tcg_temp_free_i32(tcg_tmp32); | |
4739 | } | |
4740 | } | |
4741 | ||
4ce31af4 | 4742 | /* REV with sf==1, opcode==3 ("REV64") */ |
45323209 CF |
4743 | static void handle_rev64(DisasContext *s, unsigned int sf, |
4744 | unsigned int rn, unsigned int rd) | |
4745 | { | |
4746 | if (!sf) { | |
4747 | unallocated_encoding(s); | |
4748 | return; | |
4749 | } | |
4750 | tcg_gen_bswap64_i64(cpu_reg(s, rd), cpu_reg(s, rn)); | |
4751 | } | |
4752 | ||
4ce31af4 PM |
4753 | /* REV with sf==0, opcode==2 |
4754 | * REV32 (sf==1, opcode==2) | |
45323209 CF |
4755 | */ |
4756 | static void handle_rev32(DisasContext *s, unsigned int sf, | |
4757 | unsigned int rn, unsigned int rd) | |
4758 | { | |
4759 | TCGv_i64 tcg_rd = cpu_reg(s, rd); | |
4760 | ||
4761 | if (sf) { | |
4762 | TCGv_i64 tcg_tmp = tcg_temp_new_i64(); | |
4763 | TCGv_i64 tcg_rn = read_cpu_reg(s, rn, sf); | |
4764 | ||
4765 | /* bswap32_i64 requires zero high word */ | |
4766 | tcg_gen_ext32u_i64(tcg_tmp, tcg_rn); | |
4767 | tcg_gen_bswap32_i64(tcg_rd, tcg_tmp); | |
4768 | tcg_gen_shri_i64(tcg_tmp, tcg_rn, 32); | |
4769 | tcg_gen_bswap32_i64(tcg_tmp, tcg_tmp); | |
4770 | tcg_gen_concat32_i64(tcg_rd, tcg_rd, tcg_tmp); | |
4771 | ||
4772 | tcg_temp_free_i64(tcg_tmp); | |
4773 | } else { | |
4774 | tcg_gen_ext32u_i64(tcg_rd, cpu_reg(s, rn)); | |
4775 | tcg_gen_bswap32_i64(tcg_rd, tcg_rd); | |
4776 | } | |
4777 | } | |
4778 | ||
4ce31af4 | 4779 | /* REV16 (opcode==1) */ |
45323209 CF |
4780 | static void handle_rev16(DisasContext *s, unsigned int sf, |
4781 | unsigned int rn, unsigned int rd) | |
4782 | { | |
4783 | TCGv_i64 tcg_rd = cpu_reg(s, rd); | |
4784 | TCGv_i64 tcg_tmp = tcg_temp_new_i64(); | |
4785 | TCGv_i64 tcg_rn = read_cpu_reg(s, rn, sf); | |
abb1066d | 4786 | TCGv_i64 mask = tcg_const_i64(sf ? 0x00ff00ff00ff00ffull : 0x00ff00ff); |
45323209 | 4787 | |
abb1066d RH |
4788 | tcg_gen_shri_i64(tcg_tmp, tcg_rn, 8); |
4789 | tcg_gen_and_i64(tcg_rd, tcg_rn, mask); | |
4790 | tcg_gen_and_i64(tcg_tmp, tcg_tmp, mask); | |
4791 | tcg_gen_shli_i64(tcg_rd, tcg_rd, 8); | |
4792 | tcg_gen_or_i64(tcg_rd, tcg_rd, tcg_tmp); | |
45323209 | 4793 | |
e4256c3c | 4794 | tcg_temp_free_i64(mask); |
45323209 CF |
4795 | tcg_temp_free_i64(tcg_tmp); |
4796 | } | |
4797 | ||
4ce31af4 | 4798 | /* Data-processing (1 source) |
680ead21 CF |
4799 | * 31 30 29 28 21 20 16 15 10 9 5 4 0 |
4800 | * +----+---+---+-----------------+---------+--------+------+------+ | |
4801 | * | sf | 1 | S | 1 1 0 1 0 1 1 0 | opcode2 | opcode | Rn | Rd | | |
4802 | * +----+---+---+-----------------+---------+--------+------+------+ | |
4803 | */ | |
ad7ee8a2 CF |
4804 | static void disas_data_proc_1src(DisasContext *s, uint32_t insn) |
4805 | { | |
18de2813 | 4806 | unsigned int sf, opcode, opcode2, rn, rd; |
95ebd99d | 4807 | TCGv_i64 tcg_rd; |
680ead21 | 4808 | |
18de2813 | 4809 | if (extract32(insn, 29, 1)) { |
680ead21 CF |
4810 | unallocated_encoding(s); |
4811 | return; | |
4812 | } | |
4813 | ||
4814 | sf = extract32(insn, 31, 1); | |
4815 | opcode = extract32(insn, 10, 6); | |
18de2813 | 4816 | opcode2 = extract32(insn, 16, 5); |
680ead21 CF |
4817 | rn = extract32(insn, 5, 5); |
4818 | rd = extract32(insn, 0, 5); | |
4819 | ||
18de2813 RH |
4820 | #define MAP(SF, O2, O1) ((SF) | (O1 << 1) | (O2 << 7)) |
4821 | ||
4822 | switch (MAP(sf, opcode2, opcode)) { | |
4823 | case MAP(0, 0x00, 0x00): /* RBIT */ | |
4824 | case MAP(1, 0x00, 0x00): | |
82e14b02 AG |
4825 | handle_rbit(s, sf, rn, rd); |
4826 | break; | |
18de2813 RH |
4827 | case MAP(0, 0x00, 0x01): /* REV16 */ |
4828 | case MAP(1, 0x00, 0x01): | |
45323209 CF |
4829 | handle_rev16(s, sf, rn, rd); |
4830 | break; | |
18de2813 RH |
4831 | case MAP(0, 0x00, 0x02): /* REV/REV32 */ |
4832 | case MAP(1, 0x00, 0x02): | |
45323209 CF |
4833 | handle_rev32(s, sf, rn, rd); |
4834 | break; | |
18de2813 | 4835 | case MAP(1, 0x00, 0x03): /* REV64 */ |
45323209 | 4836 | handle_rev64(s, sf, rn, rd); |
680ead21 | 4837 | break; |
18de2813 RH |
4838 | case MAP(0, 0x00, 0x04): /* CLZ */ |
4839 | case MAP(1, 0x00, 0x04): | |
680ead21 CF |
4840 | handle_clz(s, sf, rn, rd); |
4841 | break; | |
18de2813 RH |
4842 | case MAP(0, 0x00, 0x05): /* CLS */ |
4843 | case MAP(1, 0x00, 0x05): | |
e80c5020 | 4844 | handle_cls(s, sf, rn, rd); |
680ead21 | 4845 | break; |
95ebd99d RH |
4846 | case MAP(1, 0x01, 0x00): /* PACIA */ |
4847 | if (s->pauth_active) { | |
4848 | tcg_rd = cpu_reg(s, rd); | |
4849 | gen_helper_pacia(tcg_rd, cpu_env, tcg_rd, cpu_reg_sp(s, rn)); | |
4850 | } else if (!dc_isar_feature(aa64_pauth, s)) { | |
4851 | goto do_unallocated; | |
4852 | } | |
4853 | break; | |
4854 | case MAP(1, 0x01, 0x01): /* PACIB */ | |
4855 | if (s->pauth_active) { | |
4856 | tcg_rd = cpu_reg(s, rd); | |
4857 | gen_helper_pacib(tcg_rd, cpu_env, tcg_rd, cpu_reg_sp(s, rn)); | |
4858 | } else if (!dc_isar_feature(aa64_pauth, s)) { | |
4859 | goto do_unallocated; | |
4860 | } | |
4861 | break; | |
4862 | case MAP(1, 0x01, 0x02): /* PACDA */ | |
4863 | if (s->pauth_active) { | |
4864 | tcg_rd = cpu_reg(s, rd); | |
4865 | gen_helper_pacda(tcg_rd, cpu_env, tcg_rd, cpu_reg_sp(s, rn)); | |
4866 | } else if (!dc_isar_feature(aa64_pauth, s)) { | |
4867 | goto do_unallocated; | |
4868 | } | |
4869 | break; | |
4870 | case MAP(1, 0x01, 0x03): /* PACDB */ | |
4871 | if (s->pauth_active) { | |
4872 | tcg_rd = cpu_reg(s, rd); | |
4873 | gen_helper_pacdb(tcg_rd, cpu_env, tcg_rd, cpu_reg_sp(s, rn)); | |
4874 | } else if (!dc_isar_feature(aa64_pauth, s)) { | |
4875 | goto do_unallocated; | |
4876 | } | |
4877 | break; | |
4878 | case MAP(1, 0x01, 0x04): /* AUTIA */ | |
4879 | if (s->pauth_active) { | |
4880 | tcg_rd = cpu_reg(s, rd); | |
4881 | gen_helper_autia(tcg_rd, cpu_env, tcg_rd, cpu_reg_sp(s, rn)); | |
4882 | } else if (!dc_isar_feature(aa64_pauth, s)) { | |
4883 | goto do_unallocated; | |
4884 | } | |
4885 | break; | |
4886 | case MAP(1, 0x01, 0x05): /* AUTIB */ | |
4887 | if (s->pauth_active) { | |
4888 | tcg_rd = cpu_reg(s, rd); | |
4889 | gen_helper_autib(tcg_rd, cpu_env, tcg_rd, cpu_reg_sp(s, rn)); | |
4890 | } else if (!dc_isar_feature(aa64_pauth, s)) { | |
4891 | goto do_unallocated; | |
4892 | } | |
4893 | break; | |
4894 | case MAP(1, 0x01, 0x06): /* AUTDA */ | |
4895 | if (s->pauth_active) { | |
4896 | tcg_rd = cpu_reg(s, rd); | |
4897 | gen_helper_autda(tcg_rd, cpu_env, tcg_rd, cpu_reg_sp(s, rn)); | |
4898 | } else if (!dc_isar_feature(aa64_pauth, s)) { | |
4899 | goto do_unallocated; | |
4900 | } | |
4901 | break; | |
4902 | case MAP(1, 0x01, 0x07): /* AUTDB */ | |
4903 | if (s->pauth_active) { | |
4904 | tcg_rd = cpu_reg(s, rd); | |
4905 | gen_helper_autdb(tcg_rd, cpu_env, tcg_rd, cpu_reg_sp(s, rn)); | |
4906 | } else if (!dc_isar_feature(aa64_pauth, s)) { | |
4907 | goto do_unallocated; | |
4908 | } | |
4909 | break; | |
4910 | case MAP(1, 0x01, 0x08): /* PACIZA */ | |
4911 | if (!dc_isar_feature(aa64_pauth, s) || rn != 31) { | |
4912 | goto do_unallocated; | |
4913 | } else if (s->pauth_active) { | |
4914 | tcg_rd = cpu_reg(s, rd); | |
4915 | gen_helper_pacia(tcg_rd, cpu_env, tcg_rd, new_tmp_a64_zero(s)); | |
4916 | } | |
4917 | break; | |
4918 | case MAP(1, 0x01, 0x09): /* PACIZB */ | |
4919 | if (!dc_isar_feature(aa64_pauth, s) || rn != 31) { | |
4920 | goto do_unallocated; | |
4921 | } else if (s->pauth_active) { | |
4922 | tcg_rd = cpu_reg(s, rd); | |
4923 | gen_helper_pacib(tcg_rd, cpu_env, tcg_rd, new_tmp_a64_zero(s)); | |
4924 | } | |
4925 | break; | |
4926 | case MAP(1, 0x01, 0x0a): /* PACDZA */ | |
4927 | if (!dc_isar_feature(aa64_pauth, s) || rn != 31) { | |
4928 | goto do_unallocated; | |
4929 | } else if (s->pauth_active) { | |
4930 | tcg_rd = cpu_reg(s, rd); | |
4931 | gen_helper_pacda(tcg_rd, cpu_env, tcg_rd, new_tmp_a64_zero(s)); | |
4932 | } | |
4933 | break; | |
4934 | case MAP(1, 0x01, 0x0b): /* PACDZB */ | |
4935 | if (!dc_isar_feature(aa64_pauth, s) || rn != 31) { | |
4936 | goto do_unallocated; | |
4937 | } else if (s->pauth_active) { | |
4938 | tcg_rd = cpu_reg(s, rd); | |
4939 | gen_helper_pacdb(tcg_rd, cpu_env, tcg_rd, new_tmp_a64_zero(s)); | |
4940 | } | |
4941 | break; | |
4942 | case MAP(1, 0x01, 0x0c): /* AUTIZA */ | |
4943 | if (!dc_isar_feature(aa64_pauth, s) || rn != 31) { | |
4944 | goto do_unallocated; | |
4945 | } else if (s->pauth_active) { | |
4946 | tcg_rd = cpu_reg(s, rd); | |
4947 | gen_helper_autia(tcg_rd, cpu_env, tcg_rd, new_tmp_a64_zero(s)); | |
4948 | } | |
4949 | break; | |
4950 | case MAP(1, 0x01, 0x0d): /* AUTIZB */ | |
4951 | if (!dc_isar_feature(aa64_pauth, s) || rn != 31) { | |
4952 | goto do_unallocated; | |
4953 | } else if (s->pauth_active) { | |
4954 | tcg_rd = cpu_reg(s, rd); | |
4955 | gen_helper_autib(tcg_rd, cpu_env, tcg_rd, new_tmp_a64_zero(s)); | |
4956 | } | |
4957 | break; | |
4958 | case MAP(1, 0x01, 0x0e): /* AUTDZA */ | |
4959 | if (!dc_isar_feature(aa64_pauth, s) || rn != 31) { | |
4960 | goto do_unallocated; | |
4961 | } else if (s->pauth_active) { | |
4962 | tcg_rd = cpu_reg(s, rd); | |
4963 | gen_helper_autda(tcg_rd, cpu_env, tcg_rd, new_tmp_a64_zero(s)); | |
4964 | } | |
4965 | break; | |
4966 | case MAP(1, 0x01, 0x0f): /* AUTDZB */ | |
4967 | if (!dc_isar_feature(aa64_pauth, s) || rn != 31) { | |
4968 | goto do_unallocated; | |
4969 | } else if (s->pauth_active) { | |
4970 | tcg_rd = cpu_reg(s, rd); | |
4971 | gen_helper_autdb(tcg_rd, cpu_env, tcg_rd, new_tmp_a64_zero(s)); | |
4972 | } | |
4973 | break; | |
4974 | case MAP(1, 0x01, 0x10): /* XPACI */ | |
4975 | if (!dc_isar_feature(aa64_pauth, s) || rn != 31) { | |
4976 | goto do_unallocated; | |
4977 | } else if (s->pauth_active) { | |
4978 | tcg_rd = cpu_reg(s, rd); | |
4979 | gen_helper_xpaci(tcg_rd, cpu_env, tcg_rd); | |
4980 | } | |
4981 | break; | |
4982 | case MAP(1, 0x01, 0x11): /* XPACD */ | |
4983 | if (!dc_isar_feature(aa64_pauth, s) || rn != 31) { | |
4984 | goto do_unallocated; | |
4985 | } else if (s->pauth_active) { | |
4986 | tcg_rd = cpu_reg(s, rd); | |
4987 | gen_helper_xpacd(tcg_rd, cpu_env, tcg_rd); | |
4988 | } | |
4989 | break; | |
18de2813 | 4990 | default: |
95ebd99d | 4991 | do_unallocated: |
18de2813 RH |
4992 | unallocated_encoding(s); |
4993 | break; | |
680ead21 | 4994 | } |
18de2813 RH |
4995 | |
4996 | #undef MAP | |
ad7ee8a2 CF |
4997 | } |
4998 | ||
8220e911 AG |
4999 | static void handle_div(DisasContext *s, bool is_signed, unsigned int sf, |
5000 | unsigned int rm, unsigned int rn, unsigned int rd) | |
5001 | { | |
5002 | TCGv_i64 tcg_n, tcg_m, tcg_rd; | |
5003 | tcg_rd = cpu_reg(s, rd); | |
5004 | ||
5005 | if (!sf && is_signed) { | |
5006 | tcg_n = new_tmp_a64(s); | |
5007 | tcg_m = new_tmp_a64(s); | |
5008 | tcg_gen_ext32s_i64(tcg_n, cpu_reg(s, rn)); | |
5009 | tcg_gen_ext32s_i64(tcg_m, cpu_reg(s, rm)); | |
5010 | } else { | |
5011 | tcg_n = read_cpu_reg(s, rn, sf); | |
5012 | tcg_m = read_cpu_reg(s, rm, sf); | |
5013 | } | |
5014 | ||
5015 | if (is_signed) { | |
5016 | gen_helper_sdiv64(tcg_rd, tcg_n, tcg_m); | |
5017 | } else { | |
5018 | gen_helper_udiv64(tcg_rd, tcg_n, tcg_m); | |
5019 | } | |
5020 | ||
5021 | if (!sf) { /* zero extend final result */ | |
5022 | tcg_gen_ext32u_i64(tcg_rd, tcg_rd); | |
5023 | } | |
5024 | } | |
5025 | ||
4ce31af4 | 5026 | /* LSLV, LSRV, ASRV, RORV */ |
6c1adc91 AG |
5027 | static void handle_shift_reg(DisasContext *s, |
5028 | enum a64_shift_type shift_type, unsigned int sf, | |
5029 | unsigned int rm, unsigned int rn, unsigned int rd) | |
5030 | { | |
5031 | TCGv_i64 tcg_shift = tcg_temp_new_i64(); | |
5032 | TCGv_i64 tcg_rd = cpu_reg(s, rd); | |
5033 | TCGv_i64 tcg_rn = read_cpu_reg(s, rn, sf); | |
5034 | ||
5035 | tcg_gen_andi_i64(tcg_shift, cpu_reg(s, rm), sf ? 63 : 31); | |
5036 | shift_reg(tcg_rd, tcg_rn, sf, shift_type, tcg_shift); | |
5037 | tcg_temp_free_i64(tcg_shift); | |
5038 | } | |
5039 | ||
130f2e7d PM |
5040 | /* CRC32[BHWX], CRC32C[BHWX] */ |
5041 | static void handle_crc32(DisasContext *s, | |
5042 | unsigned int sf, unsigned int sz, bool crc32c, | |
5043 | unsigned int rm, unsigned int rn, unsigned int rd) | |
5044 | { | |
5045 | TCGv_i64 tcg_acc, tcg_val; | |
5046 | TCGv_i32 tcg_bytes; | |
5047 | ||
962fcbf2 | 5048 | if (!dc_isar_feature(aa64_crc32, s) |
130f2e7d PM |
5049 | || (sf == 1 && sz != 3) |
5050 | || (sf == 0 && sz == 3)) { | |
5051 | unallocated_encoding(s); | |
5052 | return; | |
5053 | } | |
5054 | ||
5055 | if (sz == 3) { | |
5056 | tcg_val = cpu_reg(s, rm); | |
5057 | } else { | |
5058 | uint64_t mask; | |
5059 | switch (sz) { | |
5060 | case 0: | |
5061 | mask = 0xFF; | |
5062 | break; | |
5063 | case 1: | |
5064 | mask = 0xFFFF; | |
5065 | break; | |
5066 | case 2: | |
5067 | mask = 0xFFFFFFFF; | |
5068 | break; | |
5069 | default: | |
5070 | g_assert_not_reached(); | |
5071 | } | |
5072 | tcg_val = new_tmp_a64(s); | |
5073 | tcg_gen_andi_i64(tcg_val, cpu_reg(s, rm), mask); | |
5074 | } | |
5075 | ||
5076 | tcg_acc = cpu_reg(s, rn); | |
5077 | tcg_bytes = tcg_const_i32(1 << sz); | |
5078 | ||
5079 | if (crc32c) { | |
5080 | gen_helper_crc32c_64(cpu_reg(s, rd), tcg_acc, tcg_val, tcg_bytes); | |
5081 | } else { | |
5082 | gen_helper_crc32_64(cpu_reg(s, rd), tcg_acc, tcg_val, tcg_bytes); | |
5083 | } | |
5084 | ||
5085 | tcg_temp_free_i32(tcg_bytes); | |
5086 | } | |
5087 | ||
4ce31af4 | 5088 | /* Data-processing (2 source) |
8220e911 AG |
5089 | * 31 30 29 28 21 20 16 15 10 9 5 4 0 |
5090 | * +----+---+---+-----------------+------+--------+------+------+ | |
5091 | * | sf | 0 | S | 1 1 0 1 0 1 1 0 | Rm | opcode | Rn | Rd | | |
5092 | * +----+---+---+-----------------+------+--------+------+------+ | |
5093 | */ | |
ad7ee8a2 CF |
5094 | static void disas_data_proc_2src(DisasContext *s, uint32_t insn) |
5095 | { | |
8220e911 AG |
5096 | unsigned int sf, rm, opcode, rn, rd; |
5097 | sf = extract32(insn, 31, 1); | |
5098 | rm = extract32(insn, 16, 5); | |
5099 | opcode = extract32(insn, 10, 6); | |
5100 | rn = extract32(insn, 5, 5); | |
5101 | rd = extract32(insn, 0, 5); | |
5102 | ||
5103 | if (extract32(insn, 29, 1)) { | |
5104 | unallocated_encoding(s); | |
5105 | return; | |
5106 | } | |
5107 | ||
5108 | switch (opcode) { | |
5109 | case 2: /* UDIV */ | |
5110 | handle_div(s, false, sf, rm, rn, rd); | |
5111 | break; | |
5112 | case 3: /* SDIV */ | |
5113 | handle_div(s, true, sf, rm, rn, rd); | |
5114 | break; | |
5115 | case 8: /* LSLV */ | |
6c1adc91 AG |
5116 | handle_shift_reg(s, A64_SHIFT_TYPE_LSL, sf, rm, rn, rd); |
5117 | break; | |
8220e911 | 5118 | case 9: /* LSRV */ |
6c1adc91 AG |
5119 | handle_shift_reg(s, A64_SHIFT_TYPE_LSR, sf, rm, rn, rd); |
5120 | break; | |
8220e911 | 5121 | case 10: /* ASRV */ |
6c1adc91 AG |
5122 | handle_shift_reg(s, A64_SHIFT_TYPE_ASR, sf, rm, rn, rd); |
5123 | break; | |
8220e911 | 5124 | case 11: /* RORV */ |
6c1adc91 AG |
5125 | handle_shift_reg(s, A64_SHIFT_TYPE_ROR, sf, rm, rn, rd); |
5126 | break; | |
b6342a9f RH |
5127 | case 12: /* PACGA */ |
5128 | if (sf == 0 || !dc_isar_feature(aa64_pauth, s)) { | |
5129 | goto do_unallocated; | |
5130 | } | |
5131 | gen_helper_pacga(cpu_reg(s, rd), cpu_env, | |
5132 | cpu_reg(s, rn), cpu_reg_sp(s, rm)); | |
5133 | break; | |
8220e911 AG |
5134 | case 16: |
5135 | case 17: | |
5136 | case 18: | |
5137 | case 19: | |
5138 | case 20: | |
5139 | case 21: | |
5140 | case 22: | |
5141 | case 23: /* CRC32 */ | |
130f2e7d PM |
5142 | { |
5143 | int sz = extract32(opcode, 0, 2); | |
5144 | bool crc32c = extract32(opcode, 2, 1); | |
5145 | handle_crc32(s, sf, sz, crc32c, rm, rn, rd); | |
8220e911 | 5146 | break; |
130f2e7d | 5147 | } |
8220e911 | 5148 | default: |
b6342a9f | 5149 | do_unallocated: |
8220e911 AG |
5150 | unallocated_encoding(s); |
5151 | break; | |
5152 | } | |
ad7ee8a2 CF |
5153 | } |
5154 | ||
4ce31af4 | 5155 | /* Data processing - register */ |
ad7ee8a2 CF |
5156 | static void disas_data_proc_reg(DisasContext *s, uint32_t insn) |
5157 | { | |
5158 | switch (extract32(insn, 24, 5)) { | |
5159 | case 0x0a: /* Logical (shifted register) */ | |
5160 | disas_logic_reg(s, insn); | |
5161 | break; | |
5162 | case 0x0b: /* Add/subtract */ | |
5163 | if (insn & (1 << 21)) { /* (extended register) */ | |
5164 | disas_add_sub_ext_reg(s, insn); | |
5165 | } else { | |
5166 | disas_add_sub_reg(s, insn); | |
5167 | } | |
5168 | break; | |
5169 | case 0x1b: /* Data-processing (3 source) */ | |
5170 | disas_data_proc_3src(s, insn); | |
5171 | break; | |
5172 | case 0x1a: | |
5173 | switch (extract32(insn, 21, 3)) { | |
5174 | case 0x0: /* Add/subtract (with carry) */ | |
5175 | disas_adc_sbc(s, insn); | |
5176 | break; | |
5177 | case 0x2: /* Conditional compare */ | |
750813cf | 5178 | disas_cc(s, insn); /* both imm and reg forms */ |
ad7ee8a2 CF |
5179 | break; |
5180 | case 0x4: /* Conditional select */ | |
5181 | disas_cond_select(s, insn); | |
5182 | break; | |
5183 | case 0x6: /* Data-processing */ | |
5184 | if (insn & (1 << 30)) { /* (1 source) */ | |
5185 | disas_data_proc_1src(s, insn); | |
5186 | } else { /* (2 source) */ | |
5187 | disas_data_proc_2src(s, insn); | |
5188 | } | |
5189 | break; | |
5190 | default: | |
5191 | unallocated_encoding(s); | |
5192 | break; | |
5193 | } | |
5194 | break; | |
5195 | default: | |
5196 | unallocated_encoding(s); | |
5197 | break; | |
5198 | } | |
5199 | } | |
5200 | ||
7a192925 | 5201 | static void handle_fp_compare(DisasContext *s, int size, |
da7dafe7 CF |
5202 | unsigned int rn, unsigned int rm, |
5203 | bool cmp_with_zero, bool signal_all_nans) | |
5204 | { | |
5205 | TCGv_i64 tcg_flags = tcg_temp_new_i64(); | |
7a192925 | 5206 | TCGv_ptr fpst = get_fpstatus_ptr(size == MO_16); |
da7dafe7 | 5207 | |
7a192925 | 5208 | if (size == MO_64) { |
da7dafe7 CF |
5209 | TCGv_i64 tcg_vn, tcg_vm; |
5210 | ||
5211 | tcg_vn = read_fp_dreg(s, rn); | |
5212 | if (cmp_with_zero) { | |
5213 | tcg_vm = tcg_const_i64(0); | |
5214 | } else { | |
5215 | tcg_vm = read_fp_dreg(s, rm); | |
5216 | } | |
5217 | if (signal_all_nans) { | |
5218 | gen_helper_vfp_cmped_a64(tcg_flags, tcg_vn, tcg_vm, fpst); | |
5219 | } else { | |
5220 | gen_helper_vfp_cmpd_a64(tcg_flags, tcg_vn, tcg_vm, fpst); | |
5221 | } | |
5222 | tcg_temp_free_i64(tcg_vn); | |
5223 | tcg_temp_free_i64(tcg_vm); | |
5224 | } else { | |
7a192925 AB |
5225 | TCGv_i32 tcg_vn = tcg_temp_new_i32(); |
5226 | TCGv_i32 tcg_vm = tcg_temp_new_i32(); | |
da7dafe7 | 5227 | |
7a192925 | 5228 | read_vec_element_i32(s, tcg_vn, rn, 0, size); |
da7dafe7 | 5229 | if (cmp_with_zero) { |
7a192925 | 5230 | tcg_gen_movi_i32(tcg_vm, 0); |
da7dafe7 | 5231 | } else { |
7a192925 | 5232 | read_vec_element_i32(s, tcg_vm, rm, 0, size); |
da7dafe7 | 5233 | } |
7a192925 AB |
5234 | |
5235 | switch (size) { | |
5236 | case MO_32: | |
5237 | if (signal_all_nans) { | |
5238 | gen_helper_vfp_cmpes_a64(tcg_flags, tcg_vn, tcg_vm, fpst); | |
5239 | } else { | |
5240 | gen_helper_vfp_cmps_a64(tcg_flags, tcg_vn, tcg_vm, fpst); | |
5241 | } | |
5242 | break; | |
5243 | case MO_16: | |
5244 | if (signal_all_nans) { | |
5245 | gen_helper_vfp_cmpeh_a64(tcg_flags, tcg_vn, tcg_vm, fpst); | |
5246 | } else { | |
5247 | gen_helper_vfp_cmph_a64(tcg_flags, tcg_vn, tcg_vm, fpst); | |
5248 | } | |
5249 | break; | |
5250 | default: | |
5251 | g_assert_not_reached(); | |
da7dafe7 | 5252 | } |
7a192925 | 5253 | |
da7dafe7 CF |
5254 | tcg_temp_free_i32(tcg_vn); |
5255 | tcg_temp_free_i32(tcg_vm); | |
5256 | } | |
5257 | ||
5258 | tcg_temp_free_ptr(fpst); | |
5259 | ||
5260 | gen_set_nzcv(tcg_flags); | |
5261 | ||
5262 | tcg_temp_free_i64(tcg_flags); | |
5263 | } | |
5264 | ||
4ce31af4 | 5265 | /* Floating point compare |
faa0ba46 PM |
5266 | * 31 30 29 28 24 23 22 21 20 16 15 14 13 10 9 5 4 0 |
5267 | * +---+---+---+-----------+------+---+------+-----+---------+------+-------+ | |
5268 | * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | op | 1 0 0 0 | Rn | op2 | | |
5269 | * +---+---+---+-----------+------+---+------+-----+---------+------+-------+ | |
5270 | */ | |
5271 | static void disas_fp_compare(DisasContext *s, uint32_t insn) | |
5272 | { | |
da7dafe7 | 5273 | unsigned int mos, type, rm, op, rn, opc, op2r; |
7a192925 | 5274 | int size; |
da7dafe7 CF |
5275 | |
5276 | mos = extract32(insn, 29, 3); | |
7a192925 | 5277 | type = extract32(insn, 22, 2); |
da7dafe7 CF |
5278 | rm = extract32(insn, 16, 5); |
5279 | op = extract32(insn, 14, 2); | |
5280 | rn = extract32(insn, 5, 5); | |
5281 | opc = extract32(insn, 3, 2); | |
5282 | op2r = extract32(insn, 0, 3); | |
5283 | ||
7a192925 AB |
5284 | if (mos || op || op2r) { |
5285 | unallocated_encoding(s); | |
5286 | return; | |
5287 | } | |
5288 | ||
5289 | switch (type) { | |
5290 | case 0: | |
5291 | size = MO_32; | |
5292 | break; | |
5293 | case 1: | |
5294 | size = MO_64; | |
5295 | break; | |
5296 | case 3: | |
5297 | size = MO_16; | |
5763190f | 5298 | if (dc_isar_feature(aa64_fp16, s)) { |
7a192925 AB |
5299 | break; |
5300 | } | |
5301 | /* fallthru */ | |
5302 | default: | |
da7dafe7 CF |
5303 | unallocated_encoding(s); |
5304 | return; | |
5305 | } | |
5306 | ||
8c6afa6a PM |
5307 | if (!fp_access_check(s)) { |
5308 | return; | |
5309 | } | |
5310 | ||
7a192925 | 5311 | handle_fp_compare(s, size, rn, rm, opc & 1, opc & 2); |
faa0ba46 PM |
5312 | } |
5313 | ||
4ce31af4 | 5314 | /* Floating point conditional compare |
faa0ba46 PM |
5315 | * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0 |
5316 | * +---+---+---+-----------+------+---+------+------+-----+------+----+------+ | |
5317 | * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 0 1 | Rn | op | nzcv | | |
5318 | * +---+---+---+-----------+------+---+------+------+-----+------+----+------+ | |
5319 | */ | |
5320 | static void disas_fp_ccomp(DisasContext *s, uint32_t insn) | |
5321 | { | |
513f1d76 CF |
5322 | unsigned int mos, type, rm, cond, rn, op, nzcv; |
5323 | TCGv_i64 tcg_flags; | |
42a268c2 | 5324 | TCGLabel *label_continue = NULL; |
7a192925 | 5325 | int size; |
513f1d76 CF |
5326 | |
5327 | mos = extract32(insn, 29, 3); | |
7a192925 | 5328 | type = extract32(insn, 22, 2); |
513f1d76 CF |
5329 | rm = extract32(insn, 16, 5); |
5330 | cond = extract32(insn, 12, 4); | |
5331 | rn = extract32(insn, 5, 5); | |
5332 | op = extract32(insn, 4, 1); | |
5333 | nzcv = extract32(insn, 0, 4); | |
5334 | ||
7a192925 AB |
5335 | if (mos) { |
5336 | unallocated_encoding(s); | |
5337 | return; | |
5338 | } | |
5339 | ||
5340 | switch (type) { | |
5341 | case 0: | |
5342 | size = MO_32; | |
5343 | break; | |
5344 | case 1: | |
5345 | size = MO_64; | |
5346 | break; | |
5347 | case 3: | |
5348 | size = MO_16; | |
5763190f | 5349 | if (dc_isar_feature(aa64_fp16, s)) { |
7a192925 AB |
5350 | break; |
5351 | } | |
5352 | /* fallthru */ | |
5353 | default: | |
513f1d76 CF |
5354 | unallocated_encoding(s); |
5355 | return; | |
5356 | } | |
5357 | ||
8c6afa6a PM |
5358 | if (!fp_access_check(s)) { |
5359 | return; | |
5360 | } | |
5361 | ||
513f1d76 | 5362 | if (cond < 0x0e) { /* not always */ |
42a268c2 | 5363 | TCGLabel *label_match = gen_new_label(); |
513f1d76 CF |
5364 | label_continue = gen_new_label(); |
5365 | arm_gen_test_cc(cond, label_match); | |
5366 | /* nomatch: */ | |
5367 | tcg_flags = tcg_const_i64(nzcv << 28); | |
5368 | gen_set_nzcv(tcg_flags); | |
5369 | tcg_temp_free_i64(tcg_flags); | |
5370 | tcg_gen_br(label_continue); | |
5371 | gen_set_label(label_match); | |
5372 | } | |
5373 | ||
7a192925 | 5374 | handle_fp_compare(s, size, rn, rm, false, op); |
513f1d76 CF |
5375 | |
5376 | if (cond < 0x0e) { | |
5377 | gen_set_label(label_continue); | |
5378 | } | |
faa0ba46 PM |
5379 | } |
5380 | ||
4ce31af4 | 5381 | /* Floating point conditional select |
faa0ba46 PM |
5382 | * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0 |
5383 | * +---+---+---+-----------+------+---+------+------+-----+------+------+ | |
5384 | * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 1 1 | Rn | Rd | | |
5385 | * +---+---+---+-----------+------+---+------+------+-----+------+------+ | |
5386 | */ | |
5387 | static void disas_fp_csel(DisasContext *s, uint32_t insn) | |
5388 | { | |
5640ff62 | 5389 | unsigned int mos, type, rm, cond, rn, rd; |
6e061029 RH |
5390 | TCGv_i64 t_true, t_false, t_zero; |
5391 | DisasCompare64 c; | |
ace97fee | 5392 | TCGMemOp sz; |
5640ff62 CF |
5393 | |
5394 | mos = extract32(insn, 29, 3); | |
ace97fee | 5395 | type = extract32(insn, 22, 2); |
5640ff62 CF |
5396 | rm = extract32(insn, 16, 5); |
5397 | cond = extract32(insn, 12, 4); | |
5398 | rn = extract32(insn, 5, 5); | |
5399 | rd = extract32(insn, 0, 5); | |
5400 | ||
ace97fee AB |
5401 | if (mos) { |
5402 | unallocated_encoding(s); | |
5403 | return; | |
5404 | } | |
5405 | ||
5406 | switch (type) { | |
5407 | case 0: | |
5408 | sz = MO_32; | |
5409 | break; | |
5410 | case 1: | |
5411 | sz = MO_64; | |
5412 | break; | |
5413 | case 3: | |
5414 | sz = MO_16; | |
5763190f | 5415 | if (dc_isar_feature(aa64_fp16, s)) { |
ace97fee AB |
5416 | break; |
5417 | } | |
5418 | /* fallthru */ | |
5419 | default: | |
5640ff62 CF |
5420 | unallocated_encoding(s); |
5421 | return; | |
5422 | } | |
5423 | ||
8c6afa6a PM |
5424 | if (!fp_access_check(s)) { |
5425 | return; | |
5426 | } | |
5427 | ||
ace97fee | 5428 | /* Zero extend sreg & hreg inputs to 64 bits now. */ |
6e061029 RH |
5429 | t_true = tcg_temp_new_i64(); |
5430 | t_false = tcg_temp_new_i64(); | |
ace97fee AB |
5431 | read_vec_element(s, t_true, rn, 0, sz); |
5432 | read_vec_element(s, t_false, rm, 0, sz); | |
5640ff62 | 5433 | |
6e061029 RH |
5434 | a64_test_cc(&c, cond); |
5435 | t_zero = tcg_const_i64(0); | |
5436 | tcg_gen_movcond_i64(c.cond, t_true, c.value, t_zero, t_true, t_false); | |
5437 | tcg_temp_free_i64(t_zero); | |
5438 | tcg_temp_free_i64(t_false); | |
5439 | a64_free_cc(&c); | |
5640ff62 | 5440 | |
ace97fee | 5441 | /* Note that sregs & hregs write back zeros to the high bits, |
6e061029 RH |
5442 | and we've already done the zero-extension. */ |
5443 | write_fp_dreg(s, rd, t_true); | |
5444 | tcg_temp_free_i64(t_true); | |
faa0ba46 PM |
5445 | } |
5446 | ||
c2c08713 AB |
5447 | /* Floating-point data-processing (1 source) - half precision */ |
5448 | static void handle_fp_1src_half(DisasContext *s, int opcode, int rd, int rn) | |
5449 | { | |
5450 | TCGv_ptr fpst = NULL; | |
3d99d931 | 5451 | TCGv_i32 tcg_op = read_fp_hreg(s, rn); |
c2c08713 AB |
5452 | TCGv_i32 tcg_res = tcg_temp_new_i32(); |
5453 | ||
c2c08713 AB |
5454 | switch (opcode) { |
5455 | case 0x0: /* FMOV */ | |
5456 | tcg_gen_mov_i32(tcg_res, tcg_op); | |
5457 | break; | |
5458 | case 0x1: /* FABS */ | |
5459 | tcg_gen_andi_i32(tcg_res, tcg_op, 0x7fff); | |
5460 | break; | |
5461 | case 0x2: /* FNEG */ | |
5462 | tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000); | |
5463 | break; | |
5464 | case 0x3: /* FSQRT */ | |
905edee9 AB |
5465 | fpst = get_fpstatus_ptr(true); |
5466 | gen_helper_sqrt_f16(tcg_res, tcg_op, fpst); | |
c2c08713 AB |
5467 | break; |
5468 | case 0x8: /* FRINTN */ | |
5469 | case 0x9: /* FRINTP */ | |
5470 | case 0xa: /* FRINTM */ | |
5471 | case 0xb: /* FRINTZ */ | |
5472 | case 0xc: /* FRINTA */ | |
5473 | { | |
5474 | TCGv_i32 tcg_rmode = tcg_const_i32(arm_rmode_to_sf(opcode & 7)); | |
5475 | fpst = get_fpstatus_ptr(true); | |
5476 | ||
5477 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); | |
5478 | gen_helper_advsimd_rinth(tcg_res, tcg_op, fpst); | |
5479 | ||
5480 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); | |
5481 | tcg_temp_free_i32(tcg_rmode); | |
5482 | break; | |
5483 | } | |
5484 | case 0xe: /* FRINTX */ | |
5485 | fpst = get_fpstatus_ptr(true); | |
5486 | gen_helper_advsimd_rinth_exact(tcg_res, tcg_op, fpst); | |
5487 | break; | |
5488 | case 0xf: /* FRINTI */ | |
5489 | fpst = get_fpstatus_ptr(true); | |
5490 | gen_helper_advsimd_rinth(tcg_res, tcg_op, fpst); | |
5491 | break; | |
5492 | default: | |
5493 | abort(); | |
5494 | } | |
5495 | ||
5496 | write_fp_sreg(s, rd, tcg_res); | |
5497 | ||
5498 | if (fpst) { | |
5499 | tcg_temp_free_ptr(fpst); | |
5500 | } | |
5501 | tcg_temp_free_i32(tcg_op); | |
5502 | tcg_temp_free_i32(tcg_res); | |
5503 | } | |
5504 | ||
4ce31af4 | 5505 | /* Floating-point data-processing (1 source) - single precision */ |
d9b0848d PM |
5506 | static void handle_fp_1src_single(DisasContext *s, int opcode, int rd, int rn) |
5507 | { | |
5508 | TCGv_ptr fpst; | |
5509 | TCGv_i32 tcg_op; | |
5510 | TCGv_i32 tcg_res; | |
5511 | ||
d81ce0ef | 5512 | fpst = get_fpstatus_ptr(false); |
d9b0848d PM |
5513 | tcg_op = read_fp_sreg(s, rn); |
5514 | tcg_res = tcg_temp_new_i32(); | |
5515 | ||
5516 | switch (opcode) { | |
5517 | case 0x0: /* FMOV */ | |
5518 | tcg_gen_mov_i32(tcg_res, tcg_op); | |
5519 | break; | |
5520 | case 0x1: /* FABS */ | |
5521 | gen_helper_vfp_abss(tcg_res, tcg_op); | |
5522 | break; | |
5523 | case 0x2: /* FNEG */ | |
5524 | gen_helper_vfp_negs(tcg_res, tcg_op); | |
5525 | break; | |
5526 | case 0x3: /* FSQRT */ | |
5527 | gen_helper_vfp_sqrts(tcg_res, tcg_op, cpu_env); | |
5528 | break; | |
5529 | case 0x8: /* FRINTN */ | |
5530 | case 0x9: /* FRINTP */ | |
5531 | case 0xa: /* FRINTM */ | |
5532 | case 0xb: /* FRINTZ */ | |
5533 | case 0xc: /* FRINTA */ | |
5534 | { | |
5535 | TCGv_i32 tcg_rmode = tcg_const_i32(arm_rmode_to_sf(opcode & 7)); | |
5536 | ||
9b049916 | 5537 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); |
d9b0848d PM |
5538 | gen_helper_rints(tcg_res, tcg_op, fpst); |
5539 | ||
9b049916 | 5540 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); |
d9b0848d PM |
5541 | tcg_temp_free_i32(tcg_rmode); |
5542 | break; | |
5543 | } | |
5544 | case 0xe: /* FRINTX */ | |
5545 | gen_helper_rints_exact(tcg_res, tcg_op, fpst); | |
5546 | break; | |
5547 | case 0xf: /* FRINTI */ | |
5548 | gen_helper_rints(tcg_res, tcg_op, fpst); | |
5549 | break; | |
5550 | default: | |
5551 | abort(); | |
5552 | } | |
5553 | ||
5554 | write_fp_sreg(s, rd, tcg_res); | |
5555 | ||
5556 | tcg_temp_free_ptr(fpst); | |
5557 | tcg_temp_free_i32(tcg_op); | |
5558 | tcg_temp_free_i32(tcg_res); | |
5559 | } | |
5560 | ||
4ce31af4 | 5561 | /* Floating-point data-processing (1 source) - double precision */ |
d9b0848d PM |
5562 | static void handle_fp_1src_double(DisasContext *s, int opcode, int rd, int rn) |
5563 | { | |
5564 | TCGv_ptr fpst; | |
5565 | TCGv_i64 tcg_op; | |
5566 | TCGv_i64 tcg_res; | |
5567 | ||
377ef731 RH |
5568 | switch (opcode) { |
5569 | case 0x0: /* FMOV */ | |
5570 | gen_gvec_fn2(s, false, rd, rn, tcg_gen_gvec_mov, 0); | |
5571 | return; | |
5572 | } | |
5573 | ||
d81ce0ef | 5574 | fpst = get_fpstatus_ptr(false); |
d9b0848d PM |
5575 | tcg_op = read_fp_dreg(s, rn); |
5576 | tcg_res = tcg_temp_new_i64(); | |
5577 | ||
5578 | switch (opcode) { | |
d9b0848d PM |
5579 | case 0x1: /* FABS */ |
5580 | gen_helper_vfp_absd(tcg_res, tcg_op); | |
5581 | break; | |
5582 | case 0x2: /* FNEG */ | |
5583 | gen_helper_vfp_negd(tcg_res, tcg_op); | |
5584 | break; | |
5585 | case 0x3: /* FSQRT */ | |
5586 | gen_helper_vfp_sqrtd(tcg_res, tcg_op, cpu_env); | |
5587 | break; | |
5588 | case 0x8: /* FRINTN */ | |
5589 | case 0x9: /* FRINTP */ | |
5590 | case 0xa: /* FRINTM */ | |
5591 | case 0xb: /* FRINTZ */ | |
5592 | case 0xc: /* FRINTA */ | |
5593 | { | |
5594 | TCGv_i32 tcg_rmode = tcg_const_i32(arm_rmode_to_sf(opcode & 7)); | |
5595 | ||
9b049916 | 5596 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); |
d9b0848d PM |
5597 | gen_helper_rintd(tcg_res, tcg_op, fpst); |
5598 | ||
9b049916 | 5599 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); |
d9b0848d PM |
5600 | tcg_temp_free_i32(tcg_rmode); |
5601 | break; | |
5602 | } | |
5603 | case 0xe: /* FRINTX */ | |
5604 | gen_helper_rintd_exact(tcg_res, tcg_op, fpst); | |
5605 | break; | |
5606 | case 0xf: /* FRINTI */ | |
5607 | gen_helper_rintd(tcg_res, tcg_op, fpst); | |
5608 | break; | |
5609 | default: | |
5610 | abort(); | |
5611 | } | |
5612 | ||
5613 | write_fp_dreg(s, rd, tcg_res); | |
5614 | ||
5615 | tcg_temp_free_ptr(fpst); | |
5616 | tcg_temp_free_i64(tcg_op); | |
5617 | tcg_temp_free_i64(tcg_res); | |
5618 | } | |
5619 | ||
8900aad2 PM |
5620 | static void handle_fp_fcvt(DisasContext *s, int opcode, |
5621 | int rd, int rn, int dtype, int ntype) | |
5622 | { | |
5623 | switch (ntype) { | |
5624 | case 0x0: | |
5625 | { | |
5626 | TCGv_i32 tcg_rn = read_fp_sreg(s, rn); | |
5627 | if (dtype == 1) { | |
5628 | /* Single to double */ | |
5629 | TCGv_i64 tcg_rd = tcg_temp_new_i64(); | |
5630 | gen_helper_vfp_fcvtds(tcg_rd, tcg_rn, cpu_env); | |
5631 | write_fp_dreg(s, rd, tcg_rd); | |
5632 | tcg_temp_free_i64(tcg_rd); | |
5633 | } else { | |
5634 | /* Single to half */ | |
5635 | TCGv_i32 tcg_rd = tcg_temp_new_i32(); | |
486624fc AB |
5636 | TCGv_i32 ahp = get_ahp_flag(); |
5637 | TCGv_ptr fpst = get_fpstatus_ptr(false); | |
5638 | ||
5639 | gen_helper_vfp_fcvt_f32_to_f16(tcg_rd, tcg_rn, fpst, ahp); | |
8900aad2 PM |
5640 | /* write_fp_sreg is OK here because top half of tcg_rd is zero */ |
5641 | write_fp_sreg(s, rd, tcg_rd); | |
5642 | tcg_temp_free_i32(tcg_rd); | |
486624fc AB |
5643 | tcg_temp_free_i32(ahp); |
5644 | tcg_temp_free_ptr(fpst); | |
8900aad2 PM |
5645 | } |
5646 | tcg_temp_free_i32(tcg_rn); | |
5647 | break; | |
5648 | } | |
5649 | case 0x1: | |
5650 | { | |
5651 | TCGv_i64 tcg_rn = read_fp_dreg(s, rn); | |
5652 | TCGv_i32 tcg_rd = tcg_temp_new_i32(); | |
5653 | if (dtype == 0) { | |
5654 | /* Double to single */ | |
5655 | gen_helper_vfp_fcvtsd(tcg_rd, tcg_rn, cpu_env); | |
5656 | } else { | |
486624fc AB |
5657 | TCGv_ptr fpst = get_fpstatus_ptr(false); |
5658 | TCGv_i32 ahp = get_ahp_flag(); | |
8900aad2 | 5659 | /* Double to half */ |
486624fc | 5660 | gen_helper_vfp_fcvt_f64_to_f16(tcg_rd, tcg_rn, fpst, ahp); |
8900aad2 | 5661 | /* write_fp_sreg is OK here because top half of tcg_rd is zero */ |
486624fc AB |
5662 | tcg_temp_free_ptr(fpst); |
5663 | tcg_temp_free_i32(ahp); | |
8900aad2 PM |
5664 | } |
5665 | write_fp_sreg(s, rd, tcg_rd); | |
5666 | tcg_temp_free_i32(tcg_rd); | |
5667 | tcg_temp_free_i64(tcg_rn); | |
5668 | break; | |
5669 | } | |
5670 | case 0x3: | |
5671 | { | |
5672 | TCGv_i32 tcg_rn = read_fp_sreg(s, rn); | |
486624fc AB |
5673 | TCGv_ptr tcg_fpst = get_fpstatus_ptr(false); |
5674 | TCGv_i32 tcg_ahp = get_ahp_flag(); | |
8900aad2 PM |
5675 | tcg_gen_ext16u_i32(tcg_rn, tcg_rn); |
5676 | if (dtype == 0) { | |
5677 | /* Half to single */ | |
5678 | TCGv_i32 tcg_rd = tcg_temp_new_i32(); | |
486624fc | 5679 | gen_helper_vfp_fcvt_f16_to_f32(tcg_rd, tcg_rn, tcg_fpst, tcg_ahp); |
8900aad2 | 5680 | write_fp_sreg(s, rd, tcg_rd); |
486624fc AB |
5681 | tcg_temp_free_ptr(tcg_fpst); |
5682 | tcg_temp_free_i32(tcg_ahp); | |
8900aad2 PM |
5683 | tcg_temp_free_i32(tcg_rd); |
5684 | } else { | |
5685 | /* Half to double */ | |
5686 | TCGv_i64 tcg_rd = tcg_temp_new_i64(); | |
486624fc | 5687 | gen_helper_vfp_fcvt_f16_to_f64(tcg_rd, tcg_rn, tcg_fpst, tcg_ahp); |
8900aad2 PM |
5688 | write_fp_dreg(s, rd, tcg_rd); |
5689 | tcg_temp_free_i64(tcg_rd); | |
5690 | } | |
5691 | tcg_temp_free_i32(tcg_rn); | |
5692 | break; | |
5693 | } | |
5694 | default: | |
5695 | abort(); | |
5696 | } | |
5697 | } | |
5698 | ||
4ce31af4 | 5699 | /* Floating point data-processing (1 source) |
faa0ba46 PM |
5700 | * 31 30 29 28 24 23 22 21 20 15 14 10 9 5 4 0 |
5701 | * +---+---+---+-----------+------+---+--------+-----------+------+------+ | |
5702 | * | M | 0 | S | 1 1 1 1 0 | type | 1 | opcode | 1 0 0 0 0 | Rn | Rd | | |
5703 | * +---+---+---+-----------+------+---+--------+-----------+------+------+ | |
5704 | */ | |
5705 | static void disas_fp_1src(DisasContext *s, uint32_t insn) | |
5706 | { | |
c1e20801 | 5707 | int mos = extract32(insn, 29, 3); |
d9b0848d PM |
5708 | int type = extract32(insn, 22, 2); |
5709 | int opcode = extract32(insn, 15, 6); | |
5710 | int rn = extract32(insn, 5, 5); | |
5711 | int rd = extract32(insn, 0, 5); | |
5712 | ||
c1e20801 PM |
5713 | if (mos) { |
5714 | unallocated_encoding(s); | |
5715 | return; | |
5716 | } | |
5717 | ||
d9b0848d PM |
5718 | switch (opcode) { |
5719 | case 0x4: case 0x5: case 0x7: | |
8900aad2 | 5720 | { |
d9b0848d | 5721 | /* FCVT between half, single and double precision */ |
8900aad2 PM |
5722 | int dtype = extract32(opcode, 0, 2); |
5723 | if (type == 2 || dtype == type) { | |
5724 | unallocated_encoding(s); | |
5725 | return; | |
5726 | } | |
8c6afa6a PM |
5727 | if (!fp_access_check(s)) { |
5728 | return; | |
5729 | } | |
5730 | ||
8900aad2 | 5731 | handle_fp_fcvt(s, opcode, rd, rn, dtype, type); |
d9b0848d | 5732 | break; |
8900aad2 | 5733 | } |
d9b0848d PM |
5734 | case 0x0 ... 0x3: |
5735 | case 0x8 ... 0xc: | |
5736 | case 0xe ... 0xf: | |
5737 | /* 32-to-32 and 64-to-64 ops */ | |
5738 | switch (type) { | |
5739 | case 0: | |
8c6afa6a PM |
5740 | if (!fp_access_check(s)) { |
5741 | return; | |
5742 | } | |
5743 | ||
d9b0848d PM |
5744 | handle_fp_1src_single(s, opcode, rd, rn); |
5745 | break; | |
5746 | case 1: | |
8c6afa6a PM |
5747 | if (!fp_access_check(s)) { |
5748 | return; | |
5749 | } | |
5750 | ||
d9b0848d PM |
5751 | handle_fp_1src_double(s, opcode, rd, rn); |
5752 | break; | |
c2c08713 | 5753 | case 3: |
5763190f | 5754 | if (!dc_isar_feature(aa64_fp16, s)) { |
c2c08713 AB |
5755 | unallocated_encoding(s); |
5756 | return; | |
5757 | } | |
5758 | ||
5759 | if (!fp_access_check(s)) { | |
5760 | return; | |
5761 | } | |
5762 | ||
5763 | handle_fp_1src_half(s, opcode, rd, rn); | |
5764 | break; | |
d9b0848d PM |
5765 | default: |
5766 | unallocated_encoding(s); | |
5767 | } | |
5768 | break; | |
5769 | default: | |
5770 | unallocated_encoding(s); | |
5771 | break; | |
5772 | } | |
faa0ba46 PM |
5773 | } |
5774 | ||
4ce31af4 | 5775 | /* Floating-point data-processing (2 source) - single precision */ |
ec73d2e0 AG |
5776 | static void handle_fp_2src_single(DisasContext *s, int opcode, |
5777 | int rd, int rn, int rm) | |
5778 | { | |
5779 | TCGv_i32 tcg_op1; | |
5780 | TCGv_i32 tcg_op2; | |
5781 | TCGv_i32 tcg_res; | |
5782 | TCGv_ptr fpst; | |
5783 | ||
5784 | tcg_res = tcg_temp_new_i32(); | |
d81ce0ef | 5785 | fpst = get_fpstatus_ptr(false); |
ec73d2e0 AG |
5786 | tcg_op1 = read_fp_sreg(s, rn); |
5787 | tcg_op2 = read_fp_sreg(s, rm); | |
5788 | ||
5789 | switch (opcode) { | |
5790 | case 0x0: /* FMUL */ | |
5791 | gen_helper_vfp_muls(tcg_res, tcg_op1, tcg_op2, fpst); | |
5792 | break; | |
5793 | case 0x1: /* FDIV */ | |
5794 | gen_helper_vfp_divs(tcg_res, tcg_op1, tcg_op2, fpst); | |
5795 | break; | |
5796 | case 0x2: /* FADD */ | |
5797 | gen_helper_vfp_adds(tcg_res, tcg_op1, tcg_op2, fpst); | |
5798 | break; | |
5799 | case 0x3: /* FSUB */ | |
5800 | gen_helper_vfp_subs(tcg_res, tcg_op1, tcg_op2, fpst); | |
5801 | break; | |
5802 | case 0x4: /* FMAX */ | |
5803 | gen_helper_vfp_maxs(tcg_res, tcg_op1, tcg_op2, fpst); | |
5804 | break; | |
5805 | case 0x5: /* FMIN */ | |
5806 | gen_helper_vfp_mins(tcg_res, tcg_op1, tcg_op2, fpst); | |
5807 | break; | |
5808 | case 0x6: /* FMAXNM */ | |
5809 | gen_helper_vfp_maxnums(tcg_res, tcg_op1, tcg_op2, fpst); | |
5810 | break; | |
5811 | case 0x7: /* FMINNM */ | |
5812 | gen_helper_vfp_minnums(tcg_res, tcg_op1, tcg_op2, fpst); | |
5813 | break; | |
5814 | case 0x8: /* FNMUL */ | |
5815 | gen_helper_vfp_muls(tcg_res, tcg_op1, tcg_op2, fpst); | |
5816 | gen_helper_vfp_negs(tcg_res, tcg_res); | |
5817 | break; | |
5818 | } | |
5819 | ||
5820 | write_fp_sreg(s, rd, tcg_res); | |
5821 | ||
5822 | tcg_temp_free_ptr(fpst); | |
5823 | tcg_temp_free_i32(tcg_op1); | |
5824 | tcg_temp_free_i32(tcg_op2); | |
5825 | tcg_temp_free_i32(tcg_res); | |
5826 | } | |
5827 | ||
4ce31af4 | 5828 | /* Floating-point data-processing (2 source) - double precision */ |
ec73d2e0 AG |
5829 | static void handle_fp_2src_double(DisasContext *s, int opcode, |
5830 | int rd, int rn, int rm) | |
5831 | { | |
5832 | TCGv_i64 tcg_op1; | |
5833 | TCGv_i64 tcg_op2; | |
5834 | TCGv_i64 tcg_res; | |
5835 | TCGv_ptr fpst; | |
5836 | ||
5837 | tcg_res = tcg_temp_new_i64(); | |
d81ce0ef | 5838 | fpst = get_fpstatus_ptr(false); |
ec73d2e0 AG |
5839 | tcg_op1 = read_fp_dreg(s, rn); |
5840 | tcg_op2 = read_fp_dreg(s, rm); | |
5841 | ||
5842 | switch (opcode) { | |
5843 | case 0x0: /* FMUL */ | |
5844 | gen_helper_vfp_muld(tcg_res, tcg_op1, tcg_op2, fpst); | |
5845 | break; | |
5846 | case 0x1: /* FDIV */ | |
5847 | gen_helper_vfp_divd(tcg_res, tcg_op1, tcg_op2, fpst); | |
5848 | break; | |
5849 | case 0x2: /* FADD */ | |
5850 | gen_helper_vfp_addd(tcg_res, tcg_op1, tcg_op2, fpst); | |
5851 | break; | |
5852 | case 0x3: /* FSUB */ | |
5853 | gen_helper_vfp_subd(tcg_res, tcg_op1, tcg_op2, fpst); | |
5854 | break; | |
5855 | case 0x4: /* FMAX */ | |
5856 | gen_helper_vfp_maxd(tcg_res, tcg_op1, tcg_op2, fpst); | |
5857 | break; | |
5858 | case 0x5: /* FMIN */ | |
5859 | gen_helper_vfp_mind(tcg_res, tcg_op1, tcg_op2, fpst); | |
5860 | break; | |
5861 | case 0x6: /* FMAXNM */ | |
5862 | gen_helper_vfp_maxnumd(tcg_res, tcg_op1, tcg_op2, fpst); | |
5863 | break; | |
5864 | case 0x7: /* FMINNM */ | |
5865 | gen_helper_vfp_minnumd(tcg_res, tcg_op1, tcg_op2, fpst); | |
5866 | break; | |
5867 | case 0x8: /* FNMUL */ | |
5868 | gen_helper_vfp_muld(tcg_res, tcg_op1, tcg_op2, fpst); | |
5869 | gen_helper_vfp_negd(tcg_res, tcg_res); | |
5870 | break; | |
5871 | } | |
5872 | ||
5873 | write_fp_dreg(s, rd, tcg_res); | |
5874 | ||
5875 | tcg_temp_free_ptr(fpst); | |
5876 | tcg_temp_free_i64(tcg_op1); | |
5877 | tcg_temp_free_i64(tcg_op2); | |
5878 | tcg_temp_free_i64(tcg_res); | |
5879 | } | |
5880 | ||
b8f5171c RH |
5881 | /* Floating-point data-processing (2 source) - half precision */ |
5882 | static void handle_fp_2src_half(DisasContext *s, int opcode, | |
5883 | int rd, int rn, int rm) | |
5884 | { | |
5885 | TCGv_i32 tcg_op1; | |
5886 | TCGv_i32 tcg_op2; | |
5887 | TCGv_i32 tcg_res; | |
5888 | TCGv_ptr fpst; | |
5889 | ||
5890 | tcg_res = tcg_temp_new_i32(); | |
5891 | fpst = get_fpstatus_ptr(true); | |
5892 | tcg_op1 = read_fp_hreg(s, rn); | |
5893 | tcg_op2 = read_fp_hreg(s, rm); | |
5894 | ||
5895 | switch (opcode) { | |
5896 | case 0x0: /* FMUL */ | |
5897 | gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst); | |
5898 | break; | |
5899 | case 0x1: /* FDIV */ | |
5900 | gen_helper_advsimd_divh(tcg_res, tcg_op1, tcg_op2, fpst); | |
5901 | break; | |
5902 | case 0x2: /* FADD */ | |
5903 | gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst); | |
5904 | break; | |
5905 | case 0x3: /* FSUB */ | |
5906 | gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst); | |
5907 | break; | |
5908 | case 0x4: /* FMAX */ | |
5909 | gen_helper_advsimd_maxh(tcg_res, tcg_op1, tcg_op2, fpst); | |
5910 | break; | |
5911 | case 0x5: /* FMIN */ | |
5912 | gen_helper_advsimd_minh(tcg_res, tcg_op1, tcg_op2, fpst); | |
5913 | break; | |
5914 | case 0x6: /* FMAXNM */ | |
5915 | gen_helper_advsimd_maxnumh(tcg_res, tcg_op1, tcg_op2, fpst); | |
5916 | break; | |
5917 | case 0x7: /* FMINNM */ | |
5918 | gen_helper_advsimd_minnumh(tcg_res, tcg_op1, tcg_op2, fpst); | |
5919 | break; | |
5920 | case 0x8: /* FNMUL */ | |
5921 | gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst); | |
5922 | tcg_gen_xori_i32(tcg_res, tcg_res, 0x8000); | |
5923 | break; | |
5924 | default: | |
5925 | g_assert_not_reached(); | |
5926 | } | |
5927 | ||
5928 | write_fp_sreg(s, rd, tcg_res); | |
5929 | ||
5930 | tcg_temp_free_ptr(fpst); | |
5931 | tcg_temp_free_i32(tcg_op1); | |
5932 | tcg_temp_free_i32(tcg_op2); | |
5933 | tcg_temp_free_i32(tcg_res); | |
5934 | } | |
5935 | ||
4ce31af4 | 5936 | /* Floating point data-processing (2 source) |
faa0ba46 PM |
5937 | * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0 |
5938 | * +---+---+---+-----------+------+---+------+--------+-----+------+------+ | |
5939 | * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | opcode | 1 0 | Rn | Rd | | |
5940 | * +---+---+---+-----------+------+---+------+--------+-----+------+------+ | |
5941 | */ | |
5942 | static void disas_fp_2src(DisasContext *s, uint32_t insn) | |
5943 | { | |
c1e20801 | 5944 | int mos = extract32(insn, 29, 3); |
ec73d2e0 AG |
5945 | int type = extract32(insn, 22, 2); |
5946 | int rd = extract32(insn, 0, 5); | |
5947 | int rn = extract32(insn, 5, 5); | |
5948 | int rm = extract32(insn, 16, 5); | |
5949 | int opcode = extract32(insn, 12, 4); | |
5950 | ||
c1e20801 | 5951 | if (opcode > 8 || mos) { |
ec73d2e0 AG |
5952 | unallocated_encoding(s); |
5953 | return; | |
5954 | } | |
5955 | ||
5956 | switch (type) { | |
5957 | case 0: | |
8c6afa6a PM |
5958 | if (!fp_access_check(s)) { |
5959 | return; | |
5960 | } | |
ec73d2e0 AG |
5961 | handle_fp_2src_single(s, opcode, rd, rn, rm); |
5962 | break; | |
5963 | case 1: | |
8c6afa6a PM |
5964 | if (!fp_access_check(s)) { |
5965 | return; | |
5966 | } | |
ec73d2e0 AG |
5967 | handle_fp_2src_double(s, opcode, rd, rn, rm); |
5968 | break; | |
b8f5171c | 5969 | case 3: |
5763190f | 5970 | if (!dc_isar_feature(aa64_fp16, s)) { |
b8f5171c RH |
5971 | unallocated_encoding(s); |
5972 | return; | |
5973 | } | |
5974 | if (!fp_access_check(s)) { | |
5975 | return; | |
5976 | } | |
5977 | handle_fp_2src_half(s, opcode, rd, rn, rm); | |
5978 | break; | |
ec73d2e0 AG |
5979 | default: |
5980 | unallocated_encoding(s); | |
5981 | } | |
faa0ba46 PM |
5982 | } |
5983 | ||
4ce31af4 | 5984 | /* Floating-point data-processing (3 source) - single precision */ |
6a30667f AG |
5985 | static void handle_fp_3src_single(DisasContext *s, bool o0, bool o1, |
5986 | int rd, int rn, int rm, int ra) | |
5987 | { | |
5988 | TCGv_i32 tcg_op1, tcg_op2, tcg_op3; | |
5989 | TCGv_i32 tcg_res = tcg_temp_new_i32(); | |
d81ce0ef | 5990 | TCGv_ptr fpst = get_fpstatus_ptr(false); |
6a30667f AG |
5991 | |
5992 | tcg_op1 = read_fp_sreg(s, rn); | |
5993 | tcg_op2 = read_fp_sreg(s, rm); | |
5994 | tcg_op3 = read_fp_sreg(s, ra); | |
5995 | ||
5996 | /* These are fused multiply-add, and must be done as one | |
5997 | * floating point operation with no rounding between the | |
5998 | * multiplication and addition steps. | |
5999 | * NB that doing the negations here as separate steps is | |
6000 | * correct : an input NaN should come out with its sign bit | |
6001 | * flipped if it is a negated-input. | |
6002 | */ | |
6003 | if (o1 == true) { | |
6004 | gen_helper_vfp_negs(tcg_op3, tcg_op3); | |
6005 | } | |
6006 | ||
6007 | if (o0 != o1) { | |
6008 | gen_helper_vfp_negs(tcg_op1, tcg_op1); | |
6009 | } | |
6010 | ||
6011 | gen_helper_vfp_muladds(tcg_res, tcg_op1, tcg_op2, tcg_op3, fpst); | |
6012 | ||
6013 | write_fp_sreg(s, rd, tcg_res); | |
6014 | ||
6015 | tcg_temp_free_ptr(fpst); | |
6016 | tcg_temp_free_i32(tcg_op1); | |
6017 | tcg_temp_free_i32(tcg_op2); | |
6018 | tcg_temp_free_i32(tcg_op3); | |
6019 | tcg_temp_free_i32(tcg_res); | |
6020 | } | |
6021 | ||
4ce31af4 | 6022 | /* Floating-point data-processing (3 source) - double precision */ |
6a30667f AG |
6023 | static void handle_fp_3src_double(DisasContext *s, bool o0, bool o1, |
6024 | int rd, int rn, int rm, int ra) | |
6025 | { | |
6026 | TCGv_i64 tcg_op1, tcg_op2, tcg_op3; | |
6027 | TCGv_i64 tcg_res = tcg_temp_new_i64(); | |
d81ce0ef | 6028 | TCGv_ptr fpst = get_fpstatus_ptr(false); |
6a30667f AG |
6029 | |
6030 | tcg_op1 = read_fp_dreg(s, rn); | |
6031 | tcg_op2 = read_fp_dreg(s, rm); | |
6032 | tcg_op3 = read_fp_dreg(s, ra); | |
6033 | ||
6034 | /* These are fused multiply-add, and must be done as one | |
6035 | * floating point operation with no rounding between the | |
6036 | * multiplication and addition steps. | |
6037 | * NB that doing the negations here as separate steps is | |
6038 | * correct : an input NaN should come out with its sign bit | |
6039 | * flipped if it is a negated-input. | |
6040 | */ | |
6041 | if (o1 == true) { | |
6042 | gen_helper_vfp_negd(tcg_op3, tcg_op3); | |
6043 | } | |
6044 | ||
6045 | if (o0 != o1) { | |
6046 | gen_helper_vfp_negd(tcg_op1, tcg_op1); | |
6047 | } | |
6048 | ||
6049 | gen_helper_vfp_muladdd(tcg_res, tcg_op1, tcg_op2, tcg_op3, fpst); | |
6050 | ||
6051 | write_fp_dreg(s, rd, tcg_res); | |
6052 | ||
6053 | tcg_temp_free_ptr(fpst); | |
6054 | tcg_temp_free_i64(tcg_op1); | |
6055 | tcg_temp_free_i64(tcg_op2); | |
6056 | tcg_temp_free_i64(tcg_op3); | |
6057 | tcg_temp_free_i64(tcg_res); | |
6058 | } | |
6059 | ||
95f9864f RH |
6060 | /* Floating-point data-processing (3 source) - half precision */ |
6061 | static void handle_fp_3src_half(DisasContext *s, bool o0, bool o1, | |
6062 | int rd, int rn, int rm, int ra) | |
6063 | { | |
6064 | TCGv_i32 tcg_op1, tcg_op2, tcg_op3; | |
6065 | TCGv_i32 tcg_res = tcg_temp_new_i32(); | |
6066 | TCGv_ptr fpst = get_fpstatus_ptr(true); | |
6067 | ||
6068 | tcg_op1 = read_fp_hreg(s, rn); | |
6069 | tcg_op2 = read_fp_hreg(s, rm); | |
6070 | tcg_op3 = read_fp_hreg(s, ra); | |
6071 | ||
6072 | /* These are fused multiply-add, and must be done as one | |
6073 | * floating point operation with no rounding between the | |
6074 | * multiplication and addition steps. | |
6075 | * NB that doing the negations here as separate steps is | |
6076 | * correct : an input NaN should come out with its sign bit | |
6077 | * flipped if it is a negated-input. | |
6078 | */ | |
6079 | if (o1 == true) { | |
6080 | tcg_gen_xori_i32(tcg_op3, tcg_op3, 0x8000); | |
6081 | } | |
6082 | ||
6083 | if (o0 != o1) { | |
6084 | tcg_gen_xori_i32(tcg_op1, tcg_op1, 0x8000); | |
6085 | } | |
6086 | ||
6087 | gen_helper_advsimd_muladdh(tcg_res, tcg_op1, tcg_op2, tcg_op3, fpst); | |
6088 | ||
6089 | write_fp_sreg(s, rd, tcg_res); | |
6090 | ||
6091 | tcg_temp_free_ptr(fpst); | |
6092 | tcg_temp_free_i32(tcg_op1); | |
6093 | tcg_temp_free_i32(tcg_op2); | |
6094 | tcg_temp_free_i32(tcg_op3); | |
6095 | tcg_temp_free_i32(tcg_res); | |
6096 | } | |
6097 | ||
4ce31af4 | 6098 | /* Floating point data-processing (3 source) |
faa0ba46 PM |
6099 | * 31 30 29 28 24 23 22 21 20 16 15 14 10 9 5 4 0 |
6100 | * +---+---+---+-----------+------+----+------+----+------+------+------+ | |
6101 | * | M | 0 | S | 1 1 1 1 1 | type | o1 | Rm | o0 | Ra | Rn | Rd | | |
6102 | * +---+---+---+-----------+------+----+------+----+------+------+------+ | |
6103 | */ | |
6104 | static void disas_fp_3src(DisasContext *s, uint32_t insn) | |
6105 | { | |
c1e20801 | 6106 | int mos = extract32(insn, 29, 3); |
6a30667f AG |
6107 | int type = extract32(insn, 22, 2); |
6108 | int rd = extract32(insn, 0, 5); | |
6109 | int rn = extract32(insn, 5, 5); | |
6110 | int ra = extract32(insn, 10, 5); | |
6111 | int rm = extract32(insn, 16, 5); | |
6112 | bool o0 = extract32(insn, 15, 1); | |
6113 | bool o1 = extract32(insn, 21, 1); | |
6114 | ||
c1e20801 PM |
6115 | if (mos) { |
6116 | unallocated_encoding(s); | |
6117 | return; | |
6118 | } | |
6119 | ||
6a30667f AG |
6120 | switch (type) { |
6121 | case 0: | |
8c6afa6a PM |
6122 | if (!fp_access_check(s)) { |
6123 | return; | |
6124 | } | |
6a30667f AG |
6125 | handle_fp_3src_single(s, o0, o1, rd, rn, rm, ra); |
6126 | break; | |
6127 | case 1: | |
8c6afa6a PM |
6128 | if (!fp_access_check(s)) { |
6129 | return; | |
6130 | } | |
6a30667f AG |
6131 | handle_fp_3src_double(s, o0, o1, rd, rn, rm, ra); |
6132 | break; | |
95f9864f | 6133 | case 3: |
5763190f | 6134 | if (!dc_isar_feature(aa64_fp16, s)) { |
95f9864f RH |
6135 | unallocated_encoding(s); |
6136 | return; | |
6137 | } | |
6138 | if (!fp_access_check(s)) { | |
6139 | return; | |
6140 | } | |
6141 | handle_fp_3src_half(s, o0, o1, rd, rn, rm, ra); | |
6142 | break; | |
6a30667f AG |
6143 | default: |
6144 | unallocated_encoding(s); | |
6145 | } | |
faa0ba46 PM |
6146 | } |
6147 | ||
e90a99fe RH |
6148 | /* The imm8 encodes the sign bit, enough bits to represent an exponent in |
6149 | * the range 01....1xx to 10....0xx, and the most significant 4 bits of | |
6150 | * the mantissa; see VFPExpandImm() in the v8 ARM ARM. | |
6151 | */ | |
8c71baed | 6152 | uint64_t vfp_expand_imm(int size, uint8_t imm8) |
e90a99fe RH |
6153 | { |
6154 | uint64_t imm; | |
6155 | ||
6156 | switch (size) { | |
6157 | case MO_64: | |
6158 | imm = (extract32(imm8, 7, 1) ? 0x8000 : 0) | | |
6159 | (extract32(imm8, 6, 1) ? 0x3fc0 : 0x4000) | | |
6160 | extract32(imm8, 0, 6); | |
6161 | imm <<= 48; | |
6162 | break; | |
6163 | case MO_32: | |
6164 | imm = (extract32(imm8, 7, 1) ? 0x8000 : 0) | | |
6165 | (extract32(imm8, 6, 1) ? 0x3e00 : 0x4000) | | |
6166 | (extract32(imm8, 0, 6) << 3); | |
6167 | imm <<= 16; | |
6168 | break; | |
8081796a RH |
6169 | case MO_16: |
6170 | imm = (extract32(imm8, 7, 1) ? 0x8000 : 0) | | |
6171 | (extract32(imm8, 6, 1) ? 0x3000 : 0x4000) | | |
6172 | (extract32(imm8, 0, 6) << 6); | |
6173 | break; | |
e90a99fe RH |
6174 | default: |
6175 | g_assert_not_reached(); | |
6176 | } | |
6177 | return imm; | |
6178 | } | |
6179 | ||
4ce31af4 | 6180 | /* Floating point immediate |
faa0ba46 PM |
6181 | * 31 30 29 28 24 23 22 21 20 13 12 10 9 5 4 0 |
6182 | * +---+---+---+-----------+------+---+------------+-------+------+------+ | |
6183 | * | M | 0 | S | 1 1 1 1 0 | type | 1 | imm8 | 1 0 0 | imm5 | Rd | | |
6184 | * +---+---+---+-----------+------+---+------------+-------+------+------+ | |
6185 | */ | |
6186 | static void disas_fp_imm(DisasContext *s, uint32_t insn) | |
6187 | { | |
6163f868 | 6188 | int rd = extract32(insn, 0, 5); |
c1e20801 | 6189 | int imm5 = extract32(insn, 5, 5); |
6163f868 | 6190 | int imm8 = extract32(insn, 13, 8); |
6ba28ddb | 6191 | int type = extract32(insn, 22, 2); |
c1e20801 | 6192 | int mos = extract32(insn, 29, 3); |
6163f868 AG |
6193 | uint64_t imm; |
6194 | TCGv_i64 tcg_res; | |
6ba28ddb | 6195 | TCGMemOp sz; |
6163f868 | 6196 | |
c1e20801 PM |
6197 | if (mos || imm5) { |
6198 | unallocated_encoding(s); | |
6199 | return; | |
6200 | } | |
6201 | ||
6ba28ddb AB |
6202 | switch (type) { |
6203 | case 0: | |
6204 | sz = MO_32; | |
6205 | break; | |
6206 | case 1: | |
6207 | sz = MO_64; | |
6208 | break; | |
6209 | case 3: | |
6210 | sz = MO_16; | |
5763190f | 6211 | if (dc_isar_feature(aa64_fp16, s)) { |
6ba28ddb AB |
6212 | break; |
6213 | } | |
6214 | /* fallthru */ | |
6215 | default: | |
6163f868 AG |
6216 | unallocated_encoding(s); |
6217 | return; | |
6218 | } | |
6219 | ||
8c6afa6a PM |
6220 | if (!fp_access_check(s)) { |
6221 | return; | |
6222 | } | |
6223 | ||
6ba28ddb | 6224 | imm = vfp_expand_imm(sz, imm8); |
6163f868 AG |
6225 | |
6226 | tcg_res = tcg_const_i64(imm); | |
6227 | write_fp_dreg(s, rd, tcg_res); | |
6228 | tcg_temp_free_i64(tcg_res); | |
faa0ba46 PM |
6229 | } |
6230 | ||
52a1f6a3 AG |
6231 | /* Handle floating point <=> fixed point conversions. Note that we can |
6232 | * also deal with fp <=> integer conversions as a special case (scale == 64) | |
6233 | * OPTME: consider handling that special case specially or at least skipping | |
6234 | * the call to scalbn in the helpers for zero shifts. | |
6235 | */ | |
6236 | static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode, | |
6237 | bool itof, int rmode, int scale, int sf, int type) | |
6238 | { | |
6239 | bool is_signed = !(opcode & 1); | |
52a1f6a3 | 6240 | TCGv_ptr tcg_fpstatus; |
564a0632 RH |
6241 | TCGv_i32 tcg_shift, tcg_single; |
6242 | TCGv_i64 tcg_double; | |
52a1f6a3 | 6243 | |
564a0632 | 6244 | tcg_fpstatus = get_fpstatus_ptr(type == 3); |
52a1f6a3 AG |
6245 | |
6246 | tcg_shift = tcg_const_i32(64 - scale); | |
6247 | ||
6248 | if (itof) { | |
6249 | TCGv_i64 tcg_int = cpu_reg(s, rn); | |
6250 | if (!sf) { | |
6251 | TCGv_i64 tcg_extend = new_tmp_a64(s); | |
6252 | ||
6253 | if (is_signed) { | |
6254 | tcg_gen_ext32s_i64(tcg_extend, tcg_int); | |
6255 | } else { | |
6256 | tcg_gen_ext32u_i64(tcg_extend, tcg_int); | |
6257 | } | |
6258 | ||
6259 | tcg_int = tcg_extend; | |
6260 | } | |
6261 | ||
564a0632 RH |
6262 | switch (type) { |
6263 | case 1: /* float64 */ | |
6264 | tcg_double = tcg_temp_new_i64(); | |
52a1f6a3 AG |
6265 | if (is_signed) { |
6266 | gen_helper_vfp_sqtod(tcg_double, tcg_int, | |
6267 | tcg_shift, tcg_fpstatus); | |
6268 | } else { | |
6269 | gen_helper_vfp_uqtod(tcg_double, tcg_int, | |
6270 | tcg_shift, tcg_fpstatus); | |
6271 | } | |
6272 | write_fp_dreg(s, rd, tcg_double); | |
6273 | tcg_temp_free_i64(tcg_double); | |
564a0632 RH |
6274 | break; |
6275 | ||
6276 | case 0: /* float32 */ | |
6277 | tcg_single = tcg_temp_new_i32(); | |
52a1f6a3 AG |
6278 | if (is_signed) { |
6279 | gen_helper_vfp_sqtos(tcg_single, tcg_int, | |
6280 | tcg_shift, tcg_fpstatus); | |
6281 | } else { | |
6282 | gen_helper_vfp_uqtos(tcg_single, tcg_int, | |
6283 | tcg_shift, tcg_fpstatus); | |
6284 | } | |
6285 | write_fp_sreg(s, rd, tcg_single); | |
6286 | tcg_temp_free_i32(tcg_single); | |
564a0632 RH |
6287 | break; |
6288 | ||
6289 | case 3: /* float16 */ | |
6290 | tcg_single = tcg_temp_new_i32(); | |
6291 | if (is_signed) { | |
6292 | gen_helper_vfp_sqtoh(tcg_single, tcg_int, | |
6293 | tcg_shift, tcg_fpstatus); | |
6294 | } else { | |
6295 | gen_helper_vfp_uqtoh(tcg_single, tcg_int, | |
6296 | tcg_shift, tcg_fpstatus); | |
6297 | } | |
6298 | write_fp_sreg(s, rd, tcg_single); | |
6299 | tcg_temp_free_i32(tcg_single); | |
6300 | break; | |
6301 | ||
6302 | default: | |
6303 | g_assert_not_reached(); | |
52a1f6a3 AG |
6304 | } |
6305 | } else { | |
6306 | TCGv_i64 tcg_int = cpu_reg(s, rd); | |
6307 | TCGv_i32 tcg_rmode; | |
6308 | ||
6309 | if (extract32(opcode, 2, 1)) { | |
6310 | /* There are too many rounding modes to all fit into rmode, | |
6311 | * so FCVTA[US] is a special case. | |
6312 | */ | |
6313 | rmode = FPROUNDING_TIEAWAY; | |
6314 | } | |
6315 | ||
6316 | tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode)); | |
6317 | ||
9b049916 | 6318 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); |
52a1f6a3 | 6319 | |
564a0632 RH |
6320 | switch (type) { |
6321 | case 1: /* float64 */ | |
6322 | tcg_double = read_fp_dreg(s, rn); | |
52a1f6a3 AG |
6323 | if (is_signed) { |
6324 | if (!sf) { | |
6325 | gen_helper_vfp_tosld(tcg_int, tcg_double, | |
6326 | tcg_shift, tcg_fpstatus); | |
6327 | } else { | |
6328 | gen_helper_vfp_tosqd(tcg_int, tcg_double, | |
6329 | tcg_shift, tcg_fpstatus); | |
6330 | } | |
6331 | } else { | |
6332 | if (!sf) { | |
6333 | gen_helper_vfp_tould(tcg_int, tcg_double, | |
6334 | tcg_shift, tcg_fpstatus); | |
6335 | } else { | |
6336 | gen_helper_vfp_touqd(tcg_int, tcg_double, | |
6337 | tcg_shift, tcg_fpstatus); | |
6338 | } | |
6339 | } | |
564a0632 RH |
6340 | if (!sf) { |
6341 | tcg_gen_ext32u_i64(tcg_int, tcg_int); | |
6342 | } | |
52a1f6a3 | 6343 | tcg_temp_free_i64(tcg_double); |
564a0632 RH |
6344 | break; |
6345 | ||
6346 | case 0: /* float32 */ | |
6347 | tcg_single = read_fp_sreg(s, rn); | |
52a1f6a3 AG |
6348 | if (sf) { |
6349 | if (is_signed) { | |
6350 | gen_helper_vfp_tosqs(tcg_int, tcg_single, | |
6351 | tcg_shift, tcg_fpstatus); | |
6352 | } else { | |
6353 | gen_helper_vfp_touqs(tcg_int, tcg_single, | |
6354 | tcg_shift, tcg_fpstatus); | |
6355 | } | |
6356 | } else { | |
6357 | TCGv_i32 tcg_dest = tcg_temp_new_i32(); | |
6358 | if (is_signed) { | |
6359 | gen_helper_vfp_tosls(tcg_dest, tcg_single, | |
6360 | tcg_shift, tcg_fpstatus); | |
6361 | } else { | |
6362 | gen_helper_vfp_touls(tcg_dest, tcg_single, | |
6363 | tcg_shift, tcg_fpstatus); | |
6364 | } | |
6365 | tcg_gen_extu_i32_i64(tcg_int, tcg_dest); | |
6366 | tcg_temp_free_i32(tcg_dest); | |
6367 | } | |
6368 | tcg_temp_free_i32(tcg_single); | |
564a0632 RH |
6369 | break; |
6370 | ||
6371 | case 3: /* float16 */ | |
6372 | tcg_single = read_fp_sreg(s, rn); | |
6373 | if (sf) { | |
6374 | if (is_signed) { | |
6375 | gen_helper_vfp_tosqh(tcg_int, tcg_single, | |
6376 | tcg_shift, tcg_fpstatus); | |
6377 | } else { | |
6378 | gen_helper_vfp_touqh(tcg_int, tcg_single, | |
6379 | tcg_shift, tcg_fpstatus); | |
6380 | } | |
6381 | } else { | |
6382 | TCGv_i32 tcg_dest = tcg_temp_new_i32(); | |
6383 | if (is_signed) { | |
6384 | gen_helper_vfp_toslh(tcg_dest, tcg_single, | |
6385 | tcg_shift, tcg_fpstatus); | |
6386 | } else { | |
6387 | gen_helper_vfp_toulh(tcg_dest, tcg_single, | |
6388 | tcg_shift, tcg_fpstatus); | |
6389 | } | |
6390 | tcg_gen_extu_i32_i64(tcg_int, tcg_dest); | |
6391 | tcg_temp_free_i32(tcg_dest); | |
6392 | } | |
6393 | tcg_temp_free_i32(tcg_single); | |
6394 | break; | |
6395 | ||
6396 | default: | |
6397 | g_assert_not_reached(); | |
52a1f6a3 AG |
6398 | } |
6399 | ||
9b049916 | 6400 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); |
52a1f6a3 | 6401 | tcg_temp_free_i32(tcg_rmode); |
52a1f6a3 AG |
6402 | } |
6403 | ||
6404 | tcg_temp_free_ptr(tcg_fpstatus); | |
6405 | tcg_temp_free_i32(tcg_shift); | |
6406 | } | |
6407 | ||
4ce31af4 | 6408 | /* Floating point <-> fixed point conversions |
faa0ba46 PM |
6409 | * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0 |
6410 | * +----+---+---+-----------+------+---+-------+--------+-------+------+------+ | |
6411 | * | sf | 0 | S | 1 1 1 1 0 | type | 0 | rmode | opcode | scale | Rn | Rd | | |
6412 | * +----+---+---+-----------+------+---+-------+--------+-------+------+------+ | |
6413 | */ | |
6414 | static void disas_fp_fixed_conv(DisasContext *s, uint32_t insn) | |
6415 | { | |
52a1f6a3 AG |
6416 | int rd = extract32(insn, 0, 5); |
6417 | int rn = extract32(insn, 5, 5); | |
6418 | int scale = extract32(insn, 10, 6); | |
6419 | int opcode = extract32(insn, 16, 3); | |
6420 | int rmode = extract32(insn, 19, 2); | |
6421 | int type = extract32(insn, 22, 2); | |
6422 | bool sbit = extract32(insn, 29, 1); | |
6423 | bool sf = extract32(insn, 31, 1); | |
6424 | bool itof; | |
6425 | ||
27527280 RH |
6426 | if (sbit || (!sf && scale < 32)) { |
6427 | unallocated_encoding(s); | |
6428 | return; | |
6429 | } | |
6430 | ||
6431 | switch (type) { | |
6432 | case 0: /* float32 */ | |
6433 | case 1: /* float64 */ | |
6434 | break; | |
6435 | case 3: /* float16 */ | |
5763190f | 6436 | if (dc_isar_feature(aa64_fp16, s)) { |
27527280 RH |
6437 | break; |
6438 | } | |
6439 | /* fallthru */ | |
6440 | default: | |
52a1f6a3 AG |
6441 | unallocated_encoding(s); |
6442 | return; | |
6443 | } | |
6444 | ||
6445 | switch ((rmode << 3) | opcode) { | |
6446 | case 0x2: /* SCVTF */ | |
6447 | case 0x3: /* UCVTF */ | |
6448 | itof = true; | |
6449 | break; | |
6450 | case 0x18: /* FCVTZS */ | |
6451 | case 0x19: /* FCVTZU */ | |
6452 | itof = false; | |
6453 | break; | |
6454 | default: | |
6455 | unallocated_encoding(s); | |
6456 | return; | |
6457 | } | |
6458 | ||
8c6afa6a PM |
6459 | if (!fp_access_check(s)) { |
6460 | return; | |
6461 | } | |
6462 | ||
52a1f6a3 | 6463 | handle_fpfpcvt(s, rd, rn, opcode, itof, FPROUNDING_ZERO, scale, sf, type); |
faa0ba46 PM |
6464 | } |
6465 | ||
ce5458e8 PM |
6466 | static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof) |
6467 | { | |
6468 | /* FMOV: gpr to or from float, double, or top half of quad fp reg, | |
6469 | * without conversion. | |
6470 | */ | |
6471 | ||
6472 | if (itof) { | |
ce5458e8 | 6473 | TCGv_i64 tcg_rn = cpu_reg(s, rn); |
9a9f1f59 | 6474 | TCGv_i64 tmp; |
ce5458e8 PM |
6475 | |
6476 | switch (type) { | |
6477 | case 0: | |
ce5458e8 | 6478 | /* 32 bit */ |
9a9f1f59 | 6479 | tmp = tcg_temp_new_i64(); |
ce5458e8 | 6480 | tcg_gen_ext32u_i64(tmp, tcg_rn); |
9a9f1f59 | 6481 | write_fp_dreg(s, rd, tmp); |
ce5458e8 PM |
6482 | tcg_temp_free_i64(tmp); |
6483 | break; | |
ce5458e8 | 6484 | case 1: |
ce5458e8 | 6485 | /* 64 bit */ |
9a9f1f59 | 6486 | write_fp_dreg(s, rd, tcg_rn); |
ce5458e8 | 6487 | break; |
ce5458e8 PM |
6488 | case 2: |
6489 | /* 64 bit to top half. */ | |
90e49638 | 6490 | tcg_gen_st_i64(tcg_rn, cpu_env, fp_reg_hi_offset(s, rd)); |
9a9f1f59 | 6491 | clear_vec_high(s, true, rd); |
ce5458e8 | 6492 | break; |
68130236 RH |
6493 | case 3: |
6494 | /* 16 bit */ | |
6495 | tmp = tcg_temp_new_i64(); | |
6496 | tcg_gen_ext16u_i64(tmp, tcg_rn); | |
6497 | write_fp_dreg(s, rd, tmp); | |
6498 | tcg_temp_free_i64(tmp); | |
6499 | break; | |
6500 | default: | |
6501 | g_assert_not_reached(); | |
ce5458e8 PM |
6502 | } |
6503 | } else { | |
ce5458e8 PM |
6504 | TCGv_i64 tcg_rd = cpu_reg(s, rd); |
6505 | ||
6506 | switch (type) { | |
6507 | case 0: | |
6508 | /* 32 bit */ | |
90e49638 | 6509 | tcg_gen_ld32u_i64(tcg_rd, cpu_env, fp_reg_offset(s, rn, MO_32)); |
ce5458e8 | 6510 | break; |
ce5458e8 PM |
6511 | case 1: |
6512 | /* 64 bit */ | |
90e49638 | 6513 | tcg_gen_ld_i64(tcg_rd, cpu_env, fp_reg_offset(s, rn, MO_64)); |
e2f90565 PM |
6514 | break; |
6515 | case 2: | |
6516 | /* 64 bits from top half */ | |
90e49638 | 6517 | tcg_gen_ld_i64(tcg_rd, cpu_env, fp_reg_hi_offset(s, rn)); |
ce5458e8 | 6518 | break; |
68130236 RH |
6519 | case 3: |
6520 | /* 16 bit */ | |
6521 | tcg_gen_ld16u_i64(tcg_rd, cpu_env, fp_reg_offset(s, rn, MO_16)); | |
6522 | break; | |
6523 | default: | |
6524 | g_assert_not_reached(); | |
ce5458e8 PM |
6525 | } |
6526 | } | |
6527 | } | |
6528 | ||
6c1f6f27 RH |
6529 | static void handle_fjcvtzs(DisasContext *s, int rd, int rn) |
6530 | { | |
6531 | TCGv_i64 t = read_fp_dreg(s, rn); | |
6532 | TCGv_ptr fpstatus = get_fpstatus_ptr(false); | |
6533 | ||
6534 | gen_helper_fjcvtzs(t, t, fpstatus); | |
6535 | ||
6536 | tcg_temp_free_ptr(fpstatus); | |
6537 | ||
6538 | tcg_gen_ext32u_i64(cpu_reg(s, rd), t); | |
6539 | tcg_gen_extrh_i64_i32(cpu_ZF, t); | |
6540 | tcg_gen_movi_i32(cpu_CF, 0); | |
6541 | tcg_gen_movi_i32(cpu_NF, 0); | |
6542 | tcg_gen_movi_i32(cpu_VF, 0); | |
6543 | ||
6544 | tcg_temp_free_i64(t); | |
6545 | } | |
6546 | ||
4ce31af4 | 6547 | /* Floating point <-> integer conversions |
faa0ba46 PM |
6548 | * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0 |
6549 | * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+ | |
c436d406 | 6550 | * | sf | 0 | S | 1 1 1 1 0 | type | 1 | rmode | opc | 0 0 0 0 0 0 | Rn | Rd | |
faa0ba46 PM |
6551 | * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+ |
6552 | */ | |
6553 | static void disas_fp_int_conv(DisasContext *s, uint32_t insn) | |
6554 | { | |
ce5458e8 PM |
6555 | int rd = extract32(insn, 0, 5); |
6556 | int rn = extract32(insn, 5, 5); | |
6557 | int opcode = extract32(insn, 16, 3); | |
6558 | int rmode = extract32(insn, 19, 2); | |
6559 | int type = extract32(insn, 22, 2); | |
6560 | bool sbit = extract32(insn, 29, 1); | |
6561 | bool sf = extract32(insn, 31, 1); | |
3c3ff684 | 6562 | bool itof = false; |
ce5458e8 | 6563 | |
c436d406 | 6564 | if (sbit) { |
3c3ff684 | 6565 | goto do_unallocated; |
c436d406 WN |
6566 | } |
6567 | ||
3c3ff684 RH |
6568 | switch (opcode) { |
6569 | case 2: /* SCVTF */ | |
6570 | case 3: /* UCVTF */ | |
6571 | itof = true; | |
6572 | /* fallthru */ | |
6573 | case 4: /* FCVTAS */ | |
6574 | case 5: /* FCVTAU */ | |
6575 | if (rmode != 0) { | |
6576 | goto do_unallocated; | |
c436d406 | 6577 | } |
3c3ff684 RH |
6578 | /* fallthru */ |
6579 | case 0: /* FCVT[NPMZ]S */ | |
6580 | case 1: /* FCVT[NPMZ]U */ | |
6581 | switch (type) { | |
6582 | case 0: /* float32 */ | |
6583 | case 1: /* float64 */ | |
ce5458e8 | 6584 | break; |
3c3ff684 RH |
6585 | case 3: /* float16 */ |
6586 | if (!dc_isar_feature(aa64_fp16, s)) { | |
6587 | goto do_unallocated; | |
68130236 | 6588 | } |
3c3ff684 | 6589 | break; |
ce5458e8 | 6590 | default: |
3c3ff684 | 6591 | goto do_unallocated; |
ce5458e8 | 6592 | } |
8c6afa6a PM |
6593 | if (!fp_access_check(s)) { |
6594 | return; | |
6595 | } | |
3c3ff684 RH |
6596 | handle_fpfpcvt(s, rd, rn, opcode, itof, rmode, 64, sf, type); |
6597 | break; | |
c436d406 | 6598 | |
3c3ff684 RH |
6599 | default: |
6600 | switch (sf << 7 | type << 5 | rmode << 3 | opcode) { | |
6601 | case 0b01100110: /* FMOV half <-> 32-bit int */ | |
6602 | case 0b01100111: | |
6603 | case 0b11100110: /* FMOV half <-> 64-bit int */ | |
6604 | case 0b11100111: | |
6605 | if (!dc_isar_feature(aa64_fp16, s)) { | |
6606 | goto do_unallocated; | |
564a0632 RH |
6607 | } |
6608 | /* fallthru */ | |
3c3ff684 RH |
6609 | case 0b00000110: /* FMOV 32-bit */ |
6610 | case 0b00000111: | |
6611 | case 0b10100110: /* FMOV 64-bit */ | |
6612 | case 0b10100111: | |
6613 | case 0b11001110: /* FMOV top half of 128-bit */ | |
6614 | case 0b11001111: | |
6615 | if (!fp_access_check(s)) { | |
6616 | return; | |
6617 | } | |
6618 | itof = opcode & 1; | |
6619 | handle_fmov(s, rd, rn, type, itof); | |
6620 | break; | |
6621 | ||
6c1f6f27 RH |
6622 | case 0b00111110: /* FJCVTZS */ |
6623 | if (!dc_isar_feature(aa64_jscvt, s)) { | |
6624 | goto do_unallocated; | |
6625 | } else if (fp_access_check(s)) { | |
6626 | handle_fjcvtzs(s, rd, rn); | |
6627 | } | |
6628 | break; | |
6629 | ||
564a0632 | 6630 | default: |
3c3ff684 | 6631 | do_unallocated: |
c436d406 WN |
6632 | unallocated_encoding(s); |
6633 | return; | |
6634 | } | |
3c3ff684 | 6635 | break; |
ce5458e8 | 6636 | } |
faa0ba46 PM |
6637 | } |
6638 | ||
6639 | /* FP-specific subcases of table C3-6 (SIMD and FP data processing) | |
6640 | * 31 30 29 28 25 24 0 | |
6641 | * +---+---+---+---------+-----------------------------+ | |
6642 | * | | 0 | | 1 1 1 1 | | | |
6643 | * +---+---+---+---------+-----------------------------+ | |
6644 | */ | |
6645 | static void disas_data_proc_fp(DisasContext *s, uint32_t insn) | |
6646 | { | |
6647 | if (extract32(insn, 24, 1)) { | |
6648 | /* Floating point data-processing (3 source) */ | |
6649 | disas_fp_3src(s, insn); | |
6650 | } else if (extract32(insn, 21, 1) == 0) { | |
6651 | /* Floating point to fixed point conversions */ | |
6652 | disas_fp_fixed_conv(s, insn); | |
6653 | } else { | |
6654 | switch (extract32(insn, 10, 2)) { | |
6655 | case 1: | |
6656 | /* Floating point conditional compare */ | |
6657 | disas_fp_ccomp(s, insn); | |
6658 | break; | |
6659 | case 2: | |
6660 | /* Floating point data-processing (2 source) */ | |
6661 | disas_fp_2src(s, insn); | |
6662 | break; | |
6663 | case 3: | |
6664 | /* Floating point conditional select */ | |
6665 | disas_fp_csel(s, insn); | |
6666 | break; | |
6667 | case 0: | |
6668 | switch (ctz32(extract32(insn, 12, 4))) { | |
6669 | case 0: /* [15:12] == xxx1 */ | |
6670 | /* Floating point immediate */ | |
6671 | disas_fp_imm(s, insn); | |
6672 | break; | |
6673 | case 1: /* [15:12] == xx10 */ | |
6674 | /* Floating point compare */ | |
6675 | disas_fp_compare(s, insn); | |
6676 | break; | |
6677 | case 2: /* [15:12] == x100 */ | |
6678 | /* Floating point data-processing (1 source) */ | |
6679 | disas_fp_1src(s, insn); | |
6680 | break; | |
6681 | case 3: /* [15:12] == 1000 */ | |
6682 | unallocated_encoding(s); | |
6683 | break; | |
6684 | default: /* [15:12] == 0000 */ | |
6685 | /* Floating point <-> integer conversions */ | |
6686 | disas_fp_int_conv(s, insn); | |
6687 | break; | |
6688 | } | |
6689 | break; | |
6690 | } | |
6691 | } | |
6692 | } | |
6693 | ||
5c73747f PM |
6694 | static void do_ext64(DisasContext *s, TCGv_i64 tcg_left, TCGv_i64 tcg_right, |
6695 | int pos) | |
6696 | { | |
6697 | /* Extract 64 bits from the middle of two concatenated 64 bit | |
6698 | * vector register slices left:right. The extracted bits start | |
6699 | * at 'pos' bits into the right (least significant) side. | |
6700 | * We return the result in tcg_right, and guarantee not to | |
6701 | * trash tcg_left. | |
6702 | */ | |
6703 | TCGv_i64 tcg_tmp = tcg_temp_new_i64(); | |
6704 | assert(pos > 0 && pos < 64); | |
6705 | ||
6706 | tcg_gen_shri_i64(tcg_right, tcg_right, pos); | |
6707 | tcg_gen_shli_i64(tcg_tmp, tcg_left, 64 - pos); | |
6708 | tcg_gen_or_i64(tcg_right, tcg_right, tcg_tmp); | |
6709 | ||
6710 | tcg_temp_free_i64(tcg_tmp); | |
6711 | } | |
6712 | ||
4ce31af4 | 6713 | /* EXT |
384b26fb AB |
6714 | * 31 30 29 24 23 22 21 20 16 15 14 11 10 9 5 4 0 |
6715 | * +---+---+-------------+-----+---+------+---+------+---+------+------+ | |
6716 | * | 0 | Q | 1 0 1 1 1 0 | op2 | 0 | Rm | 0 | imm4 | 0 | Rn | Rd | | |
6717 | * +---+---+-------------+-----+---+------+---+------+---+------+------+ | |
6718 | */ | |
6719 | static void disas_simd_ext(DisasContext *s, uint32_t insn) | |
6720 | { | |
5c73747f PM |
6721 | int is_q = extract32(insn, 30, 1); |
6722 | int op2 = extract32(insn, 22, 2); | |
6723 | int imm4 = extract32(insn, 11, 4); | |
6724 | int rm = extract32(insn, 16, 5); | |
6725 | int rn = extract32(insn, 5, 5); | |
6726 | int rd = extract32(insn, 0, 5); | |
6727 | int pos = imm4 << 3; | |
6728 | TCGv_i64 tcg_resl, tcg_resh; | |
6729 | ||
6730 | if (op2 != 0 || (!is_q && extract32(imm4, 3, 1))) { | |
6731 | unallocated_encoding(s); | |
6732 | return; | |
6733 | } | |
6734 | ||
8c6afa6a PM |
6735 | if (!fp_access_check(s)) { |
6736 | return; | |
6737 | } | |
6738 | ||
5c73747f PM |
6739 | tcg_resh = tcg_temp_new_i64(); |
6740 | tcg_resl = tcg_temp_new_i64(); | |
6741 | ||
6742 | /* Vd gets bits starting at pos bits into Vm:Vn. This is | |
6743 | * either extracting 128 bits from a 128:128 concatenation, or | |
6744 | * extracting 64 bits from a 64:64 concatenation. | |
6745 | */ | |
6746 | if (!is_q) { | |
6747 | read_vec_element(s, tcg_resl, rn, 0, MO_64); | |
6748 | if (pos != 0) { | |
6749 | read_vec_element(s, tcg_resh, rm, 0, MO_64); | |
6750 | do_ext64(s, tcg_resh, tcg_resl, pos); | |
6751 | } | |
6752 | tcg_gen_movi_i64(tcg_resh, 0); | |
6753 | } else { | |
6754 | TCGv_i64 tcg_hh; | |
6755 | typedef struct { | |
6756 | int reg; | |
6757 | int elt; | |
6758 | } EltPosns; | |
6759 | EltPosns eltposns[] = { {rn, 0}, {rn, 1}, {rm, 0}, {rm, 1} }; | |
6760 | EltPosns *elt = eltposns; | |
6761 | ||
6762 | if (pos >= 64) { | |
6763 | elt++; | |
6764 | pos -= 64; | |
6765 | } | |
6766 | ||
6767 | read_vec_element(s, tcg_resl, elt->reg, elt->elt, MO_64); | |
6768 | elt++; | |
6769 | read_vec_element(s, tcg_resh, elt->reg, elt->elt, MO_64); | |
6770 | elt++; | |
6771 | if (pos != 0) { | |
6772 | do_ext64(s, tcg_resh, tcg_resl, pos); | |
6773 | tcg_hh = tcg_temp_new_i64(); | |
6774 | read_vec_element(s, tcg_hh, elt->reg, elt->elt, MO_64); | |
6775 | do_ext64(s, tcg_hh, tcg_resh, pos); | |
6776 | tcg_temp_free_i64(tcg_hh); | |
6777 | } | |
6778 | } | |
6779 | ||
6780 | write_vec_element(s, tcg_resl, rd, 0, MO_64); | |
6781 | tcg_temp_free_i64(tcg_resl); | |
6782 | write_vec_element(s, tcg_resh, rd, 1, MO_64); | |
6783 | tcg_temp_free_i64(tcg_resh); | |
384b26fb AB |
6784 | } |
6785 | ||
4ce31af4 | 6786 | /* TBL/TBX |
384b26fb AB |
6787 | * 31 30 29 24 23 22 21 20 16 15 14 13 12 11 10 9 5 4 0 |
6788 | * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+ | |
6789 | * | 0 | Q | 0 0 1 1 1 0 | op2 | 0 | Rm | 0 | len | op | 0 0 | Rn | Rd | | |
6790 | * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+ | |
6791 | */ | |
6792 | static void disas_simd_tb(DisasContext *s, uint32_t insn) | |
6793 | { | |
7c51048f MM |
6794 | int op2 = extract32(insn, 22, 2); |
6795 | int is_q = extract32(insn, 30, 1); | |
6796 | int rm = extract32(insn, 16, 5); | |
6797 | int rn = extract32(insn, 5, 5); | |
6798 | int rd = extract32(insn, 0, 5); | |
6799 | int is_tblx = extract32(insn, 12, 1); | |
6800 | int len = extract32(insn, 13, 2); | |
6801 | TCGv_i64 tcg_resl, tcg_resh, tcg_idx; | |
6802 | TCGv_i32 tcg_regno, tcg_numregs; | |
6803 | ||
6804 | if (op2 != 0) { | |
6805 | unallocated_encoding(s); | |
6806 | return; | |
6807 | } | |
6808 | ||
8c6afa6a PM |
6809 | if (!fp_access_check(s)) { |
6810 | return; | |
6811 | } | |
6812 | ||
7c51048f MM |
6813 | /* This does a table lookup: for every byte element in the input |
6814 | * we index into a table formed from up to four vector registers, | |
6815 | * and then the output is the result of the lookups. Our helper | |
6816 | * function does the lookup operation for a single 64 bit part of | |
6817 | * the input. | |
6818 | */ | |
6819 | tcg_resl = tcg_temp_new_i64(); | |
6820 | tcg_resh = tcg_temp_new_i64(); | |
6821 | ||
6822 | if (is_tblx) { | |
6823 | read_vec_element(s, tcg_resl, rd, 0, MO_64); | |
6824 | } else { | |
6825 | tcg_gen_movi_i64(tcg_resl, 0); | |
6826 | } | |
6827 | if (is_tblx && is_q) { | |
6828 | read_vec_element(s, tcg_resh, rd, 1, MO_64); | |
6829 | } else { | |
6830 | tcg_gen_movi_i64(tcg_resh, 0); | |
6831 | } | |
6832 | ||
6833 | tcg_idx = tcg_temp_new_i64(); | |
6834 | tcg_regno = tcg_const_i32(rn); | |
6835 | tcg_numregs = tcg_const_i32(len + 1); | |
6836 | read_vec_element(s, tcg_idx, rm, 0, MO_64); | |
6837 | gen_helper_simd_tbl(tcg_resl, cpu_env, tcg_resl, tcg_idx, | |
6838 | tcg_regno, tcg_numregs); | |
6839 | if (is_q) { | |
6840 | read_vec_element(s, tcg_idx, rm, 1, MO_64); | |
6841 | gen_helper_simd_tbl(tcg_resh, cpu_env, tcg_resh, tcg_idx, | |
6842 | tcg_regno, tcg_numregs); | |
6843 | } | |
6844 | tcg_temp_free_i64(tcg_idx); | |
6845 | tcg_temp_free_i32(tcg_regno); | |
6846 | tcg_temp_free_i32(tcg_numregs); | |
6847 | ||
6848 | write_vec_element(s, tcg_resl, rd, 0, MO_64); | |
6849 | tcg_temp_free_i64(tcg_resl); | |
6850 | write_vec_element(s, tcg_resh, rd, 1, MO_64); | |
6851 | tcg_temp_free_i64(tcg_resh); | |
384b26fb AB |
6852 | } |
6853 | ||
4ce31af4 | 6854 | /* ZIP/UZP/TRN |
384b26fb AB |
6855 | * 31 30 29 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0 |
6856 | * +---+---+-------------+------+---+------+---+------------------+------+ | |
6857 | * | 0 | Q | 0 0 1 1 1 0 | size | 0 | Rm | 0 | opc | 1 0 | Rn | Rd | | |
6858 | * +---+---+-------------+------+---+------+---+------------------+------+ | |
6859 | */ | |
6860 | static void disas_simd_zip_trn(DisasContext *s, uint32_t insn) | |
6861 | { | |
5fa5469c MM |
6862 | int rd = extract32(insn, 0, 5); |
6863 | int rn = extract32(insn, 5, 5); | |
6864 | int rm = extract32(insn, 16, 5); | |
6865 | int size = extract32(insn, 22, 2); | |
6866 | /* opc field bits [1:0] indicate ZIP/UZP/TRN; | |
6867 | * bit 2 indicates 1 vs 2 variant of the insn. | |
6868 | */ | |
6869 | int opcode = extract32(insn, 12, 2); | |
6870 | bool part = extract32(insn, 14, 1); | |
6871 | bool is_q = extract32(insn, 30, 1); | |
6872 | int esize = 8 << size; | |
6873 | int i, ofs; | |
6874 | int datasize = is_q ? 128 : 64; | |
6875 | int elements = datasize / esize; | |
6876 | TCGv_i64 tcg_res, tcg_resl, tcg_resh; | |
6877 | ||
6878 | if (opcode == 0 || (size == 3 && !is_q)) { | |
6879 | unallocated_encoding(s); | |
6880 | return; | |
6881 | } | |
6882 | ||
8c6afa6a PM |
6883 | if (!fp_access_check(s)) { |
6884 | return; | |
6885 | } | |
6886 | ||
5fa5469c MM |
6887 | tcg_resl = tcg_const_i64(0); |
6888 | tcg_resh = tcg_const_i64(0); | |
6889 | tcg_res = tcg_temp_new_i64(); | |
6890 | ||
6891 | for (i = 0; i < elements; i++) { | |
6892 | switch (opcode) { | |
6893 | case 1: /* UZP1/2 */ | |
6894 | { | |
6895 | int midpoint = elements / 2; | |
6896 | if (i < midpoint) { | |
6897 | read_vec_element(s, tcg_res, rn, 2 * i + part, size); | |
6898 | } else { | |
6899 | read_vec_element(s, tcg_res, rm, | |
6900 | 2 * (i - midpoint) + part, size); | |
6901 | } | |
6902 | break; | |
6903 | } | |
6904 | case 2: /* TRN1/2 */ | |
6905 | if (i & 1) { | |
6906 | read_vec_element(s, tcg_res, rm, (i & ~1) + part, size); | |
6907 | } else { | |
6908 | read_vec_element(s, tcg_res, rn, (i & ~1) + part, size); | |
6909 | } | |
6910 | break; | |
6911 | case 3: /* ZIP1/2 */ | |
6912 | { | |
6913 | int base = part * elements / 2; | |
6914 | if (i & 1) { | |
6915 | read_vec_element(s, tcg_res, rm, base + (i >> 1), size); | |
6916 | } else { | |
6917 | read_vec_element(s, tcg_res, rn, base + (i >> 1), size); | |
6918 | } | |
6919 | break; | |
6920 | } | |
6921 | default: | |
6922 | g_assert_not_reached(); | |
6923 | } | |
6924 | ||
6925 | ofs = i * esize; | |
6926 | if (ofs < 64) { | |
6927 | tcg_gen_shli_i64(tcg_res, tcg_res, ofs); | |
6928 | tcg_gen_or_i64(tcg_resl, tcg_resl, tcg_res); | |
6929 | } else { | |
6930 | tcg_gen_shli_i64(tcg_res, tcg_res, ofs - 64); | |
6931 | tcg_gen_or_i64(tcg_resh, tcg_resh, tcg_res); | |
6932 | } | |
6933 | } | |
6934 | ||
6935 | tcg_temp_free_i64(tcg_res); | |
6936 | ||
6937 | write_vec_element(s, tcg_resl, rd, 0, MO_64); | |
6938 | tcg_temp_free_i64(tcg_resl); | |
6939 | write_vec_element(s, tcg_resh, rd, 1, MO_64); | |
6940 | tcg_temp_free_i64(tcg_resh); | |
384b26fb AB |
6941 | } |
6942 | ||
807cdd50 AB |
6943 | /* |
6944 | * do_reduction_op helper | |
6945 | * | |
6946 | * This mirrors the Reduce() pseudocode in the ARM ARM. It is | |
6947 | * important for correct NaN propagation that we do these | |
6948 | * operations in exactly the order specified by the pseudocode. | |
6949 | * | |
6950 | * This is a recursive function, TCG temps should be freed by the | |
6951 | * calling function once it is done with the values. | |
6952 | */ | |
6953 | static TCGv_i32 do_reduction_op(DisasContext *s, int fpopcode, int rn, | |
6954 | int esize, int size, int vmap, TCGv_ptr fpst) | |
6955 | { | |
6956 | if (esize == size) { | |
6957 | int element; | |
6958 | TCGMemOp msize = esize == 16 ? MO_16 : MO_32; | |
6959 | TCGv_i32 tcg_elem; | |
6960 | ||
6961 | /* We should have one register left here */ | |
6962 | assert(ctpop8(vmap) == 1); | |
6963 | element = ctz32(vmap); | |
6964 | assert(element < 8); | |
6965 | ||
6966 | tcg_elem = tcg_temp_new_i32(); | |
6967 | read_vec_element_i32(s, tcg_elem, rn, element, msize); | |
6968 | return tcg_elem; | |
4a0ff1ce | 6969 | } else { |
807cdd50 AB |
6970 | int bits = size / 2; |
6971 | int shift = ctpop8(vmap) / 2; | |
6972 | int vmap_lo = (vmap >> shift) & vmap; | |
6973 | int vmap_hi = (vmap & ~vmap_lo); | |
6974 | TCGv_i32 tcg_hi, tcg_lo, tcg_res; | |
6975 | ||
6976 | tcg_hi = do_reduction_op(s, fpopcode, rn, esize, bits, vmap_hi, fpst); | |
6977 | tcg_lo = do_reduction_op(s, fpopcode, rn, esize, bits, vmap_lo, fpst); | |
6978 | tcg_res = tcg_temp_new_i32(); | |
6979 | ||
6980 | switch (fpopcode) { | |
6981 | case 0x0c: /* fmaxnmv half-precision */ | |
6982 | gen_helper_advsimd_maxnumh(tcg_res, tcg_lo, tcg_hi, fpst); | |
6983 | break; | |
6984 | case 0x0f: /* fmaxv half-precision */ | |
6985 | gen_helper_advsimd_maxh(tcg_res, tcg_lo, tcg_hi, fpst); | |
6986 | break; | |
6987 | case 0x1c: /* fminnmv half-precision */ | |
6988 | gen_helper_advsimd_minnumh(tcg_res, tcg_lo, tcg_hi, fpst); | |
6989 | break; | |
6990 | case 0x1f: /* fminv half-precision */ | |
6991 | gen_helper_advsimd_minh(tcg_res, tcg_lo, tcg_hi, fpst); | |
6992 | break; | |
6993 | case 0x2c: /* fmaxnmv */ | |
6994 | gen_helper_vfp_maxnums(tcg_res, tcg_lo, tcg_hi, fpst); | |
6995 | break; | |
6996 | case 0x2f: /* fmaxv */ | |
6997 | gen_helper_vfp_maxs(tcg_res, tcg_lo, tcg_hi, fpst); | |
6998 | break; | |
6999 | case 0x3c: /* fminnmv */ | |
7000 | gen_helper_vfp_minnums(tcg_res, tcg_lo, tcg_hi, fpst); | |
7001 | break; | |
7002 | case 0x3f: /* fminv */ | |
7003 | gen_helper_vfp_mins(tcg_res, tcg_lo, tcg_hi, fpst); | |
7004 | break; | |
7005 | default: | |
7006 | g_assert_not_reached(); | |
4a0ff1ce | 7007 | } |
807cdd50 AB |
7008 | |
7009 | tcg_temp_free_i32(tcg_hi); | |
7010 | tcg_temp_free_i32(tcg_lo); | |
7011 | return tcg_res; | |
4a0ff1ce MM |
7012 | } |
7013 | } | |
7014 | ||
4ce31af4 | 7015 | /* AdvSIMD across lanes |
384b26fb AB |
7016 | * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0 |
7017 | * +---+---+---+-----------+------+-----------+--------+-----+------+------+ | |
7018 | * | 0 | Q | U | 0 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd | | |
7019 | * +---+---+---+-----------+------+-----------+--------+-----+------+------+ | |
7020 | */ | |
7021 | static void disas_simd_across_lanes(DisasContext *s, uint32_t insn) | |
7022 | { | |
4a0ff1ce MM |
7023 | int rd = extract32(insn, 0, 5); |
7024 | int rn = extract32(insn, 5, 5); | |
7025 | int size = extract32(insn, 22, 2); | |
7026 | int opcode = extract32(insn, 12, 5); | |
7027 | bool is_q = extract32(insn, 30, 1); | |
7028 | bool is_u = extract32(insn, 29, 1); | |
7029 | bool is_fp = false; | |
7030 | bool is_min = false; | |
7031 | int esize; | |
7032 | int elements; | |
7033 | int i; | |
7034 | TCGv_i64 tcg_res, tcg_elt; | |
7035 | ||
7036 | switch (opcode) { | |
7037 | case 0x1b: /* ADDV */ | |
7038 | if (is_u) { | |
7039 | unallocated_encoding(s); | |
7040 | return; | |
7041 | } | |
7042 | /* fall through */ | |
7043 | case 0x3: /* SADDLV, UADDLV */ | |
7044 | case 0xa: /* SMAXV, UMAXV */ | |
7045 | case 0x1a: /* SMINV, UMINV */ | |
7046 | if (size == 3 || (size == 2 && !is_q)) { | |
7047 | unallocated_encoding(s); | |
7048 | return; | |
7049 | } | |
7050 | break; | |
7051 | case 0xc: /* FMAXNMV, FMINNMV */ | |
7052 | case 0xf: /* FMAXV, FMINV */ | |
807cdd50 AB |
7053 | /* Bit 1 of size field encodes min vs max and the actual size |
7054 | * depends on the encoding of the U bit. If not set (and FP16 | |
7055 | * enabled) then we do half-precision float instead of single | |
7056 | * precision. | |
4a0ff1ce MM |
7057 | */ |
7058 | is_min = extract32(size, 1, 1); | |
7059 | is_fp = true; | |
5763190f | 7060 | if (!is_u && dc_isar_feature(aa64_fp16, s)) { |
807cdd50 AB |
7061 | size = 1; |
7062 | } else if (!is_u || !is_q || extract32(size, 0, 1)) { | |
7063 | unallocated_encoding(s); | |
7064 | return; | |
7065 | } else { | |
7066 | size = 2; | |
7067 | } | |
4a0ff1ce MM |
7068 | break; |
7069 | default: | |
7070 | unallocated_encoding(s); | |
7071 | return; | |
7072 | } | |
7073 | ||
8c6afa6a PM |
7074 | if (!fp_access_check(s)) { |
7075 | return; | |
7076 | } | |
7077 | ||
4a0ff1ce MM |
7078 | esize = 8 << size; |
7079 | elements = (is_q ? 128 : 64) / esize; | |
7080 | ||
7081 | tcg_res = tcg_temp_new_i64(); | |
7082 | tcg_elt = tcg_temp_new_i64(); | |
7083 | ||
7084 | /* These instructions operate across all lanes of a vector | |
7085 | * to produce a single result. We can guarantee that a 64 | |
7086 | * bit intermediate is sufficient: | |
7087 | * + for [US]ADDLV the maximum element size is 32 bits, and | |
7088 | * the result type is 64 bits | |
7089 | * + for FMAX*V, FMIN*V, ADDV the intermediate type is the | |
7090 | * same as the element size, which is 32 bits at most | |
7091 | * For the integer operations we can choose to work at 64 | |
7092 | * or 32 bits and truncate at the end; for simplicity | |
7093 | * we use 64 bits always. The floating point | |
7094 | * ops do require 32 bit intermediates, though. | |
7095 | */ | |
7096 | if (!is_fp) { | |
7097 | read_vec_element(s, tcg_res, rn, 0, size | (is_u ? 0 : MO_SIGN)); | |
7098 | ||
7099 | for (i = 1; i < elements; i++) { | |
7100 | read_vec_element(s, tcg_elt, rn, i, size | (is_u ? 0 : MO_SIGN)); | |
7101 | ||
7102 | switch (opcode) { | |
7103 | case 0x03: /* SADDLV / UADDLV */ | |
7104 | case 0x1b: /* ADDV */ | |
7105 | tcg_gen_add_i64(tcg_res, tcg_res, tcg_elt); | |
7106 | break; | |
7107 | case 0x0a: /* SMAXV / UMAXV */ | |
ecb8ab8d RH |
7108 | if (is_u) { |
7109 | tcg_gen_umax_i64(tcg_res, tcg_res, tcg_elt); | |
7110 | } else { | |
7111 | tcg_gen_smax_i64(tcg_res, tcg_res, tcg_elt); | |
7112 | } | |
4a0ff1ce MM |
7113 | break; |
7114 | case 0x1a: /* SMINV / UMINV */ | |
ecb8ab8d RH |
7115 | if (is_u) { |
7116 | tcg_gen_umin_i64(tcg_res, tcg_res, tcg_elt); | |
7117 | } else { | |
7118 | tcg_gen_smin_i64(tcg_res, tcg_res, tcg_elt); | |
7119 | } | |
4a0ff1ce MM |
7120 | break; |
7121 | default: | |
7122 | g_assert_not_reached(); | |
7123 | } | |
7124 | ||
7125 | } | |
7126 | } else { | |
807cdd50 AB |
7127 | /* Floating point vector reduction ops which work across 32 |
7128 | * bit (single) or 16 bit (half-precision) intermediates. | |
4a0ff1ce MM |
7129 | * Note that correct NaN propagation requires that we do these |
7130 | * operations in exactly the order specified by the pseudocode. | |
7131 | */ | |
807cdd50 AB |
7132 | TCGv_ptr fpst = get_fpstatus_ptr(size == MO_16); |
7133 | int fpopcode = opcode | is_min << 4 | is_u << 5; | |
7134 | int vmap = (1 << elements) - 1; | |
7135 | TCGv_i32 tcg_res32 = do_reduction_op(s, fpopcode, rn, esize, | |
7136 | (is_q ? 128 : 64), vmap, fpst); | |
7137 | tcg_gen_extu_i32_i64(tcg_res, tcg_res32); | |
7138 | tcg_temp_free_i32(tcg_res32); | |
4a0ff1ce MM |
7139 | tcg_temp_free_ptr(fpst); |
7140 | } | |
7141 | ||
7142 | tcg_temp_free_i64(tcg_elt); | |
7143 | ||
7144 | /* Now truncate the result to the width required for the final output */ | |
7145 | if (opcode == 0x03) { | |
7146 | /* SADDLV, UADDLV: result is 2*esize */ | |
7147 | size++; | |
7148 | } | |
7149 | ||
7150 | switch (size) { | |
7151 | case 0: | |
7152 | tcg_gen_ext8u_i64(tcg_res, tcg_res); | |
7153 | break; | |
7154 | case 1: | |
7155 | tcg_gen_ext16u_i64(tcg_res, tcg_res); | |
7156 | break; | |
7157 | case 2: | |
7158 | tcg_gen_ext32u_i64(tcg_res, tcg_res); | |
7159 | break; | |
7160 | case 3: | |
7161 | break; | |
7162 | default: | |
7163 | g_assert_not_reached(); | |
7164 | } | |
7165 | ||
7166 | write_fp_dreg(s, rd, tcg_res); | |
7167 | tcg_temp_free_i64(tcg_res); | |
384b26fb AB |
7168 | } |
7169 | ||
4ce31af4 | 7170 | /* DUP (Element, Vector) |
67bb9389 AB |
7171 | * |
7172 | * 31 30 29 21 20 16 15 10 9 5 4 0 | |
7173 | * +---+---+-------------------+--------+-------------+------+------+ | |
7174 | * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd | | |
7175 | * +---+---+-------------------+--------+-------------+------+------+ | |
7176 | * | |
7177 | * size: encoded in imm5 (see ARM ARM LowestSetBit()) | |
7178 | */ | |
7179 | static void handle_simd_dupe(DisasContext *s, int is_q, int rd, int rn, | |
7180 | int imm5) | |
7181 | { | |
7182 | int size = ctz32(imm5); | |
861a1ded | 7183 | int index = imm5 >> (size + 1); |
67bb9389 AB |
7184 | |
7185 | if (size > 3 || (size == 3 && !is_q)) { | |
7186 | unallocated_encoding(s); | |
7187 | return; | |
7188 | } | |
7189 | ||
8c6afa6a PM |
7190 | if (!fp_access_check(s)) { |
7191 | return; | |
7192 | } | |
7193 | ||
861a1ded RH |
7194 | tcg_gen_gvec_dup_mem(size, vec_full_reg_offset(s, rd), |
7195 | vec_reg_offset(s, rn, index, size), | |
7196 | is_q ? 16 : 8, vec_full_reg_size(s)); | |
67bb9389 AB |
7197 | } |
7198 | ||
4ce31af4 | 7199 | /* DUP (element, scalar) |
360a6f2d PM |
7200 | * 31 21 20 16 15 10 9 5 4 0 |
7201 | * +-----------------------+--------+-------------+------+------+ | |
7202 | * | 0 1 0 1 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd | | |
7203 | * +-----------------------+--------+-------------+------+------+ | |
7204 | */ | |
7205 | static void handle_simd_dupes(DisasContext *s, int rd, int rn, | |
7206 | int imm5) | |
7207 | { | |
7208 | int size = ctz32(imm5); | |
7209 | int index; | |
7210 | TCGv_i64 tmp; | |
7211 | ||
7212 | if (size > 3) { | |
7213 | unallocated_encoding(s); | |
7214 | return; | |
7215 | } | |
7216 | ||
8c6afa6a PM |
7217 | if (!fp_access_check(s)) { |
7218 | return; | |
7219 | } | |
7220 | ||
360a6f2d PM |
7221 | index = imm5 >> (size + 1); |
7222 | ||
7223 | /* This instruction just extracts the specified element and | |
7224 | * zero-extends it into the bottom of the destination register. | |
7225 | */ | |
7226 | tmp = tcg_temp_new_i64(); | |
7227 | read_vec_element(s, tmp, rn, index, size); | |
7228 | write_fp_dreg(s, rd, tmp); | |
7229 | tcg_temp_free_i64(tmp); | |
7230 | } | |
7231 | ||
4ce31af4 | 7232 | /* DUP (General) |
67bb9389 AB |
7233 | * |
7234 | * 31 30 29 21 20 16 15 10 9 5 4 0 | |
7235 | * +---+---+-------------------+--------+-------------+------+------+ | |
7236 | * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 1 1 | Rn | Rd | | |
7237 | * +---+---+-------------------+--------+-------------+------+------+ | |
7238 | * | |
7239 | * size: encoded in imm5 (see ARM ARM LowestSetBit()) | |
7240 | */ | |
7241 | static void handle_simd_dupg(DisasContext *s, int is_q, int rd, int rn, | |
7242 | int imm5) | |
7243 | { | |
7244 | int size = ctz32(imm5); | |
861a1ded | 7245 | uint32_t dofs, oprsz, maxsz; |
67bb9389 AB |
7246 | |
7247 | if (size > 3 || ((size == 3) && !is_q)) { | |
7248 | unallocated_encoding(s); | |
7249 | return; | |
7250 | } | |
8c6afa6a PM |
7251 | |
7252 | if (!fp_access_check(s)) { | |
7253 | return; | |
7254 | } | |
7255 | ||
861a1ded RH |
7256 | dofs = vec_full_reg_offset(s, rd); |
7257 | oprsz = is_q ? 16 : 8; | |
7258 | maxsz = vec_full_reg_size(s); | |
7259 | ||
7260 | tcg_gen_gvec_dup_i64(size, dofs, oprsz, maxsz, cpu_reg(s, rn)); | |
67bb9389 AB |
7261 | } |
7262 | ||
4ce31af4 | 7263 | /* INS (Element) |
67bb9389 AB |
7264 | * |
7265 | * 31 21 20 16 15 14 11 10 9 5 4 0 | |
7266 | * +-----------------------+--------+------------+---+------+------+ | |
7267 | * | 0 1 1 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd | | |
7268 | * +-----------------------+--------+------------+---+------+------+ | |
7269 | * | |
7270 | * size: encoded in imm5 (see ARM ARM LowestSetBit()) | |
7271 | * index: encoded in imm5<4:size+1> | |
7272 | */ | |
7273 | static void handle_simd_inse(DisasContext *s, int rd, int rn, | |
7274 | int imm4, int imm5) | |
7275 | { | |
7276 | int size = ctz32(imm5); | |
7277 | int src_index, dst_index; | |
7278 | TCGv_i64 tmp; | |
7279 | ||
7280 | if (size > 3) { | |
7281 | unallocated_encoding(s); | |
7282 | return; | |
7283 | } | |
8c6afa6a PM |
7284 | |
7285 | if (!fp_access_check(s)) { | |
7286 | return; | |
7287 | } | |
7288 | ||
67bb9389 AB |
7289 | dst_index = extract32(imm5, 1+size, 5); |
7290 | src_index = extract32(imm4, size, 4); | |
7291 | ||
7292 | tmp = tcg_temp_new_i64(); | |
7293 | ||
7294 | read_vec_element(s, tmp, rn, src_index, size); | |
7295 | write_vec_element(s, tmp, rd, dst_index, size); | |
7296 | ||
7297 | tcg_temp_free_i64(tmp); | |
7298 | } | |
7299 | ||
7300 | ||
4ce31af4 | 7301 | /* INS (General) |
67bb9389 AB |
7302 | * |
7303 | * 31 21 20 16 15 10 9 5 4 0 | |
7304 | * +-----------------------+--------+-------------+------+------+ | |
7305 | * | 0 1 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 1 1 1 | Rn | Rd | | |
7306 | * +-----------------------+--------+-------------+------+------+ | |
7307 | * | |
7308 | * size: encoded in imm5 (see ARM ARM LowestSetBit()) | |
7309 | * index: encoded in imm5<4:size+1> | |
7310 | */ | |
7311 | static void handle_simd_insg(DisasContext *s, int rd, int rn, int imm5) | |
7312 | { | |
7313 | int size = ctz32(imm5); | |
7314 | int idx; | |
7315 | ||
7316 | if (size > 3) { | |
7317 | unallocated_encoding(s); | |
7318 | return; | |
7319 | } | |
7320 | ||
8c6afa6a PM |
7321 | if (!fp_access_check(s)) { |
7322 | return; | |
7323 | } | |
7324 | ||
67bb9389 AB |
7325 | idx = extract32(imm5, 1 + size, 4 - size); |
7326 | write_vec_element(s, cpu_reg(s, rn), rd, idx, size); | |
7327 | } | |
7328 | ||
7329 | /* | |
4ce31af4 PM |
7330 | * UMOV (General) |
7331 | * SMOV (General) | |
67bb9389 AB |
7332 | * |
7333 | * 31 30 29 21 20 16 15 12 10 9 5 4 0 | |
7334 | * +---+---+-------------------+--------+-------------+------+------+ | |
7335 | * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 1 U 1 1 | Rn | Rd | | |
7336 | * +---+---+-------------------+--------+-------------+------+------+ | |
7337 | * | |
7338 | * U: unsigned when set | |
7339 | * size: encoded in imm5 (see ARM ARM LowestSetBit()) | |
7340 | */ | |
7341 | static void handle_simd_umov_smov(DisasContext *s, int is_q, int is_signed, | |
7342 | int rn, int rd, int imm5) | |
7343 | { | |
7344 | int size = ctz32(imm5); | |
7345 | int element; | |
7346 | TCGv_i64 tcg_rd; | |
7347 | ||
7348 | /* Check for UnallocatedEncodings */ | |
7349 | if (is_signed) { | |
7350 | if (size > 2 || (size == 2 && !is_q)) { | |
7351 | unallocated_encoding(s); | |
7352 | return; | |
7353 | } | |
7354 | } else { | |
7355 | if (size > 3 | |
7356 | || (size < 3 && is_q) | |
7357 | || (size == 3 && !is_q)) { | |
7358 | unallocated_encoding(s); | |
7359 | return; | |
7360 | } | |
7361 | } | |
8c6afa6a PM |
7362 | |
7363 | if (!fp_access_check(s)) { | |
7364 | return; | |
7365 | } | |
7366 | ||
67bb9389 AB |
7367 | element = extract32(imm5, 1+size, 4); |
7368 | ||
7369 | tcg_rd = cpu_reg(s, rd); | |
7370 | read_vec_element(s, tcg_rd, rn, element, size | (is_signed ? MO_SIGN : 0)); | |
7371 | if (is_signed && !is_q) { | |
7372 | tcg_gen_ext32u_i64(tcg_rd, tcg_rd); | |
7373 | } | |
7374 | } | |
7375 | ||
4ce31af4 | 7376 | /* AdvSIMD copy |
384b26fb AB |
7377 | * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0 |
7378 | * +---+---+----+-----------------+------+---+------+---+------+------+ | |
7379 | * | 0 | Q | op | 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd | | |
7380 | * +---+---+----+-----------------+------+---+------+---+------+------+ | |
7381 | */ | |
7382 | static void disas_simd_copy(DisasContext *s, uint32_t insn) | |
7383 | { | |
67bb9389 AB |
7384 | int rd = extract32(insn, 0, 5); |
7385 | int rn = extract32(insn, 5, 5); | |
7386 | int imm4 = extract32(insn, 11, 4); | |
7387 | int op = extract32(insn, 29, 1); | |
7388 | int is_q = extract32(insn, 30, 1); | |
7389 | int imm5 = extract32(insn, 16, 5); | |
7390 | ||
7391 | if (op) { | |
7392 | if (is_q) { | |
7393 | /* INS (element) */ | |
7394 | handle_simd_inse(s, rd, rn, imm4, imm5); | |
7395 | } else { | |
7396 | unallocated_encoding(s); | |
7397 | } | |
7398 | } else { | |
7399 | switch (imm4) { | |
7400 | case 0: | |
7401 | /* DUP (element - vector) */ | |
7402 | handle_simd_dupe(s, is_q, rd, rn, imm5); | |
7403 | break; | |
7404 | case 1: | |
7405 | /* DUP (general) */ | |
7406 | handle_simd_dupg(s, is_q, rd, rn, imm5); | |
7407 | break; | |
7408 | case 3: | |
7409 | if (is_q) { | |
7410 | /* INS (general) */ | |
7411 | handle_simd_insg(s, rd, rn, imm5); | |
7412 | } else { | |
7413 | unallocated_encoding(s); | |
7414 | } | |
7415 | break; | |
7416 | case 5: | |
7417 | case 7: | |
7418 | /* UMOV/SMOV (is_q indicates 32/64; imm4 indicates signedness) */ | |
7419 | handle_simd_umov_smov(s, is_q, (imm4 == 5), rn, rd, imm5); | |
7420 | break; | |
7421 | default: | |
7422 | unallocated_encoding(s); | |
7423 | break; | |
7424 | } | |
7425 | } | |
384b26fb AB |
7426 | } |
7427 | ||
4ce31af4 | 7428 | /* AdvSIMD modified immediate |
384b26fb AB |
7429 | * 31 30 29 28 19 18 16 15 12 11 10 9 5 4 0 |
7430 | * +---+---+----+---------------------+-----+-------+----+---+-------+------+ | |
7431 | * | 0 | Q | op | 0 1 1 1 1 0 0 0 0 0 | abc | cmode | o2 | 1 | defgh | Rd | | |
7432 | * +---+---+----+---------------------+-----+-------+----+---+-------+------+ | |
f3f8c4f4 AB |
7433 | * |
7434 | * There are a number of operations that can be carried out here: | |
7435 | * MOVI - move (shifted) imm into register | |
7436 | * MVNI - move inverted (shifted) imm into register | |
7437 | * ORR - bitwise OR of (shifted) imm with register | |
7438 | * BIC - bitwise clear of (shifted) imm with register | |
70b4e6a4 AB |
7439 | * With ARMv8.2 we also have: |
7440 | * FMOV half-precision | |
384b26fb AB |
7441 | */ |
7442 | static void disas_simd_mod_imm(DisasContext *s, uint32_t insn) | |
7443 | { | |
f3f8c4f4 AB |
7444 | int rd = extract32(insn, 0, 5); |
7445 | int cmode = extract32(insn, 12, 4); | |
7446 | int cmode_3_1 = extract32(cmode, 1, 3); | |
7447 | int cmode_0 = extract32(cmode, 0, 1); | |
7448 | int o2 = extract32(insn, 11, 1); | |
7449 | uint64_t abcdefgh = extract32(insn, 5, 5) | (extract32(insn, 16, 3) << 5); | |
7450 | bool is_neg = extract32(insn, 29, 1); | |
7451 | bool is_q = extract32(insn, 30, 1); | |
7452 | uint64_t imm = 0; | |
f3f8c4f4 AB |
7453 | |
7454 | if (o2 != 0 || ((cmode == 0xf) && is_neg && !is_q)) { | |
70b4e6a4 | 7455 | /* Check for FMOV (vector, immediate) - half-precision */ |
5763190f | 7456 | if (!(dc_isar_feature(aa64_fp16, s) && o2 && cmode == 0xf)) { |
70b4e6a4 AB |
7457 | unallocated_encoding(s); |
7458 | return; | |
7459 | } | |
f3f8c4f4 AB |
7460 | } |
7461 | ||
8c6afa6a PM |
7462 | if (!fp_access_check(s)) { |
7463 | return; | |
7464 | } | |
7465 | ||
f3f8c4f4 AB |
7466 | /* See AdvSIMDExpandImm() in ARM ARM */ |
7467 | switch (cmode_3_1) { | |
7468 | case 0: /* Replicate(Zeros(24):imm8, 2) */ | |
7469 | case 1: /* Replicate(Zeros(16):imm8:Zeros(8), 2) */ | |
7470 | case 2: /* Replicate(Zeros(8):imm8:Zeros(16), 2) */ | |
7471 | case 3: /* Replicate(imm8:Zeros(24), 2) */ | |
7472 | { | |
7473 | int shift = cmode_3_1 * 8; | |
7474 | imm = bitfield_replicate(abcdefgh << shift, 32); | |
7475 | break; | |
7476 | } | |
7477 | case 4: /* Replicate(Zeros(8):imm8, 4) */ | |
7478 | case 5: /* Replicate(imm8:Zeros(8), 4) */ | |
7479 | { | |
7480 | int shift = (cmode_3_1 & 0x1) * 8; | |
7481 | imm = bitfield_replicate(abcdefgh << shift, 16); | |
7482 | break; | |
7483 | } | |
7484 | case 6: | |
7485 | if (cmode_0) { | |
7486 | /* Replicate(Zeros(8):imm8:Ones(16), 2) */ | |
7487 | imm = (abcdefgh << 16) | 0xffff; | |
7488 | } else { | |
7489 | /* Replicate(Zeros(16):imm8:Ones(8), 2) */ | |
7490 | imm = (abcdefgh << 8) | 0xff; | |
7491 | } | |
7492 | imm = bitfield_replicate(imm, 32); | |
7493 | break; | |
7494 | case 7: | |
7495 | if (!cmode_0 && !is_neg) { | |
7496 | imm = bitfield_replicate(abcdefgh, 8); | |
7497 | } else if (!cmode_0 && is_neg) { | |
7498 | int i; | |
7499 | imm = 0; | |
7500 | for (i = 0; i < 8; i++) { | |
7501 | if ((abcdefgh) & (1 << i)) { | |
7502 | imm |= 0xffULL << (i * 8); | |
7503 | } | |
7504 | } | |
7505 | } else if (cmode_0) { | |
7506 | if (is_neg) { | |
7507 | imm = (abcdefgh & 0x3f) << 48; | |
7508 | if (abcdefgh & 0x80) { | |
7509 | imm |= 0x8000000000000000ULL; | |
7510 | } | |
7511 | if (abcdefgh & 0x40) { | |
7512 | imm |= 0x3fc0000000000000ULL; | |
7513 | } else { | |
7514 | imm |= 0x4000000000000000ULL; | |
7515 | } | |
7516 | } else { | |
70b4e6a4 AB |
7517 | if (o2) { |
7518 | /* FMOV (vector, immediate) - half-precision */ | |
7519 | imm = vfp_expand_imm(MO_16, abcdefgh); | |
7520 | /* now duplicate across the lanes */ | |
7521 | imm = bitfield_replicate(imm, 16); | |
f3f8c4f4 | 7522 | } else { |
70b4e6a4 AB |
7523 | imm = (abcdefgh & 0x3f) << 19; |
7524 | if (abcdefgh & 0x80) { | |
7525 | imm |= 0x80000000; | |
7526 | } | |
7527 | if (abcdefgh & 0x40) { | |
7528 | imm |= 0x3e000000; | |
7529 | } else { | |
7530 | imm |= 0x40000000; | |
7531 | } | |
7532 | imm |= (imm << 32); | |
f3f8c4f4 | 7533 | } |
f3f8c4f4 AB |
7534 | } |
7535 | } | |
7536 | break; | |
70b4e6a4 AB |
7537 | default: |
7538 | fprintf(stderr, "%s: cmode_3_1: %x\n", __func__, cmode_3_1); | |
7539 | g_assert_not_reached(); | |
f3f8c4f4 AB |
7540 | } |
7541 | ||
7542 | if (cmode_3_1 != 7 && is_neg) { | |
7543 | imm = ~imm; | |
7544 | } | |
7545 | ||
861a1ded RH |
7546 | if (!((cmode & 0x9) == 0x1 || (cmode & 0xd) == 0x9)) { |
7547 | /* MOVI or MVNI, with MVNI negation handled above. */ | |
7548 | tcg_gen_gvec_dup64i(vec_full_reg_offset(s, rd), is_q ? 16 : 8, | |
7549 | vec_full_reg_size(s), imm); | |
7550 | } else { | |
064e265d RH |
7551 | /* ORR or BIC, with BIC negation to AND handled above. */ |
7552 | if (is_neg) { | |
7553 | gen_gvec_fn2i(s, is_q, rd, rd, imm, tcg_gen_gvec_andi, MO_64); | |
7554 | } else { | |
7555 | gen_gvec_fn2i(s, is_q, rd, rd, imm, tcg_gen_gvec_ori, MO_64); | |
f3f8c4f4 | 7556 | } |
861a1ded | 7557 | } |
384b26fb AB |
7558 | } |
7559 | ||
4ce31af4 | 7560 | /* AdvSIMD scalar copy |
384b26fb AB |
7561 | * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0 |
7562 | * +-----+----+-----------------+------+---+------+---+------+------+ | |
7563 | * | 0 1 | op | 1 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd | | |
7564 | * +-----+----+-----------------+------+---+------+---+------+------+ | |
7565 | */ | |
7566 | static void disas_simd_scalar_copy(DisasContext *s, uint32_t insn) | |
7567 | { | |
360a6f2d PM |
7568 | int rd = extract32(insn, 0, 5); |
7569 | int rn = extract32(insn, 5, 5); | |
7570 | int imm4 = extract32(insn, 11, 4); | |
7571 | int imm5 = extract32(insn, 16, 5); | |
7572 | int op = extract32(insn, 29, 1); | |
7573 | ||
7574 | if (op != 0 || imm4 != 0) { | |
7575 | unallocated_encoding(s); | |
7576 | return; | |
7577 | } | |
7578 | ||
7579 | /* DUP (element, scalar) */ | |
7580 | handle_simd_dupes(s, rd, rn, imm5); | |
384b26fb AB |
7581 | } |
7582 | ||
4ce31af4 | 7583 | /* AdvSIMD scalar pairwise |
384b26fb AB |
7584 | * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0 |
7585 | * +-----+---+-----------+------+-----------+--------+-----+------+------+ | |
7586 | * | 0 1 | U | 1 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd | | |
7587 | * +-----+---+-----------+------+-----------+--------+-----+------+------+ | |
7588 | */ | |
7589 | static void disas_simd_scalar_pairwise(DisasContext *s, uint32_t insn) | |
7590 | { | |
3720a7ea PM |
7591 | int u = extract32(insn, 29, 1); |
7592 | int size = extract32(insn, 22, 2); | |
7593 | int opcode = extract32(insn, 12, 5); | |
7594 | int rn = extract32(insn, 5, 5); | |
7595 | int rd = extract32(insn, 0, 5); | |
7596 | TCGv_ptr fpst; | |
7597 | ||
7598 | /* For some ops (the FP ones), size[1] is part of the encoding. | |
7599 | * For ADDP strictly it is not but size[1] is always 1 for valid | |
7600 | * encodings. | |
7601 | */ | |
7602 | opcode |= (extract32(size, 1, 1) << 5); | |
7603 | ||
7604 | switch (opcode) { | |
7605 | case 0x3b: /* ADDP */ | |
7606 | if (u || size != 3) { | |
7607 | unallocated_encoding(s); | |
7608 | return; | |
7609 | } | |
8c6afa6a PM |
7610 | if (!fp_access_check(s)) { |
7611 | return; | |
7612 | } | |
7613 | ||
f764718d | 7614 | fpst = NULL; |
3720a7ea PM |
7615 | break; |
7616 | case 0xc: /* FMAXNMP */ | |
7617 | case 0xd: /* FADDP */ | |
7618 | case 0xf: /* FMAXP */ | |
7619 | case 0x2c: /* FMINNMP */ | |
7620 | case 0x2f: /* FMINP */ | |
5c36d895 | 7621 | /* FP op, size[0] is 32 or 64 bit*/ |
3720a7ea | 7622 | if (!u) { |
5763190f | 7623 | if (!dc_isar_feature(aa64_fp16, s)) { |
5c36d895 AB |
7624 | unallocated_encoding(s); |
7625 | return; | |
7626 | } else { | |
7627 | size = MO_16; | |
7628 | } | |
7629 | } else { | |
7630 | size = extract32(size, 0, 1) ? MO_64 : MO_32; | |
3720a7ea | 7631 | } |
5c36d895 | 7632 | |
8c6afa6a PM |
7633 | if (!fp_access_check(s)) { |
7634 | return; | |
7635 | } | |
7636 | ||
5c36d895 | 7637 | fpst = get_fpstatus_ptr(size == MO_16); |
3720a7ea PM |
7638 | break; |
7639 | default: | |
7640 | unallocated_encoding(s); | |
7641 | return; | |
7642 | } | |
7643 | ||
5c36d895 | 7644 | if (size == MO_64) { |
3720a7ea PM |
7645 | TCGv_i64 tcg_op1 = tcg_temp_new_i64(); |
7646 | TCGv_i64 tcg_op2 = tcg_temp_new_i64(); | |
7647 | TCGv_i64 tcg_res = tcg_temp_new_i64(); | |
7648 | ||
7649 | read_vec_element(s, tcg_op1, rn, 0, MO_64); | |
7650 | read_vec_element(s, tcg_op2, rn, 1, MO_64); | |
7651 | ||
7652 | switch (opcode) { | |
7653 | case 0x3b: /* ADDP */ | |
7654 | tcg_gen_add_i64(tcg_res, tcg_op1, tcg_op2); | |
7655 | break; | |
7656 | case 0xc: /* FMAXNMP */ | |
7657 | gen_helper_vfp_maxnumd(tcg_res, tcg_op1, tcg_op2, fpst); | |
7658 | break; | |
7659 | case 0xd: /* FADDP */ | |
7660 | gen_helper_vfp_addd(tcg_res, tcg_op1, tcg_op2, fpst); | |
7661 | break; | |
7662 | case 0xf: /* FMAXP */ | |
7663 | gen_helper_vfp_maxd(tcg_res, tcg_op1, tcg_op2, fpst); | |
7664 | break; | |
7665 | case 0x2c: /* FMINNMP */ | |
7666 | gen_helper_vfp_minnumd(tcg_res, tcg_op1, tcg_op2, fpst); | |
7667 | break; | |
7668 | case 0x2f: /* FMINP */ | |
7669 | gen_helper_vfp_mind(tcg_res, tcg_op1, tcg_op2, fpst); | |
7670 | break; | |
7671 | default: | |
7672 | g_assert_not_reached(); | |
7673 | } | |
7674 | ||
7675 | write_fp_dreg(s, rd, tcg_res); | |
7676 | ||
7677 | tcg_temp_free_i64(tcg_op1); | |
7678 | tcg_temp_free_i64(tcg_op2); | |
7679 | tcg_temp_free_i64(tcg_res); | |
7680 | } else { | |
7681 | TCGv_i32 tcg_op1 = tcg_temp_new_i32(); | |
7682 | TCGv_i32 tcg_op2 = tcg_temp_new_i32(); | |
7683 | TCGv_i32 tcg_res = tcg_temp_new_i32(); | |
7684 | ||
5c36d895 AB |
7685 | read_vec_element_i32(s, tcg_op1, rn, 0, size); |
7686 | read_vec_element_i32(s, tcg_op2, rn, 1, size); | |
3720a7ea | 7687 | |
5c36d895 AB |
7688 | if (size == MO_16) { |
7689 | switch (opcode) { | |
7690 | case 0xc: /* FMAXNMP */ | |
7691 | gen_helper_advsimd_maxnumh(tcg_res, tcg_op1, tcg_op2, fpst); | |
7692 | break; | |
7693 | case 0xd: /* FADDP */ | |
7694 | gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst); | |
7695 | break; | |
7696 | case 0xf: /* FMAXP */ | |
7697 | gen_helper_advsimd_maxh(tcg_res, tcg_op1, tcg_op2, fpst); | |
7698 | break; | |
7699 | case 0x2c: /* FMINNMP */ | |
7700 | gen_helper_advsimd_minnumh(tcg_res, tcg_op1, tcg_op2, fpst); | |
7701 | break; | |
7702 | case 0x2f: /* FMINP */ | |
7703 | gen_helper_advsimd_minh(tcg_res, tcg_op1, tcg_op2, fpst); | |
7704 | break; | |
7705 | default: | |
7706 | g_assert_not_reached(); | |
7707 | } | |
7708 | } else { | |
7709 | switch (opcode) { | |
7710 | case 0xc: /* FMAXNMP */ | |
7711 | gen_helper_vfp_maxnums(tcg_res, tcg_op1, tcg_op2, fpst); | |
7712 | break; | |
7713 | case 0xd: /* FADDP */ | |
7714 | gen_helper_vfp_adds(tcg_res, tcg_op1, tcg_op2, fpst); | |
7715 | break; | |
7716 | case 0xf: /* FMAXP */ | |
7717 | gen_helper_vfp_maxs(tcg_res, tcg_op1, tcg_op2, fpst); | |
7718 | break; | |
7719 | case 0x2c: /* FMINNMP */ | |
7720 | gen_helper_vfp_minnums(tcg_res, tcg_op1, tcg_op2, fpst); | |
7721 | break; | |
7722 | case 0x2f: /* FMINP */ | |
7723 | gen_helper_vfp_mins(tcg_res, tcg_op1, tcg_op2, fpst); | |
7724 | break; | |
7725 | default: | |
7726 | g_assert_not_reached(); | |
7727 | } | |
3720a7ea PM |
7728 | } |
7729 | ||
7730 | write_fp_sreg(s, rd, tcg_res); | |
7731 | ||
7732 | tcg_temp_free_i32(tcg_op1); | |
7733 | tcg_temp_free_i32(tcg_op2); | |
7734 | tcg_temp_free_i32(tcg_res); | |
7735 | } | |
7736 | ||
f764718d | 7737 | if (fpst) { |
3720a7ea PM |
7738 | tcg_temp_free_ptr(fpst); |
7739 | } | |
384b26fb AB |
7740 | } |
7741 | ||
4d1cef84 AB |
7742 | /* |
7743 | * Common SSHR[RA]/USHR[RA] - Shift right (optional rounding/accumulate) | |
7744 | * | |
7745 | * This code is handles the common shifting code and is used by both | |
7746 | * the vector and scalar code. | |
7747 | */ | |
7748 | static void handle_shri_with_rndacc(TCGv_i64 tcg_res, TCGv_i64 tcg_src, | |
7749 | TCGv_i64 tcg_rnd, bool accumulate, | |
7750 | bool is_u, int size, int shift) | |
7751 | { | |
7752 | bool extended_result = false; | |
f764718d | 7753 | bool round = tcg_rnd != NULL; |
4d1cef84 AB |
7754 | int ext_lshift = 0; |
7755 | TCGv_i64 tcg_src_hi; | |
7756 | ||
7757 | if (round && size == 3) { | |
7758 | extended_result = true; | |
7759 | ext_lshift = 64 - shift; | |
7760 | tcg_src_hi = tcg_temp_new_i64(); | |
7761 | } else if (shift == 64) { | |
7762 | if (!accumulate && is_u) { | |
7763 | /* result is zero */ | |
7764 | tcg_gen_movi_i64(tcg_res, 0); | |
7765 | return; | |
7766 | } | |
7767 | } | |
7768 | ||
7769 | /* Deal with the rounding step */ | |
7770 | if (round) { | |
7771 | if (extended_result) { | |
7772 | TCGv_i64 tcg_zero = tcg_const_i64(0); | |
7773 | if (!is_u) { | |
7774 | /* take care of sign extending tcg_res */ | |
7775 | tcg_gen_sari_i64(tcg_src_hi, tcg_src, 63); | |
7776 | tcg_gen_add2_i64(tcg_src, tcg_src_hi, | |
7777 | tcg_src, tcg_src_hi, | |
7778 | tcg_rnd, tcg_zero); | |
7779 | } else { | |
7780 | tcg_gen_add2_i64(tcg_src, tcg_src_hi, | |
7781 | tcg_src, tcg_zero, | |
7782 | tcg_rnd, tcg_zero); | |
7783 | } | |
7784 | tcg_temp_free_i64(tcg_zero); | |
7785 | } else { | |
7786 | tcg_gen_add_i64(tcg_src, tcg_src, tcg_rnd); | |
7787 | } | |
7788 | } | |
7789 | ||
7790 | /* Now do the shift right */ | |
7791 | if (round && extended_result) { | |
7792 | /* extended case, >64 bit precision required */ | |
7793 | if (ext_lshift == 0) { | |
7794 | /* special case, only high bits matter */ | |
7795 | tcg_gen_mov_i64(tcg_src, tcg_src_hi); | |
7796 | } else { | |
7797 | tcg_gen_shri_i64(tcg_src, tcg_src, shift); | |
7798 | tcg_gen_shli_i64(tcg_src_hi, tcg_src_hi, ext_lshift); | |
7799 | tcg_gen_or_i64(tcg_src, tcg_src, tcg_src_hi); | |
7800 | } | |
7801 | } else { | |
7802 | if (is_u) { | |
7803 | if (shift == 64) { | |
7804 | /* essentially shifting in 64 zeros */ | |
7805 | tcg_gen_movi_i64(tcg_src, 0); | |
7806 | } else { | |
7807 | tcg_gen_shri_i64(tcg_src, tcg_src, shift); | |
7808 | } | |
7809 | } else { | |
7810 | if (shift == 64) { | |
7811 | /* effectively extending the sign-bit */ | |
7812 | tcg_gen_sari_i64(tcg_src, tcg_src, 63); | |
7813 | } else { | |
7814 | tcg_gen_sari_i64(tcg_src, tcg_src, shift); | |
7815 | } | |
7816 | } | |
7817 | } | |
7818 | ||
7819 | if (accumulate) { | |
7820 | tcg_gen_add_i64(tcg_res, tcg_res, tcg_src); | |
7821 | } else { | |
7822 | tcg_gen_mov_i64(tcg_res, tcg_src); | |
7823 | } | |
7824 | ||
7825 | if (extended_result) { | |
7826 | tcg_temp_free_i64(tcg_src_hi); | |
7827 | } | |
7828 | } | |
7829 | ||
4d1cef84 AB |
7830 | /* SSHR[RA]/USHR[RA] - Scalar shift right (optional rounding/accumulate) */ |
7831 | static void handle_scalar_simd_shri(DisasContext *s, | |
7832 | bool is_u, int immh, int immb, | |
7833 | int opcode, int rn, int rd) | |
7834 | { | |
7835 | const int size = 3; | |
7836 | int immhb = immh << 3 | immb; | |
7837 | int shift = 2 * (8 << size) - immhb; | |
7838 | bool accumulate = false; | |
7839 | bool round = false; | |
37a706ad | 7840 | bool insert = false; |
4d1cef84 AB |
7841 | TCGv_i64 tcg_rn; |
7842 | TCGv_i64 tcg_rd; | |
7843 | TCGv_i64 tcg_round; | |
7844 | ||
7845 | if (!extract32(immh, 3, 1)) { | |
7846 | unallocated_encoding(s); | |
7847 | return; | |
7848 | } | |
7849 | ||
8c6afa6a PM |
7850 | if (!fp_access_check(s)) { |
7851 | return; | |
7852 | } | |
7853 | ||
4d1cef84 AB |
7854 | switch (opcode) { |
7855 | case 0x02: /* SSRA / USRA (accumulate) */ | |
7856 | accumulate = true; | |
7857 | break; | |
7858 | case 0x04: /* SRSHR / URSHR (rounding) */ | |
7859 | round = true; | |
7860 | break; | |
7861 | case 0x06: /* SRSRA / URSRA (accum + rounding) */ | |
7862 | accumulate = round = true; | |
7863 | break; | |
37a706ad PM |
7864 | case 0x08: /* SRI */ |
7865 | insert = true; | |
7866 | break; | |
4d1cef84 AB |
7867 | } |
7868 | ||
7869 | if (round) { | |
7870 | uint64_t round_const = 1ULL << (shift - 1); | |
7871 | tcg_round = tcg_const_i64(round_const); | |
7872 | } else { | |
f764718d | 7873 | tcg_round = NULL; |
4d1cef84 AB |
7874 | } |
7875 | ||
7876 | tcg_rn = read_fp_dreg(s, rn); | |
37a706ad | 7877 | tcg_rd = (accumulate || insert) ? read_fp_dreg(s, rd) : tcg_temp_new_i64(); |
4d1cef84 | 7878 | |
37a706ad | 7879 | if (insert) { |
cdb45a60 RH |
7880 | /* shift count same as element size is valid but does nothing; |
7881 | * special case to avoid potential shift by 64. | |
7882 | */ | |
7883 | int esize = 8 << size; | |
7884 | if (shift != esize) { | |
7885 | tcg_gen_shri_i64(tcg_rn, tcg_rn, shift); | |
7886 | tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_rn, 0, esize - shift); | |
7887 | } | |
37a706ad PM |
7888 | } else { |
7889 | handle_shri_with_rndacc(tcg_rd, tcg_rn, tcg_round, | |
7890 | accumulate, is_u, size, shift); | |
7891 | } | |
4d1cef84 AB |
7892 | |
7893 | write_fp_dreg(s, rd, tcg_rd); | |
7894 | ||
7895 | tcg_temp_free_i64(tcg_rn); | |
7896 | tcg_temp_free_i64(tcg_rd); | |
7897 | if (round) { | |
7898 | tcg_temp_free_i64(tcg_round); | |
7899 | } | |
7900 | } | |
7901 | ||
7902 | /* SHL/SLI - Scalar shift left */ | |
7903 | static void handle_scalar_simd_shli(DisasContext *s, bool insert, | |
7904 | int immh, int immb, int opcode, | |
7905 | int rn, int rd) | |
7906 | { | |
7907 | int size = 32 - clz32(immh) - 1; | |
7908 | int immhb = immh << 3 | immb; | |
7909 | int shift = immhb - (8 << size); | |
7910 | TCGv_i64 tcg_rn = new_tmp_a64(s); | |
7911 | TCGv_i64 tcg_rd = new_tmp_a64(s); | |
7912 | ||
7913 | if (!extract32(immh, 3, 1)) { | |
7914 | unallocated_encoding(s); | |
7915 | return; | |
7916 | } | |
7917 | ||
8c6afa6a PM |
7918 | if (!fp_access_check(s)) { |
7919 | return; | |
7920 | } | |
7921 | ||
4d1cef84 AB |
7922 | tcg_rn = read_fp_dreg(s, rn); |
7923 | tcg_rd = insert ? read_fp_dreg(s, rd) : tcg_temp_new_i64(); | |
7924 | ||
cdb45a60 RH |
7925 | if (insert) { |
7926 | tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_rn, shift, 64 - shift); | |
7927 | } else { | |
7928 | tcg_gen_shli_i64(tcg_rd, tcg_rn, shift); | |
7929 | } | |
4d1cef84 AB |
7930 | |
7931 | write_fp_dreg(s, rd, tcg_rd); | |
7932 | ||
7933 | tcg_temp_free_i64(tcg_rn); | |
7934 | tcg_temp_free_i64(tcg_rd); | |
7935 | } | |
7936 | ||
c1b876b2 AB |
7937 | /* SQSHRN/SQSHRUN - Saturating (signed/unsigned) shift right with |
7938 | * (signed/unsigned) narrowing */ | |
7939 | static void handle_vec_simd_sqshrn(DisasContext *s, bool is_scalar, bool is_q, | |
7940 | bool is_u_shift, bool is_u_narrow, | |
7941 | int immh, int immb, int opcode, | |
7942 | int rn, int rd) | |
7943 | { | |
7944 | int immhb = immh << 3 | immb; | |
7945 | int size = 32 - clz32(immh) - 1; | |
7946 | int esize = 8 << size; | |
7947 | int shift = (2 * esize) - immhb; | |
7948 | int elements = is_scalar ? 1 : (64 / esize); | |
7949 | bool round = extract32(opcode, 0, 1); | |
7950 | TCGMemOp ldop = (size + 1) | (is_u_shift ? 0 : MO_SIGN); | |
7951 | TCGv_i64 tcg_rn, tcg_rd, tcg_round; | |
7952 | TCGv_i32 tcg_rd_narrowed; | |
7953 | TCGv_i64 tcg_final; | |
7954 | ||
7955 | static NeonGenNarrowEnvFn * const signed_narrow_fns[4][2] = { | |
7956 | { gen_helper_neon_narrow_sat_s8, | |
7957 | gen_helper_neon_unarrow_sat8 }, | |
7958 | { gen_helper_neon_narrow_sat_s16, | |
7959 | gen_helper_neon_unarrow_sat16 }, | |
7960 | { gen_helper_neon_narrow_sat_s32, | |
7961 | gen_helper_neon_unarrow_sat32 }, | |
7962 | { NULL, NULL }, | |
7963 | }; | |
7964 | static NeonGenNarrowEnvFn * const unsigned_narrow_fns[4] = { | |
7965 | gen_helper_neon_narrow_sat_u8, | |
7966 | gen_helper_neon_narrow_sat_u16, | |
7967 | gen_helper_neon_narrow_sat_u32, | |
7968 | NULL | |
7969 | }; | |
7970 | NeonGenNarrowEnvFn *narrowfn; | |
7971 | ||
7972 | int i; | |
7973 | ||
7974 | assert(size < 4); | |
7975 | ||
7976 | if (extract32(immh, 3, 1)) { | |
7977 | unallocated_encoding(s); | |
7978 | return; | |
7979 | } | |
7980 | ||
8c6afa6a PM |
7981 | if (!fp_access_check(s)) { |
7982 | return; | |
7983 | } | |
7984 | ||
c1b876b2 AB |
7985 | if (is_u_shift) { |
7986 | narrowfn = unsigned_narrow_fns[size]; | |
7987 | } else { | |
7988 | narrowfn = signed_narrow_fns[size][is_u_narrow ? 1 : 0]; | |
7989 | } | |
7990 | ||
7991 | tcg_rn = tcg_temp_new_i64(); | |
7992 | tcg_rd = tcg_temp_new_i64(); | |
7993 | tcg_rd_narrowed = tcg_temp_new_i32(); | |
7994 | tcg_final = tcg_const_i64(0); | |
7995 | ||
7996 | if (round) { | |
7997 | uint64_t round_const = 1ULL << (shift - 1); | |
7998 | tcg_round = tcg_const_i64(round_const); | |
7999 | } else { | |
f764718d | 8000 | tcg_round = NULL; |
c1b876b2 AB |
8001 | } |
8002 | ||
8003 | for (i = 0; i < elements; i++) { | |
8004 | read_vec_element(s, tcg_rn, rn, i, ldop); | |
8005 | handle_shri_with_rndacc(tcg_rd, tcg_rn, tcg_round, | |
8006 | false, is_u_shift, size+1, shift); | |
8007 | narrowfn(tcg_rd_narrowed, cpu_env, tcg_rd); | |
8008 | tcg_gen_extu_i32_i64(tcg_rd, tcg_rd_narrowed); | |
8009 | tcg_gen_deposit_i64(tcg_final, tcg_final, tcg_rd, esize * i, esize); | |
8010 | } | |
8011 | ||
8012 | if (!is_q) { | |
c1b876b2 AB |
8013 | write_vec_element(s, tcg_final, rd, 0, MO_64); |
8014 | } else { | |
8015 | write_vec_element(s, tcg_final, rd, 1, MO_64); | |
8016 | } | |
8017 | ||
8018 | if (round) { | |
8019 | tcg_temp_free_i64(tcg_round); | |
8020 | } | |
8021 | tcg_temp_free_i64(tcg_rn); | |
8022 | tcg_temp_free_i64(tcg_rd); | |
8023 | tcg_temp_free_i32(tcg_rd_narrowed); | |
8024 | tcg_temp_free_i64(tcg_final); | |
4ff55bcb RH |
8025 | |
8026 | clear_vec_high(s, is_q, rd); | |
c1b876b2 AB |
8027 | } |
8028 | ||
a847f32c PM |
8029 | /* SQSHLU, UQSHL, SQSHL: saturating left shifts */ |
8030 | static void handle_simd_qshl(DisasContext *s, bool scalar, bool is_q, | |
8031 | bool src_unsigned, bool dst_unsigned, | |
8032 | int immh, int immb, int rn, int rd) | |
8033 | { | |
8034 | int immhb = immh << 3 | immb; | |
8035 | int size = 32 - clz32(immh) - 1; | |
8036 | int shift = immhb - (8 << size); | |
8037 | int pass; | |
8038 | ||
8039 | assert(immh != 0); | |
8040 | assert(!(scalar && is_q)); | |
8041 | ||
8042 | if (!scalar) { | |
8043 | if (!is_q && extract32(immh, 3, 1)) { | |
8044 | unallocated_encoding(s); | |
8045 | return; | |
8046 | } | |
8047 | ||
8048 | /* Since we use the variable-shift helpers we must | |
8049 | * replicate the shift count into each element of | |
8050 | * the tcg_shift value. | |
8051 | */ | |
8052 | switch (size) { | |
8053 | case 0: | |
8054 | shift |= shift << 8; | |
8055 | /* fall through */ | |
8056 | case 1: | |
8057 | shift |= shift << 16; | |
8058 | break; | |
8059 | case 2: | |
8060 | case 3: | |
8061 | break; | |
8062 | default: | |
8063 | g_assert_not_reached(); | |
8064 | } | |
8065 | } | |
8066 | ||
8c6afa6a PM |
8067 | if (!fp_access_check(s)) { |
8068 | return; | |
8069 | } | |
8070 | ||
a847f32c PM |
8071 | if (size == 3) { |
8072 | TCGv_i64 tcg_shift = tcg_const_i64(shift); | |
8073 | static NeonGenTwo64OpEnvFn * const fns[2][2] = { | |
8074 | { gen_helper_neon_qshl_s64, gen_helper_neon_qshlu_s64 }, | |
8075 | { NULL, gen_helper_neon_qshl_u64 }, | |
8076 | }; | |
8077 | NeonGenTwo64OpEnvFn *genfn = fns[src_unsigned][dst_unsigned]; | |
8078 | int maxpass = is_q ? 2 : 1; | |
8079 | ||
8080 | for (pass = 0; pass < maxpass; pass++) { | |
8081 | TCGv_i64 tcg_op = tcg_temp_new_i64(); | |
8082 | ||
8083 | read_vec_element(s, tcg_op, rn, pass, MO_64); | |
8084 | genfn(tcg_op, cpu_env, tcg_op, tcg_shift); | |
8085 | write_vec_element(s, tcg_op, rd, pass, MO_64); | |
8086 | ||
8087 | tcg_temp_free_i64(tcg_op); | |
8088 | } | |
8089 | tcg_temp_free_i64(tcg_shift); | |
4ff55bcb | 8090 | clear_vec_high(s, is_q, rd); |
a847f32c PM |
8091 | } else { |
8092 | TCGv_i32 tcg_shift = tcg_const_i32(shift); | |
8093 | static NeonGenTwoOpEnvFn * const fns[2][2][3] = { | |
8094 | { | |
8095 | { gen_helper_neon_qshl_s8, | |
8096 | gen_helper_neon_qshl_s16, | |
8097 | gen_helper_neon_qshl_s32 }, | |
8098 | { gen_helper_neon_qshlu_s8, | |
8099 | gen_helper_neon_qshlu_s16, | |
8100 | gen_helper_neon_qshlu_s32 } | |
8101 | }, { | |
8102 | { NULL, NULL, NULL }, | |
8103 | { gen_helper_neon_qshl_u8, | |
8104 | gen_helper_neon_qshl_u16, | |
8105 | gen_helper_neon_qshl_u32 } | |
8106 | } | |
8107 | }; | |
8108 | NeonGenTwoOpEnvFn *genfn = fns[src_unsigned][dst_unsigned][size]; | |
8109 | TCGMemOp memop = scalar ? size : MO_32; | |
8110 | int maxpass = scalar ? 1 : is_q ? 4 : 2; | |
8111 | ||
8112 | for (pass = 0; pass < maxpass; pass++) { | |
8113 | TCGv_i32 tcg_op = tcg_temp_new_i32(); | |
8114 | ||
8115 | read_vec_element_i32(s, tcg_op, rn, pass, memop); | |
8116 | genfn(tcg_op, cpu_env, tcg_op, tcg_shift); | |
8117 | if (scalar) { | |
8118 | switch (size) { | |
8119 | case 0: | |
8120 | tcg_gen_ext8u_i32(tcg_op, tcg_op); | |
8121 | break; | |
8122 | case 1: | |
8123 | tcg_gen_ext16u_i32(tcg_op, tcg_op); | |
8124 | break; | |
8125 | case 2: | |
8126 | break; | |
8127 | default: | |
8128 | g_assert_not_reached(); | |
8129 | } | |
8130 | write_fp_sreg(s, rd, tcg_op); | |
8131 | } else { | |
8132 | write_vec_element_i32(s, tcg_op, rd, pass, MO_32); | |
8133 | } | |
8134 | ||
8135 | tcg_temp_free_i32(tcg_op); | |
8136 | } | |
8137 | tcg_temp_free_i32(tcg_shift); | |
8138 | ||
4ff55bcb RH |
8139 | if (!scalar) { |
8140 | clear_vec_high(s, is_q, rd); | |
a847f32c PM |
8141 | } |
8142 | } | |
8143 | } | |
8144 | ||
10113b69 AB |
8145 | /* Common vector code for handling integer to FP conversion */ |
8146 | static void handle_simd_intfp_conv(DisasContext *s, int rd, int rn, | |
8147 | int elements, int is_signed, | |
8148 | int fracbits, int size) | |
8149 | { | |
93193190 AB |
8150 | TCGv_ptr tcg_fpst = get_fpstatus_ptr(size == MO_16); |
8151 | TCGv_i32 tcg_shift = NULL; | |
8152 | ||
10113b69 AB |
8153 | TCGMemOp mop = size | (is_signed ? MO_SIGN : 0); |
8154 | int pass; | |
8155 | ||
93193190 AB |
8156 | if (fracbits || size == MO_64) { |
8157 | tcg_shift = tcg_const_i32(fracbits); | |
8158 | } | |
8159 | ||
8160 | if (size == MO_64) { | |
8161 | TCGv_i64 tcg_int64 = tcg_temp_new_i64(); | |
8162 | TCGv_i64 tcg_double = tcg_temp_new_i64(); | |
8163 | ||
8164 | for (pass = 0; pass < elements; pass++) { | |
8165 | read_vec_element(s, tcg_int64, rn, pass, mop); | |
10113b69 | 8166 | |
10113b69 | 8167 | if (is_signed) { |
93193190 | 8168 | gen_helper_vfp_sqtod(tcg_double, tcg_int64, |
10113b69 AB |
8169 | tcg_shift, tcg_fpst); |
8170 | } else { | |
93193190 | 8171 | gen_helper_vfp_uqtod(tcg_double, tcg_int64, |
10113b69 AB |
8172 | tcg_shift, tcg_fpst); |
8173 | } | |
8174 | if (elements == 1) { | |
8175 | write_fp_dreg(s, rd, tcg_double); | |
8176 | } else { | |
8177 | write_vec_element(s, tcg_double, rd, pass, MO_64); | |
8178 | } | |
93193190 AB |
8179 | } |
8180 | ||
8181 | tcg_temp_free_i64(tcg_int64); | |
8182 | tcg_temp_free_i64(tcg_double); | |
8183 | ||
8184 | } else { | |
8185 | TCGv_i32 tcg_int32 = tcg_temp_new_i32(); | |
8186 | TCGv_i32 tcg_float = tcg_temp_new_i32(); | |
8187 | ||
8188 | for (pass = 0; pass < elements; pass++) { | |
8189 | read_vec_element_i32(s, tcg_int32, rn, pass, mop); | |
8190 | ||
8191 | switch (size) { | |
8192 | case MO_32: | |
8193 | if (fracbits) { | |
8194 | if (is_signed) { | |
8195 | gen_helper_vfp_sltos(tcg_float, tcg_int32, | |
8196 | tcg_shift, tcg_fpst); | |
8197 | } else { | |
8198 | gen_helper_vfp_ultos(tcg_float, tcg_int32, | |
8199 | tcg_shift, tcg_fpst); | |
8200 | } | |
8201 | } else { | |
8202 | if (is_signed) { | |
8203 | gen_helper_vfp_sitos(tcg_float, tcg_int32, tcg_fpst); | |
8204 | } else { | |
8205 | gen_helper_vfp_uitos(tcg_float, tcg_int32, tcg_fpst); | |
8206 | } | |
8207 | } | |
8208 | break; | |
8209 | case MO_16: | |
8210 | if (fracbits) { | |
8211 | if (is_signed) { | |
8212 | gen_helper_vfp_sltoh(tcg_float, tcg_int32, | |
8213 | tcg_shift, tcg_fpst); | |
8214 | } else { | |
8215 | gen_helper_vfp_ultoh(tcg_float, tcg_int32, | |
8216 | tcg_shift, tcg_fpst); | |
8217 | } | |
8218 | } else { | |
8219 | if (is_signed) { | |
8220 | gen_helper_vfp_sitoh(tcg_float, tcg_int32, tcg_fpst); | |
8221 | } else { | |
8222 | gen_helper_vfp_uitoh(tcg_float, tcg_int32, tcg_fpst); | |
8223 | } | |
8224 | } | |
8225 | break; | |
8226 | default: | |
8227 | g_assert_not_reached(); | |
10113b69 | 8228 | } |
93193190 | 8229 | |
10113b69 | 8230 | if (elements == 1) { |
93193190 | 8231 | write_fp_sreg(s, rd, tcg_float); |
10113b69 | 8232 | } else { |
93193190 | 8233 | write_vec_element_i32(s, tcg_float, rd, pass, size); |
10113b69 | 8234 | } |
10113b69 | 8235 | } |
93193190 AB |
8236 | |
8237 | tcg_temp_free_i32(tcg_int32); | |
8238 | tcg_temp_free_i32(tcg_float); | |
10113b69 AB |
8239 | } |
8240 | ||
10113b69 | 8241 | tcg_temp_free_ptr(tcg_fpst); |
93193190 AB |
8242 | if (tcg_shift) { |
8243 | tcg_temp_free_i32(tcg_shift); | |
8244 | } | |
4ff55bcb RH |
8245 | |
8246 | clear_vec_high(s, elements << size == 16, rd); | |
10113b69 AB |
8247 | } |
8248 | ||
8249 | /* UCVTF/SCVTF - Integer to FP conversion */ | |
8250 | static void handle_simd_shift_intfp_conv(DisasContext *s, bool is_scalar, | |
8251 | bool is_q, bool is_u, | |
8252 | int immh, int immb, int opcode, | |
8253 | int rn, int rd) | |
8254 | { | |
a6117fae | 8255 | int size, elements, fracbits; |
10113b69 | 8256 | int immhb = immh << 3 | immb; |
10113b69 | 8257 | |
a6117fae RH |
8258 | if (immh & 8) { |
8259 | size = MO_64; | |
8260 | if (!is_scalar && !is_q) { | |
8261 | unallocated_encoding(s); | |
8262 | return; | |
8263 | } | |
8264 | } else if (immh & 4) { | |
8265 | size = MO_32; | |
8266 | } else if (immh & 2) { | |
8267 | size = MO_16; | |
5763190f | 8268 | if (!dc_isar_feature(aa64_fp16, s)) { |
a6117fae RH |
8269 | unallocated_encoding(s); |
8270 | return; | |
8271 | } | |
8272 | } else { | |
8273 | /* immh == 0 would be a failure of the decode logic */ | |
8274 | g_assert(immh == 1); | |
10113b69 AB |
8275 | unallocated_encoding(s); |
8276 | return; | |
8277 | } | |
8278 | ||
8279 | if (is_scalar) { | |
8280 | elements = 1; | |
8281 | } else { | |
a6117fae | 8282 | elements = (8 << is_q) >> size; |
10113b69 | 8283 | } |
a6117fae | 8284 | fracbits = (16 << size) - immhb; |
8c6afa6a PM |
8285 | |
8286 | if (!fp_access_check(s)) { | |
8287 | return; | |
8288 | } | |
8289 | ||
10113b69 AB |
8290 | handle_simd_intfp_conv(s, rd, rn, elements, !is_u, fracbits, size); |
8291 | } | |
8292 | ||
2ed3ea11 PM |
8293 | /* FCVTZS, FVCVTZU - FP to fixedpoint conversion */ |
8294 | static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar, | |
8295 | bool is_q, bool is_u, | |
8296 | int immh, int immb, int rn, int rd) | |
8297 | { | |
2ed3ea11 | 8298 | int immhb = immh << 3 | immb; |
d0ba8e74 | 8299 | int pass, size, fracbits; |
2ed3ea11 PM |
8300 | TCGv_ptr tcg_fpstatus; |
8301 | TCGv_i32 tcg_rmode, tcg_shift; | |
8302 | ||
d0ba8e74 RH |
8303 | if (immh & 0x8) { |
8304 | size = MO_64; | |
8305 | if (!is_scalar && !is_q) { | |
8306 | unallocated_encoding(s); | |
8307 | return; | |
8308 | } | |
8309 | } else if (immh & 0x4) { | |
8310 | size = MO_32; | |
8311 | } else if (immh & 0x2) { | |
8312 | size = MO_16; | |
5763190f | 8313 | if (!dc_isar_feature(aa64_fp16, s)) { |
d0ba8e74 RH |
8314 | unallocated_encoding(s); |
8315 | return; | |
8316 | } | |
8317 | } else { | |
8318 | /* Should have split out AdvSIMD modified immediate earlier. */ | |
8319 | assert(immh == 1); | |
2ed3ea11 PM |
8320 | unallocated_encoding(s); |
8321 | return; | |
8322 | } | |
8323 | ||
8c6afa6a PM |
8324 | if (!fp_access_check(s)) { |
8325 | return; | |
8326 | } | |
8327 | ||
2ed3ea11 PM |
8328 | assert(!(is_scalar && is_q)); |
8329 | ||
8330 | tcg_rmode = tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO)); | |
d0ba8e74 | 8331 | tcg_fpstatus = get_fpstatus_ptr(size == MO_16); |
9b049916 | 8332 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); |
d0ba8e74 | 8333 | fracbits = (16 << size) - immhb; |
2ed3ea11 PM |
8334 | tcg_shift = tcg_const_i32(fracbits); |
8335 | ||
d0ba8e74 | 8336 | if (size == MO_64) { |
4063452e | 8337 | int maxpass = is_scalar ? 1 : 2; |
2ed3ea11 PM |
8338 | |
8339 | for (pass = 0; pass < maxpass; pass++) { | |
8340 | TCGv_i64 tcg_op = tcg_temp_new_i64(); | |
8341 | ||
8342 | read_vec_element(s, tcg_op, rn, pass, MO_64); | |
8343 | if (is_u) { | |
8344 | gen_helper_vfp_touqd(tcg_op, tcg_op, tcg_shift, tcg_fpstatus); | |
8345 | } else { | |
8346 | gen_helper_vfp_tosqd(tcg_op, tcg_op, tcg_shift, tcg_fpstatus); | |
8347 | } | |
8348 | write_vec_element(s, tcg_op, rd, pass, MO_64); | |
8349 | tcg_temp_free_i64(tcg_op); | |
8350 | } | |
4ff55bcb | 8351 | clear_vec_high(s, is_q, rd); |
2ed3ea11 | 8352 | } else { |
d0ba8e74 RH |
8353 | void (*fn)(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_ptr); |
8354 | int maxpass = is_scalar ? 1 : ((8 << is_q) >> size); | |
2ed3ea11 | 8355 | |
d0ba8e74 RH |
8356 | switch (size) { |
8357 | case MO_16: | |
2ed3ea11 | 8358 | if (is_u) { |
88808a02 | 8359 | fn = gen_helper_vfp_touhh; |
2ed3ea11 | 8360 | } else { |
88808a02 | 8361 | fn = gen_helper_vfp_toshh; |
2ed3ea11 | 8362 | } |
d0ba8e74 RH |
8363 | break; |
8364 | case MO_32: | |
2ed3ea11 | 8365 | if (is_u) { |
d0ba8e74 | 8366 | fn = gen_helper_vfp_touls; |
2ed3ea11 | 8367 | } else { |
d0ba8e74 | 8368 | fn = gen_helper_vfp_tosls; |
2ed3ea11 | 8369 | } |
d0ba8e74 RH |
8370 | break; |
8371 | default: | |
8372 | g_assert_not_reached(); | |
8373 | } | |
8374 | ||
8375 | for (pass = 0; pass < maxpass; pass++) { | |
8376 | TCGv_i32 tcg_op = tcg_temp_new_i32(); | |
8377 | ||
8378 | read_vec_element_i32(s, tcg_op, rn, pass, size); | |
8379 | fn(tcg_op, tcg_op, tcg_shift, tcg_fpstatus); | |
2ed3ea11 PM |
8380 | if (is_scalar) { |
8381 | write_fp_sreg(s, rd, tcg_op); | |
8382 | } else { | |
d0ba8e74 | 8383 | write_vec_element_i32(s, tcg_op, rd, pass, size); |
2ed3ea11 PM |
8384 | } |
8385 | tcg_temp_free_i32(tcg_op); | |
8386 | } | |
4ff55bcb RH |
8387 | if (!is_scalar) { |
8388 | clear_vec_high(s, is_q, rd); | |
2ed3ea11 PM |
8389 | } |
8390 | } | |
8391 | ||
8392 | tcg_temp_free_ptr(tcg_fpstatus); | |
8393 | tcg_temp_free_i32(tcg_shift); | |
9b049916 | 8394 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); |
2ed3ea11 PM |
8395 | tcg_temp_free_i32(tcg_rmode); |
8396 | } | |
8397 | ||
4ce31af4 | 8398 | /* AdvSIMD scalar shift by immediate |
384b26fb AB |
8399 | * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0 |
8400 | * +-----+---+-------------+------+------+--------+---+------+------+ | |
8401 | * | 0 1 | U | 1 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd | | |
8402 | * +-----+---+-------------+------+------+--------+---+------+------+ | |
4d1cef84 AB |
8403 | * |
8404 | * This is the scalar version so it works on a fixed sized registers | |
384b26fb AB |
8405 | */ |
8406 | static void disas_simd_scalar_shift_imm(DisasContext *s, uint32_t insn) | |
8407 | { | |
4d1cef84 AB |
8408 | int rd = extract32(insn, 0, 5); |
8409 | int rn = extract32(insn, 5, 5); | |
8410 | int opcode = extract32(insn, 11, 5); | |
8411 | int immb = extract32(insn, 16, 3); | |
8412 | int immh = extract32(insn, 19, 4); | |
8413 | bool is_u = extract32(insn, 29, 1); | |
8414 | ||
c1b876b2 AB |
8415 | if (immh == 0) { |
8416 | unallocated_encoding(s); | |
8417 | return; | |
8418 | } | |
8419 | ||
4d1cef84 | 8420 | switch (opcode) { |
37a706ad PM |
8421 | case 0x08: /* SRI */ |
8422 | if (!is_u) { | |
8423 | unallocated_encoding(s); | |
8424 | return; | |
8425 | } | |
8426 | /* fall through */ | |
4d1cef84 AB |
8427 | case 0x00: /* SSHR / USHR */ |
8428 | case 0x02: /* SSRA / USRA */ | |
8429 | case 0x04: /* SRSHR / URSHR */ | |
8430 | case 0x06: /* SRSRA / URSRA */ | |
8431 | handle_scalar_simd_shri(s, is_u, immh, immb, opcode, rn, rd); | |
8432 | break; | |
8433 | case 0x0a: /* SHL / SLI */ | |
8434 | handle_scalar_simd_shli(s, is_u, immh, immb, opcode, rn, rd); | |
8435 | break; | |
10113b69 AB |
8436 | case 0x1c: /* SCVTF, UCVTF */ |
8437 | handle_simd_shift_intfp_conv(s, true, false, is_u, immh, immb, | |
8438 | opcode, rn, rd); | |
8439 | break; | |
c1b876b2 AB |
8440 | case 0x10: /* SQSHRUN, SQSHRUN2 */ |
8441 | case 0x11: /* SQRSHRUN, SQRSHRUN2 */ | |
8442 | if (!is_u) { | |
8443 | unallocated_encoding(s); | |
8444 | return; | |
8445 | } | |
8446 | handle_vec_simd_sqshrn(s, true, false, false, true, | |
8447 | immh, immb, opcode, rn, rd); | |
8448 | break; | |
8449 | case 0x12: /* SQSHRN, SQSHRN2, UQSHRN */ | |
8450 | case 0x13: /* SQRSHRN, SQRSHRN2, UQRSHRN, UQRSHRN2 */ | |
8451 | handle_vec_simd_sqshrn(s, true, false, is_u, is_u, | |
8452 | immh, immb, opcode, rn, rd); | |
8453 | break; | |
a566da1b | 8454 | case 0xc: /* SQSHLU */ |
a847f32c PM |
8455 | if (!is_u) { |
8456 | unallocated_encoding(s); | |
8457 | return; | |
8458 | } | |
8459 | handle_simd_qshl(s, true, false, false, true, immh, immb, rn, rd); | |
8460 | break; | |
a566da1b | 8461 | case 0xe: /* SQSHL, UQSHL */ |
a847f32c PM |
8462 | handle_simd_qshl(s, true, false, is_u, is_u, immh, immb, rn, rd); |
8463 | break; | |
a566da1b | 8464 | case 0x1f: /* FCVTZS, FCVTZU */ |
2ed3ea11 | 8465 | handle_simd_shift_fpint_conv(s, true, false, is_u, immh, immb, rn, rd); |
4d1cef84 | 8466 | break; |
a566da1b PM |
8467 | default: |
8468 | unallocated_encoding(s); | |
8469 | break; | |
4d1cef84 | 8470 | } |
384b26fb AB |
8471 | } |
8472 | ||
4ce31af4 | 8473 | /* AdvSIMD scalar three different |
384b26fb AB |
8474 | * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0 |
8475 | * +-----+---+-----------+------+---+------+--------+-----+------+------+ | |
8476 | * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd | | |
8477 | * +-----+---+-----------+------+---+------+--------+-----+------+------+ | |
8478 | */ | |
8479 | static void disas_simd_scalar_three_reg_diff(DisasContext *s, uint32_t insn) | |
8480 | { | |
b033cd3d PM |
8481 | bool is_u = extract32(insn, 29, 1); |
8482 | int size = extract32(insn, 22, 2); | |
8483 | int opcode = extract32(insn, 12, 4); | |
8484 | int rm = extract32(insn, 16, 5); | |
8485 | int rn = extract32(insn, 5, 5); | |
8486 | int rd = extract32(insn, 0, 5); | |
8487 | ||
8488 | if (is_u) { | |
8489 | unallocated_encoding(s); | |
8490 | return; | |
8491 | } | |
8492 | ||
8493 | switch (opcode) { | |
8494 | case 0x9: /* SQDMLAL, SQDMLAL2 */ | |
8495 | case 0xb: /* SQDMLSL, SQDMLSL2 */ | |
8496 | case 0xd: /* SQDMULL, SQDMULL2 */ | |
8497 | if (size == 0 || size == 3) { | |
8498 | unallocated_encoding(s); | |
8499 | return; | |
8500 | } | |
8501 | break; | |
8502 | default: | |
8503 | unallocated_encoding(s); | |
8504 | return; | |
8505 | } | |
8506 | ||
8c6afa6a PM |
8507 | if (!fp_access_check(s)) { |
8508 | return; | |
8509 | } | |
8510 | ||
b033cd3d PM |
8511 | if (size == 2) { |
8512 | TCGv_i64 tcg_op1 = tcg_temp_new_i64(); | |
8513 | TCGv_i64 tcg_op2 = tcg_temp_new_i64(); | |
8514 | TCGv_i64 tcg_res = tcg_temp_new_i64(); | |
8515 | ||
8516 | read_vec_element(s, tcg_op1, rn, 0, MO_32 | MO_SIGN); | |
8517 | read_vec_element(s, tcg_op2, rm, 0, MO_32 | MO_SIGN); | |
8518 | ||
8519 | tcg_gen_mul_i64(tcg_res, tcg_op1, tcg_op2); | |
8520 | gen_helper_neon_addl_saturate_s64(tcg_res, cpu_env, tcg_res, tcg_res); | |
8521 | ||
8522 | switch (opcode) { | |
8523 | case 0xd: /* SQDMULL, SQDMULL2 */ | |
8524 | break; | |
8525 | case 0xb: /* SQDMLSL, SQDMLSL2 */ | |
8526 | tcg_gen_neg_i64(tcg_res, tcg_res); | |
8527 | /* fall through */ | |
8528 | case 0x9: /* SQDMLAL, SQDMLAL2 */ | |
8529 | read_vec_element(s, tcg_op1, rd, 0, MO_64); | |
8530 | gen_helper_neon_addl_saturate_s64(tcg_res, cpu_env, | |
8531 | tcg_res, tcg_op1); | |
8532 | break; | |
8533 | default: | |
8534 | g_assert_not_reached(); | |
8535 | } | |
8536 | ||
8537 | write_fp_dreg(s, rd, tcg_res); | |
8538 | ||
8539 | tcg_temp_free_i64(tcg_op1); | |
8540 | tcg_temp_free_i64(tcg_op2); | |
8541 | tcg_temp_free_i64(tcg_res); | |
8542 | } else { | |
3d99d931 RH |
8543 | TCGv_i32 tcg_op1 = read_fp_hreg(s, rn); |
8544 | TCGv_i32 tcg_op2 = read_fp_hreg(s, rm); | |
b033cd3d PM |
8545 | TCGv_i64 tcg_res = tcg_temp_new_i64(); |
8546 | ||
b033cd3d PM |
8547 | gen_helper_neon_mull_s16(tcg_res, tcg_op1, tcg_op2); |
8548 | gen_helper_neon_addl_saturate_s32(tcg_res, cpu_env, tcg_res, tcg_res); | |
8549 | ||
8550 | switch (opcode) { | |
8551 | case 0xd: /* SQDMULL, SQDMULL2 */ | |
8552 | break; | |
8553 | case 0xb: /* SQDMLSL, SQDMLSL2 */ | |
8554 | gen_helper_neon_negl_u32(tcg_res, tcg_res); | |
8555 | /* fall through */ | |
8556 | case 0x9: /* SQDMLAL, SQDMLAL2 */ | |
8557 | { | |
8558 | TCGv_i64 tcg_op3 = tcg_temp_new_i64(); | |
8559 | read_vec_element(s, tcg_op3, rd, 0, MO_32); | |
8560 | gen_helper_neon_addl_saturate_s32(tcg_res, cpu_env, | |
8561 | tcg_res, tcg_op3); | |
8562 | tcg_temp_free_i64(tcg_op3); | |
8563 | break; | |
8564 | } | |
8565 | default: | |
8566 | g_assert_not_reached(); | |
8567 | } | |
8568 | ||
8569 | tcg_gen_ext32u_i64(tcg_res, tcg_res); | |
8570 | write_fp_dreg(s, rd, tcg_res); | |
8571 | ||
8572 | tcg_temp_free_i32(tcg_op1); | |
8573 | tcg_temp_free_i32(tcg_op2); | |
8574 | tcg_temp_free_i64(tcg_res); | |
8575 | } | |
384b26fb AB |
8576 | } |
8577 | ||
b305dba6 PM |
8578 | static void handle_3same_64(DisasContext *s, int opcode, bool u, |
8579 | TCGv_i64 tcg_rd, TCGv_i64 tcg_rn, TCGv_i64 tcg_rm) | |
8580 | { | |
8581 | /* Handle 64x64->64 opcodes which are shared between the scalar | |
8582 | * and vector 3-same groups. We cover every opcode where size == 3 | |
8583 | * is valid in either the three-reg-same (integer, not pairwise) | |
3840d219 | 8584 | * or scalar-three-reg-same groups. |
b305dba6 PM |
8585 | */ |
8586 | TCGCond cond; | |
8587 | ||
8588 | switch (opcode) { | |
6d9571f7 PM |
8589 | case 0x1: /* SQADD */ |
8590 | if (u) { | |
8591 | gen_helper_neon_qadd_u64(tcg_rd, cpu_env, tcg_rn, tcg_rm); | |
8592 | } else { | |
8593 | gen_helper_neon_qadd_s64(tcg_rd, cpu_env, tcg_rn, tcg_rm); | |
8594 | } | |
8595 | break; | |
8596 | case 0x5: /* SQSUB */ | |
8597 | if (u) { | |
8598 | gen_helper_neon_qsub_u64(tcg_rd, cpu_env, tcg_rn, tcg_rm); | |
8599 | } else { | |
8600 | gen_helper_neon_qsub_s64(tcg_rd, cpu_env, tcg_rn, tcg_rm); | |
8601 | } | |
8602 | break; | |
b305dba6 PM |
8603 | case 0x6: /* CMGT, CMHI */ |
8604 | /* 64 bit integer comparison, result = test ? (2^64 - 1) : 0. | |
8605 | * We implement this using setcond (test) and then negating. | |
8606 | */ | |
8607 | cond = u ? TCG_COND_GTU : TCG_COND_GT; | |
8608 | do_cmop: | |
8609 | tcg_gen_setcond_i64(cond, tcg_rd, tcg_rn, tcg_rm); | |
8610 | tcg_gen_neg_i64(tcg_rd, tcg_rd); | |
8611 | break; | |
8612 | case 0x7: /* CMGE, CMHS */ | |
8613 | cond = u ? TCG_COND_GEU : TCG_COND_GE; | |
8614 | goto do_cmop; | |
8615 | case 0x11: /* CMTST, CMEQ */ | |
8616 | if (u) { | |
8617 | cond = TCG_COND_EQ; | |
8618 | goto do_cmop; | |
8619 | } | |
79d61de6 | 8620 | gen_cmtst_i64(tcg_rd, tcg_rn, tcg_rm); |
b305dba6 | 8621 | break; |
6d9571f7 | 8622 | case 0x8: /* SSHL, USHL */ |
b305dba6 | 8623 | if (u) { |
6d9571f7 | 8624 | gen_helper_neon_shl_u64(tcg_rd, tcg_rn, tcg_rm); |
b305dba6 | 8625 | } else { |
6d9571f7 | 8626 | gen_helper_neon_shl_s64(tcg_rd, tcg_rn, tcg_rm); |
b305dba6 PM |
8627 | } |
8628 | break; | |
b305dba6 | 8629 | case 0x9: /* SQSHL, UQSHL */ |
6d9571f7 PM |
8630 | if (u) { |
8631 | gen_helper_neon_qshl_u64(tcg_rd, cpu_env, tcg_rn, tcg_rm); | |
8632 | } else { | |
8633 | gen_helper_neon_qshl_s64(tcg_rd, cpu_env, tcg_rn, tcg_rm); | |
8634 | } | |
8635 | break; | |
b305dba6 | 8636 | case 0xa: /* SRSHL, URSHL */ |
6d9571f7 PM |
8637 | if (u) { |
8638 | gen_helper_neon_rshl_u64(tcg_rd, tcg_rn, tcg_rm); | |
8639 | } else { | |
8640 | gen_helper_neon_rshl_s64(tcg_rd, tcg_rn, tcg_rm); | |
8641 | } | |
8642 | break; | |
b305dba6 | 8643 | case 0xb: /* SQRSHL, UQRSHL */ |
6d9571f7 PM |
8644 | if (u) { |
8645 | gen_helper_neon_qrshl_u64(tcg_rd, cpu_env, tcg_rn, tcg_rm); | |
8646 | } else { | |
8647 | gen_helper_neon_qrshl_s64(tcg_rd, cpu_env, tcg_rn, tcg_rm); | |
8648 | } | |
8649 | break; | |
8650 | case 0x10: /* ADD, SUB */ | |
8651 | if (u) { | |
8652 | tcg_gen_sub_i64(tcg_rd, tcg_rn, tcg_rm); | |
8653 | } else { | |
8654 | tcg_gen_add_i64(tcg_rd, tcg_rn, tcg_rm); | |
8655 | } | |
8656 | break; | |
b305dba6 PM |
8657 | default: |
8658 | g_assert_not_reached(); | |
8659 | } | |
8660 | } | |
8661 | ||
845ea09a PM |
8662 | /* Handle the 3-same-operands float operations; shared by the scalar |
8663 | * and vector encodings. The caller must filter out any encodings | |
8664 | * not allocated for the encoding it is dealing with. | |
8665 | */ | |
8666 | static void handle_3same_float(DisasContext *s, int size, int elements, | |
8667 | int fpopcode, int rd, int rn, int rm) | |
8668 | { | |
8669 | int pass; | |
d81ce0ef | 8670 | TCGv_ptr fpst = get_fpstatus_ptr(false); |
845ea09a PM |
8671 | |
8672 | for (pass = 0; pass < elements; pass++) { | |
8673 | if (size) { | |
8674 | /* Double */ | |
8675 | TCGv_i64 tcg_op1 = tcg_temp_new_i64(); | |
8676 | TCGv_i64 tcg_op2 = tcg_temp_new_i64(); | |
8677 | TCGv_i64 tcg_res = tcg_temp_new_i64(); | |
8678 | ||
8679 | read_vec_element(s, tcg_op1, rn, pass, MO_64); | |
8680 | read_vec_element(s, tcg_op2, rm, pass, MO_64); | |
8681 | ||
8682 | switch (fpopcode) { | |
057d5f62 PM |
8683 | case 0x39: /* FMLS */ |
8684 | /* As usual for ARM, separate negation for fused multiply-add */ | |
8685 | gen_helper_vfp_negd(tcg_op1, tcg_op1); | |
8686 | /* fall through */ | |
8687 | case 0x19: /* FMLA */ | |
8688 | read_vec_element(s, tcg_res, rd, pass, MO_64); | |
8689 | gen_helper_vfp_muladdd(tcg_res, tcg_op1, tcg_op2, | |
8690 | tcg_res, fpst); | |
8691 | break; | |
845ea09a PM |
8692 | case 0x18: /* FMAXNM */ |
8693 | gen_helper_vfp_maxnumd(tcg_res, tcg_op1, tcg_op2, fpst); | |
8694 | break; | |
8695 | case 0x1a: /* FADD */ | |
8696 | gen_helper_vfp_addd(tcg_res, tcg_op1, tcg_op2, fpst); | |
8697 | break; | |
057d5f62 PM |
8698 | case 0x1b: /* FMULX */ |
8699 | gen_helper_vfp_mulxd(tcg_res, tcg_op1, tcg_op2, fpst); | |
8700 | break; | |
8908f4d1 AB |
8701 | case 0x1c: /* FCMEQ */ |
8702 | gen_helper_neon_ceq_f64(tcg_res, tcg_op1, tcg_op2, fpst); | |
8703 | break; | |
845ea09a PM |
8704 | case 0x1e: /* FMAX */ |
8705 | gen_helper_vfp_maxd(tcg_res, tcg_op1, tcg_op2, fpst); | |
8706 | break; | |
057d5f62 PM |
8707 | case 0x1f: /* FRECPS */ |
8708 | gen_helper_recpsf_f64(tcg_res, tcg_op1, tcg_op2, fpst); | |
8709 | break; | |
845ea09a PM |
8710 | case 0x38: /* FMINNM */ |
8711 | gen_helper_vfp_minnumd(tcg_res, tcg_op1, tcg_op2, fpst); | |
8712 | break; | |
8713 | case 0x3a: /* FSUB */ | |
8714 | gen_helper_vfp_subd(tcg_res, tcg_op1, tcg_op2, fpst); | |
8715 | break; | |
8716 | case 0x3e: /* FMIN */ | |
8717 | gen_helper_vfp_mind(tcg_res, tcg_op1, tcg_op2, fpst); | |
8718 | break; | |
057d5f62 PM |
8719 | case 0x3f: /* FRSQRTS */ |
8720 | gen_helper_rsqrtsf_f64(tcg_res, tcg_op1, tcg_op2, fpst); | |
8721 | break; | |
845ea09a PM |
8722 | case 0x5b: /* FMUL */ |
8723 | gen_helper_vfp_muld(tcg_res, tcg_op1, tcg_op2, fpst); | |
8724 | break; | |
8908f4d1 AB |
8725 | case 0x5c: /* FCMGE */ |
8726 | gen_helper_neon_cge_f64(tcg_res, tcg_op1, tcg_op2, fpst); | |
8727 | break; | |
057d5f62 PM |
8728 | case 0x5d: /* FACGE */ |
8729 | gen_helper_neon_acge_f64(tcg_res, tcg_op1, tcg_op2, fpst); | |
8730 | break; | |
845ea09a PM |
8731 | case 0x5f: /* FDIV */ |
8732 | gen_helper_vfp_divd(tcg_res, tcg_op1, tcg_op2, fpst); | |
8733 | break; | |
8734 | case 0x7a: /* FABD */ | |
8735 | gen_helper_vfp_subd(tcg_res, tcg_op1, tcg_op2, fpst); | |
8736 | gen_helper_vfp_absd(tcg_res, tcg_res); | |
8737 | break; | |
8908f4d1 AB |
8738 | case 0x7c: /* FCMGT */ |
8739 | gen_helper_neon_cgt_f64(tcg_res, tcg_op1, tcg_op2, fpst); | |
8740 | break; | |
057d5f62 PM |
8741 | case 0x7d: /* FACGT */ |
8742 | gen_helper_neon_acgt_f64(tcg_res, tcg_op1, tcg_op2, fpst); | |
8743 | break; | |
845ea09a PM |
8744 | default: |
8745 | g_assert_not_reached(); | |
8746 | } | |
8747 | ||
8748 | write_vec_element(s, tcg_res, rd, pass, MO_64); | |
8749 | ||
8750 | tcg_temp_free_i64(tcg_res); | |
8751 | tcg_temp_free_i64(tcg_op1); | |
8752 | tcg_temp_free_i64(tcg_op2); | |
8753 | } else { | |
8754 | /* Single */ | |
8755 | TCGv_i32 tcg_op1 = tcg_temp_new_i32(); | |
8756 | TCGv_i32 tcg_op2 = tcg_temp_new_i32(); | |
8757 | TCGv_i32 tcg_res = tcg_temp_new_i32(); | |
8758 | ||
8759 | read_vec_element_i32(s, tcg_op1, rn, pass, MO_32); | |
8760 | read_vec_element_i32(s, tcg_op2, rm, pass, MO_32); | |
8761 | ||
8762 | switch (fpopcode) { | |
057d5f62 PM |
8763 | case 0x39: /* FMLS */ |
8764 | /* As usual for ARM, separate negation for fused multiply-add */ | |
8765 | gen_helper_vfp_negs(tcg_op1, tcg_op1); | |
8766 | /* fall through */ | |
8767 | case 0x19: /* FMLA */ | |
8768 | read_vec_element_i32(s, tcg_res, rd, pass, MO_32); | |
8769 | gen_helper_vfp_muladds(tcg_res, tcg_op1, tcg_op2, | |
8770 | tcg_res, fpst); | |
8771 | break; | |
845ea09a PM |
8772 | case 0x1a: /* FADD */ |
8773 | gen_helper_vfp_adds(tcg_res, tcg_op1, tcg_op2, fpst); | |
8774 | break; | |
057d5f62 PM |
8775 | case 0x1b: /* FMULX */ |
8776 | gen_helper_vfp_mulxs(tcg_res, tcg_op1, tcg_op2, fpst); | |
8777 | break; | |
8908f4d1 AB |
8778 | case 0x1c: /* FCMEQ */ |
8779 | gen_helper_neon_ceq_f32(tcg_res, tcg_op1, tcg_op2, fpst); | |
8780 | break; | |
845ea09a PM |
8781 | case 0x1e: /* FMAX */ |
8782 | gen_helper_vfp_maxs(tcg_res, tcg_op1, tcg_op2, fpst); | |
8783 | break; | |
057d5f62 PM |
8784 | case 0x1f: /* FRECPS */ |
8785 | gen_helper_recpsf_f32(tcg_res, tcg_op1, tcg_op2, fpst); | |
8786 | break; | |
845ea09a PM |
8787 | case 0x18: /* FMAXNM */ |
8788 | gen_helper_vfp_maxnums(tcg_res, tcg_op1, tcg_op2, fpst); | |
8789 | break; | |
8790 | case 0x38: /* FMINNM */ | |
8791 | gen_helper_vfp_minnums(tcg_res, tcg_op1, tcg_op2, fpst); | |
8792 | break; | |
8793 | case 0x3a: /* FSUB */ | |
8794 | gen_helper_vfp_subs(tcg_res, tcg_op1, tcg_op2, fpst); | |
8795 | break; | |
8796 | case 0x3e: /* FMIN */ | |
8797 | gen_helper_vfp_mins(tcg_res, tcg_op1, tcg_op2, fpst); | |
8798 | break; | |
057d5f62 PM |
8799 | case 0x3f: /* FRSQRTS */ |
8800 | gen_helper_rsqrtsf_f32(tcg_res, tcg_op1, tcg_op2, fpst); | |
8801 | break; | |
845ea09a PM |
8802 | case 0x5b: /* FMUL */ |
8803 | gen_helper_vfp_muls(tcg_res, tcg_op1, tcg_op2, fpst); | |
8804 | break; | |
8908f4d1 AB |
8805 | case 0x5c: /* FCMGE */ |
8806 | gen_helper_neon_cge_f32(tcg_res, tcg_op1, tcg_op2, fpst); | |
8807 | break; | |
057d5f62 PM |
8808 | case 0x5d: /* FACGE */ |
8809 | gen_helper_neon_acge_f32(tcg_res, tcg_op1, tcg_op2, fpst); | |
8810 | break; | |
845ea09a PM |
8811 | case 0x5f: /* FDIV */ |
8812 | gen_helper_vfp_divs(tcg_res, tcg_op1, tcg_op2, fpst); | |
8813 | break; | |
8814 | case 0x7a: /* FABD */ | |
8815 | gen_helper_vfp_subs(tcg_res, tcg_op1, tcg_op2, fpst); | |
8816 | gen_helper_vfp_abss(tcg_res, tcg_res); | |
8817 | break; | |
8908f4d1 AB |
8818 | case 0x7c: /* FCMGT */ |
8819 | gen_helper_neon_cgt_f32(tcg_res, tcg_op1, tcg_op2, fpst); | |
8820 | break; | |
057d5f62 PM |
8821 | case 0x7d: /* FACGT */ |
8822 | gen_helper_neon_acgt_f32(tcg_res, tcg_op1, tcg_op2, fpst); | |
8823 | break; | |
845ea09a PM |
8824 | default: |
8825 | g_assert_not_reached(); | |
8826 | } | |
8827 | ||
8828 | if (elements == 1) { | |
8829 | /* scalar single so clear high part */ | |
8830 | TCGv_i64 tcg_tmp = tcg_temp_new_i64(); | |
8831 | ||
8832 | tcg_gen_extu_i32_i64(tcg_tmp, tcg_res); | |
8833 | write_vec_element(s, tcg_tmp, rd, pass, MO_64); | |
8834 | tcg_temp_free_i64(tcg_tmp); | |
8835 | } else { | |
8836 | write_vec_element_i32(s, tcg_res, rd, pass, MO_32); | |
8837 | } | |
8838 | ||
8839 | tcg_temp_free_i32(tcg_res); | |
8840 | tcg_temp_free_i32(tcg_op1); | |
8841 | tcg_temp_free_i32(tcg_op2); | |
8842 | } | |
8843 | } | |
8844 | ||
8845 | tcg_temp_free_ptr(fpst); | |
8846 | ||
4ff55bcb | 8847 | clear_vec_high(s, elements * (size ? 8 : 4) > 8, rd); |
845ea09a PM |
8848 | } |
8849 | ||
4ce31af4 | 8850 | /* AdvSIMD scalar three same |
384b26fb AB |
8851 | * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0 |
8852 | * +-----+---+-----------+------+---+------+--------+---+------+------+ | |
8853 | * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd | | |
8854 | * +-----+---+-----------+------+---+------+--------+---+------+------+ | |
8855 | */ | |
8856 | static void disas_simd_scalar_three_reg_same(DisasContext *s, uint32_t insn) | |
8857 | { | |
b305dba6 PM |
8858 | int rd = extract32(insn, 0, 5); |
8859 | int rn = extract32(insn, 5, 5); | |
8860 | int opcode = extract32(insn, 11, 5); | |
8861 | int rm = extract32(insn, 16, 5); | |
8862 | int size = extract32(insn, 22, 2); | |
8863 | bool u = extract32(insn, 29, 1); | |
b305dba6 PM |
8864 | TCGv_i64 tcg_rd; |
8865 | ||
8866 | if (opcode >= 0x18) { | |
8867 | /* Floating point: U, size[1] and opcode indicate operation */ | |
8868 | int fpopcode = opcode | (extract32(size, 1, 1) << 5) | (u << 6); | |
8869 | switch (fpopcode) { | |
8870 | case 0x1b: /* FMULX */ | |
b305dba6 PM |
8871 | case 0x1f: /* FRECPS */ |
8872 | case 0x3f: /* FRSQRTS */ | |
b305dba6 | 8873 | case 0x5d: /* FACGE */ |
b305dba6 | 8874 | case 0x7d: /* FACGT */ |
8908f4d1 AB |
8875 | case 0x1c: /* FCMEQ */ |
8876 | case 0x5c: /* FCMGE */ | |
8877 | case 0x7c: /* FCMGT */ | |
845ea09a PM |
8878 | case 0x7a: /* FABD */ |
8879 | break; | |
b305dba6 PM |
8880 | default: |
8881 | unallocated_encoding(s); | |
8882 | return; | |
8883 | } | |
845ea09a | 8884 | |
8c6afa6a PM |
8885 | if (!fp_access_check(s)) { |
8886 | return; | |
8887 | } | |
8888 | ||
845ea09a PM |
8889 | handle_3same_float(s, extract32(size, 0, 1), 1, fpopcode, rd, rn, rm); |
8890 | return; | |
b305dba6 PM |
8891 | } |
8892 | ||
8893 | switch (opcode) { | |
8894 | case 0x1: /* SQADD, UQADD */ | |
8895 | case 0x5: /* SQSUB, UQSUB */ | |
c0b2b5fa PM |
8896 | case 0x9: /* SQSHL, UQSHL */ |
8897 | case 0xb: /* SQRSHL, UQRSHL */ | |
8898 | break; | |
6d9571f7 PM |
8899 | case 0x8: /* SSHL, USHL */ |
8900 | case 0xa: /* SRSHL, URSHL */ | |
b305dba6 PM |
8901 | case 0x6: /* CMGT, CMHI */ |
8902 | case 0x7: /* CMGE, CMHS */ | |
8903 | case 0x11: /* CMTST, CMEQ */ | |
8904 | case 0x10: /* ADD, SUB (vector) */ | |
8905 | if (size != 3) { | |
8906 | unallocated_encoding(s); | |
8907 | return; | |
8908 | } | |
8909 | break; | |
b305dba6 PM |
8910 | case 0x16: /* SQDMULH, SQRDMULH (vector) */ |
8911 | if (size != 1 && size != 2) { | |
8912 | unallocated_encoding(s); | |
8913 | return; | |
8914 | } | |
c0b2b5fa | 8915 | break; |
b305dba6 PM |
8916 | default: |
8917 | unallocated_encoding(s); | |
8918 | return; | |
8919 | } | |
8920 | ||
8c6afa6a PM |
8921 | if (!fp_access_check(s)) { |
8922 | return; | |
8923 | } | |
8924 | ||
b305dba6 PM |
8925 | tcg_rd = tcg_temp_new_i64(); |
8926 | ||
c0b2b5fa PM |
8927 | if (size == 3) { |
8928 | TCGv_i64 tcg_rn = read_fp_dreg(s, rn); | |
8929 | TCGv_i64 tcg_rm = read_fp_dreg(s, rm); | |
8930 | ||
8931 | handle_3same_64(s, opcode, u, tcg_rd, tcg_rn, tcg_rm); | |
8932 | tcg_temp_free_i64(tcg_rn); | |
8933 | tcg_temp_free_i64(tcg_rm); | |
8934 | } else { | |
8935 | /* Do a single operation on the lowest element in the vector. | |
8936 | * We use the standard Neon helpers and rely on 0 OP 0 == 0 with | |
8937 | * no side effects for all these operations. | |
8938 | * OPTME: special-purpose helpers would avoid doing some | |
8939 | * unnecessary work in the helper for the 8 and 16 bit cases. | |
8940 | */ | |
8941 | NeonGenTwoOpEnvFn *genenvfn; | |
8942 | TCGv_i32 tcg_rn = tcg_temp_new_i32(); | |
8943 | TCGv_i32 tcg_rm = tcg_temp_new_i32(); | |
8944 | TCGv_i32 tcg_rd32 = tcg_temp_new_i32(); | |
8945 | ||
8946 | read_vec_element_i32(s, tcg_rn, rn, 0, size); | |
8947 | read_vec_element_i32(s, tcg_rm, rm, 0, size); | |
8948 | ||
8949 | switch (opcode) { | |
8950 | case 0x1: /* SQADD, UQADD */ | |
8951 | { | |
8952 | static NeonGenTwoOpEnvFn * const fns[3][2] = { | |
8953 | { gen_helper_neon_qadd_s8, gen_helper_neon_qadd_u8 }, | |
8954 | { gen_helper_neon_qadd_s16, gen_helper_neon_qadd_u16 }, | |
8955 | { gen_helper_neon_qadd_s32, gen_helper_neon_qadd_u32 }, | |
8956 | }; | |
8957 | genenvfn = fns[size][u]; | |
8958 | break; | |
8959 | } | |
8960 | case 0x5: /* SQSUB, UQSUB */ | |
8961 | { | |
8962 | static NeonGenTwoOpEnvFn * const fns[3][2] = { | |
8963 | { gen_helper_neon_qsub_s8, gen_helper_neon_qsub_u8 }, | |
8964 | { gen_helper_neon_qsub_s16, gen_helper_neon_qsub_u16 }, | |
8965 | { gen_helper_neon_qsub_s32, gen_helper_neon_qsub_u32 }, | |
8966 | }; | |
8967 | genenvfn = fns[size][u]; | |
8968 | break; | |
8969 | } | |
8970 | case 0x9: /* SQSHL, UQSHL */ | |
8971 | { | |
8972 | static NeonGenTwoOpEnvFn * const fns[3][2] = { | |
8973 | { gen_helper_neon_qshl_s8, gen_helper_neon_qshl_u8 }, | |
8974 | { gen_helper_neon_qshl_s16, gen_helper_neon_qshl_u16 }, | |
8975 | { gen_helper_neon_qshl_s32, gen_helper_neon_qshl_u32 }, | |
8976 | }; | |
8977 | genenvfn = fns[size][u]; | |
8978 | break; | |
8979 | } | |
8980 | case 0xb: /* SQRSHL, UQRSHL */ | |
8981 | { | |
8982 | static NeonGenTwoOpEnvFn * const fns[3][2] = { | |
8983 | { gen_helper_neon_qrshl_s8, gen_helper_neon_qrshl_u8 }, | |
8984 | { gen_helper_neon_qrshl_s16, gen_helper_neon_qrshl_u16 }, | |
8985 | { gen_helper_neon_qrshl_s32, gen_helper_neon_qrshl_u32 }, | |
8986 | }; | |
8987 | genenvfn = fns[size][u]; | |
8988 | break; | |
8989 | } | |
8990 | case 0x16: /* SQDMULH, SQRDMULH */ | |
8991 | { | |
8992 | static NeonGenTwoOpEnvFn * const fns[2][2] = { | |
8993 | { gen_helper_neon_qdmulh_s16, gen_helper_neon_qrdmulh_s16 }, | |
8994 | { gen_helper_neon_qdmulh_s32, gen_helper_neon_qrdmulh_s32 }, | |
8995 | }; | |
8996 | assert(size == 1 || size == 2); | |
8997 | genenvfn = fns[size - 1][u]; | |
8998 | break; | |
8999 | } | |
9000 | default: | |
9001 | g_assert_not_reached(); | |
9002 | } | |
9003 | ||
9004 | genenvfn(tcg_rd32, cpu_env, tcg_rn, tcg_rm); | |
9005 | tcg_gen_extu_i32_i64(tcg_rd, tcg_rd32); | |
9006 | tcg_temp_free_i32(tcg_rd32); | |
9007 | tcg_temp_free_i32(tcg_rn); | |
9008 | tcg_temp_free_i32(tcg_rm); | |
9009 | } | |
b305dba6 PM |
9010 | |
9011 | write_fp_dreg(s, rd, tcg_rd); | |
9012 | ||
b305dba6 | 9013 | tcg_temp_free_i64(tcg_rd); |
384b26fb AB |
9014 | } |
9015 | ||
7c93b774 AB |
9016 | /* AdvSIMD scalar three same FP16 |
9017 | * 31 30 29 28 24 23 22 21 20 16 15 14 13 11 10 9 5 4 0 | |
9018 | * +-----+---+-----------+---+-----+------+-----+--------+---+----+----+ | |
9019 | * | 0 1 | U | 1 1 1 1 0 | a | 1 0 | Rm | 0 0 | opcode | 1 | Rn | Rd | | |
9020 | * +-----+---+-----------+---+-----+------+-----+--------+---+----+----+ | |
9021 | * v: 0101 1110 0100 0000 0000 0100 0000 0000 => 5e400400 | |
9022 | * m: 1101 1111 0110 0000 1100 0100 0000 0000 => df60c400 | |
9023 | */ | |
9024 | static void disas_simd_scalar_three_reg_same_fp16(DisasContext *s, | |
9025 | uint32_t insn) | |
9026 | { | |
9027 | int rd = extract32(insn, 0, 5); | |
9028 | int rn = extract32(insn, 5, 5); | |
9029 | int opcode = extract32(insn, 11, 3); | |
9030 | int rm = extract32(insn, 16, 5); | |
9031 | bool u = extract32(insn, 29, 1); | |
9032 | bool a = extract32(insn, 23, 1); | |
9033 | int fpopcode = opcode | (a << 3) | (u << 4); | |
9034 | TCGv_ptr fpst; | |
9035 | TCGv_i32 tcg_op1; | |
9036 | TCGv_i32 tcg_op2; | |
9037 | TCGv_i32 tcg_res; | |
9038 | ||
9039 | switch (fpopcode) { | |
9040 | case 0x03: /* FMULX */ | |
9041 | case 0x04: /* FCMEQ (reg) */ | |
9042 | case 0x07: /* FRECPS */ | |
9043 | case 0x0f: /* FRSQRTS */ | |
9044 | case 0x14: /* FCMGE (reg) */ | |
9045 | case 0x15: /* FACGE */ | |
9046 | case 0x1a: /* FABD */ | |
9047 | case 0x1c: /* FCMGT (reg) */ | |
9048 | case 0x1d: /* FACGT */ | |
9049 | break; | |
9050 | default: | |
9051 | unallocated_encoding(s); | |
9052 | return; | |
9053 | } | |
9054 | ||
5763190f | 9055 | if (!dc_isar_feature(aa64_fp16, s)) { |
7c93b774 AB |
9056 | unallocated_encoding(s); |
9057 | } | |
9058 | ||
9059 | if (!fp_access_check(s)) { | |
9060 | return; | |
9061 | } | |
9062 | ||
9063 | fpst = get_fpstatus_ptr(true); | |
9064 | ||
3d99d931 RH |
9065 | tcg_op1 = read_fp_hreg(s, rn); |
9066 | tcg_op2 = read_fp_hreg(s, rm); | |
7c93b774 AB |
9067 | tcg_res = tcg_temp_new_i32(); |
9068 | ||
7c93b774 AB |
9069 | switch (fpopcode) { |
9070 | case 0x03: /* FMULX */ | |
9071 | gen_helper_advsimd_mulxh(tcg_res, tcg_op1, tcg_op2, fpst); | |
9072 | break; | |
9073 | case 0x04: /* FCMEQ (reg) */ | |
9074 | gen_helper_advsimd_ceq_f16(tcg_res, tcg_op1, tcg_op2, fpst); | |
9075 | break; | |
9076 | case 0x07: /* FRECPS */ | |
9077 | gen_helper_recpsf_f16(tcg_res, tcg_op1, tcg_op2, fpst); | |
9078 | break; | |
9079 | case 0x0f: /* FRSQRTS */ | |
9080 | gen_helper_rsqrtsf_f16(tcg_res, tcg_op1, tcg_op2, fpst); | |
9081 | break; | |
9082 | case 0x14: /* FCMGE (reg) */ | |
9083 | gen_helper_advsimd_cge_f16(tcg_res, tcg_op1, tcg_op2, fpst); | |
9084 | break; | |
9085 | case 0x15: /* FACGE */ | |
9086 | gen_helper_advsimd_acge_f16(tcg_res, tcg_op1, tcg_op2, fpst); | |
9087 | break; | |
9088 | case 0x1a: /* FABD */ | |
9089 | gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst); | |
9090 | tcg_gen_andi_i32(tcg_res, tcg_res, 0x7fff); | |
9091 | break; | |
9092 | case 0x1c: /* FCMGT (reg) */ | |
9093 | gen_helper_advsimd_cgt_f16(tcg_res, tcg_op1, tcg_op2, fpst); | |
9094 | break; | |
9095 | case 0x1d: /* FACGT */ | |
9096 | gen_helper_advsimd_acgt_f16(tcg_res, tcg_op1, tcg_op2, fpst); | |
9097 | break; | |
9098 | default: | |
9099 | g_assert_not_reached(); | |
9100 | } | |
9101 | ||
9102 | write_fp_sreg(s, rd, tcg_res); | |
9103 | ||
9104 | ||
9105 | tcg_temp_free_i32(tcg_res); | |
9106 | tcg_temp_free_i32(tcg_op1); | |
9107 | tcg_temp_free_i32(tcg_op2); | |
9108 | tcg_temp_free_ptr(fpst); | |
9109 | } | |
9110 | ||
d9061ec3 RH |
9111 | /* AdvSIMD scalar three same extra |
9112 | * 31 30 29 28 24 23 22 21 20 16 15 14 11 10 9 5 4 0 | |
9113 | * +-----+---+-----------+------+---+------+---+--------+---+----+----+ | |
9114 | * | 0 1 | U | 1 1 1 1 0 | size | 0 | Rm | 1 | opcode | 1 | Rn | Rd | | |
9115 | * +-----+---+-----------+------+---+------+---+--------+---+----+----+ | |
9116 | */ | |
9117 | static void disas_simd_scalar_three_reg_same_extra(DisasContext *s, | |
9118 | uint32_t insn) | |
9119 | { | |
9120 | int rd = extract32(insn, 0, 5); | |
9121 | int rn = extract32(insn, 5, 5); | |
9122 | int opcode = extract32(insn, 11, 4); | |
9123 | int rm = extract32(insn, 16, 5); | |
9124 | int size = extract32(insn, 22, 2); | |
9125 | bool u = extract32(insn, 29, 1); | |
9126 | TCGv_i32 ele1, ele2, ele3; | |
9127 | TCGv_i64 res; | |
962fcbf2 | 9128 | bool feature; |
d9061ec3 RH |
9129 | |
9130 | switch (u * 16 + opcode) { | |
9131 | case 0x10: /* SQRDMLAH (vector) */ | |
9132 | case 0x11: /* SQRDMLSH (vector) */ | |
9133 | if (size != 1 && size != 2) { | |
9134 | unallocated_encoding(s); | |
9135 | return; | |
9136 | } | |
962fcbf2 | 9137 | feature = dc_isar_feature(aa64_rdm, s); |
d9061ec3 RH |
9138 | break; |
9139 | default: | |
9140 | unallocated_encoding(s); | |
9141 | return; | |
9142 | } | |
962fcbf2 | 9143 | if (!feature) { |
d9061ec3 RH |
9144 | unallocated_encoding(s); |
9145 | return; | |
9146 | } | |
9147 | if (!fp_access_check(s)) { | |
9148 | return; | |
9149 | } | |
9150 | ||
9151 | /* Do a single operation on the lowest element in the vector. | |
9152 | * We use the standard Neon helpers and rely on 0 OP 0 == 0 | |
9153 | * with no side effects for all these operations. | |
9154 | * OPTME: special-purpose helpers would avoid doing some | |
9155 | * unnecessary work in the helper for the 16 bit cases. | |
9156 | */ | |
9157 | ele1 = tcg_temp_new_i32(); | |
9158 | ele2 = tcg_temp_new_i32(); | |
9159 | ele3 = tcg_temp_new_i32(); | |
9160 | ||
9161 | read_vec_element_i32(s, ele1, rn, 0, size); | |
9162 | read_vec_element_i32(s, ele2, rm, 0, size); | |
9163 | read_vec_element_i32(s, ele3, rd, 0, size); | |
9164 | ||
9165 | switch (opcode) { | |
9166 | case 0x0: /* SQRDMLAH */ | |
9167 | if (size == 1) { | |
9168 | gen_helper_neon_qrdmlah_s16(ele3, cpu_env, ele1, ele2, ele3); | |
9169 | } else { | |
9170 | gen_helper_neon_qrdmlah_s32(ele3, cpu_env, ele1, ele2, ele3); | |
9171 | } | |
9172 | break; | |
9173 | case 0x1: /* SQRDMLSH */ | |
9174 | if (size == 1) { | |
9175 | gen_helper_neon_qrdmlsh_s16(ele3, cpu_env, ele1, ele2, ele3); | |
9176 | } else { | |
9177 | gen_helper_neon_qrdmlsh_s32(ele3, cpu_env, ele1, ele2, ele3); | |
9178 | } | |
9179 | break; | |
9180 | default: | |
9181 | g_assert_not_reached(); | |
9182 | } | |
9183 | tcg_temp_free_i32(ele1); | |
9184 | tcg_temp_free_i32(ele2); | |
9185 | ||
9186 | res = tcg_temp_new_i64(); | |
9187 | tcg_gen_extu_i32_i64(res, ele3); | |
9188 | tcg_temp_free_i32(ele3); | |
9189 | ||
9190 | write_fp_dreg(s, rd, res); | |
9191 | tcg_temp_free_i64(res); | |
9192 | } | |
9193 | ||
effa8e06 | 9194 | static void handle_2misc_64(DisasContext *s, int opcode, bool u, |
04c7c6c2 PM |
9195 | TCGv_i64 tcg_rd, TCGv_i64 tcg_rn, |
9196 | TCGv_i32 tcg_rmode, TCGv_ptr tcg_fpstatus) | |
effa8e06 PM |
9197 | { |
9198 | /* Handle 64->64 opcodes which are shared between the scalar and | |
9199 | * vector 2-reg-misc groups. We cover every integer opcode where size == 3 | |
f93d0138 | 9200 | * is valid in either group and also the double-precision fp ops. |
04c7c6c2 PM |
9201 | * The caller only need provide tcg_rmode and tcg_fpstatus if the op |
9202 | * requires them. | |
effa8e06 PM |
9203 | */ |
9204 | TCGCond cond; | |
9205 | ||
9206 | switch (opcode) { | |
b05c3068 AB |
9207 | case 0x4: /* CLS, CLZ */ |
9208 | if (u) { | |
7539a012 | 9209 | tcg_gen_clzi_i64(tcg_rd, tcg_rn, 64); |
b05c3068 | 9210 | } else { |
bc21dbcc | 9211 | tcg_gen_clrsb_i64(tcg_rd, tcg_rn); |
b05c3068 AB |
9212 | } |
9213 | break; | |
86cbc418 PM |
9214 | case 0x5: /* NOT */ |
9215 | /* This opcode is shared with CNT and RBIT but we have earlier | |
9216 | * enforced that size == 3 if and only if this is the NOT insn. | |
9217 | */ | |
9218 | tcg_gen_not_i64(tcg_rd, tcg_rn); | |
9219 | break; | |
0a79bc87 AB |
9220 | case 0x7: /* SQABS, SQNEG */ |
9221 | if (u) { | |
9222 | gen_helper_neon_qneg_s64(tcg_rd, cpu_env, tcg_rn); | |
9223 | } else { | |
9224 | gen_helper_neon_qabs_s64(tcg_rd, cpu_env, tcg_rn); | |
9225 | } | |
9226 | break; | |
effa8e06 PM |
9227 | case 0xa: /* CMLT */ |
9228 | /* 64 bit integer comparison against zero, result is | |
9229 | * test ? (2^64 - 1) : 0. We implement via setcond(!test) and | |
9230 | * subtracting 1. | |
9231 | */ | |
9232 | cond = TCG_COND_LT; | |
9233 | do_cmop: | |
9234 | tcg_gen_setcondi_i64(cond, tcg_rd, tcg_rn, 0); | |
9235 | tcg_gen_neg_i64(tcg_rd, tcg_rd); | |
9236 | break; | |
9237 | case 0x8: /* CMGT, CMGE */ | |
9238 | cond = u ? TCG_COND_GE : TCG_COND_GT; | |
9239 | goto do_cmop; | |
9240 | case 0x9: /* CMEQ, CMLE */ | |
9241 | cond = u ? TCG_COND_LE : TCG_COND_EQ; | |
9242 | goto do_cmop; | |
9243 | case 0xb: /* ABS, NEG */ | |
9244 | if (u) { | |
9245 | tcg_gen_neg_i64(tcg_rd, tcg_rn); | |
9246 | } else { | |
9247 | TCGv_i64 tcg_zero = tcg_const_i64(0); | |
9248 | tcg_gen_neg_i64(tcg_rd, tcg_rn); | |
9249 | tcg_gen_movcond_i64(TCG_COND_GT, tcg_rd, tcg_rn, tcg_zero, | |
9250 | tcg_rn, tcg_rd); | |
9251 | tcg_temp_free_i64(tcg_zero); | |
9252 | } | |
9253 | break; | |
f93d0138 PM |
9254 | case 0x2f: /* FABS */ |
9255 | gen_helper_vfp_absd(tcg_rd, tcg_rn); | |
9256 | break; | |
9257 | case 0x6f: /* FNEG */ | |
9258 | gen_helper_vfp_negd(tcg_rd, tcg_rn); | |
9259 | break; | |
f612537e AB |
9260 | case 0x7f: /* FSQRT */ |
9261 | gen_helper_vfp_sqrtd(tcg_rd, tcg_rn, cpu_env); | |
9262 | break; | |
04c7c6c2 PM |
9263 | case 0x1a: /* FCVTNS */ |
9264 | case 0x1b: /* FCVTMS */ | |
9265 | case 0x1c: /* FCVTAS */ | |
9266 | case 0x3a: /* FCVTPS */ | |
9267 | case 0x3b: /* FCVTZS */ | |
9268 | { | |
9269 | TCGv_i32 tcg_shift = tcg_const_i32(0); | |
9270 | gen_helper_vfp_tosqd(tcg_rd, tcg_rn, tcg_shift, tcg_fpstatus); | |
9271 | tcg_temp_free_i32(tcg_shift); | |
9272 | break; | |
9273 | } | |
9274 | case 0x5a: /* FCVTNU */ | |
9275 | case 0x5b: /* FCVTMU */ | |
9276 | case 0x5c: /* FCVTAU */ | |
9277 | case 0x7a: /* FCVTPU */ | |
9278 | case 0x7b: /* FCVTZU */ | |
9279 | { | |
9280 | TCGv_i32 tcg_shift = tcg_const_i32(0); | |
9281 | gen_helper_vfp_touqd(tcg_rd, tcg_rn, tcg_shift, tcg_fpstatus); | |
9282 | tcg_temp_free_i32(tcg_shift); | |
9283 | break; | |
9284 | } | |
03df01ed PM |
9285 | case 0x18: /* FRINTN */ |
9286 | case 0x19: /* FRINTM */ | |
9287 | case 0x38: /* FRINTP */ | |
9288 | case 0x39: /* FRINTZ */ | |
9289 | case 0x58: /* FRINTA */ | |
9290 | case 0x79: /* FRINTI */ | |
9291 | gen_helper_rintd(tcg_rd, tcg_rn, tcg_fpstatus); | |
9292 | break; | |
9293 | case 0x59: /* FRINTX */ | |
9294 | gen_helper_rintd_exact(tcg_rd, tcg_rn, tcg_fpstatus); | |
9295 | break; | |
effa8e06 PM |
9296 | default: |
9297 | g_assert_not_reached(); | |
9298 | } | |
9299 | } | |
9300 | ||
8908f4d1 AB |
9301 | static void handle_2misc_fcmp_zero(DisasContext *s, int opcode, |
9302 | bool is_scalar, bool is_u, bool is_q, | |
9303 | int size, int rn, int rd) | |
9304 | { | |
7d4dd1a7 | 9305 | bool is_double = (size == MO_64); |
8c6afa6a PM |
9306 | TCGv_ptr fpst; |
9307 | ||
9308 | if (!fp_access_check(s)) { | |
9309 | return; | |
9310 | } | |
9311 | ||
7d4dd1a7 | 9312 | fpst = get_fpstatus_ptr(size == MO_16); |
8908f4d1 AB |
9313 | |
9314 | if (is_double) { | |
9315 | TCGv_i64 tcg_op = tcg_temp_new_i64(); | |
9316 | TCGv_i64 tcg_zero = tcg_const_i64(0); | |
9317 | TCGv_i64 tcg_res = tcg_temp_new_i64(); | |
9318 | NeonGenTwoDoubleOPFn *genfn; | |
9319 | bool swap = false; | |
9320 | int pass; | |
9321 | ||
9322 | switch (opcode) { | |
9323 | case 0x2e: /* FCMLT (zero) */ | |
9324 | swap = true; | |
9325 | /* fallthrough */ | |
9326 | case 0x2c: /* FCMGT (zero) */ | |
9327 | genfn = gen_helper_neon_cgt_f64; | |
9328 | break; | |
9329 | case 0x2d: /* FCMEQ (zero) */ | |
9330 | genfn = gen_helper_neon_ceq_f64; | |
9331 | break; | |
9332 | case 0x6d: /* FCMLE (zero) */ | |
9333 | swap = true; | |
9334 | /* fall through */ | |
9335 | case 0x6c: /* FCMGE (zero) */ | |
9336 | genfn = gen_helper_neon_cge_f64; | |
9337 | break; | |
9338 | default: | |
9339 | g_assert_not_reached(); | |
9340 | } | |
9341 | ||
9342 | for (pass = 0; pass < (is_scalar ? 1 : 2); pass++) { | |
9343 | read_vec_element(s, tcg_op, rn, pass, MO_64); | |
9344 | if (swap) { | |
9345 | genfn(tcg_res, tcg_zero, tcg_op, fpst); | |
9346 | } else { | |
9347 | genfn(tcg_res, tcg_op, tcg_zero, fpst); | |
9348 | } | |
9349 | write_vec_element(s, tcg_res, rd, pass, MO_64); | |
9350 | } | |
8908f4d1 AB |
9351 | tcg_temp_free_i64(tcg_res); |
9352 | tcg_temp_free_i64(tcg_zero); | |
9353 | tcg_temp_free_i64(tcg_op); | |
4ff55bcb RH |
9354 | |
9355 | clear_vec_high(s, !is_scalar, rd); | |
8908f4d1 AB |
9356 | } else { |
9357 | TCGv_i32 tcg_op = tcg_temp_new_i32(); | |
9358 | TCGv_i32 tcg_zero = tcg_const_i32(0); | |
9359 | TCGv_i32 tcg_res = tcg_temp_new_i32(); | |
9360 | NeonGenTwoSingleOPFn *genfn; | |
9361 | bool swap = false; | |
9362 | int pass, maxpasses; | |
9363 | ||
7d4dd1a7 AB |
9364 | if (size == MO_16) { |
9365 | switch (opcode) { | |
9366 | case 0x2e: /* FCMLT (zero) */ | |
9367 | swap = true; | |
9368 | /* fall through */ | |
9369 | case 0x2c: /* FCMGT (zero) */ | |
9370 | genfn = gen_helper_advsimd_cgt_f16; | |
9371 | break; | |
9372 | case 0x2d: /* FCMEQ (zero) */ | |
9373 | genfn = gen_helper_advsimd_ceq_f16; | |
9374 | break; | |
9375 | case 0x6d: /* FCMLE (zero) */ | |
9376 | swap = true; | |
9377 | /* fall through */ | |
9378 | case 0x6c: /* FCMGE (zero) */ | |
9379 | genfn = gen_helper_advsimd_cge_f16; | |
9380 | break; | |
9381 | default: | |
9382 | g_assert_not_reached(); | |
9383 | } | |
9384 | } else { | |
9385 | switch (opcode) { | |
9386 | case 0x2e: /* FCMLT (zero) */ | |
9387 | swap = true; | |
9388 | /* fall through */ | |
9389 | case 0x2c: /* FCMGT (zero) */ | |
9390 | genfn = gen_helper_neon_cgt_f32; | |
9391 | break; | |
9392 | case 0x2d: /* FCMEQ (zero) */ | |
9393 | genfn = gen_helper_neon_ceq_f32; | |
9394 | break; | |
9395 | case 0x6d: /* FCMLE (zero) */ | |
9396 | swap = true; | |
9397 | /* fall through */ | |
9398 | case 0x6c: /* FCMGE (zero) */ | |
9399 | genfn = gen_helper_neon_cge_f32; | |
9400 | break; | |
9401 | default: | |
9402 | g_assert_not_reached(); | |
9403 | } | |
8908f4d1 AB |
9404 | } |
9405 | ||
9406 | if (is_scalar) { | |
9407 | maxpasses = 1; | |
9408 | } else { | |
7d4dd1a7 AB |
9409 | int vector_size = 8 << is_q; |
9410 | maxpasses = vector_size >> size; | |
8908f4d1 AB |
9411 | } |
9412 | ||
9413 | for (pass = 0; pass < maxpasses; pass++) { | |
7d4dd1a7 | 9414 | read_vec_element_i32(s, tcg_op, rn, pass, size); |
8908f4d1 AB |
9415 | if (swap) { |
9416 | genfn(tcg_res, tcg_zero, tcg_op, fpst); | |
9417 | } else { | |
9418 | genfn(tcg_res, tcg_op, tcg_zero, fpst); | |
9419 | } | |
9420 | if (is_scalar) { | |
9421 | write_fp_sreg(s, rd, tcg_res); | |
9422 | } else { | |
7d4dd1a7 | 9423 | write_vec_element_i32(s, tcg_res, rd, pass, size); |
8908f4d1 AB |
9424 | } |
9425 | } | |
9426 | tcg_temp_free_i32(tcg_res); | |
9427 | tcg_temp_free_i32(tcg_zero); | |
9428 | tcg_temp_free_i32(tcg_op); | |
4ff55bcb RH |
9429 | if (!is_scalar) { |
9430 | clear_vec_high(s, is_q, rd); | |
8908f4d1 AB |
9431 | } |
9432 | } | |
9433 | ||
9434 | tcg_temp_free_ptr(fpst); | |
9435 | } | |
9436 | ||
8f0c6758 AB |
9437 | static void handle_2misc_reciprocal(DisasContext *s, int opcode, |
9438 | bool is_scalar, bool is_u, bool is_q, | |
9439 | int size, int rn, int rd) | |
9440 | { | |
9441 | bool is_double = (size == 3); | |
d81ce0ef | 9442 | TCGv_ptr fpst = get_fpstatus_ptr(false); |
8f0c6758 AB |
9443 | |
9444 | if (is_double) { | |
9445 | TCGv_i64 tcg_op = tcg_temp_new_i64(); | |
9446 | TCGv_i64 tcg_res = tcg_temp_new_i64(); | |
9447 | int pass; | |
9448 | ||
9449 | for (pass = 0; pass < (is_scalar ? 1 : 2); pass++) { | |
9450 | read_vec_element(s, tcg_op, rn, pass, MO_64); | |
9451 | switch (opcode) { | |
b6d4443a AB |
9452 | case 0x3d: /* FRECPE */ |
9453 | gen_helper_recpe_f64(tcg_res, tcg_op, fpst); | |
9454 | break; | |
8f0c6758 AB |
9455 | case 0x3f: /* FRECPX */ |
9456 | gen_helper_frecpx_f64(tcg_res, tcg_op, fpst); | |
9457 | break; | |
c2fb418e AB |
9458 | case 0x7d: /* FRSQRTE */ |
9459 | gen_helper_rsqrte_f64(tcg_res, tcg_op, fpst); | |
9460 | break; | |
8f0c6758 AB |
9461 | default: |
9462 | g_assert_not_reached(); | |
9463 | } | |
9464 | write_vec_element(s, tcg_res, rd, pass, MO_64); | |
9465 | } | |
8f0c6758 AB |
9466 | tcg_temp_free_i64(tcg_res); |
9467 | tcg_temp_free_i64(tcg_op); | |
4ff55bcb | 9468 | clear_vec_high(s, !is_scalar, rd); |
8f0c6758 AB |
9469 | } else { |
9470 | TCGv_i32 tcg_op = tcg_temp_new_i32(); | |
9471 | TCGv_i32 tcg_res = tcg_temp_new_i32(); | |
9472 | int pass, maxpasses; | |
9473 | ||
9474 | if (is_scalar) { | |
9475 | maxpasses = 1; | |
9476 | } else { | |
9477 | maxpasses = is_q ? 4 : 2; | |
9478 | } | |
9479 | ||
9480 | for (pass = 0; pass < maxpasses; pass++) { | |
9481 | read_vec_element_i32(s, tcg_op, rn, pass, MO_32); | |
9482 | ||
9483 | switch (opcode) { | |
b6d4443a AB |
9484 | case 0x3c: /* URECPE */ |
9485 | gen_helper_recpe_u32(tcg_res, tcg_op, fpst); | |
9486 | break; | |
9487 | case 0x3d: /* FRECPE */ | |
9488 | gen_helper_recpe_f32(tcg_res, tcg_op, fpst); | |
9489 | break; | |
8f0c6758 AB |
9490 | case 0x3f: /* FRECPX */ |
9491 | gen_helper_frecpx_f32(tcg_res, tcg_op, fpst); | |
9492 | break; | |
c2fb418e AB |
9493 | case 0x7d: /* FRSQRTE */ |
9494 | gen_helper_rsqrte_f32(tcg_res, tcg_op, fpst); | |
9495 | break; | |
8f0c6758 AB |
9496 | default: |
9497 | g_assert_not_reached(); | |
9498 | } | |
9499 | ||
9500 | if (is_scalar) { | |
9501 | write_fp_sreg(s, rd, tcg_res); | |
9502 | } else { | |
9503 | write_vec_element_i32(s, tcg_res, rd, pass, MO_32); | |
9504 | } | |
9505 | } | |
9506 | tcg_temp_free_i32(tcg_res); | |
9507 | tcg_temp_free_i32(tcg_op); | |
4ff55bcb RH |
9508 | if (!is_scalar) { |
9509 | clear_vec_high(s, is_q, rd); | |
8f0c6758 AB |
9510 | } |
9511 | } | |
9512 | tcg_temp_free_ptr(fpst); | |
9513 | } | |
9514 | ||
5201c136 AB |
9515 | static void handle_2misc_narrow(DisasContext *s, bool scalar, |
9516 | int opcode, bool u, bool is_q, | |
8b092ca9 AB |
9517 | int size, int rn, int rd) |
9518 | { | |
9519 | /* Handle 2-reg-misc ops which are narrowing (so each 2*size element | |
9520 | * in the source becomes a size element in the destination). | |
9521 | */ | |
9522 | int pass; | |
9523 | TCGv_i32 tcg_res[2]; | |
9524 | int destelt = is_q ? 2 : 0; | |
5201c136 | 9525 | int passes = scalar ? 1 : 2; |
8b092ca9 | 9526 | |
5201c136 AB |
9527 | if (scalar) { |
9528 | tcg_res[1] = tcg_const_i32(0); | |
9529 | } | |
9530 | ||
9531 | for (pass = 0; pass < passes; pass++) { | |
8b092ca9 AB |
9532 | TCGv_i64 tcg_op = tcg_temp_new_i64(); |
9533 | NeonGenNarrowFn *genfn = NULL; | |
9534 | NeonGenNarrowEnvFn *genenvfn = NULL; | |
9535 | ||
5201c136 AB |
9536 | if (scalar) { |
9537 | read_vec_element(s, tcg_op, rn, pass, size + 1); | |
9538 | } else { | |
9539 | read_vec_element(s, tcg_op, rn, pass, MO_64); | |
9540 | } | |
8b092ca9 AB |
9541 | tcg_res[pass] = tcg_temp_new_i32(); |
9542 | ||
9543 | switch (opcode) { | |
9544 | case 0x12: /* XTN, SQXTUN */ | |
9545 | { | |
9546 | static NeonGenNarrowFn * const xtnfns[3] = { | |
9547 | gen_helper_neon_narrow_u8, | |
9548 | gen_helper_neon_narrow_u16, | |
ecc7b3aa | 9549 | tcg_gen_extrl_i64_i32, |
8b092ca9 AB |
9550 | }; |
9551 | static NeonGenNarrowEnvFn * const sqxtunfns[3] = { | |
9552 | gen_helper_neon_unarrow_sat8, | |
9553 | gen_helper_neon_unarrow_sat16, | |
9554 | gen_helper_neon_unarrow_sat32, | |
9555 | }; | |
9556 | if (u) { | |
9557 | genenvfn = sqxtunfns[size]; | |
9558 | } else { | |
9559 | genfn = xtnfns[size]; | |
9560 | } | |
9561 | break; | |
9562 | } | |
9563 | case 0x14: /* SQXTN, UQXTN */ | |
9564 | { | |
9565 | static NeonGenNarrowEnvFn * const fns[3][2] = { | |
9566 | { gen_helper_neon_narrow_sat_s8, | |
9567 | gen_helper_neon_narrow_sat_u8 }, | |
9568 | { gen_helper_neon_narrow_sat_s16, | |
9569 | gen_helper_neon_narrow_sat_u16 }, | |
9570 | { gen_helper_neon_narrow_sat_s32, | |
9571 | gen_helper_neon_narrow_sat_u32 }, | |
9572 | }; | |
9573 | genenvfn = fns[size][u]; | |
9574 | break; | |
9575 | } | |
9576 | case 0x16: /* FCVTN, FCVTN2 */ | |
9577 | /* 32 bit to 16 bit or 64 bit to 32 bit float conversion */ | |
9578 | if (size == 2) { | |
9579 | gen_helper_vfp_fcvtsd(tcg_res[pass], tcg_op, cpu_env); | |
9580 | } else { | |
9581 | TCGv_i32 tcg_lo = tcg_temp_new_i32(); | |
9582 | TCGv_i32 tcg_hi = tcg_temp_new_i32(); | |
486624fc AB |
9583 | TCGv_ptr fpst = get_fpstatus_ptr(false); |
9584 | TCGv_i32 ahp = get_ahp_flag(); | |
9585 | ||
7cb36e18 | 9586 | tcg_gen_extr_i64_i32(tcg_lo, tcg_hi, tcg_op); |
486624fc AB |
9587 | gen_helper_vfp_fcvt_f32_to_f16(tcg_lo, tcg_lo, fpst, ahp); |
9588 | gen_helper_vfp_fcvt_f32_to_f16(tcg_hi, tcg_hi, fpst, ahp); | |
8b092ca9 AB |
9589 | tcg_gen_deposit_i32(tcg_res[pass], tcg_lo, tcg_hi, 16, 16); |
9590 | tcg_temp_free_i32(tcg_lo); | |
9591 | tcg_temp_free_i32(tcg_hi); | |
486624fc AB |
9592 | tcg_temp_free_ptr(fpst); |
9593 | tcg_temp_free_i32(ahp); | |
8b092ca9 AB |
9594 | } |
9595 | break; | |
5553955e PM |
9596 | case 0x56: /* FCVTXN, FCVTXN2 */ |
9597 | /* 64 bit to 32 bit float conversion | |
9598 | * with von Neumann rounding (round to odd) | |
9599 | */ | |
9600 | assert(size == 2); | |
9601 | gen_helper_fcvtx_f64_to_f32(tcg_res[pass], tcg_op, cpu_env); | |
9602 | break; | |
8b092ca9 AB |
9603 | default: |
9604 | g_assert_not_reached(); | |
9605 | } | |
9606 | ||
9607 | if (genfn) { | |
9608 | genfn(tcg_res[pass], tcg_op); | |
9609 | } else if (genenvfn) { | |
9610 | genenvfn(tcg_res[pass], cpu_env, tcg_op); | |
9611 | } | |
9612 | ||
9613 | tcg_temp_free_i64(tcg_op); | |
9614 | } | |
9615 | ||
9616 | for (pass = 0; pass < 2; pass++) { | |
9617 | write_vec_element_i32(s, tcg_res[pass], rd, destelt + pass, MO_32); | |
9618 | tcg_temp_free_i32(tcg_res[pass]); | |
9619 | } | |
4ff55bcb | 9620 | clear_vec_high(s, is_q, rd); |
8b092ca9 AB |
9621 | } |
9622 | ||
09e03735 AB |
9623 | /* Remaining saturating accumulating ops */ |
9624 | static void handle_2misc_satacc(DisasContext *s, bool is_scalar, bool is_u, | |
9625 | bool is_q, int size, int rn, int rd) | |
9626 | { | |
9627 | bool is_double = (size == 3); | |
9628 | ||
9629 | if (is_double) { | |
9630 | TCGv_i64 tcg_rn = tcg_temp_new_i64(); | |
9631 | TCGv_i64 tcg_rd = tcg_temp_new_i64(); | |
9632 | int pass; | |
9633 | ||
9634 | for (pass = 0; pass < (is_scalar ? 1 : 2); pass++) { | |
9635 | read_vec_element(s, tcg_rn, rn, pass, MO_64); | |
9636 | read_vec_element(s, tcg_rd, rd, pass, MO_64); | |
9637 | ||
9638 | if (is_u) { /* USQADD */ | |
9639 | gen_helper_neon_uqadd_s64(tcg_rd, cpu_env, tcg_rn, tcg_rd); | |
9640 | } else { /* SUQADD */ | |
9641 | gen_helper_neon_sqadd_u64(tcg_rd, cpu_env, tcg_rn, tcg_rd); | |
9642 | } | |
9643 | write_vec_element(s, tcg_rd, rd, pass, MO_64); | |
9644 | } | |
09e03735 AB |
9645 | tcg_temp_free_i64(tcg_rd); |
9646 | tcg_temp_free_i64(tcg_rn); | |
4ff55bcb | 9647 | clear_vec_high(s, !is_scalar, rd); |
09e03735 AB |
9648 | } else { |
9649 | TCGv_i32 tcg_rn = tcg_temp_new_i32(); | |
9650 | TCGv_i32 tcg_rd = tcg_temp_new_i32(); | |
9651 | int pass, maxpasses; | |
9652 | ||
9653 | if (is_scalar) { | |
9654 | maxpasses = 1; | |
9655 | } else { | |
9656 | maxpasses = is_q ? 4 : 2; | |
9657 | } | |
9658 | ||
9659 | for (pass = 0; pass < maxpasses; pass++) { | |
9660 | if (is_scalar) { | |
9661 | read_vec_element_i32(s, tcg_rn, rn, pass, size); | |
9662 | read_vec_element_i32(s, tcg_rd, rd, pass, size); | |
9663 | } else { | |
9664 | read_vec_element_i32(s, tcg_rn, rn, pass, MO_32); | |
9665 | read_vec_element_i32(s, tcg_rd, rd, pass, MO_32); | |
9666 | } | |
9667 | ||
9668 | if (is_u) { /* USQADD */ | |
9669 | switch (size) { | |
9670 | case 0: | |
9671 | gen_helper_neon_uqadd_s8(tcg_rd, cpu_env, tcg_rn, tcg_rd); | |
9672 | break; | |
9673 | case 1: | |
9674 | gen_helper_neon_uqadd_s16(tcg_rd, cpu_env, tcg_rn, tcg_rd); | |
9675 | break; | |
9676 | case 2: | |
9677 | gen_helper_neon_uqadd_s32(tcg_rd, cpu_env, tcg_rn, tcg_rd); | |
9678 | break; | |
9679 | default: | |
9680 | g_assert_not_reached(); | |
9681 | } | |
9682 | } else { /* SUQADD */ | |
9683 | switch (size) { | |
9684 | case 0: | |
9685 | gen_helper_neon_sqadd_u8(tcg_rd, cpu_env, tcg_rn, tcg_rd); | |
9686 | break; | |
9687 | case 1: | |
9688 | gen_helper_neon_sqadd_u16(tcg_rd, cpu_env, tcg_rn, tcg_rd); | |
9689 | break; | |
9690 | case 2: | |
9691 | gen_helper_neon_sqadd_u32(tcg_rd, cpu_env, tcg_rn, tcg_rd); | |
9692 | break; | |
9693 | default: | |
9694 | g_assert_not_reached(); | |
9695 | } | |
9696 | } | |
9697 | ||
9698 | if (is_scalar) { | |
9699 | TCGv_i64 tcg_zero = tcg_const_i64(0); | |
9700 | write_vec_element(s, tcg_zero, rd, 0, MO_64); | |
9701 | tcg_temp_free_i64(tcg_zero); | |
9702 | } | |
9703 | write_vec_element_i32(s, tcg_rd, rd, pass, MO_32); | |
9704 | } | |
09e03735 AB |
9705 | tcg_temp_free_i32(tcg_rd); |
9706 | tcg_temp_free_i32(tcg_rn); | |
4ff55bcb | 9707 | clear_vec_high(s, is_q, rd); |
09e03735 AB |
9708 | } |
9709 | } | |
9710 | ||
4ce31af4 | 9711 | /* AdvSIMD scalar two reg misc |
384b26fb AB |
9712 | * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0 |
9713 | * +-----+---+-----------+------+-----------+--------+-----+------+------+ | |
9714 | * | 0 1 | U | 1 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd | | |
9715 | * +-----+---+-----------+------+-----------+--------+-----+------+------+ | |
9716 | */ | |
9717 | static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn) | |
9718 | { | |
effa8e06 PM |
9719 | int rd = extract32(insn, 0, 5); |
9720 | int rn = extract32(insn, 5, 5); | |
9721 | int opcode = extract32(insn, 12, 5); | |
9722 | int size = extract32(insn, 22, 2); | |
9723 | bool u = extract32(insn, 29, 1); | |
04c7c6c2 PM |
9724 | bool is_fcvt = false; |
9725 | int rmode; | |
9726 | TCGv_i32 tcg_rmode; | |
9727 | TCGv_ptr tcg_fpstatus; | |
effa8e06 PM |
9728 | |
9729 | switch (opcode) { | |
09e03735 | 9730 | case 0x3: /* USQADD / SUQADD*/ |
8c6afa6a PM |
9731 | if (!fp_access_check(s)) { |
9732 | return; | |
9733 | } | |
09e03735 AB |
9734 | handle_2misc_satacc(s, true, u, false, size, rn, rd); |
9735 | return; | |
0a79bc87 AB |
9736 | case 0x7: /* SQABS / SQNEG */ |
9737 | break; | |
effa8e06 PM |
9738 | case 0xa: /* CMLT */ |
9739 | if (u) { | |
9740 | unallocated_encoding(s); | |
9741 | return; | |
9742 | } | |
9743 | /* fall through */ | |
9744 | case 0x8: /* CMGT, CMGE */ | |
9745 | case 0x9: /* CMEQ, CMLE */ | |
9746 | case 0xb: /* ABS, NEG */ | |
9747 | if (size != 3) { | |
9748 | unallocated_encoding(s); | |
9749 | return; | |
9750 | } | |
9751 | break; | |
5201c136 | 9752 | case 0x12: /* SQXTUN */ |
e44a90c5 | 9753 | if (!u) { |
5201c136 AB |
9754 | unallocated_encoding(s); |
9755 | return; | |
9756 | } | |
9757 | /* fall through */ | |
9758 | case 0x14: /* SQXTN, UQXTN */ | |
9759 | if (size == 3) { | |
9760 | unallocated_encoding(s); | |
9761 | return; | |
9762 | } | |
8c6afa6a PM |
9763 | if (!fp_access_check(s)) { |
9764 | return; | |
9765 | } | |
5201c136 AB |
9766 | handle_2misc_narrow(s, true, opcode, u, false, size, rn, rd); |
9767 | return; | |
8908f4d1 AB |
9768 | case 0xc ... 0xf: |
9769 | case 0x16 ... 0x1d: | |
9770 | case 0x1f: | |
9771 | /* Floating point: U, size[1] and opcode indicate operation; | |
9772 | * size[0] indicates single or double precision. | |
9773 | */ | |
9774 | opcode |= (extract32(size, 1, 1) << 5) | (u << 6); | |
9775 | size = extract32(size, 0, 1) ? 3 : 2; | |
9776 | switch (opcode) { | |
9777 | case 0x2c: /* FCMGT (zero) */ | |
9778 | case 0x2d: /* FCMEQ (zero) */ | |
9779 | case 0x2e: /* FCMLT (zero) */ | |
9780 | case 0x6c: /* FCMGE (zero) */ | |
9781 | case 0x6d: /* FCMLE (zero) */ | |
9782 | handle_2misc_fcmp_zero(s, opcode, true, u, true, size, rn, rd); | |
9783 | return; | |
10113b69 AB |
9784 | case 0x1d: /* SCVTF */ |
9785 | case 0x5d: /* UCVTF */ | |
9786 | { | |
9787 | bool is_signed = (opcode == 0x1d); | |
8c6afa6a PM |
9788 | if (!fp_access_check(s)) { |
9789 | return; | |
9790 | } | |
10113b69 AB |
9791 | handle_simd_intfp_conv(s, rd, rn, 1, is_signed, 0, size); |
9792 | return; | |
9793 | } | |
b6d4443a | 9794 | case 0x3d: /* FRECPE */ |
8f0c6758 | 9795 | case 0x3f: /* FRECPX */ |
c2fb418e | 9796 | case 0x7d: /* FRSQRTE */ |
8c6afa6a PM |
9797 | if (!fp_access_check(s)) { |
9798 | return; | |
9799 | } | |
8f0c6758 AB |
9800 | handle_2misc_reciprocal(s, opcode, true, u, true, size, rn, rd); |
9801 | return; | |
8908f4d1 AB |
9802 | case 0x1a: /* FCVTNS */ |
9803 | case 0x1b: /* FCVTMS */ | |
8908f4d1 AB |
9804 | case 0x3a: /* FCVTPS */ |
9805 | case 0x3b: /* FCVTZS */ | |
8908f4d1 AB |
9806 | case 0x5a: /* FCVTNU */ |
9807 | case 0x5b: /* FCVTMU */ | |
8908f4d1 AB |
9808 | case 0x7a: /* FCVTPU */ |
9809 | case 0x7b: /* FCVTZU */ | |
04c7c6c2 PM |
9810 | is_fcvt = true; |
9811 | rmode = extract32(opcode, 5, 1) | (extract32(opcode, 0, 1) << 1); | |
9812 | break; | |
9813 | case 0x1c: /* FCVTAS */ | |
9814 | case 0x5c: /* FCVTAU */ | |
9815 | /* TIEAWAY doesn't fit in the usual rounding mode encoding */ | |
9816 | is_fcvt = true; | |
9817 | rmode = FPROUNDING_TIEAWAY; | |
9818 | break; | |
04c7c6c2 | 9819 | case 0x56: /* FCVTXN, FCVTXN2 */ |
5553955e PM |
9820 | if (size == 2) { |
9821 | unallocated_encoding(s); | |
9822 | return; | |
9823 | } | |
8c6afa6a PM |
9824 | if (!fp_access_check(s)) { |
9825 | return; | |
9826 | } | |
5553955e PM |
9827 | handle_2misc_narrow(s, true, opcode, u, false, size - 1, rn, rd); |
9828 | return; | |
8908f4d1 AB |
9829 | default: |
9830 | unallocated_encoding(s); | |
9831 | return; | |
9832 | } | |
9833 | break; | |
effa8e06 | 9834 | default: |
09e03735 | 9835 | unallocated_encoding(s); |
effa8e06 PM |
9836 | return; |
9837 | } | |
9838 | ||
8c6afa6a PM |
9839 | if (!fp_access_check(s)) { |
9840 | return; | |
9841 | } | |
9842 | ||
04c7c6c2 PM |
9843 | if (is_fcvt) { |
9844 | tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode)); | |
d81ce0ef | 9845 | tcg_fpstatus = get_fpstatus_ptr(false); |
9b049916 | 9846 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); |
04c7c6c2 | 9847 | } else { |
f764718d RH |
9848 | tcg_rmode = NULL; |
9849 | tcg_fpstatus = NULL; | |
04c7c6c2 PM |
9850 | } |
9851 | ||
effa8e06 PM |
9852 | if (size == 3) { |
9853 | TCGv_i64 tcg_rn = read_fp_dreg(s, rn); | |
9854 | TCGv_i64 tcg_rd = tcg_temp_new_i64(); | |
9855 | ||
04c7c6c2 | 9856 | handle_2misc_64(s, opcode, u, tcg_rd, tcg_rn, tcg_rmode, tcg_fpstatus); |
effa8e06 PM |
9857 | write_fp_dreg(s, rd, tcg_rd); |
9858 | tcg_temp_free_i64(tcg_rd); | |
9859 | tcg_temp_free_i64(tcg_rn); | |
0a79bc87 AB |
9860 | } else { |
9861 | TCGv_i32 tcg_rn = tcg_temp_new_i32(); | |
04c7c6c2 PM |
9862 | TCGv_i32 tcg_rd = tcg_temp_new_i32(); |
9863 | ||
0a79bc87 AB |
9864 | read_vec_element_i32(s, tcg_rn, rn, 0, size); |
9865 | ||
04c7c6c2 | 9866 | switch (opcode) { |
0a79bc87 AB |
9867 | case 0x7: /* SQABS, SQNEG */ |
9868 | { | |
9869 | NeonGenOneOpEnvFn *genfn; | |
9870 | static NeonGenOneOpEnvFn * const fns[3][2] = { | |
9871 | { gen_helper_neon_qabs_s8, gen_helper_neon_qneg_s8 }, | |
9872 | { gen_helper_neon_qabs_s16, gen_helper_neon_qneg_s16 }, | |
9873 | { gen_helper_neon_qabs_s32, gen_helper_neon_qneg_s32 }, | |
9874 | }; | |
9875 | genfn = fns[size][u]; | |
9876 | genfn(tcg_rd, cpu_env, tcg_rn); | |
9877 | break; | |
9878 | } | |
04c7c6c2 PM |
9879 | case 0x1a: /* FCVTNS */ |
9880 | case 0x1b: /* FCVTMS */ | |
9881 | case 0x1c: /* FCVTAS */ | |
9882 | case 0x3a: /* FCVTPS */ | |
9883 | case 0x3b: /* FCVTZS */ | |
9884 | { | |
9885 | TCGv_i32 tcg_shift = tcg_const_i32(0); | |
9886 | gen_helper_vfp_tosls(tcg_rd, tcg_rn, tcg_shift, tcg_fpstatus); | |
9887 | tcg_temp_free_i32(tcg_shift); | |
9888 | break; | |
9889 | } | |
9890 | case 0x5a: /* FCVTNU */ | |
9891 | case 0x5b: /* FCVTMU */ | |
9892 | case 0x5c: /* FCVTAU */ | |
9893 | case 0x7a: /* FCVTPU */ | |
9894 | case 0x7b: /* FCVTZU */ | |
9895 | { | |
9896 | TCGv_i32 tcg_shift = tcg_const_i32(0); | |
9897 | gen_helper_vfp_touls(tcg_rd, tcg_rn, tcg_shift, tcg_fpstatus); | |
9898 | tcg_temp_free_i32(tcg_shift); | |
9899 | break; | |
9900 | } | |
9901 | default: | |
9902 | g_assert_not_reached(); | |
9903 | } | |
9904 | ||
9905 | write_fp_sreg(s, rd, tcg_rd); | |
9906 | tcg_temp_free_i32(tcg_rd); | |
9907 | tcg_temp_free_i32(tcg_rn); | |
effa8e06 | 9908 | } |
04c7c6c2 PM |
9909 | |
9910 | if (is_fcvt) { | |
9b049916 | 9911 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); |
04c7c6c2 PM |
9912 | tcg_temp_free_i32(tcg_rmode); |
9913 | tcg_temp_free_ptr(tcg_fpstatus); | |
9914 | } | |
384b26fb AB |
9915 | } |
9916 | ||
4d1cef84 AB |
9917 | /* SSHR[RA]/USHR[RA] - Vector shift right (optional rounding/accumulate) */ |
9918 | static void handle_vec_simd_shri(DisasContext *s, bool is_q, bool is_u, | |
9919 | int immh, int immb, int opcode, int rn, int rd) | |
9920 | { | |
9921 | int size = 32 - clz32(immh) - 1; | |
9922 | int immhb = immh << 3 | immb; | |
9923 | int shift = 2 * (8 << size) - immhb; | |
9924 | bool accumulate = false; | |
4d1cef84 AB |
9925 | int dsize = is_q ? 128 : 64; |
9926 | int esize = 8 << size; | |
9927 | int elements = dsize/esize; | |
9928 | TCGMemOp memop = size | (is_u ? 0 : MO_SIGN); | |
9929 | TCGv_i64 tcg_rn = new_tmp_a64(s); | |
9930 | TCGv_i64 tcg_rd = new_tmp_a64(s); | |
9931 | TCGv_i64 tcg_round; | |
cdb45a60 | 9932 | uint64_t round_const; |
4d1cef84 AB |
9933 | int i; |
9934 | ||
9935 | if (extract32(immh, 3, 1) && !is_q) { | |
9936 | unallocated_encoding(s); | |
9937 | return; | |
9938 | } | |
8dae4697 | 9939 | tcg_debug_assert(size <= 3); |
4d1cef84 | 9940 | |
8c6afa6a PM |
9941 | if (!fp_access_check(s)) { |
9942 | return; | |
9943 | } | |
9944 | ||
4d1cef84 AB |
9945 | switch (opcode) { |
9946 | case 0x02: /* SSRA / USRA (accumulate) */ | |
cdb45a60 RH |
9947 | if (is_u) { |
9948 | /* Shift count same as element size produces zero to add. */ | |
9949 | if (shift == 8 << size) { | |
9950 | goto done; | |
9951 | } | |
9952 | gen_gvec_op2i(s, is_q, rd, rn, shift, &usra_op[size]); | |
9953 | } else { | |
9954 | /* Shift count same as element size produces all sign to add. */ | |
9955 | if (shift == 8 << size) { | |
9956 | shift -= 1; | |
9957 | } | |
9958 | gen_gvec_op2i(s, is_q, rd, rn, shift, &ssra_op[size]); | |
9959 | } | |
9960 | return; | |
9961 | case 0x08: /* SRI */ | |
9962 | /* Shift count same as element size is valid but does nothing. */ | |
9963 | if (shift == 8 << size) { | |
9964 | goto done; | |
9965 | } | |
9966 | gen_gvec_op2i(s, is_q, rd, rn, shift, &sri_op[size]); | |
9967 | return; | |
9968 | ||
9969 | case 0x00: /* SSHR / USHR */ | |
9970 | if (is_u) { | |
9971 | if (shift == 8 << size) { | |
9972 | /* Shift count the same size as element size produces zero. */ | |
9973 | tcg_gen_gvec_dup8i(vec_full_reg_offset(s, rd), | |
9974 | is_q ? 16 : 8, vec_full_reg_size(s), 0); | |
9975 | } else { | |
9976 | gen_gvec_fn2i(s, is_q, rd, rn, shift, tcg_gen_gvec_shri, size); | |
9977 | } | |
9978 | } else { | |
9979 | /* Shift count the same size as element size produces all sign. */ | |
9980 | if (shift == 8 << size) { | |
9981 | shift -= 1; | |
9982 | } | |
9983 | gen_gvec_fn2i(s, is_q, rd, rn, shift, tcg_gen_gvec_sari, size); | |
9984 | } | |
9985 | return; | |
9986 | ||
4d1cef84 | 9987 | case 0x04: /* SRSHR / URSHR (rounding) */ |
4d1cef84 AB |
9988 | break; |
9989 | case 0x06: /* SRSRA / URSRA (accum + rounding) */ | |
cdb45a60 | 9990 | accumulate = true; |
37a706ad | 9991 | break; |
cdb45a60 RH |
9992 | default: |
9993 | g_assert_not_reached(); | |
4d1cef84 AB |
9994 | } |
9995 | ||
cdb45a60 RH |
9996 | round_const = 1ULL << (shift - 1); |
9997 | tcg_round = tcg_const_i64(round_const); | |
4d1cef84 AB |
9998 | |
9999 | for (i = 0; i < elements; i++) { | |
10000 | read_vec_element(s, tcg_rn, rn, i, memop); | |
cdb45a60 | 10001 | if (accumulate) { |
4d1cef84 AB |
10002 | read_vec_element(s, tcg_rd, rd, i, memop); |
10003 | } | |
10004 | ||
cdb45a60 RH |
10005 | handle_shri_with_rndacc(tcg_rd, tcg_rn, tcg_round, |
10006 | accumulate, is_u, size, shift); | |
4d1cef84 AB |
10007 | |
10008 | write_vec_element(s, tcg_rd, rd, i, size); | |
10009 | } | |
cdb45a60 | 10010 | tcg_temp_free_i64(tcg_round); |
4d1cef84 | 10011 | |
cdb45a60 | 10012 | done: |
4ff55bcb | 10013 | clear_vec_high(s, is_q, rd); |
cdb45a60 | 10014 | } |
4d1cef84 | 10015 | |
4d1cef84 AB |
10016 | /* SHL/SLI - Vector shift left */ |
10017 | static void handle_vec_simd_shli(DisasContext *s, bool is_q, bool insert, | |
cdb45a60 | 10018 | int immh, int immb, int opcode, int rn, int rd) |
4d1cef84 AB |
10019 | { |
10020 | int size = 32 - clz32(immh) - 1; | |
10021 | int immhb = immh << 3 | immb; | |
10022 | int shift = immhb - (8 << size); | |
4d1cef84 | 10023 | |
f6c98f91 PM |
10024 | /* Range of size is limited by decode: immh is a non-zero 4 bit field */ |
10025 | assert(size >= 0 && size <= 3); | |
4d1cef84 | 10026 | |
f6c98f91 | 10027 | if (extract32(immh, 3, 1) && !is_q) { |
4d1cef84 AB |
10028 | unallocated_encoding(s); |
10029 | return; | |
10030 | } | |
10031 | ||
8c6afa6a PM |
10032 | if (!fp_access_check(s)) { |
10033 | return; | |
10034 | } | |
10035 | ||
cdb45a60 | 10036 | if (insert) { |
f3cd8218 | 10037 | gen_gvec_op2i(s, is_q, rd, rn, shift, &sli_op[size]); |
cdb45a60 RH |
10038 | } else { |
10039 | gen_gvec_fn2i(s, is_q, rd, rn, shift, tcg_gen_gvec_shli, size); | |
4d1cef84 AB |
10040 | } |
10041 | } | |
10042 | ||
10043 | /* USHLL/SHLL - Vector shift left with widening */ | |
10044 | static void handle_vec_simd_wshli(DisasContext *s, bool is_q, bool is_u, | |
10045 | int immh, int immb, int opcode, int rn, int rd) | |
10046 | { | |
10047 | int size = 32 - clz32(immh) - 1; | |
10048 | int immhb = immh << 3 | immb; | |
10049 | int shift = immhb - (8 << size); | |
10050 | int dsize = 64; | |
10051 | int esize = 8 << size; | |
10052 | int elements = dsize/esize; | |
10053 | TCGv_i64 tcg_rn = new_tmp_a64(s); | |
10054 | TCGv_i64 tcg_rd = new_tmp_a64(s); | |
10055 | int i; | |
10056 | ||
10057 | if (size >= 3) { | |
10058 | unallocated_encoding(s); | |
10059 | return; | |
10060 | } | |
10061 | ||
8c6afa6a PM |
10062 | if (!fp_access_check(s)) { |
10063 | return; | |
10064 | } | |
10065 | ||
4d1cef84 AB |
10066 | /* For the LL variants the store is larger than the load, |
10067 | * so if rd == rn we would overwrite parts of our input. | |
10068 | * So load everything right now and use shifts in the main loop. | |
10069 | */ | |
10070 | read_vec_element(s, tcg_rn, rn, is_q ? 1 : 0, MO_64); | |
10071 | ||
10072 | for (i = 0; i < elements; i++) { | |
10073 | tcg_gen_shri_i64(tcg_rd, tcg_rn, i * esize); | |
10074 | ext_and_shift_reg(tcg_rd, tcg_rd, size | (!is_u << 2), 0); | |
10075 | tcg_gen_shli_i64(tcg_rd, tcg_rd, shift); | |
10076 | write_vec_element(s, tcg_rd, rd, i, size + 1); | |
10077 | } | |
10078 | } | |
10079 | ||
c1b876b2 AB |
10080 | /* SHRN/RSHRN - Shift right with narrowing (and potential rounding) */ |
10081 | static void handle_vec_simd_shrn(DisasContext *s, bool is_q, | |
10082 | int immh, int immb, int opcode, int rn, int rd) | |
10083 | { | |
10084 | int immhb = immh << 3 | immb; | |
10085 | int size = 32 - clz32(immh) - 1; | |
10086 | int dsize = 64; | |
10087 | int esize = 8 << size; | |
10088 | int elements = dsize/esize; | |
10089 | int shift = (2 * esize) - immhb; | |
10090 | bool round = extract32(opcode, 0, 1); | |
10091 | TCGv_i64 tcg_rn, tcg_rd, tcg_final; | |
10092 | TCGv_i64 tcg_round; | |
10093 | int i; | |
10094 | ||
10095 | if (extract32(immh, 3, 1)) { | |
10096 | unallocated_encoding(s); | |
10097 | return; | |
10098 | } | |
10099 | ||
8c6afa6a PM |
10100 | if (!fp_access_check(s)) { |
10101 | return; | |
10102 | } | |
10103 | ||
c1b876b2 AB |
10104 | tcg_rn = tcg_temp_new_i64(); |
10105 | tcg_rd = tcg_temp_new_i64(); | |
10106 | tcg_final = tcg_temp_new_i64(); | |
10107 | read_vec_element(s, tcg_final, rd, is_q ? 1 : 0, MO_64); | |
10108 | ||
10109 | if (round) { | |
10110 | uint64_t round_const = 1ULL << (shift - 1); | |
10111 | tcg_round = tcg_const_i64(round_const); | |
10112 | } else { | |
f764718d | 10113 | tcg_round = NULL; |
c1b876b2 AB |
10114 | } |
10115 | ||
10116 | for (i = 0; i < elements; i++) { | |
10117 | read_vec_element(s, tcg_rn, rn, i, size+1); | |
10118 | handle_shri_with_rndacc(tcg_rd, tcg_rn, tcg_round, | |
10119 | false, true, size+1, shift); | |
10120 | ||
10121 | tcg_gen_deposit_i64(tcg_final, tcg_final, tcg_rd, esize * i, esize); | |
10122 | } | |
10123 | ||
10124 | if (!is_q) { | |
c1b876b2 AB |
10125 | write_vec_element(s, tcg_final, rd, 0, MO_64); |
10126 | } else { | |
10127 | write_vec_element(s, tcg_final, rd, 1, MO_64); | |
10128 | } | |
c1b876b2 AB |
10129 | if (round) { |
10130 | tcg_temp_free_i64(tcg_round); | |
10131 | } | |
10132 | tcg_temp_free_i64(tcg_rn); | |
10133 | tcg_temp_free_i64(tcg_rd); | |
10134 | tcg_temp_free_i64(tcg_final); | |
4ff55bcb RH |
10135 | |
10136 | clear_vec_high(s, is_q, rd); | |
c1b876b2 AB |
10137 | } |
10138 | ||
10139 | ||
4ce31af4 | 10140 | /* AdvSIMD shift by immediate |
384b26fb AB |
10141 | * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0 |
10142 | * +---+---+---+-------------+------+------+--------+---+------+------+ | |
10143 | * | 0 | Q | U | 0 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd | | |
10144 | * +---+---+---+-------------+------+------+--------+---+------+------+ | |
10145 | */ | |
10146 | static void disas_simd_shift_imm(DisasContext *s, uint32_t insn) | |
10147 | { | |
4d1cef84 AB |
10148 | int rd = extract32(insn, 0, 5); |
10149 | int rn = extract32(insn, 5, 5); | |
10150 | int opcode = extract32(insn, 11, 5); | |
10151 | int immb = extract32(insn, 16, 3); | |
10152 | int immh = extract32(insn, 19, 4); | |
10153 | bool is_u = extract32(insn, 29, 1); | |
10154 | bool is_q = extract32(insn, 30, 1); | |
10155 | ||
10156 | switch (opcode) { | |
37a706ad PM |
10157 | case 0x08: /* SRI */ |
10158 | if (!is_u) { | |
10159 | unallocated_encoding(s); | |
10160 | return; | |
10161 | } | |
10162 | /* fall through */ | |
4d1cef84 AB |
10163 | case 0x00: /* SSHR / USHR */ |
10164 | case 0x02: /* SSRA / USRA (accumulate) */ | |
10165 | case 0x04: /* SRSHR / URSHR (rounding) */ | |
10166 | case 0x06: /* SRSRA / URSRA (accum + rounding) */ | |
10167 | handle_vec_simd_shri(s, is_q, is_u, immh, immb, opcode, rn, rd); | |
10168 | break; | |
10169 | case 0x0a: /* SHL / SLI */ | |
10170 | handle_vec_simd_shli(s, is_q, is_u, immh, immb, opcode, rn, rd); | |
10171 | break; | |
c1b876b2 AB |
10172 | case 0x10: /* SHRN */ |
10173 | case 0x11: /* RSHRN / SQRSHRUN */ | |
10174 | if (is_u) { | |
10175 | handle_vec_simd_sqshrn(s, false, is_q, false, true, immh, immb, | |
10176 | opcode, rn, rd); | |
10177 | } else { | |
10178 | handle_vec_simd_shrn(s, is_q, immh, immb, opcode, rn, rd); | |
10179 | } | |
10180 | break; | |
10181 | case 0x12: /* SQSHRN / UQSHRN */ | |
10182 | case 0x13: /* SQRSHRN / UQRSHRN */ | |
10183 | handle_vec_simd_sqshrn(s, false, is_q, is_u, is_u, immh, immb, | |
10184 | opcode, rn, rd); | |
10185 | break; | |
4d1cef84 AB |
10186 | case 0x14: /* SSHLL / USHLL */ |
10187 | handle_vec_simd_wshli(s, is_q, is_u, immh, immb, opcode, rn, rd); | |
10188 | break; | |
10113b69 AB |
10189 | case 0x1c: /* SCVTF / UCVTF */ |
10190 | handle_simd_shift_intfp_conv(s, false, is_q, is_u, immh, immb, | |
10191 | opcode, rn, rd); | |
10192 | break; | |
a566da1b | 10193 | case 0xc: /* SQSHLU */ |
a847f32c PM |
10194 | if (!is_u) { |
10195 | unallocated_encoding(s); | |
10196 | return; | |
10197 | } | |
10198 | handle_simd_qshl(s, false, is_q, false, true, immh, immb, rn, rd); | |
10199 | break; | |
a566da1b | 10200 | case 0xe: /* SQSHL, UQSHL */ |
a847f32c PM |
10201 | handle_simd_qshl(s, false, is_q, is_u, is_u, immh, immb, rn, rd); |
10202 | break; | |
10113b69 | 10203 | case 0x1f: /* FCVTZS/ FCVTZU */ |
2ed3ea11 | 10204 | handle_simd_shift_fpint_conv(s, false, is_q, is_u, immh, immb, rn, rd); |
10113b69 | 10205 | return; |
4d1cef84 | 10206 | default: |
a566da1b | 10207 | unallocated_encoding(s); |
4d1cef84 AB |
10208 | return; |
10209 | } | |
384b26fb AB |
10210 | } |
10211 | ||
70d7f984 PM |
10212 | /* Generate code to do a "long" addition or subtraction, ie one done in |
10213 | * TCGv_i64 on vector lanes twice the width specified by size. | |
10214 | */ | |
10215 | static void gen_neon_addl(int size, bool is_sub, TCGv_i64 tcg_res, | |
10216 | TCGv_i64 tcg_op1, TCGv_i64 tcg_op2) | |
10217 | { | |
10218 | static NeonGenTwo64OpFn * const fns[3][2] = { | |
10219 | { gen_helper_neon_addl_u16, gen_helper_neon_subl_u16 }, | |
10220 | { gen_helper_neon_addl_u32, gen_helper_neon_subl_u32 }, | |
10221 | { tcg_gen_add_i64, tcg_gen_sub_i64 }, | |
10222 | }; | |
10223 | NeonGenTwo64OpFn *genfn; | |
10224 | assert(size < 3); | |
10225 | ||
10226 | genfn = fns[size][is_sub]; | |
10227 | genfn(tcg_res, tcg_op1, tcg_op2); | |
10228 | } | |
10229 | ||
a08582f4 PM |
10230 | static void handle_3rd_widening(DisasContext *s, int is_q, int is_u, int size, |
10231 | int opcode, int rd, int rn, int rm) | |
10232 | { | |
10233 | /* 3-reg-different widening insns: 64 x 64 -> 128 */ | |
10234 | TCGv_i64 tcg_res[2]; | |
10235 | int pass, accop; | |
10236 | ||
10237 | tcg_res[0] = tcg_temp_new_i64(); | |
10238 | tcg_res[1] = tcg_temp_new_i64(); | |
10239 | ||
10240 | /* Does this op do an adding accumulate, a subtracting accumulate, | |
10241 | * or no accumulate at all? | |
10242 | */ | |
10243 | switch (opcode) { | |
10244 | case 5: | |
10245 | case 8: | |
10246 | case 9: | |
10247 | accop = 1; | |
10248 | break; | |
10249 | case 10: | |
10250 | case 11: | |
10251 | accop = -1; | |
10252 | break; | |
10253 | default: | |
10254 | accop = 0; | |
10255 | break; | |
10256 | } | |
10257 | ||
10258 | if (accop != 0) { | |
10259 | read_vec_element(s, tcg_res[0], rd, 0, MO_64); | |
10260 | read_vec_element(s, tcg_res[1], rd, 1, MO_64); | |
10261 | } | |
10262 | ||
10263 | /* size == 2 means two 32x32->64 operations; this is worth special | |
10264 | * casing because we can generally handle it inline. | |
10265 | */ | |
10266 | if (size == 2) { | |
10267 | for (pass = 0; pass < 2; pass++) { | |
10268 | TCGv_i64 tcg_op1 = tcg_temp_new_i64(); | |
10269 | TCGv_i64 tcg_op2 = tcg_temp_new_i64(); | |
10270 | TCGv_i64 tcg_passres; | |
10271 | TCGMemOp memop = MO_32 | (is_u ? 0 : MO_SIGN); | |
10272 | ||
10273 | int elt = pass + is_q * 2; | |
10274 | ||
10275 | read_vec_element(s, tcg_op1, rn, elt, memop); | |
10276 | read_vec_element(s, tcg_op2, rm, elt, memop); | |
10277 | ||
10278 | if (accop == 0) { | |
10279 | tcg_passres = tcg_res[pass]; | |
10280 | } else { | |
10281 | tcg_passres = tcg_temp_new_i64(); | |
10282 | } | |
10283 | ||
10284 | switch (opcode) { | |
70d7f984 PM |
10285 | case 0: /* SADDL, SADDL2, UADDL, UADDL2 */ |
10286 | tcg_gen_add_i64(tcg_passres, tcg_op1, tcg_op2); | |
10287 | break; | |
10288 | case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */ | |
10289 | tcg_gen_sub_i64(tcg_passres, tcg_op1, tcg_op2); | |
10290 | break; | |
0ae39320 PM |
10291 | case 5: /* SABAL, SABAL2, UABAL, UABAL2 */ |
10292 | case 7: /* SABDL, SABDL2, UABDL, UABDL2 */ | |
10293 | { | |
10294 | TCGv_i64 tcg_tmp1 = tcg_temp_new_i64(); | |
10295 | TCGv_i64 tcg_tmp2 = tcg_temp_new_i64(); | |
10296 | ||
10297 | tcg_gen_sub_i64(tcg_tmp1, tcg_op1, tcg_op2); | |
10298 | tcg_gen_sub_i64(tcg_tmp2, tcg_op2, tcg_op1); | |
10299 | tcg_gen_movcond_i64(is_u ? TCG_COND_GEU : TCG_COND_GE, | |
10300 | tcg_passres, | |
10301 | tcg_op1, tcg_op2, tcg_tmp1, tcg_tmp2); | |
10302 | tcg_temp_free_i64(tcg_tmp1); | |
10303 | tcg_temp_free_i64(tcg_tmp2); | |
10304 | break; | |
10305 | } | |
a08582f4 PM |
10306 | case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */ |
10307 | case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */ | |
10308 | case 12: /* UMULL, UMULL2, SMULL, SMULL2 */ | |
10309 | tcg_gen_mul_i64(tcg_passres, tcg_op1, tcg_op2); | |
10310 | break; | |
70d7f984 PM |
10311 | case 9: /* SQDMLAL, SQDMLAL2 */ |
10312 | case 11: /* SQDMLSL, SQDMLSL2 */ | |
10313 | case 13: /* SQDMULL, SQDMULL2 */ | |
10314 | tcg_gen_mul_i64(tcg_passres, tcg_op1, tcg_op2); | |
10315 | gen_helper_neon_addl_saturate_s64(tcg_passres, cpu_env, | |
10316 | tcg_passres, tcg_passres); | |
10317 | break; | |
a08582f4 PM |
10318 | default: |
10319 | g_assert_not_reached(); | |
10320 | } | |
10321 | ||
70d7f984 PM |
10322 | if (opcode == 9 || opcode == 11) { |
10323 | /* saturating accumulate ops */ | |
10324 | if (accop < 0) { | |
10325 | tcg_gen_neg_i64(tcg_passres, tcg_passres); | |
10326 | } | |
10327 | gen_helper_neon_addl_saturate_s64(tcg_res[pass], cpu_env, | |
10328 | tcg_res[pass], tcg_passres); | |
10329 | } else if (accop > 0) { | |
a08582f4 | 10330 | tcg_gen_add_i64(tcg_res[pass], tcg_res[pass], tcg_passres); |
a08582f4 PM |
10331 | } else if (accop < 0) { |
10332 | tcg_gen_sub_i64(tcg_res[pass], tcg_res[pass], tcg_passres); | |
70d7f984 PM |
10333 | } |
10334 | ||
10335 | if (accop != 0) { | |
a08582f4 PM |
10336 | tcg_temp_free_i64(tcg_passres); |
10337 | } | |
10338 | ||
10339 | tcg_temp_free_i64(tcg_op1); | |
10340 | tcg_temp_free_i64(tcg_op2); | |
10341 | } | |
10342 | } else { | |
10343 | /* size 0 or 1, generally helper functions */ | |
10344 | for (pass = 0; pass < 2; pass++) { | |
10345 | TCGv_i32 tcg_op1 = tcg_temp_new_i32(); | |
10346 | TCGv_i32 tcg_op2 = tcg_temp_new_i32(); | |
10347 | TCGv_i64 tcg_passres; | |
10348 | int elt = pass + is_q * 2; | |
10349 | ||
10350 | read_vec_element_i32(s, tcg_op1, rn, elt, MO_32); | |
10351 | read_vec_element_i32(s, tcg_op2, rm, elt, MO_32); | |
10352 | ||
10353 | if (accop == 0) { | |
10354 | tcg_passres = tcg_res[pass]; | |
10355 | } else { | |
10356 | tcg_passres = tcg_temp_new_i64(); | |
10357 | } | |
10358 | ||
10359 | switch (opcode) { | |
70d7f984 PM |
10360 | case 0: /* SADDL, SADDL2, UADDL, UADDL2 */ |
10361 | case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */ | |
10362 | { | |
10363 | TCGv_i64 tcg_op2_64 = tcg_temp_new_i64(); | |
10364 | static NeonGenWidenFn * const widenfns[2][2] = { | |
10365 | { gen_helper_neon_widen_s8, gen_helper_neon_widen_u8 }, | |
10366 | { gen_helper_neon_widen_s16, gen_helper_neon_widen_u16 }, | |
10367 | }; | |
10368 | NeonGenWidenFn *widenfn = widenfns[size][is_u]; | |
10369 | ||
10370 | widenfn(tcg_op2_64, tcg_op2); | |
10371 | widenfn(tcg_passres, tcg_op1); | |
10372 | gen_neon_addl(size, (opcode == 2), tcg_passres, | |
10373 | tcg_passres, tcg_op2_64); | |
10374 | tcg_temp_free_i64(tcg_op2_64); | |
10375 | break; | |
10376 | } | |
0ae39320 PM |
10377 | case 5: /* SABAL, SABAL2, UABAL, UABAL2 */ |
10378 | case 7: /* SABDL, SABDL2, UABDL, UABDL2 */ | |
10379 | if (size == 0) { | |
10380 | if (is_u) { | |
10381 | gen_helper_neon_abdl_u16(tcg_passres, tcg_op1, tcg_op2); | |
10382 | } else { | |
10383 | gen_helper_neon_abdl_s16(tcg_passres, tcg_op1, tcg_op2); | |
10384 | } | |
10385 | } else { | |
10386 | if (is_u) { | |
10387 | gen_helper_neon_abdl_u32(tcg_passres, tcg_op1, tcg_op2); | |
10388 | } else { | |
10389 | gen_helper_neon_abdl_s32(tcg_passres, tcg_op1, tcg_op2); | |
10390 | } | |
10391 | } | |
10392 | break; | |
a08582f4 PM |
10393 | case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */ |
10394 | case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */ | |
10395 | case 12: /* UMULL, UMULL2, SMULL, SMULL2 */ | |
10396 | if (size == 0) { | |
10397 | if (is_u) { | |
10398 | gen_helper_neon_mull_u8(tcg_passres, tcg_op1, tcg_op2); | |
10399 | } else { | |
10400 | gen_helper_neon_mull_s8(tcg_passres, tcg_op1, tcg_op2); | |
10401 | } | |
10402 | } else { | |
10403 | if (is_u) { | |
10404 | gen_helper_neon_mull_u16(tcg_passres, tcg_op1, tcg_op2); | |
10405 | } else { | |
10406 | gen_helper_neon_mull_s16(tcg_passres, tcg_op1, tcg_op2); | |
10407 | } | |
10408 | } | |
10409 | break; | |
70d7f984 PM |
10410 | case 9: /* SQDMLAL, SQDMLAL2 */ |
10411 | case 11: /* SQDMLSL, SQDMLSL2 */ | |
10412 | case 13: /* SQDMULL, SQDMULL2 */ | |
10413 | assert(size == 1); | |
10414 | gen_helper_neon_mull_s16(tcg_passres, tcg_op1, tcg_op2); | |
10415 | gen_helper_neon_addl_saturate_s32(tcg_passres, cpu_env, | |
10416 | tcg_passres, tcg_passres); | |
10417 | break; | |
a984e42c PM |
10418 | case 14: /* PMULL */ |
10419 | assert(size == 0); | |
10420 | gen_helper_neon_mull_p8(tcg_passres, tcg_op1, tcg_op2); | |
10421 | break; | |
a08582f4 PM |
10422 | default: |
10423 | g_assert_not_reached(); | |
10424 | } | |
10425 | tcg_temp_free_i32(tcg_op1); | |
10426 | tcg_temp_free_i32(tcg_op2); | |
10427 | ||
70d7f984 PM |
10428 | if (accop != 0) { |
10429 | if (opcode == 9 || opcode == 11) { | |
10430 | /* saturating accumulate ops */ | |
10431 | if (accop < 0) { | |
10432 | gen_helper_neon_negl_u32(tcg_passres, tcg_passres); | |
10433 | } | |
10434 | gen_helper_neon_addl_saturate_s32(tcg_res[pass], cpu_env, | |
10435 | tcg_res[pass], | |
10436 | tcg_passres); | |
a08582f4 | 10437 | } else { |
70d7f984 PM |
10438 | gen_neon_addl(size, (accop < 0), tcg_res[pass], |
10439 | tcg_res[pass], tcg_passres); | |
a08582f4 PM |
10440 | } |
10441 | tcg_temp_free_i64(tcg_passres); | |
10442 | } | |
10443 | } | |
10444 | } | |
10445 | ||
10446 | write_vec_element(s, tcg_res[0], rd, 0, MO_64); | |
10447 | write_vec_element(s, tcg_res[1], rd, 1, MO_64); | |
10448 | tcg_temp_free_i64(tcg_res[0]); | |
10449 | tcg_temp_free_i64(tcg_res[1]); | |
10450 | } | |
10451 | ||
dfc15c7c PM |
10452 | static void handle_3rd_wide(DisasContext *s, int is_q, int is_u, int size, |
10453 | int opcode, int rd, int rn, int rm) | |
10454 | { | |
10455 | TCGv_i64 tcg_res[2]; | |
10456 | int part = is_q ? 2 : 0; | |
10457 | int pass; | |
10458 | ||
10459 | for (pass = 0; pass < 2; pass++) { | |
10460 | TCGv_i64 tcg_op1 = tcg_temp_new_i64(); | |
10461 | TCGv_i32 tcg_op2 = tcg_temp_new_i32(); | |
10462 | TCGv_i64 tcg_op2_wide = tcg_temp_new_i64(); | |
10463 | static NeonGenWidenFn * const widenfns[3][2] = { | |
10464 | { gen_helper_neon_widen_s8, gen_helper_neon_widen_u8 }, | |
10465 | { gen_helper_neon_widen_s16, gen_helper_neon_widen_u16 }, | |
10466 | { tcg_gen_ext_i32_i64, tcg_gen_extu_i32_i64 }, | |
10467 | }; | |
10468 | NeonGenWidenFn *widenfn = widenfns[size][is_u]; | |
10469 | ||
10470 | read_vec_element(s, tcg_op1, rn, pass, MO_64); | |
10471 | read_vec_element_i32(s, tcg_op2, rm, part + pass, MO_32); | |
10472 | widenfn(tcg_op2_wide, tcg_op2); | |
10473 | tcg_temp_free_i32(tcg_op2); | |
10474 | tcg_res[pass] = tcg_temp_new_i64(); | |
10475 | gen_neon_addl(size, (opcode == 3), | |
10476 | tcg_res[pass], tcg_op1, tcg_op2_wide); | |
10477 | tcg_temp_free_i64(tcg_op1); | |
10478 | tcg_temp_free_i64(tcg_op2_wide); | |
10479 | } | |
10480 | ||
10481 | for (pass = 0; pass < 2; pass++) { | |
10482 | write_vec_element(s, tcg_res[pass], rd, pass, MO_64); | |
10483 | tcg_temp_free_i64(tcg_res[pass]); | |
10484 | } | |
10485 | } | |
10486 | ||
e4b998d4 PM |
10487 | static void do_narrow_round_high_u32(TCGv_i32 res, TCGv_i64 in) |
10488 | { | |
10489 | tcg_gen_addi_i64(in, in, 1U << 31); | |
7cb36e18 | 10490 | tcg_gen_extrh_i64_i32(res, in); |
e4b998d4 PM |
10491 | } |
10492 | ||
10493 | static void handle_3rd_narrowing(DisasContext *s, int is_q, int is_u, int size, | |
10494 | int opcode, int rd, int rn, int rm) | |
10495 | { | |
10496 | TCGv_i32 tcg_res[2]; | |
10497 | int part = is_q ? 2 : 0; | |
10498 | int pass; | |
10499 | ||
10500 | for (pass = 0; pass < 2; pass++) { | |
10501 | TCGv_i64 tcg_op1 = tcg_temp_new_i64(); | |
10502 | TCGv_i64 tcg_op2 = tcg_temp_new_i64(); | |
10503 | TCGv_i64 tcg_wideres = tcg_temp_new_i64(); | |
10504 | static NeonGenNarrowFn * const narrowfns[3][2] = { | |
10505 | { gen_helper_neon_narrow_high_u8, | |
10506 | gen_helper_neon_narrow_round_high_u8 }, | |
10507 | { gen_helper_neon_narrow_high_u16, | |
10508 | gen_helper_neon_narrow_round_high_u16 }, | |
7cb36e18 | 10509 | { tcg_gen_extrh_i64_i32, do_narrow_round_high_u32 }, |
e4b998d4 PM |
10510 | }; |
10511 | NeonGenNarrowFn *gennarrow = narrowfns[size][is_u]; | |
10512 | ||
10513 | read_vec_element(s, tcg_op1, rn, pass, MO_64); | |
10514 | read_vec_element(s, tcg_op2, rm, pass, MO_64); | |
10515 | ||
10516 | gen_neon_addl(size, (opcode == 6), tcg_wideres, tcg_op1, tcg_op2); | |
10517 | ||
10518 | tcg_temp_free_i64(tcg_op1); | |
10519 | tcg_temp_free_i64(tcg_op2); | |
10520 | ||
10521 | tcg_res[pass] = tcg_temp_new_i32(); | |
10522 | gennarrow(tcg_res[pass], tcg_wideres); | |
10523 | tcg_temp_free_i64(tcg_wideres); | |
10524 | } | |
10525 | ||
10526 | for (pass = 0; pass < 2; pass++) { | |
10527 | write_vec_element_i32(s, tcg_res[pass], rd, pass + part, MO_32); | |
10528 | tcg_temp_free_i32(tcg_res[pass]); | |
10529 | } | |
4ff55bcb | 10530 | clear_vec_high(s, is_q, rd); |
e4b998d4 PM |
10531 | } |
10532 | ||
a984e42c PM |
10533 | static void handle_pmull_64(DisasContext *s, int is_q, int rd, int rn, int rm) |
10534 | { | |
10535 | /* PMULL of 64 x 64 -> 128 is an odd special case because it | |
10536 | * is the only three-reg-diff instruction which produces a | |
10537 | * 128-bit wide result from a single operation. However since | |
10538 | * it's possible to calculate the two halves more or less | |
10539 | * separately we just use two helper calls. | |
10540 | */ | |
10541 | TCGv_i64 tcg_op1 = tcg_temp_new_i64(); | |
10542 | TCGv_i64 tcg_op2 = tcg_temp_new_i64(); | |
10543 | TCGv_i64 tcg_res = tcg_temp_new_i64(); | |
10544 | ||
10545 | read_vec_element(s, tcg_op1, rn, is_q, MO_64); | |
10546 | read_vec_element(s, tcg_op2, rm, is_q, MO_64); | |
10547 | gen_helper_neon_pmull_64_lo(tcg_res, tcg_op1, tcg_op2); | |
10548 | write_vec_element(s, tcg_res, rd, 0, MO_64); | |
10549 | gen_helper_neon_pmull_64_hi(tcg_res, tcg_op1, tcg_op2); | |
10550 | write_vec_element(s, tcg_res, rd, 1, MO_64); | |
10551 | ||
10552 | tcg_temp_free_i64(tcg_op1); | |
10553 | tcg_temp_free_i64(tcg_op2); | |
10554 | tcg_temp_free_i64(tcg_res); | |
10555 | } | |
10556 | ||
4ce31af4 | 10557 | /* AdvSIMD three different |
384b26fb AB |
10558 | * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0 |
10559 | * +---+---+---+-----------+------+---+------+--------+-----+------+------+ | |
10560 | * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd | | |
10561 | * +---+---+---+-----------+------+---+------+--------+-----+------+------+ | |
10562 | */ | |
10563 | static void disas_simd_three_reg_diff(DisasContext *s, uint32_t insn) | |
10564 | { | |
a08582f4 PM |
10565 | /* Instructions in this group fall into three basic classes |
10566 | * (in each case with the operation working on each element in | |
10567 | * the input vectors): | |
10568 | * (1) widening 64 x 64 -> 128 (with possibly Vd as an extra | |
10569 | * 128 bit input) | |
10570 | * (2) wide 64 x 128 -> 128 | |
10571 | * (3) narrowing 128 x 128 -> 64 | |
10572 | * Here we do initial decode, catch unallocated cases and | |
10573 | * dispatch to separate functions for each class. | |
10574 | */ | |
10575 | int is_q = extract32(insn, 30, 1); | |
10576 | int is_u = extract32(insn, 29, 1); | |
10577 | int size = extract32(insn, 22, 2); | |
10578 | int opcode = extract32(insn, 12, 4); | |
10579 | int rm = extract32(insn, 16, 5); | |
10580 | int rn = extract32(insn, 5, 5); | |
10581 | int rd = extract32(insn, 0, 5); | |
10582 | ||
10583 | switch (opcode) { | |
10584 | case 1: /* SADDW, SADDW2, UADDW, UADDW2 */ | |
10585 | case 3: /* SSUBW, SSUBW2, USUBW, USUBW2 */ | |
10586 | /* 64 x 128 -> 128 */ | |
dfc15c7c PM |
10587 | if (size == 3) { |
10588 | unallocated_encoding(s); | |
10589 | return; | |
10590 | } | |
8c6afa6a PM |
10591 | if (!fp_access_check(s)) { |
10592 | return; | |
10593 | } | |
dfc15c7c | 10594 | handle_3rd_wide(s, is_q, is_u, size, opcode, rd, rn, rm); |
a08582f4 PM |
10595 | break; |
10596 | case 4: /* ADDHN, ADDHN2, RADDHN, RADDHN2 */ | |
10597 | case 6: /* SUBHN, SUBHN2, RSUBHN, RSUBHN2 */ | |
10598 | /* 128 x 128 -> 64 */ | |
e4b998d4 PM |
10599 | if (size == 3) { |
10600 | unallocated_encoding(s); | |
10601 | return; | |
10602 | } | |
8c6afa6a PM |
10603 | if (!fp_access_check(s)) { |
10604 | return; | |
10605 | } | |
e4b998d4 | 10606 | handle_3rd_narrowing(s, is_q, is_u, size, opcode, rd, rn, rm); |
a08582f4 | 10607 | break; |
70d7f984 PM |
10608 | case 14: /* PMULL, PMULL2 */ |
10609 | if (is_u || size == 1 || size == 2) { | |
10610 | unallocated_encoding(s); | |
10611 | return; | |
10612 | } | |
a984e42c | 10613 | if (size == 3) { |
962fcbf2 | 10614 | if (!dc_isar_feature(aa64_pmull, s)) { |
a984e42c PM |
10615 | unallocated_encoding(s); |
10616 | return; | |
10617 | } | |
8c6afa6a PM |
10618 | if (!fp_access_check(s)) { |
10619 | return; | |
10620 | } | |
a984e42c PM |
10621 | handle_pmull_64(s, is_q, rd, rn, rm); |
10622 | return; | |
10623 | } | |
10624 | goto is_widening; | |
13caf1fd PM |
10625 | case 9: /* SQDMLAL, SQDMLAL2 */ |
10626 | case 11: /* SQDMLSL, SQDMLSL2 */ | |
10627 | case 13: /* SQDMULL, SQDMULL2 */ | |
70d7f984 | 10628 | if (is_u || size == 0) { |
a08582f4 PM |
10629 | unallocated_encoding(s); |
10630 | return; | |
10631 | } | |
10632 | /* fall through */ | |
13caf1fd PM |
10633 | case 0: /* SADDL, SADDL2, UADDL, UADDL2 */ |
10634 | case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */ | |
13caf1fd PM |
10635 | case 5: /* SABAL, SABAL2, UABAL, UABAL2 */ |
10636 | case 7: /* SABDL, SABDL2, UABDL, UABDL2 */ | |
10637 | case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */ | |
10638 | case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */ | |
10639 | case 12: /* SMULL, SMULL2, UMULL, UMULL2 */ | |
a08582f4 PM |
10640 | /* 64 x 64 -> 128 */ |
10641 | if (size == 3) { | |
10642 | unallocated_encoding(s); | |
10643 | return; | |
10644 | } | |
a984e42c | 10645 | is_widening: |
8c6afa6a PM |
10646 | if (!fp_access_check(s)) { |
10647 | return; | |
10648 | } | |
10649 | ||
a08582f4 PM |
10650 | handle_3rd_widening(s, is_q, is_u, size, opcode, rd, rn, rm); |
10651 | break; | |
10652 | default: | |
10653 | /* opcode 15 not allocated */ | |
10654 | unallocated_encoding(s); | |
10655 | break; | |
10656 | } | |
384b26fb AB |
10657 | } |
10658 | ||
e1cea114 PM |
10659 | /* Logic op (opcode == 3) subgroup of C3.6.16. */ |
10660 | static void disas_simd_3same_logic(DisasContext *s, uint32_t insn) | |
10661 | { | |
956d272e PM |
10662 | int rd = extract32(insn, 0, 5); |
10663 | int rn = extract32(insn, 5, 5); | |
10664 | int rm = extract32(insn, 16, 5); | |
10665 | int size = extract32(insn, 22, 2); | |
10666 | bool is_u = extract32(insn, 29, 1); | |
10667 | bool is_q = extract32(insn, 30, 1); | |
956d272e | 10668 | |
8c6afa6a PM |
10669 | if (!fp_access_check(s)) { |
10670 | return; | |
10671 | } | |
10672 | ||
bc48092f RH |
10673 | switch (size + 4 * is_u) { |
10674 | case 0: /* AND */ | |
10675 | gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_and, 0); | |
10676 | return; | |
10677 | case 1: /* BIC */ | |
10678 | gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_andc, 0); | |
10679 | return; | |
10680 | case 2: /* ORR */ | |
2900847f | 10681 | gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_or, 0); |
bc48092f RH |
10682 | return; |
10683 | case 3: /* ORN */ | |
10684 | gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_orc, 0); | |
10685 | return; | |
10686 | case 4: /* EOR */ | |
10687 | gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_xor, 0); | |
10688 | return; | |
956d272e | 10689 | |
bc48092f RH |
10690 | case 5: /* BSL bitwise select */ |
10691 | gen_gvec_op3(s, is_q, rd, rn, rm, &bsl_op); | |
10692 | return; | |
10693 | case 6: /* BIT, bitwise insert if true */ | |
10694 | gen_gvec_op3(s, is_q, rd, rn, rm, &bit_op); | |
10695 | return; | |
10696 | case 7: /* BIF, bitwise insert if false */ | |
10697 | gen_gvec_op3(s, is_q, rd, rn, rm, &bif_op); | |
10698 | return; | |
956d272e | 10699 | |
bc48092f RH |
10700 | default: |
10701 | g_assert_not_reached(); | |
956d272e | 10702 | } |
e1cea114 PM |
10703 | } |
10704 | ||
bc242f9b AB |
10705 | /* Pairwise op subgroup of C3.6.16. |
10706 | * | |
10707 | * This is called directly or via the handle_3same_float for float pairwise | |
10708 | * operations where the opcode and size are calculated differently. | |
10709 | */ | |
10710 | static void handle_simd_3same_pair(DisasContext *s, int is_q, int u, int opcode, | |
10711 | int size, int rn, int rm, int rd) | |
e1cea114 | 10712 | { |
bc242f9b | 10713 | TCGv_ptr fpst; |
0173a005 PM |
10714 | int pass; |
10715 | ||
bc242f9b AB |
10716 | /* Floating point operations need fpst */ |
10717 | if (opcode >= 0x58) { | |
d81ce0ef | 10718 | fpst = get_fpstatus_ptr(false); |
bc242f9b | 10719 | } else { |
f764718d | 10720 | fpst = NULL; |
0173a005 PM |
10721 | } |
10722 | ||
8c6afa6a PM |
10723 | if (!fp_access_check(s)) { |
10724 | return; | |
10725 | } | |
10726 | ||
0173a005 PM |
10727 | /* These operations work on the concatenated rm:rn, with each pair of |
10728 | * adjacent elements being operated on to produce an element in the result. | |
10729 | */ | |
10730 | if (size == 3) { | |
10731 | TCGv_i64 tcg_res[2]; | |
10732 | ||
10733 | for (pass = 0; pass < 2; pass++) { | |
10734 | TCGv_i64 tcg_op1 = tcg_temp_new_i64(); | |
10735 | TCGv_i64 tcg_op2 = tcg_temp_new_i64(); | |
10736 | int passreg = (pass == 0) ? rn : rm; | |
10737 | ||
10738 | read_vec_element(s, tcg_op1, passreg, 0, MO_64); | |
10739 | read_vec_element(s, tcg_op2, passreg, 1, MO_64); | |
10740 | tcg_res[pass] = tcg_temp_new_i64(); | |
10741 | ||
bc242f9b AB |
10742 | switch (opcode) { |
10743 | case 0x17: /* ADDP */ | |
10744 | tcg_gen_add_i64(tcg_res[pass], tcg_op1, tcg_op2); | |
10745 | break; | |
10746 | case 0x58: /* FMAXNMP */ | |
10747 | gen_helper_vfp_maxnumd(tcg_res[pass], tcg_op1, tcg_op2, fpst); | |
10748 | break; | |
10749 | case 0x5a: /* FADDP */ | |
10750 | gen_helper_vfp_addd(tcg_res[pass], tcg_op1, tcg_op2, fpst); | |
10751 | break; | |
10752 | case 0x5e: /* FMAXP */ | |
10753 | gen_helper_vfp_maxd(tcg_res[pass], tcg_op1, tcg_op2, fpst); | |
10754 | break; | |
10755 | case 0x78: /* FMINNMP */ | |
10756 | gen_helper_vfp_minnumd(tcg_res[pass], tcg_op1, tcg_op2, fpst); | |
10757 | break; | |
10758 | case 0x7e: /* FMINP */ | |
10759 | gen_helper_vfp_mind(tcg_res[pass], tcg_op1, tcg_op2, fpst); | |
10760 | break; | |
10761 | default: | |
10762 | g_assert_not_reached(); | |
10763 | } | |
0173a005 PM |
10764 | |
10765 | tcg_temp_free_i64(tcg_op1); | |
10766 | tcg_temp_free_i64(tcg_op2); | |
10767 | } | |
10768 | ||
10769 | for (pass = 0; pass < 2; pass++) { | |
10770 | write_vec_element(s, tcg_res[pass], rd, pass, MO_64); | |
10771 | tcg_temp_free_i64(tcg_res[pass]); | |
10772 | } | |
10773 | } else { | |
10774 | int maxpass = is_q ? 4 : 2; | |
10775 | TCGv_i32 tcg_res[4]; | |
10776 | ||
10777 | for (pass = 0; pass < maxpass; pass++) { | |
10778 | TCGv_i32 tcg_op1 = tcg_temp_new_i32(); | |
10779 | TCGv_i32 tcg_op2 = tcg_temp_new_i32(); | |
bc242f9b | 10780 | NeonGenTwoOpFn *genfn = NULL; |
0173a005 PM |
10781 | int passreg = pass < (maxpass / 2) ? rn : rm; |
10782 | int passelt = (is_q && (pass & 1)) ? 2 : 0; | |
10783 | ||
10784 | read_vec_element_i32(s, tcg_op1, passreg, passelt, MO_32); | |
10785 | read_vec_element_i32(s, tcg_op2, passreg, passelt + 1, MO_32); | |
10786 | tcg_res[pass] = tcg_temp_new_i32(); | |
10787 | ||
10788 | switch (opcode) { | |
10789 | case 0x17: /* ADDP */ | |
10790 | { | |
10791 | static NeonGenTwoOpFn * const fns[3] = { | |
10792 | gen_helper_neon_padd_u8, | |
10793 | gen_helper_neon_padd_u16, | |
10794 | tcg_gen_add_i32, | |
10795 | }; | |
10796 | genfn = fns[size]; | |
10797 | break; | |
10798 | } | |
10799 | case 0x14: /* SMAXP, UMAXP */ | |
10800 | { | |
10801 | static NeonGenTwoOpFn * const fns[3][2] = { | |
10802 | { gen_helper_neon_pmax_s8, gen_helper_neon_pmax_u8 }, | |
10803 | { gen_helper_neon_pmax_s16, gen_helper_neon_pmax_u16 }, | |
ecb8ab8d | 10804 | { tcg_gen_smax_i32, tcg_gen_umax_i32 }, |
0173a005 PM |
10805 | }; |
10806 | genfn = fns[size][u]; | |
10807 | break; | |
10808 | } | |
10809 | case 0x15: /* SMINP, UMINP */ | |
10810 | { | |
10811 | static NeonGenTwoOpFn * const fns[3][2] = { | |
10812 | { gen_helper_neon_pmin_s8, gen_helper_neon_pmin_u8 }, | |
10813 | { gen_helper_neon_pmin_s16, gen_helper_neon_pmin_u16 }, | |
ecb8ab8d | 10814 | { tcg_gen_smin_i32, tcg_gen_umin_i32 }, |
0173a005 PM |
10815 | }; |
10816 | genfn = fns[size][u]; | |
10817 | break; | |
10818 | } | |
bc242f9b AB |
10819 | /* The FP operations are all on single floats (32 bit) */ |
10820 | case 0x58: /* FMAXNMP */ | |
10821 | gen_helper_vfp_maxnums(tcg_res[pass], tcg_op1, tcg_op2, fpst); | |
10822 | break; | |
10823 | case 0x5a: /* FADDP */ | |
10824 | gen_helper_vfp_adds(tcg_res[pass], tcg_op1, tcg_op2, fpst); | |
10825 | break; | |
10826 | case 0x5e: /* FMAXP */ | |
10827 | gen_helper_vfp_maxs(tcg_res[pass], tcg_op1, tcg_op2, fpst); | |
10828 | break; | |
10829 | case 0x78: /* FMINNMP */ | |
10830 | gen_helper_vfp_minnums(tcg_res[pass], tcg_op1, tcg_op2, fpst); | |
10831 | break; | |
10832 | case 0x7e: /* FMINP */ | |
10833 | gen_helper_vfp_mins(tcg_res[pass], tcg_op1, tcg_op2, fpst); | |
10834 | break; | |
0173a005 PM |
10835 | default: |
10836 | g_assert_not_reached(); | |
10837 | } | |
10838 | ||
bc242f9b AB |
10839 | /* FP ops called directly, otherwise call now */ |
10840 | if (genfn) { | |
10841 | genfn(tcg_res[pass], tcg_op1, tcg_op2); | |
10842 | } | |
0173a005 PM |
10843 | |
10844 | tcg_temp_free_i32(tcg_op1); | |
10845 | tcg_temp_free_i32(tcg_op2); | |
10846 | } | |
10847 | ||
10848 | for (pass = 0; pass < maxpass; pass++) { | |
10849 | write_vec_element_i32(s, tcg_res[pass], rd, pass, MO_32); | |
10850 | tcg_temp_free_i32(tcg_res[pass]); | |
10851 | } | |
4ff55bcb | 10852 | clear_vec_high(s, is_q, rd); |
0173a005 | 10853 | } |
bc242f9b | 10854 | |
f764718d | 10855 | if (fpst) { |
bc242f9b AB |
10856 | tcg_temp_free_ptr(fpst); |
10857 | } | |
e1cea114 PM |
10858 | } |
10859 | ||
10860 | /* Floating point op subgroup of C3.6.16. */ | |
10861 | static void disas_simd_3same_float(DisasContext *s, uint32_t insn) | |
10862 | { | |
845ea09a PM |
10863 | /* For floating point ops, the U, size[1] and opcode bits |
10864 | * together indicate the operation. size[0] indicates single | |
10865 | * or double. | |
10866 | */ | |
10867 | int fpopcode = extract32(insn, 11, 5) | |
10868 | | (extract32(insn, 23, 1) << 5) | |
10869 | | (extract32(insn, 29, 1) << 6); | |
10870 | int is_q = extract32(insn, 30, 1); | |
10871 | int size = extract32(insn, 22, 1); | |
10872 | int rm = extract32(insn, 16, 5); | |
10873 | int rn = extract32(insn, 5, 5); | |
10874 | int rd = extract32(insn, 0, 5); | |
10875 | ||
10876 | int datasize = is_q ? 128 : 64; | |
10877 | int esize = 32 << size; | |
10878 | int elements = datasize / esize; | |
10879 | ||
10880 | if (size == 1 && !is_q) { | |
10881 | unallocated_encoding(s); | |
10882 | return; | |
10883 | } | |
10884 | ||
10885 | switch (fpopcode) { | |
10886 | case 0x58: /* FMAXNMP */ | |
10887 | case 0x5a: /* FADDP */ | |
10888 | case 0x5e: /* FMAXP */ | |
10889 | case 0x78: /* FMINNMP */ | |
10890 | case 0x7e: /* FMINP */ | |
bc242f9b AB |
10891 | if (size && !is_q) { |
10892 | unallocated_encoding(s); | |
10893 | return; | |
10894 | } | |
10895 | handle_simd_3same_pair(s, is_q, 0, fpopcode, size ? MO_64 : MO_32, | |
10896 | rn, rm, rd); | |
845ea09a PM |
10897 | return; |
10898 | case 0x1b: /* FMULX */ | |
845ea09a PM |
10899 | case 0x1f: /* FRECPS */ |
10900 | case 0x3f: /* FRSQRTS */ | |
845ea09a | 10901 | case 0x5d: /* FACGE */ |
845ea09a PM |
10902 | case 0x7d: /* FACGT */ |
10903 | case 0x19: /* FMLA */ | |
10904 | case 0x39: /* FMLS */ | |
845ea09a PM |
10905 | case 0x18: /* FMAXNM */ |
10906 | case 0x1a: /* FADD */ | |
8908f4d1 | 10907 | case 0x1c: /* FCMEQ */ |
845ea09a PM |
10908 | case 0x1e: /* FMAX */ |
10909 | case 0x38: /* FMINNM */ | |
10910 | case 0x3a: /* FSUB */ | |
10911 | case 0x3e: /* FMIN */ | |
10912 | case 0x5b: /* FMUL */ | |
8908f4d1 | 10913 | case 0x5c: /* FCMGE */ |
845ea09a PM |
10914 | case 0x5f: /* FDIV */ |
10915 | case 0x7a: /* FABD */ | |
8908f4d1 | 10916 | case 0x7c: /* FCMGT */ |
8c6afa6a PM |
10917 | if (!fp_access_check(s)) { |
10918 | return; | |
10919 | } | |
845ea09a PM |
10920 | handle_3same_float(s, size, elements, fpopcode, rd, rn, rm); |
10921 | return; | |
0caa5af8 RH |
10922 | |
10923 | case 0x1d: /* FMLAL */ | |
10924 | case 0x3d: /* FMLSL */ | |
10925 | case 0x59: /* FMLAL2 */ | |
10926 | case 0x79: /* FMLSL2 */ | |
10927 | if (size & 1 || !dc_isar_feature(aa64_fhm, s)) { | |
10928 | unallocated_encoding(s); | |
10929 | return; | |
10930 | } | |
10931 | if (fp_access_check(s)) { | |
10932 | int is_s = extract32(insn, 23, 1); | |
10933 | int is_2 = extract32(insn, 29, 1); | |
10934 | int data = (is_2 << 1) | is_s; | |
10935 | tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd), | |
10936 | vec_full_reg_offset(s, rn), | |
10937 | vec_full_reg_offset(s, rm), cpu_env, | |
10938 | is_q ? 16 : 8, vec_full_reg_size(s), | |
10939 | data, gen_helper_gvec_fmlal_a64); | |
10940 | } | |
10941 | return; | |
10942 | ||
845ea09a PM |
10943 | default: |
10944 | unallocated_encoding(s); | |
10945 | return; | |
10946 | } | |
e1cea114 PM |
10947 | } |
10948 | ||
10949 | /* Integer op subgroup of C3.6.16. */ | |
10950 | static void disas_simd_3same_int(DisasContext *s, uint32_t insn) | |
10951 | { | |
1f8a73af PM |
10952 | int is_q = extract32(insn, 30, 1); |
10953 | int u = extract32(insn, 29, 1); | |
10954 | int size = extract32(insn, 22, 2); | |
10955 | int opcode = extract32(insn, 11, 5); | |
10956 | int rm = extract32(insn, 16, 5); | |
10957 | int rn = extract32(insn, 5, 5); | |
10958 | int rd = extract32(insn, 0, 5); | |
10959 | int pass; | |
79d61de6 | 10960 | TCGCond cond; |
1f8a73af PM |
10961 | |
10962 | switch (opcode) { | |
10963 | case 0x13: /* MUL, PMUL */ | |
10964 | if (u && size != 0) { | |
10965 | unallocated_encoding(s); | |
10966 | return; | |
10967 | } | |
10968 | /* fall through */ | |
10969 | case 0x0: /* SHADD, UHADD */ | |
10970 | case 0x2: /* SRHADD, URHADD */ | |
10971 | case 0x4: /* SHSUB, UHSUB */ | |
10972 | case 0xc: /* SMAX, UMAX */ | |
10973 | case 0xd: /* SMIN, UMIN */ | |
10974 | case 0xe: /* SABD, UABD */ | |
10975 | case 0xf: /* SABA, UABA */ | |
10976 | case 0x12: /* MLA, MLS */ | |
10977 | if (size == 3) { | |
10978 | unallocated_encoding(s); | |
10979 | return; | |
10980 | } | |
8b12a0cf | 10981 | break; |
1f8a73af PM |
10982 | case 0x16: /* SQDMULH, SQRDMULH */ |
10983 | if (size == 0 || size == 3) { | |
10984 | unallocated_encoding(s); | |
10985 | return; | |
10986 | } | |
8b12a0cf | 10987 | break; |
1f8a73af PM |
10988 | default: |
10989 | if (size == 3 && !is_q) { | |
10990 | unallocated_encoding(s); | |
10991 | return; | |
10992 | } | |
10993 | break; | |
10994 | } | |
10995 | ||
8c6afa6a PM |
10996 | if (!fp_access_check(s)) { |
10997 | return; | |
10998 | } | |
10999 | ||
bc48092f | 11000 | switch (opcode) { |
89e68b57 RH |
11001 | case 0x01: /* SQADD, UQADD */ |
11002 | tcg_gen_gvec_4(vec_full_reg_offset(s, rd), | |
11003 | offsetof(CPUARMState, vfp.qc), | |
11004 | vec_full_reg_offset(s, rn), | |
11005 | vec_full_reg_offset(s, rm), | |
11006 | is_q ? 16 : 8, vec_full_reg_size(s), | |
11007 | (u ? uqadd_op : sqadd_op) + size); | |
11008 | return; | |
11009 | case 0x05: /* SQSUB, UQSUB */ | |
11010 | tcg_gen_gvec_4(vec_full_reg_offset(s, rd), | |
11011 | offsetof(CPUARMState, vfp.qc), | |
11012 | vec_full_reg_offset(s, rn), | |
11013 | vec_full_reg_offset(s, rm), | |
11014 | is_q ? 16 : 8, vec_full_reg_size(s), | |
11015 | (u ? uqsub_op : sqsub_op) + size); | |
11016 | return; | |
264d2a48 RH |
11017 | case 0x0c: /* SMAX, UMAX */ |
11018 | if (u) { | |
11019 | gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_umax, size); | |
11020 | } else { | |
11021 | gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_smax, size); | |
11022 | } | |
11023 | return; | |
11024 | case 0x0d: /* SMIN, UMIN */ | |
11025 | if (u) { | |
11026 | gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_umin, size); | |
11027 | } else { | |
11028 | gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_smin, size); | |
11029 | } | |
11030 | return; | |
bc48092f RH |
11031 | case 0x10: /* ADD, SUB */ |
11032 | if (u) { | |
11033 | gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_sub, size); | |
11034 | } else { | |
11035 | gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_add, size); | |
11036 | } | |
11037 | return; | |
0c7c55c4 RH |
11038 | case 0x13: /* MUL, PMUL */ |
11039 | if (!u) { /* MUL */ | |
11040 | gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_mul, size); | |
11041 | return; | |
11042 | } | |
11043 | break; | |
11044 | case 0x12: /* MLA, MLS */ | |
11045 | if (u) { | |
11046 | gen_gvec_op3(s, is_q, rd, rn, rm, &mls_op[size]); | |
11047 | } else { | |
11048 | gen_gvec_op3(s, is_q, rd, rn, rm, &mla_op[size]); | |
11049 | } | |
11050 | return; | |
79d61de6 RH |
11051 | case 0x11: |
11052 | if (!u) { /* CMTST */ | |
11053 | gen_gvec_op3(s, is_q, rd, rn, rm, &cmtst_op[size]); | |
11054 | return; | |
11055 | } | |
11056 | /* else CMEQ */ | |
11057 | cond = TCG_COND_EQ; | |
11058 | goto do_gvec_cmp; | |
11059 | case 0x06: /* CMGT, CMHI */ | |
11060 | cond = u ? TCG_COND_GTU : TCG_COND_GT; | |
11061 | goto do_gvec_cmp; | |
11062 | case 0x07: /* CMGE, CMHS */ | |
11063 | cond = u ? TCG_COND_GEU : TCG_COND_GE; | |
11064 | do_gvec_cmp: | |
11065 | tcg_gen_gvec_cmp(cond, size, vec_full_reg_offset(s, rd), | |
11066 | vec_full_reg_offset(s, rn), | |
11067 | vec_full_reg_offset(s, rm), | |
11068 | is_q ? 16 : 8, vec_full_reg_size(s)); | |
11069 | return; | |
bc48092f RH |
11070 | } |
11071 | ||
1f8a73af | 11072 | if (size == 3) { |
220ad4ca PM |
11073 | assert(is_q); |
11074 | for (pass = 0; pass < 2; pass++) { | |
1f8a73af PM |
11075 | TCGv_i64 tcg_op1 = tcg_temp_new_i64(); |
11076 | TCGv_i64 tcg_op2 = tcg_temp_new_i64(); | |
11077 | TCGv_i64 tcg_res = tcg_temp_new_i64(); | |
11078 | ||
11079 | read_vec_element(s, tcg_op1, rn, pass, MO_64); | |
11080 | read_vec_element(s, tcg_op2, rm, pass, MO_64); | |
11081 | ||
11082 | handle_3same_64(s, opcode, u, tcg_res, tcg_op1, tcg_op2); | |
11083 | ||
11084 | write_vec_element(s, tcg_res, rd, pass, MO_64); | |
11085 | ||
11086 | tcg_temp_free_i64(tcg_res); | |
11087 | tcg_temp_free_i64(tcg_op1); | |
11088 | tcg_temp_free_i64(tcg_op2); | |
11089 | } | |
11090 | } else { | |
11091 | for (pass = 0; pass < (is_q ? 4 : 2); pass++) { | |
11092 | TCGv_i32 tcg_op1 = tcg_temp_new_i32(); | |
11093 | TCGv_i32 tcg_op2 = tcg_temp_new_i32(); | |
11094 | TCGv_i32 tcg_res = tcg_temp_new_i32(); | |
6d9571f7 PM |
11095 | NeonGenTwoOpFn *genfn = NULL; |
11096 | NeonGenTwoOpEnvFn *genenvfn = NULL; | |
1f8a73af PM |
11097 | |
11098 | read_vec_element_i32(s, tcg_op1, rn, pass, MO_32); | |
11099 | read_vec_element_i32(s, tcg_op2, rm, pass, MO_32); | |
11100 | ||
11101 | switch (opcode) { | |
8b12a0cf PM |
11102 | case 0x0: /* SHADD, UHADD */ |
11103 | { | |
11104 | static NeonGenTwoOpFn * const fns[3][2] = { | |
11105 | { gen_helper_neon_hadd_s8, gen_helper_neon_hadd_u8 }, | |
11106 | { gen_helper_neon_hadd_s16, gen_helper_neon_hadd_u16 }, | |
11107 | { gen_helper_neon_hadd_s32, gen_helper_neon_hadd_u32 }, | |
11108 | }; | |
11109 | genfn = fns[size][u]; | |
11110 | break; | |
11111 | } | |
8b12a0cf PM |
11112 | case 0x2: /* SRHADD, URHADD */ |
11113 | { | |
11114 | static NeonGenTwoOpFn * const fns[3][2] = { | |
11115 | { gen_helper_neon_rhadd_s8, gen_helper_neon_rhadd_u8 }, | |
11116 | { gen_helper_neon_rhadd_s16, gen_helper_neon_rhadd_u16 }, | |
11117 | { gen_helper_neon_rhadd_s32, gen_helper_neon_rhadd_u32 }, | |
11118 | }; | |
11119 | genfn = fns[size][u]; | |
11120 | break; | |
11121 | } | |
11122 | case 0x4: /* SHSUB, UHSUB */ | |
11123 | { | |
11124 | static NeonGenTwoOpFn * const fns[3][2] = { | |
11125 | { gen_helper_neon_hsub_s8, gen_helper_neon_hsub_u8 }, | |
11126 | { gen_helper_neon_hsub_s16, gen_helper_neon_hsub_u16 }, | |
11127 | { gen_helper_neon_hsub_s32, gen_helper_neon_hsub_u32 }, | |
11128 | }; | |
11129 | genfn = fns[size][u]; | |
11130 | break; | |
11131 | } | |
6d9571f7 PM |
11132 | case 0x8: /* SSHL, USHL */ |
11133 | { | |
11134 | static NeonGenTwoOpFn * const fns[3][2] = { | |
11135 | { gen_helper_neon_shl_s8, gen_helper_neon_shl_u8 }, | |
11136 | { gen_helper_neon_shl_s16, gen_helper_neon_shl_u16 }, | |
11137 | { gen_helper_neon_shl_s32, gen_helper_neon_shl_u32 }, | |
11138 | }; | |
11139 | genfn = fns[size][u]; | |
11140 | break; | |
11141 | } | |
11142 | case 0x9: /* SQSHL, UQSHL */ | |
11143 | { | |
11144 | static NeonGenTwoOpEnvFn * const fns[3][2] = { | |
11145 | { gen_helper_neon_qshl_s8, gen_helper_neon_qshl_u8 }, | |
11146 | { gen_helper_neon_qshl_s16, gen_helper_neon_qshl_u16 }, | |
11147 | { gen_helper_neon_qshl_s32, gen_helper_neon_qshl_u32 }, | |
11148 | }; | |
11149 | genenvfn = fns[size][u]; | |
11150 | break; | |
11151 | } | |
11152 | case 0xa: /* SRSHL, URSHL */ | |
11153 | { | |
11154 | static NeonGenTwoOpFn * const fns[3][2] = { | |
11155 | { gen_helper_neon_rshl_s8, gen_helper_neon_rshl_u8 }, | |
11156 | { gen_helper_neon_rshl_s16, gen_helper_neon_rshl_u16 }, | |
11157 | { gen_helper_neon_rshl_s32, gen_helper_neon_rshl_u32 }, | |
11158 | }; | |
11159 | genfn = fns[size][u]; | |
11160 | break; | |
11161 | } | |
11162 | case 0xb: /* SQRSHL, UQRSHL */ | |
11163 | { | |
11164 | static NeonGenTwoOpEnvFn * const fns[3][2] = { | |
11165 | { gen_helper_neon_qrshl_s8, gen_helper_neon_qrshl_u8 }, | |
11166 | { gen_helper_neon_qrshl_s16, gen_helper_neon_qrshl_u16 }, | |
11167 | { gen_helper_neon_qrshl_s32, gen_helper_neon_qrshl_u32 }, | |
11168 | }; | |
11169 | genenvfn = fns[size][u]; | |
11170 | break; | |
11171 | } | |
8b12a0cf PM |
11172 | case 0xe: /* SABD, UABD */ |
11173 | case 0xf: /* SABA, UABA */ | |
11174 | { | |
11175 | static NeonGenTwoOpFn * const fns[3][2] = { | |
11176 | { gen_helper_neon_abd_s8, gen_helper_neon_abd_u8 }, | |
11177 | { gen_helper_neon_abd_s16, gen_helper_neon_abd_u16 }, | |
11178 | { gen_helper_neon_abd_s32, gen_helper_neon_abd_u32 }, | |
11179 | }; | |
11180 | genfn = fns[size][u]; | |
11181 | break; | |
11182 | } | |
8b12a0cf | 11183 | case 0x13: /* MUL, PMUL */ |
0c7c55c4 RH |
11184 | assert(u); /* PMUL */ |
11185 | assert(size == 0); | |
11186 | genfn = gen_helper_neon_mul_p8; | |
8b12a0cf | 11187 | break; |
8b12a0cf PM |
11188 | case 0x16: /* SQDMULH, SQRDMULH */ |
11189 | { | |
11190 | static NeonGenTwoOpEnvFn * const fns[2][2] = { | |
11191 | { gen_helper_neon_qdmulh_s16, gen_helper_neon_qrdmulh_s16 }, | |
11192 | { gen_helper_neon_qdmulh_s32, gen_helper_neon_qrdmulh_s32 }, | |
11193 | }; | |
11194 | assert(size == 1 || size == 2); | |
11195 | genenvfn = fns[size - 1][u]; | |
11196 | break; | |
11197 | } | |
1f8a73af PM |
11198 | default: |
11199 | g_assert_not_reached(); | |
11200 | } | |
11201 | ||
6d9571f7 PM |
11202 | if (genenvfn) { |
11203 | genenvfn(tcg_res, cpu_env, tcg_op1, tcg_op2); | |
11204 | } else { | |
11205 | genfn(tcg_res, tcg_op1, tcg_op2); | |
11206 | } | |
1f8a73af | 11207 | |
0c7c55c4 RH |
11208 | if (opcode == 0xf) { |
11209 | /* SABA, UABA: accumulating ops */ | |
11210 | static NeonGenTwoOpFn * const fns[3] = { | |
11211 | gen_helper_neon_add_u8, | |
11212 | gen_helper_neon_add_u16, | |
11213 | tcg_gen_add_i32, | |
8b12a0cf | 11214 | }; |
8b12a0cf | 11215 | |
8b12a0cf | 11216 | read_vec_element_i32(s, tcg_op1, rd, pass, MO_32); |
0c7c55c4 | 11217 | fns[size](tcg_res, tcg_op1, tcg_res); |
8b12a0cf PM |
11218 | } |
11219 | ||
1f8a73af PM |
11220 | write_vec_element_i32(s, tcg_res, rd, pass, MO_32); |
11221 | ||
11222 | tcg_temp_free_i32(tcg_res); | |
11223 | tcg_temp_free_i32(tcg_op1); | |
11224 | tcg_temp_free_i32(tcg_op2); | |
11225 | } | |
11226 | } | |
4ff55bcb | 11227 | clear_vec_high(s, is_q, rd); |
e1cea114 PM |
11228 | } |
11229 | ||
4ce31af4 | 11230 | /* AdvSIMD three same |
384b26fb AB |
11231 | * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0 |
11232 | * +---+---+---+-----------+------+---+------+--------+---+------+------+ | |
11233 | * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd | | |
11234 | * +---+---+---+-----------+------+---+------+--------+---+------+------+ | |
11235 | */ | |
11236 | static void disas_simd_three_reg_same(DisasContext *s, uint32_t insn) | |
11237 | { | |
e1cea114 PM |
11238 | int opcode = extract32(insn, 11, 5); |
11239 | ||
11240 | switch (opcode) { | |
11241 | case 0x3: /* logic ops */ | |
11242 | disas_simd_3same_logic(s, insn); | |
11243 | break; | |
11244 | case 0x17: /* ADDP */ | |
11245 | case 0x14: /* SMAXP, UMAXP */ | |
11246 | case 0x15: /* SMINP, UMINP */ | |
bc242f9b | 11247 | { |
e1cea114 | 11248 | /* Pairwise operations */ |
bc242f9b AB |
11249 | int is_q = extract32(insn, 30, 1); |
11250 | int u = extract32(insn, 29, 1); | |
11251 | int size = extract32(insn, 22, 2); | |
11252 | int rm = extract32(insn, 16, 5); | |
11253 | int rn = extract32(insn, 5, 5); | |
11254 | int rd = extract32(insn, 0, 5); | |
11255 | if (opcode == 0x17) { | |
11256 | if (u || (size == 3 && !is_q)) { | |
11257 | unallocated_encoding(s); | |
11258 | return; | |
11259 | } | |
11260 | } else { | |
11261 | if (size == 3) { | |
11262 | unallocated_encoding(s); | |
11263 | return; | |
11264 | } | |
11265 | } | |
11266 | handle_simd_3same_pair(s, is_q, u, opcode, size, rn, rm, rd); | |
e1cea114 | 11267 | break; |
bc242f9b | 11268 | } |
e1cea114 PM |
11269 | case 0x18 ... 0x31: |
11270 | /* floating point ops, sz[1] and U are part of opcode */ | |
11271 | disas_simd_3same_float(s, insn); | |
11272 | break; | |
11273 | default: | |
11274 | disas_simd_3same_int(s, insn); | |
11275 | break; | |
11276 | } | |
384b26fb AB |
11277 | } |
11278 | ||
376e8d6c AB |
11279 | /* |
11280 | * Advanced SIMD three same (ARMv8.2 FP16 variants) | |
11281 | * | |
11282 | * 31 30 29 28 24 23 22 21 20 16 15 14 13 11 10 9 5 4 0 | |
11283 | * +---+---+---+-----------+---------+------+-----+--------+---+------+------+ | |
11284 | * | 0 | Q | U | 0 1 1 1 0 | a | 1 0 | Rm | 0 0 | opcode | 1 | Rn | Rd | | |
11285 | * +---+---+---+-----------+---------+------+-----+--------+---+------+------+ | |
11286 | * | |
11287 | * This includes FMULX, FCMEQ (register), FRECPS, FRSQRTS, FCMGE | |
11288 | * (register), FACGE, FABD, FCMGT (register) and FACGT. | |
11289 | * | |
11290 | */ | |
11291 | static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn) | |
11292 | { | |
11293 | int opcode, fpopcode; | |
11294 | int is_q, u, a, rm, rn, rd; | |
11295 | int datasize, elements; | |
11296 | int pass; | |
11297 | TCGv_ptr fpst; | |
7a2c6e61 | 11298 | bool pairwise = false; |
376e8d6c | 11299 | |
5763190f | 11300 | if (!dc_isar_feature(aa64_fp16, s)) { |
376e8d6c AB |
11301 | unallocated_encoding(s); |
11302 | return; | |
11303 | } | |
11304 | ||
11305 | if (!fp_access_check(s)) { | |
11306 | return; | |
11307 | } | |
11308 | ||
11309 | /* For these floating point ops, the U, a and opcode bits | |
11310 | * together indicate the operation. | |
11311 | */ | |
11312 | opcode = extract32(insn, 11, 3); | |
11313 | u = extract32(insn, 29, 1); | |
11314 | a = extract32(insn, 23, 1); | |
11315 | is_q = extract32(insn, 30, 1); | |
11316 | rm = extract32(insn, 16, 5); | |
11317 | rn = extract32(insn, 5, 5); | |
11318 | rd = extract32(insn, 0, 5); | |
11319 | ||
11320 | fpopcode = opcode | (a << 3) | (u << 4); | |
11321 | datasize = is_q ? 128 : 64; | |
11322 | elements = datasize / 16; | |
11323 | ||
7a2c6e61 AB |
11324 | switch (fpopcode) { |
11325 | case 0x10: /* FMAXNMP */ | |
11326 | case 0x12: /* FADDP */ | |
11327 | case 0x16: /* FMAXP */ | |
11328 | case 0x18: /* FMINNMP */ | |
11329 | case 0x1e: /* FMINP */ | |
11330 | pairwise = true; | |
11331 | break; | |
11332 | } | |
11333 | ||
376e8d6c AB |
11334 | fpst = get_fpstatus_ptr(true); |
11335 | ||
7a2c6e61 AB |
11336 | if (pairwise) { |
11337 | int maxpass = is_q ? 8 : 4; | |
376e8d6c AB |
11338 | TCGv_i32 tcg_op1 = tcg_temp_new_i32(); |
11339 | TCGv_i32 tcg_op2 = tcg_temp_new_i32(); | |
7a2c6e61 | 11340 | TCGv_i32 tcg_res[8]; |
376e8d6c | 11341 | |
7a2c6e61 AB |
11342 | for (pass = 0; pass < maxpass; pass++) { |
11343 | int passreg = pass < (maxpass / 2) ? rn : rm; | |
11344 | int passelt = (pass << 1) & (maxpass - 1); | |
376e8d6c | 11345 | |
7a2c6e61 AB |
11346 | read_vec_element_i32(s, tcg_op1, passreg, passelt, MO_16); |
11347 | read_vec_element_i32(s, tcg_op2, passreg, passelt + 1, MO_16); | |
11348 | tcg_res[pass] = tcg_temp_new_i32(); | |
11349 | ||
11350 | switch (fpopcode) { | |
11351 | case 0x10: /* FMAXNMP */ | |
11352 | gen_helper_advsimd_maxnumh(tcg_res[pass], tcg_op1, tcg_op2, | |
11353 | fpst); | |
11354 | break; | |
11355 | case 0x12: /* FADDP */ | |
11356 | gen_helper_advsimd_addh(tcg_res[pass], tcg_op1, tcg_op2, fpst); | |
11357 | break; | |
11358 | case 0x16: /* FMAXP */ | |
11359 | gen_helper_advsimd_maxh(tcg_res[pass], tcg_op1, tcg_op2, fpst); | |
11360 | break; | |
11361 | case 0x18: /* FMINNMP */ | |
11362 | gen_helper_advsimd_minnumh(tcg_res[pass], tcg_op1, tcg_op2, | |
11363 | fpst); | |
11364 | break; | |
11365 | case 0x1e: /* FMINP */ | |
11366 | gen_helper_advsimd_minh(tcg_res[pass], tcg_op1, tcg_op2, fpst); | |
11367 | break; | |
11368 | default: | |
11369 | g_assert_not_reached(); | |
11370 | } | |
11371 | } | |
11372 | ||
11373 | for (pass = 0; pass < maxpass; pass++) { | |
11374 | write_vec_element_i32(s, tcg_res[pass], rd, pass, MO_16); | |
11375 | tcg_temp_free_i32(tcg_res[pass]); | |
376e8d6c AB |
11376 | } |
11377 | ||
376e8d6c AB |
11378 | tcg_temp_free_i32(tcg_op1); |
11379 | tcg_temp_free_i32(tcg_op2); | |
7a2c6e61 AB |
11380 | |
11381 | } else { | |
11382 | for (pass = 0; pass < elements; pass++) { | |
11383 | TCGv_i32 tcg_op1 = tcg_temp_new_i32(); | |
11384 | TCGv_i32 tcg_op2 = tcg_temp_new_i32(); | |
11385 | TCGv_i32 tcg_res = tcg_temp_new_i32(); | |
11386 | ||
11387 | read_vec_element_i32(s, tcg_op1, rn, pass, MO_16); | |
11388 | read_vec_element_i32(s, tcg_op2, rm, pass, MO_16); | |
11389 | ||
11390 | switch (fpopcode) { | |
11391 | case 0x0: /* FMAXNM */ | |
11392 | gen_helper_advsimd_maxnumh(tcg_res, tcg_op1, tcg_op2, fpst); | |
11393 | break; | |
11394 | case 0x1: /* FMLA */ | |
11395 | read_vec_element_i32(s, tcg_res, rd, pass, MO_16); | |
11396 | gen_helper_advsimd_muladdh(tcg_res, tcg_op1, tcg_op2, tcg_res, | |
11397 | fpst); | |
11398 | break; | |
11399 | case 0x2: /* FADD */ | |
11400 | gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst); | |
11401 | break; | |
11402 | case 0x3: /* FMULX */ | |
11403 | gen_helper_advsimd_mulxh(tcg_res, tcg_op1, tcg_op2, fpst); | |
11404 | break; | |
11405 | case 0x4: /* FCMEQ */ | |
11406 | gen_helper_advsimd_ceq_f16(tcg_res, tcg_op1, tcg_op2, fpst); | |
11407 | break; | |
11408 | case 0x6: /* FMAX */ | |
11409 | gen_helper_advsimd_maxh(tcg_res, tcg_op1, tcg_op2, fpst); | |
11410 | break; | |
11411 | case 0x7: /* FRECPS */ | |
11412 | gen_helper_recpsf_f16(tcg_res, tcg_op1, tcg_op2, fpst); | |
11413 | break; | |
11414 | case 0x8: /* FMINNM */ | |
11415 | gen_helper_advsimd_minnumh(tcg_res, tcg_op1, tcg_op2, fpst); | |
11416 | break; | |
11417 | case 0x9: /* FMLS */ | |
11418 | /* As usual for ARM, separate negation for fused multiply-add */ | |
11419 | tcg_gen_xori_i32(tcg_op1, tcg_op1, 0x8000); | |
11420 | read_vec_element_i32(s, tcg_res, rd, pass, MO_16); | |
11421 | gen_helper_advsimd_muladdh(tcg_res, tcg_op1, tcg_op2, tcg_res, | |
11422 | fpst); | |
11423 | break; | |
11424 | case 0xa: /* FSUB */ | |
11425 | gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst); | |
11426 | break; | |
11427 | case 0xe: /* FMIN */ | |
11428 | gen_helper_advsimd_minh(tcg_res, tcg_op1, tcg_op2, fpst); | |
11429 | break; | |
11430 | case 0xf: /* FRSQRTS */ | |
11431 | gen_helper_rsqrtsf_f16(tcg_res, tcg_op1, tcg_op2, fpst); | |
11432 | break; | |
11433 | case 0x13: /* FMUL */ | |
11434 | gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst); | |
11435 | break; | |
11436 | case 0x14: /* FCMGE */ | |
11437 | gen_helper_advsimd_cge_f16(tcg_res, tcg_op1, tcg_op2, fpst); | |
11438 | break; | |
11439 | case 0x15: /* FACGE */ | |
11440 | gen_helper_advsimd_acge_f16(tcg_res, tcg_op1, tcg_op2, fpst); | |
11441 | break; | |
11442 | case 0x17: /* FDIV */ | |
11443 | gen_helper_advsimd_divh(tcg_res, tcg_op1, tcg_op2, fpst); | |
11444 | break; | |
11445 | case 0x1a: /* FABD */ | |
11446 | gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst); | |
11447 | tcg_gen_andi_i32(tcg_res, tcg_res, 0x7fff); | |
11448 | break; | |
11449 | case 0x1c: /* FCMGT */ | |
11450 | gen_helper_advsimd_cgt_f16(tcg_res, tcg_op1, tcg_op2, fpst); | |
11451 | break; | |
11452 | case 0x1d: /* FACGT */ | |
11453 | gen_helper_advsimd_acgt_f16(tcg_res, tcg_op1, tcg_op2, fpst); | |
11454 | break; | |
11455 | default: | |
11456 | fprintf(stderr, "%s: insn %#04x, fpop %#2x @ %#" PRIx64 "\n", | |
11457 | __func__, insn, fpopcode, s->pc); | |
11458 | g_assert_not_reached(); | |
11459 | } | |
11460 | ||
11461 | write_vec_element_i32(s, tcg_res, rd, pass, MO_16); | |
11462 | tcg_temp_free_i32(tcg_res); | |
11463 | tcg_temp_free_i32(tcg_op1); | |
11464 | tcg_temp_free_i32(tcg_op2); | |
11465 | } | |
376e8d6c AB |
11466 | } |
11467 | ||
11468 | tcg_temp_free_ptr(fpst); | |
11469 | ||
11470 | clear_vec_high(s, is_q, rd); | |
11471 | } | |
11472 | ||
e7186d82 RH |
11473 | /* AdvSIMD three same extra |
11474 | * 31 30 29 28 24 23 22 21 20 16 15 14 11 10 9 5 4 0 | |
11475 | * +---+---+---+-----------+------+---+------+---+--------+---+----+----+ | |
11476 | * | 0 | Q | U | 0 1 1 1 0 | size | 0 | Rm | 1 | opcode | 1 | Rn | Rd | | |
11477 | * +---+---+---+-----------+------+---+------+---+--------+---+----+----+ | |
11478 | */ | |
11479 | static void disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn) | |
11480 | { | |
11481 | int rd = extract32(insn, 0, 5); | |
11482 | int rn = extract32(insn, 5, 5); | |
11483 | int opcode = extract32(insn, 11, 4); | |
11484 | int rm = extract32(insn, 16, 5); | |
11485 | int size = extract32(insn, 22, 2); | |
11486 | bool u = extract32(insn, 29, 1); | |
11487 | bool is_q = extract32(insn, 30, 1); | |
962fcbf2 RH |
11488 | bool feature; |
11489 | int rot; | |
e7186d82 RH |
11490 | |
11491 | switch (u * 16 + opcode) { | |
11492 | case 0x10: /* SQRDMLAH (vector) */ | |
11493 | case 0x11: /* SQRDMLSH (vector) */ | |
11494 | if (size != 1 && size != 2) { | |
11495 | unallocated_encoding(s); | |
11496 | return; | |
11497 | } | |
962fcbf2 | 11498 | feature = dc_isar_feature(aa64_rdm, s); |
e7186d82 | 11499 | break; |
26c470a7 RH |
11500 | case 0x02: /* SDOT (vector) */ |
11501 | case 0x12: /* UDOT (vector) */ | |
11502 | if (size != MO_32) { | |
11503 | unallocated_encoding(s); | |
11504 | return; | |
11505 | } | |
962fcbf2 | 11506 | feature = dc_isar_feature(aa64_dp, s); |
26c470a7 | 11507 | break; |
b8a4a96d RH |
11508 | case 0x18: /* FCMLA, #0 */ |
11509 | case 0x19: /* FCMLA, #90 */ | |
11510 | case 0x1a: /* FCMLA, #180 */ | |
11511 | case 0x1b: /* FCMLA, #270 */ | |
11512 | case 0x1c: /* FCADD, #90 */ | |
11513 | case 0x1e: /* FCADD, #270 */ | |
1695cd61 | 11514 | if (size == 0 |
5763190f | 11515 | || (size == 1 && !dc_isar_feature(aa64_fp16, s)) |
1695cd61 RH |
11516 | || (size == 3 && !is_q)) { |
11517 | unallocated_encoding(s); | |
11518 | return; | |
11519 | } | |
962fcbf2 | 11520 | feature = dc_isar_feature(aa64_fcma, s); |
1695cd61 | 11521 | break; |
e7186d82 RH |
11522 | default: |
11523 | unallocated_encoding(s); | |
11524 | return; | |
11525 | } | |
962fcbf2 | 11526 | if (!feature) { |
e7186d82 RH |
11527 | unallocated_encoding(s); |
11528 | return; | |
11529 | } | |
11530 | if (!fp_access_check(s)) { | |
11531 | return; | |
11532 | } | |
11533 | ||
11534 | switch (opcode) { | |
11535 | case 0x0: /* SQRDMLAH (vector) */ | |
11536 | switch (size) { | |
11537 | case 1: | |
11538 | gen_gvec_op3_env(s, is_q, rd, rn, rm, gen_helper_gvec_qrdmlah_s16); | |
11539 | break; | |
11540 | case 2: | |
11541 | gen_gvec_op3_env(s, is_q, rd, rn, rm, gen_helper_gvec_qrdmlah_s32); | |
11542 | break; | |
11543 | default: | |
11544 | g_assert_not_reached(); | |
11545 | } | |
11546 | return; | |
11547 | ||
11548 | case 0x1: /* SQRDMLSH (vector) */ | |
11549 | switch (size) { | |
11550 | case 1: | |
11551 | gen_gvec_op3_env(s, is_q, rd, rn, rm, gen_helper_gvec_qrdmlsh_s16); | |
11552 | break; | |
11553 | case 2: | |
11554 | gen_gvec_op3_env(s, is_q, rd, rn, rm, gen_helper_gvec_qrdmlsh_s32); | |
11555 | break; | |
11556 | default: | |
11557 | g_assert_not_reached(); | |
11558 | } | |
11559 | return; | |
11560 | ||
26c470a7 RH |
11561 | case 0x2: /* SDOT / UDOT */ |
11562 | gen_gvec_op3_ool(s, is_q, rd, rn, rm, 0, | |
11563 | u ? gen_helper_gvec_udot_b : gen_helper_gvec_sdot_b); | |
11564 | return; | |
11565 | ||
d17b7cdc RH |
11566 | case 0x8: /* FCMLA, #0 */ |
11567 | case 0x9: /* FCMLA, #90 */ | |
11568 | case 0xa: /* FCMLA, #180 */ | |
11569 | case 0xb: /* FCMLA, #270 */ | |
11570 | rot = extract32(opcode, 0, 2); | |
11571 | switch (size) { | |
11572 | case 1: | |
11573 | gen_gvec_op3_fpst(s, is_q, rd, rn, rm, true, rot, | |
11574 | gen_helper_gvec_fcmlah); | |
11575 | break; | |
11576 | case 2: | |
11577 | gen_gvec_op3_fpst(s, is_q, rd, rn, rm, false, rot, | |
11578 | gen_helper_gvec_fcmlas); | |
11579 | break; | |
11580 | case 3: | |
11581 | gen_gvec_op3_fpst(s, is_q, rd, rn, rm, false, rot, | |
11582 | gen_helper_gvec_fcmlad); | |
11583 | break; | |
11584 | default: | |
11585 | g_assert_not_reached(); | |
11586 | } | |
11587 | return; | |
11588 | ||
1695cd61 RH |
11589 | case 0xc: /* FCADD, #90 */ |
11590 | case 0xe: /* FCADD, #270 */ | |
11591 | rot = extract32(opcode, 1, 1); | |
11592 | switch (size) { | |
11593 | case 1: | |
11594 | gen_gvec_op3_fpst(s, is_q, rd, rn, rm, size == 1, rot, | |
11595 | gen_helper_gvec_fcaddh); | |
11596 | break; | |
11597 | case 2: | |
11598 | gen_gvec_op3_fpst(s, is_q, rd, rn, rm, size == 1, rot, | |
11599 | gen_helper_gvec_fcadds); | |
11600 | break; | |
11601 | case 3: | |
11602 | gen_gvec_op3_fpst(s, is_q, rd, rn, rm, size == 1, rot, | |
11603 | gen_helper_gvec_fcaddd); | |
11604 | break; | |
11605 | default: | |
11606 | g_assert_not_reached(); | |
11607 | } | |
11608 | return; | |
11609 | ||
e7186d82 RH |
11610 | default: |
11611 | g_assert_not_reached(); | |
11612 | } | |
11613 | } | |
11614 | ||
931c8cc2 PM |
11615 | static void handle_2misc_widening(DisasContext *s, int opcode, bool is_q, |
11616 | int size, int rn, int rd) | |
11617 | { | |
11618 | /* Handle 2-reg-misc ops which are widening (so each size element | |
11619 | * in the source becomes a 2*size element in the destination. | |
11620 | * The only instruction like this is FCVTL. | |
11621 | */ | |
11622 | int pass; | |
11623 | ||
11624 | if (size == 3) { | |
11625 | /* 32 -> 64 bit fp conversion */ | |
11626 | TCGv_i64 tcg_res[2]; | |
11627 | int srcelt = is_q ? 2 : 0; | |
11628 | ||
11629 | for (pass = 0; pass < 2; pass++) { | |
11630 | TCGv_i32 tcg_op = tcg_temp_new_i32(); | |
11631 | tcg_res[pass] = tcg_temp_new_i64(); | |
11632 | ||
11633 | read_vec_element_i32(s, tcg_op, rn, srcelt + pass, MO_32); | |
11634 | gen_helper_vfp_fcvtds(tcg_res[pass], tcg_op, cpu_env); | |
11635 | tcg_temp_free_i32(tcg_op); | |
11636 | } | |
11637 | for (pass = 0; pass < 2; pass++) { | |
11638 | write_vec_element(s, tcg_res[pass], rd, pass, MO_64); | |
11639 | tcg_temp_free_i64(tcg_res[pass]); | |
11640 | } | |
11641 | } else { | |
11642 | /* 16 -> 32 bit fp conversion */ | |
11643 | int srcelt = is_q ? 4 : 0; | |
11644 | TCGv_i32 tcg_res[4]; | |
486624fc AB |
11645 | TCGv_ptr fpst = get_fpstatus_ptr(false); |
11646 | TCGv_i32 ahp = get_ahp_flag(); | |
931c8cc2 PM |
11647 | |
11648 | for (pass = 0; pass < 4; pass++) { | |
11649 | tcg_res[pass] = tcg_temp_new_i32(); | |
11650 | ||
11651 | read_vec_element_i32(s, tcg_res[pass], rn, srcelt + pass, MO_16); | |
11652 | gen_helper_vfp_fcvt_f16_to_f32(tcg_res[pass], tcg_res[pass], | |
486624fc | 11653 | fpst, ahp); |
931c8cc2 PM |
11654 | } |
11655 | for (pass = 0; pass < 4; pass++) { | |
11656 | write_vec_element_i32(s, tcg_res[pass], rd, pass, MO_32); | |
11657 | tcg_temp_free_i32(tcg_res[pass]); | |
11658 | } | |
486624fc AB |
11659 | |
11660 | tcg_temp_free_ptr(fpst); | |
11661 | tcg_temp_free_i32(ahp); | |
931c8cc2 PM |
11662 | } |
11663 | } | |
11664 | ||
39d82118 AB |
11665 | static void handle_rev(DisasContext *s, int opcode, bool u, |
11666 | bool is_q, int size, int rn, int rd) | |
11667 | { | |
11668 | int op = (opcode << 1) | u; | |
11669 | int opsz = op + size; | |
11670 | int grp_size = 3 - opsz; | |
11671 | int dsize = is_q ? 128 : 64; | |
11672 | int i; | |
11673 | ||
11674 | if (opsz >= 3) { | |
11675 | unallocated_encoding(s); | |
11676 | return; | |
11677 | } | |
11678 | ||
8c6afa6a PM |
11679 | if (!fp_access_check(s)) { |
11680 | return; | |
11681 | } | |
11682 | ||
39d82118 AB |
11683 | if (size == 0) { |
11684 | /* Special case bytes, use bswap op on each group of elements */ | |
11685 | int groups = dsize / (8 << grp_size); | |
11686 | ||
11687 | for (i = 0; i < groups; i++) { | |
11688 | TCGv_i64 tcg_tmp = tcg_temp_new_i64(); | |
11689 | ||
11690 | read_vec_element(s, tcg_tmp, rn, i, grp_size); | |
11691 | switch (grp_size) { | |
11692 | case MO_16: | |
11693 | tcg_gen_bswap16_i64(tcg_tmp, tcg_tmp); | |
11694 | break; | |
11695 | case MO_32: | |
11696 | tcg_gen_bswap32_i64(tcg_tmp, tcg_tmp); | |
11697 | break; | |
11698 | case MO_64: | |
11699 | tcg_gen_bswap64_i64(tcg_tmp, tcg_tmp); | |
11700 | break; | |
11701 | default: | |
11702 | g_assert_not_reached(); | |
11703 | } | |
11704 | write_vec_element(s, tcg_tmp, rd, i, grp_size); | |
11705 | tcg_temp_free_i64(tcg_tmp); | |
11706 | } | |
4ff55bcb | 11707 | clear_vec_high(s, is_q, rd); |
39d82118 AB |
11708 | } else { |
11709 | int revmask = (1 << grp_size) - 1; | |
11710 | int esize = 8 << size; | |
11711 | int elements = dsize / esize; | |
11712 | TCGv_i64 tcg_rn = tcg_temp_new_i64(); | |
11713 | TCGv_i64 tcg_rd = tcg_const_i64(0); | |
11714 | TCGv_i64 tcg_rd_hi = tcg_const_i64(0); | |
11715 | ||
11716 | for (i = 0; i < elements; i++) { | |
11717 | int e_rev = (i & 0xf) ^ revmask; | |
11718 | int off = e_rev * esize; | |
11719 | read_vec_element(s, tcg_rn, rn, i, size); | |
11720 | if (off >= 64) { | |
11721 | tcg_gen_deposit_i64(tcg_rd_hi, tcg_rd_hi, | |
11722 | tcg_rn, off - 64, esize); | |
11723 | } else { | |
11724 | tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_rn, off, esize); | |
11725 | } | |
11726 | } | |
11727 | write_vec_element(s, tcg_rd, rd, 0, MO_64); | |
11728 | write_vec_element(s, tcg_rd_hi, rd, 1, MO_64); | |
11729 | ||
11730 | tcg_temp_free_i64(tcg_rd_hi); | |
11731 | tcg_temp_free_i64(tcg_rd); | |
11732 | tcg_temp_free_i64(tcg_rn); | |
11733 | } | |
11734 | } | |
11735 | ||
6781fa11 PM |
11736 | static void handle_2misc_pairwise(DisasContext *s, int opcode, bool u, |
11737 | bool is_q, int size, int rn, int rd) | |
11738 | { | |
11739 | /* Implement the pairwise operations from 2-misc: | |
11740 | * SADDLP, UADDLP, SADALP, UADALP. | |
11741 | * These all add pairs of elements in the input to produce a | |
11742 | * double-width result element in the output (possibly accumulating). | |
11743 | */ | |
11744 | bool accum = (opcode == 0x6); | |
11745 | int maxpass = is_q ? 2 : 1; | |
11746 | int pass; | |
11747 | TCGv_i64 tcg_res[2]; | |
11748 | ||
11749 | if (size == 2) { | |
11750 | /* 32 + 32 -> 64 op */ | |
11751 | TCGMemOp memop = size + (u ? 0 : MO_SIGN); | |
11752 | ||
11753 | for (pass = 0; pass < maxpass; pass++) { | |
11754 | TCGv_i64 tcg_op1 = tcg_temp_new_i64(); | |
11755 | TCGv_i64 tcg_op2 = tcg_temp_new_i64(); | |
11756 | ||
11757 | tcg_res[pass] = tcg_temp_new_i64(); | |
11758 | ||
11759 | read_vec_element(s, tcg_op1, rn, pass * 2, memop); | |
11760 | read_vec_element(s, tcg_op2, rn, pass * 2 + 1, memop); | |
11761 | tcg_gen_add_i64(tcg_res[pass], tcg_op1, tcg_op2); | |
11762 | if (accum) { | |
11763 | read_vec_element(s, tcg_op1, rd, pass, MO_64); | |
11764 | tcg_gen_add_i64(tcg_res[pass], tcg_res[pass], tcg_op1); | |
11765 | } | |
11766 | ||
11767 | tcg_temp_free_i64(tcg_op1); | |
11768 | tcg_temp_free_i64(tcg_op2); | |
11769 | } | |
11770 | } else { | |
11771 | for (pass = 0; pass < maxpass; pass++) { | |
11772 | TCGv_i64 tcg_op = tcg_temp_new_i64(); | |
11773 | NeonGenOneOpFn *genfn; | |
11774 | static NeonGenOneOpFn * const fns[2][2] = { | |
11775 | { gen_helper_neon_addlp_s8, gen_helper_neon_addlp_u8 }, | |
11776 | { gen_helper_neon_addlp_s16, gen_helper_neon_addlp_u16 }, | |
11777 | }; | |
11778 | ||
11779 | genfn = fns[size][u]; | |
11780 | ||
11781 | tcg_res[pass] = tcg_temp_new_i64(); | |
11782 | ||
11783 | read_vec_element(s, tcg_op, rn, pass, MO_64); | |
11784 | genfn(tcg_res[pass], tcg_op); | |
11785 | ||
11786 | if (accum) { | |
11787 | read_vec_element(s, tcg_op, rd, pass, MO_64); | |
11788 | if (size == 0) { | |
11789 | gen_helper_neon_addl_u16(tcg_res[pass], | |
11790 | tcg_res[pass], tcg_op); | |
11791 | } else { | |
11792 | gen_helper_neon_addl_u32(tcg_res[pass], | |
11793 | tcg_res[pass], tcg_op); | |
11794 | } | |
11795 | } | |
11796 | tcg_temp_free_i64(tcg_op); | |
11797 | } | |
11798 | } | |
11799 | if (!is_q) { | |
11800 | tcg_res[1] = tcg_const_i64(0); | |
11801 | } | |
11802 | for (pass = 0; pass < 2; pass++) { | |
11803 | write_vec_element(s, tcg_res[pass], rd, pass, MO_64); | |
11804 | tcg_temp_free_i64(tcg_res[pass]); | |
11805 | } | |
11806 | } | |
11807 | ||
73a81d10 PM |
11808 | static void handle_shll(DisasContext *s, bool is_q, int size, int rn, int rd) |
11809 | { | |
11810 | /* Implement SHLL and SHLL2 */ | |
11811 | int pass; | |
11812 | int part = is_q ? 2 : 0; | |
11813 | TCGv_i64 tcg_res[2]; | |
11814 | ||
11815 | for (pass = 0; pass < 2; pass++) { | |
11816 | static NeonGenWidenFn * const widenfns[3] = { | |
11817 | gen_helper_neon_widen_u8, | |
11818 | gen_helper_neon_widen_u16, | |
11819 | tcg_gen_extu_i32_i64, | |
11820 | }; | |
11821 | NeonGenWidenFn *widenfn = widenfns[size]; | |
11822 | TCGv_i32 tcg_op = tcg_temp_new_i32(); | |
11823 | ||
11824 | read_vec_element_i32(s, tcg_op, rn, part + pass, MO_32); | |
11825 | tcg_res[pass] = tcg_temp_new_i64(); | |
11826 | widenfn(tcg_res[pass], tcg_op); | |
11827 | tcg_gen_shli_i64(tcg_res[pass], tcg_res[pass], 8 << size); | |
11828 | ||
11829 | tcg_temp_free_i32(tcg_op); | |
11830 | } | |
11831 | ||
11832 | for (pass = 0; pass < 2; pass++) { | |
11833 | write_vec_element(s, tcg_res[pass], rd, pass, MO_64); | |
11834 | tcg_temp_free_i64(tcg_res[pass]); | |
11835 | } | |
11836 | } | |
11837 | ||
4ce31af4 | 11838 | /* AdvSIMD two reg misc |
384b26fb AB |
11839 | * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0 |
11840 | * +---+---+---+-----------+------+-----------+--------+-----+------+------+ | |
11841 | * | 0 | Q | U | 0 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd | | |
11842 | * +---+---+---+-----------+------+-----------+--------+-----+------+------+ | |
11843 | */ | |
11844 | static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn) | |
11845 | { | |
45aecc6d PM |
11846 | int size = extract32(insn, 22, 2); |
11847 | int opcode = extract32(insn, 12, 5); | |
11848 | bool u = extract32(insn, 29, 1); | |
11849 | bool is_q = extract32(insn, 30, 1); | |
94b6c911 PM |
11850 | int rn = extract32(insn, 5, 5); |
11851 | int rd = extract32(insn, 0, 5); | |
04c7c6c2 PM |
11852 | bool need_fpstatus = false; |
11853 | bool need_rmode = false; | |
11854 | int rmode = -1; | |
11855 | TCGv_i32 tcg_rmode; | |
11856 | TCGv_ptr tcg_fpstatus; | |
45aecc6d PM |
11857 | |
11858 | switch (opcode) { | |
11859 | case 0x0: /* REV64, REV32 */ | |
11860 | case 0x1: /* REV16 */ | |
39d82118 | 11861 | handle_rev(s, opcode, u, is_q, size, rn, rd); |
45aecc6d | 11862 | return; |
86cbc418 PM |
11863 | case 0x5: /* CNT, NOT, RBIT */ |
11864 | if (u && size == 0) { | |
377ef731 | 11865 | /* NOT */ |
86cbc418 PM |
11866 | break; |
11867 | } else if (u && size == 1) { | |
11868 | /* RBIT */ | |
11869 | break; | |
11870 | } else if (!u && size == 0) { | |
11871 | /* CNT */ | |
11872 | break; | |
45aecc6d | 11873 | } |
86cbc418 | 11874 | unallocated_encoding(s); |
45aecc6d | 11875 | return; |
d980fd59 PM |
11876 | case 0x12: /* XTN, XTN2, SQXTUN, SQXTUN2 */ |
11877 | case 0x14: /* SQXTN, SQXTN2, UQXTN, UQXTN2 */ | |
11878 | if (size == 3) { | |
11879 | unallocated_encoding(s); | |
11880 | return; | |
11881 | } | |
8c6afa6a PM |
11882 | if (!fp_access_check(s)) { |
11883 | return; | |
11884 | } | |
11885 | ||
5201c136 | 11886 | handle_2misc_narrow(s, false, opcode, u, is_q, size, rn, rd); |
d980fd59 | 11887 | return; |
45aecc6d | 11888 | case 0x4: /* CLS, CLZ */ |
b05c3068 AB |
11889 | if (size == 3) { |
11890 | unallocated_encoding(s); | |
11891 | return; | |
11892 | } | |
11893 | break; | |
11894 | case 0x2: /* SADDLP, UADDLP */ | |
45aecc6d | 11895 | case 0x6: /* SADALP, UADALP */ |
45aecc6d PM |
11896 | if (size == 3) { |
11897 | unallocated_encoding(s); | |
11898 | return; | |
11899 | } | |
8c6afa6a PM |
11900 | if (!fp_access_check(s)) { |
11901 | return; | |
11902 | } | |
6781fa11 | 11903 | handle_2misc_pairwise(s, opcode, u, is_q, size, rn, rd); |
45aecc6d PM |
11904 | return; |
11905 | case 0x13: /* SHLL, SHLL2 */ | |
11906 | if (u == 0 || size == 3) { | |
11907 | unallocated_encoding(s); | |
11908 | return; | |
11909 | } | |
8c6afa6a PM |
11910 | if (!fp_access_check(s)) { |
11911 | return; | |
11912 | } | |
73a81d10 | 11913 | handle_shll(s, is_q, size, rn, rd); |
45aecc6d PM |
11914 | return; |
11915 | case 0xa: /* CMLT */ | |
11916 | if (u == 1) { | |
11917 | unallocated_encoding(s); | |
11918 | return; | |
11919 | } | |
11920 | /* fall through */ | |
45aecc6d PM |
11921 | case 0x8: /* CMGT, CMGE */ |
11922 | case 0x9: /* CMEQ, CMLE */ | |
11923 | case 0xb: /* ABS, NEG */ | |
94b6c911 PM |
11924 | if (size == 3 && !is_q) { |
11925 | unallocated_encoding(s); | |
11926 | return; | |
11927 | } | |
11928 | break; | |
11929 | case 0x3: /* SUQADD, USQADD */ | |
09e03735 AB |
11930 | if (size == 3 && !is_q) { |
11931 | unallocated_encoding(s); | |
11932 | return; | |
11933 | } | |
8c6afa6a PM |
11934 | if (!fp_access_check(s)) { |
11935 | return; | |
11936 | } | |
09e03735 AB |
11937 | handle_2misc_satacc(s, false, u, is_q, size, rn, rd); |
11938 | return; | |
94b6c911 | 11939 | case 0x7: /* SQABS, SQNEG */ |
45aecc6d PM |
11940 | if (size == 3 && !is_q) { |
11941 | unallocated_encoding(s); | |
11942 | return; | |
11943 | } | |
0a79bc87 | 11944 | break; |
45aecc6d PM |
11945 | case 0xc ... 0xf: |
11946 | case 0x16 ... 0x1d: | |
11947 | case 0x1f: | |
11948 | { | |
11949 | /* Floating point: U, size[1] and opcode indicate operation; | |
11950 | * size[0] indicates single or double precision. | |
11951 | */ | |
10113b69 | 11952 | int is_double = extract32(size, 0, 1); |
45aecc6d | 11953 | opcode |= (extract32(size, 1, 1) << 5) | (u << 6); |
10113b69 | 11954 | size = is_double ? 3 : 2; |
45aecc6d | 11955 | switch (opcode) { |
f93d0138 PM |
11956 | case 0x2f: /* FABS */ |
11957 | case 0x6f: /* FNEG */ | |
11958 | if (size == 3 && !is_q) { | |
11959 | unallocated_encoding(s); | |
11960 | return; | |
11961 | } | |
11962 | break; | |
10113b69 AB |
11963 | case 0x1d: /* SCVTF */ |
11964 | case 0x5d: /* UCVTF */ | |
11965 | { | |
11966 | bool is_signed = (opcode == 0x1d) ? true : false; | |
11967 | int elements = is_double ? 2 : is_q ? 4 : 2; | |
11968 | if (is_double && !is_q) { | |
11969 | unallocated_encoding(s); | |
11970 | return; | |
11971 | } | |
8c6afa6a PM |
11972 | if (!fp_access_check(s)) { |
11973 | return; | |
11974 | } | |
10113b69 AB |
11975 | handle_simd_intfp_conv(s, rd, rn, elements, is_signed, 0, size); |
11976 | return; | |
11977 | } | |
8908f4d1 AB |
11978 | case 0x2c: /* FCMGT (zero) */ |
11979 | case 0x2d: /* FCMEQ (zero) */ | |
11980 | case 0x2e: /* FCMLT (zero) */ | |
11981 | case 0x6c: /* FCMGE (zero) */ | |
11982 | case 0x6d: /* FCMLE (zero) */ | |
11983 | if (size == 3 && !is_q) { | |
11984 | unallocated_encoding(s); | |
11985 | return; | |
11986 | } | |
11987 | handle_2misc_fcmp_zero(s, opcode, false, u, is_q, size, rn, rd); | |
11988 | return; | |
f612537e AB |
11989 | case 0x7f: /* FSQRT */ |
11990 | if (size == 3 && !is_q) { | |
11991 | unallocated_encoding(s); | |
11992 | return; | |
11993 | } | |
11994 | break; | |
04c7c6c2 PM |
11995 | case 0x1a: /* FCVTNS */ |
11996 | case 0x1b: /* FCVTMS */ | |
11997 | case 0x3a: /* FCVTPS */ | |
11998 | case 0x3b: /* FCVTZS */ | |
11999 | case 0x5a: /* FCVTNU */ | |
12000 | case 0x5b: /* FCVTMU */ | |
12001 | case 0x7a: /* FCVTPU */ | |
12002 | case 0x7b: /* FCVTZU */ | |
12003 | need_fpstatus = true; | |
12004 | need_rmode = true; | |
12005 | rmode = extract32(opcode, 5, 1) | (extract32(opcode, 0, 1) << 1); | |
12006 | if (size == 3 && !is_q) { | |
12007 | unallocated_encoding(s); | |
12008 | return; | |
12009 | } | |
12010 | break; | |
12011 | case 0x5c: /* FCVTAU */ | |
12012 | case 0x1c: /* FCVTAS */ | |
12013 | need_fpstatus = true; | |
12014 | need_rmode = true; | |
12015 | rmode = FPROUNDING_TIEAWAY; | |
12016 | if (size == 3 && !is_q) { | |
12017 | unallocated_encoding(s); | |
12018 | return; | |
12019 | } | |
12020 | break; | |
b6d4443a AB |
12021 | case 0x3c: /* URECPE */ |
12022 | if (size == 3) { | |
12023 | unallocated_encoding(s); | |
12024 | return; | |
12025 | } | |
12026 | /* fall through */ | |
12027 | case 0x3d: /* FRECPE */ | |
c2fb418e AB |
12028 | case 0x7d: /* FRSQRTE */ |
12029 | if (size == 3 && !is_q) { | |
12030 | unallocated_encoding(s); | |
12031 | return; | |
12032 | } | |
8c6afa6a PM |
12033 | if (!fp_access_check(s)) { |
12034 | return; | |
12035 | } | |
b6d4443a AB |
12036 | handle_2misc_reciprocal(s, opcode, false, u, is_q, size, rn, rd); |
12037 | return; | |
5553955e PM |
12038 | case 0x56: /* FCVTXN, FCVTXN2 */ |
12039 | if (size == 2) { | |
12040 | unallocated_encoding(s); | |
12041 | return; | |
12042 | } | |
12043 | /* fall through */ | |
45aecc6d | 12044 | case 0x16: /* FCVTN, FCVTN2 */ |
261a5b4d PM |
12045 | /* handle_2misc_narrow does a 2*size -> size operation, but these |
12046 | * instructions encode the source size rather than dest size. | |
12047 | */ | |
8c6afa6a PM |
12048 | if (!fp_access_check(s)) { |
12049 | return; | |
12050 | } | |
5201c136 | 12051 | handle_2misc_narrow(s, false, opcode, 0, is_q, size - 1, rn, rd); |
261a5b4d | 12052 | return; |
45aecc6d | 12053 | case 0x17: /* FCVTL, FCVTL2 */ |
8c6afa6a PM |
12054 | if (!fp_access_check(s)) { |
12055 | return; | |
12056 | } | |
931c8cc2 PM |
12057 | handle_2misc_widening(s, opcode, is_q, size, rn, rd); |
12058 | return; | |
45aecc6d PM |
12059 | case 0x18: /* FRINTN */ |
12060 | case 0x19: /* FRINTM */ | |
45aecc6d PM |
12061 | case 0x38: /* FRINTP */ |
12062 | case 0x39: /* FRINTZ */ | |
03df01ed PM |
12063 | need_rmode = true; |
12064 | rmode = extract32(opcode, 5, 1) | (extract32(opcode, 0, 1) << 1); | |
12065 | /* fall through */ | |
12066 | case 0x59: /* FRINTX */ | |
12067 | case 0x79: /* FRINTI */ | |
12068 | need_fpstatus = true; | |
12069 | if (size == 3 && !is_q) { | |
12070 | unallocated_encoding(s); | |
12071 | return; | |
12072 | } | |
12073 | break; | |
12074 | case 0x58: /* FRINTA */ | |
12075 | need_rmode = true; | |
12076 | rmode = FPROUNDING_TIEAWAY; | |
12077 | need_fpstatus = true; | |
12078 | if (size == 3 && !is_q) { | |
12079 | unallocated_encoding(s); | |
12080 | return; | |
12081 | } | |
12082 | break; | |
45aecc6d | 12083 | case 0x7c: /* URSQRTE */ |
c2fb418e AB |
12084 | if (size == 3) { |
12085 | unallocated_encoding(s); | |
12086 | return; | |
12087 | } | |
12088 | need_fpstatus = true; | |
12089 | break; | |
45aecc6d PM |
12090 | default: |
12091 | unallocated_encoding(s); | |
12092 | return; | |
12093 | } | |
12094 | break; | |
12095 | } | |
12096 | default: | |
12097 | unallocated_encoding(s); | |
12098 | return; | |
12099 | } | |
94b6c911 | 12100 | |
8c6afa6a PM |
12101 | if (!fp_access_check(s)) { |
12102 | return; | |
12103 | } | |
12104 | ||
9b049916 | 12105 | if (need_fpstatus || need_rmode) { |
d81ce0ef | 12106 | tcg_fpstatus = get_fpstatus_ptr(false); |
04c7c6c2 | 12107 | } else { |
f764718d | 12108 | tcg_fpstatus = NULL; |
04c7c6c2 PM |
12109 | } |
12110 | if (need_rmode) { | |
12111 | tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode)); | |
9b049916 | 12112 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); |
04c7c6c2 | 12113 | } else { |
f764718d | 12114 | tcg_rmode = NULL; |
04c7c6c2 PM |
12115 | } |
12116 | ||
377ef731 RH |
12117 | switch (opcode) { |
12118 | case 0x5: | |
12119 | if (u && size == 0) { /* NOT */ | |
12120 | gen_gvec_fn2(s, is_q, rd, rn, tcg_gen_gvec_not, 0); | |
12121 | return; | |
12122 | } | |
12123 | break; | |
12124 | case 0xb: | |
12125 | if (u) { /* NEG */ | |
12126 | gen_gvec_fn2(s, is_q, rd, rn, tcg_gen_gvec_neg, size); | |
12127 | return; | |
12128 | } | |
12129 | break; | |
12130 | } | |
12131 | ||
94b6c911 PM |
12132 | if (size == 3) { |
12133 | /* All 64-bit element operations can be shared with scalar 2misc */ | |
12134 | int pass; | |
12135 | ||
a8766e31 RH |
12136 | /* Coverity claims (size == 3 && !is_q) has been eliminated |
12137 | * from all paths leading to here. | |
12138 | */ | |
12139 | tcg_debug_assert(is_q); | |
12140 | for (pass = 0; pass < 2; pass++) { | |
94b6c911 PM |
12141 | TCGv_i64 tcg_op = tcg_temp_new_i64(); |
12142 | TCGv_i64 tcg_res = tcg_temp_new_i64(); | |
12143 | ||
12144 | read_vec_element(s, tcg_op, rn, pass, MO_64); | |
12145 | ||
04c7c6c2 PM |
12146 | handle_2misc_64(s, opcode, u, tcg_res, tcg_op, |
12147 | tcg_rmode, tcg_fpstatus); | |
94b6c911 PM |
12148 | |
12149 | write_vec_element(s, tcg_res, rd, pass, MO_64); | |
12150 | ||
12151 | tcg_temp_free_i64(tcg_res); | |
12152 | tcg_temp_free_i64(tcg_op); | |
12153 | } | |
12154 | } else { | |
12155 | int pass; | |
12156 | ||
12157 | for (pass = 0; pass < (is_q ? 4 : 2); pass++) { | |
12158 | TCGv_i32 tcg_op = tcg_temp_new_i32(); | |
12159 | TCGv_i32 tcg_res = tcg_temp_new_i32(); | |
12160 | TCGCond cond; | |
12161 | ||
12162 | read_vec_element_i32(s, tcg_op, rn, pass, MO_32); | |
12163 | ||
12164 | if (size == 2) { | |
12165 | /* Special cases for 32 bit elements */ | |
12166 | switch (opcode) { | |
12167 | case 0xa: /* CMLT */ | |
12168 | /* 32 bit integer comparison against zero, result is | |
12169 | * test ? (2^32 - 1) : 0. We implement via setcond(test) | |
12170 | * and inverting. | |
12171 | */ | |
12172 | cond = TCG_COND_LT; | |
12173 | do_cmop: | |
12174 | tcg_gen_setcondi_i32(cond, tcg_res, tcg_op, 0); | |
12175 | tcg_gen_neg_i32(tcg_res, tcg_res); | |
12176 | break; | |
12177 | case 0x8: /* CMGT, CMGE */ | |
12178 | cond = u ? TCG_COND_GE : TCG_COND_GT; | |
12179 | goto do_cmop; | |
12180 | case 0x9: /* CMEQ, CMLE */ | |
12181 | cond = u ? TCG_COND_LE : TCG_COND_EQ; | |
12182 | goto do_cmop; | |
b05c3068 AB |
12183 | case 0x4: /* CLS */ |
12184 | if (u) { | |
7539a012 | 12185 | tcg_gen_clzi_i32(tcg_res, tcg_op, 32); |
b05c3068 | 12186 | } else { |
bc21dbcc | 12187 | tcg_gen_clrsb_i32(tcg_res, tcg_op); |
b05c3068 AB |
12188 | } |
12189 | break; | |
0a79bc87 AB |
12190 | case 0x7: /* SQABS, SQNEG */ |
12191 | if (u) { | |
12192 | gen_helper_neon_qneg_s32(tcg_res, cpu_env, tcg_op); | |
12193 | } else { | |
12194 | gen_helper_neon_qabs_s32(tcg_res, cpu_env, tcg_op); | |
12195 | } | |
12196 | break; | |
94b6c911 PM |
12197 | case 0xb: /* ABS, NEG */ |
12198 | if (u) { | |
12199 | tcg_gen_neg_i32(tcg_res, tcg_op); | |
12200 | } else { | |
12201 | TCGv_i32 tcg_zero = tcg_const_i32(0); | |
12202 | tcg_gen_neg_i32(tcg_res, tcg_op); | |
12203 | tcg_gen_movcond_i32(TCG_COND_GT, tcg_res, tcg_op, | |
12204 | tcg_zero, tcg_op, tcg_res); | |
12205 | tcg_temp_free_i32(tcg_zero); | |
12206 | } | |
12207 | break; | |
f93d0138 PM |
12208 | case 0x2f: /* FABS */ |
12209 | gen_helper_vfp_abss(tcg_res, tcg_op); | |
12210 | break; | |
12211 | case 0x6f: /* FNEG */ | |
12212 | gen_helper_vfp_negs(tcg_res, tcg_op); | |
12213 | break; | |
f612537e AB |
12214 | case 0x7f: /* FSQRT */ |
12215 | gen_helper_vfp_sqrts(tcg_res, tcg_op, cpu_env); | |
12216 | break; | |
04c7c6c2 PM |
12217 | case 0x1a: /* FCVTNS */ |
12218 | case 0x1b: /* FCVTMS */ | |
12219 | case 0x1c: /* FCVTAS */ | |
12220 | case 0x3a: /* FCVTPS */ | |
12221 | case 0x3b: /* FCVTZS */ | |
12222 | { | |
12223 | TCGv_i32 tcg_shift = tcg_const_i32(0); | |
12224 | gen_helper_vfp_tosls(tcg_res, tcg_op, | |
12225 | tcg_shift, tcg_fpstatus); | |
12226 | tcg_temp_free_i32(tcg_shift); | |
12227 | break; | |
12228 | } | |
12229 | case 0x5a: /* FCVTNU */ | |
12230 | case 0x5b: /* FCVTMU */ | |
12231 | case 0x5c: /* FCVTAU */ | |
12232 | case 0x7a: /* FCVTPU */ | |
12233 | case 0x7b: /* FCVTZU */ | |
12234 | { | |
12235 | TCGv_i32 tcg_shift = tcg_const_i32(0); | |
12236 | gen_helper_vfp_touls(tcg_res, tcg_op, | |
12237 | tcg_shift, tcg_fpstatus); | |
12238 | tcg_temp_free_i32(tcg_shift); | |
12239 | break; | |
12240 | } | |
03df01ed PM |
12241 | case 0x18: /* FRINTN */ |
12242 | case 0x19: /* FRINTM */ | |
12243 | case 0x38: /* FRINTP */ | |
12244 | case 0x39: /* FRINTZ */ | |
12245 | case 0x58: /* FRINTA */ | |
12246 | case 0x79: /* FRINTI */ | |
12247 | gen_helper_rints(tcg_res, tcg_op, tcg_fpstatus); | |
12248 | break; | |
12249 | case 0x59: /* FRINTX */ | |
12250 | gen_helper_rints_exact(tcg_res, tcg_op, tcg_fpstatus); | |
12251 | break; | |
c2fb418e AB |
12252 | case 0x7c: /* URSQRTE */ |
12253 | gen_helper_rsqrte_u32(tcg_res, tcg_op, tcg_fpstatus); | |
12254 | break; | |
94b6c911 PM |
12255 | default: |
12256 | g_assert_not_reached(); | |
12257 | } | |
12258 | } else { | |
12259 | /* Use helpers for 8 and 16 bit elements */ | |
12260 | switch (opcode) { | |
86cbc418 PM |
12261 | case 0x5: /* CNT, RBIT */ |
12262 | /* For these two insns size is part of the opcode specifier | |
12263 | * (handled earlier); they always operate on byte elements. | |
12264 | */ | |
12265 | if (u) { | |
12266 | gen_helper_neon_rbit_u8(tcg_res, tcg_op); | |
12267 | } else { | |
12268 | gen_helper_neon_cnt_u8(tcg_res, tcg_op); | |
12269 | } | |
12270 | break; | |
0a79bc87 AB |
12271 | case 0x7: /* SQABS, SQNEG */ |
12272 | { | |
12273 | NeonGenOneOpEnvFn *genfn; | |
12274 | static NeonGenOneOpEnvFn * const fns[2][2] = { | |
12275 | { gen_helper_neon_qabs_s8, gen_helper_neon_qneg_s8 }, | |
12276 | { gen_helper_neon_qabs_s16, gen_helper_neon_qneg_s16 }, | |
12277 | }; | |
12278 | genfn = fns[size][u]; | |
12279 | genfn(tcg_res, cpu_env, tcg_op); | |
12280 | break; | |
12281 | } | |
94b6c911 PM |
12282 | case 0x8: /* CMGT, CMGE */ |
12283 | case 0x9: /* CMEQ, CMLE */ | |
12284 | case 0xa: /* CMLT */ | |
12285 | { | |
12286 | static NeonGenTwoOpFn * const fns[3][2] = { | |
12287 | { gen_helper_neon_cgt_s8, gen_helper_neon_cgt_s16 }, | |
12288 | { gen_helper_neon_cge_s8, gen_helper_neon_cge_s16 }, | |
12289 | { gen_helper_neon_ceq_u8, gen_helper_neon_ceq_u16 }, | |
12290 | }; | |
12291 | NeonGenTwoOpFn *genfn; | |
12292 | int comp; | |
12293 | bool reverse; | |
12294 | TCGv_i32 tcg_zero = tcg_const_i32(0); | |
12295 | ||
12296 | /* comp = index into [CMGT, CMGE, CMEQ, CMLE, CMLT] */ | |
12297 | comp = (opcode - 0x8) * 2 + u; | |
12298 | /* ...but LE, LT are implemented as reverse GE, GT */ | |
12299 | reverse = (comp > 2); | |
12300 | if (reverse) { | |
12301 | comp = 4 - comp; | |
12302 | } | |
12303 | genfn = fns[comp][size]; | |
12304 | if (reverse) { | |
12305 | genfn(tcg_res, tcg_zero, tcg_op); | |
12306 | } else { | |
12307 | genfn(tcg_res, tcg_op, tcg_zero); | |
12308 | } | |
12309 | tcg_temp_free_i32(tcg_zero); | |
12310 | break; | |
12311 | } | |
12312 | case 0xb: /* ABS, NEG */ | |
12313 | if (u) { | |
12314 | TCGv_i32 tcg_zero = tcg_const_i32(0); | |
12315 | if (size) { | |
12316 | gen_helper_neon_sub_u16(tcg_res, tcg_zero, tcg_op); | |
12317 | } else { | |
12318 | gen_helper_neon_sub_u8(tcg_res, tcg_zero, tcg_op); | |
12319 | } | |
12320 | tcg_temp_free_i32(tcg_zero); | |
12321 | } else { | |
12322 | if (size) { | |
12323 | gen_helper_neon_abs_s16(tcg_res, tcg_op); | |
12324 | } else { | |
12325 | gen_helper_neon_abs_s8(tcg_res, tcg_op); | |
12326 | } | |
12327 | } | |
12328 | break; | |
b05c3068 AB |
12329 | case 0x4: /* CLS, CLZ */ |
12330 | if (u) { | |
12331 | if (size == 0) { | |
12332 | gen_helper_neon_clz_u8(tcg_res, tcg_op); | |
12333 | } else { | |
12334 | gen_helper_neon_clz_u16(tcg_res, tcg_op); | |
12335 | } | |
12336 | } else { | |
12337 | if (size == 0) { | |
12338 | gen_helper_neon_cls_s8(tcg_res, tcg_op); | |
12339 | } else { | |
12340 | gen_helper_neon_cls_s16(tcg_res, tcg_op); | |
12341 | } | |
12342 | } | |
12343 | break; | |
94b6c911 PM |
12344 | default: |
12345 | g_assert_not_reached(); | |
12346 | } | |
12347 | } | |
12348 | ||
12349 | write_vec_element_i32(s, tcg_res, rd, pass, MO_32); | |
12350 | ||
12351 | tcg_temp_free_i32(tcg_res); | |
12352 | tcg_temp_free_i32(tcg_op); | |
12353 | } | |
12354 | } | |
4ff55bcb | 12355 | clear_vec_high(s, is_q, rd); |
04c7c6c2 PM |
12356 | |
12357 | if (need_rmode) { | |
9b049916 | 12358 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); |
04c7c6c2 PM |
12359 | tcg_temp_free_i32(tcg_rmode); |
12360 | } | |
12361 | if (need_fpstatus) { | |
12362 | tcg_temp_free_ptr(tcg_fpstatus); | |
12363 | } | |
384b26fb AB |
12364 | } |
12365 | ||
5d432be6 AB |
12366 | /* AdvSIMD [scalar] two register miscellaneous (FP16) |
12367 | * | |
12368 | * 31 30 29 28 27 24 23 22 21 17 16 12 11 10 9 5 4 0 | |
12369 | * +---+---+---+---+---------+---+-------------+--------+-----+------+------+ | |
12370 | * | 0 | Q | U | S | 1 1 1 0 | a | 1 1 1 1 0 0 | opcode | 1 0 | Rn | Rd | | |
12371 | * +---+---+---+---+---------+---+-------------+--------+-----+------+------+ | |
12372 | * mask: 1000 1111 0111 1110 0000 1100 0000 0000 0x8f7e 0c00 | |
12373 | * val: 0000 1110 0111 1000 0000 1000 0000 0000 0x0e78 0800 | |
12374 | * | |
12375 | * This actually covers two groups where scalar access is governed by | |
12376 | * bit 28. A bunch of the instructions (float to integral) only exist | |
12377 | * in the vector form and are un-allocated for the scalar decode. Also | |
12378 | * in the scalar decode Q is always 1. | |
12379 | */ | |
12380 | static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn) | |
12381 | { | |
6109aea2 AB |
12382 | int fpop, opcode, a, u; |
12383 | int rn, rd; | |
12384 | bool is_q; | |
12385 | bool is_scalar; | |
12386 | bool only_in_vector = false; | |
12387 | ||
12388 | int pass; | |
12389 | TCGv_i32 tcg_rmode = NULL; | |
12390 | TCGv_ptr tcg_fpstatus = NULL; | |
12391 | bool need_rmode = false; | |
15f8a233 | 12392 | bool need_fpst = true; |
6109aea2 | 12393 | int rmode; |
5d432be6 | 12394 | |
5763190f | 12395 | if (!dc_isar_feature(aa64_fp16, s)) { |
5d432be6 AB |
12396 | unallocated_encoding(s); |
12397 | return; | |
12398 | } | |
12399 | ||
6109aea2 AB |
12400 | rd = extract32(insn, 0, 5); |
12401 | rn = extract32(insn, 5, 5); | |
5d432be6 | 12402 | |
5d432be6 | 12403 | a = extract32(insn, 23, 1); |
6109aea2 AB |
12404 | u = extract32(insn, 29, 1); |
12405 | is_scalar = extract32(insn, 28, 1); | |
12406 | is_q = extract32(insn, 30, 1); | |
12407 | ||
12408 | opcode = extract32(insn, 12, 5); | |
5d432be6 | 12409 | fpop = deposit32(opcode, 5, 1, a); |
6109aea2 | 12410 | fpop = deposit32(fpop, 6, 1, u); |
5d432be6 | 12411 | |
7d4dd1a7 AB |
12412 | rd = extract32(insn, 0, 5); |
12413 | rn = extract32(insn, 5, 5); | |
12414 | ||
5d432be6 | 12415 | switch (fpop) { |
93193190 AB |
12416 | case 0x1d: /* SCVTF */ |
12417 | case 0x5d: /* UCVTF */ | |
12418 | { | |
12419 | int elements; | |
12420 | ||
12421 | if (is_scalar) { | |
12422 | elements = 1; | |
12423 | } else { | |
12424 | elements = (is_q ? 8 : 4); | |
12425 | } | |
12426 | ||
12427 | if (!fp_access_check(s)) { | |
12428 | return; | |
12429 | } | |
12430 | handle_simd_intfp_conv(s, rd, rn, elements, !u, 0, MO_16); | |
12431 | return; | |
12432 | } | |
7d4dd1a7 AB |
12433 | break; |
12434 | case 0x2c: /* FCMGT (zero) */ | |
12435 | case 0x2d: /* FCMEQ (zero) */ | |
12436 | case 0x2e: /* FCMLT (zero) */ | |
12437 | case 0x6c: /* FCMGE (zero) */ | |
12438 | case 0x6d: /* FCMLE (zero) */ | |
12439 | handle_2misc_fcmp_zero(s, fpop, is_scalar, 0, is_q, MO_16, rn, rd); | |
12440 | return; | |
fbd06e1e | 12441 | case 0x3d: /* FRECPE */ |
98695028 | 12442 | case 0x3f: /* FRECPX */ |
fbd06e1e | 12443 | break; |
6109aea2 AB |
12444 | case 0x18: /* FRINTN */ |
12445 | need_rmode = true; | |
12446 | only_in_vector = true; | |
12447 | rmode = FPROUNDING_TIEEVEN; | |
12448 | break; | |
12449 | case 0x19: /* FRINTM */ | |
12450 | need_rmode = true; | |
12451 | only_in_vector = true; | |
12452 | rmode = FPROUNDING_NEGINF; | |
12453 | break; | |
12454 | case 0x38: /* FRINTP */ | |
12455 | need_rmode = true; | |
12456 | only_in_vector = true; | |
12457 | rmode = FPROUNDING_POSINF; | |
12458 | break; | |
12459 | case 0x39: /* FRINTZ */ | |
12460 | need_rmode = true; | |
12461 | only_in_vector = true; | |
12462 | rmode = FPROUNDING_ZERO; | |
12463 | break; | |
12464 | case 0x58: /* FRINTA */ | |
12465 | need_rmode = true; | |
12466 | only_in_vector = true; | |
12467 | rmode = FPROUNDING_TIEAWAY; | |
12468 | break; | |
12469 | case 0x59: /* FRINTX */ | |
12470 | case 0x79: /* FRINTI */ | |
12471 | only_in_vector = true; | |
12472 | /* current rounding mode */ | |
12473 | break; | |
2df58130 AB |
12474 | case 0x1a: /* FCVTNS */ |
12475 | need_rmode = true; | |
12476 | rmode = FPROUNDING_TIEEVEN; | |
12477 | break; | |
12478 | case 0x1b: /* FCVTMS */ | |
12479 | need_rmode = true; | |
12480 | rmode = FPROUNDING_NEGINF; | |
12481 | break; | |
12482 | case 0x1c: /* FCVTAS */ | |
12483 | need_rmode = true; | |
12484 | rmode = FPROUNDING_TIEAWAY; | |
12485 | break; | |
12486 | case 0x3a: /* FCVTPS */ | |
12487 | need_rmode = true; | |
12488 | rmode = FPROUNDING_POSINF; | |
12489 | break; | |
12490 | case 0x3b: /* FCVTZS */ | |
12491 | need_rmode = true; | |
12492 | rmode = FPROUNDING_ZERO; | |
12493 | break; | |
12494 | case 0x5a: /* FCVTNU */ | |
12495 | need_rmode = true; | |
12496 | rmode = FPROUNDING_TIEEVEN; | |
12497 | break; | |
12498 | case 0x5b: /* FCVTMU */ | |
12499 | need_rmode = true; | |
12500 | rmode = FPROUNDING_NEGINF; | |
12501 | break; | |
12502 | case 0x5c: /* FCVTAU */ | |
12503 | need_rmode = true; | |
12504 | rmode = FPROUNDING_TIEAWAY; | |
12505 | break; | |
12506 | case 0x7a: /* FCVTPU */ | |
12507 | need_rmode = true; | |
12508 | rmode = FPROUNDING_POSINF; | |
12509 | break; | |
12510 | case 0x7b: /* FCVTZU */ | |
12511 | need_rmode = true; | |
12512 | rmode = FPROUNDING_ZERO; | |
12513 | break; | |
15f8a233 AB |
12514 | case 0x2f: /* FABS */ |
12515 | case 0x6f: /* FNEG */ | |
12516 | need_fpst = false; | |
12517 | break; | |
c625ff95 | 12518 | case 0x7d: /* FRSQRTE */ |
b96a54c7 AB |
12519 | case 0x7f: /* FSQRT (vector) */ |
12520 | break; | |
5d432be6 AB |
12521 | default: |
12522 | fprintf(stderr, "%s: insn %#04x fpop %#2x\n", __func__, insn, fpop); | |
12523 | g_assert_not_reached(); | |
12524 | } | |
12525 | ||
6109aea2 AB |
12526 | |
12527 | /* Check additional constraints for the scalar encoding */ | |
12528 | if (is_scalar) { | |
12529 | if (!is_q) { | |
12530 | unallocated_encoding(s); | |
12531 | return; | |
12532 | } | |
12533 | /* FRINTxx is only in the vector form */ | |
12534 | if (only_in_vector) { | |
12535 | unallocated_encoding(s); | |
12536 | return; | |
12537 | } | |
12538 | } | |
12539 | ||
12540 | if (!fp_access_check(s)) { | |
12541 | return; | |
12542 | } | |
12543 | ||
15f8a233 | 12544 | if (need_rmode || need_fpst) { |
6109aea2 AB |
12545 | tcg_fpstatus = get_fpstatus_ptr(true); |
12546 | } | |
12547 | ||
12548 | if (need_rmode) { | |
12549 | tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode)); | |
12550 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); | |
12551 | } | |
12552 | ||
12553 | if (is_scalar) { | |
3d99d931 | 12554 | TCGv_i32 tcg_op = read_fp_hreg(s, rn); |
2df58130 AB |
12555 | TCGv_i32 tcg_res = tcg_temp_new_i32(); |
12556 | ||
2df58130 AB |
12557 | switch (fpop) { |
12558 | case 0x1a: /* FCVTNS */ | |
12559 | case 0x1b: /* FCVTMS */ | |
12560 | case 0x1c: /* FCVTAS */ | |
12561 | case 0x3a: /* FCVTPS */ | |
12562 | case 0x3b: /* FCVTZS */ | |
12563 | gen_helper_advsimd_f16tosinth(tcg_res, tcg_op, tcg_fpstatus); | |
12564 | break; | |
fbd06e1e AB |
12565 | case 0x3d: /* FRECPE */ |
12566 | gen_helper_recpe_f16(tcg_res, tcg_op, tcg_fpstatus); | |
12567 | break; | |
98695028 AB |
12568 | case 0x3f: /* FRECPX */ |
12569 | gen_helper_frecpx_f16(tcg_res, tcg_op, tcg_fpstatus); | |
12570 | break; | |
2df58130 AB |
12571 | case 0x5a: /* FCVTNU */ |
12572 | case 0x5b: /* FCVTMU */ | |
12573 | case 0x5c: /* FCVTAU */ | |
12574 | case 0x7a: /* FCVTPU */ | |
12575 | case 0x7b: /* FCVTZU */ | |
12576 | gen_helper_advsimd_f16touinth(tcg_res, tcg_op, tcg_fpstatus); | |
12577 | break; | |
15f8a233 AB |
12578 | case 0x6f: /* FNEG */ |
12579 | tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000); | |
12580 | break; | |
c625ff95 AB |
12581 | case 0x7d: /* FRSQRTE */ |
12582 | gen_helper_rsqrte_f16(tcg_res, tcg_op, tcg_fpstatus); | |
12583 | break; | |
2df58130 AB |
12584 | default: |
12585 | g_assert_not_reached(); | |
12586 | } | |
12587 | ||
12588 | /* limit any sign extension going on */ | |
12589 | tcg_gen_andi_i32(tcg_res, tcg_res, 0xffff); | |
12590 | write_fp_sreg(s, rd, tcg_res); | |
12591 | ||
12592 | tcg_temp_free_i32(tcg_res); | |
12593 | tcg_temp_free_i32(tcg_op); | |
6109aea2 AB |
12594 | } else { |
12595 | for (pass = 0; pass < (is_q ? 8 : 4); pass++) { | |
12596 | TCGv_i32 tcg_op = tcg_temp_new_i32(); | |
12597 | TCGv_i32 tcg_res = tcg_temp_new_i32(); | |
12598 | ||
12599 | read_vec_element_i32(s, tcg_op, rn, pass, MO_16); | |
12600 | ||
12601 | switch (fpop) { | |
2df58130 AB |
12602 | case 0x1a: /* FCVTNS */ |
12603 | case 0x1b: /* FCVTMS */ | |
12604 | case 0x1c: /* FCVTAS */ | |
12605 | case 0x3a: /* FCVTPS */ | |
12606 | case 0x3b: /* FCVTZS */ | |
12607 | gen_helper_advsimd_f16tosinth(tcg_res, tcg_op, tcg_fpstatus); | |
12608 | break; | |
fbd06e1e AB |
12609 | case 0x3d: /* FRECPE */ |
12610 | gen_helper_recpe_f16(tcg_res, tcg_op, tcg_fpstatus); | |
12611 | break; | |
2df58130 AB |
12612 | case 0x5a: /* FCVTNU */ |
12613 | case 0x5b: /* FCVTMU */ | |
12614 | case 0x5c: /* FCVTAU */ | |
12615 | case 0x7a: /* FCVTPU */ | |
12616 | case 0x7b: /* FCVTZU */ | |
12617 | gen_helper_advsimd_f16touinth(tcg_res, tcg_op, tcg_fpstatus); | |
12618 | break; | |
6109aea2 AB |
12619 | case 0x18: /* FRINTN */ |
12620 | case 0x19: /* FRINTM */ | |
12621 | case 0x38: /* FRINTP */ | |
12622 | case 0x39: /* FRINTZ */ | |
12623 | case 0x58: /* FRINTA */ | |
12624 | case 0x79: /* FRINTI */ | |
12625 | gen_helper_advsimd_rinth(tcg_res, tcg_op, tcg_fpstatus); | |
12626 | break; | |
12627 | case 0x59: /* FRINTX */ | |
12628 | gen_helper_advsimd_rinth_exact(tcg_res, tcg_op, tcg_fpstatus); | |
12629 | break; | |
15f8a233 AB |
12630 | case 0x2f: /* FABS */ |
12631 | tcg_gen_andi_i32(tcg_res, tcg_op, 0x7fff); | |
12632 | break; | |
12633 | case 0x6f: /* FNEG */ | |
12634 | tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000); | |
12635 | break; | |
c625ff95 AB |
12636 | case 0x7d: /* FRSQRTE */ |
12637 | gen_helper_rsqrte_f16(tcg_res, tcg_op, tcg_fpstatus); | |
12638 | break; | |
b96a54c7 AB |
12639 | case 0x7f: /* FSQRT */ |
12640 | gen_helper_sqrt_f16(tcg_res, tcg_op, tcg_fpstatus); | |
12641 | break; | |
6109aea2 AB |
12642 | default: |
12643 | g_assert_not_reached(); | |
12644 | } | |
12645 | ||
12646 | write_vec_element_i32(s, tcg_res, rd, pass, MO_16); | |
12647 | ||
12648 | tcg_temp_free_i32(tcg_res); | |
12649 | tcg_temp_free_i32(tcg_op); | |
12650 | } | |
12651 | ||
12652 | clear_vec_high(s, is_q, rd); | |
12653 | } | |
12654 | ||
12655 | if (tcg_rmode) { | |
12656 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); | |
12657 | tcg_temp_free_i32(tcg_rmode); | |
12658 | } | |
12659 | ||
12660 | if (tcg_fpstatus) { | |
12661 | tcg_temp_free_ptr(tcg_fpstatus); | |
12662 | } | |
5d432be6 AB |
12663 | } |
12664 | ||
4ce31af4 | 12665 | /* AdvSIMD scalar x indexed element |
9f82e0ff PM |
12666 | * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0 |
12667 | * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+ | |
12668 | * | 0 1 | U | 1 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd | | |
12669 | * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+ | |
4ce31af4 | 12670 | * AdvSIMD vector x indexed element |
384b26fb AB |
12671 | * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0 |
12672 | * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+ | |
12673 | * | 0 | Q | U | 0 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd | | |
12674 | * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+ | |
12675 | */ | |
9f82e0ff | 12676 | static void disas_simd_indexed(DisasContext *s, uint32_t insn) |
384b26fb | 12677 | { |
f5e51e7f PM |
12678 | /* This encoding has two kinds of instruction: |
12679 | * normal, where we perform elt x idxelt => elt for each | |
12680 | * element in the vector | |
12681 | * long, where we perform elt x idxelt and generate a result of | |
12682 | * double the width of the input element | |
12683 | * The long ops have a 'part' specifier (ie come in INSN, INSN2 pairs). | |
12684 | */ | |
9f82e0ff | 12685 | bool is_scalar = extract32(insn, 28, 1); |
f5e51e7f PM |
12686 | bool is_q = extract32(insn, 30, 1); |
12687 | bool u = extract32(insn, 29, 1); | |
12688 | int size = extract32(insn, 22, 2); | |
12689 | int l = extract32(insn, 21, 1); | |
12690 | int m = extract32(insn, 20, 1); | |
12691 | /* Note that the Rm field here is only 4 bits, not 5 as it usually is */ | |
12692 | int rm = extract32(insn, 16, 4); | |
12693 | int opcode = extract32(insn, 12, 4); | |
12694 | int h = extract32(insn, 11, 1); | |
12695 | int rn = extract32(insn, 5, 5); | |
12696 | int rd = extract32(insn, 0, 5); | |
12697 | bool is_long = false; | |
d17b7cdc | 12698 | int is_fp = 0; |
5d265064 | 12699 | bool is_fp16 = false; |
f5e51e7f PM |
12700 | int index; |
12701 | TCGv_ptr fpst; | |
12702 | ||
5f81b1de RH |
12703 | switch (16 * u + opcode) { |
12704 | case 0x08: /* MUL */ | |
12705 | case 0x10: /* MLA */ | |
12706 | case 0x14: /* MLS */ | |
12707 | if (is_scalar) { | |
f5e51e7f PM |
12708 | unallocated_encoding(s); |
12709 | return; | |
12710 | } | |
12711 | break; | |
5f81b1de RH |
12712 | case 0x02: /* SMLAL, SMLAL2 */ |
12713 | case 0x12: /* UMLAL, UMLAL2 */ | |
12714 | case 0x06: /* SMLSL, SMLSL2 */ | |
12715 | case 0x16: /* UMLSL, UMLSL2 */ | |
12716 | case 0x0a: /* SMULL, SMULL2 */ | |
12717 | case 0x1a: /* UMULL, UMULL2 */ | |
9f82e0ff PM |
12718 | if (is_scalar) { |
12719 | unallocated_encoding(s); | |
12720 | return; | |
12721 | } | |
f5e51e7f PM |
12722 | is_long = true; |
12723 | break; | |
5f81b1de RH |
12724 | case 0x03: /* SQDMLAL, SQDMLAL2 */ |
12725 | case 0x07: /* SQDMLSL, SQDMLSL2 */ | |
12726 | case 0x0b: /* SQDMULL, SQDMULL2 */ | |
f5e51e7f | 12727 | is_long = true; |
f5e51e7f | 12728 | break; |
5f81b1de RH |
12729 | case 0x0c: /* SQDMULH */ |
12730 | case 0x0d: /* SQRDMULH */ | |
9f82e0ff | 12731 | break; |
5f81b1de RH |
12732 | case 0x01: /* FMLA */ |
12733 | case 0x05: /* FMLS */ | |
12734 | case 0x09: /* FMUL */ | |
12735 | case 0x19: /* FMULX */ | |
d17b7cdc | 12736 | is_fp = 1; |
f5e51e7f | 12737 | break; |
d345df7a RH |
12738 | case 0x1d: /* SQRDMLAH */ |
12739 | case 0x1f: /* SQRDMLSH */ | |
962fcbf2 | 12740 | if (!dc_isar_feature(aa64_rdm, s)) { |
d345df7a RH |
12741 | unallocated_encoding(s); |
12742 | return; | |
12743 | } | |
12744 | break; | |
26c470a7 RH |
12745 | case 0x0e: /* SDOT */ |
12746 | case 0x1e: /* UDOT */ | |
4977986c | 12747 | if (is_scalar || size != MO_32 || !dc_isar_feature(aa64_dp, s)) { |
26c470a7 RH |
12748 | unallocated_encoding(s); |
12749 | return; | |
12750 | } | |
12751 | break; | |
d17b7cdc RH |
12752 | case 0x11: /* FCMLA #0 */ |
12753 | case 0x13: /* FCMLA #90 */ | |
12754 | case 0x15: /* FCMLA #180 */ | |
12755 | case 0x17: /* FCMLA #270 */ | |
4dfabb6d | 12756 | if (is_scalar || !dc_isar_feature(aa64_fcma, s)) { |
d17b7cdc RH |
12757 | unallocated_encoding(s); |
12758 | return; | |
12759 | } | |
12760 | is_fp = 2; | |
12761 | break; | |
0caa5af8 RH |
12762 | case 0x00: /* FMLAL */ |
12763 | case 0x04: /* FMLSL */ | |
12764 | case 0x18: /* FMLAL2 */ | |
12765 | case 0x1c: /* FMLSL2 */ | |
12766 | if (is_scalar || size != MO_32 || !dc_isar_feature(aa64_fhm, s)) { | |
12767 | unallocated_encoding(s); | |
12768 | return; | |
12769 | } | |
12770 | size = MO_16; | |
12771 | /* is_fp, but we pass cpu_env not fp_status. */ | |
12772 | break; | |
f5e51e7f PM |
12773 | default: |
12774 | unallocated_encoding(s); | |
12775 | return; | |
12776 | } | |
12777 | ||
d17b7cdc RH |
12778 | switch (is_fp) { |
12779 | case 1: /* normal fp */ | |
5d265064 AB |
12780 | /* convert insn encoded size to TCGMemOp size */ |
12781 | switch (size) { | |
449f264b | 12782 | case 0: /* half-precision */ |
5d265064 | 12783 | size = MO_16; |
d17b7cdc | 12784 | is_fp16 = true; |
449f264b RH |
12785 | break; |
12786 | case MO_32: /* single precision */ | |
12787 | case MO_64: /* double precision */ | |
12788 | break; | |
12789 | default: | |
5d265064 AB |
12790 | unallocated_encoding(s); |
12791 | return; | |
f5e51e7f | 12792 | } |
d17b7cdc RH |
12793 | break; |
12794 | ||
12795 | case 2: /* complex fp */ | |
12796 | /* Each indexable element is a complex pair. */ | |
eaefb97a | 12797 | size += 1; |
d17b7cdc RH |
12798 | switch (size) { |
12799 | case MO_32: | |
12800 | if (h && !is_q) { | |
12801 | unallocated_encoding(s); | |
12802 | return; | |
12803 | } | |
12804 | is_fp16 = true; | |
12805 | break; | |
12806 | case MO_64: | |
12807 | break; | |
12808 | default: | |
12809 | unallocated_encoding(s); | |
12810 | return; | |
12811 | } | |
12812 | break; | |
12813 | ||
12814 | default: /* integer */ | |
f5e51e7f | 12815 | switch (size) { |
449f264b RH |
12816 | case MO_8: |
12817 | case MO_64: | |
f5e51e7f PM |
12818 | unallocated_encoding(s); |
12819 | return; | |
12820 | } | |
d17b7cdc RH |
12821 | break; |
12822 | } | |
5763190f | 12823 | if (is_fp16 && !dc_isar_feature(aa64_fp16, s)) { |
d17b7cdc RH |
12824 | unallocated_encoding(s); |
12825 | return; | |
f5e51e7f PM |
12826 | } |
12827 | ||
449f264b RH |
12828 | /* Given TCGMemOp size, adjust register and indexing. */ |
12829 | switch (size) { | |
12830 | case MO_16: | |
12831 | index = h << 2 | l << 1 | m; | |
12832 | break; | |
12833 | case MO_32: | |
12834 | index = h << 1 | l; | |
12835 | rm |= m << 4; | |
12836 | break; | |
12837 | case MO_64: | |
12838 | if (l || !is_q) { | |
12839 | unallocated_encoding(s); | |
12840 | return; | |
12841 | } | |
12842 | index = h; | |
12843 | rm |= m << 4; | |
12844 | break; | |
12845 | default: | |
12846 | g_assert_not_reached(); | |
12847 | } | |
12848 | ||
8c6afa6a PM |
12849 | if (!fp_access_check(s)) { |
12850 | return; | |
12851 | } | |
12852 | ||
f5e51e7f | 12853 | if (is_fp) { |
5d265064 | 12854 | fpst = get_fpstatus_ptr(is_fp16); |
f5e51e7f | 12855 | } else { |
f764718d | 12856 | fpst = NULL; |
f5e51e7f PM |
12857 | } |
12858 | ||
d17b7cdc | 12859 | switch (16 * u + opcode) { |
26c470a7 RH |
12860 | case 0x0e: /* SDOT */ |
12861 | case 0x1e: /* UDOT */ | |
12862 | gen_gvec_op3_ool(s, is_q, rd, rn, rm, index, | |
12863 | u ? gen_helper_gvec_udot_idx_b | |
12864 | : gen_helper_gvec_sdot_idx_b); | |
12865 | return; | |
d17b7cdc RH |
12866 | case 0x11: /* FCMLA #0 */ |
12867 | case 0x13: /* FCMLA #90 */ | |
12868 | case 0x15: /* FCMLA #180 */ | |
12869 | case 0x17: /* FCMLA #270 */ | |
2cc99919 RH |
12870 | { |
12871 | int rot = extract32(insn, 13, 2); | |
12872 | int data = (index << 2) | rot; | |
12873 | tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd), | |
12874 | vec_full_reg_offset(s, rn), | |
12875 | vec_full_reg_offset(s, rm), fpst, | |
12876 | is_q ? 16 : 8, vec_full_reg_size(s), data, | |
12877 | size == MO_64 | |
12878 | ? gen_helper_gvec_fcmlas_idx | |
12879 | : gen_helper_gvec_fcmlah_idx); | |
12880 | tcg_temp_free_ptr(fpst); | |
12881 | } | |
d17b7cdc | 12882 | return; |
0caa5af8 RH |
12883 | |
12884 | case 0x00: /* FMLAL */ | |
12885 | case 0x04: /* FMLSL */ | |
12886 | case 0x18: /* FMLAL2 */ | |
12887 | case 0x1c: /* FMLSL2 */ | |
12888 | { | |
12889 | int is_s = extract32(opcode, 2, 1); | |
12890 | int is_2 = u; | |
12891 | int data = (index << 2) | (is_2 << 1) | is_s; | |
12892 | tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd), | |
12893 | vec_full_reg_offset(s, rn), | |
12894 | vec_full_reg_offset(s, rm), cpu_env, | |
12895 | is_q ? 16 : 8, vec_full_reg_size(s), | |
12896 | data, gen_helper_gvec_fmlal_idx_a64); | |
12897 | } | |
12898 | return; | |
d17b7cdc RH |
12899 | } |
12900 | ||
f5e51e7f PM |
12901 | if (size == 3) { |
12902 | TCGv_i64 tcg_idx = tcg_temp_new_i64(); | |
12903 | int pass; | |
12904 | ||
12905 | assert(is_fp && is_q && !is_long); | |
12906 | ||
12907 | read_vec_element(s, tcg_idx, rm, index, MO_64); | |
12908 | ||
9f82e0ff | 12909 | for (pass = 0; pass < (is_scalar ? 1 : 2); pass++) { |
f5e51e7f PM |
12910 | TCGv_i64 tcg_op = tcg_temp_new_i64(); |
12911 | TCGv_i64 tcg_res = tcg_temp_new_i64(); | |
12912 | ||
12913 | read_vec_element(s, tcg_op, rn, pass, MO_64); | |
12914 | ||
5f81b1de RH |
12915 | switch (16 * u + opcode) { |
12916 | case 0x05: /* FMLS */ | |
f5e51e7f PM |
12917 | /* As usual for ARM, separate negation for fused multiply-add */ |
12918 | gen_helper_vfp_negd(tcg_op, tcg_op); | |
12919 | /* fall through */ | |
5f81b1de | 12920 | case 0x01: /* FMLA */ |
f5e51e7f PM |
12921 | read_vec_element(s, tcg_res, rd, pass, MO_64); |
12922 | gen_helper_vfp_muladdd(tcg_res, tcg_op, tcg_idx, tcg_res, fpst); | |
12923 | break; | |
5f81b1de RH |
12924 | case 0x09: /* FMUL */ |
12925 | gen_helper_vfp_muld(tcg_res, tcg_op, tcg_idx, fpst); | |
12926 | break; | |
12927 | case 0x19: /* FMULX */ | |
12928 | gen_helper_vfp_mulxd(tcg_res, tcg_op, tcg_idx, fpst); | |
f5e51e7f PM |
12929 | break; |
12930 | default: | |
12931 | g_assert_not_reached(); | |
12932 | } | |
12933 | ||
12934 | write_vec_element(s, tcg_res, rd, pass, MO_64); | |
12935 | tcg_temp_free_i64(tcg_op); | |
12936 | tcg_temp_free_i64(tcg_res); | |
12937 | } | |
12938 | ||
12939 | tcg_temp_free_i64(tcg_idx); | |
4ff55bcb | 12940 | clear_vec_high(s, !is_scalar, rd); |
f5e51e7f | 12941 | } else if (!is_long) { |
9f82e0ff PM |
12942 | /* 32 bit floating point, or 16 or 32 bit integer. |
12943 | * For the 16 bit scalar case we use the usual Neon helpers and | |
12944 | * rely on the fact that 0 op 0 == 0 with no side effects. | |
12945 | */ | |
f5e51e7f | 12946 | TCGv_i32 tcg_idx = tcg_temp_new_i32(); |
9f82e0ff PM |
12947 | int pass, maxpasses; |
12948 | ||
12949 | if (is_scalar) { | |
12950 | maxpasses = 1; | |
12951 | } else { | |
12952 | maxpasses = is_q ? 4 : 2; | |
12953 | } | |
f5e51e7f PM |
12954 | |
12955 | read_vec_element_i32(s, tcg_idx, rm, index, size); | |
12956 | ||
9f82e0ff | 12957 | if (size == 1 && !is_scalar) { |
f5e51e7f PM |
12958 | /* The simplest way to handle the 16x16 indexed ops is to duplicate |
12959 | * the index into both halves of the 32 bit tcg_idx and then use | |
12960 | * the usual Neon helpers. | |
12961 | */ | |
12962 | tcg_gen_deposit_i32(tcg_idx, tcg_idx, tcg_idx, 16, 16); | |
12963 | } | |
12964 | ||
9f82e0ff | 12965 | for (pass = 0; pass < maxpasses; pass++) { |
f5e51e7f PM |
12966 | TCGv_i32 tcg_op = tcg_temp_new_i32(); |
12967 | TCGv_i32 tcg_res = tcg_temp_new_i32(); | |
12968 | ||
9f82e0ff | 12969 | read_vec_element_i32(s, tcg_op, rn, pass, is_scalar ? size : MO_32); |
f5e51e7f | 12970 | |
5f81b1de RH |
12971 | switch (16 * u + opcode) { |
12972 | case 0x08: /* MUL */ | |
12973 | case 0x10: /* MLA */ | |
12974 | case 0x14: /* MLS */ | |
f5e51e7f PM |
12975 | { |
12976 | static NeonGenTwoOpFn * const fns[2][2] = { | |
12977 | { gen_helper_neon_add_u16, gen_helper_neon_sub_u16 }, | |
12978 | { tcg_gen_add_i32, tcg_gen_sub_i32 }, | |
12979 | }; | |
12980 | NeonGenTwoOpFn *genfn; | |
12981 | bool is_sub = opcode == 0x4; | |
12982 | ||
12983 | if (size == 1) { | |
12984 | gen_helper_neon_mul_u16(tcg_res, tcg_op, tcg_idx); | |
12985 | } else { | |
12986 | tcg_gen_mul_i32(tcg_res, tcg_op, tcg_idx); | |
12987 | } | |
12988 | if (opcode == 0x8) { | |
12989 | break; | |
12990 | } | |
12991 | read_vec_element_i32(s, tcg_op, rd, pass, MO_32); | |
12992 | genfn = fns[size - 1][is_sub]; | |
12993 | genfn(tcg_res, tcg_op, tcg_res); | |
12994 | break; | |
12995 | } | |
5f81b1de RH |
12996 | case 0x05: /* FMLS */ |
12997 | case 0x01: /* FMLA */ | |
5d265064 AB |
12998 | read_vec_element_i32(s, tcg_res, rd, pass, |
12999 | is_scalar ? size : MO_32); | |
13000 | switch (size) { | |
13001 | case 1: | |
13002 | if (opcode == 0x5) { | |
13003 | /* As usual for ARM, separate negation for fused | |
13004 | * multiply-add */ | |
13005 | tcg_gen_xori_i32(tcg_op, tcg_op, 0x80008000); | |
13006 | } | |
6089030c AB |
13007 | if (is_scalar) { |
13008 | gen_helper_advsimd_muladdh(tcg_res, tcg_op, tcg_idx, | |
13009 | tcg_res, fpst); | |
13010 | } else { | |
13011 | gen_helper_advsimd_muladd2h(tcg_res, tcg_op, tcg_idx, | |
13012 | tcg_res, fpst); | |
13013 | } | |
5d265064 AB |
13014 | break; |
13015 | case 2: | |
13016 | if (opcode == 0x5) { | |
13017 | /* As usual for ARM, separate negation for | |
13018 | * fused multiply-add */ | |
13019 | tcg_gen_xori_i32(tcg_op, tcg_op, 0x80000000); | |
13020 | } | |
13021 | gen_helper_vfp_muladds(tcg_res, tcg_op, tcg_idx, | |
13022 | tcg_res, fpst); | |
13023 | break; | |
13024 | default: | |
13025 | g_assert_not_reached(); | |
13026 | } | |
f5e51e7f | 13027 | break; |
5f81b1de | 13028 | case 0x09: /* FMUL */ |
5d265064 AB |
13029 | switch (size) { |
13030 | case 1: | |
5f81b1de RH |
13031 | if (is_scalar) { |
13032 | gen_helper_advsimd_mulh(tcg_res, tcg_op, | |
13033 | tcg_idx, fpst); | |
5d265064 | 13034 | } else { |
5f81b1de RH |
13035 | gen_helper_advsimd_mul2h(tcg_res, tcg_op, |
13036 | tcg_idx, fpst); | |
5d265064 AB |
13037 | } |
13038 | break; | |
13039 | case 2: | |
5f81b1de RH |
13040 | gen_helper_vfp_muls(tcg_res, tcg_op, tcg_idx, fpst); |
13041 | break; | |
13042 | default: | |
13043 | g_assert_not_reached(); | |
13044 | } | |
13045 | break; | |
13046 | case 0x19: /* FMULX */ | |
13047 | switch (size) { | |
13048 | case 1: | |
13049 | if (is_scalar) { | |
13050 | gen_helper_advsimd_mulxh(tcg_res, tcg_op, | |
13051 | tcg_idx, fpst); | |
5d265064 | 13052 | } else { |
5f81b1de RH |
13053 | gen_helper_advsimd_mulx2h(tcg_res, tcg_op, |
13054 | tcg_idx, fpst); | |
5d265064 AB |
13055 | } |
13056 | break; | |
5f81b1de RH |
13057 | case 2: |
13058 | gen_helper_vfp_mulxs(tcg_res, tcg_op, tcg_idx, fpst); | |
13059 | break; | |
5d265064 AB |
13060 | default: |
13061 | g_assert_not_reached(); | |
f5e51e7f PM |
13062 | } |
13063 | break; | |
5f81b1de | 13064 | case 0x0c: /* SQDMULH */ |
f5e51e7f PM |
13065 | if (size == 1) { |
13066 | gen_helper_neon_qdmulh_s16(tcg_res, cpu_env, | |
13067 | tcg_op, tcg_idx); | |
13068 | } else { | |
13069 | gen_helper_neon_qdmulh_s32(tcg_res, cpu_env, | |
13070 | tcg_op, tcg_idx); | |
13071 | } | |
13072 | break; | |
5f81b1de | 13073 | case 0x0d: /* SQRDMULH */ |
f5e51e7f PM |
13074 | if (size == 1) { |
13075 | gen_helper_neon_qrdmulh_s16(tcg_res, cpu_env, | |
13076 | tcg_op, tcg_idx); | |
13077 | } else { | |
13078 | gen_helper_neon_qrdmulh_s32(tcg_res, cpu_env, | |
13079 | tcg_op, tcg_idx); | |
13080 | } | |
13081 | break; | |
d345df7a RH |
13082 | case 0x1d: /* SQRDMLAH */ |
13083 | read_vec_element_i32(s, tcg_res, rd, pass, | |
13084 | is_scalar ? size : MO_32); | |
13085 | if (size == 1) { | |
13086 | gen_helper_neon_qrdmlah_s16(tcg_res, cpu_env, | |
13087 | tcg_op, tcg_idx, tcg_res); | |
13088 | } else { | |
13089 | gen_helper_neon_qrdmlah_s32(tcg_res, cpu_env, | |
13090 | tcg_op, tcg_idx, tcg_res); | |
13091 | } | |
13092 | break; | |
13093 | case 0x1f: /* SQRDMLSH */ | |
13094 | read_vec_element_i32(s, tcg_res, rd, pass, | |
13095 | is_scalar ? size : MO_32); | |
13096 | if (size == 1) { | |
13097 | gen_helper_neon_qrdmlsh_s16(tcg_res, cpu_env, | |
13098 | tcg_op, tcg_idx, tcg_res); | |
13099 | } else { | |
13100 | gen_helper_neon_qrdmlsh_s32(tcg_res, cpu_env, | |
13101 | tcg_op, tcg_idx, tcg_res); | |
13102 | } | |
13103 | break; | |
f5e51e7f PM |
13104 | default: |
13105 | g_assert_not_reached(); | |
13106 | } | |
13107 | ||
9f82e0ff PM |
13108 | if (is_scalar) { |
13109 | write_fp_sreg(s, rd, tcg_res); | |
13110 | } else { | |
13111 | write_vec_element_i32(s, tcg_res, rd, pass, MO_32); | |
13112 | } | |
13113 | ||
f5e51e7f PM |
13114 | tcg_temp_free_i32(tcg_op); |
13115 | tcg_temp_free_i32(tcg_res); | |
13116 | } | |
13117 | ||
13118 | tcg_temp_free_i32(tcg_idx); | |
4ff55bcb | 13119 | clear_vec_high(s, is_q, rd); |
f5e51e7f PM |
13120 | } else { |
13121 | /* long ops: 16x16->32 or 32x32->64 */ | |
c44ad1fd PM |
13122 | TCGv_i64 tcg_res[2]; |
13123 | int pass; | |
13124 | bool satop = extract32(opcode, 0, 1); | |
13125 | TCGMemOp memop = MO_32; | |
13126 | ||
13127 | if (satop || !u) { | |
13128 | memop |= MO_SIGN; | |
13129 | } | |
13130 | ||
13131 | if (size == 2) { | |
13132 | TCGv_i64 tcg_idx = tcg_temp_new_i64(); | |
13133 | ||
13134 | read_vec_element(s, tcg_idx, rm, index, memop); | |
13135 | ||
9f82e0ff | 13136 | for (pass = 0; pass < (is_scalar ? 1 : 2); pass++) { |
c44ad1fd PM |
13137 | TCGv_i64 tcg_op = tcg_temp_new_i64(); |
13138 | TCGv_i64 tcg_passres; | |
9f82e0ff | 13139 | int passelt; |
c44ad1fd | 13140 | |
9f82e0ff PM |
13141 | if (is_scalar) { |
13142 | passelt = 0; | |
13143 | } else { | |
13144 | passelt = pass + (is_q * 2); | |
13145 | } | |
13146 | ||
13147 | read_vec_element(s, tcg_op, rn, passelt, memop); | |
c44ad1fd PM |
13148 | |
13149 | tcg_res[pass] = tcg_temp_new_i64(); | |
13150 | ||
13151 | if (opcode == 0xa || opcode == 0xb) { | |
13152 | /* Non-accumulating ops */ | |
13153 | tcg_passres = tcg_res[pass]; | |
13154 | } else { | |
13155 | tcg_passres = tcg_temp_new_i64(); | |
13156 | } | |
13157 | ||
13158 | tcg_gen_mul_i64(tcg_passres, tcg_op, tcg_idx); | |
13159 | tcg_temp_free_i64(tcg_op); | |
13160 | ||
13161 | if (satop) { | |
13162 | /* saturating, doubling */ | |
13163 | gen_helper_neon_addl_saturate_s64(tcg_passres, cpu_env, | |
13164 | tcg_passres, tcg_passres); | |
13165 | } | |
13166 | ||
13167 | if (opcode == 0xa || opcode == 0xb) { | |
13168 | continue; | |
13169 | } | |
13170 | ||
13171 | /* Accumulating op: handle accumulate step */ | |
13172 | read_vec_element(s, tcg_res[pass], rd, pass, MO_64); | |
13173 | ||
13174 | switch (opcode) { | |
13175 | case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */ | |
13176 | tcg_gen_add_i64(tcg_res[pass], tcg_res[pass], tcg_passres); | |
13177 | break; | |
13178 | case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */ | |
13179 | tcg_gen_sub_i64(tcg_res[pass], tcg_res[pass], tcg_passres); | |
13180 | break; | |
13181 | case 0x7: /* SQDMLSL, SQDMLSL2 */ | |
13182 | tcg_gen_neg_i64(tcg_passres, tcg_passres); | |
13183 | /* fall through */ | |
13184 | case 0x3: /* SQDMLAL, SQDMLAL2 */ | |
13185 | gen_helper_neon_addl_saturate_s64(tcg_res[pass], cpu_env, | |
13186 | tcg_res[pass], | |
13187 | tcg_passres); | |
13188 | break; | |
13189 | default: | |
13190 | g_assert_not_reached(); | |
13191 | } | |
13192 | tcg_temp_free_i64(tcg_passres); | |
13193 | } | |
13194 | tcg_temp_free_i64(tcg_idx); | |
9f82e0ff | 13195 | |
4ff55bcb | 13196 | clear_vec_high(s, !is_scalar, rd); |
c44ad1fd PM |
13197 | } else { |
13198 | TCGv_i32 tcg_idx = tcg_temp_new_i32(); | |
13199 | ||
13200 | assert(size == 1); | |
13201 | read_vec_element_i32(s, tcg_idx, rm, index, size); | |
13202 | ||
9f82e0ff PM |
13203 | if (!is_scalar) { |
13204 | /* The simplest way to handle the 16x16 indexed ops is to | |
13205 | * duplicate the index into both halves of the 32 bit tcg_idx | |
13206 | * and then use the usual Neon helpers. | |
13207 | */ | |
13208 | tcg_gen_deposit_i32(tcg_idx, tcg_idx, tcg_idx, 16, 16); | |
13209 | } | |
c44ad1fd | 13210 | |
9f82e0ff | 13211 | for (pass = 0; pass < (is_scalar ? 1 : 2); pass++) { |
c44ad1fd PM |
13212 | TCGv_i32 tcg_op = tcg_temp_new_i32(); |
13213 | TCGv_i64 tcg_passres; | |
13214 | ||
9f82e0ff PM |
13215 | if (is_scalar) { |
13216 | read_vec_element_i32(s, tcg_op, rn, pass, size); | |
13217 | } else { | |
13218 | read_vec_element_i32(s, tcg_op, rn, | |
13219 | pass + (is_q * 2), MO_32); | |
13220 | } | |
13221 | ||
c44ad1fd PM |
13222 | tcg_res[pass] = tcg_temp_new_i64(); |
13223 | ||
13224 | if (opcode == 0xa || opcode == 0xb) { | |
13225 | /* Non-accumulating ops */ | |
13226 | tcg_passres = tcg_res[pass]; | |
13227 | } else { | |
13228 | tcg_passres = tcg_temp_new_i64(); | |
13229 | } | |
13230 | ||
13231 | if (memop & MO_SIGN) { | |
13232 | gen_helper_neon_mull_s16(tcg_passres, tcg_op, tcg_idx); | |
13233 | } else { | |
13234 | gen_helper_neon_mull_u16(tcg_passres, tcg_op, tcg_idx); | |
13235 | } | |
13236 | if (satop) { | |
13237 | gen_helper_neon_addl_saturate_s32(tcg_passres, cpu_env, | |
13238 | tcg_passres, tcg_passres); | |
13239 | } | |
13240 | tcg_temp_free_i32(tcg_op); | |
13241 | ||
13242 | if (opcode == 0xa || opcode == 0xb) { | |
13243 | continue; | |
13244 | } | |
13245 | ||
13246 | /* Accumulating op: handle accumulate step */ | |
13247 | read_vec_element(s, tcg_res[pass], rd, pass, MO_64); | |
13248 | ||
13249 | switch (opcode) { | |
13250 | case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */ | |
13251 | gen_helper_neon_addl_u32(tcg_res[pass], tcg_res[pass], | |
13252 | tcg_passres); | |
13253 | break; | |
13254 | case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */ | |
13255 | gen_helper_neon_subl_u32(tcg_res[pass], tcg_res[pass], | |
13256 | tcg_passres); | |
13257 | break; | |
13258 | case 0x7: /* SQDMLSL, SQDMLSL2 */ | |
13259 | gen_helper_neon_negl_u32(tcg_passres, tcg_passres); | |
13260 | /* fall through */ | |
13261 | case 0x3: /* SQDMLAL, SQDMLAL2 */ | |
13262 | gen_helper_neon_addl_saturate_s32(tcg_res[pass], cpu_env, | |
13263 | tcg_res[pass], | |
13264 | tcg_passres); | |
13265 | break; | |
13266 | default: | |
13267 | g_assert_not_reached(); | |
13268 | } | |
13269 | tcg_temp_free_i64(tcg_passres); | |
13270 | } | |
13271 | tcg_temp_free_i32(tcg_idx); | |
9f82e0ff PM |
13272 | |
13273 | if (is_scalar) { | |
13274 | tcg_gen_ext32u_i64(tcg_res[0], tcg_res[0]); | |
13275 | } | |
13276 | } | |
13277 | ||
13278 | if (is_scalar) { | |
13279 | tcg_res[1] = tcg_const_i64(0); | |
c44ad1fd PM |
13280 | } |
13281 | ||
13282 | for (pass = 0; pass < 2; pass++) { | |
13283 | write_vec_element(s, tcg_res[pass], rd, pass, MO_64); | |
13284 | tcg_temp_free_i64(tcg_res[pass]); | |
13285 | } | |
f5e51e7f PM |
13286 | } |
13287 | ||
f764718d | 13288 | if (fpst) { |
f5e51e7f PM |
13289 | tcg_temp_free_ptr(fpst); |
13290 | } | |
384b26fb AB |
13291 | } |
13292 | ||
4ce31af4 | 13293 | /* Crypto AES |
384b26fb AB |
13294 | * 31 24 23 22 21 17 16 12 11 10 9 5 4 0 |
13295 | * +-----------------+------+-----------+--------+-----+------+------+ | |
13296 | * | 0 1 0 0 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd | | |
13297 | * +-----------------+------+-----------+--------+-----+------+------+ | |
13298 | */ | |
13299 | static void disas_crypto_aes(DisasContext *s, uint32_t insn) | |
13300 | { | |
5acc765c PM |
13301 | int size = extract32(insn, 22, 2); |
13302 | int opcode = extract32(insn, 12, 5); | |
13303 | int rn = extract32(insn, 5, 5); | |
13304 | int rd = extract32(insn, 0, 5); | |
13305 | int decrypt; | |
1a66ac61 RH |
13306 | TCGv_ptr tcg_rd_ptr, tcg_rn_ptr; |
13307 | TCGv_i32 tcg_decrypt; | |
13308 | CryptoThreeOpIntFn *genfn; | |
5acc765c | 13309 | |
962fcbf2 | 13310 | if (!dc_isar_feature(aa64_aes, s) || size != 0) { |
5acc765c PM |
13311 | unallocated_encoding(s); |
13312 | return; | |
13313 | } | |
13314 | ||
13315 | switch (opcode) { | |
13316 | case 0x4: /* AESE */ | |
13317 | decrypt = 0; | |
13318 | genfn = gen_helper_crypto_aese; | |
13319 | break; | |
13320 | case 0x6: /* AESMC */ | |
13321 | decrypt = 0; | |
13322 | genfn = gen_helper_crypto_aesmc; | |
13323 | break; | |
13324 | case 0x5: /* AESD */ | |
13325 | decrypt = 1; | |
13326 | genfn = gen_helper_crypto_aese; | |
13327 | break; | |
13328 | case 0x7: /* AESIMC */ | |
13329 | decrypt = 1; | |
13330 | genfn = gen_helper_crypto_aesmc; | |
13331 | break; | |
13332 | default: | |
13333 | unallocated_encoding(s); | |
13334 | return; | |
13335 | } | |
13336 | ||
a4f5c5b7 NR |
13337 | if (!fp_access_check(s)) { |
13338 | return; | |
13339 | } | |
13340 | ||
1a66ac61 RH |
13341 | tcg_rd_ptr = vec_full_reg_ptr(s, rd); |
13342 | tcg_rn_ptr = vec_full_reg_ptr(s, rn); | |
5acc765c PM |
13343 | tcg_decrypt = tcg_const_i32(decrypt); |
13344 | ||
1a66ac61 | 13345 | genfn(tcg_rd_ptr, tcg_rn_ptr, tcg_decrypt); |
5acc765c | 13346 | |
1a66ac61 RH |
13347 | tcg_temp_free_ptr(tcg_rd_ptr); |
13348 | tcg_temp_free_ptr(tcg_rn_ptr); | |
5acc765c | 13349 | tcg_temp_free_i32(tcg_decrypt); |
384b26fb AB |
13350 | } |
13351 | ||
4ce31af4 | 13352 | /* Crypto three-reg SHA |
384b26fb AB |
13353 | * 31 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0 |
13354 | * +-----------------+------+---+------+---+--------+-----+------+------+ | |
13355 | * | 0 1 0 1 1 1 1 0 | size | 0 | Rm | 0 | opcode | 0 0 | Rn | Rd | | |
13356 | * +-----------------+------+---+------+---+--------+-----+------+------+ | |
13357 | */ | |
13358 | static void disas_crypto_three_reg_sha(DisasContext *s, uint32_t insn) | |
13359 | { | |
be56f04e PM |
13360 | int size = extract32(insn, 22, 2); |
13361 | int opcode = extract32(insn, 12, 3); | |
13362 | int rm = extract32(insn, 16, 5); | |
13363 | int rn = extract32(insn, 5, 5); | |
13364 | int rd = extract32(insn, 0, 5); | |
1a66ac61 RH |
13365 | CryptoThreeOpFn *genfn; |
13366 | TCGv_ptr tcg_rd_ptr, tcg_rn_ptr, tcg_rm_ptr; | |
962fcbf2 | 13367 | bool feature; |
be56f04e PM |
13368 | |
13369 | if (size != 0) { | |
13370 | unallocated_encoding(s); | |
13371 | return; | |
13372 | } | |
13373 | ||
13374 | switch (opcode) { | |
13375 | case 0: /* SHA1C */ | |
13376 | case 1: /* SHA1P */ | |
13377 | case 2: /* SHA1M */ | |
13378 | case 3: /* SHA1SU0 */ | |
13379 | genfn = NULL; | |
962fcbf2 | 13380 | feature = dc_isar_feature(aa64_sha1, s); |
be56f04e PM |
13381 | break; |
13382 | case 4: /* SHA256H */ | |
13383 | genfn = gen_helper_crypto_sha256h; | |
962fcbf2 | 13384 | feature = dc_isar_feature(aa64_sha256, s); |
be56f04e PM |
13385 | break; |
13386 | case 5: /* SHA256H2 */ | |
13387 | genfn = gen_helper_crypto_sha256h2; | |
962fcbf2 | 13388 | feature = dc_isar_feature(aa64_sha256, s); |
be56f04e PM |
13389 | break; |
13390 | case 6: /* SHA256SU1 */ | |
13391 | genfn = gen_helper_crypto_sha256su1; | |
962fcbf2 | 13392 | feature = dc_isar_feature(aa64_sha256, s); |
be56f04e PM |
13393 | break; |
13394 | default: | |
13395 | unallocated_encoding(s); | |
13396 | return; | |
13397 | } | |
13398 | ||
962fcbf2 | 13399 | if (!feature) { |
be56f04e PM |
13400 | unallocated_encoding(s); |
13401 | return; | |
13402 | } | |
13403 | ||
a4f5c5b7 NR |
13404 | if (!fp_access_check(s)) { |
13405 | return; | |
13406 | } | |
13407 | ||
1a66ac61 RH |
13408 | tcg_rd_ptr = vec_full_reg_ptr(s, rd); |
13409 | tcg_rn_ptr = vec_full_reg_ptr(s, rn); | |
13410 | tcg_rm_ptr = vec_full_reg_ptr(s, rm); | |
be56f04e PM |
13411 | |
13412 | if (genfn) { | |
1a66ac61 | 13413 | genfn(tcg_rd_ptr, tcg_rn_ptr, tcg_rm_ptr); |
be56f04e PM |
13414 | } else { |
13415 | TCGv_i32 tcg_opcode = tcg_const_i32(opcode); | |
13416 | ||
1a66ac61 RH |
13417 | gen_helper_crypto_sha1_3reg(tcg_rd_ptr, tcg_rn_ptr, |
13418 | tcg_rm_ptr, tcg_opcode); | |
be56f04e PM |
13419 | tcg_temp_free_i32(tcg_opcode); |
13420 | } | |
13421 | ||
1a66ac61 RH |
13422 | tcg_temp_free_ptr(tcg_rd_ptr); |
13423 | tcg_temp_free_ptr(tcg_rn_ptr); | |
13424 | tcg_temp_free_ptr(tcg_rm_ptr); | |
384b26fb AB |
13425 | } |
13426 | ||
4ce31af4 | 13427 | /* Crypto two-reg SHA |
384b26fb AB |
13428 | * 31 24 23 22 21 17 16 12 11 10 9 5 4 0 |
13429 | * +-----------------+------+-----------+--------+-----+------+------+ | |
13430 | * | 0 1 0 1 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd | | |
13431 | * +-----------------+------+-----------+--------+-----+------+------+ | |
13432 | */ | |
13433 | static void disas_crypto_two_reg_sha(DisasContext *s, uint32_t insn) | |
13434 | { | |
f6fe04d5 PM |
13435 | int size = extract32(insn, 22, 2); |
13436 | int opcode = extract32(insn, 12, 5); | |
13437 | int rn = extract32(insn, 5, 5); | |
13438 | int rd = extract32(insn, 0, 5); | |
1a66ac61 | 13439 | CryptoTwoOpFn *genfn; |
962fcbf2 | 13440 | bool feature; |
1a66ac61 | 13441 | TCGv_ptr tcg_rd_ptr, tcg_rn_ptr; |
f6fe04d5 PM |
13442 | |
13443 | if (size != 0) { | |
13444 | unallocated_encoding(s); | |
13445 | return; | |
13446 | } | |
13447 | ||
13448 | switch (opcode) { | |
13449 | case 0: /* SHA1H */ | |
962fcbf2 | 13450 | feature = dc_isar_feature(aa64_sha1, s); |
f6fe04d5 PM |
13451 | genfn = gen_helper_crypto_sha1h; |
13452 | break; | |
13453 | case 1: /* SHA1SU1 */ | |
962fcbf2 | 13454 | feature = dc_isar_feature(aa64_sha1, s); |
f6fe04d5 PM |
13455 | genfn = gen_helper_crypto_sha1su1; |
13456 | break; | |
13457 | case 2: /* SHA256SU0 */ | |
962fcbf2 | 13458 | feature = dc_isar_feature(aa64_sha256, s); |
f6fe04d5 PM |
13459 | genfn = gen_helper_crypto_sha256su0; |
13460 | break; | |
13461 | default: | |
13462 | unallocated_encoding(s); | |
13463 | return; | |
13464 | } | |
13465 | ||
962fcbf2 | 13466 | if (!feature) { |
f6fe04d5 PM |
13467 | unallocated_encoding(s); |
13468 | return; | |
13469 | } | |
13470 | ||
a4f5c5b7 NR |
13471 | if (!fp_access_check(s)) { |
13472 | return; | |
13473 | } | |
13474 | ||
1a66ac61 RH |
13475 | tcg_rd_ptr = vec_full_reg_ptr(s, rd); |
13476 | tcg_rn_ptr = vec_full_reg_ptr(s, rn); | |
f6fe04d5 | 13477 | |
1a66ac61 | 13478 | genfn(tcg_rd_ptr, tcg_rn_ptr); |
f6fe04d5 | 13479 | |
1a66ac61 RH |
13480 | tcg_temp_free_ptr(tcg_rd_ptr); |
13481 | tcg_temp_free_ptr(tcg_rn_ptr); | |
384b26fb AB |
13482 | } |
13483 | ||
90b827d1 AB |
13484 | /* Crypto three-reg SHA512 |
13485 | * 31 21 20 16 15 14 13 12 11 10 9 5 4 0 | |
13486 | * +-----------------------+------+---+---+-----+--------+------+------+ | |
13487 | * | 1 1 0 0 1 1 1 0 0 1 1 | Rm | 1 | O | 0 0 | opcode | Rn | Rd | | |
13488 | * +-----------------------+------+---+---+-----+--------+------+------+ | |
13489 | */ | |
13490 | static void disas_crypto_three_reg_sha512(DisasContext *s, uint32_t insn) | |
13491 | { | |
13492 | int opcode = extract32(insn, 10, 2); | |
13493 | int o = extract32(insn, 14, 1); | |
13494 | int rm = extract32(insn, 16, 5); | |
13495 | int rn = extract32(insn, 5, 5); | |
13496 | int rd = extract32(insn, 0, 5); | |
962fcbf2 | 13497 | bool feature; |
90b827d1 AB |
13498 | CryptoThreeOpFn *genfn; |
13499 | ||
13500 | if (o == 0) { | |
13501 | switch (opcode) { | |
13502 | case 0: /* SHA512H */ | |
962fcbf2 | 13503 | feature = dc_isar_feature(aa64_sha512, s); |
90b827d1 AB |
13504 | genfn = gen_helper_crypto_sha512h; |
13505 | break; | |
13506 | case 1: /* SHA512H2 */ | |
962fcbf2 | 13507 | feature = dc_isar_feature(aa64_sha512, s); |
90b827d1 AB |
13508 | genfn = gen_helper_crypto_sha512h2; |
13509 | break; | |
13510 | case 2: /* SHA512SU1 */ | |
962fcbf2 | 13511 | feature = dc_isar_feature(aa64_sha512, s); |
90b827d1 AB |
13512 | genfn = gen_helper_crypto_sha512su1; |
13513 | break; | |
cd270ade | 13514 | case 3: /* RAX1 */ |
962fcbf2 | 13515 | feature = dc_isar_feature(aa64_sha3, s); |
cd270ade AB |
13516 | genfn = NULL; |
13517 | break; | |
90b827d1 AB |
13518 | } |
13519 | } else { | |
80d6f4c6 AB |
13520 | switch (opcode) { |
13521 | case 0: /* SM3PARTW1 */ | |
962fcbf2 | 13522 | feature = dc_isar_feature(aa64_sm3, s); |
80d6f4c6 AB |
13523 | genfn = gen_helper_crypto_sm3partw1; |
13524 | break; | |
13525 | case 1: /* SM3PARTW2 */ | |
962fcbf2 | 13526 | feature = dc_isar_feature(aa64_sm3, s); |
80d6f4c6 AB |
13527 | genfn = gen_helper_crypto_sm3partw2; |
13528 | break; | |
b6577bcd | 13529 | case 2: /* SM4EKEY */ |
962fcbf2 | 13530 | feature = dc_isar_feature(aa64_sm4, s); |
b6577bcd AB |
13531 | genfn = gen_helper_crypto_sm4ekey; |
13532 | break; | |
80d6f4c6 AB |
13533 | default: |
13534 | unallocated_encoding(s); | |
13535 | return; | |
13536 | } | |
90b827d1 AB |
13537 | } |
13538 | ||
962fcbf2 | 13539 | if (!feature) { |
90b827d1 AB |
13540 | unallocated_encoding(s); |
13541 | return; | |
13542 | } | |
13543 | ||
13544 | if (!fp_access_check(s)) { | |
13545 | return; | |
13546 | } | |
13547 | ||
13548 | if (genfn) { | |
13549 | TCGv_ptr tcg_rd_ptr, tcg_rn_ptr, tcg_rm_ptr; | |
13550 | ||
13551 | tcg_rd_ptr = vec_full_reg_ptr(s, rd); | |
13552 | tcg_rn_ptr = vec_full_reg_ptr(s, rn); | |
13553 | tcg_rm_ptr = vec_full_reg_ptr(s, rm); | |
13554 | ||
13555 | genfn(tcg_rd_ptr, tcg_rn_ptr, tcg_rm_ptr); | |
13556 | ||
13557 | tcg_temp_free_ptr(tcg_rd_ptr); | |
13558 | tcg_temp_free_ptr(tcg_rn_ptr); | |
13559 | tcg_temp_free_ptr(tcg_rm_ptr); | |
13560 | } else { | |
cd270ade AB |
13561 | TCGv_i64 tcg_op1, tcg_op2, tcg_res[2]; |
13562 | int pass; | |
13563 | ||
13564 | tcg_op1 = tcg_temp_new_i64(); | |
13565 | tcg_op2 = tcg_temp_new_i64(); | |
13566 | tcg_res[0] = tcg_temp_new_i64(); | |
13567 | tcg_res[1] = tcg_temp_new_i64(); | |
13568 | ||
13569 | for (pass = 0; pass < 2; pass++) { | |
13570 | read_vec_element(s, tcg_op1, rn, pass, MO_64); | |
13571 | read_vec_element(s, tcg_op2, rm, pass, MO_64); | |
13572 | ||
13573 | tcg_gen_rotli_i64(tcg_res[pass], tcg_op2, 1); | |
13574 | tcg_gen_xor_i64(tcg_res[pass], tcg_res[pass], tcg_op1); | |
13575 | } | |
13576 | write_vec_element(s, tcg_res[0], rd, 0, MO_64); | |
13577 | write_vec_element(s, tcg_res[1], rd, 1, MO_64); | |
13578 | ||
13579 | tcg_temp_free_i64(tcg_op1); | |
13580 | tcg_temp_free_i64(tcg_op2); | |
13581 | tcg_temp_free_i64(tcg_res[0]); | |
13582 | tcg_temp_free_i64(tcg_res[1]); | |
90b827d1 AB |
13583 | } |
13584 | } | |
13585 | ||
13586 | /* Crypto two-reg SHA512 | |
13587 | * 31 12 11 10 9 5 4 0 | |
13588 | * +-----------------------------------------+--------+------+------+ | |
13589 | * | 1 1 0 0 1 1 1 0 1 1 0 0 0 0 0 0 1 0 0 0 | opcode | Rn | Rd | | |
13590 | * +-----------------------------------------+--------+------+------+ | |
13591 | */ | |
13592 | static void disas_crypto_two_reg_sha512(DisasContext *s, uint32_t insn) | |
13593 | { | |
13594 | int opcode = extract32(insn, 10, 2); | |
13595 | int rn = extract32(insn, 5, 5); | |
13596 | int rd = extract32(insn, 0, 5); | |
13597 | TCGv_ptr tcg_rd_ptr, tcg_rn_ptr; | |
962fcbf2 | 13598 | bool feature; |
90b827d1 AB |
13599 | CryptoTwoOpFn *genfn; |
13600 | ||
13601 | switch (opcode) { | |
13602 | case 0: /* SHA512SU0 */ | |
962fcbf2 | 13603 | feature = dc_isar_feature(aa64_sha512, s); |
90b827d1 AB |
13604 | genfn = gen_helper_crypto_sha512su0; |
13605 | break; | |
b6577bcd | 13606 | case 1: /* SM4E */ |
962fcbf2 | 13607 | feature = dc_isar_feature(aa64_sm4, s); |
b6577bcd AB |
13608 | genfn = gen_helper_crypto_sm4e; |
13609 | break; | |
90b827d1 AB |
13610 | default: |
13611 | unallocated_encoding(s); | |
13612 | return; | |
13613 | } | |
13614 | ||
962fcbf2 | 13615 | if (!feature) { |
90b827d1 AB |
13616 | unallocated_encoding(s); |
13617 | return; | |
13618 | } | |
13619 | ||
13620 | if (!fp_access_check(s)) { | |
13621 | return; | |
13622 | } | |
13623 | ||
13624 | tcg_rd_ptr = vec_full_reg_ptr(s, rd); | |
13625 | tcg_rn_ptr = vec_full_reg_ptr(s, rn); | |
13626 | ||
13627 | genfn(tcg_rd_ptr, tcg_rn_ptr); | |
13628 | ||
13629 | tcg_temp_free_ptr(tcg_rd_ptr); | |
13630 | tcg_temp_free_ptr(tcg_rn_ptr); | |
13631 | } | |
13632 | ||
cd270ade AB |
13633 | /* Crypto four-register |
13634 | * 31 23 22 21 20 16 15 14 10 9 5 4 0 | |
13635 | * +-------------------+-----+------+---+------+------+------+ | |
13636 | * | 1 1 0 0 1 1 1 0 0 | Op0 | Rm | 0 | Ra | Rn | Rd | | |
13637 | * +-------------------+-----+------+---+------+------+------+ | |
13638 | */ | |
13639 | static void disas_crypto_four_reg(DisasContext *s, uint32_t insn) | |
13640 | { | |
13641 | int op0 = extract32(insn, 21, 2); | |
13642 | int rm = extract32(insn, 16, 5); | |
13643 | int ra = extract32(insn, 10, 5); | |
13644 | int rn = extract32(insn, 5, 5); | |
13645 | int rd = extract32(insn, 0, 5); | |
962fcbf2 | 13646 | bool feature; |
cd270ade AB |
13647 | |
13648 | switch (op0) { | |
13649 | case 0: /* EOR3 */ | |
13650 | case 1: /* BCAX */ | |
962fcbf2 | 13651 | feature = dc_isar_feature(aa64_sha3, s); |
cd270ade | 13652 | break; |
80d6f4c6 | 13653 | case 2: /* SM3SS1 */ |
962fcbf2 | 13654 | feature = dc_isar_feature(aa64_sm3, s); |
80d6f4c6 | 13655 | break; |
cd270ade AB |
13656 | default: |
13657 | unallocated_encoding(s); | |
13658 | return; | |
13659 | } | |
13660 | ||
962fcbf2 | 13661 | if (!feature) { |
cd270ade AB |
13662 | unallocated_encoding(s); |
13663 | return; | |
13664 | } | |
13665 | ||
13666 | if (!fp_access_check(s)) { | |
13667 | return; | |
13668 | } | |
13669 | ||
13670 | if (op0 < 2) { | |
13671 | TCGv_i64 tcg_op1, tcg_op2, tcg_op3, tcg_res[2]; | |
13672 | int pass; | |
13673 | ||
13674 | tcg_op1 = tcg_temp_new_i64(); | |
13675 | tcg_op2 = tcg_temp_new_i64(); | |
13676 | tcg_op3 = tcg_temp_new_i64(); | |
13677 | tcg_res[0] = tcg_temp_new_i64(); | |
13678 | tcg_res[1] = tcg_temp_new_i64(); | |
13679 | ||
13680 | for (pass = 0; pass < 2; pass++) { | |
13681 | read_vec_element(s, tcg_op1, rn, pass, MO_64); | |
13682 | read_vec_element(s, tcg_op2, rm, pass, MO_64); | |
13683 | read_vec_element(s, tcg_op3, ra, pass, MO_64); | |
13684 | ||
13685 | if (op0 == 0) { | |
13686 | /* EOR3 */ | |
13687 | tcg_gen_xor_i64(tcg_res[pass], tcg_op2, tcg_op3); | |
13688 | } else { | |
13689 | /* BCAX */ | |
13690 | tcg_gen_andc_i64(tcg_res[pass], tcg_op2, tcg_op3); | |
13691 | } | |
13692 | tcg_gen_xor_i64(tcg_res[pass], tcg_res[pass], tcg_op1); | |
13693 | } | |
13694 | write_vec_element(s, tcg_res[0], rd, 0, MO_64); | |
13695 | write_vec_element(s, tcg_res[1], rd, 1, MO_64); | |
13696 | ||
13697 | tcg_temp_free_i64(tcg_op1); | |
13698 | tcg_temp_free_i64(tcg_op2); | |
13699 | tcg_temp_free_i64(tcg_op3); | |
13700 | tcg_temp_free_i64(tcg_res[0]); | |
13701 | tcg_temp_free_i64(tcg_res[1]); | |
13702 | } else { | |
80d6f4c6 AB |
13703 | TCGv_i32 tcg_op1, tcg_op2, tcg_op3, tcg_res, tcg_zero; |
13704 | ||
13705 | tcg_op1 = tcg_temp_new_i32(); | |
13706 | tcg_op2 = tcg_temp_new_i32(); | |
13707 | tcg_op3 = tcg_temp_new_i32(); | |
13708 | tcg_res = tcg_temp_new_i32(); | |
13709 | tcg_zero = tcg_const_i32(0); | |
13710 | ||
13711 | read_vec_element_i32(s, tcg_op1, rn, 3, MO_32); | |
13712 | read_vec_element_i32(s, tcg_op2, rm, 3, MO_32); | |
13713 | read_vec_element_i32(s, tcg_op3, ra, 3, MO_32); | |
13714 | ||
13715 | tcg_gen_rotri_i32(tcg_res, tcg_op1, 20); | |
13716 | tcg_gen_add_i32(tcg_res, tcg_res, tcg_op2); | |
13717 | tcg_gen_add_i32(tcg_res, tcg_res, tcg_op3); | |
13718 | tcg_gen_rotri_i32(tcg_res, tcg_res, 25); | |
13719 | ||
13720 | write_vec_element_i32(s, tcg_zero, rd, 0, MO_32); | |
13721 | write_vec_element_i32(s, tcg_zero, rd, 1, MO_32); | |
13722 | write_vec_element_i32(s, tcg_zero, rd, 2, MO_32); | |
13723 | write_vec_element_i32(s, tcg_res, rd, 3, MO_32); | |
13724 | ||
13725 | tcg_temp_free_i32(tcg_op1); | |
13726 | tcg_temp_free_i32(tcg_op2); | |
13727 | tcg_temp_free_i32(tcg_op3); | |
13728 | tcg_temp_free_i32(tcg_res); | |
13729 | tcg_temp_free_i32(tcg_zero); | |
cd270ade AB |
13730 | } |
13731 | } | |
13732 | ||
13733 | /* Crypto XAR | |
13734 | * 31 21 20 16 15 10 9 5 4 0 | |
13735 | * +-----------------------+------+--------+------+------+ | |
13736 | * | 1 1 0 0 1 1 1 0 1 0 0 | Rm | imm6 | Rn | Rd | | |
13737 | * +-----------------------+------+--------+------+------+ | |
13738 | */ | |
13739 | static void disas_crypto_xar(DisasContext *s, uint32_t insn) | |
13740 | { | |
13741 | int rm = extract32(insn, 16, 5); | |
13742 | int imm6 = extract32(insn, 10, 6); | |
13743 | int rn = extract32(insn, 5, 5); | |
13744 | int rd = extract32(insn, 0, 5); | |
13745 | TCGv_i64 tcg_op1, tcg_op2, tcg_res[2]; | |
13746 | int pass; | |
13747 | ||
962fcbf2 | 13748 | if (!dc_isar_feature(aa64_sha3, s)) { |
cd270ade AB |
13749 | unallocated_encoding(s); |
13750 | return; | |
13751 | } | |
13752 | ||
13753 | if (!fp_access_check(s)) { | |
13754 | return; | |
13755 | } | |
13756 | ||
13757 | tcg_op1 = tcg_temp_new_i64(); | |
13758 | tcg_op2 = tcg_temp_new_i64(); | |
13759 | tcg_res[0] = tcg_temp_new_i64(); | |
13760 | tcg_res[1] = tcg_temp_new_i64(); | |
13761 | ||
13762 | for (pass = 0; pass < 2; pass++) { | |
13763 | read_vec_element(s, tcg_op1, rn, pass, MO_64); | |
13764 | read_vec_element(s, tcg_op2, rm, pass, MO_64); | |
13765 | ||
13766 | tcg_gen_xor_i64(tcg_res[pass], tcg_op1, tcg_op2); | |
13767 | tcg_gen_rotri_i64(tcg_res[pass], tcg_res[pass], imm6); | |
13768 | } | |
13769 | write_vec_element(s, tcg_res[0], rd, 0, MO_64); | |
13770 | write_vec_element(s, tcg_res[1], rd, 1, MO_64); | |
13771 | ||
13772 | tcg_temp_free_i64(tcg_op1); | |
13773 | tcg_temp_free_i64(tcg_op2); | |
13774 | tcg_temp_free_i64(tcg_res[0]); | |
13775 | tcg_temp_free_i64(tcg_res[1]); | |
13776 | } | |
13777 | ||
80d6f4c6 AB |
13778 | /* Crypto three-reg imm2 |
13779 | * 31 21 20 16 15 14 13 12 11 10 9 5 4 0 | |
13780 | * +-----------------------+------+-----+------+--------+------+------+ | |
13781 | * | 1 1 0 0 1 1 1 0 0 1 0 | Rm | 1 0 | imm2 | opcode | Rn | Rd | | |
13782 | * +-----------------------+------+-----+------+--------+------+------+ | |
13783 | */ | |
13784 | static void disas_crypto_three_reg_imm2(DisasContext *s, uint32_t insn) | |
13785 | { | |
13786 | int opcode = extract32(insn, 10, 2); | |
13787 | int imm2 = extract32(insn, 12, 2); | |
13788 | int rm = extract32(insn, 16, 5); | |
13789 | int rn = extract32(insn, 5, 5); | |
13790 | int rd = extract32(insn, 0, 5); | |
13791 | TCGv_ptr tcg_rd_ptr, tcg_rn_ptr, tcg_rm_ptr; | |
13792 | TCGv_i32 tcg_imm2, tcg_opcode; | |
13793 | ||
962fcbf2 | 13794 | if (!dc_isar_feature(aa64_sm3, s)) { |
80d6f4c6 AB |
13795 | unallocated_encoding(s); |
13796 | return; | |
13797 | } | |
13798 | ||
13799 | if (!fp_access_check(s)) { | |
13800 | return; | |
13801 | } | |
13802 | ||
13803 | tcg_rd_ptr = vec_full_reg_ptr(s, rd); | |
13804 | tcg_rn_ptr = vec_full_reg_ptr(s, rn); | |
13805 | tcg_rm_ptr = vec_full_reg_ptr(s, rm); | |
13806 | tcg_imm2 = tcg_const_i32(imm2); | |
13807 | tcg_opcode = tcg_const_i32(opcode); | |
13808 | ||
13809 | gen_helper_crypto_sm3tt(tcg_rd_ptr, tcg_rn_ptr, tcg_rm_ptr, tcg_imm2, | |
13810 | tcg_opcode); | |
13811 | ||
13812 | tcg_temp_free_ptr(tcg_rd_ptr); | |
13813 | tcg_temp_free_ptr(tcg_rn_ptr); | |
13814 | tcg_temp_free_ptr(tcg_rm_ptr); | |
13815 | tcg_temp_free_i32(tcg_imm2); | |
13816 | tcg_temp_free_i32(tcg_opcode); | |
13817 | } | |
13818 | ||
384b26fb AB |
13819 | /* C3.6 Data processing - SIMD, inc Crypto |
13820 | * | |
13821 | * As the decode gets a little complex we are using a table based | |
13822 | * approach for this part of the decode. | |
13823 | */ | |
13824 | static const AArch64DecodeTable data_proc_simd[] = { | |
13825 | /* pattern , mask , fn */ | |
13826 | { 0x0e200400, 0x9f200400, disas_simd_three_reg_same }, | |
e7186d82 | 13827 | { 0x0e008400, 0x9f208400, disas_simd_three_reg_same_extra }, |
384b26fb AB |
13828 | { 0x0e200000, 0x9f200c00, disas_simd_three_reg_diff }, |
13829 | { 0x0e200800, 0x9f3e0c00, disas_simd_two_reg_misc }, | |
13830 | { 0x0e300800, 0x9f3e0c00, disas_simd_across_lanes }, | |
13831 | { 0x0e000400, 0x9fe08400, disas_simd_copy }, | |
9f82e0ff | 13832 | { 0x0f000000, 0x9f000400, disas_simd_indexed }, /* vector indexed */ |
384b26fb AB |
13833 | /* simd_mod_imm decode is a subset of simd_shift_imm, so must precede it */ |
13834 | { 0x0f000400, 0x9ff80400, disas_simd_mod_imm }, | |
13835 | { 0x0f000400, 0x9f800400, disas_simd_shift_imm }, | |
13836 | { 0x0e000000, 0xbf208c00, disas_simd_tb }, | |
13837 | { 0x0e000800, 0xbf208c00, disas_simd_zip_trn }, | |
13838 | { 0x2e000000, 0xbf208400, disas_simd_ext }, | |
13839 | { 0x5e200400, 0xdf200400, disas_simd_scalar_three_reg_same }, | |
d9061ec3 | 13840 | { 0x5e008400, 0xdf208400, disas_simd_scalar_three_reg_same_extra }, |
384b26fb AB |
13841 | { 0x5e200000, 0xdf200c00, disas_simd_scalar_three_reg_diff }, |
13842 | { 0x5e200800, 0xdf3e0c00, disas_simd_scalar_two_reg_misc }, | |
13843 | { 0x5e300800, 0xdf3e0c00, disas_simd_scalar_pairwise }, | |
13844 | { 0x5e000400, 0xdfe08400, disas_simd_scalar_copy }, | |
9f82e0ff | 13845 | { 0x5f000000, 0xdf000400, disas_simd_indexed }, /* scalar indexed */ |
384b26fb AB |
13846 | { 0x5f000400, 0xdf800400, disas_simd_scalar_shift_imm }, |
13847 | { 0x4e280800, 0xff3e0c00, disas_crypto_aes }, | |
13848 | { 0x5e000000, 0xff208c00, disas_crypto_three_reg_sha }, | |
13849 | { 0x5e280800, 0xff3e0c00, disas_crypto_two_reg_sha }, | |
90b827d1 AB |
13850 | { 0xce608000, 0xffe0b000, disas_crypto_three_reg_sha512 }, |
13851 | { 0xcec08000, 0xfffff000, disas_crypto_two_reg_sha512 }, | |
cd270ade AB |
13852 | { 0xce000000, 0xff808000, disas_crypto_four_reg }, |
13853 | { 0xce800000, 0xffe00000, disas_crypto_xar }, | |
80d6f4c6 | 13854 | { 0xce408000, 0xffe0c000, disas_crypto_three_reg_imm2 }, |
376e8d6c | 13855 | { 0x0e400400, 0x9f60c400, disas_simd_three_reg_same_fp16 }, |
5d432be6 | 13856 | { 0x0e780800, 0x8f7e0c00, disas_simd_two_reg_misc_fp16 }, |
7c93b774 | 13857 | { 0x5e400400, 0xdf60c400, disas_simd_scalar_three_reg_same_fp16 }, |
384b26fb AB |
13858 | { 0x00000000, 0x00000000, NULL } |
13859 | }; | |
13860 | ||
faa0ba46 PM |
13861 | static void disas_data_proc_simd(DisasContext *s, uint32_t insn) |
13862 | { | |
13863 | /* Note that this is called with all non-FP cases from | |
13864 | * table C3-6 so it must UNDEF for entries not specifically | |
13865 | * allocated to instructions in that table. | |
13866 | */ | |
384b26fb AB |
13867 | AArch64DecodeFn *fn = lookup_disas_fn(&data_proc_simd[0], insn); |
13868 | if (fn) { | |
13869 | fn(s, insn); | |
13870 | } else { | |
13871 | unallocated_encoding(s); | |
13872 | } | |
faa0ba46 PM |
13873 | } |
13874 | ||
ad7ee8a2 CF |
13875 | /* C3.6 Data processing - SIMD and floating point */ |
13876 | static void disas_data_proc_simd_fp(DisasContext *s, uint32_t insn) | |
13877 | { | |
faa0ba46 PM |
13878 | if (extract32(insn, 28, 1) == 1 && extract32(insn, 30, 1) == 0) { |
13879 | disas_data_proc_fp(s, insn); | |
13880 | } else { | |
13881 | /* SIMD, including crypto */ | |
13882 | disas_data_proc_simd(s, insn); | |
13883 | } | |
ad7ee8a2 CF |
13884 | } |
13885 | ||
51bf0d7a RH |
13886 | /** |
13887 | * is_guarded_page: | |
13888 | * @env: The cpu environment | |
13889 | * @s: The DisasContext | |
13890 | * | |
13891 | * Return true if the page is guarded. | |
13892 | */ | |
13893 | static bool is_guarded_page(CPUARMState *env, DisasContext *s) | |
13894 | { | |
13895 | #ifdef CONFIG_USER_ONLY | |
13896 | return false; /* FIXME */ | |
13897 | #else | |
13898 | uint64_t addr = s->base.pc_first; | |
13899 | int mmu_idx = arm_to_core_mmu_idx(s->mmu_idx); | |
13900 | unsigned int index = tlb_index(env, mmu_idx, addr); | |
13901 | CPUTLBEntry *entry = tlb_entry(env, mmu_idx, addr); | |
13902 | ||
13903 | /* | |
13904 | * We test this immediately after reading an insn, which means | |
13905 | * that any normal page must be in the TLB. The only exception | |
13906 | * would be for executing from flash or device memory, which | |
13907 | * does not retain the TLB entry. | |
13908 | * | |
13909 | * FIXME: Assume false for those, for now. We could use | |
13910 | * arm_cpu_get_phys_page_attrs_debug to re-read the page | |
13911 | * table entry even for that case. | |
13912 | */ | |
13913 | return (tlb_hit(entry->addr_code, addr) && | |
13914 | env->iotlb[mmu_idx][index].attrs.target_tlb_bit0); | |
13915 | #endif | |
13916 | } | |
13917 | ||
13918 | /** | |
13919 | * btype_destination_ok: | |
13920 | * @insn: The instruction at the branch destination | |
13921 | * @bt: SCTLR_ELx.BT | |
13922 | * @btype: PSTATE.BTYPE, and is non-zero | |
13923 | * | |
13924 | * On a guarded page, there are a limited number of insns | |
13925 | * that may be present at the branch target: | |
13926 | * - branch target identifiers, | |
13927 | * - paciasp, pacibsp, | |
13928 | * - BRK insn | |
13929 | * - HLT insn | |
13930 | * Anything else causes a Branch Target Exception. | |
13931 | * | |
13932 | * Return true if the branch is compatible, false to raise BTITRAP. | |
13933 | */ | |
13934 | static bool btype_destination_ok(uint32_t insn, bool bt, int btype) | |
13935 | { | |
13936 | if ((insn & 0xfffff01fu) == 0xd503201fu) { | |
13937 | /* HINT space */ | |
13938 | switch (extract32(insn, 5, 7)) { | |
13939 | case 0b011001: /* PACIASP */ | |
13940 | case 0b011011: /* PACIBSP */ | |
13941 | /* | |
13942 | * If SCTLR_ELx.BT, then PACI*SP are not compatible | |
13943 | * with btype == 3. Otherwise all btype are ok. | |
13944 | */ | |
13945 | return !bt || btype != 3; | |
13946 | case 0b100000: /* BTI */ | |
13947 | /* Not compatible with any btype. */ | |
13948 | return false; | |
13949 | case 0b100010: /* BTI c */ | |
13950 | /* Not compatible with btype == 3 */ | |
13951 | return btype != 3; | |
13952 | case 0b100100: /* BTI j */ | |
13953 | /* Not compatible with btype == 2 */ | |
13954 | return btype != 2; | |
13955 | case 0b100110: /* BTI jc */ | |
13956 | /* Compatible with any btype. */ | |
13957 | return true; | |
13958 | } | |
13959 | } else { | |
13960 | switch (insn & 0xffe0001fu) { | |
13961 | case 0xd4200000u: /* BRK */ | |
13962 | case 0xd4400000u: /* HLT */ | |
13963 | /* Give priority to the breakpoint exception. */ | |
13964 | return true; | |
13965 | } | |
13966 | } | |
13967 | return false; | |
13968 | } | |
13969 | ||
ad7ee8a2 | 13970 | /* C3.1 A64 instruction index by encoding */ |
40f860cd | 13971 | static void disas_a64_insn(CPUARMState *env, DisasContext *s) |
14ade10f AG |
13972 | { |
13973 | uint32_t insn; | |
13974 | ||
f9fd40eb | 13975 | insn = arm_ldl_code(env, s->pc, s->sctlr_b); |
14ade10f AG |
13976 | s->insn = insn; |
13977 | s->pc += 4; | |
13978 | ||
90e49638 PM |
13979 | s->fp_access_checked = false; |
13980 | ||
51bf0d7a RH |
13981 | if (dc_isar_feature(aa64_bti, s)) { |
13982 | if (s->base.num_insns == 1) { | |
13983 | /* | |
13984 | * At the first insn of the TB, compute s->guarded_page. | |
13985 | * We delayed computing this until successfully reading | |
13986 | * the first insn of the TB, above. This (mostly) ensures | |
13987 | * that the softmmu tlb entry has been populated, and the | |
13988 | * page table GP bit is available. | |
13989 | * | |
13990 | * Note that we need to compute this even if btype == 0, | |
13991 | * because this value is used for BR instructions later | |
13992 | * where ENV is not available. | |
13993 | */ | |
13994 | s->guarded_page = is_guarded_page(env, s); | |
13995 | ||
13996 | /* First insn can have btype set to non-zero. */ | |
13997 | tcg_debug_assert(s->btype >= 0); | |
13998 | ||
13999 | /* | |
14000 | * Note that the Branch Target Exception has fairly high | |
14001 | * priority -- below debugging exceptions but above most | |
14002 | * everything else. This allows us to handle this now | |
14003 | * instead of waiting until the insn is otherwise decoded. | |
14004 | */ | |
14005 | if (s->btype != 0 | |
14006 | && s->guarded_page | |
14007 | && !btype_destination_ok(insn, s->bt, s->btype)) { | |
14008 | gen_exception_insn(s, 4, EXCP_UDEF, syn_btitrap(s->btype), | |
14009 | default_exception_el(s)); | |
14010 | return; | |
14011 | } | |
14012 | } else { | |
14013 | /* Not the first insn: btype must be 0. */ | |
14014 | tcg_debug_assert(s->btype == 0); | |
14015 | } | |
14016 | } | |
14017 | ||
ad7ee8a2 | 14018 | switch (extract32(insn, 25, 4)) { |
38388f7e | 14019 | case 0x0: case 0x1: case 0x3: /* UNALLOCATED */ |
14ade10f AG |
14020 | unallocated_encoding(s); |
14021 | break; | |
38388f7e | 14022 | case 0x2: |
cd208a1c | 14023 | if (!dc_isar_feature(aa64_sve, s) || !disas_sve(s, insn)) { |
38388f7e RH |
14024 | unallocated_encoding(s); |
14025 | } | |
14026 | break; | |
ad7ee8a2 CF |
14027 | case 0x8: case 0x9: /* Data processing - immediate */ |
14028 | disas_data_proc_imm(s, insn); | |
14029 | break; | |
14030 | case 0xa: case 0xb: /* Branch, exception generation and system insns */ | |
14031 | disas_b_exc_sys(s, insn); | |
14032 | break; | |
14033 | case 0x4: | |
14034 | case 0x6: | |
14035 | case 0xc: | |
14036 | case 0xe: /* Loads and stores */ | |
14037 | disas_ldst(s, insn); | |
14038 | break; | |
14039 | case 0x5: | |
14040 | case 0xd: /* Data processing - register */ | |
14041 | disas_data_proc_reg(s, insn); | |
14042 | break; | |
14043 | case 0x7: | |
14044 | case 0xf: /* Data processing - SIMD and floating point */ | |
14045 | disas_data_proc_simd_fp(s, insn); | |
14046 | break; | |
14047 | default: | |
14048 | assert(FALSE); /* all 15 cases should be handled above */ | |
14049 | break; | |
14ade10f | 14050 | } |
11e169de AG |
14051 | |
14052 | /* if we allocated any temporaries, free them here */ | |
14053 | free_tmp_a64(s); | |
51bf0d7a RH |
14054 | |
14055 | /* | |
14056 | * After execution of most insns, btype is reset to 0. | |
14057 | * Note that we set btype == -1 when the insn sets btype. | |
14058 | */ | |
14059 | if (s->btype > 0 && s->base.is_jmp != DISAS_NORETURN) { | |
14060 | reset_btype(s); | |
14061 | } | |
40f860cd | 14062 | } |
14ade10f | 14063 | |
b542683d EC |
14064 | static void aarch64_tr_init_disas_context(DisasContextBase *dcbase, |
14065 | CPUState *cpu) | |
40f860cd | 14066 | { |
dcba3a8d | 14067 | DisasContext *dc = container_of(dcbase, DisasContext, base); |
5c039906 LV |
14068 | CPUARMState *env = cpu->env_ptr; |
14069 | ARMCPU *arm_cpu = arm_env_get_cpu(env); | |
aad821ac RH |
14070 | uint32_t tb_flags = dc->base.tb->flags; |
14071 | int bound, core_mmu_idx; | |
40f860cd | 14072 | |
962fcbf2 | 14073 | dc->isar = &arm_cpu->isar; |
dcba3a8d | 14074 | dc->pc = dc->base.pc_first; |
40f860cd PM |
14075 | dc->condjmp = 0; |
14076 | ||
14077 | dc->aarch64 = 1; | |
cef9ee70 SS |
14078 | /* If we are coming from secure EL0 in a system with a 32-bit EL3, then |
14079 | * there is no secure EL1, so we route exceptions to EL3. | |
14080 | */ | |
14081 | dc->secure_routed_to_el3 = arm_feature(env, ARM_FEATURE_EL3) && | |
14082 | !arm_el_is_aa64(env, 3); | |
40f860cd | 14083 | dc->thumb = 0; |
f9fd40eb | 14084 | dc->sctlr_b = 0; |
aad821ac | 14085 | dc->be_data = FIELD_EX32(tb_flags, TBFLAG_ANY, BE_DATA) ? MO_BE : MO_LE; |
40f860cd PM |
14086 | dc->condexec_mask = 0; |
14087 | dc->condexec_cond = 0; | |
aad821ac RH |
14088 | core_mmu_idx = FIELD_EX32(tb_flags, TBFLAG_ANY, MMUIDX); |
14089 | dc->mmu_idx = core_to_arm_mmu_idx(env, core_mmu_idx); | |
476a4692 | 14090 | dc->tbii = FIELD_EX32(tb_flags, TBFLAG_A64, TBII); |
4a9ee99d | 14091 | dc->tbid = FIELD_EX32(tb_flags, TBFLAG_A64, TBID); |
c1e37810 | 14092 | dc->current_el = arm_mmu_idx_to_el(dc->mmu_idx); |
40f860cd | 14093 | #if !defined(CONFIG_USER_ONLY) |
c1e37810 | 14094 | dc->user = (dc->current_el == 0); |
40f860cd | 14095 | #endif |
aad821ac RH |
14096 | dc->fp_excp_el = FIELD_EX32(tb_flags, TBFLAG_ANY, FPEXC_EL); |
14097 | dc->sve_excp_el = FIELD_EX32(tb_flags, TBFLAG_A64, SVEEXC_EL); | |
14098 | dc->sve_len = (FIELD_EX32(tb_flags, TBFLAG_A64, ZCR_LEN) + 1) * 16; | |
0816ef1b | 14099 | dc->pauth_active = FIELD_EX32(tb_flags, TBFLAG_A64, PAUTH_ACTIVE); |
08f1434a RH |
14100 | dc->bt = FIELD_EX32(tb_flags, TBFLAG_A64, BT); |
14101 | dc->btype = FIELD_EX32(tb_flags, TBFLAG_A64, BTYPE); | |
40f860cd PM |
14102 | dc->vec_len = 0; |
14103 | dc->vec_stride = 0; | |
5c039906 | 14104 | dc->cp_regs = arm_cpu->cp_regs; |
a984e42c | 14105 | dc->features = env->features; |
40f860cd | 14106 | |
7ea47fe7 PM |
14107 | /* Single step state. The code-generation logic here is: |
14108 | * SS_ACTIVE == 0: | |
14109 | * generate code with no special handling for single-stepping (except | |
14110 | * that anything that can make us go to SS_ACTIVE == 1 must end the TB; | |
14111 | * this happens anyway because those changes are all system register or | |
14112 | * PSTATE writes). | |
14113 | * SS_ACTIVE == 1, PSTATE.SS == 1: (active-not-pending) | |
14114 | * emit code for one insn | |
14115 | * emit code to clear PSTATE.SS | |
14116 | * emit code to generate software step exception for completed step | |
14117 | * end TB (as usual for having generated an exception) | |
14118 | * SS_ACTIVE == 1, PSTATE.SS == 0: (active-pending) | |
14119 | * emit code to generate a software step exception | |
14120 | * end the TB | |
14121 | */ | |
aad821ac RH |
14122 | dc->ss_active = FIELD_EX32(tb_flags, TBFLAG_ANY, SS_ACTIVE); |
14123 | dc->pstate_ss = FIELD_EX32(tb_flags, TBFLAG_ANY, PSTATE_SS); | |
7ea47fe7 | 14124 | dc->is_ldex = false; |
dcbff19b | 14125 | dc->ss_same_el = (arm_debug_target_el(env) == dc->current_el); |
7ea47fe7 | 14126 | |
dcc3a212 RH |
14127 | /* Bound the number of insns to execute to those left on the page. */ |
14128 | bound = -(dc->base.pc_first | TARGET_PAGE_MASK) / 4; | |
14129 | ||
14130 | /* If architectural single step active, limit to 1. */ | |
14131 | if (dc->ss_active) { | |
14132 | bound = 1; | |
14133 | } | |
b542683d | 14134 | dc->base.max_insns = MIN(dc->base.max_insns, bound); |
24299c89 | 14135 | |
11e169de | 14136 | init_tmp_a64_array(dc); |
5c039906 LV |
14137 | } |
14138 | ||
23169224 LV |
14139 | static void aarch64_tr_tb_start(DisasContextBase *db, CPUState *cpu) |
14140 | { | |
23169224 LV |
14141 | } |
14142 | ||
a68956ad LV |
14143 | static void aarch64_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) |
14144 | { | |
14145 | DisasContext *dc = container_of(dcbase, DisasContext, base); | |
14146 | ||
a68956ad | 14147 | tcg_gen_insn_start(dc->pc, 0, 0); |
15fa08f8 | 14148 | dc->insn_start = tcg_last_op(); |
a68956ad LV |
14149 | } |
14150 | ||
0cb56b37 LV |
14151 | static bool aarch64_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu, |
14152 | const CPUBreakpoint *bp) | |
14153 | { | |
14154 | DisasContext *dc = container_of(dcbase, DisasContext, base); | |
14155 | ||
14156 | if (bp->flags & BP_CPU) { | |
14157 | gen_a64_set_pc_im(dc->pc); | |
14158 | gen_helper_check_breakpoints(cpu_env); | |
14159 | /* End the TB early; it likely won't be executed */ | |
14160 | dc->base.is_jmp = DISAS_TOO_MANY; | |
14161 | } else { | |
14162 | gen_exception_internal_insn(dc, 0, EXCP_DEBUG); | |
14163 | /* The address covered by the breakpoint must be | |
14164 | included in [tb->pc, tb->pc + tb->size) in order | |
14165 | to for it to be properly cleared -- thus we | |
14166 | increment the PC here so that the logic setting | |
14167 | tb->size below does the right thing. */ | |
14168 | dc->pc += 4; | |
14169 | dc->base.is_jmp = DISAS_NORETURN; | |
14170 | } | |
14171 | ||
14172 | return true; | |
14173 | } | |
14174 | ||
24299c89 LV |
14175 | static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) |
14176 | { | |
14177 | DisasContext *dc = container_of(dcbase, DisasContext, base); | |
14178 | CPUARMState *env = cpu->env_ptr; | |
14179 | ||
14180 | if (dc->ss_active && !dc->pstate_ss) { | |
14181 | /* Singlestep state is Active-pending. | |
14182 | * If we're in this state at the start of a TB then either | |
14183 | * a) we just took an exception to an EL which is being debugged | |
14184 | * and this is the first insn in the exception handler | |
14185 | * b) debug exceptions were masked and we just unmasked them | |
14186 | * without changing EL (eg by clearing PSTATE.D) | |
14187 | * In either case we're going to take a swstep exception in the | |
14188 | * "did not step an insn" case, and so the syndrome ISV and EX | |
14189 | * bits should be zero. | |
14190 | */ | |
14191 | assert(dc->base.num_insns == 1); | |
14192 | gen_exception(EXCP_UDEF, syn_swstep(dc->ss_same_el, 0, 0), | |
14193 | default_exception_el(dc)); | |
14194 | dc->base.is_jmp = DISAS_NORETURN; | |
14195 | } else { | |
14196 | disas_a64_insn(env, dc); | |
14197 | } | |
14198 | ||
24299c89 | 14199 | dc->base.pc_next = dc->pc; |
23169224 | 14200 | translator_loop_temp_check(&dc->base); |
24299c89 LV |
14201 | } |
14202 | ||
be407964 LV |
14203 | static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) |
14204 | { | |
14205 | DisasContext *dc = container_of(dcbase, DisasContext, base); | |
14206 | ||
14207 | if (unlikely(dc->base.singlestep_enabled || dc->ss_active)) { | |
14208 | /* Note that this means single stepping WFI doesn't halt the CPU. | |
14209 | * For conditional branch insns this is harmless unreachable code as | |
14210 | * gen_goto_tb() has already handled emitting the debug exception | |
14211 | * (and thus a tb-jump is not possible when singlestepping). | |
14212 | */ | |
14213 | switch (dc->base.is_jmp) { | |
14214 | default: | |
14215 | gen_a64_set_pc_im(dc->pc); | |
14216 | /* fall through */ | |
dddbba99 | 14217 | case DISAS_EXIT: |
be407964 LV |
14218 | case DISAS_JUMP: |
14219 | if (dc->base.singlestep_enabled) { | |
14220 | gen_exception_internal(EXCP_DEBUG); | |
14221 | } else { | |
14222 | gen_step_complete_exception(dc); | |
14223 | } | |
14224 | break; | |
14225 | case DISAS_NORETURN: | |
14226 | break; | |
14227 | } | |
14228 | } else { | |
14229 | switch (dc->base.is_jmp) { | |
14230 | case DISAS_NEXT: | |
14231 | case DISAS_TOO_MANY: | |
14232 | gen_goto_tb(dc, 1, dc->pc); | |
14233 | break; | |
14234 | default: | |
14235 | case DISAS_UPDATE: | |
14236 | gen_a64_set_pc_im(dc->pc); | |
14237 | /* fall through */ | |
be407964 | 14238 | case DISAS_EXIT: |
07ea28b4 | 14239 | tcg_gen_exit_tb(NULL, 0); |
be407964 | 14240 | break; |
a75a52d6 VK |
14241 | case DISAS_JUMP: |
14242 | tcg_gen_lookup_and_goto_ptr(); | |
14243 | break; | |
be407964 LV |
14244 | case DISAS_NORETURN: |
14245 | case DISAS_SWI: | |
14246 | break; | |
14247 | case DISAS_WFE: | |
14248 | gen_a64_set_pc_im(dc->pc); | |
14249 | gen_helper_wfe(cpu_env); | |
14250 | break; | |
14251 | case DISAS_YIELD: | |
14252 | gen_a64_set_pc_im(dc->pc); | |
14253 | gen_helper_yield(cpu_env); | |
14254 | break; | |
14255 | case DISAS_WFI: | |
58803318 | 14256 | { |
be407964 LV |
14257 | /* This is a special case because we don't want to just halt the CPU |
14258 | * if trying to debug across a WFI. | |
14259 | */ | |
58803318 SS |
14260 | TCGv_i32 tmp = tcg_const_i32(4); |
14261 | ||
be407964 | 14262 | gen_a64_set_pc_im(dc->pc); |
58803318 SS |
14263 | gen_helper_wfi(cpu_env, tmp); |
14264 | tcg_temp_free_i32(tmp); | |
be407964 LV |
14265 | /* The helper doesn't necessarily throw an exception, but we |
14266 | * must go back to the main loop to check for interrupts anyway. | |
14267 | */ | |
07ea28b4 | 14268 | tcg_gen_exit_tb(NULL, 0); |
be407964 LV |
14269 | break; |
14270 | } | |
58803318 | 14271 | } |
be407964 | 14272 | } |
23169224 LV |
14273 | |
14274 | /* Functions above can change dc->pc, so re-align db->pc_next */ | |
14275 | dc->base.pc_next = dc->pc; | |
be407964 LV |
14276 | } |
14277 | ||
58350fa4 LV |
14278 | static void aarch64_tr_disas_log(const DisasContextBase *dcbase, |
14279 | CPUState *cpu) | |
14280 | { | |
14281 | DisasContext *dc = container_of(dcbase, DisasContext, base); | |
14282 | ||
14283 | qemu_log("IN: %s\n", lookup_symbol(dc->base.pc_first)); | |
1d48474d | 14284 | log_target_disas(cpu, dc->base.pc_first, dc->base.tb->size); |
58350fa4 LV |
14285 | } |
14286 | ||
23169224 LV |
14287 | const TranslatorOps aarch64_translator_ops = { |
14288 | .init_disas_context = aarch64_tr_init_disas_context, | |
14289 | .tb_start = aarch64_tr_tb_start, | |
14290 | .insn_start = aarch64_tr_insn_start, | |
14291 | .breakpoint_check = aarch64_tr_breakpoint_check, | |
14292 | .translate_insn = aarch64_tr_translate_insn, | |
14293 | .tb_stop = aarch64_tr_tb_stop, | |
14294 | .disas_log = aarch64_tr_disas_log, | |
14295 | }; |