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14ade10f AG |
1 | /* |
2 | * AArch64 translation | |
3 | * | |
4 | * Copyright (c) 2013 Alexander Graf <agraf@suse.de> | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
50f57e09 | 9 | * version 2.1 of the License, or (at your option) any later version. |
14ade10f AG |
10 | * |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
74c21bd0 | 19 | #include "qemu/osdep.h" |
14ade10f AG |
20 | |
21 | #include "cpu.h" | |
63c91552 | 22 | #include "exec/exec-all.h" |
dcb32f1d PMD |
23 | #include "tcg/tcg-op.h" |
24 | #include "tcg/tcg-op-gvec.h" | |
14ade10f | 25 | #include "qemu/log.h" |
1d854765 | 26 | #include "arm_ldst.h" |
14ade10f | 27 | #include "translate.h" |
ccd38087 | 28 | #include "internals.h" |
14ade10f AG |
29 | #include "qemu/host-utils.h" |
30 | ||
6b5fe137 | 31 | #include "semihosting/semihost.h" |
40f860cd PM |
32 | #include "exec/gen-icount.h" |
33 | ||
2ef6175a RH |
34 | #include "exec/helper-proto.h" |
35 | #include "exec/helper-gen.h" | |
508127e2 | 36 | #include "exec/log.h" |
14ade10f | 37 | |
a7e30d84 | 38 | #include "trace-tcg.h" |
8c71baed | 39 | #include "translate-a64.h" |
62823083 | 40 | #include "qemu/atomic128.h" |
a7e30d84 | 41 | |
14ade10f AG |
42 | static TCGv_i64 cpu_X[32]; |
43 | static TCGv_i64 cpu_pc; | |
14ade10f | 44 | |
fa2ef212 | 45 | /* Load/store exclusive handling */ |
fa2ef212 | 46 | static TCGv_i64 cpu_exclusive_high; |
fa2ef212 | 47 | |
14ade10f AG |
48 | static const char *regnames[] = { |
49 | "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", | |
50 | "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", | |
51 | "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", | |
52 | "x24", "x25", "x26", "x27", "x28", "x29", "lr", "sp" | |
53 | }; | |
54 | ||
832ffa1c AG |
55 | enum a64_shift_type { |
56 | A64_SHIFT_TYPE_LSL = 0, | |
57 | A64_SHIFT_TYPE_LSR = 1, | |
58 | A64_SHIFT_TYPE_ASR = 2, | |
59 | A64_SHIFT_TYPE_ROR = 3 | |
60 | }; | |
61 | ||
384b26fb AB |
62 | /* Table based decoder typedefs - used when the relevant bits for decode |
63 | * are too awkwardly scattered across the instruction (eg SIMD). | |
64 | */ | |
65 | typedef void AArch64DecodeFn(DisasContext *s, uint32_t insn); | |
66 | ||
67 | typedef struct AArch64DecodeTable { | |
68 | uint32_t pattern; | |
69 | uint32_t mask; | |
70 | AArch64DecodeFn *disas_fn; | |
71 | } AArch64DecodeTable; | |
72 | ||
14ade10f AG |
73 | /* initialize TCG globals. */ |
74 | void a64_translate_init(void) | |
75 | { | |
76 | int i; | |
77 | ||
e1ccc054 | 78 | cpu_pc = tcg_global_mem_new_i64(cpu_env, |
14ade10f AG |
79 | offsetof(CPUARMState, pc), |
80 | "pc"); | |
81 | for (i = 0; i < 32; i++) { | |
e1ccc054 | 82 | cpu_X[i] = tcg_global_mem_new_i64(cpu_env, |
14ade10f AG |
83 | offsetof(CPUARMState, xregs[i]), |
84 | regnames[i]); | |
85 | } | |
86 | ||
e1ccc054 | 87 | cpu_exclusive_high = tcg_global_mem_new_i64(cpu_env, |
fa2ef212 | 88 | offsetof(CPUARMState, exclusive_high), "exclusive_high"); |
14ade10f AG |
89 | } |
90 | ||
cc28fc30 RH |
91 | /* |
92 | * Return the core mmu_idx to use for A64 "unprivileged load/store" insns | |
93 | */ | |
94 | static int get_a64_user_mem_index(DisasContext *s) | |
579d21cc | 95 | { |
cc28fc30 RH |
96 | /* |
97 | * If AccType_UNPRIV is not used, the insn uses AccType_NORMAL, | |
98 | * which is the usual mmu_idx for this cpu state. | |
579d21cc | 99 | */ |
cc28fc30 | 100 | ARMMMUIdx useridx = s->mmu_idx; |
8bd5c820 | 101 | |
cc28fc30 RH |
102 | if (s->unpriv) { |
103 | /* | |
104 | * We have pre-computed the condition for AccType_UNPRIV. | |
105 | * Therefore we should never get here with a mmu_idx for | |
106 | * which we do not know the corresponding user mmu_idx. | |
107 | */ | |
108 | switch (useridx) { | |
109 | case ARMMMUIdx_E10_1: | |
452ef8cb | 110 | case ARMMMUIdx_E10_1_PAN: |
cc28fc30 RH |
111 | useridx = ARMMMUIdx_E10_0; |
112 | break; | |
113 | case ARMMMUIdx_E20_2: | |
452ef8cb | 114 | case ARMMMUIdx_E20_2_PAN: |
cc28fc30 RH |
115 | useridx = ARMMMUIdx_E20_0; |
116 | break; | |
117 | case ARMMMUIdx_SE10_1: | |
452ef8cb | 118 | case ARMMMUIdx_SE10_1_PAN: |
cc28fc30 RH |
119 | useridx = ARMMMUIdx_SE10_0; |
120 | break; | |
b6ad6062 RDC |
121 | case ARMMMUIdx_SE20_2: |
122 | case ARMMMUIdx_SE20_2_PAN: | |
123 | useridx = ARMMMUIdx_SE20_0; | |
124 | break; | |
cc28fc30 RH |
125 | default: |
126 | g_assert_not_reached(); | |
127 | } | |
579d21cc | 128 | } |
8bd5c820 | 129 | return arm_to_core_mmu_idx(useridx); |
579d21cc PM |
130 | } |
131 | ||
51bf0d7a RH |
132 | static void reset_btype(DisasContext *s) |
133 | { | |
134 | if (s->btype != 0) { | |
135 | TCGv_i32 zero = tcg_const_i32(0); | |
136 | tcg_gen_st_i32(zero, cpu_env, offsetof(CPUARMState, btype)); | |
137 | tcg_temp_free_i32(zero); | |
138 | s->btype = 0; | |
139 | } | |
140 | } | |
141 | ||
001d47b6 RH |
142 | static void set_btype(DisasContext *s, int val) |
143 | { | |
144 | TCGv_i32 tcg_val; | |
145 | ||
146 | /* BTYPE is a 2-bit field, and 0 should be done with reset_btype. */ | |
147 | tcg_debug_assert(val >= 1 && val <= 3); | |
148 | ||
149 | tcg_val = tcg_const_i32(val); | |
150 | tcg_gen_st_i32(tcg_val, cpu_env, offsetof(CPUARMState, btype)); | |
151 | tcg_temp_free_i32(tcg_val); | |
152 | s->btype = -1; | |
153 | } | |
154 | ||
14ade10f AG |
155 | void gen_a64_set_pc_im(uint64_t val) |
156 | { | |
157 | tcg_gen_movi_i64(cpu_pc, val); | |
158 | } | |
159 | ||
4a9ee99d RH |
160 | /* |
161 | * Handle Top Byte Ignore (TBI) bits. | |
6feecb8b | 162 | * |
4a9ee99d | 163 | * If address tagging is enabled via the TCR TBI bits: |
6feecb8b TH |
164 | * + for EL2 and EL3 there is only one TBI bit, and if it is set |
165 | * then the address is zero-extended, clearing bits [63:56] | |
166 | * + for EL0 and EL1, TBI0 controls addresses with bit 55 == 0 | |
167 | * and TBI1 controls addressses with bit 55 == 1. | |
168 | * If the appropriate TBI bit is set for the address then | |
169 | * the address is sign-extended from bit 55 into bits [63:56] | |
170 | * | |
4a9ee99d | 171 | * Here We have concatenated TBI{1,0} into tbi. |
6feecb8b | 172 | */ |
4a9ee99d RH |
173 | static void gen_top_byte_ignore(DisasContext *s, TCGv_i64 dst, |
174 | TCGv_i64 src, int tbi) | |
6feecb8b | 175 | { |
4a9ee99d RH |
176 | if (tbi == 0) { |
177 | /* Load unmodified address */ | |
178 | tcg_gen_mov_i64(dst, src); | |
339370b9 | 179 | } else if (!regime_has_2_ranges(s->mmu_idx)) { |
4a9ee99d RH |
180 | /* Force tag byte to all zero */ |
181 | tcg_gen_extract_i64(dst, src, 0, 56); | |
182 | } else { | |
183 | /* Sign-extend from bit 55. */ | |
184 | tcg_gen_sextract_i64(dst, src, 0, 56); | |
6feecb8b | 185 | |
2169b5c6 RH |
186 | switch (tbi) { |
187 | case 1: | |
188 | /* tbi0 but !tbi1: only use the extension if positive */ | |
189 | tcg_gen_and_i64(dst, dst, src); | |
190 | break; | |
191 | case 2: | |
192 | /* !tbi0 but tbi1: only use the extension if negative */ | |
193 | tcg_gen_or_i64(dst, dst, src); | |
194 | break; | |
195 | case 3: | |
196 | /* tbi0 and tbi1: always use the extension */ | |
197 | break; | |
198 | default: | |
199 | g_assert_not_reached(); | |
6feecb8b TH |
200 | } |
201 | } | |
4a9ee99d | 202 | } |
8733d762 | 203 | |
4a9ee99d RH |
204 | static void gen_a64_set_pc(DisasContext *s, TCGv_i64 src) |
205 | { | |
206 | /* | |
207 | * If address tagging is enabled for instructions via the TCR TBI bits, | |
208 | * then loading an address into the PC will clear out any tag. | |
209 | */ | |
210 | gen_top_byte_ignore(s, cpu_pc, src, s->tbii); | |
6feecb8b TH |
211 | } |
212 | ||
3a471103 | 213 | /* |
0a405be2 RH |
214 | * Handle MTE and/or TBI. |
215 | * | |
216 | * For TBI, ideally, we would do nothing. Proper behaviour on fault is | |
217 | * for the tag to be present in the FAR_ELx register. But for user-only | |
218 | * mode we do not have a TLB with which to implement this, so we must | |
219 | * remove the top byte now. | |
220 | * | |
221 | * Always return a fresh temporary that we can increment independently | |
222 | * of the write-back address. | |
3a471103 | 223 | */ |
0a405be2 | 224 | |
9473d0ec | 225 | TCGv_i64 clean_data_tbi(DisasContext *s, TCGv_i64 addr) |
3a471103 RH |
226 | { |
227 | TCGv_i64 clean = new_tmp_a64(s); | |
38d93168 | 228 | #ifdef CONFIG_USER_ONLY |
3a471103 | 229 | gen_top_byte_ignore(s, clean, addr, s->tbid); |
38d93168 RH |
230 | #else |
231 | tcg_gen_mov_i64(clean, addr); | |
232 | #endif | |
3a471103 RH |
233 | return clean; |
234 | } | |
235 | ||
da54941f RH |
236 | /* Insert a zero tag into src, with the result at dst. */ |
237 | static void gen_address_with_allocation_tag0(TCGv_i64 dst, TCGv_i64 src) | |
238 | { | |
239 | tcg_gen_andi_i64(dst, src, ~MAKE_64BIT_MASK(56, 4)); | |
240 | } | |
241 | ||
c15294c1 RH |
242 | static void gen_probe_access(DisasContext *s, TCGv_i64 ptr, |
243 | MMUAccessType acc, int log2_size) | |
244 | { | |
245 | TCGv_i32 t_acc = tcg_const_i32(acc); | |
246 | TCGv_i32 t_idx = tcg_const_i32(get_mem_index(s)); | |
247 | TCGv_i32 t_size = tcg_const_i32(1 << log2_size); | |
248 | ||
249 | gen_helper_probe_access(cpu_env, ptr, t_acc, t_idx, t_size); | |
250 | tcg_temp_free_i32(t_acc); | |
251 | tcg_temp_free_i32(t_idx); | |
252 | tcg_temp_free_i32(t_size); | |
253 | } | |
254 | ||
0a405be2 RH |
255 | /* |
256 | * For MTE, check a single logical or atomic access. This probes a single | |
257 | * address, the exact one specified. The size and alignment of the access | |
258 | * is not relevant to MTE, per se, but watchpoints do require the size, | |
259 | * and we want to recognize those before making any other changes to state. | |
260 | */ | |
261 | static TCGv_i64 gen_mte_check1_mmuidx(DisasContext *s, TCGv_i64 addr, | |
262 | bool is_write, bool tag_checked, | |
263 | int log2_size, bool is_unpriv, | |
264 | int core_idx) | |
265 | { | |
266 | if (tag_checked && s->mte_active[is_unpriv]) { | |
267 | TCGv_i32 tcg_desc; | |
268 | TCGv_i64 ret; | |
269 | int desc = 0; | |
270 | ||
271 | desc = FIELD_DP32(desc, MTEDESC, MIDX, core_idx); | |
272 | desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid); | |
273 | desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma); | |
274 | desc = FIELD_DP32(desc, MTEDESC, WRITE, is_write); | |
275 | desc = FIELD_DP32(desc, MTEDESC, ESIZE, 1 << log2_size); | |
276 | tcg_desc = tcg_const_i32(desc); | |
277 | ||
278 | ret = new_tmp_a64(s); | |
279 | gen_helper_mte_check1(ret, cpu_env, tcg_desc, addr); | |
280 | tcg_temp_free_i32(tcg_desc); | |
281 | ||
282 | return ret; | |
283 | } | |
284 | return clean_data_tbi(s, addr); | |
285 | } | |
286 | ||
287 | TCGv_i64 gen_mte_check1(DisasContext *s, TCGv_i64 addr, bool is_write, | |
288 | bool tag_checked, int log2_size) | |
289 | { | |
290 | return gen_mte_check1_mmuidx(s, addr, is_write, tag_checked, log2_size, | |
291 | false, get_mem_index(s)); | |
292 | } | |
293 | ||
73ceeb00 RH |
294 | /* |
295 | * For MTE, check multiple logical sequential accesses. | |
296 | */ | |
297 | TCGv_i64 gen_mte_checkN(DisasContext *s, TCGv_i64 addr, bool is_write, | |
298 | bool tag_checked, int log2_esize, int total_size) | |
299 | { | |
300 | if (tag_checked && s->mte_active[0] && total_size != (1 << log2_esize)) { | |
301 | TCGv_i32 tcg_desc; | |
302 | TCGv_i64 ret; | |
303 | int desc = 0; | |
304 | ||
305 | desc = FIELD_DP32(desc, MTEDESC, MIDX, get_mem_index(s)); | |
306 | desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid); | |
307 | desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma); | |
308 | desc = FIELD_DP32(desc, MTEDESC, WRITE, is_write); | |
309 | desc = FIELD_DP32(desc, MTEDESC, ESIZE, 1 << log2_esize); | |
310 | desc = FIELD_DP32(desc, MTEDESC, TSIZE, total_size); | |
311 | tcg_desc = tcg_const_i32(desc); | |
312 | ||
313 | ret = new_tmp_a64(s); | |
314 | gen_helper_mte_checkN(ret, cpu_env, tcg_desc, addr); | |
315 | tcg_temp_free_i32(tcg_desc); | |
316 | ||
317 | return ret; | |
318 | } | |
319 | return gen_mte_check1(s, addr, is_write, tag_checked, log2_esize); | |
320 | } | |
321 | ||
259cb684 RH |
322 | typedef struct DisasCompare64 { |
323 | TCGCond cond; | |
324 | TCGv_i64 value; | |
325 | } DisasCompare64; | |
326 | ||
327 | static void a64_test_cc(DisasCompare64 *c64, int cc) | |
328 | { | |
329 | DisasCompare c32; | |
330 | ||
331 | arm_test_cc(&c32, cc); | |
332 | ||
333 | /* Sign-extend the 32-bit value so that the GE/LT comparisons work | |
334 | * properly. The NE/EQ comparisons are also fine with this choice. */ | |
335 | c64->cond = c32.cond; | |
336 | c64->value = tcg_temp_new_i64(); | |
337 | tcg_gen_ext_i32_i64(c64->value, c32.value); | |
338 | ||
339 | arm_free_cc(&c32); | |
340 | } | |
341 | ||
342 | static void a64_free_cc(DisasCompare64 *c64) | |
343 | { | |
344 | tcg_temp_free_i64(c64->value); | |
345 | } | |
346 | ||
d4a2dc67 | 347 | static void gen_exception_internal(int excp) |
14ade10f | 348 | { |
d4a2dc67 PM |
349 | TCGv_i32 tcg_excp = tcg_const_i32(excp); |
350 | ||
351 | assert(excp_is_internal(excp)); | |
352 | gen_helper_exception_internal(cpu_env, tcg_excp); | |
353 | tcg_temp_free_i32(tcg_excp); | |
354 | } | |
355 | ||
aee828e7 | 356 | static void gen_exception_internal_insn(DisasContext *s, uint64_t pc, int excp) |
d4a2dc67 | 357 | { |
aee828e7 | 358 | gen_a64_set_pc_im(pc); |
d4a2dc67 | 359 | gen_exception_internal(excp); |
dcba3a8d | 360 | s->base.is_jmp = DISAS_NORETURN; |
14ade10f AG |
361 | } |
362 | ||
a767fac8 | 363 | static void gen_exception_insn(DisasContext *s, uint64_t pc, int excp, |
73710361 | 364 | uint32_t syndrome, uint32_t target_el) |
14ade10f | 365 | { |
a767fac8 | 366 | gen_a64_set_pc_im(pc); |
73710361 | 367 | gen_exception(excp, syndrome, target_el); |
dcba3a8d | 368 | s->base.is_jmp = DISAS_NORETURN; |
40f860cd PM |
369 | } |
370 | ||
06bcbda3 | 371 | static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syndrome) |
c900a2e6 PM |
372 | { |
373 | TCGv_i32 tcg_syn; | |
374 | ||
06bcbda3 | 375 | gen_a64_set_pc_im(s->pc_curr); |
c900a2e6 PM |
376 | tcg_syn = tcg_const_i32(syndrome); |
377 | gen_helper_exception_bkpt_insn(cpu_env, tcg_syn); | |
378 | tcg_temp_free_i32(tcg_syn); | |
379 | s->base.is_jmp = DISAS_NORETURN; | |
380 | } | |
381 | ||
7ea47fe7 PM |
382 | static void gen_step_complete_exception(DisasContext *s) |
383 | { | |
384 | /* We just completed step of an insn. Move from Active-not-pending | |
385 | * to Active-pending, and then also take the swstep exception. | |
386 | * This corresponds to making the (IMPDEF) choice to prioritize | |
387 | * swstep exceptions over asynchronous exceptions taken to an exception | |
388 | * level where debug is disabled. This choice has the advantage that | |
389 | * we do not need to maintain internal state corresponding to the | |
390 | * ISV/EX syndrome bits between completion of the step and generation | |
391 | * of the exception, and our syndrome information is always correct. | |
392 | */ | |
393 | gen_ss_advance(s); | |
c1d5f50f | 394 | gen_swstep_exception(s, 1, s->is_ldex); |
dcba3a8d | 395 | s->base.is_jmp = DISAS_NORETURN; |
7ea47fe7 PM |
396 | } |
397 | ||
40f860cd PM |
398 | static inline bool use_goto_tb(DisasContext *s, int n, uint64_t dest) |
399 | { | |
7ea47fe7 PM |
400 | /* No direct tb linking with singlestep (either QEMU's or the ARM |
401 | * debug architecture kind) or deterministic io | |
402 | */ | |
c5a49c63 EC |
403 | if (s->base.singlestep_enabled || s->ss_active || |
404 | (tb_cflags(s->base.tb) & CF_LAST_IO)) { | |
40f860cd PM |
405 | return false; |
406 | } | |
407 | ||
90aa39a1 | 408 | #ifndef CONFIG_USER_ONLY |
40f860cd | 409 | /* Only link tbs from inside the same guest page */ |
dcba3a8d | 410 | if ((s->base.tb->pc & TARGET_PAGE_MASK) != (dest & TARGET_PAGE_MASK)) { |
40f860cd PM |
411 | return false; |
412 | } | |
90aa39a1 | 413 | #endif |
40f860cd PM |
414 | |
415 | return true; | |
416 | } | |
417 | ||
418 | static inline void gen_goto_tb(DisasContext *s, int n, uint64_t dest) | |
419 | { | |
d9971435 | 420 | const TranslationBlock *tb; |
40f860cd | 421 | |
dcba3a8d | 422 | tb = s->base.tb; |
40f860cd PM |
423 | if (use_goto_tb(s, n, dest)) { |
424 | tcg_gen_goto_tb(n); | |
425 | gen_a64_set_pc_im(dest); | |
07ea28b4 | 426 | tcg_gen_exit_tb(tb, n); |
dcba3a8d | 427 | s->base.is_jmp = DISAS_NORETURN; |
40f860cd PM |
428 | } else { |
429 | gen_a64_set_pc_im(dest); | |
7ea47fe7 PM |
430 | if (s->ss_active) { |
431 | gen_step_complete_exception(s); | |
dcba3a8d | 432 | } else if (s->base.singlestep_enabled) { |
d4a2dc67 | 433 | gen_exception_internal(EXCP_DEBUG); |
cc9c1ed1 | 434 | } else { |
7f11636d | 435 | tcg_gen_lookup_and_goto_ptr(); |
dcba3a8d | 436 | s->base.is_jmp = DISAS_NORETURN; |
40f860cd | 437 | } |
40f860cd | 438 | } |
14ade10f AG |
439 | } |
440 | ||
429a71d6 RH |
441 | void unallocated_encoding(DisasContext *s) |
442 | { | |
443 | /* Unallocated and reserved encodings are uncategorized */ | |
444 | gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(), | |
445 | default_exception_el(s)); | |
446 | } | |
447 | ||
11e169de AG |
448 | static void init_tmp_a64_array(DisasContext *s) |
449 | { | |
450 | #ifdef CONFIG_DEBUG_TCG | |
f764718d | 451 | memset(s->tmp_a64, 0, sizeof(s->tmp_a64)); |
11e169de AG |
452 | #endif |
453 | s->tmp_a64_count = 0; | |
454 | } | |
455 | ||
456 | static void free_tmp_a64(DisasContext *s) | |
457 | { | |
458 | int i; | |
459 | for (i = 0; i < s->tmp_a64_count; i++) { | |
460 | tcg_temp_free_i64(s->tmp_a64[i]); | |
461 | } | |
462 | init_tmp_a64_array(s); | |
463 | } | |
464 | ||
8c71baed | 465 | TCGv_i64 new_tmp_a64(DisasContext *s) |
11e169de AG |
466 | { |
467 | assert(s->tmp_a64_count < TMP_A64_MAX); | |
468 | return s->tmp_a64[s->tmp_a64_count++] = tcg_temp_new_i64(); | |
469 | } | |
470 | ||
4b4dc975 RH |
471 | TCGv_i64 new_tmp_a64_local(DisasContext *s) |
472 | { | |
473 | assert(s->tmp_a64_count < TMP_A64_MAX); | |
474 | return s->tmp_a64[s->tmp_a64_count++] = tcg_temp_local_new_i64(); | |
475 | } | |
476 | ||
8c71baed | 477 | TCGv_i64 new_tmp_a64_zero(DisasContext *s) |
11e169de AG |
478 | { |
479 | TCGv_i64 t = new_tmp_a64(s); | |
480 | tcg_gen_movi_i64(t, 0); | |
481 | return t; | |
482 | } | |
483 | ||
71b46089 AG |
484 | /* |
485 | * Register access functions | |
486 | * | |
487 | * These functions are used for directly accessing a register in where | |
488 | * changes to the final register value are likely to be made. If you | |
489 | * need to use a register for temporary calculation (e.g. index type | |
490 | * operations) use the read_* form. | |
491 | * | |
492 | * B1.2.1 Register mappings | |
493 | * | |
494 | * In instruction register encoding 31 can refer to ZR (zero register) or | |
495 | * the SP (stack pointer) depending on context. In QEMU's case we map SP | |
496 | * to cpu_X[31] and ZR accesses to a temporary which can be discarded. | |
497 | * This is the point of the _sp forms. | |
498 | */ | |
8c71baed | 499 | TCGv_i64 cpu_reg(DisasContext *s, int reg) |
11e169de AG |
500 | { |
501 | if (reg == 31) { | |
502 | return new_tmp_a64_zero(s); | |
503 | } else { | |
504 | return cpu_X[reg]; | |
505 | } | |
506 | } | |
507 | ||
71b46089 | 508 | /* register access for when 31 == SP */ |
8c71baed | 509 | TCGv_i64 cpu_reg_sp(DisasContext *s, int reg) |
71b46089 AG |
510 | { |
511 | return cpu_X[reg]; | |
512 | } | |
513 | ||
60e53388 AG |
514 | /* read a cpu register in 32bit/64bit mode. Returns a TCGv_i64 |
515 | * representing the register contents. This TCGv is an auto-freed | |
516 | * temporary so it need not be explicitly freed, and may be modified. | |
517 | */ | |
8c71baed | 518 | TCGv_i64 read_cpu_reg(DisasContext *s, int reg, int sf) |
60e53388 AG |
519 | { |
520 | TCGv_i64 v = new_tmp_a64(s); | |
521 | if (reg != 31) { | |
522 | if (sf) { | |
523 | tcg_gen_mov_i64(v, cpu_X[reg]); | |
524 | } else { | |
525 | tcg_gen_ext32u_i64(v, cpu_X[reg]); | |
526 | } | |
527 | } else { | |
528 | tcg_gen_movi_i64(v, 0); | |
529 | } | |
530 | return v; | |
531 | } | |
532 | ||
8c71baed | 533 | TCGv_i64 read_cpu_reg_sp(DisasContext *s, int reg, int sf) |
4a08d475 PM |
534 | { |
535 | TCGv_i64 v = new_tmp_a64(s); | |
536 | if (sf) { | |
537 | tcg_gen_mov_i64(v, cpu_X[reg]); | |
538 | } else { | |
539 | tcg_gen_ext32u_i64(v, cpu_X[reg]); | |
540 | } | |
541 | return v; | |
542 | } | |
543 | ||
e2f90565 PM |
544 | /* Return the offset into CPUARMState of a slice (from |
545 | * the least significant end) of FP register Qn (ie | |
546 | * Dn, Sn, Hn or Bn). | |
547 | * (Note that this is not the same mapping as for A32; see cpu.h) | |
548 | */ | |
14776ab5 | 549 | static inline int fp_reg_offset(DisasContext *s, int regno, MemOp size) |
e2f90565 | 550 | { |
9a2b5256 | 551 | return vec_reg_offset(s, regno, 0, size); |
e2f90565 PM |
552 | } |
553 | ||
554 | /* Offset of the high half of the 128 bit vector Qn */ | |
90e49638 | 555 | static inline int fp_reg_hi_offset(DisasContext *s, int regno) |
e2f90565 | 556 | { |
9a2b5256 | 557 | return vec_reg_offset(s, regno, 1, MO_64); |
e2f90565 PM |
558 | } |
559 | ||
ec73d2e0 AG |
560 | /* Convenience accessors for reading and writing single and double |
561 | * FP registers. Writing clears the upper parts of the associated | |
562 | * 128 bit vector register, as required by the architecture. | |
563 | * Note that unlike the GP register accessors, the values returned | |
564 | * by the read functions must be manually freed. | |
565 | */ | |
566 | static TCGv_i64 read_fp_dreg(DisasContext *s, int reg) | |
567 | { | |
568 | TCGv_i64 v = tcg_temp_new_i64(); | |
569 | ||
90e49638 | 570 | tcg_gen_ld_i64(v, cpu_env, fp_reg_offset(s, reg, MO_64)); |
ec73d2e0 AG |
571 | return v; |
572 | } | |
573 | ||
574 | static TCGv_i32 read_fp_sreg(DisasContext *s, int reg) | |
575 | { | |
576 | TCGv_i32 v = tcg_temp_new_i32(); | |
577 | ||
90e49638 | 578 | tcg_gen_ld_i32(v, cpu_env, fp_reg_offset(s, reg, MO_32)); |
ec73d2e0 AG |
579 | return v; |
580 | } | |
581 | ||
3d99d931 RH |
582 | static TCGv_i32 read_fp_hreg(DisasContext *s, int reg) |
583 | { | |
584 | TCGv_i32 v = tcg_temp_new_i32(); | |
585 | ||
586 | tcg_gen_ld16u_i32(v, cpu_env, fp_reg_offset(s, reg, MO_16)); | |
587 | return v; | |
588 | } | |
589 | ||
4ff55bcb RH |
590 | /* Clear the bits above an N-bit vector, for N = (is_q ? 128 : 64). |
591 | * If SVE is not enabled, then there are only 128 bits in the vector. | |
592 | */ | |
593 | static void clear_vec_high(DisasContext *s, bool is_q, int rd) | |
594 | { | |
595 | unsigned ofs = fp_reg_offset(s, rd, MO_64); | |
596 | unsigned vsz = vec_full_reg_size(s); | |
597 | ||
5c27392d RH |
598 | /* Nop move, with side effect of clearing the tail. */ |
599 | tcg_gen_gvec_mov(MO_64, ofs, ofs, is_q ? 16 : 8, vsz); | |
4ff55bcb RH |
600 | } |
601 | ||
8c71baed | 602 | void write_fp_dreg(DisasContext *s, int reg, TCGv_i64 v) |
ec73d2e0 | 603 | { |
4ff55bcb | 604 | unsigned ofs = fp_reg_offset(s, reg, MO_64); |
ec73d2e0 | 605 | |
4ff55bcb RH |
606 | tcg_gen_st_i64(v, cpu_env, ofs); |
607 | clear_vec_high(s, false, reg); | |
ec73d2e0 AG |
608 | } |
609 | ||
610 | static void write_fp_sreg(DisasContext *s, int reg, TCGv_i32 v) | |
611 | { | |
612 | TCGv_i64 tmp = tcg_temp_new_i64(); | |
613 | ||
614 | tcg_gen_extu_i32_i64(tmp, v); | |
615 | write_fp_dreg(s, reg, tmp); | |
616 | tcg_temp_free_i64(tmp); | |
617 | } | |
618 | ||
377ef731 RH |
619 | /* Expand a 2-operand AdvSIMD vector operation using an expander function. */ |
620 | static void gen_gvec_fn2(DisasContext *s, bool is_q, int rd, int rn, | |
621 | GVecGen2Fn *gvec_fn, int vece) | |
622 | { | |
623 | gvec_fn(vece, vec_full_reg_offset(s, rd), vec_full_reg_offset(s, rn), | |
624 | is_q ? 16 : 8, vec_full_reg_size(s)); | |
625 | } | |
626 | ||
cdb45a60 RH |
627 | /* Expand a 2-operand + immediate AdvSIMD vector operation using |
628 | * an expander function. | |
629 | */ | |
630 | static void gen_gvec_fn2i(DisasContext *s, bool is_q, int rd, int rn, | |
631 | int64_t imm, GVecGen2iFn *gvec_fn, int vece) | |
632 | { | |
633 | gvec_fn(vece, vec_full_reg_offset(s, rd), vec_full_reg_offset(s, rn), | |
634 | imm, is_q ? 16 : 8, vec_full_reg_size(s)); | |
635 | } | |
636 | ||
bc48092f RH |
637 | /* Expand a 3-operand AdvSIMD vector operation using an expander function. */ |
638 | static void gen_gvec_fn3(DisasContext *s, bool is_q, int rd, int rn, int rm, | |
639 | GVecGen3Fn *gvec_fn, int vece) | |
640 | { | |
641 | gvec_fn(vece, vec_full_reg_offset(s, rd), vec_full_reg_offset(s, rn), | |
642 | vec_full_reg_offset(s, rm), is_q ? 16 : 8, vec_full_reg_size(s)); | |
643 | } | |
644 | ||
3a7a2b4e RH |
645 | /* Expand a 4-operand AdvSIMD vector operation using an expander function. */ |
646 | static void gen_gvec_fn4(DisasContext *s, bool is_q, int rd, int rn, int rm, | |
647 | int rx, GVecGen4Fn *gvec_fn, int vece) | |
648 | { | |
649 | gvec_fn(vece, vec_full_reg_offset(s, rd), vec_full_reg_offset(s, rn), | |
650 | vec_full_reg_offset(s, rm), vec_full_reg_offset(s, rx), | |
651 | is_q ? 16 : 8, vec_full_reg_size(s)); | |
652 | } | |
653 | ||
a04b68e1 RH |
654 | /* Expand a 2-operand operation using an out-of-line helper. */ |
655 | static void gen_gvec_op2_ool(DisasContext *s, bool is_q, int rd, | |
656 | int rn, int data, gen_helper_gvec_2 *fn) | |
657 | { | |
658 | tcg_gen_gvec_2_ool(vec_full_reg_offset(s, rd), | |
659 | vec_full_reg_offset(s, rn), | |
660 | is_q ? 16 : 8, vec_full_reg_size(s), data, fn); | |
661 | } | |
662 | ||
26c470a7 RH |
663 | /* Expand a 3-operand operation using an out-of-line helper. */ |
664 | static void gen_gvec_op3_ool(DisasContext *s, bool is_q, int rd, | |
665 | int rn, int rm, int data, gen_helper_gvec_3 *fn) | |
666 | { | |
667 | tcg_gen_gvec_3_ool(vec_full_reg_offset(s, rd), | |
668 | vec_full_reg_offset(s, rn), | |
669 | vec_full_reg_offset(s, rm), | |
670 | is_q ? 16 : 8, vec_full_reg_size(s), data, fn); | |
671 | } | |
672 | ||
1695cd61 RH |
673 | /* Expand a 3-operand + fpstatus pointer + simd data value operation using |
674 | * an out-of-line helper. | |
675 | */ | |
676 | static void gen_gvec_op3_fpst(DisasContext *s, bool is_q, int rd, int rn, | |
677 | int rm, bool is_fp16, int data, | |
678 | gen_helper_gvec_3_ptr *fn) | |
679 | { | |
cdfb22bb | 680 | TCGv_ptr fpst = fpstatus_ptr(is_fp16 ? FPST_FPCR_F16 : FPST_FPCR); |
1695cd61 RH |
681 | tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd), |
682 | vec_full_reg_offset(s, rn), | |
683 | vec_full_reg_offset(s, rm), fpst, | |
684 | is_q ? 16 : 8, vec_full_reg_size(s), data, fn); | |
685 | tcg_temp_free_ptr(fpst); | |
686 | } | |
687 | ||
ed78849d RH |
688 | /* Expand a 3-operand + qc + operation using an out-of-line helper. */ |
689 | static void gen_gvec_op3_qc(DisasContext *s, bool is_q, int rd, int rn, | |
690 | int rm, gen_helper_gvec_3_ptr *fn) | |
691 | { | |
692 | TCGv_ptr qc_ptr = tcg_temp_new_ptr(); | |
693 | ||
694 | tcg_gen_addi_ptr(qc_ptr, cpu_env, offsetof(CPUARMState, vfp.qc)); | |
695 | tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd), | |
696 | vec_full_reg_offset(s, rn), | |
697 | vec_full_reg_offset(s, rm), qc_ptr, | |
698 | is_q ? 16 : 8, vec_full_reg_size(s), 0, fn); | |
699 | tcg_temp_free_ptr(qc_ptr); | |
700 | } | |
701 | ||
832ffa1c AG |
702 | /* Set ZF and NF based on a 64 bit result. This is alas fiddlier |
703 | * than the 32 bit equivalent. | |
704 | */ | |
705 | static inline void gen_set_NZ64(TCGv_i64 result) | |
706 | { | |
7cb36e18 RH |
707 | tcg_gen_extr_i64_i32(cpu_ZF, cpu_NF, result); |
708 | tcg_gen_or_i32(cpu_ZF, cpu_ZF, cpu_NF); | |
832ffa1c AG |
709 | } |
710 | ||
711 | /* Set NZCV as for a logical operation: NZ as per result, CV cleared. */ | |
712 | static inline void gen_logic_CC(int sf, TCGv_i64 result) | |
713 | { | |
714 | if (sf) { | |
715 | gen_set_NZ64(result); | |
716 | } else { | |
ecc7b3aa | 717 | tcg_gen_extrl_i64_i32(cpu_ZF, result); |
7cb36e18 | 718 | tcg_gen_mov_i32(cpu_NF, cpu_ZF); |
832ffa1c AG |
719 | } |
720 | tcg_gen_movi_i32(cpu_CF, 0); | |
721 | tcg_gen_movi_i32(cpu_VF, 0); | |
722 | } | |
723 | ||
b0ff21b4 AB |
724 | /* dest = T0 + T1; compute C, N, V and Z flags */ |
725 | static void gen_add_CC(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1) | |
726 | { | |
727 | if (sf) { | |
728 | TCGv_i64 result, flag, tmp; | |
729 | result = tcg_temp_new_i64(); | |
730 | flag = tcg_temp_new_i64(); | |
731 | tmp = tcg_temp_new_i64(); | |
732 | ||
733 | tcg_gen_movi_i64(tmp, 0); | |
734 | tcg_gen_add2_i64(result, flag, t0, tmp, t1, tmp); | |
735 | ||
ecc7b3aa | 736 | tcg_gen_extrl_i64_i32(cpu_CF, flag); |
b0ff21b4 AB |
737 | |
738 | gen_set_NZ64(result); | |
739 | ||
740 | tcg_gen_xor_i64(flag, result, t0); | |
741 | tcg_gen_xor_i64(tmp, t0, t1); | |
742 | tcg_gen_andc_i64(flag, flag, tmp); | |
743 | tcg_temp_free_i64(tmp); | |
7cb36e18 | 744 | tcg_gen_extrh_i64_i32(cpu_VF, flag); |
b0ff21b4 AB |
745 | |
746 | tcg_gen_mov_i64(dest, result); | |
747 | tcg_temp_free_i64(result); | |
748 | tcg_temp_free_i64(flag); | |
749 | } else { | |
750 | /* 32 bit arithmetic */ | |
751 | TCGv_i32 t0_32 = tcg_temp_new_i32(); | |
752 | TCGv_i32 t1_32 = tcg_temp_new_i32(); | |
753 | TCGv_i32 tmp = tcg_temp_new_i32(); | |
754 | ||
755 | tcg_gen_movi_i32(tmp, 0); | |
ecc7b3aa RH |
756 | tcg_gen_extrl_i64_i32(t0_32, t0); |
757 | tcg_gen_extrl_i64_i32(t1_32, t1); | |
b0ff21b4 AB |
758 | tcg_gen_add2_i32(cpu_NF, cpu_CF, t0_32, tmp, t1_32, tmp); |
759 | tcg_gen_mov_i32(cpu_ZF, cpu_NF); | |
760 | tcg_gen_xor_i32(cpu_VF, cpu_NF, t0_32); | |
761 | tcg_gen_xor_i32(tmp, t0_32, t1_32); | |
762 | tcg_gen_andc_i32(cpu_VF, cpu_VF, tmp); | |
763 | tcg_gen_extu_i32_i64(dest, cpu_NF); | |
764 | ||
765 | tcg_temp_free_i32(tmp); | |
766 | tcg_temp_free_i32(t0_32); | |
767 | tcg_temp_free_i32(t1_32); | |
768 | } | |
769 | } | |
770 | ||
771 | /* dest = T0 - T1; compute C, N, V and Z flags */ | |
772 | static void gen_sub_CC(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1) | |
773 | { | |
774 | if (sf) { | |
775 | /* 64 bit arithmetic */ | |
776 | TCGv_i64 result, flag, tmp; | |
777 | ||
778 | result = tcg_temp_new_i64(); | |
779 | flag = tcg_temp_new_i64(); | |
780 | tcg_gen_sub_i64(result, t0, t1); | |
781 | ||
782 | gen_set_NZ64(result); | |
783 | ||
784 | tcg_gen_setcond_i64(TCG_COND_GEU, flag, t0, t1); | |
ecc7b3aa | 785 | tcg_gen_extrl_i64_i32(cpu_CF, flag); |
b0ff21b4 AB |
786 | |
787 | tcg_gen_xor_i64(flag, result, t0); | |
788 | tmp = tcg_temp_new_i64(); | |
789 | tcg_gen_xor_i64(tmp, t0, t1); | |
790 | tcg_gen_and_i64(flag, flag, tmp); | |
791 | tcg_temp_free_i64(tmp); | |
7cb36e18 | 792 | tcg_gen_extrh_i64_i32(cpu_VF, flag); |
b0ff21b4 AB |
793 | tcg_gen_mov_i64(dest, result); |
794 | tcg_temp_free_i64(flag); | |
795 | tcg_temp_free_i64(result); | |
796 | } else { | |
797 | /* 32 bit arithmetic */ | |
798 | TCGv_i32 t0_32 = tcg_temp_new_i32(); | |
799 | TCGv_i32 t1_32 = tcg_temp_new_i32(); | |
800 | TCGv_i32 tmp; | |
801 | ||
ecc7b3aa RH |
802 | tcg_gen_extrl_i64_i32(t0_32, t0); |
803 | tcg_gen_extrl_i64_i32(t1_32, t1); | |
b0ff21b4 AB |
804 | tcg_gen_sub_i32(cpu_NF, t0_32, t1_32); |
805 | tcg_gen_mov_i32(cpu_ZF, cpu_NF); | |
806 | tcg_gen_setcond_i32(TCG_COND_GEU, cpu_CF, t0_32, t1_32); | |
807 | tcg_gen_xor_i32(cpu_VF, cpu_NF, t0_32); | |
808 | tmp = tcg_temp_new_i32(); | |
809 | tcg_gen_xor_i32(tmp, t0_32, t1_32); | |
810 | tcg_temp_free_i32(t0_32); | |
811 | tcg_temp_free_i32(t1_32); | |
812 | tcg_gen_and_i32(cpu_VF, cpu_VF, tmp); | |
813 | tcg_temp_free_i32(tmp); | |
814 | tcg_gen_extu_i32_i64(dest, cpu_NF); | |
815 | } | |
816 | } | |
817 | ||
643dbb07 CF |
818 | /* dest = T0 + T1 + CF; do not compute flags. */ |
819 | static void gen_adc(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1) | |
820 | { | |
821 | TCGv_i64 flag = tcg_temp_new_i64(); | |
822 | tcg_gen_extu_i32_i64(flag, cpu_CF); | |
823 | tcg_gen_add_i64(dest, t0, t1); | |
824 | tcg_gen_add_i64(dest, dest, flag); | |
825 | tcg_temp_free_i64(flag); | |
826 | ||
827 | if (!sf) { | |
828 | tcg_gen_ext32u_i64(dest, dest); | |
829 | } | |
830 | } | |
831 | ||
832 | /* dest = T0 + T1 + CF; compute C, N, V and Z flags. */ | |
833 | static void gen_adc_CC(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1) | |
834 | { | |
835 | if (sf) { | |
836 | TCGv_i64 result, cf_64, vf_64, tmp; | |
837 | result = tcg_temp_new_i64(); | |
838 | cf_64 = tcg_temp_new_i64(); | |
839 | vf_64 = tcg_temp_new_i64(); | |
840 | tmp = tcg_const_i64(0); | |
841 | ||
842 | tcg_gen_extu_i32_i64(cf_64, cpu_CF); | |
843 | tcg_gen_add2_i64(result, cf_64, t0, tmp, cf_64, tmp); | |
844 | tcg_gen_add2_i64(result, cf_64, result, cf_64, t1, tmp); | |
ecc7b3aa | 845 | tcg_gen_extrl_i64_i32(cpu_CF, cf_64); |
643dbb07 CF |
846 | gen_set_NZ64(result); |
847 | ||
848 | tcg_gen_xor_i64(vf_64, result, t0); | |
849 | tcg_gen_xor_i64(tmp, t0, t1); | |
850 | tcg_gen_andc_i64(vf_64, vf_64, tmp); | |
7cb36e18 | 851 | tcg_gen_extrh_i64_i32(cpu_VF, vf_64); |
643dbb07 CF |
852 | |
853 | tcg_gen_mov_i64(dest, result); | |
854 | ||
855 | tcg_temp_free_i64(tmp); | |
856 | tcg_temp_free_i64(vf_64); | |
857 | tcg_temp_free_i64(cf_64); | |
858 | tcg_temp_free_i64(result); | |
859 | } else { | |
860 | TCGv_i32 t0_32, t1_32, tmp; | |
861 | t0_32 = tcg_temp_new_i32(); | |
862 | t1_32 = tcg_temp_new_i32(); | |
863 | tmp = tcg_const_i32(0); | |
864 | ||
ecc7b3aa RH |
865 | tcg_gen_extrl_i64_i32(t0_32, t0); |
866 | tcg_gen_extrl_i64_i32(t1_32, t1); | |
643dbb07 CF |
867 | tcg_gen_add2_i32(cpu_NF, cpu_CF, t0_32, tmp, cpu_CF, tmp); |
868 | tcg_gen_add2_i32(cpu_NF, cpu_CF, cpu_NF, cpu_CF, t1_32, tmp); | |
869 | ||
870 | tcg_gen_mov_i32(cpu_ZF, cpu_NF); | |
871 | tcg_gen_xor_i32(cpu_VF, cpu_NF, t0_32); | |
872 | tcg_gen_xor_i32(tmp, t0_32, t1_32); | |
873 | tcg_gen_andc_i32(cpu_VF, cpu_VF, tmp); | |
874 | tcg_gen_extu_i32_i64(dest, cpu_NF); | |
875 | ||
876 | tcg_temp_free_i32(tmp); | |
877 | tcg_temp_free_i32(t1_32); | |
878 | tcg_temp_free_i32(t0_32); | |
879 | } | |
880 | } | |
881 | ||
4a08d475 PM |
882 | /* |
883 | * Load/Store generators | |
884 | */ | |
885 | ||
886 | /* | |
60510aed | 887 | * Store from GPR register to memory. |
4a08d475 | 888 | */ |
60510aed | 889 | static void do_gpr_st_memidx(DisasContext *s, TCGv_i64 source, |
aaa1f954 EI |
890 | TCGv_i64 tcg_addr, int size, int memidx, |
891 | bool iss_valid, | |
892 | unsigned int iss_srt, | |
893 | bool iss_sf, bool iss_ar) | |
60510aed PM |
894 | { |
895 | g_assert(size <= 3); | |
aa6489da | 896 | tcg_gen_qemu_st_i64(source, tcg_addr, memidx, s->be_data + size); |
aaa1f954 EI |
897 | |
898 | if (iss_valid) { | |
899 | uint32_t syn; | |
900 | ||
901 | syn = syn_data_abort_with_iss(0, | |
902 | size, | |
903 | false, | |
904 | iss_srt, | |
905 | iss_sf, | |
906 | iss_ar, | |
907 | 0, 0, 0, 0, 0, false); | |
908 | disas_set_insn_syndrome(s, syn); | |
909 | } | |
60510aed PM |
910 | } |
911 | ||
4a08d475 | 912 | static void do_gpr_st(DisasContext *s, TCGv_i64 source, |
aaa1f954 EI |
913 | TCGv_i64 tcg_addr, int size, |
914 | bool iss_valid, | |
915 | unsigned int iss_srt, | |
916 | bool iss_sf, bool iss_ar) | |
4a08d475 | 917 | { |
aaa1f954 EI |
918 | do_gpr_st_memidx(s, source, tcg_addr, size, get_mem_index(s), |
919 | iss_valid, iss_srt, iss_sf, iss_ar); | |
4a08d475 PM |
920 | } |
921 | ||
922 | /* | |
923 | * Load from memory to GPR register | |
924 | */ | |
aaa1f954 EI |
925 | static void do_gpr_ld_memidx(DisasContext *s, |
926 | TCGv_i64 dest, TCGv_i64 tcg_addr, | |
927 | int size, bool is_signed, | |
928 | bool extend, int memidx, | |
929 | bool iss_valid, unsigned int iss_srt, | |
930 | bool iss_sf, bool iss_ar) | |
4a08d475 | 931 | { |
14776ab5 | 932 | MemOp memop = s->be_data + size; |
4a08d475 PM |
933 | |
934 | g_assert(size <= 3); | |
935 | ||
936 | if (is_signed) { | |
937 | memop += MO_SIGN; | |
938 | } | |
939 | ||
60510aed | 940 | tcg_gen_qemu_ld_i64(dest, tcg_addr, memidx, memop); |
4a08d475 PM |
941 | |
942 | if (extend && is_signed) { | |
943 | g_assert(size < 3); | |
944 | tcg_gen_ext32u_i64(dest, dest); | |
945 | } | |
aaa1f954 EI |
946 | |
947 | if (iss_valid) { | |
948 | uint32_t syn; | |
949 | ||
950 | syn = syn_data_abort_with_iss(0, | |
951 | size, | |
952 | is_signed, | |
953 | iss_srt, | |
954 | iss_sf, | |
955 | iss_ar, | |
956 | 0, 0, 0, 0, 0, false); | |
957 | disas_set_insn_syndrome(s, syn); | |
958 | } | |
4a08d475 PM |
959 | } |
960 | ||
aaa1f954 EI |
961 | static void do_gpr_ld(DisasContext *s, |
962 | TCGv_i64 dest, TCGv_i64 tcg_addr, | |
963 | int size, bool is_signed, bool extend, | |
964 | bool iss_valid, unsigned int iss_srt, | |
965 | bool iss_sf, bool iss_ar) | |
60510aed PM |
966 | { |
967 | do_gpr_ld_memidx(s, dest, tcg_addr, size, is_signed, extend, | |
aaa1f954 EI |
968 | get_mem_index(s), |
969 | iss_valid, iss_srt, iss_sf, iss_ar); | |
60510aed PM |
970 | } |
971 | ||
4a08d475 PM |
972 | /* |
973 | * Store from FP register to memory | |
974 | */ | |
975 | static void do_fp_st(DisasContext *s, int srcidx, TCGv_i64 tcg_addr, int size) | |
976 | { | |
977 | /* This writes the bottom N bits of a 128 bit wide vector to memory */ | |
4a08d475 | 978 | TCGv_i64 tmp = tcg_temp_new_i64(); |
90e49638 | 979 | tcg_gen_ld_i64(tmp, cpu_env, fp_reg_offset(s, srcidx, MO_64)); |
4a08d475 | 980 | if (size < 4) { |
aa6489da PC |
981 | tcg_gen_qemu_st_i64(tmp, tcg_addr, get_mem_index(s), |
982 | s->be_data + size); | |
4a08d475 | 983 | } else { |
aa6489da | 984 | bool be = s->be_data == MO_BE; |
4a08d475 | 985 | TCGv_i64 tcg_hiaddr = tcg_temp_new_i64(); |
aa6489da | 986 | |
4a08d475 | 987 | tcg_gen_addi_i64(tcg_hiaddr, tcg_addr, 8); |
aa6489da PC |
988 | tcg_gen_qemu_st_i64(tmp, be ? tcg_hiaddr : tcg_addr, get_mem_index(s), |
989 | s->be_data | MO_Q); | |
990 | tcg_gen_ld_i64(tmp, cpu_env, fp_reg_hi_offset(s, srcidx)); | |
991 | tcg_gen_qemu_st_i64(tmp, be ? tcg_addr : tcg_hiaddr, get_mem_index(s), | |
992 | s->be_data | MO_Q); | |
4a08d475 PM |
993 | tcg_temp_free_i64(tcg_hiaddr); |
994 | } | |
995 | ||
996 | tcg_temp_free_i64(tmp); | |
997 | } | |
998 | ||
999 | /* | |
1000 | * Load from memory to FP register | |
1001 | */ | |
1002 | static void do_fp_ld(DisasContext *s, int destidx, TCGv_i64 tcg_addr, int size) | |
1003 | { | |
1004 | /* This always zero-extends and writes to a full 128 bit wide vector */ | |
4a08d475 | 1005 | TCGv_i64 tmplo = tcg_temp_new_i64(); |
e1f77859 | 1006 | TCGv_i64 tmphi = NULL; |
4a08d475 PM |
1007 | |
1008 | if (size < 4) { | |
14776ab5 | 1009 | MemOp memop = s->be_data + size; |
4a08d475 PM |
1010 | tcg_gen_qemu_ld_i64(tmplo, tcg_addr, get_mem_index(s), memop); |
1011 | } else { | |
aa6489da | 1012 | bool be = s->be_data == MO_BE; |
4a08d475 | 1013 | TCGv_i64 tcg_hiaddr; |
aa6489da | 1014 | |
4a08d475 PM |
1015 | tmphi = tcg_temp_new_i64(); |
1016 | tcg_hiaddr = tcg_temp_new_i64(); | |
1017 | ||
4a08d475 | 1018 | tcg_gen_addi_i64(tcg_hiaddr, tcg_addr, 8); |
aa6489da PC |
1019 | tcg_gen_qemu_ld_i64(tmplo, be ? tcg_hiaddr : tcg_addr, get_mem_index(s), |
1020 | s->be_data | MO_Q); | |
1021 | tcg_gen_qemu_ld_i64(tmphi, be ? tcg_addr : tcg_hiaddr, get_mem_index(s), | |
1022 | s->be_data | MO_Q); | |
4a08d475 PM |
1023 | tcg_temp_free_i64(tcg_hiaddr); |
1024 | } | |
1025 | ||
90e49638 | 1026 | tcg_gen_st_i64(tmplo, cpu_env, fp_reg_offset(s, destidx, MO_64)); |
4a08d475 | 1027 | tcg_temp_free_i64(tmplo); |
4ff55bcb | 1028 | |
e1f77859 RH |
1029 | if (tmphi) { |
1030 | tcg_gen_st_i64(tmphi, cpu_env, fp_reg_hi_offset(s, destidx)); | |
1031 | tcg_temp_free_i64(tmphi); | |
1032 | } | |
1033 | clear_vec_high(s, tmphi != NULL, destidx); | |
4a08d475 PM |
1034 | } |
1035 | ||
72430bf5 AB |
1036 | /* |
1037 | * Vector load/store helpers. | |
1038 | * | |
1039 | * The principal difference between this and a FP load is that we don't | |
1040 | * zero extend as we are filling a partial chunk of the vector register. | |
1041 | * These functions don't support 128 bit loads/stores, which would be | |
1042 | * normal load/store operations. | |
a08582f4 PM |
1043 | * |
1044 | * The _i32 versions are useful when operating on 32 bit quantities | |
1045 | * (eg for floating point single or using Neon helper functions). | |
72430bf5 AB |
1046 | */ |
1047 | ||
1048 | /* Get value of an element within a vector register */ | |
1049 | static void read_vec_element(DisasContext *s, TCGv_i64 tcg_dest, int srcidx, | |
14776ab5 | 1050 | int element, MemOp memop) |
72430bf5 | 1051 | { |
90e49638 | 1052 | int vect_off = vec_reg_offset(s, srcidx, element, memop & MO_SIZE); |
72430bf5 AB |
1053 | switch (memop) { |
1054 | case MO_8: | |
1055 | tcg_gen_ld8u_i64(tcg_dest, cpu_env, vect_off); | |
1056 | break; | |
1057 | case MO_16: | |
1058 | tcg_gen_ld16u_i64(tcg_dest, cpu_env, vect_off); | |
1059 | break; | |
1060 | case MO_32: | |
1061 | tcg_gen_ld32u_i64(tcg_dest, cpu_env, vect_off); | |
1062 | break; | |
1063 | case MO_8|MO_SIGN: | |
1064 | tcg_gen_ld8s_i64(tcg_dest, cpu_env, vect_off); | |
1065 | break; | |
1066 | case MO_16|MO_SIGN: | |
1067 | tcg_gen_ld16s_i64(tcg_dest, cpu_env, vect_off); | |
1068 | break; | |
1069 | case MO_32|MO_SIGN: | |
1070 | tcg_gen_ld32s_i64(tcg_dest, cpu_env, vect_off); | |
1071 | break; | |
1072 | case MO_64: | |
1073 | case MO_64|MO_SIGN: | |
1074 | tcg_gen_ld_i64(tcg_dest, cpu_env, vect_off); | |
1075 | break; | |
1076 | default: | |
1077 | g_assert_not_reached(); | |
1078 | } | |
1079 | } | |
1080 | ||
a08582f4 | 1081 | static void read_vec_element_i32(DisasContext *s, TCGv_i32 tcg_dest, int srcidx, |
14776ab5 | 1082 | int element, MemOp memop) |
a08582f4 | 1083 | { |
90e49638 | 1084 | int vect_off = vec_reg_offset(s, srcidx, element, memop & MO_SIZE); |
a08582f4 PM |
1085 | switch (memop) { |
1086 | case MO_8: | |
1087 | tcg_gen_ld8u_i32(tcg_dest, cpu_env, vect_off); | |
1088 | break; | |
1089 | case MO_16: | |
1090 | tcg_gen_ld16u_i32(tcg_dest, cpu_env, vect_off); | |
1091 | break; | |
1092 | case MO_8|MO_SIGN: | |
1093 | tcg_gen_ld8s_i32(tcg_dest, cpu_env, vect_off); | |
1094 | break; | |
1095 | case MO_16|MO_SIGN: | |
1096 | tcg_gen_ld16s_i32(tcg_dest, cpu_env, vect_off); | |
1097 | break; | |
1098 | case MO_32: | |
1099 | case MO_32|MO_SIGN: | |
1100 | tcg_gen_ld_i32(tcg_dest, cpu_env, vect_off); | |
1101 | break; | |
1102 | default: | |
1103 | g_assert_not_reached(); | |
1104 | } | |
1105 | } | |
1106 | ||
72430bf5 AB |
1107 | /* Set value of an element within a vector register */ |
1108 | static void write_vec_element(DisasContext *s, TCGv_i64 tcg_src, int destidx, | |
14776ab5 | 1109 | int element, MemOp memop) |
72430bf5 | 1110 | { |
90e49638 | 1111 | int vect_off = vec_reg_offset(s, destidx, element, memop & MO_SIZE); |
72430bf5 AB |
1112 | switch (memop) { |
1113 | case MO_8: | |
1114 | tcg_gen_st8_i64(tcg_src, cpu_env, vect_off); | |
1115 | break; | |
1116 | case MO_16: | |
1117 | tcg_gen_st16_i64(tcg_src, cpu_env, vect_off); | |
1118 | break; | |
1119 | case MO_32: | |
1120 | tcg_gen_st32_i64(tcg_src, cpu_env, vect_off); | |
1121 | break; | |
1122 | case MO_64: | |
1123 | tcg_gen_st_i64(tcg_src, cpu_env, vect_off); | |
1124 | break; | |
1125 | default: | |
1126 | g_assert_not_reached(); | |
1127 | } | |
1128 | } | |
1129 | ||
1f8a73af | 1130 | static void write_vec_element_i32(DisasContext *s, TCGv_i32 tcg_src, |
14776ab5 | 1131 | int destidx, int element, MemOp memop) |
1f8a73af | 1132 | { |
90e49638 | 1133 | int vect_off = vec_reg_offset(s, destidx, element, memop & MO_SIZE); |
1f8a73af PM |
1134 | switch (memop) { |
1135 | case MO_8: | |
1136 | tcg_gen_st8_i32(tcg_src, cpu_env, vect_off); | |
1137 | break; | |
1138 | case MO_16: | |
1139 | tcg_gen_st16_i32(tcg_src, cpu_env, vect_off); | |
1140 | break; | |
1141 | case MO_32: | |
1142 | tcg_gen_st_i32(tcg_src, cpu_env, vect_off); | |
1143 | break; | |
1144 | default: | |
1145 | g_assert_not_reached(); | |
1146 | } | |
1147 | } | |
1148 | ||
72430bf5 AB |
1149 | /* Store from vector register to memory */ |
1150 | static void do_vec_st(DisasContext *s, int srcidx, int element, | |
14776ab5 | 1151 | TCGv_i64 tcg_addr, int size, MemOp endian) |
72430bf5 | 1152 | { |
72430bf5 AB |
1153 | TCGv_i64 tcg_tmp = tcg_temp_new_i64(); |
1154 | ||
1155 | read_vec_element(s, tcg_tmp, srcidx, element, size); | |
87f9a7f0 | 1156 | tcg_gen_qemu_st_i64(tcg_tmp, tcg_addr, get_mem_index(s), endian | size); |
72430bf5 AB |
1157 | |
1158 | tcg_temp_free_i64(tcg_tmp); | |
1159 | } | |
1160 | ||
1161 | /* Load from memory to vector register */ | |
1162 | static void do_vec_ld(DisasContext *s, int destidx, int element, | |
14776ab5 | 1163 | TCGv_i64 tcg_addr, int size, MemOp endian) |
72430bf5 | 1164 | { |
72430bf5 AB |
1165 | TCGv_i64 tcg_tmp = tcg_temp_new_i64(); |
1166 | ||
87f9a7f0 | 1167 | tcg_gen_qemu_ld_i64(tcg_tmp, tcg_addr, get_mem_index(s), endian | size); |
72430bf5 AB |
1168 | write_vec_element(s, tcg_tmp, destidx, element, size); |
1169 | ||
1170 | tcg_temp_free_i64(tcg_tmp); | |
1171 | } | |
1172 | ||
8c6afa6a PM |
1173 | /* Check that FP/Neon access is enabled. If it is, return |
1174 | * true. If not, emit code to generate an appropriate exception, | |
1175 | * and return false; the caller should not emit any code for | |
1176 | * the instruction. Note that this check must happen after all | |
1177 | * unallocated-encoding checks (otherwise the syndrome information | |
1178 | * for the resulting exception will be incorrect). | |
1179 | */ | |
8a40fe5f | 1180 | static bool fp_access_check(DisasContext *s) |
8c6afa6a | 1181 | { |
8a40fe5f RH |
1182 | if (s->fp_excp_el) { |
1183 | assert(!s->fp_access_checked); | |
1184 | s->fp_access_checked = true; | |
90e49638 | 1185 | |
8a40fe5f RH |
1186 | gen_exception_insn(s, s->pc_curr, EXCP_UDEF, |
1187 | syn_fp_access_trap(1, 0xe, false), s->fp_excp_el); | |
1188 | return false; | |
8c6afa6a | 1189 | } |
8a40fe5f RH |
1190 | s->fp_access_checked = true; |
1191 | return true; | |
8c6afa6a PM |
1192 | } |
1193 | ||
490aa7f1 RH |
1194 | /* Check that SVE access is enabled. If it is, return true. |
1195 | * If not, emit code to generate an appropriate exception and return false. | |
1196 | */ | |
8c71baed | 1197 | bool sve_access_check(DisasContext *s) |
490aa7f1 RH |
1198 | { |
1199 | if (s->sve_excp_el) { | |
8a40fe5f RH |
1200 | assert(!s->sve_access_checked); |
1201 | s->sve_access_checked = true; | |
1202 | ||
1203 | gen_exception_insn(s, s->pc_curr, EXCP_UDEF, | |
1204 | syn_sve_access_trap(), s->sve_excp_el); | |
490aa7f1 RH |
1205 | return false; |
1206 | } | |
8a40fe5f | 1207 | s->sve_access_checked = true; |
8c71baed | 1208 | return fp_access_check(s); |
490aa7f1 RH |
1209 | } |
1210 | ||
229b7a05 AB |
1211 | /* |
1212 | * This utility function is for doing register extension with an | |
1213 | * optional shift. You will likely want to pass a temporary for the | |
1214 | * destination register. See DecodeRegExtend() in the ARM ARM. | |
1215 | */ | |
1216 | static void ext_and_shift_reg(TCGv_i64 tcg_out, TCGv_i64 tcg_in, | |
1217 | int option, unsigned int shift) | |
1218 | { | |
1219 | int extsize = extract32(option, 0, 2); | |
1220 | bool is_signed = extract32(option, 2, 1); | |
1221 | ||
1222 | if (is_signed) { | |
1223 | switch (extsize) { | |
1224 | case 0: | |
1225 | tcg_gen_ext8s_i64(tcg_out, tcg_in); | |
1226 | break; | |
1227 | case 1: | |
1228 | tcg_gen_ext16s_i64(tcg_out, tcg_in); | |
1229 | break; | |
1230 | case 2: | |
1231 | tcg_gen_ext32s_i64(tcg_out, tcg_in); | |
1232 | break; | |
1233 | case 3: | |
1234 | tcg_gen_mov_i64(tcg_out, tcg_in); | |
1235 | break; | |
1236 | } | |
1237 | } else { | |
1238 | switch (extsize) { | |
1239 | case 0: | |
1240 | tcg_gen_ext8u_i64(tcg_out, tcg_in); | |
1241 | break; | |
1242 | case 1: | |
1243 | tcg_gen_ext16u_i64(tcg_out, tcg_in); | |
1244 | break; | |
1245 | case 2: | |
1246 | tcg_gen_ext32u_i64(tcg_out, tcg_in); | |
1247 | break; | |
1248 | case 3: | |
1249 | tcg_gen_mov_i64(tcg_out, tcg_in); | |
1250 | break; | |
1251 | } | |
1252 | } | |
1253 | ||
1254 | if (shift) { | |
1255 | tcg_gen_shli_i64(tcg_out, tcg_out, shift); | |
1256 | } | |
1257 | } | |
1258 | ||
4a08d475 PM |
1259 | static inline void gen_check_sp_alignment(DisasContext *s) |
1260 | { | |
1261 | /* The AArch64 architecture mandates that (if enabled via PSTATE | |
1262 | * or SCTLR bits) there is a check that SP is 16-aligned on every | |
1263 | * SP-relative load or store (with an exception generated if it is not). | |
1264 | * In line with general QEMU practice regarding misaligned accesses, | |
1265 | * we omit these checks for the sake of guest program performance. | |
1266 | * This function is provided as a hook so we can more easily add these | |
1267 | * checks in future (possibly as a "favour catching guest program bugs | |
1268 | * over speed" user selectable option). | |
1269 | */ | |
1270 | } | |
1271 | ||
384b26fb AB |
1272 | /* |
1273 | * This provides a simple table based table lookup decoder. It is | |
1274 | * intended to be used when the relevant bits for decode are too | |
1275 | * awkwardly placed and switch/if based logic would be confusing and | |
1276 | * deeply nested. Since it's a linear search through the table, tables | |
1277 | * should be kept small. | |
1278 | * | |
1279 | * It returns the first handler where insn & mask == pattern, or | |
1280 | * NULL if there is no match. | |
1281 | * The table is terminated by an empty mask (i.e. 0) | |
1282 | */ | |
1283 | static inline AArch64DecodeFn *lookup_disas_fn(const AArch64DecodeTable *table, | |
1284 | uint32_t insn) | |
1285 | { | |
1286 | const AArch64DecodeTable *tptr = table; | |
1287 | ||
1288 | while (tptr->mask) { | |
1289 | if ((insn & tptr->mask) == tptr->pattern) { | |
1290 | return tptr->disas_fn; | |
1291 | } | |
1292 | tptr++; | |
1293 | } | |
1294 | return NULL; | |
1295 | } | |
1296 | ||
ad7ee8a2 | 1297 | /* |
4ce31af4 PM |
1298 | * The instruction disassembly implemented here matches |
1299 | * the instruction encoding classifications in chapter C4 | |
1300 | * of the ARM Architecture Reference Manual (DDI0487B_a); | |
1301 | * classification names and decode diagrams here should generally | |
1302 | * match up with those in the manual. | |
ad7ee8a2 CF |
1303 | */ |
1304 | ||
4ce31af4 | 1305 | /* Unconditional branch (immediate) |
11e169de AG |
1306 | * 31 30 26 25 0 |
1307 | * +----+-----------+-------------------------------------+ | |
1308 | * | op | 0 0 1 0 1 | imm26 | | |
1309 | * +----+-----------+-------------------------------------+ | |
1310 | */ | |
ad7ee8a2 CF |
1311 | static void disas_uncond_b_imm(DisasContext *s, uint32_t insn) |
1312 | { | |
43722a6d | 1313 | uint64_t addr = s->pc_curr + sextract32(insn, 0, 26) * 4; |
11e169de | 1314 | |
1743d55c | 1315 | if (insn & (1U << 31)) { |
4ce31af4 | 1316 | /* BL Branch with link */ |
a0415916 | 1317 | tcg_gen_movi_i64(cpu_reg(s, 30), s->base.pc_next); |
11e169de AG |
1318 | } |
1319 | ||
4ce31af4 | 1320 | /* B Branch / BL Branch with link */ |
35862270 | 1321 | reset_btype(s); |
11e169de | 1322 | gen_goto_tb(s, 0, addr); |
ad7ee8a2 CF |
1323 | } |
1324 | ||
4ce31af4 | 1325 | /* Compare and branch (immediate) |
60e53388 AG |
1326 | * 31 30 25 24 23 5 4 0 |
1327 | * +----+-------------+----+---------------------+--------+ | |
1328 | * | sf | 0 1 1 0 1 0 | op | imm19 | Rt | | |
1329 | * +----+-------------+----+---------------------+--------+ | |
1330 | */ | |
ad7ee8a2 CF |
1331 | static void disas_comp_b_imm(DisasContext *s, uint32_t insn) |
1332 | { | |
60e53388 AG |
1333 | unsigned int sf, op, rt; |
1334 | uint64_t addr; | |
42a268c2 | 1335 | TCGLabel *label_match; |
60e53388 AG |
1336 | TCGv_i64 tcg_cmp; |
1337 | ||
1338 | sf = extract32(insn, 31, 1); | |
1339 | op = extract32(insn, 24, 1); /* 0: CBZ; 1: CBNZ */ | |
1340 | rt = extract32(insn, 0, 5); | |
43722a6d | 1341 | addr = s->pc_curr + sextract32(insn, 5, 19) * 4; |
60e53388 AG |
1342 | |
1343 | tcg_cmp = read_cpu_reg(s, rt, sf); | |
1344 | label_match = gen_new_label(); | |
1345 | ||
35862270 | 1346 | reset_btype(s); |
60e53388 AG |
1347 | tcg_gen_brcondi_i64(op ? TCG_COND_NE : TCG_COND_EQ, |
1348 | tcg_cmp, 0, label_match); | |
1349 | ||
a0415916 | 1350 | gen_goto_tb(s, 0, s->base.pc_next); |
60e53388 AG |
1351 | gen_set_label(label_match); |
1352 | gen_goto_tb(s, 1, addr); | |
ad7ee8a2 CF |
1353 | } |
1354 | ||
4ce31af4 | 1355 | /* Test and branch (immediate) |
db0f7958 AG |
1356 | * 31 30 25 24 23 19 18 5 4 0 |
1357 | * +----+-------------+----+-------+-------------+------+ | |
1358 | * | b5 | 0 1 1 0 1 1 | op | b40 | imm14 | Rt | | |
1359 | * +----+-------------+----+-------+-------------+------+ | |
1360 | */ | |
ad7ee8a2 CF |
1361 | static void disas_test_b_imm(DisasContext *s, uint32_t insn) |
1362 | { | |
db0f7958 AG |
1363 | unsigned int bit_pos, op, rt; |
1364 | uint64_t addr; | |
42a268c2 | 1365 | TCGLabel *label_match; |
db0f7958 AG |
1366 | TCGv_i64 tcg_cmp; |
1367 | ||
1368 | bit_pos = (extract32(insn, 31, 1) << 5) | extract32(insn, 19, 5); | |
1369 | op = extract32(insn, 24, 1); /* 0: TBZ; 1: TBNZ */ | |
43722a6d | 1370 | addr = s->pc_curr + sextract32(insn, 5, 14) * 4; |
db0f7958 AG |
1371 | rt = extract32(insn, 0, 5); |
1372 | ||
1373 | tcg_cmp = tcg_temp_new_i64(); | |
1374 | tcg_gen_andi_i64(tcg_cmp, cpu_reg(s, rt), (1ULL << bit_pos)); | |
1375 | label_match = gen_new_label(); | |
35862270 RH |
1376 | |
1377 | reset_btype(s); | |
db0f7958 AG |
1378 | tcg_gen_brcondi_i64(op ? TCG_COND_NE : TCG_COND_EQ, |
1379 | tcg_cmp, 0, label_match); | |
1380 | tcg_temp_free_i64(tcg_cmp); | |
a0415916 | 1381 | gen_goto_tb(s, 0, s->base.pc_next); |
db0f7958 AG |
1382 | gen_set_label(label_match); |
1383 | gen_goto_tb(s, 1, addr); | |
ad7ee8a2 CF |
1384 | } |
1385 | ||
4ce31af4 | 1386 | /* Conditional branch (immediate) |
39fb730a AG |
1387 | * 31 25 24 23 5 4 3 0 |
1388 | * +---------------+----+---------------------+----+------+ | |
1389 | * | 0 1 0 1 0 1 0 | o1 | imm19 | o0 | cond | | |
1390 | * +---------------+----+---------------------+----+------+ | |
1391 | */ | |
ad7ee8a2 CF |
1392 | static void disas_cond_b_imm(DisasContext *s, uint32_t insn) |
1393 | { | |
39fb730a AG |
1394 | unsigned int cond; |
1395 | uint64_t addr; | |
1396 | ||
1397 | if ((insn & (1 << 4)) || (insn & (1 << 24))) { | |
1398 | unallocated_encoding(s); | |
1399 | return; | |
1400 | } | |
43722a6d | 1401 | addr = s->pc_curr + sextract32(insn, 5, 19) * 4; |
39fb730a AG |
1402 | cond = extract32(insn, 0, 4); |
1403 | ||
35862270 | 1404 | reset_btype(s); |
39fb730a AG |
1405 | if (cond < 0x0e) { |
1406 | /* genuinely conditional branches */ | |
42a268c2 | 1407 | TCGLabel *label_match = gen_new_label(); |
39fb730a | 1408 | arm_gen_test_cc(cond, label_match); |
a0415916 | 1409 | gen_goto_tb(s, 0, s->base.pc_next); |
39fb730a AG |
1410 | gen_set_label(label_match); |
1411 | gen_goto_tb(s, 1, addr); | |
1412 | } else { | |
1413 | /* 0xe and 0xf are both "always" conditions */ | |
1414 | gen_goto_tb(s, 0, addr); | |
1415 | } | |
ad7ee8a2 CF |
1416 | } |
1417 | ||
4ce31af4 | 1418 | /* HINT instruction group, including various allocated HINTs */ |
87462e0f CF |
1419 | static void handle_hint(DisasContext *s, uint32_t insn, |
1420 | unsigned int op1, unsigned int op2, unsigned int crm) | |
1421 | { | |
1422 | unsigned int selector = crm << 3 | op2; | |
1423 | ||
1424 | if (op1 != 3) { | |
1425 | unallocated_encoding(s); | |
1426 | return; | |
1427 | } | |
1428 | ||
1429 | switch (selector) { | |
7c94c834 RH |
1430 | case 0b00000: /* NOP */ |
1431 | break; | |
1432 | case 0b00011: /* WFI */ | |
dcba3a8d | 1433 | s->base.is_jmp = DISAS_WFI; |
7c94c834 RH |
1434 | break; |
1435 | case 0b00001: /* YIELD */ | |
2399d4e7 EC |
1436 | /* When running in MTTCG we don't generate jumps to the yield and |
1437 | * WFE helpers as it won't affect the scheduling of other vCPUs. | |
1438 | * If we wanted to more completely model WFE/SEV so we don't busy | |
1439 | * spin unnecessarily we would need to do something more involved. | |
1440 | */ | |
2399d4e7 | 1441 | if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) { |
dcba3a8d | 1442 | s->base.is_jmp = DISAS_YIELD; |
c22edfeb | 1443 | } |
7c94c834 RH |
1444 | break; |
1445 | case 0b00010: /* WFE */ | |
2399d4e7 | 1446 | if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) { |
dcba3a8d | 1447 | s->base.is_jmp = DISAS_WFE; |
c22edfeb | 1448 | } |
7c94c834 RH |
1449 | break; |
1450 | case 0b00100: /* SEV */ | |
1451 | case 0b00101: /* SEVL */ | |
87462e0f | 1452 | /* we treat all as NOP at least for now */ |
7c94c834 RH |
1453 | break; |
1454 | case 0b00111: /* XPACLRI */ | |
1455 | if (s->pauth_active) { | |
1456 | gen_helper_xpaci(cpu_X[30], cpu_env, cpu_X[30]); | |
1457 | } | |
1458 | break; | |
1459 | case 0b01000: /* PACIA1716 */ | |
1460 | if (s->pauth_active) { | |
1461 | gen_helper_pacia(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]); | |
1462 | } | |
1463 | break; | |
1464 | case 0b01010: /* PACIB1716 */ | |
1465 | if (s->pauth_active) { | |
1466 | gen_helper_pacib(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]); | |
1467 | } | |
1468 | break; | |
1469 | case 0b01100: /* AUTIA1716 */ | |
1470 | if (s->pauth_active) { | |
1471 | gen_helper_autia(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]); | |
1472 | } | |
1473 | break; | |
1474 | case 0b01110: /* AUTIB1716 */ | |
1475 | if (s->pauth_active) { | |
1476 | gen_helper_autib(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]); | |
1477 | } | |
1478 | break; | |
1479 | case 0b11000: /* PACIAZ */ | |
1480 | if (s->pauth_active) { | |
1481 | gen_helper_pacia(cpu_X[30], cpu_env, cpu_X[30], | |
1482 | new_tmp_a64_zero(s)); | |
1483 | } | |
1484 | break; | |
1485 | case 0b11001: /* PACIASP */ | |
1486 | if (s->pauth_active) { | |
1487 | gen_helper_pacia(cpu_X[30], cpu_env, cpu_X[30], cpu_X[31]); | |
1488 | } | |
1489 | break; | |
1490 | case 0b11010: /* PACIBZ */ | |
1491 | if (s->pauth_active) { | |
1492 | gen_helper_pacib(cpu_X[30], cpu_env, cpu_X[30], | |
1493 | new_tmp_a64_zero(s)); | |
1494 | } | |
1495 | break; | |
1496 | case 0b11011: /* PACIBSP */ | |
1497 | if (s->pauth_active) { | |
1498 | gen_helper_pacib(cpu_X[30], cpu_env, cpu_X[30], cpu_X[31]); | |
1499 | } | |
1500 | break; | |
1501 | case 0b11100: /* AUTIAZ */ | |
1502 | if (s->pauth_active) { | |
1503 | gen_helper_autia(cpu_X[30], cpu_env, cpu_X[30], | |
1504 | new_tmp_a64_zero(s)); | |
1505 | } | |
1506 | break; | |
1507 | case 0b11101: /* AUTIASP */ | |
1508 | if (s->pauth_active) { | |
1509 | gen_helper_autia(cpu_X[30], cpu_env, cpu_X[30], cpu_X[31]); | |
1510 | } | |
1511 | break; | |
1512 | case 0b11110: /* AUTIBZ */ | |
1513 | if (s->pauth_active) { | |
1514 | gen_helper_autib(cpu_X[30], cpu_env, cpu_X[30], | |
1515 | new_tmp_a64_zero(s)); | |
1516 | } | |
1517 | break; | |
1518 | case 0b11111: /* AUTIBSP */ | |
1519 | if (s->pauth_active) { | |
1520 | gen_helper_autib(cpu_X[30], cpu_env, cpu_X[30], cpu_X[31]); | |
1521 | } | |
1522 | break; | |
87462e0f CF |
1523 | default: |
1524 | /* default specified as NOP equivalent */ | |
7c94c834 | 1525 | break; |
87462e0f CF |
1526 | } |
1527 | } | |
1528 | ||
fa2ef212 MM |
1529 | static void gen_clrex(DisasContext *s, uint32_t insn) |
1530 | { | |
1531 | tcg_gen_movi_i64(cpu_exclusive_addr, -1); | |
1532 | } | |
1533 | ||
87462e0f CF |
1534 | /* CLREX, DSB, DMB, ISB */ |
1535 | static void handle_sync(DisasContext *s, uint32_t insn, | |
1536 | unsigned int op1, unsigned int op2, unsigned int crm) | |
1537 | { | |
ce1bd93f PK |
1538 | TCGBar bar; |
1539 | ||
87462e0f CF |
1540 | if (op1 != 3) { |
1541 | unallocated_encoding(s); | |
1542 | return; | |
1543 | } | |
1544 | ||
1545 | switch (op2) { | |
1546 | case 2: /* CLREX */ | |
fa2ef212 | 1547 | gen_clrex(s, insn); |
87462e0f CF |
1548 | return; |
1549 | case 4: /* DSB */ | |
1550 | case 5: /* DMB */ | |
ce1bd93f PK |
1551 | switch (crm & 3) { |
1552 | case 1: /* MBReqTypes_Reads */ | |
1553 | bar = TCG_BAR_SC | TCG_MO_LD_LD | TCG_MO_LD_ST; | |
1554 | break; | |
1555 | case 2: /* MBReqTypes_Writes */ | |
1556 | bar = TCG_BAR_SC | TCG_MO_ST_ST; | |
1557 | break; | |
1558 | default: /* MBReqTypes_All */ | |
1559 | bar = TCG_BAR_SC | TCG_MO_ALL; | |
1560 | break; | |
1561 | } | |
1562 | tcg_gen_mb(bar); | |
87462e0f | 1563 | return; |
6df99dec SS |
1564 | case 6: /* ISB */ |
1565 | /* We need to break the TB after this insn to execute | |
1566 | * a self-modified code correctly and also to take | |
1567 | * any pending interrupts immediately. | |
1568 | */ | |
35862270 | 1569 | reset_btype(s); |
a0415916 | 1570 | gen_goto_tb(s, 0, s->base.pc_next); |
6df99dec | 1571 | return; |
9888bd1e RH |
1572 | |
1573 | case 7: /* SB */ | |
1574 | if (crm != 0 || !dc_isar_feature(aa64_sb, s)) { | |
1575 | goto do_unallocated; | |
1576 | } | |
1577 | /* | |
1578 | * TODO: There is no speculation barrier opcode for TCG; | |
1579 | * MB and end the TB instead. | |
1580 | */ | |
1581 | tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); | |
a0415916 | 1582 | gen_goto_tb(s, 0, s->base.pc_next); |
9888bd1e RH |
1583 | return; |
1584 | ||
87462e0f | 1585 | default: |
9888bd1e | 1586 | do_unallocated: |
87462e0f CF |
1587 | unallocated_encoding(s); |
1588 | return; | |
1589 | } | |
1590 | } | |
1591 | ||
5ef84f11 RH |
1592 | static void gen_xaflag(void) |
1593 | { | |
1594 | TCGv_i32 z = tcg_temp_new_i32(); | |
1595 | ||
1596 | tcg_gen_setcondi_i32(TCG_COND_EQ, z, cpu_ZF, 0); | |
1597 | ||
1598 | /* | |
1599 | * (!C & !Z) << 31 | |
1600 | * (!(C | Z)) << 31 | |
1601 | * ~((C | Z) << 31) | |
1602 | * ~-(C | Z) | |
1603 | * (C | Z) - 1 | |
1604 | */ | |
1605 | tcg_gen_or_i32(cpu_NF, cpu_CF, z); | |
1606 | tcg_gen_subi_i32(cpu_NF, cpu_NF, 1); | |
1607 | ||
1608 | /* !(Z & C) */ | |
1609 | tcg_gen_and_i32(cpu_ZF, z, cpu_CF); | |
1610 | tcg_gen_xori_i32(cpu_ZF, cpu_ZF, 1); | |
1611 | ||
1612 | /* (!C & Z) << 31 -> -(Z & ~C) */ | |
1613 | tcg_gen_andc_i32(cpu_VF, z, cpu_CF); | |
1614 | tcg_gen_neg_i32(cpu_VF, cpu_VF); | |
1615 | ||
1616 | /* C | Z */ | |
1617 | tcg_gen_or_i32(cpu_CF, cpu_CF, z); | |
1618 | ||
1619 | tcg_temp_free_i32(z); | |
1620 | } | |
1621 | ||
1622 | static void gen_axflag(void) | |
1623 | { | |
1624 | tcg_gen_sari_i32(cpu_VF, cpu_VF, 31); /* V ? -1 : 0 */ | |
1625 | tcg_gen_andc_i32(cpu_CF, cpu_CF, cpu_VF); /* C & !V */ | |
1626 | ||
1627 | /* !(Z | V) -> !(!ZF | V) -> ZF & !V -> ZF & ~VF */ | |
1628 | tcg_gen_andc_i32(cpu_ZF, cpu_ZF, cpu_VF); | |
1629 | ||
1630 | tcg_gen_movi_i32(cpu_NF, 0); | |
1631 | tcg_gen_movi_i32(cpu_VF, 0); | |
1632 | } | |
1633 | ||
4ce31af4 | 1634 | /* MSR (immediate) - move immediate to processor state field */ |
87462e0f CF |
1635 | static void handle_msr_i(DisasContext *s, uint32_t insn, |
1636 | unsigned int op1, unsigned int op2, unsigned int crm) | |
1637 | { | |
ff730e96 | 1638 | TCGv_i32 t1; |
9cfa0b4e | 1639 | int op = op1 << 3 | op2; |
ff730e96 RH |
1640 | |
1641 | /* End the TB by default, chaining is ok. */ | |
1642 | s->base.is_jmp = DISAS_TOO_MANY; | |
1643 | ||
9cfa0b4e | 1644 | switch (op) { |
b89d9c98 RH |
1645 | case 0x00: /* CFINV */ |
1646 | if (crm != 0 || !dc_isar_feature(aa64_condm_4, s)) { | |
1647 | goto do_unallocated; | |
1648 | } | |
1649 | tcg_gen_xori_i32(cpu_CF, cpu_CF, 1); | |
1650 | s->base.is_jmp = DISAS_NEXT; | |
1651 | break; | |
1652 | ||
5ef84f11 RH |
1653 | case 0x01: /* XAFlag */ |
1654 | if (crm != 0 || !dc_isar_feature(aa64_condm_5, s)) { | |
1655 | goto do_unallocated; | |
1656 | } | |
1657 | gen_xaflag(); | |
1658 | s->base.is_jmp = DISAS_NEXT; | |
1659 | break; | |
1660 | ||
1661 | case 0x02: /* AXFlag */ | |
1662 | if (crm != 0 || !dc_isar_feature(aa64_condm_5, s)) { | |
1663 | goto do_unallocated; | |
1664 | } | |
1665 | gen_axflag(); | |
1666 | s->base.is_jmp = DISAS_NEXT; | |
1667 | break; | |
1668 | ||
9eeb7a1c RH |
1669 | case 0x03: /* UAO */ |
1670 | if (!dc_isar_feature(aa64_uao, s) || s->current_el == 0) { | |
1671 | goto do_unallocated; | |
1672 | } | |
1673 | if (crm & 1) { | |
1674 | set_pstate_bits(PSTATE_UAO); | |
1675 | } else { | |
1676 | clear_pstate_bits(PSTATE_UAO); | |
1677 | } | |
1678 | t1 = tcg_const_i32(s->current_el); | |
1679 | gen_helper_rebuild_hflags_a64(cpu_env, t1); | |
1680 | tcg_temp_free_i32(t1); | |
1681 | break; | |
1682 | ||
220f508f RH |
1683 | case 0x04: /* PAN */ |
1684 | if (!dc_isar_feature(aa64_pan, s) || s->current_el == 0) { | |
1685 | goto do_unallocated; | |
1686 | } | |
1687 | if (crm & 1) { | |
1688 | set_pstate_bits(PSTATE_PAN); | |
1689 | } else { | |
1690 | clear_pstate_bits(PSTATE_PAN); | |
1691 | } | |
1692 | t1 = tcg_const_i32(s->current_el); | |
1693 | gen_helper_rebuild_hflags_a64(cpu_env, t1); | |
1694 | tcg_temp_free_i32(t1); | |
1695 | break; | |
1696 | ||
9cfa0b4e | 1697 | case 0x05: /* SPSel */ |
dcbff19b | 1698 | if (s->current_el == 0) { |
ff730e96 | 1699 | goto do_unallocated; |
9cfa0b4e | 1700 | } |
ff730e96 RH |
1701 | t1 = tcg_const_i32(crm & PSTATE_SP); |
1702 | gen_helper_msr_i_spsel(cpu_env, t1); | |
1703 | tcg_temp_free_i32(t1); | |
1704 | break; | |
1705 | ||
f2f68a78 RC |
1706 | case 0x19: /* SSBS */ |
1707 | if (!dc_isar_feature(aa64_ssbs, s)) { | |
1708 | goto do_unallocated; | |
1709 | } | |
1710 | if (crm & 1) { | |
1711 | set_pstate_bits(PSTATE_SSBS); | |
1712 | } else { | |
1713 | clear_pstate_bits(PSTATE_SSBS); | |
1714 | } | |
1715 | /* Don't need to rebuild hflags since SSBS is a nop */ | |
1716 | break; | |
1717 | ||
dc8b1853 RC |
1718 | case 0x1a: /* DIT */ |
1719 | if (!dc_isar_feature(aa64_dit, s)) { | |
1720 | goto do_unallocated; | |
1721 | } | |
1722 | if (crm & 1) { | |
1723 | set_pstate_bits(PSTATE_DIT); | |
1724 | } else { | |
1725 | clear_pstate_bits(PSTATE_DIT); | |
1726 | } | |
1727 | /* There's no need to rebuild hflags because DIT is a nop */ | |
1728 | break; | |
1729 | ||
9cfa0b4e | 1730 | case 0x1e: /* DAIFSet */ |
ff730e96 RH |
1731 | t1 = tcg_const_i32(crm); |
1732 | gen_helper_msr_i_daifset(cpu_env, t1); | |
1733 | tcg_temp_free_i32(t1); | |
1734 | break; | |
1735 | ||
9cfa0b4e | 1736 | case 0x1f: /* DAIFClear */ |
ff730e96 RH |
1737 | t1 = tcg_const_i32(crm); |
1738 | gen_helper_msr_i_daifclear(cpu_env, t1); | |
1739 | tcg_temp_free_i32(t1); | |
8da54b25 | 1740 | /* For DAIFClear, exit the cpu loop to re-evaluate pending IRQs. */ |
14407ec2 | 1741 | s->base.is_jmp = DISAS_UPDATE_EXIT; |
9cfa0b4e | 1742 | break; |
ff730e96 | 1743 | |
4b779ceb RH |
1744 | case 0x1c: /* TCO */ |
1745 | if (dc_isar_feature(aa64_mte, s)) { | |
1746 | /* Full MTE is enabled -- set the TCO bit as directed. */ | |
1747 | if (crm & 1) { | |
1748 | set_pstate_bits(PSTATE_TCO); | |
1749 | } else { | |
1750 | clear_pstate_bits(PSTATE_TCO); | |
1751 | } | |
1752 | t1 = tcg_const_i32(s->current_el); | |
1753 | gen_helper_rebuild_hflags_a64(cpu_env, t1); | |
1754 | tcg_temp_free_i32(t1); | |
1755 | /* Many factors, including TCO, go into MTE_ACTIVE. */ | |
1756 | s->base.is_jmp = DISAS_UPDATE_NOCHAIN; | |
1757 | } else if (dc_isar_feature(aa64_mte_insn_reg, s)) { | |
1758 | /* Only "instructions accessible at EL0" -- PSTATE.TCO is WI. */ | |
1759 | s->base.is_jmp = DISAS_NEXT; | |
1760 | } else { | |
1761 | goto do_unallocated; | |
1762 | } | |
1763 | break; | |
1764 | ||
9cfa0b4e | 1765 | default: |
ff730e96 | 1766 | do_unallocated: |
9cfa0b4e PM |
1767 | unallocated_encoding(s); |
1768 | return; | |
1769 | } | |
87462e0f CF |
1770 | } |
1771 | ||
b0d2b7d0 PM |
1772 | static void gen_get_nzcv(TCGv_i64 tcg_rt) |
1773 | { | |
1774 | TCGv_i32 tmp = tcg_temp_new_i32(); | |
1775 | TCGv_i32 nzcv = tcg_temp_new_i32(); | |
1776 | ||
1777 | /* build bit 31, N */ | |
1743d55c | 1778 | tcg_gen_andi_i32(nzcv, cpu_NF, (1U << 31)); |
b0d2b7d0 PM |
1779 | /* build bit 30, Z */ |
1780 | tcg_gen_setcondi_i32(TCG_COND_EQ, tmp, cpu_ZF, 0); | |
1781 | tcg_gen_deposit_i32(nzcv, nzcv, tmp, 30, 1); | |
1782 | /* build bit 29, C */ | |
1783 | tcg_gen_deposit_i32(nzcv, nzcv, cpu_CF, 29, 1); | |
1784 | /* build bit 28, V */ | |
1785 | tcg_gen_shri_i32(tmp, cpu_VF, 31); | |
1786 | tcg_gen_deposit_i32(nzcv, nzcv, tmp, 28, 1); | |
1787 | /* generate result */ | |
1788 | tcg_gen_extu_i32_i64(tcg_rt, nzcv); | |
1789 | ||
1790 | tcg_temp_free_i32(nzcv); | |
1791 | tcg_temp_free_i32(tmp); | |
1792 | } | |
1793 | ||
1794 | static void gen_set_nzcv(TCGv_i64 tcg_rt) | |
b0d2b7d0 PM |
1795 | { |
1796 | TCGv_i32 nzcv = tcg_temp_new_i32(); | |
1797 | ||
1798 | /* take NZCV from R[t] */ | |
ecc7b3aa | 1799 | tcg_gen_extrl_i64_i32(nzcv, tcg_rt); |
b0d2b7d0 PM |
1800 | |
1801 | /* bit 31, N */ | |
1743d55c | 1802 | tcg_gen_andi_i32(cpu_NF, nzcv, (1U << 31)); |
b0d2b7d0 PM |
1803 | /* bit 30, Z */ |
1804 | tcg_gen_andi_i32(cpu_ZF, nzcv, (1 << 30)); | |
1805 | tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_ZF, cpu_ZF, 0); | |
1806 | /* bit 29, C */ | |
1807 | tcg_gen_andi_i32(cpu_CF, nzcv, (1 << 29)); | |
1808 | tcg_gen_shri_i32(cpu_CF, cpu_CF, 29); | |
1809 | /* bit 28, V */ | |
1810 | tcg_gen_andi_i32(cpu_VF, nzcv, (1 << 28)); | |
1811 | tcg_gen_shli_i32(cpu_VF, cpu_VF, 3); | |
1812 | tcg_temp_free_i32(nzcv); | |
1813 | } | |
1814 | ||
4ce31af4 PM |
1815 | /* MRS - move from system register |
1816 | * MSR (register) - move to system register | |
1817 | * SYS | |
1818 | * SYSL | |
fea50522 PM |
1819 | * These are all essentially the same insn in 'read' and 'write' |
1820 | * versions, with varying op0 fields. | |
1821 | */ | |
1822 | static void handle_sys(DisasContext *s, uint32_t insn, bool isread, | |
1823 | unsigned int op0, unsigned int op1, unsigned int op2, | |
87462e0f CF |
1824 | unsigned int crn, unsigned int crm, unsigned int rt) |
1825 | { | |
fea50522 PM |
1826 | const ARMCPRegInfo *ri; |
1827 | TCGv_i64 tcg_rt; | |
87462e0f | 1828 | |
fea50522 PM |
1829 | ri = get_arm_cp_reginfo(s->cp_regs, |
1830 | ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, | |
1831 | crn, crm, op0, op1, op2)); | |
87462e0f | 1832 | |
fea50522 | 1833 | if (!ri) { |
626187d8 PM |
1834 | /* Unknown register; this might be a guest error or a QEMU |
1835 | * unimplemented feature. | |
1836 | */ | |
1837 | qemu_log_mask(LOG_UNIMP, "%s access to unsupported AArch64 " | |
1838 | "system register op0:%d op1:%d crn:%d crm:%d op2:%d\n", | |
1839 | isread ? "read" : "write", op0, op1, crn, crm, op2); | |
fea50522 PM |
1840 | unallocated_encoding(s); |
1841 | return; | |
1842 | } | |
1843 | ||
1844 | /* Check access permissions */ | |
dcbff19b | 1845 | if (!cp_access_ok(s->current_el, ri, isread)) { |
fea50522 PM |
1846 | unallocated_encoding(s); |
1847 | return; | |
1848 | } | |
1849 | ||
f59df3f2 PM |
1850 | if (ri->accessfn) { |
1851 | /* Emit code to perform further access permissions checks at | |
1852 | * runtime; this may result in an exception. | |
1853 | */ | |
1854 | TCGv_ptr tmpptr; | |
3f208fd7 | 1855 | TCGv_i32 tcg_syn, tcg_isread; |
8bcbf37c PM |
1856 | uint32_t syndrome; |
1857 | ||
43722a6d | 1858 | gen_a64_set_pc_im(s->pc_curr); |
f59df3f2 | 1859 | tmpptr = tcg_const_ptr(ri); |
8bcbf37c PM |
1860 | syndrome = syn_aa64_sysregtrap(op0, op1, op2, crn, crm, rt, isread); |
1861 | tcg_syn = tcg_const_i32(syndrome); | |
3f208fd7 PM |
1862 | tcg_isread = tcg_const_i32(isread); |
1863 | gen_helper_access_check_cp_reg(cpu_env, tmpptr, tcg_syn, tcg_isread); | |
f59df3f2 | 1864 | tcg_temp_free_ptr(tmpptr); |
8bcbf37c | 1865 | tcg_temp_free_i32(tcg_syn); |
3f208fd7 | 1866 | tcg_temp_free_i32(tcg_isread); |
37ff584c PM |
1867 | } else if (ri->type & ARM_CP_RAISES_EXC) { |
1868 | /* | |
1869 | * The readfn or writefn might raise an exception; | |
1870 | * synchronize the CPU state in case it does. | |
1871 | */ | |
1872 | gen_a64_set_pc_im(s->pc_curr); | |
f59df3f2 PM |
1873 | } |
1874 | ||
fea50522 PM |
1875 | /* Handle special cases first */ |
1876 | switch (ri->type & ~(ARM_CP_FLAG_MASK & ~ARM_CP_SPECIAL)) { | |
1877 | case ARM_CP_NOP: | |
1878 | return; | |
b0d2b7d0 PM |
1879 | case ARM_CP_NZCV: |
1880 | tcg_rt = cpu_reg(s, rt); | |
1881 | if (isread) { | |
1882 | gen_get_nzcv(tcg_rt); | |
1883 | } else { | |
1884 | gen_set_nzcv(tcg_rt); | |
1885 | } | |
1886 | return; | |
0eef9d98 PM |
1887 | case ARM_CP_CURRENTEL: |
1888 | /* Reads as current EL value from pstate, which is | |
1889 | * guaranteed to be constant by the tb flags. | |
1890 | */ | |
1891 | tcg_rt = cpu_reg(s, rt); | |
dcbff19b | 1892 | tcg_gen_movi_i64(tcg_rt, s->current_el << 2); |
0eef9d98 | 1893 | return; |
aca3f40b PM |
1894 | case ARM_CP_DC_ZVA: |
1895 | /* Writes clear the aligned block of memory which rt points into. */ | |
46dc1bc0 RH |
1896 | if (s->mte_active[0]) { |
1897 | TCGv_i32 t_desc; | |
1898 | int desc = 0; | |
1899 | ||
1900 | desc = FIELD_DP32(desc, MTEDESC, MIDX, get_mem_index(s)); | |
1901 | desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid); | |
1902 | desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma); | |
1903 | t_desc = tcg_const_i32(desc); | |
1904 | ||
1905 | tcg_rt = new_tmp_a64(s); | |
1906 | gen_helper_mte_check_zva(tcg_rt, cpu_env, t_desc, cpu_reg(s, rt)); | |
1907 | tcg_temp_free_i32(t_desc); | |
1908 | } else { | |
1909 | tcg_rt = clean_data_tbi(s, cpu_reg(s, rt)); | |
1910 | } | |
aca3f40b PM |
1911 | gen_helper_dc_zva(cpu_env, tcg_rt); |
1912 | return; | |
eb821168 RH |
1913 | case ARM_CP_DC_GVA: |
1914 | { | |
1915 | TCGv_i64 clean_addr, tag; | |
1916 | ||
1917 | /* | |
1918 | * DC_GVA, like DC_ZVA, requires that we supply the original | |
1919 | * pointer for an invalid page. Probe that address first. | |
1920 | */ | |
1921 | tcg_rt = cpu_reg(s, rt); | |
1922 | clean_addr = clean_data_tbi(s, tcg_rt); | |
1923 | gen_probe_access(s, clean_addr, MMU_DATA_STORE, MO_8); | |
1924 | ||
1925 | if (s->ata) { | |
1926 | /* Extract the tag from the register to match STZGM. */ | |
1927 | tag = tcg_temp_new_i64(); | |
1928 | tcg_gen_shri_i64(tag, tcg_rt, 56); | |
1929 | gen_helper_stzgm_tags(cpu_env, clean_addr, tag); | |
1930 | tcg_temp_free_i64(tag); | |
1931 | } | |
1932 | } | |
1933 | return; | |
1934 | case ARM_CP_DC_GZVA: | |
1935 | { | |
1936 | TCGv_i64 clean_addr, tag; | |
1937 | ||
1938 | /* For DC_GZVA, we can rely on DC_ZVA for the proper fault. */ | |
1939 | tcg_rt = cpu_reg(s, rt); | |
1940 | clean_addr = clean_data_tbi(s, tcg_rt); | |
1941 | gen_helper_dc_zva(cpu_env, clean_addr); | |
1942 | ||
1943 | if (s->ata) { | |
1944 | /* Extract the tag from the register to match STZGM. */ | |
1945 | tag = tcg_temp_new_i64(); | |
1946 | tcg_gen_shri_i64(tag, tcg_rt, 56); | |
1947 | gen_helper_stzgm_tags(cpu_env, clean_addr, tag); | |
1948 | tcg_temp_free_i64(tag); | |
1949 | } | |
1950 | } | |
1951 | return; | |
fea50522 PM |
1952 | default: |
1953 | break; | |
1954 | } | |
fe03d45f RH |
1955 | if ((ri->type & ARM_CP_FPU) && !fp_access_check(s)) { |
1956 | return; | |
11d7870b RH |
1957 | } else if ((ri->type & ARM_CP_SVE) && !sve_access_check(s)) { |
1958 | return; | |
fe03d45f | 1959 | } |
fea50522 | 1960 | |
c5a49c63 | 1961 | if ((tb_cflags(s->base.tb) & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) { |
fea50522 PM |
1962 | gen_io_start(); |
1963 | } | |
1964 | ||
1965 | tcg_rt = cpu_reg(s, rt); | |
1966 | ||
1967 | if (isread) { | |
1968 | if (ri->type & ARM_CP_CONST) { | |
1969 | tcg_gen_movi_i64(tcg_rt, ri->resetvalue); | |
1970 | } else if (ri->readfn) { | |
1971 | TCGv_ptr tmpptr; | |
fea50522 PM |
1972 | tmpptr = tcg_const_ptr(ri); |
1973 | gen_helper_get_cp_reg64(tcg_rt, cpu_env, tmpptr); | |
1974 | tcg_temp_free_ptr(tmpptr); | |
1975 | } else { | |
1976 | tcg_gen_ld_i64(tcg_rt, cpu_env, ri->fieldoffset); | |
1977 | } | |
1978 | } else { | |
1979 | if (ri->type & ARM_CP_CONST) { | |
1980 | /* If not forbidden by access permissions, treat as WI */ | |
1981 | return; | |
1982 | } else if (ri->writefn) { | |
1983 | TCGv_ptr tmpptr; | |
fea50522 PM |
1984 | tmpptr = tcg_const_ptr(ri); |
1985 | gen_helper_set_cp_reg64(cpu_env, tmpptr, tcg_rt); | |
1986 | tcg_temp_free_ptr(tmpptr); | |
1987 | } else { | |
1988 | tcg_gen_st_i64(tcg_rt, cpu_env, ri->fieldoffset); | |
1989 | } | |
1990 | } | |
1991 | ||
c5a49c63 | 1992 | if ((tb_cflags(s->base.tb) & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) { |
fea50522 | 1993 | /* I/O operations must end the TB here (whether read or write) */ |
14407ec2 | 1994 | s->base.is_jmp = DISAS_UPDATE_EXIT; |
69d66864 RH |
1995 | } |
1996 | if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) { | |
1997 | /* | |
1998 | * A write to any coprocessor regiser that ends a TB | |
1999 | * must rebuild the hflags for the next TB. | |
2000 | */ | |
2001 | TCGv_i32 tcg_el = tcg_const_i32(s->current_el); | |
2002 | gen_helper_rebuild_hflags_a64(cpu_env, tcg_el); | |
2003 | tcg_temp_free_i32(tcg_el); | |
2004 | /* | |
2005 | * We default to ending the TB on a coprocessor register write, | |
fea50522 PM |
2006 | * but allow this to be suppressed by the register definition |
2007 | * (usually only necessary to work around guest bugs). | |
2008 | */ | |
14407ec2 | 2009 | s->base.is_jmp = DISAS_UPDATE_EXIT; |
fea50522 | 2010 | } |
ad7ee8a2 CF |
2011 | } |
2012 | ||
4ce31af4 | 2013 | /* System |
87462e0f CF |
2014 | * 31 22 21 20 19 18 16 15 12 11 8 7 5 4 0 |
2015 | * +---------------------+---+-----+-----+-------+-------+-----+------+ | |
2016 | * | 1 1 0 1 0 1 0 1 0 0 | L | op0 | op1 | CRn | CRm | op2 | Rt | | |
2017 | * +---------------------+---+-----+-----+-------+-------+-----+------+ | |
2018 | */ | |
2019 | static void disas_system(DisasContext *s, uint32_t insn) | |
2020 | { | |
2021 | unsigned int l, op0, op1, crn, crm, op2, rt; | |
2022 | l = extract32(insn, 21, 1); | |
2023 | op0 = extract32(insn, 19, 2); | |
2024 | op1 = extract32(insn, 16, 3); | |
2025 | crn = extract32(insn, 12, 4); | |
2026 | crm = extract32(insn, 8, 4); | |
2027 | op2 = extract32(insn, 5, 3); | |
2028 | rt = extract32(insn, 0, 5); | |
2029 | ||
2030 | if (op0 == 0) { | |
2031 | if (l || rt != 31) { | |
2032 | unallocated_encoding(s); | |
2033 | return; | |
2034 | } | |
2035 | switch (crn) { | |
4ce31af4 | 2036 | case 2: /* HINT (including allocated hints like NOP, YIELD, etc) */ |
87462e0f CF |
2037 | handle_hint(s, insn, op1, op2, crm); |
2038 | break; | |
2039 | case 3: /* CLREX, DSB, DMB, ISB */ | |
2040 | handle_sync(s, insn, op1, op2, crm); | |
2041 | break; | |
4ce31af4 | 2042 | case 4: /* MSR (immediate) */ |
87462e0f CF |
2043 | handle_msr_i(s, insn, op1, op2, crm); |
2044 | break; | |
2045 | default: | |
2046 | unallocated_encoding(s); | |
2047 | break; | |
2048 | } | |
2049 | return; | |
2050 | } | |
fea50522 | 2051 | handle_sys(s, insn, l, op0, op1, op2, crn, crm, rt); |
87462e0f CF |
2052 | } |
2053 | ||
4ce31af4 | 2054 | /* Exception generation |
9618e809 AG |
2055 | * |
2056 | * 31 24 23 21 20 5 4 2 1 0 | |
2057 | * +-----------------+-----+------------------------+-----+----+ | |
2058 | * | 1 1 0 1 0 1 0 0 | opc | imm16 | op2 | LL | | |
2059 | * +-----------------------+------------------------+----------+ | |
2060 | */ | |
ad7ee8a2 CF |
2061 | static void disas_exc(DisasContext *s, uint32_t insn) |
2062 | { | |
9618e809 AG |
2063 | int opc = extract32(insn, 21, 3); |
2064 | int op2_ll = extract32(insn, 0, 5); | |
d4a2dc67 | 2065 | int imm16 = extract32(insn, 5, 16); |
e0d6e6a5 | 2066 | TCGv_i32 tmp; |
9618e809 AG |
2067 | |
2068 | switch (opc) { | |
2069 | case 0: | |
7ea47fe7 PM |
2070 | /* For SVC, HVC and SMC we advance the single-step state |
2071 | * machine before taking the exception. This is architecturally | |
2072 | * mandated, to ensure that single-stepping a system call | |
2073 | * instruction works properly. | |
2074 | */ | |
35979d71 | 2075 | switch (op2_ll) { |
957956b3 | 2076 | case 1: /* SVC */ |
35979d71 | 2077 | gen_ss_advance(s); |
a767fac8 RH |
2078 | gen_exception_insn(s, s->base.pc_next, EXCP_SWI, |
2079 | syn_aa64_svc(imm16), default_exception_el(s)); | |
35979d71 | 2080 | break; |
957956b3 | 2081 | case 2: /* HVC */ |
dcbff19b | 2082 | if (s->current_el == 0) { |
35979d71 EI |
2083 | unallocated_encoding(s); |
2084 | break; | |
2085 | } | |
2086 | /* The pre HVC helper handles cases when HVC gets trapped | |
2087 | * as an undefined insn by runtime configuration. | |
2088 | */ | |
43722a6d | 2089 | gen_a64_set_pc_im(s->pc_curr); |
35979d71 EI |
2090 | gen_helper_pre_hvc(cpu_env); |
2091 | gen_ss_advance(s); | |
a767fac8 RH |
2092 | gen_exception_insn(s, s->base.pc_next, EXCP_HVC, |
2093 | syn_aa64_hvc(imm16), 2); | |
35979d71 | 2094 | break; |
957956b3 | 2095 | case 3: /* SMC */ |
dcbff19b | 2096 | if (s->current_el == 0) { |
e0d6e6a5 EI |
2097 | unallocated_encoding(s); |
2098 | break; | |
2099 | } | |
43722a6d | 2100 | gen_a64_set_pc_im(s->pc_curr); |
e0d6e6a5 EI |
2101 | tmp = tcg_const_i32(syn_aa64_smc(imm16)); |
2102 | gen_helper_pre_smc(cpu_env, tmp); | |
2103 | tcg_temp_free_i32(tmp); | |
2104 | gen_ss_advance(s); | |
a767fac8 RH |
2105 | gen_exception_insn(s, s->base.pc_next, EXCP_SMC, |
2106 | syn_aa64_smc(imm16), 3); | |
e0d6e6a5 | 2107 | break; |
35979d71 EI |
2108 | default: |
2109 | unallocated_encoding(s); | |
2110 | break; | |
2111 | } | |
9618e809 AG |
2112 | break; |
2113 | case 1: | |
2114 | if (op2_ll != 0) { | |
2115 | unallocated_encoding(s); | |
2116 | break; | |
2117 | } | |
2118 | /* BRK */ | |
06bcbda3 | 2119 | gen_exception_bkpt_insn(s, syn_aa64_bkpt(imm16)); |
9618e809 AG |
2120 | break; |
2121 | case 2: | |
2122 | if (op2_ll != 0) { | |
2123 | unallocated_encoding(s); | |
2124 | break; | |
2125 | } | |
8012c84f PM |
2126 | /* HLT. This has two purposes. |
2127 | * Architecturally, it is an external halting debug instruction. | |
2128 | * Since QEMU doesn't implement external debug, we treat this as | |
2129 | * it is required for halting debug disabled: it will UNDEF. | |
2130 | * Secondly, "HLT 0xf000" is the A64 semihosting syscall instruction. | |
2131 | */ | |
2132 | if (semihosting_enabled() && imm16 == 0xf000) { | |
2133 | #ifndef CONFIG_USER_ONLY | |
2134 | /* In system mode, don't allow userspace access to semihosting, | |
2135 | * to provide some semblance of security (and for consistency | |
2136 | * with our 32-bit semihosting). | |
2137 | */ | |
2138 | if (s->current_el == 0) { | |
2139 | unsupported_encoding(s, insn); | |
2140 | break; | |
2141 | } | |
2142 | #endif | |
4ff5ef9e | 2143 | gen_exception_internal_insn(s, s->pc_curr, EXCP_SEMIHOST); |
8012c84f PM |
2144 | } else { |
2145 | unsupported_encoding(s, insn); | |
2146 | } | |
9618e809 AG |
2147 | break; |
2148 | case 5: | |
2149 | if (op2_ll < 1 || op2_ll > 3) { | |
2150 | unallocated_encoding(s); | |
2151 | break; | |
2152 | } | |
2153 | /* DCPS1, DCPS2, DCPS3 */ | |
2154 | unsupported_encoding(s, insn); | |
2155 | break; | |
2156 | default: | |
2157 | unallocated_encoding(s); | |
2158 | break; | |
2159 | } | |
ad7ee8a2 CF |
2160 | } |
2161 | ||
4ce31af4 | 2162 | /* Unconditional branch (register) |
b001c8c3 AG |
2163 | * 31 25 24 21 20 16 15 10 9 5 4 0 |
2164 | * +---------------+-------+-------+-------+------+-------+ | |
2165 | * | 1 1 0 1 0 1 1 | opc | op2 | op3 | Rn | op4 | | |
2166 | * +---------------+-------+-------+-------+------+-------+ | |
2167 | */ | |
ad7ee8a2 CF |
2168 | static void disas_uncond_b_reg(DisasContext *s, uint32_t insn) |
2169 | { | |
b001c8c3 | 2170 | unsigned int opc, op2, op3, rn, op4; |
001d47b6 | 2171 | unsigned btype_mod = 2; /* 0: BR, 1: BLR, 2: other */ |
d9f482a0 | 2172 | TCGv_i64 dst; |
561c0a33 | 2173 | TCGv_i64 modifier; |
b001c8c3 AG |
2174 | |
2175 | opc = extract32(insn, 21, 4); | |
2176 | op2 = extract32(insn, 16, 5); | |
2177 | op3 = extract32(insn, 10, 6); | |
2178 | rn = extract32(insn, 5, 5); | |
2179 | op4 = extract32(insn, 0, 5); | |
2180 | ||
f7cf3bfc RH |
2181 | if (op2 != 0x1f) { |
2182 | goto do_unallocated; | |
b001c8c3 AG |
2183 | } |
2184 | ||
2185 | switch (opc) { | |
2186 | case 0: /* BR */ | |
b001c8c3 | 2187 | case 1: /* BLR */ |
6feecb8b | 2188 | case 2: /* RET */ |
001d47b6 | 2189 | btype_mod = opc; |
f7cf3bfc RH |
2190 | switch (op3) { |
2191 | case 0: | |
561c0a33 | 2192 | /* BR, BLR, RET */ |
f7cf3bfc RH |
2193 | if (op4 != 0) { |
2194 | goto do_unallocated; | |
2195 | } | |
2196 | dst = cpu_reg(s, rn); | |
2197 | break; | |
2198 | ||
561c0a33 RH |
2199 | case 2: |
2200 | case 3: | |
2201 | if (!dc_isar_feature(aa64_pauth, s)) { | |
2202 | goto do_unallocated; | |
2203 | } | |
2204 | if (opc == 2) { | |
2205 | /* RETAA, RETAB */ | |
2206 | if (rn != 0x1f || op4 != 0x1f) { | |
2207 | goto do_unallocated; | |
2208 | } | |
2209 | rn = 30; | |
2210 | modifier = cpu_X[31]; | |
2211 | } else { | |
2212 | /* BRAAZ, BRABZ, BLRAAZ, BLRABZ */ | |
2213 | if (op4 != 0x1f) { | |
2214 | goto do_unallocated; | |
2215 | } | |
2216 | modifier = new_tmp_a64_zero(s); | |
2217 | } | |
2218 | if (s->pauth_active) { | |
2219 | dst = new_tmp_a64(s); | |
2220 | if (op3 == 2) { | |
2221 | gen_helper_autia(dst, cpu_env, cpu_reg(s, rn), modifier); | |
2222 | } else { | |
2223 | gen_helper_autib(dst, cpu_env, cpu_reg(s, rn), modifier); | |
2224 | } | |
2225 | } else { | |
2226 | dst = cpu_reg(s, rn); | |
2227 | } | |
2228 | break; | |
2229 | ||
f7cf3bfc RH |
2230 | default: |
2231 | goto do_unallocated; | |
2232 | } | |
f7cf3bfc | 2233 | gen_a64_set_pc(s, dst); |
6feecb8b TH |
2234 | /* BLR also needs to load return address */ |
2235 | if (opc == 1) { | |
a0415916 | 2236 | tcg_gen_movi_i64(cpu_reg(s, 30), s->base.pc_next); |
6feecb8b | 2237 | } |
b001c8c3 | 2238 | break; |
f7cf3bfc | 2239 | |
561c0a33 RH |
2240 | case 8: /* BRAA */ |
2241 | case 9: /* BLRAA */ | |
2242 | if (!dc_isar_feature(aa64_pauth, s)) { | |
2243 | goto do_unallocated; | |
2244 | } | |
1cf86a86 | 2245 | if ((op3 & ~1) != 2) { |
561c0a33 RH |
2246 | goto do_unallocated; |
2247 | } | |
001d47b6 | 2248 | btype_mod = opc & 1; |
561c0a33 RH |
2249 | if (s->pauth_active) { |
2250 | dst = new_tmp_a64(s); | |
2251 | modifier = cpu_reg_sp(s, op4); | |
2252 | if (op3 == 2) { | |
2253 | gen_helper_autia(dst, cpu_env, cpu_reg(s, rn), modifier); | |
2254 | } else { | |
2255 | gen_helper_autib(dst, cpu_env, cpu_reg(s, rn), modifier); | |
2256 | } | |
2257 | } else { | |
2258 | dst = cpu_reg(s, rn); | |
2259 | } | |
2260 | gen_a64_set_pc(s, dst); | |
2261 | /* BLRAA also needs to load return address */ | |
2262 | if (opc == 9) { | |
a0415916 | 2263 | tcg_gen_movi_i64(cpu_reg(s, 30), s->base.pc_next); |
561c0a33 RH |
2264 | } |
2265 | break; | |
2266 | ||
b001c8c3 | 2267 | case 4: /* ERET */ |
dcbff19b | 2268 | if (s->current_el == 0) { |
f7cf3bfc RH |
2269 | goto do_unallocated; |
2270 | } | |
2271 | switch (op3) { | |
561c0a33 | 2272 | case 0: /* ERET */ |
f7cf3bfc RH |
2273 | if (op4 != 0) { |
2274 | goto do_unallocated; | |
2275 | } | |
2276 | dst = tcg_temp_new_i64(); | |
2277 | tcg_gen_ld_i64(dst, cpu_env, | |
2278 | offsetof(CPUARMState, elr_el[s->current_el])); | |
2279 | break; | |
2280 | ||
561c0a33 RH |
2281 | case 2: /* ERETAA */ |
2282 | case 3: /* ERETAB */ | |
2283 | if (!dc_isar_feature(aa64_pauth, s)) { | |
2284 | goto do_unallocated; | |
2285 | } | |
2286 | if (rn != 0x1f || op4 != 0x1f) { | |
2287 | goto do_unallocated; | |
2288 | } | |
2289 | dst = tcg_temp_new_i64(); | |
2290 | tcg_gen_ld_i64(dst, cpu_env, | |
2291 | offsetof(CPUARMState, elr_el[s->current_el])); | |
2292 | if (s->pauth_active) { | |
2293 | modifier = cpu_X[31]; | |
2294 | if (op3 == 2) { | |
2295 | gen_helper_autia(dst, cpu_env, dst, modifier); | |
2296 | } else { | |
2297 | gen_helper_autib(dst, cpu_env, dst, modifier); | |
2298 | } | |
2299 | } | |
2300 | break; | |
2301 | ||
f7cf3bfc RH |
2302 | default: |
2303 | goto do_unallocated; | |
14c521d4 | 2304 | } |
e69ad9df AL |
2305 | if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { |
2306 | gen_io_start(); | |
2307 | } | |
f7cf3bfc | 2308 | |
d9f482a0 RH |
2309 | gen_helper_exception_return(cpu_env, dst); |
2310 | tcg_temp_free_i64(dst); | |
b29fd33d | 2311 | /* Must exit loop to check un-masked IRQs */ |
dcba3a8d | 2312 | s->base.is_jmp = DISAS_EXIT; |
52e60cdd | 2313 | return; |
f7cf3bfc | 2314 | |
b001c8c3 | 2315 | case 5: /* DRPS */ |
f7cf3bfc RH |
2316 | if (op3 != 0 || op4 != 0 || rn != 0x1f) { |
2317 | goto do_unallocated; | |
b001c8c3 AG |
2318 | } else { |
2319 | unsupported_encoding(s, insn); | |
2320 | } | |
2321 | return; | |
f7cf3bfc | 2322 | |
b001c8c3 | 2323 | default: |
f7cf3bfc | 2324 | do_unallocated: |
b001c8c3 AG |
2325 | unallocated_encoding(s); |
2326 | return; | |
2327 | } | |
2328 | ||
001d47b6 RH |
2329 | switch (btype_mod) { |
2330 | case 0: /* BR */ | |
2331 | if (dc_isar_feature(aa64_bti, s)) { | |
2332 | /* BR to {x16,x17} or !guard -> 1, else 3. */ | |
2333 | set_btype(s, rn == 16 || rn == 17 || !s->guarded_page ? 1 : 3); | |
2334 | } | |
2335 | break; | |
2336 | ||
2337 | case 1: /* BLR */ | |
2338 | if (dc_isar_feature(aa64_bti, s)) { | |
2339 | /* BLR sets BTYPE to 2, regardless of source guarded page. */ | |
2340 | set_btype(s, 2); | |
2341 | } | |
2342 | break; | |
2343 | ||
2344 | default: /* RET or none of the above. */ | |
2345 | /* BTYPE will be set to 0 by normal end-of-insn processing. */ | |
2346 | break; | |
2347 | } | |
2348 | ||
dcba3a8d | 2349 | s->base.is_jmp = DISAS_JUMP; |
ad7ee8a2 CF |
2350 | } |
2351 | ||
4ce31af4 | 2352 | /* Branches, exception generating and system instructions */ |
ad7ee8a2 CF |
2353 | static void disas_b_exc_sys(DisasContext *s, uint32_t insn) |
2354 | { | |
2355 | switch (extract32(insn, 25, 7)) { | |
2356 | case 0x0a: case 0x0b: | |
2357 | case 0x4a: case 0x4b: /* Unconditional branch (immediate) */ | |
2358 | disas_uncond_b_imm(s, insn); | |
2359 | break; | |
2360 | case 0x1a: case 0x5a: /* Compare & branch (immediate) */ | |
2361 | disas_comp_b_imm(s, insn); | |
2362 | break; | |
2363 | case 0x1b: case 0x5b: /* Test & branch (immediate) */ | |
2364 | disas_test_b_imm(s, insn); | |
2365 | break; | |
2366 | case 0x2a: /* Conditional branch (immediate) */ | |
2367 | disas_cond_b_imm(s, insn); | |
2368 | break; | |
2369 | case 0x6a: /* Exception generation / System */ | |
2370 | if (insn & (1 << 24)) { | |
08d5e3bd PM |
2371 | if (extract32(insn, 22, 2) == 0) { |
2372 | disas_system(s, insn); | |
2373 | } else { | |
2374 | unallocated_encoding(s); | |
2375 | } | |
ad7ee8a2 CF |
2376 | } else { |
2377 | disas_exc(s, insn); | |
2378 | } | |
2379 | break; | |
2380 | case 0x6b: /* Unconditional branch (register) */ | |
2381 | disas_uncond_b_reg(s, insn); | |
2382 | break; | |
2383 | default: | |
2384 | unallocated_encoding(s); | |
2385 | break; | |
2386 | } | |
2387 | } | |
2388 | ||
5460da50 AB |
2389 | /* |
2390 | * Load/Store exclusive instructions are implemented by remembering | |
2391 | * the value/address loaded, and seeing if these are the same | |
2392 | * when the store is performed. This is not actually the architecturally | |
2393 | * mandated semantics, but it works for typical guest code sequences | |
2394 | * and avoids having to monitor regular stores. | |
2395 | * | |
2396 | * The store exclusive uses the atomic cmpxchg primitives to avoid | |
2397 | * races in multi-threaded linux-user and when MTTCG softmmu is | |
2398 | * enabled. | |
2399 | */ | |
fa2ef212 MM |
2400 | static void gen_load_exclusive(DisasContext *s, int rt, int rt2, |
2401 | TCGv_i64 addr, int size, bool is_pair) | |
2402 | { | |
19514cde | 2403 | int idx = get_mem_index(s); |
14776ab5 | 2404 | MemOp memop = s->be_data; |
fa2ef212 MM |
2405 | |
2406 | g_assert(size <= 3); | |
fa2ef212 | 2407 | if (is_pair) { |
5460da50 | 2408 | g_assert(size >= 2); |
19514cde RH |
2409 | if (size == 2) { |
2410 | /* The pair must be single-copy atomic for the doubleword. */ | |
4a2fdb78 | 2411 | memop |= MO_64 | MO_ALIGN; |
19514cde RH |
2412 | tcg_gen_qemu_ld_i64(cpu_exclusive_val, addr, idx, memop); |
2413 | if (s->be_data == MO_LE) { | |
2414 | tcg_gen_extract_i64(cpu_reg(s, rt), cpu_exclusive_val, 0, 32); | |
2415 | tcg_gen_extract_i64(cpu_reg(s, rt2), cpu_exclusive_val, 32, 32); | |
2416 | } else { | |
2417 | tcg_gen_extract_i64(cpu_reg(s, rt), cpu_exclusive_val, 32, 32); | |
2418 | tcg_gen_extract_i64(cpu_reg(s, rt2), cpu_exclusive_val, 0, 32); | |
2419 | } | |
2420 | } else { | |
4a2fdb78 AF |
2421 | /* The pair must be single-copy atomic for *each* doubleword, not |
2422 | the entire quadword, however it must be quadword aligned. */ | |
19514cde | 2423 | memop |= MO_64; |
4a2fdb78 AF |
2424 | tcg_gen_qemu_ld_i64(cpu_exclusive_val, addr, idx, |
2425 | memop | MO_ALIGN_16); | |
19514cde RH |
2426 | |
2427 | TCGv_i64 addr2 = tcg_temp_new_i64(); | |
2428 | tcg_gen_addi_i64(addr2, addr, 8); | |
2429 | tcg_gen_qemu_ld_i64(cpu_exclusive_high, addr2, idx, memop); | |
2430 | tcg_temp_free_i64(addr2); | |
2431 | ||
2432 | tcg_gen_mov_i64(cpu_reg(s, rt), cpu_exclusive_val); | |
2433 | tcg_gen_mov_i64(cpu_reg(s, rt2), cpu_exclusive_high); | |
2434 | } | |
2435 | } else { | |
4a2fdb78 | 2436 | memop |= size | MO_ALIGN; |
19514cde RH |
2437 | tcg_gen_qemu_ld_i64(cpu_exclusive_val, addr, idx, memop); |
2438 | tcg_gen_mov_i64(cpu_reg(s, rt), cpu_exclusive_val); | |
fa2ef212 | 2439 | } |
fa2ef212 MM |
2440 | tcg_gen_mov_i64(cpu_exclusive_addr, addr); |
2441 | } | |
2442 | ||
fa2ef212 | 2443 | static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2, |
37e29a64 | 2444 | TCGv_i64 addr, int size, int is_pair) |
fa2ef212 | 2445 | { |
d324b36a PM |
2446 | /* if (env->exclusive_addr == addr && env->exclusive_val == [addr] |
2447 | * && (!is_pair || env->exclusive_high == [addr + datasize])) { | |
2448 | * [addr] = {Rt}; | |
2449 | * if (is_pair) { | |
2450 | * [addr + datasize] = {Rt2}; | |
2451 | * } | |
2452 | * {Rd} = 0; | |
2453 | * } else { | |
2454 | * {Rd} = 1; | |
2455 | * } | |
2456 | * env->exclusive_addr = -1; | |
2457 | */ | |
42a268c2 RH |
2458 | TCGLabel *fail_label = gen_new_label(); |
2459 | TCGLabel *done_label = gen_new_label(); | |
d324b36a PM |
2460 | TCGv_i64 tmp; |
2461 | ||
d324b36a PM |
2462 | tcg_gen_brcond_i64(TCG_COND_NE, addr, cpu_exclusive_addr, fail_label); |
2463 | ||
2464 | tmp = tcg_temp_new_i64(); | |
d324b36a | 2465 | if (is_pair) { |
1dd089d0 | 2466 | if (size == 2) { |
19514cde RH |
2467 | if (s->be_data == MO_LE) { |
2468 | tcg_gen_concat32_i64(tmp, cpu_reg(s, rt), cpu_reg(s, rt2)); | |
2469 | } else { | |
2470 | tcg_gen_concat32_i64(tmp, cpu_reg(s, rt2), cpu_reg(s, rt)); | |
2471 | } | |
37e29a64 RH |
2472 | tcg_gen_atomic_cmpxchg_i64(tmp, cpu_exclusive_addr, |
2473 | cpu_exclusive_val, tmp, | |
1dd089d0 | 2474 | get_mem_index(s), |
955fd0ad | 2475 | MO_64 | MO_ALIGN | s->be_data); |
19514cde | 2476 | tcg_gen_setcond_i64(TCG_COND_NE, tmp, tmp, cpu_exclusive_val); |
62823083 RH |
2477 | } else if (tb_cflags(s->base.tb) & CF_PARALLEL) { |
2478 | if (!HAVE_CMPXCHG128) { | |
2479 | gen_helper_exit_atomic(cpu_env); | |
2480 | s->base.is_jmp = DISAS_NORETURN; | |
2481 | } else if (s->be_data == MO_LE) { | |
2399d4e7 EC |
2482 | gen_helper_paired_cmpxchg64_le_parallel(tmp, cpu_env, |
2483 | cpu_exclusive_addr, | |
2484 | cpu_reg(s, rt), | |
2485 | cpu_reg(s, rt2)); | |
2486 | } else { | |
2399d4e7 EC |
2487 | gen_helper_paired_cmpxchg64_be_parallel(tmp, cpu_env, |
2488 | cpu_exclusive_addr, | |
2489 | cpu_reg(s, rt), | |
2490 | cpu_reg(s, rt2)); | |
2399d4e7 | 2491 | } |
62823083 RH |
2492 | } else if (s->be_data == MO_LE) { |
2493 | gen_helper_paired_cmpxchg64_le(tmp, cpu_env, cpu_exclusive_addr, | |
2494 | cpu_reg(s, rt), cpu_reg(s, rt2)); | |
2495 | } else { | |
2496 | gen_helper_paired_cmpxchg64_be(tmp, cpu_env, cpu_exclusive_addr, | |
2497 | cpu_reg(s, rt), cpu_reg(s, rt2)); | |
1dd089d0 EC |
2498 | } |
2499 | } else { | |
37e29a64 RH |
2500 | tcg_gen_atomic_cmpxchg_i64(tmp, cpu_exclusive_addr, cpu_exclusive_val, |
2501 | cpu_reg(s, rt), get_mem_index(s), | |
1dd089d0 EC |
2502 | size | MO_ALIGN | s->be_data); |
2503 | tcg_gen_setcond_i64(TCG_COND_NE, tmp, tmp, cpu_exclusive_val); | |
d324b36a | 2504 | } |
1dd089d0 EC |
2505 | tcg_gen_mov_i64(cpu_reg(s, rd), tmp); |
2506 | tcg_temp_free_i64(tmp); | |
d324b36a | 2507 | tcg_gen_br(done_label); |
1dd089d0 | 2508 | |
d324b36a PM |
2509 | gen_set_label(fail_label); |
2510 | tcg_gen_movi_i64(cpu_reg(s, rd), 1); | |
2511 | gen_set_label(done_label); | |
2512 | tcg_gen_movi_i64(cpu_exclusive_addr, -1); | |
fa2ef212 | 2513 | } |
fa2ef212 | 2514 | |
44ac14b0 RH |
2515 | static void gen_compare_and_swap(DisasContext *s, int rs, int rt, |
2516 | int rn, int size) | |
2517 | { | |
2518 | TCGv_i64 tcg_rs = cpu_reg(s, rs); | |
2519 | TCGv_i64 tcg_rt = cpu_reg(s, rt); | |
2520 | int memidx = get_mem_index(s); | |
3a471103 | 2521 | TCGv_i64 clean_addr; |
44ac14b0 RH |
2522 | |
2523 | if (rn == 31) { | |
2524 | gen_check_sp_alignment(s); | |
2525 | } | |
0a405be2 | 2526 | clean_addr = gen_mte_check1(s, cpu_reg_sp(s, rn), true, rn != 31, size); |
3a471103 | 2527 | tcg_gen_atomic_cmpxchg_i64(tcg_rs, clean_addr, tcg_rs, tcg_rt, memidx, |
44ac14b0 RH |
2528 | size | MO_ALIGN | s->be_data); |
2529 | } | |
2530 | ||
2531 | static void gen_compare_and_swap_pair(DisasContext *s, int rs, int rt, | |
2532 | int rn, int size) | |
2533 | { | |
2534 | TCGv_i64 s1 = cpu_reg(s, rs); | |
2535 | TCGv_i64 s2 = cpu_reg(s, rs + 1); | |
2536 | TCGv_i64 t1 = cpu_reg(s, rt); | |
2537 | TCGv_i64 t2 = cpu_reg(s, rt + 1); | |
3a471103 | 2538 | TCGv_i64 clean_addr; |
44ac14b0 RH |
2539 | int memidx = get_mem_index(s); |
2540 | ||
2541 | if (rn == 31) { | |
2542 | gen_check_sp_alignment(s); | |
2543 | } | |
0a405be2 RH |
2544 | |
2545 | /* This is a single atomic access, despite the "pair". */ | |
2546 | clean_addr = gen_mte_check1(s, cpu_reg_sp(s, rn), true, rn != 31, size + 1); | |
44ac14b0 RH |
2547 | |
2548 | if (size == 2) { | |
2549 | TCGv_i64 cmp = tcg_temp_new_i64(); | |
2550 | TCGv_i64 val = tcg_temp_new_i64(); | |
2551 | ||
2552 | if (s->be_data == MO_LE) { | |
2553 | tcg_gen_concat32_i64(val, t1, t2); | |
2554 | tcg_gen_concat32_i64(cmp, s1, s2); | |
2555 | } else { | |
2556 | tcg_gen_concat32_i64(val, t2, t1); | |
2557 | tcg_gen_concat32_i64(cmp, s2, s1); | |
2558 | } | |
2559 | ||
3a471103 | 2560 | tcg_gen_atomic_cmpxchg_i64(cmp, clean_addr, cmp, val, memidx, |
44ac14b0 RH |
2561 | MO_64 | MO_ALIGN | s->be_data); |
2562 | tcg_temp_free_i64(val); | |
2563 | ||
2564 | if (s->be_data == MO_LE) { | |
2565 | tcg_gen_extr32_i64(s1, s2, cmp); | |
2566 | } else { | |
2567 | tcg_gen_extr32_i64(s2, s1, cmp); | |
2568 | } | |
2569 | tcg_temp_free_i64(cmp); | |
2570 | } else if (tb_cflags(s->base.tb) & CF_PARALLEL) { | |
62823083 RH |
2571 | if (HAVE_CMPXCHG128) { |
2572 | TCGv_i32 tcg_rs = tcg_const_i32(rs); | |
2573 | if (s->be_data == MO_LE) { | |
3a471103 RH |
2574 | gen_helper_casp_le_parallel(cpu_env, tcg_rs, |
2575 | clean_addr, t1, t2); | |
62823083 | 2576 | } else { |
3a471103 RH |
2577 | gen_helper_casp_be_parallel(cpu_env, tcg_rs, |
2578 | clean_addr, t1, t2); | |
62823083 RH |
2579 | } |
2580 | tcg_temp_free_i32(tcg_rs); | |
44ac14b0 | 2581 | } else { |
62823083 RH |
2582 | gen_helper_exit_atomic(cpu_env); |
2583 | s->base.is_jmp = DISAS_NORETURN; | |
44ac14b0 | 2584 | } |
44ac14b0 RH |
2585 | } else { |
2586 | TCGv_i64 d1 = tcg_temp_new_i64(); | |
2587 | TCGv_i64 d2 = tcg_temp_new_i64(); | |
2588 | TCGv_i64 a2 = tcg_temp_new_i64(); | |
2589 | TCGv_i64 c1 = tcg_temp_new_i64(); | |
2590 | TCGv_i64 c2 = tcg_temp_new_i64(); | |
2591 | TCGv_i64 zero = tcg_const_i64(0); | |
2592 | ||
2593 | /* Load the two words, in memory order. */ | |
3a471103 | 2594 | tcg_gen_qemu_ld_i64(d1, clean_addr, memidx, |
44ac14b0 | 2595 | MO_64 | MO_ALIGN_16 | s->be_data); |
3a471103 | 2596 | tcg_gen_addi_i64(a2, clean_addr, 8); |
a036f530 | 2597 | tcg_gen_qemu_ld_i64(d2, a2, memidx, MO_64 | s->be_data); |
44ac14b0 RH |
2598 | |
2599 | /* Compare the two words, also in memory order. */ | |
2600 | tcg_gen_setcond_i64(TCG_COND_EQ, c1, d1, s1); | |
2601 | tcg_gen_setcond_i64(TCG_COND_EQ, c2, d2, s2); | |
2602 | tcg_gen_and_i64(c2, c2, c1); | |
2603 | ||
2604 | /* If compare equal, write back new data, else write back old data. */ | |
2605 | tcg_gen_movcond_i64(TCG_COND_NE, c1, c2, zero, t1, d1); | |
2606 | tcg_gen_movcond_i64(TCG_COND_NE, c2, c2, zero, t2, d2); | |
3a471103 | 2607 | tcg_gen_qemu_st_i64(c1, clean_addr, memidx, MO_64 | s->be_data); |
44ac14b0 RH |
2608 | tcg_gen_qemu_st_i64(c2, a2, memidx, MO_64 | s->be_data); |
2609 | tcg_temp_free_i64(a2); | |
2610 | tcg_temp_free_i64(c1); | |
2611 | tcg_temp_free_i64(c2); | |
2612 | tcg_temp_free_i64(zero); | |
2613 | ||
2614 | /* Write back the data from memory to Rs. */ | |
2615 | tcg_gen_mov_i64(s1, d1); | |
2616 | tcg_gen_mov_i64(s2, d2); | |
2617 | tcg_temp_free_i64(d1); | |
2618 | tcg_temp_free_i64(d2); | |
2619 | } | |
2620 | } | |
2621 | ||
aaa1f954 EI |
2622 | /* Update the Sixty-Four bit (SF) registersize. This logic is derived |
2623 | * from the ARMv8 specs for LDR (Shared decode for all encodings). | |
2624 | */ | |
2625 | static bool disas_ldst_compute_iss_sf(int size, bool is_signed, int opc) | |
2626 | { | |
2627 | int opc0 = extract32(opc, 0, 1); | |
2628 | int regsize; | |
2629 | ||
2630 | if (is_signed) { | |
2631 | regsize = opc0 ? 32 : 64; | |
2632 | } else { | |
2633 | regsize = size == 3 ? 64 : 32; | |
2634 | } | |
2635 | return regsize == 64; | |
2636 | } | |
2637 | ||
4ce31af4 | 2638 | /* Load/store exclusive |
fa2ef212 MM |
2639 | * |
2640 | * 31 30 29 24 23 22 21 20 16 15 14 10 9 5 4 0 | |
2641 | * +-----+-------------+----+---+----+------+----+-------+------+------+ | |
2642 | * | sz | 0 0 1 0 0 0 | o2 | L | o1 | Rs | o0 | Rt2 | Rn | Rt | | |
2643 | * +-----+-------------+----+---+----+------+----+-------+------+------+ | |
2644 | * | |
2645 | * sz: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64 bit | |
2646 | * L: 0 -> store, 1 -> load | |
2647 | * o2: 0 -> exclusive, 1 -> not | |
2648 | * o1: 0 -> single register, 1 -> register pair | |
2649 | * o0: 1 -> load-acquire/store-release, 0 -> not | |
fa2ef212 | 2650 | */ |
ad7ee8a2 CF |
2651 | static void disas_ldst_excl(DisasContext *s, uint32_t insn) |
2652 | { | |
fa2ef212 MM |
2653 | int rt = extract32(insn, 0, 5); |
2654 | int rn = extract32(insn, 5, 5); | |
2655 | int rt2 = extract32(insn, 10, 5); | |
fa2ef212 | 2656 | int rs = extract32(insn, 16, 5); |
68412d2e RH |
2657 | int is_lasr = extract32(insn, 15, 1); |
2658 | int o2_L_o1_o0 = extract32(insn, 21, 3) * 2 | is_lasr; | |
fa2ef212 | 2659 | int size = extract32(insn, 30, 2); |
3a471103 | 2660 | TCGv_i64 clean_addr; |
fa2ef212 | 2661 | |
68412d2e RH |
2662 | switch (o2_L_o1_o0) { |
2663 | case 0x0: /* STXR */ | |
2664 | case 0x1: /* STLXR */ | |
2665 | if (rn == 31) { | |
2666 | gen_check_sp_alignment(s); | |
2667 | } | |
2668 | if (is_lasr) { | |
2669 | tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); | |
2670 | } | |
0a405be2 RH |
2671 | clean_addr = gen_mte_check1(s, cpu_reg_sp(s, rn), |
2672 | true, rn != 31, size); | |
3a471103 | 2673 | gen_store_exclusive(s, rs, rt, rt2, clean_addr, size, false); |
fa2ef212 | 2674 | return; |
fa2ef212 | 2675 | |
68412d2e RH |
2676 | case 0x4: /* LDXR */ |
2677 | case 0x5: /* LDAXR */ | |
2678 | if (rn == 31) { | |
2679 | gen_check_sp_alignment(s); | |
2680 | } | |
0a405be2 RH |
2681 | clean_addr = gen_mte_check1(s, cpu_reg_sp(s, rn), |
2682 | false, rn != 31, size); | |
68412d2e | 2683 | s->is_ldex = true; |
3a471103 | 2684 | gen_load_exclusive(s, rt, rt2, clean_addr, size, false); |
68412d2e RH |
2685 | if (is_lasr) { |
2686 | tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); | |
2687 | } | |
2688 | return; | |
fa2ef212 | 2689 | |
2d7137c1 RH |
2690 | case 0x8: /* STLLR */ |
2691 | if (!dc_isar_feature(aa64_lor, s)) { | |
2692 | break; | |
2693 | } | |
2694 | /* StoreLORelease is the same as Store-Release for QEMU. */ | |
2695 | /* fall through */ | |
68412d2e RH |
2696 | case 0x9: /* STLR */ |
2697 | /* Generate ISS for non-exclusive accesses including LASR. */ | |
2698 | if (rn == 31) { | |
2699 | gen_check_sp_alignment(s); | |
2700 | } | |
2701 | tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); | |
0a405be2 RH |
2702 | clean_addr = gen_mte_check1(s, cpu_reg_sp(s, rn), |
2703 | true, rn != 31, size); | |
3a471103 | 2704 | do_gpr_st(s, cpu_reg(s, rt), clean_addr, size, true, rt, |
68412d2e RH |
2705 | disas_ldst_compute_iss_sf(size, false, 0), is_lasr); |
2706 | return; | |
fa2ef212 | 2707 | |
2d7137c1 RH |
2708 | case 0xc: /* LDLAR */ |
2709 | if (!dc_isar_feature(aa64_lor, s)) { | |
2710 | break; | |
2711 | } | |
2712 | /* LoadLOAcquire is the same as Load-Acquire for QEMU. */ | |
2713 | /* fall through */ | |
68412d2e RH |
2714 | case 0xd: /* LDAR */ |
2715 | /* Generate ISS for non-exclusive accesses including LASR. */ | |
2716 | if (rn == 31) { | |
2717 | gen_check_sp_alignment(s); | |
2718 | } | |
0a405be2 RH |
2719 | clean_addr = gen_mte_check1(s, cpu_reg_sp(s, rn), |
2720 | false, rn != 31, size); | |
3a471103 | 2721 | do_gpr_ld(s, cpu_reg(s, rt), clean_addr, size, false, false, true, rt, |
68412d2e RH |
2722 | disas_ldst_compute_iss_sf(size, false, 0), is_lasr); |
2723 | tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); | |
2724 | return; | |
2725 | ||
2726 | case 0x2: case 0x3: /* CASP / STXP */ | |
2727 | if (size & 2) { /* STXP / STLXP */ | |
2728 | if (rn == 31) { | |
2729 | gen_check_sp_alignment(s); | |
ce1bd93f | 2730 | } |
ce1bd93f PK |
2731 | if (is_lasr) { |
2732 | tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); | |
2733 | } | |
0a405be2 RH |
2734 | clean_addr = gen_mte_check1(s, cpu_reg_sp(s, rn), |
2735 | true, rn != 31, size); | |
3a471103 | 2736 | gen_store_exclusive(s, rs, rt, rt2, clean_addr, size, true); |
68412d2e | 2737 | return; |
fa2ef212 | 2738 | } |
44ac14b0 RH |
2739 | if (rt2 == 31 |
2740 | && ((rt | rs) & 1) == 0 | |
962fcbf2 | 2741 | && dc_isar_feature(aa64_atomics, s)) { |
44ac14b0 RH |
2742 | /* CASP / CASPL */ |
2743 | gen_compare_and_swap_pair(s, rs, rt, rn, size | 2); | |
2744 | return; | |
2745 | } | |
68412d2e | 2746 | break; |
aaa1f954 | 2747 | |
44ac14b0 | 2748 | case 0x6: case 0x7: /* CASPA / LDXP */ |
68412d2e RH |
2749 | if (size & 2) { /* LDXP / LDAXP */ |
2750 | if (rn == 31) { | |
2751 | gen_check_sp_alignment(s); | |
ce1bd93f | 2752 | } |
0a405be2 RH |
2753 | clean_addr = gen_mte_check1(s, cpu_reg_sp(s, rn), |
2754 | false, rn != 31, size); | |
68412d2e | 2755 | s->is_ldex = true; |
3a471103 | 2756 | gen_load_exclusive(s, rt, rt2, clean_addr, size, true); |
ce1bd93f PK |
2757 | if (is_lasr) { |
2758 | tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); | |
2759 | } | |
68412d2e | 2760 | return; |
fa2ef212 | 2761 | } |
44ac14b0 RH |
2762 | if (rt2 == 31 |
2763 | && ((rt | rs) & 1) == 0 | |
962fcbf2 | 2764 | && dc_isar_feature(aa64_atomics, s)) { |
44ac14b0 RH |
2765 | /* CASPA / CASPAL */ |
2766 | gen_compare_and_swap_pair(s, rs, rt, rn, size | 2); | |
2767 | return; | |
fa2ef212 | 2768 | } |
68412d2e RH |
2769 | break; |
2770 | ||
2771 | case 0xa: /* CAS */ | |
2772 | case 0xb: /* CASL */ | |
2773 | case 0xe: /* CASA */ | |
2774 | case 0xf: /* CASAL */ | |
962fcbf2 | 2775 | if (rt2 == 31 && dc_isar_feature(aa64_atomics, s)) { |
44ac14b0 RH |
2776 | gen_compare_and_swap(s, rs, rt, rn, size); |
2777 | return; | |
2778 | } | |
68412d2e | 2779 | break; |
fa2ef212 | 2780 | } |
68412d2e | 2781 | unallocated_encoding(s); |
ad7ee8a2 CF |
2782 | } |
2783 | ||
32b64e86 | 2784 | /* |
4ce31af4 | 2785 | * Load register (literal) |
32b64e86 AG |
2786 | * |
2787 | * 31 30 29 27 26 25 24 23 5 4 0 | |
2788 | * +-----+-------+---+-----+-------------------+-------+ | |
2789 | * | opc | 0 1 1 | V | 0 0 | imm19 | Rt | | |
2790 | * +-----+-------+---+-----+-------------------+-------+ | |
2791 | * | |
2792 | * V: 1 -> vector (simd/fp) | |
2793 | * opc (non-vector): 00 -> 32 bit, 01 -> 64 bit, | |
2794 | * 10-> 32 bit signed, 11 -> prefetch | |
2795 | * opc (vector): 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit (11 unallocated) | |
2796 | */ | |
ad7ee8a2 CF |
2797 | static void disas_ld_lit(DisasContext *s, uint32_t insn) |
2798 | { | |
32b64e86 AG |
2799 | int rt = extract32(insn, 0, 5); |
2800 | int64_t imm = sextract32(insn, 5, 19) << 2; | |
2801 | bool is_vector = extract32(insn, 26, 1); | |
2802 | int opc = extract32(insn, 30, 2); | |
2803 | bool is_signed = false; | |
2804 | int size = 2; | |
3a471103 | 2805 | TCGv_i64 tcg_rt, clean_addr; |
32b64e86 AG |
2806 | |
2807 | if (is_vector) { | |
2808 | if (opc == 3) { | |
2809 | unallocated_encoding(s); | |
2810 | return; | |
2811 | } | |
2812 | size = 2 + opc; | |
8c6afa6a PM |
2813 | if (!fp_access_check(s)) { |
2814 | return; | |
2815 | } | |
32b64e86 AG |
2816 | } else { |
2817 | if (opc == 3) { | |
2818 | /* PRFM (literal) : prefetch */ | |
2819 | return; | |
2820 | } | |
2821 | size = 2 + extract32(opc, 0, 1); | |
2822 | is_signed = extract32(opc, 1, 1); | |
2823 | } | |
2824 | ||
2825 | tcg_rt = cpu_reg(s, rt); | |
2826 | ||
43722a6d | 2827 | clean_addr = tcg_const_i64(s->pc_curr + imm); |
32b64e86 | 2828 | if (is_vector) { |
3a471103 | 2829 | do_fp_ld(s, rt, clean_addr, size); |
32b64e86 | 2830 | } else { |
aaa1f954 | 2831 | /* Only unsigned 32bit loads target 32bit registers. */ |
173ff585 | 2832 | bool iss_sf = opc != 0; |
aaa1f954 | 2833 | |
3a471103 | 2834 | do_gpr_ld(s, tcg_rt, clean_addr, size, is_signed, false, |
aaa1f954 | 2835 | true, rt, iss_sf, false); |
32b64e86 | 2836 | } |
3a471103 | 2837 | tcg_temp_free_i64(clean_addr); |
ad7ee8a2 CF |
2838 | } |
2839 | ||
4a08d475 | 2840 | /* |
4ce31af4 PM |
2841 | * LDNP (Load Pair - non-temporal hint) |
2842 | * LDP (Load Pair - non vector) | |
2843 | * LDPSW (Load Pair Signed Word - non vector) | |
2844 | * STNP (Store Pair - non-temporal hint) | |
2845 | * STP (Store Pair - non vector) | |
2846 | * LDNP (Load Pair of SIMD&FP - non-temporal hint) | |
2847 | * LDP (Load Pair of SIMD&FP) | |
2848 | * STNP (Store Pair of SIMD&FP - non-temporal hint) | |
2849 | * STP (Store Pair of SIMD&FP) | |
4a08d475 PM |
2850 | * |
2851 | * 31 30 29 27 26 25 24 23 22 21 15 14 10 9 5 4 0 | |
2852 | * +-----+-------+---+---+-------+---+-----------------------------+ | |
2853 | * | opc | 1 0 1 | V | 0 | index | L | imm7 | Rt2 | Rn | Rt | | |
2854 | * +-----+-------+---+---+-------+---+-------+-------+------+------+ | |
2855 | * | |
2856 | * opc: LDP/STP/LDNP/STNP 00 -> 32 bit, 10 -> 64 bit | |
6439d67f | 2857 | * LDPSW/STGP 01 |
4a08d475 PM |
2858 | * LDP/STP/LDNP/STNP (SIMD) 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit |
2859 | * V: 0 -> GPR, 1 -> Vector | |
2860 | * idx: 00 -> signed offset with non-temporal hint, 01 -> post-index, | |
2861 | * 10 -> signed offset, 11 -> pre-index | |
2862 | * L: 0 -> Store 1 -> Load | |
2863 | * | |
2864 | * Rt, Rt2 = GPR or SIMD registers to be stored | |
2865 | * Rn = general purpose register containing address | |
2866 | * imm7 = signed offset (multiple of 4 or 8 depending on size) | |
2867 | */ | |
ad7ee8a2 CF |
2868 | static void disas_ldst_pair(DisasContext *s, uint32_t insn) |
2869 | { | |
4a08d475 PM |
2870 | int rt = extract32(insn, 0, 5); |
2871 | int rn = extract32(insn, 5, 5); | |
2872 | int rt2 = extract32(insn, 10, 5); | |
c2ebd862 | 2873 | uint64_t offset = sextract64(insn, 15, 7); |
4a08d475 PM |
2874 | int index = extract32(insn, 23, 2); |
2875 | bool is_vector = extract32(insn, 26, 1); | |
2876 | bool is_load = extract32(insn, 22, 1); | |
2877 | int opc = extract32(insn, 30, 2); | |
2878 | ||
2879 | bool is_signed = false; | |
2880 | bool postindex = false; | |
2881 | bool wback = false; | |
6439d67f | 2882 | bool set_tag = false; |
4a08d475 | 2883 | |
3a471103 RH |
2884 | TCGv_i64 clean_addr, dirty_addr; |
2885 | ||
4a08d475 PM |
2886 | int size; |
2887 | ||
2888 | if (opc == 3) { | |
2889 | unallocated_encoding(s); | |
2890 | return; | |
2891 | } | |
2892 | ||
2893 | if (is_vector) { | |
2894 | size = 2 + opc; | |
6439d67f RH |
2895 | } else if (opc == 1 && !is_load) { |
2896 | /* STGP */ | |
2897 | if (!dc_isar_feature(aa64_mte_insn_reg, s) || index == 0) { | |
2898 | unallocated_encoding(s); | |
2899 | return; | |
2900 | } | |
2901 | size = 3; | |
2902 | set_tag = true; | |
4a08d475 PM |
2903 | } else { |
2904 | size = 2 + extract32(opc, 1, 1); | |
2905 | is_signed = extract32(opc, 0, 1); | |
2906 | if (!is_load && is_signed) { | |
2907 | unallocated_encoding(s); | |
2908 | return; | |
2909 | } | |
2910 | } | |
2911 | ||
2912 | switch (index) { | |
2913 | case 1: /* post-index */ | |
2914 | postindex = true; | |
2915 | wback = true; | |
2916 | break; | |
2917 | case 0: | |
2918 | /* signed offset with "non-temporal" hint. Since we don't emulate | |
2919 | * caches we don't care about hints to the cache system about | |
2920 | * data access patterns, and handle this identically to plain | |
2921 | * signed offset. | |
2922 | */ | |
2923 | if (is_signed) { | |
2924 | /* There is no non-temporal-hint version of LDPSW */ | |
2925 | unallocated_encoding(s); | |
2926 | return; | |
2927 | } | |
2928 | postindex = false; | |
2929 | break; | |
2930 | case 2: /* signed offset, rn not updated */ | |
2931 | postindex = false; | |
2932 | break; | |
2933 | case 3: /* pre-index */ | |
2934 | postindex = false; | |
2935 | wback = true; | |
2936 | break; | |
2937 | } | |
2938 | ||
8c6afa6a PM |
2939 | if (is_vector && !fp_access_check(s)) { |
2940 | return; | |
2941 | } | |
2942 | ||
6439d67f | 2943 | offset <<= (set_tag ? LOG2_TAG_GRANULE : size); |
4a08d475 PM |
2944 | |
2945 | if (rn == 31) { | |
2946 | gen_check_sp_alignment(s); | |
2947 | } | |
2948 | ||
3a471103 | 2949 | dirty_addr = read_cpu_reg_sp(s, rn, 1); |
4a08d475 | 2950 | if (!postindex) { |
3a471103 | 2951 | tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); |
4a08d475 PM |
2952 | } |
2953 | ||
6439d67f RH |
2954 | if (set_tag) { |
2955 | if (!s->ata) { | |
2956 | /* | |
2957 | * TODO: We could rely on the stores below, at least for | |
2958 | * system mode, if we arrange to add MO_ALIGN_16. | |
2959 | */ | |
2960 | gen_helper_stg_stub(cpu_env, dirty_addr); | |
2961 | } else if (tb_cflags(s->base.tb) & CF_PARALLEL) { | |
2962 | gen_helper_stg_parallel(cpu_env, dirty_addr, dirty_addr); | |
2963 | } else { | |
2964 | gen_helper_stg(cpu_env, dirty_addr, dirty_addr); | |
2965 | } | |
2966 | } | |
2967 | ||
73ceeb00 RH |
2968 | clean_addr = gen_mte_checkN(s, dirty_addr, !is_load, |
2969 | (wback || rn != 31) && !set_tag, | |
2970 | size, 2 << size); | |
2971 | ||
4a08d475 PM |
2972 | if (is_vector) { |
2973 | if (is_load) { | |
3a471103 | 2974 | do_fp_ld(s, rt, clean_addr, size); |
4a08d475 | 2975 | } else { |
3a471103 | 2976 | do_fp_st(s, rt, clean_addr, size); |
4a08d475 | 2977 | } |
3a471103 | 2978 | tcg_gen_addi_i64(clean_addr, clean_addr, 1 << size); |
4a08d475 | 2979 | if (is_load) { |
3a471103 | 2980 | do_fp_ld(s, rt2, clean_addr, size); |
4a08d475 | 2981 | } else { |
3a471103 | 2982 | do_fp_st(s, rt2, clean_addr, size); |
4a08d475 PM |
2983 | } |
2984 | } else { | |
3e4d91b9 | 2985 | TCGv_i64 tcg_rt = cpu_reg(s, rt); |
4a08d475 | 2986 | TCGv_i64 tcg_rt2 = cpu_reg(s, rt2); |
3e4d91b9 | 2987 | |
4a08d475 | 2988 | if (is_load) { |
3e4d91b9 RH |
2989 | TCGv_i64 tmp = tcg_temp_new_i64(); |
2990 | ||
2991 | /* Do not modify tcg_rt before recognizing any exception | |
2992 | * from the second load. | |
2993 | */ | |
3a471103 | 2994 | do_gpr_ld(s, tmp, clean_addr, size, is_signed, false, |
3e4d91b9 | 2995 | false, 0, false, false); |
3a471103 RH |
2996 | tcg_gen_addi_i64(clean_addr, clean_addr, 1 << size); |
2997 | do_gpr_ld(s, tcg_rt2, clean_addr, size, is_signed, false, | |
aaa1f954 | 2998 | false, 0, false, false); |
3e4d91b9 RH |
2999 | |
3000 | tcg_gen_mov_i64(tcg_rt, tmp); | |
3001 | tcg_temp_free_i64(tmp); | |
4a08d475 | 3002 | } else { |
3a471103 | 3003 | do_gpr_st(s, tcg_rt, clean_addr, size, |
3e4d91b9 | 3004 | false, 0, false, false); |
3a471103 RH |
3005 | tcg_gen_addi_i64(clean_addr, clean_addr, 1 << size); |
3006 | do_gpr_st(s, tcg_rt2, clean_addr, size, | |
aaa1f954 | 3007 | false, 0, false, false); |
4a08d475 PM |
3008 | } |
3009 | } | |
3010 | ||
3011 | if (wback) { | |
3012 | if (postindex) { | |
3a471103 | 3013 | tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); |
4a08d475 | 3014 | } |
3a471103 | 3015 | tcg_gen_mov_i64(cpu_reg_sp(s, rn), dirty_addr); |
4a08d475 | 3016 | } |
ad7ee8a2 CF |
3017 | } |
3018 | ||
a5e94a9d | 3019 | /* |
4ce31af4 PM |
3020 | * Load/store (immediate post-indexed) |
3021 | * Load/store (immediate pre-indexed) | |
3022 | * Load/store (unscaled immediate) | |
a5e94a9d AB |
3023 | * |
3024 | * 31 30 29 27 26 25 24 23 22 21 20 12 11 10 9 5 4 0 | |
3025 | * +----+-------+---+-----+-----+---+--------+-----+------+------+ | |
3026 | * |size| 1 1 1 | V | 0 0 | opc | 0 | imm9 | idx | Rn | Rt | | |
3027 | * +----+-------+---+-----+-----+---+--------+-----+------+------+ | |
3028 | * | |
3029 | * idx = 01 -> post-indexed, 11 pre-indexed, 00 unscaled imm. (no writeback) | |
60510aed | 3030 | 10 -> unprivileged |
a5e94a9d AB |
3031 | * V = 0 -> non-vector |
3032 | * size: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64bit | |
3033 | * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32 | |
3034 | */ | |
cd694521 EI |
3035 | static void disas_ldst_reg_imm9(DisasContext *s, uint32_t insn, |
3036 | int opc, | |
3037 | int size, | |
3038 | int rt, | |
3039 | bool is_vector) | |
a5e94a9d | 3040 | { |
a5e94a9d AB |
3041 | int rn = extract32(insn, 5, 5); |
3042 | int imm9 = sextract32(insn, 12, 9); | |
a5e94a9d AB |
3043 | int idx = extract32(insn, 10, 2); |
3044 | bool is_signed = false; | |
3045 | bool is_store = false; | |
3046 | bool is_extended = false; | |
60510aed | 3047 | bool is_unpriv = (idx == 2); |
aaa1f954 | 3048 | bool iss_valid = !is_vector; |
a5e94a9d AB |
3049 | bool post_index; |
3050 | bool writeback; | |
0a405be2 | 3051 | int memidx; |
a5e94a9d | 3052 | |
3a471103 | 3053 | TCGv_i64 clean_addr, dirty_addr; |
a5e94a9d AB |
3054 | |
3055 | if (is_vector) { | |
3056 | size |= (opc & 2) << 1; | |
60510aed | 3057 | if (size > 4 || is_unpriv) { |
a5e94a9d AB |
3058 | unallocated_encoding(s); |
3059 | return; | |
3060 | } | |
3061 | is_store = ((opc & 1) == 0); | |
8c6afa6a PM |
3062 | if (!fp_access_check(s)) { |
3063 | return; | |
3064 | } | |
a5e94a9d AB |
3065 | } else { |
3066 | if (size == 3 && opc == 2) { | |
3067 | /* PRFM - prefetch */ | |
a80c4256 | 3068 | if (idx != 0) { |
60510aed PM |
3069 | unallocated_encoding(s); |
3070 | return; | |
3071 | } | |
a5e94a9d AB |
3072 | return; |
3073 | } | |
3074 | if (opc == 3 && size > 1) { | |
3075 | unallocated_encoding(s); | |
3076 | return; | |
3077 | } | |
3078 | is_store = (opc == 0); | |
026a19c3 EI |
3079 | is_signed = extract32(opc, 1, 1); |
3080 | is_extended = (size < 3) && extract32(opc, 0, 1); | |
a5e94a9d AB |
3081 | } |
3082 | ||
3083 | switch (idx) { | |
3084 | case 0: | |
60510aed | 3085 | case 2: |
a5e94a9d AB |
3086 | post_index = false; |
3087 | writeback = false; | |
3088 | break; | |
3089 | case 1: | |
3090 | post_index = true; | |
3091 | writeback = true; | |
3092 | break; | |
3093 | case 3: | |
3094 | post_index = false; | |
3095 | writeback = true; | |
3096 | break; | |
5ca66278 EC |
3097 | default: |
3098 | g_assert_not_reached(); | |
a5e94a9d AB |
3099 | } |
3100 | ||
3101 | if (rn == 31) { | |
3102 | gen_check_sp_alignment(s); | |
3103 | } | |
a5e94a9d | 3104 | |
3a471103 | 3105 | dirty_addr = read_cpu_reg_sp(s, rn, 1); |
a5e94a9d | 3106 | if (!post_index) { |
3a471103 | 3107 | tcg_gen_addi_i64(dirty_addr, dirty_addr, imm9); |
a5e94a9d | 3108 | } |
0a405be2 RH |
3109 | |
3110 | memidx = is_unpriv ? get_a64_user_mem_index(s) : get_mem_index(s); | |
3111 | clean_addr = gen_mte_check1_mmuidx(s, dirty_addr, is_store, | |
3112 | writeback || rn != 31, | |
3113 | size, is_unpriv, memidx); | |
a5e94a9d AB |
3114 | |
3115 | if (is_vector) { | |
3116 | if (is_store) { | |
3a471103 | 3117 | do_fp_st(s, rt, clean_addr, size); |
a5e94a9d | 3118 | } else { |
3a471103 | 3119 | do_fp_ld(s, rt, clean_addr, size); |
a5e94a9d AB |
3120 | } |
3121 | } else { | |
3122 | TCGv_i64 tcg_rt = cpu_reg(s, rt); | |
aaa1f954 | 3123 | bool iss_sf = disas_ldst_compute_iss_sf(size, is_signed, opc); |
60510aed | 3124 | |
a5e94a9d | 3125 | if (is_store) { |
3a471103 | 3126 | do_gpr_st_memidx(s, tcg_rt, clean_addr, size, memidx, |
aaa1f954 | 3127 | iss_valid, rt, iss_sf, false); |
a5e94a9d | 3128 | } else { |
3a471103 | 3129 | do_gpr_ld_memidx(s, tcg_rt, clean_addr, size, |
aaa1f954 EI |
3130 | is_signed, is_extended, memidx, |
3131 | iss_valid, rt, iss_sf, false); | |
a5e94a9d AB |
3132 | } |
3133 | } | |
3134 | ||
3135 | if (writeback) { | |
3136 | TCGv_i64 tcg_rn = cpu_reg_sp(s, rn); | |
3137 | if (post_index) { | |
3a471103 | 3138 | tcg_gen_addi_i64(dirty_addr, dirty_addr, imm9); |
a5e94a9d | 3139 | } |
3a471103 | 3140 | tcg_gen_mov_i64(tcg_rn, dirty_addr); |
a5e94a9d AB |
3141 | } |
3142 | } | |
3143 | ||
229b7a05 | 3144 | /* |
4ce31af4 | 3145 | * Load/store (register offset) |
229b7a05 AB |
3146 | * |
3147 | * 31 30 29 27 26 25 24 23 22 21 20 16 15 13 12 11 10 9 5 4 0 | |
3148 | * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+ | |
3149 | * |size| 1 1 1 | V | 0 0 | opc | 1 | Rm | opt | S| 1 0 | Rn | Rt | | |
3150 | * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+ | |
3151 | * | |
3152 | * For non-vector: | |
3153 | * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit | |
3154 | * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32 | |
3155 | * For vector: | |
3156 | * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated | |
3157 | * opc<0>: 0 -> store, 1 -> load | |
3158 | * V: 1 -> vector/simd | |
3159 | * opt: extend encoding (see DecodeRegExtend) | |
3160 | * S: if S=1 then scale (essentially index by sizeof(size)) | |
3161 | * Rt: register to transfer into/out of | |
3162 | * Rn: address register or SP for base | |
3163 | * Rm: offset register or ZR for offset | |
3164 | */ | |
cd694521 EI |
3165 | static void disas_ldst_reg_roffset(DisasContext *s, uint32_t insn, |
3166 | int opc, | |
3167 | int size, | |
3168 | int rt, | |
3169 | bool is_vector) | |
229b7a05 | 3170 | { |
229b7a05 AB |
3171 | int rn = extract32(insn, 5, 5); |
3172 | int shift = extract32(insn, 12, 1); | |
3173 | int rm = extract32(insn, 16, 5); | |
229b7a05 | 3174 | int opt = extract32(insn, 13, 3); |
229b7a05 AB |
3175 | bool is_signed = false; |
3176 | bool is_store = false; | |
3177 | bool is_extended = false; | |
229b7a05 | 3178 | |
3a471103 | 3179 | TCGv_i64 tcg_rm, clean_addr, dirty_addr; |
229b7a05 AB |
3180 | |
3181 | if (extract32(opt, 1, 1) == 0) { | |
3182 | unallocated_encoding(s); | |
3183 | return; | |
3184 | } | |
3185 | ||
3186 | if (is_vector) { | |
3187 | size |= (opc & 2) << 1; | |
3188 | if (size > 4) { | |
3189 | unallocated_encoding(s); | |
3190 | return; | |
3191 | } | |
3192 | is_store = !extract32(opc, 0, 1); | |
8c6afa6a PM |
3193 | if (!fp_access_check(s)) { |
3194 | return; | |
3195 | } | |
229b7a05 AB |
3196 | } else { |
3197 | if (size == 3 && opc == 2) { | |
3198 | /* PRFM - prefetch */ | |
3199 | return; | |
3200 | } | |
3201 | if (opc == 3 && size > 1) { | |
3202 | unallocated_encoding(s); | |
3203 | return; | |
3204 | } | |
3205 | is_store = (opc == 0); | |
3206 | is_signed = extract32(opc, 1, 1); | |
3207 | is_extended = (size < 3) && extract32(opc, 0, 1); | |
3208 | } | |
3209 | ||
3210 | if (rn == 31) { | |
3211 | gen_check_sp_alignment(s); | |
3212 | } | |
3a471103 | 3213 | dirty_addr = read_cpu_reg_sp(s, rn, 1); |
229b7a05 AB |
3214 | |
3215 | tcg_rm = read_cpu_reg(s, rm, 1); | |
3216 | ext_and_shift_reg(tcg_rm, tcg_rm, opt, shift ? size : 0); | |
3217 | ||
3a471103 | 3218 | tcg_gen_add_i64(dirty_addr, dirty_addr, tcg_rm); |
0a405be2 | 3219 | clean_addr = gen_mte_check1(s, dirty_addr, is_store, true, size); |
229b7a05 AB |
3220 | |
3221 | if (is_vector) { | |
3222 | if (is_store) { | |
3a471103 | 3223 | do_fp_st(s, rt, clean_addr, size); |
229b7a05 | 3224 | } else { |
3a471103 | 3225 | do_fp_ld(s, rt, clean_addr, size); |
229b7a05 AB |
3226 | } |
3227 | } else { | |
3228 | TCGv_i64 tcg_rt = cpu_reg(s, rt); | |
aaa1f954 | 3229 | bool iss_sf = disas_ldst_compute_iss_sf(size, is_signed, opc); |
229b7a05 | 3230 | if (is_store) { |
3a471103 | 3231 | do_gpr_st(s, tcg_rt, clean_addr, size, |
aaa1f954 | 3232 | true, rt, iss_sf, false); |
229b7a05 | 3233 | } else { |
3a471103 | 3234 | do_gpr_ld(s, tcg_rt, clean_addr, size, |
aaa1f954 EI |
3235 | is_signed, is_extended, |
3236 | true, rt, iss_sf, false); | |
229b7a05 AB |
3237 | } |
3238 | } | |
3239 | } | |
3240 | ||
d5612f10 | 3241 | /* |
4ce31af4 | 3242 | * Load/store (unsigned immediate) |
d5612f10 AB |
3243 | * |
3244 | * 31 30 29 27 26 25 24 23 22 21 10 9 5 | |
3245 | * +----+-------+---+-----+-----+------------+-------+------+ | |
3246 | * |size| 1 1 1 | V | 0 1 | opc | imm12 | Rn | Rt | | |
3247 | * +----+-------+---+-----+-----+------------+-------+------+ | |
3248 | * | |
3249 | * For non-vector: | |
3250 | * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit | |
3251 | * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32 | |
3252 | * For vector: | |
3253 | * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated | |
3254 | * opc<0>: 0 -> store, 1 -> load | |
3255 | * Rn: base address register (inc SP) | |
3256 | * Rt: target register | |
3257 | */ | |
cd694521 EI |
3258 | static void disas_ldst_reg_unsigned_imm(DisasContext *s, uint32_t insn, |
3259 | int opc, | |
3260 | int size, | |
3261 | int rt, | |
3262 | bool is_vector) | |
d5612f10 | 3263 | { |
d5612f10 AB |
3264 | int rn = extract32(insn, 5, 5); |
3265 | unsigned int imm12 = extract32(insn, 10, 12); | |
d5612f10 AB |
3266 | unsigned int offset; |
3267 | ||
3a471103 | 3268 | TCGv_i64 clean_addr, dirty_addr; |
d5612f10 AB |
3269 | |
3270 | bool is_store; | |
3271 | bool is_signed = false; | |
3272 | bool is_extended = false; | |
3273 | ||
3274 | if (is_vector) { | |
3275 | size |= (opc & 2) << 1; | |
3276 | if (size > 4) { | |
3277 | unallocated_encoding(s); | |
3278 | return; | |
3279 | } | |
3280 | is_store = !extract32(opc, 0, 1); | |
8c6afa6a PM |
3281 | if (!fp_access_check(s)) { |
3282 | return; | |
3283 | } | |
d5612f10 AB |
3284 | } else { |
3285 | if (size == 3 && opc == 2) { | |
3286 | /* PRFM - prefetch */ | |
3287 | return; | |
3288 | } | |
3289 | if (opc == 3 && size > 1) { | |
3290 | unallocated_encoding(s); | |
3291 | return; | |
3292 | } | |
3293 | is_store = (opc == 0); | |
3294 | is_signed = extract32(opc, 1, 1); | |
3295 | is_extended = (size < 3) && extract32(opc, 0, 1); | |
3296 | } | |
3297 | ||
3298 | if (rn == 31) { | |
3299 | gen_check_sp_alignment(s); | |
3300 | } | |
3a471103 | 3301 | dirty_addr = read_cpu_reg_sp(s, rn, 1); |
d5612f10 | 3302 | offset = imm12 << size; |
3a471103 | 3303 | tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); |
0a405be2 | 3304 | clean_addr = gen_mte_check1(s, dirty_addr, is_store, rn != 31, size); |
d5612f10 AB |
3305 | |
3306 | if (is_vector) { | |
3307 | if (is_store) { | |
3a471103 | 3308 | do_fp_st(s, rt, clean_addr, size); |
d5612f10 | 3309 | } else { |
3a471103 | 3310 | do_fp_ld(s, rt, clean_addr, size); |
d5612f10 AB |
3311 | } |
3312 | } else { | |
3313 | TCGv_i64 tcg_rt = cpu_reg(s, rt); | |
aaa1f954 | 3314 | bool iss_sf = disas_ldst_compute_iss_sf(size, is_signed, opc); |
d5612f10 | 3315 | if (is_store) { |
3a471103 | 3316 | do_gpr_st(s, tcg_rt, clean_addr, size, |
aaa1f954 | 3317 | true, rt, iss_sf, false); |
d5612f10 | 3318 | } else { |
3a471103 | 3319 | do_gpr_ld(s, tcg_rt, clean_addr, size, is_signed, is_extended, |
aaa1f954 | 3320 | true, rt, iss_sf, false); |
d5612f10 AB |
3321 | } |
3322 | } | |
3323 | } | |
3324 | ||
68412d2e RH |
3325 | /* Atomic memory operations |
3326 | * | |
3327 | * 31 30 27 26 24 22 21 16 15 12 10 5 0 | |
3328 | * +------+-------+---+-----+-----+---+----+----+-----+-----+----+-----+ | |
3329 | * | size | 1 1 1 | V | 0 0 | A R | 1 | Rs | o3 | opc | 0 0 | Rn | Rt | | |
3330 | * +------+-------+---+-----+-----+--------+----+-----+-----+----+-----+ | |
3331 | * | |
3332 | * Rt: the result register | |
3333 | * Rn: base address or SP | |
3334 | * Rs: the source register for the operation | |
3335 | * V: vector flag (always 0 as of v8.3) | |
3336 | * A: acquire flag | |
3337 | * R: release flag | |
3338 | */ | |
3339 | static void disas_ldst_atomic(DisasContext *s, uint32_t insn, | |
3340 | int size, int rt, bool is_vector) | |
3341 | { | |
3342 | int rs = extract32(insn, 16, 5); | |
3343 | int rn = extract32(insn, 5, 5); | |
3344 | int o3_opc = extract32(insn, 12, 4); | |
2677cf9f PM |
3345 | bool r = extract32(insn, 22, 1); |
3346 | bool a = extract32(insn, 23, 1); | |
3a471103 | 3347 | TCGv_i64 tcg_rs, clean_addr; |
88a90e3d | 3348 | AtomicThreeOpFn *fn = NULL; |
68412d2e | 3349 | |
962fcbf2 | 3350 | if (is_vector || !dc_isar_feature(aa64_atomics, s)) { |
68412d2e RH |
3351 | unallocated_encoding(s); |
3352 | return; | |
3353 | } | |
3354 | switch (o3_opc) { | |
3355 | case 000: /* LDADD */ | |
74608ea4 RH |
3356 | fn = tcg_gen_atomic_fetch_add_i64; |
3357 | break; | |
68412d2e | 3358 | case 001: /* LDCLR */ |
74608ea4 RH |
3359 | fn = tcg_gen_atomic_fetch_and_i64; |
3360 | break; | |
68412d2e | 3361 | case 002: /* LDEOR */ |
74608ea4 RH |
3362 | fn = tcg_gen_atomic_fetch_xor_i64; |
3363 | break; | |
68412d2e | 3364 | case 003: /* LDSET */ |
74608ea4 RH |
3365 | fn = tcg_gen_atomic_fetch_or_i64; |
3366 | break; | |
68412d2e | 3367 | case 004: /* LDSMAX */ |
74608ea4 RH |
3368 | fn = tcg_gen_atomic_fetch_smax_i64; |
3369 | break; | |
68412d2e | 3370 | case 005: /* LDSMIN */ |
74608ea4 RH |
3371 | fn = tcg_gen_atomic_fetch_smin_i64; |
3372 | break; | |
68412d2e | 3373 | case 006: /* LDUMAX */ |
74608ea4 RH |
3374 | fn = tcg_gen_atomic_fetch_umax_i64; |
3375 | break; | |
68412d2e | 3376 | case 007: /* LDUMIN */ |
74608ea4 RH |
3377 | fn = tcg_gen_atomic_fetch_umin_i64; |
3378 | break; | |
68412d2e | 3379 | case 010: /* SWP */ |
74608ea4 RH |
3380 | fn = tcg_gen_atomic_xchg_i64; |
3381 | break; | |
2677cf9f PM |
3382 | case 014: /* LDAPR, LDAPRH, LDAPRB */ |
3383 | if (!dc_isar_feature(aa64_rcpc_8_3, s) || | |
3384 | rs != 31 || a != 1 || r != 0) { | |
3385 | unallocated_encoding(s); | |
3386 | return; | |
3387 | } | |
3388 | break; | |
68412d2e RH |
3389 | default: |
3390 | unallocated_encoding(s); | |
3391 | return; | |
3392 | } | |
68412d2e | 3393 | |
74608ea4 RH |
3394 | if (rn == 31) { |
3395 | gen_check_sp_alignment(s); | |
3396 | } | |
0a405be2 | 3397 | clean_addr = gen_mte_check1(s, cpu_reg_sp(s, rn), false, rn != 31, size); |
2677cf9f PM |
3398 | |
3399 | if (o3_opc == 014) { | |
3400 | /* | |
3401 | * LDAPR* are a special case because they are a simple load, not a | |
3402 | * fetch-and-do-something op. | |
3403 | * The architectural consistency requirements here are weaker than | |
3404 | * full load-acquire (we only need "load-acquire processor consistent"), | |
3405 | * but we choose to implement them as full LDAQ. | |
3406 | */ | |
3407 | do_gpr_ld(s, cpu_reg(s, rt), clean_addr, size, false, false, | |
3408 | true, rt, disas_ldst_compute_iss_sf(size, false, 0), true); | |
3409 | tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); | |
3410 | return; | |
3411 | } | |
3412 | ||
74608ea4 RH |
3413 | tcg_rs = read_cpu_reg(s, rs, true); |
3414 | ||
3415 | if (o3_opc == 1) { /* LDCLR */ | |
3416 | tcg_gen_not_i64(tcg_rs, tcg_rs); | |
3417 | } | |
3418 | ||
3419 | /* The tcg atomic primitives are all full barriers. Therefore we | |
3420 | * can ignore the Acquire and Release bits of this instruction. | |
3421 | */ | |
3a471103 | 3422 | fn(cpu_reg(s, rt), clean_addr, tcg_rs, get_mem_index(s), |
74608ea4 | 3423 | s->be_data | size | MO_ALIGN); |
68412d2e RH |
3424 | } |
3425 | ||
bd889f48 RH |
3426 | /* |
3427 | * PAC memory operations | |
3428 | * | |
3429 | * 31 30 27 26 24 22 21 12 11 10 5 0 | |
3430 | * +------+-------+---+-----+-----+---+--------+---+---+----+-----+ | |
3431 | * | size | 1 1 1 | V | 0 0 | M S | 1 | imm9 | W | 1 | Rn | Rt | | |
3432 | * +------+-------+---+-----+-----+---+--------+---+---+----+-----+ | |
3433 | * | |
3434 | * Rt: the result register | |
3435 | * Rn: base address or SP | |
3436 | * V: vector flag (always 0 as of v8.3) | |
3437 | * M: clear for key DA, set for key DB | |
3438 | * W: pre-indexing flag | |
3439 | * S: sign for imm9. | |
3440 | */ | |
3441 | static void disas_ldst_pac(DisasContext *s, uint32_t insn, | |
3442 | int size, int rt, bool is_vector) | |
3443 | { | |
3444 | int rn = extract32(insn, 5, 5); | |
3445 | bool is_wback = extract32(insn, 11, 1); | |
3446 | bool use_key_a = !extract32(insn, 23, 1); | |
3447 | int offset; | |
3a471103 | 3448 | TCGv_i64 clean_addr, dirty_addr, tcg_rt; |
bd889f48 RH |
3449 | |
3450 | if (size != 3 || is_vector || !dc_isar_feature(aa64_pauth, s)) { | |
3451 | unallocated_encoding(s); | |
3452 | return; | |
3453 | } | |
3454 | ||
3455 | if (rn == 31) { | |
3456 | gen_check_sp_alignment(s); | |
3457 | } | |
3a471103 | 3458 | dirty_addr = read_cpu_reg_sp(s, rn, 1); |
bd889f48 RH |
3459 | |
3460 | if (s->pauth_active) { | |
3461 | if (use_key_a) { | |
d250bb19 PC |
3462 | gen_helper_autda(dirty_addr, cpu_env, dirty_addr, |
3463 | new_tmp_a64_zero(s)); | |
bd889f48 | 3464 | } else { |
d250bb19 PC |
3465 | gen_helper_autdb(dirty_addr, cpu_env, dirty_addr, |
3466 | new_tmp_a64_zero(s)); | |
bd889f48 RH |
3467 | } |
3468 | } | |
3469 | ||
3470 | /* Form the 10-bit signed, scaled offset. */ | |
3471 | offset = (extract32(insn, 22, 1) << 9) | extract32(insn, 12, 9); | |
3472 | offset = sextract32(offset << size, 0, 10 + size); | |
3a471103 | 3473 | tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); |
bd889f48 | 3474 | |
3a471103 | 3475 | /* Note that "clean" and "dirty" here refer to TBI not PAC. */ |
0a405be2 RH |
3476 | clean_addr = gen_mte_check1(s, dirty_addr, false, |
3477 | is_wback || rn != 31, size); | |
bd889f48 | 3478 | |
3a471103 RH |
3479 | tcg_rt = cpu_reg(s, rt); |
3480 | do_gpr_ld(s, tcg_rt, clean_addr, size, /* is_signed */ false, | |
bd889f48 RH |
3481 | /* extend */ false, /* iss_valid */ !is_wback, |
3482 | /* iss_srt */ rt, /* iss_sf */ true, /* iss_ar */ false); | |
3483 | ||
3484 | if (is_wback) { | |
3a471103 | 3485 | tcg_gen_mov_i64(cpu_reg_sp(s, rn), dirty_addr); |
bd889f48 RH |
3486 | } |
3487 | } | |
3488 | ||
a1229109 PM |
3489 | /* |
3490 | * LDAPR/STLR (unscaled immediate) | |
3491 | * | |
3492 | * 31 30 24 22 21 12 10 5 0 | |
3493 | * +------+-------------+-----+---+--------+-----+----+-----+ | |
3494 | * | size | 0 1 1 0 0 1 | opc | 0 | imm9 | 0 0 | Rn | Rt | | |
3495 | * +------+-------------+-----+---+--------+-----+----+-----+ | |
3496 | * | |
3497 | * Rt: source or destination register | |
3498 | * Rn: base register | |
3499 | * imm9: unscaled immediate offset | |
3500 | * opc: 00: STLUR*, 01/10/11: various LDAPUR* | |
3501 | * size: size of load/store | |
3502 | */ | |
3503 | static void disas_ldst_ldapr_stlr(DisasContext *s, uint32_t insn) | |
3504 | { | |
3505 | int rt = extract32(insn, 0, 5); | |
3506 | int rn = extract32(insn, 5, 5); | |
3507 | int offset = sextract32(insn, 12, 9); | |
3508 | int opc = extract32(insn, 22, 2); | |
3509 | int size = extract32(insn, 30, 2); | |
3510 | TCGv_i64 clean_addr, dirty_addr; | |
3511 | bool is_store = false; | |
3512 | bool is_signed = false; | |
3513 | bool extend = false; | |
3514 | bool iss_sf; | |
3515 | ||
3516 | if (!dc_isar_feature(aa64_rcpc_8_4, s)) { | |
3517 | unallocated_encoding(s); | |
3518 | return; | |
3519 | } | |
3520 | ||
3521 | switch (opc) { | |
3522 | case 0: /* STLURB */ | |
3523 | is_store = true; | |
3524 | break; | |
3525 | case 1: /* LDAPUR* */ | |
3526 | break; | |
3527 | case 2: /* LDAPURS* 64-bit variant */ | |
3528 | if (size == 3) { | |
3529 | unallocated_encoding(s); | |
3530 | return; | |
3531 | } | |
3532 | is_signed = true; | |
3533 | break; | |
3534 | case 3: /* LDAPURS* 32-bit variant */ | |
3535 | if (size > 1) { | |
3536 | unallocated_encoding(s); | |
3537 | return; | |
3538 | } | |
3539 | is_signed = true; | |
3540 | extend = true; /* zero-extend 32->64 after signed load */ | |
3541 | break; | |
3542 | default: | |
3543 | g_assert_not_reached(); | |
3544 | } | |
3545 | ||
3546 | iss_sf = disas_ldst_compute_iss_sf(size, is_signed, opc); | |
3547 | ||
3548 | if (rn == 31) { | |
3549 | gen_check_sp_alignment(s); | |
3550 | } | |
3551 | ||
3552 | dirty_addr = read_cpu_reg_sp(s, rn, 1); | |
3553 | tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); | |
3554 | clean_addr = clean_data_tbi(s, dirty_addr); | |
3555 | ||
3556 | if (is_store) { | |
3557 | /* Store-Release semantics */ | |
3558 | tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); | |
3559 | do_gpr_st(s, cpu_reg(s, rt), clean_addr, size, true, rt, iss_sf, true); | |
3560 | } else { | |
3561 | /* | |
3562 | * Load-AcquirePC semantics; we implement as the slightly more | |
3563 | * restrictive Load-Acquire. | |
3564 | */ | |
3565 | do_gpr_ld(s, cpu_reg(s, rt), clean_addr, size, is_signed, extend, | |
3566 | true, rt, iss_sf, true); | |
3567 | tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); | |
3568 | } | |
3569 | } | |
3570 | ||
ad7ee8a2 CF |
3571 | /* Load/store register (all forms) */ |
3572 | static void disas_ldst_reg(DisasContext *s, uint32_t insn) | |
3573 | { | |
cd694521 EI |
3574 | int rt = extract32(insn, 0, 5); |
3575 | int opc = extract32(insn, 22, 2); | |
3576 | bool is_vector = extract32(insn, 26, 1); | |
3577 | int size = extract32(insn, 30, 2); | |
3578 | ||
d5612f10 AB |
3579 | switch (extract32(insn, 24, 2)) { |
3580 | case 0: | |
68412d2e | 3581 | if (extract32(insn, 21, 1) == 0) { |
60510aed PM |
3582 | /* Load/store register (unscaled immediate) |
3583 | * Load/store immediate pre/post-indexed | |
3584 | * Load/store register unprivileged | |
3585 | */ | |
cd694521 | 3586 | disas_ldst_reg_imm9(s, insn, opc, size, rt, is_vector); |
68412d2e RH |
3587 | return; |
3588 | } | |
3589 | switch (extract32(insn, 10, 2)) { | |
3590 | case 0: | |
3591 | disas_ldst_atomic(s, insn, size, rt, is_vector); | |
3592 | return; | |
3593 | case 2: | |
3594 | disas_ldst_reg_roffset(s, insn, opc, size, rt, is_vector); | |
3595 | return; | |
bd889f48 RH |
3596 | default: |
3597 | disas_ldst_pac(s, insn, size, rt, is_vector); | |
3598 | return; | |
229b7a05 | 3599 | } |
d5612f10 AB |
3600 | break; |
3601 | case 1: | |
cd694521 | 3602 | disas_ldst_reg_unsigned_imm(s, insn, opc, size, rt, is_vector); |
68412d2e | 3603 | return; |
d5612f10 | 3604 | } |
68412d2e | 3605 | unallocated_encoding(s); |
ad7ee8a2 CF |
3606 | } |
3607 | ||
4ce31af4 | 3608 | /* AdvSIMD load/store multiple structures |
72430bf5 AB |
3609 | * |
3610 | * 31 30 29 23 22 21 16 15 12 11 10 9 5 4 0 | |
3611 | * +---+---+---------------+---+-------------+--------+------+------+------+ | |
3612 | * | 0 | Q | 0 0 1 1 0 0 0 | L | 0 0 0 0 0 0 | opcode | size | Rn | Rt | | |
3613 | * +---+---+---------------+---+-------------+--------+------+------+------+ | |
3614 | * | |
4ce31af4 | 3615 | * AdvSIMD load/store multiple structures (post-indexed) |
72430bf5 AB |
3616 | * |
3617 | * 31 30 29 23 22 21 20 16 15 12 11 10 9 5 4 0 | |
3618 | * +---+---+---------------+---+---+---------+--------+------+------+------+ | |
3619 | * | 0 | Q | 0 0 1 1 0 0 1 | L | 0 | Rm | opcode | size | Rn | Rt | | |
3620 | * +---+---+---------------+---+---+---------+--------+------+------+------+ | |
3621 | * | |
3622 | * Rt: first (or only) SIMD&FP register to be transferred | |
3623 | * Rn: base address or SP | |
3624 | * Rm (post-index only): post-index register (when !31) or size dependent #imm | |
3625 | */ | |
ad7ee8a2 CF |
3626 | static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn) |
3627 | { | |
72430bf5 AB |
3628 | int rt = extract32(insn, 0, 5); |
3629 | int rn = extract32(insn, 5, 5); | |
e1f22081 | 3630 | int rm = extract32(insn, 16, 5); |
72430bf5 AB |
3631 | int size = extract32(insn, 10, 2); |
3632 | int opcode = extract32(insn, 12, 4); | |
3633 | bool is_store = !extract32(insn, 22, 1); | |
3634 | bool is_postidx = extract32(insn, 23, 1); | |
3635 | bool is_q = extract32(insn, 30, 1); | |
3a471103 | 3636 | TCGv_i64 clean_addr, tcg_rn, tcg_ebytes; |
14776ab5 | 3637 | MemOp endian = s->be_data; |
72430bf5 | 3638 | |
73ceeb00 | 3639 | int total; /* total bytes */ |
87f9a7f0 | 3640 | int elements; /* elements per vector */ |
72430bf5 AB |
3641 | int rpt; /* num iterations */ |
3642 | int selem; /* structure elements */ | |
3643 | int r; | |
3644 | ||
3645 | if (extract32(insn, 31, 1) || extract32(insn, 21, 1)) { | |
3646 | unallocated_encoding(s); | |
3647 | return; | |
3648 | } | |
3649 | ||
e1f22081 PM |
3650 | if (!is_postidx && rm != 0) { |
3651 | unallocated_encoding(s); | |
3652 | return; | |
3653 | } | |
3654 | ||
72430bf5 AB |
3655 | /* From the shared decode logic */ |
3656 | switch (opcode) { | |
3657 | case 0x0: | |
3658 | rpt = 1; | |
3659 | selem = 4; | |
3660 | break; | |
3661 | case 0x2: | |
3662 | rpt = 4; | |
3663 | selem = 1; | |
3664 | break; | |
3665 | case 0x4: | |
3666 | rpt = 1; | |
3667 | selem = 3; | |
3668 | break; | |
3669 | case 0x6: | |
3670 | rpt = 3; | |
3671 | selem = 1; | |
3672 | break; | |
3673 | case 0x7: | |
3674 | rpt = 1; | |
3675 | selem = 1; | |
3676 | break; | |
3677 | case 0x8: | |
3678 | rpt = 1; | |
3679 | selem = 2; | |
3680 | break; | |
3681 | case 0xa: | |
3682 | rpt = 2; | |
3683 | selem = 1; | |
3684 | break; | |
3685 | default: | |
3686 | unallocated_encoding(s); | |
3687 | return; | |
3688 | } | |
3689 | ||
3690 | if (size == 3 && !is_q && selem != 1) { | |
3691 | /* reserved */ | |
3692 | unallocated_encoding(s); | |
3693 | return; | |
3694 | } | |
3695 | ||
8c6afa6a PM |
3696 | if (!fp_access_check(s)) { |
3697 | return; | |
3698 | } | |
3699 | ||
72430bf5 AB |
3700 | if (rn == 31) { |
3701 | gen_check_sp_alignment(s); | |
3702 | } | |
3703 | ||
87f9a7f0 RH |
3704 | /* For our purposes, bytes are always little-endian. */ |
3705 | if (size == 0) { | |
3706 | endian = MO_LE; | |
3707 | } | |
3708 | ||
73ceeb00 RH |
3709 | total = rpt * selem * (is_q ? 16 : 8); |
3710 | tcg_rn = cpu_reg_sp(s, rn); | |
3711 | ||
3712 | /* | |
3713 | * Issue the MTE check vs the logical repeat count, before we | |
3714 | * promote consecutive little-endian elements below. | |
3715 | */ | |
3716 | clean_addr = gen_mte_checkN(s, tcg_rn, is_store, is_postidx || rn != 31, | |
3717 | size, total); | |
3718 | ||
3719 | /* | |
3720 | * Consecutive little-endian elements from a single register | |
87f9a7f0 RH |
3721 | * can be promoted to a larger little-endian operation. |
3722 | */ | |
3723 | if (selem == 1 && endian == MO_LE) { | |
3724 | size = 3; | |
3725 | } | |
73ceeb00 | 3726 | elements = (is_q ? 16 : 8) >> size; |
72430bf5 | 3727 | |
73ceeb00 | 3728 | tcg_ebytes = tcg_const_i64(1 << size); |
72430bf5 AB |
3729 | for (r = 0; r < rpt; r++) { |
3730 | int e; | |
3731 | for (e = 0; e < elements; e++) { | |
72430bf5 AB |
3732 | int xs; |
3733 | for (xs = 0; xs < selem; xs++) { | |
87f9a7f0 | 3734 | int tt = (rt + r + xs) % 32; |
72430bf5 | 3735 | if (is_store) { |
3a471103 | 3736 | do_vec_st(s, tt, e, clean_addr, size, endian); |
72430bf5 | 3737 | } else { |
3a471103 | 3738 | do_vec_ld(s, tt, e, clean_addr, size, endian); |
72430bf5 | 3739 | } |
3a471103 | 3740 | tcg_gen_add_i64(clean_addr, clean_addr, tcg_ebytes); |
72430bf5 AB |
3741 | } |
3742 | } | |
3743 | } | |
3a471103 | 3744 | tcg_temp_free_i64(tcg_ebytes); |
72430bf5 | 3745 | |
87f9a7f0 RH |
3746 | if (!is_store) { |
3747 | /* For non-quad operations, setting a slice of the low | |
3748 | * 64 bits of the register clears the high 64 bits (in | |
3749 | * the ARM ARM pseudocode this is implicit in the fact | |
3750 | * that 'rval' is a 64 bit wide variable). | |
3751 | * For quad operations, we might still need to zero the | |
3752 | * high bits of SVE. | |
3753 | */ | |
3754 | for (r = 0; r < rpt * selem; r++) { | |
3755 | int tt = (rt + r) % 32; | |
3756 | clear_vec_high(s, is_q, tt); | |
3757 | } | |
3758 | } | |
3759 | ||
72430bf5 | 3760 | if (is_postidx) { |
72430bf5 | 3761 | if (rm == 31) { |
73ceeb00 | 3762 | tcg_gen_addi_i64(tcg_rn, tcg_rn, total); |
72430bf5 AB |
3763 | } else { |
3764 | tcg_gen_add_i64(tcg_rn, tcg_rn, cpu_reg(s, rm)); | |
3765 | } | |
3766 | } | |
ad7ee8a2 CF |
3767 | } |
3768 | ||
4ce31af4 | 3769 | /* AdvSIMD load/store single structure |
df54e47d PM |
3770 | * |
3771 | * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0 | |
3772 | * +---+---+---------------+-----+-----------+-----+---+------+------+------+ | |
3773 | * | 0 | Q | 0 0 1 1 0 1 0 | L R | 0 0 0 0 0 | opc | S | size | Rn | Rt | | |
3774 | * +---+---+---------------+-----+-----------+-----+---+------+------+------+ | |
3775 | * | |
4ce31af4 | 3776 | * AdvSIMD load/store single structure (post-indexed) |
df54e47d PM |
3777 | * |
3778 | * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0 | |
3779 | * +---+---+---------------+-----+-----------+-----+---+------+------+------+ | |
3780 | * | 0 | Q | 0 0 1 1 0 1 1 | L R | Rm | opc | S | size | Rn | Rt | | |
3781 | * +---+---+---------------+-----+-----------+-----+---+------+------+------+ | |
3782 | * | |
3783 | * Rt: first (or only) SIMD&FP register to be transferred | |
3784 | * Rn: base address or SP | |
3785 | * Rm (post-index only): post-index register (when !31) or size dependent #imm | |
3786 | * index = encoded in Q:S:size dependent on size | |
3787 | * | |
3788 | * lane_size = encoded in R, opc | |
3789 | * transfer width = encoded in opc, S, size | |
3790 | */ | |
ad7ee8a2 CF |
3791 | static void disas_ldst_single_struct(DisasContext *s, uint32_t insn) |
3792 | { | |
df54e47d PM |
3793 | int rt = extract32(insn, 0, 5); |
3794 | int rn = extract32(insn, 5, 5); | |
9c72b68a | 3795 | int rm = extract32(insn, 16, 5); |
df54e47d PM |
3796 | int size = extract32(insn, 10, 2); |
3797 | int S = extract32(insn, 12, 1); | |
3798 | int opc = extract32(insn, 13, 3); | |
3799 | int R = extract32(insn, 21, 1); | |
3800 | int is_load = extract32(insn, 22, 1); | |
3801 | int is_postidx = extract32(insn, 23, 1); | |
3802 | int is_q = extract32(insn, 30, 1); | |
3803 | ||
3804 | int scale = extract32(opc, 1, 2); | |
3805 | int selem = (extract32(opc, 0, 1) << 1 | R) + 1; | |
3806 | bool replicate = false; | |
3807 | int index = is_q << 3 | S << 2 | size; | |
73ceeb00 | 3808 | int xs, total; |
3a471103 | 3809 | TCGv_i64 clean_addr, tcg_rn, tcg_ebytes; |
df54e47d | 3810 | |
9c72b68a PM |
3811 | if (extract32(insn, 31, 1)) { |
3812 | unallocated_encoding(s); | |
3813 | return; | |
3814 | } | |
3815 | if (!is_postidx && rm != 0) { | |
3816 | unallocated_encoding(s); | |
3817 | return; | |
3818 | } | |
3819 | ||
df54e47d PM |
3820 | switch (scale) { |
3821 | case 3: | |
3822 | if (!is_load || S) { | |
3823 | unallocated_encoding(s); | |
3824 | return; | |
3825 | } | |
3826 | scale = size; | |
3827 | replicate = true; | |
3828 | break; | |
3829 | case 0: | |
3830 | break; | |
3831 | case 1: | |
3832 | if (extract32(size, 0, 1)) { | |
3833 | unallocated_encoding(s); | |
3834 | return; | |
3835 | } | |
3836 | index >>= 1; | |
3837 | break; | |
3838 | case 2: | |
3839 | if (extract32(size, 1, 1)) { | |
3840 | unallocated_encoding(s); | |
3841 | return; | |
3842 | } | |
3843 | if (!extract32(size, 0, 1)) { | |
3844 | index >>= 2; | |
3845 | } else { | |
3846 | if (S) { | |
3847 | unallocated_encoding(s); | |
3848 | return; | |
3849 | } | |
3850 | index >>= 3; | |
3851 | scale = 3; | |
3852 | } | |
3853 | break; | |
3854 | default: | |
3855 | g_assert_not_reached(); | |
3856 | } | |
3857 | ||
8c6afa6a PM |
3858 | if (!fp_access_check(s)) { |
3859 | return; | |
3860 | } | |
3861 | ||
df54e47d PM |
3862 | if (rn == 31) { |
3863 | gen_check_sp_alignment(s); | |
3864 | } | |
3865 | ||
73ceeb00 | 3866 | total = selem << scale; |
df54e47d | 3867 | tcg_rn = cpu_reg_sp(s, rn); |
df54e47d | 3868 | |
73ceeb00 RH |
3869 | clean_addr = gen_mte_checkN(s, tcg_rn, !is_load, is_postidx || rn != 31, |
3870 | scale, total); | |
3871 | ||
3872 | tcg_ebytes = tcg_const_i64(1 << scale); | |
df54e47d PM |
3873 | for (xs = 0; xs < selem; xs++) { |
3874 | if (replicate) { | |
3875 | /* Load and replicate to all elements */ | |
df54e47d PM |
3876 | TCGv_i64 tcg_tmp = tcg_temp_new_i64(); |
3877 | ||
3a471103 | 3878 | tcg_gen_qemu_ld_i64(tcg_tmp, clean_addr, |
aa6489da | 3879 | get_mem_index(s), s->be_data + scale); |
10e0b33c RH |
3880 | tcg_gen_gvec_dup_i64(scale, vec_full_reg_offset(s, rt), |
3881 | (is_q + 1) * 8, vec_full_reg_size(s), | |
3882 | tcg_tmp); | |
df54e47d PM |
3883 | tcg_temp_free_i64(tcg_tmp); |
3884 | } else { | |
3885 | /* Load/store one element per register */ | |
3886 | if (is_load) { | |
3a471103 | 3887 | do_vec_ld(s, rt, index, clean_addr, scale, s->be_data); |
df54e47d | 3888 | } else { |
3a471103 | 3889 | do_vec_st(s, rt, index, clean_addr, scale, s->be_data); |
df54e47d PM |
3890 | } |
3891 | } | |
3a471103 | 3892 | tcg_gen_add_i64(clean_addr, clean_addr, tcg_ebytes); |
df54e47d PM |
3893 | rt = (rt + 1) % 32; |
3894 | } | |
3a471103 | 3895 | tcg_temp_free_i64(tcg_ebytes); |
df54e47d PM |
3896 | |
3897 | if (is_postidx) { | |
df54e47d | 3898 | if (rm == 31) { |
73ceeb00 | 3899 | tcg_gen_addi_i64(tcg_rn, tcg_rn, total); |
df54e47d PM |
3900 | } else { |
3901 | tcg_gen_add_i64(tcg_rn, tcg_rn, cpu_reg(s, rm)); | |
3902 | } | |
3903 | } | |
ad7ee8a2 CF |
3904 | } |
3905 | ||
c15294c1 RH |
3906 | /* |
3907 | * Load/Store memory tags | |
3908 | * | |
3909 | * 31 30 29 24 22 21 12 10 5 0 | |
3910 | * +-----+-------------+-----+---+------+-----+------+------+ | |
3911 | * | 1 1 | 0 1 1 0 0 1 | op1 | 1 | imm9 | op2 | Rn | Rt | | |
3912 | * +-----+-------------+-----+---+------+-----+------+------+ | |
3913 | */ | |
3914 | static void disas_ldst_tag(DisasContext *s, uint32_t insn) | |
3915 | { | |
3916 | int rt = extract32(insn, 0, 5); | |
3917 | int rn = extract32(insn, 5, 5); | |
3918 | uint64_t offset = sextract64(insn, 12, 9) << LOG2_TAG_GRANULE; | |
3919 | int op2 = extract32(insn, 10, 2); | |
3920 | int op1 = extract32(insn, 22, 2); | |
5f716a82 | 3921 | bool is_load = false, is_pair = false, is_zero = false, is_mult = false; |
c15294c1 RH |
3922 | int index = 0; |
3923 | TCGv_i64 addr, clean_addr, tcg_rt; | |
3924 | ||
3925 | /* We checked insn bits [29:24,21] in the caller. */ | |
3926 | if (extract32(insn, 30, 2) != 3) { | |
3927 | goto do_unallocated; | |
3928 | } | |
3929 | ||
3930 | /* | |
3931 | * @index is a tri-state variable which has 3 states: | |
3932 | * < 0 : post-index, writeback | |
3933 | * = 0 : signed offset | |
3934 | * > 0 : pre-index, writeback | |
3935 | */ | |
3936 | switch (op1) { | |
3937 | case 0: | |
3938 | if (op2 != 0) { | |
3939 | /* STG */ | |
3940 | index = op2 - 2; | |
5f716a82 RH |
3941 | } else { |
3942 | /* STZGM */ | |
3943 | if (s->current_el == 0 || offset != 0) { | |
3944 | goto do_unallocated; | |
3945 | } | |
3946 | is_mult = is_zero = true; | |
c15294c1 | 3947 | } |
5f716a82 | 3948 | break; |
c15294c1 RH |
3949 | case 1: |
3950 | if (op2 != 0) { | |
3951 | /* STZG */ | |
3952 | is_zero = true; | |
3953 | index = op2 - 2; | |
3954 | } else { | |
3955 | /* LDG */ | |
3956 | is_load = true; | |
3957 | } | |
3958 | break; | |
3959 | case 2: | |
3960 | if (op2 != 0) { | |
3961 | /* ST2G */ | |
3962 | is_pair = true; | |
3963 | index = op2 - 2; | |
5f716a82 RH |
3964 | } else { |
3965 | /* STGM */ | |
3966 | if (s->current_el == 0 || offset != 0) { | |
3967 | goto do_unallocated; | |
3968 | } | |
3969 | is_mult = true; | |
c15294c1 | 3970 | } |
5f716a82 | 3971 | break; |
c15294c1 RH |
3972 | case 3: |
3973 | if (op2 != 0) { | |
3974 | /* STZ2G */ | |
3975 | is_pair = is_zero = true; | |
3976 | index = op2 - 2; | |
5f716a82 RH |
3977 | } else { |
3978 | /* LDGM */ | |
3979 | if (s->current_el == 0 || offset != 0) { | |
3980 | goto do_unallocated; | |
3981 | } | |
3982 | is_mult = is_load = true; | |
c15294c1 | 3983 | } |
5f716a82 | 3984 | break; |
c15294c1 RH |
3985 | |
3986 | default: | |
3987 | do_unallocated: | |
3988 | unallocated_encoding(s); | |
3989 | return; | |
3990 | } | |
3991 | ||
5f716a82 RH |
3992 | if (is_mult |
3993 | ? !dc_isar_feature(aa64_mte, s) | |
3994 | : !dc_isar_feature(aa64_mte_insn_reg, s)) { | |
c15294c1 RH |
3995 | goto do_unallocated; |
3996 | } | |
3997 | ||
3998 | if (rn == 31) { | |
3999 | gen_check_sp_alignment(s); | |
4000 | } | |
4001 | ||
4002 | addr = read_cpu_reg_sp(s, rn, true); | |
4003 | if (index >= 0) { | |
4004 | /* pre-index or signed offset */ | |
4005 | tcg_gen_addi_i64(addr, addr, offset); | |
4006 | } | |
4007 | ||
5f716a82 RH |
4008 | if (is_mult) { |
4009 | tcg_rt = cpu_reg(s, rt); | |
4010 | ||
4011 | if (is_zero) { | |
4012 | int size = 4 << s->dcz_blocksize; | |
4013 | ||
4014 | if (s->ata) { | |
4015 | gen_helper_stzgm_tags(cpu_env, addr, tcg_rt); | |
4016 | } | |
4017 | /* | |
4018 | * The non-tags portion of STZGM is mostly like DC_ZVA, | |
4019 | * except the alignment happens before the access. | |
4020 | */ | |
4021 | clean_addr = clean_data_tbi(s, addr); | |
4022 | tcg_gen_andi_i64(clean_addr, clean_addr, -size); | |
4023 | gen_helper_dc_zva(cpu_env, clean_addr); | |
4024 | } else if (s->ata) { | |
4025 | if (is_load) { | |
4026 | gen_helper_ldgm(tcg_rt, cpu_env, addr); | |
4027 | } else { | |
4028 | gen_helper_stgm(cpu_env, addr, tcg_rt); | |
4029 | } | |
4030 | } else { | |
4031 | MMUAccessType acc = is_load ? MMU_DATA_LOAD : MMU_DATA_STORE; | |
4032 | int size = 4 << GMID_EL1_BS; | |
4033 | ||
4034 | clean_addr = clean_data_tbi(s, addr); | |
4035 | tcg_gen_andi_i64(clean_addr, clean_addr, -size); | |
4036 | gen_probe_access(s, clean_addr, acc, size); | |
4037 | ||
4038 | if (is_load) { | |
4039 | /* The result tags are zeros. */ | |
4040 | tcg_gen_movi_i64(tcg_rt, 0); | |
4041 | } | |
4042 | } | |
4043 | return; | |
4044 | } | |
4045 | ||
c15294c1 RH |
4046 | if (is_load) { |
4047 | tcg_gen_andi_i64(addr, addr, -TAG_GRANULE); | |
4048 | tcg_rt = cpu_reg(s, rt); | |
4049 | if (s->ata) { | |
4050 | gen_helper_ldg(tcg_rt, cpu_env, addr, tcg_rt); | |
4051 | } else { | |
4052 | clean_addr = clean_data_tbi(s, addr); | |
4053 | gen_probe_access(s, clean_addr, MMU_DATA_LOAD, MO_8); | |
4054 | gen_address_with_allocation_tag0(tcg_rt, addr); | |
4055 | } | |
4056 | } else { | |
4057 | tcg_rt = cpu_reg_sp(s, rt); | |
4058 | if (!s->ata) { | |
4059 | /* | |
4060 | * For STG and ST2G, we need to check alignment and probe memory. | |
4061 | * TODO: For STZG and STZ2G, we could rely on the stores below, | |
4062 | * at least for system mode; user-only won't enforce alignment. | |
4063 | */ | |
4064 | if (is_pair) { | |
4065 | gen_helper_st2g_stub(cpu_env, addr); | |
4066 | } else { | |
4067 | gen_helper_stg_stub(cpu_env, addr); | |
4068 | } | |
4069 | } else if (tb_cflags(s->base.tb) & CF_PARALLEL) { | |
4070 | if (is_pair) { | |
4071 | gen_helper_st2g_parallel(cpu_env, addr, tcg_rt); | |
4072 | } else { | |
4073 | gen_helper_stg_parallel(cpu_env, addr, tcg_rt); | |
4074 | } | |
4075 | } else { | |
4076 | if (is_pair) { | |
4077 | gen_helper_st2g(cpu_env, addr, tcg_rt); | |
4078 | } else { | |
4079 | gen_helper_stg(cpu_env, addr, tcg_rt); | |
4080 | } | |
4081 | } | |
4082 | } | |
4083 | ||
4084 | if (is_zero) { | |
4085 | TCGv_i64 clean_addr = clean_data_tbi(s, addr); | |
4086 | TCGv_i64 tcg_zero = tcg_const_i64(0); | |
4087 | int mem_index = get_mem_index(s); | |
4088 | int i, n = (1 + is_pair) << LOG2_TAG_GRANULE; | |
4089 | ||
4090 | tcg_gen_qemu_st_i64(tcg_zero, clean_addr, mem_index, | |
4091 | MO_Q | MO_ALIGN_16); | |
4092 | for (i = 8; i < n; i += 8) { | |
4093 | tcg_gen_addi_i64(clean_addr, clean_addr, 8); | |
4094 | tcg_gen_qemu_st_i64(tcg_zero, clean_addr, mem_index, MO_Q); | |
4095 | } | |
4096 | tcg_temp_free_i64(tcg_zero); | |
4097 | } | |
4098 | ||
4099 | if (index != 0) { | |
4100 | /* pre-index or post-index */ | |
4101 | if (index < 0) { | |
4102 | /* post-index */ | |
4103 | tcg_gen_addi_i64(addr, addr, offset); | |
4104 | } | |
4105 | tcg_gen_mov_i64(cpu_reg_sp(s, rn), addr); | |
4106 | } | |
4107 | } | |
4108 | ||
4ce31af4 | 4109 | /* Loads and stores */ |
ad7ee8a2 CF |
4110 | static void disas_ldst(DisasContext *s, uint32_t insn) |
4111 | { | |
4112 | switch (extract32(insn, 24, 6)) { | |
4113 | case 0x08: /* Load/store exclusive */ | |
4114 | disas_ldst_excl(s, insn); | |
4115 | break; | |
4116 | case 0x18: case 0x1c: /* Load register (literal) */ | |
4117 | disas_ld_lit(s, insn); | |
4118 | break; | |
4119 | case 0x28: case 0x29: | |
4120 | case 0x2c: case 0x2d: /* Load/store pair (all forms) */ | |
4121 | disas_ldst_pair(s, insn); | |
4122 | break; | |
4123 | case 0x38: case 0x39: | |
4124 | case 0x3c: case 0x3d: /* Load/store register (all forms) */ | |
4125 | disas_ldst_reg(s, insn); | |
4126 | break; | |
4127 | case 0x0c: /* AdvSIMD load/store multiple structures */ | |
4128 | disas_ldst_multiple_struct(s, insn); | |
4129 | break; | |
4130 | case 0x0d: /* AdvSIMD load/store single structure */ | |
4131 | disas_ldst_single_struct(s, insn); | |
4132 | break; | |
c15294c1 RH |
4133 | case 0x19: |
4134 | if (extract32(insn, 21, 1) != 0) { | |
4135 | disas_ldst_tag(s, insn); | |
4136 | } else if (extract32(insn, 10, 2) == 0) { | |
4137 | disas_ldst_ldapr_stlr(s, insn); | |
4138 | } else { | |
a1229109 | 4139 | unallocated_encoding(s); |
a1229109 | 4140 | } |
a1229109 | 4141 | break; |
ad7ee8a2 CF |
4142 | default: |
4143 | unallocated_encoding(s); | |
4144 | break; | |
4145 | } | |
4146 | } | |
4147 | ||
4ce31af4 | 4148 | /* PC-rel. addressing |
15bfe8b6 AG |
4149 | * 31 30 29 28 24 23 5 4 0 |
4150 | * +----+-------+-----------+-------------------+------+ | |
4151 | * | op | immlo | 1 0 0 0 0 | immhi | Rd | | |
4152 | * +----+-------+-----------+-------------------+------+ | |
4153 | */ | |
ad7ee8a2 CF |
4154 | static void disas_pc_rel_adr(DisasContext *s, uint32_t insn) |
4155 | { | |
15bfe8b6 AG |
4156 | unsigned int page, rd; |
4157 | uint64_t base; | |
037e1d00 | 4158 | uint64_t offset; |
15bfe8b6 AG |
4159 | |
4160 | page = extract32(insn, 31, 1); | |
4161 | /* SignExtend(immhi:immlo) -> offset */ | |
037e1d00 PM |
4162 | offset = sextract64(insn, 5, 19); |
4163 | offset = offset << 2 | extract32(insn, 29, 2); | |
15bfe8b6 | 4164 | rd = extract32(insn, 0, 5); |
43722a6d | 4165 | base = s->pc_curr; |
15bfe8b6 AG |
4166 | |
4167 | if (page) { | |
4168 | /* ADRP (page based) */ | |
4169 | base &= ~0xfff; | |
4170 | offset <<= 12; | |
4171 | } | |
4172 | ||
4173 | tcg_gen_movi_i64(cpu_reg(s, rd), base + offset); | |
ad7ee8a2 CF |
4174 | } |
4175 | ||
b0ff21b4 | 4176 | /* |
4ce31af4 | 4177 | * Add/subtract (immediate) |
b0ff21b4 | 4178 | * |
21a8b343 RH |
4179 | * 31 30 29 28 23 22 21 10 9 5 4 0 |
4180 | * +--+--+--+-------------+--+-------------+-----+-----+ | |
4181 | * |sf|op| S| 1 0 0 0 1 0 |sh| imm12 | Rn | Rd | | |
4182 | * +--+--+--+-------------+--+-------------+-----+-----+ | |
b0ff21b4 AB |
4183 | * |
4184 | * sf: 0 -> 32bit, 1 -> 64bit | |
4185 | * op: 0 -> add , 1 -> sub | |
4186 | * S: 1 -> set flags | |
21a8b343 | 4187 | * sh: 1 -> LSL imm by 12 |
b0ff21b4 | 4188 | */ |
ad7ee8a2 CF |
4189 | static void disas_add_sub_imm(DisasContext *s, uint32_t insn) |
4190 | { | |
b0ff21b4 AB |
4191 | int rd = extract32(insn, 0, 5); |
4192 | int rn = extract32(insn, 5, 5); | |
4193 | uint64_t imm = extract32(insn, 10, 12); | |
21a8b343 | 4194 | bool shift = extract32(insn, 22, 1); |
b0ff21b4 AB |
4195 | bool setflags = extract32(insn, 29, 1); |
4196 | bool sub_op = extract32(insn, 30, 1); | |
4197 | bool is_64bit = extract32(insn, 31, 1); | |
4198 | ||
4199 | TCGv_i64 tcg_rn = cpu_reg_sp(s, rn); | |
4200 | TCGv_i64 tcg_rd = setflags ? cpu_reg(s, rd) : cpu_reg_sp(s, rd); | |
4201 | TCGv_i64 tcg_result; | |
4202 | ||
21a8b343 | 4203 | if (shift) { |
b0ff21b4 | 4204 | imm <<= 12; |
b0ff21b4 AB |
4205 | } |
4206 | ||
4207 | tcg_result = tcg_temp_new_i64(); | |
4208 | if (!setflags) { | |
4209 | if (sub_op) { | |
4210 | tcg_gen_subi_i64(tcg_result, tcg_rn, imm); | |
4211 | } else { | |
4212 | tcg_gen_addi_i64(tcg_result, tcg_rn, imm); | |
4213 | } | |
4214 | } else { | |
4215 | TCGv_i64 tcg_imm = tcg_const_i64(imm); | |
4216 | if (sub_op) { | |
4217 | gen_sub_CC(is_64bit, tcg_result, tcg_rn, tcg_imm); | |
4218 | } else { | |
4219 | gen_add_CC(is_64bit, tcg_result, tcg_rn, tcg_imm); | |
4220 | } | |
4221 | tcg_temp_free_i64(tcg_imm); | |
4222 | } | |
4223 | ||
4224 | if (is_64bit) { | |
4225 | tcg_gen_mov_i64(tcg_rd, tcg_result); | |
4226 | } else { | |
4227 | tcg_gen_ext32u_i64(tcg_rd, tcg_result); | |
4228 | } | |
4229 | ||
4230 | tcg_temp_free_i64(tcg_result); | |
ad7ee8a2 CF |
4231 | } |
4232 | ||
efbc78ad RH |
4233 | /* |
4234 | * Add/subtract (immediate, with tags) | |
4235 | * | |
4236 | * 31 30 29 28 23 22 21 16 14 10 9 5 4 0 | |
4237 | * +--+--+--+-------------+--+---------+--+-------+-----+-----+ | |
4238 | * |sf|op| S| 1 0 0 0 1 1 |o2| uimm6 |o3| uimm4 | Rn | Rd | | |
4239 | * +--+--+--+-------------+--+---------+--+-------+-----+-----+ | |
4240 | * | |
4241 | * op: 0 -> add, 1 -> sub | |
4242 | */ | |
4243 | static void disas_add_sub_imm_with_tags(DisasContext *s, uint32_t insn) | |
4244 | { | |
4245 | int rd = extract32(insn, 0, 5); | |
4246 | int rn = extract32(insn, 5, 5); | |
4247 | int uimm4 = extract32(insn, 10, 4); | |
4248 | int uimm6 = extract32(insn, 16, 6); | |
4249 | bool sub_op = extract32(insn, 30, 1); | |
4250 | TCGv_i64 tcg_rn, tcg_rd; | |
4251 | int imm; | |
4252 | ||
4253 | /* Test all of sf=1, S=0, o2=0, o3=0. */ | |
4254 | if ((insn & 0xa040c000u) != 0x80000000u || | |
4255 | !dc_isar_feature(aa64_mte_insn_reg, s)) { | |
4256 | unallocated_encoding(s); | |
4257 | return; | |
4258 | } | |
4259 | ||
4260 | imm = uimm6 << LOG2_TAG_GRANULE; | |
4261 | if (sub_op) { | |
4262 | imm = -imm; | |
4263 | } | |
4264 | ||
4265 | tcg_rn = cpu_reg_sp(s, rn); | |
4266 | tcg_rd = cpu_reg_sp(s, rd); | |
4267 | ||
4268 | if (s->ata) { | |
4269 | TCGv_i32 offset = tcg_const_i32(imm); | |
4270 | TCGv_i32 tag_offset = tcg_const_i32(uimm4); | |
4271 | ||
4272 | gen_helper_addsubg(tcg_rd, cpu_env, tcg_rn, offset, tag_offset); | |
4273 | tcg_temp_free_i32(tag_offset); | |
4274 | tcg_temp_free_i32(offset); | |
4275 | } else { | |
4276 | tcg_gen_addi_i64(tcg_rd, tcg_rn, imm); | |
4277 | gen_address_with_allocation_tag0(tcg_rd, tcg_rd); | |
4278 | } | |
4279 | } | |
4280 | ||
71b46089 AG |
4281 | /* The input should be a value in the bottom e bits (with higher |
4282 | * bits zero); returns that value replicated into every element | |
4283 | * of size e in a 64 bit integer. | |
4284 | */ | |
4285 | static uint64_t bitfield_replicate(uint64_t mask, unsigned int e) | |
4286 | { | |
4287 | assert(e != 0); | |
4288 | while (e < 64) { | |
4289 | mask |= mask << e; | |
4290 | e *= 2; | |
4291 | } | |
4292 | return mask; | |
4293 | } | |
4294 | ||
4295 | /* Return a value with the bottom len bits set (where 0 < len <= 64) */ | |
4296 | static inline uint64_t bitmask64(unsigned int length) | |
4297 | { | |
4298 | assert(length > 0 && length <= 64); | |
4299 | return ~0ULL >> (64 - length); | |
4300 | } | |
4301 | ||
4302 | /* Simplified variant of pseudocode DecodeBitMasks() for the case where we | |
4303 | * only require the wmask. Returns false if the imms/immr/immn are a reserved | |
4304 | * value (ie should cause a guest UNDEF exception), and true if they are | |
4305 | * valid, in which case the decoded bit pattern is written to result. | |
4306 | */ | |
8c71baed RH |
4307 | bool logic_imm_decode_wmask(uint64_t *result, unsigned int immn, |
4308 | unsigned int imms, unsigned int immr) | |
71b46089 AG |
4309 | { |
4310 | uint64_t mask; | |
4311 | unsigned e, levels, s, r; | |
4312 | int len; | |
4313 | ||
4314 | assert(immn < 2 && imms < 64 && immr < 64); | |
4315 | ||
4316 | /* The bit patterns we create here are 64 bit patterns which | |
4317 | * are vectors of identical elements of size e = 2, 4, 8, 16, 32 or | |
4318 | * 64 bits each. Each element contains the same value: a run | |
4319 | * of between 1 and e-1 non-zero bits, rotated within the | |
4320 | * element by between 0 and e-1 bits. | |
4321 | * | |
4322 | * The element size and run length are encoded into immn (1 bit) | |
4323 | * and imms (6 bits) as follows: | |
4324 | * 64 bit elements: immn = 1, imms = <length of run - 1> | |
4325 | * 32 bit elements: immn = 0, imms = 0 : <length of run - 1> | |
4326 | * 16 bit elements: immn = 0, imms = 10 : <length of run - 1> | |
4327 | * 8 bit elements: immn = 0, imms = 110 : <length of run - 1> | |
4328 | * 4 bit elements: immn = 0, imms = 1110 : <length of run - 1> | |
4329 | * 2 bit elements: immn = 0, imms = 11110 : <length of run - 1> | |
4330 | * Notice that immn = 0, imms = 11111x is the only combination | |
4331 | * not covered by one of the above options; this is reserved. | |
4332 | * Further, <length of run - 1> all-ones is a reserved pattern. | |
4333 | * | |
4334 | * In all cases the rotation is by immr % e (and immr is 6 bits). | |
4335 | */ | |
4336 | ||
4337 | /* First determine the element size */ | |
4338 | len = 31 - clz32((immn << 6) | (~imms & 0x3f)); | |
4339 | if (len < 1) { | |
4340 | /* This is the immn == 0, imms == 0x11111x case */ | |
4341 | return false; | |
4342 | } | |
4343 | e = 1 << len; | |
4344 | ||
4345 | levels = e - 1; | |
4346 | s = imms & levels; | |
4347 | r = immr & levels; | |
4348 | ||
4349 | if (s == levels) { | |
4350 | /* <length of run - 1> mustn't be all-ones. */ | |
4351 | return false; | |
4352 | } | |
4353 | ||
4354 | /* Create the value of one element: s+1 set bits rotated | |
4355 | * by r within the element (which is e bits wide)... | |
4356 | */ | |
4357 | mask = bitmask64(s + 1); | |
e167adc9 PM |
4358 | if (r) { |
4359 | mask = (mask >> r) | (mask << (e - r)); | |
4360 | mask &= bitmask64(e); | |
4361 | } | |
71b46089 AG |
4362 | /* ...then replicate the element over the whole 64 bit value */ |
4363 | mask = bitfield_replicate(mask, e); | |
4364 | *result = mask; | |
4365 | return true; | |
4366 | } | |
4367 | ||
4ce31af4 | 4368 | /* Logical (immediate) |
71b46089 AG |
4369 | * 31 30 29 28 23 22 21 16 15 10 9 5 4 0 |
4370 | * +----+-----+-------------+---+------+------+------+------+ | |
4371 | * | sf | opc | 1 0 0 1 0 0 | N | immr | imms | Rn | Rd | | |
4372 | * +----+-----+-------------+---+------+------+------+------+ | |
4373 | */ | |
ad7ee8a2 CF |
4374 | static void disas_logic_imm(DisasContext *s, uint32_t insn) |
4375 | { | |
71b46089 AG |
4376 | unsigned int sf, opc, is_n, immr, imms, rn, rd; |
4377 | TCGv_i64 tcg_rd, tcg_rn; | |
4378 | uint64_t wmask; | |
4379 | bool is_and = false; | |
4380 | ||
4381 | sf = extract32(insn, 31, 1); | |
4382 | opc = extract32(insn, 29, 2); | |
4383 | is_n = extract32(insn, 22, 1); | |
4384 | immr = extract32(insn, 16, 6); | |
4385 | imms = extract32(insn, 10, 6); | |
4386 | rn = extract32(insn, 5, 5); | |
4387 | rd = extract32(insn, 0, 5); | |
4388 | ||
4389 | if (!sf && is_n) { | |
4390 | unallocated_encoding(s); | |
4391 | return; | |
4392 | } | |
4393 | ||
4394 | if (opc == 0x3) { /* ANDS */ | |
4395 | tcg_rd = cpu_reg(s, rd); | |
4396 | } else { | |
4397 | tcg_rd = cpu_reg_sp(s, rd); | |
4398 | } | |
4399 | tcg_rn = cpu_reg(s, rn); | |
4400 | ||
4401 | if (!logic_imm_decode_wmask(&wmask, is_n, imms, immr)) { | |
4402 | /* some immediate field values are reserved */ | |
4403 | unallocated_encoding(s); | |
4404 | return; | |
4405 | } | |
4406 | ||
4407 | if (!sf) { | |
4408 | wmask &= 0xffffffff; | |
4409 | } | |
4410 | ||
4411 | switch (opc) { | |
4412 | case 0x3: /* ANDS */ | |
4413 | case 0x0: /* AND */ | |
4414 | tcg_gen_andi_i64(tcg_rd, tcg_rn, wmask); | |
4415 | is_and = true; | |
4416 | break; | |
4417 | case 0x1: /* ORR */ | |
4418 | tcg_gen_ori_i64(tcg_rd, tcg_rn, wmask); | |
4419 | break; | |
4420 | case 0x2: /* EOR */ | |
4421 | tcg_gen_xori_i64(tcg_rd, tcg_rn, wmask); | |
4422 | break; | |
4423 | default: | |
4424 | assert(FALSE); /* must handle all above */ | |
4425 | break; | |
4426 | } | |
4427 | ||
4428 | if (!sf && !is_and) { | |
4429 | /* zero extend final result; we know we can skip this for AND | |
4430 | * since the immediate had the high 32 bits clear. | |
4431 | */ | |
4432 | tcg_gen_ext32u_i64(tcg_rd, tcg_rd); | |
4433 | } | |
4434 | ||
4435 | if (opc == 3) { /* ANDS */ | |
4436 | gen_logic_CC(sf, tcg_rd); | |
4437 | } | |
ad7ee8a2 CF |
4438 | } |
4439 | ||
ed6ec679 | 4440 | /* |
4ce31af4 | 4441 | * Move wide (immediate) |
ed6ec679 AB |
4442 | * |
4443 | * 31 30 29 28 23 22 21 20 5 4 0 | |
4444 | * +--+-----+-------------+-----+----------------+------+ | |
4445 | * |sf| opc | 1 0 0 1 0 1 | hw | imm16 | Rd | | |
4446 | * +--+-----+-------------+-----+----------------+------+ | |
4447 | * | |
4448 | * sf: 0 -> 32 bit, 1 -> 64 bit | |
4449 | * opc: 00 -> N, 10 -> Z, 11 -> K | |
4450 | * hw: shift/16 (0,16, and sf only 32, 48) | |
4451 | */ | |
ad7ee8a2 CF |
4452 | static void disas_movw_imm(DisasContext *s, uint32_t insn) |
4453 | { | |
ed6ec679 AB |
4454 | int rd = extract32(insn, 0, 5); |
4455 | uint64_t imm = extract32(insn, 5, 16); | |
4456 | int sf = extract32(insn, 31, 1); | |
4457 | int opc = extract32(insn, 29, 2); | |
4458 | int pos = extract32(insn, 21, 2) << 4; | |
4459 | TCGv_i64 tcg_rd = cpu_reg(s, rd); | |
4460 | TCGv_i64 tcg_imm; | |
4461 | ||
4462 | if (!sf && (pos >= 32)) { | |
4463 | unallocated_encoding(s); | |
4464 | return; | |
4465 | } | |
4466 | ||
4467 | switch (opc) { | |
4468 | case 0: /* MOVN */ | |
4469 | case 2: /* MOVZ */ | |
4470 | imm <<= pos; | |
4471 | if (opc == 0) { | |
4472 | imm = ~imm; | |
4473 | } | |
4474 | if (!sf) { | |
4475 | imm &= 0xffffffffu; | |
4476 | } | |
4477 | tcg_gen_movi_i64(tcg_rd, imm); | |
4478 | break; | |
4479 | case 3: /* MOVK */ | |
4480 | tcg_imm = tcg_const_i64(imm); | |
4481 | tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_imm, pos, 16); | |
4482 | tcg_temp_free_i64(tcg_imm); | |
4483 | if (!sf) { | |
4484 | tcg_gen_ext32u_i64(tcg_rd, tcg_rd); | |
4485 | } | |
4486 | break; | |
4487 | default: | |
4488 | unallocated_encoding(s); | |
4489 | break; | |
4490 | } | |
ad7ee8a2 CF |
4491 | } |
4492 | ||
4ce31af4 | 4493 | /* Bitfield |
88077742 CF |
4494 | * 31 30 29 28 23 22 21 16 15 10 9 5 4 0 |
4495 | * +----+-----+-------------+---+------+------+------+------+ | |
4496 | * | sf | opc | 1 0 0 1 1 0 | N | immr | imms | Rn | Rd | | |
4497 | * +----+-----+-------------+---+------+------+------+------+ | |
4498 | */ | |
ad7ee8a2 CF |
4499 | static void disas_bitfield(DisasContext *s, uint32_t insn) |
4500 | { | |
88077742 CF |
4501 | unsigned int sf, n, opc, ri, si, rn, rd, bitsize, pos, len; |
4502 | TCGv_i64 tcg_rd, tcg_tmp; | |
4503 | ||
4504 | sf = extract32(insn, 31, 1); | |
4505 | opc = extract32(insn, 29, 2); | |
4506 | n = extract32(insn, 22, 1); | |
4507 | ri = extract32(insn, 16, 6); | |
4508 | si = extract32(insn, 10, 6); | |
4509 | rn = extract32(insn, 5, 5); | |
4510 | rd = extract32(insn, 0, 5); | |
4511 | bitsize = sf ? 64 : 32; | |
4512 | ||
4513 | if (sf != n || ri >= bitsize || si >= bitsize || opc > 2) { | |
4514 | unallocated_encoding(s); | |
4515 | return; | |
4516 | } | |
4517 | ||
4518 | tcg_rd = cpu_reg(s, rd); | |
d3a77b42 RH |
4519 | |
4520 | /* Suppress the zero-extend for !sf. Since RI and SI are constrained | |
4521 | to be smaller than bitsize, we'll never reference data outside the | |
4522 | low 32-bits anyway. */ | |
4523 | tcg_tmp = read_cpu_reg(s, rn, 1); | |
88077742 | 4524 | |
59a71b4c | 4525 | /* Recognize simple(r) extractions. */ |
86c9ab27 | 4526 | if (si >= ri) { |
59a71b4c RH |
4527 | /* Wd<s-r:0> = Wn<s:r> */ |
4528 | len = (si - ri) + 1; | |
4529 | if (opc == 0) { /* SBFM: ASR, SBFX, SXTB, SXTH, SXTW */ | |
4530 | tcg_gen_sextract_i64(tcg_rd, tcg_tmp, ri, len); | |
ef60151b | 4531 | goto done; |
59a71b4c RH |
4532 | } else if (opc == 2) { /* UBFM: UBFX, LSR, UXTB, UXTH */ |
4533 | tcg_gen_extract_i64(tcg_rd, tcg_tmp, ri, len); | |
9924e858 RH |
4534 | return; |
4535 | } | |
87eb65a3 RH |
4536 | /* opc == 1, BFXIL fall through to deposit */ |
4537 | tcg_gen_shri_i64(tcg_tmp, tcg_tmp, ri); | |
88077742 | 4538 | pos = 0; |
88077742 | 4539 | } else { |
59a71b4c RH |
4540 | /* Handle the ri > si case with a deposit |
4541 | * Wd<32+s-r,32-r> = Wn<s:0> | |
4542 | */ | |
88077742 | 4543 | len = si + 1; |
59a71b4c | 4544 | pos = (bitsize - ri) & (bitsize - 1); |
88077742 CF |
4545 | } |
4546 | ||
59a71b4c RH |
4547 | if (opc == 0 && len < ri) { |
4548 | /* SBFM: sign extend the destination field from len to fill | |
4549 | the balance of the word. Let the deposit below insert all | |
4550 | of those sign bits. */ | |
4551 | tcg_gen_sextract_i64(tcg_tmp, tcg_tmp, 0, len); | |
4552 | len = ri; | |
4553 | } | |
88077742 | 4554 | |
87eb65a3 | 4555 | if (opc == 1) { /* BFM, BFXIL */ |
59a71b4c RH |
4556 | tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_tmp, pos, len); |
4557 | } else { | |
4558 | /* SBFM or UBFM: We start with zero, and we haven't modified | |
4559 | any bits outside bitsize, therefore the zero-extension | |
4560 | below is unneeded. */ | |
4561 | tcg_gen_deposit_z_i64(tcg_rd, tcg_tmp, pos, len); | |
4562 | return; | |
88077742 CF |
4563 | } |
4564 | ||
ef60151b | 4565 | done: |
88077742 CF |
4566 | if (!sf) { /* zero extend final result */ |
4567 | tcg_gen_ext32u_i64(tcg_rd, tcg_rd); | |
4568 | } | |
ad7ee8a2 CF |
4569 | } |
4570 | ||
4ce31af4 | 4571 | /* Extract |
e801de93 AG |
4572 | * 31 30 29 28 23 22 21 20 16 15 10 9 5 4 0 |
4573 | * +----+------+-------------+---+----+------+--------+------+------+ | |
4574 | * | sf | op21 | 1 0 0 1 1 1 | N | o0 | Rm | imms | Rn | Rd | | |
4575 | * +----+------+-------------+---+----+------+--------+------+------+ | |
4576 | */ | |
ad7ee8a2 CF |
4577 | static void disas_extract(DisasContext *s, uint32_t insn) |
4578 | { | |
e801de93 AG |
4579 | unsigned int sf, n, rm, imm, rn, rd, bitsize, op21, op0; |
4580 | ||
4581 | sf = extract32(insn, 31, 1); | |
4582 | n = extract32(insn, 22, 1); | |
4583 | rm = extract32(insn, 16, 5); | |
4584 | imm = extract32(insn, 10, 6); | |
4585 | rn = extract32(insn, 5, 5); | |
4586 | rd = extract32(insn, 0, 5); | |
4587 | op21 = extract32(insn, 29, 2); | |
4588 | op0 = extract32(insn, 21, 1); | |
4589 | bitsize = sf ? 64 : 32; | |
4590 | ||
4591 | if (sf != n || op21 || op0 || imm >= bitsize) { | |
4592 | unallocated_encoding(s); | |
4593 | } else { | |
4594 | TCGv_i64 tcg_rd, tcg_rm, tcg_rn; | |
4595 | ||
4596 | tcg_rd = cpu_reg(s, rd); | |
4597 | ||
8fb0ad8e | 4598 | if (unlikely(imm == 0)) { |
e801de93 AG |
4599 | /* tcg shl_i32/shl_i64 is undefined for 32/64 bit shifts, |
4600 | * so an extract from bit 0 is a special case. | |
4601 | */ | |
4602 | if (sf) { | |
4603 | tcg_gen_mov_i64(tcg_rd, cpu_reg(s, rm)); | |
4604 | } else { | |
4605 | tcg_gen_ext32u_i64(tcg_rd, cpu_reg(s, rm)); | |
4606 | } | |
80ac954c | 4607 | } else { |
8fb0ad8e | 4608 | tcg_rm = cpu_reg(s, rm); |
80ac954c RH |
4609 | tcg_rn = cpu_reg(s, rn); |
4610 | ||
8fb0ad8e | 4611 | if (sf) { |
80ac954c RH |
4612 | /* Specialization to ROR happens in EXTRACT2. */ |
4613 | tcg_gen_extract2_i64(tcg_rd, tcg_rm, tcg_rn, imm); | |
8fb0ad8e | 4614 | } else { |
80ac954c RH |
4615 | TCGv_i32 t0 = tcg_temp_new_i32(); |
4616 | ||
4617 | tcg_gen_extrl_i64_i32(t0, tcg_rm); | |
4618 | if (rm == rn) { | |
4619 | tcg_gen_rotri_i32(t0, t0, imm); | |
4620 | } else { | |
4621 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
4622 | tcg_gen_extrl_i64_i32(t1, tcg_rn); | |
4623 | tcg_gen_extract2_i32(t0, t0, t1, imm); | |
4624 | tcg_temp_free_i32(t1); | |
4625 | } | |
4626 | tcg_gen_extu_i32_i64(tcg_rd, t0); | |
4627 | tcg_temp_free_i32(t0); | |
8fb0ad8e | 4628 | } |
e801de93 | 4629 | } |
e801de93 | 4630 | } |
ad7ee8a2 CF |
4631 | } |
4632 | ||
4ce31af4 | 4633 | /* Data processing - immediate */ |
ad7ee8a2 CF |
4634 | static void disas_data_proc_imm(DisasContext *s, uint32_t insn) |
4635 | { | |
4636 | switch (extract32(insn, 23, 6)) { | |
4637 | case 0x20: case 0x21: /* PC-rel. addressing */ | |
4638 | disas_pc_rel_adr(s, insn); | |
4639 | break; | |
21a8b343 | 4640 | case 0x22: /* Add/subtract (immediate) */ |
ad7ee8a2 CF |
4641 | disas_add_sub_imm(s, insn); |
4642 | break; | |
efbc78ad RH |
4643 | case 0x23: /* Add/subtract (immediate, with tags) */ |
4644 | disas_add_sub_imm_with_tags(s, insn); | |
4645 | break; | |
ad7ee8a2 CF |
4646 | case 0x24: /* Logical (immediate) */ |
4647 | disas_logic_imm(s, insn); | |
4648 | break; | |
4649 | case 0x25: /* Move wide (immediate) */ | |
4650 | disas_movw_imm(s, insn); | |
4651 | break; | |
4652 | case 0x26: /* Bitfield */ | |
4653 | disas_bitfield(s, insn); | |
4654 | break; | |
4655 | case 0x27: /* Extract */ | |
4656 | disas_extract(s, insn); | |
4657 | break; | |
4658 | default: | |
4659 | unallocated_encoding(s); | |
4660 | break; | |
4661 | } | |
4662 | } | |
4663 | ||
832ffa1c AG |
4664 | /* Shift a TCGv src by TCGv shift_amount, put result in dst. |
4665 | * Note that it is the caller's responsibility to ensure that the | |
4666 | * shift amount is in range (ie 0..31 or 0..63) and provide the ARM | |
4667 | * mandated semantics for out of range shifts. | |
4668 | */ | |
4669 | static void shift_reg(TCGv_i64 dst, TCGv_i64 src, int sf, | |
4670 | enum a64_shift_type shift_type, TCGv_i64 shift_amount) | |
4671 | { | |
4672 | switch (shift_type) { | |
4673 | case A64_SHIFT_TYPE_LSL: | |
4674 | tcg_gen_shl_i64(dst, src, shift_amount); | |
4675 | break; | |
4676 | case A64_SHIFT_TYPE_LSR: | |
4677 | tcg_gen_shr_i64(dst, src, shift_amount); | |
4678 | break; | |
4679 | case A64_SHIFT_TYPE_ASR: | |
4680 | if (!sf) { | |
4681 | tcg_gen_ext32s_i64(dst, src); | |
4682 | } | |
4683 | tcg_gen_sar_i64(dst, sf ? src : dst, shift_amount); | |
4684 | break; | |
4685 | case A64_SHIFT_TYPE_ROR: | |
4686 | if (sf) { | |
4687 | tcg_gen_rotr_i64(dst, src, shift_amount); | |
4688 | } else { | |
4689 | TCGv_i32 t0, t1; | |
4690 | t0 = tcg_temp_new_i32(); | |
4691 | t1 = tcg_temp_new_i32(); | |
ecc7b3aa RH |
4692 | tcg_gen_extrl_i64_i32(t0, src); |
4693 | tcg_gen_extrl_i64_i32(t1, shift_amount); | |
832ffa1c AG |
4694 | tcg_gen_rotr_i32(t0, t0, t1); |
4695 | tcg_gen_extu_i32_i64(dst, t0); | |
4696 | tcg_temp_free_i32(t0); | |
4697 | tcg_temp_free_i32(t1); | |
4698 | } | |
4699 | break; | |
4700 | default: | |
4701 | assert(FALSE); /* all shift types should be handled */ | |
4702 | break; | |
4703 | } | |
4704 | ||
4705 | if (!sf) { /* zero extend final result */ | |
4706 | tcg_gen_ext32u_i64(dst, dst); | |
4707 | } | |
4708 | } | |
4709 | ||
4710 | /* Shift a TCGv src by immediate, put result in dst. | |
4711 | * The shift amount must be in range (this should always be true as the | |
4712 | * relevant instructions will UNDEF on bad shift immediates). | |
4713 | */ | |
4714 | static void shift_reg_imm(TCGv_i64 dst, TCGv_i64 src, int sf, | |
4715 | enum a64_shift_type shift_type, unsigned int shift_i) | |
4716 | { | |
4717 | assert(shift_i < (sf ? 64 : 32)); | |
4718 | ||
4719 | if (shift_i == 0) { | |
4720 | tcg_gen_mov_i64(dst, src); | |
4721 | } else { | |
4722 | TCGv_i64 shift_const; | |
4723 | ||
4724 | shift_const = tcg_const_i64(shift_i); | |
4725 | shift_reg(dst, src, sf, shift_type, shift_const); | |
4726 | tcg_temp_free_i64(shift_const); | |
4727 | } | |
4728 | } | |
4729 | ||
4ce31af4 | 4730 | /* Logical (shifted register) |
832ffa1c AG |
4731 | * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0 |
4732 | * +----+-----+-----------+-------+---+------+--------+------+------+ | |
4733 | * | sf | opc | 0 1 0 1 0 | shift | N | Rm | imm6 | Rn | Rd | | |
4734 | * +----+-----+-----------+-------+---+------+--------+------+------+ | |
4735 | */ | |
ad7ee8a2 CF |
4736 | static void disas_logic_reg(DisasContext *s, uint32_t insn) |
4737 | { | |
832ffa1c AG |
4738 | TCGv_i64 tcg_rd, tcg_rn, tcg_rm; |
4739 | unsigned int sf, opc, shift_type, invert, rm, shift_amount, rn, rd; | |
4740 | ||
4741 | sf = extract32(insn, 31, 1); | |
4742 | opc = extract32(insn, 29, 2); | |
4743 | shift_type = extract32(insn, 22, 2); | |
4744 | invert = extract32(insn, 21, 1); | |
4745 | rm = extract32(insn, 16, 5); | |
4746 | shift_amount = extract32(insn, 10, 6); | |
4747 | rn = extract32(insn, 5, 5); | |
4748 | rd = extract32(insn, 0, 5); | |
4749 | ||
4750 | if (!sf && (shift_amount & (1 << 5))) { | |
4751 | unallocated_encoding(s); | |
4752 | return; | |
4753 | } | |
4754 | ||
4755 | tcg_rd = cpu_reg(s, rd); | |
4756 | ||
4757 | if (opc == 1 && shift_amount == 0 && shift_type == 0 && rn == 31) { | |
4758 | /* Unshifted ORR and ORN with WZR/XZR is the standard encoding for | |
4759 | * register-register MOV and MVN, so it is worth special casing. | |
4760 | */ | |
4761 | tcg_rm = cpu_reg(s, rm); | |
4762 | if (invert) { | |
4763 | tcg_gen_not_i64(tcg_rd, tcg_rm); | |
4764 | if (!sf) { | |
4765 | tcg_gen_ext32u_i64(tcg_rd, tcg_rd); | |
4766 | } | |
4767 | } else { | |
4768 | if (sf) { | |
4769 | tcg_gen_mov_i64(tcg_rd, tcg_rm); | |
4770 | } else { | |
4771 | tcg_gen_ext32u_i64(tcg_rd, tcg_rm); | |
4772 | } | |
4773 | } | |
4774 | return; | |
4775 | } | |
4776 | ||
4777 | tcg_rm = read_cpu_reg(s, rm, sf); | |
4778 | ||
4779 | if (shift_amount) { | |
4780 | shift_reg_imm(tcg_rm, tcg_rm, sf, shift_type, shift_amount); | |
4781 | } | |
4782 | ||
4783 | tcg_rn = cpu_reg(s, rn); | |
4784 | ||
4785 | switch (opc | (invert << 2)) { | |
4786 | case 0: /* AND */ | |
4787 | case 3: /* ANDS */ | |
4788 | tcg_gen_and_i64(tcg_rd, tcg_rn, tcg_rm); | |
4789 | break; | |
4790 | case 1: /* ORR */ | |
4791 | tcg_gen_or_i64(tcg_rd, tcg_rn, tcg_rm); | |
4792 | break; | |
4793 | case 2: /* EOR */ | |
4794 | tcg_gen_xor_i64(tcg_rd, tcg_rn, tcg_rm); | |
4795 | break; | |
4796 | case 4: /* BIC */ | |
4797 | case 7: /* BICS */ | |
4798 | tcg_gen_andc_i64(tcg_rd, tcg_rn, tcg_rm); | |
4799 | break; | |
4800 | case 5: /* ORN */ | |
4801 | tcg_gen_orc_i64(tcg_rd, tcg_rn, tcg_rm); | |
4802 | break; | |
4803 | case 6: /* EON */ | |
4804 | tcg_gen_eqv_i64(tcg_rd, tcg_rn, tcg_rm); | |
4805 | break; | |
4806 | default: | |
4807 | assert(FALSE); | |
4808 | break; | |
4809 | } | |
4810 | ||
4811 | if (!sf) { | |
4812 | tcg_gen_ext32u_i64(tcg_rd, tcg_rd); | |
4813 | } | |
4814 | ||
4815 | if (opc == 3) { | |
4816 | gen_logic_CC(sf, tcg_rd); | |
4817 | } | |
ad7ee8a2 CF |
4818 | } |
4819 | ||
b0ff21b4 | 4820 | /* |
4ce31af4 | 4821 | * Add/subtract (extended register) |
b0ff21b4 AB |
4822 | * |
4823 | * 31|30|29|28 24|23 22|21|20 16|15 13|12 10|9 5|4 0| | |
4824 | * +--+--+--+-----------+-----+--+-------+------+------+----+----+ | |
4825 | * |sf|op| S| 0 1 0 1 1 | opt | 1| Rm |option| imm3 | Rn | Rd | | |
4826 | * +--+--+--+-----------+-----+--+-------+------+------+----+----+ | |
4827 | * | |
4828 | * sf: 0 -> 32bit, 1 -> 64bit | |
4829 | * op: 0 -> add , 1 -> sub | |
4830 | * S: 1 -> set flags | |
4831 | * opt: 00 | |
4832 | * option: extension type (see DecodeRegExtend) | |
4833 | * imm3: optional shift to Rm | |
4834 | * | |
4835 | * Rd = Rn + LSL(extend(Rm), amount) | |
4836 | */ | |
ad7ee8a2 CF |
4837 | static void disas_add_sub_ext_reg(DisasContext *s, uint32_t insn) |
4838 | { | |
b0ff21b4 AB |
4839 | int rd = extract32(insn, 0, 5); |
4840 | int rn = extract32(insn, 5, 5); | |
4841 | int imm3 = extract32(insn, 10, 3); | |
4842 | int option = extract32(insn, 13, 3); | |
4843 | int rm = extract32(insn, 16, 5); | |
4f611066 | 4844 | int opt = extract32(insn, 22, 2); |
b0ff21b4 AB |
4845 | bool setflags = extract32(insn, 29, 1); |
4846 | bool sub_op = extract32(insn, 30, 1); | |
4847 | bool sf = extract32(insn, 31, 1); | |
4848 | ||
4849 | TCGv_i64 tcg_rm, tcg_rn; /* temps */ | |
4850 | TCGv_i64 tcg_rd; | |
4851 | TCGv_i64 tcg_result; | |
4852 | ||
4f611066 | 4853 | if (imm3 > 4 || opt != 0) { |
b0ff21b4 AB |
4854 | unallocated_encoding(s); |
4855 | return; | |
4856 | } | |
4857 | ||
4858 | /* non-flag setting ops may use SP */ | |
4859 | if (!setflags) { | |
b0ff21b4 AB |
4860 | tcg_rd = cpu_reg_sp(s, rd); |
4861 | } else { | |
b0ff21b4 AB |
4862 | tcg_rd = cpu_reg(s, rd); |
4863 | } | |
cf4ab1af | 4864 | tcg_rn = read_cpu_reg_sp(s, rn, sf); |
b0ff21b4 AB |
4865 | |
4866 | tcg_rm = read_cpu_reg(s, rm, sf); | |
4867 | ext_and_shift_reg(tcg_rm, tcg_rm, option, imm3); | |
4868 | ||
4869 | tcg_result = tcg_temp_new_i64(); | |
4870 | ||
4871 | if (!setflags) { | |
4872 | if (sub_op) { | |
4873 | tcg_gen_sub_i64(tcg_result, tcg_rn, tcg_rm); | |
4874 | } else { | |
4875 | tcg_gen_add_i64(tcg_result, tcg_rn, tcg_rm); | |
4876 | } | |
4877 | } else { | |
4878 | if (sub_op) { | |
4879 | gen_sub_CC(sf, tcg_result, tcg_rn, tcg_rm); | |
4880 | } else { | |
4881 | gen_add_CC(sf, tcg_result, tcg_rn, tcg_rm); | |
4882 | } | |
4883 | } | |
4884 | ||
4885 | if (sf) { | |
4886 | tcg_gen_mov_i64(tcg_rd, tcg_result); | |
4887 | } else { | |
4888 | tcg_gen_ext32u_i64(tcg_rd, tcg_result); | |
4889 | } | |
4890 | ||
4891 | tcg_temp_free_i64(tcg_result); | |
ad7ee8a2 CF |
4892 | } |
4893 | ||
b0ff21b4 | 4894 | /* |
4ce31af4 | 4895 | * Add/subtract (shifted register) |
b0ff21b4 AB |
4896 | * |
4897 | * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0 | |
4898 | * +--+--+--+-----------+-----+--+-------+---------+------+------+ | |
4899 | * |sf|op| S| 0 1 0 1 1 |shift| 0| Rm | imm6 | Rn | Rd | | |
4900 | * +--+--+--+-----------+-----+--+-------+---------+------+------+ | |
4901 | * | |
4902 | * sf: 0 -> 32bit, 1 -> 64bit | |
4903 | * op: 0 -> add , 1 -> sub | |
4904 | * S: 1 -> set flags | |
4905 | * shift: 00 -> LSL, 01 -> LSR, 10 -> ASR, 11 -> RESERVED | |
4906 | * imm6: Shift amount to apply to Rm before the add/sub | |
4907 | */ | |
ad7ee8a2 CF |
4908 | static void disas_add_sub_reg(DisasContext *s, uint32_t insn) |
4909 | { | |
b0ff21b4 AB |
4910 | int rd = extract32(insn, 0, 5); |
4911 | int rn = extract32(insn, 5, 5); | |
4912 | int imm6 = extract32(insn, 10, 6); | |
4913 | int rm = extract32(insn, 16, 5); | |
4914 | int shift_type = extract32(insn, 22, 2); | |
4915 | bool setflags = extract32(insn, 29, 1); | |
4916 | bool sub_op = extract32(insn, 30, 1); | |
4917 | bool sf = extract32(insn, 31, 1); | |
4918 | ||
4919 | TCGv_i64 tcg_rd = cpu_reg(s, rd); | |
4920 | TCGv_i64 tcg_rn, tcg_rm; | |
4921 | TCGv_i64 tcg_result; | |
4922 | ||
4923 | if ((shift_type == 3) || (!sf && (imm6 > 31))) { | |
4924 | unallocated_encoding(s); | |
4925 | return; | |
4926 | } | |
4927 | ||
4928 | tcg_rn = read_cpu_reg(s, rn, sf); | |
4929 | tcg_rm = read_cpu_reg(s, rm, sf); | |
4930 | ||
4931 | shift_reg_imm(tcg_rm, tcg_rm, sf, shift_type, imm6); | |
4932 | ||
4933 | tcg_result = tcg_temp_new_i64(); | |
4934 | ||
4935 | if (!setflags) { | |
4936 | if (sub_op) { | |
4937 | tcg_gen_sub_i64(tcg_result, tcg_rn, tcg_rm); | |
4938 | } else { | |
4939 | tcg_gen_add_i64(tcg_result, tcg_rn, tcg_rm); | |
4940 | } | |
4941 | } else { | |
4942 | if (sub_op) { | |
4943 | gen_sub_CC(sf, tcg_result, tcg_rn, tcg_rm); | |
4944 | } else { | |
4945 | gen_add_CC(sf, tcg_result, tcg_rn, tcg_rm); | |
4946 | } | |
4947 | } | |
4948 | ||
4949 | if (sf) { | |
4950 | tcg_gen_mov_i64(tcg_rd, tcg_result); | |
4951 | } else { | |
4952 | tcg_gen_ext32u_i64(tcg_rd, tcg_result); | |
4953 | } | |
4954 | ||
4955 | tcg_temp_free_i64(tcg_result); | |
ad7ee8a2 CF |
4956 | } |
4957 | ||
4ce31af4 PM |
4958 | /* Data-processing (3 source) |
4959 | * | |
4960 | * 31 30 29 28 24 23 21 20 16 15 14 10 9 5 4 0 | |
4961 | * +--+------+-----------+------+------+----+------+------+------+ | |
4962 | * |sf| op54 | 1 1 0 1 1 | op31 | Rm | o0 | Ra | Rn | Rd | | |
4963 | * +--+------+-----------+------+------+----+------+------+------+ | |
52c8b9af | 4964 | */ |
ad7ee8a2 CF |
4965 | static void disas_data_proc_3src(DisasContext *s, uint32_t insn) |
4966 | { | |
52c8b9af AG |
4967 | int rd = extract32(insn, 0, 5); |
4968 | int rn = extract32(insn, 5, 5); | |
4969 | int ra = extract32(insn, 10, 5); | |
4970 | int rm = extract32(insn, 16, 5); | |
4971 | int op_id = (extract32(insn, 29, 3) << 4) | | |
4972 | (extract32(insn, 21, 3) << 1) | | |
4973 | extract32(insn, 15, 1); | |
4974 | bool sf = extract32(insn, 31, 1); | |
4975 | bool is_sub = extract32(op_id, 0, 1); | |
4976 | bool is_high = extract32(op_id, 2, 1); | |
4977 | bool is_signed = false; | |
4978 | TCGv_i64 tcg_op1; | |
4979 | TCGv_i64 tcg_op2; | |
4980 | TCGv_i64 tcg_tmp; | |
4981 | ||
4982 | /* Note that op_id is sf:op54:op31:o0 so it includes the 32/64 size flag */ | |
4983 | switch (op_id) { | |
4984 | case 0x42: /* SMADDL */ | |
4985 | case 0x43: /* SMSUBL */ | |
4986 | case 0x44: /* SMULH */ | |
4987 | is_signed = true; | |
4988 | break; | |
4989 | case 0x0: /* MADD (32bit) */ | |
4990 | case 0x1: /* MSUB (32bit) */ | |
4991 | case 0x40: /* MADD (64bit) */ | |
4992 | case 0x41: /* MSUB (64bit) */ | |
4993 | case 0x4a: /* UMADDL */ | |
4994 | case 0x4b: /* UMSUBL */ | |
4995 | case 0x4c: /* UMULH */ | |
4996 | break; | |
4997 | default: | |
4998 | unallocated_encoding(s); | |
4999 | return; | |
5000 | } | |
5001 | ||
5002 | if (is_high) { | |
5003 | TCGv_i64 low_bits = tcg_temp_new_i64(); /* low bits discarded */ | |
5004 | TCGv_i64 tcg_rd = cpu_reg(s, rd); | |
5005 | TCGv_i64 tcg_rn = cpu_reg(s, rn); | |
5006 | TCGv_i64 tcg_rm = cpu_reg(s, rm); | |
5007 | ||
5008 | if (is_signed) { | |
5009 | tcg_gen_muls2_i64(low_bits, tcg_rd, tcg_rn, tcg_rm); | |
5010 | } else { | |
5011 | tcg_gen_mulu2_i64(low_bits, tcg_rd, tcg_rn, tcg_rm); | |
5012 | } | |
5013 | ||
5014 | tcg_temp_free_i64(low_bits); | |
5015 | return; | |
5016 | } | |
5017 | ||
5018 | tcg_op1 = tcg_temp_new_i64(); | |
5019 | tcg_op2 = tcg_temp_new_i64(); | |
5020 | tcg_tmp = tcg_temp_new_i64(); | |
5021 | ||
5022 | if (op_id < 0x42) { | |
5023 | tcg_gen_mov_i64(tcg_op1, cpu_reg(s, rn)); | |
5024 | tcg_gen_mov_i64(tcg_op2, cpu_reg(s, rm)); | |
5025 | } else { | |
5026 | if (is_signed) { | |
5027 | tcg_gen_ext32s_i64(tcg_op1, cpu_reg(s, rn)); | |
5028 | tcg_gen_ext32s_i64(tcg_op2, cpu_reg(s, rm)); | |
5029 | } else { | |
5030 | tcg_gen_ext32u_i64(tcg_op1, cpu_reg(s, rn)); | |
5031 | tcg_gen_ext32u_i64(tcg_op2, cpu_reg(s, rm)); | |
5032 | } | |
5033 | } | |
5034 | ||
5035 | if (ra == 31 && !is_sub) { | |
5036 | /* Special-case MADD with rA == XZR; it is the standard MUL alias */ | |
5037 | tcg_gen_mul_i64(cpu_reg(s, rd), tcg_op1, tcg_op2); | |
5038 | } else { | |
5039 | tcg_gen_mul_i64(tcg_tmp, tcg_op1, tcg_op2); | |
5040 | if (is_sub) { | |
5041 | tcg_gen_sub_i64(cpu_reg(s, rd), cpu_reg(s, ra), tcg_tmp); | |
5042 | } else { | |
5043 | tcg_gen_add_i64(cpu_reg(s, rd), cpu_reg(s, ra), tcg_tmp); | |
5044 | } | |
5045 | } | |
5046 | ||
5047 | if (!sf) { | |
5048 | tcg_gen_ext32u_i64(cpu_reg(s, rd), cpu_reg(s, rd)); | |
5049 | } | |
5050 | ||
5051 | tcg_temp_free_i64(tcg_op1); | |
5052 | tcg_temp_free_i64(tcg_op2); | |
5053 | tcg_temp_free_i64(tcg_tmp); | |
ad7ee8a2 CF |
5054 | } |
5055 | ||
4ce31af4 | 5056 | /* Add/subtract (with carry) |
2fba34f7 RH |
5057 | * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 10 9 5 4 0 |
5058 | * +--+--+--+------------------------+------+-------------+------+-----+ | |
5059 | * |sf|op| S| 1 1 0 1 0 0 0 0 | rm | 0 0 0 0 0 0 | Rn | Rd | | |
5060 | * +--+--+--+------------------------+------+-------------+------+-----+ | |
643dbb07 CF |
5061 | */ |
5062 | ||
ad7ee8a2 CF |
5063 | static void disas_adc_sbc(DisasContext *s, uint32_t insn) |
5064 | { | |
643dbb07 CF |
5065 | unsigned int sf, op, setflags, rm, rn, rd; |
5066 | TCGv_i64 tcg_y, tcg_rn, tcg_rd; | |
5067 | ||
643dbb07 CF |
5068 | sf = extract32(insn, 31, 1); |
5069 | op = extract32(insn, 30, 1); | |
5070 | setflags = extract32(insn, 29, 1); | |
5071 | rm = extract32(insn, 16, 5); | |
5072 | rn = extract32(insn, 5, 5); | |
5073 | rd = extract32(insn, 0, 5); | |
5074 | ||
5075 | tcg_rd = cpu_reg(s, rd); | |
5076 | tcg_rn = cpu_reg(s, rn); | |
5077 | ||
5078 | if (op) { | |
5079 | tcg_y = new_tmp_a64(s); | |
5080 | tcg_gen_not_i64(tcg_y, cpu_reg(s, rm)); | |
5081 | } else { | |
5082 | tcg_y = cpu_reg(s, rm); | |
5083 | } | |
5084 | ||
5085 | if (setflags) { | |
5086 | gen_adc_CC(sf, tcg_rd, tcg_rn, tcg_y); | |
5087 | } else { | |
5088 | gen_adc(sf, tcg_rd, tcg_rn, tcg_y); | |
5089 | } | |
ad7ee8a2 CF |
5090 | } |
5091 | ||
b89d9c98 RH |
5092 | /* |
5093 | * Rotate right into flags | |
5094 | * 31 30 29 21 15 10 5 4 0 | |
5095 | * +--+--+--+-----------------+--------+-----------+------+--+------+ | |
5096 | * |sf|op| S| 1 1 0 1 0 0 0 0 | imm6 | 0 0 0 0 1 | Rn |o2| mask | | |
5097 | * +--+--+--+-----------------+--------+-----------+------+--+------+ | |
5098 | */ | |
5099 | static void disas_rotate_right_into_flags(DisasContext *s, uint32_t insn) | |
5100 | { | |
5101 | int mask = extract32(insn, 0, 4); | |
5102 | int o2 = extract32(insn, 4, 1); | |
5103 | int rn = extract32(insn, 5, 5); | |
5104 | int imm6 = extract32(insn, 15, 6); | |
5105 | int sf_op_s = extract32(insn, 29, 3); | |
5106 | TCGv_i64 tcg_rn; | |
5107 | TCGv_i32 nzcv; | |
5108 | ||
5109 | if (sf_op_s != 5 || o2 != 0 || !dc_isar_feature(aa64_condm_4, s)) { | |
5110 | unallocated_encoding(s); | |
5111 | return; | |
5112 | } | |
5113 | ||
5114 | tcg_rn = read_cpu_reg(s, rn, 1); | |
5115 | tcg_gen_rotri_i64(tcg_rn, tcg_rn, imm6); | |
5116 | ||
5117 | nzcv = tcg_temp_new_i32(); | |
5118 | tcg_gen_extrl_i64_i32(nzcv, tcg_rn); | |
5119 | ||
5120 | if (mask & 8) { /* N */ | |
5121 | tcg_gen_shli_i32(cpu_NF, nzcv, 31 - 3); | |
5122 | } | |
5123 | if (mask & 4) { /* Z */ | |
5124 | tcg_gen_not_i32(cpu_ZF, nzcv); | |
5125 | tcg_gen_andi_i32(cpu_ZF, cpu_ZF, 4); | |
5126 | } | |
5127 | if (mask & 2) { /* C */ | |
5128 | tcg_gen_extract_i32(cpu_CF, nzcv, 1, 1); | |
5129 | } | |
5130 | if (mask & 1) { /* V */ | |
5131 | tcg_gen_shli_i32(cpu_VF, nzcv, 31 - 0); | |
5132 | } | |
5133 | ||
5134 | tcg_temp_free_i32(nzcv); | |
5135 | } | |
5136 | ||
5137 | /* | |
5138 | * Evaluate into flags | |
5139 | * 31 30 29 21 15 14 10 5 4 0 | |
5140 | * +--+--+--+-----------------+---------+----+---------+------+--+------+ | |
5141 | * |sf|op| S| 1 1 0 1 0 0 0 0 | opcode2 | sz | 0 0 1 0 | Rn |o3| mask | | |
5142 | * +--+--+--+-----------------+---------+----+---------+------+--+------+ | |
5143 | */ | |
5144 | static void disas_evaluate_into_flags(DisasContext *s, uint32_t insn) | |
5145 | { | |
5146 | int o3_mask = extract32(insn, 0, 5); | |
5147 | int rn = extract32(insn, 5, 5); | |
5148 | int o2 = extract32(insn, 15, 6); | |
5149 | int sz = extract32(insn, 14, 1); | |
5150 | int sf_op_s = extract32(insn, 29, 3); | |
5151 | TCGv_i32 tmp; | |
5152 | int shift; | |
5153 | ||
5154 | if (sf_op_s != 1 || o2 != 0 || o3_mask != 0xd || | |
5155 | !dc_isar_feature(aa64_condm_4, s)) { | |
5156 | unallocated_encoding(s); | |
5157 | return; | |
5158 | } | |
5159 | shift = sz ? 16 : 24; /* SETF16 or SETF8 */ | |
5160 | ||
5161 | tmp = tcg_temp_new_i32(); | |
5162 | tcg_gen_extrl_i64_i32(tmp, cpu_reg(s, rn)); | |
5163 | tcg_gen_shli_i32(cpu_NF, tmp, shift); | |
5164 | tcg_gen_shli_i32(cpu_VF, tmp, shift - 1); | |
5165 | tcg_gen_mov_i32(cpu_ZF, cpu_NF); | |
5166 | tcg_gen_xor_i32(cpu_VF, cpu_VF, cpu_NF); | |
5167 | tcg_temp_free_i32(tmp); | |
5168 | } | |
5169 | ||
4ce31af4 | 5170 | /* Conditional compare (immediate / register) |
750813cf CF |
5171 | * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0 |
5172 | * +--+--+--+------------------------+--------+------+----+--+------+--+-----+ | |
5173 | * |sf|op| S| 1 1 0 1 0 0 1 0 |imm5/rm | cond |i/r |o2| Rn |o3|nzcv | | |
5174 | * +--+--+--+------------------------+--------+------+----+--+------+--+-----+ | |
5175 | * [1] y [0] [0] | |
5176 | */ | |
5177 | static void disas_cc(DisasContext *s, uint32_t insn) | |
ad7ee8a2 | 5178 | { |
750813cf | 5179 | unsigned int sf, op, y, cond, rn, nzcv, is_imm; |
7dd03d77 | 5180 | TCGv_i32 tcg_t0, tcg_t1, tcg_t2; |
750813cf | 5181 | TCGv_i64 tcg_tmp, tcg_y, tcg_rn; |
7dd03d77 | 5182 | DisasCompare c; |
ad7ee8a2 | 5183 | |
750813cf CF |
5184 | if (!extract32(insn, 29, 1)) { |
5185 | unallocated_encoding(s); | |
5186 | return; | |
5187 | } | |
5188 | if (insn & (1 << 10 | 1 << 4)) { | |
5189 | unallocated_encoding(s); | |
5190 | return; | |
5191 | } | |
5192 | sf = extract32(insn, 31, 1); | |
5193 | op = extract32(insn, 30, 1); | |
5194 | is_imm = extract32(insn, 11, 1); | |
5195 | y = extract32(insn, 16, 5); /* y = rm (reg) or imm5 (imm) */ | |
5196 | cond = extract32(insn, 12, 4); | |
5197 | rn = extract32(insn, 5, 5); | |
5198 | nzcv = extract32(insn, 0, 4); | |
5199 | ||
7dd03d77 RH |
5200 | /* Set T0 = !COND. */ |
5201 | tcg_t0 = tcg_temp_new_i32(); | |
5202 | arm_test_cc(&c, cond); | |
5203 | tcg_gen_setcondi_i32(tcg_invert_cond(c.cond), tcg_t0, c.value, 0); | |
5204 | arm_free_cc(&c); | |
5205 | ||
5206 | /* Load the arguments for the new comparison. */ | |
750813cf CF |
5207 | if (is_imm) { |
5208 | tcg_y = new_tmp_a64(s); | |
5209 | tcg_gen_movi_i64(tcg_y, y); | |
5210 | } else { | |
5211 | tcg_y = cpu_reg(s, y); | |
5212 | } | |
5213 | tcg_rn = cpu_reg(s, rn); | |
5214 | ||
7dd03d77 | 5215 | /* Set the flags for the new comparison. */ |
750813cf CF |
5216 | tcg_tmp = tcg_temp_new_i64(); |
5217 | if (op) { | |
5218 | gen_sub_CC(sf, tcg_tmp, tcg_rn, tcg_y); | |
5219 | } else { | |
5220 | gen_add_CC(sf, tcg_tmp, tcg_rn, tcg_y); | |
5221 | } | |
5222 | tcg_temp_free_i64(tcg_tmp); | |
5223 | ||
7dd03d77 RH |
5224 | /* If COND was false, force the flags to #nzcv. Compute two masks |
5225 | * to help with this: T1 = (COND ? 0 : -1), T2 = (COND ? -1 : 0). | |
5226 | * For tcg hosts that support ANDC, we can make do with just T1. | |
5227 | * In either case, allow the tcg optimizer to delete any unused mask. | |
5228 | */ | |
5229 | tcg_t1 = tcg_temp_new_i32(); | |
5230 | tcg_t2 = tcg_temp_new_i32(); | |
5231 | tcg_gen_neg_i32(tcg_t1, tcg_t0); | |
5232 | tcg_gen_subi_i32(tcg_t2, tcg_t0, 1); | |
5233 | ||
5234 | if (nzcv & 8) { /* N */ | |
5235 | tcg_gen_or_i32(cpu_NF, cpu_NF, tcg_t1); | |
5236 | } else { | |
5237 | if (TCG_TARGET_HAS_andc_i32) { | |
5238 | tcg_gen_andc_i32(cpu_NF, cpu_NF, tcg_t1); | |
5239 | } else { | |
5240 | tcg_gen_and_i32(cpu_NF, cpu_NF, tcg_t2); | |
5241 | } | |
5242 | } | |
5243 | if (nzcv & 4) { /* Z */ | |
5244 | if (TCG_TARGET_HAS_andc_i32) { | |
5245 | tcg_gen_andc_i32(cpu_ZF, cpu_ZF, tcg_t1); | |
5246 | } else { | |
5247 | tcg_gen_and_i32(cpu_ZF, cpu_ZF, tcg_t2); | |
5248 | } | |
5249 | } else { | |
5250 | tcg_gen_or_i32(cpu_ZF, cpu_ZF, tcg_t0); | |
5251 | } | |
5252 | if (nzcv & 2) { /* C */ | |
5253 | tcg_gen_or_i32(cpu_CF, cpu_CF, tcg_t0); | |
5254 | } else { | |
5255 | if (TCG_TARGET_HAS_andc_i32) { | |
5256 | tcg_gen_andc_i32(cpu_CF, cpu_CF, tcg_t1); | |
5257 | } else { | |
5258 | tcg_gen_and_i32(cpu_CF, cpu_CF, tcg_t2); | |
5259 | } | |
5260 | } | |
5261 | if (nzcv & 1) { /* V */ | |
5262 | tcg_gen_or_i32(cpu_VF, cpu_VF, tcg_t1); | |
5263 | } else { | |
5264 | if (TCG_TARGET_HAS_andc_i32) { | |
5265 | tcg_gen_andc_i32(cpu_VF, cpu_VF, tcg_t1); | |
5266 | } else { | |
5267 | tcg_gen_and_i32(cpu_VF, cpu_VF, tcg_t2); | |
5268 | } | |
750813cf | 5269 | } |
7dd03d77 RH |
5270 | tcg_temp_free_i32(tcg_t0); |
5271 | tcg_temp_free_i32(tcg_t1); | |
5272 | tcg_temp_free_i32(tcg_t2); | |
ad7ee8a2 CF |
5273 | } |
5274 | ||
4ce31af4 | 5275 | /* Conditional select |
e952d8c7 CF |
5276 | * 31 30 29 28 21 20 16 15 12 11 10 9 5 4 0 |
5277 | * +----+----+---+-----------------+------+------+-----+------+------+ | |
5278 | * | sf | op | S | 1 1 0 1 0 1 0 0 | Rm | cond | op2 | Rn | Rd | | |
5279 | * +----+----+---+-----------------+------+------+-----+------+------+ | |
5280 | */ | |
ad7ee8a2 CF |
5281 | static void disas_cond_select(DisasContext *s, uint32_t insn) |
5282 | { | |
e952d8c7 | 5283 | unsigned int sf, else_inv, rm, cond, else_inc, rn, rd; |
259cb684 RH |
5284 | TCGv_i64 tcg_rd, zero; |
5285 | DisasCompare64 c; | |
e952d8c7 CF |
5286 | |
5287 | if (extract32(insn, 29, 1) || extract32(insn, 11, 1)) { | |
5288 | /* S == 1 or op2<1> == 1 */ | |
5289 | unallocated_encoding(s); | |
5290 | return; | |
5291 | } | |
5292 | sf = extract32(insn, 31, 1); | |
5293 | else_inv = extract32(insn, 30, 1); | |
5294 | rm = extract32(insn, 16, 5); | |
5295 | cond = extract32(insn, 12, 4); | |
5296 | else_inc = extract32(insn, 10, 1); | |
5297 | rn = extract32(insn, 5, 5); | |
5298 | rd = extract32(insn, 0, 5); | |
5299 | ||
e952d8c7 CF |
5300 | tcg_rd = cpu_reg(s, rd); |
5301 | ||
259cb684 RH |
5302 | a64_test_cc(&c, cond); |
5303 | zero = tcg_const_i64(0); | |
e952d8c7 | 5304 | |
259cb684 RH |
5305 | if (rn == 31 && rm == 31 && (else_inc ^ else_inv)) { |
5306 | /* CSET & CSETM. */ | |
5307 | tcg_gen_setcond_i64(tcg_invert_cond(c.cond), tcg_rd, c.value, zero); | |
5308 | if (else_inv) { | |
5309 | tcg_gen_neg_i64(tcg_rd, tcg_rd); | |
5310 | } | |
5311 | } else { | |
5312 | TCGv_i64 t_true = cpu_reg(s, rn); | |
5313 | TCGv_i64 t_false = read_cpu_reg(s, rm, 1); | |
e952d8c7 | 5314 | if (else_inv && else_inc) { |
259cb684 | 5315 | tcg_gen_neg_i64(t_false, t_false); |
e952d8c7 | 5316 | } else if (else_inv) { |
259cb684 | 5317 | tcg_gen_not_i64(t_false, t_false); |
e952d8c7 | 5318 | } else if (else_inc) { |
259cb684 | 5319 | tcg_gen_addi_i64(t_false, t_false, 1); |
e952d8c7 | 5320 | } |
259cb684 RH |
5321 | tcg_gen_movcond_i64(c.cond, tcg_rd, c.value, zero, t_true, t_false); |
5322 | } | |
5323 | ||
5324 | tcg_temp_free_i64(zero); | |
5325 | a64_free_cc(&c); | |
5326 | ||
5327 | if (!sf) { | |
5328 | tcg_gen_ext32u_i64(tcg_rd, tcg_rd); | |
e952d8c7 | 5329 | } |
ad7ee8a2 CF |
5330 | } |
5331 | ||
680ead21 CF |
5332 | static void handle_clz(DisasContext *s, unsigned int sf, |
5333 | unsigned int rn, unsigned int rd) | |
5334 | { | |
5335 | TCGv_i64 tcg_rd, tcg_rn; | |
5336 | tcg_rd = cpu_reg(s, rd); | |
5337 | tcg_rn = cpu_reg(s, rn); | |
5338 | ||
5339 | if (sf) { | |
7539a012 | 5340 | tcg_gen_clzi_i64(tcg_rd, tcg_rn, 64); |
680ead21 CF |
5341 | } else { |
5342 | TCGv_i32 tcg_tmp32 = tcg_temp_new_i32(); | |
ecc7b3aa | 5343 | tcg_gen_extrl_i64_i32(tcg_tmp32, tcg_rn); |
7539a012 | 5344 | tcg_gen_clzi_i32(tcg_tmp32, tcg_tmp32, 32); |
680ead21 CF |
5345 | tcg_gen_extu_i32_i64(tcg_rd, tcg_tmp32); |
5346 | tcg_temp_free_i32(tcg_tmp32); | |
5347 | } | |
5348 | } | |
5349 | ||
e80c5020 CF |
5350 | static void handle_cls(DisasContext *s, unsigned int sf, |
5351 | unsigned int rn, unsigned int rd) | |
5352 | { | |
5353 | TCGv_i64 tcg_rd, tcg_rn; | |
5354 | tcg_rd = cpu_reg(s, rd); | |
5355 | tcg_rn = cpu_reg(s, rn); | |
5356 | ||
5357 | if (sf) { | |
bc21dbcc | 5358 | tcg_gen_clrsb_i64(tcg_rd, tcg_rn); |
e80c5020 CF |
5359 | } else { |
5360 | TCGv_i32 tcg_tmp32 = tcg_temp_new_i32(); | |
ecc7b3aa | 5361 | tcg_gen_extrl_i64_i32(tcg_tmp32, tcg_rn); |
bc21dbcc | 5362 | tcg_gen_clrsb_i32(tcg_tmp32, tcg_tmp32); |
e80c5020 CF |
5363 | tcg_gen_extu_i32_i64(tcg_rd, tcg_tmp32); |
5364 | tcg_temp_free_i32(tcg_tmp32); | |
5365 | } | |
5366 | } | |
5367 | ||
82e14b02 AG |
5368 | static void handle_rbit(DisasContext *s, unsigned int sf, |
5369 | unsigned int rn, unsigned int rd) | |
5370 | { | |
5371 | TCGv_i64 tcg_rd, tcg_rn; | |
5372 | tcg_rd = cpu_reg(s, rd); | |
5373 | tcg_rn = cpu_reg(s, rn); | |
5374 | ||
5375 | if (sf) { | |
5376 | gen_helper_rbit64(tcg_rd, tcg_rn); | |
5377 | } else { | |
5378 | TCGv_i32 tcg_tmp32 = tcg_temp_new_i32(); | |
ecc7b3aa | 5379 | tcg_gen_extrl_i64_i32(tcg_tmp32, tcg_rn); |
82e14b02 AG |
5380 | gen_helper_rbit(tcg_tmp32, tcg_tmp32); |
5381 | tcg_gen_extu_i32_i64(tcg_rd, tcg_tmp32); | |
5382 | tcg_temp_free_i32(tcg_tmp32); | |
5383 | } | |
5384 | } | |
5385 | ||
4ce31af4 | 5386 | /* REV with sf==1, opcode==3 ("REV64") */ |
45323209 CF |
5387 | static void handle_rev64(DisasContext *s, unsigned int sf, |
5388 | unsigned int rn, unsigned int rd) | |
5389 | { | |
5390 | if (!sf) { | |
5391 | unallocated_encoding(s); | |
5392 | return; | |
5393 | } | |
5394 | tcg_gen_bswap64_i64(cpu_reg(s, rd), cpu_reg(s, rn)); | |
5395 | } | |
5396 | ||
4ce31af4 PM |
5397 | /* REV with sf==0, opcode==2 |
5398 | * REV32 (sf==1, opcode==2) | |
45323209 CF |
5399 | */ |
5400 | static void handle_rev32(DisasContext *s, unsigned int sf, | |
5401 | unsigned int rn, unsigned int rd) | |
5402 | { | |
5403 | TCGv_i64 tcg_rd = cpu_reg(s, rd); | |
5404 | ||
5405 | if (sf) { | |
5406 | TCGv_i64 tcg_tmp = tcg_temp_new_i64(); | |
5407 | TCGv_i64 tcg_rn = read_cpu_reg(s, rn, sf); | |
5408 | ||
5409 | /* bswap32_i64 requires zero high word */ | |
5410 | tcg_gen_ext32u_i64(tcg_tmp, tcg_rn); | |
5411 | tcg_gen_bswap32_i64(tcg_rd, tcg_tmp); | |
5412 | tcg_gen_shri_i64(tcg_tmp, tcg_rn, 32); | |
5413 | tcg_gen_bswap32_i64(tcg_tmp, tcg_tmp); | |
5414 | tcg_gen_concat32_i64(tcg_rd, tcg_rd, tcg_tmp); | |
5415 | ||
5416 | tcg_temp_free_i64(tcg_tmp); | |
5417 | } else { | |
5418 | tcg_gen_ext32u_i64(tcg_rd, cpu_reg(s, rn)); | |
5419 | tcg_gen_bswap32_i64(tcg_rd, tcg_rd); | |
5420 | } | |
5421 | } | |
5422 | ||
4ce31af4 | 5423 | /* REV16 (opcode==1) */ |
45323209 CF |
5424 | static void handle_rev16(DisasContext *s, unsigned int sf, |
5425 | unsigned int rn, unsigned int rd) | |
5426 | { | |
5427 | TCGv_i64 tcg_rd = cpu_reg(s, rd); | |
5428 | TCGv_i64 tcg_tmp = tcg_temp_new_i64(); | |
5429 | TCGv_i64 tcg_rn = read_cpu_reg(s, rn, sf); | |
abb1066d | 5430 | TCGv_i64 mask = tcg_const_i64(sf ? 0x00ff00ff00ff00ffull : 0x00ff00ff); |
45323209 | 5431 | |
abb1066d RH |
5432 | tcg_gen_shri_i64(tcg_tmp, tcg_rn, 8); |
5433 | tcg_gen_and_i64(tcg_rd, tcg_rn, mask); | |
5434 | tcg_gen_and_i64(tcg_tmp, tcg_tmp, mask); | |
5435 | tcg_gen_shli_i64(tcg_rd, tcg_rd, 8); | |
5436 | tcg_gen_or_i64(tcg_rd, tcg_rd, tcg_tmp); | |
45323209 | 5437 | |
e4256c3c | 5438 | tcg_temp_free_i64(mask); |
45323209 CF |
5439 | tcg_temp_free_i64(tcg_tmp); |
5440 | } | |
5441 | ||
4ce31af4 | 5442 | /* Data-processing (1 source) |
680ead21 CF |
5443 | * 31 30 29 28 21 20 16 15 10 9 5 4 0 |
5444 | * +----+---+---+-----------------+---------+--------+------+------+ | |
5445 | * | sf | 1 | S | 1 1 0 1 0 1 1 0 | opcode2 | opcode | Rn | Rd | | |
5446 | * +----+---+---+-----------------+---------+--------+------+------+ | |
5447 | */ | |
ad7ee8a2 CF |
5448 | static void disas_data_proc_1src(DisasContext *s, uint32_t insn) |
5449 | { | |
18de2813 | 5450 | unsigned int sf, opcode, opcode2, rn, rd; |
95ebd99d | 5451 | TCGv_i64 tcg_rd; |
680ead21 | 5452 | |
18de2813 | 5453 | if (extract32(insn, 29, 1)) { |
680ead21 CF |
5454 | unallocated_encoding(s); |
5455 | return; | |
5456 | } | |
5457 | ||
5458 | sf = extract32(insn, 31, 1); | |
5459 | opcode = extract32(insn, 10, 6); | |
18de2813 | 5460 | opcode2 = extract32(insn, 16, 5); |
680ead21 CF |
5461 | rn = extract32(insn, 5, 5); |
5462 | rd = extract32(insn, 0, 5); | |
5463 | ||
18de2813 RH |
5464 | #define MAP(SF, O2, O1) ((SF) | (O1 << 1) | (O2 << 7)) |
5465 | ||
5466 | switch (MAP(sf, opcode2, opcode)) { | |
5467 | case MAP(0, 0x00, 0x00): /* RBIT */ | |
5468 | case MAP(1, 0x00, 0x00): | |
82e14b02 AG |
5469 | handle_rbit(s, sf, rn, rd); |
5470 | break; | |
18de2813 RH |
5471 | case MAP(0, 0x00, 0x01): /* REV16 */ |
5472 | case MAP(1, 0x00, 0x01): | |
45323209 CF |
5473 | handle_rev16(s, sf, rn, rd); |
5474 | break; | |
18de2813 RH |
5475 | case MAP(0, 0x00, 0x02): /* REV/REV32 */ |
5476 | case MAP(1, 0x00, 0x02): | |
45323209 CF |
5477 | handle_rev32(s, sf, rn, rd); |
5478 | break; | |
18de2813 | 5479 | case MAP(1, 0x00, 0x03): /* REV64 */ |
45323209 | 5480 | handle_rev64(s, sf, rn, rd); |
680ead21 | 5481 | break; |
18de2813 RH |
5482 | case MAP(0, 0x00, 0x04): /* CLZ */ |
5483 | case MAP(1, 0x00, 0x04): | |
680ead21 CF |
5484 | handle_clz(s, sf, rn, rd); |
5485 | break; | |
18de2813 RH |
5486 | case MAP(0, 0x00, 0x05): /* CLS */ |
5487 | case MAP(1, 0x00, 0x05): | |
e80c5020 | 5488 | handle_cls(s, sf, rn, rd); |
680ead21 | 5489 | break; |
95ebd99d RH |
5490 | case MAP(1, 0x01, 0x00): /* PACIA */ |
5491 | if (s->pauth_active) { | |
5492 | tcg_rd = cpu_reg(s, rd); | |
5493 | gen_helper_pacia(tcg_rd, cpu_env, tcg_rd, cpu_reg_sp(s, rn)); | |
5494 | } else if (!dc_isar_feature(aa64_pauth, s)) { | |
5495 | goto do_unallocated; | |
5496 | } | |
5497 | break; | |
5498 | case MAP(1, 0x01, 0x01): /* PACIB */ | |
5499 | if (s->pauth_active) { | |
5500 | tcg_rd = cpu_reg(s, rd); | |
5501 | gen_helper_pacib(tcg_rd, cpu_env, tcg_rd, cpu_reg_sp(s, rn)); | |
5502 | } else if (!dc_isar_feature(aa64_pauth, s)) { | |
5503 | goto do_unallocated; | |
5504 | } | |
5505 | break; | |
5506 | case MAP(1, 0x01, 0x02): /* PACDA */ | |
5507 | if (s->pauth_active) { | |
5508 | tcg_rd = cpu_reg(s, rd); | |
5509 | gen_helper_pacda(tcg_rd, cpu_env, tcg_rd, cpu_reg_sp(s, rn)); | |
5510 | } else if (!dc_isar_feature(aa64_pauth, s)) { | |
5511 | goto do_unallocated; | |
5512 | } | |
5513 | break; | |
5514 | case MAP(1, 0x01, 0x03): /* PACDB */ | |
5515 | if (s->pauth_active) { | |
5516 | tcg_rd = cpu_reg(s, rd); | |
5517 | gen_helper_pacdb(tcg_rd, cpu_env, tcg_rd, cpu_reg_sp(s, rn)); | |
5518 | } else if (!dc_isar_feature(aa64_pauth, s)) { | |
5519 | goto do_unallocated; | |
5520 | } | |
5521 | break; | |
5522 | case MAP(1, 0x01, 0x04): /* AUTIA */ | |
5523 | if (s->pauth_active) { | |
5524 | tcg_rd = cpu_reg(s, rd); | |
5525 | gen_helper_autia(tcg_rd, cpu_env, tcg_rd, cpu_reg_sp(s, rn)); | |
5526 | } else if (!dc_isar_feature(aa64_pauth, s)) { | |
5527 | goto do_unallocated; | |
5528 | } | |
5529 | break; | |
5530 | case MAP(1, 0x01, 0x05): /* AUTIB */ | |
5531 | if (s->pauth_active) { | |
5532 | tcg_rd = cpu_reg(s, rd); | |
5533 | gen_helper_autib(tcg_rd, cpu_env, tcg_rd, cpu_reg_sp(s, rn)); | |
5534 | } else if (!dc_isar_feature(aa64_pauth, s)) { | |
5535 | goto do_unallocated; | |
5536 | } | |
5537 | break; | |
5538 | case MAP(1, 0x01, 0x06): /* AUTDA */ | |
5539 | if (s->pauth_active) { | |
5540 | tcg_rd = cpu_reg(s, rd); | |
5541 | gen_helper_autda(tcg_rd, cpu_env, tcg_rd, cpu_reg_sp(s, rn)); | |
5542 | } else if (!dc_isar_feature(aa64_pauth, s)) { | |
5543 | goto do_unallocated; | |
5544 | } | |
5545 | break; | |
5546 | case MAP(1, 0x01, 0x07): /* AUTDB */ | |
5547 | if (s->pauth_active) { | |
5548 | tcg_rd = cpu_reg(s, rd); | |
5549 | gen_helper_autdb(tcg_rd, cpu_env, tcg_rd, cpu_reg_sp(s, rn)); | |
5550 | } else if (!dc_isar_feature(aa64_pauth, s)) { | |
5551 | goto do_unallocated; | |
5552 | } | |
5553 | break; | |
5554 | case MAP(1, 0x01, 0x08): /* PACIZA */ | |
5555 | if (!dc_isar_feature(aa64_pauth, s) || rn != 31) { | |
5556 | goto do_unallocated; | |
5557 | } else if (s->pauth_active) { | |
5558 | tcg_rd = cpu_reg(s, rd); | |
5559 | gen_helper_pacia(tcg_rd, cpu_env, tcg_rd, new_tmp_a64_zero(s)); | |
5560 | } | |
5561 | break; | |
5562 | case MAP(1, 0x01, 0x09): /* PACIZB */ | |
5563 | if (!dc_isar_feature(aa64_pauth, s) || rn != 31) { | |
5564 | goto do_unallocated; | |
5565 | } else if (s->pauth_active) { | |
5566 | tcg_rd = cpu_reg(s, rd); | |
5567 | gen_helper_pacib(tcg_rd, cpu_env, tcg_rd, new_tmp_a64_zero(s)); | |
5568 | } | |
5569 | break; | |
5570 | case MAP(1, 0x01, 0x0a): /* PACDZA */ | |
5571 | if (!dc_isar_feature(aa64_pauth, s) || rn != 31) { | |
5572 | goto do_unallocated; | |
5573 | } else if (s->pauth_active) { | |
5574 | tcg_rd = cpu_reg(s, rd); | |
5575 | gen_helper_pacda(tcg_rd, cpu_env, tcg_rd, new_tmp_a64_zero(s)); | |
5576 | } | |
5577 | break; | |
5578 | case MAP(1, 0x01, 0x0b): /* PACDZB */ | |
5579 | if (!dc_isar_feature(aa64_pauth, s) || rn != 31) { | |
5580 | goto do_unallocated; | |
5581 | } else if (s->pauth_active) { | |
5582 | tcg_rd = cpu_reg(s, rd); | |
5583 | gen_helper_pacdb(tcg_rd, cpu_env, tcg_rd, new_tmp_a64_zero(s)); | |
5584 | } | |
5585 | break; | |
5586 | case MAP(1, 0x01, 0x0c): /* AUTIZA */ | |
5587 | if (!dc_isar_feature(aa64_pauth, s) || rn != 31) { | |
5588 | goto do_unallocated; | |
5589 | } else if (s->pauth_active) { | |
5590 | tcg_rd = cpu_reg(s, rd); | |
5591 | gen_helper_autia(tcg_rd, cpu_env, tcg_rd, new_tmp_a64_zero(s)); | |
5592 | } | |
5593 | break; | |
5594 | case MAP(1, 0x01, 0x0d): /* AUTIZB */ | |
5595 | if (!dc_isar_feature(aa64_pauth, s) || rn != 31) { | |
5596 | goto do_unallocated; | |
5597 | } else if (s->pauth_active) { | |
5598 | tcg_rd = cpu_reg(s, rd); | |
5599 | gen_helper_autib(tcg_rd, cpu_env, tcg_rd, new_tmp_a64_zero(s)); | |
5600 | } | |
5601 | break; | |
5602 | case MAP(1, 0x01, 0x0e): /* AUTDZA */ | |
5603 | if (!dc_isar_feature(aa64_pauth, s) || rn != 31) { | |
5604 | goto do_unallocated; | |
5605 | } else if (s->pauth_active) { | |
5606 | tcg_rd = cpu_reg(s, rd); | |
5607 | gen_helper_autda(tcg_rd, cpu_env, tcg_rd, new_tmp_a64_zero(s)); | |
5608 | } | |
5609 | break; | |
5610 | case MAP(1, 0x01, 0x0f): /* AUTDZB */ | |
5611 | if (!dc_isar_feature(aa64_pauth, s) || rn != 31) { | |
5612 | goto do_unallocated; | |
5613 | } else if (s->pauth_active) { | |
5614 | tcg_rd = cpu_reg(s, rd); | |
5615 | gen_helper_autdb(tcg_rd, cpu_env, tcg_rd, new_tmp_a64_zero(s)); | |
5616 | } | |
5617 | break; | |
5618 | case MAP(1, 0x01, 0x10): /* XPACI */ | |
5619 | if (!dc_isar_feature(aa64_pauth, s) || rn != 31) { | |
5620 | goto do_unallocated; | |
5621 | } else if (s->pauth_active) { | |
5622 | tcg_rd = cpu_reg(s, rd); | |
5623 | gen_helper_xpaci(tcg_rd, cpu_env, tcg_rd); | |
5624 | } | |
5625 | break; | |
5626 | case MAP(1, 0x01, 0x11): /* XPACD */ | |
5627 | if (!dc_isar_feature(aa64_pauth, s) || rn != 31) { | |
5628 | goto do_unallocated; | |
5629 | } else if (s->pauth_active) { | |
5630 | tcg_rd = cpu_reg(s, rd); | |
5631 | gen_helper_xpacd(tcg_rd, cpu_env, tcg_rd); | |
5632 | } | |
5633 | break; | |
18de2813 | 5634 | default: |
95ebd99d | 5635 | do_unallocated: |
18de2813 RH |
5636 | unallocated_encoding(s); |
5637 | break; | |
680ead21 | 5638 | } |
18de2813 RH |
5639 | |
5640 | #undef MAP | |
ad7ee8a2 CF |
5641 | } |
5642 | ||
8220e911 AG |
5643 | static void handle_div(DisasContext *s, bool is_signed, unsigned int sf, |
5644 | unsigned int rm, unsigned int rn, unsigned int rd) | |
5645 | { | |
5646 | TCGv_i64 tcg_n, tcg_m, tcg_rd; | |
5647 | tcg_rd = cpu_reg(s, rd); | |
5648 | ||
5649 | if (!sf && is_signed) { | |
5650 | tcg_n = new_tmp_a64(s); | |
5651 | tcg_m = new_tmp_a64(s); | |
5652 | tcg_gen_ext32s_i64(tcg_n, cpu_reg(s, rn)); | |
5653 | tcg_gen_ext32s_i64(tcg_m, cpu_reg(s, rm)); | |
5654 | } else { | |
5655 | tcg_n = read_cpu_reg(s, rn, sf); | |
5656 | tcg_m = read_cpu_reg(s, rm, sf); | |
5657 | } | |
5658 | ||
5659 | if (is_signed) { | |
5660 | gen_helper_sdiv64(tcg_rd, tcg_n, tcg_m); | |
5661 | } else { | |
5662 | gen_helper_udiv64(tcg_rd, tcg_n, tcg_m); | |
5663 | } | |
5664 | ||
5665 | if (!sf) { /* zero extend final result */ | |
5666 | tcg_gen_ext32u_i64(tcg_rd, tcg_rd); | |
5667 | } | |
5668 | } | |
5669 | ||
4ce31af4 | 5670 | /* LSLV, LSRV, ASRV, RORV */ |
6c1adc91 AG |
5671 | static void handle_shift_reg(DisasContext *s, |
5672 | enum a64_shift_type shift_type, unsigned int sf, | |
5673 | unsigned int rm, unsigned int rn, unsigned int rd) | |
5674 | { | |
5675 | TCGv_i64 tcg_shift = tcg_temp_new_i64(); | |
5676 | TCGv_i64 tcg_rd = cpu_reg(s, rd); | |
5677 | TCGv_i64 tcg_rn = read_cpu_reg(s, rn, sf); | |
5678 | ||
5679 | tcg_gen_andi_i64(tcg_shift, cpu_reg(s, rm), sf ? 63 : 31); | |
5680 | shift_reg(tcg_rd, tcg_rn, sf, shift_type, tcg_shift); | |
5681 | tcg_temp_free_i64(tcg_shift); | |
5682 | } | |
5683 | ||
130f2e7d PM |
5684 | /* CRC32[BHWX], CRC32C[BHWX] */ |
5685 | static void handle_crc32(DisasContext *s, | |
5686 | unsigned int sf, unsigned int sz, bool crc32c, | |
5687 | unsigned int rm, unsigned int rn, unsigned int rd) | |
5688 | { | |
5689 | TCGv_i64 tcg_acc, tcg_val; | |
5690 | TCGv_i32 tcg_bytes; | |
5691 | ||
962fcbf2 | 5692 | if (!dc_isar_feature(aa64_crc32, s) |
130f2e7d PM |
5693 | || (sf == 1 && sz != 3) |
5694 | || (sf == 0 && sz == 3)) { | |
5695 | unallocated_encoding(s); | |
5696 | return; | |
5697 | } | |
5698 | ||
5699 | if (sz == 3) { | |
5700 | tcg_val = cpu_reg(s, rm); | |
5701 | } else { | |
5702 | uint64_t mask; | |
5703 | switch (sz) { | |
5704 | case 0: | |
5705 | mask = 0xFF; | |
5706 | break; | |
5707 | case 1: | |
5708 | mask = 0xFFFF; | |
5709 | break; | |
5710 | case 2: | |
5711 | mask = 0xFFFFFFFF; | |
5712 | break; | |
5713 | default: | |
5714 | g_assert_not_reached(); | |
5715 | } | |
5716 | tcg_val = new_tmp_a64(s); | |
5717 | tcg_gen_andi_i64(tcg_val, cpu_reg(s, rm), mask); | |
5718 | } | |
5719 | ||
5720 | tcg_acc = cpu_reg(s, rn); | |
5721 | tcg_bytes = tcg_const_i32(1 << sz); | |
5722 | ||
5723 | if (crc32c) { | |
5724 | gen_helper_crc32c_64(cpu_reg(s, rd), tcg_acc, tcg_val, tcg_bytes); | |
5725 | } else { | |
5726 | gen_helper_crc32_64(cpu_reg(s, rd), tcg_acc, tcg_val, tcg_bytes); | |
5727 | } | |
5728 | ||
5729 | tcg_temp_free_i32(tcg_bytes); | |
5730 | } | |
5731 | ||
4ce31af4 | 5732 | /* Data-processing (2 source) |
8220e911 AG |
5733 | * 31 30 29 28 21 20 16 15 10 9 5 4 0 |
5734 | * +----+---+---+-----------------+------+--------+------+------+ | |
5735 | * | sf | 0 | S | 1 1 0 1 0 1 1 0 | Rm | opcode | Rn | Rd | | |
5736 | * +----+---+---+-----------------+------+--------+------+------+ | |
5737 | */ | |
ad7ee8a2 CF |
5738 | static void disas_data_proc_2src(DisasContext *s, uint32_t insn) |
5739 | { | |
dad3015f | 5740 | unsigned int sf, rm, opcode, rn, rd, setflag; |
8220e911 | 5741 | sf = extract32(insn, 31, 1); |
dad3015f | 5742 | setflag = extract32(insn, 29, 1); |
8220e911 AG |
5743 | rm = extract32(insn, 16, 5); |
5744 | opcode = extract32(insn, 10, 6); | |
5745 | rn = extract32(insn, 5, 5); | |
5746 | rd = extract32(insn, 0, 5); | |
5747 | ||
dad3015f | 5748 | if (setflag && opcode != 0) { |
8220e911 AG |
5749 | unallocated_encoding(s); |
5750 | return; | |
5751 | } | |
5752 | ||
5753 | switch (opcode) { | |
dad3015f RH |
5754 | case 0: /* SUBP(S) */ |
5755 | if (sf == 0 || !dc_isar_feature(aa64_mte_insn_reg, s)) { | |
5756 | goto do_unallocated; | |
5757 | } else { | |
5758 | TCGv_i64 tcg_n, tcg_m, tcg_d; | |
5759 | ||
5760 | tcg_n = read_cpu_reg_sp(s, rn, true); | |
5761 | tcg_m = read_cpu_reg_sp(s, rm, true); | |
5762 | tcg_gen_sextract_i64(tcg_n, tcg_n, 0, 56); | |
5763 | tcg_gen_sextract_i64(tcg_m, tcg_m, 0, 56); | |
5764 | tcg_d = cpu_reg(s, rd); | |
5765 | ||
5766 | if (setflag) { | |
5767 | gen_sub_CC(true, tcg_d, tcg_n, tcg_m); | |
5768 | } else { | |
5769 | tcg_gen_sub_i64(tcg_d, tcg_n, tcg_m); | |
5770 | } | |
5771 | } | |
5772 | break; | |
8220e911 AG |
5773 | case 2: /* UDIV */ |
5774 | handle_div(s, false, sf, rm, rn, rd); | |
5775 | break; | |
5776 | case 3: /* SDIV */ | |
5777 | handle_div(s, true, sf, rm, rn, rd); | |
5778 | break; | |
da54941f RH |
5779 | case 4: /* IRG */ |
5780 | if (sf == 0 || !dc_isar_feature(aa64_mte_insn_reg, s)) { | |
5781 | goto do_unallocated; | |
5782 | } | |
5783 | if (s->ata) { | |
5784 | gen_helper_irg(cpu_reg_sp(s, rd), cpu_env, | |
5785 | cpu_reg_sp(s, rn), cpu_reg(s, rm)); | |
5786 | } else { | |
5787 | gen_address_with_allocation_tag0(cpu_reg_sp(s, rd), | |
5788 | cpu_reg_sp(s, rn)); | |
5789 | } | |
5790 | break; | |
438efea0 RH |
5791 | case 5: /* GMI */ |
5792 | if (sf == 0 || !dc_isar_feature(aa64_mte_insn_reg, s)) { | |
5793 | goto do_unallocated; | |
5794 | } else { | |
5795 | TCGv_i64 t1 = tcg_const_i64(1); | |
5796 | TCGv_i64 t2 = tcg_temp_new_i64(); | |
5797 | ||
5798 | tcg_gen_extract_i64(t2, cpu_reg_sp(s, rn), 56, 4); | |
5799 | tcg_gen_shl_i64(t1, t1, t2); | |
5800 | tcg_gen_or_i64(cpu_reg(s, rd), cpu_reg(s, rm), t1); | |
5801 | ||
5802 | tcg_temp_free_i64(t1); | |
5803 | tcg_temp_free_i64(t2); | |
5804 | } | |
5805 | break; | |
8220e911 | 5806 | case 8: /* LSLV */ |
6c1adc91 AG |
5807 | handle_shift_reg(s, A64_SHIFT_TYPE_LSL, sf, rm, rn, rd); |
5808 | break; | |
8220e911 | 5809 | case 9: /* LSRV */ |
6c1adc91 AG |
5810 | handle_shift_reg(s, A64_SHIFT_TYPE_LSR, sf, rm, rn, rd); |
5811 | break; | |
8220e911 | 5812 | case 10: /* ASRV */ |
6c1adc91 AG |
5813 | handle_shift_reg(s, A64_SHIFT_TYPE_ASR, sf, rm, rn, rd); |
5814 | break; | |
8220e911 | 5815 | case 11: /* RORV */ |
6c1adc91 AG |
5816 | handle_shift_reg(s, A64_SHIFT_TYPE_ROR, sf, rm, rn, rd); |
5817 | break; | |
b6342a9f RH |
5818 | case 12: /* PACGA */ |
5819 | if (sf == 0 || !dc_isar_feature(aa64_pauth, s)) { | |
5820 | goto do_unallocated; | |
5821 | } | |
5822 | gen_helper_pacga(cpu_reg(s, rd), cpu_env, | |
5823 | cpu_reg(s, rn), cpu_reg_sp(s, rm)); | |
5824 | break; | |
8220e911 AG |
5825 | case 16: |
5826 | case 17: | |
5827 | case 18: | |
5828 | case 19: | |
5829 | case 20: | |
5830 | case 21: | |
5831 | case 22: | |
5832 | case 23: /* CRC32 */ | |
130f2e7d PM |
5833 | { |
5834 | int sz = extract32(opcode, 0, 2); | |
5835 | bool crc32c = extract32(opcode, 2, 1); | |
5836 | handle_crc32(s, sf, sz, crc32c, rm, rn, rd); | |
8220e911 | 5837 | break; |
130f2e7d | 5838 | } |
8220e911 | 5839 | default: |
b6342a9f | 5840 | do_unallocated: |
8220e911 AG |
5841 | unallocated_encoding(s); |
5842 | break; | |
5843 | } | |
ad7ee8a2 CF |
5844 | } |
5845 | ||
2fba34f7 RH |
5846 | /* |
5847 | * Data processing - register | |
5848 | * 31 30 29 28 25 21 20 16 10 0 | |
5849 | * +--+---+--+---+-------+-----+-------+-------+---------+ | |
5850 | * | |op0| |op1| 1 0 1 | op2 | | op3 | | | |
5851 | * +--+---+--+---+-------+-----+-------+-------+---------+ | |
5852 | */ | |
ad7ee8a2 CF |
5853 | static void disas_data_proc_reg(DisasContext *s, uint32_t insn) |
5854 | { | |
2fba34f7 RH |
5855 | int op0 = extract32(insn, 30, 1); |
5856 | int op1 = extract32(insn, 28, 1); | |
5857 | int op2 = extract32(insn, 21, 4); | |
5858 | int op3 = extract32(insn, 10, 6); | |
5859 | ||
5860 | if (!op1) { | |
5861 | if (op2 & 8) { | |
5862 | if (op2 & 1) { | |
5863 | /* Add/sub (extended register) */ | |
5864 | disas_add_sub_ext_reg(s, insn); | |
5865 | } else { | |
5866 | /* Add/sub (shifted register) */ | |
5867 | disas_add_sub_reg(s, insn); | |
5868 | } | |
ad7ee8a2 | 5869 | } else { |
2fba34f7 RH |
5870 | /* Logical (shifted register) */ |
5871 | disas_logic_reg(s, insn); | |
ad7ee8a2 | 5872 | } |
2fba34f7 RH |
5873 | return; |
5874 | } | |
5875 | ||
5876 | switch (op2) { | |
5877 | case 0x0: | |
5878 | switch (op3) { | |
5879 | case 0x00: /* Add/subtract (with carry) */ | |
ad7ee8a2 CF |
5880 | disas_adc_sbc(s, insn); |
5881 | break; | |
2fba34f7 | 5882 | |
b89d9c98 RH |
5883 | case 0x01: /* Rotate right into flags */ |
5884 | case 0x21: | |
5885 | disas_rotate_right_into_flags(s, insn); | |
5886 | break; | |
5887 | ||
5888 | case 0x02: /* Evaluate into flags */ | |
5889 | case 0x12: | |
5890 | case 0x22: | |
5891 | case 0x32: | |
5892 | disas_evaluate_into_flags(s, insn); | |
5893 | break; | |
5894 | ||
ad7ee8a2 | 5895 | default: |
2fba34f7 | 5896 | goto do_unallocated; |
ad7ee8a2 CF |
5897 | } |
5898 | break; | |
2fba34f7 RH |
5899 | |
5900 | case 0x2: /* Conditional compare */ | |
5901 | disas_cc(s, insn); /* both imm and reg forms */ | |
5902 | break; | |
5903 | ||
5904 | case 0x4: /* Conditional select */ | |
5905 | disas_cond_select(s, insn); | |
5906 | break; | |
5907 | ||
5908 | case 0x6: /* Data-processing */ | |
5909 | if (op0) { /* (1 source) */ | |
5910 | disas_data_proc_1src(s, insn); | |
5911 | } else { /* (2 source) */ | |
5912 | disas_data_proc_2src(s, insn); | |
5913 | } | |
5914 | break; | |
5915 | case 0x8 ... 0xf: /* (3 source) */ | |
5916 | disas_data_proc_3src(s, insn); | |
5917 | break; | |
5918 | ||
ad7ee8a2 | 5919 | default: |
2fba34f7 | 5920 | do_unallocated: |
ad7ee8a2 CF |
5921 | unallocated_encoding(s); |
5922 | break; | |
5923 | } | |
5924 | } | |
5925 | ||
7a192925 | 5926 | static void handle_fp_compare(DisasContext *s, int size, |
da7dafe7 CF |
5927 | unsigned int rn, unsigned int rm, |
5928 | bool cmp_with_zero, bool signal_all_nans) | |
5929 | { | |
5930 | TCGv_i64 tcg_flags = tcg_temp_new_i64(); | |
cdfb22bb | 5931 | TCGv_ptr fpst = fpstatus_ptr(size == MO_16 ? FPST_FPCR_F16 : FPST_FPCR); |
da7dafe7 | 5932 | |
7a192925 | 5933 | if (size == MO_64) { |
da7dafe7 CF |
5934 | TCGv_i64 tcg_vn, tcg_vm; |
5935 | ||
5936 | tcg_vn = read_fp_dreg(s, rn); | |
5937 | if (cmp_with_zero) { | |
5938 | tcg_vm = tcg_const_i64(0); | |
5939 | } else { | |
5940 | tcg_vm = read_fp_dreg(s, rm); | |
5941 | } | |
5942 | if (signal_all_nans) { | |
5943 | gen_helper_vfp_cmped_a64(tcg_flags, tcg_vn, tcg_vm, fpst); | |
5944 | } else { | |
5945 | gen_helper_vfp_cmpd_a64(tcg_flags, tcg_vn, tcg_vm, fpst); | |
5946 | } | |
5947 | tcg_temp_free_i64(tcg_vn); | |
5948 | tcg_temp_free_i64(tcg_vm); | |
5949 | } else { | |
7a192925 AB |
5950 | TCGv_i32 tcg_vn = tcg_temp_new_i32(); |
5951 | TCGv_i32 tcg_vm = tcg_temp_new_i32(); | |
da7dafe7 | 5952 | |
7a192925 | 5953 | read_vec_element_i32(s, tcg_vn, rn, 0, size); |
da7dafe7 | 5954 | if (cmp_with_zero) { |
7a192925 | 5955 | tcg_gen_movi_i32(tcg_vm, 0); |
da7dafe7 | 5956 | } else { |
7a192925 | 5957 | read_vec_element_i32(s, tcg_vm, rm, 0, size); |
da7dafe7 | 5958 | } |
7a192925 AB |
5959 | |
5960 | switch (size) { | |
5961 | case MO_32: | |
5962 | if (signal_all_nans) { | |
5963 | gen_helper_vfp_cmpes_a64(tcg_flags, tcg_vn, tcg_vm, fpst); | |
5964 | } else { | |
5965 | gen_helper_vfp_cmps_a64(tcg_flags, tcg_vn, tcg_vm, fpst); | |
5966 | } | |
5967 | break; | |
5968 | case MO_16: | |
5969 | if (signal_all_nans) { | |
5970 | gen_helper_vfp_cmpeh_a64(tcg_flags, tcg_vn, tcg_vm, fpst); | |
5971 | } else { | |
5972 | gen_helper_vfp_cmph_a64(tcg_flags, tcg_vn, tcg_vm, fpst); | |
5973 | } | |
5974 | break; | |
5975 | default: | |
5976 | g_assert_not_reached(); | |
da7dafe7 | 5977 | } |
7a192925 | 5978 | |
da7dafe7 CF |
5979 | tcg_temp_free_i32(tcg_vn); |
5980 | tcg_temp_free_i32(tcg_vm); | |
5981 | } | |
5982 | ||
5983 | tcg_temp_free_ptr(fpst); | |
5984 | ||
5985 | gen_set_nzcv(tcg_flags); | |
5986 | ||
5987 | tcg_temp_free_i64(tcg_flags); | |
5988 | } | |
5989 | ||
4ce31af4 | 5990 | /* Floating point compare |
faa0ba46 PM |
5991 | * 31 30 29 28 24 23 22 21 20 16 15 14 13 10 9 5 4 0 |
5992 | * +---+---+---+-----------+------+---+------+-----+---------+------+-------+ | |
5993 | * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | op | 1 0 0 0 | Rn | op2 | | |
5994 | * +---+---+---+-----------+------+---+------+-----+---------+------+-------+ | |
5995 | */ | |
5996 | static void disas_fp_compare(DisasContext *s, uint32_t insn) | |
5997 | { | |
da7dafe7 | 5998 | unsigned int mos, type, rm, op, rn, opc, op2r; |
7a192925 | 5999 | int size; |
da7dafe7 CF |
6000 | |
6001 | mos = extract32(insn, 29, 3); | |
7a192925 | 6002 | type = extract32(insn, 22, 2); |
da7dafe7 CF |
6003 | rm = extract32(insn, 16, 5); |
6004 | op = extract32(insn, 14, 2); | |
6005 | rn = extract32(insn, 5, 5); | |
6006 | opc = extract32(insn, 3, 2); | |
6007 | op2r = extract32(insn, 0, 3); | |
6008 | ||
7a192925 AB |
6009 | if (mos || op || op2r) { |
6010 | unallocated_encoding(s); | |
6011 | return; | |
6012 | } | |
6013 | ||
6014 | switch (type) { | |
6015 | case 0: | |
6016 | size = MO_32; | |
6017 | break; | |
6018 | case 1: | |
6019 | size = MO_64; | |
6020 | break; | |
6021 | case 3: | |
6022 | size = MO_16; | |
5763190f | 6023 | if (dc_isar_feature(aa64_fp16, s)) { |
7a192925 AB |
6024 | break; |
6025 | } | |
6026 | /* fallthru */ | |
6027 | default: | |
da7dafe7 CF |
6028 | unallocated_encoding(s); |
6029 | return; | |
6030 | } | |
6031 | ||
8c6afa6a PM |
6032 | if (!fp_access_check(s)) { |
6033 | return; | |
6034 | } | |
6035 | ||
7a192925 | 6036 | handle_fp_compare(s, size, rn, rm, opc & 1, opc & 2); |
faa0ba46 PM |
6037 | } |
6038 | ||
4ce31af4 | 6039 | /* Floating point conditional compare |
faa0ba46 PM |
6040 | * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0 |
6041 | * +---+---+---+-----------+------+---+------+------+-----+------+----+------+ | |
6042 | * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 0 1 | Rn | op | nzcv | | |
6043 | * +---+---+---+-----------+------+---+------+------+-----+------+----+------+ | |
6044 | */ | |
6045 | static void disas_fp_ccomp(DisasContext *s, uint32_t insn) | |
6046 | { | |
513f1d76 CF |
6047 | unsigned int mos, type, rm, cond, rn, op, nzcv; |
6048 | TCGv_i64 tcg_flags; | |
42a268c2 | 6049 | TCGLabel *label_continue = NULL; |
7a192925 | 6050 | int size; |
513f1d76 CF |
6051 | |
6052 | mos = extract32(insn, 29, 3); | |
7a192925 | 6053 | type = extract32(insn, 22, 2); |
513f1d76 CF |
6054 | rm = extract32(insn, 16, 5); |
6055 | cond = extract32(insn, 12, 4); | |
6056 | rn = extract32(insn, 5, 5); | |
6057 | op = extract32(insn, 4, 1); | |
6058 | nzcv = extract32(insn, 0, 4); | |
6059 | ||
7a192925 AB |
6060 | if (mos) { |
6061 | unallocated_encoding(s); | |
6062 | return; | |
6063 | } | |
6064 | ||
6065 | switch (type) { | |
6066 | case 0: | |
6067 | size = MO_32; | |
6068 | break; | |
6069 | case 1: | |
6070 | size = MO_64; | |
6071 | break; | |
6072 | case 3: | |
6073 | size = MO_16; | |
5763190f | 6074 | if (dc_isar_feature(aa64_fp16, s)) { |
7a192925 AB |
6075 | break; |
6076 | } | |
6077 | /* fallthru */ | |
6078 | default: | |
513f1d76 CF |
6079 | unallocated_encoding(s); |
6080 | return; | |
6081 | } | |
6082 | ||
8c6afa6a PM |
6083 | if (!fp_access_check(s)) { |
6084 | return; | |
6085 | } | |
6086 | ||
513f1d76 | 6087 | if (cond < 0x0e) { /* not always */ |
42a268c2 | 6088 | TCGLabel *label_match = gen_new_label(); |
513f1d76 CF |
6089 | label_continue = gen_new_label(); |
6090 | arm_gen_test_cc(cond, label_match); | |
6091 | /* nomatch: */ | |
6092 | tcg_flags = tcg_const_i64(nzcv << 28); | |
6093 | gen_set_nzcv(tcg_flags); | |
6094 | tcg_temp_free_i64(tcg_flags); | |
6095 | tcg_gen_br(label_continue); | |
6096 | gen_set_label(label_match); | |
6097 | } | |
6098 | ||
7a192925 | 6099 | handle_fp_compare(s, size, rn, rm, false, op); |
513f1d76 CF |
6100 | |
6101 | if (cond < 0x0e) { | |
6102 | gen_set_label(label_continue); | |
6103 | } | |
faa0ba46 PM |
6104 | } |
6105 | ||
4ce31af4 | 6106 | /* Floating point conditional select |
faa0ba46 PM |
6107 | * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0 |
6108 | * +---+---+---+-----------+------+---+------+------+-----+------+------+ | |
6109 | * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 1 1 | Rn | Rd | | |
6110 | * +---+---+---+-----------+------+---+------+------+-----+------+------+ | |
6111 | */ | |
6112 | static void disas_fp_csel(DisasContext *s, uint32_t insn) | |
6113 | { | |
5640ff62 | 6114 | unsigned int mos, type, rm, cond, rn, rd; |
6e061029 RH |
6115 | TCGv_i64 t_true, t_false, t_zero; |
6116 | DisasCompare64 c; | |
14776ab5 | 6117 | MemOp sz; |
5640ff62 CF |
6118 | |
6119 | mos = extract32(insn, 29, 3); | |
ace97fee | 6120 | type = extract32(insn, 22, 2); |
5640ff62 CF |
6121 | rm = extract32(insn, 16, 5); |
6122 | cond = extract32(insn, 12, 4); | |
6123 | rn = extract32(insn, 5, 5); | |
6124 | rd = extract32(insn, 0, 5); | |
6125 | ||
ace97fee AB |
6126 | if (mos) { |
6127 | unallocated_encoding(s); | |
6128 | return; | |
6129 | } | |
6130 | ||
6131 | switch (type) { | |
6132 | case 0: | |
6133 | sz = MO_32; | |
6134 | break; | |
6135 | case 1: | |
6136 | sz = MO_64; | |
6137 | break; | |
6138 | case 3: | |
6139 | sz = MO_16; | |
5763190f | 6140 | if (dc_isar_feature(aa64_fp16, s)) { |
ace97fee AB |
6141 | break; |
6142 | } | |
6143 | /* fallthru */ | |
6144 | default: | |
5640ff62 CF |
6145 | unallocated_encoding(s); |
6146 | return; | |
6147 | } | |
6148 | ||
8c6afa6a PM |
6149 | if (!fp_access_check(s)) { |
6150 | return; | |
6151 | } | |
6152 | ||
ace97fee | 6153 | /* Zero extend sreg & hreg inputs to 64 bits now. */ |
6e061029 RH |
6154 | t_true = tcg_temp_new_i64(); |
6155 | t_false = tcg_temp_new_i64(); | |
ace97fee AB |
6156 | read_vec_element(s, t_true, rn, 0, sz); |
6157 | read_vec_element(s, t_false, rm, 0, sz); | |
5640ff62 | 6158 | |
6e061029 RH |
6159 | a64_test_cc(&c, cond); |
6160 | t_zero = tcg_const_i64(0); | |
6161 | tcg_gen_movcond_i64(c.cond, t_true, c.value, t_zero, t_true, t_false); | |
6162 | tcg_temp_free_i64(t_zero); | |
6163 | tcg_temp_free_i64(t_false); | |
6164 | a64_free_cc(&c); | |
5640ff62 | 6165 | |
ace97fee | 6166 | /* Note that sregs & hregs write back zeros to the high bits, |
6e061029 RH |
6167 | and we've already done the zero-extension. */ |
6168 | write_fp_dreg(s, rd, t_true); | |
6169 | tcg_temp_free_i64(t_true); | |
faa0ba46 PM |
6170 | } |
6171 | ||
c2c08713 AB |
6172 | /* Floating-point data-processing (1 source) - half precision */ |
6173 | static void handle_fp_1src_half(DisasContext *s, int opcode, int rd, int rn) | |
6174 | { | |
6175 | TCGv_ptr fpst = NULL; | |
3d99d931 | 6176 | TCGv_i32 tcg_op = read_fp_hreg(s, rn); |
c2c08713 AB |
6177 | TCGv_i32 tcg_res = tcg_temp_new_i32(); |
6178 | ||
c2c08713 AB |
6179 | switch (opcode) { |
6180 | case 0x0: /* FMOV */ | |
6181 | tcg_gen_mov_i32(tcg_res, tcg_op); | |
6182 | break; | |
6183 | case 0x1: /* FABS */ | |
6184 | tcg_gen_andi_i32(tcg_res, tcg_op, 0x7fff); | |
6185 | break; | |
6186 | case 0x2: /* FNEG */ | |
6187 | tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000); | |
6188 | break; | |
6189 | case 0x3: /* FSQRT */ | |
cdfb22bb | 6190 | fpst = fpstatus_ptr(FPST_FPCR_F16); |
905edee9 | 6191 | gen_helper_sqrt_f16(tcg_res, tcg_op, fpst); |
c2c08713 AB |
6192 | break; |
6193 | case 0x8: /* FRINTN */ | |
6194 | case 0x9: /* FRINTP */ | |
6195 | case 0xa: /* FRINTM */ | |
6196 | case 0xb: /* FRINTZ */ | |
6197 | case 0xc: /* FRINTA */ | |
6198 | { | |
6199 | TCGv_i32 tcg_rmode = tcg_const_i32(arm_rmode_to_sf(opcode & 7)); | |
cdfb22bb | 6200 | fpst = fpstatus_ptr(FPST_FPCR_F16); |
c2c08713 AB |
6201 | |
6202 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); | |
6203 | gen_helper_advsimd_rinth(tcg_res, tcg_op, fpst); | |
6204 | ||
6205 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); | |
6206 | tcg_temp_free_i32(tcg_rmode); | |
6207 | break; | |
6208 | } | |
6209 | case 0xe: /* FRINTX */ | |
cdfb22bb | 6210 | fpst = fpstatus_ptr(FPST_FPCR_F16); |
c2c08713 AB |
6211 | gen_helper_advsimd_rinth_exact(tcg_res, tcg_op, fpst); |
6212 | break; | |
6213 | case 0xf: /* FRINTI */ | |
cdfb22bb | 6214 | fpst = fpstatus_ptr(FPST_FPCR_F16); |
c2c08713 AB |
6215 | gen_helper_advsimd_rinth(tcg_res, tcg_op, fpst); |
6216 | break; | |
6217 | default: | |
6218 | abort(); | |
6219 | } | |
6220 | ||
6221 | write_fp_sreg(s, rd, tcg_res); | |
6222 | ||
6223 | if (fpst) { | |
6224 | tcg_temp_free_ptr(fpst); | |
6225 | } | |
6226 | tcg_temp_free_i32(tcg_op); | |
6227 | tcg_temp_free_i32(tcg_res); | |
6228 | } | |
6229 | ||
4ce31af4 | 6230 | /* Floating-point data-processing (1 source) - single precision */ |
d9b0848d PM |
6231 | static void handle_fp_1src_single(DisasContext *s, int opcode, int rd, int rn) |
6232 | { | |
0e4db23d RH |
6233 | void (*gen_fpst)(TCGv_i32, TCGv_i32, TCGv_ptr); |
6234 | TCGv_i32 tcg_op, tcg_res; | |
d9b0848d | 6235 | TCGv_ptr fpst; |
0e4db23d | 6236 | int rmode = -1; |
d9b0848d | 6237 | |
d9b0848d PM |
6238 | tcg_op = read_fp_sreg(s, rn); |
6239 | tcg_res = tcg_temp_new_i32(); | |
6240 | ||
6241 | switch (opcode) { | |
6242 | case 0x0: /* FMOV */ | |
6243 | tcg_gen_mov_i32(tcg_res, tcg_op); | |
0e4db23d | 6244 | goto done; |
d9b0848d PM |
6245 | case 0x1: /* FABS */ |
6246 | gen_helper_vfp_abss(tcg_res, tcg_op); | |
0e4db23d | 6247 | goto done; |
d9b0848d PM |
6248 | case 0x2: /* FNEG */ |
6249 | gen_helper_vfp_negs(tcg_res, tcg_op); | |
0e4db23d | 6250 | goto done; |
d9b0848d PM |
6251 | case 0x3: /* FSQRT */ |
6252 | gen_helper_vfp_sqrts(tcg_res, tcg_op, cpu_env); | |
0e4db23d | 6253 | goto done; |
d9b0848d PM |
6254 | case 0x8: /* FRINTN */ |
6255 | case 0x9: /* FRINTP */ | |
6256 | case 0xa: /* FRINTM */ | |
6257 | case 0xb: /* FRINTZ */ | |
6258 | case 0xc: /* FRINTA */ | |
0e4db23d RH |
6259 | rmode = arm_rmode_to_sf(opcode & 7); |
6260 | gen_fpst = gen_helper_rints; | |
d9b0848d | 6261 | break; |
d9b0848d | 6262 | case 0xe: /* FRINTX */ |
0e4db23d | 6263 | gen_fpst = gen_helper_rints_exact; |
d9b0848d PM |
6264 | break; |
6265 | case 0xf: /* FRINTI */ | |
0e4db23d | 6266 | gen_fpst = gen_helper_rints; |
d9b0848d | 6267 | break; |
6bea2563 RH |
6268 | case 0x10: /* FRINT32Z */ |
6269 | rmode = float_round_to_zero; | |
6270 | gen_fpst = gen_helper_frint32_s; | |
6271 | break; | |
6272 | case 0x11: /* FRINT32X */ | |
6273 | gen_fpst = gen_helper_frint32_s; | |
6274 | break; | |
6275 | case 0x12: /* FRINT64Z */ | |
6276 | rmode = float_round_to_zero; | |
6277 | gen_fpst = gen_helper_frint64_s; | |
6278 | break; | |
6279 | case 0x13: /* FRINT64X */ | |
6280 | gen_fpst = gen_helper_frint64_s; | |
6281 | break; | |
d9b0848d | 6282 | default: |
0e4db23d | 6283 | g_assert_not_reached(); |
d9b0848d PM |
6284 | } |
6285 | ||
cdfb22bb | 6286 | fpst = fpstatus_ptr(FPST_FPCR); |
0e4db23d RH |
6287 | if (rmode >= 0) { |
6288 | TCGv_i32 tcg_rmode = tcg_const_i32(rmode); | |
6289 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); | |
6290 | gen_fpst(tcg_res, tcg_op, fpst); | |
6291 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); | |
6292 | tcg_temp_free_i32(tcg_rmode); | |
6293 | } else { | |
6294 | gen_fpst(tcg_res, tcg_op, fpst); | |
6295 | } | |
d9b0848d | 6296 | tcg_temp_free_ptr(fpst); |
0e4db23d RH |
6297 | |
6298 | done: | |
6299 | write_fp_sreg(s, rd, tcg_res); | |
d9b0848d PM |
6300 | tcg_temp_free_i32(tcg_op); |
6301 | tcg_temp_free_i32(tcg_res); | |
6302 | } | |
6303 | ||
4ce31af4 | 6304 | /* Floating-point data-processing (1 source) - double precision */ |
d9b0848d PM |
6305 | static void handle_fp_1src_double(DisasContext *s, int opcode, int rd, int rn) |
6306 | { | |
0e4db23d RH |
6307 | void (*gen_fpst)(TCGv_i64, TCGv_i64, TCGv_ptr); |
6308 | TCGv_i64 tcg_op, tcg_res; | |
d9b0848d | 6309 | TCGv_ptr fpst; |
0e4db23d | 6310 | int rmode = -1; |
d9b0848d | 6311 | |
377ef731 RH |
6312 | switch (opcode) { |
6313 | case 0x0: /* FMOV */ | |
6314 | gen_gvec_fn2(s, false, rd, rn, tcg_gen_gvec_mov, 0); | |
6315 | return; | |
6316 | } | |
6317 | ||
d9b0848d PM |
6318 | tcg_op = read_fp_dreg(s, rn); |
6319 | tcg_res = tcg_temp_new_i64(); | |
6320 | ||
6321 | switch (opcode) { | |
d9b0848d PM |
6322 | case 0x1: /* FABS */ |
6323 | gen_helper_vfp_absd(tcg_res, tcg_op); | |
0e4db23d | 6324 | goto done; |
d9b0848d PM |
6325 | case 0x2: /* FNEG */ |
6326 | gen_helper_vfp_negd(tcg_res, tcg_op); | |
0e4db23d | 6327 | goto done; |
d9b0848d PM |
6328 | case 0x3: /* FSQRT */ |
6329 | gen_helper_vfp_sqrtd(tcg_res, tcg_op, cpu_env); | |
0e4db23d | 6330 | goto done; |
d9b0848d PM |
6331 | case 0x8: /* FRINTN */ |
6332 | case 0x9: /* FRINTP */ | |
6333 | case 0xa: /* FRINTM */ | |
6334 | case 0xb: /* FRINTZ */ | |
6335 | case 0xc: /* FRINTA */ | |
0e4db23d RH |
6336 | rmode = arm_rmode_to_sf(opcode & 7); |
6337 | gen_fpst = gen_helper_rintd; | |
d9b0848d | 6338 | break; |
d9b0848d | 6339 | case 0xe: /* FRINTX */ |
0e4db23d | 6340 | gen_fpst = gen_helper_rintd_exact; |
d9b0848d PM |
6341 | break; |
6342 | case 0xf: /* FRINTI */ | |
0e4db23d | 6343 | gen_fpst = gen_helper_rintd; |
d9b0848d | 6344 | break; |
6bea2563 RH |
6345 | case 0x10: /* FRINT32Z */ |
6346 | rmode = float_round_to_zero; | |
6347 | gen_fpst = gen_helper_frint32_d; | |
6348 | break; | |
6349 | case 0x11: /* FRINT32X */ | |
6350 | gen_fpst = gen_helper_frint32_d; | |
6351 | break; | |
6352 | case 0x12: /* FRINT64Z */ | |
6353 | rmode = float_round_to_zero; | |
6354 | gen_fpst = gen_helper_frint64_d; | |
6355 | break; | |
6356 | case 0x13: /* FRINT64X */ | |
6357 | gen_fpst = gen_helper_frint64_d; | |
6358 | break; | |
d9b0848d | 6359 | default: |
0e4db23d | 6360 | g_assert_not_reached(); |
d9b0848d PM |
6361 | } |
6362 | ||
cdfb22bb | 6363 | fpst = fpstatus_ptr(FPST_FPCR); |
0e4db23d RH |
6364 | if (rmode >= 0) { |
6365 | TCGv_i32 tcg_rmode = tcg_const_i32(rmode); | |
6366 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); | |
6367 | gen_fpst(tcg_res, tcg_op, fpst); | |
6368 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); | |
6369 | tcg_temp_free_i32(tcg_rmode); | |
6370 | } else { | |
6371 | gen_fpst(tcg_res, tcg_op, fpst); | |
6372 | } | |
d9b0848d | 6373 | tcg_temp_free_ptr(fpst); |
0e4db23d RH |
6374 | |
6375 | done: | |
6376 | write_fp_dreg(s, rd, tcg_res); | |
d9b0848d PM |
6377 | tcg_temp_free_i64(tcg_op); |
6378 | tcg_temp_free_i64(tcg_res); | |
6379 | } | |
6380 | ||
8900aad2 PM |
6381 | static void handle_fp_fcvt(DisasContext *s, int opcode, |
6382 | int rd, int rn, int dtype, int ntype) | |
6383 | { | |
6384 | switch (ntype) { | |
6385 | case 0x0: | |
6386 | { | |
6387 | TCGv_i32 tcg_rn = read_fp_sreg(s, rn); | |
6388 | if (dtype == 1) { | |
6389 | /* Single to double */ | |
6390 | TCGv_i64 tcg_rd = tcg_temp_new_i64(); | |
6391 | gen_helper_vfp_fcvtds(tcg_rd, tcg_rn, cpu_env); | |
6392 | write_fp_dreg(s, rd, tcg_rd); | |
6393 | tcg_temp_free_i64(tcg_rd); | |
6394 | } else { | |
6395 | /* Single to half */ | |
6396 | TCGv_i32 tcg_rd = tcg_temp_new_i32(); | |
486624fc | 6397 | TCGv_i32 ahp = get_ahp_flag(); |
cdfb22bb | 6398 | TCGv_ptr fpst = fpstatus_ptr(FPST_FPCR); |
486624fc AB |
6399 | |
6400 | gen_helper_vfp_fcvt_f32_to_f16(tcg_rd, tcg_rn, fpst, ahp); | |
8900aad2 PM |
6401 | /* write_fp_sreg is OK here because top half of tcg_rd is zero */ |
6402 | write_fp_sreg(s, rd, tcg_rd); | |
6403 | tcg_temp_free_i32(tcg_rd); | |
486624fc AB |
6404 | tcg_temp_free_i32(ahp); |
6405 | tcg_temp_free_ptr(fpst); | |
8900aad2 PM |
6406 | } |
6407 | tcg_temp_free_i32(tcg_rn); | |
6408 | break; | |
6409 | } | |
6410 | case 0x1: | |
6411 | { | |
6412 | TCGv_i64 tcg_rn = read_fp_dreg(s, rn); | |
6413 | TCGv_i32 tcg_rd = tcg_temp_new_i32(); | |
6414 | if (dtype == 0) { | |
6415 | /* Double to single */ | |
6416 | gen_helper_vfp_fcvtsd(tcg_rd, tcg_rn, cpu_env); | |
6417 | } else { | |
cdfb22bb | 6418 | TCGv_ptr fpst = fpstatus_ptr(FPST_FPCR); |
486624fc | 6419 | TCGv_i32 ahp = get_ahp_flag(); |
8900aad2 | 6420 | /* Double to half */ |
486624fc | 6421 | gen_helper_vfp_fcvt_f64_to_f16(tcg_rd, tcg_rn, fpst, ahp); |
8900aad2 | 6422 | /* write_fp_sreg is OK here because top half of tcg_rd is zero */ |
486624fc AB |
6423 | tcg_temp_free_ptr(fpst); |
6424 | tcg_temp_free_i32(ahp); | |
8900aad2 PM |
6425 | } |
6426 | write_fp_sreg(s, rd, tcg_rd); | |
6427 | tcg_temp_free_i32(tcg_rd); | |
6428 | tcg_temp_free_i64(tcg_rn); | |
6429 | break; | |
6430 | } | |
6431 | case 0x3: | |
6432 | { | |
6433 | TCGv_i32 tcg_rn = read_fp_sreg(s, rn); | |
cdfb22bb | 6434 | TCGv_ptr tcg_fpst = fpstatus_ptr(FPST_FPCR); |
486624fc | 6435 | TCGv_i32 tcg_ahp = get_ahp_flag(); |
8900aad2 PM |
6436 | tcg_gen_ext16u_i32(tcg_rn, tcg_rn); |
6437 | if (dtype == 0) { | |
6438 | /* Half to single */ | |
6439 | TCGv_i32 tcg_rd = tcg_temp_new_i32(); | |
486624fc | 6440 | gen_helper_vfp_fcvt_f16_to_f32(tcg_rd, tcg_rn, tcg_fpst, tcg_ahp); |
8900aad2 PM |
6441 | write_fp_sreg(s, rd, tcg_rd); |
6442 | tcg_temp_free_i32(tcg_rd); | |
6443 | } else { | |
6444 | /* Half to double */ | |
6445 | TCGv_i64 tcg_rd = tcg_temp_new_i64(); | |
486624fc | 6446 | gen_helper_vfp_fcvt_f16_to_f64(tcg_rd, tcg_rn, tcg_fpst, tcg_ahp); |
8900aad2 PM |
6447 | write_fp_dreg(s, rd, tcg_rd); |
6448 | tcg_temp_free_i64(tcg_rd); | |
6449 | } | |
6450 | tcg_temp_free_i32(tcg_rn); | |
aeab8e5e AB |
6451 | tcg_temp_free_ptr(tcg_fpst); |
6452 | tcg_temp_free_i32(tcg_ahp); | |
8900aad2 PM |
6453 | break; |
6454 | } | |
6455 | default: | |
6456 | abort(); | |
6457 | } | |
6458 | } | |
6459 | ||
4ce31af4 | 6460 | /* Floating point data-processing (1 source) |
faa0ba46 PM |
6461 | * 31 30 29 28 24 23 22 21 20 15 14 10 9 5 4 0 |
6462 | * +---+---+---+-----------+------+---+--------+-----------+------+------+ | |
6463 | * | M | 0 | S | 1 1 1 1 0 | type | 1 | opcode | 1 0 0 0 0 | Rn | Rd | | |
6464 | * +---+---+---+-----------+------+---+--------+-----------+------+------+ | |
6465 | */ | |
6466 | static void disas_fp_1src(DisasContext *s, uint32_t insn) | |
6467 | { | |
c1e20801 | 6468 | int mos = extract32(insn, 29, 3); |
d9b0848d PM |
6469 | int type = extract32(insn, 22, 2); |
6470 | int opcode = extract32(insn, 15, 6); | |
6471 | int rn = extract32(insn, 5, 5); | |
6472 | int rd = extract32(insn, 0, 5); | |
6473 | ||
c1e20801 PM |
6474 | if (mos) { |
6475 | unallocated_encoding(s); | |
6476 | return; | |
6477 | } | |
6478 | ||
d9b0848d PM |
6479 | switch (opcode) { |
6480 | case 0x4: case 0x5: case 0x7: | |
8900aad2 | 6481 | { |
d9b0848d | 6482 | /* FCVT between half, single and double precision */ |
8900aad2 PM |
6483 | int dtype = extract32(opcode, 0, 2); |
6484 | if (type == 2 || dtype == type) { | |
6485 | unallocated_encoding(s); | |
6486 | return; | |
6487 | } | |
8c6afa6a PM |
6488 | if (!fp_access_check(s)) { |
6489 | return; | |
6490 | } | |
6491 | ||
8900aad2 | 6492 | handle_fp_fcvt(s, opcode, rd, rn, dtype, type); |
d9b0848d | 6493 | break; |
8900aad2 | 6494 | } |
6bea2563 RH |
6495 | |
6496 | case 0x10 ... 0x13: /* FRINT{32,64}{X,Z} */ | |
6497 | if (type > 1 || !dc_isar_feature(aa64_frint, s)) { | |
6498 | unallocated_encoding(s); | |
6499 | return; | |
6500 | } | |
6501 | /* fall through */ | |
d9b0848d PM |
6502 | case 0x0 ... 0x3: |
6503 | case 0x8 ... 0xc: | |
6504 | case 0xe ... 0xf: | |
6505 | /* 32-to-32 and 64-to-64 ops */ | |
6506 | switch (type) { | |
6507 | case 0: | |
8c6afa6a PM |
6508 | if (!fp_access_check(s)) { |
6509 | return; | |
6510 | } | |
d9b0848d PM |
6511 | handle_fp_1src_single(s, opcode, rd, rn); |
6512 | break; | |
6513 | case 1: | |
8c6afa6a PM |
6514 | if (!fp_access_check(s)) { |
6515 | return; | |
6516 | } | |
d9b0848d PM |
6517 | handle_fp_1src_double(s, opcode, rd, rn); |
6518 | break; | |
c2c08713 | 6519 | case 3: |
5763190f | 6520 | if (!dc_isar_feature(aa64_fp16, s)) { |
c2c08713 AB |
6521 | unallocated_encoding(s); |
6522 | return; | |
6523 | } | |
6524 | ||
6525 | if (!fp_access_check(s)) { | |
6526 | return; | |
6527 | } | |
c2c08713 AB |
6528 | handle_fp_1src_half(s, opcode, rd, rn); |
6529 | break; | |
d9b0848d PM |
6530 | default: |
6531 | unallocated_encoding(s); | |
6532 | } | |
6533 | break; | |
6bea2563 | 6534 | |
d9b0848d PM |
6535 | default: |
6536 | unallocated_encoding(s); | |
6537 | break; | |
6538 | } | |
faa0ba46 PM |
6539 | } |
6540 | ||
4ce31af4 | 6541 | /* Floating-point data-processing (2 source) - single precision */ |
ec73d2e0 AG |
6542 | static void handle_fp_2src_single(DisasContext *s, int opcode, |
6543 | int rd, int rn, int rm) | |
6544 | { | |
6545 | TCGv_i32 tcg_op1; | |
6546 | TCGv_i32 tcg_op2; | |
6547 | TCGv_i32 tcg_res; | |
6548 | TCGv_ptr fpst; | |
6549 | ||
6550 | tcg_res = tcg_temp_new_i32(); | |
cdfb22bb | 6551 | fpst = fpstatus_ptr(FPST_FPCR); |
ec73d2e0 AG |
6552 | tcg_op1 = read_fp_sreg(s, rn); |
6553 | tcg_op2 = read_fp_sreg(s, rm); | |
6554 | ||
6555 | switch (opcode) { | |
6556 | case 0x0: /* FMUL */ | |
6557 | gen_helper_vfp_muls(tcg_res, tcg_op1, tcg_op2, fpst); | |
6558 | break; | |
6559 | case 0x1: /* FDIV */ | |
6560 | gen_helper_vfp_divs(tcg_res, tcg_op1, tcg_op2, fpst); | |
6561 | break; | |
6562 | case 0x2: /* FADD */ | |
6563 | gen_helper_vfp_adds(tcg_res, tcg_op1, tcg_op2, fpst); | |
6564 | break; | |
6565 | case 0x3: /* FSUB */ | |
6566 | gen_helper_vfp_subs(tcg_res, tcg_op1, tcg_op2, fpst); | |
6567 | break; | |
6568 | case 0x4: /* FMAX */ | |
6569 | gen_helper_vfp_maxs(tcg_res, tcg_op1, tcg_op2, fpst); | |
6570 | break; | |
6571 | case 0x5: /* FMIN */ | |
6572 | gen_helper_vfp_mins(tcg_res, tcg_op1, tcg_op2, fpst); | |
6573 | break; | |
6574 | case 0x6: /* FMAXNM */ | |
6575 | gen_helper_vfp_maxnums(tcg_res, tcg_op1, tcg_op2, fpst); | |
6576 | break; | |
6577 | case 0x7: /* FMINNM */ | |
6578 | gen_helper_vfp_minnums(tcg_res, tcg_op1, tcg_op2, fpst); | |
6579 | break; | |
6580 | case 0x8: /* FNMUL */ | |
6581 | gen_helper_vfp_muls(tcg_res, tcg_op1, tcg_op2, fpst); | |
6582 | gen_helper_vfp_negs(tcg_res, tcg_res); | |
6583 | break; | |
6584 | } | |
6585 | ||
6586 | write_fp_sreg(s, rd, tcg_res); | |
6587 | ||
6588 | tcg_temp_free_ptr(fpst); | |
6589 | tcg_temp_free_i32(tcg_op1); | |
6590 | tcg_temp_free_i32(tcg_op2); | |
6591 | tcg_temp_free_i32(tcg_res); | |
6592 | } | |
6593 | ||
4ce31af4 | 6594 | /* Floating-point data-processing (2 source) - double precision */ |
ec73d2e0 AG |
6595 | static void handle_fp_2src_double(DisasContext *s, int opcode, |
6596 | int rd, int rn, int rm) | |
6597 | { | |
6598 | TCGv_i64 tcg_op1; | |
6599 | TCGv_i64 tcg_op2; | |
6600 | TCGv_i64 tcg_res; | |
6601 | TCGv_ptr fpst; | |
6602 | ||
6603 | tcg_res = tcg_temp_new_i64(); | |
cdfb22bb | 6604 | fpst = fpstatus_ptr(FPST_FPCR); |
ec73d2e0 AG |
6605 | tcg_op1 = read_fp_dreg(s, rn); |
6606 | tcg_op2 = read_fp_dreg(s, rm); | |
6607 | ||
6608 | switch (opcode) { | |
6609 | case 0x0: /* FMUL */ | |
6610 | gen_helper_vfp_muld(tcg_res, tcg_op1, tcg_op2, fpst); | |
6611 | break; | |
6612 | case 0x1: /* FDIV */ | |
6613 | gen_helper_vfp_divd(tcg_res, tcg_op1, tcg_op2, fpst); | |
6614 | break; | |
6615 | case 0x2: /* FADD */ | |
6616 | gen_helper_vfp_addd(tcg_res, tcg_op1, tcg_op2, fpst); | |
6617 | break; | |
6618 | case 0x3: /* FSUB */ | |
6619 | gen_helper_vfp_subd(tcg_res, tcg_op1, tcg_op2, fpst); | |
6620 | break; | |
6621 | case 0x4: /* FMAX */ | |
6622 | gen_helper_vfp_maxd(tcg_res, tcg_op1, tcg_op2, fpst); | |
6623 | break; | |
6624 | case 0x5: /* FMIN */ | |
6625 | gen_helper_vfp_mind(tcg_res, tcg_op1, tcg_op2, fpst); | |
6626 | break; | |
6627 | case 0x6: /* FMAXNM */ | |
6628 | gen_helper_vfp_maxnumd(tcg_res, tcg_op1, tcg_op2, fpst); | |
6629 | break; | |
6630 | case 0x7: /* FMINNM */ | |
6631 | gen_helper_vfp_minnumd(tcg_res, tcg_op1, tcg_op2, fpst); | |
6632 | break; | |
6633 | case 0x8: /* FNMUL */ | |
6634 | gen_helper_vfp_muld(tcg_res, tcg_op1, tcg_op2, fpst); | |
6635 | gen_helper_vfp_negd(tcg_res, tcg_res); | |
6636 | break; | |
6637 | } | |
6638 | ||
6639 | write_fp_dreg(s, rd, tcg_res); | |
6640 | ||
6641 | tcg_temp_free_ptr(fpst); | |
6642 | tcg_temp_free_i64(tcg_op1); | |
6643 | tcg_temp_free_i64(tcg_op2); | |
6644 | tcg_temp_free_i64(tcg_res); | |
6645 | } | |
6646 | ||
b8f5171c RH |
6647 | /* Floating-point data-processing (2 source) - half precision */ |
6648 | static void handle_fp_2src_half(DisasContext *s, int opcode, | |
6649 | int rd, int rn, int rm) | |
6650 | { | |
6651 | TCGv_i32 tcg_op1; | |
6652 | TCGv_i32 tcg_op2; | |
6653 | TCGv_i32 tcg_res; | |
6654 | TCGv_ptr fpst; | |
6655 | ||
6656 | tcg_res = tcg_temp_new_i32(); | |
cdfb22bb | 6657 | fpst = fpstatus_ptr(FPST_FPCR_F16); |
b8f5171c RH |
6658 | tcg_op1 = read_fp_hreg(s, rn); |
6659 | tcg_op2 = read_fp_hreg(s, rm); | |
6660 | ||
6661 | switch (opcode) { | |
6662 | case 0x0: /* FMUL */ | |
6663 | gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst); | |
6664 | break; | |
6665 | case 0x1: /* FDIV */ | |
6666 | gen_helper_advsimd_divh(tcg_res, tcg_op1, tcg_op2, fpst); | |
6667 | break; | |
6668 | case 0x2: /* FADD */ | |
6669 | gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst); | |
6670 | break; | |
6671 | case 0x3: /* FSUB */ | |
6672 | gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst); | |
6673 | break; | |
6674 | case 0x4: /* FMAX */ | |
6675 | gen_helper_advsimd_maxh(tcg_res, tcg_op1, tcg_op2, fpst); | |
6676 | break; | |
6677 | case 0x5: /* FMIN */ | |
6678 | gen_helper_advsimd_minh(tcg_res, tcg_op1, tcg_op2, fpst); | |
6679 | break; | |
6680 | case 0x6: /* FMAXNM */ | |
6681 | gen_helper_advsimd_maxnumh(tcg_res, tcg_op1, tcg_op2, fpst); | |
6682 | break; | |
6683 | case 0x7: /* FMINNM */ | |
6684 | gen_helper_advsimd_minnumh(tcg_res, tcg_op1, tcg_op2, fpst); | |
6685 | break; | |
6686 | case 0x8: /* FNMUL */ | |
6687 | gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst); | |
6688 | tcg_gen_xori_i32(tcg_res, tcg_res, 0x8000); | |
6689 | break; | |
6690 | default: | |
6691 | g_assert_not_reached(); | |
6692 | } | |
6693 | ||
6694 | write_fp_sreg(s, rd, tcg_res); | |
6695 | ||
6696 | tcg_temp_free_ptr(fpst); | |
6697 | tcg_temp_free_i32(tcg_op1); | |
6698 | tcg_temp_free_i32(tcg_op2); | |
6699 | tcg_temp_free_i32(tcg_res); | |
6700 | } | |
6701 | ||
4ce31af4 | 6702 | /* Floating point data-processing (2 source) |
faa0ba46 PM |
6703 | * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0 |
6704 | * +---+---+---+-----------+------+---+------+--------+-----+------+------+ | |
6705 | * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | opcode | 1 0 | Rn | Rd | | |
6706 | * +---+---+---+-----------+------+---+------+--------+-----+------+------+ | |
6707 | */ | |
6708 | static void disas_fp_2src(DisasContext *s, uint32_t insn) | |
6709 | { | |
c1e20801 | 6710 | int mos = extract32(insn, 29, 3); |
ec73d2e0 AG |
6711 | int type = extract32(insn, 22, 2); |
6712 | int rd = extract32(insn, 0, 5); | |
6713 | int rn = extract32(insn, 5, 5); | |
6714 | int rm = extract32(insn, 16, 5); | |
6715 | int opcode = extract32(insn, 12, 4); | |
6716 | ||
c1e20801 | 6717 | if (opcode > 8 || mos) { |
ec73d2e0 AG |
6718 | unallocated_encoding(s); |
6719 | return; | |
6720 | } | |
6721 | ||
6722 | switch (type) { | |
6723 | case 0: | |
8c6afa6a PM |
6724 | if (!fp_access_check(s)) { |
6725 | return; | |
6726 | } | |
ec73d2e0 AG |
6727 | handle_fp_2src_single(s, opcode, rd, rn, rm); |
6728 | break; | |
6729 | case 1: | |
8c6afa6a PM |
6730 | if (!fp_access_check(s)) { |
6731 | return; | |
6732 | } | |
ec73d2e0 AG |
6733 | handle_fp_2src_double(s, opcode, rd, rn, rm); |
6734 | break; | |
b8f5171c | 6735 | case 3: |
5763190f | 6736 | if (!dc_isar_feature(aa64_fp16, s)) { |
b8f5171c RH |
6737 | unallocated_encoding(s); |
6738 | return; | |
6739 | } | |
6740 | if (!fp_access_check(s)) { | |
6741 | return; | |
6742 | } | |
6743 | handle_fp_2src_half(s, opcode, rd, rn, rm); | |
6744 | break; | |
ec73d2e0 AG |
6745 | default: |
6746 | unallocated_encoding(s); | |
6747 | } | |
faa0ba46 PM |
6748 | } |
6749 | ||
4ce31af4 | 6750 | /* Floating-point data-processing (3 source) - single precision */ |
6a30667f AG |
6751 | static void handle_fp_3src_single(DisasContext *s, bool o0, bool o1, |
6752 | int rd, int rn, int rm, int ra) | |
6753 | { | |
6754 | TCGv_i32 tcg_op1, tcg_op2, tcg_op3; | |
6755 | TCGv_i32 tcg_res = tcg_temp_new_i32(); | |
cdfb22bb | 6756 | TCGv_ptr fpst = fpstatus_ptr(FPST_FPCR); |
6a30667f AG |
6757 | |
6758 | tcg_op1 = read_fp_sreg(s, rn); | |
6759 | tcg_op2 = read_fp_sreg(s, rm); | |
6760 | tcg_op3 = read_fp_sreg(s, ra); | |
6761 | ||
6762 | /* These are fused multiply-add, and must be done as one | |
6763 | * floating point operation with no rounding between the | |
6764 | * multiplication and addition steps. | |
6765 | * NB that doing the negations here as separate steps is | |
6766 | * correct : an input NaN should come out with its sign bit | |
6767 | * flipped if it is a negated-input. | |
6768 | */ | |
6769 | if (o1 == true) { | |
6770 | gen_helper_vfp_negs(tcg_op3, tcg_op3); | |
6771 | } | |
6772 | ||
6773 | if (o0 != o1) { | |
6774 | gen_helper_vfp_negs(tcg_op1, tcg_op1); | |
6775 | } | |
6776 | ||
6777 | gen_helper_vfp_muladds(tcg_res, tcg_op1, tcg_op2, tcg_op3, fpst); | |
6778 | ||
6779 | write_fp_sreg(s, rd, tcg_res); | |
6780 | ||
6781 | tcg_temp_free_ptr(fpst); | |
6782 | tcg_temp_free_i32(tcg_op1); | |
6783 | tcg_temp_free_i32(tcg_op2); | |
6784 | tcg_temp_free_i32(tcg_op3); | |
6785 | tcg_temp_free_i32(tcg_res); | |
6786 | } | |
6787 | ||
4ce31af4 | 6788 | /* Floating-point data-processing (3 source) - double precision */ |
6a30667f AG |
6789 | static void handle_fp_3src_double(DisasContext *s, bool o0, bool o1, |
6790 | int rd, int rn, int rm, int ra) | |
6791 | { | |
6792 | TCGv_i64 tcg_op1, tcg_op2, tcg_op3; | |
6793 | TCGv_i64 tcg_res = tcg_temp_new_i64(); | |
cdfb22bb | 6794 | TCGv_ptr fpst = fpstatus_ptr(FPST_FPCR); |
6a30667f AG |
6795 | |
6796 | tcg_op1 = read_fp_dreg(s, rn); | |
6797 | tcg_op2 = read_fp_dreg(s, rm); | |
6798 | tcg_op3 = read_fp_dreg(s, ra); | |
6799 | ||
6800 | /* These are fused multiply-add, and must be done as one | |
6801 | * floating point operation with no rounding between the | |
6802 | * multiplication and addition steps. | |
6803 | * NB that doing the negations here as separate steps is | |
6804 | * correct : an input NaN should come out with its sign bit | |
6805 | * flipped if it is a negated-input. | |
6806 | */ | |
6807 | if (o1 == true) { | |
6808 | gen_helper_vfp_negd(tcg_op3, tcg_op3); | |
6809 | } | |
6810 | ||
6811 | if (o0 != o1) { | |
6812 | gen_helper_vfp_negd(tcg_op1, tcg_op1); | |
6813 | } | |
6814 | ||
6815 | gen_helper_vfp_muladdd(tcg_res, tcg_op1, tcg_op2, tcg_op3, fpst); | |
6816 | ||
6817 | write_fp_dreg(s, rd, tcg_res); | |
6818 | ||
6819 | tcg_temp_free_ptr(fpst); | |
6820 | tcg_temp_free_i64(tcg_op1); | |
6821 | tcg_temp_free_i64(tcg_op2); | |
6822 | tcg_temp_free_i64(tcg_op3); | |
6823 | tcg_temp_free_i64(tcg_res); | |
6824 | } | |
6825 | ||
95f9864f RH |
6826 | /* Floating-point data-processing (3 source) - half precision */ |
6827 | static void handle_fp_3src_half(DisasContext *s, bool o0, bool o1, | |
6828 | int rd, int rn, int rm, int ra) | |
6829 | { | |
6830 | TCGv_i32 tcg_op1, tcg_op2, tcg_op3; | |
6831 | TCGv_i32 tcg_res = tcg_temp_new_i32(); | |
cdfb22bb | 6832 | TCGv_ptr fpst = fpstatus_ptr(FPST_FPCR_F16); |
95f9864f RH |
6833 | |
6834 | tcg_op1 = read_fp_hreg(s, rn); | |
6835 | tcg_op2 = read_fp_hreg(s, rm); | |
6836 | tcg_op3 = read_fp_hreg(s, ra); | |
6837 | ||
6838 | /* These are fused multiply-add, and must be done as one | |
6839 | * floating point operation with no rounding between the | |
6840 | * multiplication and addition steps. | |
6841 | * NB that doing the negations here as separate steps is | |
6842 | * correct : an input NaN should come out with its sign bit | |
6843 | * flipped if it is a negated-input. | |
6844 | */ | |
6845 | if (o1 == true) { | |
6846 | tcg_gen_xori_i32(tcg_op3, tcg_op3, 0x8000); | |
6847 | } | |
6848 | ||
6849 | if (o0 != o1) { | |
6850 | tcg_gen_xori_i32(tcg_op1, tcg_op1, 0x8000); | |
6851 | } | |
6852 | ||
6853 | gen_helper_advsimd_muladdh(tcg_res, tcg_op1, tcg_op2, tcg_op3, fpst); | |
6854 | ||
6855 | write_fp_sreg(s, rd, tcg_res); | |
6856 | ||
6857 | tcg_temp_free_ptr(fpst); | |
6858 | tcg_temp_free_i32(tcg_op1); | |
6859 | tcg_temp_free_i32(tcg_op2); | |
6860 | tcg_temp_free_i32(tcg_op3); | |
6861 | tcg_temp_free_i32(tcg_res); | |
6862 | } | |
6863 | ||
4ce31af4 | 6864 | /* Floating point data-processing (3 source) |
faa0ba46 PM |
6865 | * 31 30 29 28 24 23 22 21 20 16 15 14 10 9 5 4 0 |
6866 | * +---+---+---+-----------+------+----+------+----+------+------+------+ | |
6867 | * | M | 0 | S | 1 1 1 1 1 | type | o1 | Rm | o0 | Ra | Rn | Rd | | |
6868 | * +---+---+---+-----------+------+----+------+----+------+------+------+ | |
6869 | */ | |
6870 | static void disas_fp_3src(DisasContext *s, uint32_t insn) | |
6871 | { | |
c1e20801 | 6872 | int mos = extract32(insn, 29, 3); |
6a30667f AG |
6873 | int type = extract32(insn, 22, 2); |
6874 | int rd = extract32(insn, 0, 5); | |
6875 | int rn = extract32(insn, 5, 5); | |
6876 | int ra = extract32(insn, 10, 5); | |
6877 | int rm = extract32(insn, 16, 5); | |
6878 | bool o0 = extract32(insn, 15, 1); | |
6879 | bool o1 = extract32(insn, 21, 1); | |
6880 | ||
c1e20801 PM |
6881 | if (mos) { |
6882 | unallocated_encoding(s); | |
6883 | return; | |
6884 | } | |
6885 | ||
6a30667f AG |
6886 | switch (type) { |
6887 | case 0: | |
8c6afa6a PM |
6888 | if (!fp_access_check(s)) { |
6889 | return; | |
6890 | } | |
6a30667f AG |
6891 | handle_fp_3src_single(s, o0, o1, rd, rn, rm, ra); |
6892 | break; | |
6893 | case 1: | |
8c6afa6a PM |
6894 | if (!fp_access_check(s)) { |
6895 | return; | |
6896 | } | |
6a30667f AG |
6897 | handle_fp_3src_double(s, o0, o1, rd, rn, rm, ra); |
6898 | break; | |
95f9864f | 6899 | case 3: |
5763190f | 6900 | if (!dc_isar_feature(aa64_fp16, s)) { |
95f9864f RH |
6901 | unallocated_encoding(s); |
6902 | return; | |
6903 | } | |
6904 | if (!fp_access_check(s)) { | |
6905 | return; | |
6906 | } | |
6907 | handle_fp_3src_half(s, o0, o1, rd, rn, rm, ra); | |
6908 | break; | |
6a30667f AG |
6909 | default: |
6910 | unallocated_encoding(s); | |
6911 | } | |
faa0ba46 PM |
6912 | } |
6913 | ||
4ce31af4 | 6914 | /* Floating point immediate |
faa0ba46 PM |
6915 | * 31 30 29 28 24 23 22 21 20 13 12 10 9 5 4 0 |
6916 | * +---+---+---+-----------+------+---+------------+-------+------+------+ | |
6917 | * | M | 0 | S | 1 1 1 1 0 | type | 1 | imm8 | 1 0 0 | imm5 | Rd | | |
6918 | * +---+---+---+-----------+------+---+------------+-------+------+------+ | |
6919 | */ | |
6920 | static void disas_fp_imm(DisasContext *s, uint32_t insn) | |
6921 | { | |
6163f868 | 6922 | int rd = extract32(insn, 0, 5); |
c1e20801 | 6923 | int imm5 = extract32(insn, 5, 5); |
6163f868 | 6924 | int imm8 = extract32(insn, 13, 8); |
6ba28ddb | 6925 | int type = extract32(insn, 22, 2); |
c1e20801 | 6926 | int mos = extract32(insn, 29, 3); |
6163f868 AG |
6927 | uint64_t imm; |
6928 | TCGv_i64 tcg_res; | |
14776ab5 | 6929 | MemOp sz; |
6163f868 | 6930 | |
c1e20801 PM |
6931 | if (mos || imm5) { |
6932 | unallocated_encoding(s); | |
6933 | return; | |
6934 | } | |
6935 | ||
6ba28ddb AB |
6936 | switch (type) { |
6937 | case 0: | |
6938 | sz = MO_32; | |
6939 | break; | |
6940 | case 1: | |
6941 | sz = MO_64; | |
6942 | break; | |
6943 | case 3: | |
6944 | sz = MO_16; | |
5763190f | 6945 | if (dc_isar_feature(aa64_fp16, s)) { |
6ba28ddb AB |
6946 | break; |
6947 | } | |
6948 | /* fallthru */ | |
6949 | default: | |
6163f868 AG |
6950 | unallocated_encoding(s); |
6951 | return; | |
6952 | } | |
6953 | ||
8c6afa6a PM |
6954 | if (!fp_access_check(s)) { |
6955 | return; | |
6956 | } | |
6957 | ||
6ba28ddb | 6958 | imm = vfp_expand_imm(sz, imm8); |
6163f868 AG |
6959 | |
6960 | tcg_res = tcg_const_i64(imm); | |
6961 | write_fp_dreg(s, rd, tcg_res); | |
6962 | tcg_temp_free_i64(tcg_res); | |
faa0ba46 PM |
6963 | } |
6964 | ||
52a1f6a3 AG |
6965 | /* Handle floating point <=> fixed point conversions. Note that we can |
6966 | * also deal with fp <=> integer conversions as a special case (scale == 64) | |
6967 | * OPTME: consider handling that special case specially or at least skipping | |
6968 | * the call to scalbn in the helpers for zero shifts. | |
6969 | */ | |
6970 | static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode, | |
6971 | bool itof, int rmode, int scale, int sf, int type) | |
6972 | { | |
6973 | bool is_signed = !(opcode & 1); | |
52a1f6a3 | 6974 | TCGv_ptr tcg_fpstatus; |
564a0632 RH |
6975 | TCGv_i32 tcg_shift, tcg_single; |
6976 | TCGv_i64 tcg_double; | |
52a1f6a3 | 6977 | |
cdfb22bb | 6978 | tcg_fpstatus = fpstatus_ptr(type == 3 ? FPST_FPCR_F16 : FPST_FPCR); |
52a1f6a3 AG |
6979 | |
6980 | tcg_shift = tcg_const_i32(64 - scale); | |
6981 | ||
6982 | if (itof) { | |
6983 | TCGv_i64 tcg_int = cpu_reg(s, rn); | |
6984 | if (!sf) { | |
6985 | TCGv_i64 tcg_extend = new_tmp_a64(s); | |
6986 | ||
6987 | if (is_signed) { | |
6988 | tcg_gen_ext32s_i64(tcg_extend, tcg_int); | |
6989 | } else { | |
6990 | tcg_gen_ext32u_i64(tcg_extend, tcg_int); | |
6991 | } | |
6992 | ||
6993 | tcg_int = tcg_extend; | |
6994 | } | |
6995 | ||
564a0632 RH |
6996 | switch (type) { |
6997 | case 1: /* float64 */ | |
6998 | tcg_double = tcg_temp_new_i64(); | |
52a1f6a3 AG |
6999 | if (is_signed) { |
7000 | gen_helper_vfp_sqtod(tcg_double, tcg_int, | |
7001 | tcg_shift, tcg_fpstatus); | |
7002 | } else { | |
7003 | gen_helper_vfp_uqtod(tcg_double, tcg_int, | |
7004 | tcg_shift, tcg_fpstatus); | |
7005 | } | |
7006 | write_fp_dreg(s, rd, tcg_double); | |
7007 | tcg_temp_free_i64(tcg_double); | |
564a0632 RH |
7008 | break; |
7009 | ||
7010 | case 0: /* float32 */ | |
7011 | tcg_single = tcg_temp_new_i32(); | |
52a1f6a3 AG |
7012 | if (is_signed) { |
7013 | gen_helper_vfp_sqtos(tcg_single, tcg_int, | |
7014 | tcg_shift, tcg_fpstatus); | |
7015 | } else { | |
7016 | gen_helper_vfp_uqtos(tcg_single, tcg_int, | |
7017 | tcg_shift, tcg_fpstatus); | |
7018 | } | |
7019 | write_fp_sreg(s, rd, tcg_single); | |
7020 | tcg_temp_free_i32(tcg_single); | |
564a0632 RH |
7021 | break; |
7022 | ||
7023 | case 3: /* float16 */ | |
7024 | tcg_single = tcg_temp_new_i32(); | |
7025 | if (is_signed) { | |
7026 | gen_helper_vfp_sqtoh(tcg_single, tcg_int, | |
7027 | tcg_shift, tcg_fpstatus); | |
7028 | } else { | |
7029 | gen_helper_vfp_uqtoh(tcg_single, tcg_int, | |
7030 | tcg_shift, tcg_fpstatus); | |
7031 | } | |
7032 | write_fp_sreg(s, rd, tcg_single); | |
7033 | tcg_temp_free_i32(tcg_single); | |
7034 | break; | |
7035 | ||
7036 | default: | |
7037 | g_assert_not_reached(); | |
52a1f6a3 AG |
7038 | } |
7039 | } else { | |
7040 | TCGv_i64 tcg_int = cpu_reg(s, rd); | |
7041 | TCGv_i32 tcg_rmode; | |
7042 | ||
7043 | if (extract32(opcode, 2, 1)) { | |
7044 | /* There are too many rounding modes to all fit into rmode, | |
7045 | * so FCVTA[US] is a special case. | |
7046 | */ | |
7047 | rmode = FPROUNDING_TIEAWAY; | |
7048 | } | |
7049 | ||
7050 | tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode)); | |
7051 | ||
9b049916 | 7052 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); |
52a1f6a3 | 7053 | |
564a0632 RH |
7054 | switch (type) { |
7055 | case 1: /* float64 */ | |
7056 | tcg_double = read_fp_dreg(s, rn); | |
52a1f6a3 AG |
7057 | if (is_signed) { |
7058 | if (!sf) { | |
7059 | gen_helper_vfp_tosld(tcg_int, tcg_double, | |
7060 | tcg_shift, tcg_fpstatus); | |
7061 | } else { | |
7062 | gen_helper_vfp_tosqd(tcg_int, tcg_double, | |
7063 | tcg_shift, tcg_fpstatus); | |
7064 | } | |
7065 | } else { | |
7066 | if (!sf) { | |
7067 | gen_helper_vfp_tould(tcg_int, tcg_double, | |
7068 | tcg_shift, tcg_fpstatus); | |
7069 | } else { | |
7070 | gen_helper_vfp_touqd(tcg_int, tcg_double, | |
7071 | tcg_shift, tcg_fpstatus); | |
7072 | } | |
7073 | } | |
564a0632 RH |
7074 | if (!sf) { |
7075 | tcg_gen_ext32u_i64(tcg_int, tcg_int); | |
7076 | } | |
52a1f6a3 | 7077 | tcg_temp_free_i64(tcg_double); |
564a0632 RH |
7078 | break; |
7079 | ||
7080 | case 0: /* float32 */ | |
7081 | tcg_single = read_fp_sreg(s, rn); | |
52a1f6a3 AG |
7082 | if (sf) { |
7083 | if (is_signed) { | |
7084 | gen_helper_vfp_tosqs(tcg_int, tcg_single, | |
7085 | tcg_shift, tcg_fpstatus); | |
7086 | } else { | |
7087 | gen_helper_vfp_touqs(tcg_int, tcg_single, | |
7088 | tcg_shift, tcg_fpstatus); | |
7089 | } | |
7090 | } else { | |
7091 | TCGv_i32 tcg_dest = tcg_temp_new_i32(); | |
7092 | if (is_signed) { | |
7093 | gen_helper_vfp_tosls(tcg_dest, tcg_single, | |
7094 | tcg_shift, tcg_fpstatus); | |
7095 | } else { | |
7096 | gen_helper_vfp_touls(tcg_dest, tcg_single, | |
7097 | tcg_shift, tcg_fpstatus); | |
7098 | } | |
7099 | tcg_gen_extu_i32_i64(tcg_int, tcg_dest); | |
7100 | tcg_temp_free_i32(tcg_dest); | |
7101 | } | |
7102 | tcg_temp_free_i32(tcg_single); | |
564a0632 RH |
7103 | break; |
7104 | ||
7105 | case 3: /* float16 */ | |
7106 | tcg_single = read_fp_sreg(s, rn); | |
7107 | if (sf) { | |
7108 | if (is_signed) { | |
7109 | gen_helper_vfp_tosqh(tcg_int, tcg_single, | |
7110 | tcg_shift, tcg_fpstatus); | |
7111 | } else { | |
7112 | gen_helper_vfp_touqh(tcg_int, tcg_single, | |
7113 | tcg_shift, tcg_fpstatus); | |
7114 | } | |
7115 | } else { | |
7116 | TCGv_i32 tcg_dest = tcg_temp_new_i32(); | |
7117 | if (is_signed) { | |
7118 | gen_helper_vfp_toslh(tcg_dest, tcg_single, | |
7119 | tcg_shift, tcg_fpstatus); | |
7120 | } else { | |
7121 | gen_helper_vfp_toulh(tcg_dest, tcg_single, | |
7122 | tcg_shift, tcg_fpstatus); | |
7123 | } | |
7124 | tcg_gen_extu_i32_i64(tcg_int, tcg_dest); | |
7125 | tcg_temp_free_i32(tcg_dest); | |
7126 | } | |
7127 | tcg_temp_free_i32(tcg_single); | |
7128 | break; | |
7129 | ||
7130 | default: | |
7131 | g_assert_not_reached(); | |
52a1f6a3 AG |
7132 | } |
7133 | ||
9b049916 | 7134 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); |
52a1f6a3 | 7135 | tcg_temp_free_i32(tcg_rmode); |
52a1f6a3 AG |
7136 | } |
7137 | ||
7138 | tcg_temp_free_ptr(tcg_fpstatus); | |
7139 | tcg_temp_free_i32(tcg_shift); | |
7140 | } | |
7141 | ||
4ce31af4 | 7142 | /* Floating point <-> fixed point conversions |
faa0ba46 PM |
7143 | * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0 |
7144 | * +----+---+---+-----------+------+---+-------+--------+-------+------+------+ | |
7145 | * | sf | 0 | S | 1 1 1 1 0 | type | 0 | rmode | opcode | scale | Rn | Rd | | |
7146 | * +----+---+---+-----------+------+---+-------+--------+-------+------+------+ | |
7147 | */ | |
7148 | static void disas_fp_fixed_conv(DisasContext *s, uint32_t insn) | |
7149 | { | |
52a1f6a3 AG |
7150 | int rd = extract32(insn, 0, 5); |
7151 | int rn = extract32(insn, 5, 5); | |
7152 | int scale = extract32(insn, 10, 6); | |
7153 | int opcode = extract32(insn, 16, 3); | |
7154 | int rmode = extract32(insn, 19, 2); | |
7155 | int type = extract32(insn, 22, 2); | |
7156 | bool sbit = extract32(insn, 29, 1); | |
7157 | bool sf = extract32(insn, 31, 1); | |
7158 | bool itof; | |
7159 | ||
27527280 RH |
7160 | if (sbit || (!sf && scale < 32)) { |
7161 | unallocated_encoding(s); | |
7162 | return; | |
7163 | } | |
7164 | ||
7165 | switch (type) { | |
7166 | case 0: /* float32 */ | |
7167 | case 1: /* float64 */ | |
7168 | break; | |
7169 | case 3: /* float16 */ | |
5763190f | 7170 | if (dc_isar_feature(aa64_fp16, s)) { |
27527280 RH |
7171 | break; |
7172 | } | |
7173 | /* fallthru */ | |
7174 | default: | |
52a1f6a3 AG |
7175 | unallocated_encoding(s); |
7176 | return; | |
7177 | } | |
7178 | ||
7179 | switch ((rmode << 3) | opcode) { | |
7180 | case 0x2: /* SCVTF */ | |
7181 | case 0x3: /* UCVTF */ | |
7182 | itof = true; | |
7183 | break; | |
7184 | case 0x18: /* FCVTZS */ | |
7185 | case 0x19: /* FCVTZU */ | |
7186 | itof = false; | |
7187 | break; | |
7188 | default: | |
7189 | unallocated_encoding(s); | |
7190 | return; | |
7191 | } | |
7192 | ||
8c6afa6a PM |
7193 | if (!fp_access_check(s)) { |
7194 | return; | |
7195 | } | |
7196 | ||
52a1f6a3 | 7197 | handle_fpfpcvt(s, rd, rn, opcode, itof, FPROUNDING_ZERO, scale, sf, type); |
faa0ba46 PM |
7198 | } |
7199 | ||
ce5458e8 PM |
7200 | static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof) |
7201 | { | |
7202 | /* FMOV: gpr to or from float, double, or top half of quad fp reg, | |
7203 | * without conversion. | |
7204 | */ | |
7205 | ||
7206 | if (itof) { | |
ce5458e8 | 7207 | TCGv_i64 tcg_rn = cpu_reg(s, rn); |
9a9f1f59 | 7208 | TCGv_i64 tmp; |
ce5458e8 PM |
7209 | |
7210 | switch (type) { | |
7211 | case 0: | |
ce5458e8 | 7212 | /* 32 bit */ |
9a9f1f59 | 7213 | tmp = tcg_temp_new_i64(); |
ce5458e8 | 7214 | tcg_gen_ext32u_i64(tmp, tcg_rn); |
9a9f1f59 | 7215 | write_fp_dreg(s, rd, tmp); |
ce5458e8 PM |
7216 | tcg_temp_free_i64(tmp); |
7217 | break; | |
ce5458e8 | 7218 | case 1: |
ce5458e8 | 7219 | /* 64 bit */ |
9a9f1f59 | 7220 | write_fp_dreg(s, rd, tcg_rn); |
ce5458e8 | 7221 | break; |
ce5458e8 PM |
7222 | case 2: |
7223 | /* 64 bit to top half. */ | |
90e49638 | 7224 | tcg_gen_st_i64(tcg_rn, cpu_env, fp_reg_hi_offset(s, rd)); |
9a9f1f59 | 7225 | clear_vec_high(s, true, rd); |
ce5458e8 | 7226 | break; |
68130236 RH |
7227 | case 3: |
7228 | /* 16 bit */ | |
7229 | tmp = tcg_temp_new_i64(); | |
7230 | tcg_gen_ext16u_i64(tmp, tcg_rn); | |
7231 | write_fp_dreg(s, rd, tmp); | |
7232 | tcg_temp_free_i64(tmp); | |
7233 | break; | |
7234 | default: | |
7235 | g_assert_not_reached(); | |
ce5458e8 PM |
7236 | } |
7237 | } else { | |
ce5458e8 PM |
7238 | TCGv_i64 tcg_rd = cpu_reg(s, rd); |
7239 | ||
7240 | switch (type) { | |
7241 | case 0: | |
7242 | /* 32 bit */ | |
90e49638 | 7243 | tcg_gen_ld32u_i64(tcg_rd, cpu_env, fp_reg_offset(s, rn, MO_32)); |
ce5458e8 | 7244 | break; |
ce5458e8 PM |
7245 | case 1: |
7246 | /* 64 bit */ | |
90e49638 | 7247 | tcg_gen_ld_i64(tcg_rd, cpu_env, fp_reg_offset(s, rn, MO_64)); |
e2f90565 PM |
7248 | break; |
7249 | case 2: | |
7250 | /* 64 bits from top half */ | |
90e49638 | 7251 | tcg_gen_ld_i64(tcg_rd, cpu_env, fp_reg_hi_offset(s, rn)); |
ce5458e8 | 7252 | break; |
68130236 RH |
7253 | case 3: |
7254 | /* 16 bit */ | |
7255 | tcg_gen_ld16u_i64(tcg_rd, cpu_env, fp_reg_offset(s, rn, MO_16)); | |
7256 | break; | |
7257 | default: | |
7258 | g_assert_not_reached(); | |
ce5458e8 PM |
7259 | } |
7260 | } | |
7261 | } | |
7262 | ||
6c1f6f27 RH |
7263 | static void handle_fjcvtzs(DisasContext *s, int rd, int rn) |
7264 | { | |
7265 | TCGv_i64 t = read_fp_dreg(s, rn); | |
cdfb22bb | 7266 | TCGv_ptr fpstatus = fpstatus_ptr(FPST_FPCR); |
6c1f6f27 RH |
7267 | |
7268 | gen_helper_fjcvtzs(t, t, fpstatus); | |
7269 | ||
7270 | tcg_temp_free_ptr(fpstatus); | |
7271 | ||
7272 | tcg_gen_ext32u_i64(cpu_reg(s, rd), t); | |
7273 | tcg_gen_extrh_i64_i32(cpu_ZF, t); | |
7274 | tcg_gen_movi_i32(cpu_CF, 0); | |
7275 | tcg_gen_movi_i32(cpu_NF, 0); | |
7276 | tcg_gen_movi_i32(cpu_VF, 0); | |
7277 | ||
7278 | tcg_temp_free_i64(t); | |
7279 | } | |
7280 | ||
4ce31af4 | 7281 | /* Floating point <-> integer conversions |
faa0ba46 PM |
7282 | * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0 |
7283 | * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+ | |
c436d406 | 7284 | * | sf | 0 | S | 1 1 1 1 0 | type | 1 | rmode | opc | 0 0 0 0 0 0 | Rn | Rd | |
faa0ba46 PM |
7285 | * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+ |
7286 | */ | |
7287 | static void disas_fp_int_conv(DisasContext *s, uint32_t insn) | |
7288 | { | |
ce5458e8 PM |
7289 | int rd = extract32(insn, 0, 5); |
7290 | int rn = extract32(insn, 5, 5); | |
7291 | int opcode = extract32(insn, 16, 3); | |
7292 | int rmode = extract32(insn, 19, 2); | |
7293 | int type = extract32(insn, 22, 2); | |
7294 | bool sbit = extract32(insn, 29, 1); | |
7295 | bool sf = extract32(insn, 31, 1); | |
3c3ff684 | 7296 | bool itof = false; |
ce5458e8 | 7297 | |
c436d406 | 7298 | if (sbit) { |
3c3ff684 | 7299 | goto do_unallocated; |
c436d406 WN |
7300 | } |
7301 | ||
3c3ff684 RH |
7302 | switch (opcode) { |
7303 | case 2: /* SCVTF */ | |
7304 | case 3: /* UCVTF */ | |
7305 | itof = true; | |
7306 | /* fallthru */ | |
7307 | case 4: /* FCVTAS */ | |
7308 | case 5: /* FCVTAU */ | |
7309 | if (rmode != 0) { | |
7310 | goto do_unallocated; | |
c436d406 | 7311 | } |
3c3ff684 RH |
7312 | /* fallthru */ |
7313 | case 0: /* FCVT[NPMZ]S */ | |
7314 | case 1: /* FCVT[NPMZ]U */ | |
7315 | switch (type) { | |
7316 | case 0: /* float32 */ | |
7317 | case 1: /* float64 */ | |
ce5458e8 | 7318 | break; |
3c3ff684 RH |
7319 | case 3: /* float16 */ |
7320 | if (!dc_isar_feature(aa64_fp16, s)) { | |
7321 | goto do_unallocated; | |
68130236 | 7322 | } |
3c3ff684 | 7323 | break; |
ce5458e8 | 7324 | default: |
3c3ff684 | 7325 | goto do_unallocated; |
ce5458e8 | 7326 | } |
8c6afa6a PM |
7327 | if (!fp_access_check(s)) { |
7328 | return; | |
7329 | } | |
3c3ff684 RH |
7330 | handle_fpfpcvt(s, rd, rn, opcode, itof, rmode, 64, sf, type); |
7331 | break; | |
c436d406 | 7332 | |
3c3ff684 RH |
7333 | default: |
7334 | switch (sf << 7 | type << 5 | rmode << 3 | opcode) { | |
7335 | case 0b01100110: /* FMOV half <-> 32-bit int */ | |
7336 | case 0b01100111: | |
7337 | case 0b11100110: /* FMOV half <-> 64-bit int */ | |
7338 | case 0b11100111: | |
7339 | if (!dc_isar_feature(aa64_fp16, s)) { | |
7340 | goto do_unallocated; | |
564a0632 RH |
7341 | } |
7342 | /* fallthru */ | |
3c3ff684 RH |
7343 | case 0b00000110: /* FMOV 32-bit */ |
7344 | case 0b00000111: | |
7345 | case 0b10100110: /* FMOV 64-bit */ | |
7346 | case 0b10100111: | |
7347 | case 0b11001110: /* FMOV top half of 128-bit */ | |
7348 | case 0b11001111: | |
7349 | if (!fp_access_check(s)) { | |
7350 | return; | |
7351 | } | |
7352 | itof = opcode & 1; | |
7353 | handle_fmov(s, rd, rn, type, itof); | |
7354 | break; | |
7355 | ||
6c1f6f27 RH |
7356 | case 0b00111110: /* FJCVTZS */ |
7357 | if (!dc_isar_feature(aa64_jscvt, s)) { | |
7358 | goto do_unallocated; | |
7359 | } else if (fp_access_check(s)) { | |
7360 | handle_fjcvtzs(s, rd, rn); | |
7361 | } | |
7362 | break; | |
7363 | ||
564a0632 | 7364 | default: |
3c3ff684 | 7365 | do_unallocated: |
c436d406 WN |
7366 | unallocated_encoding(s); |
7367 | return; | |
7368 | } | |
3c3ff684 | 7369 | break; |
ce5458e8 | 7370 | } |
faa0ba46 PM |
7371 | } |
7372 | ||
7373 | /* FP-specific subcases of table C3-6 (SIMD and FP data processing) | |
7374 | * 31 30 29 28 25 24 0 | |
7375 | * +---+---+---+---------+-----------------------------+ | |
7376 | * | | 0 | | 1 1 1 1 | | | |
7377 | * +---+---+---+---------+-----------------------------+ | |
7378 | */ | |
7379 | static void disas_data_proc_fp(DisasContext *s, uint32_t insn) | |
7380 | { | |
7381 | if (extract32(insn, 24, 1)) { | |
7382 | /* Floating point data-processing (3 source) */ | |
7383 | disas_fp_3src(s, insn); | |
7384 | } else if (extract32(insn, 21, 1) == 0) { | |
7385 | /* Floating point to fixed point conversions */ | |
7386 | disas_fp_fixed_conv(s, insn); | |
7387 | } else { | |
7388 | switch (extract32(insn, 10, 2)) { | |
7389 | case 1: | |
7390 | /* Floating point conditional compare */ | |
7391 | disas_fp_ccomp(s, insn); | |
7392 | break; | |
7393 | case 2: | |
7394 | /* Floating point data-processing (2 source) */ | |
7395 | disas_fp_2src(s, insn); | |
7396 | break; | |
7397 | case 3: | |
7398 | /* Floating point conditional select */ | |
7399 | disas_fp_csel(s, insn); | |
7400 | break; | |
7401 | case 0: | |
7402 | switch (ctz32(extract32(insn, 12, 4))) { | |
7403 | case 0: /* [15:12] == xxx1 */ | |
7404 | /* Floating point immediate */ | |
7405 | disas_fp_imm(s, insn); | |
7406 | break; | |
7407 | case 1: /* [15:12] == xx10 */ | |
7408 | /* Floating point compare */ | |
7409 | disas_fp_compare(s, insn); | |
7410 | break; | |
7411 | case 2: /* [15:12] == x100 */ | |
7412 | /* Floating point data-processing (1 source) */ | |
7413 | disas_fp_1src(s, insn); | |
7414 | break; | |
7415 | case 3: /* [15:12] == 1000 */ | |
7416 | unallocated_encoding(s); | |
7417 | break; | |
7418 | default: /* [15:12] == 0000 */ | |
7419 | /* Floating point <-> integer conversions */ | |
7420 | disas_fp_int_conv(s, insn); | |
7421 | break; | |
7422 | } | |
7423 | break; | |
7424 | } | |
7425 | } | |
7426 | } | |
7427 | ||
5c73747f PM |
7428 | static void do_ext64(DisasContext *s, TCGv_i64 tcg_left, TCGv_i64 tcg_right, |
7429 | int pos) | |
7430 | { | |
7431 | /* Extract 64 bits from the middle of two concatenated 64 bit | |
7432 | * vector register slices left:right. The extracted bits start | |
7433 | * at 'pos' bits into the right (least significant) side. | |
7434 | * We return the result in tcg_right, and guarantee not to | |
7435 | * trash tcg_left. | |
7436 | */ | |
7437 | TCGv_i64 tcg_tmp = tcg_temp_new_i64(); | |
7438 | assert(pos > 0 && pos < 64); | |
7439 | ||
7440 | tcg_gen_shri_i64(tcg_right, tcg_right, pos); | |
7441 | tcg_gen_shli_i64(tcg_tmp, tcg_left, 64 - pos); | |
7442 | tcg_gen_or_i64(tcg_right, tcg_right, tcg_tmp); | |
7443 | ||
7444 | tcg_temp_free_i64(tcg_tmp); | |
7445 | } | |
7446 | ||
4ce31af4 | 7447 | /* EXT |
384b26fb AB |
7448 | * 31 30 29 24 23 22 21 20 16 15 14 11 10 9 5 4 0 |
7449 | * +---+---+-------------+-----+---+------+---+------+---+------+------+ | |
7450 | * | 0 | Q | 1 0 1 1 1 0 | op2 | 0 | Rm | 0 | imm4 | 0 | Rn | Rd | | |
7451 | * +---+---+-------------+-----+---+------+---+------+---+------+------+ | |
7452 | */ | |
7453 | static void disas_simd_ext(DisasContext *s, uint32_t insn) | |
7454 | { | |
5c73747f PM |
7455 | int is_q = extract32(insn, 30, 1); |
7456 | int op2 = extract32(insn, 22, 2); | |
7457 | int imm4 = extract32(insn, 11, 4); | |
7458 | int rm = extract32(insn, 16, 5); | |
7459 | int rn = extract32(insn, 5, 5); | |
7460 | int rd = extract32(insn, 0, 5); | |
7461 | int pos = imm4 << 3; | |
7462 | TCGv_i64 tcg_resl, tcg_resh; | |
7463 | ||
7464 | if (op2 != 0 || (!is_q && extract32(imm4, 3, 1))) { | |
7465 | unallocated_encoding(s); | |
7466 | return; | |
7467 | } | |
7468 | ||
8c6afa6a PM |
7469 | if (!fp_access_check(s)) { |
7470 | return; | |
7471 | } | |
7472 | ||
5c73747f PM |
7473 | tcg_resh = tcg_temp_new_i64(); |
7474 | tcg_resl = tcg_temp_new_i64(); | |
7475 | ||
7476 | /* Vd gets bits starting at pos bits into Vm:Vn. This is | |
7477 | * either extracting 128 bits from a 128:128 concatenation, or | |
7478 | * extracting 64 bits from a 64:64 concatenation. | |
7479 | */ | |
7480 | if (!is_q) { | |
7481 | read_vec_element(s, tcg_resl, rn, 0, MO_64); | |
7482 | if (pos != 0) { | |
7483 | read_vec_element(s, tcg_resh, rm, 0, MO_64); | |
7484 | do_ext64(s, tcg_resh, tcg_resl, pos); | |
7485 | } | |
5c73747f PM |
7486 | } else { |
7487 | TCGv_i64 tcg_hh; | |
7488 | typedef struct { | |
7489 | int reg; | |
7490 | int elt; | |
7491 | } EltPosns; | |
7492 | EltPosns eltposns[] = { {rn, 0}, {rn, 1}, {rm, 0}, {rm, 1} }; | |
7493 | EltPosns *elt = eltposns; | |
7494 | ||
7495 | if (pos >= 64) { | |
7496 | elt++; | |
7497 | pos -= 64; | |
7498 | } | |
7499 | ||
7500 | read_vec_element(s, tcg_resl, elt->reg, elt->elt, MO_64); | |
7501 | elt++; | |
7502 | read_vec_element(s, tcg_resh, elt->reg, elt->elt, MO_64); | |
7503 | elt++; | |
7504 | if (pos != 0) { | |
7505 | do_ext64(s, tcg_resh, tcg_resl, pos); | |
7506 | tcg_hh = tcg_temp_new_i64(); | |
7507 | read_vec_element(s, tcg_hh, elt->reg, elt->elt, MO_64); | |
7508 | do_ext64(s, tcg_hh, tcg_resh, pos); | |
7509 | tcg_temp_free_i64(tcg_hh); | |
7510 | } | |
7511 | } | |
7512 | ||
7513 | write_vec_element(s, tcg_resl, rd, 0, MO_64); | |
7514 | tcg_temp_free_i64(tcg_resl); | |
e1f77859 RH |
7515 | if (is_q) { |
7516 | write_vec_element(s, tcg_resh, rd, 1, MO_64); | |
7517 | } | |
5c73747f | 7518 | tcg_temp_free_i64(tcg_resh); |
e1f77859 | 7519 | clear_vec_high(s, is_q, rd); |
384b26fb AB |
7520 | } |
7521 | ||
4ce31af4 | 7522 | /* TBL/TBX |
384b26fb AB |
7523 | * 31 30 29 24 23 22 21 20 16 15 14 13 12 11 10 9 5 4 0 |
7524 | * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+ | |
7525 | * | 0 | Q | 0 0 1 1 1 0 | op2 | 0 | Rm | 0 | len | op | 0 0 | Rn | Rd | | |
7526 | * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+ | |
7527 | */ | |
7528 | static void disas_simd_tb(DisasContext *s, uint32_t insn) | |
7529 | { | |
7c51048f MM |
7530 | int op2 = extract32(insn, 22, 2); |
7531 | int is_q = extract32(insn, 30, 1); | |
7532 | int rm = extract32(insn, 16, 5); | |
7533 | int rn = extract32(insn, 5, 5); | |
7534 | int rd = extract32(insn, 0, 5); | |
519183d3 RH |
7535 | int is_tbx = extract32(insn, 12, 1); |
7536 | int len = (extract32(insn, 13, 2) + 1) * 16; | |
7c51048f MM |
7537 | |
7538 | if (op2 != 0) { | |
7539 | unallocated_encoding(s); | |
7540 | return; | |
7541 | } | |
7542 | ||
8c6afa6a PM |
7543 | if (!fp_access_check(s)) { |
7544 | return; | |
7545 | } | |
7546 | ||
519183d3 RH |
7547 | tcg_gen_gvec_2_ptr(vec_full_reg_offset(s, rd), |
7548 | vec_full_reg_offset(s, rm), cpu_env, | |
7549 | is_q ? 16 : 8, vec_full_reg_size(s), | |
7550 | (len << 6) | (is_tbx << 5) | rn, | |
7551 | gen_helper_simd_tblx); | |
384b26fb AB |
7552 | } |
7553 | ||
4ce31af4 | 7554 | /* ZIP/UZP/TRN |
384b26fb AB |
7555 | * 31 30 29 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0 |
7556 | * +---+---+-------------+------+---+------+---+------------------+------+ | |
7557 | * | 0 | Q | 0 0 1 1 1 0 | size | 0 | Rm | 0 | opc | 1 0 | Rn | Rd | | |
7558 | * +---+---+-------------+------+---+------+---+------------------+------+ | |
7559 | */ | |
7560 | static void disas_simd_zip_trn(DisasContext *s, uint32_t insn) | |
7561 | { | |
5fa5469c MM |
7562 | int rd = extract32(insn, 0, 5); |
7563 | int rn = extract32(insn, 5, 5); | |
7564 | int rm = extract32(insn, 16, 5); | |
7565 | int size = extract32(insn, 22, 2); | |
7566 | /* opc field bits [1:0] indicate ZIP/UZP/TRN; | |
7567 | * bit 2 indicates 1 vs 2 variant of the insn. | |
7568 | */ | |
7569 | int opcode = extract32(insn, 12, 2); | |
7570 | bool part = extract32(insn, 14, 1); | |
7571 | bool is_q = extract32(insn, 30, 1); | |
7572 | int esize = 8 << size; | |
7573 | int i, ofs; | |
7574 | int datasize = is_q ? 128 : 64; | |
7575 | int elements = datasize / esize; | |
7576 | TCGv_i64 tcg_res, tcg_resl, tcg_resh; | |
7577 | ||
7578 | if (opcode == 0 || (size == 3 && !is_q)) { | |
7579 | unallocated_encoding(s); | |
7580 | return; | |
7581 | } | |
7582 | ||
8c6afa6a PM |
7583 | if (!fp_access_check(s)) { |
7584 | return; | |
7585 | } | |
7586 | ||
5fa5469c | 7587 | tcg_resl = tcg_const_i64(0); |
e1f77859 | 7588 | tcg_resh = is_q ? tcg_const_i64(0) : NULL; |
5fa5469c MM |
7589 | tcg_res = tcg_temp_new_i64(); |
7590 | ||
7591 | for (i = 0; i < elements; i++) { | |
7592 | switch (opcode) { | |
7593 | case 1: /* UZP1/2 */ | |
7594 | { | |
7595 | int midpoint = elements / 2; | |
7596 | if (i < midpoint) { | |
7597 | read_vec_element(s, tcg_res, rn, 2 * i + part, size); | |
7598 | } else { | |
7599 | read_vec_element(s, tcg_res, rm, | |
7600 | 2 * (i - midpoint) + part, size); | |
7601 | } | |
7602 | break; | |
7603 | } | |
7604 | case 2: /* TRN1/2 */ | |
7605 | if (i & 1) { | |
7606 | read_vec_element(s, tcg_res, rm, (i & ~1) + part, size); | |
7607 | } else { | |
7608 | read_vec_element(s, tcg_res, rn, (i & ~1) + part, size); | |
7609 | } | |
7610 | break; | |
7611 | case 3: /* ZIP1/2 */ | |
7612 | { | |
7613 | int base = part * elements / 2; | |
7614 | if (i & 1) { | |
7615 | read_vec_element(s, tcg_res, rm, base + (i >> 1), size); | |
7616 | } else { | |
7617 | read_vec_element(s, tcg_res, rn, base + (i >> 1), size); | |
7618 | } | |
7619 | break; | |
7620 | } | |
7621 | default: | |
7622 | g_assert_not_reached(); | |
7623 | } | |
7624 | ||
7625 | ofs = i * esize; | |
7626 | if (ofs < 64) { | |
7627 | tcg_gen_shli_i64(tcg_res, tcg_res, ofs); | |
7628 | tcg_gen_or_i64(tcg_resl, tcg_resl, tcg_res); | |
7629 | } else { | |
7630 | tcg_gen_shli_i64(tcg_res, tcg_res, ofs - 64); | |
7631 | tcg_gen_or_i64(tcg_resh, tcg_resh, tcg_res); | |
7632 | } | |
7633 | } | |
7634 | ||
7635 | tcg_temp_free_i64(tcg_res); | |
7636 | ||
7637 | write_vec_element(s, tcg_resl, rd, 0, MO_64); | |
7638 | tcg_temp_free_i64(tcg_resl); | |
e1f77859 RH |
7639 | |
7640 | if (is_q) { | |
7641 | write_vec_element(s, tcg_resh, rd, 1, MO_64); | |
7642 | tcg_temp_free_i64(tcg_resh); | |
7643 | } | |
7644 | clear_vec_high(s, is_q, rd); | |
384b26fb AB |
7645 | } |
7646 | ||
807cdd50 AB |
7647 | /* |
7648 | * do_reduction_op helper | |
7649 | * | |
7650 | * This mirrors the Reduce() pseudocode in the ARM ARM. It is | |
7651 | * important for correct NaN propagation that we do these | |
7652 | * operations in exactly the order specified by the pseudocode. | |
7653 | * | |
7654 | * This is a recursive function, TCG temps should be freed by the | |
7655 | * calling function once it is done with the values. | |
7656 | */ | |
7657 | static TCGv_i32 do_reduction_op(DisasContext *s, int fpopcode, int rn, | |
7658 | int esize, int size, int vmap, TCGv_ptr fpst) | |
7659 | { | |
7660 | if (esize == size) { | |
7661 | int element; | |
14776ab5 | 7662 | MemOp msize = esize == 16 ? MO_16 : MO_32; |
807cdd50 AB |
7663 | TCGv_i32 tcg_elem; |
7664 | ||
7665 | /* We should have one register left here */ | |
7666 | assert(ctpop8(vmap) == 1); | |
7667 | element = ctz32(vmap); | |
7668 | assert(element < 8); | |
7669 | ||
7670 | tcg_elem = tcg_temp_new_i32(); | |
7671 | read_vec_element_i32(s, tcg_elem, rn, element, msize); | |
7672 | return tcg_elem; | |
4a0ff1ce | 7673 | } else { |
807cdd50 AB |
7674 | int bits = size / 2; |
7675 | int shift = ctpop8(vmap) / 2; | |
7676 | int vmap_lo = (vmap >> shift) & vmap; | |
7677 | int vmap_hi = (vmap & ~vmap_lo); | |
7678 | TCGv_i32 tcg_hi, tcg_lo, tcg_res; | |
7679 | ||
7680 | tcg_hi = do_reduction_op(s, fpopcode, rn, esize, bits, vmap_hi, fpst); | |
7681 | tcg_lo = do_reduction_op(s, fpopcode, rn, esize, bits, vmap_lo, fpst); | |
7682 | tcg_res = tcg_temp_new_i32(); | |
7683 | ||
7684 | switch (fpopcode) { | |
7685 | case 0x0c: /* fmaxnmv half-precision */ | |
7686 | gen_helper_advsimd_maxnumh(tcg_res, tcg_lo, tcg_hi, fpst); | |
7687 | break; | |
7688 | case 0x0f: /* fmaxv half-precision */ | |
7689 | gen_helper_advsimd_maxh(tcg_res, tcg_lo, tcg_hi, fpst); | |
7690 | break; | |
7691 | case 0x1c: /* fminnmv half-precision */ | |
7692 | gen_helper_advsimd_minnumh(tcg_res, tcg_lo, tcg_hi, fpst); | |
7693 | break; | |
7694 | case 0x1f: /* fminv half-precision */ | |
7695 | gen_helper_advsimd_minh(tcg_res, tcg_lo, tcg_hi, fpst); | |
7696 | break; | |
7697 | case 0x2c: /* fmaxnmv */ | |
7698 | gen_helper_vfp_maxnums(tcg_res, tcg_lo, tcg_hi, fpst); | |
7699 | break; | |
7700 | case 0x2f: /* fmaxv */ | |
7701 | gen_helper_vfp_maxs(tcg_res, tcg_lo, tcg_hi, fpst); | |
7702 | break; | |
7703 | case 0x3c: /* fminnmv */ | |
7704 | gen_helper_vfp_minnums(tcg_res, tcg_lo, tcg_hi, fpst); | |
7705 | break; | |
7706 | case 0x3f: /* fminv */ | |
7707 | gen_helper_vfp_mins(tcg_res, tcg_lo, tcg_hi, fpst); | |
7708 | break; | |
7709 | default: | |
7710 | g_assert_not_reached(); | |
4a0ff1ce | 7711 | } |
807cdd50 AB |
7712 | |
7713 | tcg_temp_free_i32(tcg_hi); | |
7714 | tcg_temp_free_i32(tcg_lo); | |
7715 | return tcg_res; | |
4a0ff1ce MM |
7716 | } |
7717 | } | |
7718 | ||
4ce31af4 | 7719 | /* AdvSIMD across lanes |
384b26fb AB |
7720 | * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0 |
7721 | * +---+---+---+-----------+------+-----------+--------+-----+------+------+ | |
7722 | * | 0 | Q | U | 0 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd | | |
7723 | * +---+---+---+-----------+------+-----------+--------+-----+------+------+ | |
7724 | */ | |
7725 | static void disas_simd_across_lanes(DisasContext *s, uint32_t insn) | |
7726 | { | |
4a0ff1ce MM |
7727 | int rd = extract32(insn, 0, 5); |
7728 | int rn = extract32(insn, 5, 5); | |
7729 | int size = extract32(insn, 22, 2); | |
7730 | int opcode = extract32(insn, 12, 5); | |
7731 | bool is_q = extract32(insn, 30, 1); | |
7732 | bool is_u = extract32(insn, 29, 1); | |
7733 | bool is_fp = false; | |
7734 | bool is_min = false; | |
7735 | int esize; | |
7736 | int elements; | |
7737 | int i; | |
7738 | TCGv_i64 tcg_res, tcg_elt; | |
7739 | ||
7740 | switch (opcode) { | |
7741 | case 0x1b: /* ADDV */ | |
7742 | if (is_u) { | |
7743 | unallocated_encoding(s); | |
7744 | return; | |
7745 | } | |
7746 | /* fall through */ | |
7747 | case 0x3: /* SADDLV, UADDLV */ | |
7748 | case 0xa: /* SMAXV, UMAXV */ | |
7749 | case 0x1a: /* SMINV, UMINV */ | |
7750 | if (size == 3 || (size == 2 && !is_q)) { | |
7751 | unallocated_encoding(s); | |
7752 | return; | |
7753 | } | |
7754 | break; | |
7755 | case 0xc: /* FMAXNMV, FMINNMV */ | |
7756 | case 0xf: /* FMAXV, FMINV */ | |
807cdd50 AB |
7757 | /* Bit 1 of size field encodes min vs max and the actual size |
7758 | * depends on the encoding of the U bit. If not set (and FP16 | |
7759 | * enabled) then we do half-precision float instead of single | |
7760 | * precision. | |
4a0ff1ce MM |
7761 | */ |
7762 | is_min = extract32(size, 1, 1); | |
7763 | is_fp = true; | |
5763190f | 7764 | if (!is_u && dc_isar_feature(aa64_fp16, s)) { |
807cdd50 AB |
7765 | size = 1; |
7766 | } else if (!is_u || !is_q || extract32(size, 0, 1)) { | |
7767 | unallocated_encoding(s); | |
7768 | return; | |
7769 | } else { | |
7770 | size = 2; | |
7771 | } | |
4a0ff1ce MM |
7772 | break; |
7773 | default: | |
7774 | unallocated_encoding(s); | |
7775 | return; | |
7776 | } | |
7777 | ||
8c6afa6a PM |
7778 | if (!fp_access_check(s)) { |
7779 | return; | |
7780 | } | |
7781 | ||
4a0ff1ce MM |
7782 | esize = 8 << size; |
7783 | elements = (is_q ? 128 : 64) / esize; | |
7784 | ||
7785 | tcg_res = tcg_temp_new_i64(); | |
7786 | tcg_elt = tcg_temp_new_i64(); | |
7787 | ||
7788 | /* These instructions operate across all lanes of a vector | |
7789 | * to produce a single result. We can guarantee that a 64 | |
7790 | * bit intermediate is sufficient: | |
7791 | * + for [US]ADDLV the maximum element size is 32 bits, and | |
7792 | * the result type is 64 bits | |
7793 | * + for FMAX*V, FMIN*V, ADDV the intermediate type is the | |
7794 | * same as the element size, which is 32 bits at most | |
7795 | * For the integer operations we can choose to work at 64 | |
7796 | * or 32 bits and truncate at the end; for simplicity | |
7797 | * we use 64 bits always. The floating point | |
7798 | * ops do require 32 bit intermediates, though. | |
7799 | */ | |
7800 | if (!is_fp) { | |
7801 | read_vec_element(s, tcg_res, rn, 0, size | (is_u ? 0 : MO_SIGN)); | |
7802 | ||
7803 | for (i = 1; i < elements; i++) { | |
7804 | read_vec_element(s, tcg_elt, rn, i, size | (is_u ? 0 : MO_SIGN)); | |
7805 | ||
7806 | switch (opcode) { | |
7807 | case 0x03: /* SADDLV / UADDLV */ | |
7808 | case 0x1b: /* ADDV */ | |
7809 | tcg_gen_add_i64(tcg_res, tcg_res, tcg_elt); | |
7810 | break; | |
7811 | case 0x0a: /* SMAXV / UMAXV */ | |
ecb8ab8d RH |
7812 | if (is_u) { |
7813 | tcg_gen_umax_i64(tcg_res, tcg_res, tcg_elt); | |
7814 | } else { | |
7815 | tcg_gen_smax_i64(tcg_res, tcg_res, tcg_elt); | |
7816 | } | |
4a0ff1ce MM |
7817 | break; |
7818 | case 0x1a: /* SMINV / UMINV */ | |
ecb8ab8d RH |
7819 | if (is_u) { |
7820 | tcg_gen_umin_i64(tcg_res, tcg_res, tcg_elt); | |
7821 | } else { | |
7822 | tcg_gen_smin_i64(tcg_res, tcg_res, tcg_elt); | |
7823 | } | |
4a0ff1ce MM |
7824 | break; |
7825 | default: | |
7826 | g_assert_not_reached(); | |
7827 | } | |
7828 | ||
7829 | } | |
7830 | } else { | |
807cdd50 AB |
7831 | /* Floating point vector reduction ops which work across 32 |
7832 | * bit (single) or 16 bit (half-precision) intermediates. | |
4a0ff1ce MM |
7833 | * Note that correct NaN propagation requires that we do these |
7834 | * operations in exactly the order specified by the pseudocode. | |
7835 | */ | |
cdfb22bb | 7836 | TCGv_ptr fpst = fpstatus_ptr(size == MO_16 ? FPST_FPCR_F16 : FPST_FPCR); |
807cdd50 AB |
7837 | int fpopcode = opcode | is_min << 4 | is_u << 5; |
7838 | int vmap = (1 << elements) - 1; | |
7839 | TCGv_i32 tcg_res32 = do_reduction_op(s, fpopcode, rn, esize, | |
7840 | (is_q ? 128 : 64), vmap, fpst); | |
7841 | tcg_gen_extu_i32_i64(tcg_res, tcg_res32); | |
7842 | tcg_temp_free_i32(tcg_res32); | |
4a0ff1ce MM |
7843 | tcg_temp_free_ptr(fpst); |
7844 | } | |
7845 | ||
7846 | tcg_temp_free_i64(tcg_elt); | |
7847 | ||
7848 | /* Now truncate the result to the width required for the final output */ | |
7849 | if (opcode == 0x03) { | |
7850 | /* SADDLV, UADDLV: result is 2*esize */ | |
7851 | size++; | |
7852 | } | |
7853 | ||
7854 | switch (size) { | |
7855 | case 0: | |
7856 | tcg_gen_ext8u_i64(tcg_res, tcg_res); | |
7857 | break; | |
7858 | case 1: | |
7859 | tcg_gen_ext16u_i64(tcg_res, tcg_res); | |
7860 | break; | |
7861 | case 2: | |
7862 | tcg_gen_ext32u_i64(tcg_res, tcg_res); | |
7863 | break; | |
7864 | case 3: | |
7865 | break; | |
7866 | default: | |
7867 | g_assert_not_reached(); | |
7868 | } | |
7869 | ||
7870 | write_fp_dreg(s, rd, tcg_res); | |
7871 | tcg_temp_free_i64(tcg_res); | |
384b26fb AB |
7872 | } |
7873 | ||
4ce31af4 | 7874 | /* DUP (Element, Vector) |
67bb9389 AB |
7875 | * |
7876 | * 31 30 29 21 20 16 15 10 9 5 4 0 | |
7877 | * +---+---+-------------------+--------+-------------+------+------+ | |
7878 | * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd | | |
7879 | * +---+---+-------------------+--------+-------------+------+------+ | |
7880 | * | |
7881 | * size: encoded in imm5 (see ARM ARM LowestSetBit()) | |
7882 | */ | |
7883 | static void handle_simd_dupe(DisasContext *s, int is_q, int rd, int rn, | |
7884 | int imm5) | |
7885 | { | |
7886 | int size = ctz32(imm5); | |
550a0489 | 7887 | int index; |
67bb9389 AB |
7888 | |
7889 | if (size > 3 || (size == 3 && !is_q)) { | |
7890 | unallocated_encoding(s); | |
7891 | return; | |
7892 | } | |
7893 | ||
8c6afa6a PM |
7894 | if (!fp_access_check(s)) { |
7895 | return; | |
7896 | } | |
7897 | ||
550a0489 | 7898 | index = imm5 >> (size + 1); |
861a1ded RH |
7899 | tcg_gen_gvec_dup_mem(size, vec_full_reg_offset(s, rd), |
7900 | vec_reg_offset(s, rn, index, size), | |
7901 | is_q ? 16 : 8, vec_full_reg_size(s)); | |
67bb9389 AB |
7902 | } |
7903 | ||
4ce31af4 | 7904 | /* DUP (element, scalar) |
360a6f2d PM |
7905 | * 31 21 20 16 15 10 9 5 4 0 |
7906 | * +-----------------------+--------+-------------+------+------+ | |
7907 | * | 0 1 0 1 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd | | |
7908 | * +-----------------------+--------+-------------+------+------+ | |
7909 | */ | |
7910 | static void handle_simd_dupes(DisasContext *s, int rd, int rn, | |
7911 | int imm5) | |
7912 | { | |
7913 | int size = ctz32(imm5); | |
7914 | int index; | |
7915 | TCGv_i64 tmp; | |
7916 | ||
7917 | if (size > 3) { | |
7918 | unallocated_encoding(s); | |
7919 | return; | |
7920 | } | |
7921 | ||
8c6afa6a PM |
7922 | if (!fp_access_check(s)) { |
7923 | return; | |
7924 | } | |
7925 | ||
360a6f2d PM |
7926 | index = imm5 >> (size + 1); |
7927 | ||
7928 | /* This instruction just extracts the specified element and | |
7929 | * zero-extends it into the bottom of the destination register. | |
7930 | */ | |
7931 | tmp = tcg_temp_new_i64(); | |
7932 | read_vec_element(s, tmp, rn, index, size); | |
7933 | write_fp_dreg(s, rd, tmp); | |
7934 | tcg_temp_free_i64(tmp); | |
7935 | } | |
7936 | ||
4ce31af4 | 7937 | /* DUP (General) |
67bb9389 AB |
7938 | * |
7939 | * 31 30 29 21 20 16 15 10 9 5 4 0 | |
7940 | * +---+---+-------------------+--------+-------------+------+------+ | |
7941 | * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 1 1 | Rn | Rd | | |
7942 | * +---+---+-------------------+--------+-------------+------+------+ | |
7943 | * | |
7944 | * size: encoded in imm5 (see ARM ARM LowestSetBit()) | |
7945 | */ | |
7946 | static void handle_simd_dupg(DisasContext *s, int is_q, int rd, int rn, | |
7947 | int imm5) | |
7948 | { | |
7949 | int size = ctz32(imm5); | |
861a1ded | 7950 | uint32_t dofs, oprsz, maxsz; |
67bb9389 AB |
7951 | |
7952 | if (size > 3 || ((size == 3) && !is_q)) { | |
7953 | unallocated_encoding(s); | |
7954 | return; | |
7955 | } | |
8c6afa6a PM |
7956 | |
7957 | if (!fp_access_check(s)) { | |
7958 | return; | |
7959 | } | |
7960 | ||
861a1ded RH |
7961 | dofs = vec_full_reg_offset(s, rd); |
7962 | oprsz = is_q ? 16 : 8; | |
7963 | maxsz = vec_full_reg_size(s); | |
7964 | ||
7965 | tcg_gen_gvec_dup_i64(size, dofs, oprsz, maxsz, cpu_reg(s, rn)); | |
67bb9389 AB |
7966 | } |
7967 | ||
4ce31af4 | 7968 | /* INS (Element) |
67bb9389 AB |
7969 | * |
7970 | * 31 21 20 16 15 14 11 10 9 5 4 0 | |
7971 | * +-----------------------+--------+------------+---+------+------+ | |
7972 | * | 0 1 1 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd | | |
7973 | * +-----------------------+--------+------------+---+------+------+ | |
7974 | * | |
7975 | * size: encoded in imm5 (see ARM ARM LowestSetBit()) | |
7976 | * index: encoded in imm5<4:size+1> | |
7977 | */ | |
7978 | static void handle_simd_inse(DisasContext *s, int rd, int rn, | |
7979 | int imm4, int imm5) | |
7980 | { | |
7981 | int size = ctz32(imm5); | |
7982 | int src_index, dst_index; | |
7983 | TCGv_i64 tmp; | |
7984 | ||
7985 | if (size > 3) { | |
7986 | unallocated_encoding(s); | |
7987 | return; | |
7988 | } | |
8c6afa6a PM |
7989 | |
7990 | if (!fp_access_check(s)) { | |
7991 | return; | |
7992 | } | |
7993 | ||
67bb9389 AB |
7994 | dst_index = extract32(imm5, 1+size, 5); |
7995 | src_index = extract32(imm4, size, 4); | |
7996 | ||
7997 | tmp = tcg_temp_new_i64(); | |
7998 | ||
7999 | read_vec_element(s, tmp, rn, src_index, size); | |
8000 | write_vec_element(s, tmp, rd, dst_index, size); | |
8001 | ||
8002 | tcg_temp_free_i64(tmp); | |
528dc354 RH |
8003 | |
8004 | /* INS is considered a 128-bit write for SVE. */ | |
8005 | clear_vec_high(s, true, rd); | |
67bb9389 AB |
8006 | } |
8007 | ||
8008 | ||
4ce31af4 | 8009 | /* INS (General) |
67bb9389 AB |
8010 | * |
8011 | * 31 21 20 16 15 10 9 5 4 0 | |
8012 | * +-----------------------+--------+-------------+------+------+ | |
8013 | * | 0 1 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 1 1 1 | Rn | Rd | | |
8014 | * +-----------------------+--------+-------------+------+------+ | |
8015 | * | |
8016 | * size: encoded in imm5 (see ARM ARM LowestSetBit()) | |
8017 | * index: encoded in imm5<4:size+1> | |
8018 | */ | |
8019 | static void handle_simd_insg(DisasContext *s, int rd, int rn, int imm5) | |
8020 | { | |
8021 | int size = ctz32(imm5); | |
8022 | int idx; | |
8023 | ||
8024 | if (size > 3) { | |
8025 | unallocated_encoding(s); | |
8026 | return; | |
8027 | } | |
8028 | ||
8c6afa6a PM |
8029 | if (!fp_access_check(s)) { |
8030 | return; | |
8031 | } | |
8032 | ||
67bb9389 AB |
8033 | idx = extract32(imm5, 1 + size, 4 - size); |
8034 | write_vec_element(s, cpu_reg(s, rn), rd, idx, size); | |
528dc354 RH |
8035 | |
8036 | /* INS is considered a 128-bit write for SVE. */ | |
8037 | clear_vec_high(s, true, rd); | |
67bb9389 AB |
8038 | } |
8039 | ||
8040 | /* | |
4ce31af4 PM |
8041 | * UMOV (General) |
8042 | * SMOV (General) | |
67bb9389 AB |
8043 | * |
8044 | * 31 30 29 21 20 16 15 12 10 9 5 4 0 | |
8045 | * +---+---+-------------------+--------+-------------+------+------+ | |
8046 | * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 1 U 1 1 | Rn | Rd | | |
8047 | * +---+---+-------------------+--------+-------------+------+------+ | |
8048 | * | |
8049 | * U: unsigned when set | |
8050 | * size: encoded in imm5 (see ARM ARM LowestSetBit()) | |
8051 | */ | |
8052 | static void handle_simd_umov_smov(DisasContext *s, int is_q, int is_signed, | |
8053 | int rn, int rd, int imm5) | |
8054 | { | |
8055 | int size = ctz32(imm5); | |
8056 | int element; | |
8057 | TCGv_i64 tcg_rd; | |
8058 | ||
8059 | /* Check for UnallocatedEncodings */ | |
8060 | if (is_signed) { | |
8061 | if (size > 2 || (size == 2 && !is_q)) { | |
8062 | unallocated_encoding(s); | |
8063 | return; | |
8064 | } | |
8065 | } else { | |
8066 | if (size > 3 | |
8067 | || (size < 3 && is_q) | |
8068 | || (size == 3 && !is_q)) { | |
8069 | unallocated_encoding(s); | |
8070 | return; | |
8071 | } | |
8072 | } | |
8c6afa6a PM |
8073 | |
8074 | if (!fp_access_check(s)) { | |
8075 | return; | |
8076 | } | |
8077 | ||
67bb9389 AB |
8078 | element = extract32(imm5, 1+size, 4); |
8079 | ||
8080 | tcg_rd = cpu_reg(s, rd); | |
8081 | read_vec_element(s, tcg_rd, rn, element, size | (is_signed ? MO_SIGN : 0)); | |
8082 | if (is_signed && !is_q) { | |
8083 | tcg_gen_ext32u_i64(tcg_rd, tcg_rd); | |
8084 | } | |
8085 | } | |
8086 | ||
4ce31af4 | 8087 | /* AdvSIMD copy |
384b26fb AB |
8088 | * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0 |
8089 | * +---+---+----+-----------------+------+---+------+---+------+------+ | |
8090 | * | 0 | Q | op | 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd | | |
8091 | * +---+---+----+-----------------+------+---+------+---+------+------+ | |
8092 | */ | |
8093 | static void disas_simd_copy(DisasContext *s, uint32_t insn) | |
8094 | { | |
67bb9389 AB |
8095 | int rd = extract32(insn, 0, 5); |
8096 | int rn = extract32(insn, 5, 5); | |
8097 | int imm4 = extract32(insn, 11, 4); | |
8098 | int op = extract32(insn, 29, 1); | |
8099 | int is_q = extract32(insn, 30, 1); | |
8100 | int imm5 = extract32(insn, 16, 5); | |
8101 | ||
8102 | if (op) { | |
8103 | if (is_q) { | |
8104 | /* INS (element) */ | |
8105 | handle_simd_inse(s, rd, rn, imm4, imm5); | |
8106 | } else { | |
8107 | unallocated_encoding(s); | |
8108 | } | |
8109 | } else { | |
8110 | switch (imm4) { | |
8111 | case 0: | |
8112 | /* DUP (element - vector) */ | |
8113 | handle_simd_dupe(s, is_q, rd, rn, imm5); | |
8114 | break; | |
8115 | case 1: | |
8116 | /* DUP (general) */ | |
8117 | handle_simd_dupg(s, is_q, rd, rn, imm5); | |
8118 | break; | |
8119 | case 3: | |
8120 | if (is_q) { | |
8121 | /* INS (general) */ | |
8122 | handle_simd_insg(s, rd, rn, imm5); | |
8123 | } else { | |
8124 | unallocated_encoding(s); | |
8125 | } | |
8126 | break; | |
8127 | case 5: | |
8128 | case 7: | |
8129 | /* UMOV/SMOV (is_q indicates 32/64; imm4 indicates signedness) */ | |
8130 | handle_simd_umov_smov(s, is_q, (imm4 == 5), rn, rd, imm5); | |
8131 | break; | |
8132 | default: | |
8133 | unallocated_encoding(s); | |
8134 | break; | |
8135 | } | |
8136 | } | |
384b26fb AB |
8137 | } |
8138 | ||
4ce31af4 | 8139 | /* AdvSIMD modified immediate |
384b26fb AB |
8140 | * 31 30 29 28 19 18 16 15 12 11 10 9 5 4 0 |
8141 | * +---+---+----+---------------------+-----+-------+----+---+-------+------+ | |
8142 | * | 0 | Q | op | 0 1 1 1 1 0 0 0 0 0 | abc | cmode | o2 | 1 | defgh | Rd | | |
8143 | * +---+---+----+---------------------+-----+-------+----+---+-------+------+ | |
f3f8c4f4 AB |
8144 | * |
8145 | * There are a number of operations that can be carried out here: | |
8146 | * MOVI - move (shifted) imm into register | |
8147 | * MVNI - move inverted (shifted) imm into register | |
8148 | * ORR - bitwise OR of (shifted) imm with register | |
8149 | * BIC - bitwise clear of (shifted) imm with register | |
70b4e6a4 AB |
8150 | * With ARMv8.2 we also have: |
8151 | * FMOV half-precision | |
384b26fb AB |
8152 | */ |
8153 | static void disas_simd_mod_imm(DisasContext *s, uint32_t insn) | |
8154 | { | |
f3f8c4f4 AB |
8155 | int rd = extract32(insn, 0, 5); |
8156 | int cmode = extract32(insn, 12, 4); | |
8157 | int cmode_3_1 = extract32(cmode, 1, 3); | |
8158 | int cmode_0 = extract32(cmode, 0, 1); | |
8159 | int o2 = extract32(insn, 11, 1); | |
8160 | uint64_t abcdefgh = extract32(insn, 5, 5) | (extract32(insn, 16, 3) << 5); | |
8161 | bool is_neg = extract32(insn, 29, 1); | |
8162 | bool is_q = extract32(insn, 30, 1); | |
8163 | uint64_t imm = 0; | |
f3f8c4f4 AB |
8164 | |
8165 | if (o2 != 0 || ((cmode == 0xf) && is_neg && !is_q)) { | |
70b4e6a4 | 8166 | /* Check for FMOV (vector, immediate) - half-precision */ |
5763190f | 8167 | if (!(dc_isar_feature(aa64_fp16, s) && o2 && cmode == 0xf)) { |
70b4e6a4 AB |
8168 | unallocated_encoding(s); |
8169 | return; | |
8170 | } | |
f3f8c4f4 AB |
8171 | } |
8172 | ||
8c6afa6a PM |
8173 | if (!fp_access_check(s)) { |
8174 | return; | |
8175 | } | |
8176 | ||
f3f8c4f4 AB |
8177 | /* See AdvSIMDExpandImm() in ARM ARM */ |
8178 | switch (cmode_3_1) { | |
8179 | case 0: /* Replicate(Zeros(24):imm8, 2) */ | |
8180 | case 1: /* Replicate(Zeros(16):imm8:Zeros(8), 2) */ | |
8181 | case 2: /* Replicate(Zeros(8):imm8:Zeros(16), 2) */ | |
8182 | case 3: /* Replicate(imm8:Zeros(24), 2) */ | |
8183 | { | |
8184 | int shift = cmode_3_1 * 8; | |
8185 | imm = bitfield_replicate(abcdefgh << shift, 32); | |
8186 | break; | |
8187 | } | |
8188 | case 4: /* Replicate(Zeros(8):imm8, 4) */ | |
8189 | case 5: /* Replicate(imm8:Zeros(8), 4) */ | |
8190 | { | |
8191 | int shift = (cmode_3_1 & 0x1) * 8; | |
8192 | imm = bitfield_replicate(abcdefgh << shift, 16); | |
8193 | break; | |
8194 | } | |
8195 | case 6: | |
8196 | if (cmode_0) { | |
8197 | /* Replicate(Zeros(8):imm8:Ones(16), 2) */ | |
8198 | imm = (abcdefgh << 16) | 0xffff; | |
8199 | } else { | |
8200 | /* Replicate(Zeros(16):imm8:Ones(8), 2) */ | |
8201 | imm = (abcdefgh << 8) | 0xff; | |
8202 | } | |
8203 | imm = bitfield_replicate(imm, 32); | |
8204 | break; | |
8205 | case 7: | |
8206 | if (!cmode_0 && !is_neg) { | |
8207 | imm = bitfield_replicate(abcdefgh, 8); | |
8208 | } else if (!cmode_0 && is_neg) { | |
8209 | int i; | |
8210 | imm = 0; | |
8211 | for (i = 0; i < 8; i++) { | |
8212 | if ((abcdefgh) & (1 << i)) { | |
8213 | imm |= 0xffULL << (i * 8); | |
8214 | } | |
8215 | } | |
8216 | } else if (cmode_0) { | |
8217 | if (is_neg) { | |
8218 | imm = (abcdefgh & 0x3f) << 48; | |
8219 | if (abcdefgh & 0x80) { | |
8220 | imm |= 0x8000000000000000ULL; | |
8221 | } | |
8222 | if (abcdefgh & 0x40) { | |
8223 | imm |= 0x3fc0000000000000ULL; | |
8224 | } else { | |
8225 | imm |= 0x4000000000000000ULL; | |
8226 | } | |
8227 | } else { | |
70b4e6a4 AB |
8228 | if (o2) { |
8229 | /* FMOV (vector, immediate) - half-precision */ | |
8230 | imm = vfp_expand_imm(MO_16, abcdefgh); | |
8231 | /* now duplicate across the lanes */ | |
8232 | imm = bitfield_replicate(imm, 16); | |
f3f8c4f4 | 8233 | } else { |
70b4e6a4 AB |
8234 | imm = (abcdefgh & 0x3f) << 19; |
8235 | if (abcdefgh & 0x80) { | |
8236 | imm |= 0x80000000; | |
8237 | } | |
8238 | if (abcdefgh & 0x40) { | |
8239 | imm |= 0x3e000000; | |
8240 | } else { | |
8241 | imm |= 0x40000000; | |
8242 | } | |
8243 | imm |= (imm << 32); | |
f3f8c4f4 | 8244 | } |
f3f8c4f4 AB |
8245 | } |
8246 | } | |
8247 | break; | |
70b4e6a4 AB |
8248 | default: |
8249 | fprintf(stderr, "%s: cmode_3_1: %x\n", __func__, cmode_3_1); | |
8250 | g_assert_not_reached(); | |
f3f8c4f4 AB |
8251 | } |
8252 | ||
8253 | if (cmode_3_1 != 7 && is_neg) { | |
8254 | imm = ~imm; | |
8255 | } | |
8256 | ||
861a1ded RH |
8257 | if (!((cmode & 0x9) == 0x1 || (cmode & 0xd) == 0x9)) { |
8258 | /* MOVI or MVNI, with MVNI negation handled above. */ | |
8711e71f RH |
8259 | tcg_gen_gvec_dup_imm(MO_64, vec_full_reg_offset(s, rd), is_q ? 16 : 8, |
8260 | vec_full_reg_size(s), imm); | |
861a1ded | 8261 | } else { |
064e265d RH |
8262 | /* ORR or BIC, with BIC negation to AND handled above. */ |
8263 | if (is_neg) { | |
8264 | gen_gvec_fn2i(s, is_q, rd, rd, imm, tcg_gen_gvec_andi, MO_64); | |
8265 | } else { | |
8266 | gen_gvec_fn2i(s, is_q, rd, rd, imm, tcg_gen_gvec_ori, MO_64); | |
f3f8c4f4 | 8267 | } |
861a1ded | 8268 | } |
384b26fb AB |
8269 | } |
8270 | ||
4ce31af4 | 8271 | /* AdvSIMD scalar copy |
384b26fb AB |
8272 | * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0 |
8273 | * +-----+----+-----------------+------+---+------+---+------+------+ | |
8274 | * | 0 1 | op | 1 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd | | |
8275 | * +-----+----+-----------------+------+---+------+---+------+------+ | |
8276 | */ | |
8277 | static void disas_simd_scalar_copy(DisasContext *s, uint32_t insn) | |
8278 | { | |
360a6f2d PM |
8279 | int rd = extract32(insn, 0, 5); |
8280 | int rn = extract32(insn, 5, 5); | |
8281 | int imm4 = extract32(insn, 11, 4); | |
8282 | int imm5 = extract32(insn, 16, 5); | |
8283 | int op = extract32(insn, 29, 1); | |
8284 | ||
8285 | if (op != 0 || imm4 != 0) { | |
8286 | unallocated_encoding(s); | |
8287 | return; | |
8288 | } | |
8289 | ||
8290 | /* DUP (element, scalar) */ | |
8291 | handle_simd_dupes(s, rd, rn, imm5); | |
384b26fb AB |
8292 | } |
8293 | ||
4ce31af4 | 8294 | /* AdvSIMD scalar pairwise |
384b26fb AB |
8295 | * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0 |
8296 | * +-----+---+-----------+------+-----------+--------+-----+------+------+ | |
8297 | * | 0 1 | U | 1 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd | | |
8298 | * +-----+---+-----------+------+-----------+--------+-----+------+------+ | |
8299 | */ | |
8300 | static void disas_simd_scalar_pairwise(DisasContext *s, uint32_t insn) | |
8301 | { | |
3720a7ea PM |
8302 | int u = extract32(insn, 29, 1); |
8303 | int size = extract32(insn, 22, 2); | |
8304 | int opcode = extract32(insn, 12, 5); | |
8305 | int rn = extract32(insn, 5, 5); | |
8306 | int rd = extract32(insn, 0, 5); | |
8307 | TCGv_ptr fpst; | |
8308 | ||
8309 | /* For some ops (the FP ones), size[1] is part of the encoding. | |
8310 | * For ADDP strictly it is not but size[1] is always 1 for valid | |
8311 | * encodings. | |
8312 | */ | |
8313 | opcode |= (extract32(size, 1, 1) << 5); | |
8314 | ||
8315 | switch (opcode) { | |
8316 | case 0x3b: /* ADDP */ | |
8317 | if (u || size != 3) { | |
8318 | unallocated_encoding(s); | |
8319 | return; | |
8320 | } | |
8c6afa6a PM |
8321 | if (!fp_access_check(s)) { |
8322 | return; | |
8323 | } | |
8324 | ||
f764718d | 8325 | fpst = NULL; |
3720a7ea PM |
8326 | break; |
8327 | case 0xc: /* FMAXNMP */ | |
8328 | case 0xd: /* FADDP */ | |
8329 | case 0xf: /* FMAXP */ | |
8330 | case 0x2c: /* FMINNMP */ | |
8331 | case 0x2f: /* FMINP */ | |
5c36d895 | 8332 | /* FP op, size[0] is 32 or 64 bit*/ |
3720a7ea | 8333 | if (!u) { |
5763190f | 8334 | if (!dc_isar_feature(aa64_fp16, s)) { |
5c36d895 AB |
8335 | unallocated_encoding(s); |
8336 | return; | |
8337 | } else { | |
8338 | size = MO_16; | |
8339 | } | |
8340 | } else { | |
8341 | size = extract32(size, 0, 1) ? MO_64 : MO_32; | |
3720a7ea | 8342 | } |
5c36d895 | 8343 | |
8c6afa6a PM |
8344 | if (!fp_access_check(s)) { |
8345 | return; | |
8346 | } | |
8347 | ||
cdfb22bb | 8348 | fpst = fpstatus_ptr(size == MO_16 ? FPST_FPCR_F16 : FPST_FPCR); |
3720a7ea PM |
8349 | break; |
8350 | default: | |
8351 | unallocated_encoding(s); | |
8352 | return; | |
8353 | } | |
8354 | ||
5c36d895 | 8355 | if (size == MO_64) { |
3720a7ea PM |
8356 | TCGv_i64 tcg_op1 = tcg_temp_new_i64(); |
8357 | TCGv_i64 tcg_op2 = tcg_temp_new_i64(); | |
8358 | TCGv_i64 tcg_res = tcg_temp_new_i64(); | |
8359 | ||
8360 | read_vec_element(s, tcg_op1, rn, 0, MO_64); | |
8361 | read_vec_element(s, tcg_op2, rn, 1, MO_64); | |
8362 | ||
8363 | switch (opcode) { | |
8364 | case 0x3b: /* ADDP */ | |
8365 | tcg_gen_add_i64(tcg_res, tcg_op1, tcg_op2); | |
8366 | break; | |
8367 | case 0xc: /* FMAXNMP */ | |
8368 | gen_helper_vfp_maxnumd(tcg_res, tcg_op1, tcg_op2, fpst); | |
8369 | break; | |
8370 | case 0xd: /* FADDP */ | |
8371 | gen_helper_vfp_addd(tcg_res, tcg_op1, tcg_op2, fpst); | |
8372 | break; | |
8373 | case 0xf: /* FMAXP */ | |
8374 | gen_helper_vfp_maxd(tcg_res, tcg_op1, tcg_op2, fpst); | |
8375 | break; | |
8376 | case 0x2c: /* FMINNMP */ | |
8377 | gen_helper_vfp_minnumd(tcg_res, tcg_op1, tcg_op2, fpst); | |
8378 | break; | |
8379 | case 0x2f: /* FMINP */ | |
8380 | gen_helper_vfp_mind(tcg_res, tcg_op1, tcg_op2, fpst); | |
8381 | break; | |
8382 | default: | |
8383 | g_assert_not_reached(); | |
8384 | } | |
8385 | ||
8386 | write_fp_dreg(s, rd, tcg_res); | |
8387 | ||
8388 | tcg_temp_free_i64(tcg_op1); | |
8389 | tcg_temp_free_i64(tcg_op2); | |
8390 | tcg_temp_free_i64(tcg_res); | |
8391 | } else { | |
8392 | TCGv_i32 tcg_op1 = tcg_temp_new_i32(); | |
8393 | TCGv_i32 tcg_op2 = tcg_temp_new_i32(); | |
8394 | TCGv_i32 tcg_res = tcg_temp_new_i32(); | |
8395 | ||
5c36d895 AB |
8396 | read_vec_element_i32(s, tcg_op1, rn, 0, size); |
8397 | read_vec_element_i32(s, tcg_op2, rn, 1, size); | |
3720a7ea | 8398 | |
5c36d895 AB |
8399 | if (size == MO_16) { |
8400 | switch (opcode) { | |
8401 | case 0xc: /* FMAXNMP */ | |
8402 | gen_helper_advsimd_maxnumh(tcg_res, tcg_op1, tcg_op2, fpst); | |
8403 | break; | |
8404 | case 0xd: /* FADDP */ | |
8405 | gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst); | |
8406 | break; | |
8407 | case 0xf: /* FMAXP */ | |
8408 | gen_helper_advsimd_maxh(tcg_res, tcg_op1, tcg_op2, fpst); | |
8409 | break; | |
8410 | case 0x2c: /* FMINNMP */ | |
8411 | gen_helper_advsimd_minnumh(tcg_res, tcg_op1, tcg_op2, fpst); | |
8412 | break; | |
8413 | case 0x2f: /* FMINP */ | |
8414 | gen_helper_advsimd_minh(tcg_res, tcg_op1, tcg_op2, fpst); | |
8415 | break; | |
8416 | default: | |
8417 | g_assert_not_reached(); | |
8418 | } | |
8419 | } else { | |
8420 | switch (opcode) { | |
8421 | case 0xc: /* FMAXNMP */ | |
8422 | gen_helper_vfp_maxnums(tcg_res, tcg_op1, tcg_op2, fpst); | |
8423 | break; | |
8424 | case 0xd: /* FADDP */ | |
8425 | gen_helper_vfp_adds(tcg_res, tcg_op1, tcg_op2, fpst); | |
8426 | break; | |
8427 | case 0xf: /* FMAXP */ | |
8428 | gen_helper_vfp_maxs(tcg_res, tcg_op1, tcg_op2, fpst); | |
8429 | break; | |
8430 | case 0x2c: /* FMINNMP */ | |
8431 | gen_helper_vfp_minnums(tcg_res, tcg_op1, tcg_op2, fpst); | |
8432 | break; | |
8433 | case 0x2f: /* FMINP */ | |
8434 | gen_helper_vfp_mins(tcg_res, tcg_op1, tcg_op2, fpst); | |
8435 | break; | |
8436 | default: | |
8437 | g_assert_not_reached(); | |
8438 | } | |
3720a7ea PM |
8439 | } |
8440 | ||
8441 | write_fp_sreg(s, rd, tcg_res); | |
8442 | ||
8443 | tcg_temp_free_i32(tcg_op1); | |
8444 | tcg_temp_free_i32(tcg_op2); | |
8445 | tcg_temp_free_i32(tcg_res); | |
8446 | } | |
8447 | ||
f764718d | 8448 | if (fpst) { |
3720a7ea PM |
8449 | tcg_temp_free_ptr(fpst); |
8450 | } | |
384b26fb AB |
8451 | } |
8452 | ||
4d1cef84 AB |
8453 | /* |
8454 | * Common SSHR[RA]/USHR[RA] - Shift right (optional rounding/accumulate) | |
8455 | * | |
8456 | * This code is handles the common shifting code and is used by both | |
8457 | * the vector and scalar code. | |
8458 | */ | |
8459 | static void handle_shri_with_rndacc(TCGv_i64 tcg_res, TCGv_i64 tcg_src, | |
8460 | TCGv_i64 tcg_rnd, bool accumulate, | |
8461 | bool is_u, int size, int shift) | |
8462 | { | |
8463 | bool extended_result = false; | |
f764718d | 8464 | bool round = tcg_rnd != NULL; |
4d1cef84 AB |
8465 | int ext_lshift = 0; |
8466 | TCGv_i64 tcg_src_hi; | |
8467 | ||
8468 | if (round && size == 3) { | |
8469 | extended_result = true; | |
8470 | ext_lshift = 64 - shift; | |
8471 | tcg_src_hi = tcg_temp_new_i64(); | |
8472 | } else if (shift == 64) { | |
8473 | if (!accumulate && is_u) { | |
8474 | /* result is zero */ | |
8475 | tcg_gen_movi_i64(tcg_res, 0); | |
8476 | return; | |
8477 | } | |
8478 | } | |
8479 | ||
8480 | /* Deal with the rounding step */ | |
8481 | if (round) { | |
8482 | if (extended_result) { | |
8483 | TCGv_i64 tcg_zero = tcg_const_i64(0); | |
8484 | if (!is_u) { | |
8485 | /* take care of sign extending tcg_res */ | |
8486 | tcg_gen_sari_i64(tcg_src_hi, tcg_src, 63); | |
8487 | tcg_gen_add2_i64(tcg_src, tcg_src_hi, | |
8488 | tcg_src, tcg_src_hi, | |
8489 | tcg_rnd, tcg_zero); | |
8490 | } else { | |
8491 | tcg_gen_add2_i64(tcg_src, tcg_src_hi, | |
8492 | tcg_src, tcg_zero, | |
8493 | tcg_rnd, tcg_zero); | |
8494 | } | |
8495 | tcg_temp_free_i64(tcg_zero); | |
8496 | } else { | |
8497 | tcg_gen_add_i64(tcg_src, tcg_src, tcg_rnd); | |
8498 | } | |
8499 | } | |
8500 | ||
8501 | /* Now do the shift right */ | |
8502 | if (round && extended_result) { | |
8503 | /* extended case, >64 bit precision required */ | |
8504 | if (ext_lshift == 0) { | |
8505 | /* special case, only high bits matter */ | |
8506 | tcg_gen_mov_i64(tcg_src, tcg_src_hi); | |
8507 | } else { | |
8508 | tcg_gen_shri_i64(tcg_src, tcg_src, shift); | |
8509 | tcg_gen_shli_i64(tcg_src_hi, tcg_src_hi, ext_lshift); | |
8510 | tcg_gen_or_i64(tcg_src, tcg_src, tcg_src_hi); | |
8511 | } | |
8512 | } else { | |
8513 | if (is_u) { | |
8514 | if (shift == 64) { | |
8515 | /* essentially shifting in 64 zeros */ | |
8516 | tcg_gen_movi_i64(tcg_src, 0); | |
8517 | } else { | |
8518 | tcg_gen_shri_i64(tcg_src, tcg_src, shift); | |
8519 | } | |
8520 | } else { | |
8521 | if (shift == 64) { | |
8522 | /* effectively extending the sign-bit */ | |
8523 | tcg_gen_sari_i64(tcg_src, tcg_src, 63); | |
8524 | } else { | |
8525 | tcg_gen_sari_i64(tcg_src, tcg_src, shift); | |
8526 | } | |
8527 | } | |
8528 | } | |
8529 | ||
8530 | if (accumulate) { | |
8531 | tcg_gen_add_i64(tcg_res, tcg_res, tcg_src); | |
8532 | } else { | |
8533 | tcg_gen_mov_i64(tcg_res, tcg_src); | |
8534 | } | |
8535 | ||
8536 | if (extended_result) { | |
8537 | tcg_temp_free_i64(tcg_src_hi); | |
8538 | } | |
8539 | } | |
8540 | ||
4d1cef84 AB |
8541 | /* SSHR[RA]/USHR[RA] - Scalar shift right (optional rounding/accumulate) */ |
8542 | static void handle_scalar_simd_shri(DisasContext *s, | |
8543 | bool is_u, int immh, int immb, | |
8544 | int opcode, int rn, int rd) | |
8545 | { | |
8546 | const int size = 3; | |
8547 | int immhb = immh << 3 | immb; | |
8548 | int shift = 2 * (8 << size) - immhb; | |
8549 | bool accumulate = false; | |
8550 | bool round = false; | |
37a706ad | 8551 | bool insert = false; |
4d1cef84 AB |
8552 | TCGv_i64 tcg_rn; |
8553 | TCGv_i64 tcg_rd; | |
8554 | TCGv_i64 tcg_round; | |
8555 | ||
8556 | if (!extract32(immh, 3, 1)) { | |
8557 | unallocated_encoding(s); | |
8558 | return; | |
8559 | } | |
8560 | ||
8c6afa6a PM |
8561 | if (!fp_access_check(s)) { |
8562 | return; | |
8563 | } | |
8564 | ||
4d1cef84 AB |
8565 | switch (opcode) { |
8566 | case 0x02: /* SSRA / USRA (accumulate) */ | |
8567 | accumulate = true; | |
8568 | break; | |
8569 | case 0x04: /* SRSHR / URSHR (rounding) */ | |
8570 | round = true; | |
8571 | break; | |
8572 | case 0x06: /* SRSRA / URSRA (accum + rounding) */ | |
8573 | accumulate = round = true; | |
8574 | break; | |
37a706ad PM |
8575 | case 0x08: /* SRI */ |
8576 | insert = true; | |
8577 | break; | |
4d1cef84 AB |
8578 | } |
8579 | ||
8580 | if (round) { | |
8581 | uint64_t round_const = 1ULL << (shift - 1); | |
8582 | tcg_round = tcg_const_i64(round_const); | |
8583 | } else { | |
f764718d | 8584 | tcg_round = NULL; |
4d1cef84 AB |
8585 | } |
8586 | ||
8587 | tcg_rn = read_fp_dreg(s, rn); | |
37a706ad | 8588 | tcg_rd = (accumulate || insert) ? read_fp_dreg(s, rd) : tcg_temp_new_i64(); |
4d1cef84 | 8589 | |
37a706ad | 8590 | if (insert) { |
cdb45a60 RH |
8591 | /* shift count same as element size is valid but does nothing; |
8592 | * special case to avoid potential shift by 64. | |
8593 | */ | |
8594 | int esize = 8 << size; | |
8595 | if (shift != esize) { | |
8596 | tcg_gen_shri_i64(tcg_rn, tcg_rn, shift); | |
8597 | tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_rn, 0, esize - shift); | |
8598 | } | |
37a706ad PM |
8599 | } else { |
8600 | handle_shri_with_rndacc(tcg_rd, tcg_rn, tcg_round, | |
8601 | accumulate, is_u, size, shift); | |
8602 | } | |
4d1cef84 AB |
8603 | |
8604 | write_fp_dreg(s, rd, tcg_rd); | |
8605 | ||
8606 | tcg_temp_free_i64(tcg_rn); | |
8607 | tcg_temp_free_i64(tcg_rd); | |
8608 | if (round) { | |
8609 | tcg_temp_free_i64(tcg_round); | |
8610 | } | |
8611 | } | |
8612 | ||
8613 | /* SHL/SLI - Scalar shift left */ | |
8614 | static void handle_scalar_simd_shli(DisasContext *s, bool insert, | |
8615 | int immh, int immb, int opcode, | |
8616 | int rn, int rd) | |
8617 | { | |
8618 | int size = 32 - clz32(immh) - 1; | |
8619 | int immhb = immh << 3 | immb; | |
8620 | int shift = immhb - (8 << size); | |
07174c86 CQ |
8621 | TCGv_i64 tcg_rn; |
8622 | TCGv_i64 tcg_rd; | |
4d1cef84 AB |
8623 | |
8624 | if (!extract32(immh, 3, 1)) { | |
8625 | unallocated_encoding(s); | |
8626 | return; | |
8627 | } | |
8628 | ||
8c6afa6a PM |
8629 | if (!fp_access_check(s)) { |
8630 | return; | |
8631 | } | |
8632 | ||
4d1cef84 AB |
8633 | tcg_rn = read_fp_dreg(s, rn); |
8634 | tcg_rd = insert ? read_fp_dreg(s, rd) : tcg_temp_new_i64(); | |
8635 | ||
cdb45a60 RH |
8636 | if (insert) { |
8637 | tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_rn, shift, 64 - shift); | |
8638 | } else { | |
8639 | tcg_gen_shli_i64(tcg_rd, tcg_rn, shift); | |
8640 | } | |
4d1cef84 AB |
8641 | |
8642 | write_fp_dreg(s, rd, tcg_rd); | |
8643 | ||
8644 | tcg_temp_free_i64(tcg_rn); | |
8645 | tcg_temp_free_i64(tcg_rd); | |
8646 | } | |
8647 | ||
c1b876b2 AB |
8648 | /* SQSHRN/SQSHRUN - Saturating (signed/unsigned) shift right with |
8649 | * (signed/unsigned) narrowing */ | |
8650 | static void handle_vec_simd_sqshrn(DisasContext *s, bool is_scalar, bool is_q, | |
8651 | bool is_u_shift, bool is_u_narrow, | |
8652 | int immh, int immb, int opcode, | |
8653 | int rn, int rd) | |
8654 | { | |
8655 | int immhb = immh << 3 | immb; | |
8656 | int size = 32 - clz32(immh) - 1; | |
8657 | int esize = 8 << size; | |
8658 | int shift = (2 * esize) - immhb; | |
8659 | int elements = is_scalar ? 1 : (64 / esize); | |
8660 | bool round = extract32(opcode, 0, 1); | |
14776ab5 | 8661 | MemOp ldop = (size + 1) | (is_u_shift ? 0 : MO_SIGN); |
c1b876b2 AB |
8662 | TCGv_i64 tcg_rn, tcg_rd, tcg_round; |
8663 | TCGv_i32 tcg_rd_narrowed; | |
8664 | TCGv_i64 tcg_final; | |
8665 | ||
8666 | static NeonGenNarrowEnvFn * const signed_narrow_fns[4][2] = { | |
8667 | { gen_helper_neon_narrow_sat_s8, | |
8668 | gen_helper_neon_unarrow_sat8 }, | |
8669 | { gen_helper_neon_narrow_sat_s16, | |
8670 | gen_helper_neon_unarrow_sat16 }, | |
8671 | { gen_helper_neon_narrow_sat_s32, | |
8672 | gen_helper_neon_unarrow_sat32 }, | |
8673 | { NULL, NULL }, | |
8674 | }; | |
8675 | static NeonGenNarrowEnvFn * const unsigned_narrow_fns[4] = { | |
8676 | gen_helper_neon_narrow_sat_u8, | |
8677 | gen_helper_neon_narrow_sat_u16, | |
8678 | gen_helper_neon_narrow_sat_u32, | |
8679 | NULL | |
8680 | }; | |
8681 | NeonGenNarrowEnvFn *narrowfn; | |
8682 | ||
8683 | int i; | |
8684 | ||
8685 | assert(size < 4); | |
8686 | ||
8687 | if (extract32(immh, 3, 1)) { | |
8688 | unallocated_encoding(s); | |
8689 | return; | |
8690 | } | |
8691 | ||
8c6afa6a PM |
8692 | if (!fp_access_check(s)) { |
8693 | return; | |
8694 | } | |
8695 | ||
c1b876b2 AB |
8696 | if (is_u_shift) { |
8697 | narrowfn = unsigned_narrow_fns[size]; | |
8698 | } else { | |
8699 | narrowfn = signed_narrow_fns[size][is_u_narrow ? 1 : 0]; | |
8700 | } | |
8701 | ||
8702 | tcg_rn = tcg_temp_new_i64(); | |
8703 | tcg_rd = tcg_temp_new_i64(); | |
8704 | tcg_rd_narrowed = tcg_temp_new_i32(); | |
8705 | tcg_final = tcg_const_i64(0); | |
8706 | ||
8707 | if (round) { | |
8708 | uint64_t round_const = 1ULL << (shift - 1); | |
8709 | tcg_round = tcg_const_i64(round_const); | |
8710 | } else { | |
f764718d | 8711 | tcg_round = NULL; |
c1b876b2 AB |
8712 | } |
8713 | ||
8714 | for (i = 0; i < elements; i++) { | |
8715 | read_vec_element(s, tcg_rn, rn, i, ldop); | |
8716 | handle_shri_with_rndacc(tcg_rd, tcg_rn, tcg_round, | |
8717 | false, is_u_shift, size+1, shift); | |
8718 | narrowfn(tcg_rd_narrowed, cpu_env, tcg_rd); | |
8719 | tcg_gen_extu_i32_i64(tcg_rd, tcg_rd_narrowed); | |
8720 | tcg_gen_deposit_i64(tcg_final, tcg_final, tcg_rd, esize * i, esize); | |
8721 | } | |
8722 | ||
8723 | if (!is_q) { | |
c1b876b2 AB |
8724 | write_vec_element(s, tcg_final, rd, 0, MO_64); |
8725 | } else { | |
8726 | write_vec_element(s, tcg_final, rd, 1, MO_64); | |
8727 | } | |
8728 | ||
8729 | if (round) { | |
8730 | tcg_temp_free_i64(tcg_round); | |
8731 | } | |
8732 | tcg_temp_free_i64(tcg_rn); | |
8733 | tcg_temp_free_i64(tcg_rd); | |
8734 | tcg_temp_free_i32(tcg_rd_narrowed); | |
8735 | tcg_temp_free_i64(tcg_final); | |
4ff55bcb RH |
8736 | |
8737 | clear_vec_high(s, is_q, rd); | |
c1b876b2 AB |
8738 | } |
8739 | ||
a847f32c PM |
8740 | /* SQSHLU, UQSHL, SQSHL: saturating left shifts */ |
8741 | static void handle_simd_qshl(DisasContext *s, bool scalar, bool is_q, | |
8742 | bool src_unsigned, bool dst_unsigned, | |
8743 | int immh, int immb, int rn, int rd) | |
8744 | { | |
8745 | int immhb = immh << 3 | immb; | |
8746 | int size = 32 - clz32(immh) - 1; | |
8747 | int shift = immhb - (8 << size); | |
8748 | int pass; | |
8749 | ||
8750 | assert(immh != 0); | |
8751 | assert(!(scalar && is_q)); | |
8752 | ||
8753 | if (!scalar) { | |
8754 | if (!is_q && extract32(immh, 3, 1)) { | |
8755 | unallocated_encoding(s); | |
8756 | return; | |
8757 | } | |
8758 | ||
8759 | /* Since we use the variable-shift helpers we must | |
8760 | * replicate the shift count into each element of | |
8761 | * the tcg_shift value. | |
8762 | */ | |
8763 | switch (size) { | |
8764 | case 0: | |
8765 | shift |= shift << 8; | |
8766 | /* fall through */ | |
8767 | case 1: | |
8768 | shift |= shift << 16; | |
8769 | break; | |
8770 | case 2: | |
8771 | case 3: | |
8772 | break; | |
8773 | default: | |
8774 | g_assert_not_reached(); | |
8775 | } | |
8776 | } | |
8777 | ||
8c6afa6a PM |
8778 | if (!fp_access_check(s)) { |
8779 | return; | |
8780 | } | |
8781 | ||
a847f32c PM |
8782 | if (size == 3) { |
8783 | TCGv_i64 tcg_shift = tcg_const_i64(shift); | |
8784 | static NeonGenTwo64OpEnvFn * const fns[2][2] = { | |
8785 | { gen_helper_neon_qshl_s64, gen_helper_neon_qshlu_s64 }, | |
8786 | { NULL, gen_helper_neon_qshl_u64 }, | |
8787 | }; | |
8788 | NeonGenTwo64OpEnvFn *genfn = fns[src_unsigned][dst_unsigned]; | |
8789 | int maxpass = is_q ? 2 : 1; | |
8790 | ||
8791 | for (pass = 0; pass < maxpass; pass++) { | |
8792 | TCGv_i64 tcg_op = tcg_temp_new_i64(); | |
8793 | ||
8794 | read_vec_element(s, tcg_op, rn, pass, MO_64); | |
8795 | genfn(tcg_op, cpu_env, tcg_op, tcg_shift); | |
8796 | write_vec_element(s, tcg_op, rd, pass, MO_64); | |
8797 | ||
8798 | tcg_temp_free_i64(tcg_op); | |
8799 | } | |
8800 | tcg_temp_free_i64(tcg_shift); | |
4ff55bcb | 8801 | clear_vec_high(s, is_q, rd); |
a847f32c PM |
8802 | } else { |
8803 | TCGv_i32 tcg_shift = tcg_const_i32(shift); | |
8804 | static NeonGenTwoOpEnvFn * const fns[2][2][3] = { | |
8805 | { | |
8806 | { gen_helper_neon_qshl_s8, | |
8807 | gen_helper_neon_qshl_s16, | |
8808 | gen_helper_neon_qshl_s32 }, | |
8809 | { gen_helper_neon_qshlu_s8, | |
8810 | gen_helper_neon_qshlu_s16, | |
8811 | gen_helper_neon_qshlu_s32 } | |
8812 | }, { | |
8813 | { NULL, NULL, NULL }, | |
8814 | { gen_helper_neon_qshl_u8, | |
8815 | gen_helper_neon_qshl_u16, | |
8816 | gen_helper_neon_qshl_u32 } | |
8817 | } | |
8818 | }; | |
8819 | NeonGenTwoOpEnvFn *genfn = fns[src_unsigned][dst_unsigned][size]; | |
14776ab5 | 8820 | MemOp memop = scalar ? size : MO_32; |
a847f32c PM |
8821 | int maxpass = scalar ? 1 : is_q ? 4 : 2; |
8822 | ||
8823 | for (pass = 0; pass < maxpass; pass++) { | |
8824 | TCGv_i32 tcg_op = tcg_temp_new_i32(); | |
8825 | ||
8826 | read_vec_element_i32(s, tcg_op, rn, pass, memop); | |
8827 | genfn(tcg_op, cpu_env, tcg_op, tcg_shift); | |
8828 | if (scalar) { | |
8829 | switch (size) { | |
8830 | case 0: | |
8831 | tcg_gen_ext8u_i32(tcg_op, tcg_op); | |
8832 | break; | |
8833 | case 1: | |
8834 | tcg_gen_ext16u_i32(tcg_op, tcg_op); | |
8835 | break; | |
8836 | case 2: | |
8837 | break; | |
8838 | default: | |
8839 | g_assert_not_reached(); | |
8840 | } | |
8841 | write_fp_sreg(s, rd, tcg_op); | |
8842 | } else { | |
8843 | write_vec_element_i32(s, tcg_op, rd, pass, MO_32); | |
8844 | } | |
8845 | ||
8846 | tcg_temp_free_i32(tcg_op); | |
8847 | } | |
8848 | tcg_temp_free_i32(tcg_shift); | |
8849 | ||
4ff55bcb RH |
8850 | if (!scalar) { |
8851 | clear_vec_high(s, is_q, rd); | |
a847f32c PM |
8852 | } |
8853 | } | |
8854 | } | |
8855 | ||
10113b69 AB |
8856 | /* Common vector code for handling integer to FP conversion */ |
8857 | static void handle_simd_intfp_conv(DisasContext *s, int rd, int rn, | |
8858 | int elements, int is_signed, | |
8859 | int fracbits, int size) | |
8860 | { | |
cdfb22bb | 8861 | TCGv_ptr tcg_fpst = fpstatus_ptr(size == MO_16 ? FPST_FPCR_F16 : FPST_FPCR); |
93193190 AB |
8862 | TCGv_i32 tcg_shift = NULL; |
8863 | ||
14776ab5 | 8864 | MemOp mop = size | (is_signed ? MO_SIGN : 0); |
10113b69 AB |
8865 | int pass; |
8866 | ||
93193190 AB |
8867 | if (fracbits || size == MO_64) { |
8868 | tcg_shift = tcg_const_i32(fracbits); | |
8869 | } | |
8870 | ||
8871 | if (size == MO_64) { | |
8872 | TCGv_i64 tcg_int64 = tcg_temp_new_i64(); | |
8873 | TCGv_i64 tcg_double = tcg_temp_new_i64(); | |
8874 | ||
8875 | for (pass = 0; pass < elements; pass++) { | |
8876 | read_vec_element(s, tcg_int64, rn, pass, mop); | |
10113b69 | 8877 | |
10113b69 | 8878 | if (is_signed) { |
93193190 | 8879 | gen_helper_vfp_sqtod(tcg_double, tcg_int64, |
10113b69 AB |
8880 | tcg_shift, tcg_fpst); |
8881 | } else { | |
93193190 | 8882 | gen_helper_vfp_uqtod(tcg_double, tcg_int64, |
10113b69 AB |
8883 | tcg_shift, tcg_fpst); |
8884 | } | |
8885 | if (elements == 1) { | |
8886 | write_fp_dreg(s, rd, tcg_double); | |
8887 | } else { | |
8888 | write_vec_element(s, tcg_double, rd, pass, MO_64); | |
8889 | } | |
93193190 AB |
8890 | } |
8891 | ||
8892 | tcg_temp_free_i64(tcg_int64); | |
8893 | tcg_temp_free_i64(tcg_double); | |
8894 | ||
8895 | } else { | |
8896 | TCGv_i32 tcg_int32 = tcg_temp_new_i32(); | |
8897 | TCGv_i32 tcg_float = tcg_temp_new_i32(); | |
8898 | ||
8899 | for (pass = 0; pass < elements; pass++) { | |
8900 | read_vec_element_i32(s, tcg_int32, rn, pass, mop); | |
8901 | ||
8902 | switch (size) { | |
8903 | case MO_32: | |
8904 | if (fracbits) { | |
8905 | if (is_signed) { | |
8906 | gen_helper_vfp_sltos(tcg_float, tcg_int32, | |
8907 | tcg_shift, tcg_fpst); | |
8908 | } else { | |
8909 | gen_helper_vfp_ultos(tcg_float, tcg_int32, | |
8910 | tcg_shift, tcg_fpst); | |
8911 | } | |
8912 | } else { | |
8913 | if (is_signed) { | |
8914 | gen_helper_vfp_sitos(tcg_float, tcg_int32, tcg_fpst); | |
8915 | } else { | |
8916 | gen_helper_vfp_uitos(tcg_float, tcg_int32, tcg_fpst); | |
8917 | } | |
8918 | } | |
8919 | break; | |
8920 | case MO_16: | |
8921 | if (fracbits) { | |
8922 | if (is_signed) { | |
8923 | gen_helper_vfp_sltoh(tcg_float, tcg_int32, | |
8924 | tcg_shift, tcg_fpst); | |
8925 | } else { | |
8926 | gen_helper_vfp_ultoh(tcg_float, tcg_int32, | |
8927 | tcg_shift, tcg_fpst); | |
8928 | } | |
8929 | } else { | |
8930 | if (is_signed) { | |
8931 | gen_helper_vfp_sitoh(tcg_float, tcg_int32, tcg_fpst); | |
8932 | } else { | |
8933 | gen_helper_vfp_uitoh(tcg_float, tcg_int32, tcg_fpst); | |
8934 | } | |
8935 | } | |
8936 | break; | |
8937 | default: | |
8938 | g_assert_not_reached(); | |
10113b69 | 8939 | } |
93193190 | 8940 | |
10113b69 | 8941 | if (elements == 1) { |
93193190 | 8942 | write_fp_sreg(s, rd, tcg_float); |
10113b69 | 8943 | } else { |
93193190 | 8944 | write_vec_element_i32(s, tcg_float, rd, pass, size); |
10113b69 | 8945 | } |
10113b69 | 8946 | } |
93193190 AB |
8947 | |
8948 | tcg_temp_free_i32(tcg_int32); | |
8949 | tcg_temp_free_i32(tcg_float); | |
10113b69 AB |
8950 | } |
8951 | ||
10113b69 | 8952 | tcg_temp_free_ptr(tcg_fpst); |
93193190 AB |
8953 | if (tcg_shift) { |
8954 | tcg_temp_free_i32(tcg_shift); | |
8955 | } | |
4ff55bcb RH |
8956 | |
8957 | clear_vec_high(s, elements << size == 16, rd); | |
10113b69 AB |
8958 | } |
8959 | ||
8960 | /* UCVTF/SCVTF - Integer to FP conversion */ | |
8961 | static void handle_simd_shift_intfp_conv(DisasContext *s, bool is_scalar, | |
8962 | bool is_q, bool is_u, | |
8963 | int immh, int immb, int opcode, | |
8964 | int rn, int rd) | |
8965 | { | |
a6117fae | 8966 | int size, elements, fracbits; |
10113b69 | 8967 | int immhb = immh << 3 | immb; |
10113b69 | 8968 | |
a6117fae RH |
8969 | if (immh & 8) { |
8970 | size = MO_64; | |
8971 | if (!is_scalar && !is_q) { | |
8972 | unallocated_encoding(s); | |
8973 | return; | |
8974 | } | |
8975 | } else if (immh & 4) { | |
8976 | size = MO_32; | |
8977 | } else if (immh & 2) { | |
8978 | size = MO_16; | |
5763190f | 8979 | if (!dc_isar_feature(aa64_fp16, s)) { |
a6117fae RH |
8980 | unallocated_encoding(s); |
8981 | return; | |
8982 | } | |
8983 | } else { | |
8984 | /* immh == 0 would be a failure of the decode logic */ | |
8985 | g_assert(immh == 1); | |
10113b69 AB |
8986 | unallocated_encoding(s); |
8987 | return; | |
8988 | } | |
8989 | ||
8990 | if (is_scalar) { | |
8991 | elements = 1; | |
8992 | } else { | |
a6117fae | 8993 | elements = (8 << is_q) >> size; |
10113b69 | 8994 | } |
a6117fae | 8995 | fracbits = (16 << size) - immhb; |
8c6afa6a PM |
8996 | |
8997 | if (!fp_access_check(s)) { | |
8998 | return; | |
8999 | } | |
9000 | ||
10113b69 AB |
9001 | handle_simd_intfp_conv(s, rd, rn, elements, !is_u, fracbits, size); |
9002 | } | |
9003 | ||
2ed3ea11 PM |
9004 | /* FCVTZS, FVCVTZU - FP to fixedpoint conversion */ |
9005 | static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar, | |
9006 | bool is_q, bool is_u, | |
9007 | int immh, int immb, int rn, int rd) | |
9008 | { | |
2ed3ea11 | 9009 | int immhb = immh << 3 | immb; |
d0ba8e74 | 9010 | int pass, size, fracbits; |
2ed3ea11 PM |
9011 | TCGv_ptr tcg_fpstatus; |
9012 | TCGv_i32 tcg_rmode, tcg_shift; | |
9013 | ||
d0ba8e74 RH |
9014 | if (immh & 0x8) { |
9015 | size = MO_64; | |
9016 | if (!is_scalar && !is_q) { | |
9017 | unallocated_encoding(s); | |
9018 | return; | |
9019 | } | |
9020 | } else if (immh & 0x4) { | |
9021 | size = MO_32; | |
9022 | } else if (immh & 0x2) { | |
9023 | size = MO_16; | |
5763190f | 9024 | if (!dc_isar_feature(aa64_fp16, s)) { |
d0ba8e74 RH |
9025 | unallocated_encoding(s); |
9026 | return; | |
9027 | } | |
9028 | } else { | |
9029 | /* Should have split out AdvSIMD modified immediate earlier. */ | |
9030 | assert(immh == 1); | |
2ed3ea11 PM |
9031 | unallocated_encoding(s); |
9032 | return; | |
9033 | } | |
9034 | ||
8c6afa6a PM |
9035 | if (!fp_access_check(s)) { |
9036 | return; | |
9037 | } | |
9038 | ||
2ed3ea11 PM |
9039 | assert(!(is_scalar && is_q)); |
9040 | ||
9041 | tcg_rmode = tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO)); | |
cdfb22bb | 9042 | tcg_fpstatus = fpstatus_ptr(size == MO_16 ? FPST_FPCR_F16 : FPST_FPCR); |
9b049916 | 9043 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); |
d0ba8e74 | 9044 | fracbits = (16 << size) - immhb; |
2ed3ea11 PM |
9045 | tcg_shift = tcg_const_i32(fracbits); |
9046 | ||
d0ba8e74 | 9047 | if (size == MO_64) { |
4063452e | 9048 | int maxpass = is_scalar ? 1 : 2; |
2ed3ea11 PM |
9049 | |
9050 | for (pass = 0; pass < maxpass; pass++) { | |
9051 | TCGv_i64 tcg_op = tcg_temp_new_i64(); | |
9052 | ||
9053 | read_vec_element(s, tcg_op, rn, pass, MO_64); | |
9054 | if (is_u) { | |
9055 | gen_helper_vfp_touqd(tcg_op, tcg_op, tcg_shift, tcg_fpstatus); | |
9056 | } else { | |
9057 | gen_helper_vfp_tosqd(tcg_op, tcg_op, tcg_shift, tcg_fpstatus); | |
9058 | } | |
9059 | write_vec_element(s, tcg_op, rd, pass, MO_64); | |
9060 | tcg_temp_free_i64(tcg_op); | |
9061 | } | |
4ff55bcb | 9062 | clear_vec_high(s, is_q, rd); |
2ed3ea11 | 9063 | } else { |
d0ba8e74 RH |
9064 | void (*fn)(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_ptr); |
9065 | int maxpass = is_scalar ? 1 : ((8 << is_q) >> size); | |
2ed3ea11 | 9066 | |
d0ba8e74 RH |
9067 | switch (size) { |
9068 | case MO_16: | |
2ed3ea11 | 9069 | if (is_u) { |
88808a02 | 9070 | fn = gen_helper_vfp_touhh; |
2ed3ea11 | 9071 | } else { |
88808a02 | 9072 | fn = gen_helper_vfp_toshh; |
2ed3ea11 | 9073 | } |
d0ba8e74 RH |
9074 | break; |
9075 | case MO_32: | |
2ed3ea11 | 9076 | if (is_u) { |
d0ba8e74 | 9077 | fn = gen_helper_vfp_touls; |
2ed3ea11 | 9078 | } else { |
d0ba8e74 | 9079 | fn = gen_helper_vfp_tosls; |
2ed3ea11 | 9080 | } |
d0ba8e74 RH |
9081 | break; |
9082 | default: | |
9083 | g_assert_not_reached(); | |
9084 | } | |
9085 | ||
9086 | for (pass = 0; pass < maxpass; pass++) { | |
9087 | TCGv_i32 tcg_op = tcg_temp_new_i32(); | |
9088 | ||
9089 | read_vec_element_i32(s, tcg_op, rn, pass, size); | |
9090 | fn(tcg_op, tcg_op, tcg_shift, tcg_fpstatus); | |
2ed3ea11 PM |
9091 | if (is_scalar) { |
9092 | write_fp_sreg(s, rd, tcg_op); | |
9093 | } else { | |
d0ba8e74 | 9094 | write_vec_element_i32(s, tcg_op, rd, pass, size); |
2ed3ea11 PM |
9095 | } |
9096 | tcg_temp_free_i32(tcg_op); | |
9097 | } | |
4ff55bcb RH |
9098 | if (!is_scalar) { |
9099 | clear_vec_high(s, is_q, rd); | |
2ed3ea11 PM |
9100 | } |
9101 | } | |
9102 | ||
9103 | tcg_temp_free_ptr(tcg_fpstatus); | |
9104 | tcg_temp_free_i32(tcg_shift); | |
9b049916 | 9105 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); |
2ed3ea11 PM |
9106 | tcg_temp_free_i32(tcg_rmode); |
9107 | } | |
9108 | ||
4ce31af4 | 9109 | /* AdvSIMD scalar shift by immediate |
384b26fb AB |
9110 | * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0 |
9111 | * +-----+---+-------------+------+------+--------+---+------+------+ | |
9112 | * | 0 1 | U | 1 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd | | |
9113 | * +-----+---+-------------+------+------+--------+---+------+------+ | |
4d1cef84 AB |
9114 | * |
9115 | * This is the scalar version so it works on a fixed sized registers | |
384b26fb AB |
9116 | */ |
9117 | static void disas_simd_scalar_shift_imm(DisasContext *s, uint32_t insn) | |
9118 | { | |
4d1cef84 AB |
9119 | int rd = extract32(insn, 0, 5); |
9120 | int rn = extract32(insn, 5, 5); | |
9121 | int opcode = extract32(insn, 11, 5); | |
9122 | int immb = extract32(insn, 16, 3); | |
9123 | int immh = extract32(insn, 19, 4); | |
9124 | bool is_u = extract32(insn, 29, 1); | |
9125 | ||
c1b876b2 AB |
9126 | if (immh == 0) { |
9127 | unallocated_encoding(s); | |
9128 | return; | |
9129 | } | |
9130 | ||
4d1cef84 | 9131 | switch (opcode) { |
37a706ad PM |
9132 | case 0x08: /* SRI */ |
9133 | if (!is_u) { | |
9134 | unallocated_encoding(s); | |
9135 | return; | |
9136 | } | |
9137 | /* fall through */ | |
4d1cef84 AB |
9138 | case 0x00: /* SSHR / USHR */ |
9139 | case 0x02: /* SSRA / USRA */ | |
9140 | case 0x04: /* SRSHR / URSHR */ | |
9141 | case 0x06: /* SRSRA / URSRA */ | |
9142 | handle_scalar_simd_shri(s, is_u, immh, immb, opcode, rn, rd); | |
9143 | break; | |
9144 | case 0x0a: /* SHL / SLI */ | |
9145 | handle_scalar_simd_shli(s, is_u, immh, immb, opcode, rn, rd); | |
9146 | break; | |
10113b69 AB |
9147 | case 0x1c: /* SCVTF, UCVTF */ |
9148 | handle_simd_shift_intfp_conv(s, true, false, is_u, immh, immb, | |
9149 | opcode, rn, rd); | |
9150 | break; | |
c1b876b2 AB |
9151 | case 0x10: /* SQSHRUN, SQSHRUN2 */ |
9152 | case 0x11: /* SQRSHRUN, SQRSHRUN2 */ | |
9153 | if (!is_u) { | |
9154 | unallocated_encoding(s); | |
9155 | return; | |
9156 | } | |
9157 | handle_vec_simd_sqshrn(s, true, false, false, true, | |
9158 | immh, immb, opcode, rn, rd); | |
9159 | break; | |
9160 | case 0x12: /* SQSHRN, SQSHRN2, UQSHRN */ | |
9161 | case 0x13: /* SQRSHRN, SQRSHRN2, UQRSHRN, UQRSHRN2 */ | |
9162 | handle_vec_simd_sqshrn(s, true, false, is_u, is_u, | |
9163 | immh, immb, opcode, rn, rd); | |
9164 | break; | |
a566da1b | 9165 | case 0xc: /* SQSHLU */ |
a847f32c PM |
9166 | if (!is_u) { |
9167 | unallocated_encoding(s); | |
9168 | return; | |
9169 | } | |
9170 | handle_simd_qshl(s, true, false, false, true, immh, immb, rn, rd); | |
9171 | break; | |
a566da1b | 9172 | case 0xe: /* SQSHL, UQSHL */ |
a847f32c PM |
9173 | handle_simd_qshl(s, true, false, is_u, is_u, immh, immb, rn, rd); |
9174 | break; | |
a566da1b | 9175 | case 0x1f: /* FCVTZS, FCVTZU */ |
2ed3ea11 | 9176 | handle_simd_shift_fpint_conv(s, true, false, is_u, immh, immb, rn, rd); |
4d1cef84 | 9177 | break; |
a566da1b PM |
9178 | default: |
9179 | unallocated_encoding(s); | |
9180 | break; | |
4d1cef84 | 9181 | } |
384b26fb AB |
9182 | } |
9183 | ||
4ce31af4 | 9184 | /* AdvSIMD scalar three different |
384b26fb AB |
9185 | * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0 |
9186 | * +-----+---+-----------+------+---+------+--------+-----+------+------+ | |
9187 | * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd | | |
9188 | * +-----+---+-----------+------+---+------+--------+-----+------+------+ | |
9189 | */ | |
9190 | static void disas_simd_scalar_three_reg_diff(DisasContext *s, uint32_t insn) | |
9191 | { | |
b033cd3d PM |
9192 | bool is_u = extract32(insn, 29, 1); |
9193 | int size = extract32(insn, 22, 2); | |
9194 | int opcode = extract32(insn, 12, 4); | |
9195 | int rm = extract32(insn, 16, 5); | |
9196 | int rn = extract32(insn, 5, 5); | |
9197 | int rd = extract32(insn, 0, 5); | |
9198 | ||
9199 | if (is_u) { | |
9200 | unallocated_encoding(s); | |
9201 | return; | |
9202 | } | |
9203 | ||
9204 | switch (opcode) { | |
9205 | case 0x9: /* SQDMLAL, SQDMLAL2 */ | |
9206 | case 0xb: /* SQDMLSL, SQDMLSL2 */ | |
9207 | case 0xd: /* SQDMULL, SQDMULL2 */ | |
9208 | if (size == 0 || size == 3) { | |
9209 | unallocated_encoding(s); | |
9210 | return; | |
9211 | } | |
9212 | break; | |
9213 | default: | |
9214 | unallocated_encoding(s); | |
9215 | return; | |
9216 | } | |
9217 | ||
8c6afa6a PM |
9218 | if (!fp_access_check(s)) { |
9219 | return; | |
9220 | } | |
9221 | ||
b033cd3d PM |
9222 | if (size == 2) { |
9223 | TCGv_i64 tcg_op1 = tcg_temp_new_i64(); | |
9224 | TCGv_i64 tcg_op2 = tcg_temp_new_i64(); | |
9225 | TCGv_i64 tcg_res = tcg_temp_new_i64(); | |
9226 | ||
9227 | read_vec_element(s, tcg_op1, rn, 0, MO_32 | MO_SIGN); | |
9228 | read_vec_element(s, tcg_op2, rm, 0, MO_32 | MO_SIGN); | |
9229 | ||
9230 | tcg_gen_mul_i64(tcg_res, tcg_op1, tcg_op2); | |
9231 | gen_helper_neon_addl_saturate_s64(tcg_res, cpu_env, tcg_res, tcg_res); | |
9232 | ||
9233 | switch (opcode) { | |
9234 | case 0xd: /* SQDMULL, SQDMULL2 */ | |
9235 | break; | |
9236 | case 0xb: /* SQDMLSL, SQDMLSL2 */ | |
9237 | tcg_gen_neg_i64(tcg_res, tcg_res); | |
9238 | /* fall through */ | |
9239 | case 0x9: /* SQDMLAL, SQDMLAL2 */ | |
9240 | read_vec_element(s, tcg_op1, rd, 0, MO_64); | |
9241 | gen_helper_neon_addl_saturate_s64(tcg_res, cpu_env, | |
9242 | tcg_res, tcg_op1); | |
9243 | break; | |
9244 | default: | |
9245 | g_assert_not_reached(); | |
9246 | } | |
9247 | ||
9248 | write_fp_dreg(s, rd, tcg_res); | |
9249 | ||
9250 | tcg_temp_free_i64(tcg_op1); | |
9251 | tcg_temp_free_i64(tcg_op2); | |
9252 | tcg_temp_free_i64(tcg_res); | |
9253 | } else { | |
3d99d931 RH |
9254 | TCGv_i32 tcg_op1 = read_fp_hreg(s, rn); |
9255 | TCGv_i32 tcg_op2 = read_fp_hreg(s, rm); | |
b033cd3d PM |
9256 | TCGv_i64 tcg_res = tcg_temp_new_i64(); |
9257 | ||
b033cd3d PM |
9258 | gen_helper_neon_mull_s16(tcg_res, tcg_op1, tcg_op2); |
9259 | gen_helper_neon_addl_saturate_s32(tcg_res, cpu_env, tcg_res, tcg_res); | |
9260 | ||
9261 | switch (opcode) { | |
9262 | case 0xd: /* SQDMULL, SQDMULL2 */ | |
9263 | break; | |
9264 | case 0xb: /* SQDMLSL, SQDMLSL2 */ | |
9265 | gen_helper_neon_negl_u32(tcg_res, tcg_res); | |
9266 | /* fall through */ | |
9267 | case 0x9: /* SQDMLAL, SQDMLAL2 */ | |
9268 | { | |
9269 | TCGv_i64 tcg_op3 = tcg_temp_new_i64(); | |
9270 | read_vec_element(s, tcg_op3, rd, 0, MO_32); | |
9271 | gen_helper_neon_addl_saturate_s32(tcg_res, cpu_env, | |
9272 | tcg_res, tcg_op3); | |
9273 | tcg_temp_free_i64(tcg_op3); | |
9274 | break; | |
9275 | } | |
9276 | default: | |
9277 | g_assert_not_reached(); | |
9278 | } | |
9279 | ||
9280 | tcg_gen_ext32u_i64(tcg_res, tcg_res); | |
9281 | write_fp_dreg(s, rd, tcg_res); | |
9282 | ||
9283 | tcg_temp_free_i32(tcg_op1); | |
9284 | tcg_temp_free_i32(tcg_op2); | |
9285 | tcg_temp_free_i64(tcg_res); | |
9286 | } | |
384b26fb AB |
9287 | } |
9288 | ||
b305dba6 PM |
9289 | static void handle_3same_64(DisasContext *s, int opcode, bool u, |
9290 | TCGv_i64 tcg_rd, TCGv_i64 tcg_rn, TCGv_i64 tcg_rm) | |
9291 | { | |
9292 | /* Handle 64x64->64 opcodes which are shared between the scalar | |
9293 | * and vector 3-same groups. We cover every opcode where size == 3 | |
9294 | * is valid in either the three-reg-same (integer, not pairwise) | |
3840d219 | 9295 | * or scalar-three-reg-same groups. |
b305dba6 PM |
9296 | */ |
9297 | TCGCond cond; | |
9298 | ||
9299 | switch (opcode) { | |
6d9571f7 PM |
9300 | case 0x1: /* SQADD */ |
9301 | if (u) { | |
9302 | gen_helper_neon_qadd_u64(tcg_rd, cpu_env, tcg_rn, tcg_rm); | |
9303 | } else { | |
9304 | gen_helper_neon_qadd_s64(tcg_rd, cpu_env, tcg_rn, tcg_rm); | |
9305 | } | |
9306 | break; | |
9307 | case 0x5: /* SQSUB */ | |
9308 | if (u) { | |
9309 | gen_helper_neon_qsub_u64(tcg_rd, cpu_env, tcg_rn, tcg_rm); | |
9310 | } else { | |
9311 | gen_helper_neon_qsub_s64(tcg_rd, cpu_env, tcg_rn, tcg_rm); | |
9312 | } | |
9313 | break; | |
b305dba6 PM |
9314 | case 0x6: /* CMGT, CMHI */ |
9315 | /* 64 bit integer comparison, result = test ? (2^64 - 1) : 0. | |
9316 | * We implement this using setcond (test) and then negating. | |
9317 | */ | |
9318 | cond = u ? TCG_COND_GTU : TCG_COND_GT; | |
9319 | do_cmop: | |
9320 | tcg_gen_setcond_i64(cond, tcg_rd, tcg_rn, tcg_rm); | |
9321 | tcg_gen_neg_i64(tcg_rd, tcg_rd); | |
9322 | break; | |
9323 | case 0x7: /* CMGE, CMHS */ | |
9324 | cond = u ? TCG_COND_GEU : TCG_COND_GE; | |
9325 | goto do_cmop; | |
9326 | case 0x11: /* CMTST, CMEQ */ | |
9327 | if (u) { | |
9328 | cond = TCG_COND_EQ; | |
9329 | goto do_cmop; | |
9330 | } | |
79d61de6 | 9331 | gen_cmtst_i64(tcg_rd, tcg_rn, tcg_rm); |
b305dba6 | 9332 | break; |
6d9571f7 | 9333 | case 0x8: /* SSHL, USHL */ |
b305dba6 | 9334 | if (u) { |
87b74e8b | 9335 | gen_ushl_i64(tcg_rd, tcg_rn, tcg_rm); |
b305dba6 | 9336 | } else { |
87b74e8b | 9337 | gen_sshl_i64(tcg_rd, tcg_rn, tcg_rm); |
b305dba6 PM |
9338 | } |
9339 | break; | |
b305dba6 | 9340 | case 0x9: /* SQSHL, UQSHL */ |
6d9571f7 PM |
9341 | if (u) { |
9342 | gen_helper_neon_qshl_u64(tcg_rd, cpu_env, tcg_rn, tcg_rm); | |
9343 | } else { | |
9344 | gen_helper_neon_qshl_s64(tcg_rd, cpu_env, tcg_rn, tcg_rm); | |
9345 | } | |
9346 | break; | |
b305dba6 | 9347 | case 0xa: /* SRSHL, URSHL */ |
6d9571f7 PM |
9348 | if (u) { |
9349 | gen_helper_neon_rshl_u64(tcg_rd, tcg_rn, tcg_rm); | |
9350 | } else { | |
9351 | gen_helper_neon_rshl_s64(tcg_rd, tcg_rn, tcg_rm); | |
9352 | } | |
9353 | break; | |
b305dba6 | 9354 | case 0xb: /* SQRSHL, UQRSHL */ |
6d9571f7 PM |
9355 | if (u) { |
9356 | gen_helper_neon_qrshl_u64(tcg_rd, cpu_env, tcg_rn, tcg_rm); | |
9357 | } else { | |
9358 | gen_helper_neon_qrshl_s64(tcg_rd, cpu_env, tcg_rn, tcg_rm); | |
9359 | } | |
9360 | break; | |
9361 | case 0x10: /* ADD, SUB */ | |
9362 | if (u) { | |
9363 | tcg_gen_sub_i64(tcg_rd, tcg_rn, tcg_rm); | |
9364 | } else { | |
9365 | tcg_gen_add_i64(tcg_rd, tcg_rn, tcg_rm); | |
9366 | } | |
9367 | break; | |
b305dba6 PM |
9368 | default: |
9369 | g_assert_not_reached(); | |
9370 | } | |
9371 | } | |
9372 | ||
845ea09a PM |
9373 | /* Handle the 3-same-operands float operations; shared by the scalar |
9374 | * and vector encodings. The caller must filter out any encodings | |
9375 | * not allocated for the encoding it is dealing with. | |
9376 | */ | |
9377 | static void handle_3same_float(DisasContext *s, int size, int elements, | |
9378 | int fpopcode, int rd, int rn, int rm) | |
9379 | { | |
9380 | int pass; | |
cdfb22bb | 9381 | TCGv_ptr fpst = fpstatus_ptr(FPST_FPCR); |
845ea09a PM |
9382 | |
9383 | for (pass = 0; pass < elements; pass++) { | |
9384 | if (size) { | |
9385 | /* Double */ | |
9386 | TCGv_i64 tcg_op1 = tcg_temp_new_i64(); | |
9387 | TCGv_i64 tcg_op2 = tcg_temp_new_i64(); | |
9388 | TCGv_i64 tcg_res = tcg_temp_new_i64(); | |
9389 | ||
9390 | read_vec_element(s, tcg_op1, rn, pass, MO_64); | |
9391 | read_vec_element(s, tcg_op2, rm, pass, MO_64); | |
9392 | ||
9393 | switch (fpopcode) { | |
057d5f62 PM |
9394 | case 0x39: /* FMLS */ |
9395 | /* As usual for ARM, separate negation for fused multiply-add */ | |
9396 | gen_helper_vfp_negd(tcg_op1, tcg_op1); | |
9397 | /* fall through */ | |
9398 | case 0x19: /* FMLA */ | |
9399 | read_vec_element(s, tcg_res, rd, pass, MO_64); | |
9400 | gen_helper_vfp_muladdd(tcg_res, tcg_op1, tcg_op2, | |
9401 | tcg_res, fpst); | |
9402 | break; | |
845ea09a PM |
9403 | case 0x18: /* FMAXNM */ |
9404 | gen_helper_vfp_maxnumd(tcg_res, tcg_op1, tcg_op2, fpst); | |
9405 | break; | |
9406 | case 0x1a: /* FADD */ | |
9407 | gen_helper_vfp_addd(tcg_res, tcg_op1, tcg_op2, fpst); | |
9408 | break; | |
057d5f62 PM |
9409 | case 0x1b: /* FMULX */ |
9410 | gen_helper_vfp_mulxd(tcg_res, tcg_op1, tcg_op2, fpst); | |
9411 | break; | |
8908f4d1 AB |
9412 | case 0x1c: /* FCMEQ */ |
9413 | gen_helper_neon_ceq_f64(tcg_res, tcg_op1, tcg_op2, fpst); | |
9414 | break; | |
845ea09a PM |
9415 | case 0x1e: /* FMAX */ |
9416 | gen_helper_vfp_maxd(tcg_res, tcg_op1, tcg_op2, fpst); | |
9417 | break; | |
057d5f62 PM |
9418 | case 0x1f: /* FRECPS */ |
9419 | gen_helper_recpsf_f64(tcg_res, tcg_op1, tcg_op2, fpst); | |
9420 | break; | |
845ea09a PM |
9421 | case 0x38: /* FMINNM */ |
9422 | gen_helper_vfp_minnumd(tcg_res, tcg_op1, tcg_op2, fpst); | |
9423 | break; | |
9424 | case 0x3a: /* FSUB */ | |
9425 | gen_helper_vfp_subd(tcg_res, tcg_op1, tcg_op2, fpst); | |
9426 | break; | |
9427 | case 0x3e: /* FMIN */ | |
9428 | gen_helper_vfp_mind(tcg_res, tcg_op1, tcg_op2, fpst); | |
9429 | break; | |
057d5f62 PM |
9430 | case 0x3f: /* FRSQRTS */ |
9431 | gen_helper_rsqrtsf_f64(tcg_res, tcg_op1, tcg_op2, fpst); | |
9432 | break; | |
845ea09a PM |
9433 | case 0x5b: /* FMUL */ |
9434 | gen_helper_vfp_muld(tcg_res, tcg_op1, tcg_op2, fpst); | |
9435 | break; | |
8908f4d1 AB |
9436 | case 0x5c: /* FCMGE */ |
9437 | gen_helper_neon_cge_f64(tcg_res, tcg_op1, tcg_op2, fpst); | |
9438 | break; | |
057d5f62 PM |
9439 | case 0x5d: /* FACGE */ |
9440 | gen_helper_neon_acge_f64(tcg_res, tcg_op1, tcg_op2, fpst); | |
9441 | break; | |
845ea09a PM |
9442 | case 0x5f: /* FDIV */ |
9443 | gen_helper_vfp_divd(tcg_res, tcg_op1, tcg_op2, fpst); | |
9444 | break; | |
9445 | case 0x7a: /* FABD */ | |
9446 | gen_helper_vfp_subd(tcg_res, tcg_op1, tcg_op2, fpst); | |
9447 | gen_helper_vfp_absd(tcg_res, tcg_res); | |
9448 | break; | |
8908f4d1 AB |
9449 | case 0x7c: /* FCMGT */ |
9450 | gen_helper_neon_cgt_f64(tcg_res, tcg_op1, tcg_op2, fpst); | |
9451 | break; | |
057d5f62 PM |
9452 | case 0x7d: /* FACGT */ |
9453 | gen_helper_neon_acgt_f64(tcg_res, tcg_op1, tcg_op2, fpst); | |
9454 | break; | |
845ea09a PM |
9455 | default: |
9456 | g_assert_not_reached(); | |
9457 | } | |
9458 | ||
9459 | write_vec_element(s, tcg_res, rd, pass, MO_64); | |
9460 | ||
9461 | tcg_temp_free_i64(tcg_res); | |
9462 | tcg_temp_free_i64(tcg_op1); | |
9463 | tcg_temp_free_i64(tcg_op2); | |
9464 | } else { | |
9465 | /* Single */ | |
9466 | TCGv_i32 tcg_op1 = tcg_temp_new_i32(); | |
9467 | TCGv_i32 tcg_op2 = tcg_temp_new_i32(); | |
9468 | TCGv_i32 tcg_res = tcg_temp_new_i32(); | |
9469 | ||
9470 | read_vec_element_i32(s, tcg_op1, rn, pass, MO_32); | |
9471 | read_vec_element_i32(s, tcg_op2, rm, pass, MO_32); | |
9472 | ||
9473 | switch (fpopcode) { | |
057d5f62 PM |
9474 | case 0x39: /* FMLS */ |
9475 | /* As usual for ARM, separate negation for fused multiply-add */ | |
9476 | gen_helper_vfp_negs(tcg_op1, tcg_op1); | |
9477 | /* fall through */ | |
9478 | case 0x19: /* FMLA */ | |
9479 | read_vec_element_i32(s, tcg_res, rd, pass, MO_32); | |
9480 | gen_helper_vfp_muladds(tcg_res, tcg_op1, tcg_op2, | |
9481 | tcg_res, fpst); | |
9482 | break; | |
845ea09a PM |
9483 | case 0x1a: /* FADD */ |
9484 | gen_helper_vfp_adds(tcg_res, tcg_op1, tcg_op2, fpst); | |
9485 | break; | |
057d5f62 PM |
9486 | case 0x1b: /* FMULX */ |
9487 | gen_helper_vfp_mulxs(tcg_res, tcg_op1, tcg_op2, fpst); | |
9488 | break; | |
8908f4d1 AB |
9489 | case 0x1c: /* FCMEQ */ |
9490 | gen_helper_neon_ceq_f32(tcg_res, tcg_op1, tcg_op2, fpst); | |
9491 | break; | |
845ea09a PM |
9492 | case 0x1e: /* FMAX */ |
9493 | gen_helper_vfp_maxs(tcg_res, tcg_op1, tcg_op2, fpst); | |
9494 | break; | |
057d5f62 PM |
9495 | case 0x1f: /* FRECPS */ |
9496 | gen_helper_recpsf_f32(tcg_res, tcg_op1, tcg_op2, fpst); | |
9497 | break; | |
845ea09a PM |
9498 | case 0x18: /* FMAXNM */ |
9499 | gen_helper_vfp_maxnums(tcg_res, tcg_op1, tcg_op2, fpst); | |
9500 | break; | |
9501 | case 0x38: /* FMINNM */ | |
9502 | gen_helper_vfp_minnums(tcg_res, tcg_op1, tcg_op2, fpst); | |
9503 | break; | |
9504 | case 0x3a: /* FSUB */ | |
9505 | gen_helper_vfp_subs(tcg_res, tcg_op1, tcg_op2, fpst); | |
9506 | break; | |
9507 | case 0x3e: /* FMIN */ | |
9508 | gen_helper_vfp_mins(tcg_res, tcg_op1, tcg_op2, fpst); | |
9509 | break; | |
057d5f62 PM |
9510 | case 0x3f: /* FRSQRTS */ |
9511 | gen_helper_rsqrtsf_f32(tcg_res, tcg_op1, tcg_op2, fpst); | |
9512 | break; | |
845ea09a PM |
9513 | case 0x5b: /* FMUL */ |
9514 | gen_helper_vfp_muls(tcg_res, tcg_op1, tcg_op2, fpst); | |
9515 | break; | |
8908f4d1 AB |
9516 | case 0x5c: /* FCMGE */ |
9517 | gen_helper_neon_cge_f32(tcg_res, tcg_op1, tcg_op2, fpst); | |
9518 | break; | |
057d5f62 PM |
9519 | case 0x5d: /* FACGE */ |
9520 | gen_helper_neon_acge_f32(tcg_res, tcg_op1, tcg_op2, fpst); | |
9521 | break; | |
845ea09a PM |
9522 | case 0x5f: /* FDIV */ |
9523 | gen_helper_vfp_divs(tcg_res, tcg_op1, tcg_op2, fpst); | |
9524 | break; | |
9525 | case 0x7a: /* FABD */ | |
9526 | gen_helper_vfp_subs(tcg_res, tcg_op1, tcg_op2, fpst); | |
9527 | gen_helper_vfp_abss(tcg_res, tcg_res); | |
9528 | break; | |
8908f4d1 AB |
9529 | case 0x7c: /* FCMGT */ |
9530 | gen_helper_neon_cgt_f32(tcg_res, tcg_op1, tcg_op2, fpst); | |
9531 | break; | |
057d5f62 PM |
9532 | case 0x7d: /* FACGT */ |
9533 | gen_helper_neon_acgt_f32(tcg_res, tcg_op1, tcg_op2, fpst); | |
9534 | break; | |
845ea09a PM |
9535 | default: |
9536 | g_assert_not_reached(); | |
9537 | } | |
9538 | ||
9539 | if (elements == 1) { | |
9540 | /* scalar single so clear high part */ | |
9541 | TCGv_i64 tcg_tmp = tcg_temp_new_i64(); | |
9542 | ||
9543 | tcg_gen_extu_i32_i64(tcg_tmp, tcg_res); | |
9544 | write_vec_element(s, tcg_tmp, rd, pass, MO_64); | |
9545 | tcg_temp_free_i64(tcg_tmp); | |
9546 | } else { | |
9547 | write_vec_element_i32(s, tcg_res, rd, pass, MO_32); | |
9548 | } | |
9549 | ||
9550 | tcg_temp_free_i32(tcg_res); | |
9551 | tcg_temp_free_i32(tcg_op1); | |
9552 | tcg_temp_free_i32(tcg_op2); | |
9553 | } | |
9554 | } | |
9555 | ||
9556 | tcg_temp_free_ptr(fpst); | |
9557 | ||
4ff55bcb | 9558 | clear_vec_high(s, elements * (size ? 8 : 4) > 8, rd); |
845ea09a PM |
9559 | } |
9560 | ||
4ce31af4 | 9561 | /* AdvSIMD scalar three same |
384b26fb AB |
9562 | * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0 |
9563 | * +-----+---+-----------+------+---+------+--------+---+------+------+ | |
9564 | * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd | | |
9565 | * +-----+---+-----------+------+---+------+--------+---+------+------+ | |
9566 | */ | |
9567 | static void disas_simd_scalar_three_reg_same(DisasContext *s, uint32_t insn) | |
9568 | { | |
b305dba6 PM |
9569 | int rd = extract32(insn, 0, 5); |
9570 | int rn = extract32(insn, 5, 5); | |
9571 | int opcode = extract32(insn, 11, 5); | |
9572 | int rm = extract32(insn, 16, 5); | |
9573 | int size = extract32(insn, 22, 2); | |
9574 | bool u = extract32(insn, 29, 1); | |
b305dba6 PM |
9575 | TCGv_i64 tcg_rd; |
9576 | ||
9577 | if (opcode >= 0x18) { | |
9578 | /* Floating point: U, size[1] and opcode indicate operation */ | |
9579 | int fpopcode = opcode | (extract32(size, 1, 1) << 5) | (u << 6); | |
9580 | switch (fpopcode) { | |
9581 | case 0x1b: /* FMULX */ | |
b305dba6 PM |
9582 | case 0x1f: /* FRECPS */ |
9583 | case 0x3f: /* FRSQRTS */ | |
b305dba6 | 9584 | case 0x5d: /* FACGE */ |
b305dba6 | 9585 | case 0x7d: /* FACGT */ |
8908f4d1 AB |
9586 | case 0x1c: /* FCMEQ */ |
9587 | case 0x5c: /* FCMGE */ | |
9588 | case 0x7c: /* FCMGT */ | |
845ea09a PM |
9589 | case 0x7a: /* FABD */ |
9590 | break; | |
b305dba6 PM |
9591 | default: |
9592 | unallocated_encoding(s); | |
9593 | return; | |
9594 | } | |
845ea09a | 9595 | |
8c6afa6a PM |
9596 | if (!fp_access_check(s)) { |
9597 | return; | |
9598 | } | |
9599 | ||
845ea09a PM |
9600 | handle_3same_float(s, extract32(size, 0, 1), 1, fpopcode, rd, rn, rm); |
9601 | return; | |
b305dba6 PM |
9602 | } |
9603 | ||
9604 | switch (opcode) { | |
9605 | case 0x1: /* SQADD, UQADD */ | |
9606 | case 0x5: /* SQSUB, UQSUB */ | |
c0b2b5fa PM |
9607 | case 0x9: /* SQSHL, UQSHL */ |
9608 | case 0xb: /* SQRSHL, UQRSHL */ | |
9609 | break; | |
6d9571f7 PM |
9610 | case 0x8: /* SSHL, USHL */ |
9611 | case 0xa: /* SRSHL, URSHL */ | |
b305dba6 PM |
9612 | case 0x6: /* CMGT, CMHI */ |
9613 | case 0x7: /* CMGE, CMHS */ | |
9614 | case 0x11: /* CMTST, CMEQ */ | |
9615 | case 0x10: /* ADD, SUB (vector) */ | |
9616 | if (size != 3) { | |
9617 | unallocated_encoding(s); | |
9618 | return; | |
9619 | } | |
9620 | break; | |
b305dba6 PM |
9621 | case 0x16: /* SQDMULH, SQRDMULH (vector) */ |
9622 | if (size != 1 && size != 2) { | |
9623 | unallocated_encoding(s); | |
9624 | return; | |
9625 | } | |
c0b2b5fa | 9626 | break; |
b305dba6 PM |
9627 | default: |
9628 | unallocated_encoding(s); | |
9629 | return; | |
9630 | } | |
9631 | ||
8c6afa6a PM |
9632 | if (!fp_access_check(s)) { |
9633 | return; | |
9634 | } | |
9635 | ||
b305dba6 PM |
9636 | tcg_rd = tcg_temp_new_i64(); |
9637 | ||
c0b2b5fa PM |
9638 | if (size == 3) { |
9639 | TCGv_i64 tcg_rn = read_fp_dreg(s, rn); | |
9640 | TCGv_i64 tcg_rm = read_fp_dreg(s, rm); | |
9641 | ||
9642 | handle_3same_64(s, opcode, u, tcg_rd, tcg_rn, tcg_rm); | |
9643 | tcg_temp_free_i64(tcg_rn); | |
9644 | tcg_temp_free_i64(tcg_rm); | |
9645 | } else { | |
9646 | /* Do a single operation on the lowest element in the vector. | |
9647 | * We use the standard Neon helpers and rely on 0 OP 0 == 0 with | |
9648 | * no side effects for all these operations. | |
9649 | * OPTME: special-purpose helpers would avoid doing some | |
9650 | * unnecessary work in the helper for the 8 and 16 bit cases. | |
9651 | */ | |
9652 | NeonGenTwoOpEnvFn *genenvfn; | |
9653 | TCGv_i32 tcg_rn = tcg_temp_new_i32(); | |
9654 | TCGv_i32 tcg_rm = tcg_temp_new_i32(); | |
9655 | TCGv_i32 tcg_rd32 = tcg_temp_new_i32(); | |
9656 | ||
9657 | read_vec_element_i32(s, tcg_rn, rn, 0, size); | |
9658 | read_vec_element_i32(s, tcg_rm, rm, 0, size); | |
9659 | ||
9660 | switch (opcode) { | |
9661 | case 0x1: /* SQADD, UQADD */ | |
9662 | { | |
9663 | static NeonGenTwoOpEnvFn * const fns[3][2] = { | |
9664 | { gen_helper_neon_qadd_s8, gen_helper_neon_qadd_u8 }, | |
9665 | { gen_helper_neon_qadd_s16, gen_helper_neon_qadd_u16 }, | |
9666 | { gen_helper_neon_qadd_s32, gen_helper_neon_qadd_u32 }, | |
9667 | }; | |
9668 | genenvfn = fns[size][u]; | |
9669 | break; | |
9670 | } | |
9671 | case 0x5: /* SQSUB, UQSUB */ | |
9672 | { | |
9673 | static NeonGenTwoOpEnvFn * const fns[3][2] = { | |
9674 | { gen_helper_neon_qsub_s8, gen_helper_neon_qsub_u8 }, | |
9675 | { gen_helper_neon_qsub_s16, gen_helper_neon_qsub_u16 }, | |
9676 | { gen_helper_neon_qsub_s32, gen_helper_neon_qsub_u32 }, | |
9677 | }; | |
9678 | genenvfn = fns[size][u]; | |
9679 | break; | |
9680 | } | |
9681 | case 0x9: /* SQSHL, UQSHL */ | |
9682 | { | |
9683 | static NeonGenTwoOpEnvFn * const fns[3][2] = { | |
9684 | { gen_helper_neon_qshl_s8, gen_helper_neon_qshl_u8 }, | |
9685 | { gen_helper_neon_qshl_s16, gen_helper_neon_qshl_u16 }, | |
9686 | { gen_helper_neon_qshl_s32, gen_helper_neon_qshl_u32 }, | |
9687 | }; | |
9688 | genenvfn = fns[size][u]; | |
9689 | break; | |
9690 | } | |
9691 | case 0xb: /* SQRSHL, UQRSHL */ | |
9692 | { | |
9693 | static NeonGenTwoOpEnvFn * const fns[3][2] = { | |
9694 | { gen_helper_neon_qrshl_s8, gen_helper_neon_qrshl_u8 }, | |
9695 | { gen_helper_neon_qrshl_s16, gen_helper_neon_qrshl_u16 }, | |
9696 | { gen_helper_neon_qrshl_s32, gen_helper_neon_qrshl_u32 }, | |
9697 | }; | |
9698 | genenvfn = fns[size][u]; | |
9699 | break; | |
9700 | } | |
9701 | case 0x16: /* SQDMULH, SQRDMULH */ | |
9702 | { | |
9703 | static NeonGenTwoOpEnvFn * const fns[2][2] = { | |
9704 | { gen_helper_neon_qdmulh_s16, gen_helper_neon_qrdmulh_s16 }, | |
9705 | { gen_helper_neon_qdmulh_s32, gen_helper_neon_qrdmulh_s32 }, | |
9706 | }; | |
9707 | assert(size == 1 || size == 2); | |
9708 | genenvfn = fns[size - 1][u]; | |
9709 | break; | |
9710 | } | |
9711 | default: | |
9712 | g_assert_not_reached(); | |
9713 | } | |
9714 | ||
9715 | genenvfn(tcg_rd32, cpu_env, tcg_rn, tcg_rm); | |
9716 | tcg_gen_extu_i32_i64(tcg_rd, tcg_rd32); | |
9717 | tcg_temp_free_i32(tcg_rd32); | |
9718 | tcg_temp_free_i32(tcg_rn); | |
9719 | tcg_temp_free_i32(tcg_rm); | |
9720 | } | |
b305dba6 PM |
9721 | |
9722 | write_fp_dreg(s, rd, tcg_rd); | |
9723 | ||
b305dba6 | 9724 | tcg_temp_free_i64(tcg_rd); |
384b26fb AB |
9725 | } |
9726 | ||
7c93b774 AB |
9727 | /* AdvSIMD scalar three same FP16 |
9728 | * 31 30 29 28 24 23 22 21 20 16 15 14 13 11 10 9 5 4 0 | |
9729 | * +-----+---+-----------+---+-----+------+-----+--------+---+----+----+ | |
9730 | * | 0 1 | U | 1 1 1 1 0 | a | 1 0 | Rm | 0 0 | opcode | 1 | Rn | Rd | | |
9731 | * +-----+---+-----------+---+-----+------+-----+--------+---+----+----+ | |
9732 | * v: 0101 1110 0100 0000 0000 0100 0000 0000 => 5e400400 | |
9733 | * m: 1101 1111 0110 0000 1100 0100 0000 0000 => df60c400 | |
9734 | */ | |
9735 | static void disas_simd_scalar_three_reg_same_fp16(DisasContext *s, | |
9736 | uint32_t insn) | |
9737 | { | |
9738 | int rd = extract32(insn, 0, 5); | |
9739 | int rn = extract32(insn, 5, 5); | |
9740 | int opcode = extract32(insn, 11, 3); | |
9741 | int rm = extract32(insn, 16, 5); | |
9742 | bool u = extract32(insn, 29, 1); | |
9743 | bool a = extract32(insn, 23, 1); | |
9744 | int fpopcode = opcode | (a << 3) | (u << 4); | |
9745 | TCGv_ptr fpst; | |
9746 | TCGv_i32 tcg_op1; | |
9747 | TCGv_i32 tcg_op2; | |
9748 | TCGv_i32 tcg_res; | |
9749 | ||
9750 | switch (fpopcode) { | |
9751 | case 0x03: /* FMULX */ | |
9752 | case 0x04: /* FCMEQ (reg) */ | |
9753 | case 0x07: /* FRECPS */ | |
9754 | case 0x0f: /* FRSQRTS */ | |
9755 | case 0x14: /* FCMGE (reg) */ | |
9756 | case 0x15: /* FACGE */ | |
9757 | case 0x1a: /* FABD */ | |
9758 | case 0x1c: /* FCMGT (reg) */ | |
9759 | case 0x1d: /* FACGT */ | |
9760 | break; | |
9761 | default: | |
9762 | unallocated_encoding(s); | |
9763 | return; | |
9764 | } | |
9765 | ||
5763190f | 9766 | if (!dc_isar_feature(aa64_fp16, s)) { |
7c93b774 AB |
9767 | unallocated_encoding(s); |
9768 | } | |
9769 | ||
9770 | if (!fp_access_check(s)) { | |
9771 | return; | |
9772 | } | |
9773 | ||
cdfb22bb | 9774 | fpst = fpstatus_ptr(FPST_FPCR_F16); |
7c93b774 | 9775 | |
3d99d931 RH |
9776 | tcg_op1 = read_fp_hreg(s, rn); |
9777 | tcg_op2 = read_fp_hreg(s, rm); | |
7c93b774 AB |
9778 | tcg_res = tcg_temp_new_i32(); |
9779 | ||
7c93b774 AB |
9780 | switch (fpopcode) { |
9781 | case 0x03: /* FMULX */ | |
9782 | gen_helper_advsimd_mulxh(tcg_res, tcg_op1, tcg_op2, fpst); | |
9783 | break; | |
9784 | case 0x04: /* FCMEQ (reg) */ | |
9785 | gen_helper_advsimd_ceq_f16(tcg_res, tcg_op1, tcg_op2, fpst); | |
9786 | break; | |
9787 | case 0x07: /* FRECPS */ | |
9788 | gen_helper_recpsf_f16(tcg_res, tcg_op1, tcg_op2, fpst); | |
9789 | break; | |
9790 | case 0x0f: /* FRSQRTS */ | |
9791 | gen_helper_rsqrtsf_f16(tcg_res, tcg_op1, tcg_op2, fpst); | |
9792 | break; | |
9793 | case 0x14: /* FCMGE (reg) */ | |
9794 | gen_helper_advsimd_cge_f16(tcg_res, tcg_op1, tcg_op2, fpst); | |
9795 | break; | |
9796 | case 0x15: /* FACGE */ | |
9797 | gen_helper_advsimd_acge_f16(tcg_res, tcg_op1, tcg_op2, fpst); | |
9798 | break; | |
9799 | case 0x1a: /* FABD */ | |
9800 | gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst); | |
9801 | tcg_gen_andi_i32(tcg_res, tcg_res, 0x7fff); | |
9802 | break; | |
9803 | case 0x1c: /* FCMGT (reg) */ | |
9804 | gen_helper_advsimd_cgt_f16(tcg_res, tcg_op1, tcg_op2, fpst); | |
9805 | break; | |
9806 | case 0x1d: /* FACGT */ | |
9807 | gen_helper_advsimd_acgt_f16(tcg_res, tcg_op1, tcg_op2, fpst); | |
9808 | break; | |
9809 | default: | |
9810 | g_assert_not_reached(); | |
9811 | } | |
9812 | ||
9813 | write_fp_sreg(s, rd, tcg_res); | |
9814 | ||
9815 | ||
9816 | tcg_temp_free_i32(tcg_res); | |
9817 | tcg_temp_free_i32(tcg_op1); | |
9818 | tcg_temp_free_i32(tcg_op2); | |
9819 | tcg_temp_free_ptr(fpst); | |
9820 | } | |
9821 | ||
d9061ec3 RH |
9822 | /* AdvSIMD scalar three same extra |
9823 | * 31 30 29 28 24 23 22 21 20 16 15 14 11 10 9 5 4 0 | |
9824 | * +-----+---+-----------+------+---+------+---+--------+---+----+----+ | |
9825 | * | 0 1 | U | 1 1 1 1 0 | size | 0 | Rm | 1 | opcode | 1 | Rn | Rd | | |
9826 | * +-----+---+-----------+------+---+------+---+--------+---+----+----+ | |
9827 | */ | |
9828 | static void disas_simd_scalar_three_reg_same_extra(DisasContext *s, | |
9829 | uint32_t insn) | |
9830 | { | |
9831 | int rd = extract32(insn, 0, 5); | |
9832 | int rn = extract32(insn, 5, 5); | |
9833 | int opcode = extract32(insn, 11, 4); | |
9834 | int rm = extract32(insn, 16, 5); | |
9835 | int size = extract32(insn, 22, 2); | |
9836 | bool u = extract32(insn, 29, 1); | |
9837 | TCGv_i32 ele1, ele2, ele3; | |
9838 | TCGv_i64 res; | |
962fcbf2 | 9839 | bool feature; |
d9061ec3 RH |
9840 | |
9841 | switch (u * 16 + opcode) { | |
9842 | case 0x10: /* SQRDMLAH (vector) */ | |
9843 | case 0x11: /* SQRDMLSH (vector) */ | |
9844 | if (size != 1 && size != 2) { | |
9845 | unallocated_encoding(s); | |
9846 | return; | |
9847 | } | |
962fcbf2 | 9848 | feature = dc_isar_feature(aa64_rdm, s); |
d9061ec3 RH |
9849 | break; |
9850 | default: | |
9851 | unallocated_encoding(s); | |
9852 | return; | |
9853 | } | |
962fcbf2 | 9854 | if (!feature) { |
d9061ec3 RH |
9855 | unallocated_encoding(s); |
9856 | return; | |
9857 | } | |
9858 | if (!fp_access_check(s)) { | |
9859 | return; | |
9860 | } | |
9861 | ||
9862 | /* Do a single operation on the lowest element in the vector. | |
9863 | * We use the standard Neon helpers and rely on 0 OP 0 == 0 | |
9864 | * with no side effects for all these operations. | |
9865 | * OPTME: special-purpose helpers would avoid doing some | |
9866 | * unnecessary work in the helper for the 16 bit cases. | |
9867 | */ | |
9868 | ele1 = tcg_temp_new_i32(); | |
9869 | ele2 = tcg_temp_new_i32(); | |
9870 | ele3 = tcg_temp_new_i32(); | |
9871 | ||
9872 | read_vec_element_i32(s, ele1, rn, 0, size); | |
9873 | read_vec_element_i32(s, ele2, rm, 0, size); | |
9874 | read_vec_element_i32(s, ele3, rd, 0, size); | |
9875 | ||
9876 | switch (opcode) { | |
9877 | case 0x0: /* SQRDMLAH */ | |
9878 | if (size == 1) { | |
9879 | gen_helper_neon_qrdmlah_s16(ele3, cpu_env, ele1, ele2, ele3); | |
9880 | } else { | |
9881 | gen_helper_neon_qrdmlah_s32(ele3, cpu_env, ele1, ele2, ele3); | |
9882 | } | |
9883 | break; | |
9884 | case 0x1: /* SQRDMLSH */ | |
9885 | if (size == 1) { | |
9886 | gen_helper_neon_qrdmlsh_s16(ele3, cpu_env, ele1, ele2, ele3); | |
9887 | } else { | |
9888 | gen_helper_neon_qrdmlsh_s32(ele3, cpu_env, ele1, ele2, ele3); | |
9889 | } | |
9890 | break; | |
9891 | default: | |
9892 | g_assert_not_reached(); | |
9893 | } | |
9894 | tcg_temp_free_i32(ele1); | |
9895 | tcg_temp_free_i32(ele2); | |
9896 | ||
9897 | res = tcg_temp_new_i64(); | |
9898 | tcg_gen_extu_i32_i64(res, ele3); | |
9899 | tcg_temp_free_i32(ele3); | |
9900 | ||
9901 | write_fp_dreg(s, rd, res); | |
9902 | tcg_temp_free_i64(res); | |
9903 | } | |
9904 | ||
effa8e06 | 9905 | static void handle_2misc_64(DisasContext *s, int opcode, bool u, |
04c7c6c2 PM |
9906 | TCGv_i64 tcg_rd, TCGv_i64 tcg_rn, |
9907 | TCGv_i32 tcg_rmode, TCGv_ptr tcg_fpstatus) | |
effa8e06 PM |
9908 | { |
9909 | /* Handle 64->64 opcodes which are shared between the scalar and | |
9910 | * vector 2-reg-misc groups. We cover every integer opcode where size == 3 | |
f93d0138 | 9911 | * is valid in either group and also the double-precision fp ops. |
04c7c6c2 PM |
9912 | * The caller only need provide tcg_rmode and tcg_fpstatus if the op |
9913 | * requires them. | |
effa8e06 PM |
9914 | */ |
9915 | TCGCond cond; | |
9916 | ||
9917 | switch (opcode) { | |
b05c3068 AB |
9918 | case 0x4: /* CLS, CLZ */ |
9919 | if (u) { | |
7539a012 | 9920 | tcg_gen_clzi_i64(tcg_rd, tcg_rn, 64); |
b05c3068 | 9921 | } else { |
bc21dbcc | 9922 | tcg_gen_clrsb_i64(tcg_rd, tcg_rn); |
b05c3068 AB |
9923 | } |
9924 | break; | |
86cbc418 PM |
9925 | case 0x5: /* NOT */ |
9926 | /* This opcode is shared with CNT and RBIT but we have earlier | |
9927 | * enforced that size == 3 if and only if this is the NOT insn. | |
9928 | */ | |
9929 | tcg_gen_not_i64(tcg_rd, tcg_rn); | |
9930 | break; | |
0a79bc87 AB |
9931 | case 0x7: /* SQABS, SQNEG */ |
9932 | if (u) { | |
9933 | gen_helper_neon_qneg_s64(tcg_rd, cpu_env, tcg_rn); | |
9934 | } else { | |
9935 | gen_helper_neon_qabs_s64(tcg_rd, cpu_env, tcg_rn); | |
9936 | } | |
9937 | break; | |
effa8e06 PM |
9938 | case 0xa: /* CMLT */ |
9939 | /* 64 bit integer comparison against zero, result is | |
9940 | * test ? (2^64 - 1) : 0. We implement via setcond(!test) and | |
9941 | * subtracting 1. | |
9942 | */ | |
9943 | cond = TCG_COND_LT; | |
9944 | do_cmop: | |
9945 | tcg_gen_setcondi_i64(cond, tcg_rd, tcg_rn, 0); | |
9946 | tcg_gen_neg_i64(tcg_rd, tcg_rd); | |
9947 | break; | |
9948 | case 0x8: /* CMGT, CMGE */ | |
9949 | cond = u ? TCG_COND_GE : TCG_COND_GT; | |
9950 | goto do_cmop; | |
9951 | case 0x9: /* CMEQ, CMLE */ | |
9952 | cond = u ? TCG_COND_LE : TCG_COND_EQ; | |
9953 | goto do_cmop; | |
9954 | case 0xb: /* ABS, NEG */ | |
9955 | if (u) { | |
9956 | tcg_gen_neg_i64(tcg_rd, tcg_rn); | |
9957 | } else { | |
4e027a71 | 9958 | tcg_gen_abs_i64(tcg_rd, tcg_rn); |
effa8e06 PM |
9959 | } |
9960 | break; | |
f93d0138 PM |
9961 | case 0x2f: /* FABS */ |
9962 | gen_helper_vfp_absd(tcg_rd, tcg_rn); | |
9963 | break; | |
9964 | case 0x6f: /* FNEG */ | |
9965 | gen_helper_vfp_negd(tcg_rd, tcg_rn); | |
9966 | break; | |
f612537e AB |
9967 | case 0x7f: /* FSQRT */ |
9968 | gen_helper_vfp_sqrtd(tcg_rd, tcg_rn, cpu_env); | |
9969 | break; | |
04c7c6c2 PM |
9970 | case 0x1a: /* FCVTNS */ |
9971 | case 0x1b: /* FCVTMS */ | |
9972 | case 0x1c: /* FCVTAS */ | |
9973 | case 0x3a: /* FCVTPS */ | |
9974 | case 0x3b: /* FCVTZS */ | |
9975 | { | |
9976 | TCGv_i32 tcg_shift = tcg_const_i32(0); | |
9977 | gen_helper_vfp_tosqd(tcg_rd, tcg_rn, tcg_shift, tcg_fpstatus); | |
9978 | tcg_temp_free_i32(tcg_shift); | |
9979 | break; | |
9980 | } | |
9981 | case 0x5a: /* FCVTNU */ | |
9982 | case 0x5b: /* FCVTMU */ | |
9983 | case 0x5c: /* FCVTAU */ | |
9984 | case 0x7a: /* FCVTPU */ | |
9985 | case 0x7b: /* FCVTZU */ | |
9986 | { | |
9987 | TCGv_i32 tcg_shift = tcg_const_i32(0); | |
9988 | gen_helper_vfp_touqd(tcg_rd, tcg_rn, tcg_shift, tcg_fpstatus); | |
9989 | tcg_temp_free_i32(tcg_shift); | |
9990 | break; | |
9991 | } | |
03df01ed PM |
9992 | case 0x18: /* FRINTN */ |
9993 | case 0x19: /* FRINTM */ | |
9994 | case 0x38: /* FRINTP */ | |
9995 | case 0x39: /* FRINTZ */ | |
9996 | case 0x58: /* FRINTA */ | |
9997 | case 0x79: /* FRINTI */ | |
9998 | gen_helper_rintd(tcg_rd, tcg_rn, tcg_fpstatus); | |
9999 | break; | |
10000 | case 0x59: /* FRINTX */ | |
10001 | gen_helper_rintd_exact(tcg_rd, tcg_rn, tcg_fpstatus); | |
10002 | break; | |
6bea2563 RH |
10003 | case 0x1e: /* FRINT32Z */ |
10004 | case 0x5e: /* FRINT32X */ | |
10005 | gen_helper_frint32_d(tcg_rd, tcg_rn, tcg_fpstatus); | |
10006 | break; | |
10007 | case 0x1f: /* FRINT64Z */ | |
10008 | case 0x5f: /* FRINT64X */ | |
10009 | gen_helper_frint64_d(tcg_rd, tcg_rn, tcg_fpstatus); | |
10010 | break; | |
effa8e06 PM |
10011 | default: |
10012 | g_assert_not_reached(); | |
10013 | } | |
10014 | } | |
10015 | ||
8908f4d1 AB |
10016 | static void handle_2misc_fcmp_zero(DisasContext *s, int opcode, |
10017 | bool is_scalar, bool is_u, bool is_q, | |
10018 | int size, int rn, int rd) | |
10019 | { | |
7d4dd1a7 | 10020 | bool is_double = (size == MO_64); |
8c6afa6a PM |
10021 | TCGv_ptr fpst; |
10022 | ||
10023 | if (!fp_access_check(s)) { | |
10024 | return; | |
10025 | } | |
10026 | ||
cdfb22bb | 10027 | fpst = fpstatus_ptr(size == MO_16 ? FPST_FPCR_F16 : FPST_FPCR); |
8908f4d1 AB |
10028 | |
10029 | if (is_double) { | |
10030 | TCGv_i64 tcg_op = tcg_temp_new_i64(); | |
10031 | TCGv_i64 tcg_zero = tcg_const_i64(0); | |
10032 | TCGv_i64 tcg_res = tcg_temp_new_i64(); | |
5de3fd04 | 10033 | NeonGenTwoDoubleOpFn *genfn; |
8908f4d1 AB |
10034 | bool swap = false; |
10035 | int pass; | |
10036 | ||
10037 | switch (opcode) { | |
10038 | case 0x2e: /* FCMLT (zero) */ | |
10039 | swap = true; | |
10040 | /* fallthrough */ | |
10041 | case 0x2c: /* FCMGT (zero) */ | |
10042 | genfn = gen_helper_neon_cgt_f64; | |
10043 | break; | |
10044 | case 0x2d: /* FCMEQ (zero) */ | |
10045 | genfn = gen_helper_neon_ceq_f64; | |
10046 | break; | |
10047 | case 0x6d: /* FCMLE (zero) */ | |
10048 | swap = true; | |
10049 | /* fall through */ | |
10050 | case 0x6c: /* FCMGE (zero) */ | |
10051 | genfn = gen_helper_neon_cge_f64; | |
10052 | break; | |
10053 | default: | |
10054 | g_assert_not_reached(); | |
10055 | } | |
10056 | ||
10057 | for (pass = 0; pass < (is_scalar ? 1 : 2); pass++) { | |
10058 | read_vec_element(s, tcg_op, rn, pass, MO_64); | |
10059 | if (swap) { | |
10060 | genfn(tcg_res, tcg_zero, tcg_op, fpst); | |
10061 | } else { | |
10062 | genfn(tcg_res, tcg_op, tcg_zero, fpst); | |
10063 | } | |
10064 | write_vec_element(s, tcg_res, rd, pass, MO_64); | |
10065 | } | |
8908f4d1 AB |
10066 | tcg_temp_free_i64(tcg_res); |
10067 | tcg_temp_free_i64(tcg_zero); | |
10068 | tcg_temp_free_i64(tcg_op); | |
4ff55bcb RH |
10069 | |
10070 | clear_vec_high(s, !is_scalar, rd); | |
8908f4d1 AB |
10071 | } else { |
10072 | TCGv_i32 tcg_op = tcg_temp_new_i32(); | |
10073 | TCGv_i32 tcg_zero = tcg_const_i32(0); | |
10074 | TCGv_i32 tcg_res = tcg_temp_new_i32(); | |
5de3fd04 | 10075 | NeonGenTwoSingleOpFn *genfn; |
8908f4d1 AB |
10076 | bool swap = false; |
10077 | int pass, maxpasses; | |
10078 | ||
7d4dd1a7 AB |
10079 | if (size == MO_16) { |
10080 | switch (opcode) { | |
10081 | case 0x2e: /* FCMLT (zero) */ | |
10082 | swap = true; | |
10083 | /* fall through */ | |
10084 | case 0x2c: /* FCMGT (zero) */ | |
10085 | genfn = gen_helper_advsimd_cgt_f16; | |
10086 | break; | |
10087 | case 0x2d: /* FCMEQ (zero) */ | |
10088 | genfn = gen_helper_advsimd_ceq_f16; | |
10089 | break; | |
10090 | case 0x6d: /* FCMLE (zero) */ | |
10091 | swap = true; | |
10092 | /* fall through */ | |
10093 | case 0x6c: /* FCMGE (zero) */ | |
10094 | genfn = gen_helper_advsimd_cge_f16; | |
10095 | break; | |
10096 | default: | |
10097 | g_assert_not_reached(); | |
10098 | } | |
10099 | } else { | |
10100 | switch (opcode) { | |
10101 | case 0x2e: /* FCMLT (zero) */ | |
10102 | swap = true; | |
10103 | /* fall through */ | |
10104 | case 0x2c: /* FCMGT (zero) */ | |
10105 | genfn = gen_helper_neon_cgt_f32; | |
10106 | break; | |
10107 | case 0x2d: /* FCMEQ (zero) */ | |
10108 | genfn = gen_helper_neon_ceq_f32; | |
10109 | break; | |
10110 | case 0x6d: /* FCMLE (zero) */ | |
10111 | swap = true; | |
10112 | /* fall through */ | |
10113 | case 0x6c: /* FCMGE (zero) */ | |
10114 | genfn = gen_helper_neon_cge_f32; | |
10115 | break; | |
10116 | default: | |
10117 | g_assert_not_reached(); | |
10118 | } | |
8908f4d1 AB |
10119 | } |
10120 | ||
10121 | if (is_scalar) { | |
10122 | maxpasses = 1; | |
10123 | } else { | |
7d4dd1a7 AB |
10124 | int vector_size = 8 << is_q; |
10125 | maxpasses = vector_size >> size; | |
8908f4d1 AB |
10126 | } |
10127 | ||
10128 | for (pass = 0; pass < maxpasses; pass++) { | |
7d4dd1a7 | 10129 | read_vec_element_i32(s, tcg_op, rn, pass, size); |
8908f4d1 AB |
10130 | if (swap) { |
10131 | genfn(tcg_res, tcg_zero, tcg_op, fpst); | |
10132 | } else { | |
10133 | genfn(tcg_res, tcg_op, tcg_zero, fpst); | |
10134 | } | |
10135 | if (is_scalar) { | |
10136 | write_fp_sreg(s, rd, tcg_res); | |
10137 | } else { | |
7d4dd1a7 | 10138 | write_vec_element_i32(s, tcg_res, rd, pass, size); |
8908f4d1 AB |
10139 | } |
10140 | } | |
10141 | tcg_temp_free_i32(tcg_res); | |
10142 | tcg_temp_free_i32(tcg_zero); | |
10143 | tcg_temp_free_i32(tcg_op); | |
4ff55bcb RH |
10144 | if (!is_scalar) { |
10145 | clear_vec_high(s, is_q, rd); | |
8908f4d1 AB |
10146 | } |
10147 | } | |
10148 | ||
10149 | tcg_temp_free_ptr(fpst); | |
10150 | } | |
10151 | ||
8f0c6758 AB |
10152 | static void handle_2misc_reciprocal(DisasContext *s, int opcode, |
10153 | bool is_scalar, bool is_u, bool is_q, | |
10154 | int size, int rn, int rd) | |
10155 | { | |
10156 | bool is_double = (size == 3); | |
cdfb22bb | 10157 | TCGv_ptr fpst = fpstatus_ptr(FPST_FPCR); |
8f0c6758 AB |
10158 | |
10159 | if (is_double) { | |
10160 | TCGv_i64 tcg_op = tcg_temp_new_i64(); | |
10161 | TCGv_i64 tcg_res = tcg_temp_new_i64(); | |
10162 | int pass; | |
10163 | ||
10164 | for (pass = 0; pass < (is_scalar ? 1 : 2); pass++) { | |
10165 | read_vec_element(s, tcg_op, rn, pass, MO_64); | |
10166 | switch (opcode) { | |
b6d4443a AB |
10167 | case 0x3d: /* FRECPE */ |
10168 | gen_helper_recpe_f64(tcg_res, tcg_op, fpst); | |
10169 | break; | |
8f0c6758 AB |
10170 | case 0x3f: /* FRECPX */ |
10171 | gen_helper_frecpx_f64(tcg_res, tcg_op, fpst); | |
10172 | break; | |
c2fb418e AB |
10173 | case 0x7d: /* FRSQRTE */ |
10174 | gen_helper_rsqrte_f64(tcg_res, tcg_op, fpst); | |
10175 | break; | |
8f0c6758 AB |
10176 | default: |
10177 | g_assert_not_reached(); | |
10178 | } | |
10179 | write_vec_element(s, tcg_res, rd, pass, MO_64); | |
10180 | } | |
8f0c6758 AB |
10181 | tcg_temp_free_i64(tcg_res); |
10182 | tcg_temp_free_i64(tcg_op); | |
4ff55bcb | 10183 | clear_vec_high(s, !is_scalar, rd); |
8f0c6758 AB |
10184 | } else { |
10185 | TCGv_i32 tcg_op = tcg_temp_new_i32(); | |
10186 | TCGv_i32 tcg_res = tcg_temp_new_i32(); | |
10187 | int pass, maxpasses; | |
10188 | ||
10189 | if (is_scalar) { | |
10190 | maxpasses = 1; | |
10191 | } else { | |
10192 | maxpasses = is_q ? 4 : 2; | |
10193 | } | |
10194 | ||
10195 | for (pass = 0; pass < maxpasses; pass++) { | |
10196 | read_vec_element_i32(s, tcg_op, rn, pass, MO_32); | |
10197 | ||
10198 | switch (opcode) { | |
b6d4443a | 10199 | case 0x3c: /* URECPE */ |
fe6fb4be | 10200 | gen_helper_recpe_u32(tcg_res, tcg_op); |
b6d4443a AB |
10201 | break; |
10202 | case 0x3d: /* FRECPE */ | |
10203 | gen_helper_recpe_f32(tcg_res, tcg_op, fpst); | |
10204 | break; | |
8f0c6758 AB |
10205 | case 0x3f: /* FRECPX */ |
10206 | gen_helper_frecpx_f32(tcg_res, tcg_op, fpst); | |
10207 | break; | |
c2fb418e AB |
10208 | case 0x7d: /* FRSQRTE */ |
10209 | gen_helper_rsqrte_f32(tcg_res, tcg_op, fpst); | |
10210 | break; | |
8f0c6758 AB |
10211 | default: |
10212 | g_assert_not_reached(); | |
10213 | } | |
10214 | ||
10215 | if (is_scalar) { | |
10216 | write_fp_sreg(s, rd, tcg_res); | |
10217 | } else { | |
10218 | write_vec_element_i32(s, tcg_res, rd, pass, MO_32); | |
10219 | } | |
10220 | } | |
10221 | tcg_temp_free_i32(tcg_res); | |
10222 | tcg_temp_free_i32(tcg_op); | |
4ff55bcb RH |
10223 | if (!is_scalar) { |
10224 | clear_vec_high(s, is_q, rd); | |
8f0c6758 AB |
10225 | } |
10226 | } | |
10227 | tcg_temp_free_ptr(fpst); | |
10228 | } | |
10229 | ||
5201c136 AB |
10230 | static void handle_2misc_narrow(DisasContext *s, bool scalar, |
10231 | int opcode, bool u, bool is_q, | |
8b092ca9 AB |
10232 | int size, int rn, int rd) |
10233 | { | |
10234 | /* Handle 2-reg-misc ops which are narrowing (so each 2*size element | |
10235 | * in the source becomes a size element in the destination). | |
10236 | */ | |
10237 | int pass; | |
10238 | TCGv_i32 tcg_res[2]; | |
10239 | int destelt = is_q ? 2 : 0; | |
5201c136 | 10240 | int passes = scalar ? 1 : 2; |
8b092ca9 | 10241 | |
5201c136 AB |
10242 | if (scalar) { |
10243 | tcg_res[1] = tcg_const_i32(0); | |
10244 | } | |
10245 | ||
10246 | for (pass = 0; pass < passes; pass++) { | |
8b092ca9 AB |
10247 | TCGv_i64 tcg_op = tcg_temp_new_i64(); |
10248 | NeonGenNarrowFn *genfn = NULL; | |
10249 | NeonGenNarrowEnvFn *genenvfn = NULL; | |
10250 | ||
5201c136 AB |
10251 | if (scalar) { |
10252 | read_vec_element(s, tcg_op, rn, pass, size + 1); | |
10253 | } else { | |
10254 | read_vec_element(s, tcg_op, rn, pass, MO_64); | |
10255 | } | |
8b092ca9 AB |
10256 | tcg_res[pass] = tcg_temp_new_i32(); |
10257 | ||
10258 | switch (opcode) { | |
10259 | case 0x12: /* XTN, SQXTUN */ | |
10260 | { | |
10261 | static NeonGenNarrowFn * const xtnfns[3] = { | |
10262 | gen_helper_neon_narrow_u8, | |
10263 | gen_helper_neon_narrow_u16, | |
ecc7b3aa | 10264 | tcg_gen_extrl_i64_i32, |
8b092ca9 AB |
10265 | }; |
10266 | static NeonGenNarrowEnvFn * const sqxtunfns[3] = { | |
10267 | gen_helper_neon_unarrow_sat8, | |
10268 | gen_helper_neon_unarrow_sat16, | |
10269 | gen_helper_neon_unarrow_sat32, | |
10270 | }; | |
10271 | if (u) { | |
10272 | genenvfn = sqxtunfns[size]; | |
10273 | } else { | |
10274 | genfn = xtnfns[size]; | |
10275 | } | |
10276 | break; | |
10277 | } | |
10278 | case 0x14: /* SQXTN, UQXTN */ | |
10279 | { | |
10280 | static NeonGenNarrowEnvFn * const fns[3][2] = { | |
10281 | { gen_helper_neon_narrow_sat_s8, | |
10282 | gen_helper_neon_narrow_sat_u8 }, | |
10283 | { gen_helper_neon_narrow_sat_s16, | |
10284 | gen_helper_neon_narrow_sat_u16 }, | |
10285 | { gen_helper_neon_narrow_sat_s32, | |
10286 | gen_helper_neon_narrow_sat_u32 }, | |
10287 | }; | |
10288 | genenvfn = fns[size][u]; | |
10289 | break; | |
10290 | } | |
10291 | case 0x16: /* FCVTN, FCVTN2 */ | |
10292 | /* 32 bit to 16 bit or 64 bit to 32 bit float conversion */ | |
10293 | if (size == 2) { | |
10294 | gen_helper_vfp_fcvtsd(tcg_res[pass], tcg_op, cpu_env); | |
10295 | } else { | |
10296 | TCGv_i32 tcg_lo = tcg_temp_new_i32(); | |
10297 | TCGv_i32 tcg_hi = tcg_temp_new_i32(); | |
cdfb22bb | 10298 | TCGv_ptr fpst = fpstatus_ptr(FPST_FPCR); |
486624fc AB |
10299 | TCGv_i32 ahp = get_ahp_flag(); |
10300 | ||
7cb36e18 | 10301 | tcg_gen_extr_i64_i32(tcg_lo, tcg_hi, tcg_op); |
486624fc AB |
10302 | gen_helper_vfp_fcvt_f32_to_f16(tcg_lo, tcg_lo, fpst, ahp); |
10303 | gen_helper_vfp_fcvt_f32_to_f16(tcg_hi, tcg_hi, fpst, ahp); | |
8b092ca9 AB |
10304 | tcg_gen_deposit_i32(tcg_res[pass], tcg_lo, tcg_hi, 16, 16); |
10305 | tcg_temp_free_i32(tcg_lo); | |
10306 | tcg_temp_free_i32(tcg_hi); | |
486624fc AB |
10307 | tcg_temp_free_ptr(fpst); |
10308 | tcg_temp_free_i32(ahp); | |
8b092ca9 AB |
10309 | } |
10310 | break; | |
5553955e PM |
10311 | case 0x56: /* FCVTXN, FCVTXN2 */ |
10312 | /* 64 bit to 32 bit float conversion | |
10313 | * with von Neumann rounding (round to odd) | |
10314 | */ | |
10315 | assert(size == 2); | |
10316 | gen_helper_fcvtx_f64_to_f32(tcg_res[pass], tcg_op, cpu_env); | |
10317 | break; | |
8b092ca9 AB |
10318 | default: |
10319 | g_assert_not_reached(); | |
10320 | } | |
10321 | ||
10322 | if (genfn) { | |
10323 | genfn(tcg_res[pass], tcg_op); | |
10324 | } else if (genenvfn) { | |
10325 | genenvfn(tcg_res[pass], cpu_env, tcg_op); | |
10326 | } | |
10327 | ||
10328 | tcg_temp_free_i64(tcg_op); | |
10329 | } | |
10330 | ||
10331 | for (pass = 0; pass < 2; pass++) { | |
10332 | write_vec_element_i32(s, tcg_res[pass], rd, destelt + pass, MO_32); | |
10333 | tcg_temp_free_i32(tcg_res[pass]); | |
10334 | } | |
4ff55bcb | 10335 | clear_vec_high(s, is_q, rd); |
8b092ca9 AB |
10336 | } |
10337 | ||
09e03735 AB |
10338 | /* Remaining saturating accumulating ops */ |
10339 | static void handle_2misc_satacc(DisasContext *s, bool is_scalar, bool is_u, | |
10340 | bool is_q, int size, int rn, int rd) | |
10341 | { | |
10342 | bool is_double = (size == 3); | |
10343 | ||
10344 | if (is_double) { | |
10345 | TCGv_i64 tcg_rn = tcg_temp_new_i64(); | |
10346 | TCGv_i64 tcg_rd = tcg_temp_new_i64(); | |
10347 | int pass; | |
10348 | ||
10349 | for (pass = 0; pass < (is_scalar ? 1 : 2); pass++) { | |
10350 | read_vec_element(s, tcg_rn, rn, pass, MO_64); | |
10351 | read_vec_element(s, tcg_rd, rd, pass, MO_64); | |
10352 | ||
10353 | if (is_u) { /* USQADD */ | |
10354 | gen_helper_neon_uqadd_s64(tcg_rd, cpu_env, tcg_rn, tcg_rd); | |
10355 | } else { /* SUQADD */ | |
10356 | gen_helper_neon_sqadd_u64(tcg_rd, cpu_env, tcg_rn, tcg_rd); | |
10357 | } | |
10358 | write_vec_element(s, tcg_rd, rd, pass, MO_64); | |
10359 | } | |
09e03735 AB |
10360 | tcg_temp_free_i64(tcg_rd); |
10361 | tcg_temp_free_i64(tcg_rn); | |
4ff55bcb | 10362 | clear_vec_high(s, !is_scalar, rd); |
09e03735 AB |
10363 | } else { |
10364 | TCGv_i32 tcg_rn = tcg_temp_new_i32(); | |
10365 | TCGv_i32 tcg_rd = tcg_temp_new_i32(); | |
10366 | int pass, maxpasses; | |
10367 | ||
10368 | if (is_scalar) { | |
10369 | maxpasses = 1; | |
10370 | } else { | |
10371 | maxpasses = is_q ? 4 : 2; | |
10372 | } | |
10373 | ||
10374 | for (pass = 0; pass < maxpasses; pass++) { | |
10375 | if (is_scalar) { | |
10376 | read_vec_element_i32(s, tcg_rn, rn, pass, size); | |
10377 | read_vec_element_i32(s, tcg_rd, rd, pass, size); | |
10378 | } else { | |
10379 | read_vec_element_i32(s, tcg_rn, rn, pass, MO_32); | |
10380 | read_vec_element_i32(s, tcg_rd, rd, pass, MO_32); | |
10381 | } | |
10382 | ||
10383 | if (is_u) { /* USQADD */ | |
10384 | switch (size) { | |
10385 | case 0: | |
10386 | gen_helper_neon_uqadd_s8(tcg_rd, cpu_env, tcg_rn, tcg_rd); | |
10387 | break; | |
10388 | case 1: | |
10389 | gen_helper_neon_uqadd_s16(tcg_rd, cpu_env, tcg_rn, tcg_rd); | |
10390 | break; | |
10391 | case 2: | |
10392 | gen_helper_neon_uqadd_s32(tcg_rd, cpu_env, tcg_rn, tcg_rd); | |
10393 | break; | |
10394 | default: | |
10395 | g_assert_not_reached(); | |
10396 | } | |
10397 | } else { /* SUQADD */ | |
10398 | switch (size) { | |
10399 | case 0: | |
10400 | gen_helper_neon_sqadd_u8(tcg_rd, cpu_env, tcg_rn, tcg_rd); | |
10401 | break; | |
10402 | case 1: | |
10403 | gen_helper_neon_sqadd_u16(tcg_rd, cpu_env, tcg_rn, tcg_rd); | |
10404 | break; | |
10405 | case 2: | |
10406 | gen_helper_neon_sqadd_u32(tcg_rd, cpu_env, tcg_rn, tcg_rd); | |
10407 | break; | |
10408 | default: | |
10409 | g_assert_not_reached(); | |
10410 | } | |
10411 | } | |
10412 | ||
10413 | if (is_scalar) { | |
10414 | TCGv_i64 tcg_zero = tcg_const_i64(0); | |
10415 | write_vec_element(s, tcg_zero, rd, 0, MO_64); | |
10416 | tcg_temp_free_i64(tcg_zero); | |
10417 | } | |
10418 | write_vec_element_i32(s, tcg_rd, rd, pass, MO_32); | |
10419 | } | |
09e03735 AB |
10420 | tcg_temp_free_i32(tcg_rd); |
10421 | tcg_temp_free_i32(tcg_rn); | |
4ff55bcb | 10422 | clear_vec_high(s, is_q, rd); |
09e03735 AB |
10423 | } |
10424 | } | |
10425 | ||
4ce31af4 | 10426 | /* AdvSIMD scalar two reg misc |
384b26fb AB |
10427 | * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0 |
10428 | * +-----+---+-----------+------+-----------+--------+-----+------+------+ | |
10429 | * | 0 1 | U | 1 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd | | |
10430 | * +-----+---+-----------+------+-----------+--------+-----+------+------+ | |
10431 | */ | |
10432 | static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn) | |
10433 | { | |
effa8e06 PM |
10434 | int rd = extract32(insn, 0, 5); |
10435 | int rn = extract32(insn, 5, 5); | |
10436 | int opcode = extract32(insn, 12, 5); | |
10437 | int size = extract32(insn, 22, 2); | |
10438 | bool u = extract32(insn, 29, 1); | |
04c7c6c2 PM |
10439 | bool is_fcvt = false; |
10440 | int rmode; | |
10441 | TCGv_i32 tcg_rmode; | |
10442 | TCGv_ptr tcg_fpstatus; | |
effa8e06 PM |
10443 | |
10444 | switch (opcode) { | |
09e03735 | 10445 | case 0x3: /* USQADD / SUQADD*/ |
8c6afa6a PM |
10446 | if (!fp_access_check(s)) { |
10447 | return; | |
10448 | } | |
09e03735 AB |
10449 | handle_2misc_satacc(s, true, u, false, size, rn, rd); |
10450 | return; | |
0a79bc87 AB |
10451 | case 0x7: /* SQABS / SQNEG */ |
10452 | break; | |
effa8e06 PM |
10453 | case 0xa: /* CMLT */ |
10454 | if (u) { | |
10455 | unallocated_encoding(s); | |
10456 | return; | |
10457 | } | |
10458 | /* fall through */ | |
10459 | case 0x8: /* CMGT, CMGE */ | |
10460 | case 0x9: /* CMEQ, CMLE */ | |
10461 | case 0xb: /* ABS, NEG */ | |
10462 | if (size != 3) { | |
10463 | unallocated_encoding(s); | |
10464 | return; | |
10465 | } | |
10466 | break; | |
5201c136 | 10467 | case 0x12: /* SQXTUN */ |
e44a90c5 | 10468 | if (!u) { |
5201c136 AB |
10469 | unallocated_encoding(s); |
10470 | return; | |
10471 | } | |
10472 | /* fall through */ | |
10473 | case 0x14: /* SQXTN, UQXTN */ | |
10474 | if (size == 3) { | |
10475 | unallocated_encoding(s); | |
10476 | return; | |
10477 | } | |
8c6afa6a PM |
10478 | if (!fp_access_check(s)) { |
10479 | return; | |
10480 | } | |
5201c136 AB |
10481 | handle_2misc_narrow(s, true, opcode, u, false, size, rn, rd); |
10482 | return; | |
8908f4d1 AB |
10483 | case 0xc ... 0xf: |
10484 | case 0x16 ... 0x1d: | |
10485 | case 0x1f: | |
10486 | /* Floating point: U, size[1] and opcode indicate operation; | |
10487 | * size[0] indicates single or double precision. | |
10488 | */ | |
10489 | opcode |= (extract32(size, 1, 1) << 5) | (u << 6); | |
10490 | size = extract32(size, 0, 1) ? 3 : 2; | |
10491 | switch (opcode) { | |
10492 | case 0x2c: /* FCMGT (zero) */ | |
10493 | case 0x2d: /* FCMEQ (zero) */ | |
10494 | case 0x2e: /* FCMLT (zero) */ | |
10495 | case 0x6c: /* FCMGE (zero) */ | |
10496 | case 0x6d: /* FCMLE (zero) */ | |
10497 | handle_2misc_fcmp_zero(s, opcode, true, u, true, size, rn, rd); | |
10498 | return; | |
10113b69 AB |
10499 | case 0x1d: /* SCVTF */ |
10500 | case 0x5d: /* UCVTF */ | |
10501 | { | |
10502 | bool is_signed = (opcode == 0x1d); | |
8c6afa6a PM |
10503 | if (!fp_access_check(s)) { |
10504 | return; | |
10505 | } | |
10113b69 AB |
10506 | handle_simd_intfp_conv(s, rd, rn, 1, is_signed, 0, size); |
10507 | return; | |
10508 | } | |
b6d4443a | 10509 | case 0x3d: /* FRECPE */ |
8f0c6758 | 10510 | case 0x3f: /* FRECPX */ |
c2fb418e | 10511 | case 0x7d: /* FRSQRTE */ |
8c6afa6a PM |
10512 | if (!fp_access_check(s)) { |
10513 | return; | |
10514 | } | |
8f0c6758 AB |
10515 | handle_2misc_reciprocal(s, opcode, true, u, true, size, rn, rd); |
10516 | return; | |
8908f4d1 AB |
10517 | case 0x1a: /* FCVTNS */ |
10518 | case 0x1b: /* FCVTMS */ | |
8908f4d1 AB |
10519 | case 0x3a: /* FCVTPS */ |
10520 | case 0x3b: /* FCVTZS */ | |
8908f4d1 AB |
10521 | case 0x5a: /* FCVTNU */ |
10522 | case 0x5b: /* FCVTMU */ | |
8908f4d1 AB |
10523 | case 0x7a: /* FCVTPU */ |
10524 | case 0x7b: /* FCVTZU */ | |
04c7c6c2 PM |
10525 | is_fcvt = true; |
10526 | rmode = extract32(opcode, 5, 1) | (extract32(opcode, 0, 1) << 1); | |
10527 | break; | |
10528 | case 0x1c: /* FCVTAS */ | |
10529 | case 0x5c: /* FCVTAU */ | |
10530 | /* TIEAWAY doesn't fit in the usual rounding mode encoding */ | |
10531 | is_fcvt = true; | |
10532 | rmode = FPROUNDING_TIEAWAY; | |
10533 | break; | |
04c7c6c2 | 10534 | case 0x56: /* FCVTXN, FCVTXN2 */ |
5553955e PM |
10535 | if (size == 2) { |
10536 | unallocated_encoding(s); | |
10537 | return; | |
10538 | } | |
8c6afa6a PM |
10539 | if (!fp_access_check(s)) { |
10540 | return; | |
10541 | } | |
5553955e PM |
10542 | handle_2misc_narrow(s, true, opcode, u, false, size - 1, rn, rd); |
10543 | return; | |
8908f4d1 AB |
10544 | default: |
10545 | unallocated_encoding(s); | |
10546 | return; | |
10547 | } | |
10548 | break; | |
effa8e06 | 10549 | default: |
09e03735 | 10550 | unallocated_encoding(s); |
effa8e06 PM |
10551 | return; |
10552 | } | |
10553 | ||
8c6afa6a PM |
10554 | if (!fp_access_check(s)) { |
10555 | return; | |
10556 | } | |
10557 | ||
04c7c6c2 PM |
10558 | if (is_fcvt) { |
10559 | tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode)); | |
cdfb22bb | 10560 | tcg_fpstatus = fpstatus_ptr(FPST_FPCR); |
9b049916 | 10561 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); |
04c7c6c2 | 10562 | } else { |
f764718d RH |
10563 | tcg_rmode = NULL; |
10564 | tcg_fpstatus = NULL; | |
04c7c6c2 PM |
10565 | } |
10566 | ||
effa8e06 PM |
10567 | if (size == 3) { |
10568 | TCGv_i64 tcg_rn = read_fp_dreg(s, rn); | |
10569 | TCGv_i64 tcg_rd = tcg_temp_new_i64(); | |
10570 | ||
04c7c6c2 | 10571 | handle_2misc_64(s, opcode, u, tcg_rd, tcg_rn, tcg_rmode, tcg_fpstatus); |
effa8e06 PM |
10572 | write_fp_dreg(s, rd, tcg_rd); |
10573 | tcg_temp_free_i64(tcg_rd); | |
10574 | tcg_temp_free_i64(tcg_rn); | |
0a79bc87 AB |
10575 | } else { |
10576 | TCGv_i32 tcg_rn = tcg_temp_new_i32(); | |
04c7c6c2 PM |
10577 | TCGv_i32 tcg_rd = tcg_temp_new_i32(); |
10578 | ||
0a79bc87 AB |
10579 | read_vec_element_i32(s, tcg_rn, rn, 0, size); |
10580 | ||
04c7c6c2 | 10581 | switch (opcode) { |
0a79bc87 AB |
10582 | case 0x7: /* SQABS, SQNEG */ |
10583 | { | |
10584 | NeonGenOneOpEnvFn *genfn; | |
10585 | static NeonGenOneOpEnvFn * const fns[3][2] = { | |
10586 | { gen_helper_neon_qabs_s8, gen_helper_neon_qneg_s8 }, | |
10587 | { gen_helper_neon_qabs_s16, gen_helper_neon_qneg_s16 }, | |
10588 | { gen_helper_neon_qabs_s32, gen_helper_neon_qneg_s32 }, | |
10589 | }; | |
10590 | genfn = fns[size][u]; | |
10591 | genfn(tcg_rd, cpu_env, tcg_rn); | |
10592 | break; | |
10593 | } | |
04c7c6c2 PM |
10594 | case 0x1a: /* FCVTNS */ |
10595 | case 0x1b: /* FCVTMS */ | |
10596 | case 0x1c: /* FCVTAS */ | |
10597 | case 0x3a: /* FCVTPS */ | |
10598 | case 0x3b: /* FCVTZS */ | |
10599 | { | |
10600 | TCGv_i32 tcg_shift = tcg_const_i32(0); | |
10601 | gen_helper_vfp_tosls(tcg_rd, tcg_rn, tcg_shift, tcg_fpstatus); | |
10602 | tcg_temp_free_i32(tcg_shift); | |
10603 | break; | |
10604 | } | |
10605 | case 0x5a: /* FCVTNU */ | |
10606 | case 0x5b: /* FCVTMU */ | |
10607 | case 0x5c: /* FCVTAU */ | |
10608 | case 0x7a: /* FCVTPU */ | |
10609 | case 0x7b: /* FCVTZU */ | |
10610 | { | |
10611 | TCGv_i32 tcg_shift = tcg_const_i32(0); | |
10612 | gen_helper_vfp_touls(tcg_rd, tcg_rn, tcg_shift, tcg_fpstatus); | |
10613 | tcg_temp_free_i32(tcg_shift); | |
10614 | break; | |
10615 | } | |
10616 | default: | |
10617 | g_assert_not_reached(); | |
10618 | } | |
10619 | ||
10620 | write_fp_sreg(s, rd, tcg_rd); | |
10621 | tcg_temp_free_i32(tcg_rd); | |
10622 | tcg_temp_free_i32(tcg_rn); | |
effa8e06 | 10623 | } |
04c7c6c2 PM |
10624 | |
10625 | if (is_fcvt) { | |
9b049916 | 10626 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); |
04c7c6c2 PM |
10627 | tcg_temp_free_i32(tcg_rmode); |
10628 | tcg_temp_free_ptr(tcg_fpstatus); | |
10629 | } | |
384b26fb AB |
10630 | } |
10631 | ||
4d1cef84 AB |
10632 | /* SSHR[RA]/USHR[RA] - Vector shift right (optional rounding/accumulate) */ |
10633 | static void handle_vec_simd_shri(DisasContext *s, bool is_q, bool is_u, | |
10634 | int immh, int immb, int opcode, int rn, int rd) | |
10635 | { | |
10636 | int size = 32 - clz32(immh) - 1; | |
10637 | int immhb = immh << 3 | immb; | |
10638 | int shift = 2 * (8 << size) - immhb; | |
3f08f0bc | 10639 | GVecGen2iFn *gvec_fn; |
4d1cef84 AB |
10640 | |
10641 | if (extract32(immh, 3, 1) && !is_q) { | |
10642 | unallocated_encoding(s); | |
10643 | return; | |
10644 | } | |
8dae4697 | 10645 | tcg_debug_assert(size <= 3); |
4d1cef84 | 10646 | |
8c6afa6a PM |
10647 | if (!fp_access_check(s)) { |
10648 | return; | |
10649 | } | |
10650 | ||
4d1cef84 AB |
10651 | switch (opcode) { |
10652 | case 0x02: /* SSRA / USRA (accumulate) */ | |
3f08f0bc RH |
10653 | gvec_fn = is_u ? gen_gvec_usra : gen_gvec_ssra; |
10654 | break; | |
893ab054 | 10655 | |
cdb45a60 | 10656 | case 0x08: /* SRI */ |
3f08f0bc RH |
10657 | gvec_fn = gen_gvec_sri; |
10658 | break; | |
cdb45a60 RH |
10659 | |
10660 | case 0x00: /* SSHR / USHR */ | |
10661 | if (is_u) { | |
10662 | if (shift == 8 << size) { | |
10663 | /* Shift count the same size as element size produces zero. */ | |
8711e71f RH |
10664 | tcg_gen_gvec_dup_imm(size, vec_full_reg_offset(s, rd), |
10665 | is_q ? 16 : 8, vec_full_reg_size(s), 0); | |
3f08f0bc | 10666 | return; |
cdb45a60 | 10667 | } |
3f08f0bc | 10668 | gvec_fn = tcg_gen_gvec_shri; |
cdb45a60 RH |
10669 | } else { |
10670 | /* Shift count the same size as element size produces all sign. */ | |
10671 | if (shift == 8 << size) { | |
10672 | shift -= 1; | |
10673 | } | |
3f08f0bc | 10674 | gvec_fn = tcg_gen_gvec_sari; |
cdb45a60 | 10675 | } |
3f08f0bc | 10676 | break; |
cdb45a60 | 10677 | |
4d1cef84 | 10678 | case 0x04: /* SRSHR / URSHR (rounding) */ |
3f08f0bc RH |
10679 | gvec_fn = is_u ? gen_gvec_urshr : gen_gvec_srshr; |
10680 | break; | |
6ccd48d4 | 10681 | |
4d1cef84 | 10682 | case 0x06: /* SRSRA / URSRA (accum + rounding) */ |
3f08f0bc RH |
10683 | gvec_fn = is_u ? gen_gvec_ursra : gen_gvec_srsra; |
10684 | break; | |
6ccd48d4 | 10685 | |
cdb45a60 RH |
10686 | default: |
10687 | g_assert_not_reached(); | |
4d1cef84 AB |
10688 | } |
10689 | ||
3f08f0bc | 10690 | gen_gvec_fn2i(s, is_q, rd, rn, shift, gvec_fn, size); |
cdb45a60 | 10691 | } |
4d1cef84 | 10692 | |
4d1cef84 AB |
10693 | /* SHL/SLI - Vector shift left */ |
10694 | static void handle_vec_simd_shli(DisasContext *s, bool is_q, bool insert, | |
cdb45a60 | 10695 | int immh, int immb, int opcode, int rn, int rd) |
4d1cef84 AB |
10696 | { |
10697 | int size = 32 - clz32(immh) - 1; | |
10698 | int immhb = immh << 3 | immb; | |
10699 | int shift = immhb - (8 << size); | |
4d1cef84 | 10700 | |
f6c98f91 PM |
10701 | /* Range of size is limited by decode: immh is a non-zero 4 bit field */ |
10702 | assert(size >= 0 && size <= 3); | |
4d1cef84 | 10703 | |
f6c98f91 | 10704 | if (extract32(immh, 3, 1) && !is_q) { |
4d1cef84 AB |
10705 | unallocated_encoding(s); |
10706 | return; | |
10707 | } | |
10708 | ||
8c6afa6a PM |
10709 | if (!fp_access_check(s)) { |
10710 | return; | |
10711 | } | |
10712 | ||
cdb45a60 | 10713 | if (insert) { |
893ab054 | 10714 | gen_gvec_fn2i(s, is_q, rd, rn, shift, gen_gvec_sli, size); |
cdb45a60 RH |
10715 | } else { |
10716 | gen_gvec_fn2i(s, is_q, rd, rn, shift, tcg_gen_gvec_shli, size); | |
4d1cef84 AB |
10717 | } |
10718 | } | |
10719 | ||
10720 | /* USHLL/SHLL - Vector shift left with widening */ | |
10721 | static void handle_vec_simd_wshli(DisasContext *s, bool is_q, bool is_u, | |
10722 | int immh, int immb, int opcode, int rn, int rd) | |
10723 | { | |
10724 | int size = 32 - clz32(immh) - 1; | |
10725 | int immhb = immh << 3 | immb; | |
10726 | int shift = immhb - (8 << size); | |
10727 | int dsize = 64; | |
10728 | int esize = 8 << size; | |
10729 | int elements = dsize/esize; | |
10730 | TCGv_i64 tcg_rn = new_tmp_a64(s); | |
10731 | TCGv_i64 tcg_rd = new_tmp_a64(s); | |
10732 | int i; | |
10733 | ||
10734 | if (size >= 3) { | |
10735 | unallocated_encoding(s); | |
10736 | return; | |
10737 | } | |
10738 | ||
8c6afa6a PM |
10739 | if (!fp_access_check(s)) { |
10740 | return; | |
10741 | } | |
10742 | ||
4d1cef84 AB |
10743 | /* For the LL variants the store is larger than the load, |
10744 | * so if rd == rn we would overwrite parts of our input. | |
10745 | * So load everything right now and use shifts in the main loop. | |
10746 | */ | |
10747 | read_vec_element(s, tcg_rn, rn, is_q ? 1 : 0, MO_64); | |
10748 | ||
10749 | for (i = 0; i < elements; i++) { | |
10750 | tcg_gen_shri_i64(tcg_rd, tcg_rn, i * esize); | |
10751 | ext_and_shift_reg(tcg_rd, tcg_rd, size | (!is_u << 2), 0); | |
10752 | tcg_gen_shli_i64(tcg_rd, tcg_rd, shift); | |
10753 | write_vec_element(s, tcg_rd, rd, i, size + 1); | |
10754 | } | |
10755 | } | |
10756 | ||
c1b876b2 AB |
10757 | /* SHRN/RSHRN - Shift right with narrowing (and potential rounding) */ |
10758 | static void handle_vec_simd_shrn(DisasContext *s, bool is_q, | |
10759 | int immh, int immb, int opcode, int rn, int rd) | |
10760 | { | |
10761 | int immhb = immh << 3 | immb; | |
10762 | int size = 32 - clz32(immh) - 1; | |
10763 | int dsize = 64; | |
10764 | int esize = 8 << size; | |
10765 | int elements = dsize/esize; | |
10766 | int shift = (2 * esize) - immhb; | |
10767 | bool round = extract32(opcode, 0, 1); | |
10768 | TCGv_i64 tcg_rn, tcg_rd, tcg_final; | |
10769 | TCGv_i64 tcg_round; | |
10770 | int i; | |
10771 | ||
10772 | if (extract32(immh, 3, 1)) { | |
10773 | unallocated_encoding(s); | |
10774 | return; | |
10775 | } | |
10776 | ||
8c6afa6a PM |
10777 | if (!fp_access_check(s)) { |
10778 | return; | |
10779 | } | |
10780 | ||
c1b876b2 AB |
10781 | tcg_rn = tcg_temp_new_i64(); |
10782 | tcg_rd = tcg_temp_new_i64(); | |
10783 | tcg_final = tcg_temp_new_i64(); | |
10784 | read_vec_element(s, tcg_final, rd, is_q ? 1 : 0, MO_64); | |
10785 | ||
10786 | if (round) { | |
10787 | uint64_t round_const = 1ULL << (shift - 1); | |
10788 | tcg_round = tcg_const_i64(round_const); | |
10789 | } else { | |
f764718d | 10790 | tcg_round = NULL; |
c1b876b2 AB |
10791 | } |
10792 | ||
10793 | for (i = 0; i < elements; i++) { | |
10794 | read_vec_element(s, tcg_rn, rn, i, size+1); | |
10795 | handle_shri_with_rndacc(tcg_rd, tcg_rn, tcg_round, | |
10796 | false, true, size+1, shift); | |
10797 | ||
10798 | tcg_gen_deposit_i64(tcg_final, tcg_final, tcg_rd, esize * i, esize); | |
10799 | } | |
10800 | ||
10801 | if (!is_q) { | |
c1b876b2 AB |
10802 | write_vec_element(s, tcg_final, rd, 0, MO_64); |
10803 | } else { | |
10804 | write_vec_element(s, tcg_final, rd, 1, MO_64); | |
10805 | } | |
c1b876b2 AB |
10806 | if (round) { |
10807 | tcg_temp_free_i64(tcg_round); | |
10808 | } | |
10809 | tcg_temp_free_i64(tcg_rn); | |
10810 | tcg_temp_free_i64(tcg_rd); | |
10811 | tcg_temp_free_i64(tcg_final); | |
4ff55bcb RH |
10812 | |
10813 | clear_vec_high(s, is_q, rd); | |
c1b876b2 AB |
10814 | } |
10815 | ||
10816 | ||
4ce31af4 | 10817 | /* AdvSIMD shift by immediate |
384b26fb AB |
10818 | * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0 |
10819 | * +---+---+---+-------------+------+------+--------+---+------+------+ | |
10820 | * | 0 | Q | U | 0 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd | | |
10821 | * +---+---+---+-------------+------+------+--------+---+------+------+ | |
10822 | */ | |
10823 | static void disas_simd_shift_imm(DisasContext *s, uint32_t insn) | |
10824 | { | |
4d1cef84 AB |
10825 | int rd = extract32(insn, 0, 5); |
10826 | int rn = extract32(insn, 5, 5); | |
10827 | int opcode = extract32(insn, 11, 5); | |
10828 | int immb = extract32(insn, 16, 3); | |
10829 | int immh = extract32(insn, 19, 4); | |
10830 | bool is_u = extract32(insn, 29, 1); | |
10831 | bool is_q = extract32(insn, 30, 1); | |
10832 | ||
3944d58d RH |
10833 | /* data_proc_simd[] has sent immh == 0 to disas_simd_mod_imm. */ |
10834 | assert(immh != 0); | |
10835 | ||
4d1cef84 | 10836 | switch (opcode) { |
37a706ad PM |
10837 | case 0x08: /* SRI */ |
10838 | if (!is_u) { | |
10839 | unallocated_encoding(s); | |
10840 | return; | |
10841 | } | |
10842 | /* fall through */ | |
4d1cef84 AB |
10843 | case 0x00: /* SSHR / USHR */ |
10844 | case 0x02: /* SSRA / USRA (accumulate) */ | |
10845 | case 0x04: /* SRSHR / URSHR (rounding) */ | |
10846 | case 0x06: /* SRSRA / URSRA (accum + rounding) */ | |
10847 | handle_vec_simd_shri(s, is_q, is_u, immh, immb, opcode, rn, rd); | |
10848 | break; | |
10849 | case 0x0a: /* SHL / SLI */ | |
10850 | handle_vec_simd_shli(s, is_q, is_u, immh, immb, opcode, rn, rd); | |
10851 | break; | |
c1b876b2 AB |
10852 | case 0x10: /* SHRN */ |
10853 | case 0x11: /* RSHRN / SQRSHRUN */ | |
10854 | if (is_u) { | |
10855 | handle_vec_simd_sqshrn(s, false, is_q, false, true, immh, immb, | |
10856 | opcode, rn, rd); | |
10857 | } else { | |
10858 | handle_vec_simd_shrn(s, is_q, immh, immb, opcode, rn, rd); | |
10859 | } | |
10860 | break; | |
10861 | case 0x12: /* SQSHRN / UQSHRN */ | |
10862 | case 0x13: /* SQRSHRN / UQRSHRN */ | |
10863 | handle_vec_simd_sqshrn(s, false, is_q, is_u, is_u, immh, immb, | |
10864 | opcode, rn, rd); | |
10865 | break; | |
4d1cef84 AB |
10866 | case 0x14: /* SSHLL / USHLL */ |
10867 | handle_vec_simd_wshli(s, is_q, is_u, immh, immb, opcode, rn, rd); | |
10868 | break; | |
10113b69 AB |
10869 | case 0x1c: /* SCVTF / UCVTF */ |
10870 | handle_simd_shift_intfp_conv(s, false, is_q, is_u, immh, immb, | |
10871 | opcode, rn, rd); | |
10872 | break; | |
a566da1b | 10873 | case 0xc: /* SQSHLU */ |
a847f32c PM |
10874 | if (!is_u) { |
10875 | unallocated_encoding(s); | |
10876 | return; | |
10877 | } | |
10878 | handle_simd_qshl(s, false, is_q, false, true, immh, immb, rn, rd); | |
10879 | break; | |
a566da1b | 10880 | case 0xe: /* SQSHL, UQSHL */ |
a847f32c PM |
10881 | handle_simd_qshl(s, false, is_q, is_u, is_u, immh, immb, rn, rd); |
10882 | break; | |
10113b69 | 10883 | case 0x1f: /* FCVTZS/ FCVTZU */ |
2ed3ea11 | 10884 | handle_simd_shift_fpint_conv(s, false, is_q, is_u, immh, immb, rn, rd); |
10113b69 | 10885 | return; |
4d1cef84 | 10886 | default: |
a566da1b | 10887 | unallocated_encoding(s); |
4d1cef84 AB |
10888 | return; |
10889 | } | |
384b26fb AB |
10890 | } |
10891 | ||
70d7f984 PM |
10892 | /* Generate code to do a "long" addition or subtraction, ie one done in |
10893 | * TCGv_i64 on vector lanes twice the width specified by size. | |
10894 | */ | |
10895 | static void gen_neon_addl(int size, bool is_sub, TCGv_i64 tcg_res, | |
10896 | TCGv_i64 tcg_op1, TCGv_i64 tcg_op2) | |
10897 | { | |
10898 | static NeonGenTwo64OpFn * const fns[3][2] = { | |
10899 | { gen_helper_neon_addl_u16, gen_helper_neon_subl_u16 }, | |
10900 | { gen_helper_neon_addl_u32, gen_helper_neon_subl_u32 }, | |
10901 | { tcg_gen_add_i64, tcg_gen_sub_i64 }, | |
10902 | }; | |
10903 | NeonGenTwo64OpFn *genfn; | |
10904 | assert(size < 3); | |
10905 | ||
10906 | genfn = fns[size][is_sub]; | |
10907 | genfn(tcg_res, tcg_op1, tcg_op2); | |
10908 | } | |
10909 | ||
a08582f4 PM |
10910 | static void handle_3rd_widening(DisasContext *s, int is_q, int is_u, int size, |
10911 | int opcode, int rd, int rn, int rm) | |
10912 | { | |
10913 | /* 3-reg-different widening insns: 64 x 64 -> 128 */ | |
10914 | TCGv_i64 tcg_res[2]; | |
10915 | int pass, accop; | |
10916 | ||
10917 | tcg_res[0] = tcg_temp_new_i64(); | |
10918 | tcg_res[1] = tcg_temp_new_i64(); | |
10919 | ||
10920 | /* Does this op do an adding accumulate, a subtracting accumulate, | |
10921 | * or no accumulate at all? | |
10922 | */ | |
10923 | switch (opcode) { | |
10924 | case 5: | |
10925 | case 8: | |
10926 | case 9: | |
10927 | accop = 1; | |
10928 | break; | |
10929 | case 10: | |
10930 | case 11: | |
10931 | accop = -1; | |
10932 | break; | |
10933 | default: | |
10934 | accop = 0; | |
10935 | break; | |
10936 | } | |
10937 | ||
10938 | if (accop != 0) { | |
10939 | read_vec_element(s, tcg_res[0], rd, 0, MO_64); | |
10940 | read_vec_element(s, tcg_res[1], rd, 1, MO_64); | |
10941 | } | |
10942 | ||
10943 | /* size == 2 means two 32x32->64 operations; this is worth special | |
10944 | * casing because we can generally handle it inline. | |
10945 | */ | |
10946 | if (size == 2) { | |
10947 | for (pass = 0; pass < 2; pass++) { | |
10948 | TCGv_i64 tcg_op1 = tcg_temp_new_i64(); | |
10949 | TCGv_i64 tcg_op2 = tcg_temp_new_i64(); | |
10950 | TCGv_i64 tcg_passres; | |
14776ab5 | 10951 | MemOp memop = MO_32 | (is_u ? 0 : MO_SIGN); |
a08582f4 PM |
10952 | |
10953 | int elt = pass + is_q * 2; | |
10954 | ||
10955 | read_vec_element(s, tcg_op1, rn, elt, memop); | |
10956 | read_vec_element(s, tcg_op2, rm, elt, memop); | |
10957 | ||
10958 | if (accop == 0) { | |
10959 | tcg_passres = tcg_res[pass]; | |
10960 | } else { | |
10961 | tcg_passres = tcg_temp_new_i64(); | |
10962 | } | |
10963 | ||
10964 | switch (opcode) { | |
70d7f984 PM |
10965 | case 0: /* SADDL, SADDL2, UADDL, UADDL2 */ |
10966 | tcg_gen_add_i64(tcg_passres, tcg_op1, tcg_op2); | |
10967 | break; | |
10968 | case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */ | |
10969 | tcg_gen_sub_i64(tcg_passres, tcg_op1, tcg_op2); | |
10970 | break; | |
0ae39320 PM |
10971 | case 5: /* SABAL, SABAL2, UABAL, UABAL2 */ |
10972 | case 7: /* SABDL, SABDL2, UABDL, UABDL2 */ | |
10973 | { | |
10974 | TCGv_i64 tcg_tmp1 = tcg_temp_new_i64(); | |
10975 | TCGv_i64 tcg_tmp2 = tcg_temp_new_i64(); | |
10976 | ||
10977 | tcg_gen_sub_i64(tcg_tmp1, tcg_op1, tcg_op2); | |
10978 | tcg_gen_sub_i64(tcg_tmp2, tcg_op2, tcg_op1); | |
10979 | tcg_gen_movcond_i64(is_u ? TCG_COND_GEU : TCG_COND_GE, | |
10980 | tcg_passres, | |
10981 | tcg_op1, tcg_op2, tcg_tmp1, tcg_tmp2); | |
10982 | tcg_temp_free_i64(tcg_tmp1); | |
10983 | tcg_temp_free_i64(tcg_tmp2); | |
10984 | break; | |
10985 | } | |
a08582f4 PM |
10986 | case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */ |
10987 | case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */ | |
10988 | case 12: /* UMULL, UMULL2, SMULL, SMULL2 */ | |
10989 | tcg_gen_mul_i64(tcg_passres, tcg_op1, tcg_op2); | |
10990 | break; | |
70d7f984 PM |
10991 | case 9: /* SQDMLAL, SQDMLAL2 */ |
10992 | case 11: /* SQDMLSL, SQDMLSL2 */ | |
10993 | case 13: /* SQDMULL, SQDMULL2 */ | |
10994 | tcg_gen_mul_i64(tcg_passres, tcg_op1, tcg_op2); | |
10995 | gen_helper_neon_addl_saturate_s64(tcg_passres, cpu_env, | |
10996 | tcg_passres, tcg_passres); | |
10997 | break; | |
a08582f4 PM |
10998 | default: |
10999 | g_assert_not_reached(); | |
11000 | } | |
11001 | ||
70d7f984 PM |
11002 | if (opcode == 9 || opcode == 11) { |
11003 | /* saturating accumulate ops */ | |
11004 | if (accop < 0) { | |
11005 | tcg_gen_neg_i64(tcg_passres, tcg_passres); | |
11006 | } | |
11007 | gen_helper_neon_addl_saturate_s64(tcg_res[pass], cpu_env, | |
11008 | tcg_res[pass], tcg_passres); | |
11009 | } else if (accop > 0) { | |
a08582f4 | 11010 | tcg_gen_add_i64(tcg_res[pass], tcg_res[pass], tcg_passres); |
a08582f4 PM |
11011 | } else if (accop < 0) { |
11012 | tcg_gen_sub_i64(tcg_res[pass], tcg_res[pass], tcg_passres); | |
70d7f984 PM |
11013 | } |
11014 | ||
11015 | if (accop != 0) { | |
a08582f4 PM |
11016 | tcg_temp_free_i64(tcg_passres); |
11017 | } | |
11018 | ||
11019 | tcg_temp_free_i64(tcg_op1); | |
11020 | tcg_temp_free_i64(tcg_op2); | |
11021 | } | |
11022 | } else { | |
11023 | /* size 0 or 1, generally helper functions */ | |
11024 | for (pass = 0; pass < 2; pass++) { | |
11025 | TCGv_i32 tcg_op1 = tcg_temp_new_i32(); | |
11026 | TCGv_i32 tcg_op2 = tcg_temp_new_i32(); | |
11027 | TCGv_i64 tcg_passres; | |
11028 | int elt = pass + is_q * 2; | |
11029 | ||
11030 | read_vec_element_i32(s, tcg_op1, rn, elt, MO_32); | |
11031 | read_vec_element_i32(s, tcg_op2, rm, elt, MO_32); | |
11032 | ||
11033 | if (accop == 0) { | |
11034 | tcg_passres = tcg_res[pass]; | |
11035 | } else { | |
11036 | tcg_passres = tcg_temp_new_i64(); | |
11037 | } | |
11038 | ||
11039 | switch (opcode) { | |
70d7f984 PM |
11040 | case 0: /* SADDL, SADDL2, UADDL, UADDL2 */ |
11041 | case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */ | |
11042 | { | |
11043 | TCGv_i64 tcg_op2_64 = tcg_temp_new_i64(); | |
11044 | static NeonGenWidenFn * const widenfns[2][2] = { | |
11045 | { gen_helper_neon_widen_s8, gen_helper_neon_widen_u8 }, | |
11046 | { gen_helper_neon_widen_s16, gen_helper_neon_widen_u16 }, | |
11047 | }; | |
11048 | NeonGenWidenFn *widenfn = widenfns[size][is_u]; | |
11049 | ||
11050 | widenfn(tcg_op2_64, tcg_op2); | |
11051 | widenfn(tcg_passres, tcg_op1); | |
11052 | gen_neon_addl(size, (opcode == 2), tcg_passres, | |
11053 | tcg_passres, tcg_op2_64); | |
11054 | tcg_temp_free_i64(tcg_op2_64); | |
11055 | break; | |
11056 | } | |
0ae39320 PM |
11057 | case 5: /* SABAL, SABAL2, UABAL, UABAL2 */ |
11058 | case 7: /* SABDL, SABDL2, UABDL, UABDL2 */ | |
11059 | if (size == 0) { | |
11060 | if (is_u) { | |
11061 | gen_helper_neon_abdl_u16(tcg_passres, tcg_op1, tcg_op2); | |
11062 | } else { | |
11063 | gen_helper_neon_abdl_s16(tcg_passres, tcg_op1, tcg_op2); | |
11064 | } | |
11065 | } else { | |
11066 | if (is_u) { | |
11067 | gen_helper_neon_abdl_u32(tcg_passres, tcg_op1, tcg_op2); | |
11068 | } else { | |
11069 | gen_helper_neon_abdl_s32(tcg_passres, tcg_op1, tcg_op2); | |
11070 | } | |
11071 | } | |
11072 | break; | |
a08582f4 PM |
11073 | case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */ |
11074 | case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */ | |
11075 | case 12: /* UMULL, UMULL2, SMULL, SMULL2 */ | |
11076 | if (size == 0) { | |
11077 | if (is_u) { | |
11078 | gen_helper_neon_mull_u8(tcg_passres, tcg_op1, tcg_op2); | |
11079 | } else { | |
11080 | gen_helper_neon_mull_s8(tcg_passres, tcg_op1, tcg_op2); | |
11081 | } | |
11082 | } else { | |
11083 | if (is_u) { | |
11084 | gen_helper_neon_mull_u16(tcg_passres, tcg_op1, tcg_op2); | |
11085 | } else { | |
11086 | gen_helper_neon_mull_s16(tcg_passres, tcg_op1, tcg_op2); | |
11087 | } | |
11088 | } | |
11089 | break; | |
70d7f984 PM |
11090 | case 9: /* SQDMLAL, SQDMLAL2 */ |
11091 | case 11: /* SQDMLSL, SQDMLSL2 */ | |
11092 | case 13: /* SQDMULL, SQDMULL2 */ | |
11093 | assert(size == 1); | |
11094 | gen_helper_neon_mull_s16(tcg_passres, tcg_op1, tcg_op2); | |
11095 | gen_helper_neon_addl_saturate_s32(tcg_passres, cpu_env, | |
11096 | tcg_passres, tcg_passres); | |
11097 | break; | |
a08582f4 PM |
11098 | default: |
11099 | g_assert_not_reached(); | |
11100 | } | |
11101 | tcg_temp_free_i32(tcg_op1); | |
11102 | tcg_temp_free_i32(tcg_op2); | |
11103 | ||
70d7f984 PM |
11104 | if (accop != 0) { |
11105 | if (opcode == 9 || opcode == 11) { | |
11106 | /* saturating accumulate ops */ | |
11107 | if (accop < 0) { | |
11108 | gen_helper_neon_negl_u32(tcg_passres, tcg_passres); | |
11109 | } | |
11110 | gen_helper_neon_addl_saturate_s32(tcg_res[pass], cpu_env, | |
11111 | tcg_res[pass], | |
11112 | tcg_passres); | |
a08582f4 | 11113 | } else { |
70d7f984 PM |
11114 | gen_neon_addl(size, (accop < 0), tcg_res[pass], |
11115 | tcg_res[pass], tcg_passres); | |
a08582f4 PM |
11116 | } |
11117 | tcg_temp_free_i64(tcg_passres); | |
11118 | } | |
11119 | } | |
11120 | } | |
11121 | ||
11122 | write_vec_element(s, tcg_res[0], rd, 0, MO_64); | |
11123 | write_vec_element(s, tcg_res[1], rd, 1, MO_64); | |
11124 | tcg_temp_free_i64(tcg_res[0]); | |
11125 | tcg_temp_free_i64(tcg_res[1]); | |
11126 | } | |
11127 | ||
dfc15c7c PM |
11128 | static void handle_3rd_wide(DisasContext *s, int is_q, int is_u, int size, |
11129 | int opcode, int rd, int rn, int rm) | |
11130 | { | |
11131 | TCGv_i64 tcg_res[2]; | |
11132 | int part = is_q ? 2 : 0; | |
11133 | int pass; | |
11134 | ||
11135 | for (pass = 0; pass < 2; pass++) { | |
11136 | TCGv_i64 tcg_op1 = tcg_temp_new_i64(); | |
11137 | TCGv_i32 tcg_op2 = tcg_temp_new_i32(); | |
11138 | TCGv_i64 tcg_op2_wide = tcg_temp_new_i64(); | |
11139 | static NeonGenWidenFn * const widenfns[3][2] = { | |
11140 | { gen_helper_neon_widen_s8, gen_helper_neon_widen_u8 }, | |
11141 | { gen_helper_neon_widen_s16, gen_helper_neon_widen_u16 }, | |
11142 | { tcg_gen_ext_i32_i64, tcg_gen_extu_i32_i64 }, | |
11143 | }; | |
11144 | NeonGenWidenFn *widenfn = widenfns[size][is_u]; | |
11145 | ||
11146 | read_vec_element(s, tcg_op1, rn, pass, MO_64); | |
11147 | read_vec_element_i32(s, tcg_op2, rm, part + pass, MO_32); | |
11148 | widenfn(tcg_op2_wide, tcg_op2); | |
11149 | tcg_temp_free_i32(tcg_op2); | |
11150 | tcg_res[pass] = tcg_temp_new_i64(); | |
11151 | gen_neon_addl(size, (opcode == 3), | |
11152 | tcg_res[pass], tcg_op1, tcg_op2_wide); | |
11153 | tcg_temp_free_i64(tcg_op1); | |
11154 | tcg_temp_free_i64(tcg_op2_wide); | |
11155 | } | |
11156 | ||
11157 | for (pass = 0; pass < 2; pass++) { | |
11158 | write_vec_element(s, tcg_res[pass], rd, pass, MO_64); | |
11159 | tcg_temp_free_i64(tcg_res[pass]); | |
11160 | } | |
11161 | } | |
11162 | ||
e4b998d4 PM |
11163 | static void do_narrow_round_high_u32(TCGv_i32 res, TCGv_i64 in) |
11164 | { | |
11165 | tcg_gen_addi_i64(in, in, 1U << 31); | |
7cb36e18 | 11166 | tcg_gen_extrh_i64_i32(res, in); |
e4b998d4 PM |
11167 | } |
11168 | ||
11169 | static void handle_3rd_narrowing(DisasContext *s, int is_q, int is_u, int size, | |
11170 | int opcode, int rd, int rn, int rm) | |
11171 | { | |
11172 | TCGv_i32 tcg_res[2]; | |
11173 | int part = is_q ? 2 : 0; | |
11174 | int pass; | |
11175 | ||
11176 | for (pass = 0; pass < 2; pass++) { | |
11177 | TCGv_i64 tcg_op1 = tcg_temp_new_i64(); | |
11178 | TCGv_i64 tcg_op2 = tcg_temp_new_i64(); | |
11179 | TCGv_i64 tcg_wideres = tcg_temp_new_i64(); | |
11180 | static NeonGenNarrowFn * const narrowfns[3][2] = { | |
11181 | { gen_helper_neon_narrow_high_u8, | |
11182 | gen_helper_neon_narrow_round_high_u8 }, | |
11183 | { gen_helper_neon_narrow_high_u16, | |
11184 | gen_helper_neon_narrow_round_high_u16 }, | |
7cb36e18 | 11185 | { tcg_gen_extrh_i64_i32, do_narrow_round_high_u32 }, |
e4b998d4 PM |
11186 | }; |
11187 | NeonGenNarrowFn *gennarrow = narrowfns[size][is_u]; | |
11188 | ||
11189 | read_vec_element(s, tcg_op1, rn, pass, MO_64); | |
11190 | read_vec_element(s, tcg_op2, rm, pass, MO_64); | |
11191 | ||
11192 | gen_neon_addl(size, (opcode == 6), tcg_wideres, tcg_op1, tcg_op2); | |
11193 | ||
11194 | tcg_temp_free_i64(tcg_op1); | |
11195 | tcg_temp_free_i64(tcg_op2); | |
11196 | ||
11197 | tcg_res[pass] = tcg_temp_new_i32(); | |
11198 | gennarrow(tcg_res[pass], tcg_wideres); | |
11199 | tcg_temp_free_i64(tcg_wideres); | |
11200 | } | |
11201 | ||
11202 | for (pass = 0; pass < 2; pass++) { | |
11203 | write_vec_element_i32(s, tcg_res[pass], rd, pass + part, MO_32); | |
11204 | tcg_temp_free_i32(tcg_res[pass]); | |
11205 | } | |
4ff55bcb | 11206 | clear_vec_high(s, is_q, rd); |
e4b998d4 PM |
11207 | } |
11208 | ||
4ce31af4 | 11209 | /* AdvSIMD three different |
384b26fb AB |
11210 | * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0 |
11211 | * +---+---+---+-----------+------+---+------+--------+-----+------+------+ | |
11212 | * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd | | |
11213 | * +---+---+---+-----------+------+---+------+--------+-----+------+------+ | |
11214 | */ | |
11215 | static void disas_simd_three_reg_diff(DisasContext *s, uint32_t insn) | |
11216 | { | |
a08582f4 PM |
11217 | /* Instructions in this group fall into three basic classes |
11218 | * (in each case with the operation working on each element in | |
11219 | * the input vectors): | |
11220 | * (1) widening 64 x 64 -> 128 (with possibly Vd as an extra | |
11221 | * 128 bit input) | |
11222 | * (2) wide 64 x 128 -> 128 | |
11223 | * (3) narrowing 128 x 128 -> 64 | |
11224 | * Here we do initial decode, catch unallocated cases and | |
11225 | * dispatch to separate functions for each class. | |
11226 | */ | |
11227 | int is_q = extract32(insn, 30, 1); | |
11228 | int is_u = extract32(insn, 29, 1); | |
11229 | int size = extract32(insn, 22, 2); | |
11230 | int opcode = extract32(insn, 12, 4); | |
11231 | int rm = extract32(insn, 16, 5); | |
11232 | int rn = extract32(insn, 5, 5); | |
11233 | int rd = extract32(insn, 0, 5); | |
11234 | ||
11235 | switch (opcode) { | |
11236 | case 1: /* SADDW, SADDW2, UADDW, UADDW2 */ | |
11237 | case 3: /* SSUBW, SSUBW2, USUBW, USUBW2 */ | |
11238 | /* 64 x 128 -> 128 */ | |
dfc15c7c PM |
11239 | if (size == 3) { |
11240 | unallocated_encoding(s); | |
11241 | return; | |
11242 | } | |
8c6afa6a PM |
11243 | if (!fp_access_check(s)) { |
11244 | return; | |
11245 | } | |
dfc15c7c | 11246 | handle_3rd_wide(s, is_q, is_u, size, opcode, rd, rn, rm); |
a08582f4 PM |
11247 | break; |
11248 | case 4: /* ADDHN, ADDHN2, RADDHN, RADDHN2 */ | |
11249 | case 6: /* SUBHN, SUBHN2, RSUBHN, RSUBHN2 */ | |
11250 | /* 128 x 128 -> 64 */ | |
e4b998d4 PM |
11251 | if (size == 3) { |
11252 | unallocated_encoding(s); | |
11253 | return; | |
11254 | } | |
8c6afa6a PM |
11255 | if (!fp_access_check(s)) { |
11256 | return; | |
11257 | } | |
e4b998d4 | 11258 | handle_3rd_narrowing(s, is_q, is_u, size, opcode, rd, rn, rm); |
a08582f4 | 11259 | break; |
70d7f984 | 11260 | case 14: /* PMULL, PMULL2 */ |
e7e96fc5 | 11261 | if (is_u) { |
70d7f984 PM |
11262 | unallocated_encoding(s); |
11263 | return; | |
11264 | } | |
e7e96fc5 RH |
11265 | switch (size) { |
11266 | case 0: /* PMULL.P8 */ | |
11267 | if (!fp_access_check(s)) { | |
11268 | return; | |
11269 | } | |
11270 | /* The Q field specifies lo/hi half input for this insn. */ | |
11271 | gen_gvec_op3_ool(s, true, rd, rn, rm, is_q, | |
11272 | gen_helper_neon_pmull_h); | |
11273 | break; | |
11274 | ||
11275 | case 3: /* PMULL.P64 */ | |
962fcbf2 | 11276 | if (!dc_isar_feature(aa64_pmull, s)) { |
a984e42c PM |
11277 | unallocated_encoding(s); |
11278 | return; | |
11279 | } | |
8c6afa6a PM |
11280 | if (!fp_access_check(s)) { |
11281 | return; | |
11282 | } | |
b9ed510e RH |
11283 | /* The Q field specifies lo/hi half input for this insn. */ |
11284 | gen_gvec_op3_ool(s, true, rd, rn, rm, is_q, | |
11285 | gen_helper_gvec_pmull_q); | |
e7e96fc5 RH |
11286 | break; |
11287 | ||
11288 | default: | |
11289 | unallocated_encoding(s); | |
11290 | break; | |
a984e42c | 11291 | } |
e7e96fc5 | 11292 | return; |
13caf1fd PM |
11293 | case 9: /* SQDMLAL, SQDMLAL2 */ |
11294 | case 11: /* SQDMLSL, SQDMLSL2 */ | |
11295 | case 13: /* SQDMULL, SQDMULL2 */ | |
70d7f984 | 11296 | if (is_u || size == 0) { |
a08582f4 PM |
11297 | unallocated_encoding(s); |
11298 | return; | |
11299 | } | |
11300 | /* fall through */ | |
13caf1fd PM |
11301 | case 0: /* SADDL, SADDL2, UADDL, UADDL2 */ |
11302 | case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */ | |
13caf1fd PM |
11303 | case 5: /* SABAL, SABAL2, UABAL, UABAL2 */ |
11304 | case 7: /* SABDL, SABDL2, UABDL, UABDL2 */ | |
11305 | case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */ | |
11306 | case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */ | |
11307 | case 12: /* SMULL, SMULL2, UMULL, UMULL2 */ | |
a08582f4 PM |
11308 | /* 64 x 64 -> 128 */ |
11309 | if (size == 3) { | |
11310 | unallocated_encoding(s); | |
11311 | return; | |
11312 | } | |
8c6afa6a PM |
11313 | if (!fp_access_check(s)) { |
11314 | return; | |
11315 | } | |
11316 | ||
a08582f4 PM |
11317 | handle_3rd_widening(s, is_q, is_u, size, opcode, rd, rn, rm); |
11318 | break; | |
11319 | default: | |
11320 | /* opcode 15 not allocated */ | |
11321 | unallocated_encoding(s); | |
11322 | break; | |
11323 | } | |
384b26fb AB |
11324 | } |
11325 | ||
e1cea114 PM |
11326 | /* Logic op (opcode == 3) subgroup of C3.6.16. */ |
11327 | static void disas_simd_3same_logic(DisasContext *s, uint32_t insn) | |
11328 | { | |
956d272e PM |
11329 | int rd = extract32(insn, 0, 5); |
11330 | int rn = extract32(insn, 5, 5); | |
11331 | int rm = extract32(insn, 16, 5); | |
11332 | int size = extract32(insn, 22, 2); | |
11333 | bool is_u = extract32(insn, 29, 1); | |
11334 | bool is_q = extract32(insn, 30, 1); | |
956d272e | 11335 | |
8c6afa6a PM |
11336 | if (!fp_access_check(s)) { |
11337 | return; | |
11338 | } | |
11339 | ||
bc48092f RH |
11340 | switch (size + 4 * is_u) { |
11341 | case 0: /* AND */ | |
11342 | gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_and, 0); | |
11343 | return; | |
11344 | case 1: /* BIC */ | |
11345 | gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_andc, 0); | |
11346 | return; | |
11347 | case 2: /* ORR */ | |
2900847f | 11348 | gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_or, 0); |
bc48092f RH |
11349 | return; |
11350 | case 3: /* ORN */ | |
11351 | gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_orc, 0); | |
11352 | return; | |
11353 | case 4: /* EOR */ | |
11354 | gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_xor, 0); | |
11355 | return; | |
956d272e | 11356 | |
bc48092f | 11357 | case 5: /* BSL bitwise select */ |
3a7a2b4e | 11358 | gen_gvec_fn4(s, is_q, rd, rd, rn, rm, tcg_gen_gvec_bitsel, 0); |
bc48092f RH |
11359 | return; |
11360 | case 6: /* BIT, bitwise insert if true */ | |
3a7a2b4e | 11361 | gen_gvec_fn4(s, is_q, rd, rm, rn, rd, tcg_gen_gvec_bitsel, 0); |
bc48092f RH |
11362 | return; |
11363 | case 7: /* BIF, bitwise insert if false */ | |
3a7a2b4e | 11364 | gen_gvec_fn4(s, is_q, rd, rm, rd, rn, tcg_gen_gvec_bitsel, 0); |
bc48092f | 11365 | return; |
956d272e | 11366 | |
bc48092f RH |
11367 | default: |
11368 | g_assert_not_reached(); | |
956d272e | 11369 | } |
e1cea114 PM |
11370 | } |
11371 | ||
bc242f9b AB |
11372 | /* Pairwise op subgroup of C3.6.16. |
11373 | * | |
11374 | * This is called directly or via the handle_3same_float for float pairwise | |
11375 | * operations where the opcode and size are calculated differently. | |
11376 | */ | |
11377 | static void handle_simd_3same_pair(DisasContext *s, int is_q, int u, int opcode, | |
11378 | int size, int rn, int rm, int rd) | |
e1cea114 | 11379 | { |
bc242f9b | 11380 | TCGv_ptr fpst; |
0173a005 PM |
11381 | int pass; |
11382 | ||
bc242f9b AB |
11383 | /* Floating point operations need fpst */ |
11384 | if (opcode >= 0x58) { | |
cdfb22bb | 11385 | fpst = fpstatus_ptr(FPST_FPCR); |
bc242f9b | 11386 | } else { |
f764718d | 11387 | fpst = NULL; |
0173a005 PM |
11388 | } |
11389 | ||
8c6afa6a PM |
11390 | if (!fp_access_check(s)) { |
11391 | return; | |
11392 | } | |
11393 | ||
0173a005 PM |
11394 | /* These operations work on the concatenated rm:rn, with each pair of |
11395 | * adjacent elements being operated on to produce an element in the result. | |
11396 | */ | |
11397 | if (size == 3) { | |
11398 | TCGv_i64 tcg_res[2]; | |
11399 | ||
11400 | for (pass = 0; pass < 2; pass++) { | |
11401 | TCGv_i64 tcg_op1 = tcg_temp_new_i64(); | |
11402 | TCGv_i64 tcg_op2 = tcg_temp_new_i64(); | |
11403 | int passreg = (pass == 0) ? rn : rm; | |
11404 | ||
11405 | read_vec_element(s, tcg_op1, passreg, 0, MO_64); | |
11406 | read_vec_element(s, tcg_op2, passreg, 1, MO_64); | |
11407 | tcg_res[pass] = tcg_temp_new_i64(); | |
11408 | ||
bc242f9b AB |
11409 | switch (opcode) { |
11410 | case 0x17: /* ADDP */ | |
11411 | tcg_gen_add_i64(tcg_res[pass], tcg_op1, tcg_op2); | |
11412 | break; | |
11413 | case 0x58: /* FMAXNMP */ | |
11414 | gen_helper_vfp_maxnumd(tcg_res[pass], tcg_op1, tcg_op2, fpst); | |
11415 | break; | |
11416 | case 0x5a: /* FADDP */ | |
11417 | gen_helper_vfp_addd(tcg_res[pass], tcg_op1, tcg_op2, fpst); | |
11418 | break; | |
11419 | case 0x5e: /* FMAXP */ | |
11420 | gen_helper_vfp_maxd(tcg_res[pass], tcg_op1, tcg_op2, fpst); | |
11421 | break; | |
11422 | case 0x78: /* FMINNMP */ | |
11423 | gen_helper_vfp_minnumd(tcg_res[pass], tcg_op1, tcg_op2, fpst); | |
11424 | break; | |
11425 | case 0x7e: /* FMINP */ | |
11426 | gen_helper_vfp_mind(tcg_res[pass], tcg_op1, tcg_op2, fpst); | |
11427 | break; | |
11428 | default: | |
11429 | g_assert_not_reached(); | |
11430 | } | |
0173a005 PM |
11431 | |
11432 | tcg_temp_free_i64(tcg_op1); | |
11433 | tcg_temp_free_i64(tcg_op2); | |
11434 | } | |
11435 | ||
11436 | for (pass = 0; pass < 2; pass++) { | |
11437 | write_vec_element(s, tcg_res[pass], rd, pass, MO_64); | |
11438 | tcg_temp_free_i64(tcg_res[pass]); | |
11439 | } | |
11440 | } else { | |
11441 | int maxpass = is_q ? 4 : 2; | |
11442 | TCGv_i32 tcg_res[4]; | |
11443 | ||
11444 | for (pass = 0; pass < maxpass; pass++) { | |
11445 | TCGv_i32 tcg_op1 = tcg_temp_new_i32(); | |
11446 | TCGv_i32 tcg_op2 = tcg_temp_new_i32(); | |
bc242f9b | 11447 | NeonGenTwoOpFn *genfn = NULL; |
0173a005 PM |
11448 | int passreg = pass < (maxpass / 2) ? rn : rm; |
11449 | int passelt = (is_q && (pass & 1)) ? 2 : 0; | |
11450 | ||
11451 | read_vec_element_i32(s, tcg_op1, passreg, passelt, MO_32); | |
11452 | read_vec_element_i32(s, tcg_op2, passreg, passelt + 1, MO_32); | |
11453 | tcg_res[pass] = tcg_temp_new_i32(); | |
11454 | ||
11455 | switch (opcode) { | |
11456 | case 0x17: /* ADDP */ | |
11457 | { | |
11458 | static NeonGenTwoOpFn * const fns[3] = { | |
11459 | gen_helper_neon_padd_u8, | |
11460 | gen_helper_neon_padd_u16, | |
11461 | tcg_gen_add_i32, | |
11462 | }; | |
11463 | genfn = fns[size]; | |
11464 | break; | |
11465 | } | |
11466 | case 0x14: /* SMAXP, UMAXP */ | |
11467 | { | |
11468 | static NeonGenTwoOpFn * const fns[3][2] = { | |
11469 | { gen_helper_neon_pmax_s8, gen_helper_neon_pmax_u8 }, | |
11470 | { gen_helper_neon_pmax_s16, gen_helper_neon_pmax_u16 }, | |
ecb8ab8d | 11471 | { tcg_gen_smax_i32, tcg_gen_umax_i32 }, |
0173a005 PM |
11472 | }; |
11473 | genfn = fns[size][u]; | |
11474 | break; | |
11475 | } | |
11476 | case 0x15: /* SMINP, UMINP */ | |
11477 | { | |
11478 | static NeonGenTwoOpFn * const fns[3][2] = { | |
11479 | { gen_helper_neon_pmin_s8, gen_helper_neon_pmin_u8 }, | |
11480 | { gen_helper_neon_pmin_s16, gen_helper_neon_pmin_u16 }, | |
ecb8ab8d | 11481 | { tcg_gen_smin_i32, tcg_gen_umin_i32 }, |
0173a005 PM |
11482 | }; |
11483 | genfn = fns[size][u]; | |
11484 | break; | |
11485 | } | |
bc242f9b AB |
11486 | /* The FP operations are all on single floats (32 bit) */ |
11487 | case 0x58: /* FMAXNMP */ | |
11488 | gen_helper_vfp_maxnums(tcg_res[pass], tcg_op1, tcg_op2, fpst); | |
11489 | break; | |
11490 | case 0x5a: /* FADDP */ | |
11491 | gen_helper_vfp_adds(tcg_res[pass], tcg_op1, tcg_op2, fpst); | |
11492 | break; | |
11493 | case 0x5e: /* FMAXP */ | |
11494 | gen_helper_vfp_maxs(tcg_res[pass], tcg_op1, tcg_op2, fpst); | |
11495 | break; | |
11496 | case 0x78: /* FMINNMP */ | |
11497 | gen_helper_vfp_minnums(tcg_res[pass], tcg_op1, tcg_op2, fpst); | |
11498 | break; | |
11499 | case 0x7e: /* FMINP */ | |
11500 | gen_helper_vfp_mins(tcg_res[pass], tcg_op1, tcg_op2, fpst); | |
11501 | break; | |
0173a005 PM |
11502 | default: |
11503 | g_assert_not_reached(); | |
11504 | } | |
11505 | ||
bc242f9b AB |
11506 | /* FP ops called directly, otherwise call now */ |
11507 | if (genfn) { | |
11508 | genfn(tcg_res[pass], tcg_op1, tcg_op2); | |
11509 | } | |
0173a005 PM |
11510 | |
11511 | tcg_temp_free_i32(tcg_op1); | |
11512 | tcg_temp_free_i32(tcg_op2); | |
11513 | } | |
11514 | ||
11515 | for (pass = 0; pass < maxpass; pass++) { | |
11516 | write_vec_element_i32(s, tcg_res[pass], rd, pass, MO_32); | |
11517 | tcg_temp_free_i32(tcg_res[pass]); | |
11518 | } | |
4ff55bcb | 11519 | clear_vec_high(s, is_q, rd); |
0173a005 | 11520 | } |
bc242f9b | 11521 | |
f764718d | 11522 | if (fpst) { |
bc242f9b AB |
11523 | tcg_temp_free_ptr(fpst); |
11524 | } | |
e1cea114 PM |
11525 | } |
11526 | ||
11527 | /* Floating point op subgroup of C3.6.16. */ | |
11528 | static void disas_simd_3same_float(DisasContext *s, uint32_t insn) | |
11529 | { | |
845ea09a PM |
11530 | /* For floating point ops, the U, size[1] and opcode bits |
11531 | * together indicate the operation. size[0] indicates single | |
11532 | * or double. | |
11533 | */ | |
11534 | int fpopcode = extract32(insn, 11, 5) | |
11535 | | (extract32(insn, 23, 1) << 5) | |
11536 | | (extract32(insn, 29, 1) << 6); | |
11537 | int is_q = extract32(insn, 30, 1); | |
11538 | int size = extract32(insn, 22, 1); | |
11539 | int rm = extract32(insn, 16, 5); | |
11540 | int rn = extract32(insn, 5, 5); | |
11541 | int rd = extract32(insn, 0, 5); | |
11542 | ||
11543 | int datasize = is_q ? 128 : 64; | |
11544 | int esize = 32 << size; | |
11545 | int elements = datasize / esize; | |
11546 | ||
11547 | if (size == 1 && !is_q) { | |
11548 | unallocated_encoding(s); | |
11549 | return; | |
11550 | } | |
11551 | ||
11552 | switch (fpopcode) { | |
11553 | case 0x58: /* FMAXNMP */ | |
11554 | case 0x5a: /* FADDP */ | |
11555 | case 0x5e: /* FMAXP */ | |
11556 | case 0x78: /* FMINNMP */ | |
11557 | case 0x7e: /* FMINP */ | |
bc242f9b AB |
11558 | if (size && !is_q) { |
11559 | unallocated_encoding(s); | |
11560 | return; | |
11561 | } | |
11562 | handle_simd_3same_pair(s, is_q, 0, fpopcode, size ? MO_64 : MO_32, | |
11563 | rn, rm, rd); | |
845ea09a PM |
11564 | return; |
11565 | case 0x1b: /* FMULX */ | |
845ea09a PM |
11566 | case 0x1f: /* FRECPS */ |
11567 | case 0x3f: /* FRSQRTS */ | |
845ea09a | 11568 | case 0x5d: /* FACGE */ |
845ea09a PM |
11569 | case 0x7d: /* FACGT */ |
11570 | case 0x19: /* FMLA */ | |
11571 | case 0x39: /* FMLS */ | |
845ea09a PM |
11572 | case 0x18: /* FMAXNM */ |
11573 | case 0x1a: /* FADD */ | |
8908f4d1 | 11574 | case 0x1c: /* FCMEQ */ |
845ea09a PM |
11575 | case 0x1e: /* FMAX */ |
11576 | case 0x38: /* FMINNM */ | |
11577 | case 0x3a: /* FSUB */ | |
11578 | case 0x3e: /* FMIN */ | |
11579 | case 0x5b: /* FMUL */ | |
8908f4d1 | 11580 | case 0x5c: /* FCMGE */ |
845ea09a PM |
11581 | case 0x5f: /* FDIV */ |
11582 | case 0x7a: /* FABD */ | |
8908f4d1 | 11583 | case 0x7c: /* FCMGT */ |
8c6afa6a PM |
11584 | if (!fp_access_check(s)) { |
11585 | return; | |
11586 | } | |
845ea09a PM |
11587 | handle_3same_float(s, size, elements, fpopcode, rd, rn, rm); |
11588 | return; | |
0caa5af8 RH |
11589 | |
11590 | case 0x1d: /* FMLAL */ | |
11591 | case 0x3d: /* FMLSL */ | |
11592 | case 0x59: /* FMLAL2 */ | |
11593 | case 0x79: /* FMLSL2 */ | |
11594 | if (size & 1 || !dc_isar_feature(aa64_fhm, s)) { | |
11595 | unallocated_encoding(s); | |
11596 | return; | |
11597 | } | |
11598 | if (fp_access_check(s)) { | |
11599 | int is_s = extract32(insn, 23, 1); | |
11600 | int is_2 = extract32(insn, 29, 1); | |
11601 | int data = (is_2 << 1) | is_s; | |
11602 | tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd), | |
11603 | vec_full_reg_offset(s, rn), | |
11604 | vec_full_reg_offset(s, rm), cpu_env, | |
11605 | is_q ? 16 : 8, vec_full_reg_size(s), | |
11606 | data, gen_helper_gvec_fmlal_a64); | |
11607 | } | |
11608 | return; | |
11609 | ||
845ea09a PM |
11610 | default: |
11611 | unallocated_encoding(s); | |
11612 | return; | |
11613 | } | |
e1cea114 PM |
11614 | } |
11615 | ||
11616 | /* Integer op subgroup of C3.6.16. */ | |
11617 | static void disas_simd_3same_int(DisasContext *s, uint32_t insn) | |
11618 | { | |
1f8a73af PM |
11619 | int is_q = extract32(insn, 30, 1); |
11620 | int u = extract32(insn, 29, 1); | |
11621 | int size = extract32(insn, 22, 2); | |
11622 | int opcode = extract32(insn, 11, 5); | |
11623 | int rm = extract32(insn, 16, 5); | |
11624 | int rn = extract32(insn, 5, 5); | |
11625 | int rd = extract32(insn, 0, 5); | |
11626 | int pass; | |
79d61de6 | 11627 | TCGCond cond; |
1f8a73af PM |
11628 | |
11629 | switch (opcode) { | |
11630 | case 0x13: /* MUL, PMUL */ | |
11631 | if (u && size != 0) { | |
11632 | unallocated_encoding(s); | |
11633 | return; | |
11634 | } | |
11635 | /* fall through */ | |
11636 | case 0x0: /* SHADD, UHADD */ | |
11637 | case 0x2: /* SRHADD, URHADD */ | |
11638 | case 0x4: /* SHSUB, UHSUB */ | |
11639 | case 0xc: /* SMAX, UMAX */ | |
11640 | case 0xd: /* SMIN, UMIN */ | |
11641 | case 0xe: /* SABD, UABD */ | |
11642 | case 0xf: /* SABA, UABA */ | |
11643 | case 0x12: /* MLA, MLS */ | |
11644 | if (size == 3) { | |
11645 | unallocated_encoding(s); | |
11646 | return; | |
11647 | } | |
8b12a0cf | 11648 | break; |
1f8a73af PM |
11649 | case 0x16: /* SQDMULH, SQRDMULH */ |
11650 | if (size == 0 || size == 3) { | |
11651 | unallocated_encoding(s); | |
11652 | return; | |
11653 | } | |
8b12a0cf | 11654 | break; |
1f8a73af PM |
11655 | default: |
11656 | if (size == 3 && !is_q) { | |
11657 | unallocated_encoding(s); | |
11658 | return; | |
11659 | } | |
11660 | break; | |
11661 | } | |
11662 | ||
8c6afa6a PM |
11663 | if (!fp_access_check(s)) { |
11664 | return; | |
11665 | } | |
11666 | ||
bc48092f | 11667 | switch (opcode) { |
89e68b57 | 11668 | case 0x01: /* SQADD, UQADD */ |
c7715b6b RH |
11669 | if (u) { |
11670 | gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_uqadd_qc, size); | |
11671 | } else { | |
11672 | gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_sqadd_qc, size); | |
11673 | } | |
89e68b57 RH |
11674 | return; |
11675 | case 0x05: /* SQSUB, UQSUB */ | |
c7715b6b RH |
11676 | if (u) { |
11677 | gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_uqsub_qc, size); | |
11678 | } else { | |
11679 | gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_sqsub_qc, size); | |
11680 | } | |
89e68b57 | 11681 | return; |
87b74e8b | 11682 | case 0x08: /* SSHL, USHL */ |
8161b753 RH |
11683 | if (u) { |
11684 | gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_ushl, size); | |
11685 | } else { | |
11686 | gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_sshl, size); | |
11687 | } | |
87b74e8b | 11688 | return; |
264d2a48 RH |
11689 | case 0x0c: /* SMAX, UMAX */ |
11690 | if (u) { | |
11691 | gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_umax, size); | |
11692 | } else { | |
11693 | gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_smax, size); | |
11694 | } | |
11695 | return; | |
11696 | case 0x0d: /* SMIN, UMIN */ | |
11697 | if (u) { | |
11698 | gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_umin, size); | |
11699 | } else { | |
11700 | gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_smin, size); | |
11701 | } | |
11702 | return; | |
50c160d4 RH |
11703 | case 0xe: /* SABD, UABD */ |
11704 | if (u) { | |
11705 | gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_uabd, size); | |
11706 | } else { | |
11707 | gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_sabd, size); | |
11708 | } | |
11709 | return; | |
cfdb2c0c RH |
11710 | case 0xf: /* SABA, UABA */ |
11711 | if (u) { | |
11712 | gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_uaba, size); | |
11713 | } else { | |
11714 | gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_saba, size); | |
11715 | } | |
11716 | return; | |
bc48092f RH |
11717 | case 0x10: /* ADD, SUB */ |
11718 | if (u) { | |
11719 | gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_sub, size); | |
11720 | } else { | |
11721 | gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_add, size); | |
11722 | } | |
11723 | return; | |
0c7c55c4 RH |
11724 | case 0x13: /* MUL, PMUL */ |
11725 | if (!u) { /* MUL */ | |
11726 | gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_mul, size); | |
a21bb78e RH |
11727 | } else { /* PMUL */ |
11728 | gen_gvec_op3_ool(s, is_q, rd, rn, rm, 0, gen_helper_gvec_pmul_b); | |
0c7c55c4 | 11729 | } |
a21bb78e | 11730 | return; |
0c7c55c4 RH |
11731 | case 0x12: /* MLA, MLS */ |
11732 | if (u) { | |
27106320 | 11733 | gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_mls, size); |
0c7c55c4 | 11734 | } else { |
27106320 | 11735 | gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_mla, size); |
0c7c55c4 RH |
11736 | } |
11737 | return; | |
ed78849d RH |
11738 | case 0x16: /* SQDMULH, SQRDMULH */ |
11739 | { | |
11740 | static gen_helper_gvec_3_ptr * const fns[2][2] = { | |
11741 | { gen_helper_neon_sqdmulh_h, gen_helper_neon_sqrdmulh_h }, | |
11742 | { gen_helper_neon_sqdmulh_s, gen_helper_neon_sqrdmulh_s }, | |
11743 | }; | |
11744 | gen_gvec_op3_qc(s, is_q, rd, rn, rm, fns[size - 1][u]); | |
11745 | } | |
11746 | return; | |
79d61de6 RH |
11747 | case 0x11: |
11748 | if (!u) { /* CMTST */ | |
8161b753 | 11749 | gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_cmtst, size); |
79d61de6 RH |
11750 | return; |
11751 | } | |
11752 | /* else CMEQ */ | |
11753 | cond = TCG_COND_EQ; | |
11754 | goto do_gvec_cmp; | |
11755 | case 0x06: /* CMGT, CMHI */ | |
11756 | cond = u ? TCG_COND_GTU : TCG_COND_GT; | |
11757 | goto do_gvec_cmp; | |
11758 | case 0x07: /* CMGE, CMHS */ | |
11759 | cond = u ? TCG_COND_GEU : TCG_COND_GE; | |
11760 | do_gvec_cmp: | |
11761 | tcg_gen_gvec_cmp(cond, size, vec_full_reg_offset(s, rd), | |
11762 | vec_full_reg_offset(s, rn), | |
11763 | vec_full_reg_offset(s, rm), | |
11764 | is_q ? 16 : 8, vec_full_reg_size(s)); | |
11765 | return; | |
bc48092f RH |
11766 | } |
11767 | ||
1f8a73af | 11768 | if (size == 3) { |
220ad4ca PM |
11769 | assert(is_q); |
11770 | for (pass = 0; pass < 2; pass++) { | |
1f8a73af PM |
11771 | TCGv_i64 tcg_op1 = tcg_temp_new_i64(); |
11772 | TCGv_i64 tcg_op2 = tcg_temp_new_i64(); | |
11773 | TCGv_i64 tcg_res = tcg_temp_new_i64(); | |
11774 | ||
11775 | read_vec_element(s, tcg_op1, rn, pass, MO_64); | |
11776 | read_vec_element(s, tcg_op2, rm, pass, MO_64); | |
11777 | ||
11778 | handle_3same_64(s, opcode, u, tcg_res, tcg_op1, tcg_op2); | |
11779 | ||
11780 | write_vec_element(s, tcg_res, rd, pass, MO_64); | |
11781 | ||
11782 | tcg_temp_free_i64(tcg_res); | |
11783 | tcg_temp_free_i64(tcg_op1); | |
11784 | tcg_temp_free_i64(tcg_op2); | |
11785 | } | |
11786 | } else { | |
11787 | for (pass = 0; pass < (is_q ? 4 : 2); pass++) { | |
11788 | TCGv_i32 tcg_op1 = tcg_temp_new_i32(); | |
11789 | TCGv_i32 tcg_op2 = tcg_temp_new_i32(); | |
11790 | TCGv_i32 tcg_res = tcg_temp_new_i32(); | |
6d9571f7 PM |
11791 | NeonGenTwoOpFn *genfn = NULL; |
11792 | NeonGenTwoOpEnvFn *genenvfn = NULL; | |
1f8a73af PM |
11793 | |
11794 | read_vec_element_i32(s, tcg_op1, rn, pass, MO_32); | |
11795 | read_vec_element_i32(s, tcg_op2, rm, pass, MO_32); | |
11796 | ||
11797 | switch (opcode) { | |
8b12a0cf PM |
11798 | case 0x0: /* SHADD, UHADD */ |
11799 | { | |
11800 | static NeonGenTwoOpFn * const fns[3][2] = { | |
11801 | { gen_helper_neon_hadd_s8, gen_helper_neon_hadd_u8 }, | |
11802 | { gen_helper_neon_hadd_s16, gen_helper_neon_hadd_u16 }, | |
11803 | { gen_helper_neon_hadd_s32, gen_helper_neon_hadd_u32 }, | |
11804 | }; | |
11805 | genfn = fns[size][u]; | |
11806 | break; | |
11807 | } | |
8b12a0cf PM |
11808 | case 0x2: /* SRHADD, URHADD */ |
11809 | { | |
11810 | static NeonGenTwoOpFn * const fns[3][2] = { | |
11811 | { gen_helper_neon_rhadd_s8, gen_helper_neon_rhadd_u8 }, | |
11812 | { gen_helper_neon_rhadd_s16, gen_helper_neon_rhadd_u16 }, | |
11813 | { gen_helper_neon_rhadd_s32, gen_helper_neon_rhadd_u32 }, | |
11814 | }; | |
11815 | genfn = fns[size][u]; | |
11816 | break; | |
11817 | } | |
11818 | case 0x4: /* SHSUB, UHSUB */ | |
11819 | { | |
11820 | static NeonGenTwoOpFn * const fns[3][2] = { | |
11821 | { gen_helper_neon_hsub_s8, gen_helper_neon_hsub_u8 }, | |
11822 | { gen_helper_neon_hsub_s16, gen_helper_neon_hsub_u16 }, | |
11823 | { gen_helper_neon_hsub_s32, gen_helper_neon_hsub_u32 }, | |
11824 | }; | |
11825 | genfn = fns[size][u]; | |
11826 | break; | |
11827 | } | |
6d9571f7 PM |
11828 | case 0x9: /* SQSHL, UQSHL */ |
11829 | { | |
11830 | static NeonGenTwoOpEnvFn * const fns[3][2] = { | |
11831 | { gen_helper_neon_qshl_s8, gen_helper_neon_qshl_u8 }, | |
11832 | { gen_helper_neon_qshl_s16, gen_helper_neon_qshl_u16 }, | |
11833 | { gen_helper_neon_qshl_s32, gen_helper_neon_qshl_u32 }, | |
11834 | }; | |
11835 | genenvfn = fns[size][u]; | |
11836 | break; | |
11837 | } | |
11838 | case 0xa: /* SRSHL, URSHL */ | |
11839 | { | |
11840 | static NeonGenTwoOpFn * const fns[3][2] = { | |
11841 | { gen_helper_neon_rshl_s8, gen_helper_neon_rshl_u8 }, | |
11842 | { gen_helper_neon_rshl_s16, gen_helper_neon_rshl_u16 }, | |
11843 | { gen_helper_neon_rshl_s32, gen_helper_neon_rshl_u32 }, | |
11844 | }; | |
11845 | genfn = fns[size][u]; | |
11846 | break; | |
11847 | } | |
11848 | case 0xb: /* SQRSHL, UQRSHL */ | |
11849 | { | |
11850 | static NeonGenTwoOpEnvFn * const fns[3][2] = { | |
11851 | { gen_helper_neon_qrshl_s8, gen_helper_neon_qrshl_u8 }, | |
11852 | { gen_helper_neon_qrshl_s16, gen_helper_neon_qrshl_u16 }, | |
11853 | { gen_helper_neon_qrshl_s32, gen_helper_neon_qrshl_u32 }, | |
11854 | }; | |
11855 | genenvfn = fns[size][u]; | |
11856 | break; | |
11857 | } | |
1f8a73af PM |
11858 | default: |
11859 | g_assert_not_reached(); | |
11860 | } | |
11861 | ||
6d9571f7 PM |
11862 | if (genenvfn) { |
11863 | genenvfn(tcg_res, cpu_env, tcg_op1, tcg_op2); | |
11864 | } else { | |
11865 | genfn(tcg_res, tcg_op1, tcg_op2); | |
11866 | } | |
1f8a73af PM |
11867 | |
11868 | write_vec_element_i32(s, tcg_res, rd, pass, MO_32); | |
11869 | ||
11870 | tcg_temp_free_i32(tcg_res); | |
11871 | tcg_temp_free_i32(tcg_op1); | |
11872 | tcg_temp_free_i32(tcg_op2); | |
11873 | } | |
11874 | } | |
4ff55bcb | 11875 | clear_vec_high(s, is_q, rd); |
e1cea114 PM |
11876 | } |
11877 | ||
4ce31af4 | 11878 | /* AdvSIMD three same |
384b26fb AB |
11879 | * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0 |
11880 | * +---+---+---+-----------+------+---+------+--------+---+------+------+ | |
11881 | * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd | | |
11882 | * +---+---+---+-----------+------+---+------+--------+---+------+------+ | |
11883 | */ | |
11884 | static void disas_simd_three_reg_same(DisasContext *s, uint32_t insn) | |
11885 | { | |
e1cea114 PM |
11886 | int opcode = extract32(insn, 11, 5); |
11887 | ||
11888 | switch (opcode) { | |
11889 | case 0x3: /* logic ops */ | |
11890 | disas_simd_3same_logic(s, insn); | |
11891 | break; | |
11892 | case 0x17: /* ADDP */ | |
11893 | case 0x14: /* SMAXP, UMAXP */ | |
11894 | case 0x15: /* SMINP, UMINP */ | |
bc242f9b | 11895 | { |
e1cea114 | 11896 | /* Pairwise operations */ |
bc242f9b AB |
11897 | int is_q = extract32(insn, 30, 1); |
11898 | int u = extract32(insn, 29, 1); | |
11899 | int size = extract32(insn, 22, 2); | |
11900 | int rm = extract32(insn, 16, 5); | |
11901 | int rn = extract32(insn, 5, 5); | |
11902 | int rd = extract32(insn, 0, 5); | |
11903 | if (opcode == 0x17) { | |
11904 | if (u || (size == 3 && !is_q)) { | |
11905 | unallocated_encoding(s); | |
11906 | return; | |
11907 | } | |
11908 | } else { | |
11909 | if (size == 3) { | |
11910 | unallocated_encoding(s); | |
11911 | return; | |
11912 | } | |
11913 | } | |
11914 | handle_simd_3same_pair(s, is_q, u, opcode, size, rn, rm, rd); | |
e1cea114 | 11915 | break; |
bc242f9b | 11916 | } |
e1cea114 PM |
11917 | case 0x18 ... 0x31: |
11918 | /* floating point ops, sz[1] and U are part of opcode */ | |
11919 | disas_simd_3same_float(s, insn); | |
11920 | break; | |
11921 | default: | |
11922 | disas_simd_3same_int(s, insn); | |
11923 | break; | |
11924 | } | |
384b26fb AB |
11925 | } |
11926 | ||
376e8d6c AB |
11927 | /* |
11928 | * Advanced SIMD three same (ARMv8.2 FP16 variants) | |
11929 | * | |
11930 | * 31 30 29 28 24 23 22 21 20 16 15 14 13 11 10 9 5 4 0 | |
11931 | * +---+---+---+-----------+---------+------+-----+--------+---+------+------+ | |
11932 | * | 0 | Q | U | 0 1 1 1 0 | a | 1 0 | Rm | 0 0 | opcode | 1 | Rn | Rd | | |
11933 | * +---+---+---+-----------+---------+------+-----+--------+---+------+------+ | |
11934 | * | |
11935 | * This includes FMULX, FCMEQ (register), FRECPS, FRSQRTS, FCMGE | |
11936 | * (register), FACGE, FABD, FCMGT (register) and FACGT. | |
11937 | * | |
11938 | */ | |
11939 | static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn) | |
11940 | { | |
11941 | int opcode, fpopcode; | |
11942 | int is_q, u, a, rm, rn, rd; | |
11943 | int datasize, elements; | |
11944 | int pass; | |
11945 | TCGv_ptr fpst; | |
7a2c6e61 | 11946 | bool pairwise = false; |
376e8d6c | 11947 | |
5763190f | 11948 | if (!dc_isar_feature(aa64_fp16, s)) { |
376e8d6c AB |
11949 | unallocated_encoding(s); |
11950 | return; | |
11951 | } | |
11952 | ||
11953 | if (!fp_access_check(s)) { | |
11954 | return; | |
11955 | } | |
11956 | ||
11957 | /* For these floating point ops, the U, a and opcode bits | |
11958 | * together indicate the operation. | |
11959 | */ | |
11960 | opcode = extract32(insn, 11, 3); | |
11961 | u = extract32(insn, 29, 1); | |
11962 | a = extract32(insn, 23, 1); | |
11963 | is_q = extract32(insn, 30, 1); | |
11964 | rm = extract32(insn, 16, 5); | |
11965 | rn = extract32(insn, 5, 5); | |
11966 | rd = extract32(insn, 0, 5); | |
11967 | ||
11968 | fpopcode = opcode | (a << 3) | (u << 4); | |
11969 | datasize = is_q ? 128 : 64; | |
11970 | elements = datasize / 16; | |
11971 | ||
7a2c6e61 AB |
11972 | switch (fpopcode) { |
11973 | case 0x10: /* FMAXNMP */ | |
11974 | case 0x12: /* FADDP */ | |
11975 | case 0x16: /* FMAXP */ | |
11976 | case 0x18: /* FMINNMP */ | |
11977 | case 0x1e: /* FMINP */ | |
11978 | pairwise = true; | |
11979 | break; | |
11980 | } | |
11981 | ||
cdfb22bb | 11982 | fpst = fpstatus_ptr(FPST_FPCR_F16); |
376e8d6c | 11983 | |
7a2c6e61 AB |
11984 | if (pairwise) { |
11985 | int maxpass = is_q ? 8 : 4; | |
376e8d6c AB |
11986 | TCGv_i32 tcg_op1 = tcg_temp_new_i32(); |
11987 | TCGv_i32 tcg_op2 = tcg_temp_new_i32(); | |
7a2c6e61 | 11988 | TCGv_i32 tcg_res[8]; |
376e8d6c | 11989 | |
7a2c6e61 AB |
11990 | for (pass = 0; pass < maxpass; pass++) { |
11991 | int passreg = pass < (maxpass / 2) ? rn : rm; | |
11992 | int passelt = (pass << 1) & (maxpass - 1); | |
376e8d6c | 11993 | |
7a2c6e61 AB |
11994 | read_vec_element_i32(s, tcg_op1, passreg, passelt, MO_16); |
11995 | read_vec_element_i32(s, tcg_op2, passreg, passelt + 1, MO_16); | |
11996 | tcg_res[pass] = tcg_temp_new_i32(); | |
11997 | ||
11998 | switch (fpopcode) { | |
11999 | case 0x10: /* FMAXNMP */ | |
12000 | gen_helper_advsimd_maxnumh(tcg_res[pass], tcg_op1, tcg_op2, | |
12001 | fpst); | |
12002 | break; | |
12003 | case 0x12: /* FADDP */ | |
12004 | gen_helper_advsimd_addh(tcg_res[pass], tcg_op1, tcg_op2, fpst); | |
12005 | break; | |
12006 | case 0x16: /* FMAXP */ | |
12007 | gen_helper_advsimd_maxh(tcg_res[pass], tcg_op1, tcg_op2, fpst); | |
12008 | break; | |
12009 | case 0x18: /* FMINNMP */ | |
12010 | gen_helper_advsimd_minnumh(tcg_res[pass], tcg_op1, tcg_op2, | |
12011 | fpst); | |
12012 | break; | |
12013 | case 0x1e: /* FMINP */ | |
12014 | gen_helper_advsimd_minh(tcg_res[pass], tcg_op1, tcg_op2, fpst); | |
12015 | break; | |
12016 | default: | |
12017 | g_assert_not_reached(); | |
12018 | } | |
12019 | } | |
12020 | ||
12021 | for (pass = 0; pass < maxpass; pass++) { | |
12022 | write_vec_element_i32(s, tcg_res[pass], rd, pass, MO_16); | |
12023 | tcg_temp_free_i32(tcg_res[pass]); | |
376e8d6c AB |
12024 | } |
12025 | ||
376e8d6c AB |
12026 | tcg_temp_free_i32(tcg_op1); |
12027 | tcg_temp_free_i32(tcg_op2); | |
7a2c6e61 AB |
12028 | |
12029 | } else { | |
12030 | for (pass = 0; pass < elements; pass++) { | |
12031 | TCGv_i32 tcg_op1 = tcg_temp_new_i32(); | |
12032 | TCGv_i32 tcg_op2 = tcg_temp_new_i32(); | |
12033 | TCGv_i32 tcg_res = tcg_temp_new_i32(); | |
12034 | ||
12035 | read_vec_element_i32(s, tcg_op1, rn, pass, MO_16); | |
12036 | read_vec_element_i32(s, tcg_op2, rm, pass, MO_16); | |
12037 | ||
12038 | switch (fpopcode) { | |
12039 | case 0x0: /* FMAXNM */ | |
12040 | gen_helper_advsimd_maxnumh(tcg_res, tcg_op1, tcg_op2, fpst); | |
12041 | break; | |
12042 | case 0x1: /* FMLA */ | |
12043 | read_vec_element_i32(s, tcg_res, rd, pass, MO_16); | |
12044 | gen_helper_advsimd_muladdh(tcg_res, tcg_op1, tcg_op2, tcg_res, | |
12045 | fpst); | |
12046 | break; | |
12047 | case 0x2: /* FADD */ | |
12048 | gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst); | |
12049 | break; | |
12050 | case 0x3: /* FMULX */ | |
12051 | gen_helper_advsimd_mulxh(tcg_res, tcg_op1, tcg_op2, fpst); | |
12052 | break; | |
12053 | case 0x4: /* FCMEQ */ | |
12054 | gen_helper_advsimd_ceq_f16(tcg_res, tcg_op1, tcg_op2, fpst); | |
12055 | break; | |
12056 | case 0x6: /* FMAX */ | |
12057 | gen_helper_advsimd_maxh(tcg_res, tcg_op1, tcg_op2, fpst); | |
12058 | break; | |
12059 | case 0x7: /* FRECPS */ | |
12060 | gen_helper_recpsf_f16(tcg_res, tcg_op1, tcg_op2, fpst); | |
12061 | break; | |
12062 | case 0x8: /* FMINNM */ | |
12063 | gen_helper_advsimd_minnumh(tcg_res, tcg_op1, tcg_op2, fpst); | |
12064 | break; | |
12065 | case 0x9: /* FMLS */ | |
12066 | /* As usual for ARM, separate negation for fused multiply-add */ | |
12067 | tcg_gen_xori_i32(tcg_op1, tcg_op1, 0x8000); | |
12068 | read_vec_element_i32(s, tcg_res, rd, pass, MO_16); | |
12069 | gen_helper_advsimd_muladdh(tcg_res, tcg_op1, tcg_op2, tcg_res, | |
12070 | fpst); | |
12071 | break; | |
12072 | case 0xa: /* FSUB */ | |
12073 | gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst); | |
12074 | break; | |
12075 | case 0xe: /* FMIN */ | |
12076 | gen_helper_advsimd_minh(tcg_res, tcg_op1, tcg_op2, fpst); | |
12077 | break; | |
12078 | case 0xf: /* FRSQRTS */ | |
12079 | gen_helper_rsqrtsf_f16(tcg_res, tcg_op1, tcg_op2, fpst); | |
12080 | break; | |
12081 | case 0x13: /* FMUL */ | |
12082 | gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst); | |
12083 | break; | |
12084 | case 0x14: /* FCMGE */ | |
12085 | gen_helper_advsimd_cge_f16(tcg_res, tcg_op1, tcg_op2, fpst); | |
12086 | break; | |
12087 | case 0x15: /* FACGE */ | |
12088 | gen_helper_advsimd_acge_f16(tcg_res, tcg_op1, tcg_op2, fpst); | |
12089 | break; | |
12090 | case 0x17: /* FDIV */ | |
12091 | gen_helper_advsimd_divh(tcg_res, tcg_op1, tcg_op2, fpst); | |
12092 | break; | |
12093 | case 0x1a: /* FABD */ | |
12094 | gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst); | |
12095 | tcg_gen_andi_i32(tcg_res, tcg_res, 0x7fff); | |
12096 | break; | |
12097 | case 0x1c: /* FCMGT */ | |
12098 | gen_helper_advsimd_cgt_f16(tcg_res, tcg_op1, tcg_op2, fpst); | |
12099 | break; | |
12100 | case 0x1d: /* FACGT */ | |
12101 | gen_helper_advsimd_acgt_f16(tcg_res, tcg_op1, tcg_op2, fpst); | |
12102 | break; | |
12103 | default: | |
6eb55edb | 12104 | fprintf(stderr, "%s: insn 0x%04x, fpop 0x%2x @ 0x%" PRIx64 "\n", |
43722a6d | 12105 | __func__, insn, fpopcode, s->pc_curr); |
7a2c6e61 AB |
12106 | g_assert_not_reached(); |
12107 | } | |
12108 | ||
12109 | write_vec_element_i32(s, tcg_res, rd, pass, MO_16); | |
12110 | tcg_temp_free_i32(tcg_res); | |
12111 | tcg_temp_free_i32(tcg_op1); | |
12112 | tcg_temp_free_i32(tcg_op2); | |
12113 | } | |
376e8d6c AB |
12114 | } |
12115 | ||
12116 | tcg_temp_free_ptr(fpst); | |
12117 | ||
12118 | clear_vec_high(s, is_q, rd); | |
12119 | } | |
12120 | ||
e7186d82 RH |
12121 | /* AdvSIMD three same extra |
12122 | * 31 30 29 28 24 23 22 21 20 16 15 14 11 10 9 5 4 0 | |
12123 | * +---+---+---+-----------+------+---+------+---+--------+---+----+----+ | |
12124 | * | 0 | Q | U | 0 1 1 1 0 | size | 0 | Rm | 1 | opcode | 1 | Rn | Rd | | |
12125 | * +---+---+---+-----------+------+---+------+---+--------+---+----+----+ | |
12126 | */ | |
12127 | static void disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn) | |
12128 | { | |
12129 | int rd = extract32(insn, 0, 5); | |
12130 | int rn = extract32(insn, 5, 5); | |
12131 | int opcode = extract32(insn, 11, 4); | |
12132 | int rm = extract32(insn, 16, 5); | |
12133 | int size = extract32(insn, 22, 2); | |
12134 | bool u = extract32(insn, 29, 1); | |
12135 | bool is_q = extract32(insn, 30, 1); | |
962fcbf2 RH |
12136 | bool feature; |
12137 | int rot; | |
e7186d82 RH |
12138 | |
12139 | switch (u * 16 + opcode) { | |
12140 | case 0x10: /* SQRDMLAH (vector) */ | |
12141 | case 0x11: /* SQRDMLSH (vector) */ | |
12142 | if (size != 1 && size != 2) { | |
12143 | unallocated_encoding(s); | |
12144 | return; | |
12145 | } | |
962fcbf2 | 12146 | feature = dc_isar_feature(aa64_rdm, s); |
e7186d82 | 12147 | break; |
26c470a7 RH |
12148 | case 0x02: /* SDOT (vector) */ |
12149 | case 0x12: /* UDOT (vector) */ | |
12150 | if (size != MO_32) { | |
12151 | unallocated_encoding(s); | |
12152 | return; | |
12153 | } | |
962fcbf2 | 12154 | feature = dc_isar_feature(aa64_dp, s); |
26c470a7 | 12155 | break; |
b8a4a96d RH |
12156 | case 0x18: /* FCMLA, #0 */ |
12157 | case 0x19: /* FCMLA, #90 */ | |
12158 | case 0x1a: /* FCMLA, #180 */ | |
12159 | case 0x1b: /* FCMLA, #270 */ | |
12160 | case 0x1c: /* FCADD, #90 */ | |
12161 | case 0x1e: /* FCADD, #270 */ | |
1695cd61 | 12162 | if (size == 0 |
5763190f | 12163 | || (size == 1 && !dc_isar_feature(aa64_fp16, s)) |
1695cd61 RH |
12164 | || (size == 3 && !is_q)) { |
12165 | unallocated_encoding(s); | |
12166 | return; | |
12167 | } | |
962fcbf2 | 12168 | feature = dc_isar_feature(aa64_fcma, s); |
1695cd61 | 12169 | break; |
e7186d82 RH |
12170 | default: |
12171 | unallocated_encoding(s); | |
12172 | return; | |
12173 | } | |
962fcbf2 | 12174 | if (!feature) { |
e7186d82 RH |
12175 | unallocated_encoding(s); |
12176 | return; | |
12177 | } | |
12178 | if (!fp_access_check(s)) { | |
12179 | return; | |
12180 | } | |
12181 | ||
12182 | switch (opcode) { | |
12183 | case 0x0: /* SQRDMLAH (vector) */ | |
146aa66c | 12184 | gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_sqrdmlah_qc, size); |
e7186d82 RH |
12185 | return; |
12186 | ||
12187 | case 0x1: /* SQRDMLSH (vector) */ | |
146aa66c | 12188 | gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_sqrdmlsh_qc, size); |
e7186d82 RH |
12189 | return; |
12190 | ||
26c470a7 RH |
12191 | case 0x2: /* SDOT / UDOT */ |
12192 | gen_gvec_op3_ool(s, is_q, rd, rn, rm, 0, | |
12193 | u ? gen_helper_gvec_udot_b : gen_helper_gvec_sdot_b); | |
12194 | return; | |
12195 | ||
d17b7cdc RH |
12196 | case 0x8: /* FCMLA, #0 */ |
12197 | case 0x9: /* FCMLA, #90 */ | |
12198 | case 0xa: /* FCMLA, #180 */ | |
12199 | case 0xb: /* FCMLA, #270 */ | |
12200 | rot = extract32(opcode, 0, 2); | |
12201 | switch (size) { | |
12202 | case 1: | |
12203 | gen_gvec_op3_fpst(s, is_q, rd, rn, rm, true, rot, | |
12204 | gen_helper_gvec_fcmlah); | |
12205 | break; | |
12206 | case 2: | |
12207 | gen_gvec_op3_fpst(s, is_q, rd, rn, rm, false, rot, | |
12208 | gen_helper_gvec_fcmlas); | |
12209 | break; | |
12210 | case 3: | |
12211 | gen_gvec_op3_fpst(s, is_q, rd, rn, rm, false, rot, | |
12212 | gen_helper_gvec_fcmlad); | |
12213 | break; | |
12214 | default: | |
12215 | g_assert_not_reached(); | |
12216 | } | |
12217 | return; | |
12218 | ||
1695cd61 RH |
12219 | case 0xc: /* FCADD, #90 */ |
12220 | case 0xe: /* FCADD, #270 */ | |
12221 | rot = extract32(opcode, 1, 1); | |
12222 | switch (size) { | |
12223 | case 1: | |
12224 | gen_gvec_op3_fpst(s, is_q, rd, rn, rm, size == 1, rot, | |
12225 | gen_helper_gvec_fcaddh); | |
12226 | break; | |
12227 | case 2: | |
12228 | gen_gvec_op3_fpst(s, is_q, rd, rn, rm, size == 1, rot, | |
12229 | gen_helper_gvec_fcadds); | |
12230 | break; | |
12231 | case 3: | |
12232 | gen_gvec_op3_fpst(s, is_q, rd, rn, rm, size == 1, rot, | |
12233 | gen_helper_gvec_fcaddd); | |
12234 | break; | |
12235 | default: | |
12236 | g_assert_not_reached(); | |
12237 | } | |
12238 | return; | |
12239 | ||
e7186d82 RH |
12240 | default: |
12241 | g_assert_not_reached(); | |
12242 | } | |
12243 | } | |
12244 | ||
931c8cc2 PM |
12245 | static void handle_2misc_widening(DisasContext *s, int opcode, bool is_q, |
12246 | int size, int rn, int rd) | |
12247 | { | |
12248 | /* Handle 2-reg-misc ops which are widening (so each size element | |
12249 | * in the source becomes a 2*size element in the destination. | |
12250 | * The only instruction like this is FCVTL. | |
12251 | */ | |
12252 | int pass; | |
12253 | ||
12254 | if (size == 3) { | |
12255 | /* 32 -> 64 bit fp conversion */ | |
12256 | TCGv_i64 tcg_res[2]; | |
12257 | int srcelt = is_q ? 2 : 0; | |
12258 | ||
12259 | for (pass = 0; pass < 2; pass++) { | |
12260 | TCGv_i32 tcg_op = tcg_temp_new_i32(); | |
12261 | tcg_res[pass] = tcg_temp_new_i64(); | |
12262 | ||
12263 | read_vec_element_i32(s, tcg_op, rn, srcelt + pass, MO_32); | |
12264 | gen_helper_vfp_fcvtds(tcg_res[pass], tcg_op, cpu_env); | |
12265 | tcg_temp_free_i32(tcg_op); | |
12266 | } | |
12267 | for (pass = 0; pass < 2; pass++) { | |
12268 | write_vec_element(s, tcg_res[pass], rd, pass, MO_64); | |
12269 | tcg_temp_free_i64(tcg_res[pass]); | |
12270 | } | |
12271 | } else { | |
12272 | /* 16 -> 32 bit fp conversion */ | |
12273 | int srcelt = is_q ? 4 : 0; | |
12274 | TCGv_i32 tcg_res[4]; | |
cdfb22bb | 12275 | TCGv_ptr fpst = fpstatus_ptr(FPST_FPCR); |
486624fc | 12276 | TCGv_i32 ahp = get_ahp_flag(); |
931c8cc2 PM |
12277 | |
12278 | for (pass = 0; pass < 4; pass++) { | |
12279 | tcg_res[pass] = tcg_temp_new_i32(); | |
12280 | ||
12281 | read_vec_element_i32(s, tcg_res[pass], rn, srcelt + pass, MO_16); | |
12282 | gen_helper_vfp_fcvt_f16_to_f32(tcg_res[pass], tcg_res[pass], | |
486624fc | 12283 | fpst, ahp); |
931c8cc2 PM |
12284 | } |
12285 | for (pass = 0; pass < 4; pass++) { | |
12286 | write_vec_element_i32(s, tcg_res[pass], rd, pass, MO_32); | |
12287 | tcg_temp_free_i32(tcg_res[pass]); | |
12288 | } | |
486624fc AB |
12289 | |
12290 | tcg_temp_free_ptr(fpst); | |
12291 | tcg_temp_free_i32(ahp); | |
931c8cc2 PM |
12292 | } |
12293 | } | |
12294 | ||
39d82118 AB |
12295 | static void handle_rev(DisasContext *s, int opcode, bool u, |
12296 | bool is_q, int size, int rn, int rd) | |
12297 | { | |
12298 | int op = (opcode << 1) | u; | |
12299 | int opsz = op + size; | |
12300 | int grp_size = 3 - opsz; | |
12301 | int dsize = is_q ? 128 : 64; | |
12302 | int i; | |
12303 | ||
12304 | if (opsz >= 3) { | |
12305 | unallocated_encoding(s); | |
12306 | return; | |
12307 | } | |
12308 | ||
8c6afa6a PM |
12309 | if (!fp_access_check(s)) { |
12310 | return; | |
12311 | } | |
12312 | ||
39d82118 AB |
12313 | if (size == 0) { |
12314 | /* Special case bytes, use bswap op on each group of elements */ | |
12315 | int groups = dsize / (8 << grp_size); | |
12316 | ||
12317 | for (i = 0; i < groups; i++) { | |
12318 | TCGv_i64 tcg_tmp = tcg_temp_new_i64(); | |
12319 | ||
12320 | read_vec_element(s, tcg_tmp, rn, i, grp_size); | |
12321 | switch (grp_size) { | |
12322 | case MO_16: | |
12323 | tcg_gen_bswap16_i64(tcg_tmp, tcg_tmp); | |
12324 | break; | |
12325 | case MO_32: | |
12326 | tcg_gen_bswap32_i64(tcg_tmp, tcg_tmp); | |
12327 | break; | |
12328 | case MO_64: | |
12329 | tcg_gen_bswap64_i64(tcg_tmp, tcg_tmp); | |
12330 | break; | |
12331 | default: | |
12332 | g_assert_not_reached(); | |
12333 | } | |
12334 | write_vec_element(s, tcg_tmp, rd, i, grp_size); | |
12335 | tcg_temp_free_i64(tcg_tmp); | |
12336 | } | |
4ff55bcb | 12337 | clear_vec_high(s, is_q, rd); |
39d82118 AB |
12338 | } else { |
12339 | int revmask = (1 << grp_size) - 1; | |
12340 | int esize = 8 << size; | |
12341 | int elements = dsize / esize; | |
12342 | TCGv_i64 tcg_rn = tcg_temp_new_i64(); | |
12343 | TCGv_i64 tcg_rd = tcg_const_i64(0); | |
12344 | TCGv_i64 tcg_rd_hi = tcg_const_i64(0); | |
12345 | ||
12346 | for (i = 0; i < elements; i++) { | |
12347 | int e_rev = (i & 0xf) ^ revmask; | |
12348 | int off = e_rev * esize; | |
12349 | read_vec_element(s, tcg_rn, rn, i, size); | |
12350 | if (off >= 64) { | |
12351 | tcg_gen_deposit_i64(tcg_rd_hi, tcg_rd_hi, | |
12352 | tcg_rn, off - 64, esize); | |
12353 | } else { | |
12354 | tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_rn, off, esize); | |
12355 | } | |
12356 | } | |
12357 | write_vec_element(s, tcg_rd, rd, 0, MO_64); | |
12358 | write_vec_element(s, tcg_rd_hi, rd, 1, MO_64); | |
12359 | ||
12360 | tcg_temp_free_i64(tcg_rd_hi); | |
12361 | tcg_temp_free_i64(tcg_rd); | |
12362 | tcg_temp_free_i64(tcg_rn); | |
12363 | } | |
12364 | } | |
12365 | ||
6781fa11 PM |
12366 | static void handle_2misc_pairwise(DisasContext *s, int opcode, bool u, |
12367 | bool is_q, int size, int rn, int rd) | |
12368 | { | |
12369 | /* Implement the pairwise operations from 2-misc: | |
12370 | * SADDLP, UADDLP, SADALP, UADALP. | |
12371 | * These all add pairs of elements in the input to produce a | |
12372 | * double-width result element in the output (possibly accumulating). | |
12373 | */ | |
12374 | bool accum = (opcode == 0x6); | |
12375 | int maxpass = is_q ? 2 : 1; | |
12376 | int pass; | |
12377 | TCGv_i64 tcg_res[2]; | |
12378 | ||
12379 | if (size == 2) { | |
12380 | /* 32 + 32 -> 64 op */ | |
14776ab5 | 12381 | MemOp memop = size + (u ? 0 : MO_SIGN); |
6781fa11 PM |
12382 | |
12383 | for (pass = 0; pass < maxpass; pass++) { | |
12384 | TCGv_i64 tcg_op1 = tcg_temp_new_i64(); | |
12385 | TCGv_i64 tcg_op2 = tcg_temp_new_i64(); | |
12386 | ||
12387 | tcg_res[pass] = tcg_temp_new_i64(); | |
12388 | ||
12389 | read_vec_element(s, tcg_op1, rn, pass * 2, memop); | |
12390 | read_vec_element(s, tcg_op2, rn, pass * 2 + 1, memop); | |
12391 | tcg_gen_add_i64(tcg_res[pass], tcg_op1, tcg_op2); | |
12392 | if (accum) { | |
12393 | read_vec_element(s, tcg_op1, rd, pass, MO_64); | |
12394 | tcg_gen_add_i64(tcg_res[pass], tcg_res[pass], tcg_op1); | |
12395 | } | |
12396 | ||
12397 | tcg_temp_free_i64(tcg_op1); | |
12398 | tcg_temp_free_i64(tcg_op2); | |
12399 | } | |
12400 | } else { | |
12401 | for (pass = 0; pass < maxpass; pass++) { | |
12402 | TCGv_i64 tcg_op = tcg_temp_new_i64(); | |
039f4e80 PM |
12403 | NeonGenOne64OpFn *genfn; |
12404 | static NeonGenOne64OpFn * const fns[2][2] = { | |
6781fa11 PM |
12405 | { gen_helper_neon_addlp_s8, gen_helper_neon_addlp_u8 }, |
12406 | { gen_helper_neon_addlp_s16, gen_helper_neon_addlp_u16 }, | |
12407 | }; | |
12408 | ||
12409 | genfn = fns[size][u]; | |
12410 | ||
12411 | tcg_res[pass] = tcg_temp_new_i64(); | |
12412 | ||
12413 | read_vec_element(s, tcg_op, rn, pass, MO_64); | |
12414 | genfn(tcg_res[pass], tcg_op); | |
12415 | ||
12416 | if (accum) { | |
12417 | read_vec_element(s, tcg_op, rd, pass, MO_64); | |
12418 | if (size == 0) { | |
12419 | gen_helper_neon_addl_u16(tcg_res[pass], | |
12420 | tcg_res[pass], tcg_op); | |
12421 | } else { | |
12422 | gen_helper_neon_addl_u32(tcg_res[pass], | |
12423 | tcg_res[pass], tcg_op); | |
12424 | } | |
12425 | } | |
12426 | tcg_temp_free_i64(tcg_op); | |
12427 | } | |
12428 | } | |
12429 | if (!is_q) { | |
12430 | tcg_res[1] = tcg_const_i64(0); | |
12431 | } | |
12432 | for (pass = 0; pass < 2; pass++) { | |
12433 | write_vec_element(s, tcg_res[pass], rd, pass, MO_64); | |
12434 | tcg_temp_free_i64(tcg_res[pass]); | |
12435 | } | |
12436 | } | |
12437 | ||
73a81d10 PM |
12438 | static void handle_shll(DisasContext *s, bool is_q, int size, int rn, int rd) |
12439 | { | |
12440 | /* Implement SHLL and SHLL2 */ | |
12441 | int pass; | |
12442 | int part = is_q ? 2 : 0; | |
12443 | TCGv_i64 tcg_res[2]; | |
12444 | ||
12445 | for (pass = 0; pass < 2; pass++) { | |
12446 | static NeonGenWidenFn * const widenfns[3] = { | |
12447 | gen_helper_neon_widen_u8, | |
12448 | gen_helper_neon_widen_u16, | |
12449 | tcg_gen_extu_i32_i64, | |
12450 | }; | |
12451 | NeonGenWidenFn *widenfn = widenfns[size]; | |
12452 | TCGv_i32 tcg_op = tcg_temp_new_i32(); | |
12453 | ||
12454 | read_vec_element_i32(s, tcg_op, rn, part + pass, MO_32); | |
12455 | tcg_res[pass] = tcg_temp_new_i64(); | |
12456 | widenfn(tcg_res[pass], tcg_op); | |
12457 | tcg_gen_shli_i64(tcg_res[pass], tcg_res[pass], 8 << size); | |
12458 | ||
12459 | tcg_temp_free_i32(tcg_op); | |
12460 | } | |
12461 | ||
12462 | for (pass = 0; pass < 2; pass++) { | |
12463 | write_vec_element(s, tcg_res[pass], rd, pass, MO_64); | |
12464 | tcg_temp_free_i64(tcg_res[pass]); | |
12465 | } | |
12466 | } | |
12467 | ||
4ce31af4 | 12468 | /* AdvSIMD two reg misc |
384b26fb AB |
12469 | * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0 |
12470 | * +---+---+---+-----------+------+-----------+--------+-----+------+------+ | |
12471 | * | 0 | Q | U | 0 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd | | |
12472 | * +---+---+---+-----------+------+-----------+--------+-----+------+------+ | |
12473 | */ | |
12474 | static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn) | |
12475 | { | |
45aecc6d PM |
12476 | int size = extract32(insn, 22, 2); |
12477 | int opcode = extract32(insn, 12, 5); | |
12478 | bool u = extract32(insn, 29, 1); | |
12479 | bool is_q = extract32(insn, 30, 1); | |
94b6c911 PM |
12480 | int rn = extract32(insn, 5, 5); |
12481 | int rd = extract32(insn, 0, 5); | |
04c7c6c2 PM |
12482 | bool need_fpstatus = false; |
12483 | bool need_rmode = false; | |
12484 | int rmode = -1; | |
12485 | TCGv_i32 tcg_rmode; | |
12486 | TCGv_ptr tcg_fpstatus; | |
45aecc6d PM |
12487 | |
12488 | switch (opcode) { | |
12489 | case 0x0: /* REV64, REV32 */ | |
12490 | case 0x1: /* REV16 */ | |
39d82118 | 12491 | handle_rev(s, opcode, u, is_q, size, rn, rd); |
45aecc6d | 12492 | return; |
86cbc418 PM |
12493 | case 0x5: /* CNT, NOT, RBIT */ |
12494 | if (u && size == 0) { | |
377ef731 | 12495 | /* NOT */ |
86cbc418 PM |
12496 | break; |
12497 | } else if (u && size == 1) { | |
12498 | /* RBIT */ | |
12499 | break; | |
12500 | } else if (!u && size == 0) { | |
12501 | /* CNT */ | |
12502 | break; | |
45aecc6d | 12503 | } |
86cbc418 | 12504 | unallocated_encoding(s); |
45aecc6d | 12505 | return; |
d980fd59 PM |
12506 | case 0x12: /* XTN, XTN2, SQXTUN, SQXTUN2 */ |
12507 | case 0x14: /* SQXTN, SQXTN2, UQXTN, UQXTN2 */ | |
12508 | if (size == 3) { | |
12509 | unallocated_encoding(s); | |
12510 | return; | |
12511 | } | |
8c6afa6a PM |
12512 | if (!fp_access_check(s)) { |
12513 | return; | |
12514 | } | |
12515 | ||
5201c136 | 12516 | handle_2misc_narrow(s, false, opcode, u, is_q, size, rn, rd); |
d980fd59 | 12517 | return; |
45aecc6d | 12518 | case 0x4: /* CLS, CLZ */ |
b05c3068 AB |
12519 | if (size == 3) { |
12520 | unallocated_encoding(s); | |
12521 | return; | |
12522 | } | |
12523 | break; | |
12524 | case 0x2: /* SADDLP, UADDLP */ | |
45aecc6d | 12525 | case 0x6: /* SADALP, UADALP */ |
45aecc6d PM |
12526 | if (size == 3) { |
12527 | unallocated_encoding(s); | |
12528 | return; | |
12529 | } | |
8c6afa6a PM |
12530 | if (!fp_access_check(s)) { |
12531 | return; | |
12532 | } | |
6781fa11 | 12533 | handle_2misc_pairwise(s, opcode, u, is_q, size, rn, rd); |
45aecc6d PM |
12534 | return; |
12535 | case 0x13: /* SHLL, SHLL2 */ | |
12536 | if (u == 0 || size == 3) { | |
12537 | unallocated_encoding(s); | |
12538 | return; | |
12539 | } | |
8c6afa6a PM |
12540 | if (!fp_access_check(s)) { |
12541 | return; | |
12542 | } | |
73a81d10 | 12543 | handle_shll(s, is_q, size, rn, rd); |
45aecc6d PM |
12544 | return; |
12545 | case 0xa: /* CMLT */ | |
12546 | if (u == 1) { | |
12547 | unallocated_encoding(s); | |
12548 | return; | |
12549 | } | |
12550 | /* fall through */ | |
45aecc6d PM |
12551 | case 0x8: /* CMGT, CMGE */ |
12552 | case 0x9: /* CMEQ, CMLE */ | |
12553 | case 0xb: /* ABS, NEG */ | |
94b6c911 PM |
12554 | if (size == 3 && !is_q) { |
12555 | unallocated_encoding(s); | |
12556 | return; | |
12557 | } | |
12558 | break; | |
12559 | case 0x3: /* SUQADD, USQADD */ | |
09e03735 AB |
12560 | if (size == 3 && !is_q) { |
12561 | unallocated_encoding(s); | |
12562 | return; | |
12563 | } | |
8c6afa6a PM |
12564 | if (!fp_access_check(s)) { |
12565 | return; | |
12566 | } | |
09e03735 AB |
12567 | handle_2misc_satacc(s, false, u, is_q, size, rn, rd); |
12568 | return; | |
94b6c911 | 12569 | case 0x7: /* SQABS, SQNEG */ |
45aecc6d PM |
12570 | if (size == 3 && !is_q) { |
12571 | unallocated_encoding(s); | |
12572 | return; | |
12573 | } | |
0a79bc87 | 12574 | break; |
45aecc6d | 12575 | case 0xc ... 0xf: |
6bea2563 | 12576 | case 0x16 ... 0x1f: |
45aecc6d PM |
12577 | { |
12578 | /* Floating point: U, size[1] and opcode indicate operation; | |
12579 | * size[0] indicates single or double precision. | |
12580 | */ | |
10113b69 | 12581 | int is_double = extract32(size, 0, 1); |
45aecc6d | 12582 | opcode |= (extract32(size, 1, 1) << 5) | (u << 6); |
10113b69 | 12583 | size = is_double ? 3 : 2; |
45aecc6d | 12584 | switch (opcode) { |
f93d0138 PM |
12585 | case 0x2f: /* FABS */ |
12586 | case 0x6f: /* FNEG */ | |
12587 | if (size == 3 && !is_q) { | |
12588 | unallocated_encoding(s); | |
12589 | return; | |
12590 | } | |
12591 | break; | |
10113b69 AB |
12592 | case 0x1d: /* SCVTF */ |
12593 | case 0x5d: /* UCVTF */ | |
12594 | { | |
12595 | bool is_signed = (opcode == 0x1d) ? true : false; | |
12596 | int elements = is_double ? 2 : is_q ? 4 : 2; | |
12597 | if (is_double && !is_q) { | |
12598 | unallocated_encoding(s); | |
12599 | return; | |
12600 | } | |
8c6afa6a PM |
12601 | if (!fp_access_check(s)) { |
12602 | return; | |
12603 | } | |
10113b69 AB |
12604 | handle_simd_intfp_conv(s, rd, rn, elements, is_signed, 0, size); |
12605 | return; | |
12606 | } | |
8908f4d1 AB |
12607 | case 0x2c: /* FCMGT (zero) */ |
12608 | case 0x2d: /* FCMEQ (zero) */ | |
12609 | case 0x2e: /* FCMLT (zero) */ | |
12610 | case 0x6c: /* FCMGE (zero) */ | |
12611 | case 0x6d: /* FCMLE (zero) */ | |
12612 | if (size == 3 && !is_q) { | |
12613 | unallocated_encoding(s); | |
12614 | return; | |
12615 | } | |
12616 | handle_2misc_fcmp_zero(s, opcode, false, u, is_q, size, rn, rd); | |
12617 | return; | |
f612537e AB |
12618 | case 0x7f: /* FSQRT */ |
12619 | if (size == 3 && !is_q) { | |
12620 | unallocated_encoding(s); | |
12621 | return; | |
12622 | } | |
12623 | break; | |
04c7c6c2 PM |
12624 | case 0x1a: /* FCVTNS */ |
12625 | case 0x1b: /* FCVTMS */ | |
12626 | case 0x3a: /* FCVTPS */ | |
12627 | case 0x3b: /* FCVTZS */ | |
12628 | case 0x5a: /* FCVTNU */ | |
12629 | case 0x5b: /* FCVTMU */ | |
12630 | case 0x7a: /* FCVTPU */ | |
12631 | case 0x7b: /* FCVTZU */ | |
12632 | need_fpstatus = true; | |
12633 | need_rmode = true; | |
12634 | rmode = extract32(opcode, 5, 1) | (extract32(opcode, 0, 1) << 1); | |
12635 | if (size == 3 && !is_q) { | |
12636 | unallocated_encoding(s); | |
12637 | return; | |
12638 | } | |
12639 | break; | |
12640 | case 0x5c: /* FCVTAU */ | |
12641 | case 0x1c: /* FCVTAS */ | |
12642 | need_fpstatus = true; | |
12643 | need_rmode = true; | |
12644 | rmode = FPROUNDING_TIEAWAY; | |
12645 | if (size == 3 && !is_q) { | |
12646 | unallocated_encoding(s); | |
12647 | return; | |
12648 | } | |
12649 | break; | |
b6d4443a AB |
12650 | case 0x3c: /* URECPE */ |
12651 | if (size == 3) { | |
12652 | unallocated_encoding(s); | |
12653 | return; | |
12654 | } | |
12655 | /* fall through */ | |
12656 | case 0x3d: /* FRECPE */ | |
c2fb418e AB |
12657 | case 0x7d: /* FRSQRTE */ |
12658 | if (size == 3 && !is_q) { | |
12659 | unallocated_encoding(s); | |
12660 | return; | |
12661 | } | |
8c6afa6a PM |
12662 | if (!fp_access_check(s)) { |
12663 | return; | |
12664 | } | |
b6d4443a AB |
12665 | handle_2misc_reciprocal(s, opcode, false, u, is_q, size, rn, rd); |
12666 | return; | |
5553955e PM |
12667 | case 0x56: /* FCVTXN, FCVTXN2 */ |
12668 | if (size == 2) { | |
12669 | unallocated_encoding(s); | |
12670 | return; | |
12671 | } | |
12672 | /* fall through */ | |
45aecc6d | 12673 | case 0x16: /* FCVTN, FCVTN2 */ |
261a5b4d PM |
12674 | /* handle_2misc_narrow does a 2*size -> size operation, but these |
12675 | * instructions encode the source size rather than dest size. | |
12676 | */ | |
8c6afa6a PM |
12677 | if (!fp_access_check(s)) { |
12678 | return; | |
12679 | } | |
5201c136 | 12680 | handle_2misc_narrow(s, false, opcode, 0, is_q, size - 1, rn, rd); |
261a5b4d | 12681 | return; |
45aecc6d | 12682 | case 0x17: /* FCVTL, FCVTL2 */ |
8c6afa6a PM |
12683 | if (!fp_access_check(s)) { |
12684 | return; | |
12685 | } | |
931c8cc2 PM |
12686 | handle_2misc_widening(s, opcode, is_q, size, rn, rd); |
12687 | return; | |
45aecc6d PM |
12688 | case 0x18: /* FRINTN */ |
12689 | case 0x19: /* FRINTM */ | |
45aecc6d PM |
12690 | case 0x38: /* FRINTP */ |
12691 | case 0x39: /* FRINTZ */ | |
03df01ed PM |
12692 | need_rmode = true; |
12693 | rmode = extract32(opcode, 5, 1) | (extract32(opcode, 0, 1) << 1); | |
12694 | /* fall through */ | |
12695 | case 0x59: /* FRINTX */ | |
12696 | case 0x79: /* FRINTI */ | |
12697 | need_fpstatus = true; | |
12698 | if (size == 3 && !is_q) { | |
12699 | unallocated_encoding(s); | |
12700 | return; | |
12701 | } | |
12702 | break; | |
12703 | case 0x58: /* FRINTA */ | |
12704 | need_rmode = true; | |
12705 | rmode = FPROUNDING_TIEAWAY; | |
12706 | need_fpstatus = true; | |
12707 | if (size == 3 && !is_q) { | |
12708 | unallocated_encoding(s); | |
12709 | return; | |
12710 | } | |
12711 | break; | |
45aecc6d | 12712 | case 0x7c: /* URSQRTE */ |
c2fb418e AB |
12713 | if (size == 3) { |
12714 | unallocated_encoding(s); | |
12715 | return; | |
12716 | } | |
c2fb418e | 12717 | break; |
6bea2563 RH |
12718 | case 0x1e: /* FRINT32Z */ |
12719 | case 0x1f: /* FRINT64Z */ | |
12720 | need_rmode = true; | |
12721 | rmode = FPROUNDING_ZERO; | |
12722 | /* fall through */ | |
12723 | case 0x5e: /* FRINT32X */ | |
12724 | case 0x5f: /* FRINT64X */ | |
12725 | need_fpstatus = true; | |
12726 | if ((size == 3 && !is_q) || !dc_isar_feature(aa64_frint, s)) { | |
12727 | unallocated_encoding(s); | |
12728 | return; | |
12729 | } | |
12730 | break; | |
45aecc6d PM |
12731 | default: |
12732 | unallocated_encoding(s); | |
12733 | return; | |
12734 | } | |
12735 | break; | |
12736 | } | |
12737 | default: | |
12738 | unallocated_encoding(s); | |
12739 | return; | |
12740 | } | |
94b6c911 | 12741 | |
8c6afa6a PM |
12742 | if (!fp_access_check(s)) { |
12743 | return; | |
12744 | } | |
12745 | ||
9b049916 | 12746 | if (need_fpstatus || need_rmode) { |
cdfb22bb | 12747 | tcg_fpstatus = fpstatus_ptr(FPST_FPCR); |
04c7c6c2 | 12748 | } else { |
f764718d | 12749 | tcg_fpstatus = NULL; |
04c7c6c2 PM |
12750 | } |
12751 | if (need_rmode) { | |
12752 | tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode)); | |
9b049916 | 12753 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); |
04c7c6c2 | 12754 | } else { |
f764718d | 12755 | tcg_rmode = NULL; |
04c7c6c2 PM |
12756 | } |
12757 | ||
377ef731 RH |
12758 | switch (opcode) { |
12759 | case 0x5: | |
12760 | if (u && size == 0) { /* NOT */ | |
12761 | gen_gvec_fn2(s, is_q, rd, rn, tcg_gen_gvec_not, 0); | |
12762 | return; | |
12763 | } | |
12764 | break; | |
6b375d35 | 12765 | case 0x8: /* CMGT, CMGE */ |
69d5e2bf RH |
12766 | if (u) { |
12767 | gen_gvec_fn2(s, is_q, rd, rn, gen_gvec_cge0, size); | |
12768 | } else { | |
12769 | gen_gvec_fn2(s, is_q, rd, rn, gen_gvec_cgt0, size); | |
12770 | } | |
6b375d35 RH |
12771 | return; |
12772 | case 0x9: /* CMEQ, CMLE */ | |
69d5e2bf RH |
12773 | if (u) { |
12774 | gen_gvec_fn2(s, is_q, rd, rn, gen_gvec_cle0, size); | |
12775 | } else { | |
12776 | gen_gvec_fn2(s, is_q, rd, rn, gen_gvec_ceq0, size); | |
12777 | } | |
6b375d35 RH |
12778 | return; |
12779 | case 0xa: /* CMLT */ | |
69d5e2bf | 12780 | gen_gvec_fn2(s, is_q, rd, rn, gen_gvec_clt0, size); |
6b375d35 | 12781 | return; |
377ef731 | 12782 | case 0xb: |
4e027a71 | 12783 | if (u) { /* ABS, NEG */ |
377ef731 | 12784 | gen_gvec_fn2(s, is_q, rd, rn, tcg_gen_gvec_neg, size); |
4e027a71 RH |
12785 | } else { |
12786 | gen_gvec_fn2(s, is_q, rd, rn, tcg_gen_gvec_abs, size); | |
377ef731 | 12787 | } |
4e027a71 | 12788 | return; |
377ef731 RH |
12789 | } |
12790 | ||
94b6c911 PM |
12791 | if (size == 3) { |
12792 | /* All 64-bit element operations can be shared with scalar 2misc */ | |
12793 | int pass; | |
12794 | ||
a8766e31 RH |
12795 | /* Coverity claims (size == 3 && !is_q) has been eliminated |
12796 | * from all paths leading to here. | |
12797 | */ | |
12798 | tcg_debug_assert(is_q); | |
12799 | for (pass = 0; pass < 2; pass++) { | |
94b6c911 PM |
12800 | TCGv_i64 tcg_op = tcg_temp_new_i64(); |
12801 | TCGv_i64 tcg_res = tcg_temp_new_i64(); | |
12802 | ||
12803 | read_vec_element(s, tcg_op, rn, pass, MO_64); | |
12804 | ||
04c7c6c2 PM |
12805 | handle_2misc_64(s, opcode, u, tcg_res, tcg_op, |
12806 | tcg_rmode, tcg_fpstatus); | |
94b6c911 PM |
12807 | |
12808 | write_vec_element(s, tcg_res, rd, pass, MO_64); | |
12809 | ||
12810 | tcg_temp_free_i64(tcg_res); | |
12811 | tcg_temp_free_i64(tcg_op); | |
12812 | } | |
12813 | } else { | |
12814 | int pass; | |
12815 | ||
12816 | for (pass = 0; pass < (is_q ? 4 : 2); pass++) { | |
12817 | TCGv_i32 tcg_op = tcg_temp_new_i32(); | |
12818 | TCGv_i32 tcg_res = tcg_temp_new_i32(); | |
94b6c911 PM |
12819 | |
12820 | read_vec_element_i32(s, tcg_op, rn, pass, MO_32); | |
12821 | ||
12822 | if (size == 2) { | |
12823 | /* Special cases for 32 bit elements */ | |
12824 | switch (opcode) { | |
b05c3068 AB |
12825 | case 0x4: /* CLS */ |
12826 | if (u) { | |
7539a012 | 12827 | tcg_gen_clzi_i32(tcg_res, tcg_op, 32); |
b05c3068 | 12828 | } else { |
bc21dbcc | 12829 | tcg_gen_clrsb_i32(tcg_res, tcg_op); |
b05c3068 AB |
12830 | } |
12831 | break; | |
0a79bc87 AB |
12832 | case 0x7: /* SQABS, SQNEG */ |
12833 | if (u) { | |
12834 | gen_helper_neon_qneg_s32(tcg_res, cpu_env, tcg_op); | |
12835 | } else { | |
12836 | gen_helper_neon_qabs_s32(tcg_res, cpu_env, tcg_op); | |
12837 | } | |
12838 | break; | |
f93d0138 PM |
12839 | case 0x2f: /* FABS */ |
12840 | gen_helper_vfp_abss(tcg_res, tcg_op); | |
12841 | break; | |
12842 | case 0x6f: /* FNEG */ | |
12843 | gen_helper_vfp_negs(tcg_res, tcg_op); | |
12844 | break; | |
f612537e AB |
12845 | case 0x7f: /* FSQRT */ |
12846 | gen_helper_vfp_sqrts(tcg_res, tcg_op, cpu_env); | |
12847 | break; | |
04c7c6c2 PM |
12848 | case 0x1a: /* FCVTNS */ |
12849 | case 0x1b: /* FCVTMS */ | |
12850 | case 0x1c: /* FCVTAS */ | |
12851 | case 0x3a: /* FCVTPS */ | |
12852 | case 0x3b: /* FCVTZS */ | |
12853 | { | |
12854 | TCGv_i32 tcg_shift = tcg_const_i32(0); | |
12855 | gen_helper_vfp_tosls(tcg_res, tcg_op, | |
12856 | tcg_shift, tcg_fpstatus); | |
12857 | tcg_temp_free_i32(tcg_shift); | |
12858 | break; | |
12859 | } | |
12860 | case 0x5a: /* FCVTNU */ | |
12861 | case 0x5b: /* FCVTMU */ | |
12862 | case 0x5c: /* FCVTAU */ | |
12863 | case 0x7a: /* FCVTPU */ | |
12864 | case 0x7b: /* FCVTZU */ | |
12865 | { | |
12866 | TCGv_i32 tcg_shift = tcg_const_i32(0); | |
12867 | gen_helper_vfp_touls(tcg_res, tcg_op, | |
12868 | tcg_shift, tcg_fpstatus); | |
12869 | tcg_temp_free_i32(tcg_shift); | |
12870 | break; | |
12871 | } | |
03df01ed PM |
12872 | case 0x18: /* FRINTN */ |
12873 | case 0x19: /* FRINTM */ | |
12874 | case 0x38: /* FRINTP */ | |
12875 | case 0x39: /* FRINTZ */ | |
12876 | case 0x58: /* FRINTA */ | |
12877 | case 0x79: /* FRINTI */ | |
12878 | gen_helper_rints(tcg_res, tcg_op, tcg_fpstatus); | |
12879 | break; | |
12880 | case 0x59: /* FRINTX */ | |
12881 | gen_helper_rints_exact(tcg_res, tcg_op, tcg_fpstatus); | |
12882 | break; | |
c2fb418e | 12883 | case 0x7c: /* URSQRTE */ |
fe6fb4be | 12884 | gen_helper_rsqrte_u32(tcg_res, tcg_op); |
c2fb418e | 12885 | break; |
6bea2563 RH |
12886 | case 0x1e: /* FRINT32Z */ |
12887 | case 0x5e: /* FRINT32X */ | |
12888 | gen_helper_frint32_s(tcg_res, tcg_op, tcg_fpstatus); | |
12889 | break; | |
12890 | case 0x1f: /* FRINT64Z */ | |
12891 | case 0x5f: /* FRINT64X */ | |
12892 | gen_helper_frint64_s(tcg_res, tcg_op, tcg_fpstatus); | |
12893 | break; | |
94b6c911 PM |
12894 | default: |
12895 | g_assert_not_reached(); | |
12896 | } | |
12897 | } else { | |
12898 | /* Use helpers for 8 and 16 bit elements */ | |
12899 | switch (opcode) { | |
86cbc418 PM |
12900 | case 0x5: /* CNT, RBIT */ |
12901 | /* For these two insns size is part of the opcode specifier | |
12902 | * (handled earlier); they always operate on byte elements. | |
12903 | */ | |
12904 | if (u) { | |
12905 | gen_helper_neon_rbit_u8(tcg_res, tcg_op); | |
12906 | } else { | |
12907 | gen_helper_neon_cnt_u8(tcg_res, tcg_op); | |
12908 | } | |
12909 | break; | |
0a79bc87 AB |
12910 | case 0x7: /* SQABS, SQNEG */ |
12911 | { | |
12912 | NeonGenOneOpEnvFn *genfn; | |
12913 | static NeonGenOneOpEnvFn * const fns[2][2] = { | |
12914 | { gen_helper_neon_qabs_s8, gen_helper_neon_qneg_s8 }, | |
12915 | { gen_helper_neon_qabs_s16, gen_helper_neon_qneg_s16 }, | |
12916 | }; | |
12917 | genfn = fns[size][u]; | |
12918 | genfn(tcg_res, cpu_env, tcg_op); | |
12919 | break; | |
12920 | } | |
b05c3068 AB |
12921 | case 0x4: /* CLS, CLZ */ |
12922 | if (u) { | |
12923 | if (size == 0) { | |
12924 | gen_helper_neon_clz_u8(tcg_res, tcg_op); | |
12925 | } else { | |
12926 | gen_helper_neon_clz_u16(tcg_res, tcg_op); | |
12927 | } | |
12928 | } else { | |
12929 | if (size == 0) { | |
12930 | gen_helper_neon_cls_s8(tcg_res, tcg_op); | |
12931 | } else { | |
12932 | gen_helper_neon_cls_s16(tcg_res, tcg_op); | |
12933 | } | |
12934 | } | |
12935 | break; | |
94b6c911 PM |
12936 | default: |
12937 | g_assert_not_reached(); | |
12938 | } | |
12939 | } | |
12940 | ||
12941 | write_vec_element_i32(s, tcg_res, rd, pass, MO_32); | |
12942 | ||
12943 | tcg_temp_free_i32(tcg_res); | |
12944 | tcg_temp_free_i32(tcg_op); | |
12945 | } | |
12946 | } | |
4ff55bcb | 12947 | clear_vec_high(s, is_q, rd); |
04c7c6c2 PM |
12948 | |
12949 | if (need_rmode) { | |
9b049916 | 12950 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); |
04c7c6c2 PM |
12951 | tcg_temp_free_i32(tcg_rmode); |
12952 | } | |
12953 | if (need_fpstatus) { | |
12954 | tcg_temp_free_ptr(tcg_fpstatus); | |
12955 | } | |
384b26fb AB |
12956 | } |
12957 | ||
5d432be6 AB |
12958 | /* AdvSIMD [scalar] two register miscellaneous (FP16) |
12959 | * | |
12960 | * 31 30 29 28 27 24 23 22 21 17 16 12 11 10 9 5 4 0 | |
12961 | * +---+---+---+---+---------+---+-------------+--------+-----+------+------+ | |
12962 | * | 0 | Q | U | S | 1 1 1 0 | a | 1 1 1 1 0 0 | opcode | 1 0 | Rn | Rd | | |
12963 | * +---+---+---+---+---------+---+-------------+--------+-----+------+------+ | |
12964 | * mask: 1000 1111 0111 1110 0000 1100 0000 0000 0x8f7e 0c00 | |
12965 | * val: 0000 1110 0111 1000 0000 1000 0000 0000 0x0e78 0800 | |
12966 | * | |
12967 | * This actually covers two groups where scalar access is governed by | |
12968 | * bit 28. A bunch of the instructions (float to integral) only exist | |
12969 | * in the vector form and are un-allocated for the scalar decode. Also | |
12970 | * in the scalar decode Q is always 1. | |
12971 | */ | |
12972 | static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn) | |
12973 | { | |
6109aea2 AB |
12974 | int fpop, opcode, a, u; |
12975 | int rn, rd; | |
12976 | bool is_q; | |
12977 | bool is_scalar; | |
12978 | bool only_in_vector = false; | |
12979 | ||
12980 | int pass; | |
12981 | TCGv_i32 tcg_rmode = NULL; | |
12982 | TCGv_ptr tcg_fpstatus = NULL; | |
12983 | bool need_rmode = false; | |
15f8a233 | 12984 | bool need_fpst = true; |
6109aea2 | 12985 | int rmode; |
5d432be6 | 12986 | |
5763190f | 12987 | if (!dc_isar_feature(aa64_fp16, s)) { |
5d432be6 AB |
12988 | unallocated_encoding(s); |
12989 | return; | |
12990 | } | |
12991 | ||
6109aea2 AB |
12992 | rd = extract32(insn, 0, 5); |
12993 | rn = extract32(insn, 5, 5); | |
5d432be6 | 12994 | |
5d432be6 | 12995 | a = extract32(insn, 23, 1); |
6109aea2 AB |
12996 | u = extract32(insn, 29, 1); |
12997 | is_scalar = extract32(insn, 28, 1); | |
12998 | is_q = extract32(insn, 30, 1); | |
12999 | ||
13000 | opcode = extract32(insn, 12, 5); | |
5d432be6 | 13001 | fpop = deposit32(opcode, 5, 1, a); |
6109aea2 | 13002 | fpop = deposit32(fpop, 6, 1, u); |
5d432be6 AB |
13003 | |
13004 | switch (fpop) { | |
93193190 AB |
13005 | case 0x1d: /* SCVTF */ |
13006 | case 0x5d: /* UCVTF */ | |
13007 | { | |
13008 | int elements; | |
13009 | ||
13010 | if (is_scalar) { | |
13011 | elements = 1; | |
13012 | } else { | |
13013 | elements = (is_q ? 8 : 4); | |
13014 | } | |
13015 | ||
13016 | if (!fp_access_check(s)) { | |
13017 | return; | |
13018 | } | |
13019 | handle_simd_intfp_conv(s, rd, rn, elements, !u, 0, MO_16); | |
13020 | return; | |
13021 | } | |
7d4dd1a7 AB |
13022 | break; |
13023 | case 0x2c: /* FCMGT (zero) */ | |
13024 | case 0x2d: /* FCMEQ (zero) */ | |
13025 | case 0x2e: /* FCMLT (zero) */ | |
13026 | case 0x6c: /* FCMGE (zero) */ | |
13027 | case 0x6d: /* FCMLE (zero) */ | |
13028 | handle_2misc_fcmp_zero(s, fpop, is_scalar, 0, is_q, MO_16, rn, rd); | |
13029 | return; | |
fbd06e1e | 13030 | case 0x3d: /* FRECPE */ |
98695028 | 13031 | case 0x3f: /* FRECPX */ |
fbd06e1e | 13032 | break; |
6109aea2 AB |
13033 | case 0x18: /* FRINTN */ |
13034 | need_rmode = true; | |
13035 | only_in_vector = true; | |
13036 | rmode = FPROUNDING_TIEEVEN; | |
13037 | break; | |
13038 | case 0x19: /* FRINTM */ | |
13039 | need_rmode = true; | |
13040 | only_in_vector = true; | |
13041 | rmode = FPROUNDING_NEGINF; | |
13042 | break; | |
13043 | case 0x38: /* FRINTP */ | |
13044 | need_rmode = true; | |
13045 | only_in_vector = true; | |
13046 | rmode = FPROUNDING_POSINF; | |
13047 | break; | |
13048 | case 0x39: /* FRINTZ */ | |
13049 | need_rmode = true; | |
13050 | only_in_vector = true; | |
13051 | rmode = FPROUNDING_ZERO; | |
13052 | break; | |
13053 | case 0x58: /* FRINTA */ | |
13054 | need_rmode = true; | |
13055 | only_in_vector = true; | |
13056 | rmode = FPROUNDING_TIEAWAY; | |
13057 | break; | |
13058 | case 0x59: /* FRINTX */ | |
13059 | case 0x79: /* FRINTI */ | |
13060 | only_in_vector = true; | |
13061 | /* current rounding mode */ | |
13062 | break; | |
2df58130 AB |
13063 | case 0x1a: /* FCVTNS */ |
13064 | need_rmode = true; | |
13065 | rmode = FPROUNDING_TIEEVEN; | |
13066 | break; | |
13067 | case 0x1b: /* FCVTMS */ | |
13068 | need_rmode = true; | |
13069 | rmode = FPROUNDING_NEGINF; | |
13070 | break; | |
13071 | case 0x1c: /* FCVTAS */ | |
13072 | need_rmode = true; | |
13073 | rmode = FPROUNDING_TIEAWAY; | |
13074 | break; | |
13075 | case 0x3a: /* FCVTPS */ | |
13076 | need_rmode = true; | |
13077 | rmode = FPROUNDING_POSINF; | |
13078 | break; | |
13079 | case 0x3b: /* FCVTZS */ | |
13080 | need_rmode = true; | |
13081 | rmode = FPROUNDING_ZERO; | |
13082 | break; | |
13083 | case 0x5a: /* FCVTNU */ | |
13084 | need_rmode = true; | |
13085 | rmode = FPROUNDING_TIEEVEN; | |
13086 | break; | |
13087 | case 0x5b: /* FCVTMU */ | |
13088 | need_rmode = true; | |
13089 | rmode = FPROUNDING_NEGINF; | |
13090 | break; | |
13091 | case 0x5c: /* FCVTAU */ | |
13092 | need_rmode = true; | |
13093 | rmode = FPROUNDING_TIEAWAY; | |
13094 | break; | |
13095 | case 0x7a: /* FCVTPU */ | |
13096 | need_rmode = true; | |
13097 | rmode = FPROUNDING_POSINF; | |
13098 | break; | |
13099 | case 0x7b: /* FCVTZU */ | |
13100 | need_rmode = true; | |
13101 | rmode = FPROUNDING_ZERO; | |
13102 | break; | |
15f8a233 AB |
13103 | case 0x2f: /* FABS */ |
13104 | case 0x6f: /* FNEG */ | |
13105 | need_fpst = false; | |
13106 | break; | |
c625ff95 | 13107 | case 0x7d: /* FRSQRTE */ |
b96a54c7 AB |
13108 | case 0x7f: /* FSQRT (vector) */ |
13109 | break; | |
5d432be6 | 13110 | default: |
6eb55edb | 13111 | fprintf(stderr, "%s: insn 0x%04x fpop 0x%2x\n", __func__, insn, fpop); |
5d432be6 AB |
13112 | g_assert_not_reached(); |
13113 | } | |
13114 | ||
6109aea2 AB |
13115 | |
13116 | /* Check additional constraints for the scalar encoding */ | |
13117 | if (is_scalar) { | |
13118 | if (!is_q) { | |
13119 | unallocated_encoding(s); | |
13120 | return; | |
13121 | } | |
13122 | /* FRINTxx is only in the vector form */ | |
13123 | if (only_in_vector) { | |
13124 | unallocated_encoding(s); | |
13125 | return; | |
13126 | } | |
13127 | } | |
13128 | ||
13129 | if (!fp_access_check(s)) { | |
13130 | return; | |
13131 | } | |
13132 | ||
15f8a233 | 13133 | if (need_rmode || need_fpst) { |
cdfb22bb | 13134 | tcg_fpstatus = fpstatus_ptr(FPST_FPCR_F16); |
6109aea2 AB |
13135 | } |
13136 | ||
13137 | if (need_rmode) { | |
13138 | tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode)); | |
13139 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); | |
13140 | } | |
13141 | ||
13142 | if (is_scalar) { | |
3d99d931 | 13143 | TCGv_i32 tcg_op = read_fp_hreg(s, rn); |
2df58130 AB |
13144 | TCGv_i32 tcg_res = tcg_temp_new_i32(); |
13145 | ||
2df58130 AB |
13146 | switch (fpop) { |
13147 | case 0x1a: /* FCVTNS */ | |
13148 | case 0x1b: /* FCVTMS */ | |
13149 | case 0x1c: /* FCVTAS */ | |
13150 | case 0x3a: /* FCVTPS */ | |
13151 | case 0x3b: /* FCVTZS */ | |
13152 | gen_helper_advsimd_f16tosinth(tcg_res, tcg_op, tcg_fpstatus); | |
13153 | break; | |
fbd06e1e AB |
13154 | case 0x3d: /* FRECPE */ |
13155 | gen_helper_recpe_f16(tcg_res, tcg_op, tcg_fpstatus); | |
13156 | break; | |
98695028 AB |
13157 | case 0x3f: /* FRECPX */ |
13158 | gen_helper_frecpx_f16(tcg_res, tcg_op, tcg_fpstatus); | |
13159 | break; | |
2df58130 AB |
13160 | case 0x5a: /* FCVTNU */ |
13161 | case 0x5b: /* FCVTMU */ | |
13162 | case 0x5c: /* FCVTAU */ | |
13163 | case 0x7a: /* FCVTPU */ | |
13164 | case 0x7b: /* FCVTZU */ | |
13165 | gen_helper_advsimd_f16touinth(tcg_res, tcg_op, tcg_fpstatus); | |
13166 | break; | |
15f8a233 AB |
13167 | case 0x6f: /* FNEG */ |
13168 | tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000); | |
13169 | break; | |
c625ff95 AB |
13170 | case 0x7d: /* FRSQRTE */ |
13171 | gen_helper_rsqrte_f16(tcg_res, tcg_op, tcg_fpstatus); | |
13172 | break; | |
2df58130 AB |
13173 | default: |
13174 | g_assert_not_reached(); | |
13175 | } | |
13176 | ||
13177 | /* limit any sign extension going on */ | |
13178 | tcg_gen_andi_i32(tcg_res, tcg_res, 0xffff); | |
13179 | write_fp_sreg(s, rd, tcg_res); | |
13180 | ||
13181 | tcg_temp_free_i32(tcg_res); | |
13182 | tcg_temp_free_i32(tcg_op); | |
6109aea2 AB |
13183 | } else { |
13184 | for (pass = 0; pass < (is_q ? 8 : 4); pass++) { | |
13185 | TCGv_i32 tcg_op = tcg_temp_new_i32(); | |
13186 | TCGv_i32 tcg_res = tcg_temp_new_i32(); | |
13187 | ||
13188 | read_vec_element_i32(s, tcg_op, rn, pass, MO_16); | |
13189 | ||
13190 | switch (fpop) { | |
2df58130 AB |
13191 | case 0x1a: /* FCVTNS */ |
13192 | case 0x1b: /* FCVTMS */ | |
13193 | case 0x1c: /* FCVTAS */ | |
13194 | case 0x3a: /* FCVTPS */ | |
13195 | case 0x3b: /* FCVTZS */ | |
13196 | gen_helper_advsimd_f16tosinth(tcg_res, tcg_op, tcg_fpstatus); | |
13197 | break; | |
fbd06e1e AB |
13198 | case 0x3d: /* FRECPE */ |
13199 | gen_helper_recpe_f16(tcg_res, tcg_op, tcg_fpstatus); | |
13200 | break; | |
2df58130 AB |
13201 | case 0x5a: /* FCVTNU */ |
13202 | case 0x5b: /* FCVTMU */ | |
13203 | case 0x5c: /* FCVTAU */ | |
13204 | case 0x7a: /* FCVTPU */ | |
13205 | case 0x7b: /* FCVTZU */ | |
13206 | gen_helper_advsimd_f16touinth(tcg_res, tcg_op, tcg_fpstatus); | |
13207 | break; | |
6109aea2 AB |
13208 | case 0x18: /* FRINTN */ |
13209 | case 0x19: /* FRINTM */ | |
13210 | case 0x38: /* FRINTP */ | |
13211 | case 0x39: /* FRINTZ */ | |
13212 | case 0x58: /* FRINTA */ | |
13213 | case 0x79: /* FRINTI */ | |
13214 | gen_helper_advsimd_rinth(tcg_res, tcg_op, tcg_fpstatus); | |
13215 | break; | |
13216 | case 0x59: /* FRINTX */ | |
13217 | gen_helper_advsimd_rinth_exact(tcg_res, tcg_op, tcg_fpstatus); | |
13218 | break; | |
15f8a233 AB |
13219 | case 0x2f: /* FABS */ |
13220 | tcg_gen_andi_i32(tcg_res, tcg_op, 0x7fff); | |
13221 | break; | |
13222 | case 0x6f: /* FNEG */ | |
13223 | tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000); | |
13224 | break; | |
c625ff95 AB |
13225 | case 0x7d: /* FRSQRTE */ |
13226 | gen_helper_rsqrte_f16(tcg_res, tcg_op, tcg_fpstatus); | |
13227 | break; | |
b96a54c7 AB |
13228 | case 0x7f: /* FSQRT */ |
13229 | gen_helper_sqrt_f16(tcg_res, tcg_op, tcg_fpstatus); | |
13230 | break; | |
6109aea2 AB |
13231 | default: |
13232 | g_assert_not_reached(); | |
13233 | } | |
13234 | ||
13235 | write_vec_element_i32(s, tcg_res, rd, pass, MO_16); | |
13236 | ||
13237 | tcg_temp_free_i32(tcg_res); | |
13238 | tcg_temp_free_i32(tcg_op); | |
13239 | } | |
13240 | ||
13241 | clear_vec_high(s, is_q, rd); | |
13242 | } | |
13243 | ||
13244 | if (tcg_rmode) { | |
13245 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); | |
13246 | tcg_temp_free_i32(tcg_rmode); | |
13247 | } | |
13248 | ||
13249 | if (tcg_fpstatus) { | |
13250 | tcg_temp_free_ptr(tcg_fpstatus); | |
13251 | } | |
5d432be6 AB |
13252 | } |
13253 | ||
4ce31af4 | 13254 | /* AdvSIMD scalar x indexed element |
9f82e0ff PM |
13255 | * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0 |
13256 | * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+ | |
13257 | * | 0 1 | U | 1 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd | | |
13258 | * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+ | |
4ce31af4 | 13259 | * AdvSIMD vector x indexed element |
384b26fb AB |
13260 | * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0 |
13261 | * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+ | |
13262 | * | 0 | Q | U | 0 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd | | |
13263 | * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+ | |
13264 | */ | |
9f82e0ff | 13265 | static void disas_simd_indexed(DisasContext *s, uint32_t insn) |
384b26fb | 13266 | { |
f5e51e7f PM |
13267 | /* This encoding has two kinds of instruction: |
13268 | * normal, where we perform elt x idxelt => elt for each | |
13269 | * element in the vector | |
13270 | * long, where we perform elt x idxelt and generate a result of | |
13271 | * double the width of the input element | |
13272 | * The long ops have a 'part' specifier (ie come in INSN, INSN2 pairs). | |
13273 | */ | |
9f82e0ff | 13274 | bool is_scalar = extract32(insn, 28, 1); |
f5e51e7f PM |
13275 | bool is_q = extract32(insn, 30, 1); |
13276 | bool u = extract32(insn, 29, 1); | |
13277 | int size = extract32(insn, 22, 2); | |
13278 | int l = extract32(insn, 21, 1); | |
13279 | int m = extract32(insn, 20, 1); | |
13280 | /* Note that the Rm field here is only 4 bits, not 5 as it usually is */ | |
13281 | int rm = extract32(insn, 16, 4); | |
13282 | int opcode = extract32(insn, 12, 4); | |
13283 | int h = extract32(insn, 11, 1); | |
13284 | int rn = extract32(insn, 5, 5); | |
13285 | int rd = extract32(insn, 0, 5); | |
13286 | bool is_long = false; | |
d17b7cdc | 13287 | int is_fp = 0; |
5d265064 | 13288 | bool is_fp16 = false; |
f5e51e7f PM |
13289 | int index; |
13290 | TCGv_ptr fpst; | |
13291 | ||
5f81b1de RH |
13292 | switch (16 * u + opcode) { |
13293 | case 0x08: /* MUL */ | |
13294 | case 0x10: /* MLA */ | |
13295 | case 0x14: /* MLS */ | |
13296 | if (is_scalar) { | |
f5e51e7f PM |
13297 | unallocated_encoding(s); |
13298 | return; | |
13299 | } | |
13300 | break; | |
5f81b1de RH |
13301 | case 0x02: /* SMLAL, SMLAL2 */ |
13302 | case 0x12: /* UMLAL, UMLAL2 */ | |
13303 | case 0x06: /* SMLSL, SMLSL2 */ | |
13304 | case 0x16: /* UMLSL, UMLSL2 */ | |
13305 | case 0x0a: /* SMULL, SMULL2 */ | |
13306 | case 0x1a: /* UMULL, UMULL2 */ | |
9f82e0ff PM |
13307 | if (is_scalar) { |
13308 | unallocated_encoding(s); | |
13309 | return; | |
13310 | } | |
f5e51e7f PM |
13311 | is_long = true; |
13312 | break; | |
5f81b1de RH |
13313 | case 0x03: /* SQDMLAL, SQDMLAL2 */ |
13314 | case 0x07: /* SQDMLSL, SQDMLSL2 */ | |
13315 | case 0x0b: /* SQDMULL, SQDMULL2 */ | |
f5e51e7f | 13316 | is_long = true; |
f5e51e7f | 13317 | break; |
5f81b1de RH |
13318 | case 0x0c: /* SQDMULH */ |
13319 | case 0x0d: /* SQRDMULH */ | |
9f82e0ff | 13320 | break; |
5f81b1de RH |
13321 | case 0x01: /* FMLA */ |
13322 | case 0x05: /* FMLS */ | |
13323 | case 0x09: /* FMUL */ | |
13324 | case 0x19: /* FMULX */ | |
d17b7cdc | 13325 | is_fp = 1; |
f5e51e7f | 13326 | break; |
d345df7a RH |
13327 | case 0x1d: /* SQRDMLAH */ |
13328 | case 0x1f: /* SQRDMLSH */ | |
962fcbf2 | 13329 | if (!dc_isar_feature(aa64_rdm, s)) { |
d345df7a RH |
13330 | unallocated_encoding(s); |
13331 | return; | |
13332 | } | |
13333 | break; | |
26c470a7 RH |
13334 | case 0x0e: /* SDOT */ |
13335 | case 0x1e: /* UDOT */ | |
4977986c | 13336 | if (is_scalar || size != MO_32 || !dc_isar_feature(aa64_dp, s)) { |
26c470a7 RH |
13337 | unallocated_encoding(s); |
13338 | return; | |
13339 | } | |
13340 | break; | |
d17b7cdc RH |
13341 | case 0x11: /* FCMLA #0 */ |
13342 | case 0x13: /* FCMLA #90 */ | |
13343 | case 0x15: /* FCMLA #180 */ | |
13344 | case 0x17: /* FCMLA #270 */ | |
4dfabb6d | 13345 | if (is_scalar || !dc_isar_feature(aa64_fcma, s)) { |
d17b7cdc RH |
13346 | unallocated_encoding(s); |
13347 | return; | |
13348 | } | |
13349 | is_fp = 2; | |
13350 | break; | |
0caa5af8 RH |
13351 | case 0x00: /* FMLAL */ |
13352 | case 0x04: /* FMLSL */ | |
13353 | case 0x18: /* FMLAL2 */ | |
13354 | case 0x1c: /* FMLSL2 */ | |
13355 | if (is_scalar || size != MO_32 || !dc_isar_feature(aa64_fhm, s)) { | |
13356 | unallocated_encoding(s); | |
13357 | return; | |
13358 | } | |
13359 | size = MO_16; | |
13360 | /* is_fp, but we pass cpu_env not fp_status. */ | |
13361 | break; | |
f5e51e7f PM |
13362 | default: |
13363 | unallocated_encoding(s); | |
13364 | return; | |
13365 | } | |
13366 | ||
d17b7cdc RH |
13367 | switch (is_fp) { |
13368 | case 1: /* normal fp */ | |
14776ab5 | 13369 | /* convert insn encoded size to MemOp size */ |
5d265064 | 13370 | switch (size) { |
449f264b | 13371 | case 0: /* half-precision */ |
5d265064 | 13372 | size = MO_16; |
d17b7cdc | 13373 | is_fp16 = true; |
449f264b RH |
13374 | break; |
13375 | case MO_32: /* single precision */ | |
13376 | case MO_64: /* double precision */ | |
13377 | break; | |
13378 | default: | |
5d265064 AB |
13379 | unallocated_encoding(s); |
13380 | return; | |
f5e51e7f | 13381 | } |
d17b7cdc RH |
13382 | break; |
13383 | ||
13384 | case 2: /* complex fp */ | |
13385 | /* Each indexable element is a complex pair. */ | |
eaefb97a | 13386 | size += 1; |
d17b7cdc RH |
13387 | switch (size) { |
13388 | case MO_32: | |
13389 | if (h && !is_q) { | |
13390 | unallocated_encoding(s); | |
13391 | return; | |
13392 | } | |
13393 | is_fp16 = true; | |
13394 | break; | |
13395 | case MO_64: | |
13396 | break; | |
13397 | default: | |
13398 | unallocated_encoding(s); | |
13399 | return; | |
13400 | } | |
13401 | break; | |
13402 | ||
13403 | default: /* integer */ | |
f5e51e7f | 13404 | switch (size) { |
449f264b RH |
13405 | case MO_8: |
13406 | case MO_64: | |
f5e51e7f PM |
13407 | unallocated_encoding(s); |
13408 | return; | |
13409 | } | |
d17b7cdc RH |
13410 | break; |
13411 | } | |
5763190f | 13412 | if (is_fp16 && !dc_isar_feature(aa64_fp16, s)) { |
d17b7cdc RH |
13413 | unallocated_encoding(s); |
13414 | return; | |
f5e51e7f PM |
13415 | } |
13416 | ||
14776ab5 | 13417 | /* Given MemOp size, adjust register and indexing. */ |
449f264b RH |
13418 | switch (size) { |
13419 | case MO_16: | |
13420 | index = h << 2 | l << 1 | m; | |
13421 | break; | |
13422 | case MO_32: | |
13423 | index = h << 1 | l; | |
13424 | rm |= m << 4; | |
13425 | break; | |
13426 | case MO_64: | |
13427 | if (l || !is_q) { | |
13428 | unallocated_encoding(s); | |
13429 | return; | |
13430 | } | |
13431 | index = h; | |
13432 | rm |= m << 4; | |
13433 | break; | |
13434 | default: | |
13435 | g_assert_not_reached(); | |
13436 | } | |
13437 | ||
8c6afa6a PM |
13438 | if (!fp_access_check(s)) { |
13439 | return; | |
13440 | } | |
13441 | ||
f5e51e7f | 13442 | if (is_fp) { |
cdfb22bb | 13443 | fpst = fpstatus_ptr(is_fp16 ? FPST_FPCR_F16 : FPST_FPCR); |
f5e51e7f | 13444 | } else { |
f764718d | 13445 | fpst = NULL; |
f5e51e7f PM |
13446 | } |
13447 | ||
d17b7cdc | 13448 | switch (16 * u + opcode) { |
26c470a7 RH |
13449 | case 0x0e: /* SDOT */ |
13450 | case 0x1e: /* UDOT */ | |
13451 | gen_gvec_op3_ool(s, is_q, rd, rn, rm, index, | |
13452 | u ? gen_helper_gvec_udot_idx_b | |
13453 | : gen_helper_gvec_sdot_idx_b); | |
13454 | return; | |
d17b7cdc RH |
13455 | case 0x11: /* FCMLA #0 */ |
13456 | case 0x13: /* FCMLA #90 */ | |
13457 | case 0x15: /* FCMLA #180 */ | |
13458 | case 0x17: /* FCMLA #270 */ | |
2cc99919 RH |
13459 | { |
13460 | int rot = extract32(insn, 13, 2); | |
13461 | int data = (index << 2) | rot; | |
13462 | tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd), | |
13463 | vec_full_reg_offset(s, rn), | |
13464 | vec_full_reg_offset(s, rm), fpst, | |
13465 | is_q ? 16 : 8, vec_full_reg_size(s), data, | |
13466 | size == MO_64 | |
13467 | ? gen_helper_gvec_fcmlas_idx | |
13468 | : gen_helper_gvec_fcmlah_idx); | |
13469 | tcg_temp_free_ptr(fpst); | |
13470 | } | |
d17b7cdc | 13471 | return; |
0caa5af8 RH |
13472 | |
13473 | case 0x00: /* FMLAL */ | |
13474 | case 0x04: /* FMLSL */ | |
13475 | case 0x18: /* FMLAL2 */ | |
13476 | case 0x1c: /* FMLSL2 */ | |
13477 | { | |
13478 | int is_s = extract32(opcode, 2, 1); | |
13479 | int is_2 = u; | |
13480 | int data = (index << 2) | (is_2 << 1) | is_s; | |
13481 | tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd), | |
13482 | vec_full_reg_offset(s, rn), | |
13483 | vec_full_reg_offset(s, rm), cpu_env, | |
13484 | is_q ? 16 : 8, vec_full_reg_size(s), | |
13485 | data, gen_helper_gvec_fmlal_idx_a64); | |
13486 | } | |
13487 | return; | |
2e5a265e RH |
13488 | |
13489 | case 0x08: /* MUL */ | |
13490 | if (!is_long && !is_scalar) { | |
13491 | static gen_helper_gvec_3 * const fns[3] = { | |
13492 | gen_helper_gvec_mul_idx_h, | |
13493 | gen_helper_gvec_mul_idx_s, | |
13494 | gen_helper_gvec_mul_idx_d, | |
13495 | }; | |
13496 | tcg_gen_gvec_3_ool(vec_full_reg_offset(s, rd), | |
13497 | vec_full_reg_offset(s, rn), | |
13498 | vec_full_reg_offset(s, rm), | |
13499 | is_q ? 16 : 8, vec_full_reg_size(s), | |
3607440c RH |
13500 | index, fns[size - 1]); |
13501 | return; | |
13502 | } | |
13503 | break; | |
13504 | ||
13505 | case 0x10: /* MLA */ | |
13506 | if (!is_long && !is_scalar) { | |
13507 | static gen_helper_gvec_4 * const fns[3] = { | |
13508 | gen_helper_gvec_mla_idx_h, | |
13509 | gen_helper_gvec_mla_idx_s, | |
13510 | gen_helper_gvec_mla_idx_d, | |
13511 | }; | |
13512 | tcg_gen_gvec_4_ool(vec_full_reg_offset(s, rd), | |
13513 | vec_full_reg_offset(s, rn), | |
13514 | vec_full_reg_offset(s, rm), | |
13515 | vec_full_reg_offset(s, rd), | |
13516 | is_q ? 16 : 8, vec_full_reg_size(s), | |
13517 | index, fns[size - 1]); | |
13518 | return; | |
13519 | } | |
13520 | break; | |
13521 | ||
13522 | case 0x14: /* MLS */ | |
13523 | if (!is_long && !is_scalar) { | |
13524 | static gen_helper_gvec_4 * const fns[3] = { | |
13525 | gen_helper_gvec_mls_idx_h, | |
13526 | gen_helper_gvec_mls_idx_s, | |
13527 | gen_helper_gvec_mls_idx_d, | |
13528 | }; | |
13529 | tcg_gen_gvec_4_ool(vec_full_reg_offset(s, rd), | |
13530 | vec_full_reg_offset(s, rn), | |
13531 | vec_full_reg_offset(s, rm), | |
13532 | vec_full_reg_offset(s, rd), | |
13533 | is_q ? 16 : 8, vec_full_reg_size(s), | |
2e5a265e RH |
13534 | index, fns[size - 1]); |
13535 | return; | |
13536 | } | |
13537 | break; | |
d17b7cdc RH |
13538 | } |
13539 | ||
f5e51e7f PM |
13540 | if (size == 3) { |
13541 | TCGv_i64 tcg_idx = tcg_temp_new_i64(); | |
13542 | int pass; | |
13543 | ||
13544 | assert(is_fp && is_q && !is_long); | |
13545 | ||
13546 | read_vec_element(s, tcg_idx, rm, index, MO_64); | |
13547 | ||
9f82e0ff | 13548 | for (pass = 0; pass < (is_scalar ? 1 : 2); pass++) { |
f5e51e7f PM |
13549 | TCGv_i64 tcg_op = tcg_temp_new_i64(); |
13550 | TCGv_i64 tcg_res = tcg_temp_new_i64(); | |
13551 | ||
13552 | read_vec_element(s, tcg_op, rn, pass, MO_64); | |
13553 | ||
5f81b1de RH |
13554 | switch (16 * u + opcode) { |
13555 | case 0x05: /* FMLS */ | |
f5e51e7f PM |
13556 | /* As usual for ARM, separate negation for fused multiply-add */ |
13557 | gen_helper_vfp_negd(tcg_op, tcg_op); | |
13558 | /* fall through */ | |
5f81b1de | 13559 | case 0x01: /* FMLA */ |
f5e51e7f PM |
13560 | read_vec_element(s, tcg_res, rd, pass, MO_64); |
13561 | gen_helper_vfp_muladdd(tcg_res, tcg_op, tcg_idx, tcg_res, fpst); | |
13562 | break; | |
5f81b1de RH |
13563 | case 0x09: /* FMUL */ |
13564 | gen_helper_vfp_muld(tcg_res, tcg_op, tcg_idx, fpst); | |
13565 | break; | |
13566 | case 0x19: /* FMULX */ | |
13567 | gen_helper_vfp_mulxd(tcg_res, tcg_op, tcg_idx, fpst); | |
f5e51e7f PM |
13568 | break; |
13569 | default: | |
13570 | g_assert_not_reached(); | |
13571 | } | |
13572 | ||
13573 | write_vec_element(s, tcg_res, rd, pass, MO_64); | |
13574 | tcg_temp_free_i64(tcg_op); | |
13575 | tcg_temp_free_i64(tcg_res); | |
13576 | } | |
13577 | ||
13578 | tcg_temp_free_i64(tcg_idx); | |
4ff55bcb | 13579 | clear_vec_high(s, !is_scalar, rd); |
f5e51e7f | 13580 | } else if (!is_long) { |
9f82e0ff PM |
13581 | /* 32 bit floating point, or 16 or 32 bit integer. |
13582 | * For the 16 bit scalar case we use the usual Neon helpers and | |
13583 | * rely on the fact that 0 op 0 == 0 with no side effects. | |
13584 | */ | |
f5e51e7f | 13585 | TCGv_i32 tcg_idx = tcg_temp_new_i32(); |
9f82e0ff PM |
13586 | int pass, maxpasses; |
13587 | ||
13588 | if (is_scalar) { | |
13589 | maxpasses = 1; | |
13590 | } else { | |
13591 | maxpasses = is_q ? 4 : 2; | |
13592 | } | |
f5e51e7f PM |
13593 | |
13594 | read_vec_element_i32(s, tcg_idx, rm, index, size); | |
13595 | ||
9f82e0ff | 13596 | if (size == 1 && !is_scalar) { |
f5e51e7f PM |
13597 | /* The simplest way to handle the 16x16 indexed ops is to duplicate |
13598 | * the index into both halves of the 32 bit tcg_idx and then use | |
13599 | * the usual Neon helpers. | |
13600 | */ | |
13601 | tcg_gen_deposit_i32(tcg_idx, tcg_idx, tcg_idx, 16, 16); | |
13602 | } | |
13603 | ||
9f82e0ff | 13604 | for (pass = 0; pass < maxpasses; pass++) { |
f5e51e7f PM |
13605 | TCGv_i32 tcg_op = tcg_temp_new_i32(); |
13606 | TCGv_i32 tcg_res = tcg_temp_new_i32(); | |
13607 | ||
9f82e0ff | 13608 | read_vec_element_i32(s, tcg_op, rn, pass, is_scalar ? size : MO_32); |
f5e51e7f | 13609 | |
5f81b1de RH |
13610 | switch (16 * u + opcode) { |
13611 | case 0x08: /* MUL */ | |
13612 | case 0x10: /* MLA */ | |
13613 | case 0x14: /* MLS */ | |
f5e51e7f PM |
13614 | { |
13615 | static NeonGenTwoOpFn * const fns[2][2] = { | |
13616 | { gen_helper_neon_add_u16, gen_helper_neon_sub_u16 }, | |
13617 | { tcg_gen_add_i32, tcg_gen_sub_i32 }, | |
13618 | }; | |
13619 | NeonGenTwoOpFn *genfn; | |
13620 | bool is_sub = opcode == 0x4; | |
13621 | ||
13622 | if (size == 1) { | |
13623 | gen_helper_neon_mul_u16(tcg_res, tcg_op, tcg_idx); | |
13624 | } else { | |
13625 | tcg_gen_mul_i32(tcg_res, tcg_op, tcg_idx); | |
13626 | } | |
13627 | if (opcode == 0x8) { | |
13628 | break; | |
13629 | } | |
13630 | read_vec_element_i32(s, tcg_op, rd, pass, MO_32); | |
13631 | genfn = fns[size - 1][is_sub]; | |
13632 | genfn(tcg_res, tcg_op, tcg_res); | |
13633 | break; | |
13634 | } | |
5f81b1de RH |
13635 | case 0x05: /* FMLS */ |
13636 | case 0x01: /* FMLA */ | |
5d265064 AB |
13637 | read_vec_element_i32(s, tcg_res, rd, pass, |
13638 | is_scalar ? size : MO_32); | |
13639 | switch (size) { | |
13640 | case 1: | |
13641 | if (opcode == 0x5) { | |
13642 | /* As usual for ARM, separate negation for fused | |
13643 | * multiply-add */ | |
13644 | tcg_gen_xori_i32(tcg_op, tcg_op, 0x80008000); | |
13645 | } | |
6089030c AB |
13646 | if (is_scalar) { |
13647 | gen_helper_advsimd_muladdh(tcg_res, tcg_op, tcg_idx, | |
13648 | tcg_res, fpst); | |
13649 | } else { | |
13650 | gen_helper_advsimd_muladd2h(tcg_res, tcg_op, tcg_idx, | |
13651 | tcg_res, fpst); | |
13652 | } | |
5d265064 AB |
13653 | break; |
13654 | case 2: | |
13655 | if (opcode == 0x5) { | |
13656 | /* As usual for ARM, separate negation for | |
13657 | * fused multiply-add */ | |
13658 | tcg_gen_xori_i32(tcg_op, tcg_op, 0x80000000); | |
13659 | } | |
13660 | gen_helper_vfp_muladds(tcg_res, tcg_op, tcg_idx, | |
13661 | tcg_res, fpst); | |
13662 | break; | |
13663 | default: | |
13664 | g_assert_not_reached(); | |
13665 | } | |
f5e51e7f | 13666 | break; |
5f81b1de | 13667 | case 0x09: /* FMUL */ |
5d265064 AB |
13668 | switch (size) { |
13669 | case 1: | |
5f81b1de RH |
13670 | if (is_scalar) { |
13671 | gen_helper_advsimd_mulh(tcg_res, tcg_op, | |
13672 | tcg_idx, fpst); | |
5d265064 | 13673 | } else { |
5f81b1de RH |
13674 | gen_helper_advsimd_mul2h(tcg_res, tcg_op, |
13675 | tcg_idx, fpst); | |
5d265064 AB |
13676 | } |
13677 | break; | |
13678 | case 2: | |
5f81b1de RH |
13679 | gen_helper_vfp_muls(tcg_res, tcg_op, tcg_idx, fpst); |
13680 | break; | |
13681 | default: | |
13682 | g_assert_not_reached(); | |
13683 | } | |
13684 | break; | |
13685 | case 0x19: /* FMULX */ | |
13686 | switch (size) { | |
13687 | case 1: | |
13688 | if (is_scalar) { | |
13689 | gen_helper_advsimd_mulxh(tcg_res, tcg_op, | |
13690 | tcg_idx, fpst); | |
5d265064 | 13691 | } else { |
5f81b1de RH |
13692 | gen_helper_advsimd_mulx2h(tcg_res, tcg_op, |
13693 | tcg_idx, fpst); | |
5d265064 AB |
13694 | } |
13695 | break; | |
5f81b1de RH |
13696 | case 2: |
13697 | gen_helper_vfp_mulxs(tcg_res, tcg_op, tcg_idx, fpst); | |
13698 | break; | |
5d265064 AB |
13699 | default: |
13700 | g_assert_not_reached(); | |
f5e51e7f PM |
13701 | } |
13702 | break; | |
5f81b1de | 13703 | case 0x0c: /* SQDMULH */ |
f5e51e7f PM |
13704 | if (size == 1) { |
13705 | gen_helper_neon_qdmulh_s16(tcg_res, cpu_env, | |
13706 | tcg_op, tcg_idx); | |
13707 | } else { | |
13708 | gen_helper_neon_qdmulh_s32(tcg_res, cpu_env, | |
13709 | tcg_op, tcg_idx); | |
13710 | } | |
13711 | break; | |
5f81b1de | 13712 | case 0x0d: /* SQRDMULH */ |
f5e51e7f PM |
13713 | if (size == 1) { |
13714 | gen_helper_neon_qrdmulh_s16(tcg_res, cpu_env, | |
13715 | tcg_op, tcg_idx); | |
13716 | } else { | |
13717 | gen_helper_neon_qrdmulh_s32(tcg_res, cpu_env, | |
13718 | tcg_op, tcg_idx); | |
13719 | } | |
13720 | break; | |
d345df7a RH |
13721 | case 0x1d: /* SQRDMLAH */ |
13722 | read_vec_element_i32(s, tcg_res, rd, pass, | |
13723 | is_scalar ? size : MO_32); | |
13724 | if (size == 1) { | |
13725 | gen_helper_neon_qrdmlah_s16(tcg_res, cpu_env, | |
13726 | tcg_op, tcg_idx, tcg_res); | |
13727 | } else { | |
13728 | gen_helper_neon_qrdmlah_s32(tcg_res, cpu_env, | |
13729 | tcg_op, tcg_idx, tcg_res); | |
13730 | } | |
13731 | break; | |
13732 | case 0x1f: /* SQRDMLSH */ | |
13733 | read_vec_element_i32(s, tcg_res, rd, pass, | |
13734 | is_scalar ? size : MO_32); | |
13735 | if (size == 1) { | |
13736 | gen_helper_neon_qrdmlsh_s16(tcg_res, cpu_env, | |
13737 | tcg_op, tcg_idx, tcg_res); | |
13738 | } else { | |
13739 | gen_helper_neon_qrdmlsh_s32(tcg_res, cpu_env, | |
13740 | tcg_op, tcg_idx, tcg_res); | |
13741 | } | |
13742 | break; | |
f5e51e7f PM |
13743 | default: |
13744 | g_assert_not_reached(); | |
13745 | } | |
13746 | ||
9f82e0ff PM |
13747 | if (is_scalar) { |
13748 | write_fp_sreg(s, rd, tcg_res); | |
13749 | } else { | |
13750 | write_vec_element_i32(s, tcg_res, rd, pass, MO_32); | |
13751 | } | |
13752 | ||
f5e51e7f PM |
13753 | tcg_temp_free_i32(tcg_op); |
13754 | tcg_temp_free_i32(tcg_res); | |
13755 | } | |
13756 | ||
13757 | tcg_temp_free_i32(tcg_idx); | |
4ff55bcb | 13758 | clear_vec_high(s, is_q, rd); |
f5e51e7f PM |
13759 | } else { |
13760 | /* long ops: 16x16->32 or 32x32->64 */ | |
c44ad1fd PM |
13761 | TCGv_i64 tcg_res[2]; |
13762 | int pass; | |
13763 | bool satop = extract32(opcode, 0, 1); | |
14776ab5 | 13764 | MemOp memop = MO_32; |
c44ad1fd PM |
13765 | |
13766 | if (satop || !u) { | |
13767 | memop |= MO_SIGN; | |
13768 | } | |
13769 | ||
13770 | if (size == 2) { | |
13771 | TCGv_i64 tcg_idx = tcg_temp_new_i64(); | |
13772 | ||
13773 | read_vec_element(s, tcg_idx, rm, index, memop); | |
13774 | ||
9f82e0ff | 13775 | for (pass = 0; pass < (is_scalar ? 1 : 2); pass++) { |
c44ad1fd PM |
13776 | TCGv_i64 tcg_op = tcg_temp_new_i64(); |
13777 | TCGv_i64 tcg_passres; | |
9f82e0ff | 13778 | int passelt; |
c44ad1fd | 13779 | |
9f82e0ff PM |
13780 | if (is_scalar) { |
13781 | passelt = 0; | |
13782 | } else { | |
13783 | passelt = pass + (is_q * 2); | |
13784 | } | |
13785 | ||
13786 | read_vec_element(s, tcg_op, rn, passelt, memop); | |
c44ad1fd PM |
13787 | |
13788 | tcg_res[pass] = tcg_temp_new_i64(); | |
13789 | ||
13790 | if (opcode == 0xa || opcode == 0xb) { | |
13791 | /* Non-accumulating ops */ | |
13792 | tcg_passres = tcg_res[pass]; | |
13793 | } else { | |
13794 | tcg_passres = tcg_temp_new_i64(); | |
13795 | } | |
13796 | ||
13797 | tcg_gen_mul_i64(tcg_passres, tcg_op, tcg_idx); | |
13798 | tcg_temp_free_i64(tcg_op); | |
13799 | ||
13800 | if (satop) { | |
13801 | /* saturating, doubling */ | |
13802 | gen_helper_neon_addl_saturate_s64(tcg_passres, cpu_env, | |
13803 | tcg_passres, tcg_passres); | |
13804 | } | |
13805 | ||
13806 | if (opcode == 0xa || opcode == 0xb) { | |
13807 | continue; | |
13808 | } | |
13809 | ||
13810 | /* Accumulating op: handle accumulate step */ | |
13811 | read_vec_element(s, tcg_res[pass], rd, pass, MO_64); | |
13812 | ||
13813 | switch (opcode) { | |
13814 | case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */ | |
13815 | tcg_gen_add_i64(tcg_res[pass], tcg_res[pass], tcg_passres); | |
13816 | break; | |
13817 | case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */ | |
13818 | tcg_gen_sub_i64(tcg_res[pass], tcg_res[pass], tcg_passres); | |
13819 | break; | |
13820 | case 0x7: /* SQDMLSL, SQDMLSL2 */ | |
13821 | tcg_gen_neg_i64(tcg_passres, tcg_passres); | |
13822 | /* fall through */ | |
13823 | case 0x3: /* SQDMLAL, SQDMLAL2 */ | |
13824 | gen_helper_neon_addl_saturate_s64(tcg_res[pass], cpu_env, | |
13825 | tcg_res[pass], | |
13826 | tcg_passres); | |
13827 | break; | |
13828 | default: | |
13829 | g_assert_not_reached(); | |
13830 | } | |
13831 | tcg_temp_free_i64(tcg_passres); | |
13832 | } | |
13833 | tcg_temp_free_i64(tcg_idx); | |
9f82e0ff | 13834 | |
4ff55bcb | 13835 | clear_vec_high(s, !is_scalar, rd); |
c44ad1fd PM |
13836 | } else { |
13837 | TCGv_i32 tcg_idx = tcg_temp_new_i32(); | |
13838 | ||
13839 | assert(size == 1); | |
13840 | read_vec_element_i32(s, tcg_idx, rm, index, size); | |
13841 | ||
9f82e0ff PM |
13842 | if (!is_scalar) { |
13843 | /* The simplest way to handle the 16x16 indexed ops is to | |
13844 | * duplicate the index into both halves of the 32 bit tcg_idx | |
13845 | * and then use the usual Neon helpers. | |
13846 | */ | |
13847 | tcg_gen_deposit_i32(tcg_idx, tcg_idx, tcg_idx, 16, 16); | |
13848 | } | |
c44ad1fd | 13849 | |
9f82e0ff | 13850 | for (pass = 0; pass < (is_scalar ? 1 : 2); pass++) { |
c44ad1fd PM |
13851 | TCGv_i32 tcg_op = tcg_temp_new_i32(); |
13852 | TCGv_i64 tcg_passres; | |
13853 | ||
9f82e0ff PM |
13854 | if (is_scalar) { |
13855 | read_vec_element_i32(s, tcg_op, rn, pass, size); | |
13856 | } else { | |
13857 | read_vec_element_i32(s, tcg_op, rn, | |
13858 | pass + (is_q * 2), MO_32); | |
13859 | } | |
13860 | ||
c44ad1fd PM |
13861 | tcg_res[pass] = tcg_temp_new_i64(); |
13862 | ||
13863 | if (opcode == 0xa || opcode == 0xb) { | |
13864 | /* Non-accumulating ops */ | |
13865 | tcg_passres = tcg_res[pass]; | |
13866 | } else { | |
13867 | tcg_passres = tcg_temp_new_i64(); | |
13868 | } | |
13869 | ||
13870 | if (memop & MO_SIGN) { | |
13871 | gen_helper_neon_mull_s16(tcg_passres, tcg_op, tcg_idx); | |
13872 | } else { | |
13873 | gen_helper_neon_mull_u16(tcg_passres, tcg_op, tcg_idx); | |
13874 | } | |
13875 | if (satop) { | |
13876 | gen_helper_neon_addl_saturate_s32(tcg_passres, cpu_env, | |
13877 | tcg_passres, tcg_passres); | |
13878 | } | |
13879 | tcg_temp_free_i32(tcg_op); | |
13880 | ||
13881 | if (opcode == 0xa || opcode == 0xb) { | |
13882 | continue; | |
13883 | } | |
13884 | ||
13885 | /* Accumulating op: handle accumulate step */ | |
13886 | read_vec_element(s, tcg_res[pass], rd, pass, MO_64); | |
13887 | ||
13888 | switch (opcode) { | |
13889 | case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */ | |
13890 | gen_helper_neon_addl_u32(tcg_res[pass], tcg_res[pass], | |
13891 | tcg_passres); | |
13892 | break; | |
13893 | case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */ | |
13894 | gen_helper_neon_subl_u32(tcg_res[pass], tcg_res[pass], | |
13895 | tcg_passres); | |
13896 | break; | |
13897 | case 0x7: /* SQDMLSL, SQDMLSL2 */ | |
13898 | gen_helper_neon_negl_u32(tcg_passres, tcg_passres); | |
13899 | /* fall through */ | |
13900 | case 0x3: /* SQDMLAL, SQDMLAL2 */ | |
13901 | gen_helper_neon_addl_saturate_s32(tcg_res[pass], cpu_env, | |
13902 | tcg_res[pass], | |
13903 | tcg_passres); | |
13904 | break; | |
13905 | default: | |
13906 | g_assert_not_reached(); | |
13907 | } | |
13908 | tcg_temp_free_i64(tcg_passres); | |
13909 | } | |
13910 | tcg_temp_free_i32(tcg_idx); | |
9f82e0ff PM |
13911 | |
13912 | if (is_scalar) { | |
13913 | tcg_gen_ext32u_i64(tcg_res[0], tcg_res[0]); | |
13914 | } | |
13915 | } | |
13916 | ||
13917 | if (is_scalar) { | |
13918 | tcg_res[1] = tcg_const_i64(0); | |
c44ad1fd PM |
13919 | } |
13920 | ||
13921 | for (pass = 0; pass < 2; pass++) { | |
13922 | write_vec_element(s, tcg_res[pass], rd, pass, MO_64); | |
13923 | tcg_temp_free_i64(tcg_res[pass]); | |
13924 | } | |
f5e51e7f PM |
13925 | } |
13926 | ||
f764718d | 13927 | if (fpst) { |
f5e51e7f PM |
13928 | tcg_temp_free_ptr(fpst); |
13929 | } | |
384b26fb AB |
13930 | } |
13931 | ||
4ce31af4 | 13932 | /* Crypto AES |
384b26fb AB |
13933 | * 31 24 23 22 21 17 16 12 11 10 9 5 4 0 |
13934 | * +-----------------+------+-----------+--------+-----+------+------+ | |
13935 | * | 0 1 0 0 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd | | |
13936 | * +-----------------+------+-----------+--------+-----+------+------+ | |
13937 | */ | |
13938 | static void disas_crypto_aes(DisasContext *s, uint32_t insn) | |
13939 | { | |
5acc765c PM |
13940 | int size = extract32(insn, 22, 2); |
13941 | int opcode = extract32(insn, 12, 5); | |
13942 | int rn = extract32(insn, 5, 5); | |
13943 | int rd = extract32(insn, 0, 5); | |
13944 | int decrypt; | |
a04b68e1 RH |
13945 | gen_helper_gvec_2 *genfn2 = NULL; |
13946 | gen_helper_gvec_3 *genfn3 = NULL; | |
5acc765c | 13947 | |
962fcbf2 | 13948 | if (!dc_isar_feature(aa64_aes, s) || size != 0) { |
5acc765c PM |
13949 | unallocated_encoding(s); |
13950 | return; | |
13951 | } | |
13952 | ||
13953 | switch (opcode) { | |
13954 | case 0x4: /* AESE */ | |
13955 | decrypt = 0; | |
a04b68e1 | 13956 | genfn3 = gen_helper_crypto_aese; |
5acc765c PM |
13957 | break; |
13958 | case 0x6: /* AESMC */ | |
13959 | decrypt = 0; | |
a04b68e1 | 13960 | genfn2 = gen_helper_crypto_aesmc; |
5acc765c PM |
13961 | break; |
13962 | case 0x5: /* AESD */ | |
13963 | decrypt = 1; | |
a04b68e1 | 13964 | genfn3 = gen_helper_crypto_aese; |
5acc765c PM |
13965 | break; |
13966 | case 0x7: /* AESIMC */ | |
13967 | decrypt = 1; | |
a04b68e1 | 13968 | genfn2 = gen_helper_crypto_aesmc; |
5acc765c PM |
13969 | break; |
13970 | default: | |
13971 | unallocated_encoding(s); | |
13972 | return; | |
13973 | } | |
13974 | ||
a4f5c5b7 NR |
13975 | if (!fp_access_check(s)) { |
13976 | return; | |
13977 | } | |
a04b68e1 RH |
13978 | if (genfn2) { |
13979 | gen_gvec_op2_ool(s, true, rd, rn, decrypt, genfn2); | |
13980 | } else { | |
13981 | gen_gvec_op3_ool(s, true, rd, rd, rn, decrypt, genfn3); | |
13982 | } | |
384b26fb AB |
13983 | } |
13984 | ||
4ce31af4 | 13985 | /* Crypto three-reg SHA |
384b26fb AB |
13986 | * 31 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0 |
13987 | * +-----------------+------+---+------+---+--------+-----+------+------+ | |
13988 | * | 0 1 0 1 1 1 1 0 | size | 0 | Rm | 0 | opcode | 0 0 | Rn | Rd | | |
13989 | * +-----------------+------+---+------+---+--------+-----+------+------+ | |
13990 | */ | |
13991 | static void disas_crypto_three_reg_sha(DisasContext *s, uint32_t insn) | |
13992 | { | |
be56f04e PM |
13993 | int size = extract32(insn, 22, 2); |
13994 | int opcode = extract32(insn, 12, 3); | |
13995 | int rm = extract32(insn, 16, 5); | |
13996 | int rn = extract32(insn, 5, 5); | |
13997 | int rd = extract32(insn, 0, 5); | |
effa992f | 13998 | gen_helper_gvec_3 *genfn; |
962fcbf2 | 13999 | bool feature; |
be56f04e PM |
14000 | |
14001 | if (size != 0) { | |
14002 | unallocated_encoding(s); | |
14003 | return; | |
14004 | } | |
14005 | ||
14006 | switch (opcode) { | |
14007 | case 0: /* SHA1C */ | |
afc8b7d3 RH |
14008 | genfn = gen_helper_crypto_sha1c; |
14009 | feature = dc_isar_feature(aa64_sha1, s); | |
14010 | break; | |
be56f04e | 14011 | case 1: /* SHA1P */ |
afc8b7d3 RH |
14012 | genfn = gen_helper_crypto_sha1p; |
14013 | feature = dc_isar_feature(aa64_sha1, s); | |
14014 | break; | |
be56f04e | 14015 | case 2: /* SHA1M */ |
afc8b7d3 RH |
14016 | genfn = gen_helper_crypto_sha1m; |
14017 | feature = dc_isar_feature(aa64_sha1, s); | |
14018 | break; | |
be56f04e | 14019 | case 3: /* SHA1SU0 */ |
afc8b7d3 | 14020 | genfn = gen_helper_crypto_sha1su0; |
962fcbf2 | 14021 | feature = dc_isar_feature(aa64_sha1, s); |
be56f04e PM |
14022 | break; |
14023 | case 4: /* SHA256H */ | |
14024 | genfn = gen_helper_crypto_sha256h; | |
962fcbf2 | 14025 | feature = dc_isar_feature(aa64_sha256, s); |
be56f04e PM |
14026 | break; |
14027 | case 5: /* SHA256H2 */ | |
14028 | genfn = gen_helper_crypto_sha256h2; | |
962fcbf2 | 14029 | feature = dc_isar_feature(aa64_sha256, s); |
be56f04e PM |
14030 | break; |
14031 | case 6: /* SHA256SU1 */ | |
14032 | genfn = gen_helper_crypto_sha256su1; | |
962fcbf2 | 14033 | feature = dc_isar_feature(aa64_sha256, s); |
be56f04e PM |
14034 | break; |
14035 | default: | |
14036 | unallocated_encoding(s); | |
14037 | return; | |
14038 | } | |
14039 | ||
962fcbf2 | 14040 | if (!feature) { |
be56f04e PM |
14041 | unallocated_encoding(s); |
14042 | return; | |
14043 | } | |
14044 | ||
a4f5c5b7 NR |
14045 | if (!fp_access_check(s)) { |
14046 | return; | |
14047 | } | |
afc8b7d3 | 14048 | gen_gvec_op3_ool(s, true, rd, rn, rm, 0, genfn); |
384b26fb AB |
14049 | } |
14050 | ||
4ce31af4 | 14051 | /* Crypto two-reg SHA |
384b26fb AB |
14052 | * 31 24 23 22 21 17 16 12 11 10 9 5 4 0 |
14053 | * +-----------------+------+-----------+--------+-----+------+------+ | |
14054 | * | 0 1 0 1 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd | | |
14055 | * +-----------------+------+-----------+--------+-----+------+------+ | |
14056 | */ | |
14057 | static void disas_crypto_two_reg_sha(DisasContext *s, uint32_t insn) | |
14058 | { | |
f6fe04d5 PM |
14059 | int size = extract32(insn, 22, 2); |
14060 | int opcode = extract32(insn, 12, 5); | |
14061 | int rn = extract32(insn, 5, 5); | |
14062 | int rd = extract32(insn, 0, 5); | |
effa992f | 14063 | gen_helper_gvec_2 *genfn; |
962fcbf2 | 14064 | bool feature; |
f6fe04d5 PM |
14065 | |
14066 | if (size != 0) { | |
14067 | unallocated_encoding(s); | |
14068 | return; | |
14069 | } | |
14070 | ||
14071 | switch (opcode) { | |
14072 | case 0: /* SHA1H */ | |
962fcbf2 | 14073 | feature = dc_isar_feature(aa64_sha1, s); |
f6fe04d5 PM |
14074 | genfn = gen_helper_crypto_sha1h; |
14075 | break; | |
14076 | case 1: /* SHA1SU1 */ | |
962fcbf2 | 14077 | feature = dc_isar_feature(aa64_sha1, s); |
f6fe04d5 PM |
14078 | genfn = gen_helper_crypto_sha1su1; |
14079 | break; | |
14080 | case 2: /* SHA256SU0 */ | |
962fcbf2 | 14081 | feature = dc_isar_feature(aa64_sha256, s); |
f6fe04d5 PM |
14082 | genfn = gen_helper_crypto_sha256su0; |
14083 | break; | |
14084 | default: | |
14085 | unallocated_encoding(s); | |
14086 | return; | |
14087 | } | |
14088 | ||
962fcbf2 | 14089 | if (!feature) { |
f6fe04d5 PM |
14090 | unallocated_encoding(s); |
14091 | return; | |
14092 | } | |
14093 | ||
a4f5c5b7 NR |
14094 | if (!fp_access_check(s)) { |
14095 | return; | |
14096 | } | |
effa992f | 14097 | gen_gvec_op2_ool(s, true, rd, rn, 0, genfn); |
384b26fb AB |
14098 | } |
14099 | ||
1738860d RH |
14100 | static void gen_rax1_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m) |
14101 | { | |
14102 | tcg_gen_rotli_i64(d, m, 1); | |
14103 | tcg_gen_xor_i64(d, d, n); | |
14104 | } | |
14105 | ||
14106 | static void gen_rax1_vec(unsigned vece, TCGv_vec d, TCGv_vec n, TCGv_vec m) | |
14107 | { | |
14108 | tcg_gen_rotli_vec(vece, d, m, 1); | |
14109 | tcg_gen_xor_vec(vece, d, d, n); | |
14110 | } | |
14111 | ||
14112 | void gen_gvec_rax1(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, | |
14113 | uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz) | |
14114 | { | |
14115 | static const TCGOpcode vecop_list[] = { INDEX_op_rotli_vec, 0 }; | |
14116 | static const GVecGen3 op = { | |
14117 | .fni8 = gen_rax1_i64, | |
14118 | .fniv = gen_rax1_vec, | |
14119 | .opt_opc = vecop_list, | |
14120 | .fno = gen_helper_crypto_rax1, | |
14121 | .vece = MO_64, | |
14122 | }; | |
14123 | tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, opr_sz, max_sz, &op); | |
14124 | } | |
14125 | ||
90b827d1 AB |
14126 | /* Crypto three-reg SHA512 |
14127 | * 31 21 20 16 15 14 13 12 11 10 9 5 4 0 | |
14128 | * +-----------------------+------+---+---+-----+--------+------+------+ | |
14129 | * | 1 1 0 0 1 1 1 0 0 1 1 | Rm | 1 | O | 0 0 | opcode | Rn | Rd | | |
14130 | * +-----------------------+------+---+---+-----+--------+------+------+ | |
14131 | */ | |
14132 | static void disas_crypto_three_reg_sha512(DisasContext *s, uint32_t insn) | |
14133 | { | |
14134 | int opcode = extract32(insn, 10, 2); | |
14135 | int o = extract32(insn, 14, 1); | |
14136 | int rm = extract32(insn, 16, 5); | |
14137 | int rn = extract32(insn, 5, 5); | |
14138 | int rd = extract32(insn, 0, 5); | |
962fcbf2 | 14139 | bool feature; |
a04b68e1 | 14140 | gen_helper_gvec_3 *oolfn = NULL; |
1738860d | 14141 | GVecGen3Fn *gvecfn = NULL; |
90b827d1 AB |
14142 | |
14143 | if (o == 0) { | |
14144 | switch (opcode) { | |
14145 | case 0: /* SHA512H */ | |
962fcbf2 | 14146 | feature = dc_isar_feature(aa64_sha512, s); |
aaffebd6 | 14147 | oolfn = gen_helper_crypto_sha512h; |
90b827d1 AB |
14148 | break; |
14149 | case 1: /* SHA512H2 */ | |
962fcbf2 | 14150 | feature = dc_isar_feature(aa64_sha512, s); |
aaffebd6 | 14151 | oolfn = gen_helper_crypto_sha512h2; |
90b827d1 AB |
14152 | break; |
14153 | case 2: /* SHA512SU1 */ | |
962fcbf2 | 14154 | feature = dc_isar_feature(aa64_sha512, s); |
aaffebd6 | 14155 | oolfn = gen_helper_crypto_sha512su1; |
90b827d1 | 14156 | break; |
cd270ade | 14157 | case 3: /* RAX1 */ |
962fcbf2 | 14158 | feature = dc_isar_feature(aa64_sha3, s); |
1738860d | 14159 | gvecfn = gen_gvec_rax1; |
cd270ade | 14160 | break; |
c7a5e791 PN |
14161 | default: |
14162 | g_assert_not_reached(); | |
90b827d1 AB |
14163 | } |
14164 | } else { | |
80d6f4c6 AB |
14165 | switch (opcode) { |
14166 | case 0: /* SM3PARTW1 */ | |
962fcbf2 | 14167 | feature = dc_isar_feature(aa64_sm3, s); |
aaffebd6 | 14168 | oolfn = gen_helper_crypto_sm3partw1; |
80d6f4c6 AB |
14169 | break; |
14170 | case 1: /* SM3PARTW2 */ | |
962fcbf2 | 14171 | feature = dc_isar_feature(aa64_sm3, s); |
aaffebd6 | 14172 | oolfn = gen_helper_crypto_sm3partw2; |
80d6f4c6 | 14173 | break; |
b6577bcd | 14174 | case 2: /* SM4EKEY */ |
962fcbf2 | 14175 | feature = dc_isar_feature(aa64_sm4, s); |
a04b68e1 | 14176 | oolfn = gen_helper_crypto_sm4ekey; |
b6577bcd | 14177 | break; |
80d6f4c6 AB |
14178 | default: |
14179 | unallocated_encoding(s); | |
14180 | return; | |
14181 | } | |
90b827d1 AB |
14182 | } |
14183 | ||
962fcbf2 | 14184 | if (!feature) { |
90b827d1 AB |
14185 | unallocated_encoding(s); |
14186 | return; | |
14187 | } | |
14188 | ||
14189 | if (!fp_access_check(s)) { | |
14190 | return; | |
14191 | } | |
14192 | ||
a04b68e1 RH |
14193 | if (oolfn) { |
14194 | gen_gvec_op3_ool(s, true, rd, rn, rm, 0, oolfn); | |
1738860d | 14195 | } else { |
aaffebd6 | 14196 | gen_gvec_fn3(s, true, rd, rn, rm, gvecfn, MO_64); |
90b827d1 AB |
14197 | } |
14198 | } | |
14199 | ||
14200 | /* Crypto two-reg SHA512 | |
14201 | * 31 12 11 10 9 5 4 0 | |
14202 | * +-----------------------------------------+--------+------+------+ | |
14203 | * | 1 1 0 0 1 1 1 0 1 1 0 0 0 0 0 0 1 0 0 0 | opcode | Rn | Rd | | |
14204 | * +-----------------------------------------+--------+------+------+ | |
14205 | */ | |
14206 | static void disas_crypto_two_reg_sha512(DisasContext *s, uint32_t insn) | |
14207 | { | |
14208 | int opcode = extract32(insn, 10, 2); | |
14209 | int rn = extract32(insn, 5, 5); | |
14210 | int rd = extract32(insn, 0, 5); | |
962fcbf2 | 14211 | bool feature; |
90b827d1 AB |
14212 | |
14213 | switch (opcode) { | |
14214 | case 0: /* SHA512SU0 */ | |
962fcbf2 | 14215 | feature = dc_isar_feature(aa64_sha512, s); |
90b827d1 | 14216 | break; |
b6577bcd | 14217 | case 1: /* SM4E */ |
962fcbf2 | 14218 | feature = dc_isar_feature(aa64_sm4, s); |
b6577bcd | 14219 | break; |
90b827d1 AB |
14220 | default: |
14221 | unallocated_encoding(s); | |
14222 | return; | |
14223 | } | |
14224 | ||
962fcbf2 | 14225 | if (!feature) { |
90b827d1 AB |
14226 | unallocated_encoding(s); |
14227 | return; | |
14228 | } | |
14229 | ||
14230 | if (!fp_access_check(s)) { | |
14231 | return; | |
14232 | } | |
14233 | ||
aaffebd6 RH |
14234 | switch (opcode) { |
14235 | case 0: /* SHA512SU0 */ | |
14236 | gen_gvec_op2_ool(s, true, rd, rn, 0, gen_helper_crypto_sha512su0); | |
14237 | break; | |
14238 | case 1: /* SM4E */ | |
14239 | gen_gvec_op3_ool(s, true, rd, rd, rn, 0, gen_helper_crypto_sm4e); | |
14240 | break; | |
14241 | default: | |
14242 | g_assert_not_reached(); | |
a04b68e1 | 14243 | } |
90b827d1 AB |
14244 | } |
14245 | ||
cd270ade AB |
14246 | /* Crypto four-register |
14247 | * 31 23 22 21 20 16 15 14 10 9 5 4 0 | |
14248 | * +-------------------+-----+------+---+------+------+------+ | |
14249 | * | 1 1 0 0 1 1 1 0 0 | Op0 | Rm | 0 | Ra | Rn | Rd | | |
14250 | * +-------------------+-----+------+---+------+------+------+ | |
14251 | */ | |
14252 | static void disas_crypto_four_reg(DisasContext *s, uint32_t insn) | |
14253 | { | |
14254 | int op0 = extract32(insn, 21, 2); | |
14255 | int rm = extract32(insn, 16, 5); | |
14256 | int ra = extract32(insn, 10, 5); | |
14257 | int rn = extract32(insn, 5, 5); | |
14258 | int rd = extract32(insn, 0, 5); | |
962fcbf2 | 14259 | bool feature; |
cd270ade AB |
14260 | |
14261 | switch (op0) { | |
14262 | case 0: /* EOR3 */ | |
14263 | case 1: /* BCAX */ | |
962fcbf2 | 14264 | feature = dc_isar_feature(aa64_sha3, s); |
cd270ade | 14265 | break; |
80d6f4c6 | 14266 | case 2: /* SM3SS1 */ |
962fcbf2 | 14267 | feature = dc_isar_feature(aa64_sm3, s); |
80d6f4c6 | 14268 | break; |
cd270ade AB |
14269 | default: |
14270 | unallocated_encoding(s); | |
14271 | return; | |
14272 | } | |
14273 | ||
962fcbf2 | 14274 | if (!feature) { |
cd270ade AB |
14275 | unallocated_encoding(s); |
14276 | return; | |
14277 | } | |
14278 | ||
14279 | if (!fp_access_check(s)) { | |
14280 | return; | |
14281 | } | |
14282 | ||
14283 | if (op0 < 2) { | |
14284 | TCGv_i64 tcg_op1, tcg_op2, tcg_op3, tcg_res[2]; | |
14285 | int pass; | |
14286 | ||
14287 | tcg_op1 = tcg_temp_new_i64(); | |
14288 | tcg_op2 = tcg_temp_new_i64(); | |
14289 | tcg_op3 = tcg_temp_new_i64(); | |
14290 | tcg_res[0] = tcg_temp_new_i64(); | |
14291 | tcg_res[1] = tcg_temp_new_i64(); | |
14292 | ||
14293 | for (pass = 0; pass < 2; pass++) { | |
14294 | read_vec_element(s, tcg_op1, rn, pass, MO_64); | |
14295 | read_vec_element(s, tcg_op2, rm, pass, MO_64); | |
14296 | read_vec_element(s, tcg_op3, ra, pass, MO_64); | |
14297 | ||
14298 | if (op0 == 0) { | |
14299 | /* EOR3 */ | |
14300 | tcg_gen_xor_i64(tcg_res[pass], tcg_op2, tcg_op3); | |
14301 | } else { | |
14302 | /* BCAX */ | |
14303 | tcg_gen_andc_i64(tcg_res[pass], tcg_op2, tcg_op3); | |
14304 | } | |
14305 | tcg_gen_xor_i64(tcg_res[pass], tcg_res[pass], tcg_op1); | |
14306 | } | |
14307 | write_vec_element(s, tcg_res[0], rd, 0, MO_64); | |
14308 | write_vec_element(s, tcg_res[1], rd, 1, MO_64); | |
14309 | ||
14310 | tcg_temp_free_i64(tcg_op1); | |
14311 | tcg_temp_free_i64(tcg_op2); | |
14312 | tcg_temp_free_i64(tcg_op3); | |
14313 | tcg_temp_free_i64(tcg_res[0]); | |
14314 | tcg_temp_free_i64(tcg_res[1]); | |
14315 | } else { | |
80d6f4c6 AB |
14316 | TCGv_i32 tcg_op1, tcg_op2, tcg_op3, tcg_res, tcg_zero; |
14317 | ||
14318 | tcg_op1 = tcg_temp_new_i32(); | |
14319 | tcg_op2 = tcg_temp_new_i32(); | |
14320 | tcg_op3 = tcg_temp_new_i32(); | |
14321 | tcg_res = tcg_temp_new_i32(); | |
14322 | tcg_zero = tcg_const_i32(0); | |
14323 | ||
14324 | read_vec_element_i32(s, tcg_op1, rn, 3, MO_32); | |
14325 | read_vec_element_i32(s, tcg_op2, rm, 3, MO_32); | |
14326 | read_vec_element_i32(s, tcg_op3, ra, 3, MO_32); | |
14327 | ||
14328 | tcg_gen_rotri_i32(tcg_res, tcg_op1, 20); | |
14329 | tcg_gen_add_i32(tcg_res, tcg_res, tcg_op2); | |
14330 | tcg_gen_add_i32(tcg_res, tcg_res, tcg_op3); | |
14331 | tcg_gen_rotri_i32(tcg_res, tcg_res, 25); | |
14332 | ||
14333 | write_vec_element_i32(s, tcg_zero, rd, 0, MO_32); | |
14334 | write_vec_element_i32(s, tcg_zero, rd, 1, MO_32); | |
14335 | write_vec_element_i32(s, tcg_zero, rd, 2, MO_32); | |
14336 | write_vec_element_i32(s, tcg_res, rd, 3, MO_32); | |
14337 | ||
14338 | tcg_temp_free_i32(tcg_op1); | |
14339 | tcg_temp_free_i32(tcg_op2); | |
14340 | tcg_temp_free_i32(tcg_op3); | |
14341 | tcg_temp_free_i32(tcg_res); | |
14342 | tcg_temp_free_i32(tcg_zero); | |
cd270ade AB |
14343 | } |
14344 | } | |
14345 | ||
14346 | /* Crypto XAR | |
14347 | * 31 21 20 16 15 10 9 5 4 0 | |
14348 | * +-----------------------+------+--------+------+------+ | |
14349 | * | 1 1 0 0 1 1 1 0 1 0 0 | Rm | imm6 | Rn | Rd | | |
14350 | * +-----------------------+------+--------+------+------+ | |
14351 | */ | |
14352 | static void disas_crypto_xar(DisasContext *s, uint32_t insn) | |
14353 | { | |
14354 | int rm = extract32(insn, 16, 5); | |
14355 | int imm6 = extract32(insn, 10, 6); | |
14356 | int rn = extract32(insn, 5, 5); | |
14357 | int rd = extract32(insn, 0, 5); | |
14358 | TCGv_i64 tcg_op1, tcg_op2, tcg_res[2]; | |
14359 | int pass; | |
14360 | ||
962fcbf2 | 14361 | if (!dc_isar_feature(aa64_sha3, s)) { |
cd270ade AB |
14362 | unallocated_encoding(s); |
14363 | return; | |
14364 | } | |
14365 | ||
14366 | if (!fp_access_check(s)) { | |
14367 | return; | |
14368 | } | |
14369 | ||
14370 | tcg_op1 = tcg_temp_new_i64(); | |
14371 | tcg_op2 = tcg_temp_new_i64(); | |
14372 | tcg_res[0] = tcg_temp_new_i64(); | |
14373 | tcg_res[1] = tcg_temp_new_i64(); | |
14374 | ||
14375 | for (pass = 0; pass < 2; pass++) { | |
14376 | read_vec_element(s, tcg_op1, rn, pass, MO_64); | |
14377 | read_vec_element(s, tcg_op2, rm, pass, MO_64); | |
14378 | ||
14379 | tcg_gen_xor_i64(tcg_res[pass], tcg_op1, tcg_op2); | |
14380 | tcg_gen_rotri_i64(tcg_res[pass], tcg_res[pass], imm6); | |
14381 | } | |
14382 | write_vec_element(s, tcg_res[0], rd, 0, MO_64); | |
14383 | write_vec_element(s, tcg_res[1], rd, 1, MO_64); | |
14384 | ||
14385 | tcg_temp_free_i64(tcg_op1); | |
14386 | tcg_temp_free_i64(tcg_op2); | |
14387 | tcg_temp_free_i64(tcg_res[0]); | |
14388 | tcg_temp_free_i64(tcg_res[1]); | |
14389 | } | |
14390 | ||
80d6f4c6 AB |
14391 | /* Crypto three-reg imm2 |
14392 | * 31 21 20 16 15 14 13 12 11 10 9 5 4 0 | |
14393 | * +-----------------------+------+-----+------+--------+------+------+ | |
14394 | * | 1 1 0 0 1 1 1 0 0 1 0 | Rm | 1 0 | imm2 | opcode | Rn | Rd | | |
14395 | * +-----------------------+------+-----+------+--------+------+------+ | |
14396 | */ | |
14397 | static void disas_crypto_three_reg_imm2(DisasContext *s, uint32_t insn) | |
14398 | { | |
43fa36c9 RH |
14399 | static gen_helper_gvec_3 * const fns[4] = { |
14400 | gen_helper_crypto_sm3tt1a, gen_helper_crypto_sm3tt1b, | |
14401 | gen_helper_crypto_sm3tt2a, gen_helper_crypto_sm3tt2b, | |
14402 | }; | |
80d6f4c6 AB |
14403 | int opcode = extract32(insn, 10, 2); |
14404 | int imm2 = extract32(insn, 12, 2); | |
14405 | int rm = extract32(insn, 16, 5); | |
14406 | int rn = extract32(insn, 5, 5); | |
14407 | int rd = extract32(insn, 0, 5); | |
80d6f4c6 | 14408 | |
962fcbf2 | 14409 | if (!dc_isar_feature(aa64_sm3, s)) { |
80d6f4c6 AB |
14410 | unallocated_encoding(s); |
14411 | return; | |
14412 | } | |
14413 | ||
14414 | if (!fp_access_check(s)) { | |
14415 | return; | |
14416 | } | |
14417 | ||
43fa36c9 | 14418 | gen_gvec_op3_ool(s, true, rd, rn, rm, imm2, fns[opcode]); |
80d6f4c6 AB |
14419 | } |
14420 | ||
384b26fb AB |
14421 | /* C3.6 Data processing - SIMD, inc Crypto |
14422 | * | |
14423 | * As the decode gets a little complex we are using a table based | |
14424 | * approach for this part of the decode. | |
14425 | */ | |
14426 | static const AArch64DecodeTable data_proc_simd[] = { | |
14427 | /* pattern , mask , fn */ | |
14428 | { 0x0e200400, 0x9f200400, disas_simd_three_reg_same }, | |
e7186d82 | 14429 | { 0x0e008400, 0x9f208400, disas_simd_three_reg_same_extra }, |
384b26fb AB |
14430 | { 0x0e200000, 0x9f200c00, disas_simd_three_reg_diff }, |
14431 | { 0x0e200800, 0x9f3e0c00, disas_simd_two_reg_misc }, | |
14432 | { 0x0e300800, 0x9f3e0c00, disas_simd_across_lanes }, | |
14433 | { 0x0e000400, 0x9fe08400, disas_simd_copy }, | |
9f82e0ff | 14434 | { 0x0f000000, 0x9f000400, disas_simd_indexed }, /* vector indexed */ |
384b26fb AB |
14435 | /* simd_mod_imm decode is a subset of simd_shift_imm, so must precede it */ |
14436 | { 0x0f000400, 0x9ff80400, disas_simd_mod_imm }, | |
14437 | { 0x0f000400, 0x9f800400, disas_simd_shift_imm }, | |
14438 | { 0x0e000000, 0xbf208c00, disas_simd_tb }, | |
14439 | { 0x0e000800, 0xbf208c00, disas_simd_zip_trn }, | |
14440 | { 0x2e000000, 0xbf208400, disas_simd_ext }, | |
14441 | { 0x5e200400, 0xdf200400, disas_simd_scalar_three_reg_same }, | |
d9061ec3 | 14442 | { 0x5e008400, 0xdf208400, disas_simd_scalar_three_reg_same_extra }, |
384b26fb AB |
14443 | { 0x5e200000, 0xdf200c00, disas_simd_scalar_three_reg_diff }, |
14444 | { 0x5e200800, 0xdf3e0c00, disas_simd_scalar_two_reg_misc }, | |
14445 | { 0x5e300800, 0xdf3e0c00, disas_simd_scalar_pairwise }, | |
14446 | { 0x5e000400, 0xdfe08400, disas_simd_scalar_copy }, | |
9f82e0ff | 14447 | { 0x5f000000, 0xdf000400, disas_simd_indexed }, /* scalar indexed */ |
384b26fb AB |
14448 | { 0x5f000400, 0xdf800400, disas_simd_scalar_shift_imm }, |
14449 | { 0x4e280800, 0xff3e0c00, disas_crypto_aes }, | |
14450 | { 0x5e000000, 0xff208c00, disas_crypto_three_reg_sha }, | |
14451 | { 0x5e280800, 0xff3e0c00, disas_crypto_two_reg_sha }, | |
90b827d1 AB |
14452 | { 0xce608000, 0xffe0b000, disas_crypto_three_reg_sha512 }, |
14453 | { 0xcec08000, 0xfffff000, disas_crypto_two_reg_sha512 }, | |
cd270ade AB |
14454 | { 0xce000000, 0xff808000, disas_crypto_four_reg }, |
14455 | { 0xce800000, 0xffe00000, disas_crypto_xar }, | |
80d6f4c6 | 14456 | { 0xce408000, 0xffe0c000, disas_crypto_three_reg_imm2 }, |
376e8d6c | 14457 | { 0x0e400400, 0x9f60c400, disas_simd_three_reg_same_fp16 }, |
5d432be6 | 14458 | { 0x0e780800, 0x8f7e0c00, disas_simd_two_reg_misc_fp16 }, |
7c93b774 | 14459 | { 0x5e400400, 0xdf60c400, disas_simd_scalar_three_reg_same_fp16 }, |
384b26fb AB |
14460 | { 0x00000000, 0x00000000, NULL } |
14461 | }; | |
14462 | ||
faa0ba46 PM |
14463 | static void disas_data_proc_simd(DisasContext *s, uint32_t insn) |
14464 | { | |
14465 | /* Note that this is called with all non-FP cases from | |
14466 | * table C3-6 so it must UNDEF for entries not specifically | |
14467 | * allocated to instructions in that table. | |
14468 | */ | |
384b26fb AB |
14469 | AArch64DecodeFn *fn = lookup_disas_fn(&data_proc_simd[0], insn); |
14470 | if (fn) { | |
14471 | fn(s, insn); | |
14472 | } else { | |
14473 | unallocated_encoding(s); | |
14474 | } | |
faa0ba46 PM |
14475 | } |
14476 | ||
ad7ee8a2 CF |
14477 | /* C3.6 Data processing - SIMD and floating point */ |
14478 | static void disas_data_proc_simd_fp(DisasContext *s, uint32_t insn) | |
14479 | { | |
faa0ba46 PM |
14480 | if (extract32(insn, 28, 1) == 1 && extract32(insn, 30, 1) == 0) { |
14481 | disas_data_proc_fp(s, insn); | |
14482 | } else { | |
14483 | /* SIMD, including crypto */ | |
14484 | disas_data_proc_simd(s, insn); | |
14485 | } | |
ad7ee8a2 CF |
14486 | } |
14487 | ||
51bf0d7a RH |
14488 | /** |
14489 | * is_guarded_page: | |
14490 | * @env: The cpu environment | |
14491 | * @s: The DisasContext | |
14492 | * | |
14493 | * Return true if the page is guarded. | |
14494 | */ | |
14495 | static bool is_guarded_page(CPUARMState *env, DisasContext *s) | |
14496 | { | |
be5d6f48 | 14497 | uint64_t addr = s->base.pc_first; |
51bf0d7a | 14498 | #ifdef CONFIG_USER_ONLY |
be5d6f48 | 14499 | return page_get_flags(addr) & PAGE_BTI; |
51bf0d7a | 14500 | #else |
51bf0d7a RH |
14501 | int mmu_idx = arm_to_core_mmu_idx(s->mmu_idx); |
14502 | unsigned int index = tlb_index(env, mmu_idx, addr); | |
14503 | CPUTLBEntry *entry = tlb_entry(env, mmu_idx, addr); | |
14504 | ||
14505 | /* | |
14506 | * We test this immediately after reading an insn, which means | |
14507 | * that any normal page must be in the TLB. The only exception | |
14508 | * would be for executing from flash or device memory, which | |
14509 | * does not retain the TLB entry. | |
14510 | * | |
14511 | * FIXME: Assume false for those, for now. We could use | |
14512 | * arm_cpu_get_phys_page_attrs_debug to re-read the page | |
14513 | * table entry even for that case. | |
14514 | */ | |
14515 | return (tlb_hit(entry->addr_code, addr) && | |
149d3b31 | 14516 | arm_tlb_bti_gp(&env_tlb(env)->d[mmu_idx].iotlb[index].attrs)); |
51bf0d7a RH |
14517 | #endif |
14518 | } | |
14519 | ||
14520 | /** | |
14521 | * btype_destination_ok: | |
14522 | * @insn: The instruction at the branch destination | |
14523 | * @bt: SCTLR_ELx.BT | |
14524 | * @btype: PSTATE.BTYPE, and is non-zero | |
14525 | * | |
14526 | * On a guarded page, there are a limited number of insns | |
14527 | * that may be present at the branch target: | |
14528 | * - branch target identifiers, | |
14529 | * - paciasp, pacibsp, | |
14530 | * - BRK insn | |
14531 | * - HLT insn | |
14532 | * Anything else causes a Branch Target Exception. | |
14533 | * | |
14534 | * Return true if the branch is compatible, false to raise BTITRAP. | |
14535 | */ | |
14536 | static bool btype_destination_ok(uint32_t insn, bool bt, int btype) | |
14537 | { | |
14538 | if ((insn & 0xfffff01fu) == 0xd503201fu) { | |
14539 | /* HINT space */ | |
14540 | switch (extract32(insn, 5, 7)) { | |
14541 | case 0b011001: /* PACIASP */ | |
14542 | case 0b011011: /* PACIBSP */ | |
14543 | /* | |
14544 | * If SCTLR_ELx.BT, then PACI*SP are not compatible | |
14545 | * with btype == 3. Otherwise all btype are ok. | |
14546 | */ | |
14547 | return !bt || btype != 3; | |
14548 | case 0b100000: /* BTI */ | |
14549 | /* Not compatible with any btype. */ | |
14550 | return false; | |
14551 | case 0b100010: /* BTI c */ | |
14552 | /* Not compatible with btype == 3 */ | |
14553 | return btype != 3; | |
14554 | case 0b100100: /* BTI j */ | |
14555 | /* Not compatible with btype == 2 */ | |
14556 | return btype != 2; | |
14557 | case 0b100110: /* BTI jc */ | |
14558 | /* Compatible with any btype. */ | |
14559 | return true; | |
14560 | } | |
14561 | } else { | |
14562 | switch (insn & 0xffe0001fu) { | |
14563 | case 0xd4200000u: /* BRK */ | |
14564 | case 0xd4400000u: /* HLT */ | |
14565 | /* Give priority to the breakpoint exception. */ | |
14566 | return true; | |
14567 | } | |
14568 | } | |
14569 | return false; | |
14570 | } | |
14571 | ||
ad7ee8a2 | 14572 | /* C3.1 A64 instruction index by encoding */ |
40f860cd | 14573 | static void disas_a64_insn(CPUARMState *env, DisasContext *s) |
14ade10f AG |
14574 | { |
14575 | uint32_t insn; | |
14576 | ||
a0415916 RH |
14577 | s->pc_curr = s->base.pc_next; |
14578 | insn = arm_ldl_code(env, s->base.pc_next, s->sctlr_b); | |
14ade10f | 14579 | s->insn = insn; |
a0415916 | 14580 | s->base.pc_next += 4; |
14ade10f | 14581 | |
90e49638 | 14582 | s->fp_access_checked = false; |
8a40fe5f | 14583 | s->sve_access_checked = false; |
90e49638 | 14584 | |
51bf0d7a RH |
14585 | if (dc_isar_feature(aa64_bti, s)) { |
14586 | if (s->base.num_insns == 1) { | |
14587 | /* | |
14588 | * At the first insn of the TB, compute s->guarded_page. | |
14589 | * We delayed computing this until successfully reading | |
14590 | * the first insn of the TB, above. This (mostly) ensures | |
14591 | * that the softmmu tlb entry has been populated, and the | |
14592 | * page table GP bit is available. | |
14593 | * | |
14594 | * Note that we need to compute this even if btype == 0, | |
14595 | * because this value is used for BR instructions later | |
14596 | * where ENV is not available. | |
14597 | */ | |
14598 | s->guarded_page = is_guarded_page(env, s); | |
14599 | ||
14600 | /* First insn can have btype set to non-zero. */ | |
14601 | tcg_debug_assert(s->btype >= 0); | |
14602 | ||
14603 | /* | |
14604 | * Note that the Branch Target Exception has fairly high | |
14605 | * priority -- below debugging exceptions but above most | |
14606 | * everything else. This allows us to handle this now | |
14607 | * instead of waiting until the insn is otherwise decoded. | |
14608 | */ | |
14609 | if (s->btype != 0 | |
14610 | && s->guarded_page | |
14611 | && !btype_destination_ok(insn, s->bt, s->btype)) { | |
a767fac8 RH |
14612 | gen_exception_insn(s, s->pc_curr, EXCP_UDEF, |
14613 | syn_btitrap(s->btype), | |
51bf0d7a RH |
14614 | default_exception_el(s)); |
14615 | return; | |
14616 | } | |
14617 | } else { | |
14618 | /* Not the first insn: btype must be 0. */ | |
14619 | tcg_debug_assert(s->btype == 0); | |
14620 | } | |
14621 | } | |
14622 | ||
ad7ee8a2 | 14623 | switch (extract32(insn, 25, 4)) { |
38388f7e | 14624 | case 0x0: case 0x1: case 0x3: /* UNALLOCATED */ |
14ade10f AG |
14625 | unallocated_encoding(s); |
14626 | break; | |
38388f7e | 14627 | case 0x2: |
cd208a1c | 14628 | if (!dc_isar_feature(aa64_sve, s) || !disas_sve(s, insn)) { |
38388f7e RH |
14629 | unallocated_encoding(s); |
14630 | } | |
14631 | break; | |
ad7ee8a2 CF |
14632 | case 0x8: case 0x9: /* Data processing - immediate */ |
14633 | disas_data_proc_imm(s, insn); | |
14634 | break; | |
14635 | case 0xa: case 0xb: /* Branch, exception generation and system insns */ | |
14636 | disas_b_exc_sys(s, insn); | |
14637 | break; | |
14638 | case 0x4: | |
14639 | case 0x6: | |
14640 | case 0xc: | |
14641 | case 0xe: /* Loads and stores */ | |
14642 | disas_ldst(s, insn); | |
14643 | break; | |
14644 | case 0x5: | |
14645 | case 0xd: /* Data processing - register */ | |
14646 | disas_data_proc_reg(s, insn); | |
14647 | break; | |
14648 | case 0x7: | |
14649 | case 0xf: /* Data processing - SIMD and floating point */ | |
14650 | disas_data_proc_simd_fp(s, insn); | |
14651 | break; | |
14652 | default: | |
14653 | assert(FALSE); /* all 15 cases should be handled above */ | |
14654 | break; | |
14ade10f | 14655 | } |
11e169de AG |
14656 | |
14657 | /* if we allocated any temporaries, free them here */ | |
14658 | free_tmp_a64(s); | |
51bf0d7a RH |
14659 | |
14660 | /* | |
14661 | * After execution of most insns, btype is reset to 0. | |
14662 | * Note that we set btype == -1 when the insn sets btype. | |
14663 | */ | |
14664 | if (s->btype > 0 && s->base.is_jmp != DISAS_NORETURN) { | |
14665 | reset_btype(s); | |
14666 | } | |
40f860cd | 14667 | } |
14ade10f | 14668 | |
b542683d EC |
14669 | static void aarch64_tr_init_disas_context(DisasContextBase *dcbase, |
14670 | CPUState *cpu) | |
40f860cd | 14671 | { |
dcba3a8d | 14672 | DisasContext *dc = container_of(dcbase, DisasContext, base); |
5c039906 | 14673 | CPUARMState *env = cpu->env_ptr; |
2fc0cc0e | 14674 | ARMCPU *arm_cpu = env_archcpu(env); |
aad821ac RH |
14675 | uint32_t tb_flags = dc->base.tb->flags; |
14676 | int bound, core_mmu_idx; | |
40f860cd | 14677 | |
962fcbf2 | 14678 | dc->isar = &arm_cpu->isar; |
40f860cd PM |
14679 | dc->condjmp = 0; |
14680 | ||
14681 | dc->aarch64 = 1; | |
cef9ee70 SS |
14682 | /* If we are coming from secure EL0 in a system with a 32-bit EL3, then |
14683 | * there is no secure EL1, so we route exceptions to EL3. | |
14684 | */ | |
14685 | dc->secure_routed_to_el3 = arm_feature(env, ARM_FEATURE_EL3) && | |
14686 | !arm_el_is_aa64(env, 3); | |
40f860cd | 14687 | dc->thumb = 0; |
f9fd40eb | 14688 | dc->sctlr_b = 0; |
aad821ac | 14689 | dc->be_data = FIELD_EX32(tb_flags, TBFLAG_ANY, BE_DATA) ? MO_BE : MO_LE; |
40f860cd PM |
14690 | dc->condexec_mask = 0; |
14691 | dc->condexec_cond = 0; | |
aad821ac | 14692 | core_mmu_idx = FIELD_EX32(tb_flags, TBFLAG_ANY, MMUIDX); |
20dc67c9 | 14693 | dc->mmu_idx = core_to_aa64_mmu_idx(core_mmu_idx); |
476a4692 | 14694 | dc->tbii = FIELD_EX32(tb_flags, TBFLAG_A64, TBII); |
4a9ee99d | 14695 | dc->tbid = FIELD_EX32(tb_flags, TBFLAG_A64, TBID); |
81ae05fa | 14696 | dc->tcma = FIELD_EX32(tb_flags, TBFLAG_A64, TCMA); |
c1e37810 | 14697 | dc->current_el = arm_mmu_idx_to_el(dc->mmu_idx); |
40f860cd | 14698 | #if !defined(CONFIG_USER_ONLY) |
c1e37810 | 14699 | dc->user = (dc->current_el == 0); |
40f860cd | 14700 | #endif |
aad821ac RH |
14701 | dc->fp_excp_el = FIELD_EX32(tb_flags, TBFLAG_ANY, FPEXC_EL); |
14702 | dc->sve_excp_el = FIELD_EX32(tb_flags, TBFLAG_A64, SVEEXC_EL); | |
14703 | dc->sve_len = (FIELD_EX32(tb_flags, TBFLAG_A64, ZCR_LEN) + 1) * 16; | |
0816ef1b | 14704 | dc->pauth_active = FIELD_EX32(tb_flags, TBFLAG_A64, PAUTH_ACTIVE); |
08f1434a RH |
14705 | dc->bt = FIELD_EX32(tb_flags, TBFLAG_A64, BT); |
14706 | dc->btype = FIELD_EX32(tb_flags, TBFLAG_A64, BTYPE); | |
cc28fc30 | 14707 | dc->unpriv = FIELD_EX32(tb_flags, TBFLAG_A64, UNPRIV); |
81ae05fa RH |
14708 | dc->ata = FIELD_EX32(tb_flags, TBFLAG_A64, ATA); |
14709 | dc->mte_active[0] = FIELD_EX32(tb_flags, TBFLAG_A64, MTE_ACTIVE); | |
14710 | dc->mte_active[1] = FIELD_EX32(tb_flags, TBFLAG_A64, MTE0_ACTIVE); | |
40f860cd PM |
14711 | dc->vec_len = 0; |
14712 | dc->vec_stride = 0; | |
5c039906 | 14713 | dc->cp_regs = arm_cpu->cp_regs; |
a984e42c | 14714 | dc->features = env->features; |
5f716a82 | 14715 | dc->dcz_blocksize = arm_cpu->dcz_blocksize; |
40f860cd | 14716 | |
c4af8ba1 RH |
14717 | #ifdef CONFIG_USER_ONLY |
14718 | /* In sve_probe_page, we assume TBI is enabled. */ | |
14719 | tcg_debug_assert(dc->tbid & 1); | |
14720 | #endif | |
14721 | ||
7ea47fe7 PM |
14722 | /* Single step state. The code-generation logic here is: |
14723 | * SS_ACTIVE == 0: | |
14724 | * generate code with no special handling for single-stepping (except | |
14725 | * that anything that can make us go to SS_ACTIVE == 1 must end the TB; | |
14726 | * this happens anyway because those changes are all system register or | |
14727 | * PSTATE writes). | |
14728 | * SS_ACTIVE == 1, PSTATE.SS == 1: (active-not-pending) | |
14729 | * emit code for one insn | |
14730 | * emit code to clear PSTATE.SS | |
14731 | * emit code to generate software step exception for completed step | |
14732 | * end TB (as usual for having generated an exception) | |
14733 | * SS_ACTIVE == 1, PSTATE.SS == 0: (active-pending) | |
14734 | * emit code to generate a software step exception | |
14735 | * end the TB | |
14736 | */ | |
aad821ac RH |
14737 | dc->ss_active = FIELD_EX32(tb_flags, TBFLAG_ANY, SS_ACTIVE); |
14738 | dc->pstate_ss = FIELD_EX32(tb_flags, TBFLAG_ANY, PSTATE_SS); | |
7ea47fe7 | 14739 | dc->is_ldex = false; |
8bd587c1 | 14740 | dc->debug_target_el = FIELD_EX32(tb_flags, TBFLAG_ANY, DEBUG_TARGET_EL); |
7ea47fe7 | 14741 | |
dcc3a212 RH |
14742 | /* Bound the number of insns to execute to those left on the page. */ |
14743 | bound = -(dc->base.pc_first | TARGET_PAGE_MASK) / 4; | |
14744 | ||
14745 | /* If architectural single step active, limit to 1. */ | |
14746 | if (dc->ss_active) { | |
14747 | bound = 1; | |
14748 | } | |
b542683d | 14749 | dc->base.max_insns = MIN(dc->base.max_insns, bound); |
24299c89 | 14750 | |
11e169de | 14751 | init_tmp_a64_array(dc); |
5c039906 LV |
14752 | } |
14753 | ||
23169224 LV |
14754 | static void aarch64_tr_tb_start(DisasContextBase *db, CPUState *cpu) |
14755 | { | |
23169224 LV |
14756 | } |
14757 | ||
a68956ad LV |
14758 | static void aarch64_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) |
14759 | { | |
14760 | DisasContext *dc = container_of(dcbase, DisasContext, base); | |
14761 | ||
a0415916 | 14762 | tcg_gen_insn_start(dc->base.pc_next, 0, 0); |
15fa08f8 | 14763 | dc->insn_start = tcg_last_op(); |
a68956ad LV |
14764 | } |
14765 | ||
0cb56b37 LV |
14766 | static bool aarch64_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu, |
14767 | const CPUBreakpoint *bp) | |
14768 | { | |
14769 | DisasContext *dc = container_of(dcbase, DisasContext, base); | |
14770 | ||
14771 | if (bp->flags & BP_CPU) { | |
a0415916 | 14772 | gen_a64_set_pc_im(dc->base.pc_next); |
0cb56b37 LV |
14773 | gen_helper_check_breakpoints(cpu_env); |
14774 | /* End the TB early; it likely won't be executed */ | |
14775 | dc->base.is_jmp = DISAS_TOO_MANY; | |
14776 | } else { | |
aee828e7 | 14777 | gen_exception_internal_insn(dc, dc->base.pc_next, EXCP_DEBUG); |
0cb56b37 LV |
14778 | /* The address covered by the breakpoint must be |
14779 | included in [tb->pc, tb->pc + tb->size) in order | |
14780 | to for it to be properly cleared -- thus we | |
14781 | increment the PC here so that the logic setting | |
14782 | tb->size below does the right thing. */ | |
a0415916 | 14783 | dc->base.pc_next += 4; |
0cb56b37 LV |
14784 | dc->base.is_jmp = DISAS_NORETURN; |
14785 | } | |
14786 | ||
14787 | return true; | |
14788 | } | |
14789 | ||
24299c89 LV |
14790 | static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) |
14791 | { | |
14792 | DisasContext *dc = container_of(dcbase, DisasContext, base); | |
14793 | CPUARMState *env = cpu->env_ptr; | |
14794 | ||
14795 | if (dc->ss_active && !dc->pstate_ss) { | |
14796 | /* Singlestep state is Active-pending. | |
14797 | * If we're in this state at the start of a TB then either | |
14798 | * a) we just took an exception to an EL which is being debugged | |
14799 | * and this is the first insn in the exception handler | |
14800 | * b) debug exceptions were masked and we just unmasked them | |
14801 | * without changing EL (eg by clearing PSTATE.D) | |
14802 | * In either case we're going to take a swstep exception in the | |
14803 | * "did not step an insn" case, and so the syndrome ISV and EX | |
14804 | * bits should be zero. | |
14805 | */ | |
14806 | assert(dc->base.num_insns == 1); | |
c1d5f50f | 14807 | gen_swstep_exception(dc, 0, 0); |
24299c89 LV |
14808 | dc->base.is_jmp = DISAS_NORETURN; |
14809 | } else { | |
14810 | disas_a64_insn(env, dc); | |
14811 | } | |
14812 | ||
23169224 | 14813 | translator_loop_temp_check(&dc->base); |
24299c89 LV |
14814 | } |
14815 | ||
be407964 LV |
14816 | static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) |
14817 | { | |
14818 | DisasContext *dc = container_of(dcbase, DisasContext, base); | |
14819 | ||
14820 | if (unlikely(dc->base.singlestep_enabled || dc->ss_active)) { | |
14821 | /* Note that this means single stepping WFI doesn't halt the CPU. | |
14822 | * For conditional branch insns this is harmless unreachable code as | |
14823 | * gen_goto_tb() has already handled emitting the debug exception | |
14824 | * (and thus a tb-jump is not possible when singlestepping). | |
14825 | */ | |
14826 | switch (dc->base.is_jmp) { | |
14827 | default: | |
a0415916 | 14828 | gen_a64_set_pc_im(dc->base.pc_next); |
be407964 | 14829 | /* fall through */ |
dddbba99 | 14830 | case DISAS_EXIT: |
be407964 LV |
14831 | case DISAS_JUMP: |
14832 | if (dc->base.singlestep_enabled) { | |
14833 | gen_exception_internal(EXCP_DEBUG); | |
14834 | } else { | |
14835 | gen_step_complete_exception(dc); | |
14836 | } | |
14837 | break; | |
14838 | case DISAS_NORETURN: | |
14839 | break; | |
14840 | } | |
14841 | } else { | |
14842 | switch (dc->base.is_jmp) { | |
14843 | case DISAS_NEXT: | |
14844 | case DISAS_TOO_MANY: | |
a0415916 | 14845 | gen_goto_tb(dc, 1, dc->base.pc_next); |
be407964 LV |
14846 | break; |
14847 | default: | |
14407ec2 | 14848 | case DISAS_UPDATE_EXIT: |
a0415916 | 14849 | gen_a64_set_pc_im(dc->base.pc_next); |
be407964 | 14850 | /* fall through */ |
be407964 | 14851 | case DISAS_EXIT: |
07ea28b4 | 14852 | tcg_gen_exit_tb(NULL, 0); |
be407964 | 14853 | break; |
32983328 RH |
14854 | case DISAS_UPDATE_NOCHAIN: |
14855 | gen_a64_set_pc_im(dc->base.pc_next); | |
14856 | /* fall through */ | |
a75a52d6 VK |
14857 | case DISAS_JUMP: |
14858 | tcg_gen_lookup_and_goto_ptr(); | |
14859 | break; | |
be407964 LV |
14860 | case DISAS_NORETURN: |
14861 | case DISAS_SWI: | |
14862 | break; | |
14863 | case DISAS_WFE: | |
a0415916 | 14864 | gen_a64_set_pc_im(dc->base.pc_next); |
be407964 LV |
14865 | gen_helper_wfe(cpu_env); |
14866 | break; | |
14867 | case DISAS_YIELD: | |
a0415916 | 14868 | gen_a64_set_pc_im(dc->base.pc_next); |
be407964 LV |
14869 | gen_helper_yield(cpu_env); |
14870 | break; | |
14871 | case DISAS_WFI: | |
58803318 | 14872 | { |
be407964 LV |
14873 | /* This is a special case because we don't want to just halt the CPU |
14874 | * if trying to debug across a WFI. | |
14875 | */ | |
58803318 SS |
14876 | TCGv_i32 tmp = tcg_const_i32(4); |
14877 | ||
a0415916 | 14878 | gen_a64_set_pc_im(dc->base.pc_next); |
58803318 SS |
14879 | gen_helper_wfi(cpu_env, tmp); |
14880 | tcg_temp_free_i32(tmp); | |
be407964 LV |
14881 | /* The helper doesn't necessarily throw an exception, but we |
14882 | * must go back to the main loop to check for interrupts anyway. | |
14883 | */ | |
07ea28b4 | 14884 | tcg_gen_exit_tb(NULL, 0); |
be407964 LV |
14885 | break; |
14886 | } | |
58803318 | 14887 | } |
be407964 LV |
14888 | } |
14889 | } | |
14890 | ||
58350fa4 LV |
14891 | static void aarch64_tr_disas_log(const DisasContextBase *dcbase, |
14892 | CPUState *cpu) | |
14893 | { | |
14894 | DisasContext *dc = container_of(dcbase, DisasContext, base); | |
14895 | ||
14896 | qemu_log("IN: %s\n", lookup_symbol(dc->base.pc_first)); | |
1d48474d | 14897 | log_target_disas(cpu, dc->base.pc_first, dc->base.tb->size); |
58350fa4 LV |
14898 | } |
14899 | ||
23169224 LV |
14900 | const TranslatorOps aarch64_translator_ops = { |
14901 | .init_disas_context = aarch64_tr_init_disas_context, | |
14902 | .tb_start = aarch64_tr_tb_start, | |
14903 | .insn_start = aarch64_tr_insn_start, | |
14904 | .breakpoint_check = aarch64_tr_breakpoint_check, | |
14905 | .translate_insn = aarch64_tr_translate_insn, | |
14906 | .tb_stop = aarch64_tr_tb_stop, | |
14907 | .disas_log = aarch64_tr_disas_log, | |
14908 | }; |