]>
Commit | Line | Data |
---|---|---|
14ade10f AG |
1 | /* |
2 | * AArch64 translation | |
3 | * | |
4 | * Copyright (c) 2013 Alexander Graf <agraf@suse.de> | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
74c21bd0 | 19 | #include "qemu/osdep.h" |
14ade10f AG |
20 | |
21 | #include "cpu.h" | |
63c91552 | 22 | #include "exec/exec-all.h" |
dcb32f1d PMD |
23 | #include "tcg/tcg-op.h" |
24 | #include "tcg/tcg-op-gvec.h" | |
14ade10f | 25 | #include "qemu/log.h" |
1d854765 | 26 | #include "arm_ldst.h" |
14ade10f | 27 | #include "translate.h" |
ccd38087 | 28 | #include "internals.h" |
14ade10f AG |
29 | #include "qemu/host-utils.h" |
30 | ||
f1672e6f | 31 | #include "hw/semihosting/semihost.h" |
40f860cd PM |
32 | #include "exec/gen-icount.h" |
33 | ||
2ef6175a RH |
34 | #include "exec/helper-proto.h" |
35 | #include "exec/helper-gen.h" | |
508127e2 | 36 | #include "exec/log.h" |
14ade10f | 37 | |
a7e30d84 | 38 | #include "trace-tcg.h" |
8c71baed | 39 | #include "translate-a64.h" |
62823083 | 40 | #include "qemu/atomic128.h" |
a7e30d84 | 41 | |
14ade10f AG |
42 | static TCGv_i64 cpu_X[32]; |
43 | static TCGv_i64 cpu_pc; | |
14ade10f | 44 | |
fa2ef212 | 45 | /* Load/store exclusive handling */ |
fa2ef212 | 46 | static TCGv_i64 cpu_exclusive_high; |
fa2ef212 | 47 | |
14ade10f AG |
48 | static const char *regnames[] = { |
49 | "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", | |
50 | "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", | |
51 | "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", | |
52 | "x24", "x25", "x26", "x27", "x28", "x29", "lr", "sp" | |
53 | }; | |
54 | ||
832ffa1c AG |
55 | enum a64_shift_type { |
56 | A64_SHIFT_TYPE_LSL = 0, | |
57 | A64_SHIFT_TYPE_LSR = 1, | |
58 | A64_SHIFT_TYPE_ASR = 2, | |
59 | A64_SHIFT_TYPE_ROR = 3 | |
60 | }; | |
61 | ||
384b26fb AB |
62 | /* Table based decoder typedefs - used when the relevant bits for decode |
63 | * are too awkwardly scattered across the instruction (eg SIMD). | |
64 | */ | |
65 | typedef void AArch64DecodeFn(DisasContext *s, uint32_t insn); | |
66 | ||
67 | typedef struct AArch64DecodeTable { | |
68 | uint32_t pattern; | |
69 | uint32_t mask; | |
70 | AArch64DecodeFn *disas_fn; | |
71 | } AArch64DecodeTable; | |
72 | ||
14ade10f AG |
73 | /* initialize TCG globals. */ |
74 | void a64_translate_init(void) | |
75 | { | |
76 | int i; | |
77 | ||
e1ccc054 | 78 | cpu_pc = tcg_global_mem_new_i64(cpu_env, |
14ade10f AG |
79 | offsetof(CPUARMState, pc), |
80 | "pc"); | |
81 | for (i = 0; i < 32; i++) { | |
e1ccc054 | 82 | cpu_X[i] = tcg_global_mem_new_i64(cpu_env, |
14ade10f AG |
83 | offsetof(CPUARMState, xregs[i]), |
84 | regnames[i]); | |
85 | } | |
86 | ||
e1ccc054 | 87 | cpu_exclusive_high = tcg_global_mem_new_i64(cpu_env, |
fa2ef212 | 88 | offsetof(CPUARMState, exclusive_high), "exclusive_high"); |
14ade10f AG |
89 | } |
90 | ||
cc28fc30 RH |
91 | /* |
92 | * Return the core mmu_idx to use for A64 "unprivileged load/store" insns | |
93 | */ | |
94 | static int get_a64_user_mem_index(DisasContext *s) | |
579d21cc | 95 | { |
cc28fc30 RH |
96 | /* |
97 | * If AccType_UNPRIV is not used, the insn uses AccType_NORMAL, | |
98 | * which is the usual mmu_idx for this cpu state. | |
579d21cc | 99 | */ |
cc28fc30 | 100 | ARMMMUIdx useridx = s->mmu_idx; |
8bd5c820 | 101 | |
cc28fc30 RH |
102 | if (s->unpriv) { |
103 | /* | |
104 | * We have pre-computed the condition for AccType_UNPRIV. | |
105 | * Therefore we should never get here with a mmu_idx for | |
106 | * which we do not know the corresponding user mmu_idx. | |
107 | */ | |
108 | switch (useridx) { | |
109 | case ARMMMUIdx_E10_1: | |
452ef8cb | 110 | case ARMMMUIdx_E10_1_PAN: |
cc28fc30 RH |
111 | useridx = ARMMMUIdx_E10_0; |
112 | break; | |
113 | case ARMMMUIdx_E20_2: | |
452ef8cb | 114 | case ARMMMUIdx_E20_2_PAN: |
cc28fc30 RH |
115 | useridx = ARMMMUIdx_E20_0; |
116 | break; | |
117 | case ARMMMUIdx_SE10_1: | |
452ef8cb | 118 | case ARMMMUIdx_SE10_1_PAN: |
cc28fc30 RH |
119 | useridx = ARMMMUIdx_SE10_0; |
120 | break; | |
121 | default: | |
122 | g_assert_not_reached(); | |
123 | } | |
579d21cc | 124 | } |
8bd5c820 | 125 | return arm_to_core_mmu_idx(useridx); |
579d21cc PM |
126 | } |
127 | ||
51bf0d7a RH |
128 | static void reset_btype(DisasContext *s) |
129 | { | |
130 | if (s->btype != 0) { | |
131 | TCGv_i32 zero = tcg_const_i32(0); | |
132 | tcg_gen_st_i32(zero, cpu_env, offsetof(CPUARMState, btype)); | |
133 | tcg_temp_free_i32(zero); | |
134 | s->btype = 0; | |
135 | } | |
136 | } | |
137 | ||
001d47b6 RH |
138 | static void set_btype(DisasContext *s, int val) |
139 | { | |
140 | TCGv_i32 tcg_val; | |
141 | ||
142 | /* BTYPE is a 2-bit field, and 0 should be done with reset_btype. */ | |
143 | tcg_debug_assert(val >= 1 && val <= 3); | |
144 | ||
145 | tcg_val = tcg_const_i32(val); | |
146 | tcg_gen_st_i32(tcg_val, cpu_env, offsetof(CPUARMState, btype)); | |
147 | tcg_temp_free_i32(tcg_val); | |
148 | s->btype = -1; | |
149 | } | |
150 | ||
14ade10f AG |
151 | void gen_a64_set_pc_im(uint64_t val) |
152 | { | |
153 | tcg_gen_movi_i64(cpu_pc, val); | |
154 | } | |
155 | ||
4a9ee99d RH |
156 | /* |
157 | * Handle Top Byte Ignore (TBI) bits. | |
6feecb8b | 158 | * |
4a9ee99d | 159 | * If address tagging is enabled via the TCR TBI bits: |
6feecb8b TH |
160 | * + for EL2 and EL3 there is only one TBI bit, and if it is set |
161 | * then the address is zero-extended, clearing bits [63:56] | |
162 | * + for EL0 and EL1, TBI0 controls addresses with bit 55 == 0 | |
163 | * and TBI1 controls addressses with bit 55 == 1. | |
164 | * If the appropriate TBI bit is set for the address then | |
165 | * the address is sign-extended from bit 55 into bits [63:56] | |
166 | * | |
4a9ee99d | 167 | * Here We have concatenated TBI{1,0} into tbi. |
6feecb8b | 168 | */ |
4a9ee99d RH |
169 | static void gen_top_byte_ignore(DisasContext *s, TCGv_i64 dst, |
170 | TCGv_i64 src, int tbi) | |
6feecb8b | 171 | { |
4a9ee99d RH |
172 | if (tbi == 0) { |
173 | /* Load unmodified address */ | |
174 | tcg_gen_mov_i64(dst, src); | |
339370b9 | 175 | } else if (!regime_has_2_ranges(s->mmu_idx)) { |
4a9ee99d RH |
176 | /* Force tag byte to all zero */ |
177 | tcg_gen_extract_i64(dst, src, 0, 56); | |
178 | } else { | |
179 | /* Sign-extend from bit 55. */ | |
180 | tcg_gen_sextract_i64(dst, src, 0, 56); | |
6feecb8b | 181 | |
4a9ee99d RH |
182 | if (tbi != 3) { |
183 | TCGv_i64 tcg_zero = tcg_const_i64(0); | |
6feecb8b | 184 | |
4a9ee99d RH |
185 | /* |
186 | * The two TBI bits differ. | |
187 | * If tbi0, then !tbi1: only use the extension if positive. | |
188 | * if !tbi0, then tbi1: only use the extension if negative. | |
189 | */ | |
190 | tcg_gen_movcond_i64(tbi == 1 ? TCG_COND_GE : TCG_COND_LT, | |
191 | dst, dst, tcg_zero, dst, src); | |
192 | tcg_temp_free_i64(tcg_zero); | |
6feecb8b TH |
193 | } |
194 | } | |
4a9ee99d | 195 | } |
8733d762 | 196 | |
4a9ee99d RH |
197 | static void gen_a64_set_pc(DisasContext *s, TCGv_i64 src) |
198 | { | |
199 | /* | |
200 | * If address tagging is enabled for instructions via the TCR TBI bits, | |
201 | * then loading an address into the PC will clear out any tag. | |
202 | */ | |
203 | gen_top_byte_ignore(s, cpu_pc, src, s->tbii); | |
6feecb8b TH |
204 | } |
205 | ||
3a471103 | 206 | /* |
0a405be2 RH |
207 | * Handle MTE and/or TBI. |
208 | * | |
209 | * For TBI, ideally, we would do nothing. Proper behaviour on fault is | |
210 | * for the tag to be present in the FAR_ELx register. But for user-only | |
211 | * mode we do not have a TLB with which to implement this, so we must | |
212 | * remove the top byte now. | |
213 | * | |
214 | * Always return a fresh temporary that we can increment independently | |
215 | * of the write-back address. | |
3a471103 | 216 | */ |
0a405be2 | 217 | |
9473d0ec | 218 | TCGv_i64 clean_data_tbi(DisasContext *s, TCGv_i64 addr) |
3a471103 RH |
219 | { |
220 | TCGv_i64 clean = new_tmp_a64(s); | |
38d93168 | 221 | #ifdef CONFIG_USER_ONLY |
3a471103 | 222 | gen_top_byte_ignore(s, clean, addr, s->tbid); |
38d93168 RH |
223 | #else |
224 | tcg_gen_mov_i64(clean, addr); | |
225 | #endif | |
3a471103 RH |
226 | return clean; |
227 | } | |
228 | ||
da54941f RH |
229 | /* Insert a zero tag into src, with the result at dst. */ |
230 | static void gen_address_with_allocation_tag0(TCGv_i64 dst, TCGv_i64 src) | |
231 | { | |
232 | tcg_gen_andi_i64(dst, src, ~MAKE_64BIT_MASK(56, 4)); | |
233 | } | |
234 | ||
c15294c1 RH |
235 | static void gen_probe_access(DisasContext *s, TCGv_i64 ptr, |
236 | MMUAccessType acc, int log2_size) | |
237 | { | |
238 | TCGv_i32 t_acc = tcg_const_i32(acc); | |
239 | TCGv_i32 t_idx = tcg_const_i32(get_mem_index(s)); | |
240 | TCGv_i32 t_size = tcg_const_i32(1 << log2_size); | |
241 | ||
242 | gen_helper_probe_access(cpu_env, ptr, t_acc, t_idx, t_size); | |
243 | tcg_temp_free_i32(t_acc); | |
244 | tcg_temp_free_i32(t_idx); | |
245 | tcg_temp_free_i32(t_size); | |
246 | } | |
247 | ||
0a405be2 RH |
248 | /* |
249 | * For MTE, check a single logical or atomic access. This probes a single | |
250 | * address, the exact one specified. The size and alignment of the access | |
251 | * is not relevant to MTE, per se, but watchpoints do require the size, | |
252 | * and we want to recognize those before making any other changes to state. | |
253 | */ | |
254 | static TCGv_i64 gen_mte_check1_mmuidx(DisasContext *s, TCGv_i64 addr, | |
255 | bool is_write, bool tag_checked, | |
256 | int log2_size, bool is_unpriv, | |
257 | int core_idx) | |
258 | { | |
259 | if (tag_checked && s->mte_active[is_unpriv]) { | |
260 | TCGv_i32 tcg_desc; | |
261 | TCGv_i64 ret; | |
262 | int desc = 0; | |
263 | ||
264 | desc = FIELD_DP32(desc, MTEDESC, MIDX, core_idx); | |
265 | desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid); | |
266 | desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma); | |
267 | desc = FIELD_DP32(desc, MTEDESC, WRITE, is_write); | |
268 | desc = FIELD_DP32(desc, MTEDESC, ESIZE, 1 << log2_size); | |
269 | tcg_desc = tcg_const_i32(desc); | |
270 | ||
271 | ret = new_tmp_a64(s); | |
272 | gen_helper_mte_check1(ret, cpu_env, tcg_desc, addr); | |
273 | tcg_temp_free_i32(tcg_desc); | |
274 | ||
275 | return ret; | |
276 | } | |
277 | return clean_data_tbi(s, addr); | |
278 | } | |
279 | ||
280 | TCGv_i64 gen_mte_check1(DisasContext *s, TCGv_i64 addr, bool is_write, | |
281 | bool tag_checked, int log2_size) | |
282 | { | |
283 | return gen_mte_check1_mmuidx(s, addr, is_write, tag_checked, log2_size, | |
284 | false, get_mem_index(s)); | |
285 | } | |
286 | ||
73ceeb00 RH |
287 | /* |
288 | * For MTE, check multiple logical sequential accesses. | |
289 | */ | |
290 | TCGv_i64 gen_mte_checkN(DisasContext *s, TCGv_i64 addr, bool is_write, | |
291 | bool tag_checked, int log2_esize, int total_size) | |
292 | { | |
293 | if (tag_checked && s->mte_active[0] && total_size != (1 << log2_esize)) { | |
294 | TCGv_i32 tcg_desc; | |
295 | TCGv_i64 ret; | |
296 | int desc = 0; | |
297 | ||
298 | desc = FIELD_DP32(desc, MTEDESC, MIDX, get_mem_index(s)); | |
299 | desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid); | |
300 | desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma); | |
301 | desc = FIELD_DP32(desc, MTEDESC, WRITE, is_write); | |
302 | desc = FIELD_DP32(desc, MTEDESC, ESIZE, 1 << log2_esize); | |
303 | desc = FIELD_DP32(desc, MTEDESC, TSIZE, total_size); | |
304 | tcg_desc = tcg_const_i32(desc); | |
305 | ||
306 | ret = new_tmp_a64(s); | |
307 | gen_helper_mte_checkN(ret, cpu_env, tcg_desc, addr); | |
308 | tcg_temp_free_i32(tcg_desc); | |
309 | ||
310 | return ret; | |
311 | } | |
312 | return gen_mte_check1(s, addr, is_write, tag_checked, log2_esize); | |
313 | } | |
314 | ||
259cb684 RH |
315 | typedef struct DisasCompare64 { |
316 | TCGCond cond; | |
317 | TCGv_i64 value; | |
318 | } DisasCompare64; | |
319 | ||
320 | static void a64_test_cc(DisasCompare64 *c64, int cc) | |
321 | { | |
322 | DisasCompare c32; | |
323 | ||
324 | arm_test_cc(&c32, cc); | |
325 | ||
326 | /* Sign-extend the 32-bit value so that the GE/LT comparisons work | |
327 | * properly. The NE/EQ comparisons are also fine with this choice. */ | |
328 | c64->cond = c32.cond; | |
329 | c64->value = tcg_temp_new_i64(); | |
330 | tcg_gen_ext_i32_i64(c64->value, c32.value); | |
331 | ||
332 | arm_free_cc(&c32); | |
333 | } | |
334 | ||
335 | static void a64_free_cc(DisasCompare64 *c64) | |
336 | { | |
337 | tcg_temp_free_i64(c64->value); | |
338 | } | |
339 | ||
d4a2dc67 | 340 | static void gen_exception_internal(int excp) |
14ade10f | 341 | { |
d4a2dc67 PM |
342 | TCGv_i32 tcg_excp = tcg_const_i32(excp); |
343 | ||
344 | assert(excp_is_internal(excp)); | |
345 | gen_helper_exception_internal(cpu_env, tcg_excp); | |
346 | tcg_temp_free_i32(tcg_excp); | |
347 | } | |
348 | ||
aee828e7 | 349 | static void gen_exception_internal_insn(DisasContext *s, uint64_t pc, int excp) |
d4a2dc67 | 350 | { |
aee828e7 | 351 | gen_a64_set_pc_im(pc); |
d4a2dc67 | 352 | gen_exception_internal(excp); |
dcba3a8d | 353 | s->base.is_jmp = DISAS_NORETURN; |
14ade10f AG |
354 | } |
355 | ||
a767fac8 | 356 | static void gen_exception_insn(DisasContext *s, uint64_t pc, int excp, |
73710361 | 357 | uint32_t syndrome, uint32_t target_el) |
14ade10f | 358 | { |
a767fac8 | 359 | gen_a64_set_pc_im(pc); |
73710361 | 360 | gen_exception(excp, syndrome, target_el); |
dcba3a8d | 361 | s->base.is_jmp = DISAS_NORETURN; |
40f860cd PM |
362 | } |
363 | ||
06bcbda3 | 364 | static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syndrome) |
c900a2e6 PM |
365 | { |
366 | TCGv_i32 tcg_syn; | |
367 | ||
06bcbda3 | 368 | gen_a64_set_pc_im(s->pc_curr); |
c900a2e6 PM |
369 | tcg_syn = tcg_const_i32(syndrome); |
370 | gen_helper_exception_bkpt_insn(cpu_env, tcg_syn); | |
371 | tcg_temp_free_i32(tcg_syn); | |
372 | s->base.is_jmp = DISAS_NORETURN; | |
373 | } | |
374 | ||
7ea47fe7 PM |
375 | static void gen_step_complete_exception(DisasContext *s) |
376 | { | |
377 | /* We just completed step of an insn. Move from Active-not-pending | |
378 | * to Active-pending, and then also take the swstep exception. | |
379 | * This corresponds to making the (IMPDEF) choice to prioritize | |
380 | * swstep exceptions over asynchronous exceptions taken to an exception | |
381 | * level where debug is disabled. This choice has the advantage that | |
382 | * we do not need to maintain internal state corresponding to the | |
383 | * ISV/EX syndrome bits between completion of the step and generation | |
384 | * of the exception, and our syndrome information is always correct. | |
385 | */ | |
386 | gen_ss_advance(s); | |
c1d5f50f | 387 | gen_swstep_exception(s, 1, s->is_ldex); |
dcba3a8d | 388 | s->base.is_jmp = DISAS_NORETURN; |
7ea47fe7 PM |
389 | } |
390 | ||
40f860cd PM |
391 | static inline bool use_goto_tb(DisasContext *s, int n, uint64_t dest) |
392 | { | |
7ea47fe7 PM |
393 | /* No direct tb linking with singlestep (either QEMU's or the ARM |
394 | * debug architecture kind) or deterministic io | |
395 | */ | |
c5a49c63 EC |
396 | if (s->base.singlestep_enabled || s->ss_active || |
397 | (tb_cflags(s->base.tb) & CF_LAST_IO)) { | |
40f860cd PM |
398 | return false; |
399 | } | |
400 | ||
90aa39a1 | 401 | #ifndef CONFIG_USER_ONLY |
40f860cd | 402 | /* Only link tbs from inside the same guest page */ |
dcba3a8d | 403 | if ((s->base.tb->pc & TARGET_PAGE_MASK) != (dest & TARGET_PAGE_MASK)) { |
40f860cd PM |
404 | return false; |
405 | } | |
90aa39a1 | 406 | #endif |
40f860cd PM |
407 | |
408 | return true; | |
409 | } | |
410 | ||
411 | static inline void gen_goto_tb(DisasContext *s, int n, uint64_t dest) | |
412 | { | |
413 | TranslationBlock *tb; | |
414 | ||
dcba3a8d | 415 | tb = s->base.tb; |
40f860cd PM |
416 | if (use_goto_tb(s, n, dest)) { |
417 | tcg_gen_goto_tb(n); | |
418 | gen_a64_set_pc_im(dest); | |
07ea28b4 | 419 | tcg_gen_exit_tb(tb, n); |
dcba3a8d | 420 | s->base.is_jmp = DISAS_NORETURN; |
40f860cd PM |
421 | } else { |
422 | gen_a64_set_pc_im(dest); | |
7ea47fe7 PM |
423 | if (s->ss_active) { |
424 | gen_step_complete_exception(s); | |
dcba3a8d | 425 | } else if (s->base.singlestep_enabled) { |
d4a2dc67 | 426 | gen_exception_internal(EXCP_DEBUG); |
cc9c1ed1 | 427 | } else { |
7f11636d | 428 | tcg_gen_lookup_and_goto_ptr(); |
dcba3a8d | 429 | s->base.is_jmp = DISAS_NORETURN; |
40f860cd | 430 | } |
40f860cd | 431 | } |
14ade10f AG |
432 | } |
433 | ||
429a71d6 RH |
434 | void unallocated_encoding(DisasContext *s) |
435 | { | |
436 | /* Unallocated and reserved encodings are uncategorized */ | |
437 | gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(), | |
438 | default_exception_el(s)); | |
439 | } | |
440 | ||
11e169de AG |
441 | static void init_tmp_a64_array(DisasContext *s) |
442 | { | |
443 | #ifdef CONFIG_DEBUG_TCG | |
f764718d | 444 | memset(s->tmp_a64, 0, sizeof(s->tmp_a64)); |
11e169de AG |
445 | #endif |
446 | s->tmp_a64_count = 0; | |
447 | } | |
448 | ||
449 | static void free_tmp_a64(DisasContext *s) | |
450 | { | |
451 | int i; | |
452 | for (i = 0; i < s->tmp_a64_count; i++) { | |
453 | tcg_temp_free_i64(s->tmp_a64[i]); | |
454 | } | |
455 | init_tmp_a64_array(s); | |
456 | } | |
457 | ||
8c71baed | 458 | TCGv_i64 new_tmp_a64(DisasContext *s) |
11e169de AG |
459 | { |
460 | assert(s->tmp_a64_count < TMP_A64_MAX); | |
461 | return s->tmp_a64[s->tmp_a64_count++] = tcg_temp_new_i64(); | |
462 | } | |
463 | ||
8c71baed | 464 | TCGv_i64 new_tmp_a64_zero(DisasContext *s) |
11e169de AG |
465 | { |
466 | TCGv_i64 t = new_tmp_a64(s); | |
467 | tcg_gen_movi_i64(t, 0); | |
468 | return t; | |
469 | } | |
470 | ||
71b46089 AG |
471 | /* |
472 | * Register access functions | |
473 | * | |
474 | * These functions are used for directly accessing a register in where | |
475 | * changes to the final register value are likely to be made. If you | |
476 | * need to use a register for temporary calculation (e.g. index type | |
477 | * operations) use the read_* form. | |
478 | * | |
479 | * B1.2.1 Register mappings | |
480 | * | |
481 | * In instruction register encoding 31 can refer to ZR (zero register) or | |
482 | * the SP (stack pointer) depending on context. In QEMU's case we map SP | |
483 | * to cpu_X[31] and ZR accesses to a temporary which can be discarded. | |
484 | * This is the point of the _sp forms. | |
485 | */ | |
8c71baed | 486 | TCGv_i64 cpu_reg(DisasContext *s, int reg) |
11e169de AG |
487 | { |
488 | if (reg == 31) { | |
489 | return new_tmp_a64_zero(s); | |
490 | } else { | |
491 | return cpu_X[reg]; | |
492 | } | |
493 | } | |
494 | ||
71b46089 | 495 | /* register access for when 31 == SP */ |
8c71baed | 496 | TCGv_i64 cpu_reg_sp(DisasContext *s, int reg) |
71b46089 AG |
497 | { |
498 | return cpu_X[reg]; | |
499 | } | |
500 | ||
60e53388 AG |
501 | /* read a cpu register in 32bit/64bit mode. Returns a TCGv_i64 |
502 | * representing the register contents. This TCGv is an auto-freed | |
503 | * temporary so it need not be explicitly freed, and may be modified. | |
504 | */ | |
8c71baed | 505 | TCGv_i64 read_cpu_reg(DisasContext *s, int reg, int sf) |
60e53388 AG |
506 | { |
507 | TCGv_i64 v = new_tmp_a64(s); | |
508 | if (reg != 31) { | |
509 | if (sf) { | |
510 | tcg_gen_mov_i64(v, cpu_X[reg]); | |
511 | } else { | |
512 | tcg_gen_ext32u_i64(v, cpu_X[reg]); | |
513 | } | |
514 | } else { | |
515 | tcg_gen_movi_i64(v, 0); | |
516 | } | |
517 | return v; | |
518 | } | |
519 | ||
8c71baed | 520 | TCGv_i64 read_cpu_reg_sp(DisasContext *s, int reg, int sf) |
4a08d475 PM |
521 | { |
522 | TCGv_i64 v = new_tmp_a64(s); | |
523 | if (sf) { | |
524 | tcg_gen_mov_i64(v, cpu_X[reg]); | |
525 | } else { | |
526 | tcg_gen_ext32u_i64(v, cpu_X[reg]); | |
527 | } | |
528 | return v; | |
529 | } | |
530 | ||
e2f90565 PM |
531 | /* Return the offset into CPUARMState of a slice (from |
532 | * the least significant end) of FP register Qn (ie | |
533 | * Dn, Sn, Hn or Bn). | |
534 | * (Note that this is not the same mapping as for A32; see cpu.h) | |
535 | */ | |
14776ab5 | 536 | static inline int fp_reg_offset(DisasContext *s, int regno, MemOp size) |
e2f90565 | 537 | { |
9a2b5256 | 538 | return vec_reg_offset(s, regno, 0, size); |
e2f90565 PM |
539 | } |
540 | ||
541 | /* Offset of the high half of the 128 bit vector Qn */ | |
90e49638 | 542 | static inline int fp_reg_hi_offset(DisasContext *s, int regno) |
e2f90565 | 543 | { |
9a2b5256 | 544 | return vec_reg_offset(s, regno, 1, MO_64); |
e2f90565 PM |
545 | } |
546 | ||
ec73d2e0 AG |
547 | /* Convenience accessors for reading and writing single and double |
548 | * FP registers. Writing clears the upper parts of the associated | |
549 | * 128 bit vector register, as required by the architecture. | |
550 | * Note that unlike the GP register accessors, the values returned | |
551 | * by the read functions must be manually freed. | |
552 | */ | |
553 | static TCGv_i64 read_fp_dreg(DisasContext *s, int reg) | |
554 | { | |
555 | TCGv_i64 v = tcg_temp_new_i64(); | |
556 | ||
90e49638 | 557 | tcg_gen_ld_i64(v, cpu_env, fp_reg_offset(s, reg, MO_64)); |
ec73d2e0 AG |
558 | return v; |
559 | } | |
560 | ||
561 | static TCGv_i32 read_fp_sreg(DisasContext *s, int reg) | |
562 | { | |
563 | TCGv_i32 v = tcg_temp_new_i32(); | |
564 | ||
90e49638 | 565 | tcg_gen_ld_i32(v, cpu_env, fp_reg_offset(s, reg, MO_32)); |
ec73d2e0 AG |
566 | return v; |
567 | } | |
568 | ||
3d99d931 RH |
569 | static TCGv_i32 read_fp_hreg(DisasContext *s, int reg) |
570 | { | |
571 | TCGv_i32 v = tcg_temp_new_i32(); | |
572 | ||
573 | tcg_gen_ld16u_i32(v, cpu_env, fp_reg_offset(s, reg, MO_16)); | |
574 | return v; | |
575 | } | |
576 | ||
4ff55bcb RH |
577 | /* Clear the bits above an N-bit vector, for N = (is_q ? 128 : 64). |
578 | * If SVE is not enabled, then there are only 128 bits in the vector. | |
579 | */ | |
580 | static void clear_vec_high(DisasContext *s, bool is_q, int rd) | |
581 | { | |
582 | unsigned ofs = fp_reg_offset(s, rd, MO_64); | |
583 | unsigned vsz = vec_full_reg_size(s); | |
584 | ||
5c27392d RH |
585 | /* Nop move, with side effect of clearing the tail. */ |
586 | tcg_gen_gvec_mov(MO_64, ofs, ofs, is_q ? 16 : 8, vsz); | |
4ff55bcb RH |
587 | } |
588 | ||
8c71baed | 589 | void write_fp_dreg(DisasContext *s, int reg, TCGv_i64 v) |
ec73d2e0 | 590 | { |
4ff55bcb | 591 | unsigned ofs = fp_reg_offset(s, reg, MO_64); |
ec73d2e0 | 592 | |
4ff55bcb RH |
593 | tcg_gen_st_i64(v, cpu_env, ofs); |
594 | clear_vec_high(s, false, reg); | |
ec73d2e0 AG |
595 | } |
596 | ||
597 | static void write_fp_sreg(DisasContext *s, int reg, TCGv_i32 v) | |
598 | { | |
599 | TCGv_i64 tmp = tcg_temp_new_i64(); | |
600 | ||
601 | tcg_gen_extu_i32_i64(tmp, v); | |
602 | write_fp_dreg(s, reg, tmp); | |
603 | tcg_temp_free_i64(tmp); | |
604 | } | |
605 | ||
8c71baed | 606 | TCGv_ptr get_fpstatus_ptr(bool is_f16) |
ec73d2e0 AG |
607 | { |
608 | TCGv_ptr statusptr = tcg_temp_new_ptr(); | |
609 | int offset; | |
610 | ||
d81ce0ef AB |
611 | /* In A64 all instructions (both FP and Neon) use the FPCR; there |
612 | * is no equivalent of the A32 Neon "standard FPSCR value". | |
613 | * However half-precision operations operate under a different | |
614 | * FZ16 flag and use vfp.fp_status_f16 instead of vfp.fp_status. | |
ec73d2e0 | 615 | */ |
d81ce0ef AB |
616 | if (is_f16) { |
617 | offset = offsetof(CPUARMState, vfp.fp_status_f16); | |
618 | } else { | |
619 | offset = offsetof(CPUARMState, vfp.fp_status); | |
620 | } | |
ec73d2e0 AG |
621 | tcg_gen_addi_ptr(statusptr, cpu_env, offset); |
622 | return statusptr; | |
623 | } | |
624 | ||
377ef731 RH |
625 | /* Expand a 2-operand AdvSIMD vector operation using an expander function. */ |
626 | static void gen_gvec_fn2(DisasContext *s, bool is_q, int rd, int rn, | |
627 | GVecGen2Fn *gvec_fn, int vece) | |
628 | { | |
629 | gvec_fn(vece, vec_full_reg_offset(s, rd), vec_full_reg_offset(s, rn), | |
630 | is_q ? 16 : 8, vec_full_reg_size(s)); | |
631 | } | |
632 | ||
cdb45a60 RH |
633 | /* Expand a 2-operand + immediate AdvSIMD vector operation using |
634 | * an expander function. | |
635 | */ | |
636 | static void gen_gvec_fn2i(DisasContext *s, bool is_q, int rd, int rn, | |
637 | int64_t imm, GVecGen2iFn *gvec_fn, int vece) | |
638 | { | |
639 | gvec_fn(vece, vec_full_reg_offset(s, rd), vec_full_reg_offset(s, rn), | |
640 | imm, is_q ? 16 : 8, vec_full_reg_size(s)); | |
641 | } | |
642 | ||
bc48092f RH |
643 | /* Expand a 3-operand AdvSIMD vector operation using an expander function. */ |
644 | static void gen_gvec_fn3(DisasContext *s, bool is_q, int rd, int rn, int rm, | |
645 | GVecGen3Fn *gvec_fn, int vece) | |
646 | { | |
647 | gvec_fn(vece, vec_full_reg_offset(s, rd), vec_full_reg_offset(s, rn), | |
648 | vec_full_reg_offset(s, rm), is_q ? 16 : 8, vec_full_reg_size(s)); | |
649 | } | |
650 | ||
3a7a2b4e RH |
651 | /* Expand a 4-operand AdvSIMD vector operation using an expander function. */ |
652 | static void gen_gvec_fn4(DisasContext *s, bool is_q, int rd, int rn, int rm, | |
653 | int rx, GVecGen4Fn *gvec_fn, int vece) | |
654 | { | |
655 | gvec_fn(vece, vec_full_reg_offset(s, rd), vec_full_reg_offset(s, rn), | |
656 | vec_full_reg_offset(s, rm), vec_full_reg_offset(s, rx), | |
657 | is_q ? 16 : 8, vec_full_reg_size(s)); | |
658 | } | |
659 | ||
a04b68e1 RH |
660 | /* Expand a 2-operand operation using an out-of-line helper. */ |
661 | static void gen_gvec_op2_ool(DisasContext *s, bool is_q, int rd, | |
662 | int rn, int data, gen_helper_gvec_2 *fn) | |
663 | { | |
664 | tcg_gen_gvec_2_ool(vec_full_reg_offset(s, rd), | |
665 | vec_full_reg_offset(s, rn), | |
666 | is_q ? 16 : 8, vec_full_reg_size(s), data, fn); | |
667 | } | |
668 | ||
26c470a7 RH |
669 | /* Expand a 3-operand operation using an out-of-line helper. */ |
670 | static void gen_gvec_op3_ool(DisasContext *s, bool is_q, int rd, | |
671 | int rn, int rm, int data, gen_helper_gvec_3 *fn) | |
672 | { | |
673 | tcg_gen_gvec_3_ool(vec_full_reg_offset(s, rd), | |
674 | vec_full_reg_offset(s, rn), | |
675 | vec_full_reg_offset(s, rm), | |
676 | is_q ? 16 : 8, vec_full_reg_size(s), data, fn); | |
677 | } | |
678 | ||
1695cd61 RH |
679 | /* Expand a 3-operand + fpstatus pointer + simd data value operation using |
680 | * an out-of-line helper. | |
681 | */ | |
682 | static void gen_gvec_op3_fpst(DisasContext *s, bool is_q, int rd, int rn, | |
683 | int rm, bool is_fp16, int data, | |
684 | gen_helper_gvec_3_ptr *fn) | |
685 | { | |
686 | TCGv_ptr fpst = get_fpstatus_ptr(is_fp16); | |
687 | tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd), | |
688 | vec_full_reg_offset(s, rn), | |
689 | vec_full_reg_offset(s, rm), fpst, | |
690 | is_q ? 16 : 8, vec_full_reg_size(s), data, fn); | |
691 | tcg_temp_free_ptr(fpst); | |
692 | } | |
693 | ||
832ffa1c AG |
694 | /* Set ZF and NF based on a 64 bit result. This is alas fiddlier |
695 | * than the 32 bit equivalent. | |
696 | */ | |
697 | static inline void gen_set_NZ64(TCGv_i64 result) | |
698 | { | |
7cb36e18 RH |
699 | tcg_gen_extr_i64_i32(cpu_ZF, cpu_NF, result); |
700 | tcg_gen_or_i32(cpu_ZF, cpu_ZF, cpu_NF); | |
832ffa1c AG |
701 | } |
702 | ||
703 | /* Set NZCV as for a logical operation: NZ as per result, CV cleared. */ | |
704 | static inline void gen_logic_CC(int sf, TCGv_i64 result) | |
705 | { | |
706 | if (sf) { | |
707 | gen_set_NZ64(result); | |
708 | } else { | |
ecc7b3aa | 709 | tcg_gen_extrl_i64_i32(cpu_ZF, result); |
7cb36e18 | 710 | tcg_gen_mov_i32(cpu_NF, cpu_ZF); |
832ffa1c AG |
711 | } |
712 | tcg_gen_movi_i32(cpu_CF, 0); | |
713 | tcg_gen_movi_i32(cpu_VF, 0); | |
714 | } | |
715 | ||
b0ff21b4 AB |
716 | /* dest = T0 + T1; compute C, N, V and Z flags */ |
717 | static void gen_add_CC(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1) | |
718 | { | |
719 | if (sf) { | |
720 | TCGv_i64 result, flag, tmp; | |
721 | result = tcg_temp_new_i64(); | |
722 | flag = tcg_temp_new_i64(); | |
723 | tmp = tcg_temp_new_i64(); | |
724 | ||
725 | tcg_gen_movi_i64(tmp, 0); | |
726 | tcg_gen_add2_i64(result, flag, t0, tmp, t1, tmp); | |
727 | ||
ecc7b3aa | 728 | tcg_gen_extrl_i64_i32(cpu_CF, flag); |
b0ff21b4 AB |
729 | |
730 | gen_set_NZ64(result); | |
731 | ||
732 | tcg_gen_xor_i64(flag, result, t0); | |
733 | tcg_gen_xor_i64(tmp, t0, t1); | |
734 | tcg_gen_andc_i64(flag, flag, tmp); | |
735 | tcg_temp_free_i64(tmp); | |
7cb36e18 | 736 | tcg_gen_extrh_i64_i32(cpu_VF, flag); |
b0ff21b4 AB |
737 | |
738 | tcg_gen_mov_i64(dest, result); | |
739 | tcg_temp_free_i64(result); | |
740 | tcg_temp_free_i64(flag); | |
741 | } else { | |
742 | /* 32 bit arithmetic */ | |
743 | TCGv_i32 t0_32 = tcg_temp_new_i32(); | |
744 | TCGv_i32 t1_32 = tcg_temp_new_i32(); | |
745 | TCGv_i32 tmp = tcg_temp_new_i32(); | |
746 | ||
747 | tcg_gen_movi_i32(tmp, 0); | |
ecc7b3aa RH |
748 | tcg_gen_extrl_i64_i32(t0_32, t0); |
749 | tcg_gen_extrl_i64_i32(t1_32, t1); | |
b0ff21b4 AB |
750 | tcg_gen_add2_i32(cpu_NF, cpu_CF, t0_32, tmp, t1_32, tmp); |
751 | tcg_gen_mov_i32(cpu_ZF, cpu_NF); | |
752 | tcg_gen_xor_i32(cpu_VF, cpu_NF, t0_32); | |
753 | tcg_gen_xor_i32(tmp, t0_32, t1_32); | |
754 | tcg_gen_andc_i32(cpu_VF, cpu_VF, tmp); | |
755 | tcg_gen_extu_i32_i64(dest, cpu_NF); | |
756 | ||
757 | tcg_temp_free_i32(tmp); | |
758 | tcg_temp_free_i32(t0_32); | |
759 | tcg_temp_free_i32(t1_32); | |
760 | } | |
761 | } | |
762 | ||
763 | /* dest = T0 - T1; compute C, N, V and Z flags */ | |
764 | static void gen_sub_CC(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1) | |
765 | { | |
766 | if (sf) { | |
767 | /* 64 bit arithmetic */ | |
768 | TCGv_i64 result, flag, tmp; | |
769 | ||
770 | result = tcg_temp_new_i64(); | |
771 | flag = tcg_temp_new_i64(); | |
772 | tcg_gen_sub_i64(result, t0, t1); | |
773 | ||
774 | gen_set_NZ64(result); | |
775 | ||
776 | tcg_gen_setcond_i64(TCG_COND_GEU, flag, t0, t1); | |
ecc7b3aa | 777 | tcg_gen_extrl_i64_i32(cpu_CF, flag); |
b0ff21b4 AB |
778 | |
779 | tcg_gen_xor_i64(flag, result, t0); | |
780 | tmp = tcg_temp_new_i64(); | |
781 | tcg_gen_xor_i64(tmp, t0, t1); | |
782 | tcg_gen_and_i64(flag, flag, tmp); | |
783 | tcg_temp_free_i64(tmp); | |
7cb36e18 | 784 | tcg_gen_extrh_i64_i32(cpu_VF, flag); |
b0ff21b4 AB |
785 | tcg_gen_mov_i64(dest, result); |
786 | tcg_temp_free_i64(flag); | |
787 | tcg_temp_free_i64(result); | |
788 | } else { | |
789 | /* 32 bit arithmetic */ | |
790 | TCGv_i32 t0_32 = tcg_temp_new_i32(); | |
791 | TCGv_i32 t1_32 = tcg_temp_new_i32(); | |
792 | TCGv_i32 tmp; | |
793 | ||
ecc7b3aa RH |
794 | tcg_gen_extrl_i64_i32(t0_32, t0); |
795 | tcg_gen_extrl_i64_i32(t1_32, t1); | |
b0ff21b4 AB |
796 | tcg_gen_sub_i32(cpu_NF, t0_32, t1_32); |
797 | tcg_gen_mov_i32(cpu_ZF, cpu_NF); | |
798 | tcg_gen_setcond_i32(TCG_COND_GEU, cpu_CF, t0_32, t1_32); | |
799 | tcg_gen_xor_i32(cpu_VF, cpu_NF, t0_32); | |
800 | tmp = tcg_temp_new_i32(); | |
801 | tcg_gen_xor_i32(tmp, t0_32, t1_32); | |
802 | tcg_temp_free_i32(t0_32); | |
803 | tcg_temp_free_i32(t1_32); | |
804 | tcg_gen_and_i32(cpu_VF, cpu_VF, tmp); | |
805 | tcg_temp_free_i32(tmp); | |
806 | tcg_gen_extu_i32_i64(dest, cpu_NF); | |
807 | } | |
808 | } | |
809 | ||
643dbb07 CF |
810 | /* dest = T0 + T1 + CF; do not compute flags. */ |
811 | static void gen_adc(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1) | |
812 | { | |
813 | TCGv_i64 flag = tcg_temp_new_i64(); | |
814 | tcg_gen_extu_i32_i64(flag, cpu_CF); | |
815 | tcg_gen_add_i64(dest, t0, t1); | |
816 | tcg_gen_add_i64(dest, dest, flag); | |
817 | tcg_temp_free_i64(flag); | |
818 | ||
819 | if (!sf) { | |
820 | tcg_gen_ext32u_i64(dest, dest); | |
821 | } | |
822 | } | |
823 | ||
824 | /* dest = T0 + T1 + CF; compute C, N, V and Z flags. */ | |
825 | static void gen_adc_CC(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1) | |
826 | { | |
827 | if (sf) { | |
828 | TCGv_i64 result, cf_64, vf_64, tmp; | |
829 | result = tcg_temp_new_i64(); | |
830 | cf_64 = tcg_temp_new_i64(); | |
831 | vf_64 = tcg_temp_new_i64(); | |
832 | tmp = tcg_const_i64(0); | |
833 | ||
834 | tcg_gen_extu_i32_i64(cf_64, cpu_CF); | |
835 | tcg_gen_add2_i64(result, cf_64, t0, tmp, cf_64, tmp); | |
836 | tcg_gen_add2_i64(result, cf_64, result, cf_64, t1, tmp); | |
ecc7b3aa | 837 | tcg_gen_extrl_i64_i32(cpu_CF, cf_64); |
643dbb07 CF |
838 | gen_set_NZ64(result); |
839 | ||
840 | tcg_gen_xor_i64(vf_64, result, t0); | |
841 | tcg_gen_xor_i64(tmp, t0, t1); | |
842 | tcg_gen_andc_i64(vf_64, vf_64, tmp); | |
7cb36e18 | 843 | tcg_gen_extrh_i64_i32(cpu_VF, vf_64); |
643dbb07 CF |
844 | |
845 | tcg_gen_mov_i64(dest, result); | |
846 | ||
847 | tcg_temp_free_i64(tmp); | |
848 | tcg_temp_free_i64(vf_64); | |
849 | tcg_temp_free_i64(cf_64); | |
850 | tcg_temp_free_i64(result); | |
851 | } else { | |
852 | TCGv_i32 t0_32, t1_32, tmp; | |
853 | t0_32 = tcg_temp_new_i32(); | |
854 | t1_32 = tcg_temp_new_i32(); | |
855 | tmp = tcg_const_i32(0); | |
856 | ||
ecc7b3aa RH |
857 | tcg_gen_extrl_i64_i32(t0_32, t0); |
858 | tcg_gen_extrl_i64_i32(t1_32, t1); | |
643dbb07 CF |
859 | tcg_gen_add2_i32(cpu_NF, cpu_CF, t0_32, tmp, cpu_CF, tmp); |
860 | tcg_gen_add2_i32(cpu_NF, cpu_CF, cpu_NF, cpu_CF, t1_32, tmp); | |
861 | ||
862 | tcg_gen_mov_i32(cpu_ZF, cpu_NF); | |
863 | tcg_gen_xor_i32(cpu_VF, cpu_NF, t0_32); | |
864 | tcg_gen_xor_i32(tmp, t0_32, t1_32); | |
865 | tcg_gen_andc_i32(cpu_VF, cpu_VF, tmp); | |
866 | tcg_gen_extu_i32_i64(dest, cpu_NF); | |
867 | ||
868 | tcg_temp_free_i32(tmp); | |
869 | tcg_temp_free_i32(t1_32); | |
870 | tcg_temp_free_i32(t0_32); | |
871 | } | |
872 | } | |
873 | ||
4a08d475 PM |
874 | /* |
875 | * Load/Store generators | |
876 | */ | |
877 | ||
878 | /* | |
60510aed | 879 | * Store from GPR register to memory. |
4a08d475 | 880 | */ |
60510aed | 881 | static void do_gpr_st_memidx(DisasContext *s, TCGv_i64 source, |
aaa1f954 EI |
882 | TCGv_i64 tcg_addr, int size, int memidx, |
883 | bool iss_valid, | |
884 | unsigned int iss_srt, | |
885 | bool iss_sf, bool iss_ar) | |
60510aed PM |
886 | { |
887 | g_assert(size <= 3); | |
aa6489da | 888 | tcg_gen_qemu_st_i64(source, tcg_addr, memidx, s->be_data + size); |
aaa1f954 EI |
889 | |
890 | if (iss_valid) { | |
891 | uint32_t syn; | |
892 | ||
893 | syn = syn_data_abort_with_iss(0, | |
894 | size, | |
895 | false, | |
896 | iss_srt, | |
897 | iss_sf, | |
898 | iss_ar, | |
899 | 0, 0, 0, 0, 0, false); | |
900 | disas_set_insn_syndrome(s, syn); | |
901 | } | |
60510aed PM |
902 | } |
903 | ||
4a08d475 | 904 | static void do_gpr_st(DisasContext *s, TCGv_i64 source, |
aaa1f954 EI |
905 | TCGv_i64 tcg_addr, int size, |
906 | bool iss_valid, | |
907 | unsigned int iss_srt, | |
908 | bool iss_sf, bool iss_ar) | |
4a08d475 | 909 | { |
aaa1f954 EI |
910 | do_gpr_st_memidx(s, source, tcg_addr, size, get_mem_index(s), |
911 | iss_valid, iss_srt, iss_sf, iss_ar); | |
4a08d475 PM |
912 | } |
913 | ||
914 | /* | |
915 | * Load from memory to GPR register | |
916 | */ | |
aaa1f954 EI |
917 | static void do_gpr_ld_memidx(DisasContext *s, |
918 | TCGv_i64 dest, TCGv_i64 tcg_addr, | |
919 | int size, bool is_signed, | |
920 | bool extend, int memidx, | |
921 | bool iss_valid, unsigned int iss_srt, | |
922 | bool iss_sf, bool iss_ar) | |
4a08d475 | 923 | { |
14776ab5 | 924 | MemOp memop = s->be_data + size; |
4a08d475 PM |
925 | |
926 | g_assert(size <= 3); | |
927 | ||
928 | if (is_signed) { | |
929 | memop += MO_SIGN; | |
930 | } | |
931 | ||
60510aed | 932 | tcg_gen_qemu_ld_i64(dest, tcg_addr, memidx, memop); |
4a08d475 PM |
933 | |
934 | if (extend && is_signed) { | |
935 | g_assert(size < 3); | |
936 | tcg_gen_ext32u_i64(dest, dest); | |
937 | } | |
aaa1f954 EI |
938 | |
939 | if (iss_valid) { | |
940 | uint32_t syn; | |
941 | ||
942 | syn = syn_data_abort_with_iss(0, | |
943 | size, | |
944 | is_signed, | |
945 | iss_srt, | |
946 | iss_sf, | |
947 | iss_ar, | |
948 | 0, 0, 0, 0, 0, false); | |
949 | disas_set_insn_syndrome(s, syn); | |
950 | } | |
4a08d475 PM |
951 | } |
952 | ||
aaa1f954 EI |
953 | static void do_gpr_ld(DisasContext *s, |
954 | TCGv_i64 dest, TCGv_i64 tcg_addr, | |
955 | int size, bool is_signed, bool extend, | |
956 | bool iss_valid, unsigned int iss_srt, | |
957 | bool iss_sf, bool iss_ar) | |
60510aed PM |
958 | { |
959 | do_gpr_ld_memidx(s, dest, tcg_addr, size, is_signed, extend, | |
aaa1f954 EI |
960 | get_mem_index(s), |
961 | iss_valid, iss_srt, iss_sf, iss_ar); | |
60510aed PM |
962 | } |
963 | ||
4a08d475 PM |
964 | /* |
965 | * Store from FP register to memory | |
966 | */ | |
967 | static void do_fp_st(DisasContext *s, int srcidx, TCGv_i64 tcg_addr, int size) | |
968 | { | |
969 | /* This writes the bottom N bits of a 128 bit wide vector to memory */ | |
4a08d475 | 970 | TCGv_i64 tmp = tcg_temp_new_i64(); |
90e49638 | 971 | tcg_gen_ld_i64(tmp, cpu_env, fp_reg_offset(s, srcidx, MO_64)); |
4a08d475 | 972 | if (size < 4) { |
aa6489da PC |
973 | tcg_gen_qemu_st_i64(tmp, tcg_addr, get_mem_index(s), |
974 | s->be_data + size); | |
4a08d475 | 975 | } else { |
aa6489da | 976 | bool be = s->be_data == MO_BE; |
4a08d475 | 977 | TCGv_i64 tcg_hiaddr = tcg_temp_new_i64(); |
aa6489da | 978 | |
4a08d475 | 979 | tcg_gen_addi_i64(tcg_hiaddr, tcg_addr, 8); |
aa6489da PC |
980 | tcg_gen_qemu_st_i64(tmp, be ? tcg_hiaddr : tcg_addr, get_mem_index(s), |
981 | s->be_data | MO_Q); | |
982 | tcg_gen_ld_i64(tmp, cpu_env, fp_reg_hi_offset(s, srcidx)); | |
983 | tcg_gen_qemu_st_i64(tmp, be ? tcg_addr : tcg_hiaddr, get_mem_index(s), | |
984 | s->be_data | MO_Q); | |
4a08d475 PM |
985 | tcg_temp_free_i64(tcg_hiaddr); |
986 | } | |
987 | ||
988 | tcg_temp_free_i64(tmp); | |
989 | } | |
990 | ||
991 | /* | |
992 | * Load from memory to FP register | |
993 | */ | |
994 | static void do_fp_ld(DisasContext *s, int destidx, TCGv_i64 tcg_addr, int size) | |
995 | { | |
996 | /* This always zero-extends and writes to a full 128 bit wide vector */ | |
4a08d475 | 997 | TCGv_i64 tmplo = tcg_temp_new_i64(); |
e1f77859 | 998 | TCGv_i64 tmphi = NULL; |
4a08d475 PM |
999 | |
1000 | if (size < 4) { | |
14776ab5 | 1001 | MemOp memop = s->be_data + size; |
4a08d475 PM |
1002 | tcg_gen_qemu_ld_i64(tmplo, tcg_addr, get_mem_index(s), memop); |
1003 | } else { | |
aa6489da | 1004 | bool be = s->be_data == MO_BE; |
4a08d475 | 1005 | TCGv_i64 tcg_hiaddr; |
aa6489da | 1006 | |
4a08d475 PM |
1007 | tmphi = tcg_temp_new_i64(); |
1008 | tcg_hiaddr = tcg_temp_new_i64(); | |
1009 | ||
4a08d475 | 1010 | tcg_gen_addi_i64(tcg_hiaddr, tcg_addr, 8); |
aa6489da PC |
1011 | tcg_gen_qemu_ld_i64(tmplo, be ? tcg_hiaddr : tcg_addr, get_mem_index(s), |
1012 | s->be_data | MO_Q); | |
1013 | tcg_gen_qemu_ld_i64(tmphi, be ? tcg_addr : tcg_hiaddr, get_mem_index(s), | |
1014 | s->be_data | MO_Q); | |
4a08d475 PM |
1015 | tcg_temp_free_i64(tcg_hiaddr); |
1016 | } | |
1017 | ||
90e49638 | 1018 | tcg_gen_st_i64(tmplo, cpu_env, fp_reg_offset(s, destidx, MO_64)); |
4a08d475 | 1019 | tcg_temp_free_i64(tmplo); |
4ff55bcb | 1020 | |
e1f77859 RH |
1021 | if (tmphi) { |
1022 | tcg_gen_st_i64(tmphi, cpu_env, fp_reg_hi_offset(s, destidx)); | |
1023 | tcg_temp_free_i64(tmphi); | |
1024 | } | |
1025 | clear_vec_high(s, tmphi != NULL, destidx); | |
4a08d475 PM |
1026 | } |
1027 | ||
72430bf5 AB |
1028 | /* |
1029 | * Vector load/store helpers. | |
1030 | * | |
1031 | * The principal difference between this and a FP load is that we don't | |
1032 | * zero extend as we are filling a partial chunk of the vector register. | |
1033 | * These functions don't support 128 bit loads/stores, which would be | |
1034 | * normal load/store operations. | |
a08582f4 PM |
1035 | * |
1036 | * The _i32 versions are useful when operating on 32 bit quantities | |
1037 | * (eg for floating point single or using Neon helper functions). | |
72430bf5 AB |
1038 | */ |
1039 | ||
1040 | /* Get value of an element within a vector register */ | |
1041 | static void read_vec_element(DisasContext *s, TCGv_i64 tcg_dest, int srcidx, | |
14776ab5 | 1042 | int element, MemOp memop) |
72430bf5 | 1043 | { |
90e49638 | 1044 | int vect_off = vec_reg_offset(s, srcidx, element, memop & MO_SIZE); |
72430bf5 AB |
1045 | switch (memop) { |
1046 | case MO_8: | |
1047 | tcg_gen_ld8u_i64(tcg_dest, cpu_env, vect_off); | |
1048 | break; | |
1049 | case MO_16: | |
1050 | tcg_gen_ld16u_i64(tcg_dest, cpu_env, vect_off); | |
1051 | break; | |
1052 | case MO_32: | |
1053 | tcg_gen_ld32u_i64(tcg_dest, cpu_env, vect_off); | |
1054 | break; | |
1055 | case MO_8|MO_SIGN: | |
1056 | tcg_gen_ld8s_i64(tcg_dest, cpu_env, vect_off); | |
1057 | break; | |
1058 | case MO_16|MO_SIGN: | |
1059 | tcg_gen_ld16s_i64(tcg_dest, cpu_env, vect_off); | |
1060 | break; | |
1061 | case MO_32|MO_SIGN: | |
1062 | tcg_gen_ld32s_i64(tcg_dest, cpu_env, vect_off); | |
1063 | break; | |
1064 | case MO_64: | |
1065 | case MO_64|MO_SIGN: | |
1066 | tcg_gen_ld_i64(tcg_dest, cpu_env, vect_off); | |
1067 | break; | |
1068 | default: | |
1069 | g_assert_not_reached(); | |
1070 | } | |
1071 | } | |
1072 | ||
a08582f4 | 1073 | static void read_vec_element_i32(DisasContext *s, TCGv_i32 tcg_dest, int srcidx, |
14776ab5 | 1074 | int element, MemOp memop) |
a08582f4 | 1075 | { |
90e49638 | 1076 | int vect_off = vec_reg_offset(s, srcidx, element, memop & MO_SIZE); |
a08582f4 PM |
1077 | switch (memop) { |
1078 | case MO_8: | |
1079 | tcg_gen_ld8u_i32(tcg_dest, cpu_env, vect_off); | |
1080 | break; | |
1081 | case MO_16: | |
1082 | tcg_gen_ld16u_i32(tcg_dest, cpu_env, vect_off); | |
1083 | break; | |
1084 | case MO_8|MO_SIGN: | |
1085 | tcg_gen_ld8s_i32(tcg_dest, cpu_env, vect_off); | |
1086 | break; | |
1087 | case MO_16|MO_SIGN: | |
1088 | tcg_gen_ld16s_i32(tcg_dest, cpu_env, vect_off); | |
1089 | break; | |
1090 | case MO_32: | |
1091 | case MO_32|MO_SIGN: | |
1092 | tcg_gen_ld_i32(tcg_dest, cpu_env, vect_off); | |
1093 | break; | |
1094 | default: | |
1095 | g_assert_not_reached(); | |
1096 | } | |
1097 | } | |
1098 | ||
72430bf5 AB |
1099 | /* Set value of an element within a vector register */ |
1100 | static void write_vec_element(DisasContext *s, TCGv_i64 tcg_src, int destidx, | |
14776ab5 | 1101 | int element, MemOp memop) |
72430bf5 | 1102 | { |
90e49638 | 1103 | int vect_off = vec_reg_offset(s, destidx, element, memop & MO_SIZE); |
72430bf5 AB |
1104 | switch (memop) { |
1105 | case MO_8: | |
1106 | tcg_gen_st8_i64(tcg_src, cpu_env, vect_off); | |
1107 | break; | |
1108 | case MO_16: | |
1109 | tcg_gen_st16_i64(tcg_src, cpu_env, vect_off); | |
1110 | break; | |
1111 | case MO_32: | |
1112 | tcg_gen_st32_i64(tcg_src, cpu_env, vect_off); | |
1113 | break; | |
1114 | case MO_64: | |
1115 | tcg_gen_st_i64(tcg_src, cpu_env, vect_off); | |
1116 | break; | |
1117 | default: | |
1118 | g_assert_not_reached(); | |
1119 | } | |
1120 | } | |
1121 | ||
1f8a73af | 1122 | static void write_vec_element_i32(DisasContext *s, TCGv_i32 tcg_src, |
14776ab5 | 1123 | int destidx, int element, MemOp memop) |
1f8a73af | 1124 | { |
90e49638 | 1125 | int vect_off = vec_reg_offset(s, destidx, element, memop & MO_SIZE); |
1f8a73af PM |
1126 | switch (memop) { |
1127 | case MO_8: | |
1128 | tcg_gen_st8_i32(tcg_src, cpu_env, vect_off); | |
1129 | break; | |
1130 | case MO_16: | |
1131 | tcg_gen_st16_i32(tcg_src, cpu_env, vect_off); | |
1132 | break; | |
1133 | case MO_32: | |
1134 | tcg_gen_st_i32(tcg_src, cpu_env, vect_off); | |
1135 | break; | |
1136 | default: | |
1137 | g_assert_not_reached(); | |
1138 | } | |
1139 | } | |
1140 | ||
72430bf5 AB |
1141 | /* Store from vector register to memory */ |
1142 | static void do_vec_st(DisasContext *s, int srcidx, int element, | |
14776ab5 | 1143 | TCGv_i64 tcg_addr, int size, MemOp endian) |
72430bf5 | 1144 | { |
72430bf5 AB |
1145 | TCGv_i64 tcg_tmp = tcg_temp_new_i64(); |
1146 | ||
1147 | read_vec_element(s, tcg_tmp, srcidx, element, size); | |
87f9a7f0 | 1148 | tcg_gen_qemu_st_i64(tcg_tmp, tcg_addr, get_mem_index(s), endian | size); |
72430bf5 AB |
1149 | |
1150 | tcg_temp_free_i64(tcg_tmp); | |
1151 | } | |
1152 | ||
1153 | /* Load from memory to vector register */ | |
1154 | static void do_vec_ld(DisasContext *s, int destidx, int element, | |
14776ab5 | 1155 | TCGv_i64 tcg_addr, int size, MemOp endian) |
72430bf5 | 1156 | { |
72430bf5 AB |
1157 | TCGv_i64 tcg_tmp = tcg_temp_new_i64(); |
1158 | ||
87f9a7f0 | 1159 | tcg_gen_qemu_ld_i64(tcg_tmp, tcg_addr, get_mem_index(s), endian | size); |
72430bf5 AB |
1160 | write_vec_element(s, tcg_tmp, destidx, element, size); |
1161 | ||
1162 | tcg_temp_free_i64(tcg_tmp); | |
1163 | } | |
1164 | ||
8c6afa6a PM |
1165 | /* Check that FP/Neon access is enabled. If it is, return |
1166 | * true. If not, emit code to generate an appropriate exception, | |
1167 | * and return false; the caller should not emit any code for | |
1168 | * the instruction. Note that this check must happen after all | |
1169 | * unallocated-encoding checks (otherwise the syndrome information | |
1170 | * for the resulting exception will be incorrect). | |
1171 | */ | |
1172 | static inline bool fp_access_check(DisasContext *s) | |
1173 | { | |
90e49638 PM |
1174 | assert(!s->fp_access_checked); |
1175 | s->fp_access_checked = true; | |
1176 | ||
9dbbc748 | 1177 | if (!s->fp_excp_el) { |
8c6afa6a PM |
1178 | return true; |
1179 | } | |
1180 | ||
a767fac8 RH |
1181 | gen_exception_insn(s, s->pc_curr, EXCP_UDEF, |
1182 | syn_fp_access_trap(1, 0xe, false), s->fp_excp_el); | |
8c6afa6a PM |
1183 | return false; |
1184 | } | |
1185 | ||
490aa7f1 RH |
1186 | /* Check that SVE access is enabled. If it is, return true. |
1187 | * If not, emit code to generate an appropriate exception and return false. | |
1188 | */ | |
8c71baed | 1189 | bool sve_access_check(DisasContext *s) |
490aa7f1 RH |
1190 | { |
1191 | if (s->sve_excp_el) { | |
a767fac8 | 1192 | gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_sve_access_trap(), |
490aa7f1 RH |
1193 | s->sve_excp_el); |
1194 | return false; | |
1195 | } | |
8c71baed | 1196 | return fp_access_check(s); |
490aa7f1 RH |
1197 | } |
1198 | ||
229b7a05 AB |
1199 | /* |
1200 | * This utility function is for doing register extension with an | |
1201 | * optional shift. You will likely want to pass a temporary for the | |
1202 | * destination register. See DecodeRegExtend() in the ARM ARM. | |
1203 | */ | |
1204 | static void ext_and_shift_reg(TCGv_i64 tcg_out, TCGv_i64 tcg_in, | |
1205 | int option, unsigned int shift) | |
1206 | { | |
1207 | int extsize = extract32(option, 0, 2); | |
1208 | bool is_signed = extract32(option, 2, 1); | |
1209 | ||
1210 | if (is_signed) { | |
1211 | switch (extsize) { | |
1212 | case 0: | |
1213 | tcg_gen_ext8s_i64(tcg_out, tcg_in); | |
1214 | break; | |
1215 | case 1: | |
1216 | tcg_gen_ext16s_i64(tcg_out, tcg_in); | |
1217 | break; | |
1218 | case 2: | |
1219 | tcg_gen_ext32s_i64(tcg_out, tcg_in); | |
1220 | break; | |
1221 | case 3: | |
1222 | tcg_gen_mov_i64(tcg_out, tcg_in); | |
1223 | break; | |
1224 | } | |
1225 | } else { | |
1226 | switch (extsize) { | |
1227 | case 0: | |
1228 | tcg_gen_ext8u_i64(tcg_out, tcg_in); | |
1229 | break; | |
1230 | case 1: | |
1231 | tcg_gen_ext16u_i64(tcg_out, tcg_in); | |
1232 | break; | |
1233 | case 2: | |
1234 | tcg_gen_ext32u_i64(tcg_out, tcg_in); | |
1235 | break; | |
1236 | case 3: | |
1237 | tcg_gen_mov_i64(tcg_out, tcg_in); | |
1238 | break; | |
1239 | } | |
1240 | } | |
1241 | ||
1242 | if (shift) { | |
1243 | tcg_gen_shli_i64(tcg_out, tcg_out, shift); | |
1244 | } | |
1245 | } | |
1246 | ||
4a08d475 PM |
1247 | static inline void gen_check_sp_alignment(DisasContext *s) |
1248 | { | |
1249 | /* The AArch64 architecture mandates that (if enabled via PSTATE | |
1250 | * or SCTLR bits) there is a check that SP is 16-aligned on every | |
1251 | * SP-relative load or store (with an exception generated if it is not). | |
1252 | * In line with general QEMU practice regarding misaligned accesses, | |
1253 | * we omit these checks for the sake of guest program performance. | |
1254 | * This function is provided as a hook so we can more easily add these | |
1255 | * checks in future (possibly as a "favour catching guest program bugs | |
1256 | * over speed" user selectable option). | |
1257 | */ | |
1258 | } | |
1259 | ||
384b26fb AB |
1260 | /* |
1261 | * This provides a simple table based table lookup decoder. It is | |
1262 | * intended to be used when the relevant bits for decode are too | |
1263 | * awkwardly placed and switch/if based logic would be confusing and | |
1264 | * deeply nested. Since it's a linear search through the table, tables | |
1265 | * should be kept small. | |
1266 | * | |
1267 | * It returns the first handler where insn & mask == pattern, or | |
1268 | * NULL if there is no match. | |
1269 | * The table is terminated by an empty mask (i.e. 0) | |
1270 | */ | |
1271 | static inline AArch64DecodeFn *lookup_disas_fn(const AArch64DecodeTable *table, | |
1272 | uint32_t insn) | |
1273 | { | |
1274 | const AArch64DecodeTable *tptr = table; | |
1275 | ||
1276 | while (tptr->mask) { | |
1277 | if ((insn & tptr->mask) == tptr->pattern) { | |
1278 | return tptr->disas_fn; | |
1279 | } | |
1280 | tptr++; | |
1281 | } | |
1282 | return NULL; | |
1283 | } | |
1284 | ||
ad7ee8a2 | 1285 | /* |
4ce31af4 PM |
1286 | * The instruction disassembly implemented here matches |
1287 | * the instruction encoding classifications in chapter C4 | |
1288 | * of the ARM Architecture Reference Manual (DDI0487B_a); | |
1289 | * classification names and decode diagrams here should generally | |
1290 | * match up with those in the manual. | |
ad7ee8a2 CF |
1291 | */ |
1292 | ||
4ce31af4 | 1293 | /* Unconditional branch (immediate) |
11e169de AG |
1294 | * 31 30 26 25 0 |
1295 | * +----+-----------+-------------------------------------+ | |
1296 | * | op | 0 0 1 0 1 | imm26 | | |
1297 | * +----+-----------+-------------------------------------+ | |
1298 | */ | |
ad7ee8a2 CF |
1299 | static void disas_uncond_b_imm(DisasContext *s, uint32_t insn) |
1300 | { | |
43722a6d | 1301 | uint64_t addr = s->pc_curr + sextract32(insn, 0, 26) * 4; |
11e169de | 1302 | |
1743d55c | 1303 | if (insn & (1U << 31)) { |
4ce31af4 | 1304 | /* BL Branch with link */ |
a0415916 | 1305 | tcg_gen_movi_i64(cpu_reg(s, 30), s->base.pc_next); |
11e169de AG |
1306 | } |
1307 | ||
4ce31af4 | 1308 | /* B Branch / BL Branch with link */ |
35862270 | 1309 | reset_btype(s); |
11e169de | 1310 | gen_goto_tb(s, 0, addr); |
ad7ee8a2 CF |
1311 | } |
1312 | ||
4ce31af4 | 1313 | /* Compare and branch (immediate) |
60e53388 AG |
1314 | * 31 30 25 24 23 5 4 0 |
1315 | * +----+-------------+----+---------------------+--------+ | |
1316 | * | sf | 0 1 1 0 1 0 | op | imm19 | Rt | | |
1317 | * +----+-------------+----+---------------------+--------+ | |
1318 | */ | |
ad7ee8a2 CF |
1319 | static void disas_comp_b_imm(DisasContext *s, uint32_t insn) |
1320 | { | |
60e53388 AG |
1321 | unsigned int sf, op, rt; |
1322 | uint64_t addr; | |
42a268c2 | 1323 | TCGLabel *label_match; |
60e53388 AG |
1324 | TCGv_i64 tcg_cmp; |
1325 | ||
1326 | sf = extract32(insn, 31, 1); | |
1327 | op = extract32(insn, 24, 1); /* 0: CBZ; 1: CBNZ */ | |
1328 | rt = extract32(insn, 0, 5); | |
43722a6d | 1329 | addr = s->pc_curr + sextract32(insn, 5, 19) * 4; |
60e53388 AG |
1330 | |
1331 | tcg_cmp = read_cpu_reg(s, rt, sf); | |
1332 | label_match = gen_new_label(); | |
1333 | ||
35862270 | 1334 | reset_btype(s); |
60e53388 AG |
1335 | tcg_gen_brcondi_i64(op ? TCG_COND_NE : TCG_COND_EQ, |
1336 | tcg_cmp, 0, label_match); | |
1337 | ||
a0415916 | 1338 | gen_goto_tb(s, 0, s->base.pc_next); |
60e53388 AG |
1339 | gen_set_label(label_match); |
1340 | gen_goto_tb(s, 1, addr); | |
ad7ee8a2 CF |
1341 | } |
1342 | ||
4ce31af4 | 1343 | /* Test and branch (immediate) |
db0f7958 AG |
1344 | * 31 30 25 24 23 19 18 5 4 0 |
1345 | * +----+-------------+----+-------+-------------+------+ | |
1346 | * | b5 | 0 1 1 0 1 1 | op | b40 | imm14 | Rt | | |
1347 | * +----+-------------+----+-------+-------------+------+ | |
1348 | */ | |
ad7ee8a2 CF |
1349 | static void disas_test_b_imm(DisasContext *s, uint32_t insn) |
1350 | { | |
db0f7958 AG |
1351 | unsigned int bit_pos, op, rt; |
1352 | uint64_t addr; | |
42a268c2 | 1353 | TCGLabel *label_match; |
db0f7958 AG |
1354 | TCGv_i64 tcg_cmp; |
1355 | ||
1356 | bit_pos = (extract32(insn, 31, 1) << 5) | extract32(insn, 19, 5); | |
1357 | op = extract32(insn, 24, 1); /* 0: TBZ; 1: TBNZ */ | |
43722a6d | 1358 | addr = s->pc_curr + sextract32(insn, 5, 14) * 4; |
db0f7958 AG |
1359 | rt = extract32(insn, 0, 5); |
1360 | ||
1361 | tcg_cmp = tcg_temp_new_i64(); | |
1362 | tcg_gen_andi_i64(tcg_cmp, cpu_reg(s, rt), (1ULL << bit_pos)); | |
1363 | label_match = gen_new_label(); | |
35862270 RH |
1364 | |
1365 | reset_btype(s); | |
db0f7958 AG |
1366 | tcg_gen_brcondi_i64(op ? TCG_COND_NE : TCG_COND_EQ, |
1367 | tcg_cmp, 0, label_match); | |
1368 | tcg_temp_free_i64(tcg_cmp); | |
a0415916 | 1369 | gen_goto_tb(s, 0, s->base.pc_next); |
db0f7958 AG |
1370 | gen_set_label(label_match); |
1371 | gen_goto_tb(s, 1, addr); | |
ad7ee8a2 CF |
1372 | } |
1373 | ||
4ce31af4 | 1374 | /* Conditional branch (immediate) |
39fb730a AG |
1375 | * 31 25 24 23 5 4 3 0 |
1376 | * +---------------+----+---------------------+----+------+ | |
1377 | * | 0 1 0 1 0 1 0 | o1 | imm19 | o0 | cond | | |
1378 | * +---------------+----+---------------------+----+------+ | |
1379 | */ | |
ad7ee8a2 CF |
1380 | static void disas_cond_b_imm(DisasContext *s, uint32_t insn) |
1381 | { | |
39fb730a AG |
1382 | unsigned int cond; |
1383 | uint64_t addr; | |
1384 | ||
1385 | if ((insn & (1 << 4)) || (insn & (1 << 24))) { | |
1386 | unallocated_encoding(s); | |
1387 | return; | |
1388 | } | |
43722a6d | 1389 | addr = s->pc_curr + sextract32(insn, 5, 19) * 4; |
39fb730a AG |
1390 | cond = extract32(insn, 0, 4); |
1391 | ||
35862270 | 1392 | reset_btype(s); |
39fb730a AG |
1393 | if (cond < 0x0e) { |
1394 | /* genuinely conditional branches */ | |
42a268c2 | 1395 | TCGLabel *label_match = gen_new_label(); |
39fb730a | 1396 | arm_gen_test_cc(cond, label_match); |
a0415916 | 1397 | gen_goto_tb(s, 0, s->base.pc_next); |
39fb730a AG |
1398 | gen_set_label(label_match); |
1399 | gen_goto_tb(s, 1, addr); | |
1400 | } else { | |
1401 | /* 0xe and 0xf are both "always" conditions */ | |
1402 | gen_goto_tb(s, 0, addr); | |
1403 | } | |
ad7ee8a2 CF |
1404 | } |
1405 | ||
4ce31af4 | 1406 | /* HINT instruction group, including various allocated HINTs */ |
87462e0f CF |
1407 | static void handle_hint(DisasContext *s, uint32_t insn, |
1408 | unsigned int op1, unsigned int op2, unsigned int crm) | |
1409 | { | |
1410 | unsigned int selector = crm << 3 | op2; | |
1411 | ||
1412 | if (op1 != 3) { | |
1413 | unallocated_encoding(s); | |
1414 | return; | |
1415 | } | |
1416 | ||
1417 | switch (selector) { | |
7c94c834 RH |
1418 | case 0b00000: /* NOP */ |
1419 | break; | |
1420 | case 0b00011: /* WFI */ | |
dcba3a8d | 1421 | s->base.is_jmp = DISAS_WFI; |
7c94c834 RH |
1422 | break; |
1423 | case 0b00001: /* YIELD */ | |
2399d4e7 EC |
1424 | /* When running in MTTCG we don't generate jumps to the yield and |
1425 | * WFE helpers as it won't affect the scheduling of other vCPUs. | |
1426 | * If we wanted to more completely model WFE/SEV so we don't busy | |
1427 | * spin unnecessarily we would need to do something more involved. | |
1428 | */ | |
2399d4e7 | 1429 | if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) { |
dcba3a8d | 1430 | s->base.is_jmp = DISAS_YIELD; |
c22edfeb | 1431 | } |
7c94c834 RH |
1432 | break; |
1433 | case 0b00010: /* WFE */ | |
2399d4e7 | 1434 | if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) { |
dcba3a8d | 1435 | s->base.is_jmp = DISAS_WFE; |
c22edfeb | 1436 | } |
7c94c834 RH |
1437 | break; |
1438 | case 0b00100: /* SEV */ | |
1439 | case 0b00101: /* SEVL */ | |
87462e0f | 1440 | /* we treat all as NOP at least for now */ |
7c94c834 RH |
1441 | break; |
1442 | case 0b00111: /* XPACLRI */ | |
1443 | if (s->pauth_active) { | |
1444 | gen_helper_xpaci(cpu_X[30], cpu_env, cpu_X[30]); | |
1445 | } | |
1446 | break; | |
1447 | case 0b01000: /* PACIA1716 */ | |
1448 | if (s->pauth_active) { | |
1449 | gen_helper_pacia(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]); | |
1450 | } | |
1451 | break; | |
1452 | case 0b01010: /* PACIB1716 */ | |
1453 | if (s->pauth_active) { | |
1454 | gen_helper_pacib(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]); | |
1455 | } | |
1456 | break; | |
1457 | case 0b01100: /* AUTIA1716 */ | |
1458 | if (s->pauth_active) { | |
1459 | gen_helper_autia(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]); | |
1460 | } | |
1461 | break; | |
1462 | case 0b01110: /* AUTIB1716 */ | |
1463 | if (s->pauth_active) { | |
1464 | gen_helper_autib(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]); | |
1465 | } | |
1466 | break; | |
1467 | case 0b11000: /* PACIAZ */ | |
1468 | if (s->pauth_active) { | |
1469 | gen_helper_pacia(cpu_X[30], cpu_env, cpu_X[30], | |
1470 | new_tmp_a64_zero(s)); | |
1471 | } | |
1472 | break; | |
1473 | case 0b11001: /* PACIASP */ | |
1474 | if (s->pauth_active) { | |
1475 | gen_helper_pacia(cpu_X[30], cpu_env, cpu_X[30], cpu_X[31]); | |
1476 | } | |
1477 | break; | |
1478 | case 0b11010: /* PACIBZ */ | |
1479 | if (s->pauth_active) { | |
1480 | gen_helper_pacib(cpu_X[30], cpu_env, cpu_X[30], | |
1481 | new_tmp_a64_zero(s)); | |
1482 | } | |
1483 | break; | |
1484 | case 0b11011: /* PACIBSP */ | |
1485 | if (s->pauth_active) { | |
1486 | gen_helper_pacib(cpu_X[30], cpu_env, cpu_X[30], cpu_X[31]); | |
1487 | } | |
1488 | break; | |
1489 | case 0b11100: /* AUTIAZ */ | |
1490 | if (s->pauth_active) { | |
1491 | gen_helper_autia(cpu_X[30], cpu_env, cpu_X[30], | |
1492 | new_tmp_a64_zero(s)); | |
1493 | } | |
1494 | break; | |
1495 | case 0b11101: /* AUTIASP */ | |
1496 | if (s->pauth_active) { | |
1497 | gen_helper_autia(cpu_X[30], cpu_env, cpu_X[30], cpu_X[31]); | |
1498 | } | |
1499 | break; | |
1500 | case 0b11110: /* AUTIBZ */ | |
1501 | if (s->pauth_active) { | |
1502 | gen_helper_autib(cpu_X[30], cpu_env, cpu_X[30], | |
1503 | new_tmp_a64_zero(s)); | |
1504 | } | |
1505 | break; | |
1506 | case 0b11111: /* AUTIBSP */ | |
1507 | if (s->pauth_active) { | |
1508 | gen_helper_autib(cpu_X[30], cpu_env, cpu_X[30], cpu_X[31]); | |
1509 | } | |
1510 | break; | |
87462e0f CF |
1511 | default: |
1512 | /* default specified as NOP equivalent */ | |
7c94c834 | 1513 | break; |
87462e0f CF |
1514 | } |
1515 | } | |
1516 | ||
fa2ef212 MM |
1517 | static void gen_clrex(DisasContext *s, uint32_t insn) |
1518 | { | |
1519 | tcg_gen_movi_i64(cpu_exclusive_addr, -1); | |
1520 | } | |
1521 | ||
87462e0f CF |
1522 | /* CLREX, DSB, DMB, ISB */ |
1523 | static void handle_sync(DisasContext *s, uint32_t insn, | |
1524 | unsigned int op1, unsigned int op2, unsigned int crm) | |
1525 | { | |
ce1bd93f PK |
1526 | TCGBar bar; |
1527 | ||
87462e0f CF |
1528 | if (op1 != 3) { |
1529 | unallocated_encoding(s); | |
1530 | return; | |
1531 | } | |
1532 | ||
1533 | switch (op2) { | |
1534 | case 2: /* CLREX */ | |
fa2ef212 | 1535 | gen_clrex(s, insn); |
87462e0f CF |
1536 | return; |
1537 | case 4: /* DSB */ | |
1538 | case 5: /* DMB */ | |
ce1bd93f PK |
1539 | switch (crm & 3) { |
1540 | case 1: /* MBReqTypes_Reads */ | |
1541 | bar = TCG_BAR_SC | TCG_MO_LD_LD | TCG_MO_LD_ST; | |
1542 | break; | |
1543 | case 2: /* MBReqTypes_Writes */ | |
1544 | bar = TCG_BAR_SC | TCG_MO_ST_ST; | |
1545 | break; | |
1546 | default: /* MBReqTypes_All */ | |
1547 | bar = TCG_BAR_SC | TCG_MO_ALL; | |
1548 | break; | |
1549 | } | |
1550 | tcg_gen_mb(bar); | |
87462e0f | 1551 | return; |
6df99dec SS |
1552 | case 6: /* ISB */ |
1553 | /* We need to break the TB after this insn to execute | |
1554 | * a self-modified code correctly and also to take | |
1555 | * any pending interrupts immediately. | |
1556 | */ | |
35862270 | 1557 | reset_btype(s); |
a0415916 | 1558 | gen_goto_tb(s, 0, s->base.pc_next); |
6df99dec | 1559 | return; |
9888bd1e RH |
1560 | |
1561 | case 7: /* SB */ | |
1562 | if (crm != 0 || !dc_isar_feature(aa64_sb, s)) { | |
1563 | goto do_unallocated; | |
1564 | } | |
1565 | /* | |
1566 | * TODO: There is no speculation barrier opcode for TCG; | |
1567 | * MB and end the TB instead. | |
1568 | */ | |
1569 | tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); | |
a0415916 | 1570 | gen_goto_tb(s, 0, s->base.pc_next); |
9888bd1e RH |
1571 | return; |
1572 | ||
87462e0f | 1573 | default: |
9888bd1e | 1574 | do_unallocated: |
87462e0f CF |
1575 | unallocated_encoding(s); |
1576 | return; | |
1577 | } | |
1578 | } | |
1579 | ||
5ef84f11 RH |
1580 | static void gen_xaflag(void) |
1581 | { | |
1582 | TCGv_i32 z = tcg_temp_new_i32(); | |
1583 | ||
1584 | tcg_gen_setcondi_i32(TCG_COND_EQ, z, cpu_ZF, 0); | |
1585 | ||
1586 | /* | |
1587 | * (!C & !Z) << 31 | |
1588 | * (!(C | Z)) << 31 | |
1589 | * ~((C | Z) << 31) | |
1590 | * ~-(C | Z) | |
1591 | * (C | Z) - 1 | |
1592 | */ | |
1593 | tcg_gen_or_i32(cpu_NF, cpu_CF, z); | |
1594 | tcg_gen_subi_i32(cpu_NF, cpu_NF, 1); | |
1595 | ||
1596 | /* !(Z & C) */ | |
1597 | tcg_gen_and_i32(cpu_ZF, z, cpu_CF); | |
1598 | tcg_gen_xori_i32(cpu_ZF, cpu_ZF, 1); | |
1599 | ||
1600 | /* (!C & Z) << 31 -> -(Z & ~C) */ | |
1601 | tcg_gen_andc_i32(cpu_VF, z, cpu_CF); | |
1602 | tcg_gen_neg_i32(cpu_VF, cpu_VF); | |
1603 | ||
1604 | /* C | Z */ | |
1605 | tcg_gen_or_i32(cpu_CF, cpu_CF, z); | |
1606 | ||
1607 | tcg_temp_free_i32(z); | |
1608 | } | |
1609 | ||
1610 | static void gen_axflag(void) | |
1611 | { | |
1612 | tcg_gen_sari_i32(cpu_VF, cpu_VF, 31); /* V ? -1 : 0 */ | |
1613 | tcg_gen_andc_i32(cpu_CF, cpu_CF, cpu_VF); /* C & !V */ | |
1614 | ||
1615 | /* !(Z | V) -> !(!ZF | V) -> ZF & !V -> ZF & ~VF */ | |
1616 | tcg_gen_andc_i32(cpu_ZF, cpu_ZF, cpu_VF); | |
1617 | ||
1618 | tcg_gen_movi_i32(cpu_NF, 0); | |
1619 | tcg_gen_movi_i32(cpu_VF, 0); | |
1620 | } | |
1621 | ||
4ce31af4 | 1622 | /* MSR (immediate) - move immediate to processor state field */ |
87462e0f CF |
1623 | static void handle_msr_i(DisasContext *s, uint32_t insn, |
1624 | unsigned int op1, unsigned int op2, unsigned int crm) | |
1625 | { | |
ff730e96 | 1626 | TCGv_i32 t1; |
9cfa0b4e | 1627 | int op = op1 << 3 | op2; |
ff730e96 RH |
1628 | |
1629 | /* End the TB by default, chaining is ok. */ | |
1630 | s->base.is_jmp = DISAS_TOO_MANY; | |
1631 | ||
9cfa0b4e | 1632 | switch (op) { |
b89d9c98 RH |
1633 | case 0x00: /* CFINV */ |
1634 | if (crm != 0 || !dc_isar_feature(aa64_condm_4, s)) { | |
1635 | goto do_unallocated; | |
1636 | } | |
1637 | tcg_gen_xori_i32(cpu_CF, cpu_CF, 1); | |
1638 | s->base.is_jmp = DISAS_NEXT; | |
1639 | break; | |
1640 | ||
5ef84f11 RH |
1641 | case 0x01: /* XAFlag */ |
1642 | if (crm != 0 || !dc_isar_feature(aa64_condm_5, s)) { | |
1643 | goto do_unallocated; | |
1644 | } | |
1645 | gen_xaflag(); | |
1646 | s->base.is_jmp = DISAS_NEXT; | |
1647 | break; | |
1648 | ||
1649 | case 0x02: /* AXFlag */ | |
1650 | if (crm != 0 || !dc_isar_feature(aa64_condm_5, s)) { | |
1651 | goto do_unallocated; | |
1652 | } | |
1653 | gen_axflag(); | |
1654 | s->base.is_jmp = DISAS_NEXT; | |
1655 | break; | |
1656 | ||
9eeb7a1c RH |
1657 | case 0x03: /* UAO */ |
1658 | if (!dc_isar_feature(aa64_uao, s) || s->current_el == 0) { | |
1659 | goto do_unallocated; | |
1660 | } | |
1661 | if (crm & 1) { | |
1662 | set_pstate_bits(PSTATE_UAO); | |
1663 | } else { | |
1664 | clear_pstate_bits(PSTATE_UAO); | |
1665 | } | |
1666 | t1 = tcg_const_i32(s->current_el); | |
1667 | gen_helper_rebuild_hflags_a64(cpu_env, t1); | |
1668 | tcg_temp_free_i32(t1); | |
1669 | break; | |
1670 | ||
220f508f RH |
1671 | case 0x04: /* PAN */ |
1672 | if (!dc_isar_feature(aa64_pan, s) || s->current_el == 0) { | |
1673 | goto do_unallocated; | |
1674 | } | |
1675 | if (crm & 1) { | |
1676 | set_pstate_bits(PSTATE_PAN); | |
1677 | } else { | |
1678 | clear_pstate_bits(PSTATE_PAN); | |
1679 | } | |
1680 | t1 = tcg_const_i32(s->current_el); | |
1681 | gen_helper_rebuild_hflags_a64(cpu_env, t1); | |
1682 | tcg_temp_free_i32(t1); | |
1683 | break; | |
1684 | ||
9cfa0b4e | 1685 | case 0x05: /* SPSel */ |
dcbff19b | 1686 | if (s->current_el == 0) { |
ff730e96 | 1687 | goto do_unallocated; |
9cfa0b4e | 1688 | } |
ff730e96 RH |
1689 | t1 = tcg_const_i32(crm & PSTATE_SP); |
1690 | gen_helper_msr_i_spsel(cpu_env, t1); | |
1691 | tcg_temp_free_i32(t1); | |
1692 | break; | |
1693 | ||
9cfa0b4e | 1694 | case 0x1e: /* DAIFSet */ |
ff730e96 RH |
1695 | t1 = tcg_const_i32(crm); |
1696 | gen_helper_msr_i_daifset(cpu_env, t1); | |
1697 | tcg_temp_free_i32(t1); | |
1698 | break; | |
1699 | ||
9cfa0b4e | 1700 | case 0x1f: /* DAIFClear */ |
ff730e96 RH |
1701 | t1 = tcg_const_i32(crm); |
1702 | gen_helper_msr_i_daifclear(cpu_env, t1); | |
1703 | tcg_temp_free_i32(t1); | |
8da54b25 | 1704 | /* For DAIFClear, exit the cpu loop to re-evaluate pending IRQs. */ |
14407ec2 | 1705 | s->base.is_jmp = DISAS_UPDATE_EXIT; |
9cfa0b4e | 1706 | break; |
ff730e96 | 1707 | |
4b779ceb RH |
1708 | case 0x1c: /* TCO */ |
1709 | if (dc_isar_feature(aa64_mte, s)) { | |
1710 | /* Full MTE is enabled -- set the TCO bit as directed. */ | |
1711 | if (crm & 1) { | |
1712 | set_pstate_bits(PSTATE_TCO); | |
1713 | } else { | |
1714 | clear_pstate_bits(PSTATE_TCO); | |
1715 | } | |
1716 | t1 = tcg_const_i32(s->current_el); | |
1717 | gen_helper_rebuild_hflags_a64(cpu_env, t1); | |
1718 | tcg_temp_free_i32(t1); | |
1719 | /* Many factors, including TCO, go into MTE_ACTIVE. */ | |
1720 | s->base.is_jmp = DISAS_UPDATE_NOCHAIN; | |
1721 | } else if (dc_isar_feature(aa64_mte_insn_reg, s)) { | |
1722 | /* Only "instructions accessible at EL0" -- PSTATE.TCO is WI. */ | |
1723 | s->base.is_jmp = DISAS_NEXT; | |
1724 | } else { | |
1725 | goto do_unallocated; | |
1726 | } | |
1727 | break; | |
1728 | ||
9cfa0b4e | 1729 | default: |
ff730e96 | 1730 | do_unallocated: |
9cfa0b4e PM |
1731 | unallocated_encoding(s); |
1732 | return; | |
1733 | } | |
87462e0f CF |
1734 | } |
1735 | ||
b0d2b7d0 PM |
1736 | static void gen_get_nzcv(TCGv_i64 tcg_rt) |
1737 | { | |
1738 | TCGv_i32 tmp = tcg_temp_new_i32(); | |
1739 | TCGv_i32 nzcv = tcg_temp_new_i32(); | |
1740 | ||
1741 | /* build bit 31, N */ | |
1743d55c | 1742 | tcg_gen_andi_i32(nzcv, cpu_NF, (1U << 31)); |
b0d2b7d0 PM |
1743 | /* build bit 30, Z */ |
1744 | tcg_gen_setcondi_i32(TCG_COND_EQ, tmp, cpu_ZF, 0); | |
1745 | tcg_gen_deposit_i32(nzcv, nzcv, tmp, 30, 1); | |
1746 | /* build bit 29, C */ | |
1747 | tcg_gen_deposit_i32(nzcv, nzcv, cpu_CF, 29, 1); | |
1748 | /* build bit 28, V */ | |
1749 | tcg_gen_shri_i32(tmp, cpu_VF, 31); | |
1750 | tcg_gen_deposit_i32(nzcv, nzcv, tmp, 28, 1); | |
1751 | /* generate result */ | |
1752 | tcg_gen_extu_i32_i64(tcg_rt, nzcv); | |
1753 | ||
1754 | tcg_temp_free_i32(nzcv); | |
1755 | tcg_temp_free_i32(tmp); | |
1756 | } | |
1757 | ||
1758 | static void gen_set_nzcv(TCGv_i64 tcg_rt) | |
b0d2b7d0 PM |
1759 | { |
1760 | TCGv_i32 nzcv = tcg_temp_new_i32(); | |
1761 | ||
1762 | /* take NZCV from R[t] */ | |
ecc7b3aa | 1763 | tcg_gen_extrl_i64_i32(nzcv, tcg_rt); |
b0d2b7d0 PM |
1764 | |
1765 | /* bit 31, N */ | |
1743d55c | 1766 | tcg_gen_andi_i32(cpu_NF, nzcv, (1U << 31)); |
b0d2b7d0 PM |
1767 | /* bit 30, Z */ |
1768 | tcg_gen_andi_i32(cpu_ZF, nzcv, (1 << 30)); | |
1769 | tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_ZF, cpu_ZF, 0); | |
1770 | /* bit 29, C */ | |
1771 | tcg_gen_andi_i32(cpu_CF, nzcv, (1 << 29)); | |
1772 | tcg_gen_shri_i32(cpu_CF, cpu_CF, 29); | |
1773 | /* bit 28, V */ | |
1774 | tcg_gen_andi_i32(cpu_VF, nzcv, (1 << 28)); | |
1775 | tcg_gen_shli_i32(cpu_VF, cpu_VF, 3); | |
1776 | tcg_temp_free_i32(nzcv); | |
1777 | } | |
1778 | ||
4ce31af4 PM |
1779 | /* MRS - move from system register |
1780 | * MSR (register) - move to system register | |
1781 | * SYS | |
1782 | * SYSL | |
fea50522 PM |
1783 | * These are all essentially the same insn in 'read' and 'write' |
1784 | * versions, with varying op0 fields. | |
1785 | */ | |
1786 | static void handle_sys(DisasContext *s, uint32_t insn, bool isread, | |
1787 | unsigned int op0, unsigned int op1, unsigned int op2, | |
87462e0f CF |
1788 | unsigned int crn, unsigned int crm, unsigned int rt) |
1789 | { | |
fea50522 PM |
1790 | const ARMCPRegInfo *ri; |
1791 | TCGv_i64 tcg_rt; | |
87462e0f | 1792 | |
fea50522 PM |
1793 | ri = get_arm_cp_reginfo(s->cp_regs, |
1794 | ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, | |
1795 | crn, crm, op0, op1, op2)); | |
87462e0f | 1796 | |
fea50522 | 1797 | if (!ri) { |
626187d8 PM |
1798 | /* Unknown register; this might be a guest error or a QEMU |
1799 | * unimplemented feature. | |
1800 | */ | |
1801 | qemu_log_mask(LOG_UNIMP, "%s access to unsupported AArch64 " | |
1802 | "system register op0:%d op1:%d crn:%d crm:%d op2:%d\n", | |
1803 | isread ? "read" : "write", op0, op1, crn, crm, op2); | |
fea50522 PM |
1804 | unallocated_encoding(s); |
1805 | return; | |
1806 | } | |
1807 | ||
1808 | /* Check access permissions */ | |
dcbff19b | 1809 | if (!cp_access_ok(s->current_el, ri, isread)) { |
fea50522 PM |
1810 | unallocated_encoding(s); |
1811 | return; | |
1812 | } | |
1813 | ||
f59df3f2 PM |
1814 | if (ri->accessfn) { |
1815 | /* Emit code to perform further access permissions checks at | |
1816 | * runtime; this may result in an exception. | |
1817 | */ | |
1818 | TCGv_ptr tmpptr; | |
3f208fd7 | 1819 | TCGv_i32 tcg_syn, tcg_isread; |
8bcbf37c PM |
1820 | uint32_t syndrome; |
1821 | ||
43722a6d | 1822 | gen_a64_set_pc_im(s->pc_curr); |
f59df3f2 | 1823 | tmpptr = tcg_const_ptr(ri); |
8bcbf37c PM |
1824 | syndrome = syn_aa64_sysregtrap(op0, op1, op2, crn, crm, rt, isread); |
1825 | tcg_syn = tcg_const_i32(syndrome); | |
3f208fd7 PM |
1826 | tcg_isread = tcg_const_i32(isread); |
1827 | gen_helper_access_check_cp_reg(cpu_env, tmpptr, tcg_syn, tcg_isread); | |
f59df3f2 | 1828 | tcg_temp_free_ptr(tmpptr); |
8bcbf37c | 1829 | tcg_temp_free_i32(tcg_syn); |
3f208fd7 | 1830 | tcg_temp_free_i32(tcg_isread); |
37ff584c PM |
1831 | } else if (ri->type & ARM_CP_RAISES_EXC) { |
1832 | /* | |
1833 | * The readfn or writefn might raise an exception; | |
1834 | * synchronize the CPU state in case it does. | |
1835 | */ | |
1836 | gen_a64_set_pc_im(s->pc_curr); | |
f59df3f2 PM |
1837 | } |
1838 | ||
fea50522 PM |
1839 | /* Handle special cases first */ |
1840 | switch (ri->type & ~(ARM_CP_FLAG_MASK & ~ARM_CP_SPECIAL)) { | |
1841 | case ARM_CP_NOP: | |
1842 | return; | |
b0d2b7d0 PM |
1843 | case ARM_CP_NZCV: |
1844 | tcg_rt = cpu_reg(s, rt); | |
1845 | if (isread) { | |
1846 | gen_get_nzcv(tcg_rt); | |
1847 | } else { | |
1848 | gen_set_nzcv(tcg_rt); | |
1849 | } | |
1850 | return; | |
0eef9d98 PM |
1851 | case ARM_CP_CURRENTEL: |
1852 | /* Reads as current EL value from pstate, which is | |
1853 | * guaranteed to be constant by the tb flags. | |
1854 | */ | |
1855 | tcg_rt = cpu_reg(s, rt); | |
dcbff19b | 1856 | tcg_gen_movi_i64(tcg_rt, s->current_el << 2); |
0eef9d98 | 1857 | return; |
aca3f40b PM |
1858 | case ARM_CP_DC_ZVA: |
1859 | /* Writes clear the aligned block of memory which rt points into. */ | |
46dc1bc0 RH |
1860 | if (s->mte_active[0]) { |
1861 | TCGv_i32 t_desc; | |
1862 | int desc = 0; | |
1863 | ||
1864 | desc = FIELD_DP32(desc, MTEDESC, MIDX, get_mem_index(s)); | |
1865 | desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid); | |
1866 | desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma); | |
1867 | t_desc = tcg_const_i32(desc); | |
1868 | ||
1869 | tcg_rt = new_tmp_a64(s); | |
1870 | gen_helper_mte_check_zva(tcg_rt, cpu_env, t_desc, cpu_reg(s, rt)); | |
1871 | tcg_temp_free_i32(t_desc); | |
1872 | } else { | |
1873 | tcg_rt = clean_data_tbi(s, cpu_reg(s, rt)); | |
1874 | } | |
aca3f40b PM |
1875 | gen_helper_dc_zva(cpu_env, tcg_rt); |
1876 | return; | |
fea50522 PM |
1877 | default: |
1878 | break; | |
1879 | } | |
fe03d45f RH |
1880 | if ((ri->type & ARM_CP_FPU) && !fp_access_check(s)) { |
1881 | return; | |
11d7870b RH |
1882 | } else if ((ri->type & ARM_CP_SVE) && !sve_access_check(s)) { |
1883 | return; | |
fe03d45f | 1884 | } |
fea50522 | 1885 | |
c5a49c63 | 1886 | if ((tb_cflags(s->base.tb) & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) { |
fea50522 PM |
1887 | gen_io_start(); |
1888 | } | |
1889 | ||
1890 | tcg_rt = cpu_reg(s, rt); | |
1891 | ||
1892 | if (isread) { | |
1893 | if (ri->type & ARM_CP_CONST) { | |
1894 | tcg_gen_movi_i64(tcg_rt, ri->resetvalue); | |
1895 | } else if (ri->readfn) { | |
1896 | TCGv_ptr tmpptr; | |
fea50522 PM |
1897 | tmpptr = tcg_const_ptr(ri); |
1898 | gen_helper_get_cp_reg64(tcg_rt, cpu_env, tmpptr); | |
1899 | tcg_temp_free_ptr(tmpptr); | |
1900 | } else { | |
1901 | tcg_gen_ld_i64(tcg_rt, cpu_env, ri->fieldoffset); | |
1902 | } | |
1903 | } else { | |
1904 | if (ri->type & ARM_CP_CONST) { | |
1905 | /* If not forbidden by access permissions, treat as WI */ | |
1906 | return; | |
1907 | } else if (ri->writefn) { | |
1908 | TCGv_ptr tmpptr; | |
fea50522 PM |
1909 | tmpptr = tcg_const_ptr(ri); |
1910 | gen_helper_set_cp_reg64(cpu_env, tmpptr, tcg_rt); | |
1911 | tcg_temp_free_ptr(tmpptr); | |
1912 | } else { | |
1913 | tcg_gen_st_i64(tcg_rt, cpu_env, ri->fieldoffset); | |
1914 | } | |
1915 | } | |
1916 | ||
c5a49c63 | 1917 | if ((tb_cflags(s->base.tb) & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) { |
fea50522 | 1918 | /* I/O operations must end the TB here (whether read or write) */ |
14407ec2 | 1919 | s->base.is_jmp = DISAS_UPDATE_EXIT; |
69d66864 RH |
1920 | } |
1921 | if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) { | |
1922 | /* | |
1923 | * A write to any coprocessor regiser that ends a TB | |
1924 | * must rebuild the hflags for the next TB. | |
1925 | */ | |
1926 | TCGv_i32 tcg_el = tcg_const_i32(s->current_el); | |
1927 | gen_helper_rebuild_hflags_a64(cpu_env, tcg_el); | |
1928 | tcg_temp_free_i32(tcg_el); | |
1929 | /* | |
1930 | * We default to ending the TB on a coprocessor register write, | |
fea50522 PM |
1931 | * but allow this to be suppressed by the register definition |
1932 | * (usually only necessary to work around guest bugs). | |
1933 | */ | |
14407ec2 | 1934 | s->base.is_jmp = DISAS_UPDATE_EXIT; |
fea50522 | 1935 | } |
ad7ee8a2 CF |
1936 | } |
1937 | ||
4ce31af4 | 1938 | /* System |
87462e0f CF |
1939 | * 31 22 21 20 19 18 16 15 12 11 8 7 5 4 0 |
1940 | * +---------------------+---+-----+-----+-------+-------+-----+------+ | |
1941 | * | 1 1 0 1 0 1 0 1 0 0 | L | op0 | op1 | CRn | CRm | op2 | Rt | | |
1942 | * +---------------------+---+-----+-----+-------+-------+-----+------+ | |
1943 | */ | |
1944 | static void disas_system(DisasContext *s, uint32_t insn) | |
1945 | { | |
1946 | unsigned int l, op0, op1, crn, crm, op2, rt; | |
1947 | l = extract32(insn, 21, 1); | |
1948 | op0 = extract32(insn, 19, 2); | |
1949 | op1 = extract32(insn, 16, 3); | |
1950 | crn = extract32(insn, 12, 4); | |
1951 | crm = extract32(insn, 8, 4); | |
1952 | op2 = extract32(insn, 5, 3); | |
1953 | rt = extract32(insn, 0, 5); | |
1954 | ||
1955 | if (op0 == 0) { | |
1956 | if (l || rt != 31) { | |
1957 | unallocated_encoding(s); | |
1958 | return; | |
1959 | } | |
1960 | switch (crn) { | |
4ce31af4 | 1961 | case 2: /* HINT (including allocated hints like NOP, YIELD, etc) */ |
87462e0f CF |
1962 | handle_hint(s, insn, op1, op2, crm); |
1963 | break; | |
1964 | case 3: /* CLREX, DSB, DMB, ISB */ | |
1965 | handle_sync(s, insn, op1, op2, crm); | |
1966 | break; | |
4ce31af4 | 1967 | case 4: /* MSR (immediate) */ |
87462e0f CF |
1968 | handle_msr_i(s, insn, op1, op2, crm); |
1969 | break; | |
1970 | default: | |
1971 | unallocated_encoding(s); | |
1972 | break; | |
1973 | } | |
1974 | return; | |
1975 | } | |
fea50522 | 1976 | handle_sys(s, insn, l, op0, op1, op2, crn, crm, rt); |
87462e0f CF |
1977 | } |
1978 | ||
4ce31af4 | 1979 | /* Exception generation |
9618e809 AG |
1980 | * |
1981 | * 31 24 23 21 20 5 4 2 1 0 | |
1982 | * +-----------------+-----+------------------------+-----+----+ | |
1983 | * | 1 1 0 1 0 1 0 0 | opc | imm16 | op2 | LL | | |
1984 | * +-----------------------+------------------------+----------+ | |
1985 | */ | |
ad7ee8a2 CF |
1986 | static void disas_exc(DisasContext *s, uint32_t insn) |
1987 | { | |
9618e809 AG |
1988 | int opc = extract32(insn, 21, 3); |
1989 | int op2_ll = extract32(insn, 0, 5); | |
d4a2dc67 | 1990 | int imm16 = extract32(insn, 5, 16); |
e0d6e6a5 | 1991 | TCGv_i32 tmp; |
9618e809 AG |
1992 | |
1993 | switch (opc) { | |
1994 | case 0: | |
7ea47fe7 PM |
1995 | /* For SVC, HVC and SMC we advance the single-step state |
1996 | * machine before taking the exception. This is architecturally | |
1997 | * mandated, to ensure that single-stepping a system call | |
1998 | * instruction works properly. | |
1999 | */ | |
35979d71 | 2000 | switch (op2_ll) { |
957956b3 | 2001 | case 1: /* SVC */ |
35979d71 | 2002 | gen_ss_advance(s); |
a767fac8 RH |
2003 | gen_exception_insn(s, s->base.pc_next, EXCP_SWI, |
2004 | syn_aa64_svc(imm16), default_exception_el(s)); | |
35979d71 | 2005 | break; |
957956b3 | 2006 | case 2: /* HVC */ |
dcbff19b | 2007 | if (s->current_el == 0) { |
35979d71 EI |
2008 | unallocated_encoding(s); |
2009 | break; | |
2010 | } | |
2011 | /* The pre HVC helper handles cases when HVC gets trapped | |
2012 | * as an undefined insn by runtime configuration. | |
2013 | */ | |
43722a6d | 2014 | gen_a64_set_pc_im(s->pc_curr); |
35979d71 EI |
2015 | gen_helper_pre_hvc(cpu_env); |
2016 | gen_ss_advance(s); | |
a767fac8 RH |
2017 | gen_exception_insn(s, s->base.pc_next, EXCP_HVC, |
2018 | syn_aa64_hvc(imm16), 2); | |
35979d71 | 2019 | break; |
957956b3 | 2020 | case 3: /* SMC */ |
dcbff19b | 2021 | if (s->current_el == 0) { |
e0d6e6a5 EI |
2022 | unallocated_encoding(s); |
2023 | break; | |
2024 | } | |
43722a6d | 2025 | gen_a64_set_pc_im(s->pc_curr); |
e0d6e6a5 EI |
2026 | tmp = tcg_const_i32(syn_aa64_smc(imm16)); |
2027 | gen_helper_pre_smc(cpu_env, tmp); | |
2028 | tcg_temp_free_i32(tmp); | |
2029 | gen_ss_advance(s); | |
a767fac8 RH |
2030 | gen_exception_insn(s, s->base.pc_next, EXCP_SMC, |
2031 | syn_aa64_smc(imm16), 3); | |
e0d6e6a5 | 2032 | break; |
35979d71 EI |
2033 | default: |
2034 | unallocated_encoding(s); | |
2035 | break; | |
2036 | } | |
9618e809 AG |
2037 | break; |
2038 | case 1: | |
2039 | if (op2_ll != 0) { | |
2040 | unallocated_encoding(s); | |
2041 | break; | |
2042 | } | |
2043 | /* BRK */ | |
06bcbda3 | 2044 | gen_exception_bkpt_insn(s, syn_aa64_bkpt(imm16)); |
9618e809 AG |
2045 | break; |
2046 | case 2: | |
2047 | if (op2_ll != 0) { | |
2048 | unallocated_encoding(s); | |
2049 | break; | |
2050 | } | |
8012c84f PM |
2051 | /* HLT. This has two purposes. |
2052 | * Architecturally, it is an external halting debug instruction. | |
2053 | * Since QEMU doesn't implement external debug, we treat this as | |
2054 | * it is required for halting debug disabled: it will UNDEF. | |
2055 | * Secondly, "HLT 0xf000" is the A64 semihosting syscall instruction. | |
2056 | */ | |
2057 | if (semihosting_enabled() && imm16 == 0xf000) { | |
2058 | #ifndef CONFIG_USER_ONLY | |
2059 | /* In system mode, don't allow userspace access to semihosting, | |
2060 | * to provide some semblance of security (and for consistency | |
2061 | * with our 32-bit semihosting). | |
2062 | */ | |
2063 | if (s->current_el == 0) { | |
2064 | unsupported_encoding(s, insn); | |
2065 | break; | |
2066 | } | |
2067 | #endif | |
4ff5ef9e | 2068 | gen_exception_internal_insn(s, s->pc_curr, EXCP_SEMIHOST); |
8012c84f PM |
2069 | } else { |
2070 | unsupported_encoding(s, insn); | |
2071 | } | |
9618e809 AG |
2072 | break; |
2073 | case 5: | |
2074 | if (op2_ll < 1 || op2_ll > 3) { | |
2075 | unallocated_encoding(s); | |
2076 | break; | |
2077 | } | |
2078 | /* DCPS1, DCPS2, DCPS3 */ | |
2079 | unsupported_encoding(s, insn); | |
2080 | break; | |
2081 | default: | |
2082 | unallocated_encoding(s); | |
2083 | break; | |
2084 | } | |
ad7ee8a2 CF |
2085 | } |
2086 | ||
4ce31af4 | 2087 | /* Unconditional branch (register) |
b001c8c3 AG |
2088 | * 31 25 24 21 20 16 15 10 9 5 4 0 |
2089 | * +---------------+-------+-------+-------+------+-------+ | |
2090 | * | 1 1 0 1 0 1 1 | opc | op2 | op3 | Rn | op4 | | |
2091 | * +---------------+-------+-------+-------+------+-------+ | |
2092 | */ | |
ad7ee8a2 CF |
2093 | static void disas_uncond_b_reg(DisasContext *s, uint32_t insn) |
2094 | { | |
b001c8c3 | 2095 | unsigned int opc, op2, op3, rn, op4; |
001d47b6 | 2096 | unsigned btype_mod = 2; /* 0: BR, 1: BLR, 2: other */ |
d9f482a0 | 2097 | TCGv_i64 dst; |
561c0a33 | 2098 | TCGv_i64 modifier; |
b001c8c3 AG |
2099 | |
2100 | opc = extract32(insn, 21, 4); | |
2101 | op2 = extract32(insn, 16, 5); | |
2102 | op3 = extract32(insn, 10, 6); | |
2103 | rn = extract32(insn, 5, 5); | |
2104 | op4 = extract32(insn, 0, 5); | |
2105 | ||
f7cf3bfc RH |
2106 | if (op2 != 0x1f) { |
2107 | goto do_unallocated; | |
b001c8c3 AG |
2108 | } |
2109 | ||
2110 | switch (opc) { | |
2111 | case 0: /* BR */ | |
b001c8c3 | 2112 | case 1: /* BLR */ |
6feecb8b | 2113 | case 2: /* RET */ |
001d47b6 | 2114 | btype_mod = opc; |
f7cf3bfc RH |
2115 | switch (op3) { |
2116 | case 0: | |
561c0a33 | 2117 | /* BR, BLR, RET */ |
f7cf3bfc RH |
2118 | if (op4 != 0) { |
2119 | goto do_unallocated; | |
2120 | } | |
2121 | dst = cpu_reg(s, rn); | |
2122 | break; | |
2123 | ||
561c0a33 RH |
2124 | case 2: |
2125 | case 3: | |
2126 | if (!dc_isar_feature(aa64_pauth, s)) { | |
2127 | goto do_unallocated; | |
2128 | } | |
2129 | if (opc == 2) { | |
2130 | /* RETAA, RETAB */ | |
2131 | if (rn != 0x1f || op4 != 0x1f) { | |
2132 | goto do_unallocated; | |
2133 | } | |
2134 | rn = 30; | |
2135 | modifier = cpu_X[31]; | |
2136 | } else { | |
2137 | /* BRAAZ, BRABZ, BLRAAZ, BLRABZ */ | |
2138 | if (op4 != 0x1f) { | |
2139 | goto do_unallocated; | |
2140 | } | |
2141 | modifier = new_tmp_a64_zero(s); | |
2142 | } | |
2143 | if (s->pauth_active) { | |
2144 | dst = new_tmp_a64(s); | |
2145 | if (op3 == 2) { | |
2146 | gen_helper_autia(dst, cpu_env, cpu_reg(s, rn), modifier); | |
2147 | } else { | |
2148 | gen_helper_autib(dst, cpu_env, cpu_reg(s, rn), modifier); | |
2149 | } | |
2150 | } else { | |
2151 | dst = cpu_reg(s, rn); | |
2152 | } | |
2153 | break; | |
2154 | ||
f7cf3bfc RH |
2155 | default: |
2156 | goto do_unallocated; | |
2157 | } | |
f7cf3bfc | 2158 | gen_a64_set_pc(s, dst); |
6feecb8b TH |
2159 | /* BLR also needs to load return address */ |
2160 | if (opc == 1) { | |
a0415916 | 2161 | tcg_gen_movi_i64(cpu_reg(s, 30), s->base.pc_next); |
6feecb8b | 2162 | } |
b001c8c3 | 2163 | break; |
f7cf3bfc | 2164 | |
561c0a33 RH |
2165 | case 8: /* BRAA */ |
2166 | case 9: /* BLRAA */ | |
2167 | if (!dc_isar_feature(aa64_pauth, s)) { | |
2168 | goto do_unallocated; | |
2169 | } | |
1cf86a86 | 2170 | if ((op3 & ~1) != 2) { |
561c0a33 RH |
2171 | goto do_unallocated; |
2172 | } | |
001d47b6 | 2173 | btype_mod = opc & 1; |
561c0a33 RH |
2174 | if (s->pauth_active) { |
2175 | dst = new_tmp_a64(s); | |
2176 | modifier = cpu_reg_sp(s, op4); | |
2177 | if (op3 == 2) { | |
2178 | gen_helper_autia(dst, cpu_env, cpu_reg(s, rn), modifier); | |
2179 | } else { | |
2180 | gen_helper_autib(dst, cpu_env, cpu_reg(s, rn), modifier); | |
2181 | } | |
2182 | } else { | |
2183 | dst = cpu_reg(s, rn); | |
2184 | } | |
2185 | gen_a64_set_pc(s, dst); | |
2186 | /* BLRAA also needs to load return address */ | |
2187 | if (opc == 9) { | |
a0415916 | 2188 | tcg_gen_movi_i64(cpu_reg(s, 30), s->base.pc_next); |
561c0a33 RH |
2189 | } |
2190 | break; | |
2191 | ||
b001c8c3 | 2192 | case 4: /* ERET */ |
dcbff19b | 2193 | if (s->current_el == 0) { |
f7cf3bfc RH |
2194 | goto do_unallocated; |
2195 | } | |
2196 | switch (op3) { | |
561c0a33 | 2197 | case 0: /* ERET */ |
f7cf3bfc RH |
2198 | if (op4 != 0) { |
2199 | goto do_unallocated; | |
2200 | } | |
2201 | dst = tcg_temp_new_i64(); | |
2202 | tcg_gen_ld_i64(dst, cpu_env, | |
2203 | offsetof(CPUARMState, elr_el[s->current_el])); | |
2204 | break; | |
2205 | ||
561c0a33 RH |
2206 | case 2: /* ERETAA */ |
2207 | case 3: /* ERETAB */ | |
2208 | if (!dc_isar_feature(aa64_pauth, s)) { | |
2209 | goto do_unallocated; | |
2210 | } | |
2211 | if (rn != 0x1f || op4 != 0x1f) { | |
2212 | goto do_unallocated; | |
2213 | } | |
2214 | dst = tcg_temp_new_i64(); | |
2215 | tcg_gen_ld_i64(dst, cpu_env, | |
2216 | offsetof(CPUARMState, elr_el[s->current_el])); | |
2217 | if (s->pauth_active) { | |
2218 | modifier = cpu_X[31]; | |
2219 | if (op3 == 2) { | |
2220 | gen_helper_autia(dst, cpu_env, dst, modifier); | |
2221 | } else { | |
2222 | gen_helper_autib(dst, cpu_env, dst, modifier); | |
2223 | } | |
2224 | } | |
2225 | break; | |
2226 | ||
f7cf3bfc RH |
2227 | default: |
2228 | goto do_unallocated; | |
14c521d4 | 2229 | } |
e69ad9df AL |
2230 | if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { |
2231 | gen_io_start(); | |
2232 | } | |
f7cf3bfc | 2233 | |
d9f482a0 RH |
2234 | gen_helper_exception_return(cpu_env, dst); |
2235 | tcg_temp_free_i64(dst); | |
b29fd33d | 2236 | /* Must exit loop to check un-masked IRQs */ |
dcba3a8d | 2237 | s->base.is_jmp = DISAS_EXIT; |
52e60cdd | 2238 | return; |
f7cf3bfc | 2239 | |
b001c8c3 | 2240 | case 5: /* DRPS */ |
f7cf3bfc RH |
2241 | if (op3 != 0 || op4 != 0 || rn != 0x1f) { |
2242 | goto do_unallocated; | |
b001c8c3 AG |
2243 | } else { |
2244 | unsupported_encoding(s, insn); | |
2245 | } | |
2246 | return; | |
f7cf3bfc | 2247 | |
b001c8c3 | 2248 | default: |
f7cf3bfc | 2249 | do_unallocated: |
b001c8c3 AG |
2250 | unallocated_encoding(s); |
2251 | return; | |
2252 | } | |
2253 | ||
001d47b6 RH |
2254 | switch (btype_mod) { |
2255 | case 0: /* BR */ | |
2256 | if (dc_isar_feature(aa64_bti, s)) { | |
2257 | /* BR to {x16,x17} or !guard -> 1, else 3. */ | |
2258 | set_btype(s, rn == 16 || rn == 17 || !s->guarded_page ? 1 : 3); | |
2259 | } | |
2260 | break; | |
2261 | ||
2262 | case 1: /* BLR */ | |
2263 | if (dc_isar_feature(aa64_bti, s)) { | |
2264 | /* BLR sets BTYPE to 2, regardless of source guarded page. */ | |
2265 | set_btype(s, 2); | |
2266 | } | |
2267 | break; | |
2268 | ||
2269 | default: /* RET or none of the above. */ | |
2270 | /* BTYPE will be set to 0 by normal end-of-insn processing. */ | |
2271 | break; | |
2272 | } | |
2273 | ||
dcba3a8d | 2274 | s->base.is_jmp = DISAS_JUMP; |
ad7ee8a2 CF |
2275 | } |
2276 | ||
4ce31af4 | 2277 | /* Branches, exception generating and system instructions */ |
ad7ee8a2 CF |
2278 | static void disas_b_exc_sys(DisasContext *s, uint32_t insn) |
2279 | { | |
2280 | switch (extract32(insn, 25, 7)) { | |
2281 | case 0x0a: case 0x0b: | |
2282 | case 0x4a: case 0x4b: /* Unconditional branch (immediate) */ | |
2283 | disas_uncond_b_imm(s, insn); | |
2284 | break; | |
2285 | case 0x1a: case 0x5a: /* Compare & branch (immediate) */ | |
2286 | disas_comp_b_imm(s, insn); | |
2287 | break; | |
2288 | case 0x1b: case 0x5b: /* Test & branch (immediate) */ | |
2289 | disas_test_b_imm(s, insn); | |
2290 | break; | |
2291 | case 0x2a: /* Conditional branch (immediate) */ | |
2292 | disas_cond_b_imm(s, insn); | |
2293 | break; | |
2294 | case 0x6a: /* Exception generation / System */ | |
2295 | if (insn & (1 << 24)) { | |
08d5e3bd PM |
2296 | if (extract32(insn, 22, 2) == 0) { |
2297 | disas_system(s, insn); | |
2298 | } else { | |
2299 | unallocated_encoding(s); | |
2300 | } | |
ad7ee8a2 CF |
2301 | } else { |
2302 | disas_exc(s, insn); | |
2303 | } | |
2304 | break; | |
2305 | case 0x6b: /* Unconditional branch (register) */ | |
2306 | disas_uncond_b_reg(s, insn); | |
2307 | break; | |
2308 | default: | |
2309 | unallocated_encoding(s); | |
2310 | break; | |
2311 | } | |
2312 | } | |
2313 | ||
5460da50 AB |
2314 | /* |
2315 | * Load/Store exclusive instructions are implemented by remembering | |
2316 | * the value/address loaded, and seeing if these are the same | |
2317 | * when the store is performed. This is not actually the architecturally | |
2318 | * mandated semantics, but it works for typical guest code sequences | |
2319 | * and avoids having to monitor regular stores. | |
2320 | * | |
2321 | * The store exclusive uses the atomic cmpxchg primitives to avoid | |
2322 | * races in multi-threaded linux-user and when MTTCG softmmu is | |
2323 | * enabled. | |
2324 | */ | |
fa2ef212 MM |
2325 | static void gen_load_exclusive(DisasContext *s, int rt, int rt2, |
2326 | TCGv_i64 addr, int size, bool is_pair) | |
2327 | { | |
19514cde | 2328 | int idx = get_mem_index(s); |
14776ab5 | 2329 | MemOp memop = s->be_data; |
fa2ef212 MM |
2330 | |
2331 | g_assert(size <= 3); | |
fa2ef212 | 2332 | if (is_pair) { |
5460da50 | 2333 | g_assert(size >= 2); |
19514cde RH |
2334 | if (size == 2) { |
2335 | /* The pair must be single-copy atomic for the doubleword. */ | |
4a2fdb78 | 2336 | memop |= MO_64 | MO_ALIGN; |
19514cde RH |
2337 | tcg_gen_qemu_ld_i64(cpu_exclusive_val, addr, idx, memop); |
2338 | if (s->be_data == MO_LE) { | |
2339 | tcg_gen_extract_i64(cpu_reg(s, rt), cpu_exclusive_val, 0, 32); | |
2340 | tcg_gen_extract_i64(cpu_reg(s, rt2), cpu_exclusive_val, 32, 32); | |
2341 | } else { | |
2342 | tcg_gen_extract_i64(cpu_reg(s, rt), cpu_exclusive_val, 32, 32); | |
2343 | tcg_gen_extract_i64(cpu_reg(s, rt2), cpu_exclusive_val, 0, 32); | |
2344 | } | |
2345 | } else { | |
4a2fdb78 AF |
2346 | /* The pair must be single-copy atomic for *each* doubleword, not |
2347 | the entire quadword, however it must be quadword aligned. */ | |
19514cde | 2348 | memop |= MO_64; |
4a2fdb78 AF |
2349 | tcg_gen_qemu_ld_i64(cpu_exclusive_val, addr, idx, |
2350 | memop | MO_ALIGN_16); | |
19514cde RH |
2351 | |
2352 | TCGv_i64 addr2 = tcg_temp_new_i64(); | |
2353 | tcg_gen_addi_i64(addr2, addr, 8); | |
2354 | tcg_gen_qemu_ld_i64(cpu_exclusive_high, addr2, idx, memop); | |
2355 | tcg_temp_free_i64(addr2); | |
2356 | ||
2357 | tcg_gen_mov_i64(cpu_reg(s, rt), cpu_exclusive_val); | |
2358 | tcg_gen_mov_i64(cpu_reg(s, rt2), cpu_exclusive_high); | |
2359 | } | |
2360 | } else { | |
4a2fdb78 | 2361 | memop |= size | MO_ALIGN; |
19514cde RH |
2362 | tcg_gen_qemu_ld_i64(cpu_exclusive_val, addr, idx, memop); |
2363 | tcg_gen_mov_i64(cpu_reg(s, rt), cpu_exclusive_val); | |
fa2ef212 | 2364 | } |
fa2ef212 MM |
2365 | tcg_gen_mov_i64(cpu_exclusive_addr, addr); |
2366 | } | |
2367 | ||
fa2ef212 | 2368 | static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2, |
37e29a64 | 2369 | TCGv_i64 addr, int size, int is_pair) |
fa2ef212 | 2370 | { |
d324b36a PM |
2371 | /* if (env->exclusive_addr == addr && env->exclusive_val == [addr] |
2372 | * && (!is_pair || env->exclusive_high == [addr + datasize])) { | |
2373 | * [addr] = {Rt}; | |
2374 | * if (is_pair) { | |
2375 | * [addr + datasize] = {Rt2}; | |
2376 | * } | |
2377 | * {Rd} = 0; | |
2378 | * } else { | |
2379 | * {Rd} = 1; | |
2380 | * } | |
2381 | * env->exclusive_addr = -1; | |
2382 | */ | |
42a268c2 RH |
2383 | TCGLabel *fail_label = gen_new_label(); |
2384 | TCGLabel *done_label = gen_new_label(); | |
d324b36a PM |
2385 | TCGv_i64 tmp; |
2386 | ||
d324b36a PM |
2387 | tcg_gen_brcond_i64(TCG_COND_NE, addr, cpu_exclusive_addr, fail_label); |
2388 | ||
2389 | tmp = tcg_temp_new_i64(); | |
d324b36a | 2390 | if (is_pair) { |
1dd089d0 | 2391 | if (size == 2) { |
19514cde RH |
2392 | if (s->be_data == MO_LE) { |
2393 | tcg_gen_concat32_i64(tmp, cpu_reg(s, rt), cpu_reg(s, rt2)); | |
2394 | } else { | |
2395 | tcg_gen_concat32_i64(tmp, cpu_reg(s, rt2), cpu_reg(s, rt)); | |
2396 | } | |
37e29a64 RH |
2397 | tcg_gen_atomic_cmpxchg_i64(tmp, cpu_exclusive_addr, |
2398 | cpu_exclusive_val, tmp, | |
1dd089d0 | 2399 | get_mem_index(s), |
955fd0ad | 2400 | MO_64 | MO_ALIGN | s->be_data); |
19514cde | 2401 | tcg_gen_setcond_i64(TCG_COND_NE, tmp, tmp, cpu_exclusive_val); |
62823083 RH |
2402 | } else if (tb_cflags(s->base.tb) & CF_PARALLEL) { |
2403 | if (!HAVE_CMPXCHG128) { | |
2404 | gen_helper_exit_atomic(cpu_env); | |
2405 | s->base.is_jmp = DISAS_NORETURN; | |
2406 | } else if (s->be_data == MO_LE) { | |
2399d4e7 EC |
2407 | gen_helper_paired_cmpxchg64_le_parallel(tmp, cpu_env, |
2408 | cpu_exclusive_addr, | |
2409 | cpu_reg(s, rt), | |
2410 | cpu_reg(s, rt2)); | |
2411 | } else { | |
2399d4e7 EC |
2412 | gen_helper_paired_cmpxchg64_be_parallel(tmp, cpu_env, |
2413 | cpu_exclusive_addr, | |
2414 | cpu_reg(s, rt), | |
2415 | cpu_reg(s, rt2)); | |
2399d4e7 | 2416 | } |
62823083 RH |
2417 | } else if (s->be_data == MO_LE) { |
2418 | gen_helper_paired_cmpxchg64_le(tmp, cpu_env, cpu_exclusive_addr, | |
2419 | cpu_reg(s, rt), cpu_reg(s, rt2)); | |
2420 | } else { | |
2421 | gen_helper_paired_cmpxchg64_be(tmp, cpu_env, cpu_exclusive_addr, | |
2422 | cpu_reg(s, rt), cpu_reg(s, rt2)); | |
1dd089d0 EC |
2423 | } |
2424 | } else { | |
37e29a64 RH |
2425 | tcg_gen_atomic_cmpxchg_i64(tmp, cpu_exclusive_addr, cpu_exclusive_val, |
2426 | cpu_reg(s, rt), get_mem_index(s), | |
1dd089d0 EC |
2427 | size | MO_ALIGN | s->be_data); |
2428 | tcg_gen_setcond_i64(TCG_COND_NE, tmp, tmp, cpu_exclusive_val); | |
d324b36a | 2429 | } |
1dd089d0 EC |
2430 | tcg_gen_mov_i64(cpu_reg(s, rd), tmp); |
2431 | tcg_temp_free_i64(tmp); | |
d324b36a | 2432 | tcg_gen_br(done_label); |
1dd089d0 | 2433 | |
d324b36a PM |
2434 | gen_set_label(fail_label); |
2435 | tcg_gen_movi_i64(cpu_reg(s, rd), 1); | |
2436 | gen_set_label(done_label); | |
2437 | tcg_gen_movi_i64(cpu_exclusive_addr, -1); | |
fa2ef212 | 2438 | } |
fa2ef212 | 2439 | |
44ac14b0 RH |
2440 | static void gen_compare_and_swap(DisasContext *s, int rs, int rt, |
2441 | int rn, int size) | |
2442 | { | |
2443 | TCGv_i64 tcg_rs = cpu_reg(s, rs); | |
2444 | TCGv_i64 tcg_rt = cpu_reg(s, rt); | |
2445 | int memidx = get_mem_index(s); | |
3a471103 | 2446 | TCGv_i64 clean_addr; |
44ac14b0 RH |
2447 | |
2448 | if (rn == 31) { | |
2449 | gen_check_sp_alignment(s); | |
2450 | } | |
0a405be2 | 2451 | clean_addr = gen_mte_check1(s, cpu_reg_sp(s, rn), true, rn != 31, size); |
3a471103 | 2452 | tcg_gen_atomic_cmpxchg_i64(tcg_rs, clean_addr, tcg_rs, tcg_rt, memidx, |
44ac14b0 RH |
2453 | size | MO_ALIGN | s->be_data); |
2454 | } | |
2455 | ||
2456 | static void gen_compare_and_swap_pair(DisasContext *s, int rs, int rt, | |
2457 | int rn, int size) | |
2458 | { | |
2459 | TCGv_i64 s1 = cpu_reg(s, rs); | |
2460 | TCGv_i64 s2 = cpu_reg(s, rs + 1); | |
2461 | TCGv_i64 t1 = cpu_reg(s, rt); | |
2462 | TCGv_i64 t2 = cpu_reg(s, rt + 1); | |
3a471103 | 2463 | TCGv_i64 clean_addr; |
44ac14b0 RH |
2464 | int memidx = get_mem_index(s); |
2465 | ||
2466 | if (rn == 31) { | |
2467 | gen_check_sp_alignment(s); | |
2468 | } | |
0a405be2 RH |
2469 | |
2470 | /* This is a single atomic access, despite the "pair". */ | |
2471 | clean_addr = gen_mte_check1(s, cpu_reg_sp(s, rn), true, rn != 31, size + 1); | |
44ac14b0 RH |
2472 | |
2473 | if (size == 2) { | |
2474 | TCGv_i64 cmp = tcg_temp_new_i64(); | |
2475 | TCGv_i64 val = tcg_temp_new_i64(); | |
2476 | ||
2477 | if (s->be_data == MO_LE) { | |
2478 | tcg_gen_concat32_i64(val, t1, t2); | |
2479 | tcg_gen_concat32_i64(cmp, s1, s2); | |
2480 | } else { | |
2481 | tcg_gen_concat32_i64(val, t2, t1); | |
2482 | tcg_gen_concat32_i64(cmp, s2, s1); | |
2483 | } | |
2484 | ||
3a471103 | 2485 | tcg_gen_atomic_cmpxchg_i64(cmp, clean_addr, cmp, val, memidx, |
44ac14b0 RH |
2486 | MO_64 | MO_ALIGN | s->be_data); |
2487 | tcg_temp_free_i64(val); | |
2488 | ||
2489 | if (s->be_data == MO_LE) { | |
2490 | tcg_gen_extr32_i64(s1, s2, cmp); | |
2491 | } else { | |
2492 | tcg_gen_extr32_i64(s2, s1, cmp); | |
2493 | } | |
2494 | tcg_temp_free_i64(cmp); | |
2495 | } else if (tb_cflags(s->base.tb) & CF_PARALLEL) { | |
62823083 RH |
2496 | if (HAVE_CMPXCHG128) { |
2497 | TCGv_i32 tcg_rs = tcg_const_i32(rs); | |
2498 | if (s->be_data == MO_LE) { | |
3a471103 RH |
2499 | gen_helper_casp_le_parallel(cpu_env, tcg_rs, |
2500 | clean_addr, t1, t2); | |
62823083 | 2501 | } else { |
3a471103 RH |
2502 | gen_helper_casp_be_parallel(cpu_env, tcg_rs, |
2503 | clean_addr, t1, t2); | |
62823083 RH |
2504 | } |
2505 | tcg_temp_free_i32(tcg_rs); | |
44ac14b0 | 2506 | } else { |
62823083 RH |
2507 | gen_helper_exit_atomic(cpu_env); |
2508 | s->base.is_jmp = DISAS_NORETURN; | |
44ac14b0 | 2509 | } |
44ac14b0 RH |
2510 | } else { |
2511 | TCGv_i64 d1 = tcg_temp_new_i64(); | |
2512 | TCGv_i64 d2 = tcg_temp_new_i64(); | |
2513 | TCGv_i64 a2 = tcg_temp_new_i64(); | |
2514 | TCGv_i64 c1 = tcg_temp_new_i64(); | |
2515 | TCGv_i64 c2 = tcg_temp_new_i64(); | |
2516 | TCGv_i64 zero = tcg_const_i64(0); | |
2517 | ||
2518 | /* Load the two words, in memory order. */ | |
3a471103 | 2519 | tcg_gen_qemu_ld_i64(d1, clean_addr, memidx, |
44ac14b0 | 2520 | MO_64 | MO_ALIGN_16 | s->be_data); |
3a471103 | 2521 | tcg_gen_addi_i64(a2, clean_addr, 8); |
a036f530 | 2522 | tcg_gen_qemu_ld_i64(d2, a2, memidx, MO_64 | s->be_data); |
44ac14b0 RH |
2523 | |
2524 | /* Compare the two words, also in memory order. */ | |
2525 | tcg_gen_setcond_i64(TCG_COND_EQ, c1, d1, s1); | |
2526 | tcg_gen_setcond_i64(TCG_COND_EQ, c2, d2, s2); | |
2527 | tcg_gen_and_i64(c2, c2, c1); | |
2528 | ||
2529 | /* If compare equal, write back new data, else write back old data. */ | |
2530 | tcg_gen_movcond_i64(TCG_COND_NE, c1, c2, zero, t1, d1); | |
2531 | tcg_gen_movcond_i64(TCG_COND_NE, c2, c2, zero, t2, d2); | |
3a471103 | 2532 | tcg_gen_qemu_st_i64(c1, clean_addr, memidx, MO_64 | s->be_data); |
44ac14b0 RH |
2533 | tcg_gen_qemu_st_i64(c2, a2, memidx, MO_64 | s->be_data); |
2534 | tcg_temp_free_i64(a2); | |
2535 | tcg_temp_free_i64(c1); | |
2536 | tcg_temp_free_i64(c2); | |
2537 | tcg_temp_free_i64(zero); | |
2538 | ||
2539 | /* Write back the data from memory to Rs. */ | |
2540 | tcg_gen_mov_i64(s1, d1); | |
2541 | tcg_gen_mov_i64(s2, d2); | |
2542 | tcg_temp_free_i64(d1); | |
2543 | tcg_temp_free_i64(d2); | |
2544 | } | |
2545 | } | |
2546 | ||
aaa1f954 EI |
2547 | /* Update the Sixty-Four bit (SF) registersize. This logic is derived |
2548 | * from the ARMv8 specs for LDR (Shared decode for all encodings). | |
2549 | */ | |
2550 | static bool disas_ldst_compute_iss_sf(int size, bool is_signed, int opc) | |
2551 | { | |
2552 | int opc0 = extract32(opc, 0, 1); | |
2553 | int regsize; | |
2554 | ||
2555 | if (is_signed) { | |
2556 | regsize = opc0 ? 32 : 64; | |
2557 | } else { | |
2558 | regsize = size == 3 ? 64 : 32; | |
2559 | } | |
2560 | return regsize == 64; | |
2561 | } | |
2562 | ||
4ce31af4 | 2563 | /* Load/store exclusive |
fa2ef212 MM |
2564 | * |
2565 | * 31 30 29 24 23 22 21 20 16 15 14 10 9 5 4 0 | |
2566 | * +-----+-------------+----+---+----+------+----+-------+------+------+ | |
2567 | * | sz | 0 0 1 0 0 0 | o2 | L | o1 | Rs | o0 | Rt2 | Rn | Rt | | |
2568 | * +-----+-------------+----+---+----+------+----+-------+------+------+ | |
2569 | * | |
2570 | * sz: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64 bit | |
2571 | * L: 0 -> store, 1 -> load | |
2572 | * o2: 0 -> exclusive, 1 -> not | |
2573 | * o1: 0 -> single register, 1 -> register pair | |
2574 | * o0: 1 -> load-acquire/store-release, 0 -> not | |
fa2ef212 | 2575 | */ |
ad7ee8a2 CF |
2576 | static void disas_ldst_excl(DisasContext *s, uint32_t insn) |
2577 | { | |
fa2ef212 MM |
2578 | int rt = extract32(insn, 0, 5); |
2579 | int rn = extract32(insn, 5, 5); | |
2580 | int rt2 = extract32(insn, 10, 5); | |
fa2ef212 | 2581 | int rs = extract32(insn, 16, 5); |
68412d2e RH |
2582 | int is_lasr = extract32(insn, 15, 1); |
2583 | int o2_L_o1_o0 = extract32(insn, 21, 3) * 2 | is_lasr; | |
fa2ef212 | 2584 | int size = extract32(insn, 30, 2); |
3a471103 | 2585 | TCGv_i64 clean_addr; |
fa2ef212 | 2586 | |
68412d2e RH |
2587 | switch (o2_L_o1_o0) { |
2588 | case 0x0: /* STXR */ | |
2589 | case 0x1: /* STLXR */ | |
2590 | if (rn == 31) { | |
2591 | gen_check_sp_alignment(s); | |
2592 | } | |
2593 | if (is_lasr) { | |
2594 | tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); | |
2595 | } | |
0a405be2 RH |
2596 | clean_addr = gen_mte_check1(s, cpu_reg_sp(s, rn), |
2597 | true, rn != 31, size); | |
3a471103 | 2598 | gen_store_exclusive(s, rs, rt, rt2, clean_addr, size, false); |
fa2ef212 | 2599 | return; |
fa2ef212 | 2600 | |
68412d2e RH |
2601 | case 0x4: /* LDXR */ |
2602 | case 0x5: /* LDAXR */ | |
2603 | if (rn == 31) { | |
2604 | gen_check_sp_alignment(s); | |
2605 | } | |
0a405be2 RH |
2606 | clean_addr = gen_mte_check1(s, cpu_reg_sp(s, rn), |
2607 | false, rn != 31, size); | |
68412d2e | 2608 | s->is_ldex = true; |
3a471103 | 2609 | gen_load_exclusive(s, rt, rt2, clean_addr, size, false); |
68412d2e RH |
2610 | if (is_lasr) { |
2611 | tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); | |
2612 | } | |
2613 | return; | |
fa2ef212 | 2614 | |
2d7137c1 RH |
2615 | case 0x8: /* STLLR */ |
2616 | if (!dc_isar_feature(aa64_lor, s)) { | |
2617 | break; | |
2618 | } | |
2619 | /* StoreLORelease is the same as Store-Release for QEMU. */ | |
2620 | /* fall through */ | |
68412d2e RH |
2621 | case 0x9: /* STLR */ |
2622 | /* Generate ISS for non-exclusive accesses including LASR. */ | |
2623 | if (rn == 31) { | |
2624 | gen_check_sp_alignment(s); | |
2625 | } | |
2626 | tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); | |
0a405be2 RH |
2627 | clean_addr = gen_mte_check1(s, cpu_reg_sp(s, rn), |
2628 | true, rn != 31, size); | |
3a471103 | 2629 | do_gpr_st(s, cpu_reg(s, rt), clean_addr, size, true, rt, |
68412d2e RH |
2630 | disas_ldst_compute_iss_sf(size, false, 0), is_lasr); |
2631 | return; | |
fa2ef212 | 2632 | |
2d7137c1 RH |
2633 | case 0xc: /* LDLAR */ |
2634 | if (!dc_isar_feature(aa64_lor, s)) { | |
2635 | break; | |
2636 | } | |
2637 | /* LoadLOAcquire is the same as Load-Acquire for QEMU. */ | |
2638 | /* fall through */ | |
68412d2e RH |
2639 | case 0xd: /* LDAR */ |
2640 | /* Generate ISS for non-exclusive accesses including LASR. */ | |
2641 | if (rn == 31) { | |
2642 | gen_check_sp_alignment(s); | |
2643 | } | |
0a405be2 RH |
2644 | clean_addr = gen_mte_check1(s, cpu_reg_sp(s, rn), |
2645 | false, rn != 31, size); | |
3a471103 | 2646 | do_gpr_ld(s, cpu_reg(s, rt), clean_addr, size, false, false, true, rt, |
68412d2e RH |
2647 | disas_ldst_compute_iss_sf(size, false, 0), is_lasr); |
2648 | tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); | |
2649 | return; | |
2650 | ||
2651 | case 0x2: case 0x3: /* CASP / STXP */ | |
2652 | if (size & 2) { /* STXP / STLXP */ | |
2653 | if (rn == 31) { | |
2654 | gen_check_sp_alignment(s); | |
ce1bd93f | 2655 | } |
ce1bd93f PK |
2656 | if (is_lasr) { |
2657 | tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); | |
2658 | } | |
0a405be2 RH |
2659 | clean_addr = gen_mte_check1(s, cpu_reg_sp(s, rn), |
2660 | true, rn != 31, size); | |
3a471103 | 2661 | gen_store_exclusive(s, rs, rt, rt2, clean_addr, size, true); |
68412d2e | 2662 | return; |
fa2ef212 | 2663 | } |
44ac14b0 RH |
2664 | if (rt2 == 31 |
2665 | && ((rt | rs) & 1) == 0 | |
962fcbf2 | 2666 | && dc_isar_feature(aa64_atomics, s)) { |
44ac14b0 RH |
2667 | /* CASP / CASPL */ |
2668 | gen_compare_and_swap_pair(s, rs, rt, rn, size | 2); | |
2669 | return; | |
2670 | } | |
68412d2e | 2671 | break; |
aaa1f954 | 2672 | |
44ac14b0 | 2673 | case 0x6: case 0x7: /* CASPA / LDXP */ |
68412d2e RH |
2674 | if (size & 2) { /* LDXP / LDAXP */ |
2675 | if (rn == 31) { | |
2676 | gen_check_sp_alignment(s); | |
ce1bd93f | 2677 | } |
0a405be2 RH |
2678 | clean_addr = gen_mte_check1(s, cpu_reg_sp(s, rn), |
2679 | false, rn != 31, size); | |
68412d2e | 2680 | s->is_ldex = true; |
3a471103 | 2681 | gen_load_exclusive(s, rt, rt2, clean_addr, size, true); |
ce1bd93f PK |
2682 | if (is_lasr) { |
2683 | tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); | |
2684 | } | |
68412d2e | 2685 | return; |
fa2ef212 | 2686 | } |
44ac14b0 RH |
2687 | if (rt2 == 31 |
2688 | && ((rt | rs) & 1) == 0 | |
962fcbf2 | 2689 | && dc_isar_feature(aa64_atomics, s)) { |
44ac14b0 RH |
2690 | /* CASPA / CASPAL */ |
2691 | gen_compare_and_swap_pair(s, rs, rt, rn, size | 2); | |
2692 | return; | |
fa2ef212 | 2693 | } |
68412d2e RH |
2694 | break; |
2695 | ||
2696 | case 0xa: /* CAS */ | |
2697 | case 0xb: /* CASL */ | |
2698 | case 0xe: /* CASA */ | |
2699 | case 0xf: /* CASAL */ | |
962fcbf2 | 2700 | if (rt2 == 31 && dc_isar_feature(aa64_atomics, s)) { |
44ac14b0 RH |
2701 | gen_compare_and_swap(s, rs, rt, rn, size); |
2702 | return; | |
2703 | } | |
68412d2e | 2704 | break; |
fa2ef212 | 2705 | } |
68412d2e | 2706 | unallocated_encoding(s); |
ad7ee8a2 CF |
2707 | } |
2708 | ||
32b64e86 | 2709 | /* |
4ce31af4 | 2710 | * Load register (literal) |
32b64e86 AG |
2711 | * |
2712 | * 31 30 29 27 26 25 24 23 5 4 0 | |
2713 | * +-----+-------+---+-----+-------------------+-------+ | |
2714 | * | opc | 0 1 1 | V | 0 0 | imm19 | Rt | | |
2715 | * +-----+-------+---+-----+-------------------+-------+ | |
2716 | * | |
2717 | * V: 1 -> vector (simd/fp) | |
2718 | * opc (non-vector): 00 -> 32 bit, 01 -> 64 bit, | |
2719 | * 10-> 32 bit signed, 11 -> prefetch | |
2720 | * opc (vector): 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit (11 unallocated) | |
2721 | */ | |
ad7ee8a2 CF |
2722 | static void disas_ld_lit(DisasContext *s, uint32_t insn) |
2723 | { | |
32b64e86 AG |
2724 | int rt = extract32(insn, 0, 5); |
2725 | int64_t imm = sextract32(insn, 5, 19) << 2; | |
2726 | bool is_vector = extract32(insn, 26, 1); | |
2727 | int opc = extract32(insn, 30, 2); | |
2728 | bool is_signed = false; | |
2729 | int size = 2; | |
3a471103 | 2730 | TCGv_i64 tcg_rt, clean_addr; |
32b64e86 AG |
2731 | |
2732 | if (is_vector) { | |
2733 | if (opc == 3) { | |
2734 | unallocated_encoding(s); | |
2735 | return; | |
2736 | } | |
2737 | size = 2 + opc; | |
8c6afa6a PM |
2738 | if (!fp_access_check(s)) { |
2739 | return; | |
2740 | } | |
32b64e86 AG |
2741 | } else { |
2742 | if (opc == 3) { | |
2743 | /* PRFM (literal) : prefetch */ | |
2744 | return; | |
2745 | } | |
2746 | size = 2 + extract32(opc, 0, 1); | |
2747 | is_signed = extract32(opc, 1, 1); | |
2748 | } | |
2749 | ||
2750 | tcg_rt = cpu_reg(s, rt); | |
2751 | ||
43722a6d | 2752 | clean_addr = tcg_const_i64(s->pc_curr + imm); |
32b64e86 | 2753 | if (is_vector) { |
3a471103 | 2754 | do_fp_ld(s, rt, clean_addr, size); |
32b64e86 | 2755 | } else { |
aaa1f954 | 2756 | /* Only unsigned 32bit loads target 32bit registers. */ |
173ff585 | 2757 | bool iss_sf = opc != 0; |
aaa1f954 | 2758 | |
3a471103 | 2759 | do_gpr_ld(s, tcg_rt, clean_addr, size, is_signed, false, |
aaa1f954 | 2760 | true, rt, iss_sf, false); |
32b64e86 | 2761 | } |
3a471103 | 2762 | tcg_temp_free_i64(clean_addr); |
ad7ee8a2 CF |
2763 | } |
2764 | ||
4a08d475 | 2765 | /* |
4ce31af4 PM |
2766 | * LDNP (Load Pair - non-temporal hint) |
2767 | * LDP (Load Pair - non vector) | |
2768 | * LDPSW (Load Pair Signed Word - non vector) | |
2769 | * STNP (Store Pair - non-temporal hint) | |
2770 | * STP (Store Pair - non vector) | |
2771 | * LDNP (Load Pair of SIMD&FP - non-temporal hint) | |
2772 | * LDP (Load Pair of SIMD&FP) | |
2773 | * STNP (Store Pair of SIMD&FP - non-temporal hint) | |
2774 | * STP (Store Pair of SIMD&FP) | |
4a08d475 PM |
2775 | * |
2776 | * 31 30 29 27 26 25 24 23 22 21 15 14 10 9 5 4 0 | |
2777 | * +-----+-------+---+---+-------+---+-----------------------------+ | |
2778 | * | opc | 1 0 1 | V | 0 | index | L | imm7 | Rt2 | Rn | Rt | | |
2779 | * +-----+-------+---+---+-------+---+-------+-------+------+------+ | |
2780 | * | |
2781 | * opc: LDP/STP/LDNP/STNP 00 -> 32 bit, 10 -> 64 bit | |
6439d67f | 2782 | * LDPSW/STGP 01 |
4a08d475 PM |
2783 | * LDP/STP/LDNP/STNP (SIMD) 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit |
2784 | * V: 0 -> GPR, 1 -> Vector | |
2785 | * idx: 00 -> signed offset with non-temporal hint, 01 -> post-index, | |
2786 | * 10 -> signed offset, 11 -> pre-index | |
2787 | * L: 0 -> Store 1 -> Load | |
2788 | * | |
2789 | * Rt, Rt2 = GPR or SIMD registers to be stored | |
2790 | * Rn = general purpose register containing address | |
2791 | * imm7 = signed offset (multiple of 4 or 8 depending on size) | |
2792 | */ | |
ad7ee8a2 CF |
2793 | static void disas_ldst_pair(DisasContext *s, uint32_t insn) |
2794 | { | |
4a08d475 PM |
2795 | int rt = extract32(insn, 0, 5); |
2796 | int rn = extract32(insn, 5, 5); | |
2797 | int rt2 = extract32(insn, 10, 5); | |
c2ebd862 | 2798 | uint64_t offset = sextract64(insn, 15, 7); |
4a08d475 PM |
2799 | int index = extract32(insn, 23, 2); |
2800 | bool is_vector = extract32(insn, 26, 1); | |
2801 | bool is_load = extract32(insn, 22, 1); | |
2802 | int opc = extract32(insn, 30, 2); | |
2803 | ||
2804 | bool is_signed = false; | |
2805 | bool postindex = false; | |
2806 | bool wback = false; | |
6439d67f | 2807 | bool set_tag = false; |
4a08d475 | 2808 | |
3a471103 RH |
2809 | TCGv_i64 clean_addr, dirty_addr; |
2810 | ||
4a08d475 PM |
2811 | int size; |
2812 | ||
2813 | if (opc == 3) { | |
2814 | unallocated_encoding(s); | |
2815 | return; | |
2816 | } | |
2817 | ||
2818 | if (is_vector) { | |
2819 | size = 2 + opc; | |
6439d67f RH |
2820 | } else if (opc == 1 && !is_load) { |
2821 | /* STGP */ | |
2822 | if (!dc_isar_feature(aa64_mte_insn_reg, s) || index == 0) { | |
2823 | unallocated_encoding(s); | |
2824 | return; | |
2825 | } | |
2826 | size = 3; | |
2827 | set_tag = true; | |
4a08d475 PM |
2828 | } else { |
2829 | size = 2 + extract32(opc, 1, 1); | |
2830 | is_signed = extract32(opc, 0, 1); | |
2831 | if (!is_load && is_signed) { | |
2832 | unallocated_encoding(s); | |
2833 | return; | |
2834 | } | |
2835 | } | |
2836 | ||
2837 | switch (index) { | |
2838 | case 1: /* post-index */ | |
2839 | postindex = true; | |
2840 | wback = true; | |
2841 | break; | |
2842 | case 0: | |
2843 | /* signed offset with "non-temporal" hint. Since we don't emulate | |
2844 | * caches we don't care about hints to the cache system about | |
2845 | * data access patterns, and handle this identically to plain | |
2846 | * signed offset. | |
2847 | */ | |
2848 | if (is_signed) { | |
2849 | /* There is no non-temporal-hint version of LDPSW */ | |
2850 | unallocated_encoding(s); | |
2851 | return; | |
2852 | } | |
2853 | postindex = false; | |
2854 | break; | |
2855 | case 2: /* signed offset, rn not updated */ | |
2856 | postindex = false; | |
2857 | break; | |
2858 | case 3: /* pre-index */ | |
2859 | postindex = false; | |
2860 | wback = true; | |
2861 | break; | |
2862 | } | |
2863 | ||
8c6afa6a PM |
2864 | if (is_vector && !fp_access_check(s)) { |
2865 | return; | |
2866 | } | |
2867 | ||
6439d67f | 2868 | offset <<= (set_tag ? LOG2_TAG_GRANULE : size); |
4a08d475 PM |
2869 | |
2870 | if (rn == 31) { | |
2871 | gen_check_sp_alignment(s); | |
2872 | } | |
2873 | ||
3a471103 | 2874 | dirty_addr = read_cpu_reg_sp(s, rn, 1); |
4a08d475 | 2875 | if (!postindex) { |
3a471103 | 2876 | tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); |
4a08d475 PM |
2877 | } |
2878 | ||
6439d67f RH |
2879 | if (set_tag) { |
2880 | if (!s->ata) { | |
2881 | /* | |
2882 | * TODO: We could rely on the stores below, at least for | |
2883 | * system mode, if we arrange to add MO_ALIGN_16. | |
2884 | */ | |
2885 | gen_helper_stg_stub(cpu_env, dirty_addr); | |
2886 | } else if (tb_cflags(s->base.tb) & CF_PARALLEL) { | |
2887 | gen_helper_stg_parallel(cpu_env, dirty_addr, dirty_addr); | |
2888 | } else { | |
2889 | gen_helper_stg(cpu_env, dirty_addr, dirty_addr); | |
2890 | } | |
2891 | } | |
2892 | ||
73ceeb00 RH |
2893 | clean_addr = gen_mte_checkN(s, dirty_addr, !is_load, |
2894 | (wback || rn != 31) && !set_tag, | |
2895 | size, 2 << size); | |
2896 | ||
4a08d475 PM |
2897 | if (is_vector) { |
2898 | if (is_load) { | |
3a471103 | 2899 | do_fp_ld(s, rt, clean_addr, size); |
4a08d475 | 2900 | } else { |
3a471103 | 2901 | do_fp_st(s, rt, clean_addr, size); |
4a08d475 | 2902 | } |
3a471103 | 2903 | tcg_gen_addi_i64(clean_addr, clean_addr, 1 << size); |
4a08d475 | 2904 | if (is_load) { |
3a471103 | 2905 | do_fp_ld(s, rt2, clean_addr, size); |
4a08d475 | 2906 | } else { |
3a471103 | 2907 | do_fp_st(s, rt2, clean_addr, size); |
4a08d475 PM |
2908 | } |
2909 | } else { | |
3e4d91b9 | 2910 | TCGv_i64 tcg_rt = cpu_reg(s, rt); |
4a08d475 | 2911 | TCGv_i64 tcg_rt2 = cpu_reg(s, rt2); |
3e4d91b9 | 2912 | |
4a08d475 | 2913 | if (is_load) { |
3e4d91b9 RH |
2914 | TCGv_i64 tmp = tcg_temp_new_i64(); |
2915 | ||
2916 | /* Do not modify tcg_rt before recognizing any exception | |
2917 | * from the second load. | |
2918 | */ | |
3a471103 | 2919 | do_gpr_ld(s, tmp, clean_addr, size, is_signed, false, |
3e4d91b9 | 2920 | false, 0, false, false); |
3a471103 RH |
2921 | tcg_gen_addi_i64(clean_addr, clean_addr, 1 << size); |
2922 | do_gpr_ld(s, tcg_rt2, clean_addr, size, is_signed, false, | |
aaa1f954 | 2923 | false, 0, false, false); |
3e4d91b9 RH |
2924 | |
2925 | tcg_gen_mov_i64(tcg_rt, tmp); | |
2926 | tcg_temp_free_i64(tmp); | |
4a08d475 | 2927 | } else { |
3a471103 | 2928 | do_gpr_st(s, tcg_rt, clean_addr, size, |
3e4d91b9 | 2929 | false, 0, false, false); |
3a471103 RH |
2930 | tcg_gen_addi_i64(clean_addr, clean_addr, 1 << size); |
2931 | do_gpr_st(s, tcg_rt2, clean_addr, size, | |
aaa1f954 | 2932 | false, 0, false, false); |
4a08d475 PM |
2933 | } |
2934 | } | |
2935 | ||
2936 | if (wback) { | |
2937 | if (postindex) { | |
3a471103 | 2938 | tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); |
4a08d475 | 2939 | } |
3a471103 | 2940 | tcg_gen_mov_i64(cpu_reg_sp(s, rn), dirty_addr); |
4a08d475 | 2941 | } |
ad7ee8a2 CF |
2942 | } |
2943 | ||
a5e94a9d | 2944 | /* |
4ce31af4 PM |
2945 | * Load/store (immediate post-indexed) |
2946 | * Load/store (immediate pre-indexed) | |
2947 | * Load/store (unscaled immediate) | |
a5e94a9d AB |
2948 | * |
2949 | * 31 30 29 27 26 25 24 23 22 21 20 12 11 10 9 5 4 0 | |
2950 | * +----+-------+---+-----+-----+---+--------+-----+------+------+ | |
2951 | * |size| 1 1 1 | V | 0 0 | opc | 0 | imm9 | idx | Rn | Rt | | |
2952 | * +----+-------+---+-----+-----+---+--------+-----+------+------+ | |
2953 | * | |
2954 | * idx = 01 -> post-indexed, 11 pre-indexed, 00 unscaled imm. (no writeback) | |
60510aed | 2955 | 10 -> unprivileged |
a5e94a9d AB |
2956 | * V = 0 -> non-vector |
2957 | * size: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64bit | |
2958 | * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32 | |
2959 | */ | |
cd694521 EI |
2960 | static void disas_ldst_reg_imm9(DisasContext *s, uint32_t insn, |
2961 | int opc, | |
2962 | int size, | |
2963 | int rt, | |
2964 | bool is_vector) | |
a5e94a9d | 2965 | { |
a5e94a9d AB |
2966 | int rn = extract32(insn, 5, 5); |
2967 | int imm9 = sextract32(insn, 12, 9); | |
a5e94a9d AB |
2968 | int idx = extract32(insn, 10, 2); |
2969 | bool is_signed = false; | |
2970 | bool is_store = false; | |
2971 | bool is_extended = false; | |
60510aed | 2972 | bool is_unpriv = (idx == 2); |
aaa1f954 | 2973 | bool iss_valid = !is_vector; |
a5e94a9d AB |
2974 | bool post_index; |
2975 | bool writeback; | |
0a405be2 | 2976 | int memidx; |
a5e94a9d | 2977 | |
3a471103 | 2978 | TCGv_i64 clean_addr, dirty_addr; |
a5e94a9d AB |
2979 | |
2980 | if (is_vector) { | |
2981 | size |= (opc & 2) << 1; | |
60510aed | 2982 | if (size > 4 || is_unpriv) { |
a5e94a9d AB |
2983 | unallocated_encoding(s); |
2984 | return; | |
2985 | } | |
2986 | is_store = ((opc & 1) == 0); | |
8c6afa6a PM |
2987 | if (!fp_access_check(s)) { |
2988 | return; | |
2989 | } | |
a5e94a9d AB |
2990 | } else { |
2991 | if (size == 3 && opc == 2) { | |
2992 | /* PRFM - prefetch */ | |
a80c4256 | 2993 | if (idx != 0) { |
60510aed PM |
2994 | unallocated_encoding(s); |
2995 | return; | |
2996 | } | |
a5e94a9d AB |
2997 | return; |
2998 | } | |
2999 | if (opc == 3 && size > 1) { | |
3000 | unallocated_encoding(s); | |
3001 | return; | |
3002 | } | |
3003 | is_store = (opc == 0); | |
026a19c3 EI |
3004 | is_signed = extract32(opc, 1, 1); |
3005 | is_extended = (size < 3) && extract32(opc, 0, 1); | |
a5e94a9d AB |
3006 | } |
3007 | ||
3008 | switch (idx) { | |
3009 | case 0: | |
60510aed | 3010 | case 2: |
a5e94a9d AB |
3011 | post_index = false; |
3012 | writeback = false; | |
3013 | break; | |
3014 | case 1: | |
3015 | post_index = true; | |
3016 | writeback = true; | |
3017 | break; | |
3018 | case 3: | |
3019 | post_index = false; | |
3020 | writeback = true; | |
3021 | break; | |
5ca66278 EC |
3022 | default: |
3023 | g_assert_not_reached(); | |
a5e94a9d AB |
3024 | } |
3025 | ||
3026 | if (rn == 31) { | |
3027 | gen_check_sp_alignment(s); | |
3028 | } | |
a5e94a9d | 3029 | |
3a471103 | 3030 | dirty_addr = read_cpu_reg_sp(s, rn, 1); |
a5e94a9d | 3031 | if (!post_index) { |
3a471103 | 3032 | tcg_gen_addi_i64(dirty_addr, dirty_addr, imm9); |
a5e94a9d | 3033 | } |
0a405be2 RH |
3034 | |
3035 | memidx = is_unpriv ? get_a64_user_mem_index(s) : get_mem_index(s); | |
3036 | clean_addr = gen_mte_check1_mmuidx(s, dirty_addr, is_store, | |
3037 | writeback || rn != 31, | |
3038 | size, is_unpriv, memidx); | |
a5e94a9d AB |
3039 | |
3040 | if (is_vector) { | |
3041 | if (is_store) { | |
3a471103 | 3042 | do_fp_st(s, rt, clean_addr, size); |
a5e94a9d | 3043 | } else { |
3a471103 | 3044 | do_fp_ld(s, rt, clean_addr, size); |
a5e94a9d AB |
3045 | } |
3046 | } else { | |
3047 | TCGv_i64 tcg_rt = cpu_reg(s, rt); | |
aaa1f954 | 3048 | bool iss_sf = disas_ldst_compute_iss_sf(size, is_signed, opc); |
60510aed | 3049 | |
a5e94a9d | 3050 | if (is_store) { |
3a471103 | 3051 | do_gpr_st_memidx(s, tcg_rt, clean_addr, size, memidx, |
aaa1f954 | 3052 | iss_valid, rt, iss_sf, false); |
a5e94a9d | 3053 | } else { |
3a471103 | 3054 | do_gpr_ld_memidx(s, tcg_rt, clean_addr, size, |
aaa1f954 EI |
3055 | is_signed, is_extended, memidx, |
3056 | iss_valid, rt, iss_sf, false); | |
a5e94a9d AB |
3057 | } |
3058 | } | |
3059 | ||
3060 | if (writeback) { | |
3061 | TCGv_i64 tcg_rn = cpu_reg_sp(s, rn); | |
3062 | if (post_index) { | |
3a471103 | 3063 | tcg_gen_addi_i64(dirty_addr, dirty_addr, imm9); |
a5e94a9d | 3064 | } |
3a471103 | 3065 | tcg_gen_mov_i64(tcg_rn, dirty_addr); |
a5e94a9d AB |
3066 | } |
3067 | } | |
3068 | ||
229b7a05 | 3069 | /* |
4ce31af4 | 3070 | * Load/store (register offset) |
229b7a05 AB |
3071 | * |
3072 | * 31 30 29 27 26 25 24 23 22 21 20 16 15 13 12 11 10 9 5 4 0 | |
3073 | * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+ | |
3074 | * |size| 1 1 1 | V | 0 0 | opc | 1 | Rm | opt | S| 1 0 | Rn | Rt | | |
3075 | * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+ | |
3076 | * | |
3077 | * For non-vector: | |
3078 | * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit | |
3079 | * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32 | |
3080 | * For vector: | |
3081 | * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated | |
3082 | * opc<0>: 0 -> store, 1 -> load | |
3083 | * V: 1 -> vector/simd | |
3084 | * opt: extend encoding (see DecodeRegExtend) | |
3085 | * S: if S=1 then scale (essentially index by sizeof(size)) | |
3086 | * Rt: register to transfer into/out of | |
3087 | * Rn: address register or SP for base | |
3088 | * Rm: offset register or ZR for offset | |
3089 | */ | |
cd694521 EI |
3090 | static void disas_ldst_reg_roffset(DisasContext *s, uint32_t insn, |
3091 | int opc, | |
3092 | int size, | |
3093 | int rt, | |
3094 | bool is_vector) | |
229b7a05 | 3095 | { |
229b7a05 AB |
3096 | int rn = extract32(insn, 5, 5); |
3097 | int shift = extract32(insn, 12, 1); | |
3098 | int rm = extract32(insn, 16, 5); | |
229b7a05 | 3099 | int opt = extract32(insn, 13, 3); |
229b7a05 AB |
3100 | bool is_signed = false; |
3101 | bool is_store = false; | |
3102 | bool is_extended = false; | |
229b7a05 | 3103 | |
3a471103 | 3104 | TCGv_i64 tcg_rm, clean_addr, dirty_addr; |
229b7a05 AB |
3105 | |
3106 | if (extract32(opt, 1, 1) == 0) { | |
3107 | unallocated_encoding(s); | |
3108 | return; | |
3109 | } | |
3110 | ||
3111 | if (is_vector) { | |
3112 | size |= (opc & 2) << 1; | |
3113 | if (size > 4) { | |
3114 | unallocated_encoding(s); | |
3115 | return; | |
3116 | } | |
3117 | is_store = !extract32(opc, 0, 1); | |
8c6afa6a PM |
3118 | if (!fp_access_check(s)) { |
3119 | return; | |
3120 | } | |
229b7a05 AB |
3121 | } else { |
3122 | if (size == 3 && opc == 2) { | |
3123 | /* PRFM - prefetch */ | |
3124 | return; | |
3125 | } | |
3126 | if (opc == 3 && size > 1) { | |
3127 | unallocated_encoding(s); | |
3128 | return; | |
3129 | } | |
3130 | is_store = (opc == 0); | |
3131 | is_signed = extract32(opc, 1, 1); | |
3132 | is_extended = (size < 3) && extract32(opc, 0, 1); | |
3133 | } | |
3134 | ||
3135 | if (rn == 31) { | |
3136 | gen_check_sp_alignment(s); | |
3137 | } | |
3a471103 | 3138 | dirty_addr = read_cpu_reg_sp(s, rn, 1); |
229b7a05 AB |
3139 | |
3140 | tcg_rm = read_cpu_reg(s, rm, 1); | |
3141 | ext_and_shift_reg(tcg_rm, tcg_rm, opt, shift ? size : 0); | |
3142 | ||
3a471103 | 3143 | tcg_gen_add_i64(dirty_addr, dirty_addr, tcg_rm); |
0a405be2 | 3144 | clean_addr = gen_mte_check1(s, dirty_addr, is_store, true, size); |
229b7a05 AB |
3145 | |
3146 | if (is_vector) { | |
3147 | if (is_store) { | |
3a471103 | 3148 | do_fp_st(s, rt, clean_addr, size); |
229b7a05 | 3149 | } else { |
3a471103 | 3150 | do_fp_ld(s, rt, clean_addr, size); |
229b7a05 AB |
3151 | } |
3152 | } else { | |
3153 | TCGv_i64 tcg_rt = cpu_reg(s, rt); | |
aaa1f954 | 3154 | bool iss_sf = disas_ldst_compute_iss_sf(size, is_signed, opc); |
229b7a05 | 3155 | if (is_store) { |
3a471103 | 3156 | do_gpr_st(s, tcg_rt, clean_addr, size, |
aaa1f954 | 3157 | true, rt, iss_sf, false); |
229b7a05 | 3158 | } else { |
3a471103 | 3159 | do_gpr_ld(s, tcg_rt, clean_addr, size, |
aaa1f954 EI |
3160 | is_signed, is_extended, |
3161 | true, rt, iss_sf, false); | |
229b7a05 AB |
3162 | } |
3163 | } | |
3164 | } | |
3165 | ||
d5612f10 | 3166 | /* |
4ce31af4 | 3167 | * Load/store (unsigned immediate) |
d5612f10 AB |
3168 | * |
3169 | * 31 30 29 27 26 25 24 23 22 21 10 9 5 | |
3170 | * +----+-------+---+-----+-----+------------+-------+------+ | |
3171 | * |size| 1 1 1 | V | 0 1 | opc | imm12 | Rn | Rt | | |
3172 | * +----+-------+---+-----+-----+------------+-------+------+ | |
3173 | * | |
3174 | * For non-vector: | |
3175 | * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit | |
3176 | * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32 | |
3177 | * For vector: | |
3178 | * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated | |
3179 | * opc<0>: 0 -> store, 1 -> load | |
3180 | * Rn: base address register (inc SP) | |
3181 | * Rt: target register | |
3182 | */ | |
cd694521 EI |
3183 | static void disas_ldst_reg_unsigned_imm(DisasContext *s, uint32_t insn, |
3184 | int opc, | |
3185 | int size, | |
3186 | int rt, | |
3187 | bool is_vector) | |
d5612f10 | 3188 | { |
d5612f10 AB |
3189 | int rn = extract32(insn, 5, 5); |
3190 | unsigned int imm12 = extract32(insn, 10, 12); | |
d5612f10 AB |
3191 | unsigned int offset; |
3192 | ||
3a471103 | 3193 | TCGv_i64 clean_addr, dirty_addr; |
d5612f10 AB |
3194 | |
3195 | bool is_store; | |
3196 | bool is_signed = false; | |
3197 | bool is_extended = false; | |
3198 | ||
3199 | if (is_vector) { | |
3200 | size |= (opc & 2) << 1; | |
3201 | if (size > 4) { | |
3202 | unallocated_encoding(s); | |
3203 | return; | |
3204 | } | |
3205 | is_store = !extract32(opc, 0, 1); | |
8c6afa6a PM |
3206 | if (!fp_access_check(s)) { |
3207 | return; | |
3208 | } | |
d5612f10 AB |
3209 | } else { |
3210 | if (size == 3 && opc == 2) { | |
3211 | /* PRFM - prefetch */ | |
3212 | return; | |
3213 | } | |
3214 | if (opc == 3 && size > 1) { | |
3215 | unallocated_encoding(s); | |
3216 | return; | |
3217 | } | |
3218 | is_store = (opc == 0); | |
3219 | is_signed = extract32(opc, 1, 1); | |
3220 | is_extended = (size < 3) && extract32(opc, 0, 1); | |
3221 | } | |
3222 | ||
3223 | if (rn == 31) { | |
3224 | gen_check_sp_alignment(s); | |
3225 | } | |
3a471103 | 3226 | dirty_addr = read_cpu_reg_sp(s, rn, 1); |
d5612f10 | 3227 | offset = imm12 << size; |
3a471103 | 3228 | tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); |
0a405be2 | 3229 | clean_addr = gen_mte_check1(s, dirty_addr, is_store, rn != 31, size); |
d5612f10 AB |
3230 | |
3231 | if (is_vector) { | |
3232 | if (is_store) { | |
3a471103 | 3233 | do_fp_st(s, rt, clean_addr, size); |
d5612f10 | 3234 | } else { |
3a471103 | 3235 | do_fp_ld(s, rt, clean_addr, size); |
d5612f10 AB |
3236 | } |
3237 | } else { | |
3238 | TCGv_i64 tcg_rt = cpu_reg(s, rt); | |
aaa1f954 | 3239 | bool iss_sf = disas_ldst_compute_iss_sf(size, is_signed, opc); |
d5612f10 | 3240 | if (is_store) { |
3a471103 | 3241 | do_gpr_st(s, tcg_rt, clean_addr, size, |
aaa1f954 | 3242 | true, rt, iss_sf, false); |
d5612f10 | 3243 | } else { |
3a471103 | 3244 | do_gpr_ld(s, tcg_rt, clean_addr, size, is_signed, is_extended, |
aaa1f954 | 3245 | true, rt, iss_sf, false); |
d5612f10 AB |
3246 | } |
3247 | } | |
3248 | } | |
3249 | ||
68412d2e RH |
3250 | /* Atomic memory operations |
3251 | * | |
3252 | * 31 30 27 26 24 22 21 16 15 12 10 5 0 | |
3253 | * +------+-------+---+-----+-----+---+----+----+-----+-----+----+-----+ | |
3254 | * | size | 1 1 1 | V | 0 0 | A R | 1 | Rs | o3 | opc | 0 0 | Rn | Rt | | |
3255 | * +------+-------+---+-----+-----+--------+----+-----+-----+----+-----+ | |
3256 | * | |
3257 | * Rt: the result register | |
3258 | * Rn: base address or SP | |
3259 | * Rs: the source register for the operation | |
3260 | * V: vector flag (always 0 as of v8.3) | |
3261 | * A: acquire flag | |
3262 | * R: release flag | |
3263 | */ | |
3264 | static void disas_ldst_atomic(DisasContext *s, uint32_t insn, | |
3265 | int size, int rt, bool is_vector) | |
3266 | { | |
3267 | int rs = extract32(insn, 16, 5); | |
3268 | int rn = extract32(insn, 5, 5); | |
3269 | int o3_opc = extract32(insn, 12, 4); | |
2677cf9f PM |
3270 | bool r = extract32(insn, 22, 1); |
3271 | bool a = extract32(insn, 23, 1); | |
3a471103 | 3272 | TCGv_i64 tcg_rs, clean_addr; |
74608ea4 | 3273 | AtomicThreeOpFn *fn; |
68412d2e | 3274 | |
962fcbf2 | 3275 | if (is_vector || !dc_isar_feature(aa64_atomics, s)) { |
68412d2e RH |
3276 | unallocated_encoding(s); |
3277 | return; | |
3278 | } | |
3279 | switch (o3_opc) { | |
3280 | case 000: /* LDADD */ | |
74608ea4 RH |
3281 | fn = tcg_gen_atomic_fetch_add_i64; |
3282 | break; | |
68412d2e | 3283 | case 001: /* LDCLR */ |
74608ea4 RH |
3284 | fn = tcg_gen_atomic_fetch_and_i64; |
3285 | break; | |
68412d2e | 3286 | case 002: /* LDEOR */ |
74608ea4 RH |
3287 | fn = tcg_gen_atomic_fetch_xor_i64; |
3288 | break; | |
68412d2e | 3289 | case 003: /* LDSET */ |
74608ea4 RH |
3290 | fn = tcg_gen_atomic_fetch_or_i64; |
3291 | break; | |
68412d2e | 3292 | case 004: /* LDSMAX */ |
74608ea4 RH |
3293 | fn = tcg_gen_atomic_fetch_smax_i64; |
3294 | break; | |
68412d2e | 3295 | case 005: /* LDSMIN */ |
74608ea4 RH |
3296 | fn = tcg_gen_atomic_fetch_smin_i64; |
3297 | break; | |
68412d2e | 3298 | case 006: /* LDUMAX */ |
74608ea4 RH |
3299 | fn = tcg_gen_atomic_fetch_umax_i64; |
3300 | break; | |
68412d2e | 3301 | case 007: /* LDUMIN */ |
74608ea4 RH |
3302 | fn = tcg_gen_atomic_fetch_umin_i64; |
3303 | break; | |
68412d2e | 3304 | case 010: /* SWP */ |
74608ea4 RH |
3305 | fn = tcg_gen_atomic_xchg_i64; |
3306 | break; | |
2677cf9f PM |
3307 | case 014: /* LDAPR, LDAPRH, LDAPRB */ |
3308 | if (!dc_isar_feature(aa64_rcpc_8_3, s) || | |
3309 | rs != 31 || a != 1 || r != 0) { | |
3310 | unallocated_encoding(s); | |
3311 | return; | |
3312 | } | |
3313 | break; | |
68412d2e RH |
3314 | default: |
3315 | unallocated_encoding(s); | |
3316 | return; | |
3317 | } | |
68412d2e | 3318 | |
74608ea4 RH |
3319 | if (rn == 31) { |
3320 | gen_check_sp_alignment(s); | |
3321 | } | |
0a405be2 | 3322 | clean_addr = gen_mte_check1(s, cpu_reg_sp(s, rn), false, rn != 31, size); |
2677cf9f PM |
3323 | |
3324 | if (o3_opc == 014) { | |
3325 | /* | |
3326 | * LDAPR* are a special case because they are a simple load, not a | |
3327 | * fetch-and-do-something op. | |
3328 | * The architectural consistency requirements here are weaker than | |
3329 | * full load-acquire (we only need "load-acquire processor consistent"), | |
3330 | * but we choose to implement them as full LDAQ. | |
3331 | */ | |
3332 | do_gpr_ld(s, cpu_reg(s, rt), clean_addr, size, false, false, | |
3333 | true, rt, disas_ldst_compute_iss_sf(size, false, 0), true); | |
3334 | tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); | |
3335 | return; | |
3336 | } | |
3337 | ||
74608ea4 RH |
3338 | tcg_rs = read_cpu_reg(s, rs, true); |
3339 | ||
3340 | if (o3_opc == 1) { /* LDCLR */ | |
3341 | tcg_gen_not_i64(tcg_rs, tcg_rs); | |
3342 | } | |
3343 | ||
3344 | /* The tcg atomic primitives are all full barriers. Therefore we | |
3345 | * can ignore the Acquire and Release bits of this instruction. | |
3346 | */ | |
3a471103 | 3347 | fn(cpu_reg(s, rt), clean_addr, tcg_rs, get_mem_index(s), |
74608ea4 | 3348 | s->be_data | size | MO_ALIGN); |
68412d2e RH |
3349 | } |
3350 | ||
bd889f48 RH |
3351 | /* |
3352 | * PAC memory operations | |
3353 | * | |
3354 | * 31 30 27 26 24 22 21 12 11 10 5 0 | |
3355 | * +------+-------+---+-----+-----+---+--------+---+---+----+-----+ | |
3356 | * | size | 1 1 1 | V | 0 0 | M S | 1 | imm9 | W | 1 | Rn | Rt | | |
3357 | * +------+-------+---+-----+-----+---+--------+---+---+----+-----+ | |
3358 | * | |
3359 | * Rt: the result register | |
3360 | * Rn: base address or SP | |
3361 | * V: vector flag (always 0 as of v8.3) | |
3362 | * M: clear for key DA, set for key DB | |
3363 | * W: pre-indexing flag | |
3364 | * S: sign for imm9. | |
3365 | */ | |
3366 | static void disas_ldst_pac(DisasContext *s, uint32_t insn, | |
3367 | int size, int rt, bool is_vector) | |
3368 | { | |
3369 | int rn = extract32(insn, 5, 5); | |
3370 | bool is_wback = extract32(insn, 11, 1); | |
3371 | bool use_key_a = !extract32(insn, 23, 1); | |
3372 | int offset; | |
3a471103 | 3373 | TCGv_i64 clean_addr, dirty_addr, tcg_rt; |
bd889f48 RH |
3374 | |
3375 | if (size != 3 || is_vector || !dc_isar_feature(aa64_pauth, s)) { | |
3376 | unallocated_encoding(s); | |
3377 | return; | |
3378 | } | |
3379 | ||
3380 | if (rn == 31) { | |
3381 | gen_check_sp_alignment(s); | |
3382 | } | |
3a471103 | 3383 | dirty_addr = read_cpu_reg_sp(s, rn, 1); |
bd889f48 RH |
3384 | |
3385 | if (s->pauth_active) { | |
3386 | if (use_key_a) { | |
3a471103 | 3387 | gen_helper_autda(dirty_addr, cpu_env, dirty_addr, cpu_X[31]); |
bd889f48 | 3388 | } else { |
3a471103 | 3389 | gen_helper_autdb(dirty_addr, cpu_env, dirty_addr, cpu_X[31]); |
bd889f48 RH |
3390 | } |
3391 | } | |
3392 | ||
3393 | /* Form the 10-bit signed, scaled offset. */ | |
3394 | offset = (extract32(insn, 22, 1) << 9) | extract32(insn, 12, 9); | |
3395 | offset = sextract32(offset << size, 0, 10 + size); | |
3a471103 | 3396 | tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); |
bd889f48 | 3397 | |
3a471103 | 3398 | /* Note that "clean" and "dirty" here refer to TBI not PAC. */ |
0a405be2 RH |
3399 | clean_addr = gen_mte_check1(s, dirty_addr, false, |
3400 | is_wback || rn != 31, size); | |
bd889f48 | 3401 | |
3a471103 RH |
3402 | tcg_rt = cpu_reg(s, rt); |
3403 | do_gpr_ld(s, tcg_rt, clean_addr, size, /* is_signed */ false, | |
bd889f48 RH |
3404 | /* extend */ false, /* iss_valid */ !is_wback, |
3405 | /* iss_srt */ rt, /* iss_sf */ true, /* iss_ar */ false); | |
3406 | ||
3407 | if (is_wback) { | |
3a471103 | 3408 | tcg_gen_mov_i64(cpu_reg_sp(s, rn), dirty_addr); |
bd889f48 RH |
3409 | } |
3410 | } | |
3411 | ||
a1229109 PM |
3412 | /* |
3413 | * LDAPR/STLR (unscaled immediate) | |
3414 | * | |
3415 | * 31 30 24 22 21 12 10 5 0 | |
3416 | * +------+-------------+-----+---+--------+-----+----+-----+ | |
3417 | * | size | 0 1 1 0 0 1 | opc | 0 | imm9 | 0 0 | Rn | Rt | | |
3418 | * +------+-------------+-----+---+--------+-----+----+-----+ | |
3419 | * | |
3420 | * Rt: source or destination register | |
3421 | * Rn: base register | |
3422 | * imm9: unscaled immediate offset | |
3423 | * opc: 00: STLUR*, 01/10/11: various LDAPUR* | |
3424 | * size: size of load/store | |
3425 | */ | |
3426 | static void disas_ldst_ldapr_stlr(DisasContext *s, uint32_t insn) | |
3427 | { | |
3428 | int rt = extract32(insn, 0, 5); | |
3429 | int rn = extract32(insn, 5, 5); | |
3430 | int offset = sextract32(insn, 12, 9); | |
3431 | int opc = extract32(insn, 22, 2); | |
3432 | int size = extract32(insn, 30, 2); | |
3433 | TCGv_i64 clean_addr, dirty_addr; | |
3434 | bool is_store = false; | |
3435 | bool is_signed = false; | |
3436 | bool extend = false; | |
3437 | bool iss_sf; | |
3438 | ||
3439 | if (!dc_isar_feature(aa64_rcpc_8_4, s)) { | |
3440 | unallocated_encoding(s); | |
3441 | return; | |
3442 | } | |
3443 | ||
3444 | switch (opc) { | |
3445 | case 0: /* STLURB */ | |
3446 | is_store = true; | |
3447 | break; | |
3448 | case 1: /* LDAPUR* */ | |
3449 | break; | |
3450 | case 2: /* LDAPURS* 64-bit variant */ | |
3451 | if (size == 3) { | |
3452 | unallocated_encoding(s); | |
3453 | return; | |
3454 | } | |
3455 | is_signed = true; | |
3456 | break; | |
3457 | case 3: /* LDAPURS* 32-bit variant */ | |
3458 | if (size > 1) { | |
3459 | unallocated_encoding(s); | |
3460 | return; | |
3461 | } | |
3462 | is_signed = true; | |
3463 | extend = true; /* zero-extend 32->64 after signed load */ | |
3464 | break; | |
3465 | default: | |
3466 | g_assert_not_reached(); | |
3467 | } | |
3468 | ||
3469 | iss_sf = disas_ldst_compute_iss_sf(size, is_signed, opc); | |
3470 | ||
3471 | if (rn == 31) { | |
3472 | gen_check_sp_alignment(s); | |
3473 | } | |
3474 | ||
3475 | dirty_addr = read_cpu_reg_sp(s, rn, 1); | |
3476 | tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); | |
3477 | clean_addr = clean_data_tbi(s, dirty_addr); | |
3478 | ||
3479 | if (is_store) { | |
3480 | /* Store-Release semantics */ | |
3481 | tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); | |
3482 | do_gpr_st(s, cpu_reg(s, rt), clean_addr, size, true, rt, iss_sf, true); | |
3483 | } else { | |
3484 | /* | |
3485 | * Load-AcquirePC semantics; we implement as the slightly more | |
3486 | * restrictive Load-Acquire. | |
3487 | */ | |
3488 | do_gpr_ld(s, cpu_reg(s, rt), clean_addr, size, is_signed, extend, | |
3489 | true, rt, iss_sf, true); | |
3490 | tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); | |
3491 | } | |
3492 | } | |
3493 | ||
ad7ee8a2 CF |
3494 | /* Load/store register (all forms) */ |
3495 | static void disas_ldst_reg(DisasContext *s, uint32_t insn) | |
3496 | { | |
cd694521 EI |
3497 | int rt = extract32(insn, 0, 5); |
3498 | int opc = extract32(insn, 22, 2); | |
3499 | bool is_vector = extract32(insn, 26, 1); | |
3500 | int size = extract32(insn, 30, 2); | |
3501 | ||
d5612f10 AB |
3502 | switch (extract32(insn, 24, 2)) { |
3503 | case 0: | |
68412d2e | 3504 | if (extract32(insn, 21, 1) == 0) { |
60510aed PM |
3505 | /* Load/store register (unscaled immediate) |
3506 | * Load/store immediate pre/post-indexed | |
3507 | * Load/store register unprivileged | |
3508 | */ | |
cd694521 | 3509 | disas_ldst_reg_imm9(s, insn, opc, size, rt, is_vector); |
68412d2e RH |
3510 | return; |
3511 | } | |
3512 | switch (extract32(insn, 10, 2)) { | |
3513 | case 0: | |
3514 | disas_ldst_atomic(s, insn, size, rt, is_vector); | |
3515 | return; | |
3516 | case 2: | |
3517 | disas_ldst_reg_roffset(s, insn, opc, size, rt, is_vector); | |
3518 | return; | |
bd889f48 RH |
3519 | default: |
3520 | disas_ldst_pac(s, insn, size, rt, is_vector); | |
3521 | return; | |
229b7a05 | 3522 | } |
d5612f10 AB |
3523 | break; |
3524 | case 1: | |
cd694521 | 3525 | disas_ldst_reg_unsigned_imm(s, insn, opc, size, rt, is_vector); |
68412d2e | 3526 | return; |
d5612f10 | 3527 | } |
68412d2e | 3528 | unallocated_encoding(s); |
ad7ee8a2 CF |
3529 | } |
3530 | ||
4ce31af4 | 3531 | /* AdvSIMD load/store multiple structures |
72430bf5 AB |
3532 | * |
3533 | * 31 30 29 23 22 21 16 15 12 11 10 9 5 4 0 | |
3534 | * +---+---+---------------+---+-------------+--------+------+------+------+ | |
3535 | * | 0 | Q | 0 0 1 1 0 0 0 | L | 0 0 0 0 0 0 | opcode | size | Rn | Rt | | |
3536 | * +---+---+---------------+---+-------------+--------+------+------+------+ | |
3537 | * | |
4ce31af4 | 3538 | * AdvSIMD load/store multiple structures (post-indexed) |
72430bf5 AB |
3539 | * |
3540 | * 31 30 29 23 22 21 20 16 15 12 11 10 9 5 4 0 | |
3541 | * +---+---+---------------+---+---+---------+--------+------+------+------+ | |
3542 | * | 0 | Q | 0 0 1 1 0 0 1 | L | 0 | Rm | opcode | size | Rn | Rt | | |
3543 | * +---+---+---------------+---+---+---------+--------+------+------+------+ | |
3544 | * | |
3545 | * Rt: first (or only) SIMD&FP register to be transferred | |
3546 | * Rn: base address or SP | |
3547 | * Rm (post-index only): post-index register (when !31) or size dependent #imm | |
3548 | */ | |
ad7ee8a2 CF |
3549 | static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn) |
3550 | { | |
72430bf5 AB |
3551 | int rt = extract32(insn, 0, 5); |
3552 | int rn = extract32(insn, 5, 5); | |
e1f22081 | 3553 | int rm = extract32(insn, 16, 5); |
72430bf5 AB |
3554 | int size = extract32(insn, 10, 2); |
3555 | int opcode = extract32(insn, 12, 4); | |
3556 | bool is_store = !extract32(insn, 22, 1); | |
3557 | bool is_postidx = extract32(insn, 23, 1); | |
3558 | bool is_q = extract32(insn, 30, 1); | |
3a471103 | 3559 | TCGv_i64 clean_addr, tcg_rn, tcg_ebytes; |
14776ab5 | 3560 | MemOp endian = s->be_data; |
72430bf5 | 3561 | |
73ceeb00 | 3562 | int total; /* total bytes */ |
87f9a7f0 | 3563 | int elements; /* elements per vector */ |
72430bf5 AB |
3564 | int rpt; /* num iterations */ |
3565 | int selem; /* structure elements */ | |
3566 | int r; | |
3567 | ||
3568 | if (extract32(insn, 31, 1) || extract32(insn, 21, 1)) { | |
3569 | unallocated_encoding(s); | |
3570 | return; | |
3571 | } | |
3572 | ||
e1f22081 PM |
3573 | if (!is_postidx && rm != 0) { |
3574 | unallocated_encoding(s); | |
3575 | return; | |
3576 | } | |
3577 | ||
72430bf5 AB |
3578 | /* From the shared decode logic */ |
3579 | switch (opcode) { | |
3580 | case 0x0: | |
3581 | rpt = 1; | |
3582 | selem = 4; | |
3583 | break; | |
3584 | case 0x2: | |
3585 | rpt = 4; | |
3586 | selem = 1; | |
3587 | break; | |
3588 | case 0x4: | |
3589 | rpt = 1; | |
3590 | selem = 3; | |
3591 | break; | |
3592 | case 0x6: | |
3593 | rpt = 3; | |
3594 | selem = 1; | |
3595 | break; | |
3596 | case 0x7: | |
3597 | rpt = 1; | |
3598 | selem = 1; | |
3599 | break; | |
3600 | case 0x8: | |
3601 | rpt = 1; | |
3602 | selem = 2; | |
3603 | break; | |
3604 | case 0xa: | |
3605 | rpt = 2; | |
3606 | selem = 1; | |
3607 | break; | |
3608 | default: | |
3609 | unallocated_encoding(s); | |
3610 | return; | |
3611 | } | |
3612 | ||
3613 | if (size == 3 && !is_q && selem != 1) { | |
3614 | /* reserved */ | |
3615 | unallocated_encoding(s); | |
3616 | return; | |
3617 | } | |
3618 | ||
8c6afa6a PM |
3619 | if (!fp_access_check(s)) { |
3620 | return; | |
3621 | } | |
3622 | ||
72430bf5 AB |
3623 | if (rn == 31) { |
3624 | gen_check_sp_alignment(s); | |
3625 | } | |
3626 | ||
87f9a7f0 RH |
3627 | /* For our purposes, bytes are always little-endian. */ |
3628 | if (size == 0) { | |
3629 | endian = MO_LE; | |
3630 | } | |
3631 | ||
73ceeb00 RH |
3632 | total = rpt * selem * (is_q ? 16 : 8); |
3633 | tcg_rn = cpu_reg_sp(s, rn); | |
3634 | ||
3635 | /* | |
3636 | * Issue the MTE check vs the logical repeat count, before we | |
3637 | * promote consecutive little-endian elements below. | |
3638 | */ | |
3639 | clean_addr = gen_mte_checkN(s, tcg_rn, is_store, is_postidx || rn != 31, | |
3640 | size, total); | |
3641 | ||
3642 | /* | |
3643 | * Consecutive little-endian elements from a single register | |
87f9a7f0 RH |
3644 | * can be promoted to a larger little-endian operation. |
3645 | */ | |
3646 | if (selem == 1 && endian == MO_LE) { | |
3647 | size = 3; | |
3648 | } | |
73ceeb00 | 3649 | elements = (is_q ? 16 : 8) >> size; |
72430bf5 | 3650 | |
73ceeb00 | 3651 | tcg_ebytes = tcg_const_i64(1 << size); |
72430bf5 AB |
3652 | for (r = 0; r < rpt; r++) { |
3653 | int e; | |
3654 | for (e = 0; e < elements; e++) { | |
72430bf5 AB |
3655 | int xs; |
3656 | for (xs = 0; xs < selem; xs++) { | |
87f9a7f0 | 3657 | int tt = (rt + r + xs) % 32; |
72430bf5 | 3658 | if (is_store) { |
3a471103 | 3659 | do_vec_st(s, tt, e, clean_addr, size, endian); |
72430bf5 | 3660 | } else { |
3a471103 | 3661 | do_vec_ld(s, tt, e, clean_addr, size, endian); |
72430bf5 | 3662 | } |
3a471103 | 3663 | tcg_gen_add_i64(clean_addr, clean_addr, tcg_ebytes); |
72430bf5 AB |
3664 | } |
3665 | } | |
3666 | } | |
3a471103 | 3667 | tcg_temp_free_i64(tcg_ebytes); |
72430bf5 | 3668 | |
87f9a7f0 RH |
3669 | if (!is_store) { |
3670 | /* For non-quad operations, setting a slice of the low | |
3671 | * 64 bits of the register clears the high 64 bits (in | |
3672 | * the ARM ARM pseudocode this is implicit in the fact | |
3673 | * that 'rval' is a 64 bit wide variable). | |
3674 | * For quad operations, we might still need to zero the | |
3675 | * high bits of SVE. | |
3676 | */ | |
3677 | for (r = 0; r < rpt * selem; r++) { | |
3678 | int tt = (rt + r) % 32; | |
3679 | clear_vec_high(s, is_q, tt); | |
3680 | } | |
3681 | } | |
3682 | ||
72430bf5 | 3683 | if (is_postidx) { |
72430bf5 | 3684 | if (rm == 31) { |
73ceeb00 | 3685 | tcg_gen_addi_i64(tcg_rn, tcg_rn, total); |
72430bf5 AB |
3686 | } else { |
3687 | tcg_gen_add_i64(tcg_rn, tcg_rn, cpu_reg(s, rm)); | |
3688 | } | |
3689 | } | |
ad7ee8a2 CF |
3690 | } |
3691 | ||
4ce31af4 | 3692 | /* AdvSIMD load/store single structure |
df54e47d PM |
3693 | * |
3694 | * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0 | |
3695 | * +---+---+---------------+-----+-----------+-----+---+------+------+------+ | |
3696 | * | 0 | Q | 0 0 1 1 0 1 0 | L R | 0 0 0 0 0 | opc | S | size | Rn | Rt | | |
3697 | * +---+---+---------------+-----+-----------+-----+---+------+------+------+ | |
3698 | * | |
4ce31af4 | 3699 | * AdvSIMD load/store single structure (post-indexed) |
df54e47d PM |
3700 | * |
3701 | * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0 | |
3702 | * +---+---+---------------+-----+-----------+-----+---+------+------+------+ | |
3703 | * | 0 | Q | 0 0 1 1 0 1 1 | L R | Rm | opc | S | size | Rn | Rt | | |
3704 | * +---+---+---------------+-----+-----------+-----+---+------+------+------+ | |
3705 | * | |
3706 | * Rt: first (or only) SIMD&FP register to be transferred | |
3707 | * Rn: base address or SP | |
3708 | * Rm (post-index only): post-index register (when !31) or size dependent #imm | |
3709 | * index = encoded in Q:S:size dependent on size | |
3710 | * | |
3711 | * lane_size = encoded in R, opc | |
3712 | * transfer width = encoded in opc, S, size | |
3713 | */ | |
ad7ee8a2 CF |
3714 | static void disas_ldst_single_struct(DisasContext *s, uint32_t insn) |
3715 | { | |
df54e47d PM |
3716 | int rt = extract32(insn, 0, 5); |
3717 | int rn = extract32(insn, 5, 5); | |
9c72b68a | 3718 | int rm = extract32(insn, 16, 5); |
df54e47d PM |
3719 | int size = extract32(insn, 10, 2); |
3720 | int S = extract32(insn, 12, 1); | |
3721 | int opc = extract32(insn, 13, 3); | |
3722 | int R = extract32(insn, 21, 1); | |
3723 | int is_load = extract32(insn, 22, 1); | |
3724 | int is_postidx = extract32(insn, 23, 1); | |
3725 | int is_q = extract32(insn, 30, 1); | |
3726 | ||
3727 | int scale = extract32(opc, 1, 2); | |
3728 | int selem = (extract32(opc, 0, 1) << 1 | R) + 1; | |
3729 | bool replicate = false; | |
3730 | int index = is_q << 3 | S << 2 | size; | |
73ceeb00 | 3731 | int xs, total; |
3a471103 | 3732 | TCGv_i64 clean_addr, tcg_rn, tcg_ebytes; |
df54e47d | 3733 | |
9c72b68a PM |
3734 | if (extract32(insn, 31, 1)) { |
3735 | unallocated_encoding(s); | |
3736 | return; | |
3737 | } | |
3738 | if (!is_postidx && rm != 0) { | |
3739 | unallocated_encoding(s); | |
3740 | return; | |
3741 | } | |
3742 | ||
df54e47d PM |
3743 | switch (scale) { |
3744 | case 3: | |
3745 | if (!is_load || S) { | |
3746 | unallocated_encoding(s); | |
3747 | return; | |
3748 | } | |
3749 | scale = size; | |
3750 | replicate = true; | |
3751 | break; | |
3752 | case 0: | |
3753 | break; | |
3754 | case 1: | |
3755 | if (extract32(size, 0, 1)) { | |
3756 | unallocated_encoding(s); | |
3757 | return; | |
3758 | } | |
3759 | index >>= 1; | |
3760 | break; | |
3761 | case 2: | |
3762 | if (extract32(size, 1, 1)) { | |
3763 | unallocated_encoding(s); | |
3764 | return; | |
3765 | } | |
3766 | if (!extract32(size, 0, 1)) { | |
3767 | index >>= 2; | |
3768 | } else { | |
3769 | if (S) { | |
3770 | unallocated_encoding(s); | |
3771 | return; | |
3772 | } | |
3773 | index >>= 3; | |
3774 | scale = 3; | |
3775 | } | |
3776 | break; | |
3777 | default: | |
3778 | g_assert_not_reached(); | |
3779 | } | |
3780 | ||
8c6afa6a PM |
3781 | if (!fp_access_check(s)) { |
3782 | return; | |
3783 | } | |
3784 | ||
df54e47d PM |
3785 | if (rn == 31) { |
3786 | gen_check_sp_alignment(s); | |
3787 | } | |
3788 | ||
73ceeb00 | 3789 | total = selem << scale; |
df54e47d | 3790 | tcg_rn = cpu_reg_sp(s, rn); |
df54e47d | 3791 | |
73ceeb00 RH |
3792 | clean_addr = gen_mte_checkN(s, tcg_rn, !is_load, is_postidx || rn != 31, |
3793 | scale, total); | |
3794 | ||
3795 | tcg_ebytes = tcg_const_i64(1 << scale); | |
df54e47d PM |
3796 | for (xs = 0; xs < selem; xs++) { |
3797 | if (replicate) { | |
3798 | /* Load and replicate to all elements */ | |
df54e47d PM |
3799 | TCGv_i64 tcg_tmp = tcg_temp_new_i64(); |
3800 | ||
3a471103 | 3801 | tcg_gen_qemu_ld_i64(tcg_tmp, clean_addr, |
aa6489da | 3802 | get_mem_index(s), s->be_data + scale); |
10e0b33c RH |
3803 | tcg_gen_gvec_dup_i64(scale, vec_full_reg_offset(s, rt), |
3804 | (is_q + 1) * 8, vec_full_reg_size(s), | |
3805 | tcg_tmp); | |
df54e47d PM |
3806 | tcg_temp_free_i64(tcg_tmp); |
3807 | } else { | |
3808 | /* Load/store one element per register */ | |
3809 | if (is_load) { | |
3a471103 | 3810 | do_vec_ld(s, rt, index, clean_addr, scale, s->be_data); |
df54e47d | 3811 | } else { |
3a471103 | 3812 | do_vec_st(s, rt, index, clean_addr, scale, s->be_data); |
df54e47d PM |
3813 | } |
3814 | } | |
3a471103 | 3815 | tcg_gen_add_i64(clean_addr, clean_addr, tcg_ebytes); |
df54e47d PM |
3816 | rt = (rt + 1) % 32; |
3817 | } | |
3a471103 | 3818 | tcg_temp_free_i64(tcg_ebytes); |
df54e47d PM |
3819 | |
3820 | if (is_postidx) { | |
df54e47d | 3821 | if (rm == 31) { |
73ceeb00 | 3822 | tcg_gen_addi_i64(tcg_rn, tcg_rn, total); |
df54e47d PM |
3823 | } else { |
3824 | tcg_gen_add_i64(tcg_rn, tcg_rn, cpu_reg(s, rm)); | |
3825 | } | |
3826 | } | |
ad7ee8a2 CF |
3827 | } |
3828 | ||
c15294c1 RH |
3829 | /* |
3830 | * Load/Store memory tags | |
3831 | * | |
3832 | * 31 30 29 24 22 21 12 10 5 0 | |
3833 | * +-----+-------------+-----+---+------+-----+------+------+ | |
3834 | * | 1 1 | 0 1 1 0 0 1 | op1 | 1 | imm9 | op2 | Rn | Rt | | |
3835 | * +-----+-------------+-----+---+------+-----+------+------+ | |
3836 | */ | |
3837 | static void disas_ldst_tag(DisasContext *s, uint32_t insn) | |
3838 | { | |
3839 | int rt = extract32(insn, 0, 5); | |
3840 | int rn = extract32(insn, 5, 5); | |
3841 | uint64_t offset = sextract64(insn, 12, 9) << LOG2_TAG_GRANULE; | |
3842 | int op2 = extract32(insn, 10, 2); | |
3843 | int op1 = extract32(insn, 22, 2); | |
5f716a82 | 3844 | bool is_load = false, is_pair = false, is_zero = false, is_mult = false; |
c15294c1 RH |
3845 | int index = 0; |
3846 | TCGv_i64 addr, clean_addr, tcg_rt; | |
3847 | ||
3848 | /* We checked insn bits [29:24,21] in the caller. */ | |
3849 | if (extract32(insn, 30, 2) != 3) { | |
3850 | goto do_unallocated; | |
3851 | } | |
3852 | ||
3853 | /* | |
3854 | * @index is a tri-state variable which has 3 states: | |
3855 | * < 0 : post-index, writeback | |
3856 | * = 0 : signed offset | |
3857 | * > 0 : pre-index, writeback | |
3858 | */ | |
3859 | switch (op1) { | |
3860 | case 0: | |
3861 | if (op2 != 0) { | |
3862 | /* STG */ | |
3863 | index = op2 - 2; | |
5f716a82 RH |
3864 | } else { |
3865 | /* STZGM */ | |
3866 | if (s->current_el == 0 || offset != 0) { | |
3867 | goto do_unallocated; | |
3868 | } | |
3869 | is_mult = is_zero = true; | |
c15294c1 | 3870 | } |
5f716a82 | 3871 | break; |
c15294c1 RH |
3872 | case 1: |
3873 | if (op2 != 0) { | |
3874 | /* STZG */ | |
3875 | is_zero = true; | |
3876 | index = op2 - 2; | |
3877 | } else { | |
3878 | /* LDG */ | |
3879 | is_load = true; | |
3880 | } | |
3881 | break; | |
3882 | case 2: | |
3883 | if (op2 != 0) { | |
3884 | /* ST2G */ | |
3885 | is_pair = true; | |
3886 | index = op2 - 2; | |
5f716a82 RH |
3887 | } else { |
3888 | /* STGM */ | |
3889 | if (s->current_el == 0 || offset != 0) { | |
3890 | goto do_unallocated; | |
3891 | } | |
3892 | is_mult = true; | |
c15294c1 | 3893 | } |
5f716a82 | 3894 | break; |
c15294c1 RH |
3895 | case 3: |
3896 | if (op2 != 0) { | |
3897 | /* STZ2G */ | |
3898 | is_pair = is_zero = true; | |
3899 | index = op2 - 2; | |
5f716a82 RH |
3900 | } else { |
3901 | /* LDGM */ | |
3902 | if (s->current_el == 0 || offset != 0) { | |
3903 | goto do_unallocated; | |
3904 | } | |
3905 | is_mult = is_load = true; | |
c15294c1 | 3906 | } |
5f716a82 | 3907 | break; |
c15294c1 RH |
3908 | |
3909 | default: | |
3910 | do_unallocated: | |
3911 | unallocated_encoding(s); | |
3912 | return; | |
3913 | } | |
3914 | ||
5f716a82 RH |
3915 | if (is_mult |
3916 | ? !dc_isar_feature(aa64_mte, s) | |
3917 | : !dc_isar_feature(aa64_mte_insn_reg, s)) { | |
c15294c1 RH |
3918 | goto do_unallocated; |
3919 | } | |
3920 | ||
3921 | if (rn == 31) { | |
3922 | gen_check_sp_alignment(s); | |
3923 | } | |
3924 | ||
3925 | addr = read_cpu_reg_sp(s, rn, true); | |
3926 | if (index >= 0) { | |
3927 | /* pre-index or signed offset */ | |
3928 | tcg_gen_addi_i64(addr, addr, offset); | |
3929 | } | |
3930 | ||
5f716a82 RH |
3931 | if (is_mult) { |
3932 | tcg_rt = cpu_reg(s, rt); | |
3933 | ||
3934 | if (is_zero) { | |
3935 | int size = 4 << s->dcz_blocksize; | |
3936 | ||
3937 | if (s->ata) { | |
3938 | gen_helper_stzgm_tags(cpu_env, addr, tcg_rt); | |
3939 | } | |
3940 | /* | |
3941 | * The non-tags portion of STZGM is mostly like DC_ZVA, | |
3942 | * except the alignment happens before the access. | |
3943 | */ | |
3944 | clean_addr = clean_data_tbi(s, addr); | |
3945 | tcg_gen_andi_i64(clean_addr, clean_addr, -size); | |
3946 | gen_helper_dc_zva(cpu_env, clean_addr); | |
3947 | } else if (s->ata) { | |
3948 | if (is_load) { | |
3949 | gen_helper_ldgm(tcg_rt, cpu_env, addr); | |
3950 | } else { | |
3951 | gen_helper_stgm(cpu_env, addr, tcg_rt); | |
3952 | } | |
3953 | } else { | |
3954 | MMUAccessType acc = is_load ? MMU_DATA_LOAD : MMU_DATA_STORE; | |
3955 | int size = 4 << GMID_EL1_BS; | |
3956 | ||
3957 | clean_addr = clean_data_tbi(s, addr); | |
3958 | tcg_gen_andi_i64(clean_addr, clean_addr, -size); | |
3959 | gen_probe_access(s, clean_addr, acc, size); | |
3960 | ||
3961 | if (is_load) { | |
3962 | /* The result tags are zeros. */ | |
3963 | tcg_gen_movi_i64(tcg_rt, 0); | |
3964 | } | |
3965 | } | |
3966 | return; | |
3967 | } | |
3968 | ||
c15294c1 RH |
3969 | if (is_load) { |
3970 | tcg_gen_andi_i64(addr, addr, -TAG_GRANULE); | |
3971 | tcg_rt = cpu_reg(s, rt); | |
3972 | if (s->ata) { | |
3973 | gen_helper_ldg(tcg_rt, cpu_env, addr, tcg_rt); | |
3974 | } else { | |
3975 | clean_addr = clean_data_tbi(s, addr); | |
3976 | gen_probe_access(s, clean_addr, MMU_DATA_LOAD, MO_8); | |
3977 | gen_address_with_allocation_tag0(tcg_rt, addr); | |
3978 | } | |
3979 | } else { | |
3980 | tcg_rt = cpu_reg_sp(s, rt); | |
3981 | if (!s->ata) { | |
3982 | /* | |
3983 | * For STG and ST2G, we need to check alignment and probe memory. | |
3984 | * TODO: For STZG and STZ2G, we could rely on the stores below, | |
3985 | * at least for system mode; user-only won't enforce alignment. | |
3986 | */ | |
3987 | if (is_pair) { | |
3988 | gen_helper_st2g_stub(cpu_env, addr); | |
3989 | } else { | |
3990 | gen_helper_stg_stub(cpu_env, addr); | |
3991 | } | |
3992 | } else if (tb_cflags(s->base.tb) & CF_PARALLEL) { | |
3993 | if (is_pair) { | |
3994 | gen_helper_st2g_parallel(cpu_env, addr, tcg_rt); | |
3995 | } else { | |
3996 | gen_helper_stg_parallel(cpu_env, addr, tcg_rt); | |
3997 | } | |
3998 | } else { | |
3999 | if (is_pair) { | |
4000 | gen_helper_st2g(cpu_env, addr, tcg_rt); | |
4001 | } else { | |
4002 | gen_helper_stg(cpu_env, addr, tcg_rt); | |
4003 | } | |
4004 | } | |
4005 | } | |
4006 | ||
4007 | if (is_zero) { | |
4008 | TCGv_i64 clean_addr = clean_data_tbi(s, addr); | |
4009 | TCGv_i64 tcg_zero = tcg_const_i64(0); | |
4010 | int mem_index = get_mem_index(s); | |
4011 | int i, n = (1 + is_pair) << LOG2_TAG_GRANULE; | |
4012 | ||
4013 | tcg_gen_qemu_st_i64(tcg_zero, clean_addr, mem_index, | |
4014 | MO_Q | MO_ALIGN_16); | |
4015 | for (i = 8; i < n; i += 8) { | |
4016 | tcg_gen_addi_i64(clean_addr, clean_addr, 8); | |
4017 | tcg_gen_qemu_st_i64(tcg_zero, clean_addr, mem_index, MO_Q); | |
4018 | } | |
4019 | tcg_temp_free_i64(tcg_zero); | |
4020 | } | |
4021 | ||
4022 | if (index != 0) { | |
4023 | /* pre-index or post-index */ | |
4024 | if (index < 0) { | |
4025 | /* post-index */ | |
4026 | tcg_gen_addi_i64(addr, addr, offset); | |
4027 | } | |
4028 | tcg_gen_mov_i64(cpu_reg_sp(s, rn), addr); | |
4029 | } | |
4030 | } | |
4031 | ||
4ce31af4 | 4032 | /* Loads and stores */ |
ad7ee8a2 CF |
4033 | static void disas_ldst(DisasContext *s, uint32_t insn) |
4034 | { | |
4035 | switch (extract32(insn, 24, 6)) { | |
4036 | case 0x08: /* Load/store exclusive */ | |
4037 | disas_ldst_excl(s, insn); | |
4038 | break; | |
4039 | case 0x18: case 0x1c: /* Load register (literal) */ | |
4040 | disas_ld_lit(s, insn); | |
4041 | break; | |
4042 | case 0x28: case 0x29: | |
4043 | case 0x2c: case 0x2d: /* Load/store pair (all forms) */ | |
4044 | disas_ldst_pair(s, insn); | |
4045 | break; | |
4046 | case 0x38: case 0x39: | |
4047 | case 0x3c: case 0x3d: /* Load/store register (all forms) */ | |
4048 | disas_ldst_reg(s, insn); | |
4049 | break; | |
4050 | case 0x0c: /* AdvSIMD load/store multiple structures */ | |
4051 | disas_ldst_multiple_struct(s, insn); | |
4052 | break; | |
4053 | case 0x0d: /* AdvSIMD load/store single structure */ | |
4054 | disas_ldst_single_struct(s, insn); | |
4055 | break; | |
c15294c1 RH |
4056 | case 0x19: |
4057 | if (extract32(insn, 21, 1) != 0) { | |
4058 | disas_ldst_tag(s, insn); | |
4059 | } else if (extract32(insn, 10, 2) == 0) { | |
4060 | disas_ldst_ldapr_stlr(s, insn); | |
4061 | } else { | |
a1229109 | 4062 | unallocated_encoding(s); |
a1229109 | 4063 | } |
a1229109 | 4064 | break; |
ad7ee8a2 CF |
4065 | default: |
4066 | unallocated_encoding(s); | |
4067 | break; | |
4068 | } | |
4069 | } | |
4070 | ||
4ce31af4 | 4071 | /* PC-rel. addressing |
15bfe8b6 AG |
4072 | * 31 30 29 28 24 23 5 4 0 |
4073 | * +----+-------+-----------+-------------------+------+ | |
4074 | * | op | immlo | 1 0 0 0 0 | immhi | Rd | | |
4075 | * +----+-------+-----------+-------------------+------+ | |
4076 | */ | |
ad7ee8a2 CF |
4077 | static void disas_pc_rel_adr(DisasContext *s, uint32_t insn) |
4078 | { | |
15bfe8b6 AG |
4079 | unsigned int page, rd; |
4080 | uint64_t base; | |
037e1d00 | 4081 | uint64_t offset; |
15bfe8b6 AG |
4082 | |
4083 | page = extract32(insn, 31, 1); | |
4084 | /* SignExtend(immhi:immlo) -> offset */ | |
037e1d00 PM |
4085 | offset = sextract64(insn, 5, 19); |
4086 | offset = offset << 2 | extract32(insn, 29, 2); | |
15bfe8b6 | 4087 | rd = extract32(insn, 0, 5); |
43722a6d | 4088 | base = s->pc_curr; |
15bfe8b6 AG |
4089 | |
4090 | if (page) { | |
4091 | /* ADRP (page based) */ | |
4092 | base &= ~0xfff; | |
4093 | offset <<= 12; | |
4094 | } | |
4095 | ||
4096 | tcg_gen_movi_i64(cpu_reg(s, rd), base + offset); | |
ad7ee8a2 CF |
4097 | } |
4098 | ||
b0ff21b4 | 4099 | /* |
4ce31af4 | 4100 | * Add/subtract (immediate) |
b0ff21b4 | 4101 | * |
21a8b343 RH |
4102 | * 31 30 29 28 23 22 21 10 9 5 4 0 |
4103 | * +--+--+--+-------------+--+-------------+-----+-----+ | |
4104 | * |sf|op| S| 1 0 0 0 1 0 |sh| imm12 | Rn | Rd | | |
4105 | * +--+--+--+-------------+--+-------------+-----+-----+ | |
b0ff21b4 AB |
4106 | * |
4107 | * sf: 0 -> 32bit, 1 -> 64bit | |
4108 | * op: 0 -> add , 1 -> sub | |
4109 | * S: 1 -> set flags | |
21a8b343 | 4110 | * sh: 1 -> LSL imm by 12 |
b0ff21b4 | 4111 | */ |
ad7ee8a2 CF |
4112 | static void disas_add_sub_imm(DisasContext *s, uint32_t insn) |
4113 | { | |
b0ff21b4 AB |
4114 | int rd = extract32(insn, 0, 5); |
4115 | int rn = extract32(insn, 5, 5); | |
4116 | uint64_t imm = extract32(insn, 10, 12); | |
21a8b343 | 4117 | bool shift = extract32(insn, 22, 1); |
b0ff21b4 AB |
4118 | bool setflags = extract32(insn, 29, 1); |
4119 | bool sub_op = extract32(insn, 30, 1); | |
4120 | bool is_64bit = extract32(insn, 31, 1); | |
4121 | ||
4122 | TCGv_i64 tcg_rn = cpu_reg_sp(s, rn); | |
4123 | TCGv_i64 tcg_rd = setflags ? cpu_reg(s, rd) : cpu_reg_sp(s, rd); | |
4124 | TCGv_i64 tcg_result; | |
4125 | ||
21a8b343 | 4126 | if (shift) { |
b0ff21b4 | 4127 | imm <<= 12; |
b0ff21b4 AB |
4128 | } |
4129 | ||
4130 | tcg_result = tcg_temp_new_i64(); | |
4131 | if (!setflags) { | |
4132 | if (sub_op) { | |
4133 | tcg_gen_subi_i64(tcg_result, tcg_rn, imm); | |
4134 | } else { | |
4135 | tcg_gen_addi_i64(tcg_result, tcg_rn, imm); | |
4136 | } | |
4137 | } else { | |
4138 | TCGv_i64 tcg_imm = tcg_const_i64(imm); | |
4139 | if (sub_op) { | |
4140 | gen_sub_CC(is_64bit, tcg_result, tcg_rn, tcg_imm); | |
4141 | } else { | |
4142 | gen_add_CC(is_64bit, tcg_result, tcg_rn, tcg_imm); | |
4143 | } | |
4144 | tcg_temp_free_i64(tcg_imm); | |
4145 | } | |
4146 | ||
4147 | if (is_64bit) { | |
4148 | tcg_gen_mov_i64(tcg_rd, tcg_result); | |
4149 | } else { | |
4150 | tcg_gen_ext32u_i64(tcg_rd, tcg_result); | |
4151 | } | |
4152 | ||
4153 | tcg_temp_free_i64(tcg_result); | |
ad7ee8a2 CF |
4154 | } |
4155 | ||
efbc78ad RH |
4156 | /* |
4157 | * Add/subtract (immediate, with tags) | |
4158 | * | |
4159 | * 31 30 29 28 23 22 21 16 14 10 9 5 4 0 | |
4160 | * +--+--+--+-------------+--+---------+--+-------+-----+-----+ | |
4161 | * |sf|op| S| 1 0 0 0 1 1 |o2| uimm6 |o3| uimm4 | Rn | Rd | | |
4162 | * +--+--+--+-------------+--+---------+--+-------+-----+-----+ | |
4163 | * | |
4164 | * op: 0 -> add, 1 -> sub | |
4165 | */ | |
4166 | static void disas_add_sub_imm_with_tags(DisasContext *s, uint32_t insn) | |
4167 | { | |
4168 | int rd = extract32(insn, 0, 5); | |
4169 | int rn = extract32(insn, 5, 5); | |
4170 | int uimm4 = extract32(insn, 10, 4); | |
4171 | int uimm6 = extract32(insn, 16, 6); | |
4172 | bool sub_op = extract32(insn, 30, 1); | |
4173 | TCGv_i64 tcg_rn, tcg_rd; | |
4174 | int imm; | |
4175 | ||
4176 | /* Test all of sf=1, S=0, o2=0, o3=0. */ | |
4177 | if ((insn & 0xa040c000u) != 0x80000000u || | |
4178 | !dc_isar_feature(aa64_mte_insn_reg, s)) { | |
4179 | unallocated_encoding(s); | |
4180 | return; | |
4181 | } | |
4182 | ||
4183 | imm = uimm6 << LOG2_TAG_GRANULE; | |
4184 | if (sub_op) { | |
4185 | imm = -imm; | |
4186 | } | |
4187 | ||
4188 | tcg_rn = cpu_reg_sp(s, rn); | |
4189 | tcg_rd = cpu_reg_sp(s, rd); | |
4190 | ||
4191 | if (s->ata) { | |
4192 | TCGv_i32 offset = tcg_const_i32(imm); | |
4193 | TCGv_i32 tag_offset = tcg_const_i32(uimm4); | |
4194 | ||
4195 | gen_helper_addsubg(tcg_rd, cpu_env, tcg_rn, offset, tag_offset); | |
4196 | tcg_temp_free_i32(tag_offset); | |
4197 | tcg_temp_free_i32(offset); | |
4198 | } else { | |
4199 | tcg_gen_addi_i64(tcg_rd, tcg_rn, imm); | |
4200 | gen_address_with_allocation_tag0(tcg_rd, tcg_rd); | |
4201 | } | |
4202 | } | |
4203 | ||
71b46089 AG |
4204 | /* The input should be a value in the bottom e bits (with higher |
4205 | * bits zero); returns that value replicated into every element | |
4206 | * of size e in a 64 bit integer. | |
4207 | */ | |
4208 | static uint64_t bitfield_replicate(uint64_t mask, unsigned int e) | |
4209 | { | |
4210 | assert(e != 0); | |
4211 | while (e < 64) { | |
4212 | mask |= mask << e; | |
4213 | e *= 2; | |
4214 | } | |
4215 | return mask; | |
4216 | } | |
4217 | ||
4218 | /* Return a value with the bottom len bits set (where 0 < len <= 64) */ | |
4219 | static inline uint64_t bitmask64(unsigned int length) | |
4220 | { | |
4221 | assert(length > 0 && length <= 64); | |
4222 | return ~0ULL >> (64 - length); | |
4223 | } | |
4224 | ||
4225 | /* Simplified variant of pseudocode DecodeBitMasks() for the case where we | |
4226 | * only require the wmask. Returns false if the imms/immr/immn are a reserved | |
4227 | * value (ie should cause a guest UNDEF exception), and true if they are | |
4228 | * valid, in which case the decoded bit pattern is written to result. | |
4229 | */ | |
8c71baed RH |
4230 | bool logic_imm_decode_wmask(uint64_t *result, unsigned int immn, |
4231 | unsigned int imms, unsigned int immr) | |
71b46089 AG |
4232 | { |
4233 | uint64_t mask; | |
4234 | unsigned e, levels, s, r; | |
4235 | int len; | |
4236 | ||
4237 | assert(immn < 2 && imms < 64 && immr < 64); | |
4238 | ||
4239 | /* The bit patterns we create here are 64 bit patterns which | |
4240 | * are vectors of identical elements of size e = 2, 4, 8, 16, 32 or | |
4241 | * 64 bits each. Each element contains the same value: a run | |
4242 | * of between 1 and e-1 non-zero bits, rotated within the | |
4243 | * element by between 0 and e-1 bits. | |
4244 | * | |
4245 | * The element size and run length are encoded into immn (1 bit) | |
4246 | * and imms (6 bits) as follows: | |
4247 | * 64 bit elements: immn = 1, imms = <length of run - 1> | |
4248 | * 32 bit elements: immn = 0, imms = 0 : <length of run - 1> | |
4249 | * 16 bit elements: immn = 0, imms = 10 : <length of run - 1> | |
4250 | * 8 bit elements: immn = 0, imms = 110 : <length of run - 1> | |
4251 | * 4 bit elements: immn = 0, imms = 1110 : <length of run - 1> | |
4252 | * 2 bit elements: immn = 0, imms = 11110 : <length of run - 1> | |
4253 | * Notice that immn = 0, imms = 11111x is the only combination | |
4254 | * not covered by one of the above options; this is reserved. | |
4255 | * Further, <length of run - 1> all-ones is a reserved pattern. | |
4256 | * | |
4257 | * In all cases the rotation is by immr % e (and immr is 6 bits). | |
4258 | */ | |
4259 | ||
4260 | /* First determine the element size */ | |
4261 | len = 31 - clz32((immn << 6) | (~imms & 0x3f)); | |
4262 | if (len < 1) { | |
4263 | /* This is the immn == 0, imms == 0x11111x case */ | |
4264 | return false; | |
4265 | } | |
4266 | e = 1 << len; | |
4267 | ||
4268 | levels = e - 1; | |
4269 | s = imms & levels; | |
4270 | r = immr & levels; | |
4271 | ||
4272 | if (s == levels) { | |
4273 | /* <length of run - 1> mustn't be all-ones. */ | |
4274 | return false; | |
4275 | } | |
4276 | ||
4277 | /* Create the value of one element: s+1 set bits rotated | |
4278 | * by r within the element (which is e bits wide)... | |
4279 | */ | |
4280 | mask = bitmask64(s + 1); | |
e167adc9 PM |
4281 | if (r) { |
4282 | mask = (mask >> r) | (mask << (e - r)); | |
4283 | mask &= bitmask64(e); | |
4284 | } | |
71b46089 AG |
4285 | /* ...then replicate the element over the whole 64 bit value */ |
4286 | mask = bitfield_replicate(mask, e); | |
4287 | *result = mask; | |
4288 | return true; | |
4289 | } | |
4290 | ||
4ce31af4 | 4291 | /* Logical (immediate) |
71b46089 AG |
4292 | * 31 30 29 28 23 22 21 16 15 10 9 5 4 0 |
4293 | * +----+-----+-------------+---+------+------+------+------+ | |
4294 | * | sf | opc | 1 0 0 1 0 0 | N | immr | imms | Rn | Rd | | |
4295 | * +----+-----+-------------+---+------+------+------+------+ | |
4296 | */ | |
ad7ee8a2 CF |
4297 | static void disas_logic_imm(DisasContext *s, uint32_t insn) |
4298 | { | |
71b46089 AG |
4299 | unsigned int sf, opc, is_n, immr, imms, rn, rd; |
4300 | TCGv_i64 tcg_rd, tcg_rn; | |
4301 | uint64_t wmask; | |
4302 | bool is_and = false; | |
4303 | ||
4304 | sf = extract32(insn, 31, 1); | |
4305 | opc = extract32(insn, 29, 2); | |
4306 | is_n = extract32(insn, 22, 1); | |
4307 | immr = extract32(insn, 16, 6); | |
4308 | imms = extract32(insn, 10, 6); | |
4309 | rn = extract32(insn, 5, 5); | |
4310 | rd = extract32(insn, 0, 5); | |
4311 | ||
4312 | if (!sf && is_n) { | |
4313 | unallocated_encoding(s); | |
4314 | return; | |
4315 | } | |
4316 | ||
4317 | if (opc == 0x3) { /* ANDS */ | |
4318 | tcg_rd = cpu_reg(s, rd); | |
4319 | } else { | |
4320 | tcg_rd = cpu_reg_sp(s, rd); | |
4321 | } | |
4322 | tcg_rn = cpu_reg(s, rn); | |
4323 | ||
4324 | if (!logic_imm_decode_wmask(&wmask, is_n, imms, immr)) { | |
4325 | /* some immediate field values are reserved */ | |
4326 | unallocated_encoding(s); | |
4327 | return; | |
4328 | } | |
4329 | ||
4330 | if (!sf) { | |
4331 | wmask &= 0xffffffff; | |
4332 | } | |
4333 | ||
4334 | switch (opc) { | |
4335 | case 0x3: /* ANDS */ | |
4336 | case 0x0: /* AND */ | |
4337 | tcg_gen_andi_i64(tcg_rd, tcg_rn, wmask); | |
4338 | is_and = true; | |
4339 | break; | |
4340 | case 0x1: /* ORR */ | |
4341 | tcg_gen_ori_i64(tcg_rd, tcg_rn, wmask); | |
4342 | break; | |
4343 | case 0x2: /* EOR */ | |
4344 | tcg_gen_xori_i64(tcg_rd, tcg_rn, wmask); | |
4345 | break; | |
4346 | default: | |
4347 | assert(FALSE); /* must handle all above */ | |
4348 | break; | |
4349 | } | |
4350 | ||
4351 | if (!sf && !is_and) { | |
4352 | /* zero extend final result; we know we can skip this for AND | |
4353 | * since the immediate had the high 32 bits clear. | |
4354 | */ | |
4355 | tcg_gen_ext32u_i64(tcg_rd, tcg_rd); | |
4356 | } | |
4357 | ||
4358 | if (opc == 3) { /* ANDS */ | |
4359 | gen_logic_CC(sf, tcg_rd); | |
4360 | } | |
ad7ee8a2 CF |
4361 | } |
4362 | ||
ed6ec679 | 4363 | /* |
4ce31af4 | 4364 | * Move wide (immediate) |
ed6ec679 AB |
4365 | * |
4366 | * 31 30 29 28 23 22 21 20 5 4 0 | |
4367 | * +--+-----+-------------+-----+----------------+------+ | |
4368 | * |sf| opc | 1 0 0 1 0 1 | hw | imm16 | Rd | | |
4369 | * +--+-----+-------------+-----+----------------+------+ | |
4370 | * | |
4371 | * sf: 0 -> 32 bit, 1 -> 64 bit | |
4372 | * opc: 00 -> N, 10 -> Z, 11 -> K | |
4373 | * hw: shift/16 (0,16, and sf only 32, 48) | |
4374 | */ | |
ad7ee8a2 CF |
4375 | static void disas_movw_imm(DisasContext *s, uint32_t insn) |
4376 | { | |
ed6ec679 AB |
4377 | int rd = extract32(insn, 0, 5); |
4378 | uint64_t imm = extract32(insn, 5, 16); | |
4379 | int sf = extract32(insn, 31, 1); | |
4380 | int opc = extract32(insn, 29, 2); | |
4381 | int pos = extract32(insn, 21, 2) << 4; | |
4382 | TCGv_i64 tcg_rd = cpu_reg(s, rd); | |
4383 | TCGv_i64 tcg_imm; | |
4384 | ||
4385 | if (!sf && (pos >= 32)) { | |
4386 | unallocated_encoding(s); | |
4387 | return; | |
4388 | } | |
4389 | ||
4390 | switch (opc) { | |
4391 | case 0: /* MOVN */ | |
4392 | case 2: /* MOVZ */ | |
4393 | imm <<= pos; | |
4394 | if (opc == 0) { | |
4395 | imm = ~imm; | |
4396 | } | |
4397 | if (!sf) { | |
4398 | imm &= 0xffffffffu; | |
4399 | } | |
4400 | tcg_gen_movi_i64(tcg_rd, imm); | |
4401 | break; | |
4402 | case 3: /* MOVK */ | |
4403 | tcg_imm = tcg_const_i64(imm); | |
4404 | tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_imm, pos, 16); | |
4405 | tcg_temp_free_i64(tcg_imm); | |
4406 | if (!sf) { | |
4407 | tcg_gen_ext32u_i64(tcg_rd, tcg_rd); | |
4408 | } | |
4409 | break; | |
4410 | default: | |
4411 | unallocated_encoding(s); | |
4412 | break; | |
4413 | } | |
ad7ee8a2 CF |
4414 | } |
4415 | ||
4ce31af4 | 4416 | /* Bitfield |
88077742 CF |
4417 | * 31 30 29 28 23 22 21 16 15 10 9 5 4 0 |
4418 | * +----+-----+-------------+---+------+------+------+------+ | |
4419 | * | sf | opc | 1 0 0 1 1 0 | N | immr | imms | Rn | Rd | | |
4420 | * +----+-----+-------------+---+------+------+------+------+ | |
4421 | */ | |
ad7ee8a2 CF |
4422 | static void disas_bitfield(DisasContext *s, uint32_t insn) |
4423 | { | |
88077742 CF |
4424 | unsigned int sf, n, opc, ri, si, rn, rd, bitsize, pos, len; |
4425 | TCGv_i64 tcg_rd, tcg_tmp; | |
4426 | ||
4427 | sf = extract32(insn, 31, 1); | |
4428 | opc = extract32(insn, 29, 2); | |
4429 | n = extract32(insn, 22, 1); | |
4430 | ri = extract32(insn, 16, 6); | |
4431 | si = extract32(insn, 10, 6); | |
4432 | rn = extract32(insn, 5, 5); | |
4433 | rd = extract32(insn, 0, 5); | |
4434 | bitsize = sf ? 64 : 32; | |
4435 | ||
4436 | if (sf != n || ri >= bitsize || si >= bitsize || opc > 2) { | |
4437 | unallocated_encoding(s); | |
4438 | return; | |
4439 | } | |
4440 | ||
4441 | tcg_rd = cpu_reg(s, rd); | |
d3a77b42 RH |
4442 | |
4443 | /* Suppress the zero-extend for !sf. Since RI and SI are constrained | |
4444 | to be smaller than bitsize, we'll never reference data outside the | |
4445 | low 32-bits anyway. */ | |
4446 | tcg_tmp = read_cpu_reg(s, rn, 1); | |
88077742 | 4447 | |
59a71b4c | 4448 | /* Recognize simple(r) extractions. */ |
86c9ab27 | 4449 | if (si >= ri) { |
59a71b4c RH |
4450 | /* Wd<s-r:0> = Wn<s:r> */ |
4451 | len = (si - ri) + 1; | |
4452 | if (opc == 0) { /* SBFM: ASR, SBFX, SXTB, SXTH, SXTW */ | |
4453 | tcg_gen_sextract_i64(tcg_rd, tcg_tmp, ri, len); | |
ef60151b | 4454 | goto done; |
59a71b4c RH |
4455 | } else if (opc == 2) { /* UBFM: UBFX, LSR, UXTB, UXTH */ |
4456 | tcg_gen_extract_i64(tcg_rd, tcg_tmp, ri, len); | |
9924e858 RH |
4457 | return; |
4458 | } | |
87eb65a3 RH |
4459 | /* opc == 1, BFXIL fall through to deposit */ |
4460 | tcg_gen_shri_i64(tcg_tmp, tcg_tmp, ri); | |
88077742 | 4461 | pos = 0; |
88077742 | 4462 | } else { |
59a71b4c RH |
4463 | /* Handle the ri > si case with a deposit |
4464 | * Wd<32+s-r,32-r> = Wn<s:0> | |
4465 | */ | |
88077742 | 4466 | len = si + 1; |
59a71b4c | 4467 | pos = (bitsize - ri) & (bitsize - 1); |
88077742 CF |
4468 | } |
4469 | ||
59a71b4c RH |
4470 | if (opc == 0 && len < ri) { |
4471 | /* SBFM: sign extend the destination field from len to fill | |
4472 | the balance of the word. Let the deposit below insert all | |
4473 | of those sign bits. */ | |
4474 | tcg_gen_sextract_i64(tcg_tmp, tcg_tmp, 0, len); | |
4475 | len = ri; | |
4476 | } | |
88077742 | 4477 | |
87eb65a3 | 4478 | if (opc == 1) { /* BFM, BFXIL */ |
59a71b4c RH |
4479 | tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_tmp, pos, len); |
4480 | } else { | |
4481 | /* SBFM or UBFM: We start with zero, and we haven't modified | |
4482 | any bits outside bitsize, therefore the zero-extension | |
4483 | below is unneeded. */ | |
4484 | tcg_gen_deposit_z_i64(tcg_rd, tcg_tmp, pos, len); | |
4485 | return; | |
88077742 CF |
4486 | } |
4487 | ||
ef60151b | 4488 | done: |
88077742 CF |
4489 | if (!sf) { /* zero extend final result */ |
4490 | tcg_gen_ext32u_i64(tcg_rd, tcg_rd); | |
4491 | } | |
ad7ee8a2 CF |
4492 | } |
4493 | ||
4ce31af4 | 4494 | /* Extract |
e801de93 AG |
4495 | * 31 30 29 28 23 22 21 20 16 15 10 9 5 4 0 |
4496 | * +----+------+-------------+---+----+------+--------+------+------+ | |
4497 | * | sf | op21 | 1 0 0 1 1 1 | N | o0 | Rm | imms | Rn | Rd | | |
4498 | * +----+------+-------------+---+----+------+--------+------+------+ | |
4499 | */ | |
ad7ee8a2 CF |
4500 | static void disas_extract(DisasContext *s, uint32_t insn) |
4501 | { | |
e801de93 AG |
4502 | unsigned int sf, n, rm, imm, rn, rd, bitsize, op21, op0; |
4503 | ||
4504 | sf = extract32(insn, 31, 1); | |
4505 | n = extract32(insn, 22, 1); | |
4506 | rm = extract32(insn, 16, 5); | |
4507 | imm = extract32(insn, 10, 6); | |
4508 | rn = extract32(insn, 5, 5); | |
4509 | rd = extract32(insn, 0, 5); | |
4510 | op21 = extract32(insn, 29, 2); | |
4511 | op0 = extract32(insn, 21, 1); | |
4512 | bitsize = sf ? 64 : 32; | |
4513 | ||
4514 | if (sf != n || op21 || op0 || imm >= bitsize) { | |
4515 | unallocated_encoding(s); | |
4516 | } else { | |
4517 | TCGv_i64 tcg_rd, tcg_rm, tcg_rn; | |
4518 | ||
4519 | tcg_rd = cpu_reg(s, rd); | |
4520 | ||
8fb0ad8e | 4521 | if (unlikely(imm == 0)) { |
e801de93 AG |
4522 | /* tcg shl_i32/shl_i64 is undefined for 32/64 bit shifts, |
4523 | * so an extract from bit 0 is a special case. | |
4524 | */ | |
4525 | if (sf) { | |
4526 | tcg_gen_mov_i64(tcg_rd, cpu_reg(s, rm)); | |
4527 | } else { | |
4528 | tcg_gen_ext32u_i64(tcg_rd, cpu_reg(s, rm)); | |
4529 | } | |
80ac954c | 4530 | } else { |
8fb0ad8e | 4531 | tcg_rm = cpu_reg(s, rm); |
80ac954c RH |
4532 | tcg_rn = cpu_reg(s, rn); |
4533 | ||
8fb0ad8e | 4534 | if (sf) { |
80ac954c RH |
4535 | /* Specialization to ROR happens in EXTRACT2. */ |
4536 | tcg_gen_extract2_i64(tcg_rd, tcg_rm, tcg_rn, imm); | |
8fb0ad8e | 4537 | } else { |
80ac954c RH |
4538 | TCGv_i32 t0 = tcg_temp_new_i32(); |
4539 | ||
4540 | tcg_gen_extrl_i64_i32(t0, tcg_rm); | |
4541 | if (rm == rn) { | |
4542 | tcg_gen_rotri_i32(t0, t0, imm); | |
4543 | } else { | |
4544 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
4545 | tcg_gen_extrl_i64_i32(t1, tcg_rn); | |
4546 | tcg_gen_extract2_i32(t0, t0, t1, imm); | |
4547 | tcg_temp_free_i32(t1); | |
4548 | } | |
4549 | tcg_gen_extu_i32_i64(tcg_rd, t0); | |
4550 | tcg_temp_free_i32(t0); | |
8fb0ad8e | 4551 | } |
e801de93 | 4552 | } |
e801de93 | 4553 | } |
ad7ee8a2 CF |
4554 | } |
4555 | ||
4ce31af4 | 4556 | /* Data processing - immediate */ |
ad7ee8a2 CF |
4557 | static void disas_data_proc_imm(DisasContext *s, uint32_t insn) |
4558 | { | |
4559 | switch (extract32(insn, 23, 6)) { | |
4560 | case 0x20: case 0x21: /* PC-rel. addressing */ | |
4561 | disas_pc_rel_adr(s, insn); | |
4562 | break; | |
21a8b343 | 4563 | case 0x22: /* Add/subtract (immediate) */ |
ad7ee8a2 CF |
4564 | disas_add_sub_imm(s, insn); |
4565 | break; | |
efbc78ad RH |
4566 | case 0x23: /* Add/subtract (immediate, with tags) */ |
4567 | disas_add_sub_imm_with_tags(s, insn); | |
4568 | break; | |
ad7ee8a2 CF |
4569 | case 0x24: /* Logical (immediate) */ |
4570 | disas_logic_imm(s, insn); | |
4571 | break; | |
4572 | case 0x25: /* Move wide (immediate) */ | |
4573 | disas_movw_imm(s, insn); | |
4574 | break; | |
4575 | case 0x26: /* Bitfield */ | |
4576 | disas_bitfield(s, insn); | |
4577 | break; | |
4578 | case 0x27: /* Extract */ | |
4579 | disas_extract(s, insn); | |
4580 | break; | |
4581 | default: | |
4582 | unallocated_encoding(s); | |
4583 | break; | |
4584 | } | |
4585 | } | |
4586 | ||
832ffa1c AG |
4587 | /* Shift a TCGv src by TCGv shift_amount, put result in dst. |
4588 | * Note that it is the caller's responsibility to ensure that the | |
4589 | * shift amount is in range (ie 0..31 or 0..63) and provide the ARM | |
4590 | * mandated semantics for out of range shifts. | |
4591 | */ | |
4592 | static void shift_reg(TCGv_i64 dst, TCGv_i64 src, int sf, | |
4593 | enum a64_shift_type shift_type, TCGv_i64 shift_amount) | |
4594 | { | |
4595 | switch (shift_type) { | |
4596 | case A64_SHIFT_TYPE_LSL: | |
4597 | tcg_gen_shl_i64(dst, src, shift_amount); | |
4598 | break; | |
4599 | case A64_SHIFT_TYPE_LSR: | |
4600 | tcg_gen_shr_i64(dst, src, shift_amount); | |
4601 | break; | |
4602 | case A64_SHIFT_TYPE_ASR: | |
4603 | if (!sf) { | |
4604 | tcg_gen_ext32s_i64(dst, src); | |
4605 | } | |
4606 | tcg_gen_sar_i64(dst, sf ? src : dst, shift_amount); | |
4607 | break; | |
4608 | case A64_SHIFT_TYPE_ROR: | |
4609 | if (sf) { | |
4610 | tcg_gen_rotr_i64(dst, src, shift_amount); | |
4611 | } else { | |
4612 | TCGv_i32 t0, t1; | |
4613 | t0 = tcg_temp_new_i32(); | |
4614 | t1 = tcg_temp_new_i32(); | |
ecc7b3aa RH |
4615 | tcg_gen_extrl_i64_i32(t0, src); |
4616 | tcg_gen_extrl_i64_i32(t1, shift_amount); | |
832ffa1c AG |
4617 | tcg_gen_rotr_i32(t0, t0, t1); |
4618 | tcg_gen_extu_i32_i64(dst, t0); | |
4619 | tcg_temp_free_i32(t0); | |
4620 | tcg_temp_free_i32(t1); | |
4621 | } | |
4622 | break; | |
4623 | default: | |
4624 | assert(FALSE); /* all shift types should be handled */ | |
4625 | break; | |
4626 | } | |
4627 | ||
4628 | if (!sf) { /* zero extend final result */ | |
4629 | tcg_gen_ext32u_i64(dst, dst); | |
4630 | } | |
4631 | } | |
4632 | ||
4633 | /* Shift a TCGv src by immediate, put result in dst. | |
4634 | * The shift amount must be in range (this should always be true as the | |
4635 | * relevant instructions will UNDEF on bad shift immediates). | |
4636 | */ | |
4637 | static void shift_reg_imm(TCGv_i64 dst, TCGv_i64 src, int sf, | |
4638 | enum a64_shift_type shift_type, unsigned int shift_i) | |
4639 | { | |
4640 | assert(shift_i < (sf ? 64 : 32)); | |
4641 | ||
4642 | if (shift_i == 0) { | |
4643 | tcg_gen_mov_i64(dst, src); | |
4644 | } else { | |
4645 | TCGv_i64 shift_const; | |
4646 | ||
4647 | shift_const = tcg_const_i64(shift_i); | |
4648 | shift_reg(dst, src, sf, shift_type, shift_const); | |
4649 | tcg_temp_free_i64(shift_const); | |
4650 | } | |
4651 | } | |
4652 | ||
4ce31af4 | 4653 | /* Logical (shifted register) |
832ffa1c AG |
4654 | * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0 |
4655 | * +----+-----+-----------+-------+---+------+--------+------+------+ | |
4656 | * | sf | opc | 0 1 0 1 0 | shift | N | Rm | imm6 | Rn | Rd | | |
4657 | * +----+-----+-----------+-------+---+------+--------+------+------+ | |
4658 | */ | |
ad7ee8a2 CF |
4659 | static void disas_logic_reg(DisasContext *s, uint32_t insn) |
4660 | { | |
832ffa1c AG |
4661 | TCGv_i64 tcg_rd, tcg_rn, tcg_rm; |
4662 | unsigned int sf, opc, shift_type, invert, rm, shift_amount, rn, rd; | |
4663 | ||
4664 | sf = extract32(insn, 31, 1); | |
4665 | opc = extract32(insn, 29, 2); | |
4666 | shift_type = extract32(insn, 22, 2); | |
4667 | invert = extract32(insn, 21, 1); | |
4668 | rm = extract32(insn, 16, 5); | |
4669 | shift_amount = extract32(insn, 10, 6); | |
4670 | rn = extract32(insn, 5, 5); | |
4671 | rd = extract32(insn, 0, 5); | |
4672 | ||
4673 | if (!sf && (shift_amount & (1 << 5))) { | |
4674 | unallocated_encoding(s); | |
4675 | return; | |
4676 | } | |
4677 | ||
4678 | tcg_rd = cpu_reg(s, rd); | |
4679 | ||
4680 | if (opc == 1 && shift_amount == 0 && shift_type == 0 && rn == 31) { | |
4681 | /* Unshifted ORR and ORN with WZR/XZR is the standard encoding for | |
4682 | * register-register MOV and MVN, so it is worth special casing. | |
4683 | */ | |
4684 | tcg_rm = cpu_reg(s, rm); | |
4685 | if (invert) { | |
4686 | tcg_gen_not_i64(tcg_rd, tcg_rm); | |
4687 | if (!sf) { | |
4688 | tcg_gen_ext32u_i64(tcg_rd, tcg_rd); | |
4689 | } | |
4690 | } else { | |
4691 | if (sf) { | |
4692 | tcg_gen_mov_i64(tcg_rd, tcg_rm); | |
4693 | } else { | |
4694 | tcg_gen_ext32u_i64(tcg_rd, tcg_rm); | |
4695 | } | |
4696 | } | |
4697 | return; | |
4698 | } | |
4699 | ||
4700 | tcg_rm = read_cpu_reg(s, rm, sf); | |
4701 | ||
4702 | if (shift_amount) { | |
4703 | shift_reg_imm(tcg_rm, tcg_rm, sf, shift_type, shift_amount); | |
4704 | } | |
4705 | ||
4706 | tcg_rn = cpu_reg(s, rn); | |
4707 | ||
4708 | switch (opc | (invert << 2)) { | |
4709 | case 0: /* AND */ | |
4710 | case 3: /* ANDS */ | |
4711 | tcg_gen_and_i64(tcg_rd, tcg_rn, tcg_rm); | |
4712 | break; | |
4713 | case 1: /* ORR */ | |
4714 | tcg_gen_or_i64(tcg_rd, tcg_rn, tcg_rm); | |
4715 | break; | |
4716 | case 2: /* EOR */ | |
4717 | tcg_gen_xor_i64(tcg_rd, tcg_rn, tcg_rm); | |
4718 | break; | |
4719 | case 4: /* BIC */ | |
4720 | case 7: /* BICS */ | |
4721 | tcg_gen_andc_i64(tcg_rd, tcg_rn, tcg_rm); | |
4722 | break; | |
4723 | case 5: /* ORN */ | |
4724 | tcg_gen_orc_i64(tcg_rd, tcg_rn, tcg_rm); | |
4725 | break; | |
4726 | case 6: /* EON */ | |
4727 | tcg_gen_eqv_i64(tcg_rd, tcg_rn, tcg_rm); | |
4728 | break; | |
4729 | default: | |
4730 | assert(FALSE); | |
4731 | break; | |
4732 | } | |
4733 | ||
4734 | if (!sf) { | |
4735 | tcg_gen_ext32u_i64(tcg_rd, tcg_rd); | |
4736 | } | |
4737 | ||
4738 | if (opc == 3) { | |
4739 | gen_logic_CC(sf, tcg_rd); | |
4740 | } | |
ad7ee8a2 CF |
4741 | } |
4742 | ||
b0ff21b4 | 4743 | /* |
4ce31af4 | 4744 | * Add/subtract (extended register) |
b0ff21b4 AB |
4745 | * |
4746 | * 31|30|29|28 24|23 22|21|20 16|15 13|12 10|9 5|4 0| | |
4747 | * +--+--+--+-----------+-----+--+-------+------+------+----+----+ | |
4748 | * |sf|op| S| 0 1 0 1 1 | opt | 1| Rm |option| imm3 | Rn | Rd | | |
4749 | * +--+--+--+-----------+-----+--+-------+------+------+----+----+ | |
4750 | * | |
4751 | * sf: 0 -> 32bit, 1 -> 64bit | |
4752 | * op: 0 -> add , 1 -> sub | |
4753 | * S: 1 -> set flags | |
4754 | * opt: 00 | |
4755 | * option: extension type (see DecodeRegExtend) | |
4756 | * imm3: optional shift to Rm | |
4757 | * | |
4758 | * Rd = Rn + LSL(extend(Rm), amount) | |
4759 | */ | |
ad7ee8a2 CF |
4760 | static void disas_add_sub_ext_reg(DisasContext *s, uint32_t insn) |
4761 | { | |
b0ff21b4 AB |
4762 | int rd = extract32(insn, 0, 5); |
4763 | int rn = extract32(insn, 5, 5); | |
4764 | int imm3 = extract32(insn, 10, 3); | |
4765 | int option = extract32(insn, 13, 3); | |
4766 | int rm = extract32(insn, 16, 5); | |
4f611066 | 4767 | int opt = extract32(insn, 22, 2); |
b0ff21b4 AB |
4768 | bool setflags = extract32(insn, 29, 1); |
4769 | bool sub_op = extract32(insn, 30, 1); | |
4770 | bool sf = extract32(insn, 31, 1); | |
4771 | ||
4772 | TCGv_i64 tcg_rm, tcg_rn; /* temps */ | |
4773 | TCGv_i64 tcg_rd; | |
4774 | TCGv_i64 tcg_result; | |
4775 | ||
4f611066 | 4776 | if (imm3 > 4 || opt != 0) { |
b0ff21b4 AB |
4777 | unallocated_encoding(s); |
4778 | return; | |
4779 | } | |
4780 | ||
4781 | /* non-flag setting ops may use SP */ | |
4782 | if (!setflags) { | |
b0ff21b4 AB |
4783 | tcg_rd = cpu_reg_sp(s, rd); |
4784 | } else { | |
b0ff21b4 AB |
4785 | tcg_rd = cpu_reg(s, rd); |
4786 | } | |
cf4ab1af | 4787 | tcg_rn = read_cpu_reg_sp(s, rn, sf); |
b0ff21b4 AB |
4788 | |
4789 | tcg_rm = read_cpu_reg(s, rm, sf); | |
4790 | ext_and_shift_reg(tcg_rm, tcg_rm, option, imm3); | |
4791 | ||
4792 | tcg_result = tcg_temp_new_i64(); | |
4793 | ||
4794 | if (!setflags) { | |
4795 | if (sub_op) { | |
4796 | tcg_gen_sub_i64(tcg_result, tcg_rn, tcg_rm); | |
4797 | } else { | |
4798 | tcg_gen_add_i64(tcg_result, tcg_rn, tcg_rm); | |
4799 | } | |
4800 | } else { | |
4801 | if (sub_op) { | |
4802 | gen_sub_CC(sf, tcg_result, tcg_rn, tcg_rm); | |
4803 | } else { | |
4804 | gen_add_CC(sf, tcg_result, tcg_rn, tcg_rm); | |
4805 | } | |
4806 | } | |
4807 | ||
4808 | if (sf) { | |
4809 | tcg_gen_mov_i64(tcg_rd, tcg_result); | |
4810 | } else { | |
4811 | tcg_gen_ext32u_i64(tcg_rd, tcg_result); | |
4812 | } | |
4813 | ||
4814 | tcg_temp_free_i64(tcg_result); | |
ad7ee8a2 CF |
4815 | } |
4816 | ||
b0ff21b4 | 4817 | /* |
4ce31af4 | 4818 | * Add/subtract (shifted register) |
b0ff21b4 AB |
4819 | * |
4820 | * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0 | |
4821 | * +--+--+--+-----------+-----+--+-------+---------+------+------+ | |
4822 | * |sf|op| S| 0 1 0 1 1 |shift| 0| Rm | imm6 | Rn | Rd | | |
4823 | * +--+--+--+-----------+-----+--+-------+---------+------+------+ | |
4824 | * | |
4825 | * sf: 0 -> 32bit, 1 -> 64bit | |
4826 | * op: 0 -> add , 1 -> sub | |
4827 | * S: 1 -> set flags | |
4828 | * shift: 00 -> LSL, 01 -> LSR, 10 -> ASR, 11 -> RESERVED | |
4829 | * imm6: Shift amount to apply to Rm before the add/sub | |
4830 | */ | |
ad7ee8a2 CF |
4831 | static void disas_add_sub_reg(DisasContext *s, uint32_t insn) |
4832 | { | |
b0ff21b4 AB |
4833 | int rd = extract32(insn, 0, 5); |
4834 | int rn = extract32(insn, 5, 5); | |
4835 | int imm6 = extract32(insn, 10, 6); | |
4836 | int rm = extract32(insn, 16, 5); | |
4837 | int shift_type = extract32(insn, 22, 2); | |
4838 | bool setflags = extract32(insn, 29, 1); | |
4839 | bool sub_op = extract32(insn, 30, 1); | |
4840 | bool sf = extract32(insn, 31, 1); | |
4841 | ||
4842 | TCGv_i64 tcg_rd = cpu_reg(s, rd); | |
4843 | TCGv_i64 tcg_rn, tcg_rm; | |
4844 | TCGv_i64 tcg_result; | |
4845 | ||
4846 | if ((shift_type == 3) || (!sf && (imm6 > 31))) { | |
4847 | unallocated_encoding(s); | |
4848 | return; | |
4849 | } | |
4850 | ||
4851 | tcg_rn = read_cpu_reg(s, rn, sf); | |
4852 | tcg_rm = read_cpu_reg(s, rm, sf); | |
4853 | ||
4854 | shift_reg_imm(tcg_rm, tcg_rm, sf, shift_type, imm6); | |
4855 | ||
4856 | tcg_result = tcg_temp_new_i64(); | |
4857 | ||
4858 | if (!setflags) { | |
4859 | if (sub_op) { | |
4860 | tcg_gen_sub_i64(tcg_result, tcg_rn, tcg_rm); | |
4861 | } else { | |
4862 | tcg_gen_add_i64(tcg_result, tcg_rn, tcg_rm); | |
4863 | } | |
4864 | } else { | |
4865 | if (sub_op) { | |
4866 | gen_sub_CC(sf, tcg_result, tcg_rn, tcg_rm); | |
4867 | } else { | |
4868 | gen_add_CC(sf, tcg_result, tcg_rn, tcg_rm); | |
4869 | } | |
4870 | } | |
4871 | ||
4872 | if (sf) { | |
4873 | tcg_gen_mov_i64(tcg_rd, tcg_result); | |
4874 | } else { | |
4875 | tcg_gen_ext32u_i64(tcg_rd, tcg_result); | |
4876 | } | |
4877 | ||
4878 | tcg_temp_free_i64(tcg_result); | |
ad7ee8a2 CF |
4879 | } |
4880 | ||
4ce31af4 PM |
4881 | /* Data-processing (3 source) |
4882 | * | |
4883 | * 31 30 29 28 24 23 21 20 16 15 14 10 9 5 4 0 | |
4884 | * +--+------+-----------+------+------+----+------+------+------+ | |
4885 | * |sf| op54 | 1 1 0 1 1 | op31 | Rm | o0 | Ra | Rn | Rd | | |
4886 | * +--+------+-----------+------+------+----+------+------+------+ | |
52c8b9af | 4887 | */ |
ad7ee8a2 CF |
4888 | static void disas_data_proc_3src(DisasContext *s, uint32_t insn) |
4889 | { | |
52c8b9af AG |
4890 | int rd = extract32(insn, 0, 5); |
4891 | int rn = extract32(insn, 5, 5); | |
4892 | int ra = extract32(insn, 10, 5); | |
4893 | int rm = extract32(insn, 16, 5); | |
4894 | int op_id = (extract32(insn, 29, 3) << 4) | | |
4895 | (extract32(insn, 21, 3) << 1) | | |
4896 | extract32(insn, 15, 1); | |
4897 | bool sf = extract32(insn, 31, 1); | |
4898 | bool is_sub = extract32(op_id, 0, 1); | |
4899 | bool is_high = extract32(op_id, 2, 1); | |
4900 | bool is_signed = false; | |
4901 | TCGv_i64 tcg_op1; | |
4902 | TCGv_i64 tcg_op2; | |
4903 | TCGv_i64 tcg_tmp; | |
4904 | ||
4905 | /* Note that op_id is sf:op54:op31:o0 so it includes the 32/64 size flag */ | |
4906 | switch (op_id) { | |
4907 | case 0x42: /* SMADDL */ | |
4908 | case 0x43: /* SMSUBL */ | |
4909 | case 0x44: /* SMULH */ | |
4910 | is_signed = true; | |
4911 | break; | |
4912 | case 0x0: /* MADD (32bit) */ | |
4913 | case 0x1: /* MSUB (32bit) */ | |
4914 | case 0x40: /* MADD (64bit) */ | |
4915 | case 0x41: /* MSUB (64bit) */ | |
4916 | case 0x4a: /* UMADDL */ | |
4917 | case 0x4b: /* UMSUBL */ | |
4918 | case 0x4c: /* UMULH */ | |
4919 | break; | |
4920 | default: | |
4921 | unallocated_encoding(s); | |
4922 | return; | |
4923 | } | |
4924 | ||
4925 | if (is_high) { | |
4926 | TCGv_i64 low_bits = tcg_temp_new_i64(); /* low bits discarded */ | |
4927 | TCGv_i64 tcg_rd = cpu_reg(s, rd); | |
4928 | TCGv_i64 tcg_rn = cpu_reg(s, rn); | |
4929 | TCGv_i64 tcg_rm = cpu_reg(s, rm); | |
4930 | ||
4931 | if (is_signed) { | |
4932 | tcg_gen_muls2_i64(low_bits, tcg_rd, tcg_rn, tcg_rm); | |
4933 | } else { | |
4934 | tcg_gen_mulu2_i64(low_bits, tcg_rd, tcg_rn, tcg_rm); | |
4935 | } | |
4936 | ||
4937 | tcg_temp_free_i64(low_bits); | |
4938 | return; | |
4939 | } | |
4940 | ||
4941 | tcg_op1 = tcg_temp_new_i64(); | |
4942 | tcg_op2 = tcg_temp_new_i64(); | |
4943 | tcg_tmp = tcg_temp_new_i64(); | |
4944 | ||
4945 | if (op_id < 0x42) { | |
4946 | tcg_gen_mov_i64(tcg_op1, cpu_reg(s, rn)); | |
4947 | tcg_gen_mov_i64(tcg_op2, cpu_reg(s, rm)); | |
4948 | } else { | |
4949 | if (is_signed) { | |
4950 | tcg_gen_ext32s_i64(tcg_op1, cpu_reg(s, rn)); | |
4951 | tcg_gen_ext32s_i64(tcg_op2, cpu_reg(s, rm)); | |
4952 | } else { | |
4953 | tcg_gen_ext32u_i64(tcg_op1, cpu_reg(s, rn)); | |
4954 | tcg_gen_ext32u_i64(tcg_op2, cpu_reg(s, rm)); | |
4955 | } | |
4956 | } | |
4957 | ||
4958 | if (ra == 31 && !is_sub) { | |
4959 | /* Special-case MADD with rA == XZR; it is the standard MUL alias */ | |
4960 | tcg_gen_mul_i64(cpu_reg(s, rd), tcg_op1, tcg_op2); | |
4961 | } else { | |
4962 | tcg_gen_mul_i64(tcg_tmp, tcg_op1, tcg_op2); | |
4963 | if (is_sub) { | |
4964 | tcg_gen_sub_i64(cpu_reg(s, rd), cpu_reg(s, ra), tcg_tmp); | |
4965 | } else { | |
4966 | tcg_gen_add_i64(cpu_reg(s, rd), cpu_reg(s, ra), tcg_tmp); | |
4967 | } | |
4968 | } | |
4969 | ||
4970 | if (!sf) { | |
4971 | tcg_gen_ext32u_i64(cpu_reg(s, rd), cpu_reg(s, rd)); | |
4972 | } | |
4973 | ||
4974 | tcg_temp_free_i64(tcg_op1); | |
4975 | tcg_temp_free_i64(tcg_op2); | |
4976 | tcg_temp_free_i64(tcg_tmp); | |
ad7ee8a2 CF |
4977 | } |
4978 | ||
4ce31af4 | 4979 | /* Add/subtract (with carry) |
2fba34f7 RH |
4980 | * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 10 9 5 4 0 |
4981 | * +--+--+--+------------------------+------+-------------+------+-----+ | |
4982 | * |sf|op| S| 1 1 0 1 0 0 0 0 | rm | 0 0 0 0 0 0 | Rn | Rd | | |
4983 | * +--+--+--+------------------------+------+-------------+------+-----+ | |
643dbb07 CF |
4984 | */ |
4985 | ||
ad7ee8a2 CF |
4986 | static void disas_adc_sbc(DisasContext *s, uint32_t insn) |
4987 | { | |
643dbb07 CF |
4988 | unsigned int sf, op, setflags, rm, rn, rd; |
4989 | TCGv_i64 tcg_y, tcg_rn, tcg_rd; | |
4990 | ||
643dbb07 CF |
4991 | sf = extract32(insn, 31, 1); |
4992 | op = extract32(insn, 30, 1); | |
4993 | setflags = extract32(insn, 29, 1); | |
4994 | rm = extract32(insn, 16, 5); | |
4995 | rn = extract32(insn, 5, 5); | |
4996 | rd = extract32(insn, 0, 5); | |
4997 | ||
4998 | tcg_rd = cpu_reg(s, rd); | |
4999 | tcg_rn = cpu_reg(s, rn); | |
5000 | ||
5001 | if (op) { | |
5002 | tcg_y = new_tmp_a64(s); | |
5003 | tcg_gen_not_i64(tcg_y, cpu_reg(s, rm)); | |
5004 | } else { | |
5005 | tcg_y = cpu_reg(s, rm); | |
5006 | } | |
5007 | ||
5008 | if (setflags) { | |
5009 | gen_adc_CC(sf, tcg_rd, tcg_rn, tcg_y); | |
5010 | } else { | |
5011 | gen_adc(sf, tcg_rd, tcg_rn, tcg_y); | |
5012 | } | |
ad7ee8a2 CF |
5013 | } |
5014 | ||
b89d9c98 RH |
5015 | /* |
5016 | * Rotate right into flags | |
5017 | * 31 30 29 21 15 10 5 4 0 | |
5018 | * +--+--+--+-----------------+--------+-----------+------+--+------+ | |
5019 | * |sf|op| S| 1 1 0 1 0 0 0 0 | imm6 | 0 0 0 0 1 | Rn |o2| mask | | |
5020 | * +--+--+--+-----------------+--------+-----------+------+--+------+ | |
5021 | */ | |
5022 | static void disas_rotate_right_into_flags(DisasContext *s, uint32_t insn) | |
5023 | { | |
5024 | int mask = extract32(insn, 0, 4); | |
5025 | int o2 = extract32(insn, 4, 1); | |
5026 | int rn = extract32(insn, 5, 5); | |
5027 | int imm6 = extract32(insn, 15, 6); | |
5028 | int sf_op_s = extract32(insn, 29, 3); | |
5029 | TCGv_i64 tcg_rn; | |
5030 | TCGv_i32 nzcv; | |
5031 | ||
5032 | if (sf_op_s != 5 || o2 != 0 || !dc_isar_feature(aa64_condm_4, s)) { | |
5033 | unallocated_encoding(s); | |
5034 | return; | |
5035 | } | |
5036 | ||
5037 | tcg_rn = read_cpu_reg(s, rn, 1); | |
5038 | tcg_gen_rotri_i64(tcg_rn, tcg_rn, imm6); | |
5039 | ||
5040 | nzcv = tcg_temp_new_i32(); | |
5041 | tcg_gen_extrl_i64_i32(nzcv, tcg_rn); | |
5042 | ||
5043 | if (mask & 8) { /* N */ | |
5044 | tcg_gen_shli_i32(cpu_NF, nzcv, 31 - 3); | |
5045 | } | |
5046 | if (mask & 4) { /* Z */ | |
5047 | tcg_gen_not_i32(cpu_ZF, nzcv); | |
5048 | tcg_gen_andi_i32(cpu_ZF, cpu_ZF, 4); | |
5049 | } | |
5050 | if (mask & 2) { /* C */ | |
5051 | tcg_gen_extract_i32(cpu_CF, nzcv, 1, 1); | |
5052 | } | |
5053 | if (mask & 1) { /* V */ | |
5054 | tcg_gen_shli_i32(cpu_VF, nzcv, 31 - 0); | |
5055 | } | |
5056 | ||
5057 | tcg_temp_free_i32(nzcv); | |
5058 | } | |
5059 | ||
5060 | /* | |
5061 | * Evaluate into flags | |
5062 | * 31 30 29 21 15 14 10 5 4 0 | |
5063 | * +--+--+--+-----------------+---------+----+---------+------+--+------+ | |
5064 | * |sf|op| S| 1 1 0 1 0 0 0 0 | opcode2 | sz | 0 0 1 0 | Rn |o3| mask | | |
5065 | * +--+--+--+-----------------+---------+----+---------+------+--+------+ | |
5066 | */ | |
5067 | static void disas_evaluate_into_flags(DisasContext *s, uint32_t insn) | |
5068 | { | |
5069 | int o3_mask = extract32(insn, 0, 5); | |
5070 | int rn = extract32(insn, 5, 5); | |
5071 | int o2 = extract32(insn, 15, 6); | |
5072 | int sz = extract32(insn, 14, 1); | |
5073 | int sf_op_s = extract32(insn, 29, 3); | |
5074 | TCGv_i32 tmp; | |
5075 | int shift; | |
5076 | ||
5077 | if (sf_op_s != 1 || o2 != 0 || o3_mask != 0xd || | |
5078 | !dc_isar_feature(aa64_condm_4, s)) { | |
5079 | unallocated_encoding(s); | |
5080 | return; | |
5081 | } | |
5082 | shift = sz ? 16 : 24; /* SETF16 or SETF8 */ | |
5083 | ||
5084 | tmp = tcg_temp_new_i32(); | |
5085 | tcg_gen_extrl_i64_i32(tmp, cpu_reg(s, rn)); | |
5086 | tcg_gen_shli_i32(cpu_NF, tmp, shift); | |
5087 | tcg_gen_shli_i32(cpu_VF, tmp, shift - 1); | |
5088 | tcg_gen_mov_i32(cpu_ZF, cpu_NF); | |
5089 | tcg_gen_xor_i32(cpu_VF, cpu_VF, cpu_NF); | |
5090 | tcg_temp_free_i32(tmp); | |
5091 | } | |
5092 | ||
4ce31af4 | 5093 | /* Conditional compare (immediate / register) |
750813cf CF |
5094 | * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0 |
5095 | * +--+--+--+------------------------+--------+------+----+--+------+--+-----+ | |
5096 | * |sf|op| S| 1 1 0 1 0 0 1 0 |imm5/rm | cond |i/r |o2| Rn |o3|nzcv | | |
5097 | * +--+--+--+------------------------+--------+------+----+--+------+--+-----+ | |
5098 | * [1] y [0] [0] | |
5099 | */ | |
5100 | static void disas_cc(DisasContext *s, uint32_t insn) | |
ad7ee8a2 | 5101 | { |
750813cf | 5102 | unsigned int sf, op, y, cond, rn, nzcv, is_imm; |
7dd03d77 | 5103 | TCGv_i32 tcg_t0, tcg_t1, tcg_t2; |
750813cf | 5104 | TCGv_i64 tcg_tmp, tcg_y, tcg_rn; |
7dd03d77 | 5105 | DisasCompare c; |
ad7ee8a2 | 5106 | |
750813cf CF |
5107 | if (!extract32(insn, 29, 1)) { |
5108 | unallocated_encoding(s); | |
5109 | return; | |
5110 | } | |
5111 | if (insn & (1 << 10 | 1 << 4)) { | |
5112 | unallocated_encoding(s); | |
5113 | return; | |
5114 | } | |
5115 | sf = extract32(insn, 31, 1); | |
5116 | op = extract32(insn, 30, 1); | |
5117 | is_imm = extract32(insn, 11, 1); | |
5118 | y = extract32(insn, 16, 5); /* y = rm (reg) or imm5 (imm) */ | |
5119 | cond = extract32(insn, 12, 4); | |
5120 | rn = extract32(insn, 5, 5); | |
5121 | nzcv = extract32(insn, 0, 4); | |
5122 | ||
7dd03d77 RH |
5123 | /* Set T0 = !COND. */ |
5124 | tcg_t0 = tcg_temp_new_i32(); | |
5125 | arm_test_cc(&c, cond); | |
5126 | tcg_gen_setcondi_i32(tcg_invert_cond(c.cond), tcg_t0, c.value, 0); | |
5127 | arm_free_cc(&c); | |
5128 | ||
5129 | /* Load the arguments for the new comparison. */ | |
750813cf CF |
5130 | if (is_imm) { |
5131 | tcg_y = new_tmp_a64(s); | |
5132 | tcg_gen_movi_i64(tcg_y, y); | |
5133 | } else { | |
5134 | tcg_y = cpu_reg(s, y); | |
5135 | } | |
5136 | tcg_rn = cpu_reg(s, rn); | |
5137 | ||
7dd03d77 | 5138 | /* Set the flags for the new comparison. */ |
750813cf CF |
5139 | tcg_tmp = tcg_temp_new_i64(); |
5140 | if (op) { | |
5141 | gen_sub_CC(sf, tcg_tmp, tcg_rn, tcg_y); | |
5142 | } else { | |
5143 | gen_add_CC(sf, tcg_tmp, tcg_rn, tcg_y); | |
5144 | } | |
5145 | tcg_temp_free_i64(tcg_tmp); | |
5146 | ||
7dd03d77 RH |
5147 | /* If COND was false, force the flags to #nzcv. Compute two masks |
5148 | * to help with this: T1 = (COND ? 0 : -1), T2 = (COND ? -1 : 0). | |
5149 | * For tcg hosts that support ANDC, we can make do with just T1. | |
5150 | * In either case, allow the tcg optimizer to delete any unused mask. | |
5151 | */ | |
5152 | tcg_t1 = tcg_temp_new_i32(); | |
5153 | tcg_t2 = tcg_temp_new_i32(); | |
5154 | tcg_gen_neg_i32(tcg_t1, tcg_t0); | |
5155 | tcg_gen_subi_i32(tcg_t2, tcg_t0, 1); | |
5156 | ||
5157 | if (nzcv & 8) { /* N */ | |
5158 | tcg_gen_or_i32(cpu_NF, cpu_NF, tcg_t1); | |
5159 | } else { | |
5160 | if (TCG_TARGET_HAS_andc_i32) { | |
5161 | tcg_gen_andc_i32(cpu_NF, cpu_NF, tcg_t1); | |
5162 | } else { | |
5163 | tcg_gen_and_i32(cpu_NF, cpu_NF, tcg_t2); | |
5164 | } | |
5165 | } | |
5166 | if (nzcv & 4) { /* Z */ | |
5167 | if (TCG_TARGET_HAS_andc_i32) { | |
5168 | tcg_gen_andc_i32(cpu_ZF, cpu_ZF, tcg_t1); | |
5169 | } else { | |
5170 | tcg_gen_and_i32(cpu_ZF, cpu_ZF, tcg_t2); | |
5171 | } | |
5172 | } else { | |
5173 | tcg_gen_or_i32(cpu_ZF, cpu_ZF, tcg_t0); | |
5174 | } | |
5175 | if (nzcv & 2) { /* C */ | |
5176 | tcg_gen_or_i32(cpu_CF, cpu_CF, tcg_t0); | |
5177 | } else { | |
5178 | if (TCG_TARGET_HAS_andc_i32) { | |
5179 | tcg_gen_andc_i32(cpu_CF, cpu_CF, tcg_t1); | |
5180 | } else { | |
5181 | tcg_gen_and_i32(cpu_CF, cpu_CF, tcg_t2); | |
5182 | } | |
5183 | } | |
5184 | if (nzcv & 1) { /* V */ | |
5185 | tcg_gen_or_i32(cpu_VF, cpu_VF, tcg_t1); | |
5186 | } else { | |
5187 | if (TCG_TARGET_HAS_andc_i32) { | |
5188 | tcg_gen_andc_i32(cpu_VF, cpu_VF, tcg_t1); | |
5189 | } else { | |
5190 | tcg_gen_and_i32(cpu_VF, cpu_VF, tcg_t2); | |
5191 | } | |
750813cf | 5192 | } |
7dd03d77 RH |
5193 | tcg_temp_free_i32(tcg_t0); |
5194 | tcg_temp_free_i32(tcg_t1); | |
5195 | tcg_temp_free_i32(tcg_t2); | |
ad7ee8a2 CF |
5196 | } |
5197 | ||
4ce31af4 | 5198 | /* Conditional select |
e952d8c7 CF |
5199 | * 31 30 29 28 21 20 16 15 12 11 10 9 5 4 0 |
5200 | * +----+----+---+-----------------+------+------+-----+------+------+ | |
5201 | * | sf | op | S | 1 1 0 1 0 1 0 0 | Rm | cond | op2 | Rn | Rd | | |
5202 | * +----+----+---+-----------------+------+------+-----+------+------+ | |
5203 | */ | |
ad7ee8a2 CF |
5204 | static void disas_cond_select(DisasContext *s, uint32_t insn) |
5205 | { | |
e952d8c7 | 5206 | unsigned int sf, else_inv, rm, cond, else_inc, rn, rd; |
259cb684 RH |
5207 | TCGv_i64 tcg_rd, zero; |
5208 | DisasCompare64 c; | |
e952d8c7 CF |
5209 | |
5210 | if (extract32(insn, 29, 1) || extract32(insn, 11, 1)) { | |
5211 | /* S == 1 or op2<1> == 1 */ | |
5212 | unallocated_encoding(s); | |
5213 | return; | |
5214 | } | |
5215 | sf = extract32(insn, 31, 1); | |
5216 | else_inv = extract32(insn, 30, 1); | |
5217 | rm = extract32(insn, 16, 5); | |
5218 | cond = extract32(insn, 12, 4); | |
5219 | else_inc = extract32(insn, 10, 1); | |
5220 | rn = extract32(insn, 5, 5); | |
5221 | rd = extract32(insn, 0, 5); | |
5222 | ||
e952d8c7 CF |
5223 | tcg_rd = cpu_reg(s, rd); |
5224 | ||
259cb684 RH |
5225 | a64_test_cc(&c, cond); |
5226 | zero = tcg_const_i64(0); | |
e952d8c7 | 5227 | |
259cb684 RH |
5228 | if (rn == 31 && rm == 31 && (else_inc ^ else_inv)) { |
5229 | /* CSET & CSETM. */ | |
5230 | tcg_gen_setcond_i64(tcg_invert_cond(c.cond), tcg_rd, c.value, zero); | |
5231 | if (else_inv) { | |
5232 | tcg_gen_neg_i64(tcg_rd, tcg_rd); | |
5233 | } | |
5234 | } else { | |
5235 | TCGv_i64 t_true = cpu_reg(s, rn); | |
5236 | TCGv_i64 t_false = read_cpu_reg(s, rm, 1); | |
e952d8c7 | 5237 | if (else_inv && else_inc) { |
259cb684 | 5238 | tcg_gen_neg_i64(t_false, t_false); |
e952d8c7 | 5239 | } else if (else_inv) { |
259cb684 | 5240 | tcg_gen_not_i64(t_false, t_false); |
e952d8c7 | 5241 | } else if (else_inc) { |
259cb684 | 5242 | tcg_gen_addi_i64(t_false, t_false, 1); |
e952d8c7 | 5243 | } |
259cb684 RH |
5244 | tcg_gen_movcond_i64(c.cond, tcg_rd, c.value, zero, t_true, t_false); |
5245 | } | |
5246 | ||
5247 | tcg_temp_free_i64(zero); | |
5248 | a64_free_cc(&c); | |
5249 | ||
5250 | if (!sf) { | |
5251 | tcg_gen_ext32u_i64(tcg_rd, tcg_rd); | |
e952d8c7 | 5252 | } |
ad7ee8a2 CF |
5253 | } |
5254 | ||
680ead21 CF |
5255 | static void handle_clz(DisasContext *s, unsigned int sf, |
5256 | unsigned int rn, unsigned int rd) | |
5257 | { | |
5258 | TCGv_i64 tcg_rd, tcg_rn; | |
5259 | tcg_rd = cpu_reg(s, rd); | |
5260 | tcg_rn = cpu_reg(s, rn); | |
5261 | ||
5262 | if (sf) { | |
7539a012 | 5263 | tcg_gen_clzi_i64(tcg_rd, tcg_rn, 64); |
680ead21 CF |
5264 | } else { |
5265 | TCGv_i32 tcg_tmp32 = tcg_temp_new_i32(); | |
ecc7b3aa | 5266 | tcg_gen_extrl_i64_i32(tcg_tmp32, tcg_rn); |
7539a012 | 5267 | tcg_gen_clzi_i32(tcg_tmp32, tcg_tmp32, 32); |
680ead21 CF |
5268 | tcg_gen_extu_i32_i64(tcg_rd, tcg_tmp32); |
5269 | tcg_temp_free_i32(tcg_tmp32); | |
5270 | } | |
5271 | } | |
5272 | ||
e80c5020 CF |
5273 | static void handle_cls(DisasContext *s, unsigned int sf, |
5274 | unsigned int rn, unsigned int rd) | |
5275 | { | |
5276 | TCGv_i64 tcg_rd, tcg_rn; | |
5277 | tcg_rd = cpu_reg(s, rd); | |
5278 | tcg_rn = cpu_reg(s, rn); | |
5279 | ||
5280 | if (sf) { | |
bc21dbcc | 5281 | tcg_gen_clrsb_i64(tcg_rd, tcg_rn); |
e80c5020 CF |
5282 | } else { |
5283 | TCGv_i32 tcg_tmp32 = tcg_temp_new_i32(); | |
ecc7b3aa | 5284 | tcg_gen_extrl_i64_i32(tcg_tmp32, tcg_rn); |
bc21dbcc | 5285 | tcg_gen_clrsb_i32(tcg_tmp32, tcg_tmp32); |
e80c5020 CF |
5286 | tcg_gen_extu_i32_i64(tcg_rd, tcg_tmp32); |
5287 | tcg_temp_free_i32(tcg_tmp32); | |
5288 | } | |
5289 | } | |
5290 | ||
82e14b02 AG |
5291 | static void handle_rbit(DisasContext *s, unsigned int sf, |
5292 | unsigned int rn, unsigned int rd) | |
5293 | { | |
5294 | TCGv_i64 tcg_rd, tcg_rn; | |
5295 | tcg_rd = cpu_reg(s, rd); | |
5296 | tcg_rn = cpu_reg(s, rn); | |
5297 | ||
5298 | if (sf) { | |
5299 | gen_helper_rbit64(tcg_rd, tcg_rn); | |
5300 | } else { | |
5301 | TCGv_i32 tcg_tmp32 = tcg_temp_new_i32(); | |
ecc7b3aa | 5302 | tcg_gen_extrl_i64_i32(tcg_tmp32, tcg_rn); |
82e14b02 AG |
5303 | gen_helper_rbit(tcg_tmp32, tcg_tmp32); |
5304 | tcg_gen_extu_i32_i64(tcg_rd, tcg_tmp32); | |
5305 | tcg_temp_free_i32(tcg_tmp32); | |
5306 | } | |
5307 | } | |
5308 | ||
4ce31af4 | 5309 | /* REV with sf==1, opcode==3 ("REV64") */ |
45323209 CF |
5310 | static void handle_rev64(DisasContext *s, unsigned int sf, |
5311 | unsigned int rn, unsigned int rd) | |
5312 | { | |
5313 | if (!sf) { | |
5314 | unallocated_encoding(s); | |
5315 | return; | |
5316 | } | |
5317 | tcg_gen_bswap64_i64(cpu_reg(s, rd), cpu_reg(s, rn)); | |
5318 | } | |
5319 | ||
4ce31af4 PM |
5320 | /* REV with sf==0, opcode==2 |
5321 | * REV32 (sf==1, opcode==2) | |
45323209 CF |
5322 | */ |
5323 | static void handle_rev32(DisasContext *s, unsigned int sf, | |
5324 | unsigned int rn, unsigned int rd) | |
5325 | { | |
5326 | TCGv_i64 tcg_rd = cpu_reg(s, rd); | |
5327 | ||
5328 | if (sf) { | |
5329 | TCGv_i64 tcg_tmp = tcg_temp_new_i64(); | |
5330 | TCGv_i64 tcg_rn = read_cpu_reg(s, rn, sf); | |
5331 | ||
5332 | /* bswap32_i64 requires zero high word */ | |
5333 | tcg_gen_ext32u_i64(tcg_tmp, tcg_rn); | |
5334 | tcg_gen_bswap32_i64(tcg_rd, tcg_tmp); | |
5335 | tcg_gen_shri_i64(tcg_tmp, tcg_rn, 32); | |
5336 | tcg_gen_bswap32_i64(tcg_tmp, tcg_tmp); | |
5337 | tcg_gen_concat32_i64(tcg_rd, tcg_rd, tcg_tmp); | |
5338 | ||
5339 | tcg_temp_free_i64(tcg_tmp); | |
5340 | } else { | |
5341 | tcg_gen_ext32u_i64(tcg_rd, cpu_reg(s, rn)); | |
5342 | tcg_gen_bswap32_i64(tcg_rd, tcg_rd); | |
5343 | } | |
5344 | } | |
5345 | ||
4ce31af4 | 5346 | /* REV16 (opcode==1) */ |
45323209 CF |
5347 | static void handle_rev16(DisasContext *s, unsigned int sf, |
5348 | unsigned int rn, unsigned int rd) | |
5349 | { | |
5350 | TCGv_i64 tcg_rd = cpu_reg(s, rd); | |
5351 | TCGv_i64 tcg_tmp = tcg_temp_new_i64(); | |
5352 | TCGv_i64 tcg_rn = read_cpu_reg(s, rn, sf); | |
abb1066d | 5353 | TCGv_i64 mask = tcg_const_i64(sf ? 0x00ff00ff00ff00ffull : 0x00ff00ff); |
45323209 | 5354 | |
abb1066d RH |
5355 | tcg_gen_shri_i64(tcg_tmp, tcg_rn, 8); |
5356 | tcg_gen_and_i64(tcg_rd, tcg_rn, mask); | |
5357 | tcg_gen_and_i64(tcg_tmp, tcg_tmp, mask); | |
5358 | tcg_gen_shli_i64(tcg_rd, tcg_rd, 8); | |
5359 | tcg_gen_or_i64(tcg_rd, tcg_rd, tcg_tmp); | |
45323209 | 5360 | |
e4256c3c | 5361 | tcg_temp_free_i64(mask); |
45323209 CF |
5362 | tcg_temp_free_i64(tcg_tmp); |
5363 | } | |
5364 | ||
4ce31af4 | 5365 | /* Data-processing (1 source) |
680ead21 CF |
5366 | * 31 30 29 28 21 20 16 15 10 9 5 4 0 |
5367 | * +----+---+---+-----------------+---------+--------+------+------+ | |
5368 | * | sf | 1 | S | 1 1 0 1 0 1 1 0 | opcode2 | opcode | Rn | Rd | | |
5369 | * +----+---+---+-----------------+---------+--------+------+------+ | |
5370 | */ | |
ad7ee8a2 CF |
5371 | static void disas_data_proc_1src(DisasContext *s, uint32_t insn) |
5372 | { | |
18de2813 | 5373 | unsigned int sf, opcode, opcode2, rn, rd; |
95ebd99d | 5374 | TCGv_i64 tcg_rd; |
680ead21 | 5375 | |
18de2813 | 5376 | if (extract32(insn, 29, 1)) { |
680ead21 CF |
5377 | unallocated_encoding(s); |
5378 | return; | |
5379 | } | |
5380 | ||
5381 | sf = extract32(insn, 31, 1); | |
5382 | opcode = extract32(insn, 10, 6); | |
18de2813 | 5383 | opcode2 = extract32(insn, 16, 5); |
680ead21 CF |
5384 | rn = extract32(insn, 5, 5); |
5385 | rd = extract32(insn, 0, 5); | |
5386 | ||
18de2813 RH |
5387 | #define MAP(SF, O2, O1) ((SF) | (O1 << 1) | (O2 << 7)) |
5388 | ||
5389 | switch (MAP(sf, opcode2, opcode)) { | |
5390 | case MAP(0, 0x00, 0x00): /* RBIT */ | |
5391 | case MAP(1, 0x00, 0x00): | |
82e14b02 AG |
5392 | handle_rbit(s, sf, rn, rd); |
5393 | break; | |
18de2813 RH |
5394 | case MAP(0, 0x00, 0x01): /* REV16 */ |
5395 | case MAP(1, 0x00, 0x01): | |
45323209 CF |
5396 | handle_rev16(s, sf, rn, rd); |
5397 | break; | |
18de2813 RH |
5398 | case MAP(0, 0x00, 0x02): /* REV/REV32 */ |
5399 | case MAP(1, 0x00, 0x02): | |
45323209 CF |
5400 | handle_rev32(s, sf, rn, rd); |
5401 | break; | |
18de2813 | 5402 | case MAP(1, 0x00, 0x03): /* REV64 */ |
45323209 | 5403 | handle_rev64(s, sf, rn, rd); |
680ead21 | 5404 | break; |
18de2813 RH |
5405 | case MAP(0, 0x00, 0x04): /* CLZ */ |
5406 | case MAP(1, 0x00, 0x04): | |
680ead21 CF |
5407 | handle_clz(s, sf, rn, rd); |
5408 | break; | |
18de2813 RH |
5409 | case MAP(0, 0x00, 0x05): /* CLS */ |
5410 | case MAP(1, 0x00, 0x05): | |
e80c5020 | 5411 | handle_cls(s, sf, rn, rd); |
680ead21 | 5412 | break; |
95ebd99d RH |
5413 | case MAP(1, 0x01, 0x00): /* PACIA */ |
5414 | if (s->pauth_active) { | |
5415 | tcg_rd = cpu_reg(s, rd); | |
5416 | gen_helper_pacia(tcg_rd, cpu_env, tcg_rd, cpu_reg_sp(s, rn)); | |
5417 | } else if (!dc_isar_feature(aa64_pauth, s)) { | |
5418 | goto do_unallocated; | |
5419 | } | |
5420 | break; | |
5421 | case MAP(1, 0x01, 0x01): /* PACIB */ | |
5422 | if (s->pauth_active) { | |
5423 | tcg_rd = cpu_reg(s, rd); | |
5424 | gen_helper_pacib(tcg_rd, cpu_env, tcg_rd, cpu_reg_sp(s, rn)); | |
5425 | } else if (!dc_isar_feature(aa64_pauth, s)) { | |
5426 | goto do_unallocated; | |
5427 | } | |
5428 | break; | |
5429 | case MAP(1, 0x01, 0x02): /* PACDA */ | |
5430 | if (s->pauth_active) { | |
5431 | tcg_rd = cpu_reg(s, rd); | |
5432 | gen_helper_pacda(tcg_rd, cpu_env, tcg_rd, cpu_reg_sp(s, rn)); | |
5433 | } else if (!dc_isar_feature(aa64_pauth, s)) { | |
5434 | goto do_unallocated; | |
5435 | } | |
5436 | break; | |
5437 | case MAP(1, 0x01, 0x03): /* PACDB */ | |
5438 | if (s->pauth_active) { | |
5439 | tcg_rd = cpu_reg(s, rd); | |
5440 | gen_helper_pacdb(tcg_rd, cpu_env, tcg_rd, cpu_reg_sp(s, rn)); | |
5441 | } else if (!dc_isar_feature(aa64_pauth, s)) { | |
5442 | goto do_unallocated; | |
5443 | } | |
5444 | break; | |
5445 | case MAP(1, 0x01, 0x04): /* AUTIA */ | |
5446 | if (s->pauth_active) { | |
5447 | tcg_rd = cpu_reg(s, rd); | |
5448 | gen_helper_autia(tcg_rd, cpu_env, tcg_rd, cpu_reg_sp(s, rn)); | |
5449 | } else if (!dc_isar_feature(aa64_pauth, s)) { | |
5450 | goto do_unallocated; | |
5451 | } | |
5452 | break; | |
5453 | case MAP(1, 0x01, 0x05): /* AUTIB */ | |
5454 | if (s->pauth_active) { | |
5455 | tcg_rd = cpu_reg(s, rd); | |
5456 | gen_helper_autib(tcg_rd, cpu_env, tcg_rd, cpu_reg_sp(s, rn)); | |
5457 | } else if (!dc_isar_feature(aa64_pauth, s)) { | |
5458 | goto do_unallocated; | |
5459 | } | |
5460 | break; | |
5461 | case MAP(1, 0x01, 0x06): /* AUTDA */ | |
5462 | if (s->pauth_active) { | |
5463 | tcg_rd = cpu_reg(s, rd); | |
5464 | gen_helper_autda(tcg_rd, cpu_env, tcg_rd, cpu_reg_sp(s, rn)); | |
5465 | } else if (!dc_isar_feature(aa64_pauth, s)) { | |
5466 | goto do_unallocated; | |
5467 | } | |
5468 | break; | |
5469 | case MAP(1, 0x01, 0x07): /* AUTDB */ | |
5470 | if (s->pauth_active) { | |
5471 | tcg_rd = cpu_reg(s, rd); | |
5472 | gen_helper_autdb(tcg_rd, cpu_env, tcg_rd, cpu_reg_sp(s, rn)); | |
5473 | } else if (!dc_isar_feature(aa64_pauth, s)) { | |
5474 | goto do_unallocated; | |
5475 | } | |
5476 | break; | |
5477 | case MAP(1, 0x01, 0x08): /* PACIZA */ | |
5478 | if (!dc_isar_feature(aa64_pauth, s) || rn != 31) { | |
5479 | goto do_unallocated; | |
5480 | } else if (s->pauth_active) { | |
5481 | tcg_rd = cpu_reg(s, rd); | |
5482 | gen_helper_pacia(tcg_rd, cpu_env, tcg_rd, new_tmp_a64_zero(s)); | |
5483 | } | |
5484 | break; | |
5485 | case MAP(1, 0x01, 0x09): /* PACIZB */ | |
5486 | if (!dc_isar_feature(aa64_pauth, s) || rn != 31) { | |
5487 | goto do_unallocated; | |
5488 | } else if (s->pauth_active) { | |
5489 | tcg_rd = cpu_reg(s, rd); | |
5490 | gen_helper_pacib(tcg_rd, cpu_env, tcg_rd, new_tmp_a64_zero(s)); | |
5491 | } | |
5492 | break; | |
5493 | case MAP(1, 0x01, 0x0a): /* PACDZA */ | |
5494 | if (!dc_isar_feature(aa64_pauth, s) || rn != 31) { | |
5495 | goto do_unallocated; | |
5496 | } else if (s->pauth_active) { | |
5497 | tcg_rd = cpu_reg(s, rd); | |
5498 | gen_helper_pacda(tcg_rd, cpu_env, tcg_rd, new_tmp_a64_zero(s)); | |
5499 | } | |
5500 | break; | |
5501 | case MAP(1, 0x01, 0x0b): /* PACDZB */ | |
5502 | if (!dc_isar_feature(aa64_pauth, s) || rn != 31) { | |
5503 | goto do_unallocated; | |
5504 | } else if (s->pauth_active) { | |
5505 | tcg_rd = cpu_reg(s, rd); | |
5506 | gen_helper_pacdb(tcg_rd, cpu_env, tcg_rd, new_tmp_a64_zero(s)); | |
5507 | } | |
5508 | break; | |
5509 | case MAP(1, 0x01, 0x0c): /* AUTIZA */ | |
5510 | if (!dc_isar_feature(aa64_pauth, s) || rn != 31) { | |
5511 | goto do_unallocated; | |
5512 | } else if (s->pauth_active) { | |
5513 | tcg_rd = cpu_reg(s, rd); | |
5514 | gen_helper_autia(tcg_rd, cpu_env, tcg_rd, new_tmp_a64_zero(s)); | |
5515 | } | |
5516 | break; | |
5517 | case MAP(1, 0x01, 0x0d): /* AUTIZB */ | |
5518 | if (!dc_isar_feature(aa64_pauth, s) || rn != 31) { | |
5519 | goto do_unallocated; | |
5520 | } else if (s->pauth_active) { | |
5521 | tcg_rd = cpu_reg(s, rd); | |
5522 | gen_helper_autib(tcg_rd, cpu_env, tcg_rd, new_tmp_a64_zero(s)); | |
5523 | } | |
5524 | break; | |
5525 | case MAP(1, 0x01, 0x0e): /* AUTDZA */ | |
5526 | if (!dc_isar_feature(aa64_pauth, s) || rn != 31) { | |
5527 | goto do_unallocated; | |
5528 | } else if (s->pauth_active) { | |
5529 | tcg_rd = cpu_reg(s, rd); | |
5530 | gen_helper_autda(tcg_rd, cpu_env, tcg_rd, new_tmp_a64_zero(s)); | |
5531 | } | |
5532 | break; | |
5533 | case MAP(1, 0x01, 0x0f): /* AUTDZB */ | |
5534 | if (!dc_isar_feature(aa64_pauth, s) || rn != 31) { | |
5535 | goto do_unallocated; | |
5536 | } else if (s->pauth_active) { | |
5537 | tcg_rd = cpu_reg(s, rd); | |
5538 | gen_helper_autdb(tcg_rd, cpu_env, tcg_rd, new_tmp_a64_zero(s)); | |
5539 | } | |
5540 | break; | |
5541 | case MAP(1, 0x01, 0x10): /* XPACI */ | |
5542 | if (!dc_isar_feature(aa64_pauth, s) || rn != 31) { | |
5543 | goto do_unallocated; | |
5544 | } else if (s->pauth_active) { | |
5545 | tcg_rd = cpu_reg(s, rd); | |
5546 | gen_helper_xpaci(tcg_rd, cpu_env, tcg_rd); | |
5547 | } | |
5548 | break; | |
5549 | case MAP(1, 0x01, 0x11): /* XPACD */ | |
5550 | if (!dc_isar_feature(aa64_pauth, s) || rn != 31) { | |
5551 | goto do_unallocated; | |
5552 | } else if (s->pauth_active) { | |
5553 | tcg_rd = cpu_reg(s, rd); | |
5554 | gen_helper_xpacd(tcg_rd, cpu_env, tcg_rd); | |
5555 | } | |
5556 | break; | |
18de2813 | 5557 | default: |
95ebd99d | 5558 | do_unallocated: |
18de2813 RH |
5559 | unallocated_encoding(s); |
5560 | break; | |
680ead21 | 5561 | } |
18de2813 RH |
5562 | |
5563 | #undef MAP | |
ad7ee8a2 CF |
5564 | } |
5565 | ||
8220e911 AG |
5566 | static void handle_div(DisasContext *s, bool is_signed, unsigned int sf, |
5567 | unsigned int rm, unsigned int rn, unsigned int rd) | |
5568 | { | |
5569 | TCGv_i64 tcg_n, tcg_m, tcg_rd; | |
5570 | tcg_rd = cpu_reg(s, rd); | |
5571 | ||
5572 | if (!sf && is_signed) { | |
5573 | tcg_n = new_tmp_a64(s); | |
5574 | tcg_m = new_tmp_a64(s); | |
5575 | tcg_gen_ext32s_i64(tcg_n, cpu_reg(s, rn)); | |
5576 | tcg_gen_ext32s_i64(tcg_m, cpu_reg(s, rm)); | |
5577 | } else { | |
5578 | tcg_n = read_cpu_reg(s, rn, sf); | |
5579 | tcg_m = read_cpu_reg(s, rm, sf); | |
5580 | } | |
5581 | ||
5582 | if (is_signed) { | |
5583 | gen_helper_sdiv64(tcg_rd, tcg_n, tcg_m); | |
5584 | } else { | |
5585 | gen_helper_udiv64(tcg_rd, tcg_n, tcg_m); | |
5586 | } | |
5587 | ||
5588 | if (!sf) { /* zero extend final result */ | |
5589 | tcg_gen_ext32u_i64(tcg_rd, tcg_rd); | |
5590 | } | |
5591 | } | |
5592 | ||
4ce31af4 | 5593 | /* LSLV, LSRV, ASRV, RORV */ |
6c1adc91 AG |
5594 | static void handle_shift_reg(DisasContext *s, |
5595 | enum a64_shift_type shift_type, unsigned int sf, | |
5596 | unsigned int rm, unsigned int rn, unsigned int rd) | |
5597 | { | |
5598 | TCGv_i64 tcg_shift = tcg_temp_new_i64(); | |
5599 | TCGv_i64 tcg_rd = cpu_reg(s, rd); | |
5600 | TCGv_i64 tcg_rn = read_cpu_reg(s, rn, sf); | |
5601 | ||
5602 | tcg_gen_andi_i64(tcg_shift, cpu_reg(s, rm), sf ? 63 : 31); | |
5603 | shift_reg(tcg_rd, tcg_rn, sf, shift_type, tcg_shift); | |
5604 | tcg_temp_free_i64(tcg_shift); | |
5605 | } | |
5606 | ||
130f2e7d PM |
5607 | /* CRC32[BHWX], CRC32C[BHWX] */ |
5608 | static void handle_crc32(DisasContext *s, | |
5609 | unsigned int sf, unsigned int sz, bool crc32c, | |
5610 | unsigned int rm, unsigned int rn, unsigned int rd) | |
5611 | { | |
5612 | TCGv_i64 tcg_acc, tcg_val; | |
5613 | TCGv_i32 tcg_bytes; | |
5614 | ||
962fcbf2 | 5615 | if (!dc_isar_feature(aa64_crc32, s) |
130f2e7d PM |
5616 | || (sf == 1 && sz != 3) |
5617 | || (sf == 0 && sz == 3)) { | |
5618 | unallocated_encoding(s); | |
5619 | return; | |
5620 | } | |
5621 | ||
5622 | if (sz == 3) { | |
5623 | tcg_val = cpu_reg(s, rm); | |
5624 | } else { | |
5625 | uint64_t mask; | |
5626 | switch (sz) { | |
5627 | case 0: | |
5628 | mask = 0xFF; | |
5629 | break; | |
5630 | case 1: | |
5631 | mask = 0xFFFF; | |
5632 | break; | |
5633 | case 2: | |
5634 | mask = 0xFFFFFFFF; | |
5635 | break; | |
5636 | default: | |
5637 | g_assert_not_reached(); | |
5638 | } | |
5639 | tcg_val = new_tmp_a64(s); | |
5640 | tcg_gen_andi_i64(tcg_val, cpu_reg(s, rm), mask); | |
5641 | } | |
5642 | ||
5643 | tcg_acc = cpu_reg(s, rn); | |
5644 | tcg_bytes = tcg_const_i32(1 << sz); | |
5645 | ||
5646 | if (crc32c) { | |
5647 | gen_helper_crc32c_64(cpu_reg(s, rd), tcg_acc, tcg_val, tcg_bytes); | |
5648 | } else { | |
5649 | gen_helper_crc32_64(cpu_reg(s, rd), tcg_acc, tcg_val, tcg_bytes); | |
5650 | } | |
5651 | ||
5652 | tcg_temp_free_i32(tcg_bytes); | |
5653 | } | |
5654 | ||
4ce31af4 | 5655 | /* Data-processing (2 source) |
8220e911 AG |
5656 | * 31 30 29 28 21 20 16 15 10 9 5 4 0 |
5657 | * +----+---+---+-----------------+------+--------+------+------+ | |
5658 | * | sf | 0 | S | 1 1 0 1 0 1 1 0 | Rm | opcode | Rn | Rd | | |
5659 | * +----+---+---+-----------------+------+--------+------+------+ | |
5660 | */ | |
ad7ee8a2 CF |
5661 | static void disas_data_proc_2src(DisasContext *s, uint32_t insn) |
5662 | { | |
dad3015f | 5663 | unsigned int sf, rm, opcode, rn, rd, setflag; |
8220e911 | 5664 | sf = extract32(insn, 31, 1); |
dad3015f | 5665 | setflag = extract32(insn, 29, 1); |
8220e911 AG |
5666 | rm = extract32(insn, 16, 5); |
5667 | opcode = extract32(insn, 10, 6); | |
5668 | rn = extract32(insn, 5, 5); | |
5669 | rd = extract32(insn, 0, 5); | |
5670 | ||
dad3015f | 5671 | if (setflag && opcode != 0) { |
8220e911 AG |
5672 | unallocated_encoding(s); |
5673 | return; | |
5674 | } | |
5675 | ||
5676 | switch (opcode) { | |
dad3015f RH |
5677 | case 0: /* SUBP(S) */ |
5678 | if (sf == 0 || !dc_isar_feature(aa64_mte_insn_reg, s)) { | |
5679 | goto do_unallocated; | |
5680 | } else { | |
5681 | TCGv_i64 tcg_n, tcg_m, tcg_d; | |
5682 | ||
5683 | tcg_n = read_cpu_reg_sp(s, rn, true); | |
5684 | tcg_m = read_cpu_reg_sp(s, rm, true); | |
5685 | tcg_gen_sextract_i64(tcg_n, tcg_n, 0, 56); | |
5686 | tcg_gen_sextract_i64(tcg_m, tcg_m, 0, 56); | |
5687 | tcg_d = cpu_reg(s, rd); | |
5688 | ||
5689 | if (setflag) { | |
5690 | gen_sub_CC(true, tcg_d, tcg_n, tcg_m); | |
5691 | } else { | |
5692 | tcg_gen_sub_i64(tcg_d, tcg_n, tcg_m); | |
5693 | } | |
5694 | } | |
5695 | break; | |
8220e911 AG |
5696 | case 2: /* UDIV */ |
5697 | handle_div(s, false, sf, rm, rn, rd); | |
5698 | break; | |
5699 | case 3: /* SDIV */ | |
5700 | handle_div(s, true, sf, rm, rn, rd); | |
5701 | break; | |
da54941f RH |
5702 | case 4: /* IRG */ |
5703 | if (sf == 0 || !dc_isar_feature(aa64_mte_insn_reg, s)) { | |
5704 | goto do_unallocated; | |
5705 | } | |
5706 | if (s->ata) { | |
5707 | gen_helper_irg(cpu_reg_sp(s, rd), cpu_env, | |
5708 | cpu_reg_sp(s, rn), cpu_reg(s, rm)); | |
5709 | } else { | |
5710 | gen_address_with_allocation_tag0(cpu_reg_sp(s, rd), | |
5711 | cpu_reg_sp(s, rn)); | |
5712 | } | |
5713 | break; | |
438efea0 RH |
5714 | case 5: /* GMI */ |
5715 | if (sf == 0 || !dc_isar_feature(aa64_mte_insn_reg, s)) { | |
5716 | goto do_unallocated; | |
5717 | } else { | |
5718 | TCGv_i64 t1 = tcg_const_i64(1); | |
5719 | TCGv_i64 t2 = tcg_temp_new_i64(); | |
5720 | ||
5721 | tcg_gen_extract_i64(t2, cpu_reg_sp(s, rn), 56, 4); | |
5722 | tcg_gen_shl_i64(t1, t1, t2); | |
5723 | tcg_gen_or_i64(cpu_reg(s, rd), cpu_reg(s, rm), t1); | |
5724 | ||
5725 | tcg_temp_free_i64(t1); | |
5726 | tcg_temp_free_i64(t2); | |
5727 | } | |
5728 | break; | |
8220e911 | 5729 | case 8: /* LSLV */ |
6c1adc91 AG |
5730 | handle_shift_reg(s, A64_SHIFT_TYPE_LSL, sf, rm, rn, rd); |
5731 | break; | |
8220e911 | 5732 | case 9: /* LSRV */ |
6c1adc91 AG |
5733 | handle_shift_reg(s, A64_SHIFT_TYPE_LSR, sf, rm, rn, rd); |
5734 | break; | |
8220e911 | 5735 | case 10: /* ASRV */ |
6c1adc91 AG |
5736 | handle_shift_reg(s, A64_SHIFT_TYPE_ASR, sf, rm, rn, rd); |
5737 | break; | |
8220e911 | 5738 | case 11: /* RORV */ |
6c1adc91 AG |
5739 | handle_shift_reg(s, A64_SHIFT_TYPE_ROR, sf, rm, rn, rd); |
5740 | break; | |
b6342a9f RH |
5741 | case 12: /* PACGA */ |
5742 | if (sf == 0 || !dc_isar_feature(aa64_pauth, s)) { | |
5743 | goto do_unallocated; | |
5744 | } | |
5745 | gen_helper_pacga(cpu_reg(s, rd), cpu_env, | |
5746 | cpu_reg(s, rn), cpu_reg_sp(s, rm)); | |
5747 | break; | |
8220e911 AG |
5748 | case 16: |
5749 | case 17: | |
5750 | case 18: | |
5751 | case 19: | |
5752 | case 20: | |
5753 | case 21: | |
5754 | case 22: | |
5755 | case 23: /* CRC32 */ | |
130f2e7d PM |
5756 | { |
5757 | int sz = extract32(opcode, 0, 2); | |
5758 | bool crc32c = extract32(opcode, 2, 1); | |
5759 | handle_crc32(s, sf, sz, crc32c, rm, rn, rd); | |
8220e911 | 5760 | break; |
130f2e7d | 5761 | } |
8220e911 | 5762 | default: |
b6342a9f | 5763 | do_unallocated: |
8220e911 AG |
5764 | unallocated_encoding(s); |
5765 | break; | |
5766 | } | |
ad7ee8a2 CF |
5767 | } |
5768 | ||
2fba34f7 RH |
5769 | /* |
5770 | * Data processing - register | |
5771 | * 31 30 29 28 25 21 20 16 10 0 | |
5772 | * +--+---+--+---+-------+-----+-------+-------+---------+ | |
5773 | * | |op0| |op1| 1 0 1 | op2 | | op3 | | | |
5774 | * +--+---+--+---+-------+-----+-------+-------+---------+ | |
5775 | */ | |
ad7ee8a2 CF |
5776 | static void disas_data_proc_reg(DisasContext *s, uint32_t insn) |
5777 | { | |
2fba34f7 RH |
5778 | int op0 = extract32(insn, 30, 1); |
5779 | int op1 = extract32(insn, 28, 1); | |
5780 | int op2 = extract32(insn, 21, 4); | |
5781 | int op3 = extract32(insn, 10, 6); | |
5782 | ||
5783 | if (!op1) { | |
5784 | if (op2 & 8) { | |
5785 | if (op2 & 1) { | |
5786 | /* Add/sub (extended register) */ | |
5787 | disas_add_sub_ext_reg(s, insn); | |
5788 | } else { | |
5789 | /* Add/sub (shifted register) */ | |
5790 | disas_add_sub_reg(s, insn); | |
5791 | } | |
ad7ee8a2 | 5792 | } else { |
2fba34f7 RH |
5793 | /* Logical (shifted register) */ |
5794 | disas_logic_reg(s, insn); | |
ad7ee8a2 | 5795 | } |
2fba34f7 RH |
5796 | return; |
5797 | } | |
5798 | ||
5799 | switch (op2) { | |
5800 | case 0x0: | |
5801 | switch (op3) { | |
5802 | case 0x00: /* Add/subtract (with carry) */ | |
ad7ee8a2 CF |
5803 | disas_adc_sbc(s, insn); |
5804 | break; | |
2fba34f7 | 5805 | |
b89d9c98 RH |
5806 | case 0x01: /* Rotate right into flags */ |
5807 | case 0x21: | |
5808 | disas_rotate_right_into_flags(s, insn); | |
5809 | break; | |
5810 | ||
5811 | case 0x02: /* Evaluate into flags */ | |
5812 | case 0x12: | |
5813 | case 0x22: | |
5814 | case 0x32: | |
5815 | disas_evaluate_into_flags(s, insn); | |
5816 | break; | |
5817 | ||
ad7ee8a2 | 5818 | default: |
2fba34f7 | 5819 | goto do_unallocated; |
ad7ee8a2 CF |
5820 | } |
5821 | break; | |
2fba34f7 RH |
5822 | |
5823 | case 0x2: /* Conditional compare */ | |
5824 | disas_cc(s, insn); /* both imm and reg forms */ | |
5825 | break; | |
5826 | ||
5827 | case 0x4: /* Conditional select */ | |
5828 | disas_cond_select(s, insn); | |
5829 | break; | |
5830 | ||
5831 | case 0x6: /* Data-processing */ | |
5832 | if (op0) { /* (1 source) */ | |
5833 | disas_data_proc_1src(s, insn); | |
5834 | } else { /* (2 source) */ | |
5835 | disas_data_proc_2src(s, insn); | |
5836 | } | |
5837 | break; | |
5838 | case 0x8 ... 0xf: /* (3 source) */ | |
5839 | disas_data_proc_3src(s, insn); | |
5840 | break; | |
5841 | ||
ad7ee8a2 | 5842 | default: |
2fba34f7 | 5843 | do_unallocated: |
ad7ee8a2 CF |
5844 | unallocated_encoding(s); |
5845 | break; | |
5846 | } | |
5847 | } | |
5848 | ||
7a192925 | 5849 | static void handle_fp_compare(DisasContext *s, int size, |
da7dafe7 CF |
5850 | unsigned int rn, unsigned int rm, |
5851 | bool cmp_with_zero, bool signal_all_nans) | |
5852 | { | |
5853 | TCGv_i64 tcg_flags = tcg_temp_new_i64(); | |
7a192925 | 5854 | TCGv_ptr fpst = get_fpstatus_ptr(size == MO_16); |
da7dafe7 | 5855 | |
7a192925 | 5856 | if (size == MO_64) { |
da7dafe7 CF |
5857 | TCGv_i64 tcg_vn, tcg_vm; |
5858 | ||
5859 | tcg_vn = read_fp_dreg(s, rn); | |
5860 | if (cmp_with_zero) { | |
5861 | tcg_vm = tcg_const_i64(0); | |
5862 | } else { | |
5863 | tcg_vm = read_fp_dreg(s, rm); | |
5864 | } | |
5865 | if (signal_all_nans) { | |
5866 | gen_helper_vfp_cmped_a64(tcg_flags, tcg_vn, tcg_vm, fpst); | |
5867 | } else { | |
5868 | gen_helper_vfp_cmpd_a64(tcg_flags, tcg_vn, tcg_vm, fpst); | |
5869 | } | |
5870 | tcg_temp_free_i64(tcg_vn); | |
5871 | tcg_temp_free_i64(tcg_vm); | |
5872 | } else { | |
7a192925 AB |
5873 | TCGv_i32 tcg_vn = tcg_temp_new_i32(); |
5874 | TCGv_i32 tcg_vm = tcg_temp_new_i32(); | |
da7dafe7 | 5875 | |
7a192925 | 5876 | read_vec_element_i32(s, tcg_vn, rn, 0, size); |
da7dafe7 | 5877 | if (cmp_with_zero) { |
7a192925 | 5878 | tcg_gen_movi_i32(tcg_vm, 0); |
da7dafe7 | 5879 | } else { |
7a192925 | 5880 | read_vec_element_i32(s, tcg_vm, rm, 0, size); |
da7dafe7 | 5881 | } |
7a192925 AB |
5882 | |
5883 | switch (size) { | |
5884 | case MO_32: | |
5885 | if (signal_all_nans) { | |
5886 | gen_helper_vfp_cmpes_a64(tcg_flags, tcg_vn, tcg_vm, fpst); | |
5887 | } else { | |
5888 | gen_helper_vfp_cmps_a64(tcg_flags, tcg_vn, tcg_vm, fpst); | |
5889 | } | |
5890 | break; | |
5891 | case MO_16: | |
5892 | if (signal_all_nans) { | |
5893 | gen_helper_vfp_cmpeh_a64(tcg_flags, tcg_vn, tcg_vm, fpst); | |
5894 | } else { | |
5895 | gen_helper_vfp_cmph_a64(tcg_flags, tcg_vn, tcg_vm, fpst); | |
5896 | } | |
5897 | break; | |
5898 | default: | |
5899 | g_assert_not_reached(); | |
da7dafe7 | 5900 | } |
7a192925 | 5901 | |
da7dafe7 CF |
5902 | tcg_temp_free_i32(tcg_vn); |
5903 | tcg_temp_free_i32(tcg_vm); | |
5904 | } | |
5905 | ||
5906 | tcg_temp_free_ptr(fpst); | |
5907 | ||
5908 | gen_set_nzcv(tcg_flags); | |
5909 | ||
5910 | tcg_temp_free_i64(tcg_flags); | |
5911 | } | |
5912 | ||
4ce31af4 | 5913 | /* Floating point compare |
faa0ba46 PM |
5914 | * 31 30 29 28 24 23 22 21 20 16 15 14 13 10 9 5 4 0 |
5915 | * +---+---+---+-----------+------+---+------+-----+---------+------+-------+ | |
5916 | * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | op | 1 0 0 0 | Rn | op2 | | |
5917 | * +---+---+---+-----------+------+---+------+-----+---------+------+-------+ | |
5918 | */ | |
5919 | static void disas_fp_compare(DisasContext *s, uint32_t insn) | |
5920 | { | |
da7dafe7 | 5921 | unsigned int mos, type, rm, op, rn, opc, op2r; |
7a192925 | 5922 | int size; |
da7dafe7 CF |
5923 | |
5924 | mos = extract32(insn, 29, 3); | |
7a192925 | 5925 | type = extract32(insn, 22, 2); |
da7dafe7 CF |
5926 | rm = extract32(insn, 16, 5); |
5927 | op = extract32(insn, 14, 2); | |
5928 | rn = extract32(insn, 5, 5); | |
5929 | opc = extract32(insn, 3, 2); | |
5930 | op2r = extract32(insn, 0, 3); | |
5931 | ||
7a192925 AB |
5932 | if (mos || op || op2r) { |
5933 | unallocated_encoding(s); | |
5934 | return; | |
5935 | } | |
5936 | ||
5937 | switch (type) { | |
5938 | case 0: | |
5939 | size = MO_32; | |
5940 | break; | |
5941 | case 1: | |
5942 | size = MO_64; | |
5943 | break; | |
5944 | case 3: | |
5945 | size = MO_16; | |
5763190f | 5946 | if (dc_isar_feature(aa64_fp16, s)) { |
7a192925 AB |
5947 | break; |
5948 | } | |
5949 | /* fallthru */ | |
5950 | default: | |
da7dafe7 CF |
5951 | unallocated_encoding(s); |
5952 | return; | |
5953 | } | |
5954 | ||
8c6afa6a PM |
5955 | if (!fp_access_check(s)) { |
5956 | return; | |
5957 | } | |
5958 | ||
7a192925 | 5959 | handle_fp_compare(s, size, rn, rm, opc & 1, opc & 2); |
faa0ba46 PM |
5960 | } |
5961 | ||
4ce31af4 | 5962 | /* Floating point conditional compare |
faa0ba46 PM |
5963 | * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0 |
5964 | * +---+---+---+-----------+------+---+------+------+-----+------+----+------+ | |
5965 | * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 0 1 | Rn | op | nzcv | | |
5966 | * +---+---+---+-----------+------+---+------+------+-----+------+----+------+ | |
5967 | */ | |
5968 | static void disas_fp_ccomp(DisasContext *s, uint32_t insn) | |
5969 | { | |
513f1d76 CF |
5970 | unsigned int mos, type, rm, cond, rn, op, nzcv; |
5971 | TCGv_i64 tcg_flags; | |
42a268c2 | 5972 | TCGLabel *label_continue = NULL; |
7a192925 | 5973 | int size; |
513f1d76 CF |
5974 | |
5975 | mos = extract32(insn, 29, 3); | |
7a192925 | 5976 | type = extract32(insn, 22, 2); |
513f1d76 CF |
5977 | rm = extract32(insn, 16, 5); |
5978 | cond = extract32(insn, 12, 4); | |
5979 | rn = extract32(insn, 5, 5); | |
5980 | op = extract32(insn, 4, 1); | |
5981 | nzcv = extract32(insn, 0, 4); | |
5982 | ||
7a192925 AB |
5983 | if (mos) { |
5984 | unallocated_encoding(s); | |
5985 | return; | |
5986 | } | |
5987 | ||
5988 | switch (type) { | |
5989 | case 0: | |
5990 | size = MO_32; | |
5991 | break; | |
5992 | case 1: | |
5993 | size = MO_64; | |
5994 | break; | |
5995 | case 3: | |
5996 | size = MO_16; | |
5763190f | 5997 | if (dc_isar_feature(aa64_fp16, s)) { |
7a192925 AB |
5998 | break; |
5999 | } | |
6000 | /* fallthru */ | |
6001 | default: | |
513f1d76 CF |
6002 | unallocated_encoding(s); |
6003 | return; | |
6004 | } | |
6005 | ||
8c6afa6a PM |
6006 | if (!fp_access_check(s)) { |
6007 | return; | |
6008 | } | |
6009 | ||
513f1d76 | 6010 | if (cond < 0x0e) { /* not always */ |
42a268c2 | 6011 | TCGLabel *label_match = gen_new_label(); |
513f1d76 CF |
6012 | label_continue = gen_new_label(); |
6013 | arm_gen_test_cc(cond, label_match); | |
6014 | /* nomatch: */ | |
6015 | tcg_flags = tcg_const_i64(nzcv << 28); | |
6016 | gen_set_nzcv(tcg_flags); | |
6017 | tcg_temp_free_i64(tcg_flags); | |
6018 | tcg_gen_br(label_continue); | |
6019 | gen_set_label(label_match); | |
6020 | } | |
6021 | ||
7a192925 | 6022 | handle_fp_compare(s, size, rn, rm, false, op); |
513f1d76 CF |
6023 | |
6024 | if (cond < 0x0e) { | |
6025 | gen_set_label(label_continue); | |
6026 | } | |
faa0ba46 PM |
6027 | } |
6028 | ||
4ce31af4 | 6029 | /* Floating point conditional select |
faa0ba46 PM |
6030 | * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0 |
6031 | * +---+---+---+-----------+------+---+------+------+-----+------+------+ | |
6032 | * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 1 1 | Rn | Rd | | |
6033 | * +---+---+---+-----------+------+---+------+------+-----+------+------+ | |
6034 | */ | |
6035 | static void disas_fp_csel(DisasContext *s, uint32_t insn) | |
6036 | { | |
5640ff62 | 6037 | unsigned int mos, type, rm, cond, rn, rd; |
6e061029 RH |
6038 | TCGv_i64 t_true, t_false, t_zero; |
6039 | DisasCompare64 c; | |
14776ab5 | 6040 | MemOp sz; |
5640ff62 CF |
6041 | |
6042 | mos = extract32(insn, 29, 3); | |
ace97fee | 6043 | type = extract32(insn, 22, 2); |
5640ff62 CF |
6044 | rm = extract32(insn, 16, 5); |
6045 | cond = extract32(insn, 12, 4); | |
6046 | rn = extract32(insn, 5, 5); | |
6047 | rd = extract32(insn, 0, 5); | |
6048 | ||
ace97fee AB |
6049 | if (mos) { |
6050 | unallocated_encoding(s); | |
6051 | return; | |
6052 | } | |
6053 | ||
6054 | switch (type) { | |
6055 | case 0: | |
6056 | sz = MO_32; | |
6057 | break; | |
6058 | case 1: | |
6059 | sz = MO_64; | |
6060 | break; | |
6061 | case 3: | |
6062 | sz = MO_16; | |
5763190f | 6063 | if (dc_isar_feature(aa64_fp16, s)) { |
ace97fee AB |
6064 | break; |
6065 | } | |
6066 | /* fallthru */ | |
6067 | default: | |
5640ff62 CF |
6068 | unallocated_encoding(s); |
6069 | return; | |
6070 | } | |
6071 | ||
8c6afa6a PM |
6072 | if (!fp_access_check(s)) { |
6073 | return; | |
6074 | } | |
6075 | ||
ace97fee | 6076 | /* Zero extend sreg & hreg inputs to 64 bits now. */ |
6e061029 RH |
6077 | t_true = tcg_temp_new_i64(); |
6078 | t_false = tcg_temp_new_i64(); | |
ace97fee AB |
6079 | read_vec_element(s, t_true, rn, 0, sz); |
6080 | read_vec_element(s, t_false, rm, 0, sz); | |
5640ff62 | 6081 | |
6e061029 RH |
6082 | a64_test_cc(&c, cond); |
6083 | t_zero = tcg_const_i64(0); | |
6084 | tcg_gen_movcond_i64(c.cond, t_true, c.value, t_zero, t_true, t_false); | |
6085 | tcg_temp_free_i64(t_zero); | |
6086 | tcg_temp_free_i64(t_false); | |
6087 | a64_free_cc(&c); | |
5640ff62 | 6088 | |
ace97fee | 6089 | /* Note that sregs & hregs write back zeros to the high bits, |
6e061029 RH |
6090 | and we've already done the zero-extension. */ |
6091 | write_fp_dreg(s, rd, t_true); | |
6092 | tcg_temp_free_i64(t_true); | |
faa0ba46 PM |
6093 | } |
6094 | ||
c2c08713 AB |
6095 | /* Floating-point data-processing (1 source) - half precision */ |
6096 | static void handle_fp_1src_half(DisasContext *s, int opcode, int rd, int rn) | |
6097 | { | |
6098 | TCGv_ptr fpst = NULL; | |
3d99d931 | 6099 | TCGv_i32 tcg_op = read_fp_hreg(s, rn); |
c2c08713 AB |
6100 | TCGv_i32 tcg_res = tcg_temp_new_i32(); |
6101 | ||
c2c08713 AB |
6102 | switch (opcode) { |
6103 | case 0x0: /* FMOV */ | |
6104 | tcg_gen_mov_i32(tcg_res, tcg_op); | |
6105 | break; | |
6106 | case 0x1: /* FABS */ | |
6107 | tcg_gen_andi_i32(tcg_res, tcg_op, 0x7fff); | |
6108 | break; | |
6109 | case 0x2: /* FNEG */ | |
6110 | tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000); | |
6111 | break; | |
6112 | case 0x3: /* FSQRT */ | |
905edee9 AB |
6113 | fpst = get_fpstatus_ptr(true); |
6114 | gen_helper_sqrt_f16(tcg_res, tcg_op, fpst); | |
c2c08713 AB |
6115 | break; |
6116 | case 0x8: /* FRINTN */ | |
6117 | case 0x9: /* FRINTP */ | |
6118 | case 0xa: /* FRINTM */ | |
6119 | case 0xb: /* FRINTZ */ | |
6120 | case 0xc: /* FRINTA */ | |
6121 | { | |
6122 | TCGv_i32 tcg_rmode = tcg_const_i32(arm_rmode_to_sf(opcode & 7)); | |
6123 | fpst = get_fpstatus_ptr(true); | |
6124 | ||
6125 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); | |
6126 | gen_helper_advsimd_rinth(tcg_res, tcg_op, fpst); | |
6127 | ||
6128 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); | |
6129 | tcg_temp_free_i32(tcg_rmode); | |
6130 | break; | |
6131 | } | |
6132 | case 0xe: /* FRINTX */ | |
6133 | fpst = get_fpstatus_ptr(true); | |
6134 | gen_helper_advsimd_rinth_exact(tcg_res, tcg_op, fpst); | |
6135 | break; | |
6136 | case 0xf: /* FRINTI */ | |
6137 | fpst = get_fpstatus_ptr(true); | |
6138 | gen_helper_advsimd_rinth(tcg_res, tcg_op, fpst); | |
6139 | break; | |
6140 | default: | |
6141 | abort(); | |
6142 | } | |
6143 | ||
6144 | write_fp_sreg(s, rd, tcg_res); | |
6145 | ||
6146 | if (fpst) { | |
6147 | tcg_temp_free_ptr(fpst); | |
6148 | } | |
6149 | tcg_temp_free_i32(tcg_op); | |
6150 | tcg_temp_free_i32(tcg_res); | |
6151 | } | |
6152 | ||
4ce31af4 | 6153 | /* Floating-point data-processing (1 source) - single precision */ |
d9b0848d PM |
6154 | static void handle_fp_1src_single(DisasContext *s, int opcode, int rd, int rn) |
6155 | { | |
0e4db23d RH |
6156 | void (*gen_fpst)(TCGv_i32, TCGv_i32, TCGv_ptr); |
6157 | TCGv_i32 tcg_op, tcg_res; | |
d9b0848d | 6158 | TCGv_ptr fpst; |
0e4db23d | 6159 | int rmode = -1; |
d9b0848d | 6160 | |
d9b0848d PM |
6161 | tcg_op = read_fp_sreg(s, rn); |
6162 | tcg_res = tcg_temp_new_i32(); | |
6163 | ||
6164 | switch (opcode) { | |
6165 | case 0x0: /* FMOV */ | |
6166 | tcg_gen_mov_i32(tcg_res, tcg_op); | |
0e4db23d | 6167 | goto done; |
d9b0848d PM |
6168 | case 0x1: /* FABS */ |
6169 | gen_helper_vfp_abss(tcg_res, tcg_op); | |
0e4db23d | 6170 | goto done; |
d9b0848d PM |
6171 | case 0x2: /* FNEG */ |
6172 | gen_helper_vfp_negs(tcg_res, tcg_op); | |
0e4db23d | 6173 | goto done; |
d9b0848d PM |
6174 | case 0x3: /* FSQRT */ |
6175 | gen_helper_vfp_sqrts(tcg_res, tcg_op, cpu_env); | |
0e4db23d | 6176 | goto done; |
d9b0848d PM |
6177 | case 0x8: /* FRINTN */ |
6178 | case 0x9: /* FRINTP */ | |
6179 | case 0xa: /* FRINTM */ | |
6180 | case 0xb: /* FRINTZ */ | |
6181 | case 0xc: /* FRINTA */ | |
0e4db23d RH |
6182 | rmode = arm_rmode_to_sf(opcode & 7); |
6183 | gen_fpst = gen_helper_rints; | |
d9b0848d | 6184 | break; |
d9b0848d | 6185 | case 0xe: /* FRINTX */ |
0e4db23d | 6186 | gen_fpst = gen_helper_rints_exact; |
d9b0848d PM |
6187 | break; |
6188 | case 0xf: /* FRINTI */ | |
0e4db23d | 6189 | gen_fpst = gen_helper_rints; |
d9b0848d | 6190 | break; |
6bea2563 RH |
6191 | case 0x10: /* FRINT32Z */ |
6192 | rmode = float_round_to_zero; | |
6193 | gen_fpst = gen_helper_frint32_s; | |
6194 | break; | |
6195 | case 0x11: /* FRINT32X */ | |
6196 | gen_fpst = gen_helper_frint32_s; | |
6197 | break; | |
6198 | case 0x12: /* FRINT64Z */ | |
6199 | rmode = float_round_to_zero; | |
6200 | gen_fpst = gen_helper_frint64_s; | |
6201 | break; | |
6202 | case 0x13: /* FRINT64X */ | |
6203 | gen_fpst = gen_helper_frint64_s; | |
6204 | break; | |
d9b0848d | 6205 | default: |
0e4db23d | 6206 | g_assert_not_reached(); |
d9b0848d PM |
6207 | } |
6208 | ||
0e4db23d RH |
6209 | fpst = get_fpstatus_ptr(false); |
6210 | if (rmode >= 0) { | |
6211 | TCGv_i32 tcg_rmode = tcg_const_i32(rmode); | |
6212 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); | |
6213 | gen_fpst(tcg_res, tcg_op, fpst); | |
6214 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); | |
6215 | tcg_temp_free_i32(tcg_rmode); | |
6216 | } else { | |
6217 | gen_fpst(tcg_res, tcg_op, fpst); | |
6218 | } | |
d9b0848d | 6219 | tcg_temp_free_ptr(fpst); |
0e4db23d RH |
6220 | |
6221 | done: | |
6222 | write_fp_sreg(s, rd, tcg_res); | |
d9b0848d PM |
6223 | tcg_temp_free_i32(tcg_op); |
6224 | tcg_temp_free_i32(tcg_res); | |
6225 | } | |
6226 | ||
4ce31af4 | 6227 | /* Floating-point data-processing (1 source) - double precision */ |
d9b0848d PM |
6228 | static void handle_fp_1src_double(DisasContext *s, int opcode, int rd, int rn) |
6229 | { | |
0e4db23d RH |
6230 | void (*gen_fpst)(TCGv_i64, TCGv_i64, TCGv_ptr); |
6231 | TCGv_i64 tcg_op, tcg_res; | |
d9b0848d | 6232 | TCGv_ptr fpst; |
0e4db23d | 6233 | int rmode = -1; |
d9b0848d | 6234 | |
377ef731 RH |
6235 | switch (opcode) { |
6236 | case 0x0: /* FMOV */ | |
6237 | gen_gvec_fn2(s, false, rd, rn, tcg_gen_gvec_mov, 0); | |
6238 | return; | |
6239 | } | |
6240 | ||
d9b0848d PM |
6241 | tcg_op = read_fp_dreg(s, rn); |
6242 | tcg_res = tcg_temp_new_i64(); | |
6243 | ||
6244 | switch (opcode) { | |
d9b0848d PM |
6245 | case 0x1: /* FABS */ |
6246 | gen_helper_vfp_absd(tcg_res, tcg_op); | |
0e4db23d | 6247 | goto done; |
d9b0848d PM |
6248 | case 0x2: /* FNEG */ |
6249 | gen_helper_vfp_negd(tcg_res, tcg_op); | |
0e4db23d | 6250 | goto done; |
d9b0848d PM |
6251 | case 0x3: /* FSQRT */ |
6252 | gen_helper_vfp_sqrtd(tcg_res, tcg_op, cpu_env); | |
0e4db23d | 6253 | goto done; |
d9b0848d PM |
6254 | case 0x8: /* FRINTN */ |
6255 | case 0x9: /* FRINTP */ | |
6256 | case 0xa: /* FRINTM */ | |
6257 | case 0xb: /* FRINTZ */ | |
6258 | case 0xc: /* FRINTA */ | |
0e4db23d RH |
6259 | rmode = arm_rmode_to_sf(opcode & 7); |
6260 | gen_fpst = gen_helper_rintd; | |
d9b0848d | 6261 | break; |
d9b0848d | 6262 | case 0xe: /* FRINTX */ |
0e4db23d | 6263 | gen_fpst = gen_helper_rintd_exact; |
d9b0848d PM |
6264 | break; |
6265 | case 0xf: /* FRINTI */ | |
0e4db23d | 6266 | gen_fpst = gen_helper_rintd; |
d9b0848d | 6267 | break; |
6bea2563 RH |
6268 | case 0x10: /* FRINT32Z */ |
6269 | rmode = float_round_to_zero; | |
6270 | gen_fpst = gen_helper_frint32_d; | |
6271 | break; | |
6272 | case 0x11: /* FRINT32X */ | |
6273 | gen_fpst = gen_helper_frint32_d; | |
6274 | break; | |
6275 | case 0x12: /* FRINT64Z */ | |
6276 | rmode = float_round_to_zero; | |
6277 | gen_fpst = gen_helper_frint64_d; | |
6278 | break; | |
6279 | case 0x13: /* FRINT64X */ | |
6280 | gen_fpst = gen_helper_frint64_d; | |
6281 | break; | |
d9b0848d | 6282 | default: |
0e4db23d | 6283 | g_assert_not_reached(); |
d9b0848d PM |
6284 | } |
6285 | ||
0e4db23d RH |
6286 | fpst = get_fpstatus_ptr(false); |
6287 | if (rmode >= 0) { | |
6288 | TCGv_i32 tcg_rmode = tcg_const_i32(rmode); | |
6289 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); | |
6290 | gen_fpst(tcg_res, tcg_op, fpst); | |
6291 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); | |
6292 | tcg_temp_free_i32(tcg_rmode); | |
6293 | } else { | |
6294 | gen_fpst(tcg_res, tcg_op, fpst); | |
6295 | } | |
d9b0848d | 6296 | tcg_temp_free_ptr(fpst); |
0e4db23d RH |
6297 | |
6298 | done: | |
6299 | write_fp_dreg(s, rd, tcg_res); | |
d9b0848d PM |
6300 | tcg_temp_free_i64(tcg_op); |
6301 | tcg_temp_free_i64(tcg_res); | |
6302 | } | |
6303 | ||
8900aad2 PM |
6304 | static void handle_fp_fcvt(DisasContext *s, int opcode, |
6305 | int rd, int rn, int dtype, int ntype) | |
6306 | { | |
6307 | switch (ntype) { | |
6308 | case 0x0: | |
6309 | { | |
6310 | TCGv_i32 tcg_rn = read_fp_sreg(s, rn); | |
6311 | if (dtype == 1) { | |
6312 | /* Single to double */ | |
6313 | TCGv_i64 tcg_rd = tcg_temp_new_i64(); | |
6314 | gen_helper_vfp_fcvtds(tcg_rd, tcg_rn, cpu_env); | |
6315 | write_fp_dreg(s, rd, tcg_rd); | |
6316 | tcg_temp_free_i64(tcg_rd); | |
6317 | } else { | |
6318 | /* Single to half */ | |
6319 | TCGv_i32 tcg_rd = tcg_temp_new_i32(); | |
486624fc AB |
6320 | TCGv_i32 ahp = get_ahp_flag(); |
6321 | TCGv_ptr fpst = get_fpstatus_ptr(false); | |
6322 | ||
6323 | gen_helper_vfp_fcvt_f32_to_f16(tcg_rd, tcg_rn, fpst, ahp); | |
8900aad2 PM |
6324 | /* write_fp_sreg is OK here because top half of tcg_rd is zero */ |
6325 | write_fp_sreg(s, rd, tcg_rd); | |
6326 | tcg_temp_free_i32(tcg_rd); | |
486624fc AB |
6327 | tcg_temp_free_i32(ahp); |
6328 | tcg_temp_free_ptr(fpst); | |
8900aad2 PM |
6329 | } |
6330 | tcg_temp_free_i32(tcg_rn); | |
6331 | break; | |
6332 | } | |
6333 | case 0x1: | |
6334 | { | |
6335 | TCGv_i64 tcg_rn = read_fp_dreg(s, rn); | |
6336 | TCGv_i32 tcg_rd = tcg_temp_new_i32(); | |
6337 | if (dtype == 0) { | |
6338 | /* Double to single */ | |
6339 | gen_helper_vfp_fcvtsd(tcg_rd, tcg_rn, cpu_env); | |
6340 | } else { | |
486624fc AB |
6341 | TCGv_ptr fpst = get_fpstatus_ptr(false); |
6342 | TCGv_i32 ahp = get_ahp_flag(); | |
8900aad2 | 6343 | /* Double to half */ |
486624fc | 6344 | gen_helper_vfp_fcvt_f64_to_f16(tcg_rd, tcg_rn, fpst, ahp); |
8900aad2 | 6345 | /* write_fp_sreg is OK here because top half of tcg_rd is zero */ |
486624fc AB |
6346 | tcg_temp_free_ptr(fpst); |
6347 | tcg_temp_free_i32(ahp); | |
8900aad2 PM |
6348 | } |
6349 | write_fp_sreg(s, rd, tcg_rd); | |
6350 | tcg_temp_free_i32(tcg_rd); | |
6351 | tcg_temp_free_i64(tcg_rn); | |
6352 | break; | |
6353 | } | |
6354 | case 0x3: | |
6355 | { | |
6356 | TCGv_i32 tcg_rn = read_fp_sreg(s, rn); | |
486624fc AB |
6357 | TCGv_ptr tcg_fpst = get_fpstatus_ptr(false); |
6358 | TCGv_i32 tcg_ahp = get_ahp_flag(); | |
8900aad2 PM |
6359 | tcg_gen_ext16u_i32(tcg_rn, tcg_rn); |
6360 | if (dtype == 0) { | |
6361 | /* Half to single */ | |
6362 | TCGv_i32 tcg_rd = tcg_temp_new_i32(); | |
486624fc | 6363 | gen_helper_vfp_fcvt_f16_to_f32(tcg_rd, tcg_rn, tcg_fpst, tcg_ahp); |
8900aad2 PM |
6364 | write_fp_sreg(s, rd, tcg_rd); |
6365 | tcg_temp_free_i32(tcg_rd); | |
6366 | } else { | |
6367 | /* Half to double */ | |
6368 | TCGv_i64 tcg_rd = tcg_temp_new_i64(); | |
486624fc | 6369 | gen_helper_vfp_fcvt_f16_to_f64(tcg_rd, tcg_rn, tcg_fpst, tcg_ahp); |
8900aad2 PM |
6370 | write_fp_dreg(s, rd, tcg_rd); |
6371 | tcg_temp_free_i64(tcg_rd); | |
6372 | } | |
6373 | tcg_temp_free_i32(tcg_rn); | |
aeab8e5e AB |
6374 | tcg_temp_free_ptr(tcg_fpst); |
6375 | tcg_temp_free_i32(tcg_ahp); | |
8900aad2 PM |
6376 | break; |
6377 | } | |
6378 | default: | |
6379 | abort(); | |
6380 | } | |
6381 | } | |
6382 | ||
4ce31af4 | 6383 | /* Floating point data-processing (1 source) |
faa0ba46 PM |
6384 | * 31 30 29 28 24 23 22 21 20 15 14 10 9 5 4 0 |
6385 | * +---+---+---+-----------+------+---+--------+-----------+------+------+ | |
6386 | * | M | 0 | S | 1 1 1 1 0 | type | 1 | opcode | 1 0 0 0 0 | Rn | Rd | | |
6387 | * +---+---+---+-----------+------+---+--------+-----------+------+------+ | |
6388 | */ | |
6389 | static void disas_fp_1src(DisasContext *s, uint32_t insn) | |
6390 | { | |
c1e20801 | 6391 | int mos = extract32(insn, 29, 3); |
d9b0848d PM |
6392 | int type = extract32(insn, 22, 2); |
6393 | int opcode = extract32(insn, 15, 6); | |
6394 | int rn = extract32(insn, 5, 5); | |
6395 | int rd = extract32(insn, 0, 5); | |
6396 | ||
c1e20801 PM |
6397 | if (mos) { |
6398 | unallocated_encoding(s); | |
6399 | return; | |
6400 | } | |
6401 | ||
d9b0848d PM |
6402 | switch (opcode) { |
6403 | case 0x4: case 0x5: case 0x7: | |
8900aad2 | 6404 | { |
d9b0848d | 6405 | /* FCVT between half, single and double precision */ |
8900aad2 PM |
6406 | int dtype = extract32(opcode, 0, 2); |
6407 | if (type == 2 || dtype == type) { | |
6408 | unallocated_encoding(s); | |
6409 | return; | |
6410 | } | |
8c6afa6a PM |
6411 | if (!fp_access_check(s)) { |
6412 | return; | |
6413 | } | |
6414 | ||
8900aad2 | 6415 | handle_fp_fcvt(s, opcode, rd, rn, dtype, type); |
d9b0848d | 6416 | break; |
8900aad2 | 6417 | } |
6bea2563 RH |
6418 | |
6419 | case 0x10 ... 0x13: /* FRINT{32,64}{X,Z} */ | |
6420 | if (type > 1 || !dc_isar_feature(aa64_frint, s)) { | |
6421 | unallocated_encoding(s); | |
6422 | return; | |
6423 | } | |
6424 | /* fall through */ | |
d9b0848d PM |
6425 | case 0x0 ... 0x3: |
6426 | case 0x8 ... 0xc: | |
6427 | case 0xe ... 0xf: | |
6428 | /* 32-to-32 and 64-to-64 ops */ | |
6429 | switch (type) { | |
6430 | case 0: | |
8c6afa6a PM |
6431 | if (!fp_access_check(s)) { |
6432 | return; | |
6433 | } | |
d9b0848d PM |
6434 | handle_fp_1src_single(s, opcode, rd, rn); |
6435 | break; | |
6436 | case 1: | |
8c6afa6a PM |
6437 | if (!fp_access_check(s)) { |
6438 | return; | |
6439 | } | |
d9b0848d PM |
6440 | handle_fp_1src_double(s, opcode, rd, rn); |
6441 | break; | |
c2c08713 | 6442 | case 3: |
5763190f | 6443 | if (!dc_isar_feature(aa64_fp16, s)) { |
c2c08713 AB |
6444 | unallocated_encoding(s); |
6445 | return; | |
6446 | } | |
6447 | ||
6448 | if (!fp_access_check(s)) { | |
6449 | return; | |
6450 | } | |
c2c08713 AB |
6451 | handle_fp_1src_half(s, opcode, rd, rn); |
6452 | break; | |
d9b0848d PM |
6453 | default: |
6454 | unallocated_encoding(s); | |
6455 | } | |
6456 | break; | |
6bea2563 | 6457 | |
d9b0848d PM |
6458 | default: |
6459 | unallocated_encoding(s); | |
6460 | break; | |
6461 | } | |
faa0ba46 PM |
6462 | } |
6463 | ||
4ce31af4 | 6464 | /* Floating-point data-processing (2 source) - single precision */ |
ec73d2e0 AG |
6465 | static void handle_fp_2src_single(DisasContext *s, int opcode, |
6466 | int rd, int rn, int rm) | |
6467 | { | |
6468 | TCGv_i32 tcg_op1; | |
6469 | TCGv_i32 tcg_op2; | |
6470 | TCGv_i32 tcg_res; | |
6471 | TCGv_ptr fpst; | |
6472 | ||
6473 | tcg_res = tcg_temp_new_i32(); | |
d81ce0ef | 6474 | fpst = get_fpstatus_ptr(false); |
ec73d2e0 AG |
6475 | tcg_op1 = read_fp_sreg(s, rn); |
6476 | tcg_op2 = read_fp_sreg(s, rm); | |
6477 | ||
6478 | switch (opcode) { | |
6479 | case 0x0: /* FMUL */ | |
6480 | gen_helper_vfp_muls(tcg_res, tcg_op1, tcg_op2, fpst); | |
6481 | break; | |
6482 | case 0x1: /* FDIV */ | |
6483 | gen_helper_vfp_divs(tcg_res, tcg_op1, tcg_op2, fpst); | |
6484 | break; | |
6485 | case 0x2: /* FADD */ | |
6486 | gen_helper_vfp_adds(tcg_res, tcg_op1, tcg_op2, fpst); | |
6487 | break; | |
6488 | case 0x3: /* FSUB */ | |
6489 | gen_helper_vfp_subs(tcg_res, tcg_op1, tcg_op2, fpst); | |
6490 | break; | |
6491 | case 0x4: /* FMAX */ | |
6492 | gen_helper_vfp_maxs(tcg_res, tcg_op1, tcg_op2, fpst); | |
6493 | break; | |
6494 | case 0x5: /* FMIN */ | |
6495 | gen_helper_vfp_mins(tcg_res, tcg_op1, tcg_op2, fpst); | |
6496 | break; | |
6497 | case 0x6: /* FMAXNM */ | |
6498 | gen_helper_vfp_maxnums(tcg_res, tcg_op1, tcg_op2, fpst); | |
6499 | break; | |
6500 | case 0x7: /* FMINNM */ | |
6501 | gen_helper_vfp_minnums(tcg_res, tcg_op1, tcg_op2, fpst); | |
6502 | break; | |
6503 | case 0x8: /* FNMUL */ | |
6504 | gen_helper_vfp_muls(tcg_res, tcg_op1, tcg_op2, fpst); | |
6505 | gen_helper_vfp_negs(tcg_res, tcg_res); | |
6506 | break; | |
6507 | } | |
6508 | ||
6509 | write_fp_sreg(s, rd, tcg_res); | |
6510 | ||
6511 | tcg_temp_free_ptr(fpst); | |
6512 | tcg_temp_free_i32(tcg_op1); | |
6513 | tcg_temp_free_i32(tcg_op2); | |
6514 | tcg_temp_free_i32(tcg_res); | |
6515 | } | |
6516 | ||
4ce31af4 | 6517 | /* Floating-point data-processing (2 source) - double precision */ |
ec73d2e0 AG |
6518 | static void handle_fp_2src_double(DisasContext *s, int opcode, |
6519 | int rd, int rn, int rm) | |
6520 | { | |
6521 | TCGv_i64 tcg_op1; | |
6522 | TCGv_i64 tcg_op2; | |
6523 | TCGv_i64 tcg_res; | |
6524 | TCGv_ptr fpst; | |
6525 | ||
6526 | tcg_res = tcg_temp_new_i64(); | |
d81ce0ef | 6527 | fpst = get_fpstatus_ptr(false); |
ec73d2e0 AG |
6528 | tcg_op1 = read_fp_dreg(s, rn); |
6529 | tcg_op2 = read_fp_dreg(s, rm); | |
6530 | ||
6531 | switch (opcode) { | |
6532 | case 0x0: /* FMUL */ | |
6533 | gen_helper_vfp_muld(tcg_res, tcg_op1, tcg_op2, fpst); | |
6534 | break; | |
6535 | case 0x1: /* FDIV */ | |
6536 | gen_helper_vfp_divd(tcg_res, tcg_op1, tcg_op2, fpst); | |
6537 | break; | |
6538 | case 0x2: /* FADD */ | |
6539 | gen_helper_vfp_addd(tcg_res, tcg_op1, tcg_op2, fpst); | |
6540 | break; | |
6541 | case 0x3: /* FSUB */ | |
6542 | gen_helper_vfp_subd(tcg_res, tcg_op1, tcg_op2, fpst); | |
6543 | break; | |
6544 | case 0x4: /* FMAX */ | |
6545 | gen_helper_vfp_maxd(tcg_res, tcg_op1, tcg_op2, fpst); | |
6546 | break; | |
6547 | case 0x5: /* FMIN */ | |
6548 | gen_helper_vfp_mind(tcg_res, tcg_op1, tcg_op2, fpst); | |
6549 | break; | |
6550 | case 0x6: /* FMAXNM */ | |
6551 | gen_helper_vfp_maxnumd(tcg_res, tcg_op1, tcg_op2, fpst); | |
6552 | break; | |
6553 | case 0x7: /* FMINNM */ | |
6554 | gen_helper_vfp_minnumd(tcg_res, tcg_op1, tcg_op2, fpst); | |
6555 | break; | |
6556 | case 0x8: /* FNMUL */ | |
6557 | gen_helper_vfp_muld(tcg_res, tcg_op1, tcg_op2, fpst); | |
6558 | gen_helper_vfp_negd(tcg_res, tcg_res); | |
6559 | break; | |
6560 | } | |
6561 | ||
6562 | write_fp_dreg(s, rd, tcg_res); | |
6563 | ||
6564 | tcg_temp_free_ptr(fpst); | |
6565 | tcg_temp_free_i64(tcg_op1); | |
6566 | tcg_temp_free_i64(tcg_op2); | |
6567 | tcg_temp_free_i64(tcg_res); | |
6568 | } | |
6569 | ||
b8f5171c RH |
6570 | /* Floating-point data-processing (2 source) - half precision */ |
6571 | static void handle_fp_2src_half(DisasContext *s, int opcode, | |
6572 | int rd, int rn, int rm) | |
6573 | { | |
6574 | TCGv_i32 tcg_op1; | |
6575 | TCGv_i32 tcg_op2; | |
6576 | TCGv_i32 tcg_res; | |
6577 | TCGv_ptr fpst; | |
6578 | ||
6579 | tcg_res = tcg_temp_new_i32(); | |
6580 | fpst = get_fpstatus_ptr(true); | |
6581 | tcg_op1 = read_fp_hreg(s, rn); | |
6582 | tcg_op2 = read_fp_hreg(s, rm); | |
6583 | ||
6584 | switch (opcode) { | |
6585 | case 0x0: /* FMUL */ | |
6586 | gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst); | |
6587 | break; | |
6588 | case 0x1: /* FDIV */ | |
6589 | gen_helper_advsimd_divh(tcg_res, tcg_op1, tcg_op2, fpst); | |
6590 | break; | |
6591 | case 0x2: /* FADD */ | |
6592 | gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst); | |
6593 | break; | |
6594 | case 0x3: /* FSUB */ | |
6595 | gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst); | |
6596 | break; | |
6597 | case 0x4: /* FMAX */ | |
6598 | gen_helper_advsimd_maxh(tcg_res, tcg_op1, tcg_op2, fpst); | |
6599 | break; | |
6600 | case 0x5: /* FMIN */ | |
6601 | gen_helper_advsimd_minh(tcg_res, tcg_op1, tcg_op2, fpst); | |
6602 | break; | |
6603 | case 0x6: /* FMAXNM */ | |
6604 | gen_helper_advsimd_maxnumh(tcg_res, tcg_op1, tcg_op2, fpst); | |
6605 | break; | |
6606 | case 0x7: /* FMINNM */ | |
6607 | gen_helper_advsimd_minnumh(tcg_res, tcg_op1, tcg_op2, fpst); | |
6608 | break; | |
6609 | case 0x8: /* FNMUL */ | |
6610 | gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst); | |
6611 | tcg_gen_xori_i32(tcg_res, tcg_res, 0x8000); | |
6612 | break; | |
6613 | default: | |
6614 | g_assert_not_reached(); | |
6615 | } | |
6616 | ||
6617 | write_fp_sreg(s, rd, tcg_res); | |
6618 | ||
6619 | tcg_temp_free_ptr(fpst); | |
6620 | tcg_temp_free_i32(tcg_op1); | |
6621 | tcg_temp_free_i32(tcg_op2); | |
6622 | tcg_temp_free_i32(tcg_res); | |
6623 | } | |
6624 | ||
4ce31af4 | 6625 | /* Floating point data-processing (2 source) |
faa0ba46 PM |
6626 | * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0 |
6627 | * +---+---+---+-----------+------+---+------+--------+-----+------+------+ | |
6628 | * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | opcode | 1 0 | Rn | Rd | | |
6629 | * +---+---+---+-----------+------+---+------+--------+-----+------+------+ | |
6630 | */ | |
6631 | static void disas_fp_2src(DisasContext *s, uint32_t insn) | |
6632 | { | |
c1e20801 | 6633 | int mos = extract32(insn, 29, 3); |
ec73d2e0 AG |
6634 | int type = extract32(insn, 22, 2); |
6635 | int rd = extract32(insn, 0, 5); | |
6636 | int rn = extract32(insn, 5, 5); | |
6637 | int rm = extract32(insn, 16, 5); | |
6638 | int opcode = extract32(insn, 12, 4); | |
6639 | ||
c1e20801 | 6640 | if (opcode > 8 || mos) { |
ec73d2e0 AG |
6641 | unallocated_encoding(s); |
6642 | return; | |
6643 | } | |
6644 | ||
6645 | switch (type) { | |
6646 | case 0: | |
8c6afa6a PM |
6647 | if (!fp_access_check(s)) { |
6648 | return; | |
6649 | } | |
ec73d2e0 AG |
6650 | handle_fp_2src_single(s, opcode, rd, rn, rm); |
6651 | break; | |
6652 | case 1: | |
8c6afa6a PM |
6653 | if (!fp_access_check(s)) { |
6654 | return; | |
6655 | } | |
ec73d2e0 AG |
6656 | handle_fp_2src_double(s, opcode, rd, rn, rm); |
6657 | break; | |
b8f5171c | 6658 | case 3: |
5763190f | 6659 | if (!dc_isar_feature(aa64_fp16, s)) { |
b8f5171c RH |
6660 | unallocated_encoding(s); |
6661 | return; | |
6662 | } | |
6663 | if (!fp_access_check(s)) { | |
6664 | return; | |
6665 | } | |
6666 | handle_fp_2src_half(s, opcode, rd, rn, rm); | |
6667 | break; | |
ec73d2e0 AG |
6668 | default: |
6669 | unallocated_encoding(s); | |
6670 | } | |
faa0ba46 PM |
6671 | } |
6672 | ||
4ce31af4 | 6673 | /* Floating-point data-processing (3 source) - single precision */ |
6a30667f AG |
6674 | static void handle_fp_3src_single(DisasContext *s, bool o0, bool o1, |
6675 | int rd, int rn, int rm, int ra) | |
6676 | { | |
6677 | TCGv_i32 tcg_op1, tcg_op2, tcg_op3; | |
6678 | TCGv_i32 tcg_res = tcg_temp_new_i32(); | |
d81ce0ef | 6679 | TCGv_ptr fpst = get_fpstatus_ptr(false); |
6a30667f AG |
6680 | |
6681 | tcg_op1 = read_fp_sreg(s, rn); | |
6682 | tcg_op2 = read_fp_sreg(s, rm); | |
6683 | tcg_op3 = read_fp_sreg(s, ra); | |
6684 | ||
6685 | /* These are fused multiply-add, and must be done as one | |
6686 | * floating point operation with no rounding between the | |
6687 | * multiplication and addition steps. | |
6688 | * NB that doing the negations here as separate steps is | |
6689 | * correct : an input NaN should come out with its sign bit | |
6690 | * flipped if it is a negated-input. | |
6691 | */ | |
6692 | if (o1 == true) { | |
6693 | gen_helper_vfp_negs(tcg_op3, tcg_op3); | |
6694 | } | |
6695 | ||
6696 | if (o0 != o1) { | |
6697 | gen_helper_vfp_negs(tcg_op1, tcg_op1); | |
6698 | } | |
6699 | ||
6700 | gen_helper_vfp_muladds(tcg_res, tcg_op1, tcg_op2, tcg_op3, fpst); | |
6701 | ||
6702 | write_fp_sreg(s, rd, tcg_res); | |
6703 | ||
6704 | tcg_temp_free_ptr(fpst); | |
6705 | tcg_temp_free_i32(tcg_op1); | |
6706 | tcg_temp_free_i32(tcg_op2); | |
6707 | tcg_temp_free_i32(tcg_op3); | |
6708 | tcg_temp_free_i32(tcg_res); | |
6709 | } | |
6710 | ||
4ce31af4 | 6711 | /* Floating-point data-processing (3 source) - double precision */ |
6a30667f AG |
6712 | static void handle_fp_3src_double(DisasContext *s, bool o0, bool o1, |
6713 | int rd, int rn, int rm, int ra) | |
6714 | { | |
6715 | TCGv_i64 tcg_op1, tcg_op2, tcg_op3; | |
6716 | TCGv_i64 tcg_res = tcg_temp_new_i64(); | |
d81ce0ef | 6717 | TCGv_ptr fpst = get_fpstatus_ptr(false); |
6a30667f AG |
6718 | |
6719 | tcg_op1 = read_fp_dreg(s, rn); | |
6720 | tcg_op2 = read_fp_dreg(s, rm); | |
6721 | tcg_op3 = read_fp_dreg(s, ra); | |
6722 | ||
6723 | /* These are fused multiply-add, and must be done as one | |
6724 | * floating point operation with no rounding between the | |
6725 | * multiplication and addition steps. | |
6726 | * NB that doing the negations here as separate steps is | |
6727 | * correct : an input NaN should come out with its sign bit | |
6728 | * flipped if it is a negated-input. | |
6729 | */ | |
6730 | if (o1 == true) { | |
6731 | gen_helper_vfp_negd(tcg_op3, tcg_op3); | |
6732 | } | |
6733 | ||
6734 | if (o0 != o1) { | |
6735 | gen_helper_vfp_negd(tcg_op1, tcg_op1); | |
6736 | } | |
6737 | ||
6738 | gen_helper_vfp_muladdd(tcg_res, tcg_op1, tcg_op2, tcg_op3, fpst); | |
6739 | ||
6740 | write_fp_dreg(s, rd, tcg_res); | |
6741 | ||
6742 | tcg_temp_free_ptr(fpst); | |
6743 | tcg_temp_free_i64(tcg_op1); | |
6744 | tcg_temp_free_i64(tcg_op2); | |
6745 | tcg_temp_free_i64(tcg_op3); | |
6746 | tcg_temp_free_i64(tcg_res); | |
6747 | } | |
6748 | ||
95f9864f RH |
6749 | /* Floating-point data-processing (3 source) - half precision */ |
6750 | static void handle_fp_3src_half(DisasContext *s, bool o0, bool o1, | |
6751 | int rd, int rn, int rm, int ra) | |
6752 | { | |
6753 | TCGv_i32 tcg_op1, tcg_op2, tcg_op3; | |
6754 | TCGv_i32 tcg_res = tcg_temp_new_i32(); | |
6755 | TCGv_ptr fpst = get_fpstatus_ptr(true); | |
6756 | ||
6757 | tcg_op1 = read_fp_hreg(s, rn); | |
6758 | tcg_op2 = read_fp_hreg(s, rm); | |
6759 | tcg_op3 = read_fp_hreg(s, ra); | |
6760 | ||
6761 | /* These are fused multiply-add, and must be done as one | |
6762 | * floating point operation with no rounding between the | |
6763 | * multiplication and addition steps. | |
6764 | * NB that doing the negations here as separate steps is | |
6765 | * correct : an input NaN should come out with its sign bit | |
6766 | * flipped if it is a negated-input. | |
6767 | */ | |
6768 | if (o1 == true) { | |
6769 | tcg_gen_xori_i32(tcg_op3, tcg_op3, 0x8000); | |
6770 | } | |
6771 | ||
6772 | if (o0 != o1) { | |
6773 | tcg_gen_xori_i32(tcg_op1, tcg_op1, 0x8000); | |
6774 | } | |
6775 | ||
6776 | gen_helper_advsimd_muladdh(tcg_res, tcg_op1, tcg_op2, tcg_op3, fpst); | |
6777 | ||
6778 | write_fp_sreg(s, rd, tcg_res); | |
6779 | ||
6780 | tcg_temp_free_ptr(fpst); | |
6781 | tcg_temp_free_i32(tcg_op1); | |
6782 | tcg_temp_free_i32(tcg_op2); | |
6783 | tcg_temp_free_i32(tcg_op3); | |
6784 | tcg_temp_free_i32(tcg_res); | |
6785 | } | |
6786 | ||
4ce31af4 | 6787 | /* Floating point data-processing (3 source) |
faa0ba46 PM |
6788 | * 31 30 29 28 24 23 22 21 20 16 15 14 10 9 5 4 0 |
6789 | * +---+---+---+-----------+------+----+------+----+------+------+------+ | |
6790 | * | M | 0 | S | 1 1 1 1 1 | type | o1 | Rm | o0 | Ra | Rn | Rd | | |
6791 | * +---+---+---+-----------+------+----+------+----+------+------+------+ | |
6792 | */ | |
6793 | static void disas_fp_3src(DisasContext *s, uint32_t insn) | |
6794 | { | |
c1e20801 | 6795 | int mos = extract32(insn, 29, 3); |
6a30667f AG |
6796 | int type = extract32(insn, 22, 2); |
6797 | int rd = extract32(insn, 0, 5); | |
6798 | int rn = extract32(insn, 5, 5); | |
6799 | int ra = extract32(insn, 10, 5); | |
6800 | int rm = extract32(insn, 16, 5); | |
6801 | bool o0 = extract32(insn, 15, 1); | |
6802 | bool o1 = extract32(insn, 21, 1); | |
6803 | ||
c1e20801 PM |
6804 | if (mos) { |
6805 | unallocated_encoding(s); | |
6806 | return; | |
6807 | } | |
6808 | ||
6a30667f AG |
6809 | switch (type) { |
6810 | case 0: | |
8c6afa6a PM |
6811 | if (!fp_access_check(s)) { |
6812 | return; | |
6813 | } | |
6a30667f AG |
6814 | handle_fp_3src_single(s, o0, o1, rd, rn, rm, ra); |
6815 | break; | |
6816 | case 1: | |
8c6afa6a PM |
6817 | if (!fp_access_check(s)) { |
6818 | return; | |
6819 | } | |
6a30667f AG |
6820 | handle_fp_3src_double(s, o0, o1, rd, rn, rm, ra); |
6821 | break; | |
95f9864f | 6822 | case 3: |
5763190f | 6823 | if (!dc_isar_feature(aa64_fp16, s)) { |
95f9864f RH |
6824 | unallocated_encoding(s); |
6825 | return; | |
6826 | } | |
6827 | if (!fp_access_check(s)) { | |
6828 | return; | |
6829 | } | |
6830 | handle_fp_3src_half(s, o0, o1, rd, rn, rm, ra); | |
6831 | break; | |
6a30667f AG |
6832 | default: |
6833 | unallocated_encoding(s); | |
6834 | } | |
faa0ba46 PM |
6835 | } |
6836 | ||
4ce31af4 | 6837 | /* Floating point immediate |
faa0ba46 PM |
6838 | * 31 30 29 28 24 23 22 21 20 13 12 10 9 5 4 0 |
6839 | * +---+---+---+-----------+------+---+------------+-------+------+------+ | |
6840 | * | M | 0 | S | 1 1 1 1 0 | type | 1 | imm8 | 1 0 0 | imm5 | Rd | | |
6841 | * +---+---+---+-----------+------+---+------------+-------+------+------+ | |
6842 | */ | |
6843 | static void disas_fp_imm(DisasContext *s, uint32_t insn) | |
6844 | { | |
6163f868 | 6845 | int rd = extract32(insn, 0, 5); |
c1e20801 | 6846 | int imm5 = extract32(insn, 5, 5); |
6163f868 | 6847 | int imm8 = extract32(insn, 13, 8); |
6ba28ddb | 6848 | int type = extract32(insn, 22, 2); |
c1e20801 | 6849 | int mos = extract32(insn, 29, 3); |
6163f868 AG |
6850 | uint64_t imm; |
6851 | TCGv_i64 tcg_res; | |
14776ab5 | 6852 | MemOp sz; |
6163f868 | 6853 | |
c1e20801 PM |
6854 | if (mos || imm5) { |
6855 | unallocated_encoding(s); | |
6856 | return; | |
6857 | } | |
6858 | ||
6ba28ddb AB |
6859 | switch (type) { |
6860 | case 0: | |
6861 | sz = MO_32; | |
6862 | break; | |
6863 | case 1: | |
6864 | sz = MO_64; | |
6865 | break; | |
6866 | case 3: | |
6867 | sz = MO_16; | |
5763190f | 6868 | if (dc_isar_feature(aa64_fp16, s)) { |
6ba28ddb AB |
6869 | break; |
6870 | } | |
6871 | /* fallthru */ | |
6872 | default: | |
6163f868 AG |
6873 | unallocated_encoding(s); |
6874 | return; | |
6875 | } | |
6876 | ||
8c6afa6a PM |
6877 | if (!fp_access_check(s)) { |
6878 | return; | |
6879 | } | |
6880 | ||
6ba28ddb | 6881 | imm = vfp_expand_imm(sz, imm8); |
6163f868 AG |
6882 | |
6883 | tcg_res = tcg_const_i64(imm); | |
6884 | write_fp_dreg(s, rd, tcg_res); | |
6885 | tcg_temp_free_i64(tcg_res); | |
faa0ba46 PM |
6886 | } |
6887 | ||
52a1f6a3 AG |
6888 | /* Handle floating point <=> fixed point conversions. Note that we can |
6889 | * also deal with fp <=> integer conversions as a special case (scale == 64) | |
6890 | * OPTME: consider handling that special case specially or at least skipping | |
6891 | * the call to scalbn in the helpers for zero shifts. | |
6892 | */ | |
6893 | static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode, | |
6894 | bool itof, int rmode, int scale, int sf, int type) | |
6895 | { | |
6896 | bool is_signed = !(opcode & 1); | |
52a1f6a3 | 6897 | TCGv_ptr tcg_fpstatus; |
564a0632 RH |
6898 | TCGv_i32 tcg_shift, tcg_single; |
6899 | TCGv_i64 tcg_double; | |
52a1f6a3 | 6900 | |
564a0632 | 6901 | tcg_fpstatus = get_fpstatus_ptr(type == 3); |
52a1f6a3 AG |
6902 | |
6903 | tcg_shift = tcg_const_i32(64 - scale); | |
6904 | ||
6905 | if (itof) { | |
6906 | TCGv_i64 tcg_int = cpu_reg(s, rn); | |
6907 | if (!sf) { | |
6908 | TCGv_i64 tcg_extend = new_tmp_a64(s); | |
6909 | ||
6910 | if (is_signed) { | |
6911 | tcg_gen_ext32s_i64(tcg_extend, tcg_int); | |
6912 | } else { | |
6913 | tcg_gen_ext32u_i64(tcg_extend, tcg_int); | |
6914 | } | |
6915 | ||
6916 | tcg_int = tcg_extend; | |
6917 | } | |
6918 | ||
564a0632 RH |
6919 | switch (type) { |
6920 | case 1: /* float64 */ | |
6921 | tcg_double = tcg_temp_new_i64(); | |
52a1f6a3 AG |
6922 | if (is_signed) { |
6923 | gen_helper_vfp_sqtod(tcg_double, tcg_int, | |
6924 | tcg_shift, tcg_fpstatus); | |
6925 | } else { | |
6926 | gen_helper_vfp_uqtod(tcg_double, tcg_int, | |
6927 | tcg_shift, tcg_fpstatus); | |
6928 | } | |
6929 | write_fp_dreg(s, rd, tcg_double); | |
6930 | tcg_temp_free_i64(tcg_double); | |
564a0632 RH |
6931 | break; |
6932 | ||
6933 | case 0: /* float32 */ | |
6934 | tcg_single = tcg_temp_new_i32(); | |
52a1f6a3 AG |
6935 | if (is_signed) { |
6936 | gen_helper_vfp_sqtos(tcg_single, tcg_int, | |
6937 | tcg_shift, tcg_fpstatus); | |
6938 | } else { | |
6939 | gen_helper_vfp_uqtos(tcg_single, tcg_int, | |
6940 | tcg_shift, tcg_fpstatus); | |
6941 | } | |
6942 | write_fp_sreg(s, rd, tcg_single); | |
6943 | tcg_temp_free_i32(tcg_single); | |
564a0632 RH |
6944 | break; |
6945 | ||
6946 | case 3: /* float16 */ | |
6947 | tcg_single = tcg_temp_new_i32(); | |
6948 | if (is_signed) { | |
6949 | gen_helper_vfp_sqtoh(tcg_single, tcg_int, | |
6950 | tcg_shift, tcg_fpstatus); | |
6951 | } else { | |
6952 | gen_helper_vfp_uqtoh(tcg_single, tcg_int, | |
6953 | tcg_shift, tcg_fpstatus); | |
6954 | } | |
6955 | write_fp_sreg(s, rd, tcg_single); | |
6956 | tcg_temp_free_i32(tcg_single); | |
6957 | break; | |
6958 | ||
6959 | default: | |
6960 | g_assert_not_reached(); | |
52a1f6a3 AG |
6961 | } |
6962 | } else { | |
6963 | TCGv_i64 tcg_int = cpu_reg(s, rd); | |
6964 | TCGv_i32 tcg_rmode; | |
6965 | ||
6966 | if (extract32(opcode, 2, 1)) { | |
6967 | /* There are too many rounding modes to all fit into rmode, | |
6968 | * so FCVTA[US] is a special case. | |
6969 | */ | |
6970 | rmode = FPROUNDING_TIEAWAY; | |
6971 | } | |
6972 | ||
6973 | tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode)); | |
6974 | ||
9b049916 | 6975 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); |
52a1f6a3 | 6976 | |
564a0632 RH |
6977 | switch (type) { |
6978 | case 1: /* float64 */ | |
6979 | tcg_double = read_fp_dreg(s, rn); | |
52a1f6a3 AG |
6980 | if (is_signed) { |
6981 | if (!sf) { | |
6982 | gen_helper_vfp_tosld(tcg_int, tcg_double, | |
6983 | tcg_shift, tcg_fpstatus); | |
6984 | } else { | |
6985 | gen_helper_vfp_tosqd(tcg_int, tcg_double, | |
6986 | tcg_shift, tcg_fpstatus); | |
6987 | } | |
6988 | } else { | |
6989 | if (!sf) { | |
6990 | gen_helper_vfp_tould(tcg_int, tcg_double, | |
6991 | tcg_shift, tcg_fpstatus); | |
6992 | } else { | |
6993 | gen_helper_vfp_touqd(tcg_int, tcg_double, | |
6994 | tcg_shift, tcg_fpstatus); | |
6995 | } | |
6996 | } | |
564a0632 RH |
6997 | if (!sf) { |
6998 | tcg_gen_ext32u_i64(tcg_int, tcg_int); | |
6999 | } | |
52a1f6a3 | 7000 | tcg_temp_free_i64(tcg_double); |
564a0632 RH |
7001 | break; |
7002 | ||
7003 | case 0: /* float32 */ | |
7004 | tcg_single = read_fp_sreg(s, rn); | |
52a1f6a3 AG |
7005 | if (sf) { |
7006 | if (is_signed) { | |
7007 | gen_helper_vfp_tosqs(tcg_int, tcg_single, | |
7008 | tcg_shift, tcg_fpstatus); | |
7009 | } else { | |
7010 | gen_helper_vfp_touqs(tcg_int, tcg_single, | |
7011 | tcg_shift, tcg_fpstatus); | |
7012 | } | |
7013 | } else { | |
7014 | TCGv_i32 tcg_dest = tcg_temp_new_i32(); | |
7015 | if (is_signed) { | |
7016 | gen_helper_vfp_tosls(tcg_dest, tcg_single, | |
7017 | tcg_shift, tcg_fpstatus); | |
7018 | } else { | |
7019 | gen_helper_vfp_touls(tcg_dest, tcg_single, | |
7020 | tcg_shift, tcg_fpstatus); | |
7021 | } | |
7022 | tcg_gen_extu_i32_i64(tcg_int, tcg_dest); | |
7023 | tcg_temp_free_i32(tcg_dest); | |
7024 | } | |
7025 | tcg_temp_free_i32(tcg_single); | |
564a0632 RH |
7026 | break; |
7027 | ||
7028 | case 3: /* float16 */ | |
7029 | tcg_single = read_fp_sreg(s, rn); | |
7030 | if (sf) { | |
7031 | if (is_signed) { | |
7032 | gen_helper_vfp_tosqh(tcg_int, tcg_single, | |
7033 | tcg_shift, tcg_fpstatus); | |
7034 | } else { | |
7035 | gen_helper_vfp_touqh(tcg_int, tcg_single, | |
7036 | tcg_shift, tcg_fpstatus); | |
7037 | } | |
7038 | } else { | |
7039 | TCGv_i32 tcg_dest = tcg_temp_new_i32(); | |
7040 | if (is_signed) { | |
7041 | gen_helper_vfp_toslh(tcg_dest, tcg_single, | |
7042 | tcg_shift, tcg_fpstatus); | |
7043 | } else { | |
7044 | gen_helper_vfp_toulh(tcg_dest, tcg_single, | |
7045 | tcg_shift, tcg_fpstatus); | |
7046 | } | |
7047 | tcg_gen_extu_i32_i64(tcg_int, tcg_dest); | |
7048 | tcg_temp_free_i32(tcg_dest); | |
7049 | } | |
7050 | tcg_temp_free_i32(tcg_single); | |
7051 | break; | |
7052 | ||
7053 | default: | |
7054 | g_assert_not_reached(); | |
52a1f6a3 AG |
7055 | } |
7056 | ||
9b049916 | 7057 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); |
52a1f6a3 | 7058 | tcg_temp_free_i32(tcg_rmode); |
52a1f6a3 AG |
7059 | } |
7060 | ||
7061 | tcg_temp_free_ptr(tcg_fpstatus); | |
7062 | tcg_temp_free_i32(tcg_shift); | |
7063 | } | |
7064 | ||
4ce31af4 | 7065 | /* Floating point <-> fixed point conversions |
faa0ba46 PM |
7066 | * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0 |
7067 | * +----+---+---+-----------+------+---+-------+--------+-------+------+------+ | |
7068 | * | sf | 0 | S | 1 1 1 1 0 | type | 0 | rmode | opcode | scale | Rn | Rd | | |
7069 | * +----+---+---+-----------+------+---+-------+--------+-------+------+------+ | |
7070 | */ | |
7071 | static void disas_fp_fixed_conv(DisasContext *s, uint32_t insn) | |
7072 | { | |
52a1f6a3 AG |
7073 | int rd = extract32(insn, 0, 5); |
7074 | int rn = extract32(insn, 5, 5); | |
7075 | int scale = extract32(insn, 10, 6); | |
7076 | int opcode = extract32(insn, 16, 3); | |
7077 | int rmode = extract32(insn, 19, 2); | |
7078 | int type = extract32(insn, 22, 2); | |
7079 | bool sbit = extract32(insn, 29, 1); | |
7080 | bool sf = extract32(insn, 31, 1); | |
7081 | bool itof; | |
7082 | ||
27527280 RH |
7083 | if (sbit || (!sf && scale < 32)) { |
7084 | unallocated_encoding(s); | |
7085 | return; | |
7086 | } | |
7087 | ||
7088 | switch (type) { | |
7089 | case 0: /* float32 */ | |
7090 | case 1: /* float64 */ | |
7091 | break; | |
7092 | case 3: /* float16 */ | |
5763190f | 7093 | if (dc_isar_feature(aa64_fp16, s)) { |
27527280 RH |
7094 | break; |
7095 | } | |
7096 | /* fallthru */ | |
7097 | default: | |
52a1f6a3 AG |
7098 | unallocated_encoding(s); |
7099 | return; | |
7100 | } | |
7101 | ||
7102 | switch ((rmode << 3) | opcode) { | |
7103 | case 0x2: /* SCVTF */ | |
7104 | case 0x3: /* UCVTF */ | |
7105 | itof = true; | |
7106 | break; | |
7107 | case 0x18: /* FCVTZS */ | |
7108 | case 0x19: /* FCVTZU */ | |
7109 | itof = false; | |
7110 | break; | |
7111 | default: | |
7112 | unallocated_encoding(s); | |
7113 | return; | |
7114 | } | |
7115 | ||
8c6afa6a PM |
7116 | if (!fp_access_check(s)) { |
7117 | return; | |
7118 | } | |
7119 | ||
52a1f6a3 | 7120 | handle_fpfpcvt(s, rd, rn, opcode, itof, FPROUNDING_ZERO, scale, sf, type); |
faa0ba46 PM |
7121 | } |
7122 | ||
ce5458e8 PM |
7123 | static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof) |
7124 | { | |
7125 | /* FMOV: gpr to or from float, double, or top half of quad fp reg, | |
7126 | * without conversion. | |
7127 | */ | |
7128 | ||
7129 | if (itof) { | |
ce5458e8 | 7130 | TCGv_i64 tcg_rn = cpu_reg(s, rn); |
9a9f1f59 | 7131 | TCGv_i64 tmp; |
ce5458e8 PM |
7132 | |
7133 | switch (type) { | |
7134 | case 0: | |
ce5458e8 | 7135 | /* 32 bit */ |
9a9f1f59 | 7136 | tmp = tcg_temp_new_i64(); |
ce5458e8 | 7137 | tcg_gen_ext32u_i64(tmp, tcg_rn); |
9a9f1f59 | 7138 | write_fp_dreg(s, rd, tmp); |
ce5458e8 PM |
7139 | tcg_temp_free_i64(tmp); |
7140 | break; | |
ce5458e8 | 7141 | case 1: |
ce5458e8 | 7142 | /* 64 bit */ |
9a9f1f59 | 7143 | write_fp_dreg(s, rd, tcg_rn); |
ce5458e8 | 7144 | break; |
ce5458e8 PM |
7145 | case 2: |
7146 | /* 64 bit to top half. */ | |
90e49638 | 7147 | tcg_gen_st_i64(tcg_rn, cpu_env, fp_reg_hi_offset(s, rd)); |
9a9f1f59 | 7148 | clear_vec_high(s, true, rd); |
ce5458e8 | 7149 | break; |
68130236 RH |
7150 | case 3: |
7151 | /* 16 bit */ | |
7152 | tmp = tcg_temp_new_i64(); | |
7153 | tcg_gen_ext16u_i64(tmp, tcg_rn); | |
7154 | write_fp_dreg(s, rd, tmp); | |
7155 | tcg_temp_free_i64(tmp); | |
7156 | break; | |
7157 | default: | |
7158 | g_assert_not_reached(); | |
ce5458e8 PM |
7159 | } |
7160 | } else { | |
ce5458e8 PM |
7161 | TCGv_i64 tcg_rd = cpu_reg(s, rd); |
7162 | ||
7163 | switch (type) { | |
7164 | case 0: | |
7165 | /* 32 bit */ | |
90e49638 | 7166 | tcg_gen_ld32u_i64(tcg_rd, cpu_env, fp_reg_offset(s, rn, MO_32)); |
ce5458e8 | 7167 | break; |
ce5458e8 PM |
7168 | case 1: |
7169 | /* 64 bit */ | |
90e49638 | 7170 | tcg_gen_ld_i64(tcg_rd, cpu_env, fp_reg_offset(s, rn, MO_64)); |
e2f90565 PM |
7171 | break; |
7172 | case 2: | |
7173 | /* 64 bits from top half */ | |
90e49638 | 7174 | tcg_gen_ld_i64(tcg_rd, cpu_env, fp_reg_hi_offset(s, rn)); |
ce5458e8 | 7175 | break; |
68130236 RH |
7176 | case 3: |
7177 | /* 16 bit */ | |
7178 | tcg_gen_ld16u_i64(tcg_rd, cpu_env, fp_reg_offset(s, rn, MO_16)); | |
7179 | break; | |
7180 | default: | |
7181 | g_assert_not_reached(); | |
ce5458e8 PM |
7182 | } |
7183 | } | |
7184 | } | |
7185 | ||
6c1f6f27 RH |
7186 | static void handle_fjcvtzs(DisasContext *s, int rd, int rn) |
7187 | { | |
7188 | TCGv_i64 t = read_fp_dreg(s, rn); | |
7189 | TCGv_ptr fpstatus = get_fpstatus_ptr(false); | |
7190 | ||
7191 | gen_helper_fjcvtzs(t, t, fpstatus); | |
7192 | ||
7193 | tcg_temp_free_ptr(fpstatus); | |
7194 | ||
7195 | tcg_gen_ext32u_i64(cpu_reg(s, rd), t); | |
7196 | tcg_gen_extrh_i64_i32(cpu_ZF, t); | |
7197 | tcg_gen_movi_i32(cpu_CF, 0); | |
7198 | tcg_gen_movi_i32(cpu_NF, 0); | |
7199 | tcg_gen_movi_i32(cpu_VF, 0); | |
7200 | ||
7201 | tcg_temp_free_i64(t); | |
7202 | } | |
7203 | ||
4ce31af4 | 7204 | /* Floating point <-> integer conversions |
faa0ba46 PM |
7205 | * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0 |
7206 | * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+ | |
c436d406 | 7207 | * | sf | 0 | S | 1 1 1 1 0 | type | 1 | rmode | opc | 0 0 0 0 0 0 | Rn | Rd | |
faa0ba46 PM |
7208 | * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+ |
7209 | */ | |
7210 | static void disas_fp_int_conv(DisasContext *s, uint32_t insn) | |
7211 | { | |
ce5458e8 PM |
7212 | int rd = extract32(insn, 0, 5); |
7213 | int rn = extract32(insn, 5, 5); | |
7214 | int opcode = extract32(insn, 16, 3); | |
7215 | int rmode = extract32(insn, 19, 2); | |
7216 | int type = extract32(insn, 22, 2); | |
7217 | bool sbit = extract32(insn, 29, 1); | |
7218 | bool sf = extract32(insn, 31, 1); | |
3c3ff684 | 7219 | bool itof = false; |
ce5458e8 | 7220 | |
c436d406 | 7221 | if (sbit) { |
3c3ff684 | 7222 | goto do_unallocated; |
c436d406 WN |
7223 | } |
7224 | ||
3c3ff684 RH |
7225 | switch (opcode) { |
7226 | case 2: /* SCVTF */ | |
7227 | case 3: /* UCVTF */ | |
7228 | itof = true; | |
7229 | /* fallthru */ | |
7230 | case 4: /* FCVTAS */ | |
7231 | case 5: /* FCVTAU */ | |
7232 | if (rmode != 0) { | |
7233 | goto do_unallocated; | |
c436d406 | 7234 | } |
3c3ff684 RH |
7235 | /* fallthru */ |
7236 | case 0: /* FCVT[NPMZ]S */ | |
7237 | case 1: /* FCVT[NPMZ]U */ | |
7238 | switch (type) { | |
7239 | case 0: /* float32 */ | |
7240 | case 1: /* float64 */ | |
ce5458e8 | 7241 | break; |
3c3ff684 RH |
7242 | case 3: /* float16 */ |
7243 | if (!dc_isar_feature(aa64_fp16, s)) { | |
7244 | goto do_unallocated; | |
68130236 | 7245 | } |
3c3ff684 | 7246 | break; |
ce5458e8 | 7247 | default: |
3c3ff684 | 7248 | goto do_unallocated; |
ce5458e8 | 7249 | } |
8c6afa6a PM |
7250 | if (!fp_access_check(s)) { |
7251 | return; | |
7252 | } | |
3c3ff684 RH |
7253 | handle_fpfpcvt(s, rd, rn, opcode, itof, rmode, 64, sf, type); |
7254 | break; | |
c436d406 | 7255 | |
3c3ff684 RH |
7256 | default: |
7257 | switch (sf << 7 | type << 5 | rmode << 3 | opcode) { | |
7258 | case 0b01100110: /* FMOV half <-> 32-bit int */ | |
7259 | case 0b01100111: | |
7260 | case 0b11100110: /* FMOV half <-> 64-bit int */ | |
7261 | case 0b11100111: | |
7262 | if (!dc_isar_feature(aa64_fp16, s)) { | |
7263 | goto do_unallocated; | |
564a0632 RH |
7264 | } |
7265 | /* fallthru */ | |
3c3ff684 RH |
7266 | case 0b00000110: /* FMOV 32-bit */ |
7267 | case 0b00000111: | |
7268 | case 0b10100110: /* FMOV 64-bit */ | |
7269 | case 0b10100111: | |
7270 | case 0b11001110: /* FMOV top half of 128-bit */ | |
7271 | case 0b11001111: | |
7272 | if (!fp_access_check(s)) { | |
7273 | return; | |
7274 | } | |
7275 | itof = opcode & 1; | |
7276 | handle_fmov(s, rd, rn, type, itof); | |
7277 | break; | |
7278 | ||
6c1f6f27 RH |
7279 | case 0b00111110: /* FJCVTZS */ |
7280 | if (!dc_isar_feature(aa64_jscvt, s)) { | |
7281 | goto do_unallocated; | |
7282 | } else if (fp_access_check(s)) { | |
7283 | handle_fjcvtzs(s, rd, rn); | |
7284 | } | |
7285 | break; | |
7286 | ||
564a0632 | 7287 | default: |
3c3ff684 | 7288 | do_unallocated: |
c436d406 WN |
7289 | unallocated_encoding(s); |
7290 | return; | |
7291 | } | |
3c3ff684 | 7292 | break; |
ce5458e8 | 7293 | } |
faa0ba46 PM |
7294 | } |
7295 | ||
7296 | /* FP-specific subcases of table C3-6 (SIMD and FP data processing) | |
7297 | * 31 30 29 28 25 24 0 | |
7298 | * +---+---+---+---------+-----------------------------+ | |
7299 | * | | 0 | | 1 1 1 1 | | | |
7300 | * +---+---+---+---------+-----------------------------+ | |
7301 | */ | |
7302 | static void disas_data_proc_fp(DisasContext *s, uint32_t insn) | |
7303 | { | |
7304 | if (extract32(insn, 24, 1)) { | |
7305 | /* Floating point data-processing (3 source) */ | |
7306 | disas_fp_3src(s, insn); | |
7307 | } else if (extract32(insn, 21, 1) == 0) { | |
7308 | /* Floating point to fixed point conversions */ | |
7309 | disas_fp_fixed_conv(s, insn); | |
7310 | } else { | |
7311 | switch (extract32(insn, 10, 2)) { | |
7312 | case 1: | |
7313 | /* Floating point conditional compare */ | |
7314 | disas_fp_ccomp(s, insn); | |
7315 | break; | |
7316 | case 2: | |
7317 | /* Floating point data-processing (2 source) */ | |
7318 | disas_fp_2src(s, insn); | |
7319 | break; | |
7320 | case 3: | |
7321 | /* Floating point conditional select */ | |
7322 | disas_fp_csel(s, insn); | |
7323 | break; | |
7324 | case 0: | |
7325 | switch (ctz32(extract32(insn, 12, 4))) { | |
7326 | case 0: /* [15:12] == xxx1 */ | |
7327 | /* Floating point immediate */ | |
7328 | disas_fp_imm(s, insn); | |
7329 | break; | |
7330 | case 1: /* [15:12] == xx10 */ | |
7331 | /* Floating point compare */ | |
7332 | disas_fp_compare(s, insn); | |
7333 | break; | |
7334 | case 2: /* [15:12] == x100 */ | |
7335 | /* Floating point data-processing (1 source) */ | |
7336 | disas_fp_1src(s, insn); | |
7337 | break; | |
7338 | case 3: /* [15:12] == 1000 */ | |
7339 | unallocated_encoding(s); | |
7340 | break; | |
7341 | default: /* [15:12] == 0000 */ | |
7342 | /* Floating point <-> integer conversions */ | |
7343 | disas_fp_int_conv(s, insn); | |
7344 | break; | |
7345 | } | |
7346 | break; | |
7347 | } | |
7348 | } | |
7349 | } | |
7350 | ||
5c73747f PM |
7351 | static void do_ext64(DisasContext *s, TCGv_i64 tcg_left, TCGv_i64 tcg_right, |
7352 | int pos) | |
7353 | { | |
7354 | /* Extract 64 bits from the middle of two concatenated 64 bit | |
7355 | * vector register slices left:right. The extracted bits start | |
7356 | * at 'pos' bits into the right (least significant) side. | |
7357 | * We return the result in tcg_right, and guarantee not to | |
7358 | * trash tcg_left. | |
7359 | */ | |
7360 | TCGv_i64 tcg_tmp = tcg_temp_new_i64(); | |
7361 | assert(pos > 0 && pos < 64); | |
7362 | ||
7363 | tcg_gen_shri_i64(tcg_right, tcg_right, pos); | |
7364 | tcg_gen_shli_i64(tcg_tmp, tcg_left, 64 - pos); | |
7365 | tcg_gen_or_i64(tcg_right, tcg_right, tcg_tmp); | |
7366 | ||
7367 | tcg_temp_free_i64(tcg_tmp); | |
7368 | } | |
7369 | ||
4ce31af4 | 7370 | /* EXT |
384b26fb AB |
7371 | * 31 30 29 24 23 22 21 20 16 15 14 11 10 9 5 4 0 |
7372 | * +---+---+-------------+-----+---+------+---+------+---+------+------+ | |
7373 | * | 0 | Q | 1 0 1 1 1 0 | op2 | 0 | Rm | 0 | imm4 | 0 | Rn | Rd | | |
7374 | * +---+---+-------------+-----+---+------+---+------+---+------+------+ | |
7375 | */ | |
7376 | static void disas_simd_ext(DisasContext *s, uint32_t insn) | |
7377 | { | |
5c73747f PM |
7378 | int is_q = extract32(insn, 30, 1); |
7379 | int op2 = extract32(insn, 22, 2); | |
7380 | int imm4 = extract32(insn, 11, 4); | |
7381 | int rm = extract32(insn, 16, 5); | |
7382 | int rn = extract32(insn, 5, 5); | |
7383 | int rd = extract32(insn, 0, 5); | |
7384 | int pos = imm4 << 3; | |
7385 | TCGv_i64 tcg_resl, tcg_resh; | |
7386 | ||
7387 | if (op2 != 0 || (!is_q && extract32(imm4, 3, 1))) { | |
7388 | unallocated_encoding(s); | |
7389 | return; | |
7390 | } | |
7391 | ||
8c6afa6a PM |
7392 | if (!fp_access_check(s)) { |
7393 | return; | |
7394 | } | |
7395 | ||
5c73747f PM |
7396 | tcg_resh = tcg_temp_new_i64(); |
7397 | tcg_resl = tcg_temp_new_i64(); | |
7398 | ||
7399 | /* Vd gets bits starting at pos bits into Vm:Vn. This is | |
7400 | * either extracting 128 bits from a 128:128 concatenation, or | |
7401 | * extracting 64 bits from a 64:64 concatenation. | |
7402 | */ | |
7403 | if (!is_q) { | |
7404 | read_vec_element(s, tcg_resl, rn, 0, MO_64); | |
7405 | if (pos != 0) { | |
7406 | read_vec_element(s, tcg_resh, rm, 0, MO_64); | |
7407 | do_ext64(s, tcg_resh, tcg_resl, pos); | |
7408 | } | |
5c73747f PM |
7409 | } else { |
7410 | TCGv_i64 tcg_hh; | |
7411 | typedef struct { | |
7412 | int reg; | |
7413 | int elt; | |
7414 | } EltPosns; | |
7415 | EltPosns eltposns[] = { {rn, 0}, {rn, 1}, {rm, 0}, {rm, 1} }; | |
7416 | EltPosns *elt = eltposns; | |
7417 | ||
7418 | if (pos >= 64) { | |
7419 | elt++; | |
7420 | pos -= 64; | |
7421 | } | |
7422 | ||
7423 | read_vec_element(s, tcg_resl, elt->reg, elt->elt, MO_64); | |
7424 | elt++; | |
7425 | read_vec_element(s, tcg_resh, elt->reg, elt->elt, MO_64); | |
7426 | elt++; | |
7427 | if (pos != 0) { | |
7428 | do_ext64(s, tcg_resh, tcg_resl, pos); | |
7429 | tcg_hh = tcg_temp_new_i64(); | |
7430 | read_vec_element(s, tcg_hh, elt->reg, elt->elt, MO_64); | |
7431 | do_ext64(s, tcg_hh, tcg_resh, pos); | |
7432 | tcg_temp_free_i64(tcg_hh); | |
7433 | } | |
7434 | } | |
7435 | ||
7436 | write_vec_element(s, tcg_resl, rd, 0, MO_64); | |
7437 | tcg_temp_free_i64(tcg_resl); | |
e1f77859 RH |
7438 | if (is_q) { |
7439 | write_vec_element(s, tcg_resh, rd, 1, MO_64); | |
7440 | } | |
5c73747f | 7441 | tcg_temp_free_i64(tcg_resh); |
e1f77859 | 7442 | clear_vec_high(s, is_q, rd); |
384b26fb AB |
7443 | } |
7444 | ||
4ce31af4 | 7445 | /* TBL/TBX |
384b26fb AB |
7446 | * 31 30 29 24 23 22 21 20 16 15 14 13 12 11 10 9 5 4 0 |
7447 | * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+ | |
7448 | * | 0 | Q | 0 0 1 1 1 0 | op2 | 0 | Rm | 0 | len | op | 0 0 | Rn | Rd | | |
7449 | * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+ | |
7450 | */ | |
7451 | static void disas_simd_tb(DisasContext *s, uint32_t insn) | |
7452 | { | |
7c51048f MM |
7453 | int op2 = extract32(insn, 22, 2); |
7454 | int is_q = extract32(insn, 30, 1); | |
7455 | int rm = extract32(insn, 16, 5); | |
7456 | int rn = extract32(insn, 5, 5); | |
7457 | int rd = extract32(insn, 0, 5); | |
7458 | int is_tblx = extract32(insn, 12, 1); | |
7459 | int len = extract32(insn, 13, 2); | |
7460 | TCGv_i64 tcg_resl, tcg_resh, tcg_idx; | |
7461 | TCGv_i32 tcg_regno, tcg_numregs; | |
7462 | ||
7463 | if (op2 != 0) { | |
7464 | unallocated_encoding(s); | |
7465 | return; | |
7466 | } | |
7467 | ||
8c6afa6a PM |
7468 | if (!fp_access_check(s)) { |
7469 | return; | |
7470 | } | |
7471 | ||
7c51048f MM |
7472 | /* This does a table lookup: for every byte element in the input |
7473 | * we index into a table formed from up to four vector registers, | |
7474 | * and then the output is the result of the lookups. Our helper | |
7475 | * function does the lookup operation for a single 64 bit part of | |
7476 | * the input. | |
7477 | */ | |
7478 | tcg_resl = tcg_temp_new_i64(); | |
e1f77859 | 7479 | tcg_resh = NULL; |
7c51048f MM |
7480 | |
7481 | if (is_tblx) { | |
7482 | read_vec_element(s, tcg_resl, rd, 0, MO_64); | |
7483 | } else { | |
7484 | tcg_gen_movi_i64(tcg_resl, 0); | |
7485 | } | |
e1f77859 RH |
7486 | |
7487 | if (is_q) { | |
7488 | tcg_resh = tcg_temp_new_i64(); | |
7489 | if (is_tblx) { | |
7490 | read_vec_element(s, tcg_resh, rd, 1, MO_64); | |
7491 | } else { | |
7492 | tcg_gen_movi_i64(tcg_resh, 0); | |
7493 | } | |
7c51048f MM |
7494 | } |
7495 | ||
7496 | tcg_idx = tcg_temp_new_i64(); | |
7497 | tcg_regno = tcg_const_i32(rn); | |
7498 | tcg_numregs = tcg_const_i32(len + 1); | |
7499 | read_vec_element(s, tcg_idx, rm, 0, MO_64); | |
7500 | gen_helper_simd_tbl(tcg_resl, cpu_env, tcg_resl, tcg_idx, | |
7501 | tcg_regno, tcg_numregs); | |
7502 | if (is_q) { | |
7503 | read_vec_element(s, tcg_idx, rm, 1, MO_64); | |
7504 | gen_helper_simd_tbl(tcg_resh, cpu_env, tcg_resh, tcg_idx, | |
7505 | tcg_regno, tcg_numregs); | |
7506 | } | |
7507 | tcg_temp_free_i64(tcg_idx); | |
7508 | tcg_temp_free_i32(tcg_regno); | |
7509 | tcg_temp_free_i32(tcg_numregs); | |
7510 | ||
7511 | write_vec_element(s, tcg_resl, rd, 0, MO_64); | |
7512 | tcg_temp_free_i64(tcg_resl); | |
e1f77859 RH |
7513 | |
7514 | if (is_q) { | |
7515 | write_vec_element(s, tcg_resh, rd, 1, MO_64); | |
7516 | tcg_temp_free_i64(tcg_resh); | |
7517 | } | |
7518 | clear_vec_high(s, is_q, rd); | |
384b26fb AB |
7519 | } |
7520 | ||
4ce31af4 | 7521 | /* ZIP/UZP/TRN |
384b26fb AB |
7522 | * 31 30 29 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0 |
7523 | * +---+---+-------------+------+---+------+---+------------------+------+ | |
7524 | * | 0 | Q | 0 0 1 1 1 0 | size | 0 | Rm | 0 | opc | 1 0 | Rn | Rd | | |
7525 | * +---+---+-------------+------+---+------+---+------------------+------+ | |
7526 | */ | |
7527 | static void disas_simd_zip_trn(DisasContext *s, uint32_t insn) | |
7528 | { | |
5fa5469c MM |
7529 | int rd = extract32(insn, 0, 5); |
7530 | int rn = extract32(insn, 5, 5); | |
7531 | int rm = extract32(insn, 16, 5); | |
7532 | int size = extract32(insn, 22, 2); | |
7533 | /* opc field bits [1:0] indicate ZIP/UZP/TRN; | |
7534 | * bit 2 indicates 1 vs 2 variant of the insn. | |
7535 | */ | |
7536 | int opcode = extract32(insn, 12, 2); | |
7537 | bool part = extract32(insn, 14, 1); | |
7538 | bool is_q = extract32(insn, 30, 1); | |
7539 | int esize = 8 << size; | |
7540 | int i, ofs; | |
7541 | int datasize = is_q ? 128 : 64; | |
7542 | int elements = datasize / esize; | |
7543 | TCGv_i64 tcg_res, tcg_resl, tcg_resh; | |
7544 | ||
7545 | if (opcode == 0 || (size == 3 && !is_q)) { | |
7546 | unallocated_encoding(s); | |
7547 | return; | |
7548 | } | |
7549 | ||
8c6afa6a PM |
7550 | if (!fp_access_check(s)) { |
7551 | return; | |
7552 | } | |
7553 | ||
5fa5469c | 7554 | tcg_resl = tcg_const_i64(0); |
e1f77859 | 7555 | tcg_resh = is_q ? tcg_const_i64(0) : NULL; |
5fa5469c MM |
7556 | tcg_res = tcg_temp_new_i64(); |
7557 | ||
7558 | for (i = 0; i < elements; i++) { | |
7559 | switch (opcode) { | |
7560 | case 1: /* UZP1/2 */ | |
7561 | { | |
7562 | int midpoint = elements / 2; | |
7563 | if (i < midpoint) { | |
7564 | read_vec_element(s, tcg_res, rn, 2 * i + part, size); | |
7565 | } else { | |
7566 | read_vec_element(s, tcg_res, rm, | |
7567 | 2 * (i - midpoint) + part, size); | |
7568 | } | |
7569 | break; | |
7570 | } | |
7571 | case 2: /* TRN1/2 */ | |
7572 | if (i & 1) { | |
7573 | read_vec_element(s, tcg_res, rm, (i & ~1) + part, size); | |
7574 | } else { | |
7575 | read_vec_element(s, tcg_res, rn, (i & ~1) + part, size); | |
7576 | } | |
7577 | break; | |
7578 | case 3: /* ZIP1/2 */ | |
7579 | { | |
7580 | int base = part * elements / 2; | |
7581 | if (i & 1) { | |
7582 | read_vec_element(s, tcg_res, rm, base + (i >> 1), size); | |
7583 | } else { | |
7584 | read_vec_element(s, tcg_res, rn, base + (i >> 1), size); | |
7585 | } | |
7586 | break; | |
7587 | } | |
7588 | default: | |
7589 | g_assert_not_reached(); | |
7590 | } | |
7591 | ||
7592 | ofs = i * esize; | |
7593 | if (ofs < 64) { | |
7594 | tcg_gen_shli_i64(tcg_res, tcg_res, ofs); | |
7595 | tcg_gen_or_i64(tcg_resl, tcg_resl, tcg_res); | |
7596 | } else { | |
7597 | tcg_gen_shli_i64(tcg_res, tcg_res, ofs - 64); | |
7598 | tcg_gen_or_i64(tcg_resh, tcg_resh, tcg_res); | |
7599 | } | |
7600 | } | |
7601 | ||
7602 | tcg_temp_free_i64(tcg_res); | |
7603 | ||
7604 | write_vec_element(s, tcg_resl, rd, 0, MO_64); | |
7605 | tcg_temp_free_i64(tcg_resl); | |
e1f77859 RH |
7606 | |
7607 | if (is_q) { | |
7608 | write_vec_element(s, tcg_resh, rd, 1, MO_64); | |
7609 | tcg_temp_free_i64(tcg_resh); | |
7610 | } | |
7611 | clear_vec_high(s, is_q, rd); | |
384b26fb AB |
7612 | } |
7613 | ||
807cdd50 AB |
7614 | /* |
7615 | * do_reduction_op helper | |
7616 | * | |
7617 | * This mirrors the Reduce() pseudocode in the ARM ARM. It is | |
7618 | * important for correct NaN propagation that we do these | |
7619 | * operations in exactly the order specified by the pseudocode. | |
7620 | * | |
7621 | * This is a recursive function, TCG temps should be freed by the | |
7622 | * calling function once it is done with the values. | |
7623 | */ | |
7624 | static TCGv_i32 do_reduction_op(DisasContext *s, int fpopcode, int rn, | |
7625 | int esize, int size, int vmap, TCGv_ptr fpst) | |
7626 | { | |
7627 | if (esize == size) { | |
7628 | int element; | |
14776ab5 | 7629 | MemOp msize = esize == 16 ? MO_16 : MO_32; |
807cdd50 AB |
7630 | TCGv_i32 tcg_elem; |
7631 | ||
7632 | /* We should have one register left here */ | |
7633 | assert(ctpop8(vmap) == 1); | |
7634 | element = ctz32(vmap); | |
7635 | assert(element < 8); | |
7636 | ||
7637 | tcg_elem = tcg_temp_new_i32(); | |
7638 | read_vec_element_i32(s, tcg_elem, rn, element, msize); | |
7639 | return tcg_elem; | |
4a0ff1ce | 7640 | } else { |
807cdd50 AB |
7641 | int bits = size / 2; |
7642 | int shift = ctpop8(vmap) / 2; | |
7643 | int vmap_lo = (vmap >> shift) & vmap; | |
7644 | int vmap_hi = (vmap & ~vmap_lo); | |
7645 | TCGv_i32 tcg_hi, tcg_lo, tcg_res; | |
7646 | ||
7647 | tcg_hi = do_reduction_op(s, fpopcode, rn, esize, bits, vmap_hi, fpst); | |
7648 | tcg_lo = do_reduction_op(s, fpopcode, rn, esize, bits, vmap_lo, fpst); | |
7649 | tcg_res = tcg_temp_new_i32(); | |
7650 | ||
7651 | switch (fpopcode) { | |
7652 | case 0x0c: /* fmaxnmv half-precision */ | |
7653 | gen_helper_advsimd_maxnumh(tcg_res, tcg_lo, tcg_hi, fpst); | |
7654 | break; | |
7655 | case 0x0f: /* fmaxv half-precision */ | |
7656 | gen_helper_advsimd_maxh(tcg_res, tcg_lo, tcg_hi, fpst); | |
7657 | break; | |
7658 | case 0x1c: /* fminnmv half-precision */ | |
7659 | gen_helper_advsimd_minnumh(tcg_res, tcg_lo, tcg_hi, fpst); | |
7660 | break; | |
7661 | case 0x1f: /* fminv half-precision */ | |
7662 | gen_helper_advsimd_minh(tcg_res, tcg_lo, tcg_hi, fpst); | |
7663 | break; | |
7664 | case 0x2c: /* fmaxnmv */ | |
7665 | gen_helper_vfp_maxnums(tcg_res, tcg_lo, tcg_hi, fpst); | |
7666 | break; | |
7667 | case 0x2f: /* fmaxv */ | |
7668 | gen_helper_vfp_maxs(tcg_res, tcg_lo, tcg_hi, fpst); | |
7669 | break; | |
7670 | case 0x3c: /* fminnmv */ | |
7671 | gen_helper_vfp_minnums(tcg_res, tcg_lo, tcg_hi, fpst); | |
7672 | break; | |
7673 | case 0x3f: /* fminv */ | |
7674 | gen_helper_vfp_mins(tcg_res, tcg_lo, tcg_hi, fpst); | |
7675 | break; | |
7676 | default: | |
7677 | g_assert_not_reached(); | |
4a0ff1ce | 7678 | } |
807cdd50 AB |
7679 | |
7680 | tcg_temp_free_i32(tcg_hi); | |
7681 | tcg_temp_free_i32(tcg_lo); | |
7682 | return tcg_res; | |
4a0ff1ce MM |
7683 | } |
7684 | } | |
7685 | ||
4ce31af4 | 7686 | /* AdvSIMD across lanes |
384b26fb AB |
7687 | * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0 |
7688 | * +---+---+---+-----------+------+-----------+--------+-----+------+------+ | |
7689 | * | 0 | Q | U | 0 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd | | |
7690 | * +---+---+---+-----------+------+-----------+--------+-----+------+------+ | |
7691 | */ | |
7692 | static void disas_simd_across_lanes(DisasContext *s, uint32_t insn) | |
7693 | { | |
4a0ff1ce MM |
7694 | int rd = extract32(insn, 0, 5); |
7695 | int rn = extract32(insn, 5, 5); | |
7696 | int size = extract32(insn, 22, 2); | |
7697 | int opcode = extract32(insn, 12, 5); | |
7698 | bool is_q = extract32(insn, 30, 1); | |
7699 | bool is_u = extract32(insn, 29, 1); | |
7700 | bool is_fp = false; | |
7701 | bool is_min = false; | |
7702 | int esize; | |
7703 | int elements; | |
7704 | int i; | |
7705 | TCGv_i64 tcg_res, tcg_elt; | |
7706 | ||
7707 | switch (opcode) { | |
7708 | case 0x1b: /* ADDV */ | |
7709 | if (is_u) { | |
7710 | unallocated_encoding(s); | |
7711 | return; | |
7712 | } | |
7713 | /* fall through */ | |
7714 | case 0x3: /* SADDLV, UADDLV */ | |
7715 | case 0xa: /* SMAXV, UMAXV */ | |
7716 | case 0x1a: /* SMINV, UMINV */ | |
7717 | if (size == 3 || (size == 2 && !is_q)) { | |
7718 | unallocated_encoding(s); | |
7719 | return; | |
7720 | } | |
7721 | break; | |
7722 | case 0xc: /* FMAXNMV, FMINNMV */ | |
7723 | case 0xf: /* FMAXV, FMINV */ | |
807cdd50 AB |
7724 | /* Bit 1 of size field encodes min vs max and the actual size |
7725 | * depends on the encoding of the U bit. If not set (and FP16 | |
7726 | * enabled) then we do half-precision float instead of single | |
7727 | * precision. | |
4a0ff1ce MM |
7728 | */ |
7729 | is_min = extract32(size, 1, 1); | |
7730 | is_fp = true; | |
5763190f | 7731 | if (!is_u && dc_isar_feature(aa64_fp16, s)) { |
807cdd50 AB |
7732 | size = 1; |
7733 | } else if (!is_u || !is_q || extract32(size, 0, 1)) { | |
7734 | unallocated_encoding(s); | |
7735 | return; | |
7736 | } else { | |
7737 | size = 2; | |
7738 | } | |
4a0ff1ce MM |
7739 | break; |
7740 | default: | |
7741 | unallocated_encoding(s); | |
7742 | return; | |
7743 | } | |
7744 | ||
8c6afa6a PM |
7745 | if (!fp_access_check(s)) { |
7746 | return; | |
7747 | } | |
7748 | ||
4a0ff1ce MM |
7749 | esize = 8 << size; |
7750 | elements = (is_q ? 128 : 64) / esize; | |
7751 | ||
7752 | tcg_res = tcg_temp_new_i64(); | |
7753 | tcg_elt = tcg_temp_new_i64(); | |
7754 | ||
7755 | /* These instructions operate across all lanes of a vector | |
7756 | * to produce a single result. We can guarantee that a 64 | |
7757 | * bit intermediate is sufficient: | |
7758 | * + for [US]ADDLV the maximum element size is 32 bits, and | |
7759 | * the result type is 64 bits | |
7760 | * + for FMAX*V, FMIN*V, ADDV the intermediate type is the | |
7761 | * same as the element size, which is 32 bits at most | |
7762 | * For the integer operations we can choose to work at 64 | |
7763 | * or 32 bits and truncate at the end; for simplicity | |
7764 | * we use 64 bits always. The floating point | |
7765 | * ops do require 32 bit intermediates, though. | |
7766 | */ | |
7767 | if (!is_fp) { | |
7768 | read_vec_element(s, tcg_res, rn, 0, size | (is_u ? 0 : MO_SIGN)); | |
7769 | ||
7770 | for (i = 1; i < elements; i++) { | |
7771 | read_vec_element(s, tcg_elt, rn, i, size | (is_u ? 0 : MO_SIGN)); | |
7772 | ||
7773 | switch (opcode) { | |
7774 | case 0x03: /* SADDLV / UADDLV */ | |
7775 | case 0x1b: /* ADDV */ | |
7776 | tcg_gen_add_i64(tcg_res, tcg_res, tcg_elt); | |
7777 | break; | |
7778 | case 0x0a: /* SMAXV / UMAXV */ | |
ecb8ab8d RH |
7779 | if (is_u) { |
7780 | tcg_gen_umax_i64(tcg_res, tcg_res, tcg_elt); | |
7781 | } else { | |
7782 | tcg_gen_smax_i64(tcg_res, tcg_res, tcg_elt); | |
7783 | } | |
4a0ff1ce MM |
7784 | break; |
7785 | case 0x1a: /* SMINV / UMINV */ | |
ecb8ab8d RH |
7786 | if (is_u) { |
7787 | tcg_gen_umin_i64(tcg_res, tcg_res, tcg_elt); | |
7788 | } else { | |
7789 | tcg_gen_smin_i64(tcg_res, tcg_res, tcg_elt); | |
7790 | } | |
4a0ff1ce MM |
7791 | break; |
7792 | default: | |
7793 | g_assert_not_reached(); | |
7794 | } | |
7795 | ||
7796 | } | |
7797 | } else { | |
807cdd50 AB |
7798 | /* Floating point vector reduction ops which work across 32 |
7799 | * bit (single) or 16 bit (half-precision) intermediates. | |
4a0ff1ce MM |
7800 | * Note that correct NaN propagation requires that we do these |
7801 | * operations in exactly the order specified by the pseudocode. | |
7802 | */ | |
807cdd50 AB |
7803 | TCGv_ptr fpst = get_fpstatus_ptr(size == MO_16); |
7804 | int fpopcode = opcode | is_min << 4 | is_u << 5; | |
7805 | int vmap = (1 << elements) - 1; | |
7806 | TCGv_i32 tcg_res32 = do_reduction_op(s, fpopcode, rn, esize, | |
7807 | (is_q ? 128 : 64), vmap, fpst); | |
7808 | tcg_gen_extu_i32_i64(tcg_res, tcg_res32); | |
7809 | tcg_temp_free_i32(tcg_res32); | |
4a0ff1ce MM |
7810 | tcg_temp_free_ptr(fpst); |
7811 | } | |
7812 | ||
7813 | tcg_temp_free_i64(tcg_elt); | |
7814 | ||
7815 | /* Now truncate the result to the width required for the final output */ | |
7816 | if (opcode == 0x03) { | |
7817 | /* SADDLV, UADDLV: result is 2*esize */ | |
7818 | size++; | |
7819 | } | |
7820 | ||
7821 | switch (size) { | |
7822 | case 0: | |
7823 | tcg_gen_ext8u_i64(tcg_res, tcg_res); | |
7824 | break; | |
7825 | case 1: | |
7826 | tcg_gen_ext16u_i64(tcg_res, tcg_res); | |
7827 | break; | |
7828 | case 2: | |
7829 | tcg_gen_ext32u_i64(tcg_res, tcg_res); | |
7830 | break; | |
7831 | case 3: | |
7832 | break; | |
7833 | default: | |
7834 | g_assert_not_reached(); | |
7835 | } | |
7836 | ||
7837 | write_fp_dreg(s, rd, tcg_res); | |
7838 | tcg_temp_free_i64(tcg_res); | |
384b26fb AB |
7839 | } |
7840 | ||
4ce31af4 | 7841 | /* DUP (Element, Vector) |
67bb9389 AB |
7842 | * |
7843 | * 31 30 29 21 20 16 15 10 9 5 4 0 | |
7844 | * +---+---+-------------------+--------+-------------+------+------+ | |
7845 | * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd | | |
7846 | * +---+---+-------------------+--------+-------------+------+------+ | |
7847 | * | |
7848 | * size: encoded in imm5 (see ARM ARM LowestSetBit()) | |
7849 | */ | |
7850 | static void handle_simd_dupe(DisasContext *s, int is_q, int rd, int rn, | |
7851 | int imm5) | |
7852 | { | |
7853 | int size = ctz32(imm5); | |
550a0489 | 7854 | int index; |
67bb9389 AB |
7855 | |
7856 | if (size > 3 || (size == 3 && !is_q)) { | |
7857 | unallocated_encoding(s); | |
7858 | return; | |
7859 | } | |
7860 | ||
8c6afa6a PM |
7861 | if (!fp_access_check(s)) { |
7862 | return; | |
7863 | } | |
7864 | ||
550a0489 | 7865 | index = imm5 >> (size + 1); |
861a1ded RH |
7866 | tcg_gen_gvec_dup_mem(size, vec_full_reg_offset(s, rd), |
7867 | vec_reg_offset(s, rn, index, size), | |
7868 | is_q ? 16 : 8, vec_full_reg_size(s)); | |
67bb9389 AB |
7869 | } |
7870 | ||
4ce31af4 | 7871 | /* DUP (element, scalar) |
360a6f2d PM |
7872 | * 31 21 20 16 15 10 9 5 4 0 |
7873 | * +-----------------------+--------+-------------+------+------+ | |
7874 | * | 0 1 0 1 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd | | |
7875 | * +-----------------------+--------+-------------+------+------+ | |
7876 | */ | |
7877 | static void handle_simd_dupes(DisasContext *s, int rd, int rn, | |
7878 | int imm5) | |
7879 | { | |
7880 | int size = ctz32(imm5); | |
7881 | int index; | |
7882 | TCGv_i64 tmp; | |
7883 | ||
7884 | if (size > 3) { | |
7885 | unallocated_encoding(s); | |
7886 | return; | |
7887 | } | |
7888 | ||
8c6afa6a PM |
7889 | if (!fp_access_check(s)) { |
7890 | return; | |
7891 | } | |
7892 | ||
360a6f2d PM |
7893 | index = imm5 >> (size + 1); |
7894 | ||
7895 | /* This instruction just extracts the specified element and | |
7896 | * zero-extends it into the bottom of the destination register. | |
7897 | */ | |
7898 | tmp = tcg_temp_new_i64(); | |
7899 | read_vec_element(s, tmp, rn, index, size); | |
7900 | write_fp_dreg(s, rd, tmp); | |
7901 | tcg_temp_free_i64(tmp); | |
7902 | } | |
7903 | ||
4ce31af4 | 7904 | /* DUP (General) |
67bb9389 AB |
7905 | * |
7906 | * 31 30 29 21 20 16 15 10 9 5 4 0 | |
7907 | * +---+---+-------------------+--------+-------------+------+------+ | |
7908 | * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 1 1 | Rn | Rd | | |
7909 | * +---+---+-------------------+--------+-------------+------+------+ | |
7910 | * | |
7911 | * size: encoded in imm5 (see ARM ARM LowestSetBit()) | |
7912 | */ | |
7913 | static void handle_simd_dupg(DisasContext *s, int is_q, int rd, int rn, | |
7914 | int imm5) | |
7915 | { | |
7916 | int size = ctz32(imm5); | |
861a1ded | 7917 | uint32_t dofs, oprsz, maxsz; |
67bb9389 AB |
7918 | |
7919 | if (size > 3 || ((size == 3) && !is_q)) { | |
7920 | unallocated_encoding(s); | |
7921 | return; | |
7922 | } | |
8c6afa6a PM |
7923 | |
7924 | if (!fp_access_check(s)) { | |
7925 | return; | |
7926 | } | |
7927 | ||
861a1ded RH |
7928 | dofs = vec_full_reg_offset(s, rd); |
7929 | oprsz = is_q ? 16 : 8; | |
7930 | maxsz = vec_full_reg_size(s); | |
7931 | ||
7932 | tcg_gen_gvec_dup_i64(size, dofs, oprsz, maxsz, cpu_reg(s, rn)); | |
67bb9389 AB |
7933 | } |
7934 | ||
4ce31af4 | 7935 | /* INS (Element) |
67bb9389 AB |
7936 | * |
7937 | * 31 21 20 16 15 14 11 10 9 5 4 0 | |
7938 | * +-----------------------+--------+------------+---+------+------+ | |
7939 | * | 0 1 1 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd | | |
7940 | * +-----------------------+--------+------------+---+------+------+ | |
7941 | * | |
7942 | * size: encoded in imm5 (see ARM ARM LowestSetBit()) | |
7943 | * index: encoded in imm5<4:size+1> | |
7944 | */ | |
7945 | static void handle_simd_inse(DisasContext *s, int rd, int rn, | |
7946 | int imm4, int imm5) | |
7947 | { | |
7948 | int size = ctz32(imm5); | |
7949 | int src_index, dst_index; | |
7950 | TCGv_i64 tmp; | |
7951 | ||
7952 | if (size > 3) { | |
7953 | unallocated_encoding(s); | |
7954 | return; | |
7955 | } | |
8c6afa6a PM |
7956 | |
7957 | if (!fp_access_check(s)) { | |
7958 | return; | |
7959 | } | |
7960 | ||
67bb9389 AB |
7961 | dst_index = extract32(imm5, 1+size, 5); |
7962 | src_index = extract32(imm4, size, 4); | |
7963 | ||
7964 | tmp = tcg_temp_new_i64(); | |
7965 | ||
7966 | read_vec_element(s, tmp, rn, src_index, size); | |
7967 | write_vec_element(s, tmp, rd, dst_index, size); | |
7968 | ||
7969 | tcg_temp_free_i64(tmp); | |
528dc354 RH |
7970 | |
7971 | /* INS is considered a 128-bit write for SVE. */ | |
7972 | clear_vec_high(s, true, rd); | |
67bb9389 AB |
7973 | } |
7974 | ||
7975 | ||
4ce31af4 | 7976 | /* INS (General) |
67bb9389 AB |
7977 | * |
7978 | * 31 21 20 16 15 10 9 5 4 0 | |
7979 | * +-----------------------+--------+-------------+------+------+ | |
7980 | * | 0 1 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 1 1 1 | Rn | Rd | | |
7981 | * +-----------------------+--------+-------------+------+------+ | |
7982 | * | |
7983 | * size: encoded in imm5 (see ARM ARM LowestSetBit()) | |
7984 | * index: encoded in imm5<4:size+1> | |
7985 | */ | |
7986 | static void handle_simd_insg(DisasContext *s, int rd, int rn, int imm5) | |
7987 | { | |
7988 | int size = ctz32(imm5); | |
7989 | int idx; | |
7990 | ||
7991 | if (size > 3) { | |
7992 | unallocated_encoding(s); | |
7993 | return; | |
7994 | } | |
7995 | ||
8c6afa6a PM |
7996 | if (!fp_access_check(s)) { |
7997 | return; | |
7998 | } | |
7999 | ||
67bb9389 AB |
8000 | idx = extract32(imm5, 1 + size, 4 - size); |
8001 | write_vec_element(s, cpu_reg(s, rn), rd, idx, size); | |
528dc354 RH |
8002 | |
8003 | /* INS is considered a 128-bit write for SVE. */ | |
8004 | clear_vec_high(s, true, rd); | |
67bb9389 AB |
8005 | } |
8006 | ||
8007 | /* | |
4ce31af4 PM |
8008 | * UMOV (General) |
8009 | * SMOV (General) | |
67bb9389 AB |
8010 | * |
8011 | * 31 30 29 21 20 16 15 12 10 9 5 4 0 | |
8012 | * +---+---+-------------------+--------+-------------+------+------+ | |
8013 | * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 1 U 1 1 | Rn | Rd | | |
8014 | * +---+---+-------------------+--------+-------------+------+------+ | |
8015 | * | |
8016 | * U: unsigned when set | |
8017 | * size: encoded in imm5 (see ARM ARM LowestSetBit()) | |
8018 | */ | |
8019 | static void handle_simd_umov_smov(DisasContext *s, int is_q, int is_signed, | |
8020 | int rn, int rd, int imm5) | |
8021 | { | |
8022 | int size = ctz32(imm5); | |
8023 | int element; | |
8024 | TCGv_i64 tcg_rd; | |
8025 | ||
8026 | /* Check for UnallocatedEncodings */ | |
8027 | if (is_signed) { | |
8028 | if (size > 2 || (size == 2 && !is_q)) { | |
8029 | unallocated_encoding(s); | |
8030 | return; | |
8031 | } | |
8032 | } else { | |
8033 | if (size > 3 | |
8034 | || (size < 3 && is_q) | |
8035 | || (size == 3 && !is_q)) { | |
8036 | unallocated_encoding(s); | |
8037 | return; | |
8038 | } | |
8039 | } | |
8c6afa6a PM |
8040 | |
8041 | if (!fp_access_check(s)) { | |
8042 | return; | |
8043 | } | |
8044 | ||
67bb9389 AB |
8045 | element = extract32(imm5, 1+size, 4); |
8046 | ||
8047 | tcg_rd = cpu_reg(s, rd); | |
8048 | read_vec_element(s, tcg_rd, rn, element, size | (is_signed ? MO_SIGN : 0)); | |
8049 | if (is_signed && !is_q) { | |
8050 | tcg_gen_ext32u_i64(tcg_rd, tcg_rd); | |
8051 | } | |
8052 | } | |
8053 | ||
4ce31af4 | 8054 | /* AdvSIMD copy |
384b26fb AB |
8055 | * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0 |
8056 | * +---+---+----+-----------------+------+---+------+---+------+------+ | |
8057 | * | 0 | Q | op | 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd | | |
8058 | * +---+---+----+-----------------+------+---+------+---+------+------+ | |
8059 | */ | |
8060 | static void disas_simd_copy(DisasContext *s, uint32_t insn) | |
8061 | { | |
67bb9389 AB |
8062 | int rd = extract32(insn, 0, 5); |
8063 | int rn = extract32(insn, 5, 5); | |
8064 | int imm4 = extract32(insn, 11, 4); | |
8065 | int op = extract32(insn, 29, 1); | |
8066 | int is_q = extract32(insn, 30, 1); | |
8067 | int imm5 = extract32(insn, 16, 5); | |
8068 | ||
8069 | if (op) { | |
8070 | if (is_q) { | |
8071 | /* INS (element) */ | |
8072 | handle_simd_inse(s, rd, rn, imm4, imm5); | |
8073 | } else { | |
8074 | unallocated_encoding(s); | |
8075 | } | |
8076 | } else { | |
8077 | switch (imm4) { | |
8078 | case 0: | |
8079 | /* DUP (element - vector) */ | |
8080 | handle_simd_dupe(s, is_q, rd, rn, imm5); | |
8081 | break; | |
8082 | case 1: | |
8083 | /* DUP (general) */ | |
8084 | handle_simd_dupg(s, is_q, rd, rn, imm5); | |
8085 | break; | |
8086 | case 3: | |
8087 | if (is_q) { | |
8088 | /* INS (general) */ | |
8089 | handle_simd_insg(s, rd, rn, imm5); | |
8090 | } else { | |
8091 | unallocated_encoding(s); | |
8092 | } | |
8093 | break; | |
8094 | case 5: | |
8095 | case 7: | |
8096 | /* UMOV/SMOV (is_q indicates 32/64; imm4 indicates signedness) */ | |
8097 | handle_simd_umov_smov(s, is_q, (imm4 == 5), rn, rd, imm5); | |
8098 | break; | |
8099 | default: | |
8100 | unallocated_encoding(s); | |
8101 | break; | |
8102 | } | |
8103 | } | |
384b26fb AB |
8104 | } |
8105 | ||
4ce31af4 | 8106 | /* AdvSIMD modified immediate |
384b26fb AB |
8107 | * 31 30 29 28 19 18 16 15 12 11 10 9 5 4 0 |
8108 | * +---+---+----+---------------------+-----+-------+----+---+-------+------+ | |
8109 | * | 0 | Q | op | 0 1 1 1 1 0 0 0 0 0 | abc | cmode | o2 | 1 | defgh | Rd | | |
8110 | * +---+---+----+---------------------+-----+-------+----+---+-------+------+ | |
f3f8c4f4 AB |
8111 | * |
8112 | * There are a number of operations that can be carried out here: | |
8113 | * MOVI - move (shifted) imm into register | |
8114 | * MVNI - move inverted (shifted) imm into register | |
8115 | * ORR - bitwise OR of (shifted) imm with register | |
8116 | * BIC - bitwise clear of (shifted) imm with register | |
70b4e6a4 AB |
8117 | * With ARMv8.2 we also have: |
8118 | * FMOV half-precision | |
384b26fb AB |
8119 | */ |
8120 | static void disas_simd_mod_imm(DisasContext *s, uint32_t insn) | |
8121 | { | |
f3f8c4f4 AB |
8122 | int rd = extract32(insn, 0, 5); |
8123 | int cmode = extract32(insn, 12, 4); | |
8124 | int cmode_3_1 = extract32(cmode, 1, 3); | |
8125 | int cmode_0 = extract32(cmode, 0, 1); | |
8126 | int o2 = extract32(insn, 11, 1); | |
8127 | uint64_t abcdefgh = extract32(insn, 5, 5) | (extract32(insn, 16, 3) << 5); | |
8128 | bool is_neg = extract32(insn, 29, 1); | |
8129 | bool is_q = extract32(insn, 30, 1); | |
8130 | uint64_t imm = 0; | |
f3f8c4f4 AB |
8131 | |
8132 | if (o2 != 0 || ((cmode == 0xf) && is_neg && !is_q)) { | |
70b4e6a4 | 8133 | /* Check for FMOV (vector, immediate) - half-precision */ |
5763190f | 8134 | if (!(dc_isar_feature(aa64_fp16, s) && o2 && cmode == 0xf)) { |
70b4e6a4 AB |
8135 | unallocated_encoding(s); |
8136 | return; | |
8137 | } | |
f3f8c4f4 AB |
8138 | } |
8139 | ||
8c6afa6a PM |
8140 | if (!fp_access_check(s)) { |
8141 | return; | |
8142 | } | |
8143 | ||
f3f8c4f4 AB |
8144 | /* See AdvSIMDExpandImm() in ARM ARM */ |
8145 | switch (cmode_3_1) { | |
8146 | case 0: /* Replicate(Zeros(24):imm8, 2) */ | |
8147 | case 1: /* Replicate(Zeros(16):imm8:Zeros(8), 2) */ | |
8148 | case 2: /* Replicate(Zeros(8):imm8:Zeros(16), 2) */ | |
8149 | case 3: /* Replicate(imm8:Zeros(24), 2) */ | |
8150 | { | |
8151 | int shift = cmode_3_1 * 8; | |
8152 | imm = bitfield_replicate(abcdefgh << shift, 32); | |
8153 | break; | |
8154 | } | |
8155 | case 4: /* Replicate(Zeros(8):imm8, 4) */ | |
8156 | case 5: /* Replicate(imm8:Zeros(8), 4) */ | |
8157 | { | |
8158 | int shift = (cmode_3_1 & 0x1) * 8; | |
8159 | imm = bitfield_replicate(abcdefgh << shift, 16); | |
8160 | break; | |
8161 | } | |
8162 | case 6: | |
8163 | if (cmode_0) { | |
8164 | /* Replicate(Zeros(8):imm8:Ones(16), 2) */ | |
8165 | imm = (abcdefgh << 16) | 0xffff; | |
8166 | } else { | |
8167 | /* Replicate(Zeros(16):imm8:Ones(8), 2) */ | |
8168 | imm = (abcdefgh << 8) | 0xff; | |
8169 | } | |
8170 | imm = bitfield_replicate(imm, 32); | |
8171 | break; | |
8172 | case 7: | |
8173 | if (!cmode_0 && !is_neg) { | |
8174 | imm = bitfield_replicate(abcdefgh, 8); | |
8175 | } else if (!cmode_0 && is_neg) { | |
8176 | int i; | |
8177 | imm = 0; | |
8178 | for (i = 0; i < 8; i++) { | |
8179 | if ((abcdefgh) & (1 << i)) { | |
8180 | imm |= 0xffULL << (i * 8); | |
8181 | } | |
8182 | } | |
8183 | } else if (cmode_0) { | |
8184 | if (is_neg) { | |
8185 | imm = (abcdefgh & 0x3f) << 48; | |
8186 | if (abcdefgh & 0x80) { | |
8187 | imm |= 0x8000000000000000ULL; | |
8188 | } | |
8189 | if (abcdefgh & 0x40) { | |
8190 | imm |= 0x3fc0000000000000ULL; | |
8191 | } else { | |
8192 | imm |= 0x4000000000000000ULL; | |
8193 | } | |
8194 | } else { | |
70b4e6a4 AB |
8195 | if (o2) { |
8196 | /* FMOV (vector, immediate) - half-precision */ | |
8197 | imm = vfp_expand_imm(MO_16, abcdefgh); | |
8198 | /* now duplicate across the lanes */ | |
8199 | imm = bitfield_replicate(imm, 16); | |
f3f8c4f4 | 8200 | } else { |
70b4e6a4 AB |
8201 | imm = (abcdefgh & 0x3f) << 19; |
8202 | if (abcdefgh & 0x80) { | |
8203 | imm |= 0x80000000; | |
8204 | } | |
8205 | if (abcdefgh & 0x40) { | |
8206 | imm |= 0x3e000000; | |
8207 | } else { | |
8208 | imm |= 0x40000000; | |
8209 | } | |
8210 | imm |= (imm << 32); | |
f3f8c4f4 | 8211 | } |
f3f8c4f4 AB |
8212 | } |
8213 | } | |
8214 | break; | |
70b4e6a4 AB |
8215 | default: |
8216 | fprintf(stderr, "%s: cmode_3_1: %x\n", __func__, cmode_3_1); | |
8217 | g_assert_not_reached(); | |
f3f8c4f4 AB |
8218 | } |
8219 | ||
8220 | if (cmode_3_1 != 7 && is_neg) { | |
8221 | imm = ~imm; | |
8222 | } | |
8223 | ||
861a1ded RH |
8224 | if (!((cmode & 0x9) == 0x1 || (cmode & 0xd) == 0x9)) { |
8225 | /* MOVI or MVNI, with MVNI negation handled above. */ | |
8711e71f RH |
8226 | tcg_gen_gvec_dup_imm(MO_64, vec_full_reg_offset(s, rd), is_q ? 16 : 8, |
8227 | vec_full_reg_size(s), imm); | |
861a1ded | 8228 | } else { |
064e265d RH |
8229 | /* ORR or BIC, with BIC negation to AND handled above. */ |
8230 | if (is_neg) { | |
8231 | gen_gvec_fn2i(s, is_q, rd, rd, imm, tcg_gen_gvec_andi, MO_64); | |
8232 | } else { | |
8233 | gen_gvec_fn2i(s, is_q, rd, rd, imm, tcg_gen_gvec_ori, MO_64); | |
f3f8c4f4 | 8234 | } |
861a1ded | 8235 | } |
384b26fb AB |
8236 | } |
8237 | ||
4ce31af4 | 8238 | /* AdvSIMD scalar copy |
384b26fb AB |
8239 | * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0 |
8240 | * +-----+----+-----------------+------+---+------+---+------+------+ | |
8241 | * | 0 1 | op | 1 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd | | |
8242 | * +-----+----+-----------------+------+---+------+---+------+------+ | |
8243 | */ | |
8244 | static void disas_simd_scalar_copy(DisasContext *s, uint32_t insn) | |
8245 | { | |
360a6f2d PM |
8246 | int rd = extract32(insn, 0, 5); |
8247 | int rn = extract32(insn, 5, 5); | |
8248 | int imm4 = extract32(insn, 11, 4); | |
8249 | int imm5 = extract32(insn, 16, 5); | |
8250 | int op = extract32(insn, 29, 1); | |
8251 | ||
8252 | if (op != 0 || imm4 != 0) { | |
8253 | unallocated_encoding(s); | |
8254 | return; | |
8255 | } | |
8256 | ||
8257 | /* DUP (element, scalar) */ | |
8258 | handle_simd_dupes(s, rd, rn, imm5); | |
384b26fb AB |
8259 | } |
8260 | ||
4ce31af4 | 8261 | /* AdvSIMD scalar pairwise |
384b26fb AB |
8262 | * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0 |
8263 | * +-----+---+-----------+------+-----------+--------+-----+------+------+ | |
8264 | * | 0 1 | U | 1 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd | | |
8265 | * +-----+---+-----------+------+-----------+--------+-----+------+------+ | |
8266 | */ | |
8267 | static void disas_simd_scalar_pairwise(DisasContext *s, uint32_t insn) | |
8268 | { | |
3720a7ea PM |
8269 | int u = extract32(insn, 29, 1); |
8270 | int size = extract32(insn, 22, 2); | |
8271 | int opcode = extract32(insn, 12, 5); | |
8272 | int rn = extract32(insn, 5, 5); | |
8273 | int rd = extract32(insn, 0, 5); | |
8274 | TCGv_ptr fpst; | |
8275 | ||
8276 | /* For some ops (the FP ones), size[1] is part of the encoding. | |
8277 | * For ADDP strictly it is not but size[1] is always 1 for valid | |
8278 | * encodings. | |
8279 | */ | |
8280 | opcode |= (extract32(size, 1, 1) << 5); | |
8281 | ||
8282 | switch (opcode) { | |
8283 | case 0x3b: /* ADDP */ | |
8284 | if (u || size != 3) { | |
8285 | unallocated_encoding(s); | |
8286 | return; | |
8287 | } | |
8c6afa6a PM |
8288 | if (!fp_access_check(s)) { |
8289 | return; | |
8290 | } | |
8291 | ||
f764718d | 8292 | fpst = NULL; |
3720a7ea PM |
8293 | break; |
8294 | case 0xc: /* FMAXNMP */ | |
8295 | case 0xd: /* FADDP */ | |
8296 | case 0xf: /* FMAXP */ | |
8297 | case 0x2c: /* FMINNMP */ | |
8298 | case 0x2f: /* FMINP */ | |
5c36d895 | 8299 | /* FP op, size[0] is 32 or 64 bit*/ |
3720a7ea | 8300 | if (!u) { |
5763190f | 8301 | if (!dc_isar_feature(aa64_fp16, s)) { |
5c36d895 AB |
8302 | unallocated_encoding(s); |
8303 | return; | |
8304 | } else { | |
8305 | size = MO_16; | |
8306 | } | |
8307 | } else { | |
8308 | size = extract32(size, 0, 1) ? MO_64 : MO_32; | |
3720a7ea | 8309 | } |
5c36d895 | 8310 | |
8c6afa6a PM |
8311 | if (!fp_access_check(s)) { |
8312 | return; | |
8313 | } | |
8314 | ||
5c36d895 | 8315 | fpst = get_fpstatus_ptr(size == MO_16); |
3720a7ea PM |
8316 | break; |
8317 | default: | |
8318 | unallocated_encoding(s); | |
8319 | return; | |
8320 | } | |
8321 | ||
5c36d895 | 8322 | if (size == MO_64) { |
3720a7ea PM |
8323 | TCGv_i64 tcg_op1 = tcg_temp_new_i64(); |
8324 | TCGv_i64 tcg_op2 = tcg_temp_new_i64(); | |
8325 | TCGv_i64 tcg_res = tcg_temp_new_i64(); | |
8326 | ||
8327 | read_vec_element(s, tcg_op1, rn, 0, MO_64); | |
8328 | read_vec_element(s, tcg_op2, rn, 1, MO_64); | |
8329 | ||
8330 | switch (opcode) { | |
8331 | case 0x3b: /* ADDP */ | |
8332 | tcg_gen_add_i64(tcg_res, tcg_op1, tcg_op2); | |
8333 | break; | |
8334 | case 0xc: /* FMAXNMP */ | |
8335 | gen_helper_vfp_maxnumd(tcg_res, tcg_op1, tcg_op2, fpst); | |
8336 | break; | |
8337 | case 0xd: /* FADDP */ | |
8338 | gen_helper_vfp_addd(tcg_res, tcg_op1, tcg_op2, fpst); | |
8339 | break; | |
8340 | case 0xf: /* FMAXP */ | |
8341 | gen_helper_vfp_maxd(tcg_res, tcg_op1, tcg_op2, fpst); | |
8342 | break; | |
8343 | case 0x2c: /* FMINNMP */ | |
8344 | gen_helper_vfp_minnumd(tcg_res, tcg_op1, tcg_op2, fpst); | |
8345 | break; | |
8346 | case 0x2f: /* FMINP */ | |
8347 | gen_helper_vfp_mind(tcg_res, tcg_op1, tcg_op2, fpst); | |
8348 | break; | |
8349 | default: | |
8350 | g_assert_not_reached(); | |
8351 | } | |
8352 | ||
8353 | write_fp_dreg(s, rd, tcg_res); | |
8354 | ||
8355 | tcg_temp_free_i64(tcg_op1); | |
8356 | tcg_temp_free_i64(tcg_op2); | |
8357 | tcg_temp_free_i64(tcg_res); | |
8358 | } else { | |
8359 | TCGv_i32 tcg_op1 = tcg_temp_new_i32(); | |
8360 | TCGv_i32 tcg_op2 = tcg_temp_new_i32(); | |
8361 | TCGv_i32 tcg_res = tcg_temp_new_i32(); | |
8362 | ||
5c36d895 AB |
8363 | read_vec_element_i32(s, tcg_op1, rn, 0, size); |
8364 | read_vec_element_i32(s, tcg_op2, rn, 1, size); | |
3720a7ea | 8365 | |
5c36d895 AB |
8366 | if (size == MO_16) { |
8367 | switch (opcode) { | |
8368 | case 0xc: /* FMAXNMP */ | |
8369 | gen_helper_advsimd_maxnumh(tcg_res, tcg_op1, tcg_op2, fpst); | |
8370 | break; | |
8371 | case 0xd: /* FADDP */ | |
8372 | gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst); | |
8373 | break; | |
8374 | case 0xf: /* FMAXP */ | |
8375 | gen_helper_advsimd_maxh(tcg_res, tcg_op1, tcg_op2, fpst); | |
8376 | break; | |
8377 | case 0x2c: /* FMINNMP */ | |
8378 | gen_helper_advsimd_minnumh(tcg_res, tcg_op1, tcg_op2, fpst); | |
8379 | break; | |
8380 | case 0x2f: /* FMINP */ | |
8381 | gen_helper_advsimd_minh(tcg_res, tcg_op1, tcg_op2, fpst); | |
8382 | break; | |
8383 | default: | |
8384 | g_assert_not_reached(); | |
8385 | } | |
8386 | } else { | |
8387 | switch (opcode) { | |
8388 | case 0xc: /* FMAXNMP */ | |
8389 | gen_helper_vfp_maxnums(tcg_res, tcg_op1, tcg_op2, fpst); | |
8390 | break; | |
8391 | case 0xd: /* FADDP */ | |
8392 | gen_helper_vfp_adds(tcg_res, tcg_op1, tcg_op2, fpst); | |
8393 | break; | |
8394 | case 0xf: /* FMAXP */ | |
8395 | gen_helper_vfp_maxs(tcg_res, tcg_op1, tcg_op2, fpst); | |
8396 | break; | |
8397 | case 0x2c: /* FMINNMP */ | |
8398 | gen_helper_vfp_minnums(tcg_res, tcg_op1, tcg_op2, fpst); | |
8399 | break; | |
8400 | case 0x2f: /* FMINP */ | |
8401 | gen_helper_vfp_mins(tcg_res, tcg_op1, tcg_op2, fpst); | |
8402 | break; | |
8403 | default: | |
8404 | g_assert_not_reached(); | |
8405 | } | |
3720a7ea PM |
8406 | } |
8407 | ||
8408 | write_fp_sreg(s, rd, tcg_res); | |
8409 | ||
8410 | tcg_temp_free_i32(tcg_op1); | |
8411 | tcg_temp_free_i32(tcg_op2); | |
8412 | tcg_temp_free_i32(tcg_res); | |
8413 | } | |
8414 | ||
f764718d | 8415 | if (fpst) { |
3720a7ea PM |
8416 | tcg_temp_free_ptr(fpst); |
8417 | } | |
384b26fb AB |
8418 | } |
8419 | ||
4d1cef84 AB |
8420 | /* |
8421 | * Common SSHR[RA]/USHR[RA] - Shift right (optional rounding/accumulate) | |
8422 | * | |
8423 | * This code is handles the common shifting code and is used by both | |
8424 | * the vector and scalar code. | |
8425 | */ | |
8426 | static void handle_shri_with_rndacc(TCGv_i64 tcg_res, TCGv_i64 tcg_src, | |
8427 | TCGv_i64 tcg_rnd, bool accumulate, | |
8428 | bool is_u, int size, int shift) | |
8429 | { | |
8430 | bool extended_result = false; | |
f764718d | 8431 | bool round = tcg_rnd != NULL; |
4d1cef84 AB |
8432 | int ext_lshift = 0; |
8433 | TCGv_i64 tcg_src_hi; | |
8434 | ||
8435 | if (round && size == 3) { | |
8436 | extended_result = true; | |
8437 | ext_lshift = 64 - shift; | |
8438 | tcg_src_hi = tcg_temp_new_i64(); | |
8439 | } else if (shift == 64) { | |
8440 | if (!accumulate && is_u) { | |
8441 | /* result is zero */ | |
8442 | tcg_gen_movi_i64(tcg_res, 0); | |
8443 | return; | |
8444 | } | |
8445 | } | |
8446 | ||
8447 | /* Deal with the rounding step */ | |
8448 | if (round) { | |
8449 | if (extended_result) { | |
8450 | TCGv_i64 tcg_zero = tcg_const_i64(0); | |
8451 | if (!is_u) { | |
8452 | /* take care of sign extending tcg_res */ | |
8453 | tcg_gen_sari_i64(tcg_src_hi, tcg_src, 63); | |
8454 | tcg_gen_add2_i64(tcg_src, tcg_src_hi, | |
8455 | tcg_src, tcg_src_hi, | |
8456 | tcg_rnd, tcg_zero); | |
8457 | } else { | |
8458 | tcg_gen_add2_i64(tcg_src, tcg_src_hi, | |
8459 | tcg_src, tcg_zero, | |
8460 | tcg_rnd, tcg_zero); | |
8461 | } | |
8462 | tcg_temp_free_i64(tcg_zero); | |
8463 | } else { | |
8464 | tcg_gen_add_i64(tcg_src, tcg_src, tcg_rnd); | |
8465 | } | |
8466 | } | |
8467 | ||
8468 | /* Now do the shift right */ | |
8469 | if (round && extended_result) { | |
8470 | /* extended case, >64 bit precision required */ | |
8471 | if (ext_lshift == 0) { | |
8472 | /* special case, only high bits matter */ | |
8473 | tcg_gen_mov_i64(tcg_src, tcg_src_hi); | |
8474 | } else { | |
8475 | tcg_gen_shri_i64(tcg_src, tcg_src, shift); | |
8476 | tcg_gen_shli_i64(tcg_src_hi, tcg_src_hi, ext_lshift); | |
8477 | tcg_gen_or_i64(tcg_src, tcg_src, tcg_src_hi); | |
8478 | } | |
8479 | } else { | |
8480 | if (is_u) { | |
8481 | if (shift == 64) { | |
8482 | /* essentially shifting in 64 zeros */ | |
8483 | tcg_gen_movi_i64(tcg_src, 0); | |
8484 | } else { | |
8485 | tcg_gen_shri_i64(tcg_src, tcg_src, shift); | |
8486 | } | |
8487 | } else { | |
8488 | if (shift == 64) { | |
8489 | /* effectively extending the sign-bit */ | |
8490 | tcg_gen_sari_i64(tcg_src, tcg_src, 63); | |
8491 | } else { | |
8492 | tcg_gen_sari_i64(tcg_src, tcg_src, shift); | |
8493 | } | |
8494 | } | |
8495 | } | |
8496 | ||
8497 | if (accumulate) { | |
8498 | tcg_gen_add_i64(tcg_res, tcg_res, tcg_src); | |
8499 | } else { | |
8500 | tcg_gen_mov_i64(tcg_res, tcg_src); | |
8501 | } | |
8502 | ||
8503 | if (extended_result) { | |
8504 | tcg_temp_free_i64(tcg_src_hi); | |
8505 | } | |
8506 | } | |
8507 | ||
4d1cef84 AB |
8508 | /* SSHR[RA]/USHR[RA] - Scalar shift right (optional rounding/accumulate) */ |
8509 | static void handle_scalar_simd_shri(DisasContext *s, | |
8510 | bool is_u, int immh, int immb, | |
8511 | int opcode, int rn, int rd) | |
8512 | { | |
8513 | const int size = 3; | |
8514 | int immhb = immh << 3 | immb; | |
8515 | int shift = 2 * (8 << size) - immhb; | |
8516 | bool accumulate = false; | |
8517 | bool round = false; | |
37a706ad | 8518 | bool insert = false; |
4d1cef84 AB |
8519 | TCGv_i64 tcg_rn; |
8520 | TCGv_i64 tcg_rd; | |
8521 | TCGv_i64 tcg_round; | |
8522 | ||
8523 | if (!extract32(immh, 3, 1)) { | |
8524 | unallocated_encoding(s); | |
8525 | return; | |
8526 | } | |
8527 | ||
8c6afa6a PM |
8528 | if (!fp_access_check(s)) { |
8529 | return; | |
8530 | } | |
8531 | ||
4d1cef84 AB |
8532 | switch (opcode) { |
8533 | case 0x02: /* SSRA / USRA (accumulate) */ | |
8534 | accumulate = true; | |
8535 | break; | |
8536 | case 0x04: /* SRSHR / URSHR (rounding) */ | |
8537 | round = true; | |
8538 | break; | |
8539 | case 0x06: /* SRSRA / URSRA (accum + rounding) */ | |
8540 | accumulate = round = true; | |
8541 | break; | |
37a706ad PM |
8542 | case 0x08: /* SRI */ |
8543 | insert = true; | |
8544 | break; | |
4d1cef84 AB |
8545 | } |
8546 | ||
8547 | if (round) { | |
8548 | uint64_t round_const = 1ULL << (shift - 1); | |
8549 | tcg_round = tcg_const_i64(round_const); | |
8550 | } else { | |
f764718d | 8551 | tcg_round = NULL; |
4d1cef84 AB |
8552 | } |
8553 | ||
8554 | tcg_rn = read_fp_dreg(s, rn); | |
37a706ad | 8555 | tcg_rd = (accumulate || insert) ? read_fp_dreg(s, rd) : tcg_temp_new_i64(); |
4d1cef84 | 8556 | |
37a706ad | 8557 | if (insert) { |
cdb45a60 RH |
8558 | /* shift count same as element size is valid but does nothing; |
8559 | * special case to avoid potential shift by 64. | |
8560 | */ | |
8561 | int esize = 8 << size; | |
8562 | if (shift != esize) { | |
8563 | tcg_gen_shri_i64(tcg_rn, tcg_rn, shift); | |
8564 | tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_rn, 0, esize - shift); | |
8565 | } | |
37a706ad PM |
8566 | } else { |
8567 | handle_shri_with_rndacc(tcg_rd, tcg_rn, tcg_round, | |
8568 | accumulate, is_u, size, shift); | |
8569 | } | |
4d1cef84 AB |
8570 | |
8571 | write_fp_dreg(s, rd, tcg_rd); | |
8572 | ||
8573 | tcg_temp_free_i64(tcg_rn); | |
8574 | tcg_temp_free_i64(tcg_rd); | |
8575 | if (round) { | |
8576 | tcg_temp_free_i64(tcg_round); | |
8577 | } | |
8578 | } | |
8579 | ||
8580 | /* SHL/SLI - Scalar shift left */ | |
8581 | static void handle_scalar_simd_shli(DisasContext *s, bool insert, | |
8582 | int immh, int immb, int opcode, | |
8583 | int rn, int rd) | |
8584 | { | |
8585 | int size = 32 - clz32(immh) - 1; | |
8586 | int immhb = immh << 3 | immb; | |
8587 | int shift = immhb - (8 << size); | |
8588 | TCGv_i64 tcg_rn = new_tmp_a64(s); | |
8589 | TCGv_i64 tcg_rd = new_tmp_a64(s); | |
8590 | ||
8591 | if (!extract32(immh, 3, 1)) { | |
8592 | unallocated_encoding(s); | |
8593 | return; | |
8594 | } | |
8595 | ||
8c6afa6a PM |
8596 | if (!fp_access_check(s)) { |
8597 | return; | |
8598 | } | |
8599 | ||
4d1cef84 AB |
8600 | tcg_rn = read_fp_dreg(s, rn); |
8601 | tcg_rd = insert ? read_fp_dreg(s, rd) : tcg_temp_new_i64(); | |
8602 | ||
cdb45a60 RH |
8603 | if (insert) { |
8604 | tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_rn, shift, 64 - shift); | |
8605 | } else { | |
8606 | tcg_gen_shli_i64(tcg_rd, tcg_rn, shift); | |
8607 | } | |
4d1cef84 AB |
8608 | |
8609 | write_fp_dreg(s, rd, tcg_rd); | |
8610 | ||
8611 | tcg_temp_free_i64(tcg_rn); | |
8612 | tcg_temp_free_i64(tcg_rd); | |
8613 | } | |
8614 | ||
c1b876b2 AB |
8615 | /* SQSHRN/SQSHRUN - Saturating (signed/unsigned) shift right with |
8616 | * (signed/unsigned) narrowing */ | |
8617 | static void handle_vec_simd_sqshrn(DisasContext *s, bool is_scalar, bool is_q, | |
8618 | bool is_u_shift, bool is_u_narrow, | |
8619 | int immh, int immb, int opcode, | |
8620 | int rn, int rd) | |
8621 | { | |
8622 | int immhb = immh << 3 | immb; | |
8623 | int size = 32 - clz32(immh) - 1; | |
8624 | int esize = 8 << size; | |
8625 | int shift = (2 * esize) - immhb; | |
8626 | int elements = is_scalar ? 1 : (64 / esize); | |
8627 | bool round = extract32(opcode, 0, 1); | |
14776ab5 | 8628 | MemOp ldop = (size + 1) | (is_u_shift ? 0 : MO_SIGN); |
c1b876b2 AB |
8629 | TCGv_i64 tcg_rn, tcg_rd, tcg_round; |
8630 | TCGv_i32 tcg_rd_narrowed; | |
8631 | TCGv_i64 tcg_final; | |
8632 | ||
8633 | static NeonGenNarrowEnvFn * const signed_narrow_fns[4][2] = { | |
8634 | { gen_helper_neon_narrow_sat_s8, | |
8635 | gen_helper_neon_unarrow_sat8 }, | |
8636 | { gen_helper_neon_narrow_sat_s16, | |
8637 | gen_helper_neon_unarrow_sat16 }, | |
8638 | { gen_helper_neon_narrow_sat_s32, | |
8639 | gen_helper_neon_unarrow_sat32 }, | |
8640 | { NULL, NULL }, | |
8641 | }; | |
8642 | static NeonGenNarrowEnvFn * const unsigned_narrow_fns[4] = { | |
8643 | gen_helper_neon_narrow_sat_u8, | |
8644 | gen_helper_neon_narrow_sat_u16, | |
8645 | gen_helper_neon_narrow_sat_u32, | |
8646 | NULL | |
8647 | }; | |
8648 | NeonGenNarrowEnvFn *narrowfn; | |
8649 | ||
8650 | int i; | |
8651 | ||
8652 | assert(size < 4); | |
8653 | ||
8654 | if (extract32(immh, 3, 1)) { | |
8655 | unallocated_encoding(s); | |
8656 | return; | |
8657 | } | |
8658 | ||
8c6afa6a PM |
8659 | if (!fp_access_check(s)) { |
8660 | return; | |
8661 | } | |
8662 | ||
c1b876b2 AB |
8663 | if (is_u_shift) { |
8664 | narrowfn = unsigned_narrow_fns[size]; | |
8665 | } else { | |
8666 | narrowfn = signed_narrow_fns[size][is_u_narrow ? 1 : 0]; | |
8667 | } | |
8668 | ||
8669 | tcg_rn = tcg_temp_new_i64(); | |
8670 | tcg_rd = tcg_temp_new_i64(); | |
8671 | tcg_rd_narrowed = tcg_temp_new_i32(); | |
8672 | tcg_final = tcg_const_i64(0); | |
8673 | ||
8674 | if (round) { | |
8675 | uint64_t round_const = 1ULL << (shift - 1); | |
8676 | tcg_round = tcg_const_i64(round_const); | |
8677 | } else { | |
f764718d | 8678 | tcg_round = NULL; |
c1b876b2 AB |
8679 | } |
8680 | ||
8681 | for (i = 0; i < elements; i++) { | |
8682 | read_vec_element(s, tcg_rn, rn, i, ldop); | |
8683 | handle_shri_with_rndacc(tcg_rd, tcg_rn, tcg_round, | |
8684 | false, is_u_shift, size+1, shift); | |
8685 | narrowfn(tcg_rd_narrowed, cpu_env, tcg_rd); | |
8686 | tcg_gen_extu_i32_i64(tcg_rd, tcg_rd_narrowed); | |
8687 | tcg_gen_deposit_i64(tcg_final, tcg_final, tcg_rd, esize * i, esize); | |
8688 | } | |
8689 | ||
8690 | if (!is_q) { | |
c1b876b2 AB |
8691 | write_vec_element(s, tcg_final, rd, 0, MO_64); |
8692 | } else { | |
8693 | write_vec_element(s, tcg_final, rd, 1, MO_64); | |
8694 | } | |
8695 | ||
8696 | if (round) { | |
8697 | tcg_temp_free_i64(tcg_round); | |
8698 | } | |
8699 | tcg_temp_free_i64(tcg_rn); | |
8700 | tcg_temp_free_i64(tcg_rd); | |
8701 | tcg_temp_free_i32(tcg_rd_narrowed); | |
8702 | tcg_temp_free_i64(tcg_final); | |
4ff55bcb RH |
8703 | |
8704 | clear_vec_high(s, is_q, rd); | |
c1b876b2 AB |
8705 | } |
8706 | ||
a847f32c PM |
8707 | /* SQSHLU, UQSHL, SQSHL: saturating left shifts */ |
8708 | static void handle_simd_qshl(DisasContext *s, bool scalar, bool is_q, | |
8709 | bool src_unsigned, bool dst_unsigned, | |
8710 | int immh, int immb, int rn, int rd) | |
8711 | { | |
8712 | int immhb = immh << 3 | immb; | |
8713 | int size = 32 - clz32(immh) - 1; | |
8714 | int shift = immhb - (8 << size); | |
8715 | int pass; | |
8716 | ||
8717 | assert(immh != 0); | |
8718 | assert(!(scalar && is_q)); | |
8719 | ||
8720 | if (!scalar) { | |
8721 | if (!is_q && extract32(immh, 3, 1)) { | |
8722 | unallocated_encoding(s); | |
8723 | return; | |
8724 | } | |
8725 | ||
8726 | /* Since we use the variable-shift helpers we must | |
8727 | * replicate the shift count into each element of | |
8728 | * the tcg_shift value. | |
8729 | */ | |
8730 | switch (size) { | |
8731 | case 0: | |
8732 | shift |= shift << 8; | |
8733 | /* fall through */ | |
8734 | case 1: | |
8735 | shift |= shift << 16; | |
8736 | break; | |
8737 | case 2: | |
8738 | case 3: | |
8739 | break; | |
8740 | default: | |
8741 | g_assert_not_reached(); | |
8742 | } | |
8743 | } | |
8744 | ||
8c6afa6a PM |
8745 | if (!fp_access_check(s)) { |
8746 | return; | |
8747 | } | |
8748 | ||
a847f32c PM |
8749 | if (size == 3) { |
8750 | TCGv_i64 tcg_shift = tcg_const_i64(shift); | |
8751 | static NeonGenTwo64OpEnvFn * const fns[2][2] = { | |
8752 | { gen_helper_neon_qshl_s64, gen_helper_neon_qshlu_s64 }, | |
8753 | { NULL, gen_helper_neon_qshl_u64 }, | |
8754 | }; | |
8755 | NeonGenTwo64OpEnvFn *genfn = fns[src_unsigned][dst_unsigned]; | |
8756 | int maxpass = is_q ? 2 : 1; | |
8757 | ||
8758 | for (pass = 0; pass < maxpass; pass++) { | |
8759 | TCGv_i64 tcg_op = tcg_temp_new_i64(); | |
8760 | ||
8761 | read_vec_element(s, tcg_op, rn, pass, MO_64); | |
8762 | genfn(tcg_op, cpu_env, tcg_op, tcg_shift); | |
8763 | write_vec_element(s, tcg_op, rd, pass, MO_64); | |
8764 | ||
8765 | tcg_temp_free_i64(tcg_op); | |
8766 | } | |
8767 | tcg_temp_free_i64(tcg_shift); | |
4ff55bcb | 8768 | clear_vec_high(s, is_q, rd); |
a847f32c PM |
8769 | } else { |
8770 | TCGv_i32 tcg_shift = tcg_const_i32(shift); | |
8771 | static NeonGenTwoOpEnvFn * const fns[2][2][3] = { | |
8772 | { | |
8773 | { gen_helper_neon_qshl_s8, | |
8774 | gen_helper_neon_qshl_s16, | |
8775 | gen_helper_neon_qshl_s32 }, | |
8776 | { gen_helper_neon_qshlu_s8, | |
8777 | gen_helper_neon_qshlu_s16, | |
8778 | gen_helper_neon_qshlu_s32 } | |
8779 | }, { | |
8780 | { NULL, NULL, NULL }, | |
8781 | { gen_helper_neon_qshl_u8, | |
8782 | gen_helper_neon_qshl_u16, | |
8783 | gen_helper_neon_qshl_u32 } | |
8784 | } | |
8785 | }; | |
8786 | NeonGenTwoOpEnvFn *genfn = fns[src_unsigned][dst_unsigned][size]; | |
14776ab5 | 8787 | MemOp memop = scalar ? size : MO_32; |
a847f32c PM |
8788 | int maxpass = scalar ? 1 : is_q ? 4 : 2; |
8789 | ||
8790 | for (pass = 0; pass < maxpass; pass++) { | |
8791 | TCGv_i32 tcg_op = tcg_temp_new_i32(); | |
8792 | ||
8793 | read_vec_element_i32(s, tcg_op, rn, pass, memop); | |
8794 | genfn(tcg_op, cpu_env, tcg_op, tcg_shift); | |
8795 | if (scalar) { | |
8796 | switch (size) { | |
8797 | case 0: | |
8798 | tcg_gen_ext8u_i32(tcg_op, tcg_op); | |
8799 | break; | |
8800 | case 1: | |
8801 | tcg_gen_ext16u_i32(tcg_op, tcg_op); | |
8802 | break; | |
8803 | case 2: | |
8804 | break; | |
8805 | default: | |
8806 | g_assert_not_reached(); | |
8807 | } | |
8808 | write_fp_sreg(s, rd, tcg_op); | |
8809 | } else { | |
8810 | write_vec_element_i32(s, tcg_op, rd, pass, MO_32); | |
8811 | } | |
8812 | ||
8813 | tcg_temp_free_i32(tcg_op); | |
8814 | } | |
8815 | tcg_temp_free_i32(tcg_shift); | |
8816 | ||
4ff55bcb RH |
8817 | if (!scalar) { |
8818 | clear_vec_high(s, is_q, rd); | |
a847f32c PM |
8819 | } |
8820 | } | |
8821 | } | |
8822 | ||
10113b69 AB |
8823 | /* Common vector code for handling integer to FP conversion */ |
8824 | static void handle_simd_intfp_conv(DisasContext *s, int rd, int rn, | |
8825 | int elements, int is_signed, | |
8826 | int fracbits, int size) | |
8827 | { | |
93193190 AB |
8828 | TCGv_ptr tcg_fpst = get_fpstatus_ptr(size == MO_16); |
8829 | TCGv_i32 tcg_shift = NULL; | |
8830 | ||
14776ab5 | 8831 | MemOp mop = size | (is_signed ? MO_SIGN : 0); |
10113b69 AB |
8832 | int pass; |
8833 | ||
93193190 AB |
8834 | if (fracbits || size == MO_64) { |
8835 | tcg_shift = tcg_const_i32(fracbits); | |
8836 | } | |
8837 | ||
8838 | if (size == MO_64) { | |
8839 | TCGv_i64 tcg_int64 = tcg_temp_new_i64(); | |
8840 | TCGv_i64 tcg_double = tcg_temp_new_i64(); | |
8841 | ||
8842 | for (pass = 0; pass < elements; pass++) { | |
8843 | read_vec_element(s, tcg_int64, rn, pass, mop); | |
10113b69 | 8844 | |
10113b69 | 8845 | if (is_signed) { |
93193190 | 8846 | gen_helper_vfp_sqtod(tcg_double, tcg_int64, |
10113b69 AB |
8847 | tcg_shift, tcg_fpst); |
8848 | } else { | |
93193190 | 8849 | gen_helper_vfp_uqtod(tcg_double, tcg_int64, |
10113b69 AB |
8850 | tcg_shift, tcg_fpst); |
8851 | } | |
8852 | if (elements == 1) { | |
8853 | write_fp_dreg(s, rd, tcg_double); | |
8854 | } else { | |
8855 | write_vec_element(s, tcg_double, rd, pass, MO_64); | |
8856 | } | |
93193190 AB |
8857 | } |
8858 | ||
8859 | tcg_temp_free_i64(tcg_int64); | |
8860 | tcg_temp_free_i64(tcg_double); | |
8861 | ||
8862 | } else { | |
8863 | TCGv_i32 tcg_int32 = tcg_temp_new_i32(); | |
8864 | TCGv_i32 tcg_float = tcg_temp_new_i32(); | |
8865 | ||
8866 | for (pass = 0; pass < elements; pass++) { | |
8867 | read_vec_element_i32(s, tcg_int32, rn, pass, mop); | |
8868 | ||
8869 | switch (size) { | |
8870 | case MO_32: | |
8871 | if (fracbits) { | |
8872 | if (is_signed) { | |
8873 | gen_helper_vfp_sltos(tcg_float, tcg_int32, | |
8874 | tcg_shift, tcg_fpst); | |
8875 | } else { | |
8876 | gen_helper_vfp_ultos(tcg_float, tcg_int32, | |
8877 | tcg_shift, tcg_fpst); | |
8878 | } | |
8879 | } else { | |
8880 | if (is_signed) { | |
8881 | gen_helper_vfp_sitos(tcg_float, tcg_int32, tcg_fpst); | |
8882 | } else { | |
8883 | gen_helper_vfp_uitos(tcg_float, tcg_int32, tcg_fpst); | |
8884 | } | |
8885 | } | |
8886 | break; | |
8887 | case MO_16: | |
8888 | if (fracbits) { | |
8889 | if (is_signed) { | |
8890 | gen_helper_vfp_sltoh(tcg_float, tcg_int32, | |
8891 | tcg_shift, tcg_fpst); | |
8892 | } else { | |
8893 | gen_helper_vfp_ultoh(tcg_float, tcg_int32, | |
8894 | tcg_shift, tcg_fpst); | |
8895 | } | |
8896 | } else { | |
8897 | if (is_signed) { | |
8898 | gen_helper_vfp_sitoh(tcg_float, tcg_int32, tcg_fpst); | |
8899 | } else { | |
8900 | gen_helper_vfp_uitoh(tcg_float, tcg_int32, tcg_fpst); | |
8901 | } | |
8902 | } | |
8903 | break; | |
8904 | default: | |
8905 | g_assert_not_reached(); | |
10113b69 | 8906 | } |
93193190 | 8907 | |
10113b69 | 8908 | if (elements == 1) { |
93193190 | 8909 | write_fp_sreg(s, rd, tcg_float); |
10113b69 | 8910 | } else { |
93193190 | 8911 | write_vec_element_i32(s, tcg_float, rd, pass, size); |
10113b69 | 8912 | } |
10113b69 | 8913 | } |
93193190 AB |
8914 | |
8915 | tcg_temp_free_i32(tcg_int32); | |
8916 | tcg_temp_free_i32(tcg_float); | |
10113b69 AB |
8917 | } |
8918 | ||
10113b69 | 8919 | tcg_temp_free_ptr(tcg_fpst); |
93193190 AB |
8920 | if (tcg_shift) { |
8921 | tcg_temp_free_i32(tcg_shift); | |
8922 | } | |
4ff55bcb RH |
8923 | |
8924 | clear_vec_high(s, elements << size == 16, rd); | |
10113b69 AB |
8925 | } |
8926 | ||
8927 | /* UCVTF/SCVTF - Integer to FP conversion */ | |
8928 | static void handle_simd_shift_intfp_conv(DisasContext *s, bool is_scalar, | |
8929 | bool is_q, bool is_u, | |
8930 | int immh, int immb, int opcode, | |
8931 | int rn, int rd) | |
8932 | { | |
a6117fae | 8933 | int size, elements, fracbits; |
10113b69 | 8934 | int immhb = immh << 3 | immb; |
10113b69 | 8935 | |
a6117fae RH |
8936 | if (immh & 8) { |
8937 | size = MO_64; | |
8938 | if (!is_scalar && !is_q) { | |
8939 | unallocated_encoding(s); | |
8940 | return; | |
8941 | } | |
8942 | } else if (immh & 4) { | |
8943 | size = MO_32; | |
8944 | } else if (immh & 2) { | |
8945 | size = MO_16; | |
5763190f | 8946 | if (!dc_isar_feature(aa64_fp16, s)) { |
a6117fae RH |
8947 | unallocated_encoding(s); |
8948 | return; | |
8949 | } | |
8950 | } else { | |
8951 | /* immh == 0 would be a failure of the decode logic */ | |
8952 | g_assert(immh == 1); | |
10113b69 AB |
8953 | unallocated_encoding(s); |
8954 | return; | |
8955 | } | |
8956 | ||
8957 | if (is_scalar) { | |
8958 | elements = 1; | |
8959 | } else { | |
a6117fae | 8960 | elements = (8 << is_q) >> size; |
10113b69 | 8961 | } |
a6117fae | 8962 | fracbits = (16 << size) - immhb; |
8c6afa6a PM |
8963 | |
8964 | if (!fp_access_check(s)) { | |
8965 | return; | |
8966 | } | |
8967 | ||
10113b69 AB |
8968 | handle_simd_intfp_conv(s, rd, rn, elements, !is_u, fracbits, size); |
8969 | } | |
8970 | ||
2ed3ea11 PM |
8971 | /* FCVTZS, FVCVTZU - FP to fixedpoint conversion */ |
8972 | static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar, | |
8973 | bool is_q, bool is_u, | |
8974 | int immh, int immb, int rn, int rd) | |
8975 | { | |
2ed3ea11 | 8976 | int immhb = immh << 3 | immb; |
d0ba8e74 | 8977 | int pass, size, fracbits; |
2ed3ea11 PM |
8978 | TCGv_ptr tcg_fpstatus; |
8979 | TCGv_i32 tcg_rmode, tcg_shift; | |
8980 | ||
d0ba8e74 RH |
8981 | if (immh & 0x8) { |
8982 | size = MO_64; | |
8983 | if (!is_scalar && !is_q) { | |
8984 | unallocated_encoding(s); | |
8985 | return; | |
8986 | } | |
8987 | } else if (immh & 0x4) { | |
8988 | size = MO_32; | |
8989 | } else if (immh & 0x2) { | |
8990 | size = MO_16; | |
5763190f | 8991 | if (!dc_isar_feature(aa64_fp16, s)) { |
d0ba8e74 RH |
8992 | unallocated_encoding(s); |
8993 | return; | |
8994 | } | |
8995 | } else { | |
8996 | /* Should have split out AdvSIMD modified immediate earlier. */ | |
8997 | assert(immh == 1); | |
2ed3ea11 PM |
8998 | unallocated_encoding(s); |
8999 | return; | |
9000 | } | |
9001 | ||
8c6afa6a PM |
9002 | if (!fp_access_check(s)) { |
9003 | return; | |
9004 | } | |
9005 | ||
2ed3ea11 PM |
9006 | assert(!(is_scalar && is_q)); |
9007 | ||
9008 | tcg_rmode = tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO)); | |
d0ba8e74 | 9009 | tcg_fpstatus = get_fpstatus_ptr(size == MO_16); |
9b049916 | 9010 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); |
d0ba8e74 | 9011 | fracbits = (16 << size) - immhb; |
2ed3ea11 PM |
9012 | tcg_shift = tcg_const_i32(fracbits); |
9013 | ||
d0ba8e74 | 9014 | if (size == MO_64) { |
4063452e | 9015 | int maxpass = is_scalar ? 1 : 2; |
2ed3ea11 PM |
9016 | |
9017 | for (pass = 0; pass < maxpass; pass++) { | |
9018 | TCGv_i64 tcg_op = tcg_temp_new_i64(); | |
9019 | ||
9020 | read_vec_element(s, tcg_op, rn, pass, MO_64); | |
9021 | if (is_u) { | |
9022 | gen_helper_vfp_touqd(tcg_op, tcg_op, tcg_shift, tcg_fpstatus); | |
9023 | } else { | |
9024 | gen_helper_vfp_tosqd(tcg_op, tcg_op, tcg_shift, tcg_fpstatus); | |
9025 | } | |
9026 | write_vec_element(s, tcg_op, rd, pass, MO_64); | |
9027 | tcg_temp_free_i64(tcg_op); | |
9028 | } | |
4ff55bcb | 9029 | clear_vec_high(s, is_q, rd); |
2ed3ea11 | 9030 | } else { |
d0ba8e74 RH |
9031 | void (*fn)(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_ptr); |
9032 | int maxpass = is_scalar ? 1 : ((8 << is_q) >> size); | |
2ed3ea11 | 9033 | |
d0ba8e74 RH |
9034 | switch (size) { |
9035 | case MO_16: | |
2ed3ea11 | 9036 | if (is_u) { |
88808a02 | 9037 | fn = gen_helper_vfp_touhh; |
2ed3ea11 | 9038 | } else { |
88808a02 | 9039 | fn = gen_helper_vfp_toshh; |
2ed3ea11 | 9040 | } |
d0ba8e74 RH |
9041 | break; |
9042 | case MO_32: | |
2ed3ea11 | 9043 | if (is_u) { |
d0ba8e74 | 9044 | fn = gen_helper_vfp_touls; |
2ed3ea11 | 9045 | } else { |
d0ba8e74 | 9046 | fn = gen_helper_vfp_tosls; |
2ed3ea11 | 9047 | } |
d0ba8e74 RH |
9048 | break; |
9049 | default: | |
9050 | g_assert_not_reached(); | |
9051 | } | |
9052 | ||
9053 | for (pass = 0; pass < maxpass; pass++) { | |
9054 | TCGv_i32 tcg_op = tcg_temp_new_i32(); | |
9055 | ||
9056 | read_vec_element_i32(s, tcg_op, rn, pass, size); | |
9057 | fn(tcg_op, tcg_op, tcg_shift, tcg_fpstatus); | |
2ed3ea11 PM |
9058 | if (is_scalar) { |
9059 | write_fp_sreg(s, rd, tcg_op); | |
9060 | } else { | |
d0ba8e74 | 9061 | write_vec_element_i32(s, tcg_op, rd, pass, size); |
2ed3ea11 PM |
9062 | } |
9063 | tcg_temp_free_i32(tcg_op); | |
9064 | } | |
4ff55bcb RH |
9065 | if (!is_scalar) { |
9066 | clear_vec_high(s, is_q, rd); | |
2ed3ea11 PM |
9067 | } |
9068 | } | |
9069 | ||
9070 | tcg_temp_free_ptr(tcg_fpstatus); | |
9071 | tcg_temp_free_i32(tcg_shift); | |
9b049916 | 9072 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); |
2ed3ea11 PM |
9073 | tcg_temp_free_i32(tcg_rmode); |
9074 | } | |
9075 | ||
4ce31af4 | 9076 | /* AdvSIMD scalar shift by immediate |
384b26fb AB |
9077 | * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0 |
9078 | * +-----+---+-------------+------+------+--------+---+------+------+ | |
9079 | * | 0 1 | U | 1 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd | | |
9080 | * +-----+---+-------------+------+------+--------+---+------+------+ | |
4d1cef84 AB |
9081 | * |
9082 | * This is the scalar version so it works on a fixed sized registers | |
384b26fb AB |
9083 | */ |
9084 | static void disas_simd_scalar_shift_imm(DisasContext *s, uint32_t insn) | |
9085 | { | |
4d1cef84 AB |
9086 | int rd = extract32(insn, 0, 5); |
9087 | int rn = extract32(insn, 5, 5); | |
9088 | int opcode = extract32(insn, 11, 5); | |
9089 | int immb = extract32(insn, 16, 3); | |
9090 | int immh = extract32(insn, 19, 4); | |
9091 | bool is_u = extract32(insn, 29, 1); | |
9092 | ||
c1b876b2 AB |
9093 | if (immh == 0) { |
9094 | unallocated_encoding(s); | |
9095 | return; | |
9096 | } | |
9097 | ||
4d1cef84 | 9098 | switch (opcode) { |
37a706ad PM |
9099 | case 0x08: /* SRI */ |
9100 | if (!is_u) { | |
9101 | unallocated_encoding(s); | |
9102 | return; | |
9103 | } | |
9104 | /* fall through */ | |
4d1cef84 AB |
9105 | case 0x00: /* SSHR / USHR */ |
9106 | case 0x02: /* SSRA / USRA */ | |
9107 | case 0x04: /* SRSHR / URSHR */ | |
9108 | case 0x06: /* SRSRA / URSRA */ | |
9109 | handle_scalar_simd_shri(s, is_u, immh, immb, opcode, rn, rd); | |
9110 | break; | |
9111 | case 0x0a: /* SHL / SLI */ | |
9112 | handle_scalar_simd_shli(s, is_u, immh, immb, opcode, rn, rd); | |
9113 | break; | |
10113b69 AB |
9114 | case 0x1c: /* SCVTF, UCVTF */ |
9115 | handle_simd_shift_intfp_conv(s, true, false, is_u, immh, immb, | |
9116 | opcode, rn, rd); | |
9117 | break; | |
c1b876b2 AB |
9118 | case 0x10: /* SQSHRUN, SQSHRUN2 */ |
9119 | case 0x11: /* SQRSHRUN, SQRSHRUN2 */ | |
9120 | if (!is_u) { | |
9121 | unallocated_encoding(s); | |
9122 | return; | |
9123 | } | |
9124 | handle_vec_simd_sqshrn(s, true, false, false, true, | |
9125 | immh, immb, opcode, rn, rd); | |
9126 | break; | |
9127 | case 0x12: /* SQSHRN, SQSHRN2, UQSHRN */ | |
9128 | case 0x13: /* SQRSHRN, SQRSHRN2, UQRSHRN, UQRSHRN2 */ | |
9129 | handle_vec_simd_sqshrn(s, true, false, is_u, is_u, | |
9130 | immh, immb, opcode, rn, rd); | |
9131 | break; | |
a566da1b | 9132 | case 0xc: /* SQSHLU */ |
a847f32c PM |
9133 | if (!is_u) { |
9134 | unallocated_encoding(s); | |
9135 | return; | |
9136 | } | |
9137 | handle_simd_qshl(s, true, false, false, true, immh, immb, rn, rd); | |
9138 | break; | |
a566da1b | 9139 | case 0xe: /* SQSHL, UQSHL */ |
a847f32c PM |
9140 | handle_simd_qshl(s, true, false, is_u, is_u, immh, immb, rn, rd); |
9141 | break; | |
a566da1b | 9142 | case 0x1f: /* FCVTZS, FCVTZU */ |
2ed3ea11 | 9143 | handle_simd_shift_fpint_conv(s, true, false, is_u, immh, immb, rn, rd); |
4d1cef84 | 9144 | break; |
a566da1b PM |
9145 | default: |
9146 | unallocated_encoding(s); | |
9147 | break; | |
4d1cef84 | 9148 | } |
384b26fb AB |
9149 | } |
9150 | ||
4ce31af4 | 9151 | /* AdvSIMD scalar three different |
384b26fb AB |
9152 | * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0 |
9153 | * +-----+---+-----------+------+---+------+--------+-----+------+------+ | |
9154 | * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd | | |
9155 | * +-----+---+-----------+------+---+------+--------+-----+------+------+ | |
9156 | */ | |
9157 | static void disas_simd_scalar_three_reg_diff(DisasContext *s, uint32_t insn) | |
9158 | { | |
b033cd3d PM |
9159 | bool is_u = extract32(insn, 29, 1); |
9160 | int size = extract32(insn, 22, 2); | |
9161 | int opcode = extract32(insn, 12, 4); | |
9162 | int rm = extract32(insn, 16, 5); | |
9163 | int rn = extract32(insn, 5, 5); | |
9164 | int rd = extract32(insn, 0, 5); | |
9165 | ||
9166 | if (is_u) { | |
9167 | unallocated_encoding(s); | |
9168 | return; | |
9169 | } | |
9170 | ||
9171 | switch (opcode) { | |
9172 | case 0x9: /* SQDMLAL, SQDMLAL2 */ | |
9173 | case 0xb: /* SQDMLSL, SQDMLSL2 */ | |
9174 | case 0xd: /* SQDMULL, SQDMULL2 */ | |
9175 | if (size == 0 || size == 3) { | |
9176 | unallocated_encoding(s); | |
9177 | return; | |
9178 | } | |
9179 | break; | |
9180 | default: | |
9181 | unallocated_encoding(s); | |
9182 | return; | |
9183 | } | |
9184 | ||
8c6afa6a PM |
9185 | if (!fp_access_check(s)) { |
9186 | return; | |
9187 | } | |
9188 | ||
b033cd3d PM |
9189 | if (size == 2) { |
9190 | TCGv_i64 tcg_op1 = tcg_temp_new_i64(); | |
9191 | TCGv_i64 tcg_op2 = tcg_temp_new_i64(); | |
9192 | TCGv_i64 tcg_res = tcg_temp_new_i64(); | |
9193 | ||
9194 | read_vec_element(s, tcg_op1, rn, 0, MO_32 | MO_SIGN); | |
9195 | read_vec_element(s, tcg_op2, rm, 0, MO_32 | MO_SIGN); | |
9196 | ||
9197 | tcg_gen_mul_i64(tcg_res, tcg_op1, tcg_op2); | |
9198 | gen_helper_neon_addl_saturate_s64(tcg_res, cpu_env, tcg_res, tcg_res); | |
9199 | ||
9200 | switch (opcode) { | |
9201 | case 0xd: /* SQDMULL, SQDMULL2 */ | |
9202 | break; | |
9203 | case 0xb: /* SQDMLSL, SQDMLSL2 */ | |
9204 | tcg_gen_neg_i64(tcg_res, tcg_res); | |
9205 | /* fall through */ | |
9206 | case 0x9: /* SQDMLAL, SQDMLAL2 */ | |
9207 | read_vec_element(s, tcg_op1, rd, 0, MO_64); | |
9208 | gen_helper_neon_addl_saturate_s64(tcg_res, cpu_env, | |
9209 | tcg_res, tcg_op1); | |
9210 | break; | |
9211 | default: | |
9212 | g_assert_not_reached(); | |
9213 | } | |
9214 | ||
9215 | write_fp_dreg(s, rd, tcg_res); | |
9216 | ||
9217 | tcg_temp_free_i64(tcg_op1); | |
9218 | tcg_temp_free_i64(tcg_op2); | |
9219 | tcg_temp_free_i64(tcg_res); | |
9220 | } else { | |
3d99d931 RH |
9221 | TCGv_i32 tcg_op1 = read_fp_hreg(s, rn); |
9222 | TCGv_i32 tcg_op2 = read_fp_hreg(s, rm); | |
b033cd3d PM |
9223 | TCGv_i64 tcg_res = tcg_temp_new_i64(); |
9224 | ||
b033cd3d PM |
9225 | gen_helper_neon_mull_s16(tcg_res, tcg_op1, tcg_op2); |
9226 | gen_helper_neon_addl_saturate_s32(tcg_res, cpu_env, tcg_res, tcg_res); | |
9227 | ||
9228 | switch (opcode) { | |
9229 | case 0xd: /* SQDMULL, SQDMULL2 */ | |
9230 | break; | |
9231 | case 0xb: /* SQDMLSL, SQDMLSL2 */ | |
9232 | gen_helper_neon_negl_u32(tcg_res, tcg_res); | |
9233 | /* fall through */ | |
9234 | case 0x9: /* SQDMLAL, SQDMLAL2 */ | |
9235 | { | |
9236 | TCGv_i64 tcg_op3 = tcg_temp_new_i64(); | |
9237 | read_vec_element(s, tcg_op3, rd, 0, MO_32); | |
9238 | gen_helper_neon_addl_saturate_s32(tcg_res, cpu_env, | |
9239 | tcg_res, tcg_op3); | |
9240 | tcg_temp_free_i64(tcg_op3); | |
9241 | break; | |
9242 | } | |
9243 | default: | |
9244 | g_assert_not_reached(); | |
9245 | } | |
9246 | ||
9247 | tcg_gen_ext32u_i64(tcg_res, tcg_res); | |
9248 | write_fp_dreg(s, rd, tcg_res); | |
9249 | ||
9250 | tcg_temp_free_i32(tcg_op1); | |
9251 | tcg_temp_free_i32(tcg_op2); | |
9252 | tcg_temp_free_i64(tcg_res); | |
9253 | } | |
384b26fb AB |
9254 | } |
9255 | ||
b305dba6 PM |
9256 | static void handle_3same_64(DisasContext *s, int opcode, bool u, |
9257 | TCGv_i64 tcg_rd, TCGv_i64 tcg_rn, TCGv_i64 tcg_rm) | |
9258 | { | |
9259 | /* Handle 64x64->64 opcodes which are shared between the scalar | |
9260 | * and vector 3-same groups. We cover every opcode where size == 3 | |
9261 | * is valid in either the three-reg-same (integer, not pairwise) | |
3840d219 | 9262 | * or scalar-three-reg-same groups. |
b305dba6 PM |
9263 | */ |
9264 | TCGCond cond; | |
9265 | ||
9266 | switch (opcode) { | |
6d9571f7 PM |
9267 | case 0x1: /* SQADD */ |
9268 | if (u) { | |
9269 | gen_helper_neon_qadd_u64(tcg_rd, cpu_env, tcg_rn, tcg_rm); | |
9270 | } else { | |
9271 | gen_helper_neon_qadd_s64(tcg_rd, cpu_env, tcg_rn, tcg_rm); | |
9272 | } | |
9273 | break; | |
9274 | case 0x5: /* SQSUB */ | |
9275 | if (u) { | |
9276 | gen_helper_neon_qsub_u64(tcg_rd, cpu_env, tcg_rn, tcg_rm); | |
9277 | } else { | |
9278 | gen_helper_neon_qsub_s64(tcg_rd, cpu_env, tcg_rn, tcg_rm); | |
9279 | } | |
9280 | break; | |
b305dba6 PM |
9281 | case 0x6: /* CMGT, CMHI */ |
9282 | /* 64 bit integer comparison, result = test ? (2^64 - 1) : 0. | |
9283 | * We implement this using setcond (test) and then negating. | |
9284 | */ | |
9285 | cond = u ? TCG_COND_GTU : TCG_COND_GT; | |
9286 | do_cmop: | |
9287 | tcg_gen_setcond_i64(cond, tcg_rd, tcg_rn, tcg_rm); | |
9288 | tcg_gen_neg_i64(tcg_rd, tcg_rd); | |
9289 | break; | |
9290 | case 0x7: /* CMGE, CMHS */ | |
9291 | cond = u ? TCG_COND_GEU : TCG_COND_GE; | |
9292 | goto do_cmop; | |
9293 | case 0x11: /* CMTST, CMEQ */ | |
9294 | if (u) { | |
9295 | cond = TCG_COND_EQ; | |
9296 | goto do_cmop; | |
9297 | } | |
79d61de6 | 9298 | gen_cmtst_i64(tcg_rd, tcg_rn, tcg_rm); |
b305dba6 | 9299 | break; |
6d9571f7 | 9300 | case 0x8: /* SSHL, USHL */ |
b305dba6 | 9301 | if (u) { |
87b74e8b | 9302 | gen_ushl_i64(tcg_rd, tcg_rn, tcg_rm); |
b305dba6 | 9303 | } else { |
87b74e8b | 9304 | gen_sshl_i64(tcg_rd, tcg_rn, tcg_rm); |
b305dba6 PM |
9305 | } |
9306 | break; | |
b305dba6 | 9307 | case 0x9: /* SQSHL, UQSHL */ |
6d9571f7 PM |
9308 | if (u) { |
9309 | gen_helper_neon_qshl_u64(tcg_rd, cpu_env, tcg_rn, tcg_rm); | |
9310 | } else { | |
9311 | gen_helper_neon_qshl_s64(tcg_rd, cpu_env, tcg_rn, tcg_rm); | |
9312 | } | |
9313 | break; | |
b305dba6 | 9314 | case 0xa: /* SRSHL, URSHL */ |
6d9571f7 PM |
9315 | if (u) { |
9316 | gen_helper_neon_rshl_u64(tcg_rd, tcg_rn, tcg_rm); | |
9317 | } else { | |
9318 | gen_helper_neon_rshl_s64(tcg_rd, tcg_rn, tcg_rm); | |
9319 | } | |
9320 | break; | |
b305dba6 | 9321 | case 0xb: /* SQRSHL, UQRSHL */ |
6d9571f7 PM |
9322 | if (u) { |
9323 | gen_helper_neon_qrshl_u64(tcg_rd, cpu_env, tcg_rn, tcg_rm); | |
9324 | } else { | |
9325 | gen_helper_neon_qrshl_s64(tcg_rd, cpu_env, tcg_rn, tcg_rm); | |
9326 | } | |
9327 | break; | |
9328 | case 0x10: /* ADD, SUB */ | |
9329 | if (u) { | |
9330 | tcg_gen_sub_i64(tcg_rd, tcg_rn, tcg_rm); | |
9331 | } else { | |
9332 | tcg_gen_add_i64(tcg_rd, tcg_rn, tcg_rm); | |
9333 | } | |
9334 | break; | |
b305dba6 PM |
9335 | default: |
9336 | g_assert_not_reached(); | |
9337 | } | |
9338 | } | |
9339 | ||
845ea09a PM |
9340 | /* Handle the 3-same-operands float operations; shared by the scalar |
9341 | * and vector encodings. The caller must filter out any encodings | |
9342 | * not allocated for the encoding it is dealing with. | |
9343 | */ | |
9344 | static void handle_3same_float(DisasContext *s, int size, int elements, | |
9345 | int fpopcode, int rd, int rn, int rm) | |
9346 | { | |
9347 | int pass; | |
d81ce0ef | 9348 | TCGv_ptr fpst = get_fpstatus_ptr(false); |
845ea09a PM |
9349 | |
9350 | for (pass = 0; pass < elements; pass++) { | |
9351 | if (size) { | |
9352 | /* Double */ | |
9353 | TCGv_i64 tcg_op1 = tcg_temp_new_i64(); | |
9354 | TCGv_i64 tcg_op2 = tcg_temp_new_i64(); | |
9355 | TCGv_i64 tcg_res = tcg_temp_new_i64(); | |
9356 | ||
9357 | read_vec_element(s, tcg_op1, rn, pass, MO_64); | |
9358 | read_vec_element(s, tcg_op2, rm, pass, MO_64); | |
9359 | ||
9360 | switch (fpopcode) { | |
057d5f62 PM |
9361 | case 0x39: /* FMLS */ |
9362 | /* As usual for ARM, separate negation for fused multiply-add */ | |
9363 | gen_helper_vfp_negd(tcg_op1, tcg_op1); | |
9364 | /* fall through */ | |
9365 | case 0x19: /* FMLA */ | |
9366 | read_vec_element(s, tcg_res, rd, pass, MO_64); | |
9367 | gen_helper_vfp_muladdd(tcg_res, tcg_op1, tcg_op2, | |
9368 | tcg_res, fpst); | |
9369 | break; | |
845ea09a PM |
9370 | case 0x18: /* FMAXNM */ |
9371 | gen_helper_vfp_maxnumd(tcg_res, tcg_op1, tcg_op2, fpst); | |
9372 | break; | |
9373 | case 0x1a: /* FADD */ | |
9374 | gen_helper_vfp_addd(tcg_res, tcg_op1, tcg_op2, fpst); | |
9375 | break; | |
057d5f62 PM |
9376 | case 0x1b: /* FMULX */ |
9377 | gen_helper_vfp_mulxd(tcg_res, tcg_op1, tcg_op2, fpst); | |
9378 | break; | |
8908f4d1 AB |
9379 | case 0x1c: /* FCMEQ */ |
9380 | gen_helper_neon_ceq_f64(tcg_res, tcg_op1, tcg_op2, fpst); | |
9381 | break; | |
845ea09a PM |
9382 | case 0x1e: /* FMAX */ |
9383 | gen_helper_vfp_maxd(tcg_res, tcg_op1, tcg_op2, fpst); | |
9384 | break; | |
057d5f62 PM |
9385 | case 0x1f: /* FRECPS */ |
9386 | gen_helper_recpsf_f64(tcg_res, tcg_op1, tcg_op2, fpst); | |
9387 | break; | |
845ea09a PM |
9388 | case 0x38: /* FMINNM */ |
9389 | gen_helper_vfp_minnumd(tcg_res, tcg_op1, tcg_op2, fpst); | |
9390 | break; | |
9391 | case 0x3a: /* FSUB */ | |
9392 | gen_helper_vfp_subd(tcg_res, tcg_op1, tcg_op2, fpst); | |
9393 | break; | |
9394 | case 0x3e: /* FMIN */ | |
9395 | gen_helper_vfp_mind(tcg_res, tcg_op1, tcg_op2, fpst); | |
9396 | break; | |
057d5f62 PM |
9397 | case 0x3f: /* FRSQRTS */ |
9398 | gen_helper_rsqrtsf_f64(tcg_res, tcg_op1, tcg_op2, fpst); | |
9399 | break; | |
845ea09a PM |
9400 | case 0x5b: /* FMUL */ |
9401 | gen_helper_vfp_muld(tcg_res, tcg_op1, tcg_op2, fpst); | |
9402 | break; | |
8908f4d1 AB |
9403 | case 0x5c: /* FCMGE */ |
9404 | gen_helper_neon_cge_f64(tcg_res, tcg_op1, tcg_op2, fpst); | |
9405 | break; | |
057d5f62 PM |
9406 | case 0x5d: /* FACGE */ |
9407 | gen_helper_neon_acge_f64(tcg_res, tcg_op1, tcg_op2, fpst); | |
9408 | break; | |
845ea09a PM |
9409 | case 0x5f: /* FDIV */ |
9410 | gen_helper_vfp_divd(tcg_res, tcg_op1, tcg_op2, fpst); | |
9411 | break; | |
9412 | case 0x7a: /* FABD */ | |
9413 | gen_helper_vfp_subd(tcg_res, tcg_op1, tcg_op2, fpst); | |
9414 | gen_helper_vfp_absd(tcg_res, tcg_res); | |
9415 | break; | |
8908f4d1 AB |
9416 | case 0x7c: /* FCMGT */ |
9417 | gen_helper_neon_cgt_f64(tcg_res, tcg_op1, tcg_op2, fpst); | |
9418 | break; | |
057d5f62 PM |
9419 | case 0x7d: /* FACGT */ |
9420 | gen_helper_neon_acgt_f64(tcg_res, tcg_op1, tcg_op2, fpst); | |
9421 | break; | |
845ea09a PM |
9422 | default: |
9423 | g_assert_not_reached(); | |
9424 | } | |
9425 | ||
9426 | write_vec_element(s, tcg_res, rd, pass, MO_64); | |
9427 | ||
9428 | tcg_temp_free_i64(tcg_res); | |
9429 | tcg_temp_free_i64(tcg_op1); | |
9430 | tcg_temp_free_i64(tcg_op2); | |
9431 | } else { | |
9432 | /* Single */ | |
9433 | TCGv_i32 tcg_op1 = tcg_temp_new_i32(); | |
9434 | TCGv_i32 tcg_op2 = tcg_temp_new_i32(); | |
9435 | TCGv_i32 tcg_res = tcg_temp_new_i32(); | |
9436 | ||
9437 | read_vec_element_i32(s, tcg_op1, rn, pass, MO_32); | |
9438 | read_vec_element_i32(s, tcg_op2, rm, pass, MO_32); | |
9439 | ||
9440 | switch (fpopcode) { | |
057d5f62 PM |
9441 | case 0x39: /* FMLS */ |
9442 | /* As usual for ARM, separate negation for fused multiply-add */ | |
9443 | gen_helper_vfp_negs(tcg_op1, tcg_op1); | |
9444 | /* fall through */ | |
9445 | case 0x19: /* FMLA */ | |
9446 | read_vec_element_i32(s, tcg_res, rd, pass, MO_32); | |
9447 | gen_helper_vfp_muladds(tcg_res, tcg_op1, tcg_op2, | |
9448 | tcg_res, fpst); | |
9449 | break; | |
845ea09a PM |
9450 | case 0x1a: /* FADD */ |
9451 | gen_helper_vfp_adds(tcg_res, tcg_op1, tcg_op2, fpst); | |
9452 | break; | |
057d5f62 PM |
9453 | case 0x1b: /* FMULX */ |
9454 | gen_helper_vfp_mulxs(tcg_res, tcg_op1, tcg_op2, fpst); | |
9455 | break; | |
8908f4d1 AB |
9456 | case 0x1c: /* FCMEQ */ |
9457 | gen_helper_neon_ceq_f32(tcg_res, tcg_op1, tcg_op2, fpst); | |
9458 | break; | |
845ea09a PM |
9459 | case 0x1e: /* FMAX */ |
9460 | gen_helper_vfp_maxs(tcg_res, tcg_op1, tcg_op2, fpst); | |
9461 | break; | |
057d5f62 PM |
9462 | case 0x1f: /* FRECPS */ |
9463 | gen_helper_recpsf_f32(tcg_res, tcg_op1, tcg_op2, fpst); | |
9464 | break; | |
845ea09a PM |
9465 | case 0x18: /* FMAXNM */ |
9466 | gen_helper_vfp_maxnums(tcg_res, tcg_op1, tcg_op2, fpst); | |
9467 | break; | |
9468 | case 0x38: /* FMINNM */ | |
9469 | gen_helper_vfp_minnums(tcg_res, tcg_op1, tcg_op2, fpst); | |
9470 | break; | |
9471 | case 0x3a: /* FSUB */ | |
9472 | gen_helper_vfp_subs(tcg_res, tcg_op1, tcg_op2, fpst); | |
9473 | break; | |
9474 | case 0x3e: /* FMIN */ | |
9475 | gen_helper_vfp_mins(tcg_res, tcg_op1, tcg_op2, fpst); | |
9476 | break; | |
057d5f62 PM |
9477 | case 0x3f: /* FRSQRTS */ |
9478 | gen_helper_rsqrtsf_f32(tcg_res, tcg_op1, tcg_op2, fpst); | |
9479 | break; | |
845ea09a PM |
9480 | case 0x5b: /* FMUL */ |
9481 | gen_helper_vfp_muls(tcg_res, tcg_op1, tcg_op2, fpst); | |
9482 | break; | |
8908f4d1 AB |
9483 | case 0x5c: /* FCMGE */ |
9484 | gen_helper_neon_cge_f32(tcg_res, tcg_op1, tcg_op2, fpst); | |
9485 | break; | |
057d5f62 PM |
9486 | case 0x5d: /* FACGE */ |
9487 | gen_helper_neon_acge_f32(tcg_res, tcg_op1, tcg_op2, fpst); | |
9488 | break; | |
845ea09a PM |
9489 | case 0x5f: /* FDIV */ |
9490 | gen_helper_vfp_divs(tcg_res, tcg_op1, tcg_op2, fpst); | |
9491 | break; | |
9492 | case 0x7a: /* FABD */ | |
9493 | gen_helper_vfp_subs(tcg_res, tcg_op1, tcg_op2, fpst); | |
9494 | gen_helper_vfp_abss(tcg_res, tcg_res); | |
9495 | break; | |
8908f4d1 AB |
9496 | case 0x7c: /* FCMGT */ |
9497 | gen_helper_neon_cgt_f32(tcg_res, tcg_op1, tcg_op2, fpst); | |
9498 | break; | |
057d5f62 PM |
9499 | case 0x7d: /* FACGT */ |
9500 | gen_helper_neon_acgt_f32(tcg_res, tcg_op1, tcg_op2, fpst); | |
9501 | break; | |
845ea09a PM |
9502 | default: |
9503 | g_assert_not_reached(); | |
9504 | } | |
9505 | ||
9506 | if (elements == 1) { | |
9507 | /* scalar single so clear high part */ | |
9508 | TCGv_i64 tcg_tmp = tcg_temp_new_i64(); | |
9509 | ||
9510 | tcg_gen_extu_i32_i64(tcg_tmp, tcg_res); | |
9511 | write_vec_element(s, tcg_tmp, rd, pass, MO_64); | |
9512 | tcg_temp_free_i64(tcg_tmp); | |
9513 | } else { | |
9514 | write_vec_element_i32(s, tcg_res, rd, pass, MO_32); | |
9515 | } | |
9516 | ||
9517 | tcg_temp_free_i32(tcg_res); | |
9518 | tcg_temp_free_i32(tcg_op1); | |
9519 | tcg_temp_free_i32(tcg_op2); | |
9520 | } | |
9521 | } | |
9522 | ||
9523 | tcg_temp_free_ptr(fpst); | |
9524 | ||
4ff55bcb | 9525 | clear_vec_high(s, elements * (size ? 8 : 4) > 8, rd); |
845ea09a PM |
9526 | } |
9527 | ||
4ce31af4 | 9528 | /* AdvSIMD scalar three same |
384b26fb AB |
9529 | * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0 |
9530 | * +-----+---+-----------+------+---+------+--------+---+------+------+ | |
9531 | * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd | | |
9532 | * +-----+---+-----------+------+---+------+--------+---+------+------+ | |
9533 | */ | |
9534 | static void disas_simd_scalar_three_reg_same(DisasContext *s, uint32_t insn) | |
9535 | { | |
b305dba6 PM |
9536 | int rd = extract32(insn, 0, 5); |
9537 | int rn = extract32(insn, 5, 5); | |
9538 | int opcode = extract32(insn, 11, 5); | |
9539 | int rm = extract32(insn, 16, 5); | |
9540 | int size = extract32(insn, 22, 2); | |
9541 | bool u = extract32(insn, 29, 1); | |
b305dba6 PM |
9542 | TCGv_i64 tcg_rd; |
9543 | ||
9544 | if (opcode >= 0x18) { | |
9545 | /* Floating point: U, size[1] and opcode indicate operation */ | |
9546 | int fpopcode = opcode | (extract32(size, 1, 1) << 5) | (u << 6); | |
9547 | switch (fpopcode) { | |
9548 | case 0x1b: /* FMULX */ | |
b305dba6 PM |
9549 | case 0x1f: /* FRECPS */ |
9550 | case 0x3f: /* FRSQRTS */ | |
b305dba6 | 9551 | case 0x5d: /* FACGE */ |
b305dba6 | 9552 | case 0x7d: /* FACGT */ |
8908f4d1 AB |
9553 | case 0x1c: /* FCMEQ */ |
9554 | case 0x5c: /* FCMGE */ | |
9555 | case 0x7c: /* FCMGT */ | |
845ea09a PM |
9556 | case 0x7a: /* FABD */ |
9557 | break; | |
b305dba6 PM |
9558 | default: |
9559 | unallocated_encoding(s); | |
9560 | return; | |
9561 | } | |
845ea09a | 9562 | |
8c6afa6a PM |
9563 | if (!fp_access_check(s)) { |
9564 | return; | |
9565 | } | |
9566 | ||
845ea09a PM |
9567 | handle_3same_float(s, extract32(size, 0, 1), 1, fpopcode, rd, rn, rm); |
9568 | return; | |
b305dba6 PM |
9569 | } |
9570 | ||
9571 | switch (opcode) { | |
9572 | case 0x1: /* SQADD, UQADD */ | |
9573 | case 0x5: /* SQSUB, UQSUB */ | |
c0b2b5fa PM |
9574 | case 0x9: /* SQSHL, UQSHL */ |
9575 | case 0xb: /* SQRSHL, UQRSHL */ | |
9576 | break; | |
6d9571f7 PM |
9577 | case 0x8: /* SSHL, USHL */ |
9578 | case 0xa: /* SRSHL, URSHL */ | |
b305dba6 PM |
9579 | case 0x6: /* CMGT, CMHI */ |
9580 | case 0x7: /* CMGE, CMHS */ | |
9581 | case 0x11: /* CMTST, CMEQ */ | |
9582 | case 0x10: /* ADD, SUB (vector) */ | |
9583 | if (size != 3) { | |
9584 | unallocated_encoding(s); | |
9585 | return; | |
9586 | } | |
9587 | break; | |
b305dba6 PM |
9588 | case 0x16: /* SQDMULH, SQRDMULH (vector) */ |
9589 | if (size != 1 && size != 2) { | |
9590 | unallocated_encoding(s); | |
9591 | return; | |
9592 | } | |
c0b2b5fa | 9593 | break; |
b305dba6 PM |
9594 | default: |
9595 | unallocated_encoding(s); | |
9596 | return; | |
9597 | } | |
9598 | ||
8c6afa6a PM |
9599 | if (!fp_access_check(s)) { |
9600 | return; | |
9601 | } | |
9602 | ||
b305dba6 PM |
9603 | tcg_rd = tcg_temp_new_i64(); |
9604 | ||
c0b2b5fa PM |
9605 | if (size == 3) { |
9606 | TCGv_i64 tcg_rn = read_fp_dreg(s, rn); | |
9607 | TCGv_i64 tcg_rm = read_fp_dreg(s, rm); | |
9608 | ||
9609 | handle_3same_64(s, opcode, u, tcg_rd, tcg_rn, tcg_rm); | |
9610 | tcg_temp_free_i64(tcg_rn); | |
9611 | tcg_temp_free_i64(tcg_rm); | |
9612 | } else { | |
9613 | /* Do a single operation on the lowest element in the vector. | |
9614 | * We use the standard Neon helpers and rely on 0 OP 0 == 0 with | |
9615 | * no side effects for all these operations. | |
9616 | * OPTME: special-purpose helpers would avoid doing some | |
9617 | * unnecessary work in the helper for the 8 and 16 bit cases. | |
9618 | */ | |
9619 | NeonGenTwoOpEnvFn *genenvfn; | |
9620 | TCGv_i32 tcg_rn = tcg_temp_new_i32(); | |
9621 | TCGv_i32 tcg_rm = tcg_temp_new_i32(); | |
9622 | TCGv_i32 tcg_rd32 = tcg_temp_new_i32(); | |
9623 | ||
9624 | read_vec_element_i32(s, tcg_rn, rn, 0, size); | |
9625 | read_vec_element_i32(s, tcg_rm, rm, 0, size); | |
9626 | ||
9627 | switch (opcode) { | |
9628 | case 0x1: /* SQADD, UQADD */ | |
9629 | { | |
9630 | static NeonGenTwoOpEnvFn * const fns[3][2] = { | |
9631 | { gen_helper_neon_qadd_s8, gen_helper_neon_qadd_u8 }, | |
9632 | { gen_helper_neon_qadd_s16, gen_helper_neon_qadd_u16 }, | |
9633 | { gen_helper_neon_qadd_s32, gen_helper_neon_qadd_u32 }, | |
9634 | }; | |
9635 | genenvfn = fns[size][u]; | |
9636 | break; | |
9637 | } | |
9638 | case 0x5: /* SQSUB, UQSUB */ | |
9639 | { | |
9640 | static NeonGenTwoOpEnvFn * const fns[3][2] = { | |
9641 | { gen_helper_neon_qsub_s8, gen_helper_neon_qsub_u8 }, | |
9642 | { gen_helper_neon_qsub_s16, gen_helper_neon_qsub_u16 }, | |
9643 | { gen_helper_neon_qsub_s32, gen_helper_neon_qsub_u32 }, | |
9644 | }; | |
9645 | genenvfn = fns[size][u]; | |
9646 | break; | |
9647 | } | |
9648 | case 0x9: /* SQSHL, UQSHL */ | |
9649 | { | |
9650 | static NeonGenTwoOpEnvFn * const fns[3][2] = { | |
9651 | { gen_helper_neon_qshl_s8, gen_helper_neon_qshl_u8 }, | |
9652 | { gen_helper_neon_qshl_s16, gen_helper_neon_qshl_u16 }, | |
9653 | { gen_helper_neon_qshl_s32, gen_helper_neon_qshl_u32 }, | |
9654 | }; | |
9655 | genenvfn = fns[size][u]; | |
9656 | break; | |
9657 | } | |
9658 | case 0xb: /* SQRSHL, UQRSHL */ | |
9659 | { | |
9660 | static NeonGenTwoOpEnvFn * const fns[3][2] = { | |
9661 | { gen_helper_neon_qrshl_s8, gen_helper_neon_qrshl_u8 }, | |
9662 | { gen_helper_neon_qrshl_s16, gen_helper_neon_qrshl_u16 }, | |
9663 | { gen_helper_neon_qrshl_s32, gen_helper_neon_qrshl_u32 }, | |
9664 | }; | |
9665 | genenvfn = fns[size][u]; | |
9666 | break; | |
9667 | } | |
9668 | case 0x16: /* SQDMULH, SQRDMULH */ | |
9669 | { | |
9670 | static NeonGenTwoOpEnvFn * const fns[2][2] = { | |
9671 | { gen_helper_neon_qdmulh_s16, gen_helper_neon_qrdmulh_s16 }, | |
9672 | { gen_helper_neon_qdmulh_s32, gen_helper_neon_qrdmulh_s32 }, | |
9673 | }; | |
9674 | assert(size == 1 || size == 2); | |
9675 | genenvfn = fns[size - 1][u]; | |
9676 | break; | |
9677 | } | |
9678 | default: | |
9679 | g_assert_not_reached(); | |
9680 | } | |
9681 | ||
9682 | genenvfn(tcg_rd32, cpu_env, tcg_rn, tcg_rm); | |
9683 | tcg_gen_extu_i32_i64(tcg_rd, tcg_rd32); | |
9684 | tcg_temp_free_i32(tcg_rd32); | |
9685 | tcg_temp_free_i32(tcg_rn); | |
9686 | tcg_temp_free_i32(tcg_rm); | |
9687 | } | |
b305dba6 PM |
9688 | |
9689 | write_fp_dreg(s, rd, tcg_rd); | |
9690 | ||
b305dba6 | 9691 | tcg_temp_free_i64(tcg_rd); |
384b26fb AB |
9692 | } |
9693 | ||
7c93b774 AB |
9694 | /* AdvSIMD scalar three same FP16 |
9695 | * 31 30 29 28 24 23 22 21 20 16 15 14 13 11 10 9 5 4 0 | |
9696 | * +-----+---+-----------+---+-----+------+-----+--------+---+----+----+ | |
9697 | * | 0 1 | U | 1 1 1 1 0 | a | 1 0 | Rm | 0 0 | opcode | 1 | Rn | Rd | | |
9698 | * +-----+---+-----------+---+-----+------+-----+--------+---+----+----+ | |
9699 | * v: 0101 1110 0100 0000 0000 0100 0000 0000 => 5e400400 | |
9700 | * m: 1101 1111 0110 0000 1100 0100 0000 0000 => df60c400 | |
9701 | */ | |
9702 | static void disas_simd_scalar_three_reg_same_fp16(DisasContext *s, | |
9703 | uint32_t insn) | |
9704 | { | |
9705 | int rd = extract32(insn, 0, 5); | |
9706 | int rn = extract32(insn, 5, 5); | |
9707 | int opcode = extract32(insn, 11, 3); | |
9708 | int rm = extract32(insn, 16, 5); | |
9709 | bool u = extract32(insn, 29, 1); | |
9710 | bool a = extract32(insn, 23, 1); | |
9711 | int fpopcode = opcode | (a << 3) | (u << 4); | |
9712 | TCGv_ptr fpst; | |
9713 | TCGv_i32 tcg_op1; | |
9714 | TCGv_i32 tcg_op2; | |
9715 | TCGv_i32 tcg_res; | |
9716 | ||
9717 | switch (fpopcode) { | |
9718 | case 0x03: /* FMULX */ | |
9719 | case 0x04: /* FCMEQ (reg) */ | |
9720 | case 0x07: /* FRECPS */ | |
9721 | case 0x0f: /* FRSQRTS */ | |
9722 | case 0x14: /* FCMGE (reg) */ | |
9723 | case 0x15: /* FACGE */ | |
9724 | case 0x1a: /* FABD */ | |
9725 | case 0x1c: /* FCMGT (reg) */ | |
9726 | case 0x1d: /* FACGT */ | |
9727 | break; | |
9728 | default: | |
9729 | unallocated_encoding(s); | |
9730 | return; | |
9731 | } | |
9732 | ||
5763190f | 9733 | if (!dc_isar_feature(aa64_fp16, s)) { |
7c93b774 AB |
9734 | unallocated_encoding(s); |
9735 | } | |
9736 | ||
9737 | if (!fp_access_check(s)) { | |
9738 | return; | |
9739 | } | |
9740 | ||
9741 | fpst = get_fpstatus_ptr(true); | |
9742 | ||
3d99d931 RH |
9743 | tcg_op1 = read_fp_hreg(s, rn); |
9744 | tcg_op2 = read_fp_hreg(s, rm); | |
7c93b774 AB |
9745 | tcg_res = tcg_temp_new_i32(); |
9746 | ||
7c93b774 AB |
9747 | switch (fpopcode) { |
9748 | case 0x03: /* FMULX */ | |
9749 | gen_helper_advsimd_mulxh(tcg_res, tcg_op1, tcg_op2, fpst); | |
9750 | break; | |
9751 | case 0x04: /* FCMEQ (reg) */ | |
9752 | gen_helper_advsimd_ceq_f16(tcg_res, tcg_op1, tcg_op2, fpst); | |
9753 | break; | |
9754 | case 0x07: /* FRECPS */ | |
9755 | gen_helper_recpsf_f16(tcg_res, tcg_op1, tcg_op2, fpst); | |
9756 | break; | |
9757 | case 0x0f: /* FRSQRTS */ | |
9758 | gen_helper_rsqrtsf_f16(tcg_res, tcg_op1, tcg_op2, fpst); | |
9759 | break; | |
9760 | case 0x14: /* FCMGE (reg) */ | |
9761 | gen_helper_advsimd_cge_f16(tcg_res, tcg_op1, tcg_op2, fpst); | |
9762 | break; | |
9763 | case 0x15: /* FACGE */ | |
9764 | gen_helper_advsimd_acge_f16(tcg_res, tcg_op1, tcg_op2, fpst); | |
9765 | break; | |
9766 | case 0x1a: /* FABD */ | |
9767 | gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst); | |
9768 | tcg_gen_andi_i32(tcg_res, tcg_res, 0x7fff); | |
9769 | break; | |
9770 | case 0x1c: /* FCMGT (reg) */ | |
9771 | gen_helper_advsimd_cgt_f16(tcg_res, tcg_op1, tcg_op2, fpst); | |
9772 | break; | |
9773 | case 0x1d: /* FACGT */ | |
9774 | gen_helper_advsimd_acgt_f16(tcg_res, tcg_op1, tcg_op2, fpst); | |
9775 | break; | |
9776 | default: | |
9777 | g_assert_not_reached(); | |
9778 | } | |
9779 | ||
9780 | write_fp_sreg(s, rd, tcg_res); | |
9781 | ||
9782 | ||
9783 | tcg_temp_free_i32(tcg_res); | |
9784 | tcg_temp_free_i32(tcg_op1); | |
9785 | tcg_temp_free_i32(tcg_op2); | |
9786 | tcg_temp_free_ptr(fpst); | |
9787 | } | |
9788 | ||
d9061ec3 RH |
9789 | /* AdvSIMD scalar three same extra |
9790 | * 31 30 29 28 24 23 22 21 20 16 15 14 11 10 9 5 4 0 | |
9791 | * +-----+---+-----------+------+---+------+---+--------+---+----+----+ | |
9792 | * | 0 1 | U | 1 1 1 1 0 | size | 0 | Rm | 1 | opcode | 1 | Rn | Rd | | |
9793 | * +-----+---+-----------+------+---+------+---+--------+---+----+----+ | |
9794 | */ | |
9795 | static void disas_simd_scalar_three_reg_same_extra(DisasContext *s, | |
9796 | uint32_t insn) | |
9797 | { | |
9798 | int rd = extract32(insn, 0, 5); | |
9799 | int rn = extract32(insn, 5, 5); | |
9800 | int opcode = extract32(insn, 11, 4); | |
9801 | int rm = extract32(insn, 16, 5); | |
9802 | int size = extract32(insn, 22, 2); | |
9803 | bool u = extract32(insn, 29, 1); | |
9804 | TCGv_i32 ele1, ele2, ele3; | |
9805 | TCGv_i64 res; | |
962fcbf2 | 9806 | bool feature; |
d9061ec3 RH |
9807 | |
9808 | switch (u * 16 + opcode) { | |
9809 | case 0x10: /* SQRDMLAH (vector) */ | |
9810 | case 0x11: /* SQRDMLSH (vector) */ | |
9811 | if (size != 1 && size != 2) { | |
9812 | unallocated_encoding(s); | |
9813 | return; | |
9814 | } | |
962fcbf2 | 9815 | feature = dc_isar_feature(aa64_rdm, s); |
d9061ec3 RH |
9816 | break; |
9817 | default: | |
9818 | unallocated_encoding(s); | |
9819 | return; | |
9820 | } | |
962fcbf2 | 9821 | if (!feature) { |
d9061ec3 RH |
9822 | unallocated_encoding(s); |
9823 | return; | |
9824 | } | |
9825 | if (!fp_access_check(s)) { | |
9826 | return; | |
9827 | } | |
9828 | ||
9829 | /* Do a single operation on the lowest element in the vector. | |
9830 | * We use the standard Neon helpers and rely on 0 OP 0 == 0 | |
9831 | * with no side effects for all these operations. | |
9832 | * OPTME: special-purpose helpers would avoid doing some | |
9833 | * unnecessary work in the helper for the 16 bit cases. | |
9834 | */ | |
9835 | ele1 = tcg_temp_new_i32(); | |
9836 | ele2 = tcg_temp_new_i32(); | |
9837 | ele3 = tcg_temp_new_i32(); | |
9838 | ||
9839 | read_vec_element_i32(s, ele1, rn, 0, size); | |
9840 | read_vec_element_i32(s, ele2, rm, 0, size); | |
9841 | read_vec_element_i32(s, ele3, rd, 0, size); | |
9842 | ||
9843 | switch (opcode) { | |
9844 | case 0x0: /* SQRDMLAH */ | |
9845 | if (size == 1) { | |
9846 | gen_helper_neon_qrdmlah_s16(ele3, cpu_env, ele1, ele2, ele3); | |
9847 | } else { | |
9848 | gen_helper_neon_qrdmlah_s32(ele3, cpu_env, ele1, ele2, ele3); | |
9849 | } | |
9850 | break; | |
9851 | case 0x1: /* SQRDMLSH */ | |
9852 | if (size == 1) { | |
9853 | gen_helper_neon_qrdmlsh_s16(ele3, cpu_env, ele1, ele2, ele3); | |
9854 | } else { | |
9855 | gen_helper_neon_qrdmlsh_s32(ele3, cpu_env, ele1, ele2, ele3); | |
9856 | } | |
9857 | break; | |
9858 | default: | |
9859 | g_assert_not_reached(); | |
9860 | } | |
9861 | tcg_temp_free_i32(ele1); | |
9862 | tcg_temp_free_i32(ele2); | |
9863 | ||
9864 | res = tcg_temp_new_i64(); | |
9865 | tcg_gen_extu_i32_i64(res, ele3); | |
9866 | tcg_temp_free_i32(ele3); | |
9867 | ||
9868 | write_fp_dreg(s, rd, res); | |
9869 | tcg_temp_free_i64(res); | |
9870 | } | |
9871 | ||
effa8e06 | 9872 | static void handle_2misc_64(DisasContext *s, int opcode, bool u, |
04c7c6c2 PM |
9873 | TCGv_i64 tcg_rd, TCGv_i64 tcg_rn, |
9874 | TCGv_i32 tcg_rmode, TCGv_ptr tcg_fpstatus) | |
effa8e06 PM |
9875 | { |
9876 | /* Handle 64->64 opcodes which are shared between the scalar and | |
9877 | * vector 2-reg-misc groups. We cover every integer opcode where size == 3 | |
f93d0138 | 9878 | * is valid in either group and also the double-precision fp ops. |
04c7c6c2 PM |
9879 | * The caller only need provide tcg_rmode and tcg_fpstatus if the op |
9880 | * requires them. | |
effa8e06 PM |
9881 | */ |
9882 | TCGCond cond; | |
9883 | ||
9884 | switch (opcode) { | |
b05c3068 AB |
9885 | case 0x4: /* CLS, CLZ */ |
9886 | if (u) { | |
7539a012 | 9887 | tcg_gen_clzi_i64(tcg_rd, tcg_rn, 64); |
b05c3068 | 9888 | } else { |
bc21dbcc | 9889 | tcg_gen_clrsb_i64(tcg_rd, tcg_rn); |
b05c3068 AB |
9890 | } |
9891 | break; | |
86cbc418 PM |
9892 | case 0x5: /* NOT */ |
9893 | /* This opcode is shared with CNT and RBIT but we have earlier | |
9894 | * enforced that size == 3 if and only if this is the NOT insn. | |
9895 | */ | |
9896 | tcg_gen_not_i64(tcg_rd, tcg_rn); | |
9897 | break; | |
0a79bc87 AB |
9898 | case 0x7: /* SQABS, SQNEG */ |
9899 | if (u) { | |
9900 | gen_helper_neon_qneg_s64(tcg_rd, cpu_env, tcg_rn); | |
9901 | } else { | |
9902 | gen_helper_neon_qabs_s64(tcg_rd, cpu_env, tcg_rn); | |
9903 | } | |
9904 | break; | |
effa8e06 PM |
9905 | case 0xa: /* CMLT */ |
9906 | /* 64 bit integer comparison against zero, result is | |
9907 | * test ? (2^64 - 1) : 0. We implement via setcond(!test) and | |
9908 | * subtracting 1. | |
9909 | */ | |
9910 | cond = TCG_COND_LT; | |
9911 | do_cmop: | |
9912 | tcg_gen_setcondi_i64(cond, tcg_rd, tcg_rn, 0); | |
9913 | tcg_gen_neg_i64(tcg_rd, tcg_rd); | |
9914 | break; | |
9915 | case 0x8: /* CMGT, CMGE */ | |
9916 | cond = u ? TCG_COND_GE : TCG_COND_GT; | |
9917 | goto do_cmop; | |
9918 | case 0x9: /* CMEQ, CMLE */ | |
9919 | cond = u ? TCG_COND_LE : TCG_COND_EQ; | |
9920 | goto do_cmop; | |
9921 | case 0xb: /* ABS, NEG */ | |
9922 | if (u) { | |
9923 | tcg_gen_neg_i64(tcg_rd, tcg_rn); | |
9924 | } else { | |
4e027a71 | 9925 | tcg_gen_abs_i64(tcg_rd, tcg_rn); |
effa8e06 PM |
9926 | } |
9927 | break; | |
f93d0138 PM |
9928 | case 0x2f: /* FABS */ |
9929 | gen_helper_vfp_absd(tcg_rd, tcg_rn); | |
9930 | break; | |
9931 | case 0x6f: /* FNEG */ | |
9932 | gen_helper_vfp_negd(tcg_rd, tcg_rn); | |
9933 | break; | |
f612537e AB |
9934 | case 0x7f: /* FSQRT */ |
9935 | gen_helper_vfp_sqrtd(tcg_rd, tcg_rn, cpu_env); | |
9936 | break; | |
04c7c6c2 PM |
9937 | case 0x1a: /* FCVTNS */ |
9938 | case 0x1b: /* FCVTMS */ | |
9939 | case 0x1c: /* FCVTAS */ | |
9940 | case 0x3a: /* FCVTPS */ | |
9941 | case 0x3b: /* FCVTZS */ | |
9942 | { | |
9943 | TCGv_i32 tcg_shift = tcg_const_i32(0); | |
9944 | gen_helper_vfp_tosqd(tcg_rd, tcg_rn, tcg_shift, tcg_fpstatus); | |
9945 | tcg_temp_free_i32(tcg_shift); | |
9946 | break; | |
9947 | } | |
9948 | case 0x5a: /* FCVTNU */ | |
9949 | case 0x5b: /* FCVTMU */ | |
9950 | case 0x5c: /* FCVTAU */ | |
9951 | case 0x7a: /* FCVTPU */ | |
9952 | case 0x7b: /* FCVTZU */ | |
9953 | { | |
9954 | TCGv_i32 tcg_shift = tcg_const_i32(0); | |
9955 | gen_helper_vfp_touqd(tcg_rd, tcg_rn, tcg_shift, tcg_fpstatus); | |
9956 | tcg_temp_free_i32(tcg_shift); | |
9957 | break; | |
9958 | } | |
03df01ed PM |
9959 | case 0x18: /* FRINTN */ |
9960 | case 0x19: /* FRINTM */ | |
9961 | case 0x38: /* FRINTP */ | |
9962 | case 0x39: /* FRINTZ */ | |
9963 | case 0x58: /* FRINTA */ | |
9964 | case 0x79: /* FRINTI */ | |
9965 | gen_helper_rintd(tcg_rd, tcg_rn, tcg_fpstatus); | |
9966 | break; | |
9967 | case 0x59: /* FRINTX */ | |
9968 | gen_helper_rintd_exact(tcg_rd, tcg_rn, tcg_fpstatus); | |
9969 | break; | |
6bea2563 RH |
9970 | case 0x1e: /* FRINT32Z */ |
9971 | case 0x5e: /* FRINT32X */ | |
9972 | gen_helper_frint32_d(tcg_rd, tcg_rn, tcg_fpstatus); | |
9973 | break; | |
9974 | case 0x1f: /* FRINT64Z */ | |
9975 | case 0x5f: /* FRINT64X */ | |
9976 | gen_helper_frint64_d(tcg_rd, tcg_rn, tcg_fpstatus); | |
9977 | break; | |
effa8e06 PM |
9978 | default: |
9979 | g_assert_not_reached(); | |
9980 | } | |
9981 | } | |
9982 | ||
8908f4d1 AB |
9983 | static void handle_2misc_fcmp_zero(DisasContext *s, int opcode, |
9984 | bool is_scalar, bool is_u, bool is_q, | |
9985 | int size, int rn, int rd) | |
9986 | { | |
7d4dd1a7 | 9987 | bool is_double = (size == MO_64); |
8c6afa6a PM |
9988 | TCGv_ptr fpst; |
9989 | ||
9990 | if (!fp_access_check(s)) { | |
9991 | return; | |
9992 | } | |
9993 | ||
7d4dd1a7 | 9994 | fpst = get_fpstatus_ptr(size == MO_16); |
8908f4d1 AB |
9995 | |
9996 | if (is_double) { | |
9997 | TCGv_i64 tcg_op = tcg_temp_new_i64(); | |
9998 | TCGv_i64 tcg_zero = tcg_const_i64(0); | |
9999 | TCGv_i64 tcg_res = tcg_temp_new_i64(); | |
5de3fd04 | 10000 | NeonGenTwoDoubleOpFn *genfn; |
8908f4d1 AB |
10001 | bool swap = false; |
10002 | int pass; | |
10003 | ||
10004 | switch (opcode) { | |
10005 | case 0x2e: /* FCMLT (zero) */ | |
10006 | swap = true; | |
10007 | /* fallthrough */ | |
10008 | case 0x2c: /* FCMGT (zero) */ | |
10009 | genfn = gen_helper_neon_cgt_f64; | |
10010 | break; | |
10011 | case 0x2d: /* FCMEQ (zero) */ | |
10012 | genfn = gen_helper_neon_ceq_f64; | |
10013 | break; | |
10014 | case 0x6d: /* FCMLE (zero) */ | |
10015 | swap = true; | |
10016 | /* fall through */ | |
10017 | case 0x6c: /* FCMGE (zero) */ | |
10018 | genfn = gen_helper_neon_cge_f64; | |
10019 | break; | |
10020 | default: | |
10021 | g_assert_not_reached(); | |
10022 | } | |
10023 | ||
10024 | for (pass = 0; pass < (is_scalar ? 1 : 2); pass++) { | |
10025 | read_vec_element(s, tcg_op, rn, pass, MO_64); | |
10026 | if (swap) { | |
10027 | genfn(tcg_res, tcg_zero, tcg_op, fpst); | |
10028 | } else { | |
10029 | genfn(tcg_res, tcg_op, tcg_zero, fpst); | |
10030 | } | |
10031 | write_vec_element(s, tcg_res, rd, pass, MO_64); | |
10032 | } | |
8908f4d1 AB |
10033 | tcg_temp_free_i64(tcg_res); |
10034 | tcg_temp_free_i64(tcg_zero); | |
10035 | tcg_temp_free_i64(tcg_op); | |
4ff55bcb RH |
10036 | |
10037 | clear_vec_high(s, !is_scalar, rd); | |
8908f4d1 AB |
10038 | } else { |
10039 | TCGv_i32 tcg_op = tcg_temp_new_i32(); | |
10040 | TCGv_i32 tcg_zero = tcg_const_i32(0); | |
10041 | TCGv_i32 tcg_res = tcg_temp_new_i32(); | |
5de3fd04 | 10042 | NeonGenTwoSingleOpFn *genfn; |
8908f4d1 AB |
10043 | bool swap = false; |
10044 | int pass, maxpasses; | |
10045 | ||
7d4dd1a7 AB |
10046 | if (size == MO_16) { |
10047 | switch (opcode) { | |
10048 | case 0x2e: /* FCMLT (zero) */ | |
10049 | swap = true; | |
10050 | /* fall through */ | |
10051 | case 0x2c: /* FCMGT (zero) */ | |
10052 | genfn = gen_helper_advsimd_cgt_f16; | |
10053 | break; | |
10054 | case 0x2d: /* FCMEQ (zero) */ | |
10055 | genfn = gen_helper_advsimd_ceq_f16; | |
10056 | break; | |
10057 | case 0x6d: /* FCMLE (zero) */ | |
10058 | swap = true; | |
10059 | /* fall through */ | |
10060 | case 0x6c: /* FCMGE (zero) */ | |
10061 | genfn = gen_helper_advsimd_cge_f16; | |
10062 | break; | |
10063 | default: | |
10064 | g_assert_not_reached(); | |
10065 | } | |
10066 | } else { | |
10067 | switch (opcode) { | |
10068 | case 0x2e: /* FCMLT (zero) */ | |
10069 | swap = true; | |
10070 | /* fall through */ | |
10071 | case 0x2c: /* FCMGT (zero) */ | |
10072 | genfn = gen_helper_neon_cgt_f32; | |
10073 | break; | |
10074 | case 0x2d: /* FCMEQ (zero) */ | |
10075 | genfn = gen_helper_neon_ceq_f32; | |
10076 | break; | |
10077 | case 0x6d: /* FCMLE (zero) */ | |
10078 | swap = true; | |
10079 | /* fall through */ | |
10080 | case 0x6c: /* FCMGE (zero) */ | |
10081 | genfn = gen_helper_neon_cge_f32; | |
10082 | break; | |
10083 | default: | |
10084 | g_assert_not_reached(); | |
10085 | } | |
8908f4d1 AB |
10086 | } |
10087 | ||
10088 | if (is_scalar) { | |
10089 | maxpasses = 1; | |
10090 | } else { | |
7d4dd1a7 AB |
10091 | int vector_size = 8 << is_q; |
10092 | maxpasses = vector_size >> size; | |
8908f4d1 AB |
10093 | } |
10094 | ||
10095 | for (pass = 0; pass < maxpasses; pass++) { | |
7d4dd1a7 | 10096 | read_vec_element_i32(s, tcg_op, rn, pass, size); |
8908f4d1 AB |
10097 | if (swap) { |
10098 | genfn(tcg_res, tcg_zero, tcg_op, fpst); | |
10099 | } else { | |
10100 | genfn(tcg_res, tcg_op, tcg_zero, fpst); | |
10101 | } | |
10102 | if (is_scalar) { | |
10103 | write_fp_sreg(s, rd, tcg_res); | |
10104 | } else { | |
7d4dd1a7 | 10105 | write_vec_element_i32(s, tcg_res, rd, pass, size); |
8908f4d1 AB |
10106 | } |
10107 | } | |
10108 | tcg_temp_free_i32(tcg_res); | |
10109 | tcg_temp_free_i32(tcg_zero); | |
10110 | tcg_temp_free_i32(tcg_op); | |
4ff55bcb RH |
10111 | if (!is_scalar) { |
10112 | clear_vec_high(s, is_q, rd); | |
8908f4d1 AB |
10113 | } |
10114 | } | |
10115 | ||
10116 | tcg_temp_free_ptr(fpst); | |
10117 | } | |
10118 | ||
8f0c6758 AB |
10119 | static void handle_2misc_reciprocal(DisasContext *s, int opcode, |
10120 | bool is_scalar, bool is_u, bool is_q, | |
10121 | int size, int rn, int rd) | |
10122 | { | |
10123 | bool is_double = (size == 3); | |
d81ce0ef | 10124 | TCGv_ptr fpst = get_fpstatus_ptr(false); |
8f0c6758 AB |
10125 | |
10126 | if (is_double) { | |
10127 | TCGv_i64 tcg_op = tcg_temp_new_i64(); | |
10128 | TCGv_i64 tcg_res = tcg_temp_new_i64(); | |
10129 | int pass; | |
10130 | ||
10131 | for (pass = 0; pass < (is_scalar ? 1 : 2); pass++) { | |
10132 | read_vec_element(s, tcg_op, rn, pass, MO_64); | |
10133 | switch (opcode) { | |
b6d4443a AB |
10134 | case 0x3d: /* FRECPE */ |
10135 | gen_helper_recpe_f64(tcg_res, tcg_op, fpst); | |
10136 | break; | |
8f0c6758 AB |
10137 | case 0x3f: /* FRECPX */ |
10138 | gen_helper_frecpx_f64(tcg_res, tcg_op, fpst); | |
10139 | break; | |
c2fb418e AB |
10140 | case 0x7d: /* FRSQRTE */ |
10141 | gen_helper_rsqrte_f64(tcg_res, tcg_op, fpst); | |
10142 | break; | |
8f0c6758 AB |
10143 | default: |
10144 | g_assert_not_reached(); | |
10145 | } | |
10146 | write_vec_element(s, tcg_res, rd, pass, MO_64); | |
10147 | } | |
8f0c6758 AB |
10148 | tcg_temp_free_i64(tcg_res); |
10149 | tcg_temp_free_i64(tcg_op); | |
4ff55bcb | 10150 | clear_vec_high(s, !is_scalar, rd); |
8f0c6758 AB |
10151 | } else { |
10152 | TCGv_i32 tcg_op = tcg_temp_new_i32(); | |
10153 | TCGv_i32 tcg_res = tcg_temp_new_i32(); | |
10154 | int pass, maxpasses; | |
10155 | ||
10156 | if (is_scalar) { | |
10157 | maxpasses = 1; | |
10158 | } else { | |
10159 | maxpasses = is_q ? 4 : 2; | |
10160 | } | |
10161 | ||
10162 | for (pass = 0; pass < maxpasses; pass++) { | |
10163 | read_vec_element_i32(s, tcg_op, rn, pass, MO_32); | |
10164 | ||
10165 | switch (opcode) { | |
b6d4443a | 10166 | case 0x3c: /* URECPE */ |
fe6fb4be | 10167 | gen_helper_recpe_u32(tcg_res, tcg_op); |
b6d4443a AB |
10168 | break; |
10169 | case 0x3d: /* FRECPE */ | |
10170 | gen_helper_recpe_f32(tcg_res, tcg_op, fpst); | |
10171 | break; | |
8f0c6758 AB |
10172 | case 0x3f: /* FRECPX */ |
10173 | gen_helper_frecpx_f32(tcg_res, tcg_op, fpst); | |
10174 | break; | |
c2fb418e AB |
10175 | case 0x7d: /* FRSQRTE */ |
10176 | gen_helper_rsqrte_f32(tcg_res, tcg_op, fpst); | |
10177 | break; | |
8f0c6758 AB |
10178 | default: |
10179 | g_assert_not_reached(); | |
10180 | } | |
10181 | ||
10182 | if (is_scalar) { | |
10183 | write_fp_sreg(s, rd, tcg_res); | |
10184 | } else { | |
10185 | write_vec_element_i32(s, tcg_res, rd, pass, MO_32); | |
10186 | } | |
10187 | } | |
10188 | tcg_temp_free_i32(tcg_res); | |
10189 | tcg_temp_free_i32(tcg_op); | |
4ff55bcb RH |
10190 | if (!is_scalar) { |
10191 | clear_vec_high(s, is_q, rd); | |
8f0c6758 AB |
10192 | } |
10193 | } | |
10194 | tcg_temp_free_ptr(fpst); | |
10195 | } | |
10196 | ||
5201c136 AB |
10197 | static void handle_2misc_narrow(DisasContext *s, bool scalar, |
10198 | int opcode, bool u, bool is_q, | |
8b092ca9 AB |
10199 | int size, int rn, int rd) |
10200 | { | |
10201 | /* Handle 2-reg-misc ops which are narrowing (so each 2*size element | |
10202 | * in the source becomes a size element in the destination). | |
10203 | */ | |
10204 | int pass; | |
10205 | TCGv_i32 tcg_res[2]; | |
10206 | int destelt = is_q ? 2 : 0; | |
5201c136 | 10207 | int passes = scalar ? 1 : 2; |
8b092ca9 | 10208 | |
5201c136 AB |
10209 | if (scalar) { |
10210 | tcg_res[1] = tcg_const_i32(0); | |
10211 | } | |
10212 | ||
10213 | for (pass = 0; pass < passes; pass++) { | |
8b092ca9 AB |
10214 | TCGv_i64 tcg_op = tcg_temp_new_i64(); |
10215 | NeonGenNarrowFn *genfn = NULL; | |
10216 | NeonGenNarrowEnvFn *genenvfn = NULL; | |
10217 | ||
5201c136 AB |
10218 | if (scalar) { |
10219 | read_vec_element(s, tcg_op, rn, pass, size + 1); | |
10220 | } else { | |
10221 | read_vec_element(s, tcg_op, rn, pass, MO_64); | |
10222 | } | |
8b092ca9 AB |
10223 | tcg_res[pass] = tcg_temp_new_i32(); |
10224 | ||
10225 | switch (opcode) { | |
10226 | case 0x12: /* XTN, SQXTUN */ | |
10227 | { | |
10228 | static NeonGenNarrowFn * const xtnfns[3] = { | |
10229 | gen_helper_neon_narrow_u8, | |
10230 | gen_helper_neon_narrow_u16, | |
ecc7b3aa | 10231 | tcg_gen_extrl_i64_i32, |
8b092ca9 AB |
10232 | }; |
10233 | static NeonGenNarrowEnvFn * const sqxtunfns[3] = { | |
10234 | gen_helper_neon_unarrow_sat8, | |
10235 | gen_helper_neon_unarrow_sat16, | |
10236 | gen_helper_neon_unarrow_sat32, | |
10237 | }; | |
10238 | if (u) { | |
10239 | genenvfn = sqxtunfns[size]; | |
10240 | } else { | |
10241 | genfn = xtnfns[size]; | |
10242 | } | |
10243 | break; | |
10244 | } | |
10245 | case 0x14: /* SQXTN, UQXTN */ | |
10246 | { | |
10247 | static NeonGenNarrowEnvFn * const fns[3][2] = { | |
10248 | { gen_helper_neon_narrow_sat_s8, | |
10249 | gen_helper_neon_narrow_sat_u8 }, | |
10250 | { gen_helper_neon_narrow_sat_s16, | |
10251 | gen_helper_neon_narrow_sat_u16 }, | |
10252 | { gen_helper_neon_narrow_sat_s32, | |
10253 | gen_helper_neon_narrow_sat_u32 }, | |
10254 | }; | |
10255 | genenvfn = fns[size][u]; | |
10256 | break; | |
10257 | } | |
10258 | case 0x16: /* FCVTN, FCVTN2 */ | |
10259 | /* 32 bit to 16 bit or 64 bit to 32 bit float conversion */ | |
10260 | if (size == 2) { | |
10261 | gen_helper_vfp_fcvtsd(tcg_res[pass], tcg_op, cpu_env); | |
10262 | } else { | |
10263 | TCGv_i32 tcg_lo = tcg_temp_new_i32(); | |
10264 | TCGv_i32 tcg_hi = tcg_temp_new_i32(); | |
486624fc AB |
10265 | TCGv_ptr fpst = get_fpstatus_ptr(false); |
10266 | TCGv_i32 ahp = get_ahp_flag(); | |
10267 | ||
7cb36e18 | 10268 | tcg_gen_extr_i64_i32(tcg_lo, tcg_hi, tcg_op); |
486624fc AB |
10269 | gen_helper_vfp_fcvt_f32_to_f16(tcg_lo, tcg_lo, fpst, ahp); |
10270 | gen_helper_vfp_fcvt_f32_to_f16(tcg_hi, tcg_hi, fpst, ahp); | |
8b092ca9 AB |
10271 | tcg_gen_deposit_i32(tcg_res[pass], tcg_lo, tcg_hi, 16, 16); |
10272 | tcg_temp_free_i32(tcg_lo); | |
10273 | tcg_temp_free_i32(tcg_hi); | |
486624fc AB |
10274 | tcg_temp_free_ptr(fpst); |
10275 | tcg_temp_free_i32(ahp); | |
8b092ca9 AB |
10276 | } |
10277 | break; | |
5553955e PM |
10278 | case 0x56: /* FCVTXN, FCVTXN2 */ |
10279 | /* 64 bit to 32 bit float conversion | |
10280 | * with von Neumann rounding (round to odd) | |
10281 | */ | |
10282 | assert(size == 2); | |
10283 | gen_helper_fcvtx_f64_to_f32(tcg_res[pass], tcg_op, cpu_env); | |
10284 | break; | |
8b092ca9 AB |
10285 | default: |
10286 | g_assert_not_reached(); | |
10287 | } | |
10288 | ||
10289 | if (genfn) { | |
10290 | genfn(tcg_res[pass], tcg_op); | |
10291 | } else if (genenvfn) { | |
10292 | genenvfn(tcg_res[pass], cpu_env, tcg_op); | |
10293 | } | |
10294 | ||
10295 | tcg_temp_free_i64(tcg_op); | |
10296 | } | |
10297 | ||
10298 | for (pass = 0; pass < 2; pass++) { | |
10299 | write_vec_element_i32(s, tcg_res[pass], rd, destelt + pass, MO_32); | |
10300 | tcg_temp_free_i32(tcg_res[pass]); | |
10301 | } | |
4ff55bcb | 10302 | clear_vec_high(s, is_q, rd); |
8b092ca9 AB |
10303 | } |
10304 | ||
09e03735 AB |
10305 | /* Remaining saturating accumulating ops */ |
10306 | static void handle_2misc_satacc(DisasContext *s, bool is_scalar, bool is_u, | |
10307 | bool is_q, int size, int rn, int rd) | |
10308 | { | |
10309 | bool is_double = (size == 3); | |
10310 | ||
10311 | if (is_double) { | |
10312 | TCGv_i64 tcg_rn = tcg_temp_new_i64(); | |
10313 | TCGv_i64 tcg_rd = tcg_temp_new_i64(); | |
10314 | int pass; | |
10315 | ||
10316 | for (pass = 0; pass < (is_scalar ? 1 : 2); pass++) { | |
10317 | read_vec_element(s, tcg_rn, rn, pass, MO_64); | |
10318 | read_vec_element(s, tcg_rd, rd, pass, MO_64); | |
10319 | ||
10320 | if (is_u) { /* USQADD */ | |
10321 | gen_helper_neon_uqadd_s64(tcg_rd, cpu_env, tcg_rn, tcg_rd); | |
10322 | } else { /* SUQADD */ | |
10323 | gen_helper_neon_sqadd_u64(tcg_rd, cpu_env, tcg_rn, tcg_rd); | |
10324 | } | |
10325 | write_vec_element(s, tcg_rd, rd, pass, MO_64); | |
10326 | } | |
09e03735 AB |
10327 | tcg_temp_free_i64(tcg_rd); |
10328 | tcg_temp_free_i64(tcg_rn); | |
4ff55bcb | 10329 | clear_vec_high(s, !is_scalar, rd); |
09e03735 AB |
10330 | } else { |
10331 | TCGv_i32 tcg_rn = tcg_temp_new_i32(); | |
10332 | TCGv_i32 tcg_rd = tcg_temp_new_i32(); | |
10333 | int pass, maxpasses; | |
10334 | ||
10335 | if (is_scalar) { | |
10336 | maxpasses = 1; | |
10337 | } else { | |
10338 | maxpasses = is_q ? 4 : 2; | |
10339 | } | |
10340 | ||
10341 | for (pass = 0; pass < maxpasses; pass++) { | |
10342 | if (is_scalar) { | |
10343 | read_vec_element_i32(s, tcg_rn, rn, pass, size); | |
10344 | read_vec_element_i32(s, tcg_rd, rd, pass, size); | |
10345 | } else { | |
10346 | read_vec_element_i32(s, tcg_rn, rn, pass, MO_32); | |
10347 | read_vec_element_i32(s, tcg_rd, rd, pass, MO_32); | |
10348 | } | |
10349 | ||
10350 | if (is_u) { /* USQADD */ | |
10351 | switch (size) { | |
10352 | case 0: | |
10353 | gen_helper_neon_uqadd_s8(tcg_rd, cpu_env, tcg_rn, tcg_rd); | |
10354 | break; | |
10355 | case 1: | |
10356 | gen_helper_neon_uqadd_s16(tcg_rd, cpu_env, tcg_rn, tcg_rd); | |
10357 | break; | |
10358 | case 2: | |
10359 | gen_helper_neon_uqadd_s32(tcg_rd, cpu_env, tcg_rn, tcg_rd); | |
10360 | break; | |
10361 | default: | |
10362 | g_assert_not_reached(); | |
10363 | } | |
10364 | } else { /* SUQADD */ | |
10365 | switch (size) { | |
10366 | case 0: | |
10367 | gen_helper_neon_sqadd_u8(tcg_rd, cpu_env, tcg_rn, tcg_rd); | |
10368 | break; | |
10369 | case 1: | |
10370 | gen_helper_neon_sqadd_u16(tcg_rd, cpu_env, tcg_rn, tcg_rd); | |
10371 | break; | |
10372 | case 2: | |
10373 | gen_helper_neon_sqadd_u32(tcg_rd, cpu_env, tcg_rn, tcg_rd); | |
10374 | break; | |
10375 | default: | |
10376 | g_assert_not_reached(); | |
10377 | } | |
10378 | } | |
10379 | ||
10380 | if (is_scalar) { | |
10381 | TCGv_i64 tcg_zero = tcg_const_i64(0); | |
10382 | write_vec_element(s, tcg_zero, rd, 0, MO_64); | |
10383 | tcg_temp_free_i64(tcg_zero); | |
10384 | } | |
10385 | write_vec_element_i32(s, tcg_rd, rd, pass, MO_32); | |
10386 | } | |
09e03735 AB |
10387 | tcg_temp_free_i32(tcg_rd); |
10388 | tcg_temp_free_i32(tcg_rn); | |
4ff55bcb | 10389 | clear_vec_high(s, is_q, rd); |
09e03735 AB |
10390 | } |
10391 | } | |
10392 | ||
4ce31af4 | 10393 | /* AdvSIMD scalar two reg misc |
384b26fb AB |
10394 | * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0 |
10395 | * +-----+---+-----------+------+-----------+--------+-----+------+------+ | |
10396 | * | 0 1 | U | 1 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd | | |
10397 | * +-----+---+-----------+------+-----------+--------+-----+------+------+ | |
10398 | */ | |
10399 | static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn) | |
10400 | { | |
effa8e06 PM |
10401 | int rd = extract32(insn, 0, 5); |
10402 | int rn = extract32(insn, 5, 5); | |
10403 | int opcode = extract32(insn, 12, 5); | |
10404 | int size = extract32(insn, 22, 2); | |
10405 | bool u = extract32(insn, 29, 1); | |
04c7c6c2 PM |
10406 | bool is_fcvt = false; |
10407 | int rmode; | |
10408 | TCGv_i32 tcg_rmode; | |
10409 | TCGv_ptr tcg_fpstatus; | |
effa8e06 PM |
10410 | |
10411 | switch (opcode) { | |
09e03735 | 10412 | case 0x3: /* USQADD / SUQADD*/ |
8c6afa6a PM |
10413 | if (!fp_access_check(s)) { |
10414 | return; | |
10415 | } | |
09e03735 AB |
10416 | handle_2misc_satacc(s, true, u, false, size, rn, rd); |
10417 | return; | |
0a79bc87 AB |
10418 | case 0x7: /* SQABS / SQNEG */ |
10419 | break; | |
effa8e06 PM |
10420 | case 0xa: /* CMLT */ |
10421 | if (u) { | |
10422 | unallocated_encoding(s); | |
10423 | return; | |
10424 | } | |
10425 | /* fall through */ | |
10426 | case 0x8: /* CMGT, CMGE */ | |
10427 | case 0x9: /* CMEQ, CMLE */ | |
10428 | case 0xb: /* ABS, NEG */ | |
10429 | if (size != 3) { | |
10430 | unallocated_encoding(s); | |
10431 | return; | |
10432 | } | |
10433 | break; | |
5201c136 | 10434 | case 0x12: /* SQXTUN */ |
e44a90c5 | 10435 | if (!u) { |
5201c136 AB |
10436 | unallocated_encoding(s); |
10437 | return; | |
10438 | } | |
10439 | /* fall through */ | |
10440 | case 0x14: /* SQXTN, UQXTN */ | |
10441 | if (size == 3) { | |
10442 | unallocated_encoding(s); | |
10443 | return; | |
10444 | } | |
8c6afa6a PM |
10445 | if (!fp_access_check(s)) { |
10446 | return; | |
10447 | } | |
5201c136 AB |
10448 | handle_2misc_narrow(s, true, opcode, u, false, size, rn, rd); |
10449 | return; | |
8908f4d1 AB |
10450 | case 0xc ... 0xf: |
10451 | case 0x16 ... 0x1d: | |
10452 | case 0x1f: | |
10453 | /* Floating point: U, size[1] and opcode indicate operation; | |
10454 | * size[0] indicates single or double precision. | |
10455 | */ | |
10456 | opcode |= (extract32(size, 1, 1) << 5) | (u << 6); | |
10457 | size = extract32(size, 0, 1) ? 3 : 2; | |
10458 | switch (opcode) { | |
10459 | case 0x2c: /* FCMGT (zero) */ | |
10460 | case 0x2d: /* FCMEQ (zero) */ | |
10461 | case 0x2e: /* FCMLT (zero) */ | |
10462 | case 0x6c: /* FCMGE (zero) */ | |
10463 | case 0x6d: /* FCMLE (zero) */ | |
10464 | handle_2misc_fcmp_zero(s, opcode, true, u, true, size, rn, rd); | |
10465 | return; | |
10113b69 AB |
10466 | case 0x1d: /* SCVTF */ |
10467 | case 0x5d: /* UCVTF */ | |
10468 | { | |
10469 | bool is_signed = (opcode == 0x1d); | |
8c6afa6a PM |
10470 | if (!fp_access_check(s)) { |
10471 | return; | |
10472 | } | |
10113b69 AB |
10473 | handle_simd_intfp_conv(s, rd, rn, 1, is_signed, 0, size); |
10474 | return; | |
10475 | } | |
b6d4443a | 10476 | case 0x3d: /* FRECPE */ |
8f0c6758 | 10477 | case 0x3f: /* FRECPX */ |
c2fb418e | 10478 | case 0x7d: /* FRSQRTE */ |
8c6afa6a PM |
10479 | if (!fp_access_check(s)) { |
10480 | return; | |
10481 | } | |
8f0c6758 AB |
10482 | handle_2misc_reciprocal(s, opcode, true, u, true, size, rn, rd); |
10483 | return; | |
8908f4d1 AB |
10484 | case 0x1a: /* FCVTNS */ |
10485 | case 0x1b: /* FCVTMS */ | |
8908f4d1 AB |
10486 | case 0x3a: /* FCVTPS */ |
10487 | case 0x3b: /* FCVTZS */ | |
8908f4d1 AB |
10488 | case 0x5a: /* FCVTNU */ |
10489 | case 0x5b: /* FCVTMU */ | |
8908f4d1 AB |
10490 | case 0x7a: /* FCVTPU */ |
10491 | case 0x7b: /* FCVTZU */ | |
04c7c6c2 PM |
10492 | is_fcvt = true; |
10493 | rmode = extract32(opcode, 5, 1) | (extract32(opcode, 0, 1) << 1); | |
10494 | break; | |
10495 | case 0x1c: /* FCVTAS */ | |
10496 | case 0x5c: /* FCVTAU */ | |
10497 | /* TIEAWAY doesn't fit in the usual rounding mode encoding */ | |
10498 | is_fcvt = true; | |
10499 | rmode = FPROUNDING_TIEAWAY; | |
10500 | break; | |
04c7c6c2 | 10501 | case 0x56: /* FCVTXN, FCVTXN2 */ |
5553955e PM |
10502 | if (size == 2) { |
10503 | unallocated_encoding(s); | |
10504 | return; | |
10505 | } | |
8c6afa6a PM |
10506 | if (!fp_access_check(s)) { |
10507 | return; | |
10508 | } | |
5553955e PM |
10509 | handle_2misc_narrow(s, true, opcode, u, false, size - 1, rn, rd); |
10510 | return; | |
8908f4d1 AB |
10511 | default: |
10512 | unallocated_encoding(s); | |
10513 | return; | |
10514 | } | |
10515 | break; | |
effa8e06 | 10516 | default: |
09e03735 | 10517 | unallocated_encoding(s); |
effa8e06 PM |
10518 | return; |
10519 | } | |
10520 | ||
8c6afa6a PM |
10521 | if (!fp_access_check(s)) { |
10522 | return; | |
10523 | } | |
10524 | ||
04c7c6c2 PM |
10525 | if (is_fcvt) { |
10526 | tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode)); | |
d81ce0ef | 10527 | tcg_fpstatus = get_fpstatus_ptr(false); |
9b049916 | 10528 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); |
04c7c6c2 | 10529 | } else { |
f764718d RH |
10530 | tcg_rmode = NULL; |
10531 | tcg_fpstatus = NULL; | |
04c7c6c2 PM |
10532 | } |
10533 | ||
effa8e06 PM |
10534 | if (size == 3) { |
10535 | TCGv_i64 tcg_rn = read_fp_dreg(s, rn); | |
10536 | TCGv_i64 tcg_rd = tcg_temp_new_i64(); | |
10537 | ||
04c7c6c2 | 10538 | handle_2misc_64(s, opcode, u, tcg_rd, tcg_rn, tcg_rmode, tcg_fpstatus); |
effa8e06 PM |
10539 | write_fp_dreg(s, rd, tcg_rd); |
10540 | tcg_temp_free_i64(tcg_rd); | |
10541 | tcg_temp_free_i64(tcg_rn); | |
0a79bc87 AB |
10542 | } else { |
10543 | TCGv_i32 tcg_rn = tcg_temp_new_i32(); | |
04c7c6c2 PM |
10544 | TCGv_i32 tcg_rd = tcg_temp_new_i32(); |
10545 | ||
0a79bc87 AB |
10546 | read_vec_element_i32(s, tcg_rn, rn, 0, size); |
10547 | ||
04c7c6c2 | 10548 | switch (opcode) { |
0a79bc87 AB |
10549 | case 0x7: /* SQABS, SQNEG */ |
10550 | { | |
10551 | NeonGenOneOpEnvFn *genfn; | |
10552 | static NeonGenOneOpEnvFn * const fns[3][2] = { | |
10553 | { gen_helper_neon_qabs_s8, gen_helper_neon_qneg_s8 }, | |
10554 | { gen_helper_neon_qabs_s16, gen_helper_neon_qneg_s16 }, | |
10555 | { gen_helper_neon_qabs_s32, gen_helper_neon_qneg_s32 }, | |
10556 | }; | |
10557 | genfn = fns[size][u]; | |
10558 | genfn(tcg_rd, cpu_env, tcg_rn); | |
10559 | break; | |
10560 | } | |
04c7c6c2 PM |
10561 | case 0x1a: /* FCVTNS */ |
10562 | case 0x1b: /* FCVTMS */ | |
10563 | case 0x1c: /* FCVTAS */ | |
10564 | case 0x3a: /* FCVTPS */ | |
10565 | case 0x3b: /* FCVTZS */ | |
10566 | { | |
10567 | TCGv_i32 tcg_shift = tcg_const_i32(0); | |
10568 | gen_helper_vfp_tosls(tcg_rd, tcg_rn, tcg_shift, tcg_fpstatus); | |
10569 | tcg_temp_free_i32(tcg_shift); | |
10570 | break; | |
10571 | } | |
10572 | case 0x5a: /* FCVTNU */ | |
10573 | case 0x5b: /* FCVTMU */ | |
10574 | case 0x5c: /* FCVTAU */ | |
10575 | case 0x7a: /* FCVTPU */ | |
10576 | case 0x7b: /* FCVTZU */ | |
10577 | { | |
10578 | TCGv_i32 tcg_shift = tcg_const_i32(0); | |
10579 | gen_helper_vfp_touls(tcg_rd, tcg_rn, tcg_shift, tcg_fpstatus); | |
10580 | tcg_temp_free_i32(tcg_shift); | |
10581 | break; | |
10582 | } | |
10583 | default: | |
10584 | g_assert_not_reached(); | |
10585 | } | |
10586 | ||
10587 | write_fp_sreg(s, rd, tcg_rd); | |
10588 | tcg_temp_free_i32(tcg_rd); | |
10589 | tcg_temp_free_i32(tcg_rn); | |
effa8e06 | 10590 | } |
04c7c6c2 PM |
10591 | |
10592 | if (is_fcvt) { | |
9b049916 | 10593 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); |
04c7c6c2 PM |
10594 | tcg_temp_free_i32(tcg_rmode); |
10595 | tcg_temp_free_ptr(tcg_fpstatus); | |
10596 | } | |
384b26fb AB |
10597 | } |
10598 | ||
4d1cef84 AB |
10599 | /* SSHR[RA]/USHR[RA] - Vector shift right (optional rounding/accumulate) */ |
10600 | static void handle_vec_simd_shri(DisasContext *s, bool is_q, bool is_u, | |
10601 | int immh, int immb, int opcode, int rn, int rd) | |
10602 | { | |
10603 | int size = 32 - clz32(immh) - 1; | |
10604 | int immhb = immh << 3 | immb; | |
10605 | int shift = 2 * (8 << size) - immhb; | |
3f08f0bc | 10606 | GVecGen2iFn *gvec_fn; |
4d1cef84 AB |
10607 | |
10608 | if (extract32(immh, 3, 1) && !is_q) { | |
10609 | unallocated_encoding(s); | |
10610 | return; | |
10611 | } | |
8dae4697 | 10612 | tcg_debug_assert(size <= 3); |
4d1cef84 | 10613 | |
8c6afa6a PM |
10614 | if (!fp_access_check(s)) { |
10615 | return; | |
10616 | } | |
10617 | ||
4d1cef84 AB |
10618 | switch (opcode) { |
10619 | case 0x02: /* SSRA / USRA (accumulate) */ | |
3f08f0bc RH |
10620 | gvec_fn = is_u ? gen_gvec_usra : gen_gvec_ssra; |
10621 | break; | |
893ab054 | 10622 | |
cdb45a60 | 10623 | case 0x08: /* SRI */ |
3f08f0bc RH |
10624 | gvec_fn = gen_gvec_sri; |
10625 | break; | |
cdb45a60 RH |
10626 | |
10627 | case 0x00: /* SSHR / USHR */ | |
10628 | if (is_u) { | |
10629 | if (shift == 8 << size) { | |
10630 | /* Shift count the same size as element size produces zero. */ | |
8711e71f RH |
10631 | tcg_gen_gvec_dup_imm(size, vec_full_reg_offset(s, rd), |
10632 | is_q ? 16 : 8, vec_full_reg_size(s), 0); | |
3f08f0bc | 10633 | return; |
cdb45a60 | 10634 | } |
3f08f0bc | 10635 | gvec_fn = tcg_gen_gvec_shri; |
cdb45a60 RH |
10636 | } else { |
10637 | /* Shift count the same size as element size produces all sign. */ | |
10638 | if (shift == 8 << size) { | |
10639 | shift -= 1; | |
10640 | } | |
3f08f0bc | 10641 | gvec_fn = tcg_gen_gvec_sari; |
cdb45a60 | 10642 | } |
3f08f0bc | 10643 | break; |
cdb45a60 | 10644 | |
4d1cef84 | 10645 | case 0x04: /* SRSHR / URSHR (rounding) */ |
3f08f0bc RH |
10646 | gvec_fn = is_u ? gen_gvec_urshr : gen_gvec_srshr; |
10647 | break; | |
6ccd48d4 | 10648 | |
4d1cef84 | 10649 | case 0x06: /* SRSRA / URSRA (accum + rounding) */ |
3f08f0bc RH |
10650 | gvec_fn = is_u ? gen_gvec_ursra : gen_gvec_srsra; |
10651 | break; | |
6ccd48d4 | 10652 | |
cdb45a60 RH |
10653 | default: |
10654 | g_assert_not_reached(); | |
4d1cef84 AB |
10655 | } |
10656 | ||
3f08f0bc | 10657 | gen_gvec_fn2i(s, is_q, rd, rn, shift, gvec_fn, size); |
cdb45a60 | 10658 | } |
4d1cef84 | 10659 | |
4d1cef84 AB |
10660 | /* SHL/SLI - Vector shift left */ |
10661 | static void handle_vec_simd_shli(DisasContext *s, bool is_q, bool insert, | |
cdb45a60 | 10662 | int immh, int immb, int opcode, int rn, int rd) |
4d1cef84 AB |
10663 | { |
10664 | int size = 32 - clz32(immh) - 1; | |
10665 | int immhb = immh << 3 | immb; | |
10666 | int shift = immhb - (8 << size); | |
4d1cef84 | 10667 | |
f6c98f91 PM |
10668 | /* Range of size is limited by decode: immh is a non-zero 4 bit field */ |
10669 | assert(size >= 0 && size <= 3); | |
4d1cef84 | 10670 | |
f6c98f91 | 10671 | if (extract32(immh, 3, 1) && !is_q) { |
4d1cef84 AB |
10672 | unallocated_encoding(s); |
10673 | return; | |
10674 | } | |
10675 | ||
8c6afa6a PM |
10676 | if (!fp_access_check(s)) { |
10677 | return; | |
10678 | } | |
10679 | ||
cdb45a60 | 10680 | if (insert) { |
893ab054 | 10681 | gen_gvec_fn2i(s, is_q, rd, rn, shift, gen_gvec_sli, size); |
cdb45a60 RH |
10682 | } else { |
10683 | gen_gvec_fn2i(s, is_q, rd, rn, shift, tcg_gen_gvec_shli, size); | |
4d1cef84 AB |
10684 | } |
10685 | } | |
10686 | ||
10687 | /* USHLL/SHLL - Vector shift left with widening */ | |
10688 | static void handle_vec_simd_wshli(DisasContext *s, bool is_q, bool is_u, | |
10689 | int immh, int immb, int opcode, int rn, int rd) | |
10690 | { | |
10691 | int size = 32 - clz32(immh) - 1; | |
10692 | int immhb = immh << 3 | immb; | |
10693 | int shift = immhb - (8 << size); | |
10694 | int dsize = 64; | |
10695 | int esize = 8 << size; | |
10696 | int elements = dsize/esize; | |
10697 | TCGv_i64 tcg_rn = new_tmp_a64(s); | |
10698 | TCGv_i64 tcg_rd = new_tmp_a64(s); | |
10699 | int i; | |
10700 | ||
10701 | if (size >= 3) { | |
10702 | unallocated_encoding(s); | |
10703 | return; | |
10704 | } | |
10705 | ||
8c6afa6a PM |
10706 | if (!fp_access_check(s)) { |
10707 | return; | |
10708 | } | |
10709 | ||
4d1cef84 AB |
10710 | /* For the LL variants the store is larger than the load, |
10711 | * so if rd == rn we would overwrite parts of our input. | |
10712 | * So load everything right now and use shifts in the main loop. | |
10713 | */ | |
10714 | read_vec_element(s, tcg_rn, rn, is_q ? 1 : 0, MO_64); | |
10715 | ||
10716 | for (i = 0; i < elements; i++) { | |
10717 | tcg_gen_shri_i64(tcg_rd, tcg_rn, i * esize); | |
10718 | ext_and_shift_reg(tcg_rd, tcg_rd, size | (!is_u << 2), 0); | |
10719 | tcg_gen_shli_i64(tcg_rd, tcg_rd, shift); | |
10720 | write_vec_element(s, tcg_rd, rd, i, size + 1); | |
10721 | } | |
10722 | } | |
10723 | ||
c1b876b2 AB |
10724 | /* SHRN/RSHRN - Shift right with narrowing (and potential rounding) */ |
10725 | static void handle_vec_simd_shrn(DisasContext *s, bool is_q, | |
10726 | int immh, int immb, int opcode, int rn, int rd) | |
10727 | { | |
10728 | int immhb = immh << 3 | immb; | |
10729 | int size = 32 - clz32(immh) - 1; | |
10730 | int dsize = 64; | |
10731 | int esize = 8 << size; | |
10732 | int elements = dsize/esize; | |
10733 | int shift = (2 * esize) - immhb; | |
10734 | bool round = extract32(opcode, 0, 1); | |
10735 | TCGv_i64 tcg_rn, tcg_rd, tcg_final; | |
10736 | TCGv_i64 tcg_round; | |
10737 | int i; | |
10738 | ||
10739 | if (extract32(immh, 3, 1)) { | |
10740 | unallocated_encoding(s); | |
10741 | return; | |
10742 | } | |
10743 | ||
8c6afa6a PM |
10744 | if (!fp_access_check(s)) { |
10745 | return; | |
10746 | } | |
10747 | ||
c1b876b2 AB |
10748 | tcg_rn = tcg_temp_new_i64(); |
10749 | tcg_rd = tcg_temp_new_i64(); | |
10750 | tcg_final = tcg_temp_new_i64(); | |
10751 | read_vec_element(s, tcg_final, rd, is_q ? 1 : 0, MO_64); | |
10752 | ||
10753 | if (round) { | |
10754 | uint64_t round_const = 1ULL << (shift - 1); | |
10755 | tcg_round = tcg_const_i64(round_const); | |
10756 | } else { | |
f764718d | 10757 | tcg_round = NULL; |
c1b876b2 AB |
10758 | } |
10759 | ||
10760 | for (i = 0; i < elements; i++) { | |
10761 | read_vec_element(s, tcg_rn, rn, i, size+1); | |
10762 | handle_shri_with_rndacc(tcg_rd, tcg_rn, tcg_round, | |
10763 | false, true, size+1, shift); | |
10764 | ||
10765 | tcg_gen_deposit_i64(tcg_final, tcg_final, tcg_rd, esize * i, esize); | |
10766 | } | |
10767 | ||
10768 | if (!is_q) { | |
c1b876b2 AB |
10769 | write_vec_element(s, tcg_final, rd, 0, MO_64); |
10770 | } else { | |
10771 | write_vec_element(s, tcg_final, rd, 1, MO_64); | |
10772 | } | |
c1b876b2 AB |
10773 | if (round) { |
10774 | tcg_temp_free_i64(tcg_round); | |
10775 | } | |
10776 | tcg_temp_free_i64(tcg_rn); | |
10777 | tcg_temp_free_i64(tcg_rd); | |
10778 | tcg_temp_free_i64(tcg_final); | |
4ff55bcb RH |
10779 | |
10780 | clear_vec_high(s, is_q, rd); | |
c1b876b2 AB |
10781 | } |
10782 | ||
10783 | ||
4ce31af4 | 10784 | /* AdvSIMD shift by immediate |
384b26fb AB |
10785 | * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0 |
10786 | * +---+---+---+-------------+------+------+--------+---+------+------+ | |
10787 | * | 0 | Q | U | 0 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd | | |
10788 | * +---+---+---+-------------+------+------+--------+---+------+------+ | |
10789 | */ | |
10790 | static void disas_simd_shift_imm(DisasContext *s, uint32_t insn) | |
10791 | { | |
4d1cef84 AB |
10792 | int rd = extract32(insn, 0, 5); |
10793 | int rn = extract32(insn, 5, 5); | |
10794 | int opcode = extract32(insn, 11, 5); | |
10795 | int immb = extract32(insn, 16, 3); | |
10796 | int immh = extract32(insn, 19, 4); | |
10797 | bool is_u = extract32(insn, 29, 1); | |
10798 | bool is_q = extract32(insn, 30, 1); | |
10799 | ||
3944d58d RH |
10800 | /* data_proc_simd[] has sent immh == 0 to disas_simd_mod_imm. */ |
10801 | assert(immh != 0); | |
10802 | ||
4d1cef84 | 10803 | switch (opcode) { |
37a706ad PM |
10804 | case 0x08: /* SRI */ |
10805 | if (!is_u) { | |
10806 | unallocated_encoding(s); | |
10807 | return; | |
10808 | } | |
10809 | /* fall through */ | |
4d1cef84 AB |
10810 | case 0x00: /* SSHR / USHR */ |
10811 | case 0x02: /* SSRA / USRA (accumulate) */ | |
10812 | case 0x04: /* SRSHR / URSHR (rounding) */ | |
10813 | case 0x06: /* SRSRA / URSRA (accum + rounding) */ | |
10814 | handle_vec_simd_shri(s, is_q, is_u, immh, immb, opcode, rn, rd); | |
10815 | break; | |
10816 | case 0x0a: /* SHL / SLI */ | |
10817 | handle_vec_simd_shli(s, is_q, is_u, immh, immb, opcode, rn, rd); | |
10818 | break; | |
c1b876b2 AB |
10819 | case 0x10: /* SHRN */ |
10820 | case 0x11: /* RSHRN / SQRSHRUN */ | |
10821 | if (is_u) { | |
10822 | handle_vec_simd_sqshrn(s, false, is_q, false, true, immh, immb, | |
10823 | opcode, rn, rd); | |
10824 | } else { | |
10825 | handle_vec_simd_shrn(s, is_q, immh, immb, opcode, rn, rd); | |
10826 | } | |
10827 | break; | |
10828 | case 0x12: /* SQSHRN / UQSHRN */ | |
10829 | case 0x13: /* SQRSHRN / UQRSHRN */ | |
10830 | handle_vec_simd_sqshrn(s, false, is_q, is_u, is_u, immh, immb, | |
10831 | opcode, rn, rd); | |
10832 | break; | |
4d1cef84 AB |
10833 | case 0x14: /* SSHLL / USHLL */ |
10834 | handle_vec_simd_wshli(s, is_q, is_u, immh, immb, opcode, rn, rd); | |
10835 | break; | |
10113b69 AB |
10836 | case 0x1c: /* SCVTF / UCVTF */ |
10837 | handle_simd_shift_intfp_conv(s, false, is_q, is_u, immh, immb, | |
10838 | opcode, rn, rd); | |
10839 | break; | |
a566da1b | 10840 | case 0xc: /* SQSHLU */ |
a847f32c PM |
10841 | if (!is_u) { |
10842 | unallocated_encoding(s); | |
10843 | return; | |
10844 | } | |
10845 | handle_simd_qshl(s, false, is_q, false, true, immh, immb, rn, rd); | |
10846 | break; | |
a566da1b | 10847 | case 0xe: /* SQSHL, UQSHL */ |
a847f32c PM |
10848 | handle_simd_qshl(s, false, is_q, is_u, is_u, immh, immb, rn, rd); |
10849 | break; | |
10113b69 | 10850 | case 0x1f: /* FCVTZS/ FCVTZU */ |
2ed3ea11 | 10851 | handle_simd_shift_fpint_conv(s, false, is_q, is_u, immh, immb, rn, rd); |
10113b69 | 10852 | return; |
4d1cef84 | 10853 | default: |
a566da1b | 10854 | unallocated_encoding(s); |
4d1cef84 AB |
10855 | return; |
10856 | } | |
384b26fb AB |
10857 | } |
10858 | ||
70d7f984 PM |
10859 | /* Generate code to do a "long" addition or subtraction, ie one done in |
10860 | * TCGv_i64 on vector lanes twice the width specified by size. | |
10861 | */ | |
10862 | static void gen_neon_addl(int size, bool is_sub, TCGv_i64 tcg_res, | |
10863 | TCGv_i64 tcg_op1, TCGv_i64 tcg_op2) | |
10864 | { | |
10865 | static NeonGenTwo64OpFn * const fns[3][2] = { | |
10866 | { gen_helper_neon_addl_u16, gen_helper_neon_subl_u16 }, | |
10867 | { gen_helper_neon_addl_u32, gen_helper_neon_subl_u32 }, | |
10868 | { tcg_gen_add_i64, tcg_gen_sub_i64 }, | |
10869 | }; | |
10870 | NeonGenTwo64OpFn *genfn; | |
10871 | assert(size < 3); | |
10872 | ||
10873 | genfn = fns[size][is_sub]; | |
10874 | genfn(tcg_res, tcg_op1, tcg_op2); | |
10875 | } | |
10876 | ||
a08582f4 PM |
10877 | static void handle_3rd_widening(DisasContext *s, int is_q, int is_u, int size, |
10878 | int opcode, int rd, int rn, int rm) | |
10879 | { | |
10880 | /* 3-reg-different widening insns: 64 x 64 -> 128 */ | |
10881 | TCGv_i64 tcg_res[2]; | |
10882 | int pass, accop; | |
10883 | ||
10884 | tcg_res[0] = tcg_temp_new_i64(); | |
10885 | tcg_res[1] = tcg_temp_new_i64(); | |
10886 | ||
10887 | /* Does this op do an adding accumulate, a subtracting accumulate, | |
10888 | * or no accumulate at all? | |
10889 | */ | |
10890 | switch (opcode) { | |
10891 | case 5: | |
10892 | case 8: | |
10893 | case 9: | |
10894 | accop = 1; | |
10895 | break; | |
10896 | case 10: | |
10897 | case 11: | |
10898 | accop = -1; | |
10899 | break; | |
10900 | default: | |
10901 | accop = 0; | |
10902 | break; | |
10903 | } | |
10904 | ||
10905 | if (accop != 0) { | |
10906 | read_vec_element(s, tcg_res[0], rd, 0, MO_64); | |
10907 | read_vec_element(s, tcg_res[1], rd, 1, MO_64); | |
10908 | } | |
10909 | ||
10910 | /* size == 2 means two 32x32->64 operations; this is worth special | |
10911 | * casing because we can generally handle it inline. | |
10912 | */ | |
10913 | if (size == 2) { | |
10914 | for (pass = 0; pass < 2; pass++) { | |
10915 | TCGv_i64 tcg_op1 = tcg_temp_new_i64(); | |
10916 | TCGv_i64 tcg_op2 = tcg_temp_new_i64(); | |
10917 | TCGv_i64 tcg_passres; | |
14776ab5 | 10918 | MemOp memop = MO_32 | (is_u ? 0 : MO_SIGN); |
a08582f4 PM |
10919 | |
10920 | int elt = pass + is_q * 2; | |
10921 | ||
10922 | read_vec_element(s, tcg_op1, rn, elt, memop); | |
10923 | read_vec_element(s, tcg_op2, rm, elt, memop); | |
10924 | ||
10925 | if (accop == 0) { | |
10926 | tcg_passres = tcg_res[pass]; | |
10927 | } else { | |
10928 | tcg_passres = tcg_temp_new_i64(); | |
10929 | } | |
10930 | ||
10931 | switch (opcode) { | |
70d7f984 PM |
10932 | case 0: /* SADDL, SADDL2, UADDL, UADDL2 */ |
10933 | tcg_gen_add_i64(tcg_passres, tcg_op1, tcg_op2); | |
10934 | break; | |
10935 | case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */ | |
10936 | tcg_gen_sub_i64(tcg_passres, tcg_op1, tcg_op2); | |
10937 | break; | |
0ae39320 PM |
10938 | case 5: /* SABAL, SABAL2, UABAL, UABAL2 */ |
10939 | case 7: /* SABDL, SABDL2, UABDL, UABDL2 */ | |
10940 | { | |
10941 | TCGv_i64 tcg_tmp1 = tcg_temp_new_i64(); | |
10942 | TCGv_i64 tcg_tmp2 = tcg_temp_new_i64(); | |
10943 | ||
10944 | tcg_gen_sub_i64(tcg_tmp1, tcg_op1, tcg_op2); | |
10945 | tcg_gen_sub_i64(tcg_tmp2, tcg_op2, tcg_op1); | |
10946 | tcg_gen_movcond_i64(is_u ? TCG_COND_GEU : TCG_COND_GE, | |
10947 | tcg_passres, | |
10948 | tcg_op1, tcg_op2, tcg_tmp1, tcg_tmp2); | |
10949 | tcg_temp_free_i64(tcg_tmp1); | |
10950 | tcg_temp_free_i64(tcg_tmp2); | |
10951 | break; | |
10952 | } | |
a08582f4 PM |
10953 | case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */ |
10954 | case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */ | |
10955 | case 12: /* UMULL, UMULL2, SMULL, SMULL2 */ | |
10956 | tcg_gen_mul_i64(tcg_passres, tcg_op1, tcg_op2); | |
10957 | break; | |
70d7f984 PM |
10958 | case 9: /* SQDMLAL, SQDMLAL2 */ |
10959 | case 11: /* SQDMLSL, SQDMLSL2 */ | |
10960 | case 13: /* SQDMULL, SQDMULL2 */ | |
10961 | tcg_gen_mul_i64(tcg_passres, tcg_op1, tcg_op2); | |
10962 | gen_helper_neon_addl_saturate_s64(tcg_passres, cpu_env, | |
10963 | tcg_passres, tcg_passres); | |
10964 | break; | |
a08582f4 PM |
10965 | default: |
10966 | g_assert_not_reached(); | |
10967 | } | |
10968 | ||
70d7f984 PM |
10969 | if (opcode == 9 || opcode == 11) { |
10970 | /* saturating accumulate ops */ | |
10971 | if (accop < 0) { | |
10972 | tcg_gen_neg_i64(tcg_passres, tcg_passres); | |
10973 | } | |
10974 | gen_helper_neon_addl_saturate_s64(tcg_res[pass], cpu_env, | |
10975 | tcg_res[pass], tcg_passres); | |
10976 | } else if (accop > 0) { | |
a08582f4 | 10977 | tcg_gen_add_i64(tcg_res[pass], tcg_res[pass], tcg_passres); |
a08582f4 PM |
10978 | } else if (accop < 0) { |
10979 | tcg_gen_sub_i64(tcg_res[pass], tcg_res[pass], tcg_passres); | |
70d7f984 PM |
10980 | } |
10981 | ||
10982 | if (accop != 0) { | |
a08582f4 PM |
10983 | tcg_temp_free_i64(tcg_passres); |
10984 | } | |
10985 | ||
10986 | tcg_temp_free_i64(tcg_op1); | |
10987 | tcg_temp_free_i64(tcg_op2); | |
10988 | } | |
10989 | } else { | |
10990 | /* size 0 or 1, generally helper functions */ | |
10991 | for (pass = 0; pass < 2; pass++) { | |
10992 | TCGv_i32 tcg_op1 = tcg_temp_new_i32(); | |
10993 | TCGv_i32 tcg_op2 = tcg_temp_new_i32(); | |
10994 | TCGv_i64 tcg_passres; | |
10995 | int elt = pass + is_q * 2; | |
10996 | ||
10997 | read_vec_element_i32(s, tcg_op1, rn, elt, MO_32); | |
10998 | read_vec_element_i32(s, tcg_op2, rm, elt, MO_32); | |
10999 | ||
11000 | if (accop == 0) { | |
11001 | tcg_passres = tcg_res[pass]; | |
11002 | } else { | |
11003 | tcg_passres = tcg_temp_new_i64(); | |
11004 | } | |
11005 | ||
11006 | switch (opcode) { | |
70d7f984 PM |
11007 | case 0: /* SADDL, SADDL2, UADDL, UADDL2 */ |
11008 | case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */ | |
11009 | { | |
11010 | TCGv_i64 tcg_op2_64 = tcg_temp_new_i64(); | |
11011 | static NeonGenWidenFn * const widenfns[2][2] = { | |
11012 | { gen_helper_neon_widen_s8, gen_helper_neon_widen_u8 }, | |
11013 | { gen_helper_neon_widen_s16, gen_helper_neon_widen_u16 }, | |
11014 | }; | |
11015 | NeonGenWidenFn *widenfn = widenfns[size][is_u]; | |
11016 | ||
11017 | widenfn(tcg_op2_64, tcg_op2); | |
11018 | widenfn(tcg_passres, tcg_op1); | |
11019 | gen_neon_addl(size, (opcode == 2), tcg_passres, | |
11020 | tcg_passres, tcg_op2_64); | |
11021 | tcg_temp_free_i64(tcg_op2_64); | |
11022 | break; | |
11023 | } | |
0ae39320 PM |
11024 | case 5: /* SABAL, SABAL2, UABAL, UABAL2 */ |
11025 | case 7: /* SABDL, SABDL2, UABDL, UABDL2 */ | |
11026 | if (size == 0) { | |
11027 | if (is_u) { | |
11028 | gen_helper_neon_abdl_u16(tcg_passres, tcg_op1, tcg_op2); | |
11029 | } else { | |
11030 | gen_helper_neon_abdl_s16(tcg_passres, tcg_op1, tcg_op2); | |
11031 | } | |
11032 | } else { | |
11033 | if (is_u) { | |
11034 | gen_helper_neon_abdl_u32(tcg_passres, tcg_op1, tcg_op2); | |
11035 | } else { | |
11036 | gen_helper_neon_abdl_s32(tcg_passres, tcg_op1, tcg_op2); | |
11037 | } | |
11038 | } | |
11039 | break; | |
a08582f4 PM |
11040 | case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */ |
11041 | case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */ | |
11042 | case 12: /* UMULL, UMULL2, SMULL, SMULL2 */ | |
11043 | if (size == 0) { | |
11044 | if (is_u) { | |
11045 | gen_helper_neon_mull_u8(tcg_passres, tcg_op1, tcg_op2); | |
11046 | } else { | |
11047 | gen_helper_neon_mull_s8(tcg_passres, tcg_op1, tcg_op2); | |
11048 | } | |
11049 | } else { | |
11050 | if (is_u) { | |
11051 | gen_helper_neon_mull_u16(tcg_passres, tcg_op1, tcg_op2); | |
11052 | } else { | |
11053 | gen_helper_neon_mull_s16(tcg_passres, tcg_op1, tcg_op2); | |
11054 | } | |
11055 | } | |
11056 | break; | |
70d7f984 PM |
11057 | case 9: /* SQDMLAL, SQDMLAL2 */ |
11058 | case 11: /* SQDMLSL, SQDMLSL2 */ | |
11059 | case 13: /* SQDMULL, SQDMULL2 */ | |
11060 | assert(size == 1); | |
11061 | gen_helper_neon_mull_s16(tcg_passres, tcg_op1, tcg_op2); | |
11062 | gen_helper_neon_addl_saturate_s32(tcg_passres, cpu_env, | |
11063 | tcg_passres, tcg_passres); | |
11064 | break; | |
a08582f4 PM |
11065 | default: |
11066 | g_assert_not_reached(); | |
11067 | } | |
11068 | tcg_temp_free_i32(tcg_op1); | |
11069 | tcg_temp_free_i32(tcg_op2); | |
11070 | ||
70d7f984 PM |
11071 | if (accop != 0) { |
11072 | if (opcode == 9 || opcode == 11) { | |
11073 | /* saturating accumulate ops */ | |
11074 | if (accop < 0) { | |
11075 | gen_helper_neon_negl_u32(tcg_passres, tcg_passres); | |
11076 | } | |
11077 | gen_helper_neon_addl_saturate_s32(tcg_res[pass], cpu_env, | |
11078 | tcg_res[pass], | |
11079 | tcg_passres); | |
a08582f4 | 11080 | } else { |
70d7f984 PM |
11081 | gen_neon_addl(size, (accop < 0), tcg_res[pass], |
11082 | tcg_res[pass], tcg_passres); | |
a08582f4 PM |
11083 | } |
11084 | tcg_temp_free_i64(tcg_passres); | |
11085 | } | |
11086 | } | |
11087 | } | |
11088 | ||
11089 | write_vec_element(s, tcg_res[0], rd, 0, MO_64); | |
11090 | write_vec_element(s, tcg_res[1], rd, 1, MO_64); | |
11091 | tcg_temp_free_i64(tcg_res[0]); | |
11092 | tcg_temp_free_i64(tcg_res[1]); | |
11093 | } | |
11094 | ||
dfc15c7c PM |
11095 | static void handle_3rd_wide(DisasContext *s, int is_q, int is_u, int size, |
11096 | int opcode, int rd, int rn, int rm) | |
11097 | { | |
11098 | TCGv_i64 tcg_res[2]; | |
11099 | int part = is_q ? 2 : 0; | |
11100 | int pass; | |
11101 | ||
11102 | for (pass = 0; pass < 2; pass++) { | |
11103 | TCGv_i64 tcg_op1 = tcg_temp_new_i64(); | |
11104 | TCGv_i32 tcg_op2 = tcg_temp_new_i32(); | |
11105 | TCGv_i64 tcg_op2_wide = tcg_temp_new_i64(); | |
11106 | static NeonGenWidenFn * const widenfns[3][2] = { | |
11107 | { gen_helper_neon_widen_s8, gen_helper_neon_widen_u8 }, | |
11108 | { gen_helper_neon_widen_s16, gen_helper_neon_widen_u16 }, | |
11109 | { tcg_gen_ext_i32_i64, tcg_gen_extu_i32_i64 }, | |
11110 | }; | |
11111 | NeonGenWidenFn *widenfn = widenfns[size][is_u]; | |
11112 | ||
11113 | read_vec_element(s, tcg_op1, rn, pass, MO_64); | |
11114 | read_vec_element_i32(s, tcg_op2, rm, part + pass, MO_32); | |
11115 | widenfn(tcg_op2_wide, tcg_op2); | |
11116 | tcg_temp_free_i32(tcg_op2); | |
11117 | tcg_res[pass] = tcg_temp_new_i64(); | |
11118 | gen_neon_addl(size, (opcode == 3), | |
11119 | tcg_res[pass], tcg_op1, tcg_op2_wide); | |
11120 | tcg_temp_free_i64(tcg_op1); | |
11121 | tcg_temp_free_i64(tcg_op2_wide); | |
11122 | } | |
11123 | ||
11124 | for (pass = 0; pass < 2; pass++) { | |
11125 | write_vec_element(s, tcg_res[pass], rd, pass, MO_64); | |
11126 | tcg_temp_free_i64(tcg_res[pass]); | |
11127 | } | |
11128 | } | |
11129 | ||
e4b998d4 PM |
11130 | static void do_narrow_round_high_u32(TCGv_i32 res, TCGv_i64 in) |
11131 | { | |
11132 | tcg_gen_addi_i64(in, in, 1U << 31); | |
7cb36e18 | 11133 | tcg_gen_extrh_i64_i32(res, in); |
e4b998d4 PM |
11134 | } |
11135 | ||
11136 | static void handle_3rd_narrowing(DisasContext *s, int is_q, int is_u, int size, | |
11137 | int opcode, int rd, int rn, int rm) | |
11138 | { | |
11139 | TCGv_i32 tcg_res[2]; | |
11140 | int part = is_q ? 2 : 0; | |
11141 | int pass; | |
11142 | ||
11143 | for (pass = 0; pass < 2; pass++) { | |
11144 | TCGv_i64 tcg_op1 = tcg_temp_new_i64(); | |
11145 | TCGv_i64 tcg_op2 = tcg_temp_new_i64(); | |
11146 | TCGv_i64 tcg_wideres = tcg_temp_new_i64(); | |
11147 | static NeonGenNarrowFn * const narrowfns[3][2] = { | |
11148 | { gen_helper_neon_narrow_high_u8, | |
11149 | gen_helper_neon_narrow_round_high_u8 }, | |
11150 | { gen_helper_neon_narrow_high_u16, | |
11151 | gen_helper_neon_narrow_round_high_u16 }, | |
7cb36e18 | 11152 | { tcg_gen_extrh_i64_i32, do_narrow_round_high_u32 }, |
e4b998d4 PM |
11153 | }; |
11154 | NeonGenNarrowFn *gennarrow = narrowfns[size][is_u]; | |
11155 | ||
11156 | read_vec_element(s, tcg_op1, rn, pass, MO_64); | |
11157 | read_vec_element(s, tcg_op2, rm, pass, MO_64); | |
11158 | ||
11159 | gen_neon_addl(size, (opcode == 6), tcg_wideres, tcg_op1, tcg_op2); | |
11160 | ||
11161 | tcg_temp_free_i64(tcg_op1); | |
11162 | tcg_temp_free_i64(tcg_op2); | |
11163 | ||
11164 | tcg_res[pass] = tcg_temp_new_i32(); | |
11165 | gennarrow(tcg_res[pass], tcg_wideres); | |
11166 | tcg_temp_free_i64(tcg_wideres); | |
11167 | } | |
11168 | ||
11169 | for (pass = 0; pass < 2; pass++) { | |
11170 | write_vec_element_i32(s, tcg_res[pass], rd, pass + part, MO_32); | |
11171 | tcg_temp_free_i32(tcg_res[pass]); | |
11172 | } | |
4ff55bcb | 11173 | clear_vec_high(s, is_q, rd); |
e4b998d4 PM |
11174 | } |
11175 | ||
4ce31af4 | 11176 | /* AdvSIMD three different |
384b26fb AB |
11177 | * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0 |
11178 | * +---+---+---+-----------+------+---+------+--------+-----+------+------+ | |
11179 | * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd | | |
11180 | * +---+---+---+-----------+------+---+------+--------+-----+------+------+ | |
11181 | */ | |
11182 | static void disas_simd_three_reg_diff(DisasContext *s, uint32_t insn) | |
11183 | { | |
a08582f4 PM |
11184 | /* Instructions in this group fall into three basic classes |
11185 | * (in each case with the operation working on each element in | |
11186 | * the input vectors): | |
11187 | * (1) widening 64 x 64 -> 128 (with possibly Vd as an extra | |
11188 | * 128 bit input) | |
11189 | * (2) wide 64 x 128 -> 128 | |
11190 | * (3) narrowing 128 x 128 -> 64 | |
11191 | * Here we do initial decode, catch unallocated cases and | |
11192 | * dispatch to separate functions for each class. | |
11193 | */ | |
11194 | int is_q = extract32(insn, 30, 1); | |
11195 | int is_u = extract32(insn, 29, 1); | |
11196 | int size = extract32(insn, 22, 2); | |
11197 | int opcode = extract32(insn, 12, 4); | |
11198 | int rm = extract32(insn, 16, 5); | |
11199 | int rn = extract32(insn, 5, 5); | |
11200 | int rd = extract32(insn, 0, 5); | |
11201 | ||
11202 | switch (opcode) { | |
11203 | case 1: /* SADDW, SADDW2, UADDW, UADDW2 */ | |
11204 | case 3: /* SSUBW, SSUBW2, USUBW, USUBW2 */ | |
11205 | /* 64 x 128 -> 128 */ | |
dfc15c7c PM |
11206 | if (size == 3) { |
11207 | unallocated_encoding(s); | |
11208 | return; | |
11209 | } | |
8c6afa6a PM |
11210 | if (!fp_access_check(s)) { |
11211 | return; | |
11212 | } | |
dfc15c7c | 11213 | handle_3rd_wide(s, is_q, is_u, size, opcode, rd, rn, rm); |
a08582f4 PM |
11214 | break; |
11215 | case 4: /* ADDHN, ADDHN2, RADDHN, RADDHN2 */ | |
11216 | case 6: /* SUBHN, SUBHN2, RSUBHN, RSUBHN2 */ | |
11217 | /* 128 x 128 -> 64 */ | |
e4b998d4 PM |
11218 | if (size == 3) { |
11219 | unallocated_encoding(s); | |
11220 | return; | |
11221 | } | |
8c6afa6a PM |
11222 | if (!fp_access_check(s)) { |
11223 | return; | |
11224 | } | |
e4b998d4 | 11225 | handle_3rd_narrowing(s, is_q, is_u, size, opcode, rd, rn, rm); |
a08582f4 | 11226 | break; |
70d7f984 | 11227 | case 14: /* PMULL, PMULL2 */ |
e7e96fc5 | 11228 | if (is_u) { |
70d7f984 PM |
11229 | unallocated_encoding(s); |
11230 | return; | |
11231 | } | |
e7e96fc5 RH |
11232 | switch (size) { |
11233 | case 0: /* PMULL.P8 */ | |
11234 | if (!fp_access_check(s)) { | |
11235 | return; | |
11236 | } | |
11237 | /* The Q field specifies lo/hi half input for this insn. */ | |
11238 | gen_gvec_op3_ool(s, true, rd, rn, rm, is_q, | |
11239 | gen_helper_neon_pmull_h); | |
11240 | break; | |
11241 | ||
11242 | case 3: /* PMULL.P64 */ | |
962fcbf2 | 11243 | if (!dc_isar_feature(aa64_pmull, s)) { |
a984e42c PM |
11244 | unallocated_encoding(s); |
11245 | return; | |
11246 | } | |
8c6afa6a PM |
11247 | if (!fp_access_check(s)) { |
11248 | return; | |
11249 | } | |
b9ed510e RH |
11250 | /* The Q field specifies lo/hi half input for this insn. */ |
11251 | gen_gvec_op3_ool(s, true, rd, rn, rm, is_q, | |
11252 | gen_helper_gvec_pmull_q); | |
e7e96fc5 RH |
11253 | break; |
11254 | ||
11255 | default: | |
11256 | unallocated_encoding(s); | |
11257 | break; | |
a984e42c | 11258 | } |
e7e96fc5 | 11259 | return; |
13caf1fd PM |
11260 | case 9: /* SQDMLAL, SQDMLAL2 */ |
11261 | case 11: /* SQDMLSL, SQDMLSL2 */ | |
11262 | case 13: /* SQDMULL, SQDMULL2 */ | |
70d7f984 | 11263 | if (is_u || size == 0) { |
a08582f4 PM |
11264 | unallocated_encoding(s); |
11265 | return; | |
11266 | } | |
11267 | /* fall through */ | |
13caf1fd PM |
11268 | case 0: /* SADDL, SADDL2, UADDL, UADDL2 */ |
11269 | case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */ | |
13caf1fd PM |
11270 | case 5: /* SABAL, SABAL2, UABAL, UABAL2 */ |
11271 | case 7: /* SABDL, SABDL2, UABDL, UABDL2 */ | |
11272 | case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */ | |
11273 | case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */ | |
11274 | case 12: /* SMULL, SMULL2, UMULL, UMULL2 */ | |
a08582f4 PM |
11275 | /* 64 x 64 -> 128 */ |
11276 | if (size == 3) { | |
11277 | unallocated_encoding(s); | |
11278 | return; | |
11279 | } | |
8c6afa6a PM |
11280 | if (!fp_access_check(s)) { |
11281 | return; | |
11282 | } | |
11283 | ||
a08582f4 PM |
11284 | handle_3rd_widening(s, is_q, is_u, size, opcode, rd, rn, rm); |
11285 | break; | |
11286 | default: | |
11287 | /* opcode 15 not allocated */ | |
11288 | unallocated_encoding(s); | |
11289 | break; | |
11290 | } | |
384b26fb AB |
11291 | } |
11292 | ||
e1cea114 PM |
11293 | /* Logic op (opcode == 3) subgroup of C3.6.16. */ |
11294 | static void disas_simd_3same_logic(DisasContext *s, uint32_t insn) | |
11295 | { | |
956d272e PM |
11296 | int rd = extract32(insn, 0, 5); |
11297 | int rn = extract32(insn, 5, 5); | |
11298 | int rm = extract32(insn, 16, 5); | |
11299 | int size = extract32(insn, 22, 2); | |
11300 | bool is_u = extract32(insn, 29, 1); | |
11301 | bool is_q = extract32(insn, 30, 1); | |
956d272e | 11302 | |
8c6afa6a PM |
11303 | if (!fp_access_check(s)) { |
11304 | return; | |
11305 | } | |
11306 | ||
bc48092f RH |
11307 | switch (size + 4 * is_u) { |
11308 | case 0: /* AND */ | |
11309 | gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_and, 0); | |
11310 | return; | |
11311 | case 1: /* BIC */ | |
11312 | gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_andc, 0); | |
11313 | return; | |
11314 | case 2: /* ORR */ | |
2900847f | 11315 | gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_or, 0); |
bc48092f RH |
11316 | return; |
11317 | case 3: /* ORN */ | |
11318 | gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_orc, 0); | |
11319 | return; | |
11320 | case 4: /* EOR */ | |
11321 | gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_xor, 0); | |
11322 | return; | |
956d272e | 11323 | |
bc48092f | 11324 | case 5: /* BSL bitwise select */ |
3a7a2b4e | 11325 | gen_gvec_fn4(s, is_q, rd, rd, rn, rm, tcg_gen_gvec_bitsel, 0); |
bc48092f RH |
11326 | return; |
11327 | case 6: /* BIT, bitwise insert if true */ | |
3a7a2b4e | 11328 | gen_gvec_fn4(s, is_q, rd, rm, rn, rd, tcg_gen_gvec_bitsel, 0); |
bc48092f RH |
11329 | return; |
11330 | case 7: /* BIF, bitwise insert if false */ | |
3a7a2b4e | 11331 | gen_gvec_fn4(s, is_q, rd, rm, rd, rn, tcg_gen_gvec_bitsel, 0); |
bc48092f | 11332 | return; |
956d272e | 11333 | |
bc48092f RH |
11334 | default: |
11335 | g_assert_not_reached(); | |
956d272e | 11336 | } |
e1cea114 PM |
11337 | } |
11338 | ||
bc242f9b AB |
11339 | /* Pairwise op subgroup of C3.6.16. |
11340 | * | |
11341 | * This is called directly or via the handle_3same_float for float pairwise | |
11342 | * operations where the opcode and size are calculated differently. | |
11343 | */ | |
11344 | static void handle_simd_3same_pair(DisasContext *s, int is_q, int u, int opcode, | |
11345 | int size, int rn, int rm, int rd) | |
e1cea114 | 11346 | { |
bc242f9b | 11347 | TCGv_ptr fpst; |
0173a005 PM |
11348 | int pass; |
11349 | ||
bc242f9b AB |
11350 | /* Floating point operations need fpst */ |
11351 | if (opcode >= 0x58) { | |
d81ce0ef | 11352 | fpst = get_fpstatus_ptr(false); |
bc242f9b | 11353 | } else { |
f764718d | 11354 | fpst = NULL; |
0173a005 PM |
11355 | } |
11356 | ||
8c6afa6a PM |
11357 | if (!fp_access_check(s)) { |
11358 | return; | |
11359 | } | |
11360 | ||
0173a005 PM |
11361 | /* These operations work on the concatenated rm:rn, with each pair of |
11362 | * adjacent elements being operated on to produce an element in the result. | |
11363 | */ | |
11364 | if (size == 3) { | |
11365 | TCGv_i64 tcg_res[2]; | |
11366 | ||
11367 | for (pass = 0; pass < 2; pass++) { | |
11368 | TCGv_i64 tcg_op1 = tcg_temp_new_i64(); | |
11369 | TCGv_i64 tcg_op2 = tcg_temp_new_i64(); | |
11370 | int passreg = (pass == 0) ? rn : rm; | |
11371 | ||
11372 | read_vec_element(s, tcg_op1, passreg, 0, MO_64); | |
11373 | read_vec_element(s, tcg_op2, passreg, 1, MO_64); | |
11374 | tcg_res[pass] = tcg_temp_new_i64(); | |
11375 | ||
bc242f9b AB |
11376 | switch (opcode) { |
11377 | case 0x17: /* ADDP */ | |
11378 | tcg_gen_add_i64(tcg_res[pass], tcg_op1, tcg_op2); | |
11379 | break; | |
11380 | case 0x58: /* FMAXNMP */ | |
11381 | gen_helper_vfp_maxnumd(tcg_res[pass], tcg_op1, tcg_op2, fpst); | |
11382 | break; | |
11383 | case 0x5a: /* FADDP */ | |
11384 | gen_helper_vfp_addd(tcg_res[pass], tcg_op1, tcg_op2, fpst); | |
11385 | break; | |
11386 | case 0x5e: /* FMAXP */ | |
11387 | gen_helper_vfp_maxd(tcg_res[pass], tcg_op1, tcg_op2, fpst); | |
11388 | break; | |
11389 | case 0x78: /* FMINNMP */ | |
11390 | gen_helper_vfp_minnumd(tcg_res[pass], tcg_op1, tcg_op2, fpst); | |
11391 | break; | |
11392 | case 0x7e: /* FMINP */ | |
11393 | gen_helper_vfp_mind(tcg_res[pass], tcg_op1, tcg_op2, fpst); | |
11394 | break; | |
11395 | default: | |
11396 | g_assert_not_reached(); | |
11397 | } | |
0173a005 PM |
11398 | |
11399 | tcg_temp_free_i64(tcg_op1); | |
11400 | tcg_temp_free_i64(tcg_op2); | |
11401 | } | |
11402 | ||
11403 | for (pass = 0; pass < 2; pass++) { | |
11404 | write_vec_element(s, tcg_res[pass], rd, pass, MO_64); | |
11405 | tcg_temp_free_i64(tcg_res[pass]); | |
11406 | } | |
11407 | } else { | |
11408 | int maxpass = is_q ? 4 : 2; | |
11409 | TCGv_i32 tcg_res[4]; | |
11410 | ||
11411 | for (pass = 0; pass < maxpass; pass++) { | |
11412 | TCGv_i32 tcg_op1 = tcg_temp_new_i32(); | |
11413 | TCGv_i32 tcg_op2 = tcg_temp_new_i32(); | |
bc242f9b | 11414 | NeonGenTwoOpFn *genfn = NULL; |
0173a005 PM |
11415 | int passreg = pass < (maxpass / 2) ? rn : rm; |
11416 | int passelt = (is_q && (pass & 1)) ? 2 : 0; | |
11417 | ||
11418 | read_vec_element_i32(s, tcg_op1, passreg, passelt, MO_32); | |
11419 | read_vec_element_i32(s, tcg_op2, passreg, passelt + 1, MO_32); | |
11420 | tcg_res[pass] = tcg_temp_new_i32(); | |
11421 | ||
11422 | switch (opcode) { | |
11423 | case 0x17: /* ADDP */ | |
11424 | { | |
11425 | static NeonGenTwoOpFn * const fns[3] = { | |
11426 | gen_helper_neon_padd_u8, | |
11427 | gen_helper_neon_padd_u16, | |
11428 | tcg_gen_add_i32, | |
11429 | }; | |
11430 | genfn = fns[size]; | |
11431 | break; | |
11432 | } | |
11433 | case 0x14: /* SMAXP, UMAXP */ | |
11434 | { | |
11435 | static NeonGenTwoOpFn * const fns[3][2] = { | |
11436 | { gen_helper_neon_pmax_s8, gen_helper_neon_pmax_u8 }, | |
11437 | { gen_helper_neon_pmax_s16, gen_helper_neon_pmax_u16 }, | |
ecb8ab8d | 11438 | { tcg_gen_smax_i32, tcg_gen_umax_i32 }, |
0173a005 PM |
11439 | }; |
11440 | genfn = fns[size][u]; | |
11441 | break; | |
11442 | } | |
11443 | case 0x15: /* SMINP, UMINP */ | |
11444 | { | |
11445 | static NeonGenTwoOpFn * const fns[3][2] = { | |
11446 | { gen_helper_neon_pmin_s8, gen_helper_neon_pmin_u8 }, | |
11447 | { gen_helper_neon_pmin_s16, gen_helper_neon_pmin_u16 }, | |
ecb8ab8d | 11448 | { tcg_gen_smin_i32, tcg_gen_umin_i32 }, |
0173a005 PM |
11449 | }; |
11450 | genfn = fns[size][u]; | |
11451 | break; | |
11452 | } | |
bc242f9b AB |
11453 | /* The FP operations are all on single floats (32 bit) */ |
11454 | case 0x58: /* FMAXNMP */ | |
11455 | gen_helper_vfp_maxnums(tcg_res[pass], tcg_op1, tcg_op2, fpst); | |
11456 | break; | |
11457 | case 0x5a: /* FADDP */ | |
11458 | gen_helper_vfp_adds(tcg_res[pass], tcg_op1, tcg_op2, fpst); | |
11459 | break; | |
11460 | case 0x5e: /* FMAXP */ | |
11461 | gen_helper_vfp_maxs(tcg_res[pass], tcg_op1, tcg_op2, fpst); | |
11462 | break; | |
11463 | case 0x78: /* FMINNMP */ | |
11464 | gen_helper_vfp_minnums(tcg_res[pass], tcg_op1, tcg_op2, fpst); | |
11465 | break; | |
11466 | case 0x7e: /* FMINP */ | |
11467 | gen_helper_vfp_mins(tcg_res[pass], tcg_op1, tcg_op2, fpst); | |
11468 | break; | |
0173a005 PM |
11469 | default: |
11470 | g_assert_not_reached(); | |
11471 | } | |
11472 | ||
bc242f9b AB |
11473 | /* FP ops called directly, otherwise call now */ |
11474 | if (genfn) { | |
11475 | genfn(tcg_res[pass], tcg_op1, tcg_op2); | |
11476 | } | |
0173a005 PM |
11477 | |
11478 | tcg_temp_free_i32(tcg_op1); | |
11479 | tcg_temp_free_i32(tcg_op2); | |
11480 | } | |
11481 | ||
11482 | for (pass = 0; pass < maxpass; pass++) { | |
11483 | write_vec_element_i32(s, tcg_res[pass], rd, pass, MO_32); | |
11484 | tcg_temp_free_i32(tcg_res[pass]); | |
11485 | } | |
4ff55bcb | 11486 | clear_vec_high(s, is_q, rd); |
0173a005 | 11487 | } |
bc242f9b | 11488 | |
f764718d | 11489 | if (fpst) { |
bc242f9b AB |
11490 | tcg_temp_free_ptr(fpst); |
11491 | } | |
e1cea114 PM |
11492 | } |
11493 | ||
11494 | /* Floating point op subgroup of C3.6.16. */ | |
11495 | static void disas_simd_3same_float(DisasContext *s, uint32_t insn) | |
11496 | { | |
845ea09a PM |
11497 | /* For floating point ops, the U, size[1] and opcode bits |
11498 | * together indicate the operation. size[0] indicates single | |
11499 | * or double. | |
11500 | */ | |
11501 | int fpopcode = extract32(insn, 11, 5) | |
11502 | | (extract32(insn, 23, 1) << 5) | |
11503 | | (extract32(insn, 29, 1) << 6); | |
11504 | int is_q = extract32(insn, 30, 1); | |
11505 | int size = extract32(insn, 22, 1); | |
11506 | int rm = extract32(insn, 16, 5); | |
11507 | int rn = extract32(insn, 5, 5); | |
11508 | int rd = extract32(insn, 0, 5); | |
11509 | ||
11510 | int datasize = is_q ? 128 : 64; | |
11511 | int esize = 32 << size; | |
11512 | int elements = datasize / esize; | |
11513 | ||
11514 | if (size == 1 && !is_q) { | |
11515 | unallocated_encoding(s); | |
11516 | return; | |
11517 | } | |
11518 | ||
11519 | switch (fpopcode) { | |
11520 | case 0x58: /* FMAXNMP */ | |
11521 | case 0x5a: /* FADDP */ | |
11522 | case 0x5e: /* FMAXP */ | |
11523 | case 0x78: /* FMINNMP */ | |
11524 | case 0x7e: /* FMINP */ | |
bc242f9b AB |
11525 | if (size && !is_q) { |
11526 | unallocated_encoding(s); | |
11527 | return; | |
11528 | } | |
11529 | handle_simd_3same_pair(s, is_q, 0, fpopcode, size ? MO_64 : MO_32, | |
11530 | rn, rm, rd); | |
845ea09a PM |
11531 | return; |
11532 | case 0x1b: /* FMULX */ | |
845ea09a PM |
11533 | case 0x1f: /* FRECPS */ |
11534 | case 0x3f: /* FRSQRTS */ | |
845ea09a | 11535 | case 0x5d: /* FACGE */ |
845ea09a PM |
11536 | case 0x7d: /* FACGT */ |
11537 | case 0x19: /* FMLA */ | |
11538 | case 0x39: /* FMLS */ | |
845ea09a PM |
11539 | case 0x18: /* FMAXNM */ |
11540 | case 0x1a: /* FADD */ | |
8908f4d1 | 11541 | case 0x1c: /* FCMEQ */ |
845ea09a PM |
11542 | case 0x1e: /* FMAX */ |
11543 | case 0x38: /* FMINNM */ | |
11544 | case 0x3a: /* FSUB */ | |
11545 | case 0x3e: /* FMIN */ | |
11546 | case 0x5b: /* FMUL */ | |
8908f4d1 | 11547 | case 0x5c: /* FCMGE */ |
845ea09a PM |
11548 | case 0x5f: /* FDIV */ |
11549 | case 0x7a: /* FABD */ | |
8908f4d1 | 11550 | case 0x7c: /* FCMGT */ |
8c6afa6a PM |
11551 | if (!fp_access_check(s)) { |
11552 | return; | |
11553 | } | |
845ea09a PM |
11554 | handle_3same_float(s, size, elements, fpopcode, rd, rn, rm); |
11555 | return; | |
0caa5af8 RH |
11556 | |
11557 | case 0x1d: /* FMLAL */ | |
11558 | case 0x3d: /* FMLSL */ | |
11559 | case 0x59: /* FMLAL2 */ | |
11560 | case 0x79: /* FMLSL2 */ | |
11561 | if (size & 1 || !dc_isar_feature(aa64_fhm, s)) { | |
11562 | unallocated_encoding(s); | |
11563 | return; | |
11564 | } | |
11565 | if (fp_access_check(s)) { | |
11566 | int is_s = extract32(insn, 23, 1); | |
11567 | int is_2 = extract32(insn, 29, 1); | |
11568 | int data = (is_2 << 1) | is_s; | |
11569 | tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd), | |
11570 | vec_full_reg_offset(s, rn), | |
11571 | vec_full_reg_offset(s, rm), cpu_env, | |
11572 | is_q ? 16 : 8, vec_full_reg_size(s), | |
11573 | data, gen_helper_gvec_fmlal_a64); | |
11574 | } | |
11575 | return; | |
11576 | ||
845ea09a PM |
11577 | default: |
11578 | unallocated_encoding(s); | |
11579 | return; | |
11580 | } | |
e1cea114 PM |
11581 | } |
11582 | ||
11583 | /* Integer op subgroup of C3.6.16. */ | |
11584 | static void disas_simd_3same_int(DisasContext *s, uint32_t insn) | |
11585 | { | |
1f8a73af PM |
11586 | int is_q = extract32(insn, 30, 1); |
11587 | int u = extract32(insn, 29, 1); | |
11588 | int size = extract32(insn, 22, 2); | |
11589 | int opcode = extract32(insn, 11, 5); | |
11590 | int rm = extract32(insn, 16, 5); | |
11591 | int rn = extract32(insn, 5, 5); | |
11592 | int rd = extract32(insn, 0, 5); | |
11593 | int pass; | |
79d61de6 | 11594 | TCGCond cond; |
1f8a73af PM |
11595 | |
11596 | switch (opcode) { | |
11597 | case 0x13: /* MUL, PMUL */ | |
11598 | if (u && size != 0) { | |
11599 | unallocated_encoding(s); | |
11600 | return; | |
11601 | } | |
11602 | /* fall through */ | |
11603 | case 0x0: /* SHADD, UHADD */ | |
11604 | case 0x2: /* SRHADD, URHADD */ | |
11605 | case 0x4: /* SHSUB, UHSUB */ | |
11606 | case 0xc: /* SMAX, UMAX */ | |
11607 | case 0xd: /* SMIN, UMIN */ | |
11608 | case 0xe: /* SABD, UABD */ | |
11609 | case 0xf: /* SABA, UABA */ | |
11610 | case 0x12: /* MLA, MLS */ | |
11611 | if (size == 3) { | |
11612 | unallocated_encoding(s); | |
11613 | return; | |
11614 | } | |
8b12a0cf | 11615 | break; |
1f8a73af PM |
11616 | case 0x16: /* SQDMULH, SQRDMULH */ |
11617 | if (size == 0 || size == 3) { | |
11618 | unallocated_encoding(s); | |
11619 | return; | |
11620 | } | |
8b12a0cf | 11621 | break; |
1f8a73af PM |
11622 | default: |
11623 | if (size == 3 && !is_q) { | |
11624 | unallocated_encoding(s); | |
11625 | return; | |
11626 | } | |
11627 | break; | |
11628 | } | |
11629 | ||
8c6afa6a PM |
11630 | if (!fp_access_check(s)) { |
11631 | return; | |
11632 | } | |
11633 | ||
bc48092f | 11634 | switch (opcode) { |
89e68b57 | 11635 | case 0x01: /* SQADD, UQADD */ |
c7715b6b RH |
11636 | if (u) { |
11637 | gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_uqadd_qc, size); | |
11638 | } else { | |
11639 | gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_sqadd_qc, size); | |
11640 | } | |
89e68b57 RH |
11641 | return; |
11642 | case 0x05: /* SQSUB, UQSUB */ | |
c7715b6b RH |
11643 | if (u) { |
11644 | gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_uqsub_qc, size); | |
11645 | } else { | |
11646 | gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_sqsub_qc, size); | |
11647 | } | |
89e68b57 | 11648 | return; |
87b74e8b | 11649 | case 0x08: /* SSHL, USHL */ |
8161b753 RH |
11650 | if (u) { |
11651 | gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_ushl, size); | |
11652 | } else { | |
11653 | gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_sshl, size); | |
11654 | } | |
87b74e8b | 11655 | return; |
264d2a48 RH |
11656 | case 0x0c: /* SMAX, UMAX */ |
11657 | if (u) { | |
11658 | gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_umax, size); | |
11659 | } else { | |
11660 | gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_smax, size); | |
11661 | } | |
11662 | return; | |
11663 | case 0x0d: /* SMIN, UMIN */ | |
11664 | if (u) { | |
11665 | gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_umin, size); | |
11666 | } else { | |
11667 | gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_smin, size); | |
11668 | } | |
11669 | return; | |
50c160d4 RH |
11670 | case 0xe: /* SABD, UABD */ |
11671 | if (u) { | |
11672 | gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_uabd, size); | |
11673 | } else { | |
11674 | gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_sabd, size); | |
11675 | } | |
11676 | return; | |
cfdb2c0c RH |
11677 | case 0xf: /* SABA, UABA */ |
11678 | if (u) { | |
11679 | gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_uaba, size); | |
11680 | } else { | |
11681 | gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_saba, size); | |
11682 | } | |
11683 | return; | |
bc48092f RH |
11684 | case 0x10: /* ADD, SUB */ |
11685 | if (u) { | |
11686 | gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_sub, size); | |
11687 | } else { | |
11688 | gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_add, size); | |
11689 | } | |
11690 | return; | |
0c7c55c4 RH |
11691 | case 0x13: /* MUL, PMUL */ |
11692 | if (!u) { /* MUL */ | |
11693 | gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_mul, size); | |
a21bb78e RH |
11694 | } else { /* PMUL */ |
11695 | gen_gvec_op3_ool(s, is_q, rd, rn, rm, 0, gen_helper_gvec_pmul_b); | |
0c7c55c4 | 11696 | } |
a21bb78e | 11697 | return; |
0c7c55c4 RH |
11698 | case 0x12: /* MLA, MLS */ |
11699 | if (u) { | |
27106320 | 11700 | gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_mls, size); |
0c7c55c4 | 11701 | } else { |
27106320 | 11702 | gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_mla, size); |
0c7c55c4 RH |
11703 | } |
11704 | return; | |
79d61de6 RH |
11705 | case 0x11: |
11706 | if (!u) { /* CMTST */ | |
8161b753 | 11707 | gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_cmtst, size); |
79d61de6 RH |
11708 | return; |
11709 | } | |
11710 | /* else CMEQ */ | |
11711 | cond = TCG_COND_EQ; | |
11712 | goto do_gvec_cmp; | |
11713 | case 0x06: /* CMGT, CMHI */ | |
11714 | cond = u ? TCG_COND_GTU : TCG_COND_GT; | |
11715 | goto do_gvec_cmp; | |
11716 | case 0x07: /* CMGE, CMHS */ | |
11717 | cond = u ? TCG_COND_GEU : TCG_COND_GE; | |
11718 | do_gvec_cmp: | |
11719 | tcg_gen_gvec_cmp(cond, size, vec_full_reg_offset(s, rd), | |
11720 | vec_full_reg_offset(s, rn), | |
11721 | vec_full_reg_offset(s, rm), | |
11722 | is_q ? 16 : 8, vec_full_reg_size(s)); | |
11723 | return; | |
bc48092f RH |
11724 | } |
11725 | ||
1f8a73af | 11726 | if (size == 3) { |
220ad4ca PM |
11727 | assert(is_q); |
11728 | for (pass = 0; pass < 2; pass++) { | |
1f8a73af PM |
11729 | TCGv_i64 tcg_op1 = tcg_temp_new_i64(); |
11730 | TCGv_i64 tcg_op2 = tcg_temp_new_i64(); | |
11731 | TCGv_i64 tcg_res = tcg_temp_new_i64(); | |
11732 | ||
11733 | read_vec_element(s, tcg_op1, rn, pass, MO_64); | |
11734 | read_vec_element(s, tcg_op2, rm, pass, MO_64); | |
11735 | ||
11736 | handle_3same_64(s, opcode, u, tcg_res, tcg_op1, tcg_op2); | |
11737 | ||
11738 | write_vec_element(s, tcg_res, rd, pass, MO_64); | |
11739 | ||
11740 | tcg_temp_free_i64(tcg_res); | |
11741 | tcg_temp_free_i64(tcg_op1); | |
11742 | tcg_temp_free_i64(tcg_op2); | |
11743 | } | |
11744 | } else { | |
11745 | for (pass = 0; pass < (is_q ? 4 : 2); pass++) { | |
11746 | TCGv_i32 tcg_op1 = tcg_temp_new_i32(); | |
11747 | TCGv_i32 tcg_op2 = tcg_temp_new_i32(); | |
11748 | TCGv_i32 tcg_res = tcg_temp_new_i32(); | |
6d9571f7 PM |
11749 | NeonGenTwoOpFn *genfn = NULL; |
11750 | NeonGenTwoOpEnvFn *genenvfn = NULL; | |
1f8a73af PM |
11751 | |
11752 | read_vec_element_i32(s, tcg_op1, rn, pass, MO_32); | |
11753 | read_vec_element_i32(s, tcg_op2, rm, pass, MO_32); | |
11754 | ||
11755 | switch (opcode) { | |
8b12a0cf PM |
11756 | case 0x0: /* SHADD, UHADD */ |
11757 | { | |
11758 | static NeonGenTwoOpFn * const fns[3][2] = { | |
11759 | { gen_helper_neon_hadd_s8, gen_helper_neon_hadd_u8 }, | |
11760 | { gen_helper_neon_hadd_s16, gen_helper_neon_hadd_u16 }, | |
11761 | { gen_helper_neon_hadd_s32, gen_helper_neon_hadd_u32 }, | |
11762 | }; | |
11763 | genfn = fns[size][u]; | |
11764 | break; | |
11765 | } | |
8b12a0cf PM |
11766 | case 0x2: /* SRHADD, URHADD */ |
11767 | { | |
11768 | static NeonGenTwoOpFn * const fns[3][2] = { | |
11769 | { gen_helper_neon_rhadd_s8, gen_helper_neon_rhadd_u8 }, | |
11770 | { gen_helper_neon_rhadd_s16, gen_helper_neon_rhadd_u16 }, | |
11771 | { gen_helper_neon_rhadd_s32, gen_helper_neon_rhadd_u32 }, | |
11772 | }; | |
11773 | genfn = fns[size][u]; | |
11774 | break; | |
11775 | } | |
11776 | case 0x4: /* SHSUB, UHSUB */ | |
11777 | { | |
11778 | static NeonGenTwoOpFn * const fns[3][2] = { | |
11779 | { gen_helper_neon_hsub_s8, gen_helper_neon_hsub_u8 }, | |
11780 | { gen_helper_neon_hsub_s16, gen_helper_neon_hsub_u16 }, | |
11781 | { gen_helper_neon_hsub_s32, gen_helper_neon_hsub_u32 }, | |
11782 | }; | |
11783 | genfn = fns[size][u]; | |
11784 | break; | |
11785 | } | |
6d9571f7 PM |
11786 | case 0x9: /* SQSHL, UQSHL */ |
11787 | { | |
11788 | static NeonGenTwoOpEnvFn * const fns[3][2] = { | |
11789 | { gen_helper_neon_qshl_s8, gen_helper_neon_qshl_u8 }, | |
11790 | { gen_helper_neon_qshl_s16, gen_helper_neon_qshl_u16 }, | |
11791 | { gen_helper_neon_qshl_s32, gen_helper_neon_qshl_u32 }, | |
11792 | }; | |
11793 | genenvfn = fns[size][u]; | |
11794 | break; | |
11795 | } | |
11796 | case 0xa: /* SRSHL, URSHL */ | |
11797 | { | |
11798 | static NeonGenTwoOpFn * const fns[3][2] = { | |
11799 | { gen_helper_neon_rshl_s8, gen_helper_neon_rshl_u8 }, | |
11800 | { gen_helper_neon_rshl_s16, gen_helper_neon_rshl_u16 }, | |
11801 | { gen_helper_neon_rshl_s32, gen_helper_neon_rshl_u32 }, | |
11802 | }; | |
11803 | genfn = fns[size][u]; | |
11804 | break; | |
11805 | } | |
11806 | case 0xb: /* SQRSHL, UQRSHL */ | |
11807 | { | |
11808 | static NeonGenTwoOpEnvFn * const fns[3][2] = { | |
11809 | { gen_helper_neon_qrshl_s8, gen_helper_neon_qrshl_u8 }, | |
11810 | { gen_helper_neon_qrshl_s16, gen_helper_neon_qrshl_u16 }, | |
11811 | { gen_helper_neon_qrshl_s32, gen_helper_neon_qrshl_u32 }, | |
11812 | }; | |
11813 | genenvfn = fns[size][u]; | |
11814 | break; | |
11815 | } | |
8b12a0cf PM |
11816 | case 0x16: /* SQDMULH, SQRDMULH */ |
11817 | { | |
11818 | static NeonGenTwoOpEnvFn * const fns[2][2] = { | |
11819 | { gen_helper_neon_qdmulh_s16, gen_helper_neon_qrdmulh_s16 }, | |
11820 | { gen_helper_neon_qdmulh_s32, gen_helper_neon_qrdmulh_s32 }, | |
11821 | }; | |
11822 | assert(size == 1 || size == 2); | |
11823 | genenvfn = fns[size - 1][u]; | |
11824 | break; | |
11825 | } | |
1f8a73af PM |
11826 | default: |
11827 | g_assert_not_reached(); | |
11828 | } | |
11829 | ||
6d9571f7 PM |
11830 | if (genenvfn) { |
11831 | genenvfn(tcg_res, cpu_env, tcg_op1, tcg_op2); | |
11832 | } else { | |
11833 | genfn(tcg_res, tcg_op1, tcg_op2); | |
11834 | } | |
1f8a73af PM |
11835 | |
11836 | write_vec_element_i32(s, tcg_res, rd, pass, MO_32); | |
11837 | ||
11838 | tcg_temp_free_i32(tcg_res); | |
11839 | tcg_temp_free_i32(tcg_op1); | |
11840 | tcg_temp_free_i32(tcg_op2); | |
11841 | } | |
11842 | } | |
4ff55bcb | 11843 | clear_vec_high(s, is_q, rd); |
e1cea114 PM |
11844 | } |
11845 | ||
4ce31af4 | 11846 | /* AdvSIMD three same |
384b26fb AB |
11847 | * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0 |
11848 | * +---+---+---+-----------+------+---+------+--------+---+------+------+ | |
11849 | * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd | | |
11850 | * +---+---+---+-----------+------+---+------+--------+---+------+------+ | |
11851 | */ | |
11852 | static void disas_simd_three_reg_same(DisasContext *s, uint32_t insn) | |
11853 | { | |
e1cea114 PM |
11854 | int opcode = extract32(insn, 11, 5); |
11855 | ||
11856 | switch (opcode) { | |
11857 | case 0x3: /* logic ops */ | |
11858 | disas_simd_3same_logic(s, insn); | |
11859 | break; | |
11860 | case 0x17: /* ADDP */ | |
11861 | case 0x14: /* SMAXP, UMAXP */ | |
11862 | case 0x15: /* SMINP, UMINP */ | |
bc242f9b | 11863 | { |
e1cea114 | 11864 | /* Pairwise operations */ |
bc242f9b AB |
11865 | int is_q = extract32(insn, 30, 1); |
11866 | int u = extract32(insn, 29, 1); | |
11867 | int size = extract32(insn, 22, 2); | |
11868 | int rm = extract32(insn, 16, 5); | |
11869 | int rn = extract32(insn, 5, 5); | |
11870 | int rd = extract32(insn, 0, 5); | |
11871 | if (opcode == 0x17) { | |
11872 | if (u || (size == 3 && !is_q)) { | |
11873 | unallocated_encoding(s); | |
11874 | return; | |
11875 | } | |
11876 | } else { | |
11877 | if (size == 3) { | |
11878 | unallocated_encoding(s); | |
11879 | return; | |
11880 | } | |
11881 | } | |
11882 | handle_simd_3same_pair(s, is_q, u, opcode, size, rn, rm, rd); | |
e1cea114 | 11883 | break; |
bc242f9b | 11884 | } |
e1cea114 PM |
11885 | case 0x18 ... 0x31: |
11886 | /* floating point ops, sz[1] and U are part of opcode */ | |
11887 | disas_simd_3same_float(s, insn); | |
11888 | break; | |
11889 | default: | |
11890 | disas_simd_3same_int(s, insn); | |
11891 | break; | |
11892 | } | |
384b26fb AB |
11893 | } |
11894 | ||
376e8d6c AB |
11895 | /* |
11896 | * Advanced SIMD three same (ARMv8.2 FP16 variants) | |
11897 | * | |
11898 | * 31 30 29 28 24 23 22 21 20 16 15 14 13 11 10 9 5 4 0 | |
11899 | * +---+---+---+-----------+---------+------+-----+--------+---+------+------+ | |
11900 | * | 0 | Q | U | 0 1 1 1 0 | a | 1 0 | Rm | 0 0 | opcode | 1 | Rn | Rd | | |
11901 | * +---+---+---+-----------+---------+------+-----+--------+---+------+------+ | |
11902 | * | |
11903 | * This includes FMULX, FCMEQ (register), FRECPS, FRSQRTS, FCMGE | |
11904 | * (register), FACGE, FABD, FCMGT (register) and FACGT. | |
11905 | * | |
11906 | */ | |
11907 | static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn) | |
11908 | { | |
11909 | int opcode, fpopcode; | |
11910 | int is_q, u, a, rm, rn, rd; | |
11911 | int datasize, elements; | |
11912 | int pass; | |
11913 | TCGv_ptr fpst; | |
7a2c6e61 | 11914 | bool pairwise = false; |
376e8d6c | 11915 | |
5763190f | 11916 | if (!dc_isar_feature(aa64_fp16, s)) { |
376e8d6c AB |
11917 | unallocated_encoding(s); |
11918 | return; | |
11919 | } | |
11920 | ||
11921 | if (!fp_access_check(s)) { | |
11922 | return; | |
11923 | } | |
11924 | ||
11925 | /* For these floating point ops, the U, a and opcode bits | |
11926 | * together indicate the operation. | |
11927 | */ | |
11928 | opcode = extract32(insn, 11, 3); | |
11929 | u = extract32(insn, 29, 1); | |
11930 | a = extract32(insn, 23, 1); | |
11931 | is_q = extract32(insn, 30, 1); | |
11932 | rm = extract32(insn, 16, 5); | |
11933 | rn = extract32(insn, 5, 5); | |
11934 | rd = extract32(insn, 0, 5); | |
11935 | ||
11936 | fpopcode = opcode | (a << 3) | (u << 4); | |
11937 | datasize = is_q ? 128 : 64; | |
11938 | elements = datasize / 16; | |
11939 | ||
7a2c6e61 AB |
11940 | switch (fpopcode) { |
11941 | case 0x10: /* FMAXNMP */ | |
11942 | case 0x12: /* FADDP */ | |
11943 | case 0x16: /* FMAXP */ | |
11944 | case 0x18: /* FMINNMP */ | |
11945 | case 0x1e: /* FMINP */ | |
11946 | pairwise = true; | |
11947 | break; | |
11948 | } | |
11949 | ||
376e8d6c AB |
11950 | fpst = get_fpstatus_ptr(true); |
11951 | ||
7a2c6e61 AB |
11952 | if (pairwise) { |
11953 | int maxpass = is_q ? 8 : 4; | |
376e8d6c AB |
11954 | TCGv_i32 tcg_op1 = tcg_temp_new_i32(); |
11955 | TCGv_i32 tcg_op2 = tcg_temp_new_i32(); | |
7a2c6e61 | 11956 | TCGv_i32 tcg_res[8]; |
376e8d6c | 11957 | |
7a2c6e61 AB |
11958 | for (pass = 0; pass < maxpass; pass++) { |
11959 | int passreg = pass < (maxpass / 2) ? rn : rm; | |
11960 | int passelt = (pass << 1) & (maxpass - 1); | |
376e8d6c | 11961 | |
7a2c6e61 AB |
11962 | read_vec_element_i32(s, tcg_op1, passreg, passelt, MO_16); |
11963 | read_vec_element_i32(s, tcg_op2, passreg, passelt + 1, MO_16); | |
11964 | tcg_res[pass] = tcg_temp_new_i32(); | |
11965 | ||
11966 | switch (fpopcode) { | |
11967 | case 0x10: /* FMAXNMP */ | |
11968 | gen_helper_advsimd_maxnumh(tcg_res[pass], tcg_op1, tcg_op2, | |
11969 | fpst); | |
11970 | break; | |
11971 | case 0x12: /* FADDP */ | |
11972 | gen_helper_advsimd_addh(tcg_res[pass], tcg_op1, tcg_op2, fpst); | |
11973 | break; | |
11974 | case 0x16: /* FMAXP */ | |
11975 | gen_helper_advsimd_maxh(tcg_res[pass], tcg_op1, tcg_op2, fpst); | |
11976 | break; | |
11977 | case 0x18: /* FMINNMP */ | |
11978 | gen_helper_advsimd_minnumh(tcg_res[pass], tcg_op1, tcg_op2, | |
11979 | fpst); | |
11980 | break; | |
11981 | case 0x1e: /* FMINP */ | |
11982 | gen_helper_advsimd_minh(tcg_res[pass], tcg_op1, tcg_op2, fpst); | |
11983 | break; | |
11984 | default: | |
11985 | g_assert_not_reached(); | |
11986 | } | |
11987 | } | |
11988 | ||
11989 | for (pass = 0; pass < maxpass; pass++) { | |
11990 | write_vec_element_i32(s, tcg_res[pass], rd, pass, MO_16); | |
11991 | tcg_temp_free_i32(tcg_res[pass]); | |
376e8d6c AB |
11992 | } |
11993 | ||
376e8d6c AB |
11994 | tcg_temp_free_i32(tcg_op1); |
11995 | tcg_temp_free_i32(tcg_op2); | |
7a2c6e61 AB |
11996 | |
11997 | } else { | |
11998 | for (pass = 0; pass < elements; pass++) { | |
11999 | TCGv_i32 tcg_op1 = tcg_temp_new_i32(); | |
12000 | TCGv_i32 tcg_op2 = tcg_temp_new_i32(); | |
12001 | TCGv_i32 tcg_res = tcg_temp_new_i32(); | |
12002 | ||
12003 | read_vec_element_i32(s, tcg_op1, rn, pass, MO_16); | |
12004 | read_vec_element_i32(s, tcg_op2, rm, pass, MO_16); | |
12005 | ||
12006 | switch (fpopcode) { | |
12007 | case 0x0: /* FMAXNM */ | |
12008 | gen_helper_advsimd_maxnumh(tcg_res, tcg_op1, tcg_op2, fpst); | |
12009 | break; | |
12010 | case 0x1: /* FMLA */ | |
12011 | read_vec_element_i32(s, tcg_res, rd, pass, MO_16); | |
12012 | gen_helper_advsimd_muladdh(tcg_res, tcg_op1, tcg_op2, tcg_res, | |
12013 | fpst); | |
12014 | break; | |
12015 | case 0x2: /* FADD */ | |
12016 | gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst); | |
12017 | break; | |
12018 | case 0x3: /* FMULX */ | |
12019 | gen_helper_advsimd_mulxh(tcg_res, tcg_op1, tcg_op2, fpst); | |
12020 | break; | |
12021 | case 0x4: /* FCMEQ */ | |
12022 | gen_helper_advsimd_ceq_f16(tcg_res, tcg_op1, tcg_op2, fpst); | |
12023 | break; | |
12024 | case 0x6: /* FMAX */ | |
12025 | gen_helper_advsimd_maxh(tcg_res, tcg_op1, tcg_op2, fpst); | |
12026 | break; | |
12027 | case 0x7: /* FRECPS */ | |
12028 | gen_helper_recpsf_f16(tcg_res, tcg_op1, tcg_op2, fpst); | |
12029 | break; | |
12030 | case 0x8: /* FMINNM */ | |
12031 | gen_helper_advsimd_minnumh(tcg_res, tcg_op1, tcg_op2, fpst); | |
12032 | break; | |
12033 | case 0x9: /* FMLS */ | |
12034 | /* As usual for ARM, separate negation for fused multiply-add */ | |
12035 | tcg_gen_xori_i32(tcg_op1, tcg_op1, 0x8000); | |
12036 | read_vec_element_i32(s, tcg_res, rd, pass, MO_16); | |
12037 | gen_helper_advsimd_muladdh(tcg_res, tcg_op1, tcg_op2, tcg_res, | |
12038 | fpst); | |
12039 | break; | |
12040 | case 0xa: /* FSUB */ | |
12041 | gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst); | |
12042 | break; | |
12043 | case 0xe: /* FMIN */ | |
12044 | gen_helper_advsimd_minh(tcg_res, tcg_op1, tcg_op2, fpst); | |
12045 | break; | |
12046 | case 0xf: /* FRSQRTS */ | |
12047 | gen_helper_rsqrtsf_f16(tcg_res, tcg_op1, tcg_op2, fpst); | |
12048 | break; | |
12049 | case 0x13: /* FMUL */ | |
12050 | gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst); | |
12051 | break; | |
12052 | case 0x14: /* FCMGE */ | |
12053 | gen_helper_advsimd_cge_f16(tcg_res, tcg_op1, tcg_op2, fpst); | |
12054 | break; | |
12055 | case 0x15: /* FACGE */ | |
12056 | gen_helper_advsimd_acge_f16(tcg_res, tcg_op1, tcg_op2, fpst); | |
12057 | break; | |
12058 | case 0x17: /* FDIV */ | |
12059 | gen_helper_advsimd_divh(tcg_res, tcg_op1, tcg_op2, fpst); | |
12060 | break; | |
12061 | case 0x1a: /* FABD */ | |
12062 | gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst); | |
12063 | tcg_gen_andi_i32(tcg_res, tcg_res, 0x7fff); | |
12064 | break; | |
12065 | case 0x1c: /* FCMGT */ | |
12066 | gen_helper_advsimd_cgt_f16(tcg_res, tcg_op1, tcg_op2, fpst); | |
12067 | break; | |
12068 | case 0x1d: /* FACGT */ | |
12069 | gen_helper_advsimd_acgt_f16(tcg_res, tcg_op1, tcg_op2, fpst); | |
12070 | break; | |
12071 | default: | |
12072 | fprintf(stderr, "%s: insn %#04x, fpop %#2x @ %#" PRIx64 "\n", | |
43722a6d | 12073 | __func__, insn, fpopcode, s->pc_curr); |
7a2c6e61 AB |
12074 | g_assert_not_reached(); |
12075 | } | |
12076 | ||
12077 | write_vec_element_i32(s, tcg_res, rd, pass, MO_16); | |
12078 | tcg_temp_free_i32(tcg_res); | |
12079 | tcg_temp_free_i32(tcg_op1); | |
12080 | tcg_temp_free_i32(tcg_op2); | |
12081 | } | |
376e8d6c AB |
12082 | } |
12083 | ||
12084 | tcg_temp_free_ptr(fpst); | |
12085 | ||
12086 | clear_vec_high(s, is_q, rd); | |
12087 | } | |
12088 | ||
e7186d82 RH |
12089 | /* AdvSIMD three same extra |
12090 | * 31 30 29 28 24 23 22 21 20 16 15 14 11 10 9 5 4 0 | |
12091 | * +---+---+---+-----------+------+---+------+---+--------+---+----+----+ | |
12092 | * | 0 | Q | U | 0 1 1 1 0 | size | 0 | Rm | 1 | opcode | 1 | Rn | Rd | | |
12093 | * +---+---+---+-----------+------+---+------+---+--------+---+----+----+ | |
12094 | */ | |
12095 | static void disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn) | |
12096 | { | |
12097 | int rd = extract32(insn, 0, 5); | |
12098 | int rn = extract32(insn, 5, 5); | |
12099 | int opcode = extract32(insn, 11, 4); | |
12100 | int rm = extract32(insn, 16, 5); | |
12101 | int size = extract32(insn, 22, 2); | |
12102 | bool u = extract32(insn, 29, 1); | |
12103 | bool is_q = extract32(insn, 30, 1); | |
962fcbf2 RH |
12104 | bool feature; |
12105 | int rot; | |
e7186d82 RH |
12106 | |
12107 | switch (u * 16 + opcode) { | |
12108 | case 0x10: /* SQRDMLAH (vector) */ | |
12109 | case 0x11: /* SQRDMLSH (vector) */ | |
12110 | if (size != 1 && size != 2) { | |
12111 | unallocated_encoding(s); | |
12112 | return; | |
12113 | } | |
962fcbf2 | 12114 | feature = dc_isar_feature(aa64_rdm, s); |
e7186d82 | 12115 | break; |
26c470a7 RH |
12116 | case 0x02: /* SDOT (vector) */ |
12117 | case 0x12: /* UDOT (vector) */ | |
12118 | if (size != MO_32) { | |
12119 | unallocated_encoding(s); | |
12120 | return; | |
12121 | } | |
962fcbf2 | 12122 | feature = dc_isar_feature(aa64_dp, s); |
26c470a7 | 12123 | break; |
b8a4a96d RH |
12124 | case 0x18: /* FCMLA, #0 */ |
12125 | case 0x19: /* FCMLA, #90 */ | |
12126 | case 0x1a: /* FCMLA, #180 */ | |
12127 | case 0x1b: /* FCMLA, #270 */ | |
12128 | case 0x1c: /* FCADD, #90 */ | |
12129 | case 0x1e: /* FCADD, #270 */ | |
1695cd61 | 12130 | if (size == 0 |
5763190f | 12131 | || (size == 1 && !dc_isar_feature(aa64_fp16, s)) |
1695cd61 RH |
12132 | || (size == 3 && !is_q)) { |
12133 | unallocated_encoding(s); | |
12134 | return; | |
12135 | } | |
962fcbf2 | 12136 | feature = dc_isar_feature(aa64_fcma, s); |
1695cd61 | 12137 | break; |
e7186d82 RH |
12138 | default: |
12139 | unallocated_encoding(s); | |
12140 | return; | |
12141 | } | |
962fcbf2 | 12142 | if (!feature) { |
e7186d82 RH |
12143 | unallocated_encoding(s); |
12144 | return; | |
12145 | } | |
12146 | if (!fp_access_check(s)) { | |
12147 | return; | |
12148 | } | |
12149 | ||
12150 | switch (opcode) { | |
12151 | case 0x0: /* SQRDMLAH (vector) */ | |
146aa66c | 12152 | gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_sqrdmlah_qc, size); |
e7186d82 RH |
12153 | return; |
12154 | ||
12155 | case 0x1: /* SQRDMLSH (vector) */ | |
146aa66c | 12156 | gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_sqrdmlsh_qc, size); |
e7186d82 RH |
12157 | return; |
12158 | ||
26c470a7 RH |
12159 | case 0x2: /* SDOT / UDOT */ |
12160 | gen_gvec_op3_ool(s, is_q, rd, rn, rm, 0, | |
12161 | u ? gen_helper_gvec_udot_b : gen_helper_gvec_sdot_b); | |
12162 | return; | |
12163 | ||
d17b7cdc RH |
12164 | case 0x8: /* FCMLA, #0 */ |
12165 | case 0x9: /* FCMLA, #90 */ | |
12166 | case 0xa: /* FCMLA, #180 */ | |
12167 | case 0xb: /* FCMLA, #270 */ | |
12168 | rot = extract32(opcode, 0, 2); | |
12169 | switch (size) { | |
12170 | case 1: | |
12171 | gen_gvec_op3_fpst(s, is_q, rd, rn, rm, true, rot, | |
12172 | gen_helper_gvec_fcmlah); | |
12173 | break; | |
12174 | case 2: | |
12175 | gen_gvec_op3_fpst(s, is_q, rd, rn, rm, false, rot, | |
12176 | gen_helper_gvec_fcmlas); | |
12177 | break; | |
12178 | case 3: | |
12179 | gen_gvec_op3_fpst(s, is_q, rd, rn, rm, false, rot, | |
12180 | gen_helper_gvec_fcmlad); | |
12181 | break; | |
12182 | default: | |
12183 | g_assert_not_reached(); | |
12184 | } | |
12185 | return; | |
12186 | ||
1695cd61 RH |
12187 | case 0xc: /* FCADD, #90 */ |
12188 | case 0xe: /* FCADD, #270 */ | |
12189 | rot = extract32(opcode, 1, 1); | |
12190 | switch (size) { | |
12191 | case 1: | |
12192 | gen_gvec_op3_fpst(s, is_q, rd, rn, rm, size == 1, rot, | |
12193 | gen_helper_gvec_fcaddh); | |
12194 | break; | |
12195 | case 2: | |
12196 | gen_gvec_op3_fpst(s, is_q, rd, rn, rm, size == 1, rot, | |
12197 | gen_helper_gvec_fcadds); | |
12198 | break; | |
12199 | case 3: | |
12200 | gen_gvec_op3_fpst(s, is_q, rd, rn, rm, size == 1, rot, | |
12201 | gen_helper_gvec_fcaddd); | |
12202 | break; | |
12203 | default: | |
12204 | g_assert_not_reached(); | |
12205 | } | |
12206 | return; | |
12207 | ||
e7186d82 RH |
12208 | default: |
12209 | g_assert_not_reached(); | |
12210 | } | |
12211 | } | |
12212 | ||
931c8cc2 PM |
12213 | static void handle_2misc_widening(DisasContext *s, int opcode, bool is_q, |
12214 | int size, int rn, int rd) | |
12215 | { | |
12216 | /* Handle 2-reg-misc ops which are widening (so each size element | |
12217 | * in the source becomes a 2*size element in the destination. | |
12218 | * The only instruction like this is FCVTL. | |
12219 | */ | |
12220 | int pass; | |
12221 | ||
12222 | if (size == 3) { | |
12223 | /* 32 -> 64 bit fp conversion */ | |
12224 | TCGv_i64 tcg_res[2]; | |
12225 | int srcelt = is_q ? 2 : 0; | |
12226 | ||
12227 | for (pass = 0; pass < 2; pass++) { | |
12228 | TCGv_i32 tcg_op = tcg_temp_new_i32(); | |
12229 | tcg_res[pass] = tcg_temp_new_i64(); | |
12230 | ||
12231 | read_vec_element_i32(s, tcg_op, rn, srcelt + pass, MO_32); | |
12232 | gen_helper_vfp_fcvtds(tcg_res[pass], tcg_op, cpu_env); | |
12233 | tcg_temp_free_i32(tcg_op); | |
12234 | } | |
12235 | for (pass = 0; pass < 2; pass++) { | |
12236 | write_vec_element(s, tcg_res[pass], rd, pass, MO_64); | |
12237 | tcg_temp_free_i64(tcg_res[pass]); | |
12238 | } | |
12239 | } else { | |
12240 | /* 16 -> 32 bit fp conversion */ | |
12241 | int srcelt = is_q ? 4 : 0; | |
12242 | TCGv_i32 tcg_res[4]; | |
486624fc AB |
12243 | TCGv_ptr fpst = get_fpstatus_ptr(false); |
12244 | TCGv_i32 ahp = get_ahp_flag(); | |
931c8cc2 PM |
12245 | |
12246 | for (pass = 0; pass < 4; pass++) { | |
12247 | tcg_res[pass] = tcg_temp_new_i32(); | |
12248 | ||
12249 | read_vec_element_i32(s, tcg_res[pass], rn, srcelt + pass, MO_16); | |
12250 | gen_helper_vfp_fcvt_f16_to_f32(tcg_res[pass], tcg_res[pass], | |
486624fc | 12251 | fpst, ahp); |
931c8cc2 PM |
12252 | } |
12253 | for (pass = 0; pass < 4; pass++) { | |
12254 | write_vec_element_i32(s, tcg_res[pass], rd, pass, MO_32); | |
12255 | tcg_temp_free_i32(tcg_res[pass]); | |
12256 | } | |
486624fc AB |
12257 | |
12258 | tcg_temp_free_ptr(fpst); | |
12259 | tcg_temp_free_i32(ahp); | |
931c8cc2 PM |
12260 | } |
12261 | } | |
12262 | ||
39d82118 AB |
12263 | static void handle_rev(DisasContext *s, int opcode, bool u, |
12264 | bool is_q, int size, int rn, int rd) | |
12265 | { | |
12266 | int op = (opcode << 1) | u; | |
12267 | int opsz = op + size; | |
12268 | int grp_size = 3 - opsz; | |
12269 | int dsize = is_q ? 128 : 64; | |
12270 | int i; | |
12271 | ||
12272 | if (opsz >= 3) { | |
12273 | unallocated_encoding(s); | |
12274 | return; | |
12275 | } | |
12276 | ||
8c6afa6a PM |
12277 | if (!fp_access_check(s)) { |
12278 | return; | |
12279 | } | |
12280 | ||
39d82118 AB |
12281 | if (size == 0) { |
12282 | /* Special case bytes, use bswap op on each group of elements */ | |
12283 | int groups = dsize / (8 << grp_size); | |
12284 | ||
12285 | for (i = 0; i < groups; i++) { | |
12286 | TCGv_i64 tcg_tmp = tcg_temp_new_i64(); | |
12287 | ||
12288 | read_vec_element(s, tcg_tmp, rn, i, grp_size); | |
12289 | switch (grp_size) { | |
12290 | case MO_16: | |
12291 | tcg_gen_bswap16_i64(tcg_tmp, tcg_tmp); | |
12292 | break; | |
12293 | case MO_32: | |
12294 | tcg_gen_bswap32_i64(tcg_tmp, tcg_tmp); | |
12295 | break; | |
12296 | case MO_64: | |
12297 | tcg_gen_bswap64_i64(tcg_tmp, tcg_tmp); | |
12298 | break; | |
12299 | default: | |
12300 | g_assert_not_reached(); | |
12301 | } | |
12302 | write_vec_element(s, tcg_tmp, rd, i, grp_size); | |
12303 | tcg_temp_free_i64(tcg_tmp); | |
12304 | } | |
4ff55bcb | 12305 | clear_vec_high(s, is_q, rd); |
39d82118 AB |
12306 | } else { |
12307 | int revmask = (1 << grp_size) - 1; | |
12308 | int esize = 8 << size; | |
12309 | int elements = dsize / esize; | |
12310 | TCGv_i64 tcg_rn = tcg_temp_new_i64(); | |
12311 | TCGv_i64 tcg_rd = tcg_const_i64(0); | |
12312 | TCGv_i64 tcg_rd_hi = tcg_const_i64(0); | |
12313 | ||
12314 | for (i = 0; i < elements; i++) { | |
12315 | int e_rev = (i & 0xf) ^ revmask; | |
12316 | int off = e_rev * esize; | |
12317 | read_vec_element(s, tcg_rn, rn, i, size); | |
12318 | if (off >= 64) { | |
12319 | tcg_gen_deposit_i64(tcg_rd_hi, tcg_rd_hi, | |
12320 | tcg_rn, off - 64, esize); | |
12321 | } else { | |
12322 | tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_rn, off, esize); | |
12323 | } | |
12324 | } | |
12325 | write_vec_element(s, tcg_rd, rd, 0, MO_64); | |
12326 | write_vec_element(s, tcg_rd_hi, rd, 1, MO_64); | |
12327 | ||
12328 | tcg_temp_free_i64(tcg_rd_hi); | |
12329 | tcg_temp_free_i64(tcg_rd); | |
12330 | tcg_temp_free_i64(tcg_rn); | |
12331 | } | |
12332 | } | |
12333 | ||
6781fa11 PM |
12334 | static void handle_2misc_pairwise(DisasContext *s, int opcode, bool u, |
12335 | bool is_q, int size, int rn, int rd) | |
12336 | { | |
12337 | /* Implement the pairwise operations from 2-misc: | |
12338 | * SADDLP, UADDLP, SADALP, UADALP. | |
12339 | * These all add pairs of elements in the input to produce a | |
12340 | * double-width result element in the output (possibly accumulating). | |
12341 | */ | |
12342 | bool accum = (opcode == 0x6); | |
12343 | int maxpass = is_q ? 2 : 1; | |
12344 | int pass; | |
12345 | TCGv_i64 tcg_res[2]; | |
12346 | ||
12347 | if (size == 2) { | |
12348 | /* 32 + 32 -> 64 op */ | |
14776ab5 | 12349 | MemOp memop = size + (u ? 0 : MO_SIGN); |
6781fa11 PM |
12350 | |
12351 | for (pass = 0; pass < maxpass; pass++) { | |
12352 | TCGv_i64 tcg_op1 = tcg_temp_new_i64(); | |
12353 | TCGv_i64 tcg_op2 = tcg_temp_new_i64(); | |
12354 | ||
12355 | tcg_res[pass] = tcg_temp_new_i64(); | |
12356 | ||
12357 | read_vec_element(s, tcg_op1, rn, pass * 2, memop); | |
12358 | read_vec_element(s, tcg_op2, rn, pass * 2 + 1, memop); | |
12359 | tcg_gen_add_i64(tcg_res[pass], tcg_op1, tcg_op2); | |
12360 | if (accum) { | |
12361 | read_vec_element(s, tcg_op1, rd, pass, MO_64); | |
12362 | tcg_gen_add_i64(tcg_res[pass], tcg_res[pass], tcg_op1); | |
12363 | } | |
12364 | ||
12365 | tcg_temp_free_i64(tcg_op1); | |
12366 | tcg_temp_free_i64(tcg_op2); | |
12367 | } | |
12368 | } else { | |
12369 | for (pass = 0; pass < maxpass; pass++) { | |
12370 | TCGv_i64 tcg_op = tcg_temp_new_i64(); | |
039f4e80 PM |
12371 | NeonGenOne64OpFn *genfn; |
12372 | static NeonGenOne64OpFn * const fns[2][2] = { | |
6781fa11 PM |
12373 | { gen_helper_neon_addlp_s8, gen_helper_neon_addlp_u8 }, |
12374 | { gen_helper_neon_addlp_s16, gen_helper_neon_addlp_u16 }, | |
12375 | }; | |
12376 | ||
12377 | genfn = fns[size][u]; | |
12378 | ||
12379 | tcg_res[pass] = tcg_temp_new_i64(); | |
12380 | ||
12381 | read_vec_element(s, tcg_op, rn, pass, MO_64); | |
12382 | genfn(tcg_res[pass], tcg_op); | |
12383 | ||
12384 | if (accum) { | |
12385 | read_vec_element(s, tcg_op, rd, pass, MO_64); | |
12386 | if (size == 0) { | |
12387 | gen_helper_neon_addl_u16(tcg_res[pass], | |
12388 | tcg_res[pass], tcg_op); | |
12389 | } else { | |
12390 | gen_helper_neon_addl_u32(tcg_res[pass], | |
12391 | tcg_res[pass], tcg_op); | |
12392 | } | |
12393 | } | |
12394 | tcg_temp_free_i64(tcg_op); | |
12395 | } | |
12396 | } | |
12397 | if (!is_q) { | |
12398 | tcg_res[1] = tcg_const_i64(0); | |
12399 | } | |
12400 | for (pass = 0; pass < 2; pass++) { | |
12401 | write_vec_element(s, tcg_res[pass], rd, pass, MO_64); | |
12402 | tcg_temp_free_i64(tcg_res[pass]); | |
12403 | } | |
12404 | } | |
12405 | ||
73a81d10 PM |
12406 | static void handle_shll(DisasContext *s, bool is_q, int size, int rn, int rd) |
12407 | { | |
12408 | /* Implement SHLL and SHLL2 */ | |
12409 | int pass; | |
12410 | int part = is_q ? 2 : 0; | |
12411 | TCGv_i64 tcg_res[2]; | |
12412 | ||
12413 | for (pass = 0; pass < 2; pass++) { | |
12414 | static NeonGenWidenFn * const widenfns[3] = { | |
12415 | gen_helper_neon_widen_u8, | |
12416 | gen_helper_neon_widen_u16, | |
12417 | tcg_gen_extu_i32_i64, | |
12418 | }; | |
12419 | NeonGenWidenFn *widenfn = widenfns[size]; | |
12420 | TCGv_i32 tcg_op = tcg_temp_new_i32(); | |
12421 | ||
12422 | read_vec_element_i32(s, tcg_op, rn, part + pass, MO_32); | |
12423 | tcg_res[pass] = tcg_temp_new_i64(); | |
12424 | widenfn(tcg_res[pass], tcg_op); | |
12425 | tcg_gen_shli_i64(tcg_res[pass], tcg_res[pass], 8 << size); | |
12426 | ||
12427 | tcg_temp_free_i32(tcg_op); | |
12428 | } | |
12429 | ||
12430 | for (pass = 0; pass < 2; pass++) { | |
12431 | write_vec_element(s, tcg_res[pass], rd, pass, MO_64); | |
12432 | tcg_temp_free_i64(tcg_res[pass]); | |
12433 | } | |
12434 | } | |
12435 | ||
4ce31af4 | 12436 | /* AdvSIMD two reg misc |
384b26fb AB |
12437 | * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0 |
12438 | * +---+---+---+-----------+------+-----------+--------+-----+------+------+ | |
12439 | * | 0 | Q | U | 0 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd | | |
12440 | * +---+---+---+-----------+------+-----------+--------+-----+------+------+ | |
12441 | */ | |
12442 | static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn) | |
12443 | { | |
45aecc6d PM |
12444 | int size = extract32(insn, 22, 2); |
12445 | int opcode = extract32(insn, 12, 5); | |
12446 | bool u = extract32(insn, 29, 1); | |
12447 | bool is_q = extract32(insn, 30, 1); | |
94b6c911 PM |
12448 | int rn = extract32(insn, 5, 5); |
12449 | int rd = extract32(insn, 0, 5); | |
04c7c6c2 PM |
12450 | bool need_fpstatus = false; |
12451 | bool need_rmode = false; | |
12452 | int rmode = -1; | |
12453 | TCGv_i32 tcg_rmode; | |
12454 | TCGv_ptr tcg_fpstatus; | |
45aecc6d PM |
12455 | |
12456 | switch (opcode) { | |
12457 | case 0x0: /* REV64, REV32 */ | |
12458 | case 0x1: /* REV16 */ | |
39d82118 | 12459 | handle_rev(s, opcode, u, is_q, size, rn, rd); |
45aecc6d | 12460 | return; |
86cbc418 PM |
12461 | case 0x5: /* CNT, NOT, RBIT */ |
12462 | if (u && size == 0) { | |
377ef731 | 12463 | /* NOT */ |
86cbc418 PM |
12464 | break; |
12465 | } else if (u && size == 1) { | |
12466 | /* RBIT */ | |
12467 | break; | |
12468 | } else if (!u && size == 0) { | |
12469 | /* CNT */ | |
12470 | break; | |
45aecc6d | 12471 | } |
86cbc418 | 12472 | unallocated_encoding(s); |
45aecc6d | 12473 | return; |
d980fd59 PM |
12474 | case 0x12: /* XTN, XTN2, SQXTUN, SQXTUN2 */ |
12475 | case 0x14: /* SQXTN, SQXTN2, UQXTN, UQXTN2 */ | |
12476 | if (size == 3) { | |
12477 | unallocated_encoding(s); | |
12478 | return; | |
12479 | } | |
8c6afa6a PM |
12480 | if (!fp_access_check(s)) { |
12481 | return; | |
12482 | } | |
12483 | ||
5201c136 | 12484 | handle_2misc_narrow(s, false, opcode, u, is_q, size, rn, rd); |
d980fd59 | 12485 | return; |
45aecc6d | 12486 | case 0x4: /* CLS, CLZ */ |
b05c3068 AB |
12487 | if (size == 3) { |
12488 | unallocated_encoding(s); | |
12489 | return; | |
12490 | } | |
12491 | break; | |
12492 | case 0x2: /* SADDLP, UADDLP */ | |
45aecc6d | 12493 | case 0x6: /* SADALP, UADALP */ |
45aecc6d PM |
12494 | if (size == 3) { |
12495 | unallocated_encoding(s); | |
12496 | return; | |
12497 | } | |
8c6afa6a PM |
12498 | if (!fp_access_check(s)) { |
12499 | return; | |
12500 | } | |
6781fa11 | 12501 | handle_2misc_pairwise(s, opcode, u, is_q, size, rn, rd); |
45aecc6d PM |
12502 | return; |
12503 | case 0x13: /* SHLL, SHLL2 */ | |
12504 | if (u == 0 || size == 3) { | |
12505 | unallocated_encoding(s); | |
12506 | return; | |
12507 | } | |
8c6afa6a PM |
12508 | if (!fp_access_check(s)) { |
12509 | return; | |
12510 | } | |
73a81d10 | 12511 | handle_shll(s, is_q, size, rn, rd); |
45aecc6d PM |
12512 | return; |
12513 | case 0xa: /* CMLT */ | |
12514 | if (u == 1) { | |
12515 | unallocated_encoding(s); | |
12516 | return; | |
12517 | } | |
12518 | /* fall through */ | |
45aecc6d PM |
12519 | case 0x8: /* CMGT, CMGE */ |
12520 | case 0x9: /* CMEQ, CMLE */ | |
12521 | case 0xb: /* ABS, NEG */ | |
94b6c911 PM |
12522 | if (size == 3 && !is_q) { |
12523 | unallocated_encoding(s); | |
12524 | return; | |
12525 | } | |
12526 | break; | |
12527 | case 0x3: /* SUQADD, USQADD */ | |
09e03735 AB |
12528 | if (size == 3 && !is_q) { |
12529 | unallocated_encoding(s); | |
12530 | return; | |
12531 | } | |
8c6afa6a PM |
12532 | if (!fp_access_check(s)) { |
12533 | return; | |
12534 | } | |
09e03735 AB |
12535 | handle_2misc_satacc(s, false, u, is_q, size, rn, rd); |
12536 | return; | |
94b6c911 | 12537 | case 0x7: /* SQABS, SQNEG */ |
45aecc6d PM |
12538 | if (size == 3 && !is_q) { |
12539 | unallocated_encoding(s); | |
12540 | return; | |
12541 | } | |
0a79bc87 | 12542 | break; |
45aecc6d | 12543 | case 0xc ... 0xf: |
6bea2563 | 12544 | case 0x16 ... 0x1f: |
45aecc6d PM |
12545 | { |
12546 | /* Floating point: U, size[1] and opcode indicate operation; | |
12547 | * size[0] indicates single or double precision. | |
12548 | */ | |
10113b69 | 12549 | int is_double = extract32(size, 0, 1); |
45aecc6d | 12550 | opcode |= (extract32(size, 1, 1) << 5) | (u << 6); |
10113b69 | 12551 | size = is_double ? 3 : 2; |
45aecc6d | 12552 | switch (opcode) { |
f93d0138 PM |
12553 | case 0x2f: /* FABS */ |
12554 | case 0x6f: /* FNEG */ | |
12555 | if (size == 3 && !is_q) { | |
12556 | unallocated_encoding(s); | |
12557 | return; | |
12558 | } | |
12559 | break; | |
10113b69 AB |
12560 | case 0x1d: /* SCVTF */ |
12561 | case 0x5d: /* UCVTF */ | |
12562 | { | |
12563 | bool is_signed = (opcode == 0x1d) ? true : false; | |
12564 | int elements = is_double ? 2 : is_q ? 4 : 2; | |
12565 | if (is_double && !is_q) { | |
12566 | unallocated_encoding(s); | |
12567 | return; | |
12568 | } | |
8c6afa6a PM |
12569 | if (!fp_access_check(s)) { |
12570 | return; | |
12571 | } | |
10113b69 AB |
12572 | handle_simd_intfp_conv(s, rd, rn, elements, is_signed, 0, size); |
12573 | return; | |
12574 | } | |
8908f4d1 AB |
12575 | case 0x2c: /* FCMGT (zero) */ |
12576 | case 0x2d: /* FCMEQ (zero) */ | |
12577 | case 0x2e: /* FCMLT (zero) */ | |
12578 | case 0x6c: /* FCMGE (zero) */ | |
12579 | case 0x6d: /* FCMLE (zero) */ | |
12580 | if (size == 3 && !is_q) { | |
12581 | unallocated_encoding(s); | |
12582 | return; | |
12583 | } | |
12584 | handle_2misc_fcmp_zero(s, opcode, false, u, is_q, size, rn, rd); | |
12585 | return; | |
f612537e AB |
12586 | case 0x7f: /* FSQRT */ |
12587 | if (size == 3 && !is_q) { | |
12588 | unallocated_encoding(s); | |
12589 | return; | |
12590 | } | |
12591 | break; | |
04c7c6c2 PM |
12592 | case 0x1a: /* FCVTNS */ |
12593 | case 0x1b: /* FCVTMS */ | |
12594 | case 0x3a: /* FCVTPS */ | |
12595 | case 0x3b: /* FCVTZS */ | |
12596 | case 0x5a: /* FCVTNU */ | |
12597 | case 0x5b: /* FCVTMU */ | |
12598 | case 0x7a: /* FCVTPU */ | |
12599 | case 0x7b: /* FCVTZU */ | |
12600 | need_fpstatus = true; | |
12601 | need_rmode = true; | |
12602 | rmode = extract32(opcode, 5, 1) | (extract32(opcode, 0, 1) << 1); | |
12603 | if (size == 3 && !is_q) { | |
12604 | unallocated_encoding(s); | |
12605 | return; | |
12606 | } | |
12607 | break; | |
12608 | case 0x5c: /* FCVTAU */ | |
12609 | case 0x1c: /* FCVTAS */ | |
12610 | need_fpstatus = true; | |
12611 | need_rmode = true; | |
12612 | rmode = FPROUNDING_TIEAWAY; | |
12613 | if (size == 3 && !is_q) { | |
12614 | unallocated_encoding(s); | |
12615 | return; | |
12616 | } | |
12617 | break; | |
b6d4443a AB |
12618 | case 0x3c: /* URECPE */ |
12619 | if (size == 3) { | |
12620 | unallocated_encoding(s); | |
12621 | return; | |
12622 | } | |
12623 | /* fall through */ | |
12624 | case 0x3d: /* FRECPE */ | |
c2fb418e AB |
12625 | case 0x7d: /* FRSQRTE */ |
12626 | if (size == 3 && !is_q) { | |
12627 | unallocated_encoding(s); | |
12628 | return; | |
12629 | } | |
8c6afa6a PM |
12630 | if (!fp_access_check(s)) { |
12631 | return; | |
12632 | } | |
b6d4443a AB |
12633 | handle_2misc_reciprocal(s, opcode, false, u, is_q, size, rn, rd); |
12634 | return; | |
5553955e PM |
12635 | case 0x56: /* FCVTXN, FCVTXN2 */ |
12636 | if (size == 2) { | |
12637 | unallocated_encoding(s); | |
12638 | return; | |
12639 | } | |
12640 | /* fall through */ | |
45aecc6d | 12641 | case 0x16: /* FCVTN, FCVTN2 */ |
261a5b4d PM |
12642 | /* handle_2misc_narrow does a 2*size -> size operation, but these |
12643 | * instructions encode the source size rather than dest size. | |
12644 | */ | |
8c6afa6a PM |
12645 | if (!fp_access_check(s)) { |
12646 | return; | |
12647 | } | |
5201c136 | 12648 | handle_2misc_narrow(s, false, opcode, 0, is_q, size - 1, rn, rd); |
261a5b4d | 12649 | return; |
45aecc6d | 12650 | case 0x17: /* FCVTL, FCVTL2 */ |
8c6afa6a PM |
12651 | if (!fp_access_check(s)) { |
12652 | return; | |
12653 | } | |
931c8cc2 PM |
12654 | handle_2misc_widening(s, opcode, is_q, size, rn, rd); |
12655 | return; | |
45aecc6d PM |
12656 | case 0x18: /* FRINTN */ |
12657 | case 0x19: /* FRINTM */ | |
45aecc6d PM |
12658 | case 0x38: /* FRINTP */ |
12659 | case 0x39: /* FRINTZ */ | |
03df01ed PM |
12660 | need_rmode = true; |
12661 | rmode = extract32(opcode, 5, 1) | (extract32(opcode, 0, 1) << 1); | |
12662 | /* fall through */ | |
12663 | case 0x59: /* FRINTX */ | |
12664 | case 0x79: /* FRINTI */ | |
12665 | need_fpstatus = true; | |
12666 | if (size == 3 && !is_q) { | |
12667 | unallocated_encoding(s); | |
12668 | return; | |
12669 | } | |
12670 | break; | |
12671 | case 0x58: /* FRINTA */ | |
12672 | need_rmode = true; | |
12673 | rmode = FPROUNDING_TIEAWAY; | |
12674 | need_fpstatus = true; | |
12675 | if (size == 3 && !is_q) { | |
12676 | unallocated_encoding(s); | |
12677 | return; | |
12678 | } | |
12679 | break; | |
45aecc6d | 12680 | case 0x7c: /* URSQRTE */ |
c2fb418e AB |
12681 | if (size == 3) { |
12682 | unallocated_encoding(s); | |
12683 | return; | |
12684 | } | |
c2fb418e | 12685 | break; |
6bea2563 RH |
12686 | case 0x1e: /* FRINT32Z */ |
12687 | case 0x1f: /* FRINT64Z */ | |
12688 | need_rmode = true; | |
12689 | rmode = FPROUNDING_ZERO; | |
12690 | /* fall through */ | |
12691 | case 0x5e: /* FRINT32X */ | |
12692 | case 0x5f: /* FRINT64X */ | |
12693 | need_fpstatus = true; | |
12694 | if ((size == 3 && !is_q) || !dc_isar_feature(aa64_frint, s)) { | |
12695 | unallocated_encoding(s); | |
12696 | return; | |
12697 | } | |
12698 | break; | |
45aecc6d PM |
12699 | default: |
12700 | unallocated_encoding(s); | |
12701 | return; | |
12702 | } | |
12703 | break; | |
12704 | } | |
12705 | default: | |
12706 | unallocated_encoding(s); | |
12707 | return; | |
12708 | } | |
94b6c911 | 12709 | |
8c6afa6a PM |
12710 | if (!fp_access_check(s)) { |
12711 | return; | |
12712 | } | |
12713 | ||
9b049916 | 12714 | if (need_fpstatus || need_rmode) { |
d81ce0ef | 12715 | tcg_fpstatus = get_fpstatus_ptr(false); |
04c7c6c2 | 12716 | } else { |
f764718d | 12717 | tcg_fpstatus = NULL; |
04c7c6c2 PM |
12718 | } |
12719 | if (need_rmode) { | |
12720 | tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode)); | |
9b049916 | 12721 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); |
04c7c6c2 | 12722 | } else { |
f764718d | 12723 | tcg_rmode = NULL; |
04c7c6c2 PM |
12724 | } |
12725 | ||
377ef731 RH |
12726 | switch (opcode) { |
12727 | case 0x5: | |
12728 | if (u && size == 0) { /* NOT */ | |
12729 | gen_gvec_fn2(s, is_q, rd, rn, tcg_gen_gvec_not, 0); | |
12730 | return; | |
12731 | } | |
12732 | break; | |
6b375d35 | 12733 | case 0x8: /* CMGT, CMGE */ |
69d5e2bf RH |
12734 | if (u) { |
12735 | gen_gvec_fn2(s, is_q, rd, rn, gen_gvec_cge0, size); | |
12736 | } else { | |
12737 | gen_gvec_fn2(s, is_q, rd, rn, gen_gvec_cgt0, size); | |
12738 | } | |
6b375d35 RH |
12739 | return; |
12740 | case 0x9: /* CMEQ, CMLE */ | |
69d5e2bf RH |
12741 | if (u) { |
12742 | gen_gvec_fn2(s, is_q, rd, rn, gen_gvec_cle0, size); | |
12743 | } else { | |
12744 | gen_gvec_fn2(s, is_q, rd, rn, gen_gvec_ceq0, size); | |
12745 | } | |
6b375d35 RH |
12746 | return; |
12747 | case 0xa: /* CMLT */ | |
69d5e2bf | 12748 | gen_gvec_fn2(s, is_q, rd, rn, gen_gvec_clt0, size); |
6b375d35 | 12749 | return; |
377ef731 | 12750 | case 0xb: |
4e027a71 | 12751 | if (u) { /* ABS, NEG */ |
377ef731 | 12752 | gen_gvec_fn2(s, is_q, rd, rn, tcg_gen_gvec_neg, size); |
4e027a71 RH |
12753 | } else { |
12754 | gen_gvec_fn2(s, is_q, rd, rn, tcg_gen_gvec_abs, size); | |
377ef731 | 12755 | } |
4e027a71 | 12756 | return; |
377ef731 RH |
12757 | } |
12758 | ||
94b6c911 PM |
12759 | if (size == 3) { |
12760 | /* All 64-bit element operations can be shared with scalar 2misc */ | |
12761 | int pass; | |
12762 | ||
a8766e31 RH |
12763 | /* Coverity claims (size == 3 && !is_q) has been eliminated |
12764 | * from all paths leading to here. | |
12765 | */ | |
12766 | tcg_debug_assert(is_q); | |
12767 | for (pass = 0; pass < 2; pass++) { | |
94b6c911 PM |
12768 | TCGv_i64 tcg_op = tcg_temp_new_i64(); |
12769 | TCGv_i64 tcg_res = tcg_temp_new_i64(); | |
12770 | ||
12771 | read_vec_element(s, tcg_op, rn, pass, MO_64); | |
12772 | ||
04c7c6c2 PM |
12773 | handle_2misc_64(s, opcode, u, tcg_res, tcg_op, |
12774 | tcg_rmode, tcg_fpstatus); | |
94b6c911 PM |
12775 | |
12776 | write_vec_element(s, tcg_res, rd, pass, MO_64); | |
12777 | ||
12778 | tcg_temp_free_i64(tcg_res); | |
12779 | tcg_temp_free_i64(tcg_op); | |
12780 | } | |
12781 | } else { | |
12782 | int pass; | |
12783 | ||
12784 | for (pass = 0; pass < (is_q ? 4 : 2); pass++) { | |
12785 | TCGv_i32 tcg_op = tcg_temp_new_i32(); | |
12786 | TCGv_i32 tcg_res = tcg_temp_new_i32(); | |
94b6c911 PM |
12787 | |
12788 | read_vec_element_i32(s, tcg_op, rn, pass, MO_32); | |
12789 | ||
12790 | if (size == 2) { | |
12791 | /* Special cases for 32 bit elements */ | |
12792 | switch (opcode) { | |
b05c3068 AB |
12793 | case 0x4: /* CLS */ |
12794 | if (u) { | |
7539a012 | 12795 | tcg_gen_clzi_i32(tcg_res, tcg_op, 32); |
b05c3068 | 12796 | } else { |
bc21dbcc | 12797 | tcg_gen_clrsb_i32(tcg_res, tcg_op); |
b05c3068 AB |
12798 | } |
12799 | break; | |
0a79bc87 AB |
12800 | case 0x7: /* SQABS, SQNEG */ |
12801 | if (u) { | |
12802 | gen_helper_neon_qneg_s32(tcg_res, cpu_env, tcg_op); | |
12803 | } else { | |
12804 | gen_helper_neon_qabs_s32(tcg_res, cpu_env, tcg_op); | |
12805 | } | |
12806 | break; | |
f93d0138 PM |
12807 | case 0x2f: /* FABS */ |
12808 | gen_helper_vfp_abss(tcg_res, tcg_op); | |
12809 | break; | |
12810 | case 0x6f: /* FNEG */ | |
12811 | gen_helper_vfp_negs(tcg_res, tcg_op); | |
12812 | break; | |
f612537e AB |
12813 | case 0x7f: /* FSQRT */ |
12814 | gen_helper_vfp_sqrts(tcg_res, tcg_op, cpu_env); | |
12815 | break; | |
04c7c6c2 PM |
12816 | case 0x1a: /* FCVTNS */ |
12817 | case 0x1b: /* FCVTMS */ | |
12818 | case 0x1c: /* FCVTAS */ | |
12819 | case 0x3a: /* FCVTPS */ | |
12820 | case 0x3b: /* FCVTZS */ | |
12821 | { | |
12822 | TCGv_i32 tcg_shift = tcg_const_i32(0); | |
12823 | gen_helper_vfp_tosls(tcg_res, tcg_op, | |
12824 | tcg_shift, tcg_fpstatus); | |
12825 | tcg_temp_free_i32(tcg_shift); | |
12826 | break; | |
12827 | } | |
12828 | case 0x5a: /* FCVTNU */ | |
12829 | case 0x5b: /* FCVTMU */ | |
12830 | case 0x5c: /* FCVTAU */ | |
12831 | case 0x7a: /* FCVTPU */ | |
12832 | case 0x7b: /* FCVTZU */ | |
12833 | { | |
12834 | TCGv_i32 tcg_shift = tcg_const_i32(0); | |
12835 | gen_helper_vfp_touls(tcg_res, tcg_op, | |
12836 | tcg_shift, tcg_fpstatus); | |
12837 | tcg_temp_free_i32(tcg_shift); | |
12838 | break; | |
12839 | } | |
03df01ed PM |
12840 | case 0x18: /* FRINTN */ |
12841 | case 0x19: /* FRINTM */ | |
12842 | case 0x38: /* FRINTP */ | |
12843 | case 0x39: /* FRINTZ */ | |
12844 | case 0x58: /* FRINTA */ | |
12845 | case 0x79: /* FRINTI */ | |
12846 | gen_helper_rints(tcg_res, tcg_op, tcg_fpstatus); | |
12847 | break; | |
12848 | case 0x59: /* FRINTX */ | |
12849 | gen_helper_rints_exact(tcg_res, tcg_op, tcg_fpstatus); | |
12850 | break; | |
c2fb418e | 12851 | case 0x7c: /* URSQRTE */ |
fe6fb4be | 12852 | gen_helper_rsqrte_u32(tcg_res, tcg_op); |
c2fb418e | 12853 | break; |
6bea2563 RH |
12854 | case 0x1e: /* FRINT32Z */ |
12855 | case 0x5e: /* FRINT32X */ | |
12856 | gen_helper_frint32_s(tcg_res, tcg_op, tcg_fpstatus); | |
12857 | break; | |
12858 | case 0x1f: /* FRINT64Z */ | |
12859 | case 0x5f: /* FRINT64X */ | |
12860 | gen_helper_frint64_s(tcg_res, tcg_op, tcg_fpstatus); | |
12861 | break; | |
94b6c911 PM |
12862 | default: |
12863 | g_assert_not_reached(); | |
12864 | } | |
12865 | } else { | |
12866 | /* Use helpers for 8 and 16 bit elements */ | |
12867 | switch (opcode) { | |
86cbc418 PM |
12868 | case 0x5: /* CNT, RBIT */ |
12869 | /* For these two insns size is part of the opcode specifier | |
12870 | * (handled earlier); they always operate on byte elements. | |
12871 | */ | |
12872 | if (u) { | |
12873 | gen_helper_neon_rbit_u8(tcg_res, tcg_op); | |
12874 | } else { | |
12875 | gen_helper_neon_cnt_u8(tcg_res, tcg_op); | |
12876 | } | |
12877 | break; | |
0a79bc87 AB |
12878 | case 0x7: /* SQABS, SQNEG */ |
12879 | { | |
12880 | NeonGenOneOpEnvFn *genfn; | |
12881 | static NeonGenOneOpEnvFn * const fns[2][2] = { | |
12882 | { gen_helper_neon_qabs_s8, gen_helper_neon_qneg_s8 }, | |
12883 | { gen_helper_neon_qabs_s16, gen_helper_neon_qneg_s16 }, | |
12884 | }; | |
12885 | genfn = fns[size][u]; | |
12886 | genfn(tcg_res, cpu_env, tcg_op); | |
12887 | break; | |
12888 | } | |
b05c3068 AB |
12889 | case 0x4: /* CLS, CLZ */ |
12890 | if (u) { | |
12891 | if (size == 0) { | |
12892 | gen_helper_neon_clz_u8(tcg_res, tcg_op); | |
12893 | } else { | |
12894 | gen_helper_neon_clz_u16(tcg_res, tcg_op); | |
12895 | } | |
12896 | } else { | |
12897 | if (size == 0) { | |
12898 | gen_helper_neon_cls_s8(tcg_res, tcg_op); | |
12899 | } else { | |
12900 | gen_helper_neon_cls_s16(tcg_res, tcg_op); | |
12901 | } | |
12902 | } | |
12903 | break; | |
94b6c911 PM |
12904 | default: |
12905 | g_assert_not_reached(); | |
12906 | } | |
12907 | } | |
12908 | ||
12909 | write_vec_element_i32(s, tcg_res, rd, pass, MO_32); | |
12910 | ||
12911 | tcg_temp_free_i32(tcg_res); | |
12912 | tcg_temp_free_i32(tcg_op); | |
12913 | } | |
12914 | } | |
4ff55bcb | 12915 | clear_vec_high(s, is_q, rd); |
04c7c6c2 PM |
12916 | |
12917 | if (need_rmode) { | |
9b049916 | 12918 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); |
04c7c6c2 PM |
12919 | tcg_temp_free_i32(tcg_rmode); |
12920 | } | |
12921 | if (need_fpstatus) { | |
12922 | tcg_temp_free_ptr(tcg_fpstatus); | |
12923 | } | |
384b26fb AB |
12924 | } |
12925 | ||
5d432be6 AB |
12926 | /* AdvSIMD [scalar] two register miscellaneous (FP16) |
12927 | * | |
12928 | * 31 30 29 28 27 24 23 22 21 17 16 12 11 10 9 5 4 0 | |
12929 | * +---+---+---+---+---------+---+-------------+--------+-----+------+------+ | |
12930 | * | 0 | Q | U | S | 1 1 1 0 | a | 1 1 1 1 0 0 | opcode | 1 0 | Rn | Rd | | |
12931 | * +---+---+---+---+---------+---+-------------+--------+-----+------+------+ | |
12932 | * mask: 1000 1111 0111 1110 0000 1100 0000 0000 0x8f7e 0c00 | |
12933 | * val: 0000 1110 0111 1000 0000 1000 0000 0000 0x0e78 0800 | |
12934 | * | |
12935 | * This actually covers two groups where scalar access is governed by | |
12936 | * bit 28. A bunch of the instructions (float to integral) only exist | |
12937 | * in the vector form and are un-allocated for the scalar decode. Also | |
12938 | * in the scalar decode Q is always 1. | |
12939 | */ | |
12940 | static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn) | |
12941 | { | |
6109aea2 AB |
12942 | int fpop, opcode, a, u; |
12943 | int rn, rd; | |
12944 | bool is_q; | |
12945 | bool is_scalar; | |
12946 | bool only_in_vector = false; | |
12947 | ||
12948 | int pass; | |
12949 | TCGv_i32 tcg_rmode = NULL; | |
12950 | TCGv_ptr tcg_fpstatus = NULL; | |
12951 | bool need_rmode = false; | |
15f8a233 | 12952 | bool need_fpst = true; |
6109aea2 | 12953 | int rmode; |
5d432be6 | 12954 | |
5763190f | 12955 | if (!dc_isar_feature(aa64_fp16, s)) { |
5d432be6 AB |
12956 | unallocated_encoding(s); |
12957 | return; | |
12958 | } | |
12959 | ||
6109aea2 AB |
12960 | rd = extract32(insn, 0, 5); |
12961 | rn = extract32(insn, 5, 5); | |
5d432be6 | 12962 | |
5d432be6 | 12963 | a = extract32(insn, 23, 1); |
6109aea2 AB |
12964 | u = extract32(insn, 29, 1); |
12965 | is_scalar = extract32(insn, 28, 1); | |
12966 | is_q = extract32(insn, 30, 1); | |
12967 | ||
12968 | opcode = extract32(insn, 12, 5); | |
5d432be6 | 12969 | fpop = deposit32(opcode, 5, 1, a); |
6109aea2 | 12970 | fpop = deposit32(fpop, 6, 1, u); |
5d432be6 | 12971 | |
7d4dd1a7 AB |
12972 | rd = extract32(insn, 0, 5); |
12973 | rn = extract32(insn, 5, 5); | |
12974 | ||
5d432be6 | 12975 | switch (fpop) { |
93193190 AB |
12976 | case 0x1d: /* SCVTF */ |
12977 | case 0x5d: /* UCVTF */ | |
12978 | { | |
12979 | int elements; | |
12980 | ||
12981 | if (is_scalar) { | |
12982 | elements = 1; | |
12983 | } else { | |
12984 | elements = (is_q ? 8 : 4); | |
12985 | } | |
12986 | ||
12987 | if (!fp_access_check(s)) { | |
12988 | return; | |
12989 | } | |
12990 | handle_simd_intfp_conv(s, rd, rn, elements, !u, 0, MO_16); | |
12991 | return; | |
12992 | } | |
7d4dd1a7 AB |
12993 | break; |
12994 | case 0x2c: /* FCMGT (zero) */ | |
12995 | case 0x2d: /* FCMEQ (zero) */ | |
12996 | case 0x2e: /* FCMLT (zero) */ | |
12997 | case 0x6c: /* FCMGE (zero) */ | |
12998 | case 0x6d: /* FCMLE (zero) */ | |
12999 | handle_2misc_fcmp_zero(s, fpop, is_scalar, 0, is_q, MO_16, rn, rd); | |
13000 | return; | |
fbd06e1e | 13001 | case 0x3d: /* FRECPE */ |
98695028 | 13002 | case 0x3f: /* FRECPX */ |
fbd06e1e | 13003 | break; |
6109aea2 AB |
13004 | case 0x18: /* FRINTN */ |
13005 | need_rmode = true; | |
13006 | only_in_vector = true; | |
13007 | rmode = FPROUNDING_TIEEVEN; | |
13008 | break; | |
13009 | case 0x19: /* FRINTM */ | |
13010 | need_rmode = true; | |
13011 | only_in_vector = true; | |
13012 | rmode = FPROUNDING_NEGINF; | |
13013 | break; | |
13014 | case 0x38: /* FRINTP */ | |
13015 | need_rmode = true; | |
13016 | only_in_vector = true; | |
13017 | rmode = FPROUNDING_POSINF; | |
13018 | break; | |
13019 | case 0x39: /* FRINTZ */ | |
13020 | need_rmode = true; | |
13021 | only_in_vector = true; | |
13022 | rmode = FPROUNDING_ZERO; | |
13023 | break; | |
13024 | case 0x58: /* FRINTA */ | |
13025 | need_rmode = true; | |
13026 | only_in_vector = true; | |
13027 | rmode = FPROUNDING_TIEAWAY; | |
13028 | break; | |
13029 | case 0x59: /* FRINTX */ | |
13030 | case 0x79: /* FRINTI */ | |
13031 | only_in_vector = true; | |
13032 | /* current rounding mode */ | |
13033 | break; | |
2df58130 AB |
13034 | case 0x1a: /* FCVTNS */ |
13035 | need_rmode = true; | |
13036 | rmode = FPROUNDING_TIEEVEN; | |
13037 | break; | |
13038 | case 0x1b: /* FCVTMS */ | |
13039 | need_rmode = true; | |
13040 | rmode = FPROUNDING_NEGINF; | |
13041 | break; | |
13042 | case 0x1c: /* FCVTAS */ | |
13043 | need_rmode = true; | |
13044 | rmode = FPROUNDING_TIEAWAY; | |
13045 | break; | |
13046 | case 0x3a: /* FCVTPS */ | |
13047 | need_rmode = true; | |
13048 | rmode = FPROUNDING_POSINF; | |
13049 | break; | |
13050 | case 0x3b: /* FCVTZS */ | |
13051 | need_rmode = true; | |
13052 | rmode = FPROUNDING_ZERO; | |
13053 | break; | |
13054 | case 0x5a: /* FCVTNU */ | |
13055 | need_rmode = true; | |
13056 | rmode = FPROUNDING_TIEEVEN; | |
13057 | break; | |
13058 | case 0x5b: /* FCVTMU */ | |
13059 | need_rmode = true; | |
13060 | rmode = FPROUNDING_NEGINF; | |
13061 | break; | |
13062 | case 0x5c: /* FCVTAU */ | |
13063 | need_rmode = true; | |
13064 | rmode = FPROUNDING_TIEAWAY; | |
13065 | break; | |
13066 | case 0x7a: /* FCVTPU */ | |
13067 | need_rmode = true; | |
13068 | rmode = FPROUNDING_POSINF; | |
13069 | break; | |
13070 | case 0x7b: /* FCVTZU */ | |
13071 | need_rmode = true; | |
13072 | rmode = FPROUNDING_ZERO; | |
13073 | break; | |
15f8a233 AB |
13074 | case 0x2f: /* FABS */ |
13075 | case 0x6f: /* FNEG */ | |
13076 | need_fpst = false; | |
13077 | break; | |
c625ff95 | 13078 | case 0x7d: /* FRSQRTE */ |
b96a54c7 AB |
13079 | case 0x7f: /* FSQRT (vector) */ |
13080 | break; | |
5d432be6 AB |
13081 | default: |
13082 | fprintf(stderr, "%s: insn %#04x fpop %#2x\n", __func__, insn, fpop); | |
13083 | g_assert_not_reached(); | |
13084 | } | |
13085 | ||
6109aea2 AB |
13086 | |
13087 | /* Check additional constraints for the scalar encoding */ | |
13088 | if (is_scalar) { | |
13089 | if (!is_q) { | |
13090 | unallocated_encoding(s); | |
13091 | return; | |
13092 | } | |
13093 | /* FRINTxx is only in the vector form */ | |
13094 | if (only_in_vector) { | |
13095 | unallocated_encoding(s); | |
13096 | return; | |
13097 | } | |
13098 | } | |
13099 | ||
13100 | if (!fp_access_check(s)) { | |
13101 | return; | |
13102 | } | |
13103 | ||
15f8a233 | 13104 | if (need_rmode || need_fpst) { |
6109aea2 AB |
13105 | tcg_fpstatus = get_fpstatus_ptr(true); |
13106 | } | |
13107 | ||
13108 | if (need_rmode) { | |
13109 | tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode)); | |
13110 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); | |
13111 | } | |
13112 | ||
13113 | if (is_scalar) { | |
3d99d931 | 13114 | TCGv_i32 tcg_op = read_fp_hreg(s, rn); |
2df58130 AB |
13115 | TCGv_i32 tcg_res = tcg_temp_new_i32(); |
13116 | ||
2df58130 AB |
13117 | switch (fpop) { |
13118 | case 0x1a: /* FCVTNS */ | |
13119 | case 0x1b: /* FCVTMS */ | |
13120 | case 0x1c: /* FCVTAS */ | |
13121 | case 0x3a: /* FCVTPS */ | |
13122 | case 0x3b: /* FCVTZS */ | |
13123 | gen_helper_advsimd_f16tosinth(tcg_res, tcg_op, tcg_fpstatus); | |
13124 | break; | |
fbd06e1e AB |
13125 | case 0x3d: /* FRECPE */ |
13126 | gen_helper_recpe_f16(tcg_res, tcg_op, tcg_fpstatus); | |
13127 | break; | |
98695028 AB |
13128 | case 0x3f: /* FRECPX */ |
13129 | gen_helper_frecpx_f16(tcg_res, tcg_op, tcg_fpstatus); | |
13130 | break; | |
2df58130 AB |
13131 | case 0x5a: /* FCVTNU */ |
13132 | case 0x5b: /* FCVTMU */ | |
13133 | case 0x5c: /* FCVTAU */ | |
13134 | case 0x7a: /* FCVTPU */ | |
13135 | case 0x7b: /* FCVTZU */ | |
13136 | gen_helper_advsimd_f16touinth(tcg_res, tcg_op, tcg_fpstatus); | |
13137 | break; | |
15f8a233 AB |
13138 | case 0x6f: /* FNEG */ |
13139 | tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000); | |
13140 | break; | |
c625ff95 AB |
13141 | case 0x7d: /* FRSQRTE */ |
13142 | gen_helper_rsqrte_f16(tcg_res, tcg_op, tcg_fpstatus); | |
13143 | break; | |
2df58130 AB |
13144 | default: |
13145 | g_assert_not_reached(); | |
13146 | } | |
13147 | ||
13148 | /* limit any sign extension going on */ | |
13149 | tcg_gen_andi_i32(tcg_res, tcg_res, 0xffff); | |
13150 | write_fp_sreg(s, rd, tcg_res); | |
13151 | ||
13152 | tcg_temp_free_i32(tcg_res); | |
13153 | tcg_temp_free_i32(tcg_op); | |
6109aea2 AB |
13154 | } else { |
13155 | for (pass = 0; pass < (is_q ? 8 : 4); pass++) { | |
13156 | TCGv_i32 tcg_op = tcg_temp_new_i32(); | |
13157 | TCGv_i32 tcg_res = tcg_temp_new_i32(); | |
13158 | ||
13159 | read_vec_element_i32(s, tcg_op, rn, pass, MO_16); | |
13160 | ||
13161 | switch (fpop) { | |
2df58130 AB |
13162 | case 0x1a: /* FCVTNS */ |
13163 | case 0x1b: /* FCVTMS */ | |
13164 | case 0x1c: /* FCVTAS */ | |
13165 | case 0x3a: /* FCVTPS */ | |
13166 | case 0x3b: /* FCVTZS */ | |
13167 | gen_helper_advsimd_f16tosinth(tcg_res, tcg_op, tcg_fpstatus); | |
13168 | break; | |
fbd06e1e AB |
13169 | case 0x3d: /* FRECPE */ |
13170 | gen_helper_recpe_f16(tcg_res, tcg_op, tcg_fpstatus); | |
13171 | break; | |
2df58130 AB |
13172 | case 0x5a: /* FCVTNU */ |
13173 | case 0x5b: /* FCVTMU */ | |
13174 | case 0x5c: /* FCVTAU */ | |
13175 | case 0x7a: /* FCVTPU */ | |
13176 | case 0x7b: /* FCVTZU */ | |
13177 | gen_helper_advsimd_f16touinth(tcg_res, tcg_op, tcg_fpstatus); | |
13178 | break; | |
6109aea2 AB |
13179 | case 0x18: /* FRINTN */ |
13180 | case 0x19: /* FRINTM */ | |
13181 | case 0x38: /* FRINTP */ | |
13182 | case 0x39: /* FRINTZ */ | |
13183 | case 0x58: /* FRINTA */ | |
13184 | case 0x79: /* FRINTI */ | |
13185 | gen_helper_advsimd_rinth(tcg_res, tcg_op, tcg_fpstatus); | |
13186 | break; | |
13187 | case 0x59: /* FRINTX */ | |
13188 | gen_helper_advsimd_rinth_exact(tcg_res, tcg_op, tcg_fpstatus); | |
13189 | break; | |
15f8a233 AB |
13190 | case 0x2f: /* FABS */ |
13191 | tcg_gen_andi_i32(tcg_res, tcg_op, 0x7fff); | |
13192 | break; | |
13193 | case 0x6f: /* FNEG */ | |
13194 | tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000); | |
13195 | break; | |
c625ff95 AB |
13196 | case 0x7d: /* FRSQRTE */ |
13197 | gen_helper_rsqrte_f16(tcg_res, tcg_op, tcg_fpstatus); | |
13198 | break; | |
b96a54c7 AB |
13199 | case 0x7f: /* FSQRT */ |
13200 | gen_helper_sqrt_f16(tcg_res, tcg_op, tcg_fpstatus); | |
13201 | break; | |
6109aea2 AB |
13202 | default: |
13203 | g_assert_not_reached(); | |
13204 | } | |
13205 | ||
13206 | write_vec_element_i32(s, tcg_res, rd, pass, MO_16); | |
13207 | ||
13208 | tcg_temp_free_i32(tcg_res); | |
13209 | tcg_temp_free_i32(tcg_op); | |
13210 | } | |
13211 | ||
13212 | clear_vec_high(s, is_q, rd); | |
13213 | } | |
13214 | ||
13215 | if (tcg_rmode) { | |
13216 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); | |
13217 | tcg_temp_free_i32(tcg_rmode); | |
13218 | } | |
13219 | ||
13220 | if (tcg_fpstatus) { | |
13221 | tcg_temp_free_ptr(tcg_fpstatus); | |
13222 | } | |
5d432be6 AB |
13223 | } |
13224 | ||
4ce31af4 | 13225 | /* AdvSIMD scalar x indexed element |
9f82e0ff PM |
13226 | * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0 |
13227 | * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+ | |
13228 | * | 0 1 | U | 1 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd | | |
13229 | * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+ | |
4ce31af4 | 13230 | * AdvSIMD vector x indexed element |
384b26fb AB |
13231 | * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0 |
13232 | * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+ | |
13233 | * | 0 | Q | U | 0 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd | | |
13234 | * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+ | |
13235 | */ | |
9f82e0ff | 13236 | static void disas_simd_indexed(DisasContext *s, uint32_t insn) |
384b26fb | 13237 | { |
f5e51e7f PM |
13238 | /* This encoding has two kinds of instruction: |
13239 | * normal, where we perform elt x idxelt => elt for each | |
13240 | * element in the vector | |
13241 | * long, where we perform elt x idxelt and generate a result of | |
13242 | * double the width of the input element | |
13243 | * The long ops have a 'part' specifier (ie come in INSN, INSN2 pairs). | |
13244 | */ | |
9f82e0ff | 13245 | bool is_scalar = extract32(insn, 28, 1); |
f5e51e7f PM |
13246 | bool is_q = extract32(insn, 30, 1); |
13247 | bool u = extract32(insn, 29, 1); | |
13248 | int size = extract32(insn, 22, 2); | |
13249 | int l = extract32(insn, 21, 1); | |
13250 | int m = extract32(insn, 20, 1); | |
13251 | /* Note that the Rm field here is only 4 bits, not 5 as it usually is */ | |
13252 | int rm = extract32(insn, 16, 4); | |
13253 | int opcode = extract32(insn, 12, 4); | |
13254 | int h = extract32(insn, 11, 1); | |
13255 | int rn = extract32(insn, 5, 5); | |
13256 | int rd = extract32(insn, 0, 5); | |
13257 | bool is_long = false; | |
d17b7cdc | 13258 | int is_fp = 0; |
5d265064 | 13259 | bool is_fp16 = false; |
f5e51e7f PM |
13260 | int index; |
13261 | TCGv_ptr fpst; | |
13262 | ||
5f81b1de RH |
13263 | switch (16 * u + opcode) { |
13264 | case 0x08: /* MUL */ | |
13265 | case 0x10: /* MLA */ | |
13266 | case 0x14: /* MLS */ | |
13267 | if (is_scalar) { | |
f5e51e7f PM |
13268 | unallocated_encoding(s); |
13269 | return; | |
13270 | } | |
13271 | break; | |
5f81b1de RH |
13272 | case 0x02: /* SMLAL, SMLAL2 */ |
13273 | case 0x12: /* UMLAL, UMLAL2 */ | |
13274 | case 0x06: /* SMLSL, SMLSL2 */ | |
13275 | case 0x16: /* UMLSL, UMLSL2 */ | |
13276 | case 0x0a: /* SMULL, SMULL2 */ | |
13277 | case 0x1a: /* UMULL, UMULL2 */ | |
9f82e0ff PM |
13278 | if (is_scalar) { |
13279 | unallocated_encoding(s); | |
13280 | return; | |
13281 | } | |
f5e51e7f PM |
13282 | is_long = true; |
13283 | break; | |
5f81b1de RH |
13284 | case 0x03: /* SQDMLAL, SQDMLAL2 */ |
13285 | case 0x07: /* SQDMLSL, SQDMLSL2 */ | |
13286 | case 0x0b: /* SQDMULL, SQDMULL2 */ | |
f5e51e7f | 13287 | is_long = true; |
f5e51e7f | 13288 | break; |
5f81b1de RH |
13289 | case 0x0c: /* SQDMULH */ |
13290 | case 0x0d: /* SQRDMULH */ | |
9f82e0ff | 13291 | break; |
5f81b1de RH |
13292 | case 0x01: /* FMLA */ |
13293 | case 0x05: /* FMLS */ | |
13294 | case 0x09: /* FMUL */ | |
13295 | case 0x19: /* FMULX */ | |
d17b7cdc | 13296 | is_fp = 1; |
f5e51e7f | 13297 | break; |
d345df7a RH |
13298 | case 0x1d: /* SQRDMLAH */ |
13299 | case 0x1f: /* SQRDMLSH */ | |
962fcbf2 | 13300 | if (!dc_isar_feature(aa64_rdm, s)) { |
d345df7a RH |
13301 | unallocated_encoding(s); |
13302 | return; | |
13303 | } | |
13304 | break; | |
26c470a7 RH |
13305 | case 0x0e: /* SDOT */ |
13306 | case 0x1e: /* UDOT */ | |
4977986c | 13307 | if (is_scalar || size != MO_32 || !dc_isar_feature(aa64_dp, s)) { |
26c470a7 RH |
13308 | unallocated_encoding(s); |
13309 | return; | |
13310 | } | |
13311 | break; | |
d17b7cdc RH |
13312 | case 0x11: /* FCMLA #0 */ |
13313 | case 0x13: /* FCMLA #90 */ | |
13314 | case 0x15: /* FCMLA #180 */ | |
13315 | case 0x17: /* FCMLA #270 */ | |
4dfabb6d | 13316 | if (is_scalar || !dc_isar_feature(aa64_fcma, s)) { |
d17b7cdc RH |
13317 | unallocated_encoding(s); |
13318 | return; | |
13319 | } | |
13320 | is_fp = 2; | |
13321 | break; | |
0caa5af8 RH |
13322 | case 0x00: /* FMLAL */ |
13323 | case 0x04: /* FMLSL */ | |
13324 | case 0x18: /* FMLAL2 */ | |
13325 | case 0x1c: /* FMLSL2 */ | |
13326 | if (is_scalar || size != MO_32 || !dc_isar_feature(aa64_fhm, s)) { | |
13327 | unallocated_encoding(s); | |
13328 | return; | |
13329 | } | |
13330 | size = MO_16; | |
13331 | /* is_fp, but we pass cpu_env not fp_status. */ | |
13332 | break; | |
f5e51e7f PM |
13333 | default: |
13334 | unallocated_encoding(s); | |
13335 | return; | |
13336 | } | |
13337 | ||
d17b7cdc RH |
13338 | switch (is_fp) { |
13339 | case 1: /* normal fp */ | |
14776ab5 | 13340 | /* convert insn encoded size to MemOp size */ |
5d265064 | 13341 | switch (size) { |
449f264b | 13342 | case 0: /* half-precision */ |
5d265064 | 13343 | size = MO_16; |
d17b7cdc | 13344 | is_fp16 = true; |
449f264b RH |
13345 | break; |
13346 | case MO_32: /* single precision */ | |
13347 | case MO_64: /* double precision */ | |
13348 | break; | |
13349 | default: | |
5d265064 AB |
13350 | unallocated_encoding(s); |
13351 | return; | |
f5e51e7f | 13352 | } |
d17b7cdc RH |
13353 | break; |
13354 | ||
13355 | case 2: /* complex fp */ | |
13356 | /* Each indexable element is a complex pair. */ | |
eaefb97a | 13357 | size += 1; |
d17b7cdc RH |
13358 | switch (size) { |
13359 | case MO_32: | |
13360 | if (h && !is_q) { | |
13361 | unallocated_encoding(s); | |
13362 | return; | |
13363 | } | |
13364 | is_fp16 = true; | |
13365 | break; | |
13366 | case MO_64: | |
13367 | break; | |
13368 | default: | |
13369 | unallocated_encoding(s); | |
13370 | return; | |
13371 | } | |
13372 | break; | |
13373 | ||
13374 | default: /* integer */ | |
f5e51e7f | 13375 | switch (size) { |
449f264b RH |
13376 | case MO_8: |
13377 | case MO_64: | |
f5e51e7f PM |
13378 | unallocated_encoding(s); |
13379 | return; | |
13380 | } | |
d17b7cdc RH |
13381 | break; |
13382 | } | |
5763190f | 13383 | if (is_fp16 && !dc_isar_feature(aa64_fp16, s)) { |
d17b7cdc RH |
13384 | unallocated_encoding(s); |
13385 | return; | |
f5e51e7f PM |
13386 | } |
13387 | ||
14776ab5 | 13388 | /* Given MemOp size, adjust register and indexing. */ |
449f264b RH |
13389 | switch (size) { |
13390 | case MO_16: | |
13391 | index = h << 2 | l << 1 | m; | |
13392 | break; | |
13393 | case MO_32: | |
13394 | index = h << 1 | l; | |
13395 | rm |= m << 4; | |
13396 | break; | |
13397 | case MO_64: | |
13398 | if (l || !is_q) { | |
13399 | unallocated_encoding(s); | |
13400 | return; | |
13401 | } | |
13402 | index = h; | |
13403 | rm |= m << 4; | |
13404 | break; | |
13405 | default: | |
13406 | g_assert_not_reached(); | |
13407 | } | |
13408 | ||
8c6afa6a PM |
13409 | if (!fp_access_check(s)) { |
13410 | return; | |
13411 | } | |
13412 | ||
f5e51e7f | 13413 | if (is_fp) { |
5d265064 | 13414 | fpst = get_fpstatus_ptr(is_fp16); |
f5e51e7f | 13415 | } else { |
f764718d | 13416 | fpst = NULL; |
f5e51e7f PM |
13417 | } |
13418 | ||
d17b7cdc | 13419 | switch (16 * u + opcode) { |
26c470a7 RH |
13420 | case 0x0e: /* SDOT */ |
13421 | case 0x1e: /* UDOT */ | |
13422 | gen_gvec_op3_ool(s, is_q, rd, rn, rm, index, | |
13423 | u ? gen_helper_gvec_udot_idx_b | |
13424 | : gen_helper_gvec_sdot_idx_b); | |
13425 | return; | |
d17b7cdc RH |
13426 | case 0x11: /* FCMLA #0 */ |
13427 | case 0x13: /* FCMLA #90 */ | |
13428 | case 0x15: /* FCMLA #180 */ | |
13429 | case 0x17: /* FCMLA #270 */ | |
2cc99919 RH |
13430 | { |
13431 | int rot = extract32(insn, 13, 2); | |
13432 | int data = (index << 2) | rot; | |
13433 | tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd), | |
13434 | vec_full_reg_offset(s, rn), | |
13435 | vec_full_reg_offset(s, rm), fpst, | |
13436 | is_q ? 16 : 8, vec_full_reg_size(s), data, | |
13437 | size == MO_64 | |
13438 | ? gen_helper_gvec_fcmlas_idx | |
13439 | : gen_helper_gvec_fcmlah_idx); | |
13440 | tcg_temp_free_ptr(fpst); | |
13441 | } | |
d17b7cdc | 13442 | return; |
0caa5af8 RH |
13443 | |
13444 | case 0x00: /* FMLAL */ | |
13445 | case 0x04: /* FMLSL */ | |
13446 | case 0x18: /* FMLAL2 */ | |
13447 | case 0x1c: /* FMLSL2 */ | |
13448 | { | |
13449 | int is_s = extract32(opcode, 2, 1); | |
13450 | int is_2 = u; | |
13451 | int data = (index << 2) | (is_2 << 1) | is_s; | |
13452 | tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd), | |
13453 | vec_full_reg_offset(s, rn), | |
13454 | vec_full_reg_offset(s, rm), cpu_env, | |
13455 | is_q ? 16 : 8, vec_full_reg_size(s), | |
13456 | data, gen_helper_gvec_fmlal_idx_a64); | |
13457 | } | |
13458 | return; | |
d17b7cdc RH |
13459 | } |
13460 | ||
f5e51e7f PM |
13461 | if (size == 3) { |
13462 | TCGv_i64 tcg_idx = tcg_temp_new_i64(); | |
13463 | int pass; | |
13464 | ||
13465 | assert(is_fp && is_q && !is_long); | |
13466 | ||
13467 | read_vec_element(s, tcg_idx, rm, index, MO_64); | |
13468 | ||
9f82e0ff | 13469 | for (pass = 0; pass < (is_scalar ? 1 : 2); pass++) { |
f5e51e7f PM |
13470 | TCGv_i64 tcg_op = tcg_temp_new_i64(); |
13471 | TCGv_i64 tcg_res = tcg_temp_new_i64(); | |
13472 | ||
13473 | read_vec_element(s, tcg_op, rn, pass, MO_64); | |
13474 | ||
5f81b1de RH |
13475 | switch (16 * u + opcode) { |
13476 | case 0x05: /* FMLS */ | |
f5e51e7f PM |
13477 | /* As usual for ARM, separate negation for fused multiply-add */ |
13478 | gen_helper_vfp_negd(tcg_op, tcg_op); | |
13479 | /* fall through */ | |
5f81b1de | 13480 | case 0x01: /* FMLA */ |
f5e51e7f PM |
13481 | read_vec_element(s, tcg_res, rd, pass, MO_64); |
13482 | gen_helper_vfp_muladdd(tcg_res, tcg_op, tcg_idx, tcg_res, fpst); | |
13483 | break; | |
5f81b1de RH |
13484 | case 0x09: /* FMUL */ |
13485 | gen_helper_vfp_muld(tcg_res, tcg_op, tcg_idx, fpst); | |
13486 | break; | |
13487 | case 0x19: /* FMULX */ | |
13488 | gen_helper_vfp_mulxd(tcg_res, tcg_op, tcg_idx, fpst); | |
f5e51e7f PM |
13489 | break; |
13490 | default: | |
13491 | g_assert_not_reached(); | |
13492 | } | |
13493 | ||
13494 | write_vec_element(s, tcg_res, rd, pass, MO_64); | |
13495 | tcg_temp_free_i64(tcg_op); | |
13496 | tcg_temp_free_i64(tcg_res); | |
13497 | } | |
13498 | ||
13499 | tcg_temp_free_i64(tcg_idx); | |
4ff55bcb | 13500 | clear_vec_high(s, !is_scalar, rd); |
f5e51e7f | 13501 | } else if (!is_long) { |
9f82e0ff PM |
13502 | /* 32 bit floating point, or 16 or 32 bit integer. |
13503 | * For the 16 bit scalar case we use the usual Neon helpers and | |
13504 | * rely on the fact that 0 op 0 == 0 with no side effects. | |
13505 | */ | |
f5e51e7f | 13506 | TCGv_i32 tcg_idx = tcg_temp_new_i32(); |
9f82e0ff PM |
13507 | int pass, maxpasses; |
13508 | ||
13509 | if (is_scalar) { | |
13510 | maxpasses = 1; | |
13511 | } else { | |
13512 | maxpasses = is_q ? 4 : 2; | |
13513 | } | |
f5e51e7f PM |
13514 | |
13515 | read_vec_element_i32(s, tcg_idx, rm, index, size); | |
13516 | ||
9f82e0ff | 13517 | if (size == 1 && !is_scalar) { |
f5e51e7f PM |
13518 | /* The simplest way to handle the 16x16 indexed ops is to duplicate |
13519 | * the index into both halves of the 32 bit tcg_idx and then use | |
13520 | * the usual Neon helpers. | |
13521 | */ | |
13522 | tcg_gen_deposit_i32(tcg_idx, tcg_idx, tcg_idx, 16, 16); | |
13523 | } | |
13524 | ||
9f82e0ff | 13525 | for (pass = 0; pass < maxpasses; pass++) { |
f5e51e7f PM |
13526 | TCGv_i32 tcg_op = tcg_temp_new_i32(); |
13527 | TCGv_i32 tcg_res = tcg_temp_new_i32(); | |
13528 | ||
9f82e0ff | 13529 | read_vec_element_i32(s, tcg_op, rn, pass, is_scalar ? size : MO_32); |
f5e51e7f | 13530 | |
5f81b1de RH |
13531 | switch (16 * u + opcode) { |
13532 | case 0x08: /* MUL */ | |
13533 | case 0x10: /* MLA */ | |
13534 | case 0x14: /* MLS */ | |
f5e51e7f PM |
13535 | { |
13536 | static NeonGenTwoOpFn * const fns[2][2] = { | |
13537 | { gen_helper_neon_add_u16, gen_helper_neon_sub_u16 }, | |
13538 | { tcg_gen_add_i32, tcg_gen_sub_i32 }, | |
13539 | }; | |
13540 | NeonGenTwoOpFn *genfn; | |
13541 | bool is_sub = opcode == 0x4; | |
13542 | ||
13543 | if (size == 1) { | |
13544 | gen_helper_neon_mul_u16(tcg_res, tcg_op, tcg_idx); | |
13545 | } else { | |
13546 | tcg_gen_mul_i32(tcg_res, tcg_op, tcg_idx); | |
13547 | } | |
13548 | if (opcode == 0x8) { | |
13549 | break; | |
13550 | } | |
13551 | read_vec_element_i32(s, tcg_op, rd, pass, MO_32); | |
13552 | genfn = fns[size - 1][is_sub]; | |
13553 | genfn(tcg_res, tcg_op, tcg_res); | |
13554 | break; | |
13555 | } | |
5f81b1de RH |
13556 | case 0x05: /* FMLS */ |
13557 | case 0x01: /* FMLA */ | |
5d265064 AB |
13558 | read_vec_element_i32(s, tcg_res, rd, pass, |
13559 | is_scalar ? size : MO_32); | |
13560 | switch (size) { | |
13561 | case 1: | |
13562 | if (opcode == 0x5) { | |
13563 | /* As usual for ARM, separate negation for fused | |
13564 | * multiply-add */ | |
13565 | tcg_gen_xori_i32(tcg_op, tcg_op, 0x80008000); | |
13566 | } | |
6089030c AB |
13567 | if (is_scalar) { |
13568 | gen_helper_advsimd_muladdh(tcg_res, tcg_op, tcg_idx, | |
13569 | tcg_res, fpst); | |
13570 | } else { | |
13571 | gen_helper_advsimd_muladd2h(tcg_res, tcg_op, tcg_idx, | |
13572 | tcg_res, fpst); | |
13573 | } | |
5d265064 AB |
13574 | break; |
13575 | case 2: | |
13576 | if (opcode == 0x5) { | |
13577 | /* As usual for ARM, separate negation for | |
13578 | * fused multiply-add */ | |
13579 | tcg_gen_xori_i32(tcg_op, tcg_op, 0x80000000); | |
13580 | } | |
13581 | gen_helper_vfp_muladds(tcg_res, tcg_op, tcg_idx, | |
13582 | tcg_res, fpst); | |
13583 | break; | |
13584 | default: | |
13585 | g_assert_not_reached(); | |
13586 | } | |
f5e51e7f | 13587 | break; |
5f81b1de | 13588 | case 0x09: /* FMUL */ |
5d265064 AB |
13589 | switch (size) { |
13590 | case 1: | |
5f81b1de RH |
13591 | if (is_scalar) { |
13592 | gen_helper_advsimd_mulh(tcg_res, tcg_op, | |
13593 | tcg_idx, fpst); | |
5d265064 | 13594 | } else { |
5f81b1de RH |
13595 | gen_helper_advsimd_mul2h(tcg_res, tcg_op, |
13596 | tcg_idx, fpst); | |
5d265064 AB |
13597 | } |
13598 | break; | |
13599 | case 2: | |
5f81b1de RH |
13600 | gen_helper_vfp_muls(tcg_res, tcg_op, tcg_idx, fpst); |
13601 | break; | |
13602 | default: | |
13603 | g_assert_not_reached(); | |
13604 | } | |
13605 | break; | |
13606 | case 0x19: /* FMULX */ | |
13607 | switch (size) { | |
13608 | case 1: | |
13609 | if (is_scalar) { | |
13610 | gen_helper_advsimd_mulxh(tcg_res, tcg_op, | |
13611 | tcg_idx, fpst); | |
5d265064 | 13612 | } else { |
5f81b1de RH |
13613 | gen_helper_advsimd_mulx2h(tcg_res, tcg_op, |
13614 | tcg_idx, fpst); | |
5d265064 AB |
13615 | } |
13616 | break; | |
5f81b1de RH |
13617 | case 2: |
13618 | gen_helper_vfp_mulxs(tcg_res, tcg_op, tcg_idx, fpst); | |
13619 | break; | |
5d265064 AB |
13620 | default: |
13621 | g_assert_not_reached(); | |
f5e51e7f PM |
13622 | } |
13623 | break; | |
5f81b1de | 13624 | case 0x0c: /* SQDMULH */ |
f5e51e7f PM |
13625 | if (size == 1) { |
13626 | gen_helper_neon_qdmulh_s16(tcg_res, cpu_env, | |
13627 | tcg_op, tcg_idx); | |
13628 | } else { | |
13629 | gen_helper_neon_qdmulh_s32(tcg_res, cpu_env, | |
13630 | tcg_op, tcg_idx); | |
13631 | } | |
13632 | break; | |
5f81b1de | 13633 | case 0x0d: /* SQRDMULH */ |
f5e51e7f PM |
13634 | if (size == 1) { |
13635 | gen_helper_neon_qrdmulh_s16(tcg_res, cpu_env, | |
13636 | tcg_op, tcg_idx); | |
13637 | } else { | |
13638 | gen_helper_neon_qrdmulh_s32(tcg_res, cpu_env, | |
13639 | tcg_op, tcg_idx); | |
13640 | } | |
13641 | break; | |
d345df7a RH |
13642 | case 0x1d: /* SQRDMLAH */ |
13643 | read_vec_element_i32(s, tcg_res, rd, pass, | |
13644 | is_scalar ? size : MO_32); | |
13645 | if (size == 1) { | |
13646 | gen_helper_neon_qrdmlah_s16(tcg_res, cpu_env, | |
13647 | tcg_op, tcg_idx, tcg_res); | |
13648 | } else { | |
13649 | gen_helper_neon_qrdmlah_s32(tcg_res, cpu_env, | |
13650 | tcg_op, tcg_idx, tcg_res); | |
13651 | } | |
13652 | break; | |
13653 | case 0x1f: /* SQRDMLSH */ | |
13654 | read_vec_element_i32(s, tcg_res, rd, pass, | |
13655 | is_scalar ? size : MO_32); | |
13656 | if (size == 1) { | |
13657 | gen_helper_neon_qrdmlsh_s16(tcg_res, cpu_env, | |
13658 | tcg_op, tcg_idx, tcg_res); | |
13659 | } else { | |
13660 | gen_helper_neon_qrdmlsh_s32(tcg_res, cpu_env, | |
13661 | tcg_op, tcg_idx, tcg_res); | |
13662 | } | |
13663 | break; | |
f5e51e7f PM |
13664 | default: |
13665 | g_assert_not_reached(); | |
13666 | } | |
13667 | ||
9f82e0ff PM |
13668 | if (is_scalar) { |
13669 | write_fp_sreg(s, rd, tcg_res); | |
13670 | } else { | |
13671 | write_vec_element_i32(s, tcg_res, rd, pass, MO_32); | |
13672 | } | |
13673 | ||
f5e51e7f PM |
13674 | tcg_temp_free_i32(tcg_op); |
13675 | tcg_temp_free_i32(tcg_res); | |
13676 | } | |
13677 | ||
13678 | tcg_temp_free_i32(tcg_idx); | |
4ff55bcb | 13679 | clear_vec_high(s, is_q, rd); |
f5e51e7f PM |
13680 | } else { |
13681 | /* long ops: 16x16->32 or 32x32->64 */ | |
c44ad1fd PM |
13682 | TCGv_i64 tcg_res[2]; |
13683 | int pass; | |
13684 | bool satop = extract32(opcode, 0, 1); | |
14776ab5 | 13685 | MemOp memop = MO_32; |
c44ad1fd PM |
13686 | |
13687 | if (satop || !u) { | |
13688 | memop |= MO_SIGN; | |
13689 | } | |
13690 | ||
13691 | if (size == 2) { | |
13692 | TCGv_i64 tcg_idx = tcg_temp_new_i64(); | |
13693 | ||
13694 | read_vec_element(s, tcg_idx, rm, index, memop); | |
13695 | ||
9f82e0ff | 13696 | for (pass = 0; pass < (is_scalar ? 1 : 2); pass++) { |
c44ad1fd PM |
13697 | TCGv_i64 tcg_op = tcg_temp_new_i64(); |
13698 | TCGv_i64 tcg_passres; | |
9f82e0ff | 13699 | int passelt; |
c44ad1fd | 13700 | |
9f82e0ff PM |
13701 | if (is_scalar) { |
13702 | passelt = 0; | |
13703 | } else { | |
13704 | passelt = pass + (is_q * 2); | |
13705 | } | |
13706 | ||
13707 | read_vec_element(s, tcg_op, rn, passelt, memop); | |
c44ad1fd PM |
13708 | |
13709 | tcg_res[pass] = tcg_temp_new_i64(); | |
13710 | ||
13711 | if (opcode == 0xa || opcode == 0xb) { | |
13712 | /* Non-accumulating ops */ | |
13713 | tcg_passres = tcg_res[pass]; | |
13714 | } else { | |
13715 | tcg_passres = tcg_temp_new_i64(); | |
13716 | } | |
13717 | ||
13718 | tcg_gen_mul_i64(tcg_passres, tcg_op, tcg_idx); | |
13719 | tcg_temp_free_i64(tcg_op); | |
13720 | ||
13721 | if (satop) { | |
13722 | /* saturating, doubling */ | |
13723 | gen_helper_neon_addl_saturate_s64(tcg_passres, cpu_env, | |
13724 | tcg_passres, tcg_passres); | |
13725 | } | |
13726 | ||
13727 | if (opcode == 0xa || opcode == 0xb) { | |
13728 | continue; | |
13729 | } | |
13730 | ||
13731 | /* Accumulating op: handle accumulate step */ | |
13732 | read_vec_element(s, tcg_res[pass], rd, pass, MO_64); | |
13733 | ||
13734 | switch (opcode) { | |
13735 | case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */ | |
13736 | tcg_gen_add_i64(tcg_res[pass], tcg_res[pass], tcg_passres); | |
13737 | break; | |
13738 | case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */ | |
13739 | tcg_gen_sub_i64(tcg_res[pass], tcg_res[pass], tcg_passres); | |
13740 | break; | |
13741 | case 0x7: /* SQDMLSL, SQDMLSL2 */ | |
13742 | tcg_gen_neg_i64(tcg_passres, tcg_passres); | |
13743 | /* fall through */ | |
13744 | case 0x3: /* SQDMLAL, SQDMLAL2 */ | |
13745 | gen_helper_neon_addl_saturate_s64(tcg_res[pass], cpu_env, | |
13746 | tcg_res[pass], | |
13747 | tcg_passres); | |
13748 | break; | |
13749 | default: | |
13750 | g_assert_not_reached(); | |
13751 | } | |
13752 | tcg_temp_free_i64(tcg_passres); | |
13753 | } | |
13754 | tcg_temp_free_i64(tcg_idx); | |
9f82e0ff | 13755 | |
4ff55bcb | 13756 | clear_vec_high(s, !is_scalar, rd); |
c44ad1fd PM |
13757 | } else { |
13758 | TCGv_i32 tcg_idx = tcg_temp_new_i32(); | |
13759 | ||
13760 | assert(size == 1); | |
13761 | read_vec_element_i32(s, tcg_idx, rm, index, size); | |
13762 | ||
9f82e0ff PM |
13763 | if (!is_scalar) { |
13764 | /* The simplest way to handle the 16x16 indexed ops is to | |
13765 | * duplicate the index into both halves of the 32 bit tcg_idx | |
13766 | * and then use the usual Neon helpers. | |
13767 | */ | |
13768 | tcg_gen_deposit_i32(tcg_idx, tcg_idx, tcg_idx, 16, 16); | |
13769 | } | |
c44ad1fd | 13770 | |
9f82e0ff | 13771 | for (pass = 0; pass < (is_scalar ? 1 : 2); pass++) { |
c44ad1fd PM |
13772 | TCGv_i32 tcg_op = tcg_temp_new_i32(); |
13773 | TCGv_i64 tcg_passres; | |
13774 | ||
9f82e0ff PM |
13775 | if (is_scalar) { |
13776 | read_vec_element_i32(s, tcg_op, rn, pass, size); | |
13777 | } else { | |
13778 | read_vec_element_i32(s, tcg_op, rn, | |
13779 | pass + (is_q * 2), MO_32); | |
13780 | } | |
13781 | ||
c44ad1fd PM |
13782 | tcg_res[pass] = tcg_temp_new_i64(); |
13783 | ||
13784 | if (opcode == 0xa || opcode == 0xb) { | |
13785 | /* Non-accumulating ops */ | |
13786 | tcg_passres = tcg_res[pass]; | |
13787 | } else { | |
13788 | tcg_passres = tcg_temp_new_i64(); | |
13789 | } | |
13790 | ||
13791 | if (memop & MO_SIGN) { | |
13792 | gen_helper_neon_mull_s16(tcg_passres, tcg_op, tcg_idx); | |
13793 | } else { | |
13794 | gen_helper_neon_mull_u16(tcg_passres, tcg_op, tcg_idx); | |
13795 | } | |
13796 | if (satop) { | |
13797 | gen_helper_neon_addl_saturate_s32(tcg_passres, cpu_env, | |
13798 | tcg_passres, tcg_passres); | |
13799 | } | |
13800 | tcg_temp_free_i32(tcg_op); | |
13801 | ||
13802 | if (opcode == 0xa || opcode == 0xb) { | |
13803 | continue; | |
13804 | } | |
13805 | ||
13806 | /* Accumulating op: handle accumulate step */ | |
13807 | read_vec_element(s, tcg_res[pass], rd, pass, MO_64); | |
13808 | ||
13809 | switch (opcode) { | |
13810 | case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */ | |
13811 | gen_helper_neon_addl_u32(tcg_res[pass], tcg_res[pass], | |
13812 | tcg_passres); | |
13813 | break; | |
13814 | case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */ | |
13815 | gen_helper_neon_subl_u32(tcg_res[pass], tcg_res[pass], | |
13816 | tcg_passres); | |
13817 | break; | |
13818 | case 0x7: /* SQDMLSL, SQDMLSL2 */ | |
13819 | gen_helper_neon_negl_u32(tcg_passres, tcg_passres); | |
13820 | /* fall through */ | |
13821 | case 0x3: /* SQDMLAL, SQDMLAL2 */ | |
13822 | gen_helper_neon_addl_saturate_s32(tcg_res[pass], cpu_env, | |
13823 | tcg_res[pass], | |
13824 | tcg_passres); | |
13825 | break; | |
13826 | default: | |
13827 | g_assert_not_reached(); | |
13828 | } | |
13829 | tcg_temp_free_i64(tcg_passres); | |
13830 | } | |
13831 | tcg_temp_free_i32(tcg_idx); | |
9f82e0ff PM |
13832 | |
13833 | if (is_scalar) { | |
13834 | tcg_gen_ext32u_i64(tcg_res[0], tcg_res[0]); | |
13835 | } | |
13836 | } | |
13837 | ||
13838 | if (is_scalar) { | |
13839 | tcg_res[1] = tcg_const_i64(0); | |
c44ad1fd PM |
13840 | } |
13841 | ||
13842 | for (pass = 0; pass < 2; pass++) { | |
13843 | write_vec_element(s, tcg_res[pass], rd, pass, MO_64); | |
13844 | tcg_temp_free_i64(tcg_res[pass]); | |
13845 | } | |
f5e51e7f PM |
13846 | } |
13847 | ||
f764718d | 13848 | if (fpst) { |
f5e51e7f PM |
13849 | tcg_temp_free_ptr(fpst); |
13850 | } | |
384b26fb AB |
13851 | } |
13852 | ||
4ce31af4 | 13853 | /* Crypto AES |
384b26fb AB |
13854 | * 31 24 23 22 21 17 16 12 11 10 9 5 4 0 |
13855 | * +-----------------+------+-----------+--------+-----+------+------+ | |
13856 | * | 0 1 0 0 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd | | |
13857 | * +-----------------+------+-----------+--------+-----+------+------+ | |
13858 | */ | |
13859 | static void disas_crypto_aes(DisasContext *s, uint32_t insn) | |
13860 | { | |
5acc765c PM |
13861 | int size = extract32(insn, 22, 2); |
13862 | int opcode = extract32(insn, 12, 5); | |
13863 | int rn = extract32(insn, 5, 5); | |
13864 | int rd = extract32(insn, 0, 5); | |
13865 | int decrypt; | |
a04b68e1 RH |
13866 | gen_helper_gvec_2 *genfn2 = NULL; |
13867 | gen_helper_gvec_3 *genfn3 = NULL; | |
5acc765c | 13868 | |
962fcbf2 | 13869 | if (!dc_isar_feature(aa64_aes, s) || size != 0) { |
5acc765c PM |
13870 | unallocated_encoding(s); |
13871 | return; | |
13872 | } | |
13873 | ||
13874 | switch (opcode) { | |
13875 | case 0x4: /* AESE */ | |
13876 | decrypt = 0; | |
a04b68e1 | 13877 | genfn3 = gen_helper_crypto_aese; |
5acc765c PM |
13878 | break; |
13879 | case 0x6: /* AESMC */ | |
13880 | decrypt = 0; | |
a04b68e1 | 13881 | genfn2 = gen_helper_crypto_aesmc; |
5acc765c PM |
13882 | break; |
13883 | case 0x5: /* AESD */ | |
13884 | decrypt = 1; | |
a04b68e1 | 13885 | genfn3 = gen_helper_crypto_aese; |
5acc765c PM |
13886 | break; |
13887 | case 0x7: /* AESIMC */ | |
13888 | decrypt = 1; | |
a04b68e1 | 13889 | genfn2 = gen_helper_crypto_aesmc; |
5acc765c PM |
13890 | break; |
13891 | default: | |
13892 | unallocated_encoding(s); | |
13893 | return; | |
13894 | } | |
13895 | ||
a4f5c5b7 NR |
13896 | if (!fp_access_check(s)) { |
13897 | return; | |
13898 | } | |
a04b68e1 RH |
13899 | if (genfn2) { |
13900 | gen_gvec_op2_ool(s, true, rd, rn, decrypt, genfn2); | |
13901 | } else { | |
13902 | gen_gvec_op3_ool(s, true, rd, rd, rn, decrypt, genfn3); | |
13903 | } | |
384b26fb AB |
13904 | } |
13905 | ||
4ce31af4 | 13906 | /* Crypto three-reg SHA |
384b26fb AB |
13907 | * 31 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0 |
13908 | * +-----------------+------+---+------+---+--------+-----+------+------+ | |
13909 | * | 0 1 0 1 1 1 1 0 | size | 0 | Rm | 0 | opcode | 0 0 | Rn | Rd | | |
13910 | * +-----------------+------+---+------+---+--------+-----+------+------+ | |
13911 | */ | |
13912 | static void disas_crypto_three_reg_sha(DisasContext *s, uint32_t insn) | |
13913 | { | |
be56f04e PM |
13914 | int size = extract32(insn, 22, 2); |
13915 | int opcode = extract32(insn, 12, 3); | |
13916 | int rm = extract32(insn, 16, 5); | |
13917 | int rn = extract32(insn, 5, 5); | |
13918 | int rd = extract32(insn, 0, 5); | |
effa992f | 13919 | gen_helper_gvec_3 *genfn; |
962fcbf2 | 13920 | bool feature; |
be56f04e PM |
13921 | |
13922 | if (size != 0) { | |
13923 | unallocated_encoding(s); | |
13924 | return; | |
13925 | } | |
13926 | ||
13927 | switch (opcode) { | |
13928 | case 0: /* SHA1C */ | |
afc8b7d3 RH |
13929 | genfn = gen_helper_crypto_sha1c; |
13930 | feature = dc_isar_feature(aa64_sha1, s); | |
13931 | break; | |
be56f04e | 13932 | case 1: /* SHA1P */ |
afc8b7d3 RH |
13933 | genfn = gen_helper_crypto_sha1p; |
13934 | feature = dc_isar_feature(aa64_sha1, s); | |
13935 | break; | |
be56f04e | 13936 | case 2: /* SHA1M */ |
afc8b7d3 RH |
13937 | genfn = gen_helper_crypto_sha1m; |
13938 | feature = dc_isar_feature(aa64_sha1, s); | |
13939 | break; | |
be56f04e | 13940 | case 3: /* SHA1SU0 */ |
afc8b7d3 | 13941 | genfn = gen_helper_crypto_sha1su0; |
962fcbf2 | 13942 | feature = dc_isar_feature(aa64_sha1, s); |
be56f04e PM |
13943 | break; |
13944 | case 4: /* SHA256H */ | |
13945 | genfn = gen_helper_crypto_sha256h; | |
962fcbf2 | 13946 | feature = dc_isar_feature(aa64_sha256, s); |
be56f04e PM |
13947 | break; |
13948 | case 5: /* SHA256H2 */ | |
13949 | genfn = gen_helper_crypto_sha256h2; | |
962fcbf2 | 13950 | feature = dc_isar_feature(aa64_sha256, s); |
be56f04e PM |
13951 | break; |
13952 | case 6: /* SHA256SU1 */ | |
13953 | genfn = gen_helper_crypto_sha256su1; | |
962fcbf2 | 13954 | feature = dc_isar_feature(aa64_sha256, s); |
be56f04e PM |
13955 | break; |
13956 | default: | |
13957 | unallocated_encoding(s); | |
13958 | return; | |
13959 | } | |
13960 | ||
962fcbf2 | 13961 | if (!feature) { |
be56f04e PM |
13962 | unallocated_encoding(s); |
13963 | return; | |
13964 | } | |
13965 | ||
a4f5c5b7 NR |
13966 | if (!fp_access_check(s)) { |
13967 | return; | |
13968 | } | |
afc8b7d3 | 13969 | gen_gvec_op3_ool(s, true, rd, rn, rm, 0, genfn); |
384b26fb AB |
13970 | } |
13971 | ||
4ce31af4 | 13972 | /* Crypto two-reg SHA |
384b26fb AB |
13973 | * 31 24 23 22 21 17 16 12 11 10 9 5 4 0 |
13974 | * +-----------------+------+-----------+--------+-----+------+------+ | |
13975 | * | 0 1 0 1 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd | | |
13976 | * +-----------------+------+-----------+--------+-----+------+------+ | |
13977 | */ | |
13978 | static void disas_crypto_two_reg_sha(DisasContext *s, uint32_t insn) | |
13979 | { | |
f6fe04d5 PM |
13980 | int size = extract32(insn, 22, 2); |
13981 | int opcode = extract32(insn, 12, 5); | |
13982 | int rn = extract32(insn, 5, 5); | |
13983 | int rd = extract32(insn, 0, 5); | |
effa992f | 13984 | gen_helper_gvec_2 *genfn; |
962fcbf2 | 13985 | bool feature; |
f6fe04d5 PM |
13986 | |
13987 | if (size != 0) { | |
13988 | unallocated_encoding(s); | |
13989 | return; | |
13990 | } | |
13991 | ||
13992 | switch (opcode) { | |
13993 | case 0: /* SHA1H */ | |
962fcbf2 | 13994 | feature = dc_isar_feature(aa64_sha1, s); |
f6fe04d5 PM |
13995 | genfn = gen_helper_crypto_sha1h; |
13996 | break; | |
13997 | case 1: /* SHA1SU1 */ | |
962fcbf2 | 13998 | feature = dc_isar_feature(aa64_sha1, s); |
f6fe04d5 PM |
13999 | genfn = gen_helper_crypto_sha1su1; |
14000 | break; | |
14001 | case 2: /* SHA256SU0 */ | |
962fcbf2 | 14002 | feature = dc_isar_feature(aa64_sha256, s); |
f6fe04d5 PM |
14003 | genfn = gen_helper_crypto_sha256su0; |
14004 | break; | |
14005 | default: | |
14006 | unallocated_encoding(s); | |
14007 | return; | |
14008 | } | |
14009 | ||
962fcbf2 | 14010 | if (!feature) { |
f6fe04d5 PM |
14011 | unallocated_encoding(s); |
14012 | return; | |
14013 | } | |
14014 | ||
a4f5c5b7 NR |
14015 | if (!fp_access_check(s)) { |
14016 | return; | |
14017 | } | |
effa992f | 14018 | gen_gvec_op2_ool(s, true, rd, rn, 0, genfn); |
384b26fb AB |
14019 | } |
14020 | ||
1738860d RH |
14021 | static void gen_rax1_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m) |
14022 | { | |
14023 | tcg_gen_rotli_i64(d, m, 1); | |
14024 | tcg_gen_xor_i64(d, d, n); | |
14025 | } | |
14026 | ||
14027 | static void gen_rax1_vec(unsigned vece, TCGv_vec d, TCGv_vec n, TCGv_vec m) | |
14028 | { | |
14029 | tcg_gen_rotli_vec(vece, d, m, 1); | |
14030 | tcg_gen_xor_vec(vece, d, d, n); | |
14031 | } | |
14032 | ||
14033 | void gen_gvec_rax1(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, | |
14034 | uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz) | |
14035 | { | |
14036 | static const TCGOpcode vecop_list[] = { INDEX_op_rotli_vec, 0 }; | |
14037 | static const GVecGen3 op = { | |
14038 | .fni8 = gen_rax1_i64, | |
14039 | .fniv = gen_rax1_vec, | |
14040 | .opt_opc = vecop_list, | |
14041 | .fno = gen_helper_crypto_rax1, | |
14042 | .vece = MO_64, | |
14043 | }; | |
14044 | tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, opr_sz, max_sz, &op); | |
14045 | } | |
14046 | ||
90b827d1 AB |
14047 | /* Crypto three-reg SHA512 |
14048 | * 31 21 20 16 15 14 13 12 11 10 9 5 4 0 | |
14049 | * +-----------------------+------+---+---+-----+--------+------+------+ | |
14050 | * | 1 1 0 0 1 1 1 0 0 1 1 | Rm | 1 | O | 0 0 | opcode | Rn | Rd | | |
14051 | * +-----------------------+------+---+---+-----+--------+------+------+ | |
14052 | */ | |
14053 | static void disas_crypto_three_reg_sha512(DisasContext *s, uint32_t insn) | |
14054 | { | |
14055 | int opcode = extract32(insn, 10, 2); | |
14056 | int o = extract32(insn, 14, 1); | |
14057 | int rm = extract32(insn, 16, 5); | |
14058 | int rn = extract32(insn, 5, 5); | |
14059 | int rd = extract32(insn, 0, 5); | |
962fcbf2 | 14060 | bool feature; |
a04b68e1 | 14061 | gen_helper_gvec_3 *oolfn = NULL; |
1738860d | 14062 | GVecGen3Fn *gvecfn = NULL; |
90b827d1 AB |
14063 | |
14064 | if (o == 0) { | |
14065 | switch (opcode) { | |
14066 | case 0: /* SHA512H */ | |
962fcbf2 | 14067 | feature = dc_isar_feature(aa64_sha512, s); |
aaffebd6 | 14068 | oolfn = gen_helper_crypto_sha512h; |
90b827d1 AB |
14069 | break; |
14070 | case 1: /* SHA512H2 */ | |
962fcbf2 | 14071 | feature = dc_isar_feature(aa64_sha512, s); |
aaffebd6 | 14072 | oolfn = gen_helper_crypto_sha512h2; |
90b827d1 AB |
14073 | break; |
14074 | case 2: /* SHA512SU1 */ | |
962fcbf2 | 14075 | feature = dc_isar_feature(aa64_sha512, s); |
aaffebd6 | 14076 | oolfn = gen_helper_crypto_sha512su1; |
90b827d1 | 14077 | break; |
cd270ade | 14078 | case 3: /* RAX1 */ |
962fcbf2 | 14079 | feature = dc_isar_feature(aa64_sha3, s); |
1738860d | 14080 | gvecfn = gen_gvec_rax1; |
cd270ade | 14081 | break; |
c7a5e791 PN |
14082 | default: |
14083 | g_assert_not_reached(); | |
90b827d1 AB |
14084 | } |
14085 | } else { | |
80d6f4c6 AB |
14086 | switch (opcode) { |
14087 | case 0: /* SM3PARTW1 */ | |
962fcbf2 | 14088 | feature = dc_isar_feature(aa64_sm3, s); |
aaffebd6 | 14089 | oolfn = gen_helper_crypto_sm3partw1; |
80d6f4c6 AB |
14090 | break; |
14091 | case 1: /* SM3PARTW2 */ | |
962fcbf2 | 14092 | feature = dc_isar_feature(aa64_sm3, s); |
aaffebd6 | 14093 | oolfn = gen_helper_crypto_sm3partw2; |
80d6f4c6 | 14094 | break; |
b6577bcd | 14095 | case 2: /* SM4EKEY */ |
962fcbf2 | 14096 | feature = dc_isar_feature(aa64_sm4, s); |
a04b68e1 | 14097 | oolfn = gen_helper_crypto_sm4ekey; |
b6577bcd | 14098 | break; |
80d6f4c6 AB |
14099 | default: |
14100 | unallocated_encoding(s); | |
14101 | return; | |
14102 | } | |
90b827d1 AB |
14103 | } |
14104 | ||
962fcbf2 | 14105 | if (!feature) { |
90b827d1 AB |
14106 | unallocated_encoding(s); |
14107 | return; | |
14108 | } | |
14109 | ||
14110 | if (!fp_access_check(s)) { | |
14111 | return; | |
14112 | } | |
14113 | ||
a04b68e1 RH |
14114 | if (oolfn) { |
14115 | gen_gvec_op3_ool(s, true, rd, rn, rm, 0, oolfn); | |
1738860d | 14116 | } else { |
aaffebd6 | 14117 | gen_gvec_fn3(s, true, rd, rn, rm, gvecfn, MO_64); |
90b827d1 AB |
14118 | } |
14119 | } | |
14120 | ||
14121 | /* Crypto two-reg SHA512 | |
14122 | * 31 12 11 10 9 5 4 0 | |
14123 | * +-----------------------------------------+--------+------+------+ | |
14124 | * | 1 1 0 0 1 1 1 0 1 1 0 0 0 0 0 0 1 0 0 0 | opcode | Rn | Rd | | |
14125 | * +-----------------------------------------+--------+------+------+ | |
14126 | */ | |
14127 | static void disas_crypto_two_reg_sha512(DisasContext *s, uint32_t insn) | |
14128 | { | |
14129 | int opcode = extract32(insn, 10, 2); | |
14130 | int rn = extract32(insn, 5, 5); | |
14131 | int rd = extract32(insn, 0, 5); | |
962fcbf2 | 14132 | bool feature; |
90b827d1 AB |
14133 | |
14134 | switch (opcode) { | |
14135 | case 0: /* SHA512SU0 */ | |
962fcbf2 | 14136 | feature = dc_isar_feature(aa64_sha512, s); |
90b827d1 | 14137 | break; |
b6577bcd | 14138 | case 1: /* SM4E */ |
962fcbf2 | 14139 | feature = dc_isar_feature(aa64_sm4, s); |
b6577bcd | 14140 | break; |
90b827d1 AB |
14141 | default: |
14142 | unallocated_encoding(s); | |
14143 | return; | |
14144 | } | |
14145 | ||
962fcbf2 | 14146 | if (!feature) { |
90b827d1 AB |
14147 | unallocated_encoding(s); |
14148 | return; | |
14149 | } | |
14150 | ||
14151 | if (!fp_access_check(s)) { | |
14152 | return; | |
14153 | } | |
14154 | ||
aaffebd6 RH |
14155 | switch (opcode) { |
14156 | case 0: /* SHA512SU0 */ | |
14157 | gen_gvec_op2_ool(s, true, rd, rn, 0, gen_helper_crypto_sha512su0); | |
14158 | break; | |
14159 | case 1: /* SM4E */ | |
14160 | gen_gvec_op3_ool(s, true, rd, rd, rn, 0, gen_helper_crypto_sm4e); | |
14161 | break; | |
14162 | default: | |
14163 | g_assert_not_reached(); | |
a04b68e1 | 14164 | } |
90b827d1 AB |
14165 | } |
14166 | ||
cd270ade AB |
14167 | /* Crypto four-register |
14168 | * 31 23 22 21 20 16 15 14 10 9 5 4 0 | |
14169 | * +-------------------+-----+------+---+------+------+------+ | |
14170 | * | 1 1 0 0 1 1 1 0 0 | Op0 | Rm | 0 | Ra | Rn | Rd | | |
14171 | * +-------------------+-----+------+---+------+------+------+ | |
14172 | */ | |
14173 | static void disas_crypto_four_reg(DisasContext *s, uint32_t insn) | |
14174 | { | |
14175 | int op0 = extract32(insn, 21, 2); | |
14176 | int rm = extract32(insn, 16, 5); | |
14177 | int ra = extract32(insn, 10, 5); | |
14178 | int rn = extract32(insn, 5, 5); | |
14179 | int rd = extract32(insn, 0, 5); | |
962fcbf2 | 14180 | bool feature; |
cd270ade AB |
14181 | |
14182 | switch (op0) { | |
14183 | case 0: /* EOR3 */ | |
14184 | case 1: /* BCAX */ | |
962fcbf2 | 14185 | feature = dc_isar_feature(aa64_sha3, s); |
cd270ade | 14186 | break; |
80d6f4c6 | 14187 | case 2: /* SM3SS1 */ |
962fcbf2 | 14188 | feature = dc_isar_feature(aa64_sm3, s); |
80d6f4c6 | 14189 | break; |
cd270ade AB |
14190 | default: |
14191 | unallocated_encoding(s); | |
14192 | return; | |
14193 | } | |
14194 | ||
962fcbf2 | 14195 | if (!feature) { |
cd270ade AB |
14196 | unallocated_encoding(s); |
14197 | return; | |
14198 | } | |
14199 | ||
14200 | if (!fp_access_check(s)) { | |
14201 | return; | |
14202 | } | |
14203 | ||
14204 | if (op0 < 2) { | |
14205 | TCGv_i64 tcg_op1, tcg_op2, tcg_op3, tcg_res[2]; | |
14206 | int pass; | |
14207 | ||
14208 | tcg_op1 = tcg_temp_new_i64(); | |
14209 | tcg_op2 = tcg_temp_new_i64(); | |
14210 | tcg_op3 = tcg_temp_new_i64(); | |
14211 | tcg_res[0] = tcg_temp_new_i64(); | |
14212 | tcg_res[1] = tcg_temp_new_i64(); | |
14213 | ||
14214 | for (pass = 0; pass < 2; pass++) { | |
14215 | read_vec_element(s, tcg_op1, rn, pass, MO_64); | |
14216 | read_vec_element(s, tcg_op2, rm, pass, MO_64); | |
14217 | read_vec_element(s, tcg_op3, ra, pass, MO_64); | |
14218 | ||
14219 | if (op0 == 0) { | |
14220 | /* EOR3 */ | |
14221 | tcg_gen_xor_i64(tcg_res[pass], tcg_op2, tcg_op3); | |
14222 | } else { | |
14223 | /* BCAX */ | |
14224 | tcg_gen_andc_i64(tcg_res[pass], tcg_op2, tcg_op3); | |
14225 | } | |
14226 | tcg_gen_xor_i64(tcg_res[pass], tcg_res[pass], tcg_op1); | |
14227 | } | |
14228 | write_vec_element(s, tcg_res[0], rd, 0, MO_64); | |
14229 | write_vec_element(s, tcg_res[1], rd, 1, MO_64); | |
14230 | ||
14231 | tcg_temp_free_i64(tcg_op1); | |
14232 | tcg_temp_free_i64(tcg_op2); | |
14233 | tcg_temp_free_i64(tcg_op3); | |
14234 | tcg_temp_free_i64(tcg_res[0]); | |
14235 | tcg_temp_free_i64(tcg_res[1]); | |
14236 | } else { | |
80d6f4c6 AB |
14237 | TCGv_i32 tcg_op1, tcg_op2, tcg_op3, tcg_res, tcg_zero; |
14238 | ||
14239 | tcg_op1 = tcg_temp_new_i32(); | |
14240 | tcg_op2 = tcg_temp_new_i32(); | |
14241 | tcg_op3 = tcg_temp_new_i32(); | |
14242 | tcg_res = tcg_temp_new_i32(); | |
14243 | tcg_zero = tcg_const_i32(0); | |
14244 | ||
14245 | read_vec_element_i32(s, tcg_op1, rn, 3, MO_32); | |
14246 | read_vec_element_i32(s, tcg_op2, rm, 3, MO_32); | |
14247 | read_vec_element_i32(s, tcg_op3, ra, 3, MO_32); | |
14248 | ||
14249 | tcg_gen_rotri_i32(tcg_res, tcg_op1, 20); | |
14250 | tcg_gen_add_i32(tcg_res, tcg_res, tcg_op2); | |
14251 | tcg_gen_add_i32(tcg_res, tcg_res, tcg_op3); | |
14252 | tcg_gen_rotri_i32(tcg_res, tcg_res, 25); | |
14253 | ||
14254 | write_vec_element_i32(s, tcg_zero, rd, 0, MO_32); | |
14255 | write_vec_element_i32(s, tcg_zero, rd, 1, MO_32); | |
14256 | write_vec_element_i32(s, tcg_zero, rd, 2, MO_32); | |
14257 | write_vec_element_i32(s, tcg_res, rd, 3, MO_32); | |
14258 | ||
14259 | tcg_temp_free_i32(tcg_op1); | |
14260 | tcg_temp_free_i32(tcg_op2); | |
14261 | tcg_temp_free_i32(tcg_op3); | |
14262 | tcg_temp_free_i32(tcg_res); | |
14263 | tcg_temp_free_i32(tcg_zero); | |
cd270ade AB |
14264 | } |
14265 | } | |
14266 | ||
14267 | /* Crypto XAR | |
14268 | * 31 21 20 16 15 10 9 5 4 0 | |
14269 | * +-----------------------+------+--------+------+------+ | |
14270 | * | 1 1 0 0 1 1 1 0 1 0 0 | Rm | imm6 | Rn | Rd | | |
14271 | * +-----------------------+------+--------+------+------+ | |
14272 | */ | |
14273 | static void disas_crypto_xar(DisasContext *s, uint32_t insn) | |
14274 | { | |
14275 | int rm = extract32(insn, 16, 5); | |
14276 | int imm6 = extract32(insn, 10, 6); | |
14277 | int rn = extract32(insn, 5, 5); | |
14278 | int rd = extract32(insn, 0, 5); | |
14279 | TCGv_i64 tcg_op1, tcg_op2, tcg_res[2]; | |
14280 | int pass; | |
14281 | ||
962fcbf2 | 14282 | if (!dc_isar_feature(aa64_sha3, s)) { |
cd270ade AB |
14283 | unallocated_encoding(s); |
14284 | return; | |
14285 | } | |
14286 | ||
14287 | if (!fp_access_check(s)) { | |
14288 | return; | |
14289 | } | |
14290 | ||
14291 | tcg_op1 = tcg_temp_new_i64(); | |
14292 | tcg_op2 = tcg_temp_new_i64(); | |
14293 | tcg_res[0] = tcg_temp_new_i64(); | |
14294 | tcg_res[1] = tcg_temp_new_i64(); | |
14295 | ||
14296 | for (pass = 0; pass < 2; pass++) { | |
14297 | read_vec_element(s, tcg_op1, rn, pass, MO_64); | |
14298 | read_vec_element(s, tcg_op2, rm, pass, MO_64); | |
14299 | ||
14300 | tcg_gen_xor_i64(tcg_res[pass], tcg_op1, tcg_op2); | |
14301 | tcg_gen_rotri_i64(tcg_res[pass], tcg_res[pass], imm6); | |
14302 | } | |
14303 | write_vec_element(s, tcg_res[0], rd, 0, MO_64); | |
14304 | write_vec_element(s, tcg_res[1], rd, 1, MO_64); | |
14305 | ||
14306 | tcg_temp_free_i64(tcg_op1); | |
14307 | tcg_temp_free_i64(tcg_op2); | |
14308 | tcg_temp_free_i64(tcg_res[0]); | |
14309 | tcg_temp_free_i64(tcg_res[1]); | |
14310 | } | |
14311 | ||
80d6f4c6 AB |
14312 | /* Crypto three-reg imm2 |
14313 | * 31 21 20 16 15 14 13 12 11 10 9 5 4 0 | |
14314 | * +-----------------------+------+-----+------+--------+------+------+ | |
14315 | * | 1 1 0 0 1 1 1 0 0 1 0 | Rm | 1 0 | imm2 | opcode | Rn | Rd | | |
14316 | * +-----------------------+------+-----+------+--------+------+------+ | |
14317 | */ | |
14318 | static void disas_crypto_three_reg_imm2(DisasContext *s, uint32_t insn) | |
14319 | { | |
43fa36c9 RH |
14320 | static gen_helper_gvec_3 * const fns[4] = { |
14321 | gen_helper_crypto_sm3tt1a, gen_helper_crypto_sm3tt1b, | |
14322 | gen_helper_crypto_sm3tt2a, gen_helper_crypto_sm3tt2b, | |
14323 | }; | |
80d6f4c6 AB |
14324 | int opcode = extract32(insn, 10, 2); |
14325 | int imm2 = extract32(insn, 12, 2); | |
14326 | int rm = extract32(insn, 16, 5); | |
14327 | int rn = extract32(insn, 5, 5); | |
14328 | int rd = extract32(insn, 0, 5); | |
80d6f4c6 | 14329 | |
962fcbf2 | 14330 | if (!dc_isar_feature(aa64_sm3, s)) { |
80d6f4c6 AB |
14331 | unallocated_encoding(s); |
14332 | return; | |
14333 | } | |
14334 | ||
14335 | if (!fp_access_check(s)) { | |
14336 | return; | |
14337 | } | |
14338 | ||
43fa36c9 | 14339 | gen_gvec_op3_ool(s, true, rd, rn, rm, imm2, fns[opcode]); |
80d6f4c6 AB |
14340 | } |
14341 | ||
384b26fb AB |
14342 | /* C3.6 Data processing - SIMD, inc Crypto |
14343 | * | |
14344 | * As the decode gets a little complex we are using a table based | |
14345 | * approach for this part of the decode. | |
14346 | */ | |
14347 | static const AArch64DecodeTable data_proc_simd[] = { | |
14348 | /* pattern , mask , fn */ | |
14349 | { 0x0e200400, 0x9f200400, disas_simd_three_reg_same }, | |
e7186d82 | 14350 | { 0x0e008400, 0x9f208400, disas_simd_three_reg_same_extra }, |
384b26fb AB |
14351 | { 0x0e200000, 0x9f200c00, disas_simd_three_reg_diff }, |
14352 | { 0x0e200800, 0x9f3e0c00, disas_simd_two_reg_misc }, | |
14353 | { 0x0e300800, 0x9f3e0c00, disas_simd_across_lanes }, | |
14354 | { 0x0e000400, 0x9fe08400, disas_simd_copy }, | |
9f82e0ff | 14355 | { 0x0f000000, 0x9f000400, disas_simd_indexed }, /* vector indexed */ |
384b26fb AB |
14356 | /* simd_mod_imm decode is a subset of simd_shift_imm, so must precede it */ |
14357 | { 0x0f000400, 0x9ff80400, disas_simd_mod_imm }, | |
14358 | { 0x0f000400, 0x9f800400, disas_simd_shift_imm }, | |
14359 | { 0x0e000000, 0xbf208c00, disas_simd_tb }, | |
14360 | { 0x0e000800, 0xbf208c00, disas_simd_zip_trn }, | |
14361 | { 0x2e000000, 0xbf208400, disas_simd_ext }, | |
14362 | { 0x5e200400, 0xdf200400, disas_simd_scalar_three_reg_same }, | |
d9061ec3 | 14363 | { 0x5e008400, 0xdf208400, disas_simd_scalar_three_reg_same_extra }, |
384b26fb AB |
14364 | { 0x5e200000, 0xdf200c00, disas_simd_scalar_three_reg_diff }, |
14365 | { 0x5e200800, 0xdf3e0c00, disas_simd_scalar_two_reg_misc }, | |
14366 | { 0x5e300800, 0xdf3e0c00, disas_simd_scalar_pairwise }, | |
14367 | { 0x5e000400, 0xdfe08400, disas_simd_scalar_copy }, | |
9f82e0ff | 14368 | { 0x5f000000, 0xdf000400, disas_simd_indexed }, /* scalar indexed */ |
384b26fb AB |
14369 | { 0x5f000400, 0xdf800400, disas_simd_scalar_shift_imm }, |
14370 | { 0x4e280800, 0xff3e0c00, disas_crypto_aes }, | |
14371 | { 0x5e000000, 0xff208c00, disas_crypto_three_reg_sha }, | |
14372 | { 0x5e280800, 0xff3e0c00, disas_crypto_two_reg_sha }, | |
90b827d1 AB |
14373 | { 0xce608000, 0xffe0b000, disas_crypto_three_reg_sha512 }, |
14374 | { 0xcec08000, 0xfffff000, disas_crypto_two_reg_sha512 }, | |
cd270ade AB |
14375 | { 0xce000000, 0xff808000, disas_crypto_four_reg }, |
14376 | { 0xce800000, 0xffe00000, disas_crypto_xar }, | |
80d6f4c6 | 14377 | { 0xce408000, 0xffe0c000, disas_crypto_three_reg_imm2 }, |
376e8d6c | 14378 | { 0x0e400400, 0x9f60c400, disas_simd_three_reg_same_fp16 }, |
5d432be6 | 14379 | { 0x0e780800, 0x8f7e0c00, disas_simd_two_reg_misc_fp16 }, |
7c93b774 | 14380 | { 0x5e400400, 0xdf60c400, disas_simd_scalar_three_reg_same_fp16 }, |
384b26fb AB |
14381 | { 0x00000000, 0x00000000, NULL } |
14382 | }; | |
14383 | ||
faa0ba46 PM |
14384 | static void disas_data_proc_simd(DisasContext *s, uint32_t insn) |
14385 | { | |
14386 | /* Note that this is called with all non-FP cases from | |
14387 | * table C3-6 so it must UNDEF for entries not specifically | |
14388 | * allocated to instructions in that table. | |
14389 | */ | |
384b26fb AB |
14390 | AArch64DecodeFn *fn = lookup_disas_fn(&data_proc_simd[0], insn); |
14391 | if (fn) { | |
14392 | fn(s, insn); | |
14393 | } else { | |
14394 | unallocated_encoding(s); | |
14395 | } | |
faa0ba46 PM |
14396 | } |
14397 | ||
ad7ee8a2 CF |
14398 | /* C3.6 Data processing - SIMD and floating point */ |
14399 | static void disas_data_proc_simd_fp(DisasContext *s, uint32_t insn) | |
14400 | { | |
faa0ba46 PM |
14401 | if (extract32(insn, 28, 1) == 1 && extract32(insn, 30, 1) == 0) { |
14402 | disas_data_proc_fp(s, insn); | |
14403 | } else { | |
14404 | /* SIMD, including crypto */ | |
14405 | disas_data_proc_simd(s, insn); | |
14406 | } | |
ad7ee8a2 CF |
14407 | } |
14408 | ||
51bf0d7a RH |
14409 | /** |
14410 | * is_guarded_page: | |
14411 | * @env: The cpu environment | |
14412 | * @s: The DisasContext | |
14413 | * | |
14414 | * Return true if the page is guarded. | |
14415 | */ | |
14416 | static bool is_guarded_page(CPUARMState *env, DisasContext *s) | |
14417 | { | |
14418 | #ifdef CONFIG_USER_ONLY | |
14419 | return false; /* FIXME */ | |
14420 | #else | |
14421 | uint64_t addr = s->base.pc_first; | |
14422 | int mmu_idx = arm_to_core_mmu_idx(s->mmu_idx); | |
14423 | unsigned int index = tlb_index(env, mmu_idx, addr); | |
14424 | CPUTLBEntry *entry = tlb_entry(env, mmu_idx, addr); | |
14425 | ||
14426 | /* | |
14427 | * We test this immediately after reading an insn, which means | |
14428 | * that any normal page must be in the TLB. The only exception | |
14429 | * would be for executing from flash or device memory, which | |
14430 | * does not retain the TLB entry. | |
14431 | * | |
14432 | * FIXME: Assume false for those, for now. We could use | |
14433 | * arm_cpu_get_phys_page_attrs_debug to re-read the page | |
14434 | * table entry even for that case. | |
14435 | */ | |
14436 | return (tlb_hit(entry->addr_code, addr) && | |
149d3b31 | 14437 | arm_tlb_bti_gp(&env_tlb(env)->d[mmu_idx].iotlb[index].attrs)); |
51bf0d7a RH |
14438 | #endif |
14439 | } | |
14440 | ||
14441 | /** | |
14442 | * btype_destination_ok: | |
14443 | * @insn: The instruction at the branch destination | |
14444 | * @bt: SCTLR_ELx.BT | |
14445 | * @btype: PSTATE.BTYPE, and is non-zero | |
14446 | * | |
14447 | * On a guarded page, there are a limited number of insns | |
14448 | * that may be present at the branch target: | |
14449 | * - branch target identifiers, | |
14450 | * - paciasp, pacibsp, | |
14451 | * - BRK insn | |
14452 | * - HLT insn | |
14453 | * Anything else causes a Branch Target Exception. | |
14454 | * | |
14455 | * Return true if the branch is compatible, false to raise BTITRAP. | |
14456 | */ | |
14457 | static bool btype_destination_ok(uint32_t insn, bool bt, int btype) | |
14458 | { | |
14459 | if ((insn & 0xfffff01fu) == 0xd503201fu) { | |
14460 | /* HINT space */ | |
14461 | switch (extract32(insn, 5, 7)) { | |
14462 | case 0b011001: /* PACIASP */ | |
14463 | case 0b011011: /* PACIBSP */ | |
14464 | /* | |
14465 | * If SCTLR_ELx.BT, then PACI*SP are not compatible | |
14466 | * with btype == 3. Otherwise all btype are ok. | |
14467 | */ | |
14468 | return !bt || btype != 3; | |
14469 | case 0b100000: /* BTI */ | |
14470 | /* Not compatible with any btype. */ | |
14471 | return false; | |
14472 | case 0b100010: /* BTI c */ | |
14473 | /* Not compatible with btype == 3 */ | |
14474 | return btype != 3; | |
14475 | case 0b100100: /* BTI j */ | |
14476 | /* Not compatible with btype == 2 */ | |
14477 | return btype != 2; | |
14478 | case 0b100110: /* BTI jc */ | |
14479 | /* Compatible with any btype. */ | |
14480 | return true; | |
14481 | } | |
14482 | } else { | |
14483 | switch (insn & 0xffe0001fu) { | |
14484 | case 0xd4200000u: /* BRK */ | |
14485 | case 0xd4400000u: /* HLT */ | |
14486 | /* Give priority to the breakpoint exception. */ | |
14487 | return true; | |
14488 | } | |
14489 | } | |
14490 | return false; | |
14491 | } | |
14492 | ||
ad7ee8a2 | 14493 | /* C3.1 A64 instruction index by encoding */ |
40f860cd | 14494 | static void disas_a64_insn(CPUARMState *env, DisasContext *s) |
14ade10f AG |
14495 | { |
14496 | uint32_t insn; | |
14497 | ||
a0415916 RH |
14498 | s->pc_curr = s->base.pc_next; |
14499 | insn = arm_ldl_code(env, s->base.pc_next, s->sctlr_b); | |
14ade10f | 14500 | s->insn = insn; |
a0415916 | 14501 | s->base.pc_next += 4; |
14ade10f | 14502 | |
90e49638 PM |
14503 | s->fp_access_checked = false; |
14504 | ||
51bf0d7a RH |
14505 | if (dc_isar_feature(aa64_bti, s)) { |
14506 | if (s->base.num_insns == 1) { | |
14507 | /* | |
14508 | * At the first insn of the TB, compute s->guarded_page. | |
14509 | * We delayed computing this until successfully reading | |
14510 | * the first insn of the TB, above. This (mostly) ensures | |
14511 | * that the softmmu tlb entry has been populated, and the | |
14512 | * page table GP bit is available. | |
14513 | * | |
14514 | * Note that we need to compute this even if btype == 0, | |
14515 | * because this value is used for BR instructions later | |
14516 | * where ENV is not available. | |
14517 | */ | |
14518 | s->guarded_page = is_guarded_page(env, s); | |
14519 | ||
14520 | /* First insn can have btype set to non-zero. */ | |
14521 | tcg_debug_assert(s->btype >= 0); | |
14522 | ||
14523 | /* | |
14524 | * Note that the Branch Target Exception has fairly high | |
14525 | * priority -- below debugging exceptions but above most | |
14526 | * everything else. This allows us to handle this now | |
14527 | * instead of waiting until the insn is otherwise decoded. | |
14528 | */ | |
14529 | if (s->btype != 0 | |
14530 | && s->guarded_page | |
14531 | && !btype_destination_ok(insn, s->bt, s->btype)) { | |
a767fac8 RH |
14532 | gen_exception_insn(s, s->pc_curr, EXCP_UDEF, |
14533 | syn_btitrap(s->btype), | |
51bf0d7a RH |
14534 | default_exception_el(s)); |
14535 | return; | |
14536 | } | |
14537 | } else { | |
14538 | /* Not the first insn: btype must be 0. */ | |
14539 | tcg_debug_assert(s->btype == 0); | |
14540 | } | |
14541 | } | |
14542 | ||
ad7ee8a2 | 14543 | switch (extract32(insn, 25, 4)) { |
38388f7e | 14544 | case 0x0: case 0x1: case 0x3: /* UNALLOCATED */ |
14ade10f AG |
14545 | unallocated_encoding(s); |
14546 | break; | |
38388f7e | 14547 | case 0x2: |
cd208a1c | 14548 | if (!dc_isar_feature(aa64_sve, s) || !disas_sve(s, insn)) { |
38388f7e RH |
14549 | unallocated_encoding(s); |
14550 | } | |
14551 | break; | |
ad7ee8a2 CF |
14552 | case 0x8: case 0x9: /* Data processing - immediate */ |
14553 | disas_data_proc_imm(s, insn); | |
14554 | break; | |
14555 | case 0xa: case 0xb: /* Branch, exception generation and system insns */ | |
14556 | disas_b_exc_sys(s, insn); | |
14557 | break; | |
14558 | case 0x4: | |
14559 | case 0x6: | |
14560 | case 0xc: | |
14561 | case 0xe: /* Loads and stores */ | |
14562 | disas_ldst(s, insn); | |
14563 | break; | |
14564 | case 0x5: | |
14565 | case 0xd: /* Data processing - register */ | |
14566 | disas_data_proc_reg(s, insn); | |
14567 | break; | |
14568 | case 0x7: | |
14569 | case 0xf: /* Data processing - SIMD and floating point */ | |
14570 | disas_data_proc_simd_fp(s, insn); | |
14571 | break; | |
14572 | default: | |
14573 | assert(FALSE); /* all 15 cases should be handled above */ | |
14574 | break; | |
14ade10f | 14575 | } |
11e169de AG |
14576 | |
14577 | /* if we allocated any temporaries, free them here */ | |
14578 | free_tmp_a64(s); | |
51bf0d7a RH |
14579 | |
14580 | /* | |
14581 | * After execution of most insns, btype is reset to 0. | |
14582 | * Note that we set btype == -1 when the insn sets btype. | |
14583 | */ | |
14584 | if (s->btype > 0 && s->base.is_jmp != DISAS_NORETURN) { | |
14585 | reset_btype(s); | |
14586 | } | |
40f860cd | 14587 | } |
14ade10f | 14588 | |
b542683d EC |
14589 | static void aarch64_tr_init_disas_context(DisasContextBase *dcbase, |
14590 | CPUState *cpu) | |
40f860cd | 14591 | { |
dcba3a8d | 14592 | DisasContext *dc = container_of(dcbase, DisasContext, base); |
5c039906 | 14593 | CPUARMState *env = cpu->env_ptr; |
2fc0cc0e | 14594 | ARMCPU *arm_cpu = env_archcpu(env); |
aad821ac RH |
14595 | uint32_t tb_flags = dc->base.tb->flags; |
14596 | int bound, core_mmu_idx; | |
40f860cd | 14597 | |
962fcbf2 | 14598 | dc->isar = &arm_cpu->isar; |
40f860cd PM |
14599 | dc->condjmp = 0; |
14600 | ||
14601 | dc->aarch64 = 1; | |
cef9ee70 SS |
14602 | /* If we are coming from secure EL0 in a system with a 32-bit EL3, then |
14603 | * there is no secure EL1, so we route exceptions to EL3. | |
14604 | */ | |
14605 | dc->secure_routed_to_el3 = arm_feature(env, ARM_FEATURE_EL3) && | |
14606 | !arm_el_is_aa64(env, 3); | |
40f860cd | 14607 | dc->thumb = 0; |
f9fd40eb | 14608 | dc->sctlr_b = 0; |
aad821ac | 14609 | dc->be_data = FIELD_EX32(tb_flags, TBFLAG_ANY, BE_DATA) ? MO_BE : MO_LE; |
40f860cd PM |
14610 | dc->condexec_mask = 0; |
14611 | dc->condexec_cond = 0; | |
aad821ac | 14612 | core_mmu_idx = FIELD_EX32(tb_flags, TBFLAG_ANY, MMUIDX); |
20dc67c9 | 14613 | dc->mmu_idx = core_to_aa64_mmu_idx(core_mmu_idx); |
476a4692 | 14614 | dc->tbii = FIELD_EX32(tb_flags, TBFLAG_A64, TBII); |
4a9ee99d | 14615 | dc->tbid = FIELD_EX32(tb_flags, TBFLAG_A64, TBID); |
81ae05fa | 14616 | dc->tcma = FIELD_EX32(tb_flags, TBFLAG_A64, TCMA); |
c1e37810 | 14617 | dc->current_el = arm_mmu_idx_to_el(dc->mmu_idx); |
40f860cd | 14618 | #if !defined(CONFIG_USER_ONLY) |
c1e37810 | 14619 | dc->user = (dc->current_el == 0); |
40f860cd | 14620 | #endif |
aad821ac RH |
14621 | dc->fp_excp_el = FIELD_EX32(tb_flags, TBFLAG_ANY, FPEXC_EL); |
14622 | dc->sve_excp_el = FIELD_EX32(tb_flags, TBFLAG_A64, SVEEXC_EL); | |
14623 | dc->sve_len = (FIELD_EX32(tb_flags, TBFLAG_A64, ZCR_LEN) + 1) * 16; | |
0816ef1b | 14624 | dc->pauth_active = FIELD_EX32(tb_flags, TBFLAG_A64, PAUTH_ACTIVE); |
08f1434a RH |
14625 | dc->bt = FIELD_EX32(tb_flags, TBFLAG_A64, BT); |
14626 | dc->btype = FIELD_EX32(tb_flags, TBFLAG_A64, BTYPE); | |
cc28fc30 | 14627 | dc->unpriv = FIELD_EX32(tb_flags, TBFLAG_A64, UNPRIV); |
81ae05fa RH |
14628 | dc->ata = FIELD_EX32(tb_flags, TBFLAG_A64, ATA); |
14629 | dc->mte_active[0] = FIELD_EX32(tb_flags, TBFLAG_A64, MTE_ACTIVE); | |
14630 | dc->mte_active[1] = FIELD_EX32(tb_flags, TBFLAG_A64, MTE0_ACTIVE); | |
40f860cd PM |
14631 | dc->vec_len = 0; |
14632 | dc->vec_stride = 0; | |
5c039906 | 14633 | dc->cp_regs = arm_cpu->cp_regs; |
a984e42c | 14634 | dc->features = env->features; |
5f716a82 | 14635 | dc->dcz_blocksize = arm_cpu->dcz_blocksize; |
40f860cd | 14636 | |
c4af8ba1 RH |
14637 | #ifdef CONFIG_USER_ONLY |
14638 | /* In sve_probe_page, we assume TBI is enabled. */ | |
14639 | tcg_debug_assert(dc->tbid & 1); | |
14640 | #endif | |
14641 | ||
7ea47fe7 PM |
14642 | /* Single step state. The code-generation logic here is: |
14643 | * SS_ACTIVE == 0: | |
14644 | * generate code with no special handling for single-stepping (except | |
14645 | * that anything that can make us go to SS_ACTIVE == 1 must end the TB; | |
14646 | * this happens anyway because those changes are all system register or | |
14647 | * PSTATE writes). | |
14648 | * SS_ACTIVE == 1, PSTATE.SS == 1: (active-not-pending) | |
14649 | * emit code for one insn | |
14650 | * emit code to clear PSTATE.SS | |
14651 | * emit code to generate software step exception for completed step | |
14652 | * end TB (as usual for having generated an exception) | |
14653 | * SS_ACTIVE == 1, PSTATE.SS == 0: (active-pending) | |
14654 | * emit code to generate a software step exception | |
14655 | * end the TB | |
14656 | */ | |
aad821ac RH |
14657 | dc->ss_active = FIELD_EX32(tb_flags, TBFLAG_ANY, SS_ACTIVE); |
14658 | dc->pstate_ss = FIELD_EX32(tb_flags, TBFLAG_ANY, PSTATE_SS); | |
7ea47fe7 | 14659 | dc->is_ldex = false; |
8bd587c1 | 14660 | dc->debug_target_el = FIELD_EX32(tb_flags, TBFLAG_ANY, DEBUG_TARGET_EL); |
7ea47fe7 | 14661 | |
dcc3a212 RH |
14662 | /* Bound the number of insns to execute to those left on the page. */ |
14663 | bound = -(dc->base.pc_first | TARGET_PAGE_MASK) / 4; | |
14664 | ||
14665 | /* If architectural single step active, limit to 1. */ | |
14666 | if (dc->ss_active) { | |
14667 | bound = 1; | |
14668 | } | |
b542683d | 14669 | dc->base.max_insns = MIN(dc->base.max_insns, bound); |
24299c89 | 14670 | |
11e169de | 14671 | init_tmp_a64_array(dc); |
5c039906 LV |
14672 | } |
14673 | ||
23169224 LV |
14674 | static void aarch64_tr_tb_start(DisasContextBase *db, CPUState *cpu) |
14675 | { | |
23169224 LV |
14676 | } |
14677 | ||
a68956ad LV |
14678 | static void aarch64_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) |
14679 | { | |
14680 | DisasContext *dc = container_of(dcbase, DisasContext, base); | |
14681 | ||
a0415916 | 14682 | tcg_gen_insn_start(dc->base.pc_next, 0, 0); |
15fa08f8 | 14683 | dc->insn_start = tcg_last_op(); |
a68956ad LV |
14684 | } |
14685 | ||
0cb56b37 LV |
14686 | static bool aarch64_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu, |
14687 | const CPUBreakpoint *bp) | |
14688 | { | |
14689 | DisasContext *dc = container_of(dcbase, DisasContext, base); | |
14690 | ||
14691 | if (bp->flags & BP_CPU) { | |
a0415916 | 14692 | gen_a64_set_pc_im(dc->base.pc_next); |
0cb56b37 LV |
14693 | gen_helper_check_breakpoints(cpu_env); |
14694 | /* End the TB early; it likely won't be executed */ | |
14695 | dc->base.is_jmp = DISAS_TOO_MANY; | |
14696 | } else { | |
aee828e7 | 14697 | gen_exception_internal_insn(dc, dc->base.pc_next, EXCP_DEBUG); |
0cb56b37 LV |
14698 | /* The address covered by the breakpoint must be |
14699 | included in [tb->pc, tb->pc + tb->size) in order | |
14700 | to for it to be properly cleared -- thus we | |
14701 | increment the PC here so that the logic setting | |
14702 | tb->size below does the right thing. */ | |
a0415916 | 14703 | dc->base.pc_next += 4; |
0cb56b37 LV |
14704 | dc->base.is_jmp = DISAS_NORETURN; |
14705 | } | |
14706 | ||
14707 | return true; | |
14708 | } | |
14709 | ||
24299c89 LV |
14710 | static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) |
14711 | { | |
14712 | DisasContext *dc = container_of(dcbase, DisasContext, base); | |
14713 | CPUARMState *env = cpu->env_ptr; | |
14714 | ||
14715 | if (dc->ss_active && !dc->pstate_ss) { | |
14716 | /* Singlestep state is Active-pending. | |
14717 | * If we're in this state at the start of a TB then either | |
14718 | * a) we just took an exception to an EL which is being debugged | |
14719 | * and this is the first insn in the exception handler | |
14720 | * b) debug exceptions were masked and we just unmasked them | |
14721 | * without changing EL (eg by clearing PSTATE.D) | |
14722 | * In either case we're going to take a swstep exception in the | |
14723 | * "did not step an insn" case, and so the syndrome ISV and EX | |
14724 | * bits should be zero. | |
14725 | */ | |
14726 | assert(dc->base.num_insns == 1); | |
c1d5f50f | 14727 | gen_swstep_exception(dc, 0, 0); |
24299c89 LV |
14728 | dc->base.is_jmp = DISAS_NORETURN; |
14729 | } else { | |
14730 | disas_a64_insn(env, dc); | |
14731 | } | |
14732 | ||
23169224 | 14733 | translator_loop_temp_check(&dc->base); |
24299c89 LV |
14734 | } |
14735 | ||
be407964 LV |
14736 | static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) |
14737 | { | |
14738 | DisasContext *dc = container_of(dcbase, DisasContext, base); | |
14739 | ||
14740 | if (unlikely(dc->base.singlestep_enabled || dc->ss_active)) { | |
14741 | /* Note that this means single stepping WFI doesn't halt the CPU. | |
14742 | * For conditional branch insns this is harmless unreachable code as | |
14743 | * gen_goto_tb() has already handled emitting the debug exception | |
14744 | * (and thus a tb-jump is not possible when singlestepping). | |
14745 | */ | |
14746 | switch (dc->base.is_jmp) { | |
14747 | default: | |
a0415916 | 14748 | gen_a64_set_pc_im(dc->base.pc_next); |
be407964 | 14749 | /* fall through */ |
dddbba99 | 14750 | case DISAS_EXIT: |
be407964 LV |
14751 | case DISAS_JUMP: |
14752 | if (dc->base.singlestep_enabled) { | |
14753 | gen_exception_internal(EXCP_DEBUG); | |
14754 | } else { | |
14755 | gen_step_complete_exception(dc); | |
14756 | } | |
14757 | break; | |
14758 | case DISAS_NORETURN: | |
14759 | break; | |
14760 | } | |
14761 | } else { | |
14762 | switch (dc->base.is_jmp) { | |
14763 | case DISAS_NEXT: | |
14764 | case DISAS_TOO_MANY: | |
a0415916 | 14765 | gen_goto_tb(dc, 1, dc->base.pc_next); |
be407964 LV |
14766 | break; |
14767 | default: | |
14407ec2 | 14768 | case DISAS_UPDATE_EXIT: |
a0415916 | 14769 | gen_a64_set_pc_im(dc->base.pc_next); |
be407964 | 14770 | /* fall through */ |
be407964 | 14771 | case DISAS_EXIT: |
07ea28b4 | 14772 | tcg_gen_exit_tb(NULL, 0); |
be407964 | 14773 | break; |
32983328 RH |
14774 | case DISAS_UPDATE_NOCHAIN: |
14775 | gen_a64_set_pc_im(dc->base.pc_next); | |
14776 | /* fall through */ | |
a75a52d6 VK |
14777 | case DISAS_JUMP: |
14778 | tcg_gen_lookup_and_goto_ptr(); | |
14779 | break; | |
be407964 LV |
14780 | case DISAS_NORETURN: |
14781 | case DISAS_SWI: | |
14782 | break; | |
14783 | case DISAS_WFE: | |
a0415916 | 14784 | gen_a64_set_pc_im(dc->base.pc_next); |
be407964 LV |
14785 | gen_helper_wfe(cpu_env); |
14786 | break; | |
14787 | case DISAS_YIELD: | |
a0415916 | 14788 | gen_a64_set_pc_im(dc->base.pc_next); |
be407964 LV |
14789 | gen_helper_yield(cpu_env); |
14790 | break; | |
14791 | case DISAS_WFI: | |
58803318 | 14792 | { |
be407964 LV |
14793 | /* This is a special case because we don't want to just halt the CPU |
14794 | * if trying to debug across a WFI. | |
14795 | */ | |
58803318 SS |
14796 | TCGv_i32 tmp = tcg_const_i32(4); |
14797 | ||
a0415916 | 14798 | gen_a64_set_pc_im(dc->base.pc_next); |
58803318 SS |
14799 | gen_helper_wfi(cpu_env, tmp); |
14800 | tcg_temp_free_i32(tmp); | |
be407964 LV |
14801 | /* The helper doesn't necessarily throw an exception, but we |
14802 | * must go back to the main loop to check for interrupts anyway. | |
14803 | */ | |
07ea28b4 | 14804 | tcg_gen_exit_tb(NULL, 0); |
be407964 LV |
14805 | break; |
14806 | } | |
58803318 | 14807 | } |
be407964 LV |
14808 | } |
14809 | } | |
14810 | ||
58350fa4 LV |
14811 | static void aarch64_tr_disas_log(const DisasContextBase *dcbase, |
14812 | CPUState *cpu) | |
14813 | { | |
14814 | DisasContext *dc = container_of(dcbase, DisasContext, base); | |
14815 | ||
14816 | qemu_log("IN: %s\n", lookup_symbol(dc->base.pc_first)); | |
1d48474d | 14817 | log_target_disas(cpu, dc->base.pc_first, dc->base.tb->size); |
58350fa4 LV |
14818 | } |
14819 | ||
23169224 LV |
14820 | const TranslatorOps aarch64_translator_ops = { |
14821 | .init_disas_context = aarch64_tr_init_disas_context, | |
14822 | .tb_start = aarch64_tr_tb_start, | |
14823 | .insn_start = aarch64_tr_insn_start, | |
14824 | .breakpoint_check = aarch64_tr_breakpoint_check, | |
14825 | .translate_insn = aarch64_tr_translate_insn, | |
14826 | .tb_stop = aarch64_tr_tb_stop, | |
14827 | .disas_log = aarch64_tr_disas_log, | |
14828 | }; |