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14ade10f AG |
1 | /* |
2 | * AArch64 translation | |
3 | * | |
4 | * Copyright (c) 2013 Alexander Graf <agraf@suse.de> | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
74c21bd0 | 19 | #include "qemu/osdep.h" |
14ade10f AG |
20 | |
21 | #include "cpu.h" | |
63c91552 | 22 | #include "exec/exec-all.h" |
dcb32f1d PMD |
23 | #include "tcg/tcg-op.h" |
24 | #include "tcg/tcg-op-gvec.h" | |
14ade10f | 25 | #include "qemu/log.h" |
1d854765 | 26 | #include "arm_ldst.h" |
14ade10f | 27 | #include "translate.h" |
ccd38087 | 28 | #include "internals.h" |
14ade10f AG |
29 | #include "qemu/host-utils.h" |
30 | ||
f1672e6f | 31 | #include "hw/semihosting/semihost.h" |
40f860cd PM |
32 | #include "exec/gen-icount.h" |
33 | ||
2ef6175a RH |
34 | #include "exec/helper-proto.h" |
35 | #include "exec/helper-gen.h" | |
508127e2 | 36 | #include "exec/log.h" |
14ade10f | 37 | |
a7e30d84 | 38 | #include "trace-tcg.h" |
8c71baed | 39 | #include "translate-a64.h" |
62823083 | 40 | #include "qemu/atomic128.h" |
a7e30d84 | 41 | |
14ade10f AG |
42 | static TCGv_i64 cpu_X[32]; |
43 | static TCGv_i64 cpu_pc; | |
14ade10f | 44 | |
fa2ef212 | 45 | /* Load/store exclusive handling */ |
fa2ef212 | 46 | static TCGv_i64 cpu_exclusive_high; |
fa2ef212 | 47 | |
14ade10f AG |
48 | static const char *regnames[] = { |
49 | "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", | |
50 | "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", | |
51 | "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", | |
52 | "x24", "x25", "x26", "x27", "x28", "x29", "lr", "sp" | |
53 | }; | |
54 | ||
832ffa1c AG |
55 | enum a64_shift_type { |
56 | A64_SHIFT_TYPE_LSL = 0, | |
57 | A64_SHIFT_TYPE_LSR = 1, | |
58 | A64_SHIFT_TYPE_ASR = 2, | |
59 | A64_SHIFT_TYPE_ROR = 3 | |
60 | }; | |
61 | ||
384b26fb AB |
62 | /* Table based decoder typedefs - used when the relevant bits for decode |
63 | * are too awkwardly scattered across the instruction (eg SIMD). | |
64 | */ | |
65 | typedef void AArch64DecodeFn(DisasContext *s, uint32_t insn); | |
66 | ||
67 | typedef struct AArch64DecodeTable { | |
68 | uint32_t pattern; | |
69 | uint32_t mask; | |
70 | AArch64DecodeFn *disas_fn; | |
71 | } AArch64DecodeTable; | |
72 | ||
14ade10f AG |
73 | /* initialize TCG globals. */ |
74 | void a64_translate_init(void) | |
75 | { | |
76 | int i; | |
77 | ||
e1ccc054 | 78 | cpu_pc = tcg_global_mem_new_i64(cpu_env, |
14ade10f AG |
79 | offsetof(CPUARMState, pc), |
80 | "pc"); | |
81 | for (i = 0; i < 32; i++) { | |
e1ccc054 | 82 | cpu_X[i] = tcg_global_mem_new_i64(cpu_env, |
14ade10f AG |
83 | offsetof(CPUARMState, xregs[i]), |
84 | regnames[i]); | |
85 | } | |
86 | ||
e1ccc054 | 87 | cpu_exclusive_high = tcg_global_mem_new_i64(cpu_env, |
fa2ef212 | 88 | offsetof(CPUARMState, exclusive_high), "exclusive_high"); |
14ade10f AG |
89 | } |
90 | ||
cc28fc30 RH |
91 | /* |
92 | * Return the core mmu_idx to use for A64 "unprivileged load/store" insns | |
93 | */ | |
94 | static int get_a64_user_mem_index(DisasContext *s) | |
579d21cc | 95 | { |
cc28fc30 RH |
96 | /* |
97 | * If AccType_UNPRIV is not used, the insn uses AccType_NORMAL, | |
98 | * which is the usual mmu_idx for this cpu state. | |
579d21cc | 99 | */ |
cc28fc30 | 100 | ARMMMUIdx useridx = s->mmu_idx; |
8bd5c820 | 101 | |
cc28fc30 RH |
102 | if (s->unpriv) { |
103 | /* | |
104 | * We have pre-computed the condition for AccType_UNPRIV. | |
105 | * Therefore we should never get here with a mmu_idx for | |
106 | * which we do not know the corresponding user mmu_idx. | |
107 | */ | |
108 | switch (useridx) { | |
109 | case ARMMMUIdx_E10_1: | |
452ef8cb | 110 | case ARMMMUIdx_E10_1_PAN: |
cc28fc30 RH |
111 | useridx = ARMMMUIdx_E10_0; |
112 | break; | |
113 | case ARMMMUIdx_E20_2: | |
452ef8cb | 114 | case ARMMMUIdx_E20_2_PAN: |
cc28fc30 RH |
115 | useridx = ARMMMUIdx_E20_0; |
116 | break; | |
117 | case ARMMMUIdx_SE10_1: | |
452ef8cb | 118 | case ARMMMUIdx_SE10_1_PAN: |
cc28fc30 RH |
119 | useridx = ARMMMUIdx_SE10_0; |
120 | break; | |
121 | default: | |
122 | g_assert_not_reached(); | |
123 | } | |
579d21cc | 124 | } |
8bd5c820 | 125 | return arm_to_core_mmu_idx(useridx); |
579d21cc PM |
126 | } |
127 | ||
51bf0d7a RH |
128 | static void reset_btype(DisasContext *s) |
129 | { | |
130 | if (s->btype != 0) { | |
131 | TCGv_i32 zero = tcg_const_i32(0); | |
132 | tcg_gen_st_i32(zero, cpu_env, offsetof(CPUARMState, btype)); | |
133 | tcg_temp_free_i32(zero); | |
134 | s->btype = 0; | |
135 | } | |
136 | } | |
137 | ||
001d47b6 RH |
138 | static void set_btype(DisasContext *s, int val) |
139 | { | |
140 | TCGv_i32 tcg_val; | |
141 | ||
142 | /* BTYPE is a 2-bit field, and 0 should be done with reset_btype. */ | |
143 | tcg_debug_assert(val >= 1 && val <= 3); | |
144 | ||
145 | tcg_val = tcg_const_i32(val); | |
146 | tcg_gen_st_i32(tcg_val, cpu_env, offsetof(CPUARMState, btype)); | |
147 | tcg_temp_free_i32(tcg_val); | |
148 | s->btype = -1; | |
149 | } | |
150 | ||
14ade10f AG |
151 | void gen_a64_set_pc_im(uint64_t val) |
152 | { | |
153 | tcg_gen_movi_i64(cpu_pc, val); | |
154 | } | |
155 | ||
4a9ee99d RH |
156 | /* |
157 | * Handle Top Byte Ignore (TBI) bits. | |
6feecb8b | 158 | * |
4a9ee99d | 159 | * If address tagging is enabled via the TCR TBI bits: |
6feecb8b TH |
160 | * + for EL2 and EL3 there is only one TBI bit, and if it is set |
161 | * then the address is zero-extended, clearing bits [63:56] | |
162 | * + for EL0 and EL1, TBI0 controls addresses with bit 55 == 0 | |
163 | * and TBI1 controls addressses with bit 55 == 1. | |
164 | * If the appropriate TBI bit is set for the address then | |
165 | * the address is sign-extended from bit 55 into bits [63:56] | |
166 | * | |
4a9ee99d | 167 | * Here We have concatenated TBI{1,0} into tbi. |
6feecb8b | 168 | */ |
4a9ee99d RH |
169 | static void gen_top_byte_ignore(DisasContext *s, TCGv_i64 dst, |
170 | TCGv_i64 src, int tbi) | |
6feecb8b | 171 | { |
4a9ee99d RH |
172 | if (tbi == 0) { |
173 | /* Load unmodified address */ | |
174 | tcg_gen_mov_i64(dst, src); | |
339370b9 | 175 | } else if (!regime_has_2_ranges(s->mmu_idx)) { |
4a9ee99d RH |
176 | /* Force tag byte to all zero */ |
177 | tcg_gen_extract_i64(dst, src, 0, 56); | |
178 | } else { | |
179 | /* Sign-extend from bit 55. */ | |
180 | tcg_gen_sextract_i64(dst, src, 0, 56); | |
6feecb8b | 181 | |
4a9ee99d RH |
182 | if (tbi != 3) { |
183 | TCGv_i64 tcg_zero = tcg_const_i64(0); | |
6feecb8b | 184 | |
4a9ee99d RH |
185 | /* |
186 | * The two TBI bits differ. | |
187 | * If tbi0, then !tbi1: only use the extension if positive. | |
188 | * if !tbi0, then tbi1: only use the extension if negative. | |
189 | */ | |
190 | tcg_gen_movcond_i64(tbi == 1 ? TCG_COND_GE : TCG_COND_LT, | |
191 | dst, dst, tcg_zero, dst, src); | |
192 | tcg_temp_free_i64(tcg_zero); | |
6feecb8b TH |
193 | } |
194 | } | |
4a9ee99d | 195 | } |
8733d762 | 196 | |
4a9ee99d RH |
197 | static void gen_a64_set_pc(DisasContext *s, TCGv_i64 src) |
198 | { | |
199 | /* | |
200 | * If address tagging is enabled for instructions via the TCR TBI bits, | |
201 | * then loading an address into the PC will clear out any tag. | |
202 | */ | |
203 | gen_top_byte_ignore(s, cpu_pc, src, s->tbii); | |
6feecb8b TH |
204 | } |
205 | ||
3a471103 RH |
206 | /* |
207 | * Return a "clean" address for ADDR according to TBID. | |
208 | * This is always a fresh temporary, as we need to be able to | |
209 | * increment this independently of a dirty write-back address. | |
210 | */ | |
211 | static TCGv_i64 clean_data_tbi(DisasContext *s, TCGv_i64 addr) | |
212 | { | |
213 | TCGv_i64 clean = new_tmp_a64(s); | |
38d93168 RH |
214 | /* |
215 | * In order to get the correct value in the FAR_ELx register, | |
216 | * we must present the memory subsystem with the "dirty" address | |
217 | * including the TBI. In system mode we can make this work via | |
218 | * the TLB, dropping the TBI during translation. But for user-only | |
219 | * mode we don't have that option, and must remove the top byte now. | |
220 | */ | |
221 | #ifdef CONFIG_USER_ONLY | |
3a471103 | 222 | gen_top_byte_ignore(s, clean, addr, s->tbid); |
38d93168 RH |
223 | #else |
224 | tcg_gen_mov_i64(clean, addr); | |
225 | #endif | |
3a471103 RH |
226 | return clean; |
227 | } | |
228 | ||
da54941f RH |
229 | /* Insert a zero tag into src, with the result at dst. */ |
230 | static void gen_address_with_allocation_tag0(TCGv_i64 dst, TCGv_i64 src) | |
231 | { | |
232 | tcg_gen_andi_i64(dst, src, ~MAKE_64BIT_MASK(56, 4)); | |
233 | } | |
234 | ||
259cb684 RH |
235 | typedef struct DisasCompare64 { |
236 | TCGCond cond; | |
237 | TCGv_i64 value; | |
238 | } DisasCompare64; | |
239 | ||
240 | static void a64_test_cc(DisasCompare64 *c64, int cc) | |
241 | { | |
242 | DisasCompare c32; | |
243 | ||
244 | arm_test_cc(&c32, cc); | |
245 | ||
246 | /* Sign-extend the 32-bit value so that the GE/LT comparisons work | |
247 | * properly. The NE/EQ comparisons are also fine with this choice. */ | |
248 | c64->cond = c32.cond; | |
249 | c64->value = tcg_temp_new_i64(); | |
250 | tcg_gen_ext_i32_i64(c64->value, c32.value); | |
251 | ||
252 | arm_free_cc(&c32); | |
253 | } | |
254 | ||
255 | static void a64_free_cc(DisasCompare64 *c64) | |
256 | { | |
257 | tcg_temp_free_i64(c64->value); | |
258 | } | |
259 | ||
d4a2dc67 | 260 | static void gen_exception_internal(int excp) |
14ade10f | 261 | { |
d4a2dc67 PM |
262 | TCGv_i32 tcg_excp = tcg_const_i32(excp); |
263 | ||
264 | assert(excp_is_internal(excp)); | |
265 | gen_helper_exception_internal(cpu_env, tcg_excp); | |
266 | tcg_temp_free_i32(tcg_excp); | |
267 | } | |
268 | ||
aee828e7 | 269 | static void gen_exception_internal_insn(DisasContext *s, uint64_t pc, int excp) |
d4a2dc67 | 270 | { |
aee828e7 | 271 | gen_a64_set_pc_im(pc); |
d4a2dc67 | 272 | gen_exception_internal(excp); |
dcba3a8d | 273 | s->base.is_jmp = DISAS_NORETURN; |
14ade10f AG |
274 | } |
275 | ||
a767fac8 | 276 | static void gen_exception_insn(DisasContext *s, uint64_t pc, int excp, |
73710361 | 277 | uint32_t syndrome, uint32_t target_el) |
14ade10f | 278 | { |
a767fac8 | 279 | gen_a64_set_pc_im(pc); |
73710361 | 280 | gen_exception(excp, syndrome, target_el); |
dcba3a8d | 281 | s->base.is_jmp = DISAS_NORETURN; |
40f860cd PM |
282 | } |
283 | ||
06bcbda3 | 284 | static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syndrome) |
c900a2e6 PM |
285 | { |
286 | TCGv_i32 tcg_syn; | |
287 | ||
06bcbda3 | 288 | gen_a64_set_pc_im(s->pc_curr); |
c900a2e6 PM |
289 | tcg_syn = tcg_const_i32(syndrome); |
290 | gen_helper_exception_bkpt_insn(cpu_env, tcg_syn); | |
291 | tcg_temp_free_i32(tcg_syn); | |
292 | s->base.is_jmp = DISAS_NORETURN; | |
293 | } | |
294 | ||
7ea47fe7 PM |
295 | static void gen_step_complete_exception(DisasContext *s) |
296 | { | |
297 | /* We just completed step of an insn. Move from Active-not-pending | |
298 | * to Active-pending, and then also take the swstep exception. | |
299 | * This corresponds to making the (IMPDEF) choice to prioritize | |
300 | * swstep exceptions over asynchronous exceptions taken to an exception | |
301 | * level where debug is disabled. This choice has the advantage that | |
302 | * we do not need to maintain internal state corresponding to the | |
303 | * ISV/EX syndrome bits between completion of the step and generation | |
304 | * of the exception, and our syndrome information is always correct. | |
305 | */ | |
306 | gen_ss_advance(s); | |
c1d5f50f | 307 | gen_swstep_exception(s, 1, s->is_ldex); |
dcba3a8d | 308 | s->base.is_jmp = DISAS_NORETURN; |
7ea47fe7 PM |
309 | } |
310 | ||
40f860cd PM |
311 | static inline bool use_goto_tb(DisasContext *s, int n, uint64_t dest) |
312 | { | |
7ea47fe7 PM |
313 | /* No direct tb linking with singlestep (either QEMU's or the ARM |
314 | * debug architecture kind) or deterministic io | |
315 | */ | |
c5a49c63 EC |
316 | if (s->base.singlestep_enabled || s->ss_active || |
317 | (tb_cflags(s->base.tb) & CF_LAST_IO)) { | |
40f860cd PM |
318 | return false; |
319 | } | |
320 | ||
90aa39a1 | 321 | #ifndef CONFIG_USER_ONLY |
40f860cd | 322 | /* Only link tbs from inside the same guest page */ |
dcba3a8d | 323 | if ((s->base.tb->pc & TARGET_PAGE_MASK) != (dest & TARGET_PAGE_MASK)) { |
40f860cd PM |
324 | return false; |
325 | } | |
90aa39a1 | 326 | #endif |
40f860cd PM |
327 | |
328 | return true; | |
329 | } | |
330 | ||
331 | static inline void gen_goto_tb(DisasContext *s, int n, uint64_t dest) | |
332 | { | |
333 | TranslationBlock *tb; | |
334 | ||
dcba3a8d | 335 | tb = s->base.tb; |
40f860cd PM |
336 | if (use_goto_tb(s, n, dest)) { |
337 | tcg_gen_goto_tb(n); | |
338 | gen_a64_set_pc_im(dest); | |
07ea28b4 | 339 | tcg_gen_exit_tb(tb, n); |
dcba3a8d | 340 | s->base.is_jmp = DISAS_NORETURN; |
40f860cd PM |
341 | } else { |
342 | gen_a64_set_pc_im(dest); | |
7ea47fe7 PM |
343 | if (s->ss_active) { |
344 | gen_step_complete_exception(s); | |
dcba3a8d | 345 | } else if (s->base.singlestep_enabled) { |
d4a2dc67 | 346 | gen_exception_internal(EXCP_DEBUG); |
cc9c1ed1 | 347 | } else { |
7f11636d | 348 | tcg_gen_lookup_and_goto_ptr(); |
dcba3a8d | 349 | s->base.is_jmp = DISAS_NORETURN; |
40f860cd | 350 | } |
40f860cd | 351 | } |
14ade10f AG |
352 | } |
353 | ||
429a71d6 RH |
354 | void unallocated_encoding(DisasContext *s) |
355 | { | |
356 | /* Unallocated and reserved encodings are uncategorized */ | |
357 | gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(), | |
358 | default_exception_el(s)); | |
359 | } | |
360 | ||
11e169de AG |
361 | static void init_tmp_a64_array(DisasContext *s) |
362 | { | |
363 | #ifdef CONFIG_DEBUG_TCG | |
f764718d | 364 | memset(s->tmp_a64, 0, sizeof(s->tmp_a64)); |
11e169de AG |
365 | #endif |
366 | s->tmp_a64_count = 0; | |
367 | } | |
368 | ||
369 | static void free_tmp_a64(DisasContext *s) | |
370 | { | |
371 | int i; | |
372 | for (i = 0; i < s->tmp_a64_count; i++) { | |
373 | tcg_temp_free_i64(s->tmp_a64[i]); | |
374 | } | |
375 | init_tmp_a64_array(s); | |
376 | } | |
377 | ||
8c71baed | 378 | TCGv_i64 new_tmp_a64(DisasContext *s) |
11e169de AG |
379 | { |
380 | assert(s->tmp_a64_count < TMP_A64_MAX); | |
381 | return s->tmp_a64[s->tmp_a64_count++] = tcg_temp_new_i64(); | |
382 | } | |
383 | ||
8c71baed | 384 | TCGv_i64 new_tmp_a64_zero(DisasContext *s) |
11e169de AG |
385 | { |
386 | TCGv_i64 t = new_tmp_a64(s); | |
387 | tcg_gen_movi_i64(t, 0); | |
388 | return t; | |
389 | } | |
390 | ||
71b46089 AG |
391 | /* |
392 | * Register access functions | |
393 | * | |
394 | * These functions are used for directly accessing a register in where | |
395 | * changes to the final register value are likely to be made. If you | |
396 | * need to use a register for temporary calculation (e.g. index type | |
397 | * operations) use the read_* form. | |
398 | * | |
399 | * B1.2.1 Register mappings | |
400 | * | |
401 | * In instruction register encoding 31 can refer to ZR (zero register) or | |
402 | * the SP (stack pointer) depending on context. In QEMU's case we map SP | |
403 | * to cpu_X[31] and ZR accesses to a temporary which can be discarded. | |
404 | * This is the point of the _sp forms. | |
405 | */ | |
8c71baed | 406 | TCGv_i64 cpu_reg(DisasContext *s, int reg) |
11e169de AG |
407 | { |
408 | if (reg == 31) { | |
409 | return new_tmp_a64_zero(s); | |
410 | } else { | |
411 | return cpu_X[reg]; | |
412 | } | |
413 | } | |
414 | ||
71b46089 | 415 | /* register access for when 31 == SP */ |
8c71baed | 416 | TCGv_i64 cpu_reg_sp(DisasContext *s, int reg) |
71b46089 AG |
417 | { |
418 | return cpu_X[reg]; | |
419 | } | |
420 | ||
60e53388 AG |
421 | /* read a cpu register in 32bit/64bit mode. Returns a TCGv_i64 |
422 | * representing the register contents. This TCGv is an auto-freed | |
423 | * temporary so it need not be explicitly freed, and may be modified. | |
424 | */ | |
8c71baed | 425 | TCGv_i64 read_cpu_reg(DisasContext *s, int reg, int sf) |
60e53388 AG |
426 | { |
427 | TCGv_i64 v = new_tmp_a64(s); | |
428 | if (reg != 31) { | |
429 | if (sf) { | |
430 | tcg_gen_mov_i64(v, cpu_X[reg]); | |
431 | } else { | |
432 | tcg_gen_ext32u_i64(v, cpu_X[reg]); | |
433 | } | |
434 | } else { | |
435 | tcg_gen_movi_i64(v, 0); | |
436 | } | |
437 | return v; | |
438 | } | |
439 | ||
8c71baed | 440 | TCGv_i64 read_cpu_reg_sp(DisasContext *s, int reg, int sf) |
4a08d475 PM |
441 | { |
442 | TCGv_i64 v = new_tmp_a64(s); | |
443 | if (sf) { | |
444 | tcg_gen_mov_i64(v, cpu_X[reg]); | |
445 | } else { | |
446 | tcg_gen_ext32u_i64(v, cpu_X[reg]); | |
447 | } | |
448 | return v; | |
449 | } | |
450 | ||
e2f90565 PM |
451 | /* Return the offset into CPUARMState of a slice (from |
452 | * the least significant end) of FP register Qn (ie | |
453 | * Dn, Sn, Hn or Bn). | |
454 | * (Note that this is not the same mapping as for A32; see cpu.h) | |
455 | */ | |
14776ab5 | 456 | static inline int fp_reg_offset(DisasContext *s, int regno, MemOp size) |
e2f90565 | 457 | { |
9a2b5256 | 458 | return vec_reg_offset(s, regno, 0, size); |
e2f90565 PM |
459 | } |
460 | ||
461 | /* Offset of the high half of the 128 bit vector Qn */ | |
90e49638 | 462 | static inline int fp_reg_hi_offset(DisasContext *s, int regno) |
e2f90565 | 463 | { |
9a2b5256 | 464 | return vec_reg_offset(s, regno, 1, MO_64); |
e2f90565 PM |
465 | } |
466 | ||
ec73d2e0 AG |
467 | /* Convenience accessors for reading and writing single and double |
468 | * FP registers. Writing clears the upper parts of the associated | |
469 | * 128 bit vector register, as required by the architecture. | |
470 | * Note that unlike the GP register accessors, the values returned | |
471 | * by the read functions must be manually freed. | |
472 | */ | |
473 | static TCGv_i64 read_fp_dreg(DisasContext *s, int reg) | |
474 | { | |
475 | TCGv_i64 v = tcg_temp_new_i64(); | |
476 | ||
90e49638 | 477 | tcg_gen_ld_i64(v, cpu_env, fp_reg_offset(s, reg, MO_64)); |
ec73d2e0 AG |
478 | return v; |
479 | } | |
480 | ||
481 | static TCGv_i32 read_fp_sreg(DisasContext *s, int reg) | |
482 | { | |
483 | TCGv_i32 v = tcg_temp_new_i32(); | |
484 | ||
90e49638 | 485 | tcg_gen_ld_i32(v, cpu_env, fp_reg_offset(s, reg, MO_32)); |
ec73d2e0 AG |
486 | return v; |
487 | } | |
488 | ||
3d99d931 RH |
489 | static TCGv_i32 read_fp_hreg(DisasContext *s, int reg) |
490 | { | |
491 | TCGv_i32 v = tcg_temp_new_i32(); | |
492 | ||
493 | tcg_gen_ld16u_i32(v, cpu_env, fp_reg_offset(s, reg, MO_16)); | |
494 | return v; | |
495 | } | |
496 | ||
4ff55bcb RH |
497 | /* Clear the bits above an N-bit vector, for N = (is_q ? 128 : 64). |
498 | * If SVE is not enabled, then there are only 128 bits in the vector. | |
499 | */ | |
500 | static void clear_vec_high(DisasContext *s, bool is_q, int rd) | |
501 | { | |
502 | unsigned ofs = fp_reg_offset(s, rd, MO_64); | |
503 | unsigned vsz = vec_full_reg_size(s); | |
504 | ||
5c27392d RH |
505 | /* Nop move, with side effect of clearing the tail. */ |
506 | tcg_gen_gvec_mov(MO_64, ofs, ofs, is_q ? 16 : 8, vsz); | |
4ff55bcb RH |
507 | } |
508 | ||
8c71baed | 509 | void write_fp_dreg(DisasContext *s, int reg, TCGv_i64 v) |
ec73d2e0 | 510 | { |
4ff55bcb | 511 | unsigned ofs = fp_reg_offset(s, reg, MO_64); |
ec73d2e0 | 512 | |
4ff55bcb RH |
513 | tcg_gen_st_i64(v, cpu_env, ofs); |
514 | clear_vec_high(s, false, reg); | |
ec73d2e0 AG |
515 | } |
516 | ||
517 | static void write_fp_sreg(DisasContext *s, int reg, TCGv_i32 v) | |
518 | { | |
519 | TCGv_i64 tmp = tcg_temp_new_i64(); | |
520 | ||
521 | tcg_gen_extu_i32_i64(tmp, v); | |
522 | write_fp_dreg(s, reg, tmp); | |
523 | tcg_temp_free_i64(tmp); | |
524 | } | |
525 | ||
8c71baed | 526 | TCGv_ptr get_fpstatus_ptr(bool is_f16) |
ec73d2e0 AG |
527 | { |
528 | TCGv_ptr statusptr = tcg_temp_new_ptr(); | |
529 | int offset; | |
530 | ||
d81ce0ef AB |
531 | /* In A64 all instructions (both FP and Neon) use the FPCR; there |
532 | * is no equivalent of the A32 Neon "standard FPSCR value". | |
533 | * However half-precision operations operate under a different | |
534 | * FZ16 flag and use vfp.fp_status_f16 instead of vfp.fp_status. | |
ec73d2e0 | 535 | */ |
d81ce0ef AB |
536 | if (is_f16) { |
537 | offset = offsetof(CPUARMState, vfp.fp_status_f16); | |
538 | } else { | |
539 | offset = offsetof(CPUARMState, vfp.fp_status); | |
540 | } | |
ec73d2e0 AG |
541 | tcg_gen_addi_ptr(statusptr, cpu_env, offset); |
542 | return statusptr; | |
543 | } | |
544 | ||
377ef731 RH |
545 | /* Expand a 2-operand AdvSIMD vector operation using an expander function. */ |
546 | static void gen_gvec_fn2(DisasContext *s, bool is_q, int rd, int rn, | |
547 | GVecGen2Fn *gvec_fn, int vece) | |
548 | { | |
549 | gvec_fn(vece, vec_full_reg_offset(s, rd), vec_full_reg_offset(s, rn), | |
550 | is_q ? 16 : 8, vec_full_reg_size(s)); | |
551 | } | |
552 | ||
cdb45a60 RH |
553 | /* Expand a 2-operand + immediate AdvSIMD vector operation using |
554 | * an expander function. | |
555 | */ | |
556 | static void gen_gvec_fn2i(DisasContext *s, bool is_q, int rd, int rn, | |
557 | int64_t imm, GVecGen2iFn *gvec_fn, int vece) | |
558 | { | |
559 | gvec_fn(vece, vec_full_reg_offset(s, rd), vec_full_reg_offset(s, rn), | |
560 | imm, is_q ? 16 : 8, vec_full_reg_size(s)); | |
561 | } | |
562 | ||
bc48092f RH |
563 | /* Expand a 3-operand AdvSIMD vector operation using an expander function. */ |
564 | static void gen_gvec_fn3(DisasContext *s, bool is_q, int rd, int rn, int rm, | |
565 | GVecGen3Fn *gvec_fn, int vece) | |
566 | { | |
567 | gvec_fn(vece, vec_full_reg_offset(s, rd), vec_full_reg_offset(s, rn), | |
568 | vec_full_reg_offset(s, rm), is_q ? 16 : 8, vec_full_reg_size(s)); | |
569 | } | |
570 | ||
3a7a2b4e RH |
571 | /* Expand a 4-operand AdvSIMD vector operation using an expander function. */ |
572 | static void gen_gvec_fn4(DisasContext *s, bool is_q, int rd, int rn, int rm, | |
573 | int rx, GVecGen4Fn *gvec_fn, int vece) | |
574 | { | |
575 | gvec_fn(vece, vec_full_reg_offset(s, rd), vec_full_reg_offset(s, rn), | |
576 | vec_full_reg_offset(s, rm), vec_full_reg_offset(s, rx), | |
577 | is_q ? 16 : 8, vec_full_reg_size(s)); | |
578 | } | |
579 | ||
a04b68e1 RH |
580 | /* Expand a 2-operand operation using an out-of-line helper. */ |
581 | static void gen_gvec_op2_ool(DisasContext *s, bool is_q, int rd, | |
582 | int rn, int data, gen_helper_gvec_2 *fn) | |
583 | { | |
584 | tcg_gen_gvec_2_ool(vec_full_reg_offset(s, rd), | |
585 | vec_full_reg_offset(s, rn), | |
586 | is_q ? 16 : 8, vec_full_reg_size(s), data, fn); | |
587 | } | |
588 | ||
26c470a7 RH |
589 | /* Expand a 3-operand operation using an out-of-line helper. */ |
590 | static void gen_gvec_op3_ool(DisasContext *s, bool is_q, int rd, | |
591 | int rn, int rm, int data, gen_helper_gvec_3 *fn) | |
592 | { | |
593 | tcg_gen_gvec_3_ool(vec_full_reg_offset(s, rd), | |
594 | vec_full_reg_offset(s, rn), | |
595 | vec_full_reg_offset(s, rm), | |
596 | is_q ? 16 : 8, vec_full_reg_size(s), data, fn); | |
597 | } | |
598 | ||
1695cd61 RH |
599 | /* Expand a 3-operand + fpstatus pointer + simd data value operation using |
600 | * an out-of-line helper. | |
601 | */ | |
602 | static void gen_gvec_op3_fpst(DisasContext *s, bool is_q, int rd, int rn, | |
603 | int rm, bool is_fp16, int data, | |
604 | gen_helper_gvec_3_ptr *fn) | |
605 | { | |
606 | TCGv_ptr fpst = get_fpstatus_ptr(is_fp16); | |
607 | tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd), | |
608 | vec_full_reg_offset(s, rn), | |
609 | vec_full_reg_offset(s, rm), fpst, | |
610 | is_q ? 16 : 8, vec_full_reg_size(s), data, fn); | |
611 | tcg_temp_free_ptr(fpst); | |
612 | } | |
613 | ||
832ffa1c AG |
614 | /* Set ZF and NF based on a 64 bit result. This is alas fiddlier |
615 | * than the 32 bit equivalent. | |
616 | */ | |
617 | static inline void gen_set_NZ64(TCGv_i64 result) | |
618 | { | |
7cb36e18 RH |
619 | tcg_gen_extr_i64_i32(cpu_ZF, cpu_NF, result); |
620 | tcg_gen_or_i32(cpu_ZF, cpu_ZF, cpu_NF); | |
832ffa1c AG |
621 | } |
622 | ||
623 | /* Set NZCV as for a logical operation: NZ as per result, CV cleared. */ | |
624 | static inline void gen_logic_CC(int sf, TCGv_i64 result) | |
625 | { | |
626 | if (sf) { | |
627 | gen_set_NZ64(result); | |
628 | } else { | |
ecc7b3aa | 629 | tcg_gen_extrl_i64_i32(cpu_ZF, result); |
7cb36e18 | 630 | tcg_gen_mov_i32(cpu_NF, cpu_ZF); |
832ffa1c AG |
631 | } |
632 | tcg_gen_movi_i32(cpu_CF, 0); | |
633 | tcg_gen_movi_i32(cpu_VF, 0); | |
634 | } | |
635 | ||
b0ff21b4 AB |
636 | /* dest = T0 + T1; compute C, N, V and Z flags */ |
637 | static void gen_add_CC(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1) | |
638 | { | |
639 | if (sf) { | |
640 | TCGv_i64 result, flag, tmp; | |
641 | result = tcg_temp_new_i64(); | |
642 | flag = tcg_temp_new_i64(); | |
643 | tmp = tcg_temp_new_i64(); | |
644 | ||
645 | tcg_gen_movi_i64(tmp, 0); | |
646 | tcg_gen_add2_i64(result, flag, t0, tmp, t1, tmp); | |
647 | ||
ecc7b3aa | 648 | tcg_gen_extrl_i64_i32(cpu_CF, flag); |
b0ff21b4 AB |
649 | |
650 | gen_set_NZ64(result); | |
651 | ||
652 | tcg_gen_xor_i64(flag, result, t0); | |
653 | tcg_gen_xor_i64(tmp, t0, t1); | |
654 | tcg_gen_andc_i64(flag, flag, tmp); | |
655 | tcg_temp_free_i64(tmp); | |
7cb36e18 | 656 | tcg_gen_extrh_i64_i32(cpu_VF, flag); |
b0ff21b4 AB |
657 | |
658 | tcg_gen_mov_i64(dest, result); | |
659 | tcg_temp_free_i64(result); | |
660 | tcg_temp_free_i64(flag); | |
661 | } else { | |
662 | /* 32 bit arithmetic */ | |
663 | TCGv_i32 t0_32 = tcg_temp_new_i32(); | |
664 | TCGv_i32 t1_32 = tcg_temp_new_i32(); | |
665 | TCGv_i32 tmp = tcg_temp_new_i32(); | |
666 | ||
667 | tcg_gen_movi_i32(tmp, 0); | |
ecc7b3aa RH |
668 | tcg_gen_extrl_i64_i32(t0_32, t0); |
669 | tcg_gen_extrl_i64_i32(t1_32, t1); | |
b0ff21b4 AB |
670 | tcg_gen_add2_i32(cpu_NF, cpu_CF, t0_32, tmp, t1_32, tmp); |
671 | tcg_gen_mov_i32(cpu_ZF, cpu_NF); | |
672 | tcg_gen_xor_i32(cpu_VF, cpu_NF, t0_32); | |
673 | tcg_gen_xor_i32(tmp, t0_32, t1_32); | |
674 | tcg_gen_andc_i32(cpu_VF, cpu_VF, tmp); | |
675 | tcg_gen_extu_i32_i64(dest, cpu_NF); | |
676 | ||
677 | tcg_temp_free_i32(tmp); | |
678 | tcg_temp_free_i32(t0_32); | |
679 | tcg_temp_free_i32(t1_32); | |
680 | } | |
681 | } | |
682 | ||
683 | /* dest = T0 - T1; compute C, N, V and Z flags */ | |
684 | static void gen_sub_CC(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1) | |
685 | { | |
686 | if (sf) { | |
687 | /* 64 bit arithmetic */ | |
688 | TCGv_i64 result, flag, tmp; | |
689 | ||
690 | result = tcg_temp_new_i64(); | |
691 | flag = tcg_temp_new_i64(); | |
692 | tcg_gen_sub_i64(result, t0, t1); | |
693 | ||
694 | gen_set_NZ64(result); | |
695 | ||
696 | tcg_gen_setcond_i64(TCG_COND_GEU, flag, t0, t1); | |
ecc7b3aa | 697 | tcg_gen_extrl_i64_i32(cpu_CF, flag); |
b0ff21b4 AB |
698 | |
699 | tcg_gen_xor_i64(flag, result, t0); | |
700 | tmp = tcg_temp_new_i64(); | |
701 | tcg_gen_xor_i64(tmp, t0, t1); | |
702 | tcg_gen_and_i64(flag, flag, tmp); | |
703 | tcg_temp_free_i64(tmp); | |
7cb36e18 | 704 | tcg_gen_extrh_i64_i32(cpu_VF, flag); |
b0ff21b4 AB |
705 | tcg_gen_mov_i64(dest, result); |
706 | tcg_temp_free_i64(flag); | |
707 | tcg_temp_free_i64(result); | |
708 | } else { | |
709 | /* 32 bit arithmetic */ | |
710 | TCGv_i32 t0_32 = tcg_temp_new_i32(); | |
711 | TCGv_i32 t1_32 = tcg_temp_new_i32(); | |
712 | TCGv_i32 tmp; | |
713 | ||
ecc7b3aa RH |
714 | tcg_gen_extrl_i64_i32(t0_32, t0); |
715 | tcg_gen_extrl_i64_i32(t1_32, t1); | |
b0ff21b4 AB |
716 | tcg_gen_sub_i32(cpu_NF, t0_32, t1_32); |
717 | tcg_gen_mov_i32(cpu_ZF, cpu_NF); | |
718 | tcg_gen_setcond_i32(TCG_COND_GEU, cpu_CF, t0_32, t1_32); | |
719 | tcg_gen_xor_i32(cpu_VF, cpu_NF, t0_32); | |
720 | tmp = tcg_temp_new_i32(); | |
721 | tcg_gen_xor_i32(tmp, t0_32, t1_32); | |
722 | tcg_temp_free_i32(t0_32); | |
723 | tcg_temp_free_i32(t1_32); | |
724 | tcg_gen_and_i32(cpu_VF, cpu_VF, tmp); | |
725 | tcg_temp_free_i32(tmp); | |
726 | tcg_gen_extu_i32_i64(dest, cpu_NF); | |
727 | } | |
728 | } | |
729 | ||
643dbb07 CF |
730 | /* dest = T0 + T1 + CF; do not compute flags. */ |
731 | static void gen_adc(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1) | |
732 | { | |
733 | TCGv_i64 flag = tcg_temp_new_i64(); | |
734 | tcg_gen_extu_i32_i64(flag, cpu_CF); | |
735 | tcg_gen_add_i64(dest, t0, t1); | |
736 | tcg_gen_add_i64(dest, dest, flag); | |
737 | tcg_temp_free_i64(flag); | |
738 | ||
739 | if (!sf) { | |
740 | tcg_gen_ext32u_i64(dest, dest); | |
741 | } | |
742 | } | |
743 | ||
744 | /* dest = T0 + T1 + CF; compute C, N, V and Z flags. */ | |
745 | static void gen_adc_CC(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1) | |
746 | { | |
747 | if (sf) { | |
748 | TCGv_i64 result, cf_64, vf_64, tmp; | |
749 | result = tcg_temp_new_i64(); | |
750 | cf_64 = tcg_temp_new_i64(); | |
751 | vf_64 = tcg_temp_new_i64(); | |
752 | tmp = tcg_const_i64(0); | |
753 | ||
754 | tcg_gen_extu_i32_i64(cf_64, cpu_CF); | |
755 | tcg_gen_add2_i64(result, cf_64, t0, tmp, cf_64, tmp); | |
756 | tcg_gen_add2_i64(result, cf_64, result, cf_64, t1, tmp); | |
ecc7b3aa | 757 | tcg_gen_extrl_i64_i32(cpu_CF, cf_64); |
643dbb07 CF |
758 | gen_set_NZ64(result); |
759 | ||
760 | tcg_gen_xor_i64(vf_64, result, t0); | |
761 | tcg_gen_xor_i64(tmp, t0, t1); | |
762 | tcg_gen_andc_i64(vf_64, vf_64, tmp); | |
7cb36e18 | 763 | tcg_gen_extrh_i64_i32(cpu_VF, vf_64); |
643dbb07 CF |
764 | |
765 | tcg_gen_mov_i64(dest, result); | |
766 | ||
767 | tcg_temp_free_i64(tmp); | |
768 | tcg_temp_free_i64(vf_64); | |
769 | tcg_temp_free_i64(cf_64); | |
770 | tcg_temp_free_i64(result); | |
771 | } else { | |
772 | TCGv_i32 t0_32, t1_32, tmp; | |
773 | t0_32 = tcg_temp_new_i32(); | |
774 | t1_32 = tcg_temp_new_i32(); | |
775 | tmp = tcg_const_i32(0); | |
776 | ||
ecc7b3aa RH |
777 | tcg_gen_extrl_i64_i32(t0_32, t0); |
778 | tcg_gen_extrl_i64_i32(t1_32, t1); | |
643dbb07 CF |
779 | tcg_gen_add2_i32(cpu_NF, cpu_CF, t0_32, tmp, cpu_CF, tmp); |
780 | tcg_gen_add2_i32(cpu_NF, cpu_CF, cpu_NF, cpu_CF, t1_32, tmp); | |
781 | ||
782 | tcg_gen_mov_i32(cpu_ZF, cpu_NF); | |
783 | tcg_gen_xor_i32(cpu_VF, cpu_NF, t0_32); | |
784 | tcg_gen_xor_i32(tmp, t0_32, t1_32); | |
785 | tcg_gen_andc_i32(cpu_VF, cpu_VF, tmp); | |
786 | tcg_gen_extu_i32_i64(dest, cpu_NF); | |
787 | ||
788 | tcg_temp_free_i32(tmp); | |
789 | tcg_temp_free_i32(t1_32); | |
790 | tcg_temp_free_i32(t0_32); | |
791 | } | |
792 | } | |
793 | ||
4a08d475 PM |
794 | /* |
795 | * Load/Store generators | |
796 | */ | |
797 | ||
798 | /* | |
60510aed | 799 | * Store from GPR register to memory. |
4a08d475 | 800 | */ |
60510aed | 801 | static void do_gpr_st_memidx(DisasContext *s, TCGv_i64 source, |
aaa1f954 EI |
802 | TCGv_i64 tcg_addr, int size, int memidx, |
803 | bool iss_valid, | |
804 | unsigned int iss_srt, | |
805 | bool iss_sf, bool iss_ar) | |
60510aed PM |
806 | { |
807 | g_assert(size <= 3); | |
aa6489da | 808 | tcg_gen_qemu_st_i64(source, tcg_addr, memidx, s->be_data + size); |
aaa1f954 EI |
809 | |
810 | if (iss_valid) { | |
811 | uint32_t syn; | |
812 | ||
813 | syn = syn_data_abort_with_iss(0, | |
814 | size, | |
815 | false, | |
816 | iss_srt, | |
817 | iss_sf, | |
818 | iss_ar, | |
819 | 0, 0, 0, 0, 0, false); | |
820 | disas_set_insn_syndrome(s, syn); | |
821 | } | |
60510aed PM |
822 | } |
823 | ||
4a08d475 | 824 | static void do_gpr_st(DisasContext *s, TCGv_i64 source, |
aaa1f954 EI |
825 | TCGv_i64 tcg_addr, int size, |
826 | bool iss_valid, | |
827 | unsigned int iss_srt, | |
828 | bool iss_sf, bool iss_ar) | |
4a08d475 | 829 | { |
aaa1f954 EI |
830 | do_gpr_st_memidx(s, source, tcg_addr, size, get_mem_index(s), |
831 | iss_valid, iss_srt, iss_sf, iss_ar); | |
4a08d475 PM |
832 | } |
833 | ||
834 | /* | |
835 | * Load from memory to GPR register | |
836 | */ | |
aaa1f954 EI |
837 | static void do_gpr_ld_memidx(DisasContext *s, |
838 | TCGv_i64 dest, TCGv_i64 tcg_addr, | |
839 | int size, bool is_signed, | |
840 | bool extend, int memidx, | |
841 | bool iss_valid, unsigned int iss_srt, | |
842 | bool iss_sf, bool iss_ar) | |
4a08d475 | 843 | { |
14776ab5 | 844 | MemOp memop = s->be_data + size; |
4a08d475 PM |
845 | |
846 | g_assert(size <= 3); | |
847 | ||
848 | if (is_signed) { | |
849 | memop += MO_SIGN; | |
850 | } | |
851 | ||
60510aed | 852 | tcg_gen_qemu_ld_i64(dest, tcg_addr, memidx, memop); |
4a08d475 PM |
853 | |
854 | if (extend && is_signed) { | |
855 | g_assert(size < 3); | |
856 | tcg_gen_ext32u_i64(dest, dest); | |
857 | } | |
aaa1f954 EI |
858 | |
859 | if (iss_valid) { | |
860 | uint32_t syn; | |
861 | ||
862 | syn = syn_data_abort_with_iss(0, | |
863 | size, | |
864 | is_signed, | |
865 | iss_srt, | |
866 | iss_sf, | |
867 | iss_ar, | |
868 | 0, 0, 0, 0, 0, false); | |
869 | disas_set_insn_syndrome(s, syn); | |
870 | } | |
4a08d475 PM |
871 | } |
872 | ||
aaa1f954 EI |
873 | static void do_gpr_ld(DisasContext *s, |
874 | TCGv_i64 dest, TCGv_i64 tcg_addr, | |
875 | int size, bool is_signed, bool extend, | |
876 | bool iss_valid, unsigned int iss_srt, | |
877 | bool iss_sf, bool iss_ar) | |
60510aed PM |
878 | { |
879 | do_gpr_ld_memidx(s, dest, tcg_addr, size, is_signed, extend, | |
aaa1f954 EI |
880 | get_mem_index(s), |
881 | iss_valid, iss_srt, iss_sf, iss_ar); | |
60510aed PM |
882 | } |
883 | ||
4a08d475 PM |
884 | /* |
885 | * Store from FP register to memory | |
886 | */ | |
887 | static void do_fp_st(DisasContext *s, int srcidx, TCGv_i64 tcg_addr, int size) | |
888 | { | |
889 | /* This writes the bottom N bits of a 128 bit wide vector to memory */ | |
4a08d475 | 890 | TCGv_i64 tmp = tcg_temp_new_i64(); |
90e49638 | 891 | tcg_gen_ld_i64(tmp, cpu_env, fp_reg_offset(s, srcidx, MO_64)); |
4a08d475 | 892 | if (size < 4) { |
aa6489da PC |
893 | tcg_gen_qemu_st_i64(tmp, tcg_addr, get_mem_index(s), |
894 | s->be_data + size); | |
4a08d475 | 895 | } else { |
aa6489da | 896 | bool be = s->be_data == MO_BE; |
4a08d475 | 897 | TCGv_i64 tcg_hiaddr = tcg_temp_new_i64(); |
aa6489da | 898 | |
4a08d475 | 899 | tcg_gen_addi_i64(tcg_hiaddr, tcg_addr, 8); |
aa6489da PC |
900 | tcg_gen_qemu_st_i64(tmp, be ? tcg_hiaddr : tcg_addr, get_mem_index(s), |
901 | s->be_data | MO_Q); | |
902 | tcg_gen_ld_i64(tmp, cpu_env, fp_reg_hi_offset(s, srcidx)); | |
903 | tcg_gen_qemu_st_i64(tmp, be ? tcg_addr : tcg_hiaddr, get_mem_index(s), | |
904 | s->be_data | MO_Q); | |
4a08d475 PM |
905 | tcg_temp_free_i64(tcg_hiaddr); |
906 | } | |
907 | ||
908 | tcg_temp_free_i64(tmp); | |
909 | } | |
910 | ||
911 | /* | |
912 | * Load from memory to FP register | |
913 | */ | |
914 | static void do_fp_ld(DisasContext *s, int destidx, TCGv_i64 tcg_addr, int size) | |
915 | { | |
916 | /* This always zero-extends and writes to a full 128 bit wide vector */ | |
4a08d475 | 917 | TCGv_i64 tmplo = tcg_temp_new_i64(); |
e1f77859 | 918 | TCGv_i64 tmphi = NULL; |
4a08d475 PM |
919 | |
920 | if (size < 4) { | |
14776ab5 | 921 | MemOp memop = s->be_data + size; |
4a08d475 PM |
922 | tcg_gen_qemu_ld_i64(tmplo, tcg_addr, get_mem_index(s), memop); |
923 | } else { | |
aa6489da | 924 | bool be = s->be_data == MO_BE; |
4a08d475 | 925 | TCGv_i64 tcg_hiaddr; |
aa6489da | 926 | |
4a08d475 PM |
927 | tmphi = tcg_temp_new_i64(); |
928 | tcg_hiaddr = tcg_temp_new_i64(); | |
929 | ||
4a08d475 | 930 | tcg_gen_addi_i64(tcg_hiaddr, tcg_addr, 8); |
aa6489da PC |
931 | tcg_gen_qemu_ld_i64(tmplo, be ? tcg_hiaddr : tcg_addr, get_mem_index(s), |
932 | s->be_data | MO_Q); | |
933 | tcg_gen_qemu_ld_i64(tmphi, be ? tcg_addr : tcg_hiaddr, get_mem_index(s), | |
934 | s->be_data | MO_Q); | |
4a08d475 PM |
935 | tcg_temp_free_i64(tcg_hiaddr); |
936 | } | |
937 | ||
90e49638 | 938 | tcg_gen_st_i64(tmplo, cpu_env, fp_reg_offset(s, destidx, MO_64)); |
4a08d475 | 939 | tcg_temp_free_i64(tmplo); |
4ff55bcb | 940 | |
e1f77859 RH |
941 | if (tmphi) { |
942 | tcg_gen_st_i64(tmphi, cpu_env, fp_reg_hi_offset(s, destidx)); | |
943 | tcg_temp_free_i64(tmphi); | |
944 | } | |
945 | clear_vec_high(s, tmphi != NULL, destidx); | |
4a08d475 PM |
946 | } |
947 | ||
72430bf5 AB |
948 | /* |
949 | * Vector load/store helpers. | |
950 | * | |
951 | * The principal difference between this and a FP load is that we don't | |
952 | * zero extend as we are filling a partial chunk of the vector register. | |
953 | * These functions don't support 128 bit loads/stores, which would be | |
954 | * normal load/store operations. | |
a08582f4 PM |
955 | * |
956 | * The _i32 versions are useful when operating on 32 bit quantities | |
957 | * (eg for floating point single or using Neon helper functions). | |
72430bf5 AB |
958 | */ |
959 | ||
960 | /* Get value of an element within a vector register */ | |
961 | static void read_vec_element(DisasContext *s, TCGv_i64 tcg_dest, int srcidx, | |
14776ab5 | 962 | int element, MemOp memop) |
72430bf5 | 963 | { |
90e49638 | 964 | int vect_off = vec_reg_offset(s, srcidx, element, memop & MO_SIZE); |
72430bf5 AB |
965 | switch (memop) { |
966 | case MO_8: | |
967 | tcg_gen_ld8u_i64(tcg_dest, cpu_env, vect_off); | |
968 | break; | |
969 | case MO_16: | |
970 | tcg_gen_ld16u_i64(tcg_dest, cpu_env, vect_off); | |
971 | break; | |
972 | case MO_32: | |
973 | tcg_gen_ld32u_i64(tcg_dest, cpu_env, vect_off); | |
974 | break; | |
975 | case MO_8|MO_SIGN: | |
976 | tcg_gen_ld8s_i64(tcg_dest, cpu_env, vect_off); | |
977 | break; | |
978 | case MO_16|MO_SIGN: | |
979 | tcg_gen_ld16s_i64(tcg_dest, cpu_env, vect_off); | |
980 | break; | |
981 | case MO_32|MO_SIGN: | |
982 | tcg_gen_ld32s_i64(tcg_dest, cpu_env, vect_off); | |
983 | break; | |
984 | case MO_64: | |
985 | case MO_64|MO_SIGN: | |
986 | tcg_gen_ld_i64(tcg_dest, cpu_env, vect_off); | |
987 | break; | |
988 | default: | |
989 | g_assert_not_reached(); | |
990 | } | |
991 | } | |
992 | ||
a08582f4 | 993 | static void read_vec_element_i32(DisasContext *s, TCGv_i32 tcg_dest, int srcidx, |
14776ab5 | 994 | int element, MemOp memop) |
a08582f4 | 995 | { |
90e49638 | 996 | int vect_off = vec_reg_offset(s, srcidx, element, memop & MO_SIZE); |
a08582f4 PM |
997 | switch (memop) { |
998 | case MO_8: | |
999 | tcg_gen_ld8u_i32(tcg_dest, cpu_env, vect_off); | |
1000 | break; | |
1001 | case MO_16: | |
1002 | tcg_gen_ld16u_i32(tcg_dest, cpu_env, vect_off); | |
1003 | break; | |
1004 | case MO_8|MO_SIGN: | |
1005 | tcg_gen_ld8s_i32(tcg_dest, cpu_env, vect_off); | |
1006 | break; | |
1007 | case MO_16|MO_SIGN: | |
1008 | tcg_gen_ld16s_i32(tcg_dest, cpu_env, vect_off); | |
1009 | break; | |
1010 | case MO_32: | |
1011 | case MO_32|MO_SIGN: | |
1012 | tcg_gen_ld_i32(tcg_dest, cpu_env, vect_off); | |
1013 | break; | |
1014 | default: | |
1015 | g_assert_not_reached(); | |
1016 | } | |
1017 | } | |
1018 | ||
72430bf5 AB |
1019 | /* Set value of an element within a vector register */ |
1020 | static void write_vec_element(DisasContext *s, TCGv_i64 tcg_src, int destidx, | |
14776ab5 | 1021 | int element, MemOp memop) |
72430bf5 | 1022 | { |
90e49638 | 1023 | int vect_off = vec_reg_offset(s, destidx, element, memop & MO_SIZE); |
72430bf5 AB |
1024 | switch (memop) { |
1025 | case MO_8: | |
1026 | tcg_gen_st8_i64(tcg_src, cpu_env, vect_off); | |
1027 | break; | |
1028 | case MO_16: | |
1029 | tcg_gen_st16_i64(tcg_src, cpu_env, vect_off); | |
1030 | break; | |
1031 | case MO_32: | |
1032 | tcg_gen_st32_i64(tcg_src, cpu_env, vect_off); | |
1033 | break; | |
1034 | case MO_64: | |
1035 | tcg_gen_st_i64(tcg_src, cpu_env, vect_off); | |
1036 | break; | |
1037 | default: | |
1038 | g_assert_not_reached(); | |
1039 | } | |
1040 | } | |
1041 | ||
1f8a73af | 1042 | static void write_vec_element_i32(DisasContext *s, TCGv_i32 tcg_src, |
14776ab5 | 1043 | int destidx, int element, MemOp memop) |
1f8a73af | 1044 | { |
90e49638 | 1045 | int vect_off = vec_reg_offset(s, destidx, element, memop & MO_SIZE); |
1f8a73af PM |
1046 | switch (memop) { |
1047 | case MO_8: | |
1048 | tcg_gen_st8_i32(tcg_src, cpu_env, vect_off); | |
1049 | break; | |
1050 | case MO_16: | |
1051 | tcg_gen_st16_i32(tcg_src, cpu_env, vect_off); | |
1052 | break; | |
1053 | case MO_32: | |
1054 | tcg_gen_st_i32(tcg_src, cpu_env, vect_off); | |
1055 | break; | |
1056 | default: | |
1057 | g_assert_not_reached(); | |
1058 | } | |
1059 | } | |
1060 | ||
72430bf5 AB |
1061 | /* Store from vector register to memory */ |
1062 | static void do_vec_st(DisasContext *s, int srcidx, int element, | |
14776ab5 | 1063 | TCGv_i64 tcg_addr, int size, MemOp endian) |
72430bf5 | 1064 | { |
72430bf5 AB |
1065 | TCGv_i64 tcg_tmp = tcg_temp_new_i64(); |
1066 | ||
1067 | read_vec_element(s, tcg_tmp, srcidx, element, size); | |
87f9a7f0 | 1068 | tcg_gen_qemu_st_i64(tcg_tmp, tcg_addr, get_mem_index(s), endian | size); |
72430bf5 AB |
1069 | |
1070 | tcg_temp_free_i64(tcg_tmp); | |
1071 | } | |
1072 | ||
1073 | /* Load from memory to vector register */ | |
1074 | static void do_vec_ld(DisasContext *s, int destidx, int element, | |
14776ab5 | 1075 | TCGv_i64 tcg_addr, int size, MemOp endian) |
72430bf5 | 1076 | { |
72430bf5 AB |
1077 | TCGv_i64 tcg_tmp = tcg_temp_new_i64(); |
1078 | ||
87f9a7f0 | 1079 | tcg_gen_qemu_ld_i64(tcg_tmp, tcg_addr, get_mem_index(s), endian | size); |
72430bf5 AB |
1080 | write_vec_element(s, tcg_tmp, destidx, element, size); |
1081 | ||
1082 | tcg_temp_free_i64(tcg_tmp); | |
1083 | } | |
1084 | ||
8c6afa6a PM |
1085 | /* Check that FP/Neon access is enabled. If it is, return |
1086 | * true. If not, emit code to generate an appropriate exception, | |
1087 | * and return false; the caller should not emit any code for | |
1088 | * the instruction. Note that this check must happen after all | |
1089 | * unallocated-encoding checks (otherwise the syndrome information | |
1090 | * for the resulting exception will be incorrect). | |
1091 | */ | |
1092 | static inline bool fp_access_check(DisasContext *s) | |
1093 | { | |
90e49638 PM |
1094 | assert(!s->fp_access_checked); |
1095 | s->fp_access_checked = true; | |
1096 | ||
9dbbc748 | 1097 | if (!s->fp_excp_el) { |
8c6afa6a PM |
1098 | return true; |
1099 | } | |
1100 | ||
a767fac8 RH |
1101 | gen_exception_insn(s, s->pc_curr, EXCP_UDEF, |
1102 | syn_fp_access_trap(1, 0xe, false), s->fp_excp_el); | |
8c6afa6a PM |
1103 | return false; |
1104 | } | |
1105 | ||
490aa7f1 RH |
1106 | /* Check that SVE access is enabled. If it is, return true. |
1107 | * If not, emit code to generate an appropriate exception and return false. | |
1108 | */ | |
8c71baed | 1109 | bool sve_access_check(DisasContext *s) |
490aa7f1 RH |
1110 | { |
1111 | if (s->sve_excp_el) { | |
a767fac8 | 1112 | gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_sve_access_trap(), |
490aa7f1 RH |
1113 | s->sve_excp_el); |
1114 | return false; | |
1115 | } | |
8c71baed | 1116 | return fp_access_check(s); |
490aa7f1 RH |
1117 | } |
1118 | ||
229b7a05 AB |
1119 | /* |
1120 | * This utility function is for doing register extension with an | |
1121 | * optional shift. You will likely want to pass a temporary for the | |
1122 | * destination register. See DecodeRegExtend() in the ARM ARM. | |
1123 | */ | |
1124 | static void ext_and_shift_reg(TCGv_i64 tcg_out, TCGv_i64 tcg_in, | |
1125 | int option, unsigned int shift) | |
1126 | { | |
1127 | int extsize = extract32(option, 0, 2); | |
1128 | bool is_signed = extract32(option, 2, 1); | |
1129 | ||
1130 | if (is_signed) { | |
1131 | switch (extsize) { | |
1132 | case 0: | |
1133 | tcg_gen_ext8s_i64(tcg_out, tcg_in); | |
1134 | break; | |
1135 | case 1: | |
1136 | tcg_gen_ext16s_i64(tcg_out, tcg_in); | |
1137 | break; | |
1138 | case 2: | |
1139 | tcg_gen_ext32s_i64(tcg_out, tcg_in); | |
1140 | break; | |
1141 | case 3: | |
1142 | tcg_gen_mov_i64(tcg_out, tcg_in); | |
1143 | break; | |
1144 | } | |
1145 | } else { | |
1146 | switch (extsize) { | |
1147 | case 0: | |
1148 | tcg_gen_ext8u_i64(tcg_out, tcg_in); | |
1149 | break; | |
1150 | case 1: | |
1151 | tcg_gen_ext16u_i64(tcg_out, tcg_in); | |
1152 | break; | |
1153 | case 2: | |
1154 | tcg_gen_ext32u_i64(tcg_out, tcg_in); | |
1155 | break; | |
1156 | case 3: | |
1157 | tcg_gen_mov_i64(tcg_out, tcg_in); | |
1158 | break; | |
1159 | } | |
1160 | } | |
1161 | ||
1162 | if (shift) { | |
1163 | tcg_gen_shli_i64(tcg_out, tcg_out, shift); | |
1164 | } | |
1165 | } | |
1166 | ||
4a08d475 PM |
1167 | static inline void gen_check_sp_alignment(DisasContext *s) |
1168 | { | |
1169 | /* The AArch64 architecture mandates that (if enabled via PSTATE | |
1170 | * or SCTLR bits) there is a check that SP is 16-aligned on every | |
1171 | * SP-relative load or store (with an exception generated if it is not). | |
1172 | * In line with general QEMU practice regarding misaligned accesses, | |
1173 | * we omit these checks for the sake of guest program performance. | |
1174 | * This function is provided as a hook so we can more easily add these | |
1175 | * checks in future (possibly as a "favour catching guest program bugs | |
1176 | * over speed" user selectable option). | |
1177 | */ | |
1178 | } | |
1179 | ||
384b26fb AB |
1180 | /* |
1181 | * This provides a simple table based table lookup decoder. It is | |
1182 | * intended to be used when the relevant bits for decode are too | |
1183 | * awkwardly placed and switch/if based logic would be confusing and | |
1184 | * deeply nested. Since it's a linear search through the table, tables | |
1185 | * should be kept small. | |
1186 | * | |
1187 | * It returns the first handler where insn & mask == pattern, or | |
1188 | * NULL if there is no match. | |
1189 | * The table is terminated by an empty mask (i.e. 0) | |
1190 | */ | |
1191 | static inline AArch64DecodeFn *lookup_disas_fn(const AArch64DecodeTable *table, | |
1192 | uint32_t insn) | |
1193 | { | |
1194 | const AArch64DecodeTable *tptr = table; | |
1195 | ||
1196 | while (tptr->mask) { | |
1197 | if ((insn & tptr->mask) == tptr->pattern) { | |
1198 | return tptr->disas_fn; | |
1199 | } | |
1200 | tptr++; | |
1201 | } | |
1202 | return NULL; | |
1203 | } | |
1204 | ||
ad7ee8a2 | 1205 | /* |
4ce31af4 PM |
1206 | * The instruction disassembly implemented here matches |
1207 | * the instruction encoding classifications in chapter C4 | |
1208 | * of the ARM Architecture Reference Manual (DDI0487B_a); | |
1209 | * classification names and decode diagrams here should generally | |
1210 | * match up with those in the manual. | |
ad7ee8a2 CF |
1211 | */ |
1212 | ||
4ce31af4 | 1213 | /* Unconditional branch (immediate) |
11e169de AG |
1214 | * 31 30 26 25 0 |
1215 | * +----+-----------+-------------------------------------+ | |
1216 | * | op | 0 0 1 0 1 | imm26 | | |
1217 | * +----+-----------+-------------------------------------+ | |
1218 | */ | |
ad7ee8a2 CF |
1219 | static void disas_uncond_b_imm(DisasContext *s, uint32_t insn) |
1220 | { | |
43722a6d | 1221 | uint64_t addr = s->pc_curr + sextract32(insn, 0, 26) * 4; |
11e169de | 1222 | |
1743d55c | 1223 | if (insn & (1U << 31)) { |
4ce31af4 | 1224 | /* BL Branch with link */ |
a0415916 | 1225 | tcg_gen_movi_i64(cpu_reg(s, 30), s->base.pc_next); |
11e169de AG |
1226 | } |
1227 | ||
4ce31af4 | 1228 | /* B Branch / BL Branch with link */ |
35862270 | 1229 | reset_btype(s); |
11e169de | 1230 | gen_goto_tb(s, 0, addr); |
ad7ee8a2 CF |
1231 | } |
1232 | ||
4ce31af4 | 1233 | /* Compare and branch (immediate) |
60e53388 AG |
1234 | * 31 30 25 24 23 5 4 0 |
1235 | * +----+-------------+----+---------------------+--------+ | |
1236 | * | sf | 0 1 1 0 1 0 | op | imm19 | Rt | | |
1237 | * +----+-------------+----+---------------------+--------+ | |
1238 | */ | |
ad7ee8a2 CF |
1239 | static void disas_comp_b_imm(DisasContext *s, uint32_t insn) |
1240 | { | |
60e53388 AG |
1241 | unsigned int sf, op, rt; |
1242 | uint64_t addr; | |
42a268c2 | 1243 | TCGLabel *label_match; |
60e53388 AG |
1244 | TCGv_i64 tcg_cmp; |
1245 | ||
1246 | sf = extract32(insn, 31, 1); | |
1247 | op = extract32(insn, 24, 1); /* 0: CBZ; 1: CBNZ */ | |
1248 | rt = extract32(insn, 0, 5); | |
43722a6d | 1249 | addr = s->pc_curr + sextract32(insn, 5, 19) * 4; |
60e53388 AG |
1250 | |
1251 | tcg_cmp = read_cpu_reg(s, rt, sf); | |
1252 | label_match = gen_new_label(); | |
1253 | ||
35862270 | 1254 | reset_btype(s); |
60e53388 AG |
1255 | tcg_gen_brcondi_i64(op ? TCG_COND_NE : TCG_COND_EQ, |
1256 | tcg_cmp, 0, label_match); | |
1257 | ||
a0415916 | 1258 | gen_goto_tb(s, 0, s->base.pc_next); |
60e53388 AG |
1259 | gen_set_label(label_match); |
1260 | gen_goto_tb(s, 1, addr); | |
ad7ee8a2 CF |
1261 | } |
1262 | ||
4ce31af4 | 1263 | /* Test and branch (immediate) |
db0f7958 AG |
1264 | * 31 30 25 24 23 19 18 5 4 0 |
1265 | * +----+-------------+----+-------+-------------+------+ | |
1266 | * | b5 | 0 1 1 0 1 1 | op | b40 | imm14 | Rt | | |
1267 | * +----+-------------+----+-------+-------------+------+ | |
1268 | */ | |
ad7ee8a2 CF |
1269 | static void disas_test_b_imm(DisasContext *s, uint32_t insn) |
1270 | { | |
db0f7958 AG |
1271 | unsigned int bit_pos, op, rt; |
1272 | uint64_t addr; | |
42a268c2 | 1273 | TCGLabel *label_match; |
db0f7958 AG |
1274 | TCGv_i64 tcg_cmp; |
1275 | ||
1276 | bit_pos = (extract32(insn, 31, 1) << 5) | extract32(insn, 19, 5); | |
1277 | op = extract32(insn, 24, 1); /* 0: TBZ; 1: TBNZ */ | |
43722a6d | 1278 | addr = s->pc_curr + sextract32(insn, 5, 14) * 4; |
db0f7958 AG |
1279 | rt = extract32(insn, 0, 5); |
1280 | ||
1281 | tcg_cmp = tcg_temp_new_i64(); | |
1282 | tcg_gen_andi_i64(tcg_cmp, cpu_reg(s, rt), (1ULL << bit_pos)); | |
1283 | label_match = gen_new_label(); | |
35862270 RH |
1284 | |
1285 | reset_btype(s); | |
db0f7958 AG |
1286 | tcg_gen_brcondi_i64(op ? TCG_COND_NE : TCG_COND_EQ, |
1287 | tcg_cmp, 0, label_match); | |
1288 | tcg_temp_free_i64(tcg_cmp); | |
a0415916 | 1289 | gen_goto_tb(s, 0, s->base.pc_next); |
db0f7958 AG |
1290 | gen_set_label(label_match); |
1291 | gen_goto_tb(s, 1, addr); | |
ad7ee8a2 CF |
1292 | } |
1293 | ||
4ce31af4 | 1294 | /* Conditional branch (immediate) |
39fb730a AG |
1295 | * 31 25 24 23 5 4 3 0 |
1296 | * +---------------+----+---------------------+----+------+ | |
1297 | * | 0 1 0 1 0 1 0 | o1 | imm19 | o0 | cond | | |
1298 | * +---------------+----+---------------------+----+------+ | |
1299 | */ | |
ad7ee8a2 CF |
1300 | static void disas_cond_b_imm(DisasContext *s, uint32_t insn) |
1301 | { | |
39fb730a AG |
1302 | unsigned int cond; |
1303 | uint64_t addr; | |
1304 | ||
1305 | if ((insn & (1 << 4)) || (insn & (1 << 24))) { | |
1306 | unallocated_encoding(s); | |
1307 | return; | |
1308 | } | |
43722a6d | 1309 | addr = s->pc_curr + sextract32(insn, 5, 19) * 4; |
39fb730a AG |
1310 | cond = extract32(insn, 0, 4); |
1311 | ||
35862270 | 1312 | reset_btype(s); |
39fb730a AG |
1313 | if (cond < 0x0e) { |
1314 | /* genuinely conditional branches */ | |
42a268c2 | 1315 | TCGLabel *label_match = gen_new_label(); |
39fb730a | 1316 | arm_gen_test_cc(cond, label_match); |
a0415916 | 1317 | gen_goto_tb(s, 0, s->base.pc_next); |
39fb730a AG |
1318 | gen_set_label(label_match); |
1319 | gen_goto_tb(s, 1, addr); | |
1320 | } else { | |
1321 | /* 0xe and 0xf are both "always" conditions */ | |
1322 | gen_goto_tb(s, 0, addr); | |
1323 | } | |
ad7ee8a2 CF |
1324 | } |
1325 | ||
4ce31af4 | 1326 | /* HINT instruction group, including various allocated HINTs */ |
87462e0f CF |
1327 | static void handle_hint(DisasContext *s, uint32_t insn, |
1328 | unsigned int op1, unsigned int op2, unsigned int crm) | |
1329 | { | |
1330 | unsigned int selector = crm << 3 | op2; | |
1331 | ||
1332 | if (op1 != 3) { | |
1333 | unallocated_encoding(s); | |
1334 | return; | |
1335 | } | |
1336 | ||
1337 | switch (selector) { | |
7c94c834 RH |
1338 | case 0b00000: /* NOP */ |
1339 | break; | |
1340 | case 0b00011: /* WFI */ | |
dcba3a8d | 1341 | s->base.is_jmp = DISAS_WFI; |
7c94c834 RH |
1342 | break; |
1343 | case 0b00001: /* YIELD */ | |
2399d4e7 EC |
1344 | /* When running in MTTCG we don't generate jumps to the yield and |
1345 | * WFE helpers as it won't affect the scheduling of other vCPUs. | |
1346 | * If we wanted to more completely model WFE/SEV so we don't busy | |
1347 | * spin unnecessarily we would need to do something more involved. | |
1348 | */ | |
2399d4e7 | 1349 | if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) { |
dcba3a8d | 1350 | s->base.is_jmp = DISAS_YIELD; |
c22edfeb | 1351 | } |
7c94c834 RH |
1352 | break; |
1353 | case 0b00010: /* WFE */ | |
2399d4e7 | 1354 | if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) { |
dcba3a8d | 1355 | s->base.is_jmp = DISAS_WFE; |
c22edfeb | 1356 | } |
7c94c834 RH |
1357 | break; |
1358 | case 0b00100: /* SEV */ | |
1359 | case 0b00101: /* SEVL */ | |
87462e0f | 1360 | /* we treat all as NOP at least for now */ |
7c94c834 RH |
1361 | break; |
1362 | case 0b00111: /* XPACLRI */ | |
1363 | if (s->pauth_active) { | |
1364 | gen_helper_xpaci(cpu_X[30], cpu_env, cpu_X[30]); | |
1365 | } | |
1366 | break; | |
1367 | case 0b01000: /* PACIA1716 */ | |
1368 | if (s->pauth_active) { | |
1369 | gen_helper_pacia(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]); | |
1370 | } | |
1371 | break; | |
1372 | case 0b01010: /* PACIB1716 */ | |
1373 | if (s->pauth_active) { | |
1374 | gen_helper_pacib(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]); | |
1375 | } | |
1376 | break; | |
1377 | case 0b01100: /* AUTIA1716 */ | |
1378 | if (s->pauth_active) { | |
1379 | gen_helper_autia(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]); | |
1380 | } | |
1381 | break; | |
1382 | case 0b01110: /* AUTIB1716 */ | |
1383 | if (s->pauth_active) { | |
1384 | gen_helper_autib(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]); | |
1385 | } | |
1386 | break; | |
1387 | case 0b11000: /* PACIAZ */ | |
1388 | if (s->pauth_active) { | |
1389 | gen_helper_pacia(cpu_X[30], cpu_env, cpu_X[30], | |
1390 | new_tmp_a64_zero(s)); | |
1391 | } | |
1392 | break; | |
1393 | case 0b11001: /* PACIASP */ | |
1394 | if (s->pauth_active) { | |
1395 | gen_helper_pacia(cpu_X[30], cpu_env, cpu_X[30], cpu_X[31]); | |
1396 | } | |
1397 | break; | |
1398 | case 0b11010: /* PACIBZ */ | |
1399 | if (s->pauth_active) { | |
1400 | gen_helper_pacib(cpu_X[30], cpu_env, cpu_X[30], | |
1401 | new_tmp_a64_zero(s)); | |
1402 | } | |
1403 | break; | |
1404 | case 0b11011: /* PACIBSP */ | |
1405 | if (s->pauth_active) { | |
1406 | gen_helper_pacib(cpu_X[30], cpu_env, cpu_X[30], cpu_X[31]); | |
1407 | } | |
1408 | break; | |
1409 | case 0b11100: /* AUTIAZ */ | |
1410 | if (s->pauth_active) { | |
1411 | gen_helper_autia(cpu_X[30], cpu_env, cpu_X[30], | |
1412 | new_tmp_a64_zero(s)); | |
1413 | } | |
1414 | break; | |
1415 | case 0b11101: /* AUTIASP */ | |
1416 | if (s->pauth_active) { | |
1417 | gen_helper_autia(cpu_X[30], cpu_env, cpu_X[30], cpu_X[31]); | |
1418 | } | |
1419 | break; | |
1420 | case 0b11110: /* AUTIBZ */ | |
1421 | if (s->pauth_active) { | |
1422 | gen_helper_autib(cpu_X[30], cpu_env, cpu_X[30], | |
1423 | new_tmp_a64_zero(s)); | |
1424 | } | |
1425 | break; | |
1426 | case 0b11111: /* AUTIBSP */ | |
1427 | if (s->pauth_active) { | |
1428 | gen_helper_autib(cpu_X[30], cpu_env, cpu_X[30], cpu_X[31]); | |
1429 | } | |
1430 | break; | |
87462e0f CF |
1431 | default: |
1432 | /* default specified as NOP equivalent */ | |
7c94c834 | 1433 | break; |
87462e0f CF |
1434 | } |
1435 | } | |
1436 | ||
fa2ef212 MM |
1437 | static void gen_clrex(DisasContext *s, uint32_t insn) |
1438 | { | |
1439 | tcg_gen_movi_i64(cpu_exclusive_addr, -1); | |
1440 | } | |
1441 | ||
87462e0f CF |
1442 | /* CLREX, DSB, DMB, ISB */ |
1443 | static void handle_sync(DisasContext *s, uint32_t insn, | |
1444 | unsigned int op1, unsigned int op2, unsigned int crm) | |
1445 | { | |
ce1bd93f PK |
1446 | TCGBar bar; |
1447 | ||
87462e0f CF |
1448 | if (op1 != 3) { |
1449 | unallocated_encoding(s); | |
1450 | return; | |
1451 | } | |
1452 | ||
1453 | switch (op2) { | |
1454 | case 2: /* CLREX */ | |
fa2ef212 | 1455 | gen_clrex(s, insn); |
87462e0f CF |
1456 | return; |
1457 | case 4: /* DSB */ | |
1458 | case 5: /* DMB */ | |
ce1bd93f PK |
1459 | switch (crm & 3) { |
1460 | case 1: /* MBReqTypes_Reads */ | |
1461 | bar = TCG_BAR_SC | TCG_MO_LD_LD | TCG_MO_LD_ST; | |
1462 | break; | |
1463 | case 2: /* MBReqTypes_Writes */ | |
1464 | bar = TCG_BAR_SC | TCG_MO_ST_ST; | |
1465 | break; | |
1466 | default: /* MBReqTypes_All */ | |
1467 | bar = TCG_BAR_SC | TCG_MO_ALL; | |
1468 | break; | |
1469 | } | |
1470 | tcg_gen_mb(bar); | |
87462e0f | 1471 | return; |
6df99dec SS |
1472 | case 6: /* ISB */ |
1473 | /* We need to break the TB after this insn to execute | |
1474 | * a self-modified code correctly and also to take | |
1475 | * any pending interrupts immediately. | |
1476 | */ | |
35862270 | 1477 | reset_btype(s); |
a0415916 | 1478 | gen_goto_tb(s, 0, s->base.pc_next); |
6df99dec | 1479 | return; |
9888bd1e RH |
1480 | |
1481 | case 7: /* SB */ | |
1482 | if (crm != 0 || !dc_isar_feature(aa64_sb, s)) { | |
1483 | goto do_unallocated; | |
1484 | } | |
1485 | /* | |
1486 | * TODO: There is no speculation barrier opcode for TCG; | |
1487 | * MB and end the TB instead. | |
1488 | */ | |
1489 | tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); | |
a0415916 | 1490 | gen_goto_tb(s, 0, s->base.pc_next); |
9888bd1e RH |
1491 | return; |
1492 | ||
87462e0f | 1493 | default: |
9888bd1e | 1494 | do_unallocated: |
87462e0f CF |
1495 | unallocated_encoding(s); |
1496 | return; | |
1497 | } | |
1498 | } | |
1499 | ||
5ef84f11 RH |
1500 | static void gen_xaflag(void) |
1501 | { | |
1502 | TCGv_i32 z = tcg_temp_new_i32(); | |
1503 | ||
1504 | tcg_gen_setcondi_i32(TCG_COND_EQ, z, cpu_ZF, 0); | |
1505 | ||
1506 | /* | |
1507 | * (!C & !Z) << 31 | |
1508 | * (!(C | Z)) << 31 | |
1509 | * ~((C | Z) << 31) | |
1510 | * ~-(C | Z) | |
1511 | * (C | Z) - 1 | |
1512 | */ | |
1513 | tcg_gen_or_i32(cpu_NF, cpu_CF, z); | |
1514 | tcg_gen_subi_i32(cpu_NF, cpu_NF, 1); | |
1515 | ||
1516 | /* !(Z & C) */ | |
1517 | tcg_gen_and_i32(cpu_ZF, z, cpu_CF); | |
1518 | tcg_gen_xori_i32(cpu_ZF, cpu_ZF, 1); | |
1519 | ||
1520 | /* (!C & Z) << 31 -> -(Z & ~C) */ | |
1521 | tcg_gen_andc_i32(cpu_VF, z, cpu_CF); | |
1522 | tcg_gen_neg_i32(cpu_VF, cpu_VF); | |
1523 | ||
1524 | /* C | Z */ | |
1525 | tcg_gen_or_i32(cpu_CF, cpu_CF, z); | |
1526 | ||
1527 | tcg_temp_free_i32(z); | |
1528 | } | |
1529 | ||
1530 | static void gen_axflag(void) | |
1531 | { | |
1532 | tcg_gen_sari_i32(cpu_VF, cpu_VF, 31); /* V ? -1 : 0 */ | |
1533 | tcg_gen_andc_i32(cpu_CF, cpu_CF, cpu_VF); /* C & !V */ | |
1534 | ||
1535 | /* !(Z | V) -> !(!ZF | V) -> ZF & !V -> ZF & ~VF */ | |
1536 | tcg_gen_andc_i32(cpu_ZF, cpu_ZF, cpu_VF); | |
1537 | ||
1538 | tcg_gen_movi_i32(cpu_NF, 0); | |
1539 | tcg_gen_movi_i32(cpu_VF, 0); | |
1540 | } | |
1541 | ||
4ce31af4 | 1542 | /* MSR (immediate) - move immediate to processor state field */ |
87462e0f CF |
1543 | static void handle_msr_i(DisasContext *s, uint32_t insn, |
1544 | unsigned int op1, unsigned int op2, unsigned int crm) | |
1545 | { | |
ff730e96 | 1546 | TCGv_i32 t1; |
9cfa0b4e | 1547 | int op = op1 << 3 | op2; |
ff730e96 RH |
1548 | |
1549 | /* End the TB by default, chaining is ok. */ | |
1550 | s->base.is_jmp = DISAS_TOO_MANY; | |
1551 | ||
9cfa0b4e | 1552 | switch (op) { |
b89d9c98 RH |
1553 | case 0x00: /* CFINV */ |
1554 | if (crm != 0 || !dc_isar_feature(aa64_condm_4, s)) { | |
1555 | goto do_unallocated; | |
1556 | } | |
1557 | tcg_gen_xori_i32(cpu_CF, cpu_CF, 1); | |
1558 | s->base.is_jmp = DISAS_NEXT; | |
1559 | break; | |
1560 | ||
5ef84f11 RH |
1561 | case 0x01: /* XAFlag */ |
1562 | if (crm != 0 || !dc_isar_feature(aa64_condm_5, s)) { | |
1563 | goto do_unallocated; | |
1564 | } | |
1565 | gen_xaflag(); | |
1566 | s->base.is_jmp = DISAS_NEXT; | |
1567 | break; | |
1568 | ||
1569 | case 0x02: /* AXFlag */ | |
1570 | if (crm != 0 || !dc_isar_feature(aa64_condm_5, s)) { | |
1571 | goto do_unallocated; | |
1572 | } | |
1573 | gen_axflag(); | |
1574 | s->base.is_jmp = DISAS_NEXT; | |
1575 | break; | |
1576 | ||
9eeb7a1c RH |
1577 | case 0x03: /* UAO */ |
1578 | if (!dc_isar_feature(aa64_uao, s) || s->current_el == 0) { | |
1579 | goto do_unallocated; | |
1580 | } | |
1581 | if (crm & 1) { | |
1582 | set_pstate_bits(PSTATE_UAO); | |
1583 | } else { | |
1584 | clear_pstate_bits(PSTATE_UAO); | |
1585 | } | |
1586 | t1 = tcg_const_i32(s->current_el); | |
1587 | gen_helper_rebuild_hflags_a64(cpu_env, t1); | |
1588 | tcg_temp_free_i32(t1); | |
1589 | break; | |
1590 | ||
220f508f RH |
1591 | case 0x04: /* PAN */ |
1592 | if (!dc_isar_feature(aa64_pan, s) || s->current_el == 0) { | |
1593 | goto do_unallocated; | |
1594 | } | |
1595 | if (crm & 1) { | |
1596 | set_pstate_bits(PSTATE_PAN); | |
1597 | } else { | |
1598 | clear_pstate_bits(PSTATE_PAN); | |
1599 | } | |
1600 | t1 = tcg_const_i32(s->current_el); | |
1601 | gen_helper_rebuild_hflags_a64(cpu_env, t1); | |
1602 | tcg_temp_free_i32(t1); | |
1603 | break; | |
1604 | ||
9cfa0b4e | 1605 | case 0x05: /* SPSel */ |
dcbff19b | 1606 | if (s->current_el == 0) { |
ff730e96 | 1607 | goto do_unallocated; |
9cfa0b4e | 1608 | } |
ff730e96 RH |
1609 | t1 = tcg_const_i32(crm & PSTATE_SP); |
1610 | gen_helper_msr_i_spsel(cpu_env, t1); | |
1611 | tcg_temp_free_i32(t1); | |
1612 | break; | |
1613 | ||
9cfa0b4e | 1614 | case 0x1e: /* DAIFSet */ |
ff730e96 RH |
1615 | t1 = tcg_const_i32(crm); |
1616 | gen_helper_msr_i_daifset(cpu_env, t1); | |
1617 | tcg_temp_free_i32(t1); | |
1618 | break; | |
1619 | ||
9cfa0b4e | 1620 | case 0x1f: /* DAIFClear */ |
ff730e96 RH |
1621 | t1 = tcg_const_i32(crm); |
1622 | gen_helper_msr_i_daifclear(cpu_env, t1); | |
1623 | tcg_temp_free_i32(t1); | |
8da54b25 | 1624 | /* For DAIFClear, exit the cpu loop to re-evaluate pending IRQs. */ |
14407ec2 | 1625 | s->base.is_jmp = DISAS_UPDATE_EXIT; |
9cfa0b4e | 1626 | break; |
ff730e96 | 1627 | |
4b779ceb RH |
1628 | case 0x1c: /* TCO */ |
1629 | if (dc_isar_feature(aa64_mte, s)) { | |
1630 | /* Full MTE is enabled -- set the TCO bit as directed. */ | |
1631 | if (crm & 1) { | |
1632 | set_pstate_bits(PSTATE_TCO); | |
1633 | } else { | |
1634 | clear_pstate_bits(PSTATE_TCO); | |
1635 | } | |
1636 | t1 = tcg_const_i32(s->current_el); | |
1637 | gen_helper_rebuild_hflags_a64(cpu_env, t1); | |
1638 | tcg_temp_free_i32(t1); | |
1639 | /* Many factors, including TCO, go into MTE_ACTIVE. */ | |
1640 | s->base.is_jmp = DISAS_UPDATE_NOCHAIN; | |
1641 | } else if (dc_isar_feature(aa64_mte_insn_reg, s)) { | |
1642 | /* Only "instructions accessible at EL0" -- PSTATE.TCO is WI. */ | |
1643 | s->base.is_jmp = DISAS_NEXT; | |
1644 | } else { | |
1645 | goto do_unallocated; | |
1646 | } | |
1647 | break; | |
1648 | ||
9cfa0b4e | 1649 | default: |
ff730e96 | 1650 | do_unallocated: |
9cfa0b4e PM |
1651 | unallocated_encoding(s); |
1652 | return; | |
1653 | } | |
87462e0f CF |
1654 | } |
1655 | ||
b0d2b7d0 PM |
1656 | static void gen_get_nzcv(TCGv_i64 tcg_rt) |
1657 | { | |
1658 | TCGv_i32 tmp = tcg_temp_new_i32(); | |
1659 | TCGv_i32 nzcv = tcg_temp_new_i32(); | |
1660 | ||
1661 | /* build bit 31, N */ | |
1743d55c | 1662 | tcg_gen_andi_i32(nzcv, cpu_NF, (1U << 31)); |
b0d2b7d0 PM |
1663 | /* build bit 30, Z */ |
1664 | tcg_gen_setcondi_i32(TCG_COND_EQ, tmp, cpu_ZF, 0); | |
1665 | tcg_gen_deposit_i32(nzcv, nzcv, tmp, 30, 1); | |
1666 | /* build bit 29, C */ | |
1667 | tcg_gen_deposit_i32(nzcv, nzcv, cpu_CF, 29, 1); | |
1668 | /* build bit 28, V */ | |
1669 | tcg_gen_shri_i32(tmp, cpu_VF, 31); | |
1670 | tcg_gen_deposit_i32(nzcv, nzcv, tmp, 28, 1); | |
1671 | /* generate result */ | |
1672 | tcg_gen_extu_i32_i64(tcg_rt, nzcv); | |
1673 | ||
1674 | tcg_temp_free_i32(nzcv); | |
1675 | tcg_temp_free_i32(tmp); | |
1676 | } | |
1677 | ||
1678 | static void gen_set_nzcv(TCGv_i64 tcg_rt) | |
b0d2b7d0 PM |
1679 | { |
1680 | TCGv_i32 nzcv = tcg_temp_new_i32(); | |
1681 | ||
1682 | /* take NZCV from R[t] */ | |
ecc7b3aa | 1683 | tcg_gen_extrl_i64_i32(nzcv, tcg_rt); |
b0d2b7d0 PM |
1684 | |
1685 | /* bit 31, N */ | |
1743d55c | 1686 | tcg_gen_andi_i32(cpu_NF, nzcv, (1U << 31)); |
b0d2b7d0 PM |
1687 | /* bit 30, Z */ |
1688 | tcg_gen_andi_i32(cpu_ZF, nzcv, (1 << 30)); | |
1689 | tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_ZF, cpu_ZF, 0); | |
1690 | /* bit 29, C */ | |
1691 | tcg_gen_andi_i32(cpu_CF, nzcv, (1 << 29)); | |
1692 | tcg_gen_shri_i32(cpu_CF, cpu_CF, 29); | |
1693 | /* bit 28, V */ | |
1694 | tcg_gen_andi_i32(cpu_VF, nzcv, (1 << 28)); | |
1695 | tcg_gen_shli_i32(cpu_VF, cpu_VF, 3); | |
1696 | tcg_temp_free_i32(nzcv); | |
1697 | } | |
1698 | ||
4ce31af4 PM |
1699 | /* MRS - move from system register |
1700 | * MSR (register) - move to system register | |
1701 | * SYS | |
1702 | * SYSL | |
fea50522 PM |
1703 | * These are all essentially the same insn in 'read' and 'write' |
1704 | * versions, with varying op0 fields. | |
1705 | */ | |
1706 | static void handle_sys(DisasContext *s, uint32_t insn, bool isread, | |
1707 | unsigned int op0, unsigned int op1, unsigned int op2, | |
87462e0f CF |
1708 | unsigned int crn, unsigned int crm, unsigned int rt) |
1709 | { | |
fea50522 PM |
1710 | const ARMCPRegInfo *ri; |
1711 | TCGv_i64 tcg_rt; | |
87462e0f | 1712 | |
fea50522 PM |
1713 | ri = get_arm_cp_reginfo(s->cp_regs, |
1714 | ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, | |
1715 | crn, crm, op0, op1, op2)); | |
87462e0f | 1716 | |
fea50522 | 1717 | if (!ri) { |
626187d8 PM |
1718 | /* Unknown register; this might be a guest error or a QEMU |
1719 | * unimplemented feature. | |
1720 | */ | |
1721 | qemu_log_mask(LOG_UNIMP, "%s access to unsupported AArch64 " | |
1722 | "system register op0:%d op1:%d crn:%d crm:%d op2:%d\n", | |
1723 | isread ? "read" : "write", op0, op1, crn, crm, op2); | |
fea50522 PM |
1724 | unallocated_encoding(s); |
1725 | return; | |
1726 | } | |
1727 | ||
1728 | /* Check access permissions */ | |
dcbff19b | 1729 | if (!cp_access_ok(s->current_el, ri, isread)) { |
fea50522 PM |
1730 | unallocated_encoding(s); |
1731 | return; | |
1732 | } | |
1733 | ||
f59df3f2 PM |
1734 | if (ri->accessfn) { |
1735 | /* Emit code to perform further access permissions checks at | |
1736 | * runtime; this may result in an exception. | |
1737 | */ | |
1738 | TCGv_ptr tmpptr; | |
3f208fd7 | 1739 | TCGv_i32 tcg_syn, tcg_isread; |
8bcbf37c PM |
1740 | uint32_t syndrome; |
1741 | ||
43722a6d | 1742 | gen_a64_set_pc_im(s->pc_curr); |
f59df3f2 | 1743 | tmpptr = tcg_const_ptr(ri); |
8bcbf37c PM |
1744 | syndrome = syn_aa64_sysregtrap(op0, op1, op2, crn, crm, rt, isread); |
1745 | tcg_syn = tcg_const_i32(syndrome); | |
3f208fd7 PM |
1746 | tcg_isread = tcg_const_i32(isread); |
1747 | gen_helper_access_check_cp_reg(cpu_env, tmpptr, tcg_syn, tcg_isread); | |
f59df3f2 | 1748 | tcg_temp_free_ptr(tmpptr); |
8bcbf37c | 1749 | tcg_temp_free_i32(tcg_syn); |
3f208fd7 | 1750 | tcg_temp_free_i32(tcg_isread); |
37ff584c PM |
1751 | } else if (ri->type & ARM_CP_RAISES_EXC) { |
1752 | /* | |
1753 | * The readfn or writefn might raise an exception; | |
1754 | * synchronize the CPU state in case it does. | |
1755 | */ | |
1756 | gen_a64_set_pc_im(s->pc_curr); | |
f59df3f2 PM |
1757 | } |
1758 | ||
fea50522 PM |
1759 | /* Handle special cases first */ |
1760 | switch (ri->type & ~(ARM_CP_FLAG_MASK & ~ARM_CP_SPECIAL)) { | |
1761 | case ARM_CP_NOP: | |
1762 | return; | |
b0d2b7d0 PM |
1763 | case ARM_CP_NZCV: |
1764 | tcg_rt = cpu_reg(s, rt); | |
1765 | if (isread) { | |
1766 | gen_get_nzcv(tcg_rt); | |
1767 | } else { | |
1768 | gen_set_nzcv(tcg_rt); | |
1769 | } | |
1770 | return; | |
0eef9d98 PM |
1771 | case ARM_CP_CURRENTEL: |
1772 | /* Reads as current EL value from pstate, which is | |
1773 | * guaranteed to be constant by the tb flags. | |
1774 | */ | |
1775 | tcg_rt = cpu_reg(s, rt); | |
dcbff19b | 1776 | tcg_gen_movi_i64(tcg_rt, s->current_el << 2); |
0eef9d98 | 1777 | return; |
aca3f40b PM |
1778 | case ARM_CP_DC_ZVA: |
1779 | /* Writes clear the aligned block of memory which rt points into. */ | |
597d61a3 | 1780 | tcg_rt = clean_data_tbi(s, cpu_reg(s, rt)); |
aca3f40b PM |
1781 | gen_helper_dc_zva(cpu_env, tcg_rt); |
1782 | return; | |
fea50522 PM |
1783 | default: |
1784 | break; | |
1785 | } | |
fe03d45f RH |
1786 | if ((ri->type & ARM_CP_FPU) && !fp_access_check(s)) { |
1787 | return; | |
11d7870b RH |
1788 | } else if ((ri->type & ARM_CP_SVE) && !sve_access_check(s)) { |
1789 | return; | |
fe03d45f | 1790 | } |
fea50522 | 1791 | |
c5a49c63 | 1792 | if ((tb_cflags(s->base.tb) & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) { |
fea50522 PM |
1793 | gen_io_start(); |
1794 | } | |
1795 | ||
1796 | tcg_rt = cpu_reg(s, rt); | |
1797 | ||
1798 | if (isread) { | |
1799 | if (ri->type & ARM_CP_CONST) { | |
1800 | tcg_gen_movi_i64(tcg_rt, ri->resetvalue); | |
1801 | } else if (ri->readfn) { | |
1802 | TCGv_ptr tmpptr; | |
fea50522 PM |
1803 | tmpptr = tcg_const_ptr(ri); |
1804 | gen_helper_get_cp_reg64(tcg_rt, cpu_env, tmpptr); | |
1805 | tcg_temp_free_ptr(tmpptr); | |
1806 | } else { | |
1807 | tcg_gen_ld_i64(tcg_rt, cpu_env, ri->fieldoffset); | |
1808 | } | |
1809 | } else { | |
1810 | if (ri->type & ARM_CP_CONST) { | |
1811 | /* If not forbidden by access permissions, treat as WI */ | |
1812 | return; | |
1813 | } else if (ri->writefn) { | |
1814 | TCGv_ptr tmpptr; | |
fea50522 PM |
1815 | tmpptr = tcg_const_ptr(ri); |
1816 | gen_helper_set_cp_reg64(cpu_env, tmpptr, tcg_rt); | |
1817 | tcg_temp_free_ptr(tmpptr); | |
1818 | } else { | |
1819 | tcg_gen_st_i64(tcg_rt, cpu_env, ri->fieldoffset); | |
1820 | } | |
1821 | } | |
1822 | ||
c5a49c63 | 1823 | if ((tb_cflags(s->base.tb) & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) { |
fea50522 | 1824 | /* I/O operations must end the TB here (whether read or write) */ |
14407ec2 | 1825 | s->base.is_jmp = DISAS_UPDATE_EXIT; |
69d66864 RH |
1826 | } |
1827 | if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) { | |
1828 | /* | |
1829 | * A write to any coprocessor regiser that ends a TB | |
1830 | * must rebuild the hflags for the next TB. | |
1831 | */ | |
1832 | TCGv_i32 tcg_el = tcg_const_i32(s->current_el); | |
1833 | gen_helper_rebuild_hflags_a64(cpu_env, tcg_el); | |
1834 | tcg_temp_free_i32(tcg_el); | |
1835 | /* | |
1836 | * We default to ending the TB on a coprocessor register write, | |
fea50522 PM |
1837 | * but allow this to be suppressed by the register definition |
1838 | * (usually only necessary to work around guest bugs). | |
1839 | */ | |
14407ec2 | 1840 | s->base.is_jmp = DISAS_UPDATE_EXIT; |
fea50522 | 1841 | } |
ad7ee8a2 CF |
1842 | } |
1843 | ||
4ce31af4 | 1844 | /* System |
87462e0f CF |
1845 | * 31 22 21 20 19 18 16 15 12 11 8 7 5 4 0 |
1846 | * +---------------------+---+-----+-----+-------+-------+-----+------+ | |
1847 | * | 1 1 0 1 0 1 0 1 0 0 | L | op0 | op1 | CRn | CRm | op2 | Rt | | |
1848 | * +---------------------+---+-----+-----+-------+-------+-----+------+ | |
1849 | */ | |
1850 | static void disas_system(DisasContext *s, uint32_t insn) | |
1851 | { | |
1852 | unsigned int l, op0, op1, crn, crm, op2, rt; | |
1853 | l = extract32(insn, 21, 1); | |
1854 | op0 = extract32(insn, 19, 2); | |
1855 | op1 = extract32(insn, 16, 3); | |
1856 | crn = extract32(insn, 12, 4); | |
1857 | crm = extract32(insn, 8, 4); | |
1858 | op2 = extract32(insn, 5, 3); | |
1859 | rt = extract32(insn, 0, 5); | |
1860 | ||
1861 | if (op0 == 0) { | |
1862 | if (l || rt != 31) { | |
1863 | unallocated_encoding(s); | |
1864 | return; | |
1865 | } | |
1866 | switch (crn) { | |
4ce31af4 | 1867 | case 2: /* HINT (including allocated hints like NOP, YIELD, etc) */ |
87462e0f CF |
1868 | handle_hint(s, insn, op1, op2, crm); |
1869 | break; | |
1870 | case 3: /* CLREX, DSB, DMB, ISB */ | |
1871 | handle_sync(s, insn, op1, op2, crm); | |
1872 | break; | |
4ce31af4 | 1873 | case 4: /* MSR (immediate) */ |
87462e0f CF |
1874 | handle_msr_i(s, insn, op1, op2, crm); |
1875 | break; | |
1876 | default: | |
1877 | unallocated_encoding(s); | |
1878 | break; | |
1879 | } | |
1880 | return; | |
1881 | } | |
fea50522 | 1882 | handle_sys(s, insn, l, op0, op1, op2, crn, crm, rt); |
87462e0f CF |
1883 | } |
1884 | ||
4ce31af4 | 1885 | /* Exception generation |
9618e809 AG |
1886 | * |
1887 | * 31 24 23 21 20 5 4 2 1 0 | |
1888 | * +-----------------+-----+------------------------+-----+----+ | |
1889 | * | 1 1 0 1 0 1 0 0 | opc | imm16 | op2 | LL | | |
1890 | * +-----------------------+------------------------+----------+ | |
1891 | */ | |
ad7ee8a2 CF |
1892 | static void disas_exc(DisasContext *s, uint32_t insn) |
1893 | { | |
9618e809 AG |
1894 | int opc = extract32(insn, 21, 3); |
1895 | int op2_ll = extract32(insn, 0, 5); | |
d4a2dc67 | 1896 | int imm16 = extract32(insn, 5, 16); |
e0d6e6a5 | 1897 | TCGv_i32 tmp; |
9618e809 AG |
1898 | |
1899 | switch (opc) { | |
1900 | case 0: | |
7ea47fe7 PM |
1901 | /* For SVC, HVC and SMC we advance the single-step state |
1902 | * machine before taking the exception. This is architecturally | |
1903 | * mandated, to ensure that single-stepping a system call | |
1904 | * instruction works properly. | |
1905 | */ | |
35979d71 | 1906 | switch (op2_ll) { |
957956b3 | 1907 | case 1: /* SVC */ |
35979d71 | 1908 | gen_ss_advance(s); |
a767fac8 RH |
1909 | gen_exception_insn(s, s->base.pc_next, EXCP_SWI, |
1910 | syn_aa64_svc(imm16), default_exception_el(s)); | |
35979d71 | 1911 | break; |
957956b3 | 1912 | case 2: /* HVC */ |
dcbff19b | 1913 | if (s->current_el == 0) { |
35979d71 EI |
1914 | unallocated_encoding(s); |
1915 | break; | |
1916 | } | |
1917 | /* The pre HVC helper handles cases when HVC gets trapped | |
1918 | * as an undefined insn by runtime configuration. | |
1919 | */ | |
43722a6d | 1920 | gen_a64_set_pc_im(s->pc_curr); |
35979d71 EI |
1921 | gen_helper_pre_hvc(cpu_env); |
1922 | gen_ss_advance(s); | |
a767fac8 RH |
1923 | gen_exception_insn(s, s->base.pc_next, EXCP_HVC, |
1924 | syn_aa64_hvc(imm16), 2); | |
35979d71 | 1925 | break; |
957956b3 | 1926 | case 3: /* SMC */ |
dcbff19b | 1927 | if (s->current_el == 0) { |
e0d6e6a5 EI |
1928 | unallocated_encoding(s); |
1929 | break; | |
1930 | } | |
43722a6d | 1931 | gen_a64_set_pc_im(s->pc_curr); |
e0d6e6a5 EI |
1932 | tmp = tcg_const_i32(syn_aa64_smc(imm16)); |
1933 | gen_helper_pre_smc(cpu_env, tmp); | |
1934 | tcg_temp_free_i32(tmp); | |
1935 | gen_ss_advance(s); | |
a767fac8 RH |
1936 | gen_exception_insn(s, s->base.pc_next, EXCP_SMC, |
1937 | syn_aa64_smc(imm16), 3); | |
e0d6e6a5 | 1938 | break; |
35979d71 EI |
1939 | default: |
1940 | unallocated_encoding(s); | |
1941 | break; | |
1942 | } | |
9618e809 AG |
1943 | break; |
1944 | case 1: | |
1945 | if (op2_ll != 0) { | |
1946 | unallocated_encoding(s); | |
1947 | break; | |
1948 | } | |
1949 | /* BRK */ | |
06bcbda3 | 1950 | gen_exception_bkpt_insn(s, syn_aa64_bkpt(imm16)); |
9618e809 AG |
1951 | break; |
1952 | case 2: | |
1953 | if (op2_ll != 0) { | |
1954 | unallocated_encoding(s); | |
1955 | break; | |
1956 | } | |
8012c84f PM |
1957 | /* HLT. This has two purposes. |
1958 | * Architecturally, it is an external halting debug instruction. | |
1959 | * Since QEMU doesn't implement external debug, we treat this as | |
1960 | * it is required for halting debug disabled: it will UNDEF. | |
1961 | * Secondly, "HLT 0xf000" is the A64 semihosting syscall instruction. | |
1962 | */ | |
1963 | if (semihosting_enabled() && imm16 == 0xf000) { | |
1964 | #ifndef CONFIG_USER_ONLY | |
1965 | /* In system mode, don't allow userspace access to semihosting, | |
1966 | * to provide some semblance of security (and for consistency | |
1967 | * with our 32-bit semihosting). | |
1968 | */ | |
1969 | if (s->current_el == 0) { | |
1970 | unsupported_encoding(s, insn); | |
1971 | break; | |
1972 | } | |
1973 | #endif | |
4ff5ef9e | 1974 | gen_exception_internal_insn(s, s->pc_curr, EXCP_SEMIHOST); |
8012c84f PM |
1975 | } else { |
1976 | unsupported_encoding(s, insn); | |
1977 | } | |
9618e809 AG |
1978 | break; |
1979 | case 5: | |
1980 | if (op2_ll < 1 || op2_ll > 3) { | |
1981 | unallocated_encoding(s); | |
1982 | break; | |
1983 | } | |
1984 | /* DCPS1, DCPS2, DCPS3 */ | |
1985 | unsupported_encoding(s, insn); | |
1986 | break; | |
1987 | default: | |
1988 | unallocated_encoding(s); | |
1989 | break; | |
1990 | } | |
ad7ee8a2 CF |
1991 | } |
1992 | ||
4ce31af4 | 1993 | /* Unconditional branch (register) |
b001c8c3 AG |
1994 | * 31 25 24 21 20 16 15 10 9 5 4 0 |
1995 | * +---------------+-------+-------+-------+------+-------+ | |
1996 | * | 1 1 0 1 0 1 1 | opc | op2 | op3 | Rn | op4 | | |
1997 | * +---------------+-------+-------+-------+------+-------+ | |
1998 | */ | |
ad7ee8a2 CF |
1999 | static void disas_uncond_b_reg(DisasContext *s, uint32_t insn) |
2000 | { | |
b001c8c3 | 2001 | unsigned int opc, op2, op3, rn, op4; |
001d47b6 | 2002 | unsigned btype_mod = 2; /* 0: BR, 1: BLR, 2: other */ |
d9f482a0 | 2003 | TCGv_i64 dst; |
561c0a33 | 2004 | TCGv_i64 modifier; |
b001c8c3 AG |
2005 | |
2006 | opc = extract32(insn, 21, 4); | |
2007 | op2 = extract32(insn, 16, 5); | |
2008 | op3 = extract32(insn, 10, 6); | |
2009 | rn = extract32(insn, 5, 5); | |
2010 | op4 = extract32(insn, 0, 5); | |
2011 | ||
f7cf3bfc RH |
2012 | if (op2 != 0x1f) { |
2013 | goto do_unallocated; | |
b001c8c3 AG |
2014 | } |
2015 | ||
2016 | switch (opc) { | |
2017 | case 0: /* BR */ | |
b001c8c3 | 2018 | case 1: /* BLR */ |
6feecb8b | 2019 | case 2: /* RET */ |
001d47b6 | 2020 | btype_mod = opc; |
f7cf3bfc RH |
2021 | switch (op3) { |
2022 | case 0: | |
561c0a33 | 2023 | /* BR, BLR, RET */ |
f7cf3bfc RH |
2024 | if (op4 != 0) { |
2025 | goto do_unallocated; | |
2026 | } | |
2027 | dst = cpu_reg(s, rn); | |
2028 | break; | |
2029 | ||
561c0a33 RH |
2030 | case 2: |
2031 | case 3: | |
2032 | if (!dc_isar_feature(aa64_pauth, s)) { | |
2033 | goto do_unallocated; | |
2034 | } | |
2035 | if (opc == 2) { | |
2036 | /* RETAA, RETAB */ | |
2037 | if (rn != 0x1f || op4 != 0x1f) { | |
2038 | goto do_unallocated; | |
2039 | } | |
2040 | rn = 30; | |
2041 | modifier = cpu_X[31]; | |
2042 | } else { | |
2043 | /* BRAAZ, BRABZ, BLRAAZ, BLRABZ */ | |
2044 | if (op4 != 0x1f) { | |
2045 | goto do_unallocated; | |
2046 | } | |
2047 | modifier = new_tmp_a64_zero(s); | |
2048 | } | |
2049 | if (s->pauth_active) { | |
2050 | dst = new_tmp_a64(s); | |
2051 | if (op3 == 2) { | |
2052 | gen_helper_autia(dst, cpu_env, cpu_reg(s, rn), modifier); | |
2053 | } else { | |
2054 | gen_helper_autib(dst, cpu_env, cpu_reg(s, rn), modifier); | |
2055 | } | |
2056 | } else { | |
2057 | dst = cpu_reg(s, rn); | |
2058 | } | |
2059 | break; | |
2060 | ||
f7cf3bfc RH |
2061 | default: |
2062 | goto do_unallocated; | |
2063 | } | |
f7cf3bfc | 2064 | gen_a64_set_pc(s, dst); |
6feecb8b TH |
2065 | /* BLR also needs to load return address */ |
2066 | if (opc == 1) { | |
a0415916 | 2067 | tcg_gen_movi_i64(cpu_reg(s, 30), s->base.pc_next); |
6feecb8b | 2068 | } |
b001c8c3 | 2069 | break; |
f7cf3bfc | 2070 | |
561c0a33 RH |
2071 | case 8: /* BRAA */ |
2072 | case 9: /* BLRAA */ | |
2073 | if (!dc_isar_feature(aa64_pauth, s)) { | |
2074 | goto do_unallocated; | |
2075 | } | |
1cf86a86 | 2076 | if ((op3 & ~1) != 2) { |
561c0a33 RH |
2077 | goto do_unallocated; |
2078 | } | |
001d47b6 | 2079 | btype_mod = opc & 1; |
561c0a33 RH |
2080 | if (s->pauth_active) { |
2081 | dst = new_tmp_a64(s); | |
2082 | modifier = cpu_reg_sp(s, op4); | |
2083 | if (op3 == 2) { | |
2084 | gen_helper_autia(dst, cpu_env, cpu_reg(s, rn), modifier); | |
2085 | } else { | |
2086 | gen_helper_autib(dst, cpu_env, cpu_reg(s, rn), modifier); | |
2087 | } | |
2088 | } else { | |
2089 | dst = cpu_reg(s, rn); | |
2090 | } | |
2091 | gen_a64_set_pc(s, dst); | |
2092 | /* BLRAA also needs to load return address */ | |
2093 | if (opc == 9) { | |
a0415916 | 2094 | tcg_gen_movi_i64(cpu_reg(s, 30), s->base.pc_next); |
561c0a33 RH |
2095 | } |
2096 | break; | |
2097 | ||
b001c8c3 | 2098 | case 4: /* ERET */ |
dcbff19b | 2099 | if (s->current_el == 0) { |
f7cf3bfc RH |
2100 | goto do_unallocated; |
2101 | } | |
2102 | switch (op3) { | |
561c0a33 | 2103 | case 0: /* ERET */ |
f7cf3bfc RH |
2104 | if (op4 != 0) { |
2105 | goto do_unallocated; | |
2106 | } | |
2107 | dst = tcg_temp_new_i64(); | |
2108 | tcg_gen_ld_i64(dst, cpu_env, | |
2109 | offsetof(CPUARMState, elr_el[s->current_el])); | |
2110 | break; | |
2111 | ||
561c0a33 RH |
2112 | case 2: /* ERETAA */ |
2113 | case 3: /* ERETAB */ | |
2114 | if (!dc_isar_feature(aa64_pauth, s)) { | |
2115 | goto do_unallocated; | |
2116 | } | |
2117 | if (rn != 0x1f || op4 != 0x1f) { | |
2118 | goto do_unallocated; | |
2119 | } | |
2120 | dst = tcg_temp_new_i64(); | |
2121 | tcg_gen_ld_i64(dst, cpu_env, | |
2122 | offsetof(CPUARMState, elr_el[s->current_el])); | |
2123 | if (s->pauth_active) { | |
2124 | modifier = cpu_X[31]; | |
2125 | if (op3 == 2) { | |
2126 | gen_helper_autia(dst, cpu_env, dst, modifier); | |
2127 | } else { | |
2128 | gen_helper_autib(dst, cpu_env, dst, modifier); | |
2129 | } | |
2130 | } | |
2131 | break; | |
2132 | ||
f7cf3bfc RH |
2133 | default: |
2134 | goto do_unallocated; | |
14c521d4 | 2135 | } |
e69ad9df AL |
2136 | if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { |
2137 | gen_io_start(); | |
2138 | } | |
f7cf3bfc | 2139 | |
d9f482a0 RH |
2140 | gen_helper_exception_return(cpu_env, dst); |
2141 | tcg_temp_free_i64(dst); | |
b29fd33d | 2142 | /* Must exit loop to check un-masked IRQs */ |
dcba3a8d | 2143 | s->base.is_jmp = DISAS_EXIT; |
52e60cdd | 2144 | return; |
f7cf3bfc | 2145 | |
b001c8c3 | 2146 | case 5: /* DRPS */ |
f7cf3bfc RH |
2147 | if (op3 != 0 || op4 != 0 || rn != 0x1f) { |
2148 | goto do_unallocated; | |
b001c8c3 AG |
2149 | } else { |
2150 | unsupported_encoding(s, insn); | |
2151 | } | |
2152 | return; | |
f7cf3bfc | 2153 | |
b001c8c3 | 2154 | default: |
f7cf3bfc | 2155 | do_unallocated: |
b001c8c3 AG |
2156 | unallocated_encoding(s); |
2157 | return; | |
2158 | } | |
2159 | ||
001d47b6 RH |
2160 | switch (btype_mod) { |
2161 | case 0: /* BR */ | |
2162 | if (dc_isar_feature(aa64_bti, s)) { | |
2163 | /* BR to {x16,x17} or !guard -> 1, else 3. */ | |
2164 | set_btype(s, rn == 16 || rn == 17 || !s->guarded_page ? 1 : 3); | |
2165 | } | |
2166 | break; | |
2167 | ||
2168 | case 1: /* BLR */ | |
2169 | if (dc_isar_feature(aa64_bti, s)) { | |
2170 | /* BLR sets BTYPE to 2, regardless of source guarded page. */ | |
2171 | set_btype(s, 2); | |
2172 | } | |
2173 | break; | |
2174 | ||
2175 | default: /* RET or none of the above. */ | |
2176 | /* BTYPE will be set to 0 by normal end-of-insn processing. */ | |
2177 | break; | |
2178 | } | |
2179 | ||
dcba3a8d | 2180 | s->base.is_jmp = DISAS_JUMP; |
ad7ee8a2 CF |
2181 | } |
2182 | ||
4ce31af4 | 2183 | /* Branches, exception generating and system instructions */ |
ad7ee8a2 CF |
2184 | static void disas_b_exc_sys(DisasContext *s, uint32_t insn) |
2185 | { | |
2186 | switch (extract32(insn, 25, 7)) { | |
2187 | case 0x0a: case 0x0b: | |
2188 | case 0x4a: case 0x4b: /* Unconditional branch (immediate) */ | |
2189 | disas_uncond_b_imm(s, insn); | |
2190 | break; | |
2191 | case 0x1a: case 0x5a: /* Compare & branch (immediate) */ | |
2192 | disas_comp_b_imm(s, insn); | |
2193 | break; | |
2194 | case 0x1b: case 0x5b: /* Test & branch (immediate) */ | |
2195 | disas_test_b_imm(s, insn); | |
2196 | break; | |
2197 | case 0x2a: /* Conditional branch (immediate) */ | |
2198 | disas_cond_b_imm(s, insn); | |
2199 | break; | |
2200 | case 0x6a: /* Exception generation / System */ | |
2201 | if (insn & (1 << 24)) { | |
08d5e3bd PM |
2202 | if (extract32(insn, 22, 2) == 0) { |
2203 | disas_system(s, insn); | |
2204 | } else { | |
2205 | unallocated_encoding(s); | |
2206 | } | |
ad7ee8a2 CF |
2207 | } else { |
2208 | disas_exc(s, insn); | |
2209 | } | |
2210 | break; | |
2211 | case 0x6b: /* Unconditional branch (register) */ | |
2212 | disas_uncond_b_reg(s, insn); | |
2213 | break; | |
2214 | default: | |
2215 | unallocated_encoding(s); | |
2216 | break; | |
2217 | } | |
2218 | } | |
2219 | ||
5460da50 AB |
2220 | /* |
2221 | * Load/Store exclusive instructions are implemented by remembering | |
2222 | * the value/address loaded, and seeing if these are the same | |
2223 | * when the store is performed. This is not actually the architecturally | |
2224 | * mandated semantics, but it works for typical guest code sequences | |
2225 | * and avoids having to monitor regular stores. | |
2226 | * | |
2227 | * The store exclusive uses the atomic cmpxchg primitives to avoid | |
2228 | * races in multi-threaded linux-user and when MTTCG softmmu is | |
2229 | * enabled. | |
2230 | */ | |
fa2ef212 MM |
2231 | static void gen_load_exclusive(DisasContext *s, int rt, int rt2, |
2232 | TCGv_i64 addr, int size, bool is_pair) | |
2233 | { | |
19514cde | 2234 | int idx = get_mem_index(s); |
14776ab5 | 2235 | MemOp memop = s->be_data; |
fa2ef212 MM |
2236 | |
2237 | g_assert(size <= 3); | |
fa2ef212 | 2238 | if (is_pair) { |
5460da50 | 2239 | g_assert(size >= 2); |
19514cde RH |
2240 | if (size == 2) { |
2241 | /* The pair must be single-copy atomic for the doubleword. */ | |
4a2fdb78 | 2242 | memop |= MO_64 | MO_ALIGN; |
19514cde RH |
2243 | tcg_gen_qemu_ld_i64(cpu_exclusive_val, addr, idx, memop); |
2244 | if (s->be_data == MO_LE) { | |
2245 | tcg_gen_extract_i64(cpu_reg(s, rt), cpu_exclusive_val, 0, 32); | |
2246 | tcg_gen_extract_i64(cpu_reg(s, rt2), cpu_exclusive_val, 32, 32); | |
2247 | } else { | |
2248 | tcg_gen_extract_i64(cpu_reg(s, rt), cpu_exclusive_val, 32, 32); | |
2249 | tcg_gen_extract_i64(cpu_reg(s, rt2), cpu_exclusive_val, 0, 32); | |
2250 | } | |
2251 | } else { | |
4a2fdb78 AF |
2252 | /* The pair must be single-copy atomic for *each* doubleword, not |
2253 | the entire quadword, however it must be quadword aligned. */ | |
19514cde | 2254 | memop |= MO_64; |
4a2fdb78 AF |
2255 | tcg_gen_qemu_ld_i64(cpu_exclusive_val, addr, idx, |
2256 | memop | MO_ALIGN_16); | |
19514cde RH |
2257 | |
2258 | TCGv_i64 addr2 = tcg_temp_new_i64(); | |
2259 | tcg_gen_addi_i64(addr2, addr, 8); | |
2260 | tcg_gen_qemu_ld_i64(cpu_exclusive_high, addr2, idx, memop); | |
2261 | tcg_temp_free_i64(addr2); | |
2262 | ||
2263 | tcg_gen_mov_i64(cpu_reg(s, rt), cpu_exclusive_val); | |
2264 | tcg_gen_mov_i64(cpu_reg(s, rt2), cpu_exclusive_high); | |
2265 | } | |
2266 | } else { | |
4a2fdb78 | 2267 | memop |= size | MO_ALIGN; |
19514cde RH |
2268 | tcg_gen_qemu_ld_i64(cpu_exclusive_val, addr, idx, memop); |
2269 | tcg_gen_mov_i64(cpu_reg(s, rt), cpu_exclusive_val); | |
fa2ef212 | 2270 | } |
fa2ef212 MM |
2271 | tcg_gen_mov_i64(cpu_exclusive_addr, addr); |
2272 | } | |
2273 | ||
fa2ef212 | 2274 | static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2, |
37e29a64 | 2275 | TCGv_i64 addr, int size, int is_pair) |
fa2ef212 | 2276 | { |
d324b36a PM |
2277 | /* if (env->exclusive_addr == addr && env->exclusive_val == [addr] |
2278 | * && (!is_pair || env->exclusive_high == [addr + datasize])) { | |
2279 | * [addr] = {Rt}; | |
2280 | * if (is_pair) { | |
2281 | * [addr + datasize] = {Rt2}; | |
2282 | * } | |
2283 | * {Rd} = 0; | |
2284 | * } else { | |
2285 | * {Rd} = 1; | |
2286 | * } | |
2287 | * env->exclusive_addr = -1; | |
2288 | */ | |
42a268c2 RH |
2289 | TCGLabel *fail_label = gen_new_label(); |
2290 | TCGLabel *done_label = gen_new_label(); | |
d324b36a PM |
2291 | TCGv_i64 tmp; |
2292 | ||
d324b36a PM |
2293 | tcg_gen_brcond_i64(TCG_COND_NE, addr, cpu_exclusive_addr, fail_label); |
2294 | ||
2295 | tmp = tcg_temp_new_i64(); | |
d324b36a | 2296 | if (is_pair) { |
1dd089d0 | 2297 | if (size == 2) { |
19514cde RH |
2298 | if (s->be_data == MO_LE) { |
2299 | tcg_gen_concat32_i64(tmp, cpu_reg(s, rt), cpu_reg(s, rt2)); | |
2300 | } else { | |
2301 | tcg_gen_concat32_i64(tmp, cpu_reg(s, rt2), cpu_reg(s, rt)); | |
2302 | } | |
37e29a64 RH |
2303 | tcg_gen_atomic_cmpxchg_i64(tmp, cpu_exclusive_addr, |
2304 | cpu_exclusive_val, tmp, | |
1dd089d0 | 2305 | get_mem_index(s), |
955fd0ad | 2306 | MO_64 | MO_ALIGN | s->be_data); |
19514cde | 2307 | tcg_gen_setcond_i64(TCG_COND_NE, tmp, tmp, cpu_exclusive_val); |
62823083 RH |
2308 | } else if (tb_cflags(s->base.tb) & CF_PARALLEL) { |
2309 | if (!HAVE_CMPXCHG128) { | |
2310 | gen_helper_exit_atomic(cpu_env); | |
2311 | s->base.is_jmp = DISAS_NORETURN; | |
2312 | } else if (s->be_data == MO_LE) { | |
2399d4e7 EC |
2313 | gen_helper_paired_cmpxchg64_le_parallel(tmp, cpu_env, |
2314 | cpu_exclusive_addr, | |
2315 | cpu_reg(s, rt), | |
2316 | cpu_reg(s, rt2)); | |
2317 | } else { | |
2399d4e7 EC |
2318 | gen_helper_paired_cmpxchg64_be_parallel(tmp, cpu_env, |
2319 | cpu_exclusive_addr, | |
2320 | cpu_reg(s, rt), | |
2321 | cpu_reg(s, rt2)); | |
2399d4e7 | 2322 | } |
62823083 RH |
2323 | } else if (s->be_data == MO_LE) { |
2324 | gen_helper_paired_cmpxchg64_le(tmp, cpu_env, cpu_exclusive_addr, | |
2325 | cpu_reg(s, rt), cpu_reg(s, rt2)); | |
2326 | } else { | |
2327 | gen_helper_paired_cmpxchg64_be(tmp, cpu_env, cpu_exclusive_addr, | |
2328 | cpu_reg(s, rt), cpu_reg(s, rt2)); | |
1dd089d0 EC |
2329 | } |
2330 | } else { | |
37e29a64 RH |
2331 | tcg_gen_atomic_cmpxchg_i64(tmp, cpu_exclusive_addr, cpu_exclusive_val, |
2332 | cpu_reg(s, rt), get_mem_index(s), | |
1dd089d0 EC |
2333 | size | MO_ALIGN | s->be_data); |
2334 | tcg_gen_setcond_i64(TCG_COND_NE, tmp, tmp, cpu_exclusive_val); | |
d324b36a | 2335 | } |
1dd089d0 EC |
2336 | tcg_gen_mov_i64(cpu_reg(s, rd), tmp); |
2337 | tcg_temp_free_i64(tmp); | |
d324b36a | 2338 | tcg_gen_br(done_label); |
1dd089d0 | 2339 | |
d324b36a PM |
2340 | gen_set_label(fail_label); |
2341 | tcg_gen_movi_i64(cpu_reg(s, rd), 1); | |
2342 | gen_set_label(done_label); | |
2343 | tcg_gen_movi_i64(cpu_exclusive_addr, -1); | |
fa2ef212 | 2344 | } |
fa2ef212 | 2345 | |
44ac14b0 RH |
2346 | static void gen_compare_and_swap(DisasContext *s, int rs, int rt, |
2347 | int rn, int size) | |
2348 | { | |
2349 | TCGv_i64 tcg_rs = cpu_reg(s, rs); | |
2350 | TCGv_i64 tcg_rt = cpu_reg(s, rt); | |
2351 | int memidx = get_mem_index(s); | |
3a471103 | 2352 | TCGv_i64 clean_addr; |
44ac14b0 RH |
2353 | |
2354 | if (rn == 31) { | |
2355 | gen_check_sp_alignment(s); | |
2356 | } | |
3a471103 RH |
2357 | clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn)); |
2358 | tcg_gen_atomic_cmpxchg_i64(tcg_rs, clean_addr, tcg_rs, tcg_rt, memidx, | |
44ac14b0 RH |
2359 | size | MO_ALIGN | s->be_data); |
2360 | } | |
2361 | ||
2362 | static void gen_compare_and_swap_pair(DisasContext *s, int rs, int rt, | |
2363 | int rn, int size) | |
2364 | { | |
2365 | TCGv_i64 s1 = cpu_reg(s, rs); | |
2366 | TCGv_i64 s2 = cpu_reg(s, rs + 1); | |
2367 | TCGv_i64 t1 = cpu_reg(s, rt); | |
2368 | TCGv_i64 t2 = cpu_reg(s, rt + 1); | |
3a471103 | 2369 | TCGv_i64 clean_addr; |
44ac14b0 RH |
2370 | int memidx = get_mem_index(s); |
2371 | ||
2372 | if (rn == 31) { | |
2373 | gen_check_sp_alignment(s); | |
2374 | } | |
3a471103 | 2375 | clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn)); |
44ac14b0 RH |
2376 | |
2377 | if (size == 2) { | |
2378 | TCGv_i64 cmp = tcg_temp_new_i64(); | |
2379 | TCGv_i64 val = tcg_temp_new_i64(); | |
2380 | ||
2381 | if (s->be_data == MO_LE) { | |
2382 | tcg_gen_concat32_i64(val, t1, t2); | |
2383 | tcg_gen_concat32_i64(cmp, s1, s2); | |
2384 | } else { | |
2385 | tcg_gen_concat32_i64(val, t2, t1); | |
2386 | tcg_gen_concat32_i64(cmp, s2, s1); | |
2387 | } | |
2388 | ||
3a471103 | 2389 | tcg_gen_atomic_cmpxchg_i64(cmp, clean_addr, cmp, val, memidx, |
44ac14b0 RH |
2390 | MO_64 | MO_ALIGN | s->be_data); |
2391 | tcg_temp_free_i64(val); | |
2392 | ||
2393 | if (s->be_data == MO_LE) { | |
2394 | tcg_gen_extr32_i64(s1, s2, cmp); | |
2395 | } else { | |
2396 | tcg_gen_extr32_i64(s2, s1, cmp); | |
2397 | } | |
2398 | tcg_temp_free_i64(cmp); | |
2399 | } else if (tb_cflags(s->base.tb) & CF_PARALLEL) { | |
62823083 RH |
2400 | if (HAVE_CMPXCHG128) { |
2401 | TCGv_i32 tcg_rs = tcg_const_i32(rs); | |
2402 | if (s->be_data == MO_LE) { | |
3a471103 RH |
2403 | gen_helper_casp_le_parallel(cpu_env, tcg_rs, |
2404 | clean_addr, t1, t2); | |
62823083 | 2405 | } else { |
3a471103 RH |
2406 | gen_helper_casp_be_parallel(cpu_env, tcg_rs, |
2407 | clean_addr, t1, t2); | |
62823083 RH |
2408 | } |
2409 | tcg_temp_free_i32(tcg_rs); | |
44ac14b0 | 2410 | } else { |
62823083 RH |
2411 | gen_helper_exit_atomic(cpu_env); |
2412 | s->base.is_jmp = DISAS_NORETURN; | |
44ac14b0 | 2413 | } |
44ac14b0 RH |
2414 | } else { |
2415 | TCGv_i64 d1 = tcg_temp_new_i64(); | |
2416 | TCGv_i64 d2 = tcg_temp_new_i64(); | |
2417 | TCGv_i64 a2 = tcg_temp_new_i64(); | |
2418 | TCGv_i64 c1 = tcg_temp_new_i64(); | |
2419 | TCGv_i64 c2 = tcg_temp_new_i64(); | |
2420 | TCGv_i64 zero = tcg_const_i64(0); | |
2421 | ||
2422 | /* Load the two words, in memory order. */ | |
3a471103 | 2423 | tcg_gen_qemu_ld_i64(d1, clean_addr, memidx, |
44ac14b0 | 2424 | MO_64 | MO_ALIGN_16 | s->be_data); |
3a471103 | 2425 | tcg_gen_addi_i64(a2, clean_addr, 8); |
a036f530 | 2426 | tcg_gen_qemu_ld_i64(d2, a2, memidx, MO_64 | s->be_data); |
44ac14b0 RH |
2427 | |
2428 | /* Compare the two words, also in memory order. */ | |
2429 | tcg_gen_setcond_i64(TCG_COND_EQ, c1, d1, s1); | |
2430 | tcg_gen_setcond_i64(TCG_COND_EQ, c2, d2, s2); | |
2431 | tcg_gen_and_i64(c2, c2, c1); | |
2432 | ||
2433 | /* If compare equal, write back new data, else write back old data. */ | |
2434 | tcg_gen_movcond_i64(TCG_COND_NE, c1, c2, zero, t1, d1); | |
2435 | tcg_gen_movcond_i64(TCG_COND_NE, c2, c2, zero, t2, d2); | |
3a471103 | 2436 | tcg_gen_qemu_st_i64(c1, clean_addr, memidx, MO_64 | s->be_data); |
44ac14b0 RH |
2437 | tcg_gen_qemu_st_i64(c2, a2, memidx, MO_64 | s->be_data); |
2438 | tcg_temp_free_i64(a2); | |
2439 | tcg_temp_free_i64(c1); | |
2440 | tcg_temp_free_i64(c2); | |
2441 | tcg_temp_free_i64(zero); | |
2442 | ||
2443 | /* Write back the data from memory to Rs. */ | |
2444 | tcg_gen_mov_i64(s1, d1); | |
2445 | tcg_gen_mov_i64(s2, d2); | |
2446 | tcg_temp_free_i64(d1); | |
2447 | tcg_temp_free_i64(d2); | |
2448 | } | |
2449 | } | |
2450 | ||
aaa1f954 EI |
2451 | /* Update the Sixty-Four bit (SF) registersize. This logic is derived |
2452 | * from the ARMv8 specs for LDR (Shared decode for all encodings). | |
2453 | */ | |
2454 | static bool disas_ldst_compute_iss_sf(int size, bool is_signed, int opc) | |
2455 | { | |
2456 | int opc0 = extract32(opc, 0, 1); | |
2457 | int regsize; | |
2458 | ||
2459 | if (is_signed) { | |
2460 | regsize = opc0 ? 32 : 64; | |
2461 | } else { | |
2462 | regsize = size == 3 ? 64 : 32; | |
2463 | } | |
2464 | return regsize == 64; | |
2465 | } | |
2466 | ||
4ce31af4 | 2467 | /* Load/store exclusive |
fa2ef212 MM |
2468 | * |
2469 | * 31 30 29 24 23 22 21 20 16 15 14 10 9 5 4 0 | |
2470 | * +-----+-------------+----+---+----+------+----+-------+------+------+ | |
2471 | * | sz | 0 0 1 0 0 0 | o2 | L | o1 | Rs | o0 | Rt2 | Rn | Rt | | |
2472 | * +-----+-------------+----+---+----+------+----+-------+------+------+ | |
2473 | * | |
2474 | * sz: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64 bit | |
2475 | * L: 0 -> store, 1 -> load | |
2476 | * o2: 0 -> exclusive, 1 -> not | |
2477 | * o1: 0 -> single register, 1 -> register pair | |
2478 | * o0: 1 -> load-acquire/store-release, 0 -> not | |
fa2ef212 | 2479 | */ |
ad7ee8a2 CF |
2480 | static void disas_ldst_excl(DisasContext *s, uint32_t insn) |
2481 | { | |
fa2ef212 MM |
2482 | int rt = extract32(insn, 0, 5); |
2483 | int rn = extract32(insn, 5, 5); | |
2484 | int rt2 = extract32(insn, 10, 5); | |
fa2ef212 | 2485 | int rs = extract32(insn, 16, 5); |
68412d2e RH |
2486 | int is_lasr = extract32(insn, 15, 1); |
2487 | int o2_L_o1_o0 = extract32(insn, 21, 3) * 2 | is_lasr; | |
fa2ef212 | 2488 | int size = extract32(insn, 30, 2); |
3a471103 | 2489 | TCGv_i64 clean_addr; |
fa2ef212 | 2490 | |
68412d2e RH |
2491 | switch (o2_L_o1_o0) { |
2492 | case 0x0: /* STXR */ | |
2493 | case 0x1: /* STLXR */ | |
2494 | if (rn == 31) { | |
2495 | gen_check_sp_alignment(s); | |
2496 | } | |
2497 | if (is_lasr) { | |
2498 | tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); | |
2499 | } | |
3a471103 RH |
2500 | clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn)); |
2501 | gen_store_exclusive(s, rs, rt, rt2, clean_addr, size, false); | |
fa2ef212 | 2502 | return; |
fa2ef212 | 2503 | |
68412d2e RH |
2504 | case 0x4: /* LDXR */ |
2505 | case 0x5: /* LDAXR */ | |
2506 | if (rn == 31) { | |
2507 | gen_check_sp_alignment(s); | |
2508 | } | |
3a471103 | 2509 | clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn)); |
68412d2e | 2510 | s->is_ldex = true; |
3a471103 | 2511 | gen_load_exclusive(s, rt, rt2, clean_addr, size, false); |
68412d2e RH |
2512 | if (is_lasr) { |
2513 | tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); | |
2514 | } | |
2515 | return; | |
fa2ef212 | 2516 | |
2d7137c1 RH |
2517 | case 0x8: /* STLLR */ |
2518 | if (!dc_isar_feature(aa64_lor, s)) { | |
2519 | break; | |
2520 | } | |
2521 | /* StoreLORelease is the same as Store-Release for QEMU. */ | |
2522 | /* fall through */ | |
68412d2e RH |
2523 | case 0x9: /* STLR */ |
2524 | /* Generate ISS for non-exclusive accesses including LASR. */ | |
2525 | if (rn == 31) { | |
2526 | gen_check_sp_alignment(s); | |
2527 | } | |
2528 | tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); | |
3a471103 RH |
2529 | clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn)); |
2530 | do_gpr_st(s, cpu_reg(s, rt), clean_addr, size, true, rt, | |
68412d2e RH |
2531 | disas_ldst_compute_iss_sf(size, false, 0), is_lasr); |
2532 | return; | |
fa2ef212 | 2533 | |
2d7137c1 RH |
2534 | case 0xc: /* LDLAR */ |
2535 | if (!dc_isar_feature(aa64_lor, s)) { | |
2536 | break; | |
2537 | } | |
2538 | /* LoadLOAcquire is the same as Load-Acquire for QEMU. */ | |
2539 | /* fall through */ | |
68412d2e RH |
2540 | case 0xd: /* LDAR */ |
2541 | /* Generate ISS for non-exclusive accesses including LASR. */ | |
2542 | if (rn == 31) { | |
2543 | gen_check_sp_alignment(s); | |
2544 | } | |
3a471103 RH |
2545 | clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn)); |
2546 | do_gpr_ld(s, cpu_reg(s, rt), clean_addr, size, false, false, true, rt, | |
68412d2e RH |
2547 | disas_ldst_compute_iss_sf(size, false, 0), is_lasr); |
2548 | tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); | |
2549 | return; | |
2550 | ||
2551 | case 0x2: case 0x3: /* CASP / STXP */ | |
2552 | if (size & 2) { /* STXP / STLXP */ | |
2553 | if (rn == 31) { | |
2554 | gen_check_sp_alignment(s); | |
ce1bd93f | 2555 | } |
ce1bd93f PK |
2556 | if (is_lasr) { |
2557 | tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); | |
2558 | } | |
3a471103 RH |
2559 | clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn)); |
2560 | gen_store_exclusive(s, rs, rt, rt2, clean_addr, size, true); | |
68412d2e | 2561 | return; |
fa2ef212 | 2562 | } |
44ac14b0 RH |
2563 | if (rt2 == 31 |
2564 | && ((rt | rs) & 1) == 0 | |
962fcbf2 | 2565 | && dc_isar_feature(aa64_atomics, s)) { |
44ac14b0 RH |
2566 | /* CASP / CASPL */ |
2567 | gen_compare_and_swap_pair(s, rs, rt, rn, size | 2); | |
2568 | return; | |
2569 | } | |
68412d2e | 2570 | break; |
aaa1f954 | 2571 | |
44ac14b0 | 2572 | case 0x6: case 0x7: /* CASPA / LDXP */ |
68412d2e RH |
2573 | if (size & 2) { /* LDXP / LDAXP */ |
2574 | if (rn == 31) { | |
2575 | gen_check_sp_alignment(s); | |
ce1bd93f | 2576 | } |
3a471103 | 2577 | clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn)); |
68412d2e | 2578 | s->is_ldex = true; |
3a471103 | 2579 | gen_load_exclusive(s, rt, rt2, clean_addr, size, true); |
ce1bd93f PK |
2580 | if (is_lasr) { |
2581 | tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); | |
2582 | } | |
68412d2e | 2583 | return; |
fa2ef212 | 2584 | } |
44ac14b0 RH |
2585 | if (rt2 == 31 |
2586 | && ((rt | rs) & 1) == 0 | |
962fcbf2 | 2587 | && dc_isar_feature(aa64_atomics, s)) { |
44ac14b0 RH |
2588 | /* CASPA / CASPAL */ |
2589 | gen_compare_and_swap_pair(s, rs, rt, rn, size | 2); | |
2590 | return; | |
fa2ef212 | 2591 | } |
68412d2e RH |
2592 | break; |
2593 | ||
2594 | case 0xa: /* CAS */ | |
2595 | case 0xb: /* CASL */ | |
2596 | case 0xe: /* CASA */ | |
2597 | case 0xf: /* CASAL */ | |
962fcbf2 | 2598 | if (rt2 == 31 && dc_isar_feature(aa64_atomics, s)) { |
44ac14b0 RH |
2599 | gen_compare_and_swap(s, rs, rt, rn, size); |
2600 | return; | |
2601 | } | |
68412d2e | 2602 | break; |
fa2ef212 | 2603 | } |
68412d2e | 2604 | unallocated_encoding(s); |
ad7ee8a2 CF |
2605 | } |
2606 | ||
32b64e86 | 2607 | /* |
4ce31af4 | 2608 | * Load register (literal) |
32b64e86 AG |
2609 | * |
2610 | * 31 30 29 27 26 25 24 23 5 4 0 | |
2611 | * +-----+-------+---+-----+-------------------+-------+ | |
2612 | * | opc | 0 1 1 | V | 0 0 | imm19 | Rt | | |
2613 | * +-----+-------+---+-----+-------------------+-------+ | |
2614 | * | |
2615 | * V: 1 -> vector (simd/fp) | |
2616 | * opc (non-vector): 00 -> 32 bit, 01 -> 64 bit, | |
2617 | * 10-> 32 bit signed, 11 -> prefetch | |
2618 | * opc (vector): 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit (11 unallocated) | |
2619 | */ | |
ad7ee8a2 CF |
2620 | static void disas_ld_lit(DisasContext *s, uint32_t insn) |
2621 | { | |
32b64e86 AG |
2622 | int rt = extract32(insn, 0, 5); |
2623 | int64_t imm = sextract32(insn, 5, 19) << 2; | |
2624 | bool is_vector = extract32(insn, 26, 1); | |
2625 | int opc = extract32(insn, 30, 2); | |
2626 | bool is_signed = false; | |
2627 | int size = 2; | |
3a471103 | 2628 | TCGv_i64 tcg_rt, clean_addr; |
32b64e86 AG |
2629 | |
2630 | if (is_vector) { | |
2631 | if (opc == 3) { | |
2632 | unallocated_encoding(s); | |
2633 | return; | |
2634 | } | |
2635 | size = 2 + opc; | |
8c6afa6a PM |
2636 | if (!fp_access_check(s)) { |
2637 | return; | |
2638 | } | |
32b64e86 AG |
2639 | } else { |
2640 | if (opc == 3) { | |
2641 | /* PRFM (literal) : prefetch */ | |
2642 | return; | |
2643 | } | |
2644 | size = 2 + extract32(opc, 0, 1); | |
2645 | is_signed = extract32(opc, 1, 1); | |
2646 | } | |
2647 | ||
2648 | tcg_rt = cpu_reg(s, rt); | |
2649 | ||
43722a6d | 2650 | clean_addr = tcg_const_i64(s->pc_curr + imm); |
32b64e86 | 2651 | if (is_vector) { |
3a471103 | 2652 | do_fp_ld(s, rt, clean_addr, size); |
32b64e86 | 2653 | } else { |
aaa1f954 | 2654 | /* Only unsigned 32bit loads target 32bit registers. */ |
173ff585 | 2655 | bool iss_sf = opc != 0; |
aaa1f954 | 2656 | |
3a471103 | 2657 | do_gpr_ld(s, tcg_rt, clean_addr, size, is_signed, false, |
aaa1f954 | 2658 | true, rt, iss_sf, false); |
32b64e86 | 2659 | } |
3a471103 | 2660 | tcg_temp_free_i64(clean_addr); |
ad7ee8a2 CF |
2661 | } |
2662 | ||
4a08d475 | 2663 | /* |
4ce31af4 PM |
2664 | * LDNP (Load Pair - non-temporal hint) |
2665 | * LDP (Load Pair - non vector) | |
2666 | * LDPSW (Load Pair Signed Word - non vector) | |
2667 | * STNP (Store Pair - non-temporal hint) | |
2668 | * STP (Store Pair - non vector) | |
2669 | * LDNP (Load Pair of SIMD&FP - non-temporal hint) | |
2670 | * LDP (Load Pair of SIMD&FP) | |
2671 | * STNP (Store Pair of SIMD&FP - non-temporal hint) | |
2672 | * STP (Store Pair of SIMD&FP) | |
4a08d475 PM |
2673 | * |
2674 | * 31 30 29 27 26 25 24 23 22 21 15 14 10 9 5 4 0 | |
2675 | * +-----+-------+---+---+-------+---+-----------------------------+ | |
2676 | * | opc | 1 0 1 | V | 0 | index | L | imm7 | Rt2 | Rn | Rt | | |
2677 | * +-----+-------+---+---+-------+---+-------+-------+------+------+ | |
2678 | * | |
2679 | * opc: LDP/STP/LDNP/STNP 00 -> 32 bit, 10 -> 64 bit | |
2680 | * LDPSW 01 | |
2681 | * LDP/STP/LDNP/STNP (SIMD) 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit | |
2682 | * V: 0 -> GPR, 1 -> Vector | |
2683 | * idx: 00 -> signed offset with non-temporal hint, 01 -> post-index, | |
2684 | * 10 -> signed offset, 11 -> pre-index | |
2685 | * L: 0 -> Store 1 -> Load | |
2686 | * | |
2687 | * Rt, Rt2 = GPR or SIMD registers to be stored | |
2688 | * Rn = general purpose register containing address | |
2689 | * imm7 = signed offset (multiple of 4 or 8 depending on size) | |
2690 | */ | |
ad7ee8a2 CF |
2691 | static void disas_ldst_pair(DisasContext *s, uint32_t insn) |
2692 | { | |
4a08d475 PM |
2693 | int rt = extract32(insn, 0, 5); |
2694 | int rn = extract32(insn, 5, 5); | |
2695 | int rt2 = extract32(insn, 10, 5); | |
c2ebd862 | 2696 | uint64_t offset = sextract64(insn, 15, 7); |
4a08d475 PM |
2697 | int index = extract32(insn, 23, 2); |
2698 | bool is_vector = extract32(insn, 26, 1); | |
2699 | bool is_load = extract32(insn, 22, 1); | |
2700 | int opc = extract32(insn, 30, 2); | |
2701 | ||
2702 | bool is_signed = false; | |
2703 | bool postindex = false; | |
2704 | bool wback = false; | |
2705 | ||
3a471103 RH |
2706 | TCGv_i64 clean_addr, dirty_addr; |
2707 | ||
4a08d475 PM |
2708 | int size; |
2709 | ||
2710 | if (opc == 3) { | |
2711 | unallocated_encoding(s); | |
2712 | return; | |
2713 | } | |
2714 | ||
2715 | if (is_vector) { | |
2716 | size = 2 + opc; | |
2717 | } else { | |
2718 | size = 2 + extract32(opc, 1, 1); | |
2719 | is_signed = extract32(opc, 0, 1); | |
2720 | if (!is_load && is_signed) { | |
2721 | unallocated_encoding(s); | |
2722 | return; | |
2723 | } | |
2724 | } | |
2725 | ||
2726 | switch (index) { | |
2727 | case 1: /* post-index */ | |
2728 | postindex = true; | |
2729 | wback = true; | |
2730 | break; | |
2731 | case 0: | |
2732 | /* signed offset with "non-temporal" hint. Since we don't emulate | |
2733 | * caches we don't care about hints to the cache system about | |
2734 | * data access patterns, and handle this identically to plain | |
2735 | * signed offset. | |
2736 | */ | |
2737 | if (is_signed) { | |
2738 | /* There is no non-temporal-hint version of LDPSW */ | |
2739 | unallocated_encoding(s); | |
2740 | return; | |
2741 | } | |
2742 | postindex = false; | |
2743 | break; | |
2744 | case 2: /* signed offset, rn not updated */ | |
2745 | postindex = false; | |
2746 | break; | |
2747 | case 3: /* pre-index */ | |
2748 | postindex = false; | |
2749 | wback = true; | |
2750 | break; | |
2751 | } | |
2752 | ||
8c6afa6a PM |
2753 | if (is_vector && !fp_access_check(s)) { |
2754 | return; | |
2755 | } | |
2756 | ||
4a08d475 PM |
2757 | offset <<= size; |
2758 | ||
2759 | if (rn == 31) { | |
2760 | gen_check_sp_alignment(s); | |
2761 | } | |
2762 | ||
3a471103 | 2763 | dirty_addr = read_cpu_reg_sp(s, rn, 1); |
4a08d475 | 2764 | if (!postindex) { |
3a471103 | 2765 | tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); |
4a08d475 | 2766 | } |
3a471103 | 2767 | clean_addr = clean_data_tbi(s, dirty_addr); |
4a08d475 PM |
2768 | |
2769 | if (is_vector) { | |
2770 | if (is_load) { | |
3a471103 | 2771 | do_fp_ld(s, rt, clean_addr, size); |
4a08d475 | 2772 | } else { |
3a471103 | 2773 | do_fp_st(s, rt, clean_addr, size); |
4a08d475 | 2774 | } |
3a471103 | 2775 | tcg_gen_addi_i64(clean_addr, clean_addr, 1 << size); |
4a08d475 | 2776 | if (is_load) { |
3a471103 | 2777 | do_fp_ld(s, rt2, clean_addr, size); |
4a08d475 | 2778 | } else { |
3a471103 | 2779 | do_fp_st(s, rt2, clean_addr, size); |
4a08d475 PM |
2780 | } |
2781 | } else { | |
3e4d91b9 | 2782 | TCGv_i64 tcg_rt = cpu_reg(s, rt); |
4a08d475 | 2783 | TCGv_i64 tcg_rt2 = cpu_reg(s, rt2); |
3e4d91b9 | 2784 | |
4a08d475 | 2785 | if (is_load) { |
3e4d91b9 RH |
2786 | TCGv_i64 tmp = tcg_temp_new_i64(); |
2787 | ||
2788 | /* Do not modify tcg_rt before recognizing any exception | |
2789 | * from the second load. | |
2790 | */ | |
3a471103 | 2791 | do_gpr_ld(s, tmp, clean_addr, size, is_signed, false, |
3e4d91b9 | 2792 | false, 0, false, false); |
3a471103 RH |
2793 | tcg_gen_addi_i64(clean_addr, clean_addr, 1 << size); |
2794 | do_gpr_ld(s, tcg_rt2, clean_addr, size, is_signed, false, | |
aaa1f954 | 2795 | false, 0, false, false); |
3e4d91b9 RH |
2796 | |
2797 | tcg_gen_mov_i64(tcg_rt, tmp); | |
2798 | tcg_temp_free_i64(tmp); | |
4a08d475 | 2799 | } else { |
3a471103 | 2800 | do_gpr_st(s, tcg_rt, clean_addr, size, |
3e4d91b9 | 2801 | false, 0, false, false); |
3a471103 RH |
2802 | tcg_gen_addi_i64(clean_addr, clean_addr, 1 << size); |
2803 | do_gpr_st(s, tcg_rt2, clean_addr, size, | |
aaa1f954 | 2804 | false, 0, false, false); |
4a08d475 PM |
2805 | } |
2806 | } | |
2807 | ||
2808 | if (wback) { | |
2809 | if (postindex) { | |
3a471103 | 2810 | tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); |
4a08d475 | 2811 | } |
3a471103 | 2812 | tcg_gen_mov_i64(cpu_reg_sp(s, rn), dirty_addr); |
4a08d475 | 2813 | } |
ad7ee8a2 CF |
2814 | } |
2815 | ||
a5e94a9d | 2816 | /* |
4ce31af4 PM |
2817 | * Load/store (immediate post-indexed) |
2818 | * Load/store (immediate pre-indexed) | |
2819 | * Load/store (unscaled immediate) | |
a5e94a9d AB |
2820 | * |
2821 | * 31 30 29 27 26 25 24 23 22 21 20 12 11 10 9 5 4 0 | |
2822 | * +----+-------+---+-----+-----+---+--------+-----+------+------+ | |
2823 | * |size| 1 1 1 | V | 0 0 | opc | 0 | imm9 | idx | Rn | Rt | | |
2824 | * +----+-------+---+-----+-----+---+--------+-----+------+------+ | |
2825 | * | |
2826 | * idx = 01 -> post-indexed, 11 pre-indexed, 00 unscaled imm. (no writeback) | |
60510aed | 2827 | 10 -> unprivileged |
a5e94a9d AB |
2828 | * V = 0 -> non-vector |
2829 | * size: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64bit | |
2830 | * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32 | |
2831 | */ | |
cd694521 EI |
2832 | static void disas_ldst_reg_imm9(DisasContext *s, uint32_t insn, |
2833 | int opc, | |
2834 | int size, | |
2835 | int rt, | |
2836 | bool is_vector) | |
a5e94a9d | 2837 | { |
a5e94a9d AB |
2838 | int rn = extract32(insn, 5, 5); |
2839 | int imm9 = sextract32(insn, 12, 9); | |
a5e94a9d AB |
2840 | int idx = extract32(insn, 10, 2); |
2841 | bool is_signed = false; | |
2842 | bool is_store = false; | |
2843 | bool is_extended = false; | |
60510aed | 2844 | bool is_unpriv = (idx == 2); |
aaa1f954 | 2845 | bool iss_valid = !is_vector; |
a5e94a9d AB |
2846 | bool post_index; |
2847 | bool writeback; | |
2848 | ||
3a471103 | 2849 | TCGv_i64 clean_addr, dirty_addr; |
a5e94a9d AB |
2850 | |
2851 | if (is_vector) { | |
2852 | size |= (opc & 2) << 1; | |
60510aed | 2853 | if (size > 4 || is_unpriv) { |
a5e94a9d AB |
2854 | unallocated_encoding(s); |
2855 | return; | |
2856 | } | |
2857 | is_store = ((opc & 1) == 0); | |
8c6afa6a PM |
2858 | if (!fp_access_check(s)) { |
2859 | return; | |
2860 | } | |
a5e94a9d AB |
2861 | } else { |
2862 | if (size == 3 && opc == 2) { | |
2863 | /* PRFM - prefetch */ | |
a80c4256 | 2864 | if (idx != 0) { |
60510aed PM |
2865 | unallocated_encoding(s); |
2866 | return; | |
2867 | } | |
a5e94a9d AB |
2868 | return; |
2869 | } | |
2870 | if (opc == 3 && size > 1) { | |
2871 | unallocated_encoding(s); | |
2872 | return; | |
2873 | } | |
2874 | is_store = (opc == 0); | |
026a19c3 EI |
2875 | is_signed = extract32(opc, 1, 1); |
2876 | is_extended = (size < 3) && extract32(opc, 0, 1); | |
a5e94a9d AB |
2877 | } |
2878 | ||
2879 | switch (idx) { | |
2880 | case 0: | |
60510aed | 2881 | case 2: |
a5e94a9d AB |
2882 | post_index = false; |
2883 | writeback = false; | |
2884 | break; | |
2885 | case 1: | |
2886 | post_index = true; | |
2887 | writeback = true; | |
2888 | break; | |
2889 | case 3: | |
2890 | post_index = false; | |
2891 | writeback = true; | |
2892 | break; | |
5ca66278 EC |
2893 | default: |
2894 | g_assert_not_reached(); | |
a5e94a9d AB |
2895 | } |
2896 | ||
2897 | if (rn == 31) { | |
2898 | gen_check_sp_alignment(s); | |
2899 | } | |
a5e94a9d | 2900 | |
3a471103 | 2901 | dirty_addr = read_cpu_reg_sp(s, rn, 1); |
a5e94a9d | 2902 | if (!post_index) { |
3a471103 | 2903 | tcg_gen_addi_i64(dirty_addr, dirty_addr, imm9); |
a5e94a9d | 2904 | } |
3a471103 | 2905 | clean_addr = clean_data_tbi(s, dirty_addr); |
a5e94a9d AB |
2906 | |
2907 | if (is_vector) { | |
2908 | if (is_store) { | |
3a471103 | 2909 | do_fp_st(s, rt, clean_addr, size); |
a5e94a9d | 2910 | } else { |
3a471103 | 2911 | do_fp_ld(s, rt, clean_addr, size); |
a5e94a9d AB |
2912 | } |
2913 | } else { | |
2914 | TCGv_i64 tcg_rt = cpu_reg(s, rt); | |
579d21cc | 2915 | int memidx = is_unpriv ? get_a64_user_mem_index(s) : get_mem_index(s); |
aaa1f954 | 2916 | bool iss_sf = disas_ldst_compute_iss_sf(size, is_signed, opc); |
60510aed | 2917 | |
a5e94a9d | 2918 | if (is_store) { |
3a471103 | 2919 | do_gpr_st_memidx(s, tcg_rt, clean_addr, size, memidx, |
aaa1f954 | 2920 | iss_valid, rt, iss_sf, false); |
a5e94a9d | 2921 | } else { |
3a471103 | 2922 | do_gpr_ld_memidx(s, tcg_rt, clean_addr, size, |
aaa1f954 EI |
2923 | is_signed, is_extended, memidx, |
2924 | iss_valid, rt, iss_sf, false); | |
a5e94a9d AB |
2925 | } |
2926 | } | |
2927 | ||
2928 | if (writeback) { | |
2929 | TCGv_i64 tcg_rn = cpu_reg_sp(s, rn); | |
2930 | if (post_index) { | |
3a471103 | 2931 | tcg_gen_addi_i64(dirty_addr, dirty_addr, imm9); |
a5e94a9d | 2932 | } |
3a471103 | 2933 | tcg_gen_mov_i64(tcg_rn, dirty_addr); |
a5e94a9d AB |
2934 | } |
2935 | } | |
2936 | ||
229b7a05 | 2937 | /* |
4ce31af4 | 2938 | * Load/store (register offset) |
229b7a05 AB |
2939 | * |
2940 | * 31 30 29 27 26 25 24 23 22 21 20 16 15 13 12 11 10 9 5 4 0 | |
2941 | * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+ | |
2942 | * |size| 1 1 1 | V | 0 0 | opc | 1 | Rm | opt | S| 1 0 | Rn | Rt | | |
2943 | * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+ | |
2944 | * | |
2945 | * For non-vector: | |
2946 | * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit | |
2947 | * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32 | |
2948 | * For vector: | |
2949 | * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated | |
2950 | * opc<0>: 0 -> store, 1 -> load | |
2951 | * V: 1 -> vector/simd | |
2952 | * opt: extend encoding (see DecodeRegExtend) | |
2953 | * S: if S=1 then scale (essentially index by sizeof(size)) | |
2954 | * Rt: register to transfer into/out of | |
2955 | * Rn: address register or SP for base | |
2956 | * Rm: offset register or ZR for offset | |
2957 | */ | |
cd694521 EI |
2958 | static void disas_ldst_reg_roffset(DisasContext *s, uint32_t insn, |
2959 | int opc, | |
2960 | int size, | |
2961 | int rt, | |
2962 | bool is_vector) | |
229b7a05 | 2963 | { |
229b7a05 AB |
2964 | int rn = extract32(insn, 5, 5); |
2965 | int shift = extract32(insn, 12, 1); | |
2966 | int rm = extract32(insn, 16, 5); | |
229b7a05 | 2967 | int opt = extract32(insn, 13, 3); |
229b7a05 AB |
2968 | bool is_signed = false; |
2969 | bool is_store = false; | |
2970 | bool is_extended = false; | |
229b7a05 | 2971 | |
3a471103 | 2972 | TCGv_i64 tcg_rm, clean_addr, dirty_addr; |
229b7a05 AB |
2973 | |
2974 | if (extract32(opt, 1, 1) == 0) { | |
2975 | unallocated_encoding(s); | |
2976 | return; | |
2977 | } | |
2978 | ||
2979 | if (is_vector) { | |
2980 | size |= (opc & 2) << 1; | |
2981 | if (size > 4) { | |
2982 | unallocated_encoding(s); | |
2983 | return; | |
2984 | } | |
2985 | is_store = !extract32(opc, 0, 1); | |
8c6afa6a PM |
2986 | if (!fp_access_check(s)) { |
2987 | return; | |
2988 | } | |
229b7a05 AB |
2989 | } else { |
2990 | if (size == 3 && opc == 2) { | |
2991 | /* PRFM - prefetch */ | |
2992 | return; | |
2993 | } | |
2994 | if (opc == 3 && size > 1) { | |
2995 | unallocated_encoding(s); | |
2996 | return; | |
2997 | } | |
2998 | is_store = (opc == 0); | |
2999 | is_signed = extract32(opc, 1, 1); | |
3000 | is_extended = (size < 3) && extract32(opc, 0, 1); | |
3001 | } | |
3002 | ||
3003 | if (rn == 31) { | |
3004 | gen_check_sp_alignment(s); | |
3005 | } | |
3a471103 | 3006 | dirty_addr = read_cpu_reg_sp(s, rn, 1); |
229b7a05 AB |
3007 | |
3008 | tcg_rm = read_cpu_reg(s, rm, 1); | |
3009 | ext_and_shift_reg(tcg_rm, tcg_rm, opt, shift ? size : 0); | |
3010 | ||
3a471103 RH |
3011 | tcg_gen_add_i64(dirty_addr, dirty_addr, tcg_rm); |
3012 | clean_addr = clean_data_tbi(s, dirty_addr); | |
229b7a05 AB |
3013 | |
3014 | if (is_vector) { | |
3015 | if (is_store) { | |
3a471103 | 3016 | do_fp_st(s, rt, clean_addr, size); |
229b7a05 | 3017 | } else { |
3a471103 | 3018 | do_fp_ld(s, rt, clean_addr, size); |
229b7a05 AB |
3019 | } |
3020 | } else { | |
3021 | TCGv_i64 tcg_rt = cpu_reg(s, rt); | |
aaa1f954 | 3022 | bool iss_sf = disas_ldst_compute_iss_sf(size, is_signed, opc); |
229b7a05 | 3023 | if (is_store) { |
3a471103 | 3024 | do_gpr_st(s, tcg_rt, clean_addr, size, |
aaa1f954 | 3025 | true, rt, iss_sf, false); |
229b7a05 | 3026 | } else { |
3a471103 | 3027 | do_gpr_ld(s, tcg_rt, clean_addr, size, |
aaa1f954 EI |
3028 | is_signed, is_extended, |
3029 | true, rt, iss_sf, false); | |
229b7a05 AB |
3030 | } |
3031 | } | |
3032 | } | |
3033 | ||
d5612f10 | 3034 | /* |
4ce31af4 | 3035 | * Load/store (unsigned immediate) |
d5612f10 AB |
3036 | * |
3037 | * 31 30 29 27 26 25 24 23 22 21 10 9 5 | |
3038 | * +----+-------+---+-----+-----+------------+-------+------+ | |
3039 | * |size| 1 1 1 | V | 0 1 | opc | imm12 | Rn | Rt | | |
3040 | * +----+-------+---+-----+-----+------------+-------+------+ | |
3041 | * | |
3042 | * For non-vector: | |
3043 | * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit | |
3044 | * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32 | |
3045 | * For vector: | |
3046 | * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated | |
3047 | * opc<0>: 0 -> store, 1 -> load | |
3048 | * Rn: base address register (inc SP) | |
3049 | * Rt: target register | |
3050 | */ | |
cd694521 EI |
3051 | static void disas_ldst_reg_unsigned_imm(DisasContext *s, uint32_t insn, |
3052 | int opc, | |
3053 | int size, | |
3054 | int rt, | |
3055 | bool is_vector) | |
d5612f10 | 3056 | { |
d5612f10 AB |
3057 | int rn = extract32(insn, 5, 5); |
3058 | unsigned int imm12 = extract32(insn, 10, 12); | |
d5612f10 AB |
3059 | unsigned int offset; |
3060 | ||
3a471103 | 3061 | TCGv_i64 clean_addr, dirty_addr; |
d5612f10 AB |
3062 | |
3063 | bool is_store; | |
3064 | bool is_signed = false; | |
3065 | bool is_extended = false; | |
3066 | ||
3067 | if (is_vector) { | |
3068 | size |= (opc & 2) << 1; | |
3069 | if (size > 4) { | |
3070 | unallocated_encoding(s); | |
3071 | return; | |
3072 | } | |
3073 | is_store = !extract32(opc, 0, 1); | |
8c6afa6a PM |
3074 | if (!fp_access_check(s)) { |
3075 | return; | |
3076 | } | |
d5612f10 AB |
3077 | } else { |
3078 | if (size == 3 && opc == 2) { | |
3079 | /* PRFM - prefetch */ | |
3080 | return; | |
3081 | } | |
3082 | if (opc == 3 && size > 1) { | |
3083 | unallocated_encoding(s); | |
3084 | return; | |
3085 | } | |
3086 | is_store = (opc == 0); | |
3087 | is_signed = extract32(opc, 1, 1); | |
3088 | is_extended = (size < 3) && extract32(opc, 0, 1); | |
3089 | } | |
3090 | ||
3091 | if (rn == 31) { | |
3092 | gen_check_sp_alignment(s); | |
3093 | } | |
3a471103 | 3094 | dirty_addr = read_cpu_reg_sp(s, rn, 1); |
d5612f10 | 3095 | offset = imm12 << size; |
3a471103 RH |
3096 | tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); |
3097 | clean_addr = clean_data_tbi(s, dirty_addr); | |
d5612f10 AB |
3098 | |
3099 | if (is_vector) { | |
3100 | if (is_store) { | |
3a471103 | 3101 | do_fp_st(s, rt, clean_addr, size); |
d5612f10 | 3102 | } else { |
3a471103 | 3103 | do_fp_ld(s, rt, clean_addr, size); |
d5612f10 AB |
3104 | } |
3105 | } else { | |
3106 | TCGv_i64 tcg_rt = cpu_reg(s, rt); | |
aaa1f954 | 3107 | bool iss_sf = disas_ldst_compute_iss_sf(size, is_signed, opc); |
d5612f10 | 3108 | if (is_store) { |
3a471103 | 3109 | do_gpr_st(s, tcg_rt, clean_addr, size, |
aaa1f954 | 3110 | true, rt, iss_sf, false); |
d5612f10 | 3111 | } else { |
3a471103 | 3112 | do_gpr_ld(s, tcg_rt, clean_addr, size, is_signed, is_extended, |
aaa1f954 | 3113 | true, rt, iss_sf, false); |
d5612f10 AB |
3114 | } |
3115 | } | |
3116 | } | |
3117 | ||
68412d2e RH |
3118 | /* Atomic memory operations |
3119 | * | |
3120 | * 31 30 27 26 24 22 21 16 15 12 10 5 0 | |
3121 | * +------+-------+---+-----+-----+---+----+----+-----+-----+----+-----+ | |
3122 | * | size | 1 1 1 | V | 0 0 | A R | 1 | Rs | o3 | opc | 0 0 | Rn | Rt | | |
3123 | * +------+-------+---+-----+-----+--------+----+-----+-----+----+-----+ | |
3124 | * | |
3125 | * Rt: the result register | |
3126 | * Rn: base address or SP | |
3127 | * Rs: the source register for the operation | |
3128 | * V: vector flag (always 0 as of v8.3) | |
3129 | * A: acquire flag | |
3130 | * R: release flag | |
3131 | */ | |
3132 | static void disas_ldst_atomic(DisasContext *s, uint32_t insn, | |
3133 | int size, int rt, bool is_vector) | |
3134 | { | |
3135 | int rs = extract32(insn, 16, 5); | |
3136 | int rn = extract32(insn, 5, 5); | |
3137 | int o3_opc = extract32(insn, 12, 4); | |
2677cf9f PM |
3138 | bool r = extract32(insn, 22, 1); |
3139 | bool a = extract32(insn, 23, 1); | |
3a471103 | 3140 | TCGv_i64 tcg_rs, clean_addr; |
74608ea4 | 3141 | AtomicThreeOpFn *fn; |
68412d2e | 3142 | |
962fcbf2 | 3143 | if (is_vector || !dc_isar_feature(aa64_atomics, s)) { |
68412d2e RH |
3144 | unallocated_encoding(s); |
3145 | return; | |
3146 | } | |
3147 | switch (o3_opc) { | |
3148 | case 000: /* LDADD */ | |
74608ea4 RH |
3149 | fn = tcg_gen_atomic_fetch_add_i64; |
3150 | break; | |
68412d2e | 3151 | case 001: /* LDCLR */ |
74608ea4 RH |
3152 | fn = tcg_gen_atomic_fetch_and_i64; |
3153 | break; | |
68412d2e | 3154 | case 002: /* LDEOR */ |
74608ea4 RH |
3155 | fn = tcg_gen_atomic_fetch_xor_i64; |
3156 | break; | |
68412d2e | 3157 | case 003: /* LDSET */ |
74608ea4 RH |
3158 | fn = tcg_gen_atomic_fetch_or_i64; |
3159 | break; | |
68412d2e | 3160 | case 004: /* LDSMAX */ |
74608ea4 RH |
3161 | fn = tcg_gen_atomic_fetch_smax_i64; |
3162 | break; | |
68412d2e | 3163 | case 005: /* LDSMIN */ |
74608ea4 RH |
3164 | fn = tcg_gen_atomic_fetch_smin_i64; |
3165 | break; | |
68412d2e | 3166 | case 006: /* LDUMAX */ |
74608ea4 RH |
3167 | fn = tcg_gen_atomic_fetch_umax_i64; |
3168 | break; | |
68412d2e | 3169 | case 007: /* LDUMIN */ |
74608ea4 RH |
3170 | fn = tcg_gen_atomic_fetch_umin_i64; |
3171 | break; | |
68412d2e | 3172 | case 010: /* SWP */ |
74608ea4 RH |
3173 | fn = tcg_gen_atomic_xchg_i64; |
3174 | break; | |
2677cf9f PM |
3175 | case 014: /* LDAPR, LDAPRH, LDAPRB */ |
3176 | if (!dc_isar_feature(aa64_rcpc_8_3, s) || | |
3177 | rs != 31 || a != 1 || r != 0) { | |
3178 | unallocated_encoding(s); | |
3179 | return; | |
3180 | } | |
3181 | break; | |
68412d2e RH |
3182 | default: |
3183 | unallocated_encoding(s); | |
3184 | return; | |
3185 | } | |
68412d2e | 3186 | |
74608ea4 RH |
3187 | if (rn == 31) { |
3188 | gen_check_sp_alignment(s); | |
3189 | } | |
3a471103 | 3190 | clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn)); |
2677cf9f PM |
3191 | |
3192 | if (o3_opc == 014) { | |
3193 | /* | |
3194 | * LDAPR* are a special case because they are a simple load, not a | |
3195 | * fetch-and-do-something op. | |
3196 | * The architectural consistency requirements here are weaker than | |
3197 | * full load-acquire (we only need "load-acquire processor consistent"), | |
3198 | * but we choose to implement them as full LDAQ. | |
3199 | */ | |
3200 | do_gpr_ld(s, cpu_reg(s, rt), clean_addr, size, false, false, | |
3201 | true, rt, disas_ldst_compute_iss_sf(size, false, 0), true); | |
3202 | tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); | |
3203 | return; | |
3204 | } | |
3205 | ||
74608ea4 RH |
3206 | tcg_rs = read_cpu_reg(s, rs, true); |
3207 | ||
3208 | if (o3_opc == 1) { /* LDCLR */ | |
3209 | tcg_gen_not_i64(tcg_rs, tcg_rs); | |
3210 | } | |
3211 | ||
3212 | /* The tcg atomic primitives are all full barriers. Therefore we | |
3213 | * can ignore the Acquire and Release bits of this instruction. | |
3214 | */ | |
3a471103 | 3215 | fn(cpu_reg(s, rt), clean_addr, tcg_rs, get_mem_index(s), |
74608ea4 | 3216 | s->be_data | size | MO_ALIGN); |
68412d2e RH |
3217 | } |
3218 | ||
bd889f48 RH |
3219 | /* |
3220 | * PAC memory operations | |
3221 | * | |
3222 | * 31 30 27 26 24 22 21 12 11 10 5 0 | |
3223 | * +------+-------+---+-----+-----+---+--------+---+---+----+-----+ | |
3224 | * | size | 1 1 1 | V | 0 0 | M S | 1 | imm9 | W | 1 | Rn | Rt | | |
3225 | * +------+-------+---+-----+-----+---+--------+---+---+----+-----+ | |
3226 | * | |
3227 | * Rt: the result register | |
3228 | * Rn: base address or SP | |
3229 | * V: vector flag (always 0 as of v8.3) | |
3230 | * M: clear for key DA, set for key DB | |
3231 | * W: pre-indexing flag | |
3232 | * S: sign for imm9. | |
3233 | */ | |
3234 | static void disas_ldst_pac(DisasContext *s, uint32_t insn, | |
3235 | int size, int rt, bool is_vector) | |
3236 | { | |
3237 | int rn = extract32(insn, 5, 5); | |
3238 | bool is_wback = extract32(insn, 11, 1); | |
3239 | bool use_key_a = !extract32(insn, 23, 1); | |
3240 | int offset; | |
3a471103 | 3241 | TCGv_i64 clean_addr, dirty_addr, tcg_rt; |
bd889f48 RH |
3242 | |
3243 | if (size != 3 || is_vector || !dc_isar_feature(aa64_pauth, s)) { | |
3244 | unallocated_encoding(s); | |
3245 | return; | |
3246 | } | |
3247 | ||
3248 | if (rn == 31) { | |
3249 | gen_check_sp_alignment(s); | |
3250 | } | |
3a471103 | 3251 | dirty_addr = read_cpu_reg_sp(s, rn, 1); |
bd889f48 RH |
3252 | |
3253 | if (s->pauth_active) { | |
3254 | if (use_key_a) { | |
3a471103 | 3255 | gen_helper_autda(dirty_addr, cpu_env, dirty_addr, cpu_X[31]); |
bd889f48 | 3256 | } else { |
3a471103 | 3257 | gen_helper_autdb(dirty_addr, cpu_env, dirty_addr, cpu_X[31]); |
bd889f48 RH |
3258 | } |
3259 | } | |
3260 | ||
3261 | /* Form the 10-bit signed, scaled offset. */ | |
3262 | offset = (extract32(insn, 22, 1) << 9) | extract32(insn, 12, 9); | |
3263 | offset = sextract32(offset << size, 0, 10 + size); | |
3a471103 | 3264 | tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); |
bd889f48 | 3265 | |
3a471103 RH |
3266 | /* Note that "clean" and "dirty" here refer to TBI not PAC. */ |
3267 | clean_addr = clean_data_tbi(s, dirty_addr); | |
bd889f48 | 3268 | |
3a471103 RH |
3269 | tcg_rt = cpu_reg(s, rt); |
3270 | do_gpr_ld(s, tcg_rt, clean_addr, size, /* is_signed */ false, | |
bd889f48 RH |
3271 | /* extend */ false, /* iss_valid */ !is_wback, |
3272 | /* iss_srt */ rt, /* iss_sf */ true, /* iss_ar */ false); | |
3273 | ||
3274 | if (is_wback) { | |
3a471103 | 3275 | tcg_gen_mov_i64(cpu_reg_sp(s, rn), dirty_addr); |
bd889f48 RH |
3276 | } |
3277 | } | |
3278 | ||
a1229109 PM |
3279 | /* |
3280 | * LDAPR/STLR (unscaled immediate) | |
3281 | * | |
3282 | * 31 30 24 22 21 12 10 5 0 | |
3283 | * +------+-------------+-----+---+--------+-----+----+-----+ | |
3284 | * | size | 0 1 1 0 0 1 | opc | 0 | imm9 | 0 0 | Rn | Rt | | |
3285 | * +------+-------------+-----+---+--------+-----+----+-----+ | |
3286 | * | |
3287 | * Rt: source or destination register | |
3288 | * Rn: base register | |
3289 | * imm9: unscaled immediate offset | |
3290 | * opc: 00: STLUR*, 01/10/11: various LDAPUR* | |
3291 | * size: size of load/store | |
3292 | */ | |
3293 | static void disas_ldst_ldapr_stlr(DisasContext *s, uint32_t insn) | |
3294 | { | |
3295 | int rt = extract32(insn, 0, 5); | |
3296 | int rn = extract32(insn, 5, 5); | |
3297 | int offset = sextract32(insn, 12, 9); | |
3298 | int opc = extract32(insn, 22, 2); | |
3299 | int size = extract32(insn, 30, 2); | |
3300 | TCGv_i64 clean_addr, dirty_addr; | |
3301 | bool is_store = false; | |
3302 | bool is_signed = false; | |
3303 | bool extend = false; | |
3304 | bool iss_sf; | |
3305 | ||
3306 | if (!dc_isar_feature(aa64_rcpc_8_4, s)) { | |
3307 | unallocated_encoding(s); | |
3308 | return; | |
3309 | } | |
3310 | ||
3311 | switch (opc) { | |
3312 | case 0: /* STLURB */ | |
3313 | is_store = true; | |
3314 | break; | |
3315 | case 1: /* LDAPUR* */ | |
3316 | break; | |
3317 | case 2: /* LDAPURS* 64-bit variant */ | |
3318 | if (size == 3) { | |
3319 | unallocated_encoding(s); | |
3320 | return; | |
3321 | } | |
3322 | is_signed = true; | |
3323 | break; | |
3324 | case 3: /* LDAPURS* 32-bit variant */ | |
3325 | if (size > 1) { | |
3326 | unallocated_encoding(s); | |
3327 | return; | |
3328 | } | |
3329 | is_signed = true; | |
3330 | extend = true; /* zero-extend 32->64 after signed load */ | |
3331 | break; | |
3332 | default: | |
3333 | g_assert_not_reached(); | |
3334 | } | |
3335 | ||
3336 | iss_sf = disas_ldst_compute_iss_sf(size, is_signed, opc); | |
3337 | ||
3338 | if (rn == 31) { | |
3339 | gen_check_sp_alignment(s); | |
3340 | } | |
3341 | ||
3342 | dirty_addr = read_cpu_reg_sp(s, rn, 1); | |
3343 | tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); | |
3344 | clean_addr = clean_data_tbi(s, dirty_addr); | |
3345 | ||
3346 | if (is_store) { | |
3347 | /* Store-Release semantics */ | |
3348 | tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); | |
3349 | do_gpr_st(s, cpu_reg(s, rt), clean_addr, size, true, rt, iss_sf, true); | |
3350 | } else { | |
3351 | /* | |
3352 | * Load-AcquirePC semantics; we implement as the slightly more | |
3353 | * restrictive Load-Acquire. | |
3354 | */ | |
3355 | do_gpr_ld(s, cpu_reg(s, rt), clean_addr, size, is_signed, extend, | |
3356 | true, rt, iss_sf, true); | |
3357 | tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); | |
3358 | } | |
3359 | } | |
3360 | ||
ad7ee8a2 CF |
3361 | /* Load/store register (all forms) */ |
3362 | static void disas_ldst_reg(DisasContext *s, uint32_t insn) | |
3363 | { | |
cd694521 EI |
3364 | int rt = extract32(insn, 0, 5); |
3365 | int opc = extract32(insn, 22, 2); | |
3366 | bool is_vector = extract32(insn, 26, 1); | |
3367 | int size = extract32(insn, 30, 2); | |
3368 | ||
d5612f10 AB |
3369 | switch (extract32(insn, 24, 2)) { |
3370 | case 0: | |
68412d2e | 3371 | if (extract32(insn, 21, 1) == 0) { |
60510aed PM |
3372 | /* Load/store register (unscaled immediate) |
3373 | * Load/store immediate pre/post-indexed | |
3374 | * Load/store register unprivileged | |
3375 | */ | |
cd694521 | 3376 | disas_ldst_reg_imm9(s, insn, opc, size, rt, is_vector); |
68412d2e RH |
3377 | return; |
3378 | } | |
3379 | switch (extract32(insn, 10, 2)) { | |
3380 | case 0: | |
3381 | disas_ldst_atomic(s, insn, size, rt, is_vector); | |
3382 | return; | |
3383 | case 2: | |
3384 | disas_ldst_reg_roffset(s, insn, opc, size, rt, is_vector); | |
3385 | return; | |
bd889f48 RH |
3386 | default: |
3387 | disas_ldst_pac(s, insn, size, rt, is_vector); | |
3388 | return; | |
229b7a05 | 3389 | } |
d5612f10 AB |
3390 | break; |
3391 | case 1: | |
cd694521 | 3392 | disas_ldst_reg_unsigned_imm(s, insn, opc, size, rt, is_vector); |
68412d2e | 3393 | return; |
d5612f10 | 3394 | } |
68412d2e | 3395 | unallocated_encoding(s); |
ad7ee8a2 CF |
3396 | } |
3397 | ||
4ce31af4 | 3398 | /* AdvSIMD load/store multiple structures |
72430bf5 AB |
3399 | * |
3400 | * 31 30 29 23 22 21 16 15 12 11 10 9 5 4 0 | |
3401 | * +---+---+---------------+---+-------------+--------+------+------+------+ | |
3402 | * | 0 | Q | 0 0 1 1 0 0 0 | L | 0 0 0 0 0 0 | opcode | size | Rn | Rt | | |
3403 | * +---+---+---------------+---+-------------+--------+------+------+------+ | |
3404 | * | |
4ce31af4 | 3405 | * AdvSIMD load/store multiple structures (post-indexed) |
72430bf5 AB |
3406 | * |
3407 | * 31 30 29 23 22 21 20 16 15 12 11 10 9 5 4 0 | |
3408 | * +---+---+---------------+---+---+---------+--------+------+------+------+ | |
3409 | * | 0 | Q | 0 0 1 1 0 0 1 | L | 0 | Rm | opcode | size | Rn | Rt | | |
3410 | * +---+---+---------------+---+---+---------+--------+------+------+------+ | |
3411 | * | |
3412 | * Rt: first (or only) SIMD&FP register to be transferred | |
3413 | * Rn: base address or SP | |
3414 | * Rm (post-index only): post-index register (when !31) or size dependent #imm | |
3415 | */ | |
ad7ee8a2 CF |
3416 | static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn) |
3417 | { | |
72430bf5 AB |
3418 | int rt = extract32(insn, 0, 5); |
3419 | int rn = extract32(insn, 5, 5); | |
e1f22081 | 3420 | int rm = extract32(insn, 16, 5); |
72430bf5 AB |
3421 | int size = extract32(insn, 10, 2); |
3422 | int opcode = extract32(insn, 12, 4); | |
3423 | bool is_store = !extract32(insn, 22, 1); | |
3424 | bool is_postidx = extract32(insn, 23, 1); | |
3425 | bool is_q = extract32(insn, 30, 1); | |
3a471103 | 3426 | TCGv_i64 clean_addr, tcg_rn, tcg_ebytes; |
14776ab5 | 3427 | MemOp endian = s->be_data; |
72430bf5 | 3428 | |
87f9a7f0 RH |
3429 | int ebytes; /* bytes per element */ |
3430 | int elements; /* elements per vector */ | |
72430bf5 AB |
3431 | int rpt; /* num iterations */ |
3432 | int selem; /* structure elements */ | |
3433 | int r; | |
3434 | ||
3435 | if (extract32(insn, 31, 1) || extract32(insn, 21, 1)) { | |
3436 | unallocated_encoding(s); | |
3437 | return; | |
3438 | } | |
3439 | ||
e1f22081 PM |
3440 | if (!is_postidx && rm != 0) { |
3441 | unallocated_encoding(s); | |
3442 | return; | |
3443 | } | |
3444 | ||
72430bf5 AB |
3445 | /* From the shared decode logic */ |
3446 | switch (opcode) { | |
3447 | case 0x0: | |
3448 | rpt = 1; | |
3449 | selem = 4; | |
3450 | break; | |
3451 | case 0x2: | |
3452 | rpt = 4; | |
3453 | selem = 1; | |
3454 | break; | |
3455 | case 0x4: | |
3456 | rpt = 1; | |
3457 | selem = 3; | |
3458 | break; | |
3459 | case 0x6: | |
3460 | rpt = 3; | |
3461 | selem = 1; | |
3462 | break; | |
3463 | case 0x7: | |
3464 | rpt = 1; | |
3465 | selem = 1; | |
3466 | break; | |
3467 | case 0x8: | |
3468 | rpt = 1; | |
3469 | selem = 2; | |
3470 | break; | |
3471 | case 0xa: | |
3472 | rpt = 2; | |
3473 | selem = 1; | |
3474 | break; | |
3475 | default: | |
3476 | unallocated_encoding(s); | |
3477 | return; | |
3478 | } | |
3479 | ||
3480 | if (size == 3 && !is_q && selem != 1) { | |
3481 | /* reserved */ | |
3482 | unallocated_encoding(s); | |
3483 | return; | |
3484 | } | |
3485 | ||
8c6afa6a PM |
3486 | if (!fp_access_check(s)) { |
3487 | return; | |
3488 | } | |
3489 | ||
72430bf5 AB |
3490 | if (rn == 31) { |
3491 | gen_check_sp_alignment(s); | |
3492 | } | |
3493 | ||
87f9a7f0 RH |
3494 | /* For our purposes, bytes are always little-endian. */ |
3495 | if (size == 0) { | |
3496 | endian = MO_LE; | |
3497 | } | |
3498 | ||
3499 | /* Consecutive little-endian elements from a single register | |
3500 | * can be promoted to a larger little-endian operation. | |
3501 | */ | |
3502 | if (selem == 1 && endian == MO_LE) { | |
3503 | size = 3; | |
3504 | } | |
3505 | ebytes = 1 << size; | |
3506 | elements = (is_q ? 16 : 8) / ebytes; | |
3507 | ||
72430bf5 | 3508 | tcg_rn = cpu_reg_sp(s, rn); |
3a471103 | 3509 | clean_addr = clean_data_tbi(s, tcg_rn); |
a7d8143a | 3510 | tcg_ebytes = tcg_const_i64(ebytes); |
72430bf5 AB |
3511 | |
3512 | for (r = 0; r < rpt; r++) { | |
3513 | int e; | |
3514 | for (e = 0; e < elements; e++) { | |
72430bf5 AB |
3515 | int xs; |
3516 | for (xs = 0; xs < selem; xs++) { | |
87f9a7f0 | 3517 | int tt = (rt + r + xs) % 32; |
72430bf5 | 3518 | if (is_store) { |
3a471103 | 3519 | do_vec_st(s, tt, e, clean_addr, size, endian); |
72430bf5 | 3520 | } else { |
3a471103 | 3521 | do_vec_ld(s, tt, e, clean_addr, size, endian); |
72430bf5 | 3522 | } |
3a471103 | 3523 | tcg_gen_add_i64(clean_addr, clean_addr, tcg_ebytes); |
72430bf5 AB |
3524 | } |
3525 | } | |
3526 | } | |
3a471103 | 3527 | tcg_temp_free_i64(tcg_ebytes); |
72430bf5 | 3528 | |
87f9a7f0 RH |
3529 | if (!is_store) { |
3530 | /* For non-quad operations, setting a slice of the low | |
3531 | * 64 bits of the register clears the high 64 bits (in | |
3532 | * the ARM ARM pseudocode this is implicit in the fact | |
3533 | * that 'rval' is a 64 bit wide variable). | |
3534 | * For quad operations, we might still need to zero the | |
3535 | * high bits of SVE. | |
3536 | */ | |
3537 | for (r = 0; r < rpt * selem; r++) { | |
3538 | int tt = (rt + r) % 32; | |
3539 | clear_vec_high(s, is_q, tt); | |
3540 | } | |
3541 | } | |
3542 | ||
72430bf5 | 3543 | if (is_postidx) { |
72430bf5 | 3544 | if (rm == 31) { |
3a471103 | 3545 | tcg_gen_addi_i64(tcg_rn, tcg_rn, rpt * elements * selem * ebytes); |
72430bf5 AB |
3546 | } else { |
3547 | tcg_gen_add_i64(tcg_rn, tcg_rn, cpu_reg(s, rm)); | |
3548 | } | |
3549 | } | |
ad7ee8a2 CF |
3550 | } |
3551 | ||
4ce31af4 | 3552 | /* AdvSIMD load/store single structure |
df54e47d PM |
3553 | * |
3554 | * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0 | |
3555 | * +---+---+---------------+-----+-----------+-----+---+------+------+------+ | |
3556 | * | 0 | Q | 0 0 1 1 0 1 0 | L R | 0 0 0 0 0 | opc | S | size | Rn | Rt | | |
3557 | * +---+---+---------------+-----+-----------+-----+---+------+------+------+ | |
3558 | * | |
4ce31af4 | 3559 | * AdvSIMD load/store single structure (post-indexed) |
df54e47d PM |
3560 | * |
3561 | * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0 | |
3562 | * +---+---+---------------+-----+-----------+-----+---+------+------+------+ | |
3563 | * | 0 | Q | 0 0 1 1 0 1 1 | L R | Rm | opc | S | size | Rn | Rt | | |
3564 | * +---+---+---------------+-----+-----------+-----+---+------+------+------+ | |
3565 | * | |
3566 | * Rt: first (or only) SIMD&FP register to be transferred | |
3567 | * Rn: base address or SP | |
3568 | * Rm (post-index only): post-index register (when !31) or size dependent #imm | |
3569 | * index = encoded in Q:S:size dependent on size | |
3570 | * | |
3571 | * lane_size = encoded in R, opc | |
3572 | * transfer width = encoded in opc, S, size | |
3573 | */ | |
ad7ee8a2 CF |
3574 | static void disas_ldst_single_struct(DisasContext *s, uint32_t insn) |
3575 | { | |
df54e47d PM |
3576 | int rt = extract32(insn, 0, 5); |
3577 | int rn = extract32(insn, 5, 5); | |
9c72b68a | 3578 | int rm = extract32(insn, 16, 5); |
df54e47d PM |
3579 | int size = extract32(insn, 10, 2); |
3580 | int S = extract32(insn, 12, 1); | |
3581 | int opc = extract32(insn, 13, 3); | |
3582 | int R = extract32(insn, 21, 1); | |
3583 | int is_load = extract32(insn, 22, 1); | |
3584 | int is_postidx = extract32(insn, 23, 1); | |
3585 | int is_q = extract32(insn, 30, 1); | |
3586 | ||
3587 | int scale = extract32(opc, 1, 2); | |
3588 | int selem = (extract32(opc, 0, 1) << 1 | R) + 1; | |
3589 | bool replicate = false; | |
3590 | int index = is_q << 3 | S << 2 | size; | |
3591 | int ebytes, xs; | |
3a471103 | 3592 | TCGv_i64 clean_addr, tcg_rn, tcg_ebytes; |
df54e47d | 3593 | |
9c72b68a PM |
3594 | if (extract32(insn, 31, 1)) { |
3595 | unallocated_encoding(s); | |
3596 | return; | |
3597 | } | |
3598 | if (!is_postidx && rm != 0) { | |
3599 | unallocated_encoding(s); | |
3600 | return; | |
3601 | } | |
3602 | ||
df54e47d PM |
3603 | switch (scale) { |
3604 | case 3: | |
3605 | if (!is_load || S) { | |
3606 | unallocated_encoding(s); | |
3607 | return; | |
3608 | } | |
3609 | scale = size; | |
3610 | replicate = true; | |
3611 | break; | |
3612 | case 0: | |
3613 | break; | |
3614 | case 1: | |
3615 | if (extract32(size, 0, 1)) { | |
3616 | unallocated_encoding(s); | |
3617 | return; | |
3618 | } | |
3619 | index >>= 1; | |
3620 | break; | |
3621 | case 2: | |
3622 | if (extract32(size, 1, 1)) { | |
3623 | unallocated_encoding(s); | |
3624 | return; | |
3625 | } | |
3626 | if (!extract32(size, 0, 1)) { | |
3627 | index >>= 2; | |
3628 | } else { | |
3629 | if (S) { | |
3630 | unallocated_encoding(s); | |
3631 | return; | |
3632 | } | |
3633 | index >>= 3; | |
3634 | scale = 3; | |
3635 | } | |
3636 | break; | |
3637 | default: | |
3638 | g_assert_not_reached(); | |
3639 | } | |
3640 | ||
8c6afa6a PM |
3641 | if (!fp_access_check(s)) { |
3642 | return; | |
3643 | } | |
3644 | ||
df54e47d PM |
3645 | ebytes = 1 << scale; |
3646 | ||
3647 | if (rn == 31) { | |
3648 | gen_check_sp_alignment(s); | |
3649 | } | |
3650 | ||
3651 | tcg_rn = cpu_reg_sp(s, rn); | |
3a471103 | 3652 | clean_addr = clean_data_tbi(s, tcg_rn); |
a7d8143a | 3653 | tcg_ebytes = tcg_const_i64(ebytes); |
df54e47d PM |
3654 | |
3655 | for (xs = 0; xs < selem; xs++) { | |
3656 | if (replicate) { | |
3657 | /* Load and replicate to all elements */ | |
df54e47d PM |
3658 | TCGv_i64 tcg_tmp = tcg_temp_new_i64(); |
3659 | ||
3a471103 | 3660 | tcg_gen_qemu_ld_i64(tcg_tmp, clean_addr, |
aa6489da | 3661 | get_mem_index(s), s->be_data + scale); |
10e0b33c RH |
3662 | tcg_gen_gvec_dup_i64(scale, vec_full_reg_offset(s, rt), |
3663 | (is_q + 1) * 8, vec_full_reg_size(s), | |
3664 | tcg_tmp); | |
df54e47d PM |
3665 | tcg_temp_free_i64(tcg_tmp); |
3666 | } else { | |
3667 | /* Load/store one element per register */ | |
3668 | if (is_load) { | |
3a471103 | 3669 | do_vec_ld(s, rt, index, clean_addr, scale, s->be_data); |
df54e47d | 3670 | } else { |
3a471103 | 3671 | do_vec_st(s, rt, index, clean_addr, scale, s->be_data); |
df54e47d PM |
3672 | } |
3673 | } | |
3a471103 | 3674 | tcg_gen_add_i64(clean_addr, clean_addr, tcg_ebytes); |
df54e47d PM |
3675 | rt = (rt + 1) % 32; |
3676 | } | |
3a471103 | 3677 | tcg_temp_free_i64(tcg_ebytes); |
df54e47d PM |
3678 | |
3679 | if (is_postidx) { | |
df54e47d | 3680 | if (rm == 31) { |
3a471103 | 3681 | tcg_gen_addi_i64(tcg_rn, tcg_rn, selem * ebytes); |
df54e47d PM |
3682 | } else { |
3683 | tcg_gen_add_i64(tcg_rn, tcg_rn, cpu_reg(s, rm)); | |
3684 | } | |
3685 | } | |
ad7ee8a2 CF |
3686 | } |
3687 | ||
4ce31af4 | 3688 | /* Loads and stores */ |
ad7ee8a2 CF |
3689 | static void disas_ldst(DisasContext *s, uint32_t insn) |
3690 | { | |
3691 | switch (extract32(insn, 24, 6)) { | |
3692 | case 0x08: /* Load/store exclusive */ | |
3693 | disas_ldst_excl(s, insn); | |
3694 | break; | |
3695 | case 0x18: case 0x1c: /* Load register (literal) */ | |
3696 | disas_ld_lit(s, insn); | |
3697 | break; | |
3698 | case 0x28: case 0x29: | |
3699 | case 0x2c: case 0x2d: /* Load/store pair (all forms) */ | |
3700 | disas_ldst_pair(s, insn); | |
3701 | break; | |
3702 | case 0x38: case 0x39: | |
3703 | case 0x3c: case 0x3d: /* Load/store register (all forms) */ | |
3704 | disas_ldst_reg(s, insn); | |
3705 | break; | |
3706 | case 0x0c: /* AdvSIMD load/store multiple structures */ | |
3707 | disas_ldst_multiple_struct(s, insn); | |
3708 | break; | |
3709 | case 0x0d: /* AdvSIMD load/store single structure */ | |
3710 | disas_ldst_single_struct(s, insn); | |
3711 | break; | |
a1229109 PM |
3712 | case 0x19: /* LDAPR/STLR (unscaled immediate) */ |
3713 | if (extract32(insn, 10, 2) != 0 || | |
3714 | extract32(insn, 21, 1) != 0) { | |
3715 | unallocated_encoding(s); | |
3716 | break; | |
3717 | } | |
3718 | disas_ldst_ldapr_stlr(s, insn); | |
3719 | break; | |
ad7ee8a2 CF |
3720 | default: |
3721 | unallocated_encoding(s); | |
3722 | break; | |
3723 | } | |
3724 | } | |
3725 | ||
4ce31af4 | 3726 | /* PC-rel. addressing |
15bfe8b6 AG |
3727 | * 31 30 29 28 24 23 5 4 0 |
3728 | * +----+-------+-----------+-------------------+------+ | |
3729 | * | op | immlo | 1 0 0 0 0 | immhi | Rd | | |
3730 | * +----+-------+-----------+-------------------+------+ | |
3731 | */ | |
ad7ee8a2 CF |
3732 | static void disas_pc_rel_adr(DisasContext *s, uint32_t insn) |
3733 | { | |
15bfe8b6 AG |
3734 | unsigned int page, rd; |
3735 | uint64_t base; | |
037e1d00 | 3736 | uint64_t offset; |
15bfe8b6 AG |
3737 | |
3738 | page = extract32(insn, 31, 1); | |
3739 | /* SignExtend(immhi:immlo) -> offset */ | |
037e1d00 PM |
3740 | offset = sextract64(insn, 5, 19); |
3741 | offset = offset << 2 | extract32(insn, 29, 2); | |
15bfe8b6 | 3742 | rd = extract32(insn, 0, 5); |
43722a6d | 3743 | base = s->pc_curr; |
15bfe8b6 AG |
3744 | |
3745 | if (page) { | |
3746 | /* ADRP (page based) */ | |
3747 | base &= ~0xfff; | |
3748 | offset <<= 12; | |
3749 | } | |
3750 | ||
3751 | tcg_gen_movi_i64(cpu_reg(s, rd), base + offset); | |
ad7ee8a2 CF |
3752 | } |
3753 | ||
b0ff21b4 | 3754 | /* |
4ce31af4 | 3755 | * Add/subtract (immediate) |
b0ff21b4 | 3756 | * |
21a8b343 RH |
3757 | * 31 30 29 28 23 22 21 10 9 5 4 0 |
3758 | * +--+--+--+-------------+--+-------------+-----+-----+ | |
3759 | * |sf|op| S| 1 0 0 0 1 0 |sh| imm12 | Rn | Rd | | |
3760 | * +--+--+--+-------------+--+-------------+-----+-----+ | |
b0ff21b4 AB |
3761 | * |
3762 | * sf: 0 -> 32bit, 1 -> 64bit | |
3763 | * op: 0 -> add , 1 -> sub | |
3764 | * S: 1 -> set flags | |
21a8b343 | 3765 | * sh: 1 -> LSL imm by 12 |
b0ff21b4 | 3766 | */ |
ad7ee8a2 CF |
3767 | static void disas_add_sub_imm(DisasContext *s, uint32_t insn) |
3768 | { | |
b0ff21b4 AB |
3769 | int rd = extract32(insn, 0, 5); |
3770 | int rn = extract32(insn, 5, 5); | |
3771 | uint64_t imm = extract32(insn, 10, 12); | |
21a8b343 | 3772 | bool shift = extract32(insn, 22, 1); |
b0ff21b4 AB |
3773 | bool setflags = extract32(insn, 29, 1); |
3774 | bool sub_op = extract32(insn, 30, 1); | |
3775 | bool is_64bit = extract32(insn, 31, 1); | |
3776 | ||
3777 | TCGv_i64 tcg_rn = cpu_reg_sp(s, rn); | |
3778 | TCGv_i64 tcg_rd = setflags ? cpu_reg(s, rd) : cpu_reg_sp(s, rd); | |
3779 | TCGv_i64 tcg_result; | |
3780 | ||
21a8b343 | 3781 | if (shift) { |
b0ff21b4 | 3782 | imm <<= 12; |
b0ff21b4 AB |
3783 | } |
3784 | ||
3785 | tcg_result = tcg_temp_new_i64(); | |
3786 | if (!setflags) { | |
3787 | if (sub_op) { | |
3788 | tcg_gen_subi_i64(tcg_result, tcg_rn, imm); | |
3789 | } else { | |
3790 | tcg_gen_addi_i64(tcg_result, tcg_rn, imm); | |
3791 | } | |
3792 | } else { | |
3793 | TCGv_i64 tcg_imm = tcg_const_i64(imm); | |
3794 | if (sub_op) { | |
3795 | gen_sub_CC(is_64bit, tcg_result, tcg_rn, tcg_imm); | |
3796 | } else { | |
3797 | gen_add_CC(is_64bit, tcg_result, tcg_rn, tcg_imm); | |
3798 | } | |
3799 | tcg_temp_free_i64(tcg_imm); | |
3800 | } | |
3801 | ||
3802 | if (is_64bit) { | |
3803 | tcg_gen_mov_i64(tcg_rd, tcg_result); | |
3804 | } else { | |
3805 | tcg_gen_ext32u_i64(tcg_rd, tcg_result); | |
3806 | } | |
3807 | ||
3808 | tcg_temp_free_i64(tcg_result); | |
ad7ee8a2 CF |
3809 | } |
3810 | ||
efbc78ad RH |
3811 | /* |
3812 | * Add/subtract (immediate, with tags) | |
3813 | * | |
3814 | * 31 30 29 28 23 22 21 16 14 10 9 5 4 0 | |
3815 | * +--+--+--+-------------+--+---------+--+-------+-----+-----+ | |
3816 | * |sf|op| S| 1 0 0 0 1 1 |o2| uimm6 |o3| uimm4 | Rn | Rd | | |
3817 | * +--+--+--+-------------+--+---------+--+-------+-----+-----+ | |
3818 | * | |
3819 | * op: 0 -> add, 1 -> sub | |
3820 | */ | |
3821 | static void disas_add_sub_imm_with_tags(DisasContext *s, uint32_t insn) | |
3822 | { | |
3823 | int rd = extract32(insn, 0, 5); | |
3824 | int rn = extract32(insn, 5, 5); | |
3825 | int uimm4 = extract32(insn, 10, 4); | |
3826 | int uimm6 = extract32(insn, 16, 6); | |
3827 | bool sub_op = extract32(insn, 30, 1); | |
3828 | TCGv_i64 tcg_rn, tcg_rd; | |
3829 | int imm; | |
3830 | ||
3831 | /* Test all of sf=1, S=0, o2=0, o3=0. */ | |
3832 | if ((insn & 0xa040c000u) != 0x80000000u || | |
3833 | !dc_isar_feature(aa64_mte_insn_reg, s)) { | |
3834 | unallocated_encoding(s); | |
3835 | return; | |
3836 | } | |
3837 | ||
3838 | imm = uimm6 << LOG2_TAG_GRANULE; | |
3839 | if (sub_op) { | |
3840 | imm = -imm; | |
3841 | } | |
3842 | ||
3843 | tcg_rn = cpu_reg_sp(s, rn); | |
3844 | tcg_rd = cpu_reg_sp(s, rd); | |
3845 | ||
3846 | if (s->ata) { | |
3847 | TCGv_i32 offset = tcg_const_i32(imm); | |
3848 | TCGv_i32 tag_offset = tcg_const_i32(uimm4); | |
3849 | ||
3850 | gen_helper_addsubg(tcg_rd, cpu_env, tcg_rn, offset, tag_offset); | |
3851 | tcg_temp_free_i32(tag_offset); | |
3852 | tcg_temp_free_i32(offset); | |
3853 | } else { | |
3854 | tcg_gen_addi_i64(tcg_rd, tcg_rn, imm); | |
3855 | gen_address_with_allocation_tag0(tcg_rd, tcg_rd); | |
3856 | } | |
3857 | } | |
3858 | ||
71b46089 AG |
3859 | /* The input should be a value in the bottom e bits (with higher |
3860 | * bits zero); returns that value replicated into every element | |
3861 | * of size e in a 64 bit integer. | |
3862 | */ | |
3863 | static uint64_t bitfield_replicate(uint64_t mask, unsigned int e) | |
3864 | { | |
3865 | assert(e != 0); | |
3866 | while (e < 64) { | |
3867 | mask |= mask << e; | |
3868 | e *= 2; | |
3869 | } | |
3870 | return mask; | |
3871 | } | |
3872 | ||
3873 | /* Return a value with the bottom len bits set (where 0 < len <= 64) */ | |
3874 | static inline uint64_t bitmask64(unsigned int length) | |
3875 | { | |
3876 | assert(length > 0 && length <= 64); | |
3877 | return ~0ULL >> (64 - length); | |
3878 | } | |
3879 | ||
3880 | /* Simplified variant of pseudocode DecodeBitMasks() for the case where we | |
3881 | * only require the wmask. Returns false if the imms/immr/immn are a reserved | |
3882 | * value (ie should cause a guest UNDEF exception), and true if they are | |
3883 | * valid, in which case the decoded bit pattern is written to result. | |
3884 | */ | |
8c71baed RH |
3885 | bool logic_imm_decode_wmask(uint64_t *result, unsigned int immn, |
3886 | unsigned int imms, unsigned int immr) | |
71b46089 AG |
3887 | { |
3888 | uint64_t mask; | |
3889 | unsigned e, levels, s, r; | |
3890 | int len; | |
3891 | ||
3892 | assert(immn < 2 && imms < 64 && immr < 64); | |
3893 | ||
3894 | /* The bit patterns we create here are 64 bit patterns which | |
3895 | * are vectors of identical elements of size e = 2, 4, 8, 16, 32 or | |
3896 | * 64 bits each. Each element contains the same value: a run | |
3897 | * of between 1 and e-1 non-zero bits, rotated within the | |
3898 | * element by between 0 and e-1 bits. | |
3899 | * | |
3900 | * The element size and run length are encoded into immn (1 bit) | |
3901 | * and imms (6 bits) as follows: | |
3902 | * 64 bit elements: immn = 1, imms = <length of run - 1> | |
3903 | * 32 bit elements: immn = 0, imms = 0 : <length of run - 1> | |
3904 | * 16 bit elements: immn = 0, imms = 10 : <length of run - 1> | |
3905 | * 8 bit elements: immn = 0, imms = 110 : <length of run - 1> | |
3906 | * 4 bit elements: immn = 0, imms = 1110 : <length of run - 1> | |
3907 | * 2 bit elements: immn = 0, imms = 11110 : <length of run - 1> | |
3908 | * Notice that immn = 0, imms = 11111x is the only combination | |
3909 | * not covered by one of the above options; this is reserved. | |
3910 | * Further, <length of run - 1> all-ones is a reserved pattern. | |
3911 | * | |
3912 | * In all cases the rotation is by immr % e (and immr is 6 bits). | |
3913 | */ | |
3914 | ||
3915 | /* First determine the element size */ | |
3916 | len = 31 - clz32((immn << 6) | (~imms & 0x3f)); | |
3917 | if (len < 1) { | |
3918 | /* This is the immn == 0, imms == 0x11111x case */ | |
3919 | return false; | |
3920 | } | |
3921 | e = 1 << len; | |
3922 | ||
3923 | levels = e - 1; | |
3924 | s = imms & levels; | |
3925 | r = immr & levels; | |
3926 | ||
3927 | if (s == levels) { | |
3928 | /* <length of run - 1> mustn't be all-ones. */ | |
3929 | return false; | |
3930 | } | |
3931 | ||
3932 | /* Create the value of one element: s+1 set bits rotated | |
3933 | * by r within the element (which is e bits wide)... | |
3934 | */ | |
3935 | mask = bitmask64(s + 1); | |
e167adc9 PM |
3936 | if (r) { |
3937 | mask = (mask >> r) | (mask << (e - r)); | |
3938 | mask &= bitmask64(e); | |
3939 | } | |
71b46089 AG |
3940 | /* ...then replicate the element over the whole 64 bit value */ |
3941 | mask = bitfield_replicate(mask, e); | |
3942 | *result = mask; | |
3943 | return true; | |
3944 | } | |
3945 | ||
4ce31af4 | 3946 | /* Logical (immediate) |
71b46089 AG |
3947 | * 31 30 29 28 23 22 21 16 15 10 9 5 4 0 |
3948 | * +----+-----+-------------+---+------+------+------+------+ | |
3949 | * | sf | opc | 1 0 0 1 0 0 | N | immr | imms | Rn | Rd | | |
3950 | * +----+-----+-------------+---+------+------+------+------+ | |
3951 | */ | |
ad7ee8a2 CF |
3952 | static void disas_logic_imm(DisasContext *s, uint32_t insn) |
3953 | { | |
71b46089 AG |
3954 | unsigned int sf, opc, is_n, immr, imms, rn, rd; |
3955 | TCGv_i64 tcg_rd, tcg_rn; | |
3956 | uint64_t wmask; | |
3957 | bool is_and = false; | |
3958 | ||
3959 | sf = extract32(insn, 31, 1); | |
3960 | opc = extract32(insn, 29, 2); | |
3961 | is_n = extract32(insn, 22, 1); | |
3962 | immr = extract32(insn, 16, 6); | |
3963 | imms = extract32(insn, 10, 6); | |
3964 | rn = extract32(insn, 5, 5); | |
3965 | rd = extract32(insn, 0, 5); | |
3966 | ||
3967 | if (!sf && is_n) { | |
3968 | unallocated_encoding(s); | |
3969 | return; | |
3970 | } | |
3971 | ||
3972 | if (opc == 0x3) { /* ANDS */ | |
3973 | tcg_rd = cpu_reg(s, rd); | |
3974 | } else { | |
3975 | tcg_rd = cpu_reg_sp(s, rd); | |
3976 | } | |
3977 | tcg_rn = cpu_reg(s, rn); | |
3978 | ||
3979 | if (!logic_imm_decode_wmask(&wmask, is_n, imms, immr)) { | |
3980 | /* some immediate field values are reserved */ | |
3981 | unallocated_encoding(s); | |
3982 | return; | |
3983 | } | |
3984 | ||
3985 | if (!sf) { | |
3986 | wmask &= 0xffffffff; | |
3987 | } | |
3988 | ||
3989 | switch (opc) { | |
3990 | case 0x3: /* ANDS */ | |
3991 | case 0x0: /* AND */ | |
3992 | tcg_gen_andi_i64(tcg_rd, tcg_rn, wmask); | |
3993 | is_and = true; | |
3994 | break; | |
3995 | case 0x1: /* ORR */ | |
3996 | tcg_gen_ori_i64(tcg_rd, tcg_rn, wmask); | |
3997 | break; | |
3998 | case 0x2: /* EOR */ | |
3999 | tcg_gen_xori_i64(tcg_rd, tcg_rn, wmask); | |
4000 | break; | |
4001 | default: | |
4002 | assert(FALSE); /* must handle all above */ | |
4003 | break; | |
4004 | } | |
4005 | ||
4006 | if (!sf && !is_and) { | |
4007 | /* zero extend final result; we know we can skip this for AND | |
4008 | * since the immediate had the high 32 bits clear. | |
4009 | */ | |
4010 | tcg_gen_ext32u_i64(tcg_rd, tcg_rd); | |
4011 | } | |
4012 | ||
4013 | if (opc == 3) { /* ANDS */ | |
4014 | gen_logic_CC(sf, tcg_rd); | |
4015 | } | |
ad7ee8a2 CF |
4016 | } |
4017 | ||
ed6ec679 | 4018 | /* |
4ce31af4 | 4019 | * Move wide (immediate) |
ed6ec679 AB |
4020 | * |
4021 | * 31 30 29 28 23 22 21 20 5 4 0 | |
4022 | * +--+-----+-------------+-----+----------------+------+ | |
4023 | * |sf| opc | 1 0 0 1 0 1 | hw | imm16 | Rd | | |
4024 | * +--+-----+-------------+-----+----------------+------+ | |
4025 | * | |
4026 | * sf: 0 -> 32 bit, 1 -> 64 bit | |
4027 | * opc: 00 -> N, 10 -> Z, 11 -> K | |
4028 | * hw: shift/16 (0,16, and sf only 32, 48) | |
4029 | */ | |
ad7ee8a2 CF |
4030 | static void disas_movw_imm(DisasContext *s, uint32_t insn) |
4031 | { | |
ed6ec679 AB |
4032 | int rd = extract32(insn, 0, 5); |
4033 | uint64_t imm = extract32(insn, 5, 16); | |
4034 | int sf = extract32(insn, 31, 1); | |
4035 | int opc = extract32(insn, 29, 2); | |
4036 | int pos = extract32(insn, 21, 2) << 4; | |
4037 | TCGv_i64 tcg_rd = cpu_reg(s, rd); | |
4038 | TCGv_i64 tcg_imm; | |
4039 | ||
4040 | if (!sf && (pos >= 32)) { | |
4041 | unallocated_encoding(s); | |
4042 | return; | |
4043 | } | |
4044 | ||
4045 | switch (opc) { | |
4046 | case 0: /* MOVN */ | |
4047 | case 2: /* MOVZ */ | |
4048 | imm <<= pos; | |
4049 | if (opc == 0) { | |
4050 | imm = ~imm; | |
4051 | } | |
4052 | if (!sf) { | |
4053 | imm &= 0xffffffffu; | |
4054 | } | |
4055 | tcg_gen_movi_i64(tcg_rd, imm); | |
4056 | break; | |
4057 | case 3: /* MOVK */ | |
4058 | tcg_imm = tcg_const_i64(imm); | |
4059 | tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_imm, pos, 16); | |
4060 | tcg_temp_free_i64(tcg_imm); | |
4061 | if (!sf) { | |
4062 | tcg_gen_ext32u_i64(tcg_rd, tcg_rd); | |
4063 | } | |
4064 | break; | |
4065 | default: | |
4066 | unallocated_encoding(s); | |
4067 | break; | |
4068 | } | |
ad7ee8a2 CF |
4069 | } |
4070 | ||
4ce31af4 | 4071 | /* Bitfield |
88077742 CF |
4072 | * 31 30 29 28 23 22 21 16 15 10 9 5 4 0 |
4073 | * +----+-----+-------------+---+------+------+------+------+ | |
4074 | * | sf | opc | 1 0 0 1 1 0 | N | immr | imms | Rn | Rd | | |
4075 | * +----+-----+-------------+---+------+------+------+------+ | |
4076 | */ | |
ad7ee8a2 CF |
4077 | static void disas_bitfield(DisasContext *s, uint32_t insn) |
4078 | { | |
88077742 CF |
4079 | unsigned int sf, n, opc, ri, si, rn, rd, bitsize, pos, len; |
4080 | TCGv_i64 tcg_rd, tcg_tmp; | |
4081 | ||
4082 | sf = extract32(insn, 31, 1); | |
4083 | opc = extract32(insn, 29, 2); | |
4084 | n = extract32(insn, 22, 1); | |
4085 | ri = extract32(insn, 16, 6); | |
4086 | si = extract32(insn, 10, 6); | |
4087 | rn = extract32(insn, 5, 5); | |
4088 | rd = extract32(insn, 0, 5); | |
4089 | bitsize = sf ? 64 : 32; | |
4090 | ||
4091 | if (sf != n || ri >= bitsize || si >= bitsize || opc > 2) { | |
4092 | unallocated_encoding(s); | |
4093 | return; | |
4094 | } | |
4095 | ||
4096 | tcg_rd = cpu_reg(s, rd); | |
d3a77b42 RH |
4097 | |
4098 | /* Suppress the zero-extend for !sf. Since RI and SI are constrained | |
4099 | to be smaller than bitsize, we'll never reference data outside the | |
4100 | low 32-bits anyway. */ | |
4101 | tcg_tmp = read_cpu_reg(s, rn, 1); | |
88077742 | 4102 | |
59a71b4c | 4103 | /* Recognize simple(r) extractions. */ |
86c9ab27 | 4104 | if (si >= ri) { |
59a71b4c RH |
4105 | /* Wd<s-r:0> = Wn<s:r> */ |
4106 | len = (si - ri) + 1; | |
4107 | if (opc == 0) { /* SBFM: ASR, SBFX, SXTB, SXTH, SXTW */ | |
4108 | tcg_gen_sextract_i64(tcg_rd, tcg_tmp, ri, len); | |
ef60151b | 4109 | goto done; |
59a71b4c RH |
4110 | } else if (opc == 2) { /* UBFM: UBFX, LSR, UXTB, UXTH */ |
4111 | tcg_gen_extract_i64(tcg_rd, tcg_tmp, ri, len); | |
9924e858 RH |
4112 | return; |
4113 | } | |
87eb65a3 RH |
4114 | /* opc == 1, BFXIL fall through to deposit */ |
4115 | tcg_gen_shri_i64(tcg_tmp, tcg_tmp, ri); | |
88077742 | 4116 | pos = 0; |
88077742 | 4117 | } else { |
59a71b4c RH |
4118 | /* Handle the ri > si case with a deposit |
4119 | * Wd<32+s-r,32-r> = Wn<s:0> | |
4120 | */ | |
88077742 | 4121 | len = si + 1; |
59a71b4c | 4122 | pos = (bitsize - ri) & (bitsize - 1); |
88077742 CF |
4123 | } |
4124 | ||
59a71b4c RH |
4125 | if (opc == 0 && len < ri) { |
4126 | /* SBFM: sign extend the destination field from len to fill | |
4127 | the balance of the word. Let the deposit below insert all | |
4128 | of those sign bits. */ | |
4129 | tcg_gen_sextract_i64(tcg_tmp, tcg_tmp, 0, len); | |
4130 | len = ri; | |
4131 | } | |
88077742 | 4132 | |
87eb65a3 | 4133 | if (opc == 1) { /* BFM, BFXIL */ |
59a71b4c RH |
4134 | tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_tmp, pos, len); |
4135 | } else { | |
4136 | /* SBFM or UBFM: We start with zero, and we haven't modified | |
4137 | any bits outside bitsize, therefore the zero-extension | |
4138 | below is unneeded. */ | |
4139 | tcg_gen_deposit_z_i64(tcg_rd, tcg_tmp, pos, len); | |
4140 | return; | |
88077742 CF |
4141 | } |
4142 | ||
ef60151b | 4143 | done: |
88077742 CF |
4144 | if (!sf) { /* zero extend final result */ |
4145 | tcg_gen_ext32u_i64(tcg_rd, tcg_rd); | |
4146 | } | |
ad7ee8a2 CF |
4147 | } |
4148 | ||
4ce31af4 | 4149 | /* Extract |
e801de93 AG |
4150 | * 31 30 29 28 23 22 21 20 16 15 10 9 5 4 0 |
4151 | * +----+------+-------------+---+----+------+--------+------+------+ | |
4152 | * | sf | op21 | 1 0 0 1 1 1 | N | o0 | Rm | imms | Rn | Rd | | |
4153 | * +----+------+-------------+---+----+------+--------+------+------+ | |
4154 | */ | |
ad7ee8a2 CF |
4155 | static void disas_extract(DisasContext *s, uint32_t insn) |
4156 | { | |
e801de93 AG |
4157 | unsigned int sf, n, rm, imm, rn, rd, bitsize, op21, op0; |
4158 | ||
4159 | sf = extract32(insn, 31, 1); | |
4160 | n = extract32(insn, 22, 1); | |
4161 | rm = extract32(insn, 16, 5); | |
4162 | imm = extract32(insn, 10, 6); | |
4163 | rn = extract32(insn, 5, 5); | |
4164 | rd = extract32(insn, 0, 5); | |
4165 | op21 = extract32(insn, 29, 2); | |
4166 | op0 = extract32(insn, 21, 1); | |
4167 | bitsize = sf ? 64 : 32; | |
4168 | ||
4169 | if (sf != n || op21 || op0 || imm >= bitsize) { | |
4170 | unallocated_encoding(s); | |
4171 | } else { | |
4172 | TCGv_i64 tcg_rd, tcg_rm, tcg_rn; | |
4173 | ||
4174 | tcg_rd = cpu_reg(s, rd); | |
4175 | ||
8fb0ad8e | 4176 | if (unlikely(imm == 0)) { |
e801de93 AG |
4177 | /* tcg shl_i32/shl_i64 is undefined for 32/64 bit shifts, |
4178 | * so an extract from bit 0 is a special case. | |
4179 | */ | |
4180 | if (sf) { | |
4181 | tcg_gen_mov_i64(tcg_rd, cpu_reg(s, rm)); | |
4182 | } else { | |
4183 | tcg_gen_ext32u_i64(tcg_rd, cpu_reg(s, rm)); | |
4184 | } | |
80ac954c | 4185 | } else { |
8fb0ad8e | 4186 | tcg_rm = cpu_reg(s, rm); |
80ac954c RH |
4187 | tcg_rn = cpu_reg(s, rn); |
4188 | ||
8fb0ad8e | 4189 | if (sf) { |
80ac954c RH |
4190 | /* Specialization to ROR happens in EXTRACT2. */ |
4191 | tcg_gen_extract2_i64(tcg_rd, tcg_rm, tcg_rn, imm); | |
8fb0ad8e | 4192 | } else { |
80ac954c RH |
4193 | TCGv_i32 t0 = tcg_temp_new_i32(); |
4194 | ||
4195 | tcg_gen_extrl_i64_i32(t0, tcg_rm); | |
4196 | if (rm == rn) { | |
4197 | tcg_gen_rotri_i32(t0, t0, imm); | |
4198 | } else { | |
4199 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
4200 | tcg_gen_extrl_i64_i32(t1, tcg_rn); | |
4201 | tcg_gen_extract2_i32(t0, t0, t1, imm); | |
4202 | tcg_temp_free_i32(t1); | |
4203 | } | |
4204 | tcg_gen_extu_i32_i64(tcg_rd, t0); | |
4205 | tcg_temp_free_i32(t0); | |
8fb0ad8e | 4206 | } |
e801de93 | 4207 | } |
e801de93 | 4208 | } |
ad7ee8a2 CF |
4209 | } |
4210 | ||
4ce31af4 | 4211 | /* Data processing - immediate */ |
ad7ee8a2 CF |
4212 | static void disas_data_proc_imm(DisasContext *s, uint32_t insn) |
4213 | { | |
4214 | switch (extract32(insn, 23, 6)) { | |
4215 | case 0x20: case 0x21: /* PC-rel. addressing */ | |
4216 | disas_pc_rel_adr(s, insn); | |
4217 | break; | |
21a8b343 | 4218 | case 0x22: /* Add/subtract (immediate) */ |
ad7ee8a2 CF |
4219 | disas_add_sub_imm(s, insn); |
4220 | break; | |
efbc78ad RH |
4221 | case 0x23: /* Add/subtract (immediate, with tags) */ |
4222 | disas_add_sub_imm_with_tags(s, insn); | |
4223 | break; | |
ad7ee8a2 CF |
4224 | case 0x24: /* Logical (immediate) */ |
4225 | disas_logic_imm(s, insn); | |
4226 | break; | |
4227 | case 0x25: /* Move wide (immediate) */ | |
4228 | disas_movw_imm(s, insn); | |
4229 | break; | |
4230 | case 0x26: /* Bitfield */ | |
4231 | disas_bitfield(s, insn); | |
4232 | break; | |
4233 | case 0x27: /* Extract */ | |
4234 | disas_extract(s, insn); | |
4235 | break; | |
4236 | default: | |
4237 | unallocated_encoding(s); | |
4238 | break; | |
4239 | } | |
4240 | } | |
4241 | ||
832ffa1c AG |
4242 | /* Shift a TCGv src by TCGv shift_amount, put result in dst. |
4243 | * Note that it is the caller's responsibility to ensure that the | |
4244 | * shift amount is in range (ie 0..31 or 0..63) and provide the ARM | |
4245 | * mandated semantics for out of range shifts. | |
4246 | */ | |
4247 | static void shift_reg(TCGv_i64 dst, TCGv_i64 src, int sf, | |
4248 | enum a64_shift_type shift_type, TCGv_i64 shift_amount) | |
4249 | { | |
4250 | switch (shift_type) { | |
4251 | case A64_SHIFT_TYPE_LSL: | |
4252 | tcg_gen_shl_i64(dst, src, shift_amount); | |
4253 | break; | |
4254 | case A64_SHIFT_TYPE_LSR: | |
4255 | tcg_gen_shr_i64(dst, src, shift_amount); | |
4256 | break; | |
4257 | case A64_SHIFT_TYPE_ASR: | |
4258 | if (!sf) { | |
4259 | tcg_gen_ext32s_i64(dst, src); | |
4260 | } | |
4261 | tcg_gen_sar_i64(dst, sf ? src : dst, shift_amount); | |
4262 | break; | |
4263 | case A64_SHIFT_TYPE_ROR: | |
4264 | if (sf) { | |
4265 | tcg_gen_rotr_i64(dst, src, shift_amount); | |
4266 | } else { | |
4267 | TCGv_i32 t0, t1; | |
4268 | t0 = tcg_temp_new_i32(); | |
4269 | t1 = tcg_temp_new_i32(); | |
ecc7b3aa RH |
4270 | tcg_gen_extrl_i64_i32(t0, src); |
4271 | tcg_gen_extrl_i64_i32(t1, shift_amount); | |
832ffa1c AG |
4272 | tcg_gen_rotr_i32(t0, t0, t1); |
4273 | tcg_gen_extu_i32_i64(dst, t0); | |
4274 | tcg_temp_free_i32(t0); | |
4275 | tcg_temp_free_i32(t1); | |
4276 | } | |
4277 | break; | |
4278 | default: | |
4279 | assert(FALSE); /* all shift types should be handled */ | |
4280 | break; | |
4281 | } | |
4282 | ||
4283 | if (!sf) { /* zero extend final result */ | |
4284 | tcg_gen_ext32u_i64(dst, dst); | |
4285 | } | |
4286 | } | |
4287 | ||
4288 | /* Shift a TCGv src by immediate, put result in dst. | |
4289 | * The shift amount must be in range (this should always be true as the | |
4290 | * relevant instructions will UNDEF on bad shift immediates). | |
4291 | */ | |
4292 | static void shift_reg_imm(TCGv_i64 dst, TCGv_i64 src, int sf, | |
4293 | enum a64_shift_type shift_type, unsigned int shift_i) | |
4294 | { | |
4295 | assert(shift_i < (sf ? 64 : 32)); | |
4296 | ||
4297 | if (shift_i == 0) { | |
4298 | tcg_gen_mov_i64(dst, src); | |
4299 | } else { | |
4300 | TCGv_i64 shift_const; | |
4301 | ||
4302 | shift_const = tcg_const_i64(shift_i); | |
4303 | shift_reg(dst, src, sf, shift_type, shift_const); | |
4304 | tcg_temp_free_i64(shift_const); | |
4305 | } | |
4306 | } | |
4307 | ||
4ce31af4 | 4308 | /* Logical (shifted register) |
832ffa1c AG |
4309 | * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0 |
4310 | * +----+-----+-----------+-------+---+------+--------+------+------+ | |
4311 | * | sf | opc | 0 1 0 1 0 | shift | N | Rm | imm6 | Rn | Rd | | |
4312 | * +----+-----+-----------+-------+---+------+--------+------+------+ | |
4313 | */ | |
ad7ee8a2 CF |
4314 | static void disas_logic_reg(DisasContext *s, uint32_t insn) |
4315 | { | |
832ffa1c AG |
4316 | TCGv_i64 tcg_rd, tcg_rn, tcg_rm; |
4317 | unsigned int sf, opc, shift_type, invert, rm, shift_amount, rn, rd; | |
4318 | ||
4319 | sf = extract32(insn, 31, 1); | |
4320 | opc = extract32(insn, 29, 2); | |
4321 | shift_type = extract32(insn, 22, 2); | |
4322 | invert = extract32(insn, 21, 1); | |
4323 | rm = extract32(insn, 16, 5); | |
4324 | shift_amount = extract32(insn, 10, 6); | |
4325 | rn = extract32(insn, 5, 5); | |
4326 | rd = extract32(insn, 0, 5); | |
4327 | ||
4328 | if (!sf && (shift_amount & (1 << 5))) { | |
4329 | unallocated_encoding(s); | |
4330 | return; | |
4331 | } | |
4332 | ||
4333 | tcg_rd = cpu_reg(s, rd); | |
4334 | ||
4335 | if (opc == 1 && shift_amount == 0 && shift_type == 0 && rn == 31) { | |
4336 | /* Unshifted ORR and ORN with WZR/XZR is the standard encoding for | |
4337 | * register-register MOV and MVN, so it is worth special casing. | |
4338 | */ | |
4339 | tcg_rm = cpu_reg(s, rm); | |
4340 | if (invert) { | |
4341 | tcg_gen_not_i64(tcg_rd, tcg_rm); | |
4342 | if (!sf) { | |
4343 | tcg_gen_ext32u_i64(tcg_rd, tcg_rd); | |
4344 | } | |
4345 | } else { | |
4346 | if (sf) { | |
4347 | tcg_gen_mov_i64(tcg_rd, tcg_rm); | |
4348 | } else { | |
4349 | tcg_gen_ext32u_i64(tcg_rd, tcg_rm); | |
4350 | } | |
4351 | } | |
4352 | return; | |
4353 | } | |
4354 | ||
4355 | tcg_rm = read_cpu_reg(s, rm, sf); | |
4356 | ||
4357 | if (shift_amount) { | |
4358 | shift_reg_imm(tcg_rm, tcg_rm, sf, shift_type, shift_amount); | |
4359 | } | |
4360 | ||
4361 | tcg_rn = cpu_reg(s, rn); | |
4362 | ||
4363 | switch (opc | (invert << 2)) { | |
4364 | case 0: /* AND */ | |
4365 | case 3: /* ANDS */ | |
4366 | tcg_gen_and_i64(tcg_rd, tcg_rn, tcg_rm); | |
4367 | break; | |
4368 | case 1: /* ORR */ | |
4369 | tcg_gen_or_i64(tcg_rd, tcg_rn, tcg_rm); | |
4370 | break; | |
4371 | case 2: /* EOR */ | |
4372 | tcg_gen_xor_i64(tcg_rd, tcg_rn, tcg_rm); | |
4373 | break; | |
4374 | case 4: /* BIC */ | |
4375 | case 7: /* BICS */ | |
4376 | tcg_gen_andc_i64(tcg_rd, tcg_rn, tcg_rm); | |
4377 | break; | |
4378 | case 5: /* ORN */ | |
4379 | tcg_gen_orc_i64(tcg_rd, tcg_rn, tcg_rm); | |
4380 | break; | |
4381 | case 6: /* EON */ | |
4382 | tcg_gen_eqv_i64(tcg_rd, tcg_rn, tcg_rm); | |
4383 | break; | |
4384 | default: | |
4385 | assert(FALSE); | |
4386 | break; | |
4387 | } | |
4388 | ||
4389 | if (!sf) { | |
4390 | tcg_gen_ext32u_i64(tcg_rd, tcg_rd); | |
4391 | } | |
4392 | ||
4393 | if (opc == 3) { | |
4394 | gen_logic_CC(sf, tcg_rd); | |
4395 | } | |
ad7ee8a2 CF |
4396 | } |
4397 | ||
b0ff21b4 | 4398 | /* |
4ce31af4 | 4399 | * Add/subtract (extended register) |
b0ff21b4 AB |
4400 | * |
4401 | * 31|30|29|28 24|23 22|21|20 16|15 13|12 10|9 5|4 0| | |
4402 | * +--+--+--+-----------+-----+--+-------+------+------+----+----+ | |
4403 | * |sf|op| S| 0 1 0 1 1 | opt | 1| Rm |option| imm3 | Rn | Rd | | |
4404 | * +--+--+--+-----------+-----+--+-------+------+------+----+----+ | |
4405 | * | |
4406 | * sf: 0 -> 32bit, 1 -> 64bit | |
4407 | * op: 0 -> add , 1 -> sub | |
4408 | * S: 1 -> set flags | |
4409 | * opt: 00 | |
4410 | * option: extension type (see DecodeRegExtend) | |
4411 | * imm3: optional shift to Rm | |
4412 | * | |
4413 | * Rd = Rn + LSL(extend(Rm), amount) | |
4414 | */ | |
ad7ee8a2 CF |
4415 | static void disas_add_sub_ext_reg(DisasContext *s, uint32_t insn) |
4416 | { | |
b0ff21b4 AB |
4417 | int rd = extract32(insn, 0, 5); |
4418 | int rn = extract32(insn, 5, 5); | |
4419 | int imm3 = extract32(insn, 10, 3); | |
4420 | int option = extract32(insn, 13, 3); | |
4421 | int rm = extract32(insn, 16, 5); | |
4f611066 | 4422 | int opt = extract32(insn, 22, 2); |
b0ff21b4 AB |
4423 | bool setflags = extract32(insn, 29, 1); |
4424 | bool sub_op = extract32(insn, 30, 1); | |
4425 | bool sf = extract32(insn, 31, 1); | |
4426 | ||
4427 | TCGv_i64 tcg_rm, tcg_rn; /* temps */ | |
4428 | TCGv_i64 tcg_rd; | |
4429 | TCGv_i64 tcg_result; | |
4430 | ||
4f611066 | 4431 | if (imm3 > 4 || opt != 0) { |
b0ff21b4 AB |
4432 | unallocated_encoding(s); |
4433 | return; | |
4434 | } | |
4435 | ||
4436 | /* non-flag setting ops may use SP */ | |
4437 | if (!setflags) { | |
b0ff21b4 AB |
4438 | tcg_rd = cpu_reg_sp(s, rd); |
4439 | } else { | |
b0ff21b4 AB |
4440 | tcg_rd = cpu_reg(s, rd); |
4441 | } | |
cf4ab1af | 4442 | tcg_rn = read_cpu_reg_sp(s, rn, sf); |
b0ff21b4 AB |
4443 | |
4444 | tcg_rm = read_cpu_reg(s, rm, sf); | |
4445 | ext_and_shift_reg(tcg_rm, tcg_rm, option, imm3); | |
4446 | ||
4447 | tcg_result = tcg_temp_new_i64(); | |
4448 | ||
4449 | if (!setflags) { | |
4450 | if (sub_op) { | |
4451 | tcg_gen_sub_i64(tcg_result, tcg_rn, tcg_rm); | |
4452 | } else { | |
4453 | tcg_gen_add_i64(tcg_result, tcg_rn, tcg_rm); | |
4454 | } | |
4455 | } else { | |
4456 | if (sub_op) { | |
4457 | gen_sub_CC(sf, tcg_result, tcg_rn, tcg_rm); | |
4458 | } else { | |
4459 | gen_add_CC(sf, tcg_result, tcg_rn, tcg_rm); | |
4460 | } | |
4461 | } | |
4462 | ||
4463 | if (sf) { | |
4464 | tcg_gen_mov_i64(tcg_rd, tcg_result); | |
4465 | } else { | |
4466 | tcg_gen_ext32u_i64(tcg_rd, tcg_result); | |
4467 | } | |
4468 | ||
4469 | tcg_temp_free_i64(tcg_result); | |
ad7ee8a2 CF |
4470 | } |
4471 | ||
b0ff21b4 | 4472 | /* |
4ce31af4 | 4473 | * Add/subtract (shifted register) |
b0ff21b4 AB |
4474 | * |
4475 | * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0 | |
4476 | * +--+--+--+-----------+-----+--+-------+---------+------+------+ | |
4477 | * |sf|op| S| 0 1 0 1 1 |shift| 0| Rm | imm6 | Rn | Rd | | |
4478 | * +--+--+--+-----------+-----+--+-------+---------+------+------+ | |
4479 | * | |
4480 | * sf: 0 -> 32bit, 1 -> 64bit | |
4481 | * op: 0 -> add , 1 -> sub | |
4482 | * S: 1 -> set flags | |
4483 | * shift: 00 -> LSL, 01 -> LSR, 10 -> ASR, 11 -> RESERVED | |
4484 | * imm6: Shift amount to apply to Rm before the add/sub | |
4485 | */ | |
ad7ee8a2 CF |
4486 | static void disas_add_sub_reg(DisasContext *s, uint32_t insn) |
4487 | { | |
b0ff21b4 AB |
4488 | int rd = extract32(insn, 0, 5); |
4489 | int rn = extract32(insn, 5, 5); | |
4490 | int imm6 = extract32(insn, 10, 6); | |
4491 | int rm = extract32(insn, 16, 5); | |
4492 | int shift_type = extract32(insn, 22, 2); | |
4493 | bool setflags = extract32(insn, 29, 1); | |
4494 | bool sub_op = extract32(insn, 30, 1); | |
4495 | bool sf = extract32(insn, 31, 1); | |
4496 | ||
4497 | TCGv_i64 tcg_rd = cpu_reg(s, rd); | |
4498 | TCGv_i64 tcg_rn, tcg_rm; | |
4499 | TCGv_i64 tcg_result; | |
4500 | ||
4501 | if ((shift_type == 3) || (!sf && (imm6 > 31))) { | |
4502 | unallocated_encoding(s); | |
4503 | return; | |
4504 | } | |
4505 | ||
4506 | tcg_rn = read_cpu_reg(s, rn, sf); | |
4507 | tcg_rm = read_cpu_reg(s, rm, sf); | |
4508 | ||
4509 | shift_reg_imm(tcg_rm, tcg_rm, sf, shift_type, imm6); | |
4510 | ||
4511 | tcg_result = tcg_temp_new_i64(); | |
4512 | ||
4513 | if (!setflags) { | |
4514 | if (sub_op) { | |
4515 | tcg_gen_sub_i64(tcg_result, tcg_rn, tcg_rm); | |
4516 | } else { | |
4517 | tcg_gen_add_i64(tcg_result, tcg_rn, tcg_rm); | |
4518 | } | |
4519 | } else { | |
4520 | if (sub_op) { | |
4521 | gen_sub_CC(sf, tcg_result, tcg_rn, tcg_rm); | |
4522 | } else { | |
4523 | gen_add_CC(sf, tcg_result, tcg_rn, tcg_rm); | |
4524 | } | |
4525 | } | |
4526 | ||
4527 | if (sf) { | |
4528 | tcg_gen_mov_i64(tcg_rd, tcg_result); | |
4529 | } else { | |
4530 | tcg_gen_ext32u_i64(tcg_rd, tcg_result); | |
4531 | } | |
4532 | ||
4533 | tcg_temp_free_i64(tcg_result); | |
ad7ee8a2 CF |
4534 | } |
4535 | ||
4ce31af4 PM |
4536 | /* Data-processing (3 source) |
4537 | * | |
4538 | * 31 30 29 28 24 23 21 20 16 15 14 10 9 5 4 0 | |
4539 | * +--+------+-----------+------+------+----+------+------+------+ | |
4540 | * |sf| op54 | 1 1 0 1 1 | op31 | Rm | o0 | Ra | Rn | Rd | | |
4541 | * +--+------+-----------+------+------+----+------+------+------+ | |
52c8b9af | 4542 | */ |
ad7ee8a2 CF |
4543 | static void disas_data_proc_3src(DisasContext *s, uint32_t insn) |
4544 | { | |
52c8b9af AG |
4545 | int rd = extract32(insn, 0, 5); |
4546 | int rn = extract32(insn, 5, 5); | |
4547 | int ra = extract32(insn, 10, 5); | |
4548 | int rm = extract32(insn, 16, 5); | |
4549 | int op_id = (extract32(insn, 29, 3) << 4) | | |
4550 | (extract32(insn, 21, 3) << 1) | | |
4551 | extract32(insn, 15, 1); | |
4552 | bool sf = extract32(insn, 31, 1); | |
4553 | bool is_sub = extract32(op_id, 0, 1); | |
4554 | bool is_high = extract32(op_id, 2, 1); | |
4555 | bool is_signed = false; | |
4556 | TCGv_i64 tcg_op1; | |
4557 | TCGv_i64 tcg_op2; | |
4558 | TCGv_i64 tcg_tmp; | |
4559 | ||
4560 | /* Note that op_id is sf:op54:op31:o0 so it includes the 32/64 size flag */ | |
4561 | switch (op_id) { | |
4562 | case 0x42: /* SMADDL */ | |
4563 | case 0x43: /* SMSUBL */ | |
4564 | case 0x44: /* SMULH */ | |
4565 | is_signed = true; | |
4566 | break; | |
4567 | case 0x0: /* MADD (32bit) */ | |
4568 | case 0x1: /* MSUB (32bit) */ | |
4569 | case 0x40: /* MADD (64bit) */ | |
4570 | case 0x41: /* MSUB (64bit) */ | |
4571 | case 0x4a: /* UMADDL */ | |
4572 | case 0x4b: /* UMSUBL */ | |
4573 | case 0x4c: /* UMULH */ | |
4574 | break; | |
4575 | default: | |
4576 | unallocated_encoding(s); | |
4577 | return; | |
4578 | } | |
4579 | ||
4580 | if (is_high) { | |
4581 | TCGv_i64 low_bits = tcg_temp_new_i64(); /* low bits discarded */ | |
4582 | TCGv_i64 tcg_rd = cpu_reg(s, rd); | |
4583 | TCGv_i64 tcg_rn = cpu_reg(s, rn); | |
4584 | TCGv_i64 tcg_rm = cpu_reg(s, rm); | |
4585 | ||
4586 | if (is_signed) { | |
4587 | tcg_gen_muls2_i64(low_bits, tcg_rd, tcg_rn, tcg_rm); | |
4588 | } else { | |
4589 | tcg_gen_mulu2_i64(low_bits, tcg_rd, tcg_rn, tcg_rm); | |
4590 | } | |
4591 | ||
4592 | tcg_temp_free_i64(low_bits); | |
4593 | return; | |
4594 | } | |
4595 | ||
4596 | tcg_op1 = tcg_temp_new_i64(); | |
4597 | tcg_op2 = tcg_temp_new_i64(); | |
4598 | tcg_tmp = tcg_temp_new_i64(); | |
4599 | ||
4600 | if (op_id < 0x42) { | |
4601 | tcg_gen_mov_i64(tcg_op1, cpu_reg(s, rn)); | |
4602 | tcg_gen_mov_i64(tcg_op2, cpu_reg(s, rm)); | |
4603 | } else { | |
4604 | if (is_signed) { | |
4605 | tcg_gen_ext32s_i64(tcg_op1, cpu_reg(s, rn)); | |
4606 | tcg_gen_ext32s_i64(tcg_op2, cpu_reg(s, rm)); | |
4607 | } else { | |
4608 | tcg_gen_ext32u_i64(tcg_op1, cpu_reg(s, rn)); | |
4609 | tcg_gen_ext32u_i64(tcg_op2, cpu_reg(s, rm)); | |
4610 | } | |
4611 | } | |
4612 | ||
4613 | if (ra == 31 && !is_sub) { | |
4614 | /* Special-case MADD with rA == XZR; it is the standard MUL alias */ | |
4615 | tcg_gen_mul_i64(cpu_reg(s, rd), tcg_op1, tcg_op2); | |
4616 | } else { | |
4617 | tcg_gen_mul_i64(tcg_tmp, tcg_op1, tcg_op2); | |
4618 | if (is_sub) { | |
4619 | tcg_gen_sub_i64(cpu_reg(s, rd), cpu_reg(s, ra), tcg_tmp); | |
4620 | } else { | |
4621 | tcg_gen_add_i64(cpu_reg(s, rd), cpu_reg(s, ra), tcg_tmp); | |
4622 | } | |
4623 | } | |
4624 | ||
4625 | if (!sf) { | |
4626 | tcg_gen_ext32u_i64(cpu_reg(s, rd), cpu_reg(s, rd)); | |
4627 | } | |
4628 | ||
4629 | tcg_temp_free_i64(tcg_op1); | |
4630 | tcg_temp_free_i64(tcg_op2); | |
4631 | tcg_temp_free_i64(tcg_tmp); | |
ad7ee8a2 CF |
4632 | } |
4633 | ||
4ce31af4 | 4634 | /* Add/subtract (with carry) |
2fba34f7 RH |
4635 | * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 10 9 5 4 0 |
4636 | * +--+--+--+------------------------+------+-------------+------+-----+ | |
4637 | * |sf|op| S| 1 1 0 1 0 0 0 0 | rm | 0 0 0 0 0 0 | Rn | Rd | | |
4638 | * +--+--+--+------------------------+------+-------------+------+-----+ | |
643dbb07 CF |
4639 | */ |
4640 | ||
ad7ee8a2 CF |
4641 | static void disas_adc_sbc(DisasContext *s, uint32_t insn) |
4642 | { | |
643dbb07 CF |
4643 | unsigned int sf, op, setflags, rm, rn, rd; |
4644 | TCGv_i64 tcg_y, tcg_rn, tcg_rd; | |
4645 | ||
643dbb07 CF |
4646 | sf = extract32(insn, 31, 1); |
4647 | op = extract32(insn, 30, 1); | |
4648 | setflags = extract32(insn, 29, 1); | |
4649 | rm = extract32(insn, 16, 5); | |
4650 | rn = extract32(insn, 5, 5); | |
4651 | rd = extract32(insn, 0, 5); | |
4652 | ||
4653 | tcg_rd = cpu_reg(s, rd); | |
4654 | tcg_rn = cpu_reg(s, rn); | |
4655 | ||
4656 | if (op) { | |
4657 | tcg_y = new_tmp_a64(s); | |
4658 | tcg_gen_not_i64(tcg_y, cpu_reg(s, rm)); | |
4659 | } else { | |
4660 | tcg_y = cpu_reg(s, rm); | |
4661 | } | |
4662 | ||
4663 | if (setflags) { | |
4664 | gen_adc_CC(sf, tcg_rd, tcg_rn, tcg_y); | |
4665 | } else { | |
4666 | gen_adc(sf, tcg_rd, tcg_rn, tcg_y); | |
4667 | } | |
ad7ee8a2 CF |
4668 | } |
4669 | ||
b89d9c98 RH |
4670 | /* |
4671 | * Rotate right into flags | |
4672 | * 31 30 29 21 15 10 5 4 0 | |
4673 | * +--+--+--+-----------------+--------+-----------+------+--+------+ | |
4674 | * |sf|op| S| 1 1 0 1 0 0 0 0 | imm6 | 0 0 0 0 1 | Rn |o2| mask | | |
4675 | * +--+--+--+-----------------+--------+-----------+------+--+------+ | |
4676 | */ | |
4677 | static void disas_rotate_right_into_flags(DisasContext *s, uint32_t insn) | |
4678 | { | |
4679 | int mask = extract32(insn, 0, 4); | |
4680 | int o2 = extract32(insn, 4, 1); | |
4681 | int rn = extract32(insn, 5, 5); | |
4682 | int imm6 = extract32(insn, 15, 6); | |
4683 | int sf_op_s = extract32(insn, 29, 3); | |
4684 | TCGv_i64 tcg_rn; | |
4685 | TCGv_i32 nzcv; | |
4686 | ||
4687 | if (sf_op_s != 5 || o2 != 0 || !dc_isar_feature(aa64_condm_4, s)) { | |
4688 | unallocated_encoding(s); | |
4689 | return; | |
4690 | } | |
4691 | ||
4692 | tcg_rn = read_cpu_reg(s, rn, 1); | |
4693 | tcg_gen_rotri_i64(tcg_rn, tcg_rn, imm6); | |
4694 | ||
4695 | nzcv = tcg_temp_new_i32(); | |
4696 | tcg_gen_extrl_i64_i32(nzcv, tcg_rn); | |
4697 | ||
4698 | if (mask & 8) { /* N */ | |
4699 | tcg_gen_shli_i32(cpu_NF, nzcv, 31 - 3); | |
4700 | } | |
4701 | if (mask & 4) { /* Z */ | |
4702 | tcg_gen_not_i32(cpu_ZF, nzcv); | |
4703 | tcg_gen_andi_i32(cpu_ZF, cpu_ZF, 4); | |
4704 | } | |
4705 | if (mask & 2) { /* C */ | |
4706 | tcg_gen_extract_i32(cpu_CF, nzcv, 1, 1); | |
4707 | } | |
4708 | if (mask & 1) { /* V */ | |
4709 | tcg_gen_shli_i32(cpu_VF, nzcv, 31 - 0); | |
4710 | } | |
4711 | ||
4712 | tcg_temp_free_i32(nzcv); | |
4713 | } | |
4714 | ||
4715 | /* | |
4716 | * Evaluate into flags | |
4717 | * 31 30 29 21 15 14 10 5 4 0 | |
4718 | * +--+--+--+-----------------+---------+----+---------+------+--+------+ | |
4719 | * |sf|op| S| 1 1 0 1 0 0 0 0 | opcode2 | sz | 0 0 1 0 | Rn |o3| mask | | |
4720 | * +--+--+--+-----------------+---------+----+---------+------+--+------+ | |
4721 | */ | |
4722 | static void disas_evaluate_into_flags(DisasContext *s, uint32_t insn) | |
4723 | { | |
4724 | int o3_mask = extract32(insn, 0, 5); | |
4725 | int rn = extract32(insn, 5, 5); | |
4726 | int o2 = extract32(insn, 15, 6); | |
4727 | int sz = extract32(insn, 14, 1); | |
4728 | int sf_op_s = extract32(insn, 29, 3); | |
4729 | TCGv_i32 tmp; | |
4730 | int shift; | |
4731 | ||
4732 | if (sf_op_s != 1 || o2 != 0 || o3_mask != 0xd || | |
4733 | !dc_isar_feature(aa64_condm_4, s)) { | |
4734 | unallocated_encoding(s); | |
4735 | return; | |
4736 | } | |
4737 | shift = sz ? 16 : 24; /* SETF16 or SETF8 */ | |
4738 | ||
4739 | tmp = tcg_temp_new_i32(); | |
4740 | tcg_gen_extrl_i64_i32(tmp, cpu_reg(s, rn)); | |
4741 | tcg_gen_shli_i32(cpu_NF, tmp, shift); | |
4742 | tcg_gen_shli_i32(cpu_VF, tmp, shift - 1); | |
4743 | tcg_gen_mov_i32(cpu_ZF, cpu_NF); | |
4744 | tcg_gen_xor_i32(cpu_VF, cpu_VF, cpu_NF); | |
4745 | tcg_temp_free_i32(tmp); | |
4746 | } | |
4747 | ||
4ce31af4 | 4748 | /* Conditional compare (immediate / register) |
750813cf CF |
4749 | * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0 |
4750 | * +--+--+--+------------------------+--------+------+----+--+------+--+-----+ | |
4751 | * |sf|op| S| 1 1 0 1 0 0 1 0 |imm5/rm | cond |i/r |o2| Rn |o3|nzcv | | |
4752 | * +--+--+--+------------------------+--------+------+----+--+------+--+-----+ | |
4753 | * [1] y [0] [0] | |
4754 | */ | |
4755 | static void disas_cc(DisasContext *s, uint32_t insn) | |
ad7ee8a2 | 4756 | { |
750813cf | 4757 | unsigned int sf, op, y, cond, rn, nzcv, is_imm; |
7dd03d77 | 4758 | TCGv_i32 tcg_t0, tcg_t1, tcg_t2; |
750813cf | 4759 | TCGv_i64 tcg_tmp, tcg_y, tcg_rn; |
7dd03d77 | 4760 | DisasCompare c; |
ad7ee8a2 | 4761 | |
750813cf CF |
4762 | if (!extract32(insn, 29, 1)) { |
4763 | unallocated_encoding(s); | |
4764 | return; | |
4765 | } | |
4766 | if (insn & (1 << 10 | 1 << 4)) { | |
4767 | unallocated_encoding(s); | |
4768 | return; | |
4769 | } | |
4770 | sf = extract32(insn, 31, 1); | |
4771 | op = extract32(insn, 30, 1); | |
4772 | is_imm = extract32(insn, 11, 1); | |
4773 | y = extract32(insn, 16, 5); /* y = rm (reg) or imm5 (imm) */ | |
4774 | cond = extract32(insn, 12, 4); | |
4775 | rn = extract32(insn, 5, 5); | |
4776 | nzcv = extract32(insn, 0, 4); | |
4777 | ||
7dd03d77 RH |
4778 | /* Set T0 = !COND. */ |
4779 | tcg_t0 = tcg_temp_new_i32(); | |
4780 | arm_test_cc(&c, cond); | |
4781 | tcg_gen_setcondi_i32(tcg_invert_cond(c.cond), tcg_t0, c.value, 0); | |
4782 | arm_free_cc(&c); | |
4783 | ||
4784 | /* Load the arguments for the new comparison. */ | |
750813cf CF |
4785 | if (is_imm) { |
4786 | tcg_y = new_tmp_a64(s); | |
4787 | tcg_gen_movi_i64(tcg_y, y); | |
4788 | } else { | |
4789 | tcg_y = cpu_reg(s, y); | |
4790 | } | |
4791 | tcg_rn = cpu_reg(s, rn); | |
4792 | ||
7dd03d77 | 4793 | /* Set the flags for the new comparison. */ |
750813cf CF |
4794 | tcg_tmp = tcg_temp_new_i64(); |
4795 | if (op) { | |
4796 | gen_sub_CC(sf, tcg_tmp, tcg_rn, tcg_y); | |
4797 | } else { | |
4798 | gen_add_CC(sf, tcg_tmp, tcg_rn, tcg_y); | |
4799 | } | |
4800 | tcg_temp_free_i64(tcg_tmp); | |
4801 | ||
7dd03d77 RH |
4802 | /* If COND was false, force the flags to #nzcv. Compute two masks |
4803 | * to help with this: T1 = (COND ? 0 : -1), T2 = (COND ? -1 : 0). | |
4804 | * For tcg hosts that support ANDC, we can make do with just T1. | |
4805 | * In either case, allow the tcg optimizer to delete any unused mask. | |
4806 | */ | |
4807 | tcg_t1 = tcg_temp_new_i32(); | |
4808 | tcg_t2 = tcg_temp_new_i32(); | |
4809 | tcg_gen_neg_i32(tcg_t1, tcg_t0); | |
4810 | tcg_gen_subi_i32(tcg_t2, tcg_t0, 1); | |
4811 | ||
4812 | if (nzcv & 8) { /* N */ | |
4813 | tcg_gen_or_i32(cpu_NF, cpu_NF, tcg_t1); | |
4814 | } else { | |
4815 | if (TCG_TARGET_HAS_andc_i32) { | |
4816 | tcg_gen_andc_i32(cpu_NF, cpu_NF, tcg_t1); | |
4817 | } else { | |
4818 | tcg_gen_and_i32(cpu_NF, cpu_NF, tcg_t2); | |
4819 | } | |
4820 | } | |
4821 | if (nzcv & 4) { /* Z */ | |
4822 | if (TCG_TARGET_HAS_andc_i32) { | |
4823 | tcg_gen_andc_i32(cpu_ZF, cpu_ZF, tcg_t1); | |
4824 | } else { | |
4825 | tcg_gen_and_i32(cpu_ZF, cpu_ZF, tcg_t2); | |
4826 | } | |
4827 | } else { | |
4828 | tcg_gen_or_i32(cpu_ZF, cpu_ZF, tcg_t0); | |
4829 | } | |
4830 | if (nzcv & 2) { /* C */ | |
4831 | tcg_gen_or_i32(cpu_CF, cpu_CF, tcg_t0); | |
4832 | } else { | |
4833 | if (TCG_TARGET_HAS_andc_i32) { | |
4834 | tcg_gen_andc_i32(cpu_CF, cpu_CF, tcg_t1); | |
4835 | } else { | |
4836 | tcg_gen_and_i32(cpu_CF, cpu_CF, tcg_t2); | |
4837 | } | |
4838 | } | |
4839 | if (nzcv & 1) { /* V */ | |
4840 | tcg_gen_or_i32(cpu_VF, cpu_VF, tcg_t1); | |
4841 | } else { | |
4842 | if (TCG_TARGET_HAS_andc_i32) { | |
4843 | tcg_gen_andc_i32(cpu_VF, cpu_VF, tcg_t1); | |
4844 | } else { | |
4845 | tcg_gen_and_i32(cpu_VF, cpu_VF, tcg_t2); | |
4846 | } | |
750813cf | 4847 | } |
7dd03d77 RH |
4848 | tcg_temp_free_i32(tcg_t0); |
4849 | tcg_temp_free_i32(tcg_t1); | |
4850 | tcg_temp_free_i32(tcg_t2); | |
ad7ee8a2 CF |
4851 | } |
4852 | ||
4ce31af4 | 4853 | /* Conditional select |
e952d8c7 CF |
4854 | * 31 30 29 28 21 20 16 15 12 11 10 9 5 4 0 |
4855 | * +----+----+---+-----------------+------+------+-----+------+------+ | |
4856 | * | sf | op | S | 1 1 0 1 0 1 0 0 | Rm | cond | op2 | Rn | Rd | | |
4857 | * +----+----+---+-----------------+------+------+-----+------+------+ | |
4858 | */ | |
ad7ee8a2 CF |
4859 | static void disas_cond_select(DisasContext *s, uint32_t insn) |
4860 | { | |
e952d8c7 | 4861 | unsigned int sf, else_inv, rm, cond, else_inc, rn, rd; |
259cb684 RH |
4862 | TCGv_i64 tcg_rd, zero; |
4863 | DisasCompare64 c; | |
e952d8c7 CF |
4864 | |
4865 | if (extract32(insn, 29, 1) || extract32(insn, 11, 1)) { | |
4866 | /* S == 1 or op2<1> == 1 */ | |
4867 | unallocated_encoding(s); | |
4868 | return; | |
4869 | } | |
4870 | sf = extract32(insn, 31, 1); | |
4871 | else_inv = extract32(insn, 30, 1); | |
4872 | rm = extract32(insn, 16, 5); | |
4873 | cond = extract32(insn, 12, 4); | |
4874 | else_inc = extract32(insn, 10, 1); | |
4875 | rn = extract32(insn, 5, 5); | |
4876 | rd = extract32(insn, 0, 5); | |
4877 | ||
e952d8c7 CF |
4878 | tcg_rd = cpu_reg(s, rd); |
4879 | ||
259cb684 RH |
4880 | a64_test_cc(&c, cond); |
4881 | zero = tcg_const_i64(0); | |
e952d8c7 | 4882 | |
259cb684 RH |
4883 | if (rn == 31 && rm == 31 && (else_inc ^ else_inv)) { |
4884 | /* CSET & CSETM. */ | |
4885 | tcg_gen_setcond_i64(tcg_invert_cond(c.cond), tcg_rd, c.value, zero); | |
4886 | if (else_inv) { | |
4887 | tcg_gen_neg_i64(tcg_rd, tcg_rd); | |
4888 | } | |
4889 | } else { | |
4890 | TCGv_i64 t_true = cpu_reg(s, rn); | |
4891 | TCGv_i64 t_false = read_cpu_reg(s, rm, 1); | |
e952d8c7 | 4892 | if (else_inv && else_inc) { |
259cb684 | 4893 | tcg_gen_neg_i64(t_false, t_false); |
e952d8c7 | 4894 | } else if (else_inv) { |
259cb684 | 4895 | tcg_gen_not_i64(t_false, t_false); |
e952d8c7 | 4896 | } else if (else_inc) { |
259cb684 | 4897 | tcg_gen_addi_i64(t_false, t_false, 1); |
e952d8c7 | 4898 | } |
259cb684 RH |
4899 | tcg_gen_movcond_i64(c.cond, tcg_rd, c.value, zero, t_true, t_false); |
4900 | } | |
4901 | ||
4902 | tcg_temp_free_i64(zero); | |
4903 | a64_free_cc(&c); | |
4904 | ||
4905 | if (!sf) { | |
4906 | tcg_gen_ext32u_i64(tcg_rd, tcg_rd); | |
e952d8c7 | 4907 | } |
ad7ee8a2 CF |
4908 | } |
4909 | ||
680ead21 CF |
4910 | static void handle_clz(DisasContext *s, unsigned int sf, |
4911 | unsigned int rn, unsigned int rd) | |
4912 | { | |
4913 | TCGv_i64 tcg_rd, tcg_rn; | |
4914 | tcg_rd = cpu_reg(s, rd); | |
4915 | tcg_rn = cpu_reg(s, rn); | |
4916 | ||
4917 | if (sf) { | |
7539a012 | 4918 | tcg_gen_clzi_i64(tcg_rd, tcg_rn, 64); |
680ead21 CF |
4919 | } else { |
4920 | TCGv_i32 tcg_tmp32 = tcg_temp_new_i32(); | |
ecc7b3aa | 4921 | tcg_gen_extrl_i64_i32(tcg_tmp32, tcg_rn); |
7539a012 | 4922 | tcg_gen_clzi_i32(tcg_tmp32, tcg_tmp32, 32); |
680ead21 CF |
4923 | tcg_gen_extu_i32_i64(tcg_rd, tcg_tmp32); |
4924 | tcg_temp_free_i32(tcg_tmp32); | |
4925 | } | |
4926 | } | |
4927 | ||
e80c5020 CF |
4928 | static void handle_cls(DisasContext *s, unsigned int sf, |
4929 | unsigned int rn, unsigned int rd) | |
4930 | { | |
4931 | TCGv_i64 tcg_rd, tcg_rn; | |
4932 | tcg_rd = cpu_reg(s, rd); | |
4933 | tcg_rn = cpu_reg(s, rn); | |
4934 | ||
4935 | if (sf) { | |
bc21dbcc | 4936 | tcg_gen_clrsb_i64(tcg_rd, tcg_rn); |
e80c5020 CF |
4937 | } else { |
4938 | TCGv_i32 tcg_tmp32 = tcg_temp_new_i32(); | |
ecc7b3aa | 4939 | tcg_gen_extrl_i64_i32(tcg_tmp32, tcg_rn); |
bc21dbcc | 4940 | tcg_gen_clrsb_i32(tcg_tmp32, tcg_tmp32); |
e80c5020 CF |
4941 | tcg_gen_extu_i32_i64(tcg_rd, tcg_tmp32); |
4942 | tcg_temp_free_i32(tcg_tmp32); | |
4943 | } | |
4944 | } | |
4945 | ||
82e14b02 AG |
4946 | static void handle_rbit(DisasContext *s, unsigned int sf, |
4947 | unsigned int rn, unsigned int rd) | |
4948 | { | |
4949 | TCGv_i64 tcg_rd, tcg_rn; | |
4950 | tcg_rd = cpu_reg(s, rd); | |
4951 | tcg_rn = cpu_reg(s, rn); | |
4952 | ||
4953 | if (sf) { | |
4954 | gen_helper_rbit64(tcg_rd, tcg_rn); | |
4955 | } else { | |
4956 | TCGv_i32 tcg_tmp32 = tcg_temp_new_i32(); | |
ecc7b3aa | 4957 | tcg_gen_extrl_i64_i32(tcg_tmp32, tcg_rn); |
82e14b02 AG |
4958 | gen_helper_rbit(tcg_tmp32, tcg_tmp32); |
4959 | tcg_gen_extu_i32_i64(tcg_rd, tcg_tmp32); | |
4960 | tcg_temp_free_i32(tcg_tmp32); | |
4961 | } | |
4962 | } | |
4963 | ||
4ce31af4 | 4964 | /* REV with sf==1, opcode==3 ("REV64") */ |
45323209 CF |
4965 | static void handle_rev64(DisasContext *s, unsigned int sf, |
4966 | unsigned int rn, unsigned int rd) | |
4967 | { | |
4968 | if (!sf) { | |
4969 | unallocated_encoding(s); | |
4970 | return; | |
4971 | } | |
4972 | tcg_gen_bswap64_i64(cpu_reg(s, rd), cpu_reg(s, rn)); | |
4973 | } | |
4974 | ||
4ce31af4 PM |
4975 | /* REV with sf==0, opcode==2 |
4976 | * REV32 (sf==1, opcode==2) | |
45323209 CF |
4977 | */ |
4978 | static void handle_rev32(DisasContext *s, unsigned int sf, | |
4979 | unsigned int rn, unsigned int rd) | |
4980 | { | |
4981 | TCGv_i64 tcg_rd = cpu_reg(s, rd); | |
4982 | ||
4983 | if (sf) { | |
4984 | TCGv_i64 tcg_tmp = tcg_temp_new_i64(); | |
4985 | TCGv_i64 tcg_rn = read_cpu_reg(s, rn, sf); | |
4986 | ||
4987 | /* bswap32_i64 requires zero high word */ | |
4988 | tcg_gen_ext32u_i64(tcg_tmp, tcg_rn); | |
4989 | tcg_gen_bswap32_i64(tcg_rd, tcg_tmp); | |
4990 | tcg_gen_shri_i64(tcg_tmp, tcg_rn, 32); | |
4991 | tcg_gen_bswap32_i64(tcg_tmp, tcg_tmp); | |
4992 | tcg_gen_concat32_i64(tcg_rd, tcg_rd, tcg_tmp); | |
4993 | ||
4994 | tcg_temp_free_i64(tcg_tmp); | |
4995 | } else { | |
4996 | tcg_gen_ext32u_i64(tcg_rd, cpu_reg(s, rn)); | |
4997 | tcg_gen_bswap32_i64(tcg_rd, tcg_rd); | |
4998 | } | |
4999 | } | |
5000 | ||
4ce31af4 | 5001 | /* REV16 (opcode==1) */ |
45323209 CF |
5002 | static void handle_rev16(DisasContext *s, unsigned int sf, |
5003 | unsigned int rn, unsigned int rd) | |
5004 | { | |
5005 | TCGv_i64 tcg_rd = cpu_reg(s, rd); | |
5006 | TCGv_i64 tcg_tmp = tcg_temp_new_i64(); | |
5007 | TCGv_i64 tcg_rn = read_cpu_reg(s, rn, sf); | |
abb1066d | 5008 | TCGv_i64 mask = tcg_const_i64(sf ? 0x00ff00ff00ff00ffull : 0x00ff00ff); |
45323209 | 5009 | |
abb1066d RH |
5010 | tcg_gen_shri_i64(tcg_tmp, tcg_rn, 8); |
5011 | tcg_gen_and_i64(tcg_rd, tcg_rn, mask); | |
5012 | tcg_gen_and_i64(tcg_tmp, tcg_tmp, mask); | |
5013 | tcg_gen_shli_i64(tcg_rd, tcg_rd, 8); | |
5014 | tcg_gen_or_i64(tcg_rd, tcg_rd, tcg_tmp); | |
45323209 | 5015 | |
e4256c3c | 5016 | tcg_temp_free_i64(mask); |
45323209 CF |
5017 | tcg_temp_free_i64(tcg_tmp); |
5018 | } | |
5019 | ||
4ce31af4 | 5020 | /* Data-processing (1 source) |
680ead21 CF |
5021 | * 31 30 29 28 21 20 16 15 10 9 5 4 0 |
5022 | * +----+---+---+-----------------+---------+--------+------+------+ | |
5023 | * | sf | 1 | S | 1 1 0 1 0 1 1 0 | opcode2 | opcode | Rn | Rd | | |
5024 | * +----+---+---+-----------------+---------+--------+------+------+ | |
5025 | */ | |
ad7ee8a2 CF |
5026 | static void disas_data_proc_1src(DisasContext *s, uint32_t insn) |
5027 | { | |
18de2813 | 5028 | unsigned int sf, opcode, opcode2, rn, rd; |
95ebd99d | 5029 | TCGv_i64 tcg_rd; |
680ead21 | 5030 | |
18de2813 | 5031 | if (extract32(insn, 29, 1)) { |
680ead21 CF |
5032 | unallocated_encoding(s); |
5033 | return; | |
5034 | } | |
5035 | ||
5036 | sf = extract32(insn, 31, 1); | |
5037 | opcode = extract32(insn, 10, 6); | |
18de2813 | 5038 | opcode2 = extract32(insn, 16, 5); |
680ead21 CF |
5039 | rn = extract32(insn, 5, 5); |
5040 | rd = extract32(insn, 0, 5); | |
5041 | ||
18de2813 RH |
5042 | #define MAP(SF, O2, O1) ((SF) | (O1 << 1) | (O2 << 7)) |
5043 | ||
5044 | switch (MAP(sf, opcode2, opcode)) { | |
5045 | case MAP(0, 0x00, 0x00): /* RBIT */ | |
5046 | case MAP(1, 0x00, 0x00): | |
82e14b02 AG |
5047 | handle_rbit(s, sf, rn, rd); |
5048 | break; | |
18de2813 RH |
5049 | case MAP(0, 0x00, 0x01): /* REV16 */ |
5050 | case MAP(1, 0x00, 0x01): | |
45323209 CF |
5051 | handle_rev16(s, sf, rn, rd); |
5052 | break; | |
18de2813 RH |
5053 | case MAP(0, 0x00, 0x02): /* REV/REV32 */ |
5054 | case MAP(1, 0x00, 0x02): | |
45323209 CF |
5055 | handle_rev32(s, sf, rn, rd); |
5056 | break; | |
18de2813 | 5057 | case MAP(1, 0x00, 0x03): /* REV64 */ |
45323209 | 5058 | handle_rev64(s, sf, rn, rd); |
680ead21 | 5059 | break; |
18de2813 RH |
5060 | case MAP(0, 0x00, 0x04): /* CLZ */ |
5061 | case MAP(1, 0x00, 0x04): | |
680ead21 CF |
5062 | handle_clz(s, sf, rn, rd); |
5063 | break; | |
18de2813 RH |
5064 | case MAP(0, 0x00, 0x05): /* CLS */ |
5065 | case MAP(1, 0x00, 0x05): | |
e80c5020 | 5066 | handle_cls(s, sf, rn, rd); |
680ead21 | 5067 | break; |
95ebd99d RH |
5068 | case MAP(1, 0x01, 0x00): /* PACIA */ |
5069 | if (s->pauth_active) { | |
5070 | tcg_rd = cpu_reg(s, rd); | |
5071 | gen_helper_pacia(tcg_rd, cpu_env, tcg_rd, cpu_reg_sp(s, rn)); | |
5072 | } else if (!dc_isar_feature(aa64_pauth, s)) { | |
5073 | goto do_unallocated; | |
5074 | } | |
5075 | break; | |
5076 | case MAP(1, 0x01, 0x01): /* PACIB */ | |
5077 | if (s->pauth_active) { | |
5078 | tcg_rd = cpu_reg(s, rd); | |
5079 | gen_helper_pacib(tcg_rd, cpu_env, tcg_rd, cpu_reg_sp(s, rn)); | |
5080 | } else if (!dc_isar_feature(aa64_pauth, s)) { | |
5081 | goto do_unallocated; | |
5082 | } | |
5083 | break; | |
5084 | case MAP(1, 0x01, 0x02): /* PACDA */ | |
5085 | if (s->pauth_active) { | |
5086 | tcg_rd = cpu_reg(s, rd); | |
5087 | gen_helper_pacda(tcg_rd, cpu_env, tcg_rd, cpu_reg_sp(s, rn)); | |
5088 | } else if (!dc_isar_feature(aa64_pauth, s)) { | |
5089 | goto do_unallocated; | |
5090 | } | |
5091 | break; | |
5092 | case MAP(1, 0x01, 0x03): /* PACDB */ | |
5093 | if (s->pauth_active) { | |
5094 | tcg_rd = cpu_reg(s, rd); | |
5095 | gen_helper_pacdb(tcg_rd, cpu_env, tcg_rd, cpu_reg_sp(s, rn)); | |
5096 | } else if (!dc_isar_feature(aa64_pauth, s)) { | |
5097 | goto do_unallocated; | |
5098 | } | |
5099 | break; | |
5100 | case MAP(1, 0x01, 0x04): /* AUTIA */ | |
5101 | if (s->pauth_active) { | |
5102 | tcg_rd = cpu_reg(s, rd); | |
5103 | gen_helper_autia(tcg_rd, cpu_env, tcg_rd, cpu_reg_sp(s, rn)); | |
5104 | } else if (!dc_isar_feature(aa64_pauth, s)) { | |
5105 | goto do_unallocated; | |
5106 | } | |
5107 | break; | |
5108 | case MAP(1, 0x01, 0x05): /* AUTIB */ | |
5109 | if (s->pauth_active) { | |
5110 | tcg_rd = cpu_reg(s, rd); | |
5111 | gen_helper_autib(tcg_rd, cpu_env, tcg_rd, cpu_reg_sp(s, rn)); | |
5112 | } else if (!dc_isar_feature(aa64_pauth, s)) { | |
5113 | goto do_unallocated; | |
5114 | } | |
5115 | break; | |
5116 | case MAP(1, 0x01, 0x06): /* AUTDA */ | |
5117 | if (s->pauth_active) { | |
5118 | tcg_rd = cpu_reg(s, rd); | |
5119 | gen_helper_autda(tcg_rd, cpu_env, tcg_rd, cpu_reg_sp(s, rn)); | |
5120 | } else if (!dc_isar_feature(aa64_pauth, s)) { | |
5121 | goto do_unallocated; | |
5122 | } | |
5123 | break; | |
5124 | case MAP(1, 0x01, 0x07): /* AUTDB */ | |
5125 | if (s->pauth_active) { | |
5126 | tcg_rd = cpu_reg(s, rd); | |
5127 | gen_helper_autdb(tcg_rd, cpu_env, tcg_rd, cpu_reg_sp(s, rn)); | |
5128 | } else if (!dc_isar_feature(aa64_pauth, s)) { | |
5129 | goto do_unallocated; | |
5130 | } | |
5131 | break; | |
5132 | case MAP(1, 0x01, 0x08): /* PACIZA */ | |
5133 | if (!dc_isar_feature(aa64_pauth, s) || rn != 31) { | |
5134 | goto do_unallocated; | |
5135 | } else if (s->pauth_active) { | |
5136 | tcg_rd = cpu_reg(s, rd); | |
5137 | gen_helper_pacia(tcg_rd, cpu_env, tcg_rd, new_tmp_a64_zero(s)); | |
5138 | } | |
5139 | break; | |
5140 | case MAP(1, 0x01, 0x09): /* PACIZB */ | |
5141 | if (!dc_isar_feature(aa64_pauth, s) || rn != 31) { | |
5142 | goto do_unallocated; | |
5143 | } else if (s->pauth_active) { | |
5144 | tcg_rd = cpu_reg(s, rd); | |
5145 | gen_helper_pacib(tcg_rd, cpu_env, tcg_rd, new_tmp_a64_zero(s)); | |
5146 | } | |
5147 | break; | |
5148 | case MAP(1, 0x01, 0x0a): /* PACDZA */ | |
5149 | if (!dc_isar_feature(aa64_pauth, s) || rn != 31) { | |
5150 | goto do_unallocated; | |
5151 | } else if (s->pauth_active) { | |
5152 | tcg_rd = cpu_reg(s, rd); | |
5153 | gen_helper_pacda(tcg_rd, cpu_env, tcg_rd, new_tmp_a64_zero(s)); | |
5154 | } | |
5155 | break; | |
5156 | case MAP(1, 0x01, 0x0b): /* PACDZB */ | |
5157 | if (!dc_isar_feature(aa64_pauth, s) || rn != 31) { | |
5158 | goto do_unallocated; | |
5159 | } else if (s->pauth_active) { | |
5160 | tcg_rd = cpu_reg(s, rd); | |
5161 | gen_helper_pacdb(tcg_rd, cpu_env, tcg_rd, new_tmp_a64_zero(s)); | |
5162 | } | |
5163 | break; | |
5164 | case MAP(1, 0x01, 0x0c): /* AUTIZA */ | |
5165 | if (!dc_isar_feature(aa64_pauth, s) || rn != 31) { | |
5166 | goto do_unallocated; | |
5167 | } else if (s->pauth_active) { | |
5168 | tcg_rd = cpu_reg(s, rd); | |
5169 | gen_helper_autia(tcg_rd, cpu_env, tcg_rd, new_tmp_a64_zero(s)); | |
5170 | } | |
5171 | break; | |
5172 | case MAP(1, 0x01, 0x0d): /* AUTIZB */ | |
5173 | if (!dc_isar_feature(aa64_pauth, s) || rn != 31) { | |
5174 | goto do_unallocated; | |
5175 | } else if (s->pauth_active) { | |
5176 | tcg_rd = cpu_reg(s, rd); | |
5177 | gen_helper_autib(tcg_rd, cpu_env, tcg_rd, new_tmp_a64_zero(s)); | |
5178 | } | |
5179 | break; | |
5180 | case MAP(1, 0x01, 0x0e): /* AUTDZA */ | |
5181 | if (!dc_isar_feature(aa64_pauth, s) || rn != 31) { | |
5182 | goto do_unallocated; | |
5183 | } else if (s->pauth_active) { | |
5184 | tcg_rd = cpu_reg(s, rd); | |
5185 | gen_helper_autda(tcg_rd, cpu_env, tcg_rd, new_tmp_a64_zero(s)); | |
5186 | } | |
5187 | break; | |
5188 | case MAP(1, 0x01, 0x0f): /* AUTDZB */ | |
5189 | if (!dc_isar_feature(aa64_pauth, s) || rn != 31) { | |
5190 | goto do_unallocated; | |
5191 | } else if (s->pauth_active) { | |
5192 | tcg_rd = cpu_reg(s, rd); | |
5193 | gen_helper_autdb(tcg_rd, cpu_env, tcg_rd, new_tmp_a64_zero(s)); | |
5194 | } | |
5195 | break; | |
5196 | case MAP(1, 0x01, 0x10): /* XPACI */ | |
5197 | if (!dc_isar_feature(aa64_pauth, s) || rn != 31) { | |
5198 | goto do_unallocated; | |
5199 | } else if (s->pauth_active) { | |
5200 | tcg_rd = cpu_reg(s, rd); | |
5201 | gen_helper_xpaci(tcg_rd, cpu_env, tcg_rd); | |
5202 | } | |
5203 | break; | |
5204 | case MAP(1, 0x01, 0x11): /* XPACD */ | |
5205 | if (!dc_isar_feature(aa64_pauth, s) || rn != 31) { | |
5206 | goto do_unallocated; | |
5207 | } else if (s->pauth_active) { | |
5208 | tcg_rd = cpu_reg(s, rd); | |
5209 | gen_helper_xpacd(tcg_rd, cpu_env, tcg_rd); | |
5210 | } | |
5211 | break; | |
18de2813 | 5212 | default: |
95ebd99d | 5213 | do_unallocated: |
18de2813 RH |
5214 | unallocated_encoding(s); |
5215 | break; | |
680ead21 | 5216 | } |
18de2813 RH |
5217 | |
5218 | #undef MAP | |
ad7ee8a2 CF |
5219 | } |
5220 | ||
8220e911 AG |
5221 | static void handle_div(DisasContext *s, bool is_signed, unsigned int sf, |
5222 | unsigned int rm, unsigned int rn, unsigned int rd) | |
5223 | { | |
5224 | TCGv_i64 tcg_n, tcg_m, tcg_rd; | |
5225 | tcg_rd = cpu_reg(s, rd); | |
5226 | ||
5227 | if (!sf && is_signed) { | |
5228 | tcg_n = new_tmp_a64(s); | |
5229 | tcg_m = new_tmp_a64(s); | |
5230 | tcg_gen_ext32s_i64(tcg_n, cpu_reg(s, rn)); | |
5231 | tcg_gen_ext32s_i64(tcg_m, cpu_reg(s, rm)); | |
5232 | } else { | |
5233 | tcg_n = read_cpu_reg(s, rn, sf); | |
5234 | tcg_m = read_cpu_reg(s, rm, sf); | |
5235 | } | |
5236 | ||
5237 | if (is_signed) { | |
5238 | gen_helper_sdiv64(tcg_rd, tcg_n, tcg_m); | |
5239 | } else { | |
5240 | gen_helper_udiv64(tcg_rd, tcg_n, tcg_m); | |
5241 | } | |
5242 | ||
5243 | if (!sf) { /* zero extend final result */ | |
5244 | tcg_gen_ext32u_i64(tcg_rd, tcg_rd); | |
5245 | } | |
5246 | } | |
5247 | ||
4ce31af4 | 5248 | /* LSLV, LSRV, ASRV, RORV */ |
6c1adc91 AG |
5249 | static void handle_shift_reg(DisasContext *s, |
5250 | enum a64_shift_type shift_type, unsigned int sf, | |
5251 | unsigned int rm, unsigned int rn, unsigned int rd) | |
5252 | { | |
5253 | TCGv_i64 tcg_shift = tcg_temp_new_i64(); | |
5254 | TCGv_i64 tcg_rd = cpu_reg(s, rd); | |
5255 | TCGv_i64 tcg_rn = read_cpu_reg(s, rn, sf); | |
5256 | ||
5257 | tcg_gen_andi_i64(tcg_shift, cpu_reg(s, rm), sf ? 63 : 31); | |
5258 | shift_reg(tcg_rd, tcg_rn, sf, shift_type, tcg_shift); | |
5259 | tcg_temp_free_i64(tcg_shift); | |
5260 | } | |
5261 | ||
130f2e7d PM |
5262 | /* CRC32[BHWX], CRC32C[BHWX] */ |
5263 | static void handle_crc32(DisasContext *s, | |
5264 | unsigned int sf, unsigned int sz, bool crc32c, | |
5265 | unsigned int rm, unsigned int rn, unsigned int rd) | |
5266 | { | |
5267 | TCGv_i64 tcg_acc, tcg_val; | |
5268 | TCGv_i32 tcg_bytes; | |
5269 | ||
962fcbf2 | 5270 | if (!dc_isar_feature(aa64_crc32, s) |
130f2e7d PM |
5271 | || (sf == 1 && sz != 3) |
5272 | || (sf == 0 && sz == 3)) { | |
5273 | unallocated_encoding(s); | |
5274 | return; | |
5275 | } | |
5276 | ||
5277 | if (sz == 3) { | |
5278 | tcg_val = cpu_reg(s, rm); | |
5279 | } else { | |
5280 | uint64_t mask; | |
5281 | switch (sz) { | |
5282 | case 0: | |
5283 | mask = 0xFF; | |
5284 | break; | |
5285 | case 1: | |
5286 | mask = 0xFFFF; | |
5287 | break; | |
5288 | case 2: | |
5289 | mask = 0xFFFFFFFF; | |
5290 | break; | |
5291 | default: | |
5292 | g_assert_not_reached(); | |
5293 | } | |
5294 | tcg_val = new_tmp_a64(s); | |
5295 | tcg_gen_andi_i64(tcg_val, cpu_reg(s, rm), mask); | |
5296 | } | |
5297 | ||
5298 | tcg_acc = cpu_reg(s, rn); | |
5299 | tcg_bytes = tcg_const_i32(1 << sz); | |
5300 | ||
5301 | if (crc32c) { | |
5302 | gen_helper_crc32c_64(cpu_reg(s, rd), tcg_acc, tcg_val, tcg_bytes); | |
5303 | } else { | |
5304 | gen_helper_crc32_64(cpu_reg(s, rd), tcg_acc, tcg_val, tcg_bytes); | |
5305 | } | |
5306 | ||
5307 | tcg_temp_free_i32(tcg_bytes); | |
5308 | } | |
5309 | ||
4ce31af4 | 5310 | /* Data-processing (2 source) |
8220e911 AG |
5311 | * 31 30 29 28 21 20 16 15 10 9 5 4 0 |
5312 | * +----+---+---+-----------------+------+--------+------+------+ | |
5313 | * | sf | 0 | S | 1 1 0 1 0 1 1 0 | Rm | opcode | Rn | Rd | | |
5314 | * +----+---+---+-----------------+------+--------+------+------+ | |
5315 | */ | |
ad7ee8a2 CF |
5316 | static void disas_data_proc_2src(DisasContext *s, uint32_t insn) |
5317 | { | |
8220e911 AG |
5318 | unsigned int sf, rm, opcode, rn, rd; |
5319 | sf = extract32(insn, 31, 1); | |
5320 | rm = extract32(insn, 16, 5); | |
5321 | opcode = extract32(insn, 10, 6); | |
5322 | rn = extract32(insn, 5, 5); | |
5323 | rd = extract32(insn, 0, 5); | |
5324 | ||
5325 | if (extract32(insn, 29, 1)) { | |
5326 | unallocated_encoding(s); | |
5327 | return; | |
5328 | } | |
5329 | ||
5330 | switch (opcode) { | |
5331 | case 2: /* UDIV */ | |
5332 | handle_div(s, false, sf, rm, rn, rd); | |
5333 | break; | |
5334 | case 3: /* SDIV */ | |
5335 | handle_div(s, true, sf, rm, rn, rd); | |
5336 | break; | |
da54941f RH |
5337 | case 4: /* IRG */ |
5338 | if (sf == 0 || !dc_isar_feature(aa64_mte_insn_reg, s)) { | |
5339 | goto do_unallocated; | |
5340 | } | |
5341 | if (s->ata) { | |
5342 | gen_helper_irg(cpu_reg_sp(s, rd), cpu_env, | |
5343 | cpu_reg_sp(s, rn), cpu_reg(s, rm)); | |
5344 | } else { | |
5345 | gen_address_with_allocation_tag0(cpu_reg_sp(s, rd), | |
5346 | cpu_reg_sp(s, rn)); | |
5347 | } | |
5348 | break; | |
8220e911 | 5349 | case 8: /* LSLV */ |
6c1adc91 AG |
5350 | handle_shift_reg(s, A64_SHIFT_TYPE_LSL, sf, rm, rn, rd); |
5351 | break; | |
8220e911 | 5352 | case 9: /* LSRV */ |
6c1adc91 AG |
5353 | handle_shift_reg(s, A64_SHIFT_TYPE_LSR, sf, rm, rn, rd); |
5354 | break; | |
8220e911 | 5355 | case 10: /* ASRV */ |
6c1adc91 AG |
5356 | handle_shift_reg(s, A64_SHIFT_TYPE_ASR, sf, rm, rn, rd); |
5357 | break; | |
8220e911 | 5358 | case 11: /* RORV */ |
6c1adc91 AG |
5359 | handle_shift_reg(s, A64_SHIFT_TYPE_ROR, sf, rm, rn, rd); |
5360 | break; | |
b6342a9f RH |
5361 | case 12: /* PACGA */ |
5362 | if (sf == 0 || !dc_isar_feature(aa64_pauth, s)) { | |
5363 | goto do_unallocated; | |
5364 | } | |
5365 | gen_helper_pacga(cpu_reg(s, rd), cpu_env, | |
5366 | cpu_reg(s, rn), cpu_reg_sp(s, rm)); | |
5367 | break; | |
8220e911 AG |
5368 | case 16: |
5369 | case 17: | |
5370 | case 18: | |
5371 | case 19: | |
5372 | case 20: | |
5373 | case 21: | |
5374 | case 22: | |
5375 | case 23: /* CRC32 */ | |
130f2e7d PM |
5376 | { |
5377 | int sz = extract32(opcode, 0, 2); | |
5378 | bool crc32c = extract32(opcode, 2, 1); | |
5379 | handle_crc32(s, sf, sz, crc32c, rm, rn, rd); | |
8220e911 | 5380 | break; |
130f2e7d | 5381 | } |
8220e911 | 5382 | default: |
b6342a9f | 5383 | do_unallocated: |
8220e911 AG |
5384 | unallocated_encoding(s); |
5385 | break; | |
5386 | } | |
ad7ee8a2 CF |
5387 | } |
5388 | ||
2fba34f7 RH |
5389 | /* |
5390 | * Data processing - register | |
5391 | * 31 30 29 28 25 21 20 16 10 0 | |
5392 | * +--+---+--+---+-------+-----+-------+-------+---------+ | |
5393 | * | |op0| |op1| 1 0 1 | op2 | | op3 | | | |
5394 | * +--+---+--+---+-------+-----+-------+-------+---------+ | |
5395 | */ | |
ad7ee8a2 CF |
5396 | static void disas_data_proc_reg(DisasContext *s, uint32_t insn) |
5397 | { | |
2fba34f7 RH |
5398 | int op0 = extract32(insn, 30, 1); |
5399 | int op1 = extract32(insn, 28, 1); | |
5400 | int op2 = extract32(insn, 21, 4); | |
5401 | int op3 = extract32(insn, 10, 6); | |
5402 | ||
5403 | if (!op1) { | |
5404 | if (op2 & 8) { | |
5405 | if (op2 & 1) { | |
5406 | /* Add/sub (extended register) */ | |
5407 | disas_add_sub_ext_reg(s, insn); | |
5408 | } else { | |
5409 | /* Add/sub (shifted register) */ | |
5410 | disas_add_sub_reg(s, insn); | |
5411 | } | |
ad7ee8a2 | 5412 | } else { |
2fba34f7 RH |
5413 | /* Logical (shifted register) */ |
5414 | disas_logic_reg(s, insn); | |
ad7ee8a2 | 5415 | } |
2fba34f7 RH |
5416 | return; |
5417 | } | |
5418 | ||
5419 | switch (op2) { | |
5420 | case 0x0: | |
5421 | switch (op3) { | |
5422 | case 0x00: /* Add/subtract (with carry) */ | |
ad7ee8a2 CF |
5423 | disas_adc_sbc(s, insn); |
5424 | break; | |
2fba34f7 | 5425 | |
b89d9c98 RH |
5426 | case 0x01: /* Rotate right into flags */ |
5427 | case 0x21: | |
5428 | disas_rotate_right_into_flags(s, insn); | |
5429 | break; | |
5430 | ||
5431 | case 0x02: /* Evaluate into flags */ | |
5432 | case 0x12: | |
5433 | case 0x22: | |
5434 | case 0x32: | |
5435 | disas_evaluate_into_flags(s, insn); | |
5436 | break; | |
5437 | ||
ad7ee8a2 | 5438 | default: |
2fba34f7 | 5439 | goto do_unallocated; |
ad7ee8a2 CF |
5440 | } |
5441 | break; | |
2fba34f7 RH |
5442 | |
5443 | case 0x2: /* Conditional compare */ | |
5444 | disas_cc(s, insn); /* both imm and reg forms */ | |
5445 | break; | |
5446 | ||
5447 | case 0x4: /* Conditional select */ | |
5448 | disas_cond_select(s, insn); | |
5449 | break; | |
5450 | ||
5451 | case 0x6: /* Data-processing */ | |
5452 | if (op0) { /* (1 source) */ | |
5453 | disas_data_proc_1src(s, insn); | |
5454 | } else { /* (2 source) */ | |
5455 | disas_data_proc_2src(s, insn); | |
5456 | } | |
5457 | break; | |
5458 | case 0x8 ... 0xf: /* (3 source) */ | |
5459 | disas_data_proc_3src(s, insn); | |
5460 | break; | |
5461 | ||
ad7ee8a2 | 5462 | default: |
2fba34f7 | 5463 | do_unallocated: |
ad7ee8a2 CF |
5464 | unallocated_encoding(s); |
5465 | break; | |
5466 | } | |
5467 | } | |
5468 | ||
7a192925 | 5469 | static void handle_fp_compare(DisasContext *s, int size, |
da7dafe7 CF |
5470 | unsigned int rn, unsigned int rm, |
5471 | bool cmp_with_zero, bool signal_all_nans) | |
5472 | { | |
5473 | TCGv_i64 tcg_flags = tcg_temp_new_i64(); | |
7a192925 | 5474 | TCGv_ptr fpst = get_fpstatus_ptr(size == MO_16); |
da7dafe7 | 5475 | |
7a192925 | 5476 | if (size == MO_64) { |
da7dafe7 CF |
5477 | TCGv_i64 tcg_vn, tcg_vm; |
5478 | ||
5479 | tcg_vn = read_fp_dreg(s, rn); | |
5480 | if (cmp_with_zero) { | |
5481 | tcg_vm = tcg_const_i64(0); | |
5482 | } else { | |
5483 | tcg_vm = read_fp_dreg(s, rm); | |
5484 | } | |
5485 | if (signal_all_nans) { | |
5486 | gen_helper_vfp_cmped_a64(tcg_flags, tcg_vn, tcg_vm, fpst); | |
5487 | } else { | |
5488 | gen_helper_vfp_cmpd_a64(tcg_flags, tcg_vn, tcg_vm, fpst); | |
5489 | } | |
5490 | tcg_temp_free_i64(tcg_vn); | |
5491 | tcg_temp_free_i64(tcg_vm); | |
5492 | } else { | |
7a192925 AB |
5493 | TCGv_i32 tcg_vn = tcg_temp_new_i32(); |
5494 | TCGv_i32 tcg_vm = tcg_temp_new_i32(); | |
da7dafe7 | 5495 | |
7a192925 | 5496 | read_vec_element_i32(s, tcg_vn, rn, 0, size); |
da7dafe7 | 5497 | if (cmp_with_zero) { |
7a192925 | 5498 | tcg_gen_movi_i32(tcg_vm, 0); |
da7dafe7 | 5499 | } else { |
7a192925 | 5500 | read_vec_element_i32(s, tcg_vm, rm, 0, size); |
da7dafe7 | 5501 | } |
7a192925 AB |
5502 | |
5503 | switch (size) { | |
5504 | case MO_32: | |
5505 | if (signal_all_nans) { | |
5506 | gen_helper_vfp_cmpes_a64(tcg_flags, tcg_vn, tcg_vm, fpst); | |
5507 | } else { | |
5508 | gen_helper_vfp_cmps_a64(tcg_flags, tcg_vn, tcg_vm, fpst); | |
5509 | } | |
5510 | break; | |
5511 | case MO_16: | |
5512 | if (signal_all_nans) { | |
5513 | gen_helper_vfp_cmpeh_a64(tcg_flags, tcg_vn, tcg_vm, fpst); | |
5514 | } else { | |
5515 | gen_helper_vfp_cmph_a64(tcg_flags, tcg_vn, tcg_vm, fpst); | |
5516 | } | |
5517 | break; | |
5518 | default: | |
5519 | g_assert_not_reached(); | |
da7dafe7 | 5520 | } |
7a192925 | 5521 | |
da7dafe7 CF |
5522 | tcg_temp_free_i32(tcg_vn); |
5523 | tcg_temp_free_i32(tcg_vm); | |
5524 | } | |
5525 | ||
5526 | tcg_temp_free_ptr(fpst); | |
5527 | ||
5528 | gen_set_nzcv(tcg_flags); | |
5529 | ||
5530 | tcg_temp_free_i64(tcg_flags); | |
5531 | } | |
5532 | ||
4ce31af4 | 5533 | /* Floating point compare |
faa0ba46 PM |
5534 | * 31 30 29 28 24 23 22 21 20 16 15 14 13 10 9 5 4 0 |
5535 | * +---+---+---+-----------+------+---+------+-----+---------+------+-------+ | |
5536 | * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | op | 1 0 0 0 | Rn | op2 | | |
5537 | * +---+---+---+-----------+------+---+------+-----+---------+------+-------+ | |
5538 | */ | |
5539 | static void disas_fp_compare(DisasContext *s, uint32_t insn) | |
5540 | { | |
da7dafe7 | 5541 | unsigned int mos, type, rm, op, rn, opc, op2r; |
7a192925 | 5542 | int size; |
da7dafe7 CF |
5543 | |
5544 | mos = extract32(insn, 29, 3); | |
7a192925 | 5545 | type = extract32(insn, 22, 2); |
da7dafe7 CF |
5546 | rm = extract32(insn, 16, 5); |
5547 | op = extract32(insn, 14, 2); | |
5548 | rn = extract32(insn, 5, 5); | |
5549 | opc = extract32(insn, 3, 2); | |
5550 | op2r = extract32(insn, 0, 3); | |
5551 | ||
7a192925 AB |
5552 | if (mos || op || op2r) { |
5553 | unallocated_encoding(s); | |
5554 | return; | |
5555 | } | |
5556 | ||
5557 | switch (type) { | |
5558 | case 0: | |
5559 | size = MO_32; | |
5560 | break; | |
5561 | case 1: | |
5562 | size = MO_64; | |
5563 | break; | |
5564 | case 3: | |
5565 | size = MO_16; | |
5763190f | 5566 | if (dc_isar_feature(aa64_fp16, s)) { |
7a192925 AB |
5567 | break; |
5568 | } | |
5569 | /* fallthru */ | |
5570 | default: | |
da7dafe7 CF |
5571 | unallocated_encoding(s); |
5572 | return; | |
5573 | } | |
5574 | ||
8c6afa6a PM |
5575 | if (!fp_access_check(s)) { |
5576 | return; | |
5577 | } | |
5578 | ||
7a192925 | 5579 | handle_fp_compare(s, size, rn, rm, opc & 1, opc & 2); |
faa0ba46 PM |
5580 | } |
5581 | ||
4ce31af4 | 5582 | /* Floating point conditional compare |
faa0ba46 PM |
5583 | * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0 |
5584 | * +---+---+---+-----------+------+---+------+------+-----+------+----+------+ | |
5585 | * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 0 1 | Rn | op | nzcv | | |
5586 | * +---+---+---+-----------+------+---+------+------+-----+------+----+------+ | |
5587 | */ | |
5588 | static void disas_fp_ccomp(DisasContext *s, uint32_t insn) | |
5589 | { | |
513f1d76 CF |
5590 | unsigned int mos, type, rm, cond, rn, op, nzcv; |
5591 | TCGv_i64 tcg_flags; | |
42a268c2 | 5592 | TCGLabel *label_continue = NULL; |
7a192925 | 5593 | int size; |
513f1d76 CF |
5594 | |
5595 | mos = extract32(insn, 29, 3); | |
7a192925 | 5596 | type = extract32(insn, 22, 2); |
513f1d76 CF |
5597 | rm = extract32(insn, 16, 5); |
5598 | cond = extract32(insn, 12, 4); | |
5599 | rn = extract32(insn, 5, 5); | |
5600 | op = extract32(insn, 4, 1); | |
5601 | nzcv = extract32(insn, 0, 4); | |
5602 | ||
7a192925 AB |
5603 | if (mos) { |
5604 | unallocated_encoding(s); | |
5605 | return; | |
5606 | } | |
5607 | ||
5608 | switch (type) { | |
5609 | case 0: | |
5610 | size = MO_32; | |
5611 | break; | |
5612 | case 1: | |
5613 | size = MO_64; | |
5614 | break; | |
5615 | case 3: | |
5616 | size = MO_16; | |
5763190f | 5617 | if (dc_isar_feature(aa64_fp16, s)) { |
7a192925 AB |
5618 | break; |
5619 | } | |
5620 | /* fallthru */ | |
5621 | default: | |
513f1d76 CF |
5622 | unallocated_encoding(s); |
5623 | return; | |
5624 | } | |
5625 | ||
8c6afa6a PM |
5626 | if (!fp_access_check(s)) { |
5627 | return; | |
5628 | } | |
5629 | ||
513f1d76 | 5630 | if (cond < 0x0e) { /* not always */ |
42a268c2 | 5631 | TCGLabel *label_match = gen_new_label(); |
513f1d76 CF |
5632 | label_continue = gen_new_label(); |
5633 | arm_gen_test_cc(cond, label_match); | |
5634 | /* nomatch: */ | |
5635 | tcg_flags = tcg_const_i64(nzcv << 28); | |
5636 | gen_set_nzcv(tcg_flags); | |
5637 | tcg_temp_free_i64(tcg_flags); | |
5638 | tcg_gen_br(label_continue); | |
5639 | gen_set_label(label_match); | |
5640 | } | |
5641 | ||
7a192925 | 5642 | handle_fp_compare(s, size, rn, rm, false, op); |
513f1d76 CF |
5643 | |
5644 | if (cond < 0x0e) { | |
5645 | gen_set_label(label_continue); | |
5646 | } | |
faa0ba46 PM |
5647 | } |
5648 | ||
4ce31af4 | 5649 | /* Floating point conditional select |
faa0ba46 PM |
5650 | * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0 |
5651 | * +---+---+---+-----------+------+---+------+------+-----+------+------+ | |
5652 | * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 1 1 | Rn | Rd | | |
5653 | * +---+---+---+-----------+------+---+------+------+-----+------+------+ | |
5654 | */ | |
5655 | static void disas_fp_csel(DisasContext *s, uint32_t insn) | |
5656 | { | |
5640ff62 | 5657 | unsigned int mos, type, rm, cond, rn, rd; |
6e061029 RH |
5658 | TCGv_i64 t_true, t_false, t_zero; |
5659 | DisasCompare64 c; | |
14776ab5 | 5660 | MemOp sz; |
5640ff62 CF |
5661 | |
5662 | mos = extract32(insn, 29, 3); | |
ace97fee | 5663 | type = extract32(insn, 22, 2); |
5640ff62 CF |
5664 | rm = extract32(insn, 16, 5); |
5665 | cond = extract32(insn, 12, 4); | |
5666 | rn = extract32(insn, 5, 5); | |
5667 | rd = extract32(insn, 0, 5); | |
5668 | ||
ace97fee AB |
5669 | if (mos) { |
5670 | unallocated_encoding(s); | |
5671 | return; | |
5672 | } | |
5673 | ||
5674 | switch (type) { | |
5675 | case 0: | |
5676 | sz = MO_32; | |
5677 | break; | |
5678 | case 1: | |
5679 | sz = MO_64; | |
5680 | break; | |
5681 | case 3: | |
5682 | sz = MO_16; | |
5763190f | 5683 | if (dc_isar_feature(aa64_fp16, s)) { |
ace97fee AB |
5684 | break; |
5685 | } | |
5686 | /* fallthru */ | |
5687 | default: | |
5640ff62 CF |
5688 | unallocated_encoding(s); |
5689 | return; | |
5690 | } | |
5691 | ||
8c6afa6a PM |
5692 | if (!fp_access_check(s)) { |
5693 | return; | |
5694 | } | |
5695 | ||
ace97fee | 5696 | /* Zero extend sreg & hreg inputs to 64 bits now. */ |
6e061029 RH |
5697 | t_true = tcg_temp_new_i64(); |
5698 | t_false = tcg_temp_new_i64(); | |
ace97fee AB |
5699 | read_vec_element(s, t_true, rn, 0, sz); |
5700 | read_vec_element(s, t_false, rm, 0, sz); | |
5640ff62 | 5701 | |
6e061029 RH |
5702 | a64_test_cc(&c, cond); |
5703 | t_zero = tcg_const_i64(0); | |
5704 | tcg_gen_movcond_i64(c.cond, t_true, c.value, t_zero, t_true, t_false); | |
5705 | tcg_temp_free_i64(t_zero); | |
5706 | tcg_temp_free_i64(t_false); | |
5707 | a64_free_cc(&c); | |
5640ff62 | 5708 | |
ace97fee | 5709 | /* Note that sregs & hregs write back zeros to the high bits, |
6e061029 RH |
5710 | and we've already done the zero-extension. */ |
5711 | write_fp_dreg(s, rd, t_true); | |
5712 | tcg_temp_free_i64(t_true); | |
faa0ba46 PM |
5713 | } |
5714 | ||
c2c08713 AB |
5715 | /* Floating-point data-processing (1 source) - half precision */ |
5716 | static void handle_fp_1src_half(DisasContext *s, int opcode, int rd, int rn) | |
5717 | { | |
5718 | TCGv_ptr fpst = NULL; | |
3d99d931 | 5719 | TCGv_i32 tcg_op = read_fp_hreg(s, rn); |
c2c08713 AB |
5720 | TCGv_i32 tcg_res = tcg_temp_new_i32(); |
5721 | ||
c2c08713 AB |
5722 | switch (opcode) { |
5723 | case 0x0: /* FMOV */ | |
5724 | tcg_gen_mov_i32(tcg_res, tcg_op); | |
5725 | break; | |
5726 | case 0x1: /* FABS */ | |
5727 | tcg_gen_andi_i32(tcg_res, tcg_op, 0x7fff); | |
5728 | break; | |
5729 | case 0x2: /* FNEG */ | |
5730 | tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000); | |
5731 | break; | |
5732 | case 0x3: /* FSQRT */ | |
905edee9 AB |
5733 | fpst = get_fpstatus_ptr(true); |
5734 | gen_helper_sqrt_f16(tcg_res, tcg_op, fpst); | |
c2c08713 AB |
5735 | break; |
5736 | case 0x8: /* FRINTN */ | |
5737 | case 0x9: /* FRINTP */ | |
5738 | case 0xa: /* FRINTM */ | |
5739 | case 0xb: /* FRINTZ */ | |
5740 | case 0xc: /* FRINTA */ | |
5741 | { | |
5742 | TCGv_i32 tcg_rmode = tcg_const_i32(arm_rmode_to_sf(opcode & 7)); | |
5743 | fpst = get_fpstatus_ptr(true); | |
5744 | ||
5745 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); | |
5746 | gen_helper_advsimd_rinth(tcg_res, tcg_op, fpst); | |
5747 | ||
5748 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); | |
5749 | tcg_temp_free_i32(tcg_rmode); | |
5750 | break; | |
5751 | } | |
5752 | case 0xe: /* FRINTX */ | |
5753 | fpst = get_fpstatus_ptr(true); | |
5754 | gen_helper_advsimd_rinth_exact(tcg_res, tcg_op, fpst); | |
5755 | break; | |
5756 | case 0xf: /* FRINTI */ | |
5757 | fpst = get_fpstatus_ptr(true); | |
5758 | gen_helper_advsimd_rinth(tcg_res, tcg_op, fpst); | |
5759 | break; | |
5760 | default: | |
5761 | abort(); | |
5762 | } | |
5763 | ||
5764 | write_fp_sreg(s, rd, tcg_res); | |
5765 | ||
5766 | if (fpst) { | |
5767 | tcg_temp_free_ptr(fpst); | |
5768 | } | |
5769 | tcg_temp_free_i32(tcg_op); | |
5770 | tcg_temp_free_i32(tcg_res); | |
5771 | } | |
5772 | ||
4ce31af4 | 5773 | /* Floating-point data-processing (1 source) - single precision */ |
d9b0848d PM |
5774 | static void handle_fp_1src_single(DisasContext *s, int opcode, int rd, int rn) |
5775 | { | |
0e4db23d RH |
5776 | void (*gen_fpst)(TCGv_i32, TCGv_i32, TCGv_ptr); |
5777 | TCGv_i32 tcg_op, tcg_res; | |
d9b0848d | 5778 | TCGv_ptr fpst; |
0e4db23d | 5779 | int rmode = -1; |
d9b0848d | 5780 | |
d9b0848d PM |
5781 | tcg_op = read_fp_sreg(s, rn); |
5782 | tcg_res = tcg_temp_new_i32(); | |
5783 | ||
5784 | switch (opcode) { | |
5785 | case 0x0: /* FMOV */ | |
5786 | tcg_gen_mov_i32(tcg_res, tcg_op); | |
0e4db23d | 5787 | goto done; |
d9b0848d PM |
5788 | case 0x1: /* FABS */ |
5789 | gen_helper_vfp_abss(tcg_res, tcg_op); | |
0e4db23d | 5790 | goto done; |
d9b0848d PM |
5791 | case 0x2: /* FNEG */ |
5792 | gen_helper_vfp_negs(tcg_res, tcg_op); | |
0e4db23d | 5793 | goto done; |
d9b0848d PM |
5794 | case 0x3: /* FSQRT */ |
5795 | gen_helper_vfp_sqrts(tcg_res, tcg_op, cpu_env); | |
0e4db23d | 5796 | goto done; |
d9b0848d PM |
5797 | case 0x8: /* FRINTN */ |
5798 | case 0x9: /* FRINTP */ | |
5799 | case 0xa: /* FRINTM */ | |
5800 | case 0xb: /* FRINTZ */ | |
5801 | case 0xc: /* FRINTA */ | |
0e4db23d RH |
5802 | rmode = arm_rmode_to_sf(opcode & 7); |
5803 | gen_fpst = gen_helper_rints; | |
d9b0848d | 5804 | break; |
d9b0848d | 5805 | case 0xe: /* FRINTX */ |
0e4db23d | 5806 | gen_fpst = gen_helper_rints_exact; |
d9b0848d PM |
5807 | break; |
5808 | case 0xf: /* FRINTI */ | |
0e4db23d | 5809 | gen_fpst = gen_helper_rints; |
d9b0848d | 5810 | break; |
6bea2563 RH |
5811 | case 0x10: /* FRINT32Z */ |
5812 | rmode = float_round_to_zero; | |
5813 | gen_fpst = gen_helper_frint32_s; | |
5814 | break; | |
5815 | case 0x11: /* FRINT32X */ | |
5816 | gen_fpst = gen_helper_frint32_s; | |
5817 | break; | |
5818 | case 0x12: /* FRINT64Z */ | |
5819 | rmode = float_round_to_zero; | |
5820 | gen_fpst = gen_helper_frint64_s; | |
5821 | break; | |
5822 | case 0x13: /* FRINT64X */ | |
5823 | gen_fpst = gen_helper_frint64_s; | |
5824 | break; | |
d9b0848d | 5825 | default: |
0e4db23d | 5826 | g_assert_not_reached(); |
d9b0848d PM |
5827 | } |
5828 | ||
0e4db23d RH |
5829 | fpst = get_fpstatus_ptr(false); |
5830 | if (rmode >= 0) { | |
5831 | TCGv_i32 tcg_rmode = tcg_const_i32(rmode); | |
5832 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); | |
5833 | gen_fpst(tcg_res, tcg_op, fpst); | |
5834 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); | |
5835 | tcg_temp_free_i32(tcg_rmode); | |
5836 | } else { | |
5837 | gen_fpst(tcg_res, tcg_op, fpst); | |
5838 | } | |
d9b0848d | 5839 | tcg_temp_free_ptr(fpst); |
0e4db23d RH |
5840 | |
5841 | done: | |
5842 | write_fp_sreg(s, rd, tcg_res); | |
d9b0848d PM |
5843 | tcg_temp_free_i32(tcg_op); |
5844 | tcg_temp_free_i32(tcg_res); | |
5845 | } | |
5846 | ||
4ce31af4 | 5847 | /* Floating-point data-processing (1 source) - double precision */ |
d9b0848d PM |
5848 | static void handle_fp_1src_double(DisasContext *s, int opcode, int rd, int rn) |
5849 | { | |
0e4db23d RH |
5850 | void (*gen_fpst)(TCGv_i64, TCGv_i64, TCGv_ptr); |
5851 | TCGv_i64 tcg_op, tcg_res; | |
d9b0848d | 5852 | TCGv_ptr fpst; |
0e4db23d | 5853 | int rmode = -1; |
d9b0848d | 5854 | |
377ef731 RH |
5855 | switch (opcode) { |
5856 | case 0x0: /* FMOV */ | |
5857 | gen_gvec_fn2(s, false, rd, rn, tcg_gen_gvec_mov, 0); | |
5858 | return; | |
5859 | } | |
5860 | ||
d9b0848d PM |
5861 | tcg_op = read_fp_dreg(s, rn); |
5862 | tcg_res = tcg_temp_new_i64(); | |
5863 | ||
5864 | switch (opcode) { | |
d9b0848d PM |
5865 | case 0x1: /* FABS */ |
5866 | gen_helper_vfp_absd(tcg_res, tcg_op); | |
0e4db23d | 5867 | goto done; |
d9b0848d PM |
5868 | case 0x2: /* FNEG */ |
5869 | gen_helper_vfp_negd(tcg_res, tcg_op); | |
0e4db23d | 5870 | goto done; |
d9b0848d PM |
5871 | case 0x3: /* FSQRT */ |
5872 | gen_helper_vfp_sqrtd(tcg_res, tcg_op, cpu_env); | |
0e4db23d | 5873 | goto done; |
d9b0848d PM |
5874 | case 0x8: /* FRINTN */ |
5875 | case 0x9: /* FRINTP */ | |
5876 | case 0xa: /* FRINTM */ | |
5877 | case 0xb: /* FRINTZ */ | |
5878 | case 0xc: /* FRINTA */ | |
0e4db23d RH |
5879 | rmode = arm_rmode_to_sf(opcode & 7); |
5880 | gen_fpst = gen_helper_rintd; | |
d9b0848d | 5881 | break; |
d9b0848d | 5882 | case 0xe: /* FRINTX */ |
0e4db23d | 5883 | gen_fpst = gen_helper_rintd_exact; |
d9b0848d PM |
5884 | break; |
5885 | case 0xf: /* FRINTI */ | |
0e4db23d | 5886 | gen_fpst = gen_helper_rintd; |
d9b0848d | 5887 | break; |
6bea2563 RH |
5888 | case 0x10: /* FRINT32Z */ |
5889 | rmode = float_round_to_zero; | |
5890 | gen_fpst = gen_helper_frint32_d; | |
5891 | break; | |
5892 | case 0x11: /* FRINT32X */ | |
5893 | gen_fpst = gen_helper_frint32_d; | |
5894 | break; | |
5895 | case 0x12: /* FRINT64Z */ | |
5896 | rmode = float_round_to_zero; | |
5897 | gen_fpst = gen_helper_frint64_d; | |
5898 | break; | |
5899 | case 0x13: /* FRINT64X */ | |
5900 | gen_fpst = gen_helper_frint64_d; | |
5901 | break; | |
d9b0848d | 5902 | default: |
0e4db23d | 5903 | g_assert_not_reached(); |
d9b0848d PM |
5904 | } |
5905 | ||
0e4db23d RH |
5906 | fpst = get_fpstatus_ptr(false); |
5907 | if (rmode >= 0) { | |
5908 | TCGv_i32 tcg_rmode = tcg_const_i32(rmode); | |
5909 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); | |
5910 | gen_fpst(tcg_res, tcg_op, fpst); | |
5911 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); | |
5912 | tcg_temp_free_i32(tcg_rmode); | |
5913 | } else { | |
5914 | gen_fpst(tcg_res, tcg_op, fpst); | |
5915 | } | |
d9b0848d | 5916 | tcg_temp_free_ptr(fpst); |
0e4db23d RH |
5917 | |
5918 | done: | |
5919 | write_fp_dreg(s, rd, tcg_res); | |
d9b0848d PM |
5920 | tcg_temp_free_i64(tcg_op); |
5921 | tcg_temp_free_i64(tcg_res); | |
5922 | } | |
5923 | ||
8900aad2 PM |
5924 | static void handle_fp_fcvt(DisasContext *s, int opcode, |
5925 | int rd, int rn, int dtype, int ntype) | |
5926 | { | |
5927 | switch (ntype) { | |
5928 | case 0x0: | |
5929 | { | |
5930 | TCGv_i32 tcg_rn = read_fp_sreg(s, rn); | |
5931 | if (dtype == 1) { | |
5932 | /* Single to double */ | |
5933 | TCGv_i64 tcg_rd = tcg_temp_new_i64(); | |
5934 | gen_helper_vfp_fcvtds(tcg_rd, tcg_rn, cpu_env); | |
5935 | write_fp_dreg(s, rd, tcg_rd); | |
5936 | tcg_temp_free_i64(tcg_rd); | |
5937 | } else { | |
5938 | /* Single to half */ | |
5939 | TCGv_i32 tcg_rd = tcg_temp_new_i32(); | |
486624fc AB |
5940 | TCGv_i32 ahp = get_ahp_flag(); |
5941 | TCGv_ptr fpst = get_fpstatus_ptr(false); | |
5942 | ||
5943 | gen_helper_vfp_fcvt_f32_to_f16(tcg_rd, tcg_rn, fpst, ahp); | |
8900aad2 PM |
5944 | /* write_fp_sreg is OK here because top half of tcg_rd is zero */ |
5945 | write_fp_sreg(s, rd, tcg_rd); | |
5946 | tcg_temp_free_i32(tcg_rd); | |
486624fc AB |
5947 | tcg_temp_free_i32(ahp); |
5948 | tcg_temp_free_ptr(fpst); | |
8900aad2 PM |
5949 | } |
5950 | tcg_temp_free_i32(tcg_rn); | |
5951 | break; | |
5952 | } | |
5953 | case 0x1: | |
5954 | { | |
5955 | TCGv_i64 tcg_rn = read_fp_dreg(s, rn); | |
5956 | TCGv_i32 tcg_rd = tcg_temp_new_i32(); | |
5957 | if (dtype == 0) { | |
5958 | /* Double to single */ | |
5959 | gen_helper_vfp_fcvtsd(tcg_rd, tcg_rn, cpu_env); | |
5960 | } else { | |
486624fc AB |
5961 | TCGv_ptr fpst = get_fpstatus_ptr(false); |
5962 | TCGv_i32 ahp = get_ahp_flag(); | |
8900aad2 | 5963 | /* Double to half */ |
486624fc | 5964 | gen_helper_vfp_fcvt_f64_to_f16(tcg_rd, tcg_rn, fpst, ahp); |
8900aad2 | 5965 | /* write_fp_sreg is OK here because top half of tcg_rd is zero */ |
486624fc AB |
5966 | tcg_temp_free_ptr(fpst); |
5967 | tcg_temp_free_i32(ahp); | |
8900aad2 PM |
5968 | } |
5969 | write_fp_sreg(s, rd, tcg_rd); | |
5970 | tcg_temp_free_i32(tcg_rd); | |
5971 | tcg_temp_free_i64(tcg_rn); | |
5972 | break; | |
5973 | } | |
5974 | case 0x3: | |
5975 | { | |
5976 | TCGv_i32 tcg_rn = read_fp_sreg(s, rn); | |
486624fc AB |
5977 | TCGv_ptr tcg_fpst = get_fpstatus_ptr(false); |
5978 | TCGv_i32 tcg_ahp = get_ahp_flag(); | |
8900aad2 PM |
5979 | tcg_gen_ext16u_i32(tcg_rn, tcg_rn); |
5980 | if (dtype == 0) { | |
5981 | /* Half to single */ | |
5982 | TCGv_i32 tcg_rd = tcg_temp_new_i32(); | |
486624fc | 5983 | gen_helper_vfp_fcvt_f16_to_f32(tcg_rd, tcg_rn, tcg_fpst, tcg_ahp); |
8900aad2 PM |
5984 | write_fp_sreg(s, rd, tcg_rd); |
5985 | tcg_temp_free_i32(tcg_rd); | |
5986 | } else { | |
5987 | /* Half to double */ | |
5988 | TCGv_i64 tcg_rd = tcg_temp_new_i64(); | |
486624fc | 5989 | gen_helper_vfp_fcvt_f16_to_f64(tcg_rd, tcg_rn, tcg_fpst, tcg_ahp); |
8900aad2 PM |
5990 | write_fp_dreg(s, rd, tcg_rd); |
5991 | tcg_temp_free_i64(tcg_rd); | |
5992 | } | |
5993 | tcg_temp_free_i32(tcg_rn); | |
aeab8e5e AB |
5994 | tcg_temp_free_ptr(tcg_fpst); |
5995 | tcg_temp_free_i32(tcg_ahp); | |
8900aad2 PM |
5996 | break; |
5997 | } | |
5998 | default: | |
5999 | abort(); | |
6000 | } | |
6001 | } | |
6002 | ||
4ce31af4 | 6003 | /* Floating point data-processing (1 source) |
faa0ba46 PM |
6004 | * 31 30 29 28 24 23 22 21 20 15 14 10 9 5 4 0 |
6005 | * +---+---+---+-----------+------+---+--------+-----------+------+------+ | |
6006 | * | M | 0 | S | 1 1 1 1 0 | type | 1 | opcode | 1 0 0 0 0 | Rn | Rd | | |
6007 | * +---+---+---+-----------+------+---+--------+-----------+------+------+ | |
6008 | */ | |
6009 | static void disas_fp_1src(DisasContext *s, uint32_t insn) | |
6010 | { | |
c1e20801 | 6011 | int mos = extract32(insn, 29, 3); |
d9b0848d PM |
6012 | int type = extract32(insn, 22, 2); |
6013 | int opcode = extract32(insn, 15, 6); | |
6014 | int rn = extract32(insn, 5, 5); | |
6015 | int rd = extract32(insn, 0, 5); | |
6016 | ||
c1e20801 PM |
6017 | if (mos) { |
6018 | unallocated_encoding(s); | |
6019 | return; | |
6020 | } | |
6021 | ||
d9b0848d PM |
6022 | switch (opcode) { |
6023 | case 0x4: case 0x5: case 0x7: | |
8900aad2 | 6024 | { |
d9b0848d | 6025 | /* FCVT between half, single and double precision */ |
8900aad2 PM |
6026 | int dtype = extract32(opcode, 0, 2); |
6027 | if (type == 2 || dtype == type) { | |
6028 | unallocated_encoding(s); | |
6029 | return; | |
6030 | } | |
8c6afa6a PM |
6031 | if (!fp_access_check(s)) { |
6032 | return; | |
6033 | } | |
6034 | ||
8900aad2 | 6035 | handle_fp_fcvt(s, opcode, rd, rn, dtype, type); |
d9b0848d | 6036 | break; |
8900aad2 | 6037 | } |
6bea2563 RH |
6038 | |
6039 | case 0x10 ... 0x13: /* FRINT{32,64}{X,Z} */ | |
6040 | if (type > 1 || !dc_isar_feature(aa64_frint, s)) { | |
6041 | unallocated_encoding(s); | |
6042 | return; | |
6043 | } | |
6044 | /* fall through */ | |
d9b0848d PM |
6045 | case 0x0 ... 0x3: |
6046 | case 0x8 ... 0xc: | |
6047 | case 0xe ... 0xf: | |
6048 | /* 32-to-32 and 64-to-64 ops */ | |
6049 | switch (type) { | |
6050 | case 0: | |
8c6afa6a PM |
6051 | if (!fp_access_check(s)) { |
6052 | return; | |
6053 | } | |
d9b0848d PM |
6054 | handle_fp_1src_single(s, opcode, rd, rn); |
6055 | break; | |
6056 | case 1: | |
8c6afa6a PM |
6057 | if (!fp_access_check(s)) { |
6058 | return; | |
6059 | } | |
d9b0848d PM |
6060 | handle_fp_1src_double(s, opcode, rd, rn); |
6061 | break; | |
c2c08713 | 6062 | case 3: |
5763190f | 6063 | if (!dc_isar_feature(aa64_fp16, s)) { |
c2c08713 AB |
6064 | unallocated_encoding(s); |
6065 | return; | |
6066 | } | |
6067 | ||
6068 | if (!fp_access_check(s)) { | |
6069 | return; | |
6070 | } | |
c2c08713 AB |
6071 | handle_fp_1src_half(s, opcode, rd, rn); |
6072 | break; | |
d9b0848d PM |
6073 | default: |
6074 | unallocated_encoding(s); | |
6075 | } | |
6076 | break; | |
6bea2563 | 6077 | |
d9b0848d PM |
6078 | default: |
6079 | unallocated_encoding(s); | |
6080 | break; | |
6081 | } | |
faa0ba46 PM |
6082 | } |
6083 | ||
4ce31af4 | 6084 | /* Floating-point data-processing (2 source) - single precision */ |
ec73d2e0 AG |
6085 | static void handle_fp_2src_single(DisasContext *s, int opcode, |
6086 | int rd, int rn, int rm) | |
6087 | { | |
6088 | TCGv_i32 tcg_op1; | |
6089 | TCGv_i32 tcg_op2; | |
6090 | TCGv_i32 tcg_res; | |
6091 | TCGv_ptr fpst; | |
6092 | ||
6093 | tcg_res = tcg_temp_new_i32(); | |
d81ce0ef | 6094 | fpst = get_fpstatus_ptr(false); |
ec73d2e0 AG |
6095 | tcg_op1 = read_fp_sreg(s, rn); |
6096 | tcg_op2 = read_fp_sreg(s, rm); | |
6097 | ||
6098 | switch (opcode) { | |
6099 | case 0x0: /* FMUL */ | |
6100 | gen_helper_vfp_muls(tcg_res, tcg_op1, tcg_op2, fpst); | |
6101 | break; | |
6102 | case 0x1: /* FDIV */ | |
6103 | gen_helper_vfp_divs(tcg_res, tcg_op1, tcg_op2, fpst); | |
6104 | break; | |
6105 | case 0x2: /* FADD */ | |
6106 | gen_helper_vfp_adds(tcg_res, tcg_op1, tcg_op2, fpst); | |
6107 | break; | |
6108 | case 0x3: /* FSUB */ | |
6109 | gen_helper_vfp_subs(tcg_res, tcg_op1, tcg_op2, fpst); | |
6110 | break; | |
6111 | case 0x4: /* FMAX */ | |
6112 | gen_helper_vfp_maxs(tcg_res, tcg_op1, tcg_op2, fpst); | |
6113 | break; | |
6114 | case 0x5: /* FMIN */ | |
6115 | gen_helper_vfp_mins(tcg_res, tcg_op1, tcg_op2, fpst); | |
6116 | break; | |
6117 | case 0x6: /* FMAXNM */ | |
6118 | gen_helper_vfp_maxnums(tcg_res, tcg_op1, tcg_op2, fpst); | |
6119 | break; | |
6120 | case 0x7: /* FMINNM */ | |
6121 | gen_helper_vfp_minnums(tcg_res, tcg_op1, tcg_op2, fpst); | |
6122 | break; | |
6123 | case 0x8: /* FNMUL */ | |
6124 | gen_helper_vfp_muls(tcg_res, tcg_op1, tcg_op2, fpst); | |
6125 | gen_helper_vfp_negs(tcg_res, tcg_res); | |
6126 | break; | |
6127 | } | |
6128 | ||
6129 | write_fp_sreg(s, rd, tcg_res); | |
6130 | ||
6131 | tcg_temp_free_ptr(fpst); | |
6132 | tcg_temp_free_i32(tcg_op1); | |
6133 | tcg_temp_free_i32(tcg_op2); | |
6134 | tcg_temp_free_i32(tcg_res); | |
6135 | } | |
6136 | ||
4ce31af4 | 6137 | /* Floating-point data-processing (2 source) - double precision */ |
ec73d2e0 AG |
6138 | static void handle_fp_2src_double(DisasContext *s, int opcode, |
6139 | int rd, int rn, int rm) | |
6140 | { | |
6141 | TCGv_i64 tcg_op1; | |
6142 | TCGv_i64 tcg_op2; | |
6143 | TCGv_i64 tcg_res; | |
6144 | TCGv_ptr fpst; | |
6145 | ||
6146 | tcg_res = tcg_temp_new_i64(); | |
d81ce0ef | 6147 | fpst = get_fpstatus_ptr(false); |
ec73d2e0 AG |
6148 | tcg_op1 = read_fp_dreg(s, rn); |
6149 | tcg_op2 = read_fp_dreg(s, rm); | |
6150 | ||
6151 | switch (opcode) { | |
6152 | case 0x0: /* FMUL */ | |
6153 | gen_helper_vfp_muld(tcg_res, tcg_op1, tcg_op2, fpst); | |
6154 | break; | |
6155 | case 0x1: /* FDIV */ | |
6156 | gen_helper_vfp_divd(tcg_res, tcg_op1, tcg_op2, fpst); | |
6157 | break; | |
6158 | case 0x2: /* FADD */ | |
6159 | gen_helper_vfp_addd(tcg_res, tcg_op1, tcg_op2, fpst); | |
6160 | break; | |
6161 | case 0x3: /* FSUB */ | |
6162 | gen_helper_vfp_subd(tcg_res, tcg_op1, tcg_op2, fpst); | |
6163 | break; | |
6164 | case 0x4: /* FMAX */ | |
6165 | gen_helper_vfp_maxd(tcg_res, tcg_op1, tcg_op2, fpst); | |
6166 | break; | |
6167 | case 0x5: /* FMIN */ | |
6168 | gen_helper_vfp_mind(tcg_res, tcg_op1, tcg_op2, fpst); | |
6169 | break; | |
6170 | case 0x6: /* FMAXNM */ | |
6171 | gen_helper_vfp_maxnumd(tcg_res, tcg_op1, tcg_op2, fpst); | |
6172 | break; | |
6173 | case 0x7: /* FMINNM */ | |
6174 | gen_helper_vfp_minnumd(tcg_res, tcg_op1, tcg_op2, fpst); | |
6175 | break; | |
6176 | case 0x8: /* FNMUL */ | |
6177 | gen_helper_vfp_muld(tcg_res, tcg_op1, tcg_op2, fpst); | |
6178 | gen_helper_vfp_negd(tcg_res, tcg_res); | |
6179 | break; | |
6180 | } | |
6181 | ||
6182 | write_fp_dreg(s, rd, tcg_res); | |
6183 | ||
6184 | tcg_temp_free_ptr(fpst); | |
6185 | tcg_temp_free_i64(tcg_op1); | |
6186 | tcg_temp_free_i64(tcg_op2); | |
6187 | tcg_temp_free_i64(tcg_res); | |
6188 | } | |
6189 | ||
b8f5171c RH |
6190 | /* Floating-point data-processing (2 source) - half precision */ |
6191 | static void handle_fp_2src_half(DisasContext *s, int opcode, | |
6192 | int rd, int rn, int rm) | |
6193 | { | |
6194 | TCGv_i32 tcg_op1; | |
6195 | TCGv_i32 tcg_op2; | |
6196 | TCGv_i32 tcg_res; | |
6197 | TCGv_ptr fpst; | |
6198 | ||
6199 | tcg_res = tcg_temp_new_i32(); | |
6200 | fpst = get_fpstatus_ptr(true); | |
6201 | tcg_op1 = read_fp_hreg(s, rn); | |
6202 | tcg_op2 = read_fp_hreg(s, rm); | |
6203 | ||
6204 | switch (opcode) { | |
6205 | case 0x0: /* FMUL */ | |
6206 | gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst); | |
6207 | break; | |
6208 | case 0x1: /* FDIV */ | |
6209 | gen_helper_advsimd_divh(tcg_res, tcg_op1, tcg_op2, fpst); | |
6210 | break; | |
6211 | case 0x2: /* FADD */ | |
6212 | gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst); | |
6213 | break; | |
6214 | case 0x3: /* FSUB */ | |
6215 | gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst); | |
6216 | break; | |
6217 | case 0x4: /* FMAX */ | |
6218 | gen_helper_advsimd_maxh(tcg_res, tcg_op1, tcg_op2, fpst); | |
6219 | break; | |
6220 | case 0x5: /* FMIN */ | |
6221 | gen_helper_advsimd_minh(tcg_res, tcg_op1, tcg_op2, fpst); | |
6222 | break; | |
6223 | case 0x6: /* FMAXNM */ | |
6224 | gen_helper_advsimd_maxnumh(tcg_res, tcg_op1, tcg_op2, fpst); | |
6225 | break; | |
6226 | case 0x7: /* FMINNM */ | |
6227 | gen_helper_advsimd_minnumh(tcg_res, tcg_op1, tcg_op2, fpst); | |
6228 | break; | |
6229 | case 0x8: /* FNMUL */ | |
6230 | gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst); | |
6231 | tcg_gen_xori_i32(tcg_res, tcg_res, 0x8000); | |
6232 | break; | |
6233 | default: | |
6234 | g_assert_not_reached(); | |
6235 | } | |
6236 | ||
6237 | write_fp_sreg(s, rd, tcg_res); | |
6238 | ||
6239 | tcg_temp_free_ptr(fpst); | |
6240 | tcg_temp_free_i32(tcg_op1); | |
6241 | tcg_temp_free_i32(tcg_op2); | |
6242 | tcg_temp_free_i32(tcg_res); | |
6243 | } | |
6244 | ||
4ce31af4 | 6245 | /* Floating point data-processing (2 source) |
faa0ba46 PM |
6246 | * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0 |
6247 | * +---+---+---+-----------+------+---+------+--------+-----+------+------+ | |
6248 | * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | opcode | 1 0 | Rn | Rd | | |
6249 | * +---+---+---+-----------+------+---+------+--------+-----+------+------+ | |
6250 | */ | |
6251 | static void disas_fp_2src(DisasContext *s, uint32_t insn) | |
6252 | { | |
c1e20801 | 6253 | int mos = extract32(insn, 29, 3); |
ec73d2e0 AG |
6254 | int type = extract32(insn, 22, 2); |
6255 | int rd = extract32(insn, 0, 5); | |
6256 | int rn = extract32(insn, 5, 5); | |
6257 | int rm = extract32(insn, 16, 5); | |
6258 | int opcode = extract32(insn, 12, 4); | |
6259 | ||
c1e20801 | 6260 | if (opcode > 8 || mos) { |
ec73d2e0 AG |
6261 | unallocated_encoding(s); |
6262 | return; | |
6263 | } | |
6264 | ||
6265 | switch (type) { | |
6266 | case 0: | |
8c6afa6a PM |
6267 | if (!fp_access_check(s)) { |
6268 | return; | |
6269 | } | |
ec73d2e0 AG |
6270 | handle_fp_2src_single(s, opcode, rd, rn, rm); |
6271 | break; | |
6272 | case 1: | |
8c6afa6a PM |
6273 | if (!fp_access_check(s)) { |
6274 | return; | |
6275 | } | |
ec73d2e0 AG |
6276 | handle_fp_2src_double(s, opcode, rd, rn, rm); |
6277 | break; | |
b8f5171c | 6278 | case 3: |
5763190f | 6279 | if (!dc_isar_feature(aa64_fp16, s)) { |
b8f5171c RH |
6280 | unallocated_encoding(s); |
6281 | return; | |
6282 | } | |
6283 | if (!fp_access_check(s)) { | |
6284 | return; | |
6285 | } | |
6286 | handle_fp_2src_half(s, opcode, rd, rn, rm); | |
6287 | break; | |
ec73d2e0 AG |
6288 | default: |
6289 | unallocated_encoding(s); | |
6290 | } | |
faa0ba46 PM |
6291 | } |
6292 | ||
4ce31af4 | 6293 | /* Floating-point data-processing (3 source) - single precision */ |
6a30667f AG |
6294 | static void handle_fp_3src_single(DisasContext *s, bool o0, bool o1, |
6295 | int rd, int rn, int rm, int ra) | |
6296 | { | |
6297 | TCGv_i32 tcg_op1, tcg_op2, tcg_op3; | |
6298 | TCGv_i32 tcg_res = tcg_temp_new_i32(); | |
d81ce0ef | 6299 | TCGv_ptr fpst = get_fpstatus_ptr(false); |
6a30667f AG |
6300 | |
6301 | tcg_op1 = read_fp_sreg(s, rn); | |
6302 | tcg_op2 = read_fp_sreg(s, rm); | |
6303 | tcg_op3 = read_fp_sreg(s, ra); | |
6304 | ||
6305 | /* These are fused multiply-add, and must be done as one | |
6306 | * floating point operation with no rounding between the | |
6307 | * multiplication and addition steps. | |
6308 | * NB that doing the negations here as separate steps is | |
6309 | * correct : an input NaN should come out with its sign bit | |
6310 | * flipped if it is a negated-input. | |
6311 | */ | |
6312 | if (o1 == true) { | |
6313 | gen_helper_vfp_negs(tcg_op3, tcg_op3); | |
6314 | } | |
6315 | ||
6316 | if (o0 != o1) { | |
6317 | gen_helper_vfp_negs(tcg_op1, tcg_op1); | |
6318 | } | |
6319 | ||
6320 | gen_helper_vfp_muladds(tcg_res, tcg_op1, tcg_op2, tcg_op3, fpst); | |
6321 | ||
6322 | write_fp_sreg(s, rd, tcg_res); | |
6323 | ||
6324 | tcg_temp_free_ptr(fpst); | |
6325 | tcg_temp_free_i32(tcg_op1); | |
6326 | tcg_temp_free_i32(tcg_op2); | |
6327 | tcg_temp_free_i32(tcg_op3); | |
6328 | tcg_temp_free_i32(tcg_res); | |
6329 | } | |
6330 | ||
4ce31af4 | 6331 | /* Floating-point data-processing (3 source) - double precision */ |
6a30667f AG |
6332 | static void handle_fp_3src_double(DisasContext *s, bool o0, bool o1, |
6333 | int rd, int rn, int rm, int ra) | |
6334 | { | |
6335 | TCGv_i64 tcg_op1, tcg_op2, tcg_op3; | |
6336 | TCGv_i64 tcg_res = tcg_temp_new_i64(); | |
d81ce0ef | 6337 | TCGv_ptr fpst = get_fpstatus_ptr(false); |
6a30667f AG |
6338 | |
6339 | tcg_op1 = read_fp_dreg(s, rn); | |
6340 | tcg_op2 = read_fp_dreg(s, rm); | |
6341 | tcg_op3 = read_fp_dreg(s, ra); | |
6342 | ||
6343 | /* These are fused multiply-add, and must be done as one | |
6344 | * floating point operation with no rounding between the | |
6345 | * multiplication and addition steps. | |
6346 | * NB that doing the negations here as separate steps is | |
6347 | * correct : an input NaN should come out with its sign bit | |
6348 | * flipped if it is a negated-input. | |
6349 | */ | |
6350 | if (o1 == true) { | |
6351 | gen_helper_vfp_negd(tcg_op3, tcg_op3); | |
6352 | } | |
6353 | ||
6354 | if (o0 != o1) { | |
6355 | gen_helper_vfp_negd(tcg_op1, tcg_op1); | |
6356 | } | |
6357 | ||
6358 | gen_helper_vfp_muladdd(tcg_res, tcg_op1, tcg_op2, tcg_op3, fpst); | |
6359 | ||
6360 | write_fp_dreg(s, rd, tcg_res); | |
6361 | ||
6362 | tcg_temp_free_ptr(fpst); | |
6363 | tcg_temp_free_i64(tcg_op1); | |
6364 | tcg_temp_free_i64(tcg_op2); | |
6365 | tcg_temp_free_i64(tcg_op3); | |
6366 | tcg_temp_free_i64(tcg_res); | |
6367 | } | |
6368 | ||
95f9864f RH |
6369 | /* Floating-point data-processing (3 source) - half precision */ |
6370 | static void handle_fp_3src_half(DisasContext *s, bool o0, bool o1, | |
6371 | int rd, int rn, int rm, int ra) | |
6372 | { | |
6373 | TCGv_i32 tcg_op1, tcg_op2, tcg_op3; | |
6374 | TCGv_i32 tcg_res = tcg_temp_new_i32(); | |
6375 | TCGv_ptr fpst = get_fpstatus_ptr(true); | |
6376 | ||
6377 | tcg_op1 = read_fp_hreg(s, rn); | |
6378 | tcg_op2 = read_fp_hreg(s, rm); | |
6379 | tcg_op3 = read_fp_hreg(s, ra); | |
6380 | ||
6381 | /* These are fused multiply-add, and must be done as one | |
6382 | * floating point operation with no rounding between the | |
6383 | * multiplication and addition steps. | |
6384 | * NB that doing the negations here as separate steps is | |
6385 | * correct : an input NaN should come out with its sign bit | |
6386 | * flipped if it is a negated-input. | |
6387 | */ | |
6388 | if (o1 == true) { | |
6389 | tcg_gen_xori_i32(tcg_op3, tcg_op3, 0x8000); | |
6390 | } | |
6391 | ||
6392 | if (o0 != o1) { | |
6393 | tcg_gen_xori_i32(tcg_op1, tcg_op1, 0x8000); | |
6394 | } | |
6395 | ||
6396 | gen_helper_advsimd_muladdh(tcg_res, tcg_op1, tcg_op2, tcg_op3, fpst); | |
6397 | ||
6398 | write_fp_sreg(s, rd, tcg_res); | |
6399 | ||
6400 | tcg_temp_free_ptr(fpst); | |
6401 | tcg_temp_free_i32(tcg_op1); | |
6402 | tcg_temp_free_i32(tcg_op2); | |
6403 | tcg_temp_free_i32(tcg_op3); | |
6404 | tcg_temp_free_i32(tcg_res); | |
6405 | } | |
6406 | ||
4ce31af4 | 6407 | /* Floating point data-processing (3 source) |
faa0ba46 PM |
6408 | * 31 30 29 28 24 23 22 21 20 16 15 14 10 9 5 4 0 |
6409 | * +---+---+---+-----------+------+----+------+----+------+------+------+ | |
6410 | * | M | 0 | S | 1 1 1 1 1 | type | o1 | Rm | o0 | Ra | Rn | Rd | | |
6411 | * +---+---+---+-----------+------+----+------+----+------+------+------+ | |
6412 | */ | |
6413 | static void disas_fp_3src(DisasContext *s, uint32_t insn) | |
6414 | { | |
c1e20801 | 6415 | int mos = extract32(insn, 29, 3); |
6a30667f AG |
6416 | int type = extract32(insn, 22, 2); |
6417 | int rd = extract32(insn, 0, 5); | |
6418 | int rn = extract32(insn, 5, 5); | |
6419 | int ra = extract32(insn, 10, 5); | |
6420 | int rm = extract32(insn, 16, 5); | |
6421 | bool o0 = extract32(insn, 15, 1); | |
6422 | bool o1 = extract32(insn, 21, 1); | |
6423 | ||
c1e20801 PM |
6424 | if (mos) { |
6425 | unallocated_encoding(s); | |
6426 | return; | |
6427 | } | |
6428 | ||
6a30667f AG |
6429 | switch (type) { |
6430 | case 0: | |
8c6afa6a PM |
6431 | if (!fp_access_check(s)) { |
6432 | return; | |
6433 | } | |
6a30667f AG |
6434 | handle_fp_3src_single(s, o0, o1, rd, rn, rm, ra); |
6435 | break; | |
6436 | case 1: | |
8c6afa6a PM |
6437 | if (!fp_access_check(s)) { |
6438 | return; | |
6439 | } | |
6a30667f AG |
6440 | handle_fp_3src_double(s, o0, o1, rd, rn, rm, ra); |
6441 | break; | |
95f9864f | 6442 | case 3: |
5763190f | 6443 | if (!dc_isar_feature(aa64_fp16, s)) { |
95f9864f RH |
6444 | unallocated_encoding(s); |
6445 | return; | |
6446 | } | |
6447 | if (!fp_access_check(s)) { | |
6448 | return; | |
6449 | } | |
6450 | handle_fp_3src_half(s, o0, o1, rd, rn, rm, ra); | |
6451 | break; | |
6a30667f AG |
6452 | default: |
6453 | unallocated_encoding(s); | |
6454 | } | |
faa0ba46 PM |
6455 | } |
6456 | ||
4ce31af4 | 6457 | /* Floating point immediate |
faa0ba46 PM |
6458 | * 31 30 29 28 24 23 22 21 20 13 12 10 9 5 4 0 |
6459 | * +---+---+---+-----------+------+---+------------+-------+------+------+ | |
6460 | * | M | 0 | S | 1 1 1 1 0 | type | 1 | imm8 | 1 0 0 | imm5 | Rd | | |
6461 | * +---+---+---+-----------+------+---+------------+-------+------+------+ | |
6462 | */ | |
6463 | static void disas_fp_imm(DisasContext *s, uint32_t insn) | |
6464 | { | |
6163f868 | 6465 | int rd = extract32(insn, 0, 5); |
c1e20801 | 6466 | int imm5 = extract32(insn, 5, 5); |
6163f868 | 6467 | int imm8 = extract32(insn, 13, 8); |
6ba28ddb | 6468 | int type = extract32(insn, 22, 2); |
c1e20801 | 6469 | int mos = extract32(insn, 29, 3); |
6163f868 AG |
6470 | uint64_t imm; |
6471 | TCGv_i64 tcg_res; | |
14776ab5 | 6472 | MemOp sz; |
6163f868 | 6473 | |
c1e20801 PM |
6474 | if (mos || imm5) { |
6475 | unallocated_encoding(s); | |
6476 | return; | |
6477 | } | |
6478 | ||
6ba28ddb AB |
6479 | switch (type) { |
6480 | case 0: | |
6481 | sz = MO_32; | |
6482 | break; | |
6483 | case 1: | |
6484 | sz = MO_64; | |
6485 | break; | |
6486 | case 3: | |
6487 | sz = MO_16; | |
5763190f | 6488 | if (dc_isar_feature(aa64_fp16, s)) { |
6ba28ddb AB |
6489 | break; |
6490 | } | |
6491 | /* fallthru */ | |
6492 | default: | |
6163f868 AG |
6493 | unallocated_encoding(s); |
6494 | return; | |
6495 | } | |
6496 | ||
8c6afa6a PM |
6497 | if (!fp_access_check(s)) { |
6498 | return; | |
6499 | } | |
6500 | ||
6ba28ddb | 6501 | imm = vfp_expand_imm(sz, imm8); |
6163f868 AG |
6502 | |
6503 | tcg_res = tcg_const_i64(imm); | |
6504 | write_fp_dreg(s, rd, tcg_res); | |
6505 | tcg_temp_free_i64(tcg_res); | |
faa0ba46 PM |
6506 | } |
6507 | ||
52a1f6a3 AG |
6508 | /* Handle floating point <=> fixed point conversions. Note that we can |
6509 | * also deal with fp <=> integer conversions as a special case (scale == 64) | |
6510 | * OPTME: consider handling that special case specially or at least skipping | |
6511 | * the call to scalbn in the helpers for zero shifts. | |
6512 | */ | |
6513 | static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode, | |
6514 | bool itof, int rmode, int scale, int sf, int type) | |
6515 | { | |
6516 | bool is_signed = !(opcode & 1); | |
52a1f6a3 | 6517 | TCGv_ptr tcg_fpstatus; |
564a0632 RH |
6518 | TCGv_i32 tcg_shift, tcg_single; |
6519 | TCGv_i64 tcg_double; | |
52a1f6a3 | 6520 | |
564a0632 | 6521 | tcg_fpstatus = get_fpstatus_ptr(type == 3); |
52a1f6a3 AG |
6522 | |
6523 | tcg_shift = tcg_const_i32(64 - scale); | |
6524 | ||
6525 | if (itof) { | |
6526 | TCGv_i64 tcg_int = cpu_reg(s, rn); | |
6527 | if (!sf) { | |
6528 | TCGv_i64 tcg_extend = new_tmp_a64(s); | |
6529 | ||
6530 | if (is_signed) { | |
6531 | tcg_gen_ext32s_i64(tcg_extend, tcg_int); | |
6532 | } else { | |
6533 | tcg_gen_ext32u_i64(tcg_extend, tcg_int); | |
6534 | } | |
6535 | ||
6536 | tcg_int = tcg_extend; | |
6537 | } | |
6538 | ||
564a0632 RH |
6539 | switch (type) { |
6540 | case 1: /* float64 */ | |
6541 | tcg_double = tcg_temp_new_i64(); | |
52a1f6a3 AG |
6542 | if (is_signed) { |
6543 | gen_helper_vfp_sqtod(tcg_double, tcg_int, | |
6544 | tcg_shift, tcg_fpstatus); | |
6545 | } else { | |
6546 | gen_helper_vfp_uqtod(tcg_double, tcg_int, | |
6547 | tcg_shift, tcg_fpstatus); | |
6548 | } | |
6549 | write_fp_dreg(s, rd, tcg_double); | |
6550 | tcg_temp_free_i64(tcg_double); | |
564a0632 RH |
6551 | break; |
6552 | ||
6553 | case 0: /* float32 */ | |
6554 | tcg_single = tcg_temp_new_i32(); | |
52a1f6a3 AG |
6555 | if (is_signed) { |
6556 | gen_helper_vfp_sqtos(tcg_single, tcg_int, | |
6557 | tcg_shift, tcg_fpstatus); | |
6558 | } else { | |
6559 | gen_helper_vfp_uqtos(tcg_single, tcg_int, | |
6560 | tcg_shift, tcg_fpstatus); | |
6561 | } | |
6562 | write_fp_sreg(s, rd, tcg_single); | |
6563 | tcg_temp_free_i32(tcg_single); | |
564a0632 RH |
6564 | break; |
6565 | ||
6566 | case 3: /* float16 */ | |
6567 | tcg_single = tcg_temp_new_i32(); | |
6568 | if (is_signed) { | |
6569 | gen_helper_vfp_sqtoh(tcg_single, tcg_int, | |
6570 | tcg_shift, tcg_fpstatus); | |
6571 | } else { | |
6572 | gen_helper_vfp_uqtoh(tcg_single, tcg_int, | |
6573 | tcg_shift, tcg_fpstatus); | |
6574 | } | |
6575 | write_fp_sreg(s, rd, tcg_single); | |
6576 | tcg_temp_free_i32(tcg_single); | |
6577 | break; | |
6578 | ||
6579 | default: | |
6580 | g_assert_not_reached(); | |
52a1f6a3 AG |
6581 | } |
6582 | } else { | |
6583 | TCGv_i64 tcg_int = cpu_reg(s, rd); | |
6584 | TCGv_i32 tcg_rmode; | |
6585 | ||
6586 | if (extract32(opcode, 2, 1)) { | |
6587 | /* There are too many rounding modes to all fit into rmode, | |
6588 | * so FCVTA[US] is a special case. | |
6589 | */ | |
6590 | rmode = FPROUNDING_TIEAWAY; | |
6591 | } | |
6592 | ||
6593 | tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode)); | |
6594 | ||
9b049916 | 6595 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); |
52a1f6a3 | 6596 | |
564a0632 RH |
6597 | switch (type) { |
6598 | case 1: /* float64 */ | |
6599 | tcg_double = read_fp_dreg(s, rn); | |
52a1f6a3 AG |
6600 | if (is_signed) { |
6601 | if (!sf) { | |
6602 | gen_helper_vfp_tosld(tcg_int, tcg_double, | |
6603 | tcg_shift, tcg_fpstatus); | |
6604 | } else { | |
6605 | gen_helper_vfp_tosqd(tcg_int, tcg_double, | |
6606 | tcg_shift, tcg_fpstatus); | |
6607 | } | |
6608 | } else { | |
6609 | if (!sf) { | |
6610 | gen_helper_vfp_tould(tcg_int, tcg_double, | |
6611 | tcg_shift, tcg_fpstatus); | |
6612 | } else { | |
6613 | gen_helper_vfp_touqd(tcg_int, tcg_double, | |
6614 | tcg_shift, tcg_fpstatus); | |
6615 | } | |
6616 | } | |
564a0632 RH |
6617 | if (!sf) { |
6618 | tcg_gen_ext32u_i64(tcg_int, tcg_int); | |
6619 | } | |
52a1f6a3 | 6620 | tcg_temp_free_i64(tcg_double); |
564a0632 RH |
6621 | break; |
6622 | ||
6623 | case 0: /* float32 */ | |
6624 | tcg_single = read_fp_sreg(s, rn); | |
52a1f6a3 AG |
6625 | if (sf) { |
6626 | if (is_signed) { | |
6627 | gen_helper_vfp_tosqs(tcg_int, tcg_single, | |
6628 | tcg_shift, tcg_fpstatus); | |
6629 | } else { | |
6630 | gen_helper_vfp_touqs(tcg_int, tcg_single, | |
6631 | tcg_shift, tcg_fpstatus); | |
6632 | } | |
6633 | } else { | |
6634 | TCGv_i32 tcg_dest = tcg_temp_new_i32(); | |
6635 | if (is_signed) { | |
6636 | gen_helper_vfp_tosls(tcg_dest, tcg_single, | |
6637 | tcg_shift, tcg_fpstatus); | |
6638 | } else { | |
6639 | gen_helper_vfp_touls(tcg_dest, tcg_single, | |
6640 | tcg_shift, tcg_fpstatus); | |
6641 | } | |
6642 | tcg_gen_extu_i32_i64(tcg_int, tcg_dest); | |
6643 | tcg_temp_free_i32(tcg_dest); | |
6644 | } | |
6645 | tcg_temp_free_i32(tcg_single); | |
564a0632 RH |
6646 | break; |
6647 | ||
6648 | case 3: /* float16 */ | |
6649 | tcg_single = read_fp_sreg(s, rn); | |
6650 | if (sf) { | |
6651 | if (is_signed) { | |
6652 | gen_helper_vfp_tosqh(tcg_int, tcg_single, | |
6653 | tcg_shift, tcg_fpstatus); | |
6654 | } else { | |
6655 | gen_helper_vfp_touqh(tcg_int, tcg_single, | |
6656 | tcg_shift, tcg_fpstatus); | |
6657 | } | |
6658 | } else { | |
6659 | TCGv_i32 tcg_dest = tcg_temp_new_i32(); | |
6660 | if (is_signed) { | |
6661 | gen_helper_vfp_toslh(tcg_dest, tcg_single, | |
6662 | tcg_shift, tcg_fpstatus); | |
6663 | } else { | |
6664 | gen_helper_vfp_toulh(tcg_dest, tcg_single, | |
6665 | tcg_shift, tcg_fpstatus); | |
6666 | } | |
6667 | tcg_gen_extu_i32_i64(tcg_int, tcg_dest); | |
6668 | tcg_temp_free_i32(tcg_dest); | |
6669 | } | |
6670 | tcg_temp_free_i32(tcg_single); | |
6671 | break; | |
6672 | ||
6673 | default: | |
6674 | g_assert_not_reached(); | |
52a1f6a3 AG |
6675 | } |
6676 | ||
9b049916 | 6677 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); |
52a1f6a3 | 6678 | tcg_temp_free_i32(tcg_rmode); |
52a1f6a3 AG |
6679 | } |
6680 | ||
6681 | tcg_temp_free_ptr(tcg_fpstatus); | |
6682 | tcg_temp_free_i32(tcg_shift); | |
6683 | } | |
6684 | ||
4ce31af4 | 6685 | /* Floating point <-> fixed point conversions |
faa0ba46 PM |
6686 | * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0 |
6687 | * +----+---+---+-----------+------+---+-------+--------+-------+------+------+ | |
6688 | * | sf | 0 | S | 1 1 1 1 0 | type | 0 | rmode | opcode | scale | Rn | Rd | | |
6689 | * +----+---+---+-----------+------+---+-------+--------+-------+------+------+ | |
6690 | */ | |
6691 | static void disas_fp_fixed_conv(DisasContext *s, uint32_t insn) | |
6692 | { | |
52a1f6a3 AG |
6693 | int rd = extract32(insn, 0, 5); |
6694 | int rn = extract32(insn, 5, 5); | |
6695 | int scale = extract32(insn, 10, 6); | |
6696 | int opcode = extract32(insn, 16, 3); | |
6697 | int rmode = extract32(insn, 19, 2); | |
6698 | int type = extract32(insn, 22, 2); | |
6699 | bool sbit = extract32(insn, 29, 1); | |
6700 | bool sf = extract32(insn, 31, 1); | |
6701 | bool itof; | |
6702 | ||
27527280 RH |
6703 | if (sbit || (!sf && scale < 32)) { |
6704 | unallocated_encoding(s); | |
6705 | return; | |
6706 | } | |
6707 | ||
6708 | switch (type) { | |
6709 | case 0: /* float32 */ | |
6710 | case 1: /* float64 */ | |
6711 | break; | |
6712 | case 3: /* float16 */ | |
5763190f | 6713 | if (dc_isar_feature(aa64_fp16, s)) { |
27527280 RH |
6714 | break; |
6715 | } | |
6716 | /* fallthru */ | |
6717 | default: | |
52a1f6a3 AG |
6718 | unallocated_encoding(s); |
6719 | return; | |
6720 | } | |
6721 | ||
6722 | switch ((rmode << 3) | opcode) { | |
6723 | case 0x2: /* SCVTF */ | |
6724 | case 0x3: /* UCVTF */ | |
6725 | itof = true; | |
6726 | break; | |
6727 | case 0x18: /* FCVTZS */ | |
6728 | case 0x19: /* FCVTZU */ | |
6729 | itof = false; | |
6730 | break; | |
6731 | default: | |
6732 | unallocated_encoding(s); | |
6733 | return; | |
6734 | } | |
6735 | ||
8c6afa6a PM |
6736 | if (!fp_access_check(s)) { |
6737 | return; | |
6738 | } | |
6739 | ||
52a1f6a3 | 6740 | handle_fpfpcvt(s, rd, rn, opcode, itof, FPROUNDING_ZERO, scale, sf, type); |
faa0ba46 PM |
6741 | } |
6742 | ||
ce5458e8 PM |
6743 | static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof) |
6744 | { | |
6745 | /* FMOV: gpr to or from float, double, or top half of quad fp reg, | |
6746 | * without conversion. | |
6747 | */ | |
6748 | ||
6749 | if (itof) { | |
ce5458e8 | 6750 | TCGv_i64 tcg_rn = cpu_reg(s, rn); |
9a9f1f59 | 6751 | TCGv_i64 tmp; |
ce5458e8 PM |
6752 | |
6753 | switch (type) { | |
6754 | case 0: | |
ce5458e8 | 6755 | /* 32 bit */ |
9a9f1f59 | 6756 | tmp = tcg_temp_new_i64(); |
ce5458e8 | 6757 | tcg_gen_ext32u_i64(tmp, tcg_rn); |
9a9f1f59 | 6758 | write_fp_dreg(s, rd, tmp); |
ce5458e8 PM |
6759 | tcg_temp_free_i64(tmp); |
6760 | break; | |
ce5458e8 | 6761 | case 1: |
ce5458e8 | 6762 | /* 64 bit */ |
9a9f1f59 | 6763 | write_fp_dreg(s, rd, tcg_rn); |
ce5458e8 | 6764 | break; |
ce5458e8 PM |
6765 | case 2: |
6766 | /* 64 bit to top half. */ | |
90e49638 | 6767 | tcg_gen_st_i64(tcg_rn, cpu_env, fp_reg_hi_offset(s, rd)); |
9a9f1f59 | 6768 | clear_vec_high(s, true, rd); |
ce5458e8 | 6769 | break; |
68130236 RH |
6770 | case 3: |
6771 | /* 16 bit */ | |
6772 | tmp = tcg_temp_new_i64(); | |
6773 | tcg_gen_ext16u_i64(tmp, tcg_rn); | |
6774 | write_fp_dreg(s, rd, tmp); | |
6775 | tcg_temp_free_i64(tmp); | |
6776 | break; | |
6777 | default: | |
6778 | g_assert_not_reached(); | |
ce5458e8 PM |
6779 | } |
6780 | } else { | |
ce5458e8 PM |
6781 | TCGv_i64 tcg_rd = cpu_reg(s, rd); |
6782 | ||
6783 | switch (type) { | |
6784 | case 0: | |
6785 | /* 32 bit */ | |
90e49638 | 6786 | tcg_gen_ld32u_i64(tcg_rd, cpu_env, fp_reg_offset(s, rn, MO_32)); |
ce5458e8 | 6787 | break; |
ce5458e8 PM |
6788 | case 1: |
6789 | /* 64 bit */ | |
90e49638 | 6790 | tcg_gen_ld_i64(tcg_rd, cpu_env, fp_reg_offset(s, rn, MO_64)); |
e2f90565 PM |
6791 | break; |
6792 | case 2: | |
6793 | /* 64 bits from top half */ | |
90e49638 | 6794 | tcg_gen_ld_i64(tcg_rd, cpu_env, fp_reg_hi_offset(s, rn)); |
ce5458e8 | 6795 | break; |
68130236 RH |
6796 | case 3: |
6797 | /* 16 bit */ | |
6798 | tcg_gen_ld16u_i64(tcg_rd, cpu_env, fp_reg_offset(s, rn, MO_16)); | |
6799 | break; | |
6800 | default: | |
6801 | g_assert_not_reached(); | |
ce5458e8 PM |
6802 | } |
6803 | } | |
6804 | } | |
6805 | ||
6c1f6f27 RH |
6806 | static void handle_fjcvtzs(DisasContext *s, int rd, int rn) |
6807 | { | |
6808 | TCGv_i64 t = read_fp_dreg(s, rn); | |
6809 | TCGv_ptr fpstatus = get_fpstatus_ptr(false); | |
6810 | ||
6811 | gen_helper_fjcvtzs(t, t, fpstatus); | |
6812 | ||
6813 | tcg_temp_free_ptr(fpstatus); | |
6814 | ||
6815 | tcg_gen_ext32u_i64(cpu_reg(s, rd), t); | |
6816 | tcg_gen_extrh_i64_i32(cpu_ZF, t); | |
6817 | tcg_gen_movi_i32(cpu_CF, 0); | |
6818 | tcg_gen_movi_i32(cpu_NF, 0); | |
6819 | tcg_gen_movi_i32(cpu_VF, 0); | |
6820 | ||
6821 | tcg_temp_free_i64(t); | |
6822 | } | |
6823 | ||
4ce31af4 | 6824 | /* Floating point <-> integer conversions |
faa0ba46 PM |
6825 | * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0 |
6826 | * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+ | |
c436d406 | 6827 | * | sf | 0 | S | 1 1 1 1 0 | type | 1 | rmode | opc | 0 0 0 0 0 0 | Rn | Rd | |
faa0ba46 PM |
6828 | * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+ |
6829 | */ | |
6830 | static void disas_fp_int_conv(DisasContext *s, uint32_t insn) | |
6831 | { | |
ce5458e8 PM |
6832 | int rd = extract32(insn, 0, 5); |
6833 | int rn = extract32(insn, 5, 5); | |
6834 | int opcode = extract32(insn, 16, 3); | |
6835 | int rmode = extract32(insn, 19, 2); | |
6836 | int type = extract32(insn, 22, 2); | |
6837 | bool sbit = extract32(insn, 29, 1); | |
6838 | bool sf = extract32(insn, 31, 1); | |
3c3ff684 | 6839 | bool itof = false; |
ce5458e8 | 6840 | |
c436d406 | 6841 | if (sbit) { |
3c3ff684 | 6842 | goto do_unallocated; |
c436d406 WN |
6843 | } |
6844 | ||
3c3ff684 RH |
6845 | switch (opcode) { |
6846 | case 2: /* SCVTF */ | |
6847 | case 3: /* UCVTF */ | |
6848 | itof = true; | |
6849 | /* fallthru */ | |
6850 | case 4: /* FCVTAS */ | |
6851 | case 5: /* FCVTAU */ | |
6852 | if (rmode != 0) { | |
6853 | goto do_unallocated; | |
c436d406 | 6854 | } |
3c3ff684 RH |
6855 | /* fallthru */ |
6856 | case 0: /* FCVT[NPMZ]S */ | |
6857 | case 1: /* FCVT[NPMZ]U */ | |
6858 | switch (type) { | |
6859 | case 0: /* float32 */ | |
6860 | case 1: /* float64 */ | |
ce5458e8 | 6861 | break; |
3c3ff684 RH |
6862 | case 3: /* float16 */ |
6863 | if (!dc_isar_feature(aa64_fp16, s)) { | |
6864 | goto do_unallocated; | |
68130236 | 6865 | } |
3c3ff684 | 6866 | break; |
ce5458e8 | 6867 | default: |
3c3ff684 | 6868 | goto do_unallocated; |
ce5458e8 | 6869 | } |
8c6afa6a PM |
6870 | if (!fp_access_check(s)) { |
6871 | return; | |
6872 | } | |
3c3ff684 RH |
6873 | handle_fpfpcvt(s, rd, rn, opcode, itof, rmode, 64, sf, type); |
6874 | break; | |
c436d406 | 6875 | |
3c3ff684 RH |
6876 | default: |
6877 | switch (sf << 7 | type << 5 | rmode << 3 | opcode) { | |
6878 | case 0b01100110: /* FMOV half <-> 32-bit int */ | |
6879 | case 0b01100111: | |
6880 | case 0b11100110: /* FMOV half <-> 64-bit int */ | |
6881 | case 0b11100111: | |
6882 | if (!dc_isar_feature(aa64_fp16, s)) { | |
6883 | goto do_unallocated; | |
564a0632 RH |
6884 | } |
6885 | /* fallthru */ | |
3c3ff684 RH |
6886 | case 0b00000110: /* FMOV 32-bit */ |
6887 | case 0b00000111: | |
6888 | case 0b10100110: /* FMOV 64-bit */ | |
6889 | case 0b10100111: | |
6890 | case 0b11001110: /* FMOV top half of 128-bit */ | |
6891 | case 0b11001111: | |
6892 | if (!fp_access_check(s)) { | |
6893 | return; | |
6894 | } | |
6895 | itof = opcode & 1; | |
6896 | handle_fmov(s, rd, rn, type, itof); | |
6897 | break; | |
6898 | ||
6c1f6f27 RH |
6899 | case 0b00111110: /* FJCVTZS */ |
6900 | if (!dc_isar_feature(aa64_jscvt, s)) { | |
6901 | goto do_unallocated; | |
6902 | } else if (fp_access_check(s)) { | |
6903 | handle_fjcvtzs(s, rd, rn); | |
6904 | } | |
6905 | break; | |
6906 | ||
564a0632 | 6907 | default: |
3c3ff684 | 6908 | do_unallocated: |
c436d406 WN |
6909 | unallocated_encoding(s); |
6910 | return; | |
6911 | } | |
3c3ff684 | 6912 | break; |
ce5458e8 | 6913 | } |
faa0ba46 PM |
6914 | } |
6915 | ||
6916 | /* FP-specific subcases of table C3-6 (SIMD and FP data processing) | |
6917 | * 31 30 29 28 25 24 0 | |
6918 | * +---+---+---+---------+-----------------------------+ | |
6919 | * | | 0 | | 1 1 1 1 | | | |
6920 | * +---+---+---+---------+-----------------------------+ | |
6921 | */ | |
6922 | static void disas_data_proc_fp(DisasContext *s, uint32_t insn) | |
6923 | { | |
6924 | if (extract32(insn, 24, 1)) { | |
6925 | /* Floating point data-processing (3 source) */ | |
6926 | disas_fp_3src(s, insn); | |
6927 | } else if (extract32(insn, 21, 1) == 0) { | |
6928 | /* Floating point to fixed point conversions */ | |
6929 | disas_fp_fixed_conv(s, insn); | |
6930 | } else { | |
6931 | switch (extract32(insn, 10, 2)) { | |
6932 | case 1: | |
6933 | /* Floating point conditional compare */ | |
6934 | disas_fp_ccomp(s, insn); | |
6935 | break; | |
6936 | case 2: | |
6937 | /* Floating point data-processing (2 source) */ | |
6938 | disas_fp_2src(s, insn); | |
6939 | break; | |
6940 | case 3: | |
6941 | /* Floating point conditional select */ | |
6942 | disas_fp_csel(s, insn); | |
6943 | break; | |
6944 | case 0: | |
6945 | switch (ctz32(extract32(insn, 12, 4))) { | |
6946 | case 0: /* [15:12] == xxx1 */ | |
6947 | /* Floating point immediate */ | |
6948 | disas_fp_imm(s, insn); | |
6949 | break; | |
6950 | case 1: /* [15:12] == xx10 */ | |
6951 | /* Floating point compare */ | |
6952 | disas_fp_compare(s, insn); | |
6953 | break; | |
6954 | case 2: /* [15:12] == x100 */ | |
6955 | /* Floating point data-processing (1 source) */ | |
6956 | disas_fp_1src(s, insn); | |
6957 | break; | |
6958 | case 3: /* [15:12] == 1000 */ | |
6959 | unallocated_encoding(s); | |
6960 | break; | |
6961 | default: /* [15:12] == 0000 */ | |
6962 | /* Floating point <-> integer conversions */ | |
6963 | disas_fp_int_conv(s, insn); | |
6964 | break; | |
6965 | } | |
6966 | break; | |
6967 | } | |
6968 | } | |
6969 | } | |
6970 | ||
5c73747f PM |
6971 | static void do_ext64(DisasContext *s, TCGv_i64 tcg_left, TCGv_i64 tcg_right, |
6972 | int pos) | |
6973 | { | |
6974 | /* Extract 64 bits from the middle of two concatenated 64 bit | |
6975 | * vector register slices left:right. The extracted bits start | |
6976 | * at 'pos' bits into the right (least significant) side. | |
6977 | * We return the result in tcg_right, and guarantee not to | |
6978 | * trash tcg_left. | |
6979 | */ | |
6980 | TCGv_i64 tcg_tmp = tcg_temp_new_i64(); | |
6981 | assert(pos > 0 && pos < 64); | |
6982 | ||
6983 | tcg_gen_shri_i64(tcg_right, tcg_right, pos); | |
6984 | tcg_gen_shli_i64(tcg_tmp, tcg_left, 64 - pos); | |
6985 | tcg_gen_or_i64(tcg_right, tcg_right, tcg_tmp); | |
6986 | ||
6987 | tcg_temp_free_i64(tcg_tmp); | |
6988 | } | |
6989 | ||
4ce31af4 | 6990 | /* EXT |
384b26fb AB |
6991 | * 31 30 29 24 23 22 21 20 16 15 14 11 10 9 5 4 0 |
6992 | * +---+---+-------------+-----+---+------+---+------+---+------+------+ | |
6993 | * | 0 | Q | 1 0 1 1 1 0 | op2 | 0 | Rm | 0 | imm4 | 0 | Rn | Rd | | |
6994 | * +---+---+-------------+-----+---+------+---+------+---+------+------+ | |
6995 | */ | |
6996 | static void disas_simd_ext(DisasContext *s, uint32_t insn) | |
6997 | { | |
5c73747f PM |
6998 | int is_q = extract32(insn, 30, 1); |
6999 | int op2 = extract32(insn, 22, 2); | |
7000 | int imm4 = extract32(insn, 11, 4); | |
7001 | int rm = extract32(insn, 16, 5); | |
7002 | int rn = extract32(insn, 5, 5); | |
7003 | int rd = extract32(insn, 0, 5); | |
7004 | int pos = imm4 << 3; | |
7005 | TCGv_i64 tcg_resl, tcg_resh; | |
7006 | ||
7007 | if (op2 != 0 || (!is_q && extract32(imm4, 3, 1))) { | |
7008 | unallocated_encoding(s); | |
7009 | return; | |
7010 | } | |
7011 | ||
8c6afa6a PM |
7012 | if (!fp_access_check(s)) { |
7013 | return; | |
7014 | } | |
7015 | ||
5c73747f PM |
7016 | tcg_resh = tcg_temp_new_i64(); |
7017 | tcg_resl = tcg_temp_new_i64(); | |
7018 | ||
7019 | /* Vd gets bits starting at pos bits into Vm:Vn. This is | |
7020 | * either extracting 128 bits from a 128:128 concatenation, or | |
7021 | * extracting 64 bits from a 64:64 concatenation. | |
7022 | */ | |
7023 | if (!is_q) { | |
7024 | read_vec_element(s, tcg_resl, rn, 0, MO_64); | |
7025 | if (pos != 0) { | |
7026 | read_vec_element(s, tcg_resh, rm, 0, MO_64); | |
7027 | do_ext64(s, tcg_resh, tcg_resl, pos); | |
7028 | } | |
5c73747f PM |
7029 | } else { |
7030 | TCGv_i64 tcg_hh; | |
7031 | typedef struct { | |
7032 | int reg; | |
7033 | int elt; | |
7034 | } EltPosns; | |
7035 | EltPosns eltposns[] = { {rn, 0}, {rn, 1}, {rm, 0}, {rm, 1} }; | |
7036 | EltPosns *elt = eltposns; | |
7037 | ||
7038 | if (pos >= 64) { | |
7039 | elt++; | |
7040 | pos -= 64; | |
7041 | } | |
7042 | ||
7043 | read_vec_element(s, tcg_resl, elt->reg, elt->elt, MO_64); | |
7044 | elt++; | |
7045 | read_vec_element(s, tcg_resh, elt->reg, elt->elt, MO_64); | |
7046 | elt++; | |
7047 | if (pos != 0) { | |
7048 | do_ext64(s, tcg_resh, tcg_resl, pos); | |
7049 | tcg_hh = tcg_temp_new_i64(); | |
7050 | read_vec_element(s, tcg_hh, elt->reg, elt->elt, MO_64); | |
7051 | do_ext64(s, tcg_hh, tcg_resh, pos); | |
7052 | tcg_temp_free_i64(tcg_hh); | |
7053 | } | |
7054 | } | |
7055 | ||
7056 | write_vec_element(s, tcg_resl, rd, 0, MO_64); | |
7057 | tcg_temp_free_i64(tcg_resl); | |
e1f77859 RH |
7058 | if (is_q) { |
7059 | write_vec_element(s, tcg_resh, rd, 1, MO_64); | |
7060 | } | |
5c73747f | 7061 | tcg_temp_free_i64(tcg_resh); |
e1f77859 | 7062 | clear_vec_high(s, is_q, rd); |
384b26fb AB |
7063 | } |
7064 | ||
4ce31af4 | 7065 | /* TBL/TBX |
384b26fb AB |
7066 | * 31 30 29 24 23 22 21 20 16 15 14 13 12 11 10 9 5 4 0 |
7067 | * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+ | |
7068 | * | 0 | Q | 0 0 1 1 1 0 | op2 | 0 | Rm | 0 | len | op | 0 0 | Rn | Rd | | |
7069 | * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+ | |
7070 | */ | |
7071 | static void disas_simd_tb(DisasContext *s, uint32_t insn) | |
7072 | { | |
7c51048f MM |
7073 | int op2 = extract32(insn, 22, 2); |
7074 | int is_q = extract32(insn, 30, 1); | |
7075 | int rm = extract32(insn, 16, 5); | |
7076 | int rn = extract32(insn, 5, 5); | |
7077 | int rd = extract32(insn, 0, 5); | |
7078 | int is_tblx = extract32(insn, 12, 1); | |
7079 | int len = extract32(insn, 13, 2); | |
7080 | TCGv_i64 tcg_resl, tcg_resh, tcg_idx; | |
7081 | TCGv_i32 tcg_regno, tcg_numregs; | |
7082 | ||
7083 | if (op2 != 0) { | |
7084 | unallocated_encoding(s); | |
7085 | return; | |
7086 | } | |
7087 | ||
8c6afa6a PM |
7088 | if (!fp_access_check(s)) { |
7089 | return; | |
7090 | } | |
7091 | ||
7c51048f MM |
7092 | /* This does a table lookup: for every byte element in the input |
7093 | * we index into a table formed from up to four vector registers, | |
7094 | * and then the output is the result of the lookups. Our helper | |
7095 | * function does the lookup operation for a single 64 bit part of | |
7096 | * the input. | |
7097 | */ | |
7098 | tcg_resl = tcg_temp_new_i64(); | |
e1f77859 | 7099 | tcg_resh = NULL; |
7c51048f MM |
7100 | |
7101 | if (is_tblx) { | |
7102 | read_vec_element(s, tcg_resl, rd, 0, MO_64); | |
7103 | } else { | |
7104 | tcg_gen_movi_i64(tcg_resl, 0); | |
7105 | } | |
e1f77859 RH |
7106 | |
7107 | if (is_q) { | |
7108 | tcg_resh = tcg_temp_new_i64(); | |
7109 | if (is_tblx) { | |
7110 | read_vec_element(s, tcg_resh, rd, 1, MO_64); | |
7111 | } else { | |
7112 | tcg_gen_movi_i64(tcg_resh, 0); | |
7113 | } | |
7c51048f MM |
7114 | } |
7115 | ||
7116 | tcg_idx = tcg_temp_new_i64(); | |
7117 | tcg_regno = tcg_const_i32(rn); | |
7118 | tcg_numregs = tcg_const_i32(len + 1); | |
7119 | read_vec_element(s, tcg_idx, rm, 0, MO_64); | |
7120 | gen_helper_simd_tbl(tcg_resl, cpu_env, tcg_resl, tcg_idx, | |
7121 | tcg_regno, tcg_numregs); | |
7122 | if (is_q) { | |
7123 | read_vec_element(s, tcg_idx, rm, 1, MO_64); | |
7124 | gen_helper_simd_tbl(tcg_resh, cpu_env, tcg_resh, tcg_idx, | |
7125 | tcg_regno, tcg_numregs); | |
7126 | } | |
7127 | tcg_temp_free_i64(tcg_idx); | |
7128 | tcg_temp_free_i32(tcg_regno); | |
7129 | tcg_temp_free_i32(tcg_numregs); | |
7130 | ||
7131 | write_vec_element(s, tcg_resl, rd, 0, MO_64); | |
7132 | tcg_temp_free_i64(tcg_resl); | |
e1f77859 RH |
7133 | |
7134 | if (is_q) { | |
7135 | write_vec_element(s, tcg_resh, rd, 1, MO_64); | |
7136 | tcg_temp_free_i64(tcg_resh); | |
7137 | } | |
7138 | clear_vec_high(s, is_q, rd); | |
384b26fb AB |
7139 | } |
7140 | ||
4ce31af4 | 7141 | /* ZIP/UZP/TRN |
384b26fb AB |
7142 | * 31 30 29 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0 |
7143 | * +---+---+-------------+------+---+------+---+------------------+------+ | |
7144 | * | 0 | Q | 0 0 1 1 1 0 | size | 0 | Rm | 0 | opc | 1 0 | Rn | Rd | | |
7145 | * +---+---+-------------+------+---+------+---+------------------+------+ | |
7146 | */ | |
7147 | static void disas_simd_zip_trn(DisasContext *s, uint32_t insn) | |
7148 | { | |
5fa5469c MM |
7149 | int rd = extract32(insn, 0, 5); |
7150 | int rn = extract32(insn, 5, 5); | |
7151 | int rm = extract32(insn, 16, 5); | |
7152 | int size = extract32(insn, 22, 2); | |
7153 | /* opc field bits [1:0] indicate ZIP/UZP/TRN; | |
7154 | * bit 2 indicates 1 vs 2 variant of the insn. | |
7155 | */ | |
7156 | int opcode = extract32(insn, 12, 2); | |
7157 | bool part = extract32(insn, 14, 1); | |
7158 | bool is_q = extract32(insn, 30, 1); | |
7159 | int esize = 8 << size; | |
7160 | int i, ofs; | |
7161 | int datasize = is_q ? 128 : 64; | |
7162 | int elements = datasize / esize; | |
7163 | TCGv_i64 tcg_res, tcg_resl, tcg_resh; | |
7164 | ||
7165 | if (opcode == 0 || (size == 3 && !is_q)) { | |
7166 | unallocated_encoding(s); | |
7167 | return; | |
7168 | } | |
7169 | ||
8c6afa6a PM |
7170 | if (!fp_access_check(s)) { |
7171 | return; | |
7172 | } | |
7173 | ||
5fa5469c | 7174 | tcg_resl = tcg_const_i64(0); |
e1f77859 | 7175 | tcg_resh = is_q ? tcg_const_i64(0) : NULL; |
5fa5469c MM |
7176 | tcg_res = tcg_temp_new_i64(); |
7177 | ||
7178 | for (i = 0; i < elements; i++) { | |
7179 | switch (opcode) { | |
7180 | case 1: /* UZP1/2 */ | |
7181 | { | |
7182 | int midpoint = elements / 2; | |
7183 | if (i < midpoint) { | |
7184 | read_vec_element(s, tcg_res, rn, 2 * i + part, size); | |
7185 | } else { | |
7186 | read_vec_element(s, tcg_res, rm, | |
7187 | 2 * (i - midpoint) + part, size); | |
7188 | } | |
7189 | break; | |
7190 | } | |
7191 | case 2: /* TRN1/2 */ | |
7192 | if (i & 1) { | |
7193 | read_vec_element(s, tcg_res, rm, (i & ~1) + part, size); | |
7194 | } else { | |
7195 | read_vec_element(s, tcg_res, rn, (i & ~1) + part, size); | |
7196 | } | |
7197 | break; | |
7198 | case 3: /* ZIP1/2 */ | |
7199 | { | |
7200 | int base = part * elements / 2; | |
7201 | if (i & 1) { | |
7202 | read_vec_element(s, tcg_res, rm, base + (i >> 1), size); | |
7203 | } else { | |
7204 | read_vec_element(s, tcg_res, rn, base + (i >> 1), size); | |
7205 | } | |
7206 | break; | |
7207 | } | |
7208 | default: | |
7209 | g_assert_not_reached(); | |
7210 | } | |
7211 | ||
7212 | ofs = i * esize; | |
7213 | if (ofs < 64) { | |
7214 | tcg_gen_shli_i64(tcg_res, tcg_res, ofs); | |
7215 | tcg_gen_or_i64(tcg_resl, tcg_resl, tcg_res); | |
7216 | } else { | |
7217 | tcg_gen_shli_i64(tcg_res, tcg_res, ofs - 64); | |
7218 | tcg_gen_or_i64(tcg_resh, tcg_resh, tcg_res); | |
7219 | } | |
7220 | } | |
7221 | ||
7222 | tcg_temp_free_i64(tcg_res); | |
7223 | ||
7224 | write_vec_element(s, tcg_resl, rd, 0, MO_64); | |
7225 | tcg_temp_free_i64(tcg_resl); | |
e1f77859 RH |
7226 | |
7227 | if (is_q) { | |
7228 | write_vec_element(s, tcg_resh, rd, 1, MO_64); | |
7229 | tcg_temp_free_i64(tcg_resh); | |
7230 | } | |
7231 | clear_vec_high(s, is_q, rd); | |
384b26fb AB |
7232 | } |
7233 | ||
807cdd50 AB |
7234 | /* |
7235 | * do_reduction_op helper | |
7236 | * | |
7237 | * This mirrors the Reduce() pseudocode in the ARM ARM. It is | |
7238 | * important for correct NaN propagation that we do these | |
7239 | * operations in exactly the order specified by the pseudocode. | |
7240 | * | |
7241 | * This is a recursive function, TCG temps should be freed by the | |
7242 | * calling function once it is done with the values. | |
7243 | */ | |
7244 | static TCGv_i32 do_reduction_op(DisasContext *s, int fpopcode, int rn, | |
7245 | int esize, int size, int vmap, TCGv_ptr fpst) | |
7246 | { | |
7247 | if (esize == size) { | |
7248 | int element; | |
14776ab5 | 7249 | MemOp msize = esize == 16 ? MO_16 : MO_32; |
807cdd50 AB |
7250 | TCGv_i32 tcg_elem; |
7251 | ||
7252 | /* We should have one register left here */ | |
7253 | assert(ctpop8(vmap) == 1); | |
7254 | element = ctz32(vmap); | |
7255 | assert(element < 8); | |
7256 | ||
7257 | tcg_elem = tcg_temp_new_i32(); | |
7258 | read_vec_element_i32(s, tcg_elem, rn, element, msize); | |
7259 | return tcg_elem; | |
4a0ff1ce | 7260 | } else { |
807cdd50 AB |
7261 | int bits = size / 2; |
7262 | int shift = ctpop8(vmap) / 2; | |
7263 | int vmap_lo = (vmap >> shift) & vmap; | |
7264 | int vmap_hi = (vmap & ~vmap_lo); | |
7265 | TCGv_i32 tcg_hi, tcg_lo, tcg_res; | |
7266 | ||
7267 | tcg_hi = do_reduction_op(s, fpopcode, rn, esize, bits, vmap_hi, fpst); | |
7268 | tcg_lo = do_reduction_op(s, fpopcode, rn, esize, bits, vmap_lo, fpst); | |
7269 | tcg_res = tcg_temp_new_i32(); | |
7270 | ||
7271 | switch (fpopcode) { | |
7272 | case 0x0c: /* fmaxnmv half-precision */ | |
7273 | gen_helper_advsimd_maxnumh(tcg_res, tcg_lo, tcg_hi, fpst); | |
7274 | break; | |
7275 | case 0x0f: /* fmaxv half-precision */ | |
7276 | gen_helper_advsimd_maxh(tcg_res, tcg_lo, tcg_hi, fpst); | |
7277 | break; | |
7278 | case 0x1c: /* fminnmv half-precision */ | |
7279 | gen_helper_advsimd_minnumh(tcg_res, tcg_lo, tcg_hi, fpst); | |
7280 | break; | |
7281 | case 0x1f: /* fminv half-precision */ | |
7282 | gen_helper_advsimd_minh(tcg_res, tcg_lo, tcg_hi, fpst); | |
7283 | break; | |
7284 | case 0x2c: /* fmaxnmv */ | |
7285 | gen_helper_vfp_maxnums(tcg_res, tcg_lo, tcg_hi, fpst); | |
7286 | break; | |
7287 | case 0x2f: /* fmaxv */ | |
7288 | gen_helper_vfp_maxs(tcg_res, tcg_lo, tcg_hi, fpst); | |
7289 | break; | |
7290 | case 0x3c: /* fminnmv */ | |
7291 | gen_helper_vfp_minnums(tcg_res, tcg_lo, tcg_hi, fpst); | |
7292 | break; | |
7293 | case 0x3f: /* fminv */ | |
7294 | gen_helper_vfp_mins(tcg_res, tcg_lo, tcg_hi, fpst); | |
7295 | break; | |
7296 | default: | |
7297 | g_assert_not_reached(); | |
4a0ff1ce | 7298 | } |
807cdd50 AB |
7299 | |
7300 | tcg_temp_free_i32(tcg_hi); | |
7301 | tcg_temp_free_i32(tcg_lo); | |
7302 | return tcg_res; | |
4a0ff1ce MM |
7303 | } |
7304 | } | |
7305 | ||
4ce31af4 | 7306 | /* AdvSIMD across lanes |
384b26fb AB |
7307 | * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0 |
7308 | * +---+---+---+-----------+------+-----------+--------+-----+------+------+ | |
7309 | * | 0 | Q | U | 0 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd | | |
7310 | * +---+---+---+-----------+------+-----------+--------+-----+------+------+ | |
7311 | */ | |
7312 | static void disas_simd_across_lanes(DisasContext *s, uint32_t insn) | |
7313 | { | |
4a0ff1ce MM |
7314 | int rd = extract32(insn, 0, 5); |
7315 | int rn = extract32(insn, 5, 5); | |
7316 | int size = extract32(insn, 22, 2); | |
7317 | int opcode = extract32(insn, 12, 5); | |
7318 | bool is_q = extract32(insn, 30, 1); | |
7319 | bool is_u = extract32(insn, 29, 1); | |
7320 | bool is_fp = false; | |
7321 | bool is_min = false; | |
7322 | int esize; | |
7323 | int elements; | |
7324 | int i; | |
7325 | TCGv_i64 tcg_res, tcg_elt; | |
7326 | ||
7327 | switch (opcode) { | |
7328 | case 0x1b: /* ADDV */ | |
7329 | if (is_u) { | |
7330 | unallocated_encoding(s); | |
7331 | return; | |
7332 | } | |
7333 | /* fall through */ | |
7334 | case 0x3: /* SADDLV, UADDLV */ | |
7335 | case 0xa: /* SMAXV, UMAXV */ | |
7336 | case 0x1a: /* SMINV, UMINV */ | |
7337 | if (size == 3 || (size == 2 && !is_q)) { | |
7338 | unallocated_encoding(s); | |
7339 | return; | |
7340 | } | |
7341 | break; | |
7342 | case 0xc: /* FMAXNMV, FMINNMV */ | |
7343 | case 0xf: /* FMAXV, FMINV */ | |
807cdd50 AB |
7344 | /* Bit 1 of size field encodes min vs max and the actual size |
7345 | * depends on the encoding of the U bit. If not set (and FP16 | |
7346 | * enabled) then we do half-precision float instead of single | |
7347 | * precision. | |
4a0ff1ce MM |
7348 | */ |
7349 | is_min = extract32(size, 1, 1); | |
7350 | is_fp = true; | |
5763190f | 7351 | if (!is_u && dc_isar_feature(aa64_fp16, s)) { |
807cdd50 AB |
7352 | size = 1; |
7353 | } else if (!is_u || !is_q || extract32(size, 0, 1)) { | |
7354 | unallocated_encoding(s); | |
7355 | return; | |
7356 | } else { | |
7357 | size = 2; | |
7358 | } | |
4a0ff1ce MM |
7359 | break; |
7360 | default: | |
7361 | unallocated_encoding(s); | |
7362 | return; | |
7363 | } | |
7364 | ||
8c6afa6a PM |
7365 | if (!fp_access_check(s)) { |
7366 | return; | |
7367 | } | |
7368 | ||
4a0ff1ce MM |
7369 | esize = 8 << size; |
7370 | elements = (is_q ? 128 : 64) / esize; | |
7371 | ||
7372 | tcg_res = tcg_temp_new_i64(); | |
7373 | tcg_elt = tcg_temp_new_i64(); | |
7374 | ||
7375 | /* These instructions operate across all lanes of a vector | |
7376 | * to produce a single result. We can guarantee that a 64 | |
7377 | * bit intermediate is sufficient: | |
7378 | * + for [US]ADDLV the maximum element size is 32 bits, and | |
7379 | * the result type is 64 bits | |
7380 | * + for FMAX*V, FMIN*V, ADDV the intermediate type is the | |
7381 | * same as the element size, which is 32 bits at most | |
7382 | * For the integer operations we can choose to work at 64 | |
7383 | * or 32 bits and truncate at the end; for simplicity | |
7384 | * we use 64 bits always. The floating point | |
7385 | * ops do require 32 bit intermediates, though. | |
7386 | */ | |
7387 | if (!is_fp) { | |
7388 | read_vec_element(s, tcg_res, rn, 0, size | (is_u ? 0 : MO_SIGN)); | |
7389 | ||
7390 | for (i = 1; i < elements; i++) { | |
7391 | read_vec_element(s, tcg_elt, rn, i, size | (is_u ? 0 : MO_SIGN)); | |
7392 | ||
7393 | switch (opcode) { | |
7394 | case 0x03: /* SADDLV / UADDLV */ | |
7395 | case 0x1b: /* ADDV */ | |
7396 | tcg_gen_add_i64(tcg_res, tcg_res, tcg_elt); | |
7397 | break; | |
7398 | case 0x0a: /* SMAXV / UMAXV */ | |
ecb8ab8d RH |
7399 | if (is_u) { |
7400 | tcg_gen_umax_i64(tcg_res, tcg_res, tcg_elt); | |
7401 | } else { | |
7402 | tcg_gen_smax_i64(tcg_res, tcg_res, tcg_elt); | |
7403 | } | |
4a0ff1ce MM |
7404 | break; |
7405 | case 0x1a: /* SMINV / UMINV */ | |
ecb8ab8d RH |
7406 | if (is_u) { |
7407 | tcg_gen_umin_i64(tcg_res, tcg_res, tcg_elt); | |
7408 | } else { | |
7409 | tcg_gen_smin_i64(tcg_res, tcg_res, tcg_elt); | |
7410 | } | |
4a0ff1ce MM |
7411 | break; |
7412 | default: | |
7413 | g_assert_not_reached(); | |
7414 | } | |
7415 | ||
7416 | } | |
7417 | } else { | |
807cdd50 AB |
7418 | /* Floating point vector reduction ops which work across 32 |
7419 | * bit (single) or 16 bit (half-precision) intermediates. | |
4a0ff1ce MM |
7420 | * Note that correct NaN propagation requires that we do these |
7421 | * operations in exactly the order specified by the pseudocode. | |
7422 | */ | |
807cdd50 AB |
7423 | TCGv_ptr fpst = get_fpstatus_ptr(size == MO_16); |
7424 | int fpopcode = opcode | is_min << 4 | is_u << 5; | |
7425 | int vmap = (1 << elements) - 1; | |
7426 | TCGv_i32 tcg_res32 = do_reduction_op(s, fpopcode, rn, esize, | |
7427 | (is_q ? 128 : 64), vmap, fpst); | |
7428 | tcg_gen_extu_i32_i64(tcg_res, tcg_res32); | |
7429 | tcg_temp_free_i32(tcg_res32); | |
4a0ff1ce MM |
7430 | tcg_temp_free_ptr(fpst); |
7431 | } | |
7432 | ||
7433 | tcg_temp_free_i64(tcg_elt); | |
7434 | ||
7435 | /* Now truncate the result to the width required for the final output */ | |
7436 | if (opcode == 0x03) { | |
7437 | /* SADDLV, UADDLV: result is 2*esize */ | |
7438 | size++; | |
7439 | } | |
7440 | ||
7441 | switch (size) { | |
7442 | case 0: | |
7443 | tcg_gen_ext8u_i64(tcg_res, tcg_res); | |
7444 | break; | |
7445 | case 1: | |
7446 | tcg_gen_ext16u_i64(tcg_res, tcg_res); | |
7447 | break; | |
7448 | case 2: | |
7449 | tcg_gen_ext32u_i64(tcg_res, tcg_res); | |
7450 | break; | |
7451 | case 3: | |
7452 | break; | |
7453 | default: | |
7454 | g_assert_not_reached(); | |
7455 | } | |
7456 | ||
7457 | write_fp_dreg(s, rd, tcg_res); | |
7458 | tcg_temp_free_i64(tcg_res); | |
384b26fb AB |
7459 | } |
7460 | ||
4ce31af4 | 7461 | /* DUP (Element, Vector) |
67bb9389 AB |
7462 | * |
7463 | * 31 30 29 21 20 16 15 10 9 5 4 0 | |
7464 | * +---+---+-------------------+--------+-------------+------+------+ | |
7465 | * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd | | |
7466 | * +---+---+-------------------+--------+-------------+------+------+ | |
7467 | * | |
7468 | * size: encoded in imm5 (see ARM ARM LowestSetBit()) | |
7469 | */ | |
7470 | static void handle_simd_dupe(DisasContext *s, int is_q, int rd, int rn, | |
7471 | int imm5) | |
7472 | { | |
7473 | int size = ctz32(imm5); | |
550a0489 | 7474 | int index; |
67bb9389 AB |
7475 | |
7476 | if (size > 3 || (size == 3 && !is_q)) { | |
7477 | unallocated_encoding(s); | |
7478 | return; | |
7479 | } | |
7480 | ||
8c6afa6a PM |
7481 | if (!fp_access_check(s)) { |
7482 | return; | |
7483 | } | |
7484 | ||
550a0489 | 7485 | index = imm5 >> (size + 1); |
861a1ded RH |
7486 | tcg_gen_gvec_dup_mem(size, vec_full_reg_offset(s, rd), |
7487 | vec_reg_offset(s, rn, index, size), | |
7488 | is_q ? 16 : 8, vec_full_reg_size(s)); | |
67bb9389 AB |
7489 | } |
7490 | ||
4ce31af4 | 7491 | /* DUP (element, scalar) |
360a6f2d PM |
7492 | * 31 21 20 16 15 10 9 5 4 0 |
7493 | * +-----------------------+--------+-------------+------+------+ | |
7494 | * | 0 1 0 1 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd | | |
7495 | * +-----------------------+--------+-------------+------+------+ | |
7496 | */ | |
7497 | static void handle_simd_dupes(DisasContext *s, int rd, int rn, | |
7498 | int imm5) | |
7499 | { | |
7500 | int size = ctz32(imm5); | |
7501 | int index; | |
7502 | TCGv_i64 tmp; | |
7503 | ||
7504 | if (size > 3) { | |
7505 | unallocated_encoding(s); | |
7506 | return; | |
7507 | } | |
7508 | ||
8c6afa6a PM |
7509 | if (!fp_access_check(s)) { |
7510 | return; | |
7511 | } | |
7512 | ||
360a6f2d PM |
7513 | index = imm5 >> (size + 1); |
7514 | ||
7515 | /* This instruction just extracts the specified element and | |
7516 | * zero-extends it into the bottom of the destination register. | |
7517 | */ | |
7518 | tmp = tcg_temp_new_i64(); | |
7519 | read_vec_element(s, tmp, rn, index, size); | |
7520 | write_fp_dreg(s, rd, tmp); | |
7521 | tcg_temp_free_i64(tmp); | |
7522 | } | |
7523 | ||
4ce31af4 | 7524 | /* DUP (General) |
67bb9389 AB |
7525 | * |
7526 | * 31 30 29 21 20 16 15 10 9 5 4 0 | |
7527 | * +---+---+-------------------+--------+-------------+------+------+ | |
7528 | * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 1 1 | Rn | Rd | | |
7529 | * +---+---+-------------------+--------+-------------+------+------+ | |
7530 | * | |
7531 | * size: encoded in imm5 (see ARM ARM LowestSetBit()) | |
7532 | */ | |
7533 | static void handle_simd_dupg(DisasContext *s, int is_q, int rd, int rn, | |
7534 | int imm5) | |
7535 | { | |
7536 | int size = ctz32(imm5); | |
861a1ded | 7537 | uint32_t dofs, oprsz, maxsz; |
67bb9389 AB |
7538 | |
7539 | if (size > 3 || ((size == 3) && !is_q)) { | |
7540 | unallocated_encoding(s); | |
7541 | return; | |
7542 | } | |
8c6afa6a PM |
7543 | |
7544 | if (!fp_access_check(s)) { | |
7545 | return; | |
7546 | } | |
7547 | ||
861a1ded RH |
7548 | dofs = vec_full_reg_offset(s, rd); |
7549 | oprsz = is_q ? 16 : 8; | |
7550 | maxsz = vec_full_reg_size(s); | |
7551 | ||
7552 | tcg_gen_gvec_dup_i64(size, dofs, oprsz, maxsz, cpu_reg(s, rn)); | |
67bb9389 AB |
7553 | } |
7554 | ||
4ce31af4 | 7555 | /* INS (Element) |
67bb9389 AB |
7556 | * |
7557 | * 31 21 20 16 15 14 11 10 9 5 4 0 | |
7558 | * +-----------------------+--------+------------+---+------+------+ | |
7559 | * | 0 1 1 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd | | |
7560 | * +-----------------------+--------+------------+---+------+------+ | |
7561 | * | |
7562 | * size: encoded in imm5 (see ARM ARM LowestSetBit()) | |
7563 | * index: encoded in imm5<4:size+1> | |
7564 | */ | |
7565 | static void handle_simd_inse(DisasContext *s, int rd, int rn, | |
7566 | int imm4, int imm5) | |
7567 | { | |
7568 | int size = ctz32(imm5); | |
7569 | int src_index, dst_index; | |
7570 | TCGv_i64 tmp; | |
7571 | ||
7572 | if (size > 3) { | |
7573 | unallocated_encoding(s); | |
7574 | return; | |
7575 | } | |
8c6afa6a PM |
7576 | |
7577 | if (!fp_access_check(s)) { | |
7578 | return; | |
7579 | } | |
7580 | ||
67bb9389 AB |
7581 | dst_index = extract32(imm5, 1+size, 5); |
7582 | src_index = extract32(imm4, size, 4); | |
7583 | ||
7584 | tmp = tcg_temp_new_i64(); | |
7585 | ||
7586 | read_vec_element(s, tmp, rn, src_index, size); | |
7587 | write_vec_element(s, tmp, rd, dst_index, size); | |
7588 | ||
7589 | tcg_temp_free_i64(tmp); | |
528dc354 RH |
7590 | |
7591 | /* INS is considered a 128-bit write for SVE. */ | |
7592 | clear_vec_high(s, true, rd); | |
67bb9389 AB |
7593 | } |
7594 | ||
7595 | ||
4ce31af4 | 7596 | /* INS (General) |
67bb9389 AB |
7597 | * |
7598 | * 31 21 20 16 15 10 9 5 4 0 | |
7599 | * +-----------------------+--------+-------------+------+------+ | |
7600 | * | 0 1 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 1 1 1 | Rn | Rd | | |
7601 | * +-----------------------+--------+-------------+------+------+ | |
7602 | * | |
7603 | * size: encoded in imm5 (see ARM ARM LowestSetBit()) | |
7604 | * index: encoded in imm5<4:size+1> | |
7605 | */ | |
7606 | static void handle_simd_insg(DisasContext *s, int rd, int rn, int imm5) | |
7607 | { | |
7608 | int size = ctz32(imm5); | |
7609 | int idx; | |
7610 | ||
7611 | if (size > 3) { | |
7612 | unallocated_encoding(s); | |
7613 | return; | |
7614 | } | |
7615 | ||
8c6afa6a PM |
7616 | if (!fp_access_check(s)) { |
7617 | return; | |
7618 | } | |
7619 | ||
67bb9389 AB |
7620 | idx = extract32(imm5, 1 + size, 4 - size); |
7621 | write_vec_element(s, cpu_reg(s, rn), rd, idx, size); | |
528dc354 RH |
7622 | |
7623 | /* INS is considered a 128-bit write for SVE. */ | |
7624 | clear_vec_high(s, true, rd); | |
67bb9389 AB |
7625 | } |
7626 | ||
7627 | /* | |
4ce31af4 PM |
7628 | * UMOV (General) |
7629 | * SMOV (General) | |
67bb9389 AB |
7630 | * |
7631 | * 31 30 29 21 20 16 15 12 10 9 5 4 0 | |
7632 | * +---+---+-------------------+--------+-------------+------+------+ | |
7633 | * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 1 U 1 1 | Rn | Rd | | |
7634 | * +---+---+-------------------+--------+-------------+------+------+ | |
7635 | * | |
7636 | * U: unsigned when set | |
7637 | * size: encoded in imm5 (see ARM ARM LowestSetBit()) | |
7638 | */ | |
7639 | static void handle_simd_umov_smov(DisasContext *s, int is_q, int is_signed, | |
7640 | int rn, int rd, int imm5) | |
7641 | { | |
7642 | int size = ctz32(imm5); | |
7643 | int element; | |
7644 | TCGv_i64 tcg_rd; | |
7645 | ||
7646 | /* Check for UnallocatedEncodings */ | |
7647 | if (is_signed) { | |
7648 | if (size > 2 || (size == 2 && !is_q)) { | |
7649 | unallocated_encoding(s); | |
7650 | return; | |
7651 | } | |
7652 | } else { | |
7653 | if (size > 3 | |
7654 | || (size < 3 && is_q) | |
7655 | || (size == 3 && !is_q)) { | |
7656 | unallocated_encoding(s); | |
7657 | return; | |
7658 | } | |
7659 | } | |
8c6afa6a PM |
7660 | |
7661 | if (!fp_access_check(s)) { | |
7662 | return; | |
7663 | } | |
7664 | ||
67bb9389 AB |
7665 | element = extract32(imm5, 1+size, 4); |
7666 | ||
7667 | tcg_rd = cpu_reg(s, rd); | |
7668 | read_vec_element(s, tcg_rd, rn, element, size | (is_signed ? MO_SIGN : 0)); | |
7669 | if (is_signed && !is_q) { | |
7670 | tcg_gen_ext32u_i64(tcg_rd, tcg_rd); | |
7671 | } | |
7672 | } | |
7673 | ||
4ce31af4 | 7674 | /* AdvSIMD copy |
384b26fb AB |
7675 | * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0 |
7676 | * +---+---+----+-----------------+------+---+------+---+------+------+ | |
7677 | * | 0 | Q | op | 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd | | |
7678 | * +---+---+----+-----------------+------+---+------+---+------+------+ | |
7679 | */ | |
7680 | static void disas_simd_copy(DisasContext *s, uint32_t insn) | |
7681 | { | |
67bb9389 AB |
7682 | int rd = extract32(insn, 0, 5); |
7683 | int rn = extract32(insn, 5, 5); | |
7684 | int imm4 = extract32(insn, 11, 4); | |
7685 | int op = extract32(insn, 29, 1); | |
7686 | int is_q = extract32(insn, 30, 1); | |
7687 | int imm5 = extract32(insn, 16, 5); | |
7688 | ||
7689 | if (op) { | |
7690 | if (is_q) { | |
7691 | /* INS (element) */ | |
7692 | handle_simd_inse(s, rd, rn, imm4, imm5); | |
7693 | } else { | |
7694 | unallocated_encoding(s); | |
7695 | } | |
7696 | } else { | |
7697 | switch (imm4) { | |
7698 | case 0: | |
7699 | /* DUP (element - vector) */ | |
7700 | handle_simd_dupe(s, is_q, rd, rn, imm5); | |
7701 | break; | |
7702 | case 1: | |
7703 | /* DUP (general) */ | |
7704 | handle_simd_dupg(s, is_q, rd, rn, imm5); | |
7705 | break; | |
7706 | case 3: | |
7707 | if (is_q) { | |
7708 | /* INS (general) */ | |
7709 | handle_simd_insg(s, rd, rn, imm5); | |
7710 | } else { | |
7711 | unallocated_encoding(s); | |
7712 | } | |
7713 | break; | |
7714 | case 5: | |
7715 | case 7: | |
7716 | /* UMOV/SMOV (is_q indicates 32/64; imm4 indicates signedness) */ | |
7717 | handle_simd_umov_smov(s, is_q, (imm4 == 5), rn, rd, imm5); | |
7718 | break; | |
7719 | default: | |
7720 | unallocated_encoding(s); | |
7721 | break; | |
7722 | } | |
7723 | } | |
384b26fb AB |
7724 | } |
7725 | ||
4ce31af4 | 7726 | /* AdvSIMD modified immediate |
384b26fb AB |
7727 | * 31 30 29 28 19 18 16 15 12 11 10 9 5 4 0 |
7728 | * +---+---+----+---------------------+-----+-------+----+---+-------+------+ | |
7729 | * | 0 | Q | op | 0 1 1 1 1 0 0 0 0 0 | abc | cmode | o2 | 1 | defgh | Rd | | |
7730 | * +---+---+----+---------------------+-----+-------+----+---+-------+------+ | |
f3f8c4f4 AB |
7731 | * |
7732 | * There are a number of operations that can be carried out here: | |
7733 | * MOVI - move (shifted) imm into register | |
7734 | * MVNI - move inverted (shifted) imm into register | |
7735 | * ORR - bitwise OR of (shifted) imm with register | |
7736 | * BIC - bitwise clear of (shifted) imm with register | |
70b4e6a4 AB |
7737 | * With ARMv8.2 we also have: |
7738 | * FMOV half-precision | |
384b26fb AB |
7739 | */ |
7740 | static void disas_simd_mod_imm(DisasContext *s, uint32_t insn) | |
7741 | { | |
f3f8c4f4 AB |
7742 | int rd = extract32(insn, 0, 5); |
7743 | int cmode = extract32(insn, 12, 4); | |
7744 | int cmode_3_1 = extract32(cmode, 1, 3); | |
7745 | int cmode_0 = extract32(cmode, 0, 1); | |
7746 | int o2 = extract32(insn, 11, 1); | |
7747 | uint64_t abcdefgh = extract32(insn, 5, 5) | (extract32(insn, 16, 3) << 5); | |
7748 | bool is_neg = extract32(insn, 29, 1); | |
7749 | bool is_q = extract32(insn, 30, 1); | |
7750 | uint64_t imm = 0; | |
f3f8c4f4 AB |
7751 | |
7752 | if (o2 != 0 || ((cmode == 0xf) && is_neg && !is_q)) { | |
70b4e6a4 | 7753 | /* Check for FMOV (vector, immediate) - half-precision */ |
5763190f | 7754 | if (!(dc_isar_feature(aa64_fp16, s) && o2 && cmode == 0xf)) { |
70b4e6a4 AB |
7755 | unallocated_encoding(s); |
7756 | return; | |
7757 | } | |
f3f8c4f4 AB |
7758 | } |
7759 | ||
8c6afa6a PM |
7760 | if (!fp_access_check(s)) { |
7761 | return; | |
7762 | } | |
7763 | ||
f3f8c4f4 AB |
7764 | /* See AdvSIMDExpandImm() in ARM ARM */ |
7765 | switch (cmode_3_1) { | |
7766 | case 0: /* Replicate(Zeros(24):imm8, 2) */ | |
7767 | case 1: /* Replicate(Zeros(16):imm8:Zeros(8), 2) */ | |
7768 | case 2: /* Replicate(Zeros(8):imm8:Zeros(16), 2) */ | |
7769 | case 3: /* Replicate(imm8:Zeros(24), 2) */ | |
7770 | { | |
7771 | int shift = cmode_3_1 * 8; | |
7772 | imm = bitfield_replicate(abcdefgh << shift, 32); | |
7773 | break; | |
7774 | } | |
7775 | case 4: /* Replicate(Zeros(8):imm8, 4) */ | |
7776 | case 5: /* Replicate(imm8:Zeros(8), 4) */ | |
7777 | { | |
7778 | int shift = (cmode_3_1 & 0x1) * 8; | |
7779 | imm = bitfield_replicate(abcdefgh << shift, 16); | |
7780 | break; | |
7781 | } | |
7782 | case 6: | |
7783 | if (cmode_0) { | |
7784 | /* Replicate(Zeros(8):imm8:Ones(16), 2) */ | |
7785 | imm = (abcdefgh << 16) | 0xffff; | |
7786 | } else { | |
7787 | /* Replicate(Zeros(16):imm8:Ones(8), 2) */ | |
7788 | imm = (abcdefgh << 8) | 0xff; | |
7789 | } | |
7790 | imm = bitfield_replicate(imm, 32); | |
7791 | break; | |
7792 | case 7: | |
7793 | if (!cmode_0 && !is_neg) { | |
7794 | imm = bitfield_replicate(abcdefgh, 8); | |
7795 | } else if (!cmode_0 && is_neg) { | |
7796 | int i; | |
7797 | imm = 0; | |
7798 | for (i = 0; i < 8; i++) { | |
7799 | if ((abcdefgh) & (1 << i)) { | |
7800 | imm |= 0xffULL << (i * 8); | |
7801 | } | |
7802 | } | |
7803 | } else if (cmode_0) { | |
7804 | if (is_neg) { | |
7805 | imm = (abcdefgh & 0x3f) << 48; | |
7806 | if (abcdefgh & 0x80) { | |
7807 | imm |= 0x8000000000000000ULL; | |
7808 | } | |
7809 | if (abcdefgh & 0x40) { | |
7810 | imm |= 0x3fc0000000000000ULL; | |
7811 | } else { | |
7812 | imm |= 0x4000000000000000ULL; | |
7813 | } | |
7814 | } else { | |
70b4e6a4 AB |
7815 | if (o2) { |
7816 | /* FMOV (vector, immediate) - half-precision */ | |
7817 | imm = vfp_expand_imm(MO_16, abcdefgh); | |
7818 | /* now duplicate across the lanes */ | |
7819 | imm = bitfield_replicate(imm, 16); | |
f3f8c4f4 | 7820 | } else { |
70b4e6a4 AB |
7821 | imm = (abcdefgh & 0x3f) << 19; |
7822 | if (abcdefgh & 0x80) { | |
7823 | imm |= 0x80000000; | |
7824 | } | |
7825 | if (abcdefgh & 0x40) { | |
7826 | imm |= 0x3e000000; | |
7827 | } else { | |
7828 | imm |= 0x40000000; | |
7829 | } | |
7830 | imm |= (imm << 32); | |
f3f8c4f4 | 7831 | } |
f3f8c4f4 AB |
7832 | } |
7833 | } | |
7834 | break; | |
70b4e6a4 AB |
7835 | default: |
7836 | fprintf(stderr, "%s: cmode_3_1: %x\n", __func__, cmode_3_1); | |
7837 | g_assert_not_reached(); | |
f3f8c4f4 AB |
7838 | } |
7839 | ||
7840 | if (cmode_3_1 != 7 && is_neg) { | |
7841 | imm = ~imm; | |
7842 | } | |
7843 | ||
861a1ded RH |
7844 | if (!((cmode & 0x9) == 0x1 || (cmode & 0xd) == 0x9)) { |
7845 | /* MOVI or MVNI, with MVNI negation handled above. */ | |
8711e71f RH |
7846 | tcg_gen_gvec_dup_imm(MO_64, vec_full_reg_offset(s, rd), is_q ? 16 : 8, |
7847 | vec_full_reg_size(s), imm); | |
861a1ded | 7848 | } else { |
064e265d RH |
7849 | /* ORR or BIC, with BIC negation to AND handled above. */ |
7850 | if (is_neg) { | |
7851 | gen_gvec_fn2i(s, is_q, rd, rd, imm, tcg_gen_gvec_andi, MO_64); | |
7852 | } else { | |
7853 | gen_gvec_fn2i(s, is_q, rd, rd, imm, tcg_gen_gvec_ori, MO_64); | |
f3f8c4f4 | 7854 | } |
861a1ded | 7855 | } |
384b26fb AB |
7856 | } |
7857 | ||
4ce31af4 | 7858 | /* AdvSIMD scalar copy |
384b26fb AB |
7859 | * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0 |
7860 | * +-----+----+-----------------+------+---+------+---+------+------+ | |
7861 | * | 0 1 | op | 1 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd | | |
7862 | * +-----+----+-----------------+------+---+------+---+------+------+ | |
7863 | */ | |
7864 | static void disas_simd_scalar_copy(DisasContext *s, uint32_t insn) | |
7865 | { | |
360a6f2d PM |
7866 | int rd = extract32(insn, 0, 5); |
7867 | int rn = extract32(insn, 5, 5); | |
7868 | int imm4 = extract32(insn, 11, 4); | |
7869 | int imm5 = extract32(insn, 16, 5); | |
7870 | int op = extract32(insn, 29, 1); | |
7871 | ||
7872 | if (op != 0 || imm4 != 0) { | |
7873 | unallocated_encoding(s); | |
7874 | return; | |
7875 | } | |
7876 | ||
7877 | /* DUP (element, scalar) */ | |
7878 | handle_simd_dupes(s, rd, rn, imm5); | |
384b26fb AB |
7879 | } |
7880 | ||
4ce31af4 | 7881 | /* AdvSIMD scalar pairwise |
384b26fb AB |
7882 | * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0 |
7883 | * +-----+---+-----------+------+-----------+--------+-----+------+------+ | |
7884 | * | 0 1 | U | 1 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd | | |
7885 | * +-----+---+-----------+------+-----------+--------+-----+------+------+ | |
7886 | */ | |
7887 | static void disas_simd_scalar_pairwise(DisasContext *s, uint32_t insn) | |
7888 | { | |
3720a7ea PM |
7889 | int u = extract32(insn, 29, 1); |
7890 | int size = extract32(insn, 22, 2); | |
7891 | int opcode = extract32(insn, 12, 5); | |
7892 | int rn = extract32(insn, 5, 5); | |
7893 | int rd = extract32(insn, 0, 5); | |
7894 | TCGv_ptr fpst; | |
7895 | ||
7896 | /* For some ops (the FP ones), size[1] is part of the encoding. | |
7897 | * For ADDP strictly it is not but size[1] is always 1 for valid | |
7898 | * encodings. | |
7899 | */ | |
7900 | opcode |= (extract32(size, 1, 1) << 5); | |
7901 | ||
7902 | switch (opcode) { | |
7903 | case 0x3b: /* ADDP */ | |
7904 | if (u || size != 3) { | |
7905 | unallocated_encoding(s); | |
7906 | return; | |
7907 | } | |
8c6afa6a PM |
7908 | if (!fp_access_check(s)) { |
7909 | return; | |
7910 | } | |
7911 | ||
f764718d | 7912 | fpst = NULL; |
3720a7ea PM |
7913 | break; |
7914 | case 0xc: /* FMAXNMP */ | |
7915 | case 0xd: /* FADDP */ | |
7916 | case 0xf: /* FMAXP */ | |
7917 | case 0x2c: /* FMINNMP */ | |
7918 | case 0x2f: /* FMINP */ | |
5c36d895 | 7919 | /* FP op, size[0] is 32 or 64 bit*/ |
3720a7ea | 7920 | if (!u) { |
5763190f | 7921 | if (!dc_isar_feature(aa64_fp16, s)) { |
5c36d895 AB |
7922 | unallocated_encoding(s); |
7923 | return; | |
7924 | } else { | |
7925 | size = MO_16; | |
7926 | } | |
7927 | } else { | |
7928 | size = extract32(size, 0, 1) ? MO_64 : MO_32; | |
3720a7ea | 7929 | } |
5c36d895 | 7930 | |
8c6afa6a PM |
7931 | if (!fp_access_check(s)) { |
7932 | return; | |
7933 | } | |
7934 | ||
5c36d895 | 7935 | fpst = get_fpstatus_ptr(size == MO_16); |
3720a7ea PM |
7936 | break; |
7937 | default: | |
7938 | unallocated_encoding(s); | |
7939 | return; | |
7940 | } | |
7941 | ||
5c36d895 | 7942 | if (size == MO_64) { |
3720a7ea PM |
7943 | TCGv_i64 tcg_op1 = tcg_temp_new_i64(); |
7944 | TCGv_i64 tcg_op2 = tcg_temp_new_i64(); | |
7945 | TCGv_i64 tcg_res = tcg_temp_new_i64(); | |
7946 | ||
7947 | read_vec_element(s, tcg_op1, rn, 0, MO_64); | |
7948 | read_vec_element(s, tcg_op2, rn, 1, MO_64); | |
7949 | ||
7950 | switch (opcode) { | |
7951 | case 0x3b: /* ADDP */ | |
7952 | tcg_gen_add_i64(tcg_res, tcg_op1, tcg_op2); | |
7953 | break; | |
7954 | case 0xc: /* FMAXNMP */ | |
7955 | gen_helper_vfp_maxnumd(tcg_res, tcg_op1, tcg_op2, fpst); | |
7956 | break; | |
7957 | case 0xd: /* FADDP */ | |
7958 | gen_helper_vfp_addd(tcg_res, tcg_op1, tcg_op2, fpst); | |
7959 | break; | |
7960 | case 0xf: /* FMAXP */ | |
7961 | gen_helper_vfp_maxd(tcg_res, tcg_op1, tcg_op2, fpst); | |
7962 | break; | |
7963 | case 0x2c: /* FMINNMP */ | |
7964 | gen_helper_vfp_minnumd(tcg_res, tcg_op1, tcg_op2, fpst); | |
7965 | break; | |
7966 | case 0x2f: /* FMINP */ | |
7967 | gen_helper_vfp_mind(tcg_res, tcg_op1, tcg_op2, fpst); | |
7968 | break; | |
7969 | default: | |
7970 | g_assert_not_reached(); | |
7971 | } | |
7972 | ||
7973 | write_fp_dreg(s, rd, tcg_res); | |
7974 | ||
7975 | tcg_temp_free_i64(tcg_op1); | |
7976 | tcg_temp_free_i64(tcg_op2); | |
7977 | tcg_temp_free_i64(tcg_res); | |
7978 | } else { | |
7979 | TCGv_i32 tcg_op1 = tcg_temp_new_i32(); | |
7980 | TCGv_i32 tcg_op2 = tcg_temp_new_i32(); | |
7981 | TCGv_i32 tcg_res = tcg_temp_new_i32(); | |
7982 | ||
5c36d895 AB |
7983 | read_vec_element_i32(s, tcg_op1, rn, 0, size); |
7984 | read_vec_element_i32(s, tcg_op2, rn, 1, size); | |
3720a7ea | 7985 | |
5c36d895 AB |
7986 | if (size == MO_16) { |
7987 | switch (opcode) { | |
7988 | case 0xc: /* FMAXNMP */ | |
7989 | gen_helper_advsimd_maxnumh(tcg_res, tcg_op1, tcg_op2, fpst); | |
7990 | break; | |
7991 | case 0xd: /* FADDP */ | |
7992 | gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst); | |
7993 | break; | |
7994 | case 0xf: /* FMAXP */ | |
7995 | gen_helper_advsimd_maxh(tcg_res, tcg_op1, tcg_op2, fpst); | |
7996 | break; | |
7997 | case 0x2c: /* FMINNMP */ | |
7998 | gen_helper_advsimd_minnumh(tcg_res, tcg_op1, tcg_op2, fpst); | |
7999 | break; | |
8000 | case 0x2f: /* FMINP */ | |
8001 | gen_helper_advsimd_minh(tcg_res, tcg_op1, tcg_op2, fpst); | |
8002 | break; | |
8003 | default: | |
8004 | g_assert_not_reached(); | |
8005 | } | |
8006 | } else { | |
8007 | switch (opcode) { | |
8008 | case 0xc: /* FMAXNMP */ | |
8009 | gen_helper_vfp_maxnums(tcg_res, tcg_op1, tcg_op2, fpst); | |
8010 | break; | |
8011 | case 0xd: /* FADDP */ | |
8012 | gen_helper_vfp_adds(tcg_res, tcg_op1, tcg_op2, fpst); | |
8013 | break; | |
8014 | case 0xf: /* FMAXP */ | |
8015 | gen_helper_vfp_maxs(tcg_res, tcg_op1, tcg_op2, fpst); | |
8016 | break; | |
8017 | case 0x2c: /* FMINNMP */ | |
8018 | gen_helper_vfp_minnums(tcg_res, tcg_op1, tcg_op2, fpst); | |
8019 | break; | |
8020 | case 0x2f: /* FMINP */ | |
8021 | gen_helper_vfp_mins(tcg_res, tcg_op1, tcg_op2, fpst); | |
8022 | break; | |
8023 | default: | |
8024 | g_assert_not_reached(); | |
8025 | } | |
3720a7ea PM |
8026 | } |
8027 | ||
8028 | write_fp_sreg(s, rd, tcg_res); | |
8029 | ||
8030 | tcg_temp_free_i32(tcg_op1); | |
8031 | tcg_temp_free_i32(tcg_op2); | |
8032 | tcg_temp_free_i32(tcg_res); | |
8033 | } | |
8034 | ||
f764718d | 8035 | if (fpst) { |
3720a7ea PM |
8036 | tcg_temp_free_ptr(fpst); |
8037 | } | |
384b26fb AB |
8038 | } |
8039 | ||
4d1cef84 AB |
8040 | /* |
8041 | * Common SSHR[RA]/USHR[RA] - Shift right (optional rounding/accumulate) | |
8042 | * | |
8043 | * This code is handles the common shifting code and is used by both | |
8044 | * the vector and scalar code. | |
8045 | */ | |
8046 | static void handle_shri_with_rndacc(TCGv_i64 tcg_res, TCGv_i64 tcg_src, | |
8047 | TCGv_i64 tcg_rnd, bool accumulate, | |
8048 | bool is_u, int size, int shift) | |
8049 | { | |
8050 | bool extended_result = false; | |
f764718d | 8051 | bool round = tcg_rnd != NULL; |
4d1cef84 AB |
8052 | int ext_lshift = 0; |
8053 | TCGv_i64 tcg_src_hi; | |
8054 | ||
8055 | if (round && size == 3) { | |
8056 | extended_result = true; | |
8057 | ext_lshift = 64 - shift; | |
8058 | tcg_src_hi = tcg_temp_new_i64(); | |
8059 | } else if (shift == 64) { | |
8060 | if (!accumulate && is_u) { | |
8061 | /* result is zero */ | |
8062 | tcg_gen_movi_i64(tcg_res, 0); | |
8063 | return; | |
8064 | } | |
8065 | } | |
8066 | ||
8067 | /* Deal with the rounding step */ | |
8068 | if (round) { | |
8069 | if (extended_result) { | |
8070 | TCGv_i64 tcg_zero = tcg_const_i64(0); | |
8071 | if (!is_u) { | |
8072 | /* take care of sign extending tcg_res */ | |
8073 | tcg_gen_sari_i64(tcg_src_hi, tcg_src, 63); | |
8074 | tcg_gen_add2_i64(tcg_src, tcg_src_hi, | |
8075 | tcg_src, tcg_src_hi, | |
8076 | tcg_rnd, tcg_zero); | |
8077 | } else { | |
8078 | tcg_gen_add2_i64(tcg_src, tcg_src_hi, | |
8079 | tcg_src, tcg_zero, | |
8080 | tcg_rnd, tcg_zero); | |
8081 | } | |
8082 | tcg_temp_free_i64(tcg_zero); | |
8083 | } else { | |
8084 | tcg_gen_add_i64(tcg_src, tcg_src, tcg_rnd); | |
8085 | } | |
8086 | } | |
8087 | ||
8088 | /* Now do the shift right */ | |
8089 | if (round && extended_result) { | |
8090 | /* extended case, >64 bit precision required */ | |
8091 | if (ext_lshift == 0) { | |
8092 | /* special case, only high bits matter */ | |
8093 | tcg_gen_mov_i64(tcg_src, tcg_src_hi); | |
8094 | } else { | |
8095 | tcg_gen_shri_i64(tcg_src, tcg_src, shift); | |
8096 | tcg_gen_shli_i64(tcg_src_hi, tcg_src_hi, ext_lshift); | |
8097 | tcg_gen_or_i64(tcg_src, tcg_src, tcg_src_hi); | |
8098 | } | |
8099 | } else { | |
8100 | if (is_u) { | |
8101 | if (shift == 64) { | |
8102 | /* essentially shifting in 64 zeros */ | |
8103 | tcg_gen_movi_i64(tcg_src, 0); | |
8104 | } else { | |
8105 | tcg_gen_shri_i64(tcg_src, tcg_src, shift); | |
8106 | } | |
8107 | } else { | |
8108 | if (shift == 64) { | |
8109 | /* effectively extending the sign-bit */ | |
8110 | tcg_gen_sari_i64(tcg_src, tcg_src, 63); | |
8111 | } else { | |
8112 | tcg_gen_sari_i64(tcg_src, tcg_src, shift); | |
8113 | } | |
8114 | } | |
8115 | } | |
8116 | ||
8117 | if (accumulate) { | |
8118 | tcg_gen_add_i64(tcg_res, tcg_res, tcg_src); | |
8119 | } else { | |
8120 | tcg_gen_mov_i64(tcg_res, tcg_src); | |
8121 | } | |
8122 | ||
8123 | if (extended_result) { | |
8124 | tcg_temp_free_i64(tcg_src_hi); | |
8125 | } | |
8126 | } | |
8127 | ||
4d1cef84 AB |
8128 | /* SSHR[RA]/USHR[RA] - Scalar shift right (optional rounding/accumulate) */ |
8129 | static void handle_scalar_simd_shri(DisasContext *s, | |
8130 | bool is_u, int immh, int immb, | |
8131 | int opcode, int rn, int rd) | |
8132 | { | |
8133 | const int size = 3; | |
8134 | int immhb = immh << 3 | immb; | |
8135 | int shift = 2 * (8 << size) - immhb; | |
8136 | bool accumulate = false; | |
8137 | bool round = false; | |
37a706ad | 8138 | bool insert = false; |
4d1cef84 AB |
8139 | TCGv_i64 tcg_rn; |
8140 | TCGv_i64 tcg_rd; | |
8141 | TCGv_i64 tcg_round; | |
8142 | ||
8143 | if (!extract32(immh, 3, 1)) { | |
8144 | unallocated_encoding(s); | |
8145 | return; | |
8146 | } | |
8147 | ||
8c6afa6a PM |
8148 | if (!fp_access_check(s)) { |
8149 | return; | |
8150 | } | |
8151 | ||
4d1cef84 AB |
8152 | switch (opcode) { |
8153 | case 0x02: /* SSRA / USRA (accumulate) */ | |
8154 | accumulate = true; | |
8155 | break; | |
8156 | case 0x04: /* SRSHR / URSHR (rounding) */ | |
8157 | round = true; | |
8158 | break; | |
8159 | case 0x06: /* SRSRA / URSRA (accum + rounding) */ | |
8160 | accumulate = round = true; | |
8161 | break; | |
37a706ad PM |
8162 | case 0x08: /* SRI */ |
8163 | insert = true; | |
8164 | break; | |
4d1cef84 AB |
8165 | } |
8166 | ||
8167 | if (round) { | |
8168 | uint64_t round_const = 1ULL << (shift - 1); | |
8169 | tcg_round = tcg_const_i64(round_const); | |
8170 | } else { | |
f764718d | 8171 | tcg_round = NULL; |
4d1cef84 AB |
8172 | } |
8173 | ||
8174 | tcg_rn = read_fp_dreg(s, rn); | |
37a706ad | 8175 | tcg_rd = (accumulate || insert) ? read_fp_dreg(s, rd) : tcg_temp_new_i64(); |
4d1cef84 | 8176 | |
37a706ad | 8177 | if (insert) { |
cdb45a60 RH |
8178 | /* shift count same as element size is valid but does nothing; |
8179 | * special case to avoid potential shift by 64. | |
8180 | */ | |
8181 | int esize = 8 << size; | |
8182 | if (shift != esize) { | |
8183 | tcg_gen_shri_i64(tcg_rn, tcg_rn, shift); | |
8184 | tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_rn, 0, esize - shift); | |
8185 | } | |
37a706ad PM |
8186 | } else { |
8187 | handle_shri_with_rndacc(tcg_rd, tcg_rn, tcg_round, | |
8188 | accumulate, is_u, size, shift); | |
8189 | } | |
4d1cef84 AB |
8190 | |
8191 | write_fp_dreg(s, rd, tcg_rd); | |
8192 | ||
8193 | tcg_temp_free_i64(tcg_rn); | |
8194 | tcg_temp_free_i64(tcg_rd); | |
8195 | if (round) { | |
8196 | tcg_temp_free_i64(tcg_round); | |
8197 | } | |
8198 | } | |
8199 | ||
8200 | /* SHL/SLI - Scalar shift left */ | |
8201 | static void handle_scalar_simd_shli(DisasContext *s, bool insert, | |
8202 | int immh, int immb, int opcode, | |
8203 | int rn, int rd) | |
8204 | { | |
8205 | int size = 32 - clz32(immh) - 1; | |
8206 | int immhb = immh << 3 | immb; | |
8207 | int shift = immhb - (8 << size); | |
8208 | TCGv_i64 tcg_rn = new_tmp_a64(s); | |
8209 | TCGv_i64 tcg_rd = new_tmp_a64(s); | |
8210 | ||
8211 | if (!extract32(immh, 3, 1)) { | |
8212 | unallocated_encoding(s); | |
8213 | return; | |
8214 | } | |
8215 | ||
8c6afa6a PM |
8216 | if (!fp_access_check(s)) { |
8217 | return; | |
8218 | } | |
8219 | ||
4d1cef84 AB |
8220 | tcg_rn = read_fp_dreg(s, rn); |
8221 | tcg_rd = insert ? read_fp_dreg(s, rd) : tcg_temp_new_i64(); | |
8222 | ||
cdb45a60 RH |
8223 | if (insert) { |
8224 | tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_rn, shift, 64 - shift); | |
8225 | } else { | |
8226 | tcg_gen_shli_i64(tcg_rd, tcg_rn, shift); | |
8227 | } | |
4d1cef84 AB |
8228 | |
8229 | write_fp_dreg(s, rd, tcg_rd); | |
8230 | ||
8231 | tcg_temp_free_i64(tcg_rn); | |
8232 | tcg_temp_free_i64(tcg_rd); | |
8233 | } | |
8234 | ||
c1b876b2 AB |
8235 | /* SQSHRN/SQSHRUN - Saturating (signed/unsigned) shift right with |
8236 | * (signed/unsigned) narrowing */ | |
8237 | static void handle_vec_simd_sqshrn(DisasContext *s, bool is_scalar, bool is_q, | |
8238 | bool is_u_shift, bool is_u_narrow, | |
8239 | int immh, int immb, int opcode, | |
8240 | int rn, int rd) | |
8241 | { | |
8242 | int immhb = immh << 3 | immb; | |
8243 | int size = 32 - clz32(immh) - 1; | |
8244 | int esize = 8 << size; | |
8245 | int shift = (2 * esize) - immhb; | |
8246 | int elements = is_scalar ? 1 : (64 / esize); | |
8247 | bool round = extract32(opcode, 0, 1); | |
14776ab5 | 8248 | MemOp ldop = (size + 1) | (is_u_shift ? 0 : MO_SIGN); |
c1b876b2 AB |
8249 | TCGv_i64 tcg_rn, tcg_rd, tcg_round; |
8250 | TCGv_i32 tcg_rd_narrowed; | |
8251 | TCGv_i64 tcg_final; | |
8252 | ||
8253 | static NeonGenNarrowEnvFn * const signed_narrow_fns[4][2] = { | |
8254 | { gen_helper_neon_narrow_sat_s8, | |
8255 | gen_helper_neon_unarrow_sat8 }, | |
8256 | { gen_helper_neon_narrow_sat_s16, | |
8257 | gen_helper_neon_unarrow_sat16 }, | |
8258 | { gen_helper_neon_narrow_sat_s32, | |
8259 | gen_helper_neon_unarrow_sat32 }, | |
8260 | { NULL, NULL }, | |
8261 | }; | |
8262 | static NeonGenNarrowEnvFn * const unsigned_narrow_fns[4] = { | |
8263 | gen_helper_neon_narrow_sat_u8, | |
8264 | gen_helper_neon_narrow_sat_u16, | |
8265 | gen_helper_neon_narrow_sat_u32, | |
8266 | NULL | |
8267 | }; | |
8268 | NeonGenNarrowEnvFn *narrowfn; | |
8269 | ||
8270 | int i; | |
8271 | ||
8272 | assert(size < 4); | |
8273 | ||
8274 | if (extract32(immh, 3, 1)) { | |
8275 | unallocated_encoding(s); | |
8276 | return; | |
8277 | } | |
8278 | ||
8c6afa6a PM |
8279 | if (!fp_access_check(s)) { |
8280 | return; | |
8281 | } | |
8282 | ||
c1b876b2 AB |
8283 | if (is_u_shift) { |
8284 | narrowfn = unsigned_narrow_fns[size]; | |
8285 | } else { | |
8286 | narrowfn = signed_narrow_fns[size][is_u_narrow ? 1 : 0]; | |
8287 | } | |
8288 | ||
8289 | tcg_rn = tcg_temp_new_i64(); | |
8290 | tcg_rd = tcg_temp_new_i64(); | |
8291 | tcg_rd_narrowed = tcg_temp_new_i32(); | |
8292 | tcg_final = tcg_const_i64(0); | |
8293 | ||
8294 | if (round) { | |
8295 | uint64_t round_const = 1ULL << (shift - 1); | |
8296 | tcg_round = tcg_const_i64(round_const); | |
8297 | } else { | |
f764718d | 8298 | tcg_round = NULL; |
c1b876b2 AB |
8299 | } |
8300 | ||
8301 | for (i = 0; i < elements; i++) { | |
8302 | read_vec_element(s, tcg_rn, rn, i, ldop); | |
8303 | handle_shri_with_rndacc(tcg_rd, tcg_rn, tcg_round, | |
8304 | false, is_u_shift, size+1, shift); | |
8305 | narrowfn(tcg_rd_narrowed, cpu_env, tcg_rd); | |
8306 | tcg_gen_extu_i32_i64(tcg_rd, tcg_rd_narrowed); | |
8307 | tcg_gen_deposit_i64(tcg_final, tcg_final, tcg_rd, esize * i, esize); | |
8308 | } | |
8309 | ||
8310 | if (!is_q) { | |
c1b876b2 AB |
8311 | write_vec_element(s, tcg_final, rd, 0, MO_64); |
8312 | } else { | |
8313 | write_vec_element(s, tcg_final, rd, 1, MO_64); | |
8314 | } | |
8315 | ||
8316 | if (round) { | |
8317 | tcg_temp_free_i64(tcg_round); | |
8318 | } | |
8319 | tcg_temp_free_i64(tcg_rn); | |
8320 | tcg_temp_free_i64(tcg_rd); | |
8321 | tcg_temp_free_i32(tcg_rd_narrowed); | |
8322 | tcg_temp_free_i64(tcg_final); | |
4ff55bcb RH |
8323 | |
8324 | clear_vec_high(s, is_q, rd); | |
c1b876b2 AB |
8325 | } |
8326 | ||
a847f32c PM |
8327 | /* SQSHLU, UQSHL, SQSHL: saturating left shifts */ |
8328 | static void handle_simd_qshl(DisasContext *s, bool scalar, bool is_q, | |
8329 | bool src_unsigned, bool dst_unsigned, | |
8330 | int immh, int immb, int rn, int rd) | |
8331 | { | |
8332 | int immhb = immh << 3 | immb; | |
8333 | int size = 32 - clz32(immh) - 1; | |
8334 | int shift = immhb - (8 << size); | |
8335 | int pass; | |
8336 | ||
8337 | assert(immh != 0); | |
8338 | assert(!(scalar && is_q)); | |
8339 | ||
8340 | if (!scalar) { | |
8341 | if (!is_q && extract32(immh, 3, 1)) { | |
8342 | unallocated_encoding(s); | |
8343 | return; | |
8344 | } | |
8345 | ||
8346 | /* Since we use the variable-shift helpers we must | |
8347 | * replicate the shift count into each element of | |
8348 | * the tcg_shift value. | |
8349 | */ | |
8350 | switch (size) { | |
8351 | case 0: | |
8352 | shift |= shift << 8; | |
8353 | /* fall through */ | |
8354 | case 1: | |
8355 | shift |= shift << 16; | |
8356 | break; | |
8357 | case 2: | |
8358 | case 3: | |
8359 | break; | |
8360 | default: | |
8361 | g_assert_not_reached(); | |
8362 | } | |
8363 | } | |
8364 | ||
8c6afa6a PM |
8365 | if (!fp_access_check(s)) { |
8366 | return; | |
8367 | } | |
8368 | ||
a847f32c PM |
8369 | if (size == 3) { |
8370 | TCGv_i64 tcg_shift = tcg_const_i64(shift); | |
8371 | static NeonGenTwo64OpEnvFn * const fns[2][2] = { | |
8372 | { gen_helper_neon_qshl_s64, gen_helper_neon_qshlu_s64 }, | |
8373 | { NULL, gen_helper_neon_qshl_u64 }, | |
8374 | }; | |
8375 | NeonGenTwo64OpEnvFn *genfn = fns[src_unsigned][dst_unsigned]; | |
8376 | int maxpass = is_q ? 2 : 1; | |
8377 | ||
8378 | for (pass = 0; pass < maxpass; pass++) { | |
8379 | TCGv_i64 tcg_op = tcg_temp_new_i64(); | |
8380 | ||
8381 | read_vec_element(s, tcg_op, rn, pass, MO_64); | |
8382 | genfn(tcg_op, cpu_env, tcg_op, tcg_shift); | |
8383 | write_vec_element(s, tcg_op, rd, pass, MO_64); | |
8384 | ||
8385 | tcg_temp_free_i64(tcg_op); | |
8386 | } | |
8387 | tcg_temp_free_i64(tcg_shift); | |
4ff55bcb | 8388 | clear_vec_high(s, is_q, rd); |
a847f32c PM |
8389 | } else { |
8390 | TCGv_i32 tcg_shift = tcg_const_i32(shift); | |
8391 | static NeonGenTwoOpEnvFn * const fns[2][2][3] = { | |
8392 | { | |
8393 | { gen_helper_neon_qshl_s8, | |
8394 | gen_helper_neon_qshl_s16, | |
8395 | gen_helper_neon_qshl_s32 }, | |
8396 | { gen_helper_neon_qshlu_s8, | |
8397 | gen_helper_neon_qshlu_s16, | |
8398 | gen_helper_neon_qshlu_s32 } | |
8399 | }, { | |
8400 | { NULL, NULL, NULL }, | |
8401 | { gen_helper_neon_qshl_u8, | |
8402 | gen_helper_neon_qshl_u16, | |
8403 | gen_helper_neon_qshl_u32 } | |
8404 | } | |
8405 | }; | |
8406 | NeonGenTwoOpEnvFn *genfn = fns[src_unsigned][dst_unsigned][size]; | |
14776ab5 | 8407 | MemOp memop = scalar ? size : MO_32; |
a847f32c PM |
8408 | int maxpass = scalar ? 1 : is_q ? 4 : 2; |
8409 | ||
8410 | for (pass = 0; pass < maxpass; pass++) { | |
8411 | TCGv_i32 tcg_op = tcg_temp_new_i32(); | |
8412 | ||
8413 | read_vec_element_i32(s, tcg_op, rn, pass, memop); | |
8414 | genfn(tcg_op, cpu_env, tcg_op, tcg_shift); | |
8415 | if (scalar) { | |
8416 | switch (size) { | |
8417 | case 0: | |
8418 | tcg_gen_ext8u_i32(tcg_op, tcg_op); | |
8419 | break; | |
8420 | case 1: | |
8421 | tcg_gen_ext16u_i32(tcg_op, tcg_op); | |
8422 | break; | |
8423 | case 2: | |
8424 | break; | |
8425 | default: | |
8426 | g_assert_not_reached(); | |
8427 | } | |
8428 | write_fp_sreg(s, rd, tcg_op); | |
8429 | } else { | |
8430 | write_vec_element_i32(s, tcg_op, rd, pass, MO_32); | |
8431 | } | |
8432 | ||
8433 | tcg_temp_free_i32(tcg_op); | |
8434 | } | |
8435 | tcg_temp_free_i32(tcg_shift); | |
8436 | ||
4ff55bcb RH |
8437 | if (!scalar) { |
8438 | clear_vec_high(s, is_q, rd); | |
a847f32c PM |
8439 | } |
8440 | } | |
8441 | } | |
8442 | ||
10113b69 AB |
8443 | /* Common vector code for handling integer to FP conversion */ |
8444 | static void handle_simd_intfp_conv(DisasContext *s, int rd, int rn, | |
8445 | int elements, int is_signed, | |
8446 | int fracbits, int size) | |
8447 | { | |
93193190 AB |
8448 | TCGv_ptr tcg_fpst = get_fpstatus_ptr(size == MO_16); |
8449 | TCGv_i32 tcg_shift = NULL; | |
8450 | ||
14776ab5 | 8451 | MemOp mop = size | (is_signed ? MO_SIGN : 0); |
10113b69 AB |
8452 | int pass; |
8453 | ||
93193190 AB |
8454 | if (fracbits || size == MO_64) { |
8455 | tcg_shift = tcg_const_i32(fracbits); | |
8456 | } | |
8457 | ||
8458 | if (size == MO_64) { | |
8459 | TCGv_i64 tcg_int64 = tcg_temp_new_i64(); | |
8460 | TCGv_i64 tcg_double = tcg_temp_new_i64(); | |
8461 | ||
8462 | for (pass = 0; pass < elements; pass++) { | |
8463 | read_vec_element(s, tcg_int64, rn, pass, mop); | |
10113b69 | 8464 | |
10113b69 | 8465 | if (is_signed) { |
93193190 | 8466 | gen_helper_vfp_sqtod(tcg_double, tcg_int64, |
10113b69 AB |
8467 | tcg_shift, tcg_fpst); |
8468 | } else { | |
93193190 | 8469 | gen_helper_vfp_uqtod(tcg_double, tcg_int64, |
10113b69 AB |
8470 | tcg_shift, tcg_fpst); |
8471 | } | |
8472 | if (elements == 1) { | |
8473 | write_fp_dreg(s, rd, tcg_double); | |
8474 | } else { | |
8475 | write_vec_element(s, tcg_double, rd, pass, MO_64); | |
8476 | } | |
93193190 AB |
8477 | } |
8478 | ||
8479 | tcg_temp_free_i64(tcg_int64); | |
8480 | tcg_temp_free_i64(tcg_double); | |
8481 | ||
8482 | } else { | |
8483 | TCGv_i32 tcg_int32 = tcg_temp_new_i32(); | |
8484 | TCGv_i32 tcg_float = tcg_temp_new_i32(); | |
8485 | ||
8486 | for (pass = 0; pass < elements; pass++) { | |
8487 | read_vec_element_i32(s, tcg_int32, rn, pass, mop); | |
8488 | ||
8489 | switch (size) { | |
8490 | case MO_32: | |
8491 | if (fracbits) { | |
8492 | if (is_signed) { | |
8493 | gen_helper_vfp_sltos(tcg_float, tcg_int32, | |
8494 | tcg_shift, tcg_fpst); | |
8495 | } else { | |
8496 | gen_helper_vfp_ultos(tcg_float, tcg_int32, | |
8497 | tcg_shift, tcg_fpst); | |
8498 | } | |
8499 | } else { | |
8500 | if (is_signed) { | |
8501 | gen_helper_vfp_sitos(tcg_float, tcg_int32, tcg_fpst); | |
8502 | } else { | |
8503 | gen_helper_vfp_uitos(tcg_float, tcg_int32, tcg_fpst); | |
8504 | } | |
8505 | } | |
8506 | break; | |
8507 | case MO_16: | |
8508 | if (fracbits) { | |
8509 | if (is_signed) { | |
8510 | gen_helper_vfp_sltoh(tcg_float, tcg_int32, | |
8511 | tcg_shift, tcg_fpst); | |
8512 | } else { | |
8513 | gen_helper_vfp_ultoh(tcg_float, tcg_int32, | |
8514 | tcg_shift, tcg_fpst); | |
8515 | } | |
8516 | } else { | |
8517 | if (is_signed) { | |
8518 | gen_helper_vfp_sitoh(tcg_float, tcg_int32, tcg_fpst); | |
8519 | } else { | |
8520 | gen_helper_vfp_uitoh(tcg_float, tcg_int32, tcg_fpst); | |
8521 | } | |
8522 | } | |
8523 | break; | |
8524 | default: | |
8525 | g_assert_not_reached(); | |
10113b69 | 8526 | } |
93193190 | 8527 | |
10113b69 | 8528 | if (elements == 1) { |
93193190 | 8529 | write_fp_sreg(s, rd, tcg_float); |
10113b69 | 8530 | } else { |
93193190 | 8531 | write_vec_element_i32(s, tcg_float, rd, pass, size); |
10113b69 | 8532 | } |
10113b69 | 8533 | } |
93193190 AB |
8534 | |
8535 | tcg_temp_free_i32(tcg_int32); | |
8536 | tcg_temp_free_i32(tcg_float); | |
10113b69 AB |
8537 | } |
8538 | ||
10113b69 | 8539 | tcg_temp_free_ptr(tcg_fpst); |
93193190 AB |
8540 | if (tcg_shift) { |
8541 | tcg_temp_free_i32(tcg_shift); | |
8542 | } | |
4ff55bcb RH |
8543 | |
8544 | clear_vec_high(s, elements << size == 16, rd); | |
10113b69 AB |
8545 | } |
8546 | ||
8547 | /* UCVTF/SCVTF - Integer to FP conversion */ | |
8548 | static void handle_simd_shift_intfp_conv(DisasContext *s, bool is_scalar, | |
8549 | bool is_q, bool is_u, | |
8550 | int immh, int immb, int opcode, | |
8551 | int rn, int rd) | |
8552 | { | |
a6117fae | 8553 | int size, elements, fracbits; |
10113b69 | 8554 | int immhb = immh << 3 | immb; |
10113b69 | 8555 | |
a6117fae RH |
8556 | if (immh & 8) { |
8557 | size = MO_64; | |
8558 | if (!is_scalar && !is_q) { | |
8559 | unallocated_encoding(s); | |
8560 | return; | |
8561 | } | |
8562 | } else if (immh & 4) { | |
8563 | size = MO_32; | |
8564 | } else if (immh & 2) { | |
8565 | size = MO_16; | |
5763190f | 8566 | if (!dc_isar_feature(aa64_fp16, s)) { |
a6117fae RH |
8567 | unallocated_encoding(s); |
8568 | return; | |
8569 | } | |
8570 | } else { | |
8571 | /* immh == 0 would be a failure of the decode logic */ | |
8572 | g_assert(immh == 1); | |
10113b69 AB |
8573 | unallocated_encoding(s); |
8574 | return; | |
8575 | } | |
8576 | ||
8577 | if (is_scalar) { | |
8578 | elements = 1; | |
8579 | } else { | |
a6117fae | 8580 | elements = (8 << is_q) >> size; |
10113b69 | 8581 | } |
a6117fae | 8582 | fracbits = (16 << size) - immhb; |
8c6afa6a PM |
8583 | |
8584 | if (!fp_access_check(s)) { | |
8585 | return; | |
8586 | } | |
8587 | ||
10113b69 AB |
8588 | handle_simd_intfp_conv(s, rd, rn, elements, !is_u, fracbits, size); |
8589 | } | |
8590 | ||
2ed3ea11 PM |
8591 | /* FCVTZS, FVCVTZU - FP to fixedpoint conversion */ |
8592 | static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar, | |
8593 | bool is_q, bool is_u, | |
8594 | int immh, int immb, int rn, int rd) | |
8595 | { | |
2ed3ea11 | 8596 | int immhb = immh << 3 | immb; |
d0ba8e74 | 8597 | int pass, size, fracbits; |
2ed3ea11 PM |
8598 | TCGv_ptr tcg_fpstatus; |
8599 | TCGv_i32 tcg_rmode, tcg_shift; | |
8600 | ||
d0ba8e74 RH |
8601 | if (immh & 0x8) { |
8602 | size = MO_64; | |
8603 | if (!is_scalar && !is_q) { | |
8604 | unallocated_encoding(s); | |
8605 | return; | |
8606 | } | |
8607 | } else if (immh & 0x4) { | |
8608 | size = MO_32; | |
8609 | } else if (immh & 0x2) { | |
8610 | size = MO_16; | |
5763190f | 8611 | if (!dc_isar_feature(aa64_fp16, s)) { |
d0ba8e74 RH |
8612 | unallocated_encoding(s); |
8613 | return; | |
8614 | } | |
8615 | } else { | |
8616 | /* Should have split out AdvSIMD modified immediate earlier. */ | |
8617 | assert(immh == 1); | |
2ed3ea11 PM |
8618 | unallocated_encoding(s); |
8619 | return; | |
8620 | } | |
8621 | ||
8c6afa6a PM |
8622 | if (!fp_access_check(s)) { |
8623 | return; | |
8624 | } | |
8625 | ||
2ed3ea11 PM |
8626 | assert(!(is_scalar && is_q)); |
8627 | ||
8628 | tcg_rmode = tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO)); | |
d0ba8e74 | 8629 | tcg_fpstatus = get_fpstatus_ptr(size == MO_16); |
9b049916 | 8630 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); |
d0ba8e74 | 8631 | fracbits = (16 << size) - immhb; |
2ed3ea11 PM |
8632 | tcg_shift = tcg_const_i32(fracbits); |
8633 | ||
d0ba8e74 | 8634 | if (size == MO_64) { |
4063452e | 8635 | int maxpass = is_scalar ? 1 : 2; |
2ed3ea11 PM |
8636 | |
8637 | for (pass = 0; pass < maxpass; pass++) { | |
8638 | TCGv_i64 tcg_op = tcg_temp_new_i64(); | |
8639 | ||
8640 | read_vec_element(s, tcg_op, rn, pass, MO_64); | |
8641 | if (is_u) { | |
8642 | gen_helper_vfp_touqd(tcg_op, tcg_op, tcg_shift, tcg_fpstatus); | |
8643 | } else { | |
8644 | gen_helper_vfp_tosqd(tcg_op, tcg_op, tcg_shift, tcg_fpstatus); | |
8645 | } | |
8646 | write_vec_element(s, tcg_op, rd, pass, MO_64); | |
8647 | tcg_temp_free_i64(tcg_op); | |
8648 | } | |
4ff55bcb | 8649 | clear_vec_high(s, is_q, rd); |
2ed3ea11 | 8650 | } else { |
d0ba8e74 RH |
8651 | void (*fn)(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_ptr); |
8652 | int maxpass = is_scalar ? 1 : ((8 << is_q) >> size); | |
2ed3ea11 | 8653 | |
d0ba8e74 RH |
8654 | switch (size) { |
8655 | case MO_16: | |
2ed3ea11 | 8656 | if (is_u) { |
88808a02 | 8657 | fn = gen_helper_vfp_touhh; |
2ed3ea11 | 8658 | } else { |
88808a02 | 8659 | fn = gen_helper_vfp_toshh; |
2ed3ea11 | 8660 | } |
d0ba8e74 RH |
8661 | break; |
8662 | case MO_32: | |
2ed3ea11 | 8663 | if (is_u) { |
d0ba8e74 | 8664 | fn = gen_helper_vfp_touls; |
2ed3ea11 | 8665 | } else { |
d0ba8e74 | 8666 | fn = gen_helper_vfp_tosls; |
2ed3ea11 | 8667 | } |
d0ba8e74 RH |
8668 | break; |
8669 | default: | |
8670 | g_assert_not_reached(); | |
8671 | } | |
8672 | ||
8673 | for (pass = 0; pass < maxpass; pass++) { | |
8674 | TCGv_i32 tcg_op = tcg_temp_new_i32(); | |
8675 | ||
8676 | read_vec_element_i32(s, tcg_op, rn, pass, size); | |
8677 | fn(tcg_op, tcg_op, tcg_shift, tcg_fpstatus); | |
2ed3ea11 PM |
8678 | if (is_scalar) { |
8679 | write_fp_sreg(s, rd, tcg_op); | |
8680 | } else { | |
d0ba8e74 | 8681 | write_vec_element_i32(s, tcg_op, rd, pass, size); |
2ed3ea11 PM |
8682 | } |
8683 | tcg_temp_free_i32(tcg_op); | |
8684 | } | |
4ff55bcb RH |
8685 | if (!is_scalar) { |
8686 | clear_vec_high(s, is_q, rd); | |
2ed3ea11 PM |
8687 | } |
8688 | } | |
8689 | ||
8690 | tcg_temp_free_ptr(tcg_fpstatus); | |
8691 | tcg_temp_free_i32(tcg_shift); | |
9b049916 | 8692 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); |
2ed3ea11 PM |
8693 | tcg_temp_free_i32(tcg_rmode); |
8694 | } | |
8695 | ||
4ce31af4 | 8696 | /* AdvSIMD scalar shift by immediate |
384b26fb AB |
8697 | * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0 |
8698 | * +-----+---+-------------+------+------+--------+---+------+------+ | |
8699 | * | 0 1 | U | 1 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd | | |
8700 | * +-----+---+-------------+------+------+--------+---+------+------+ | |
4d1cef84 AB |
8701 | * |
8702 | * This is the scalar version so it works on a fixed sized registers | |
384b26fb AB |
8703 | */ |
8704 | static void disas_simd_scalar_shift_imm(DisasContext *s, uint32_t insn) | |
8705 | { | |
4d1cef84 AB |
8706 | int rd = extract32(insn, 0, 5); |
8707 | int rn = extract32(insn, 5, 5); | |
8708 | int opcode = extract32(insn, 11, 5); | |
8709 | int immb = extract32(insn, 16, 3); | |
8710 | int immh = extract32(insn, 19, 4); | |
8711 | bool is_u = extract32(insn, 29, 1); | |
8712 | ||
c1b876b2 AB |
8713 | if (immh == 0) { |
8714 | unallocated_encoding(s); | |
8715 | return; | |
8716 | } | |
8717 | ||
4d1cef84 | 8718 | switch (opcode) { |
37a706ad PM |
8719 | case 0x08: /* SRI */ |
8720 | if (!is_u) { | |
8721 | unallocated_encoding(s); | |
8722 | return; | |
8723 | } | |
8724 | /* fall through */ | |
4d1cef84 AB |
8725 | case 0x00: /* SSHR / USHR */ |
8726 | case 0x02: /* SSRA / USRA */ | |
8727 | case 0x04: /* SRSHR / URSHR */ | |
8728 | case 0x06: /* SRSRA / URSRA */ | |
8729 | handle_scalar_simd_shri(s, is_u, immh, immb, opcode, rn, rd); | |
8730 | break; | |
8731 | case 0x0a: /* SHL / SLI */ | |
8732 | handle_scalar_simd_shli(s, is_u, immh, immb, opcode, rn, rd); | |
8733 | break; | |
10113b69 AB |
8734 | case 0x1c: /* SCVTF, UCVTF */ |
8735 | handle_simd_shift_intfp_conv(s, true, false, is_u, immh, immb, | |
8736 | opcode, rn, rd); | |
8737 | break; | |
c1b876b2 AB |
8738 | case 0x10: /* SQSHRUN, SQSHRUN2 */ |
8739 | case 0x11: /* SQRSHRUN, SQRSHRUN2 */ | |
8740 | if (!is_u) { | |
8741 | unallocated_encoding(s); | |
8742 | return; | |
8743 | } | |
8744 | handle_vec_simd_sqshrn(s, true, false, false, true, | |
8745 | immh, immb, opcode, rn, rd); | |
8746 | break; | |
8747 | case 0x12: /* SQSHRN, SQSHRN2, UQSHRN */ | |
8748 | case 0x13: /* SQRSHRN, SQRSHRN2, UQRSHRN, UQRSHRN2 */ | |
8749 | handle_vec_simd_sqshrn(s, true, false, is_u, is_u, | |
8750 | immh, immb, opcode, rn, rd); | |
8751 | break; | |
a566da1b | 8752 | case 0xc: /* SQSHLU */ |
a847f32c PM |
8753 | if (!is_u) { |
8754 | unallocated_encoding(s); | |
8755 | return; | |
8756 | } | |
8757 | handle_simd_qshl(s, true, false, false, true, immh, immb, rn, rd); | |
8758 | break; | |
a566da1b | 8759 | case 0xe: /* SQSHL, UQSHL */ |
a847f32c PM |
8760 | handle_simd_qshl(s, true, false, is_u, is_u, immh, immb, rn, rd); |
8761 | break; | |
a566da1b | 8762 | case 0x1f: /* FCVTZS, FCVTZU */ |
2ed3ea11 | 8763 | handle_simd_shift_fpint_conv(s, true, false, is_u, immh, immb, rn, rd); |
4d1cef84 | 8764 | break; |
a566da1b PM |
8765 | default: |
8766 | unallocated_encoding(s); | |
8767 | break; | |
4d1cef84 | 8768 | } |
384b26fb AB |
8769 | } |
8770 | ||
4ce31af4 | 8771 | /* AdvSIMD scalar three different |
384b26fb AB |
8772 | * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0 |
8773 | * +-----+---+-----------+------+---+------+--------+-----+------+------+ | |
8774 | * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd | | |
8775 | * +-----+---+-----------+------+---+------+--------+-----+------+------+ | |
8776 | */ | |
8777 | static void disas_simd_scalar_three_reg_diff(DisasContext *s, uint32_t insn) | |
8778 | { | |
b033cd3d PM |
8779 | bool is_u = extract32(insn, 29, 1); |
8780 | int size = extract32(insn, 22, 2); | |
8781 | int opcode = extract32(insn, 12, 4); | |
8782 | int rm = extract32(insn, 16, 5); | |
8783 | int rn = extract32(insn, 5, 5); | |
8784 | int rd = extract32(insn, 0, 5); | |
8785 | ||
8786 | if (is_u) { | |
8787 | unallocated_encoding(s); | |
8788 | return; | |
8789 | } | |
8790 | ||
8791 | switch (opcode) { | |
8792 | case 0x9: /* SQDMLAL, SQDMLAL2 */ | |
8793 | case 0xb: /* SQDMLSL, SQDMLSL2 */ | |
8794 | case 0xd: /* SQDMULL, SQDMULL2 */ | |
8795 | if (size == 0 || size == 3) { | |
8796 | unallocated_encoding(s); | |
8797 | return; | |
8798 | } | |
8799 | break; | |
8800 | default: | |
8801 | unallocated_encoding(s); | |
8802 | return; | |
8803 | } | |
8804 | ||
8c6afa6a PM |
8805 | if (!fp_access_check(s)) { |
8806 | return; | |
8807 | } | |
8808 | ||
b033cd3d PM |
8809 | if (size == 2) { |
8810 | TCGv_i64 tcg_op1 = tcg_temp_new_i64(); | |
8811 | TCGv_i64 tcg_op2 = tcg_temp_new_i64(); | |
8812 | TCGv_i64 tcg_res = tcg_temp_new_i64(); | |
8813 | ||
8814 | read_vec_element(s, tcg_op1, rn, 0, MO_32 | MO_SIGN); | |
8815 | read_vec_element(s, tcg_op2, rm, 0, MO_32 | MO_SIGN); | |
8816 | ||
8817 | tcg_gen_mul_i64(tcg_res, tcg_op1, tcg_op2); | |
8818 | gen_helper_neon_addl_saturate_s64(tcg_res, cpu_env, tcg_res, tcg_res); | |
8819 | ||
8820 | switch (opcode) { | |
8821 | case 0xd: /* SQDMULL, SQDMULL2 */ | |
8822 | break; | |
8823 | case 0xb: /* SQDMLSL, SQDMLSL2 */ | |
8824 | tcg_gen_neg_i64(tcg_res, tcg_res); | |
8825 | /* fall through */ | |
8826 | case 0x9: /* SQDMLAL, SQDMLAL2 */ | |
8827 | read_vec_element(s, tcg_op1, rd, 0, MO_64); | |
8828 | gen_helper_neon_addl_saturate_s64(tcg_res, cpu_env, | |
8829 | tcg_res, tcg_op1); | |
8830 | break; | |
8831 | default: | |
8832 | g_assert_not_reached(); | |
8833 | } | |
8834 | ||
8835 | write_fp_dreg(s, rd, tcg_res); | |
8836 | ||
8837 | tcg_temp_free_i64(tcg_op1); | |
8838 | tcg_temp_free_i64(tcg_op2); | |
8839 | tcg_temp_free_i64(tcg_res); | |
8840 | } else { | |
3d99d931 RH |
8841 | TCGv_i32 tcg_op1 = read_fp_hreg(s, rn); |
8842 | TCGv_i32 tcg_op2 = read_fp_hreg(s, rm); | |
b033cd3d PM |
8843 | TCGv_i64 tcg_res = tcg_temp_new_i64(); |
8844 | ||
b033cd3d PM |
8845 | gen_helper_neon_mull_s16(tcg_res, tcg_op1, tcg_op2); |
8846 | gen_helper_neon_addl_saturate_s32(tcg_res, cpu_env, tcg_res, tcg_res); | |
8847 | ||
8848 | switch (opcode) { | |
8849 | case 0xd: /* SQDMULL, SQDMULL2 */ | |
8850 | break; | |
8851 | case 0xb: /* SQDMLSL, SQDMLSL2 */ | |
8852 | gen_helper_neon_negl_u32(tcg_res, tcg_res); | |
8853 | /* fall through */ | |
8854 | case 0x9: /* SQDMLAL, SQDMLAL2 */ | |
8855 | { | |
8856 | TCGv_i64 tcg_op3 = tcg_temp_new_i64(); | |
8857 | read_vec_element(s, tcg_op3, rd, 0, MO_32); | |
8858 | gen_helper_neon_addl_saturate_s32(tcg_res, cpu_env, | |
8859 | tcg_res, tcg_op3); | |
8860 | tcg_temp_free_i64(tcg_op3); | |
8861 | break; | |
8862 | } | |
8863 | default: | |
8864 | g_assert_not_reached(); | |
8865 | } | |
8866 | ||
8867 | tcg_gen_ext32u_i64(tcg_res, tcg_res); | |
8868 | write_fp_dreg(s, rd, tcg_res); | |
8869 | ||
8870 | tcg_temp_free_i32(tcg_op1); | |
8871 | tcg_temp_free_i32(tcg_op2); | |
8872 | tcg_temp_free_i64(tcg_res); | |
8873 | } | |
384b26fb AB |
8874 | } |
8875 | ||
b305dba6 PM |
8876 | static void handle_3same_64(DisasContext *s, int opcode, bool u, |
8877 | TCGv_i64 tcg_rd, TCGv_i64 tcg_rn, TCGv_i64 tcg_rm) | |
8878 | { | |
8879 | /* Handle 64x64->64 opcodes which are shared between the scalar | |
8880 | * and vector 3-same groups. We cover every opcode where size == 3 | |
8881 | * is valid in either the three-reg-same (integer, not pairwise) | |
3840d219 | 8882 | * or scalar-three-reg-same groups. |
b305dba6 PM |
8883 | */ |
8884 | TCGCond cond; | |
8885 | ||
8886 | switch (opcode) { | |
6d9571f7 PM |
8887 | case 0x1: /* SQADD */ |
8888 | if (u) { | |
8889 | gen_helper_neon_qadd_u64(tcg_rd, cpu_env, tcg_rn, tcg_rm); | |
8890 | } else { | |
8891 | gen_helper_neon_qadd_s64(tcg_rd, cpu_env, tcg_rn, tcg_rm); | |
8892 | } | |
8893 | break; | |
8894 | case 0x5: /* SQSUB */ | |
8895 | if (u) { | |
8896 | gen_helper_neon_qsub_u64(tcg_rd, cpu_env, tcg_rn, tcg_rm); | |
8897 | } else { | |
8898 | gen_helper_neon_qsub_s64(tcg_rd, cpu_env, tcg_rn, tcg_rm); | |
8899 | } | |
8900 | break; | |
b305dba6 PM |
8901 | case 0x6: /* CMGT, CMHI */ |
8902 | /* 64 bit integer comparison, result = test ? (2^64 - 1) : 0. | |
8903 | * We implement this using setcond (test) and then negating. | |
8904 | */ | |
8905 | cond = u ? TCG_COND_GTU : TCG_COND_GT; | |
8906 | do_cmop: | |
8907 | tcg_gen_setcond_i64(cond, tcg_rd, tcg_rn, tcg_rm); | |
8908 | tcg_gen_neg_i64(tcg_rd, tcg_rd); | |
8909 | break; | |
8910 | case 0x7: /* CMGE, CMHS */ | |
8911 | cond = u ? TCG_COND_GEU : TCG_COND_GE; | |
8912 | goto do_cmop; | |
8913 | case 0x11: /* CMTST, CMEQ */ | |
8914 | if (u) { | |
8915 | cond = TCG_COND_EQ; | |
8916 | goto do_cmop; | |
8917 | } | |
79d61de6 | 8918 | gen_cmtst_i64(tcg_rd, tcg_rn, tcg_rm); |
b305dba6 | 8919 | break; |
6d9571f7 | 8920 | case 0x8: /* SSHL, USHL */ |
b305dba6 | 8921 | if (u) { |
87b74e8b | 8922 | gen_ushl_i64(tcg_rd, tcg_rn, tcg_rm); |
b305dba6 | 8923 | } else { |
87b74e8b | 8924 | gen_sshl_i64(tcg_rd, tcg_rn, tcg_rm); |
b305dba6 PM |
8925 | } |
8926 | break; | |
b305dba6 | 8927 | case 0x9: /* SQSHL, UQSHL */ |
6d9571f7 PM |
8928 | if (u) { |
8929 | gen_helper_neon_qshl_u64(tcg_rd, cpu_env, tcg_rn, tcg_rm); | |
8930 | } else { | |
8931 | gen_helper_neon_qshl_s64(tcg_rd, cpu_env, tcg_rn, tcg_rm); | |
8932 | } | |
8933 | break; | |
b305dba6 | 8934 | case 0xa: /* SRSHL, URSHL */ |
6d9571f7 PM |
8935 | if (u) { |
8936 | gen_helper_neon_rshl_u64(tcg_rd, tcg_rn, tcg_rm); | |
8937 | } else { | |
8938 | gen_helper_neon_rshl_s64(tcg_rd, tcg_rn, tcg_rm); | |
8939 | } | |
8940 | break; | |
b305dba6 | 8941 | case 0xb: /* SQRSHL, UQRSHL */ |
6d9571f7 PM |
8942 | if (u) { |
8943 | gen_helper_neon_qrshl_u64(tcg_rd, cpu_env, tcg_rn, tcg_rm); | |
8944 | } else { | |
8945 | gen_helper_neon_qrshl_s64(tcg_rd, cpu_env, tcg_rn, tcg_rm); | |
8946 | } | |
8947 | break; | |
8948 | case 0x10: /* ADD, SUB */ | |
8949 | if (u) { | |
8950 | tcg_gen_sub_i64(tcg_rd, tcg_rn, tcg_rm); | |
8951 | } else { | |
8952 | tcg_gen_add_i64(tcg_rd, tcg_rn, tcg_rm); | |
8953 | } | |
8954 | break; | |
b305dba6 PM |
8955 | default: |
8956 | g_assert_not_reached(); | |
8957 | } | |
8958 | } | |
8959 | ||
845ea09a PM |
8960 | /* Handle the 3-same-operands float operations; shared by the scalar |
8961 | * and vector encodings. The caller must filter out any encodings | |
8962 | * not allocated for the encoding it is dealing with. | |
8963 | */ | |
8964 | static void handle_3same_float(DisasContext *s, int size, int elements, | |
8965 | int fpopcode, int rd, int rn, int rm) | |
8966 | { | |
8967 | int pass; | |
d81ce0ef | 8968 | TCGv_ptr fpst = get_fpstatus_ptr(false); |
845ea09a PM |
8969 | |
8970 | for (pass = 0; pass < elements; pass++) { | |
8971 | if (size) { | |
8972 | /* Double */ | |
8973 | TCGv_i64 tcg_op1 = tcg_temp_new_i64(); | |
8974 | TCGv_i64 tcg_op2 = tcg_temp_new_i64(); | |
8975 | TCGv_i64 tcg_res = tcg_temp_new_i64(); | |
8976 | ||
8977 | read_vec_element(s, tcg_op1, rn, pass, MO_64); | |
8978 | read_vec_element(s, tcg_op2, rm, pass, MO_64); | |
8979 | ||
8980 | switch (fpopcode) { | |
057d5f62 PM |
8981 | case 0x39: /* FMLS */ |
8982 | /* As usual for ARM, separate negation for fused multiply-add */ | |
8983 | gen_helper_vfp_negd(tcg_op1, tcg_op1); | |
8984 | /* fall through */ | |
8985 | case 0x19: /* FMLA */ | |
8986 | read_vec_element(s, tcg_res, rd, pass, MO_64); | |
8987 | gen_helper_vfp_muladdd(tcg_res, tcg_op1, tcg_op2, | |
8988 | tcg_res, fpst); | |
8989 | break; | |
845ea09a PM |
8990 | case 0x18: /* FMAXNM */ |
8991 | gen_helper_vfp_maxnumd(tcg_res, tcg_op1, tcg_op2, fpst); | |
8992 | break; | |
8993 | case 0x1a: /* FADD */ | |
8994 | gen_helper_vfp_addd(tcg_res, tcg_op1, tcg_op2, fpst); | |
8995 | break; | |
057d5f62 PM |
8996 | case 0x1b: /* FMULX */ |
8997 | gen_helper_vfp_mulxd(tcg_res, tcg_op1, tcg_op2, fpst); | |
8998 | break; | |
8908f4d1 AB |
8999 | case 0x1c: /* FCMEQ */ |
9000 | gen_helper_neon_ceq_f64(tcg_res, tcg_op1, tcg_op2, fpst); | |
9001 | break; | |
845ea09a PM |
9002 | case 0x1e: /* FMAX */ |
9003 | gen_helper_vfp_maxd(tcg_res, tcg_op1, tcg_op2, fpst); | |
9004 | break; | |
057d5f62 PM |
9005 | case 0x1f: /* FRECPS */ |
9006 | gen_helper_recpsf_f64(tcg_res, tcg_op1, tcg_op2, fpst); | |
9007 | break; | |
845ea09a PM |
9008 | case 0x38: /* FMINNM */ |
9009 | gen_helper_vfp_minnumd(tcg_res, tcg_op1, tcg_op2, fpst); | |
9010 | break; | |
9011 | case 0x3a: /* FSUB */ | |
9012 | gen_helper_vfp_subd(tcg_res, tcg_op1, tcg_op2, fpst); | |
9013 | break; | |
9014 | case 0x3e: /* FMIN */ | |
9015 | gen_helper_vfp_mind(tcg_res, tcg_op1, tcg_op2, fpst); | |
9016 | break; | |
057d5f62 PM |
9017 | case 0x3f: /* FRSQRTS */ |
9018 | gen_helper_rsqrtsf_f64(tcg_res, tcg_op1, tcg_op2, fpst); | |
9019 | break; | |
845ea09a PM |
9020 | case 0x5b: /* FMUL */ |
9021 | gen_helper_vfp_muld(tcg_res, tcg_op1, tcg_op2, fpst); | |
9022 | break; | |
8908f4d1 AB |
9023 | case 0x5c: /* FCMGE */ |
9024 | gen_helper_neon_cge_f64(tcg_res, tcg_op1, tcg_op2, fpst); | |
9025 | break; | |
057d5f62 PM |
9026 | case 0x5d: /* FACGE */ |
9027 | gen_helper_neon_acge_f64(tcg_res, tcg_op1, tcg_op2, fpst); | |
9028 | break; | |
845ea09a PM |
9029 | case 0x5f: /* FDIV */ |
9030 | gen_helper_vfp_divd(tcg_res, tcg_op1, tcg_op2, fpst); | |
9031 | break; | |
9032 | case 0x7a: /* FABD */ | |
9033 | gen_helper_vfp_subd(tcg_res, tcg_op1, tcg_op2, fpst); | |
9034 | gen_helper_vfp_absd(tcg_res, tcg_res); | |
9035 | break; | |
8908f4d1 AB |
9036 | case 0x7c: /* FCMGT */ |
9037 | gen_helper_neon_cgt_f64(tcg_res, tcg_op1, tcg_op2, fpst); | |
9038 | break; | |
057d5f62 PM |
9039 | case 0x7d: /* FACGT */ |
9040 | gen_helper_neon_acgt_f64(tcg_res, tcg_op1, tcg_op2, fpst); | |
9041 | break; | |
845ea09a PM |
9042 | default: |
9043 | g_assert_not_reached(); | |
9044 | } | |
9045 | ||
9046 | write_vec_element(s, tcg_res, rd, pass, MO_64); | |
9047 | ||
9048 | tcg_temp_free_i64(tcg_res); | |
9049 | tcg_temp_free_i64(tcg_op1); | |
9050 | tcg_temp_free_i64(tcg_op2); | |
9051 | } else { | |
9052 | /* Single */ | |
9053 | TCGv_i32 tcg_op1 = tcg_temp_new_i32(); | |
9054 | TCGv_i32 tcg_op2 = tcg_temp_new_i32(); | |
9055 | TCGv_i32 tcg_res = tcg_temp_new_i32(); | |
9056 | ||
9057 | read_vec_element_i32(s, tcg_op1, rn, pass, MO_32); | |
9058 | read_vec_element_i32(s, tcg_op2, rm, pass, MO_32); | |
9059 | ||
9060 | switch (fpopcode) { | |
057d5f62 PM |
9061 | case 0x39: /* FMLS */ |
9062 | /* As usual for ARM, separate negation for fused multiply-add */ | |
9063 | gen_helper_vfp_negs(tcg_op1, tcg_op1); | |
9064 | /* fall through */ | |
9065 | case 0x19: /* FMLA */ | |
9066 | read_vec_element_i32(s, tcg_res, rd, pass, MO_32); | |
9067 | gen_helper_vfp_muladds(tcg_res, tcg_op1, tcg_op2, | |
9068 | tcg_res, fpst); | |
9069 | break; | |
845ea09a PM |
9070 | case 0x1a: /* FADD */ |
9071 | gen_helper_vfp_adds(tcg_res, tcg_op1, tcg_op2, fpst); | |
9072 | break; | |
057d5f62 PM |
9073 | case 0x1b: /* FMULX */ |
9074 | gen_helper_vfp_mulxs(tcg_res, tcg_op1, tcg_op2, fpst); | |
9075 | break; | |
8908f4d1 AB |
9076 | case 0x1c: /* FCMEQ */ |
9077 | gen_helper_neon_ceq_f32(tcg_res, tcg_op1, tcg_op2, fpst); | |
9078 | break; | |
845ea09a PM |
9079 | case 0x1e: /* FMAX */ |
9080 | gen_helper_vfp_maxs(tcg_res, tcg_op1, tcg_op2, fpst); | |
9081 | break; | |
057d5f62 PM |
9082 | case 0x1f: /* FRECPS */ |
9083 | gen_helper_recpsf_f32(tcg_res, tcg_op1, tcg_op2, fpst); | |
9084 | break; | |
845ea09a PM |
9085 | case 0x18: /* FMAXNM */ |
9086 | gen_helper_vfp_maxnums(tcg_res, tcg_op1, tcg_op2, fpst); | |
9087 | break; | |
9088 | case 0x38: /* FMINNM */ | |
9089 | gen_helper_vfp_minnums(tcg_res, tcg_op1, tcg_op2, fpst); | |
9090 | break; | |
9091 | case 0x3a: /* FSUB */ | |
9092 | gen_helper_vfp_subs(tcg_res, tcg_op1, tcg_op2, fpst); | |
9093 | break; | |
9094 | case 0x3e: /* FMIN */ | |
9095 | gen_helper_vfp_mins(tcg_res, tcg_op1, tcg_op2, fpst); | |
9096 | break; | |
057d5f62 PM |
9097 | case 0x3f: /* FRSQRTS */ |
9098 | gen_helper_rsqrtsf_f32(tcg_res, tcg_op1, tcg_op2, fpst); | |
9099 | break; | |
845ea09a PM |
9100 | case 0x5b: /* FMUL */ |
9101 | gen_helper_vfp_muls(tcg_res, tcg_op1, tcg_op2, fpst); | |
9102 | break; | |
8908f4d1 AB |
9103 | case 0x5c: /* FCMGE */ |
9104 | gen_helper_neon_cge_f32(tcg_res, tcg_op1, tcg_op2, fpst); | |
9105 | break; | |
057d5f62 PM |
9106 | case 0x5d: /* FACGE */ |
9107 | gen_helper_neon_acge_f32(tcg_res, tcg_op1, tcg_op2, fpst); | |
9108 | break; | |
845ea09a PM |
9109 | case 0x5f: /* FDIV */ |
9110 | gen_helper_vfp_divs(tcg_res, tcg_op1, tcg_op2, fpst); | |
9111 | break; | |
9112 | case 0x7a: /* FABD */ | |
9113 | gen_helper_vfp_subs(tcg_res, tcg_op1, tcg_op2, fpst); | |
9114 | gen_helper_vfp_abss(tcg_res, tcg_res); | |
9115 | break; | |
8908f4d1 AB |
9116 | case 0x7c: /* FCMGT */ |
9117 | gen_helper_neon_cgt_f32(tcg_res, tcg_op1, tcg_op2, fpst); | |
9118 | break; | |
057d5f62 PM |
9119 | case 0x7d: /* FACGT */ |
9120 | gen_helper_neon_acgt_f32(tcg_res, tcg_op1, tcg_op2, fpst); | |
9121 | break; | |
845ea09a PM |
9122 | default: |
9123 | g_assert_not_reached(); | |
9124 | } | |
9125 | ||
9126 | if (elements == 1) { | |
9127 | /* scalar single so clear high part */ | |
9128 | TCGv_i64 tcg_tmp = tcg_temp_new_i64(); | |
9129 | ||
9130 | tcg_gen_extu_i32_i64(tcg_tmp, tcg_res); | |
9131 | write_vec_element(s, tcg_tmp, rd, pass, MO_64); | |
9132 | tcg_temp_free_i64(tcg_tmp); | |
9133 | } else { | |
9134 | write_vec_element_i32(s, tcg_res, rd, pass, MO_32); | |
9135 | } | |
9136 | ||
9137 | tcg_temp_free_i32(tcg_res); | |
9138 | tcg_temp_free_i32(tcg_op1); | |
9139 | tcg_temp_free_i32(tcg_op2); | |
9140 | } | |
9141 | } | |
9142 | ||
9143 | tcg_temp_free_ptr(fpst); | |
9144 | ||
4ff55bcb | 9145 | clear_vec_high(s, elements * (size ? 8 : 4) > 8, rd); |
845ea09a PM |
9146 | } |
9147 | ||
4ce31af4 | 9148 | /* AdvSIMD scalar three same |
384b26fb AB |
9149 | * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0 |
9150 | * +-----+---+-----------+------+---+------+--------+---+------+------+ | |
9151 | * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd | | |
9152 | * +-----+---+-----------+------+---+------+--------+---+------+------+ | |
9153 | */ | |
9154 | static void disas_simd_scalar_three_reg_same(DisasContext *s, uint32_t insn) | |
9155 | { | |
b305dba6 PM |
9156 | int rd = extract32(insn, 0, 5); |
9157 | int rn = extract32(insn, 5, 5); | |
9158 | int opcode = extract32(insn, 11, 5); | |
9159 | int rm = extract32(insn, 16, 5); | |
9160 | int size = extract32(insn, 22, 2); | |
9161 | bool u = extract32(insn, 29, 1); | |
b305dba6 PM |
9162 | TCGv_i64 tcg_rd; |
9163 | ||
9164 | if (opcode >= 0x18) { | |
9165 | /* Floating point: U, size[1] and opcode indicate operation */ | |
9166 | int fpopcode = opcode | (extract32(size, 1, 1) << 5) | (u << 6); | |
9167 | switch (fpopcode) { | |
9168 | case 0x1b: /* FMULX */ | |
b305dba6 PM |
9169 | case 0x1f: /* FRECPS */ |
9170 | case 0x3f: /* FRSQRTS */ | |
b305dba6 | 9171 | case 0x5d: /* FACGE */ |
b305dba6 | 9172 | case 0x7d: /* FACGT */ |
8908f4d1 AB |
9173 | case 0x1c: /* FCMEQ */ |
9174 | case 0x5c: /* FCMGE */ | |
9175 | case 0x7c: /* FCMGT */ | |
845ea09a PM |
9176 | case 0x7a: /* FABD */ |
9177 | break; | |
b305dba6 PM |
9178 | default: |
9179 | unallocated_encoding(s); | |
9180 | return; | |
9181 | } | |
845ea09a | 9182 | |
8c6afa6a PM |
9183 | if (!fp_access_check(s)) { |
9184 | return; | |
9185 | } | |
9186 | ||
845ea09a PM |
9187 | handle_3same_float(s, extract32(size, 0, 1), 1, fpopcode, rd, rn, rm); |
9188 | return; | |
b305dba6 PM |
9189 | } |
9190 | ||
9191 | switch (opcode) { | |
9192 | case 0x1: /* SQADD, UQADD */ | |
9193 | case 0x5: /* SQSUB, UQSUB */ | |
c0b2b5fa PM |
9194 | case 0x9: /* SQSHL, UQSHL */ |
9195 | case 0xb: /* SQRSHL, UQRSHL */ | |
9196 | break; | |
6d9571f7 PM |
9197 | case 0x8: /* SSHL, USHL */ |
9198 | case 0xa: /* SRSHL, URSHL */ | |
b305dba6 PM |
9199 | case 0x6: /* CMGT, CMHI */ |
9200 | case 0x7: /* CMGE, CMHS */ | |
9201 | case 0x11: /* CMTST, CMEQ */ | |
9202 | case 0x10: /* ADD, SUB (vector) */ | |
9203 | if (size != 3) { | |
9204 | unallocated_encoding(s); | |
9205 | return; | |
9206 | } | |
9207 | break; | |
b305dba6 PM |
9208 | case 0x16: /* SQDMULH, SQRDMULH (vector) */ |
9209 | if (size != 1 && size != 2) { | |
9210 | unallocated_encoding(s); | |
9211 | return; | |
9212 | } | |
c0b2b5fa | 9213 | break; |
b305dba6 PM |
9214 | default: |
9215 | unallocated_encoding(s); | |
9216 | return; | |
9217 | } | |
9218 | ||
8c6afa6a PM |
9219 | if (!fp_access_check(s)) { |
9220 | return; | |
9221 | } | |
9222 | ||
b305dba6 PM |
9223 | tcg_rd = tcg_temp_new_i64(); |
9224 | ||
c0b2b5fa PM |
9225 | if (size == 3) { |
9226 | TCGv_i64 tcg_rn = read_fp_dreg(s, rn); | |
9227 | TCGv_i64 tcg_rm = read_fp_dreg(s, rm); | |
9228 | ||
9229 | handle_3same_64(s, opcode, u, tcg_rd, tcg_rn, tcg_rm); | |
9230 | tcg_temp_free_i64(tcg_rn); | |
9231 | tcg_temp_free_i64(tcg_rm); | |
9232 | } else { | |
9233 | /* Do a single operation on the lowest element in the vector. | |
9234 | * We use the standard Neon helpers and rely on 0 OP 0 == 0 with | |
9235 | * no side effects for all these operations. | |
9236 | * OPTME: special-purpose helpers would avoid doing some | |
9237 | * unnecessary work in the helper for the 8 and 16 bit cases. | |
9238 | */ | |
9239 | NeonGenTwoOpEnvFn *genenvfn; | |
9240 | TCGv_i32 tcg_rn = tcg_temp_new_i32(); | |
9241 | TCGv_i32 tcg_rm = tcg_temp_new_i32(); | |
9242 | TCGv_i32 tcg_rd32 = tcg_temp_new_i32(); | |
9243 | ||
9244 | read_vec_element_i32(s, tcg_rn, rn, 0, size); | |
9245 | read_vec_element_i32(s, tcg_rm, rm, 0, size); | |
9246 | ||
9247 | switch (opcode) { | |
9248 | case 0x1: /* SQADD, UQADD */ | |
9249 | { | |
9250 | static NeonGenTwoOpEnvFn * const fns[3][2] = { | |
9251 | { gen_helper_neon_qadd_s8, gen_helper_neon_qadd_u8 }, | |
9252 | { gen_helper_neon_qadd_s16, gen_helper_neon_qadd_u16 }, | |
9253 | { gen_helper_neon_qadd_s32, gen_helper_neon_qadd_u32 }, | |
9254 | }; | |
9255 | genenvfn = fns[size][u]; | |
9256 | break; | |
9257 | } | |
9258 | case 0x5: /* SQSUB, UQSUB */ | |
9259 | { | |
9260 | static NeonGenTwoOpEnvFn * const fns[3][2] = { | |
9261 | { gen_helper_neon_qsub_s8, gen_helper_neon_qsub_u8 }, | |
9262 | { gen_helper_neon_qsub_s16, gen_helper_neon_qsub_u16 }, | |
9263 | { gen_helper_neon_qsub_s32, gen_helper_neon_qsub_u32 }, | |
9264 | }; | |
9265 | genenvfn = fns[size][u]; | |
9266 | break; | |
9267 | } | |
9268 | case 0x9: /* SQSHL, UQSHL */ | |
9269 | { | |
9270 | static NeonGenTwoOpEnvFn * const fns[3][2] = { | |
9271 | { gen_helper_neon_qshl_s8, gen_helper_neon_qshl_u8 }, | |
9272 | { gen_helper_neon_qshl_s16, gen_helper_neon_qshl_u16 }, | |
9273 | { gen_helper_neon_qshl_s32, gen_helper_neon_qshl_u32 }, | |
9274 | }; | |
9275 | genenvfn = fns[size][u]; | |
9276 | break; | |
9277 | } | |
9278 | case 0xb: /* SQRSHL, UQRSHL */ | |
9279 | { | |
9280 | static NeonGenTwoOpEnvFn * const fns[3][2] = { | |
9281 | { gen_helper_neon_qrshl_s8, gen_helper_neon_qrshl_u8 }, | |
9282 | { gen_helper_neon_qrshl_s16, gen_helper_neon_qrshl_u16 }, | |
9283 | { gen_helper_neon_qrshl_s32, gen_helper_neon_qrshl_u32 }, | |
9284 | }; | |
9285 | genenvfn = fns[size][u]; | |
9286 | break; | |
9287 | } | |
9288 | case 0x16: /* SQDMULH, SQRDMULH */ | |
9289 | { | |
9290 | static NeonGenTwoOpEnvFn * const fns[2][2] = { | |
9291 | { gen_helper_neon_qdmulh_s16, gen_helper_neon_qrdmulh_s16 }, | |
9292 | { gen_helper_neon_qdmulh_s32, gen_helper_neon_qrdmulh_s32 }, | |
9293 | }; | |
9294 | assert(size == 1 || size == 2); | |
9295 | genenvfn = fns[size - 1][u]; | |
9296 | break; | |
9297 | } | |
9298 | default: | |
9299 | g_assert_not_reached(); | |
9300 | } | |
9301 | ||
9302 | genenvfn(tcg_rd32, cpu_env, tcg_rn, tcg_rm); | |
9303 | tcg_gen_extu_i32_i64(tcg_rd, tcg_rd32); | |
9304 | tcg_temp_free_i32(tcg_rd32); | |
9305 | tcg_temp_free_i32(tcg_rn); | |
9306 | tcg_temp_free_i32(tcg_rm); | |
9307 | } | |
b305dba6 PM |
9308 | |
9309 | write_fp_dreg(s, rd, tcg_rd); | |
9310 | ||
b305dba6 | 9311 | tcg_temp_free_i64(tcg_rd); |
384b26fb AB |
9312 | } |
9313 | ||
7c93b774 AB |
9314 | /* AdvSIMD scalar three same FP16 |
9315 | * 31 30 29 28 24 23 22 21 20 16 15 14 13 11 10 9 5 4 0 | |
9316 | * +-----+---+-----------+---+-----+------+-----+--------+---+----+----+ | |
9317 | * | 0 1 | U | 1 1 1 1 0 | a | 1 0 | Rm | 0 0 | opcode | 1 | Rn | Rd | | |
9318 | * +-----+---+-----------+---+-----+------+-----+--------+---+----+----+ | |
9319 | * v: 0101 1110 0100 0000 0000 0100 0000 0000 => 5e400400 | |
9320 | * m: 1101 1111 0110 0000 1100 0100 0000 0000 => df60c400 | |
9321 | */ | |
9322 | static void disas_simd_scalar_three_reg_same_fp16(DisasContext *s, | |
9323 | uint32_t insn) | |
9324 | { | |
9325 | int rd = extract32(insn, 0, 5); | |
9326 | int rn = extract32(insn, 5, 5); | |
9327 | int opcode = extract32(insn, 11, 3); | |
9328 | int rm = extract32(insn, 16, 5); | |
9329 | bool u = extract32(insn, 29, 1); | |
9330 | bool a = extract32(insn, 23, 1); | |
9331 | int fpopcode = opcode | (a << 3) | (u << 4); | |
9332 | TCGv_ptr fpst; | |
9333 | TCGv_i32 tcg_op1; | |
9334 | TCGv_i32 tcg_op2; | |
9335 | TCGv_i32 tcg_res; | |
9336 | ||
9337 | switch (fpopcode) { | |
9338 | case 0x03: /* FMULX */ | |
9339 | case 0x04: /* FCMEQ (reg) */ | |
9340 | case 0x07: /* FRECPS */ | |
9341 | case 0x0f: /* FRSQRTS */ | |
9342 | case 0x14: /* FCMGE (reg) */ | |
9343 | case 0x15: /* FACGE */ | |
9344 | case 0x1a: /* FABD */ | |
9345 | case 0x1c: /* FCMGT (reg) */ | |
9346 | case 0x1d: /* FACGT */ | |
9347 | break; | |
9348 | default: | |
9349 | unallocated_encoding(s); | |
9350 | return; | |
9351 | } | |
9352 | ||
5763190f | 9353 | if (!dc_isar_feature(aa64_fp16, s)) { |
7c93b774 AB |
9354 | unallocated_encoding(s); |
9355 | } | |
9356 | ||
9357 | if (!fp_access_check(s)) { | |
9358 | return; | |
9359 | } | |
9360 | ||
9361 | fpst = get_fpstatus_ptr(true); | |
9362 | ||
3d99d931 RH |
9363 | tcg_op1 = read_fp_hreg(s, rn); |
9364 | tcg_op2 = read_fp_hreg(s, rm); | |
7c93b774 AB |
9365 | tcg_res = tcg_temp_new_i32(); |
9366 | ||
7c93b774 AB |
9367 | switch (fpopcode) { |
9368 | case 0x03: /* FMULX */ | |
9369 | gen_helper_advsimd_mulxh(tcg_res, tcg_op1, tcg_op2, fpst); | |
9370 | break; | |
9371 | case 0x04: /* FCMEQ (reg) */ | |
9372 | gen_helper_advsimd_ceq_f16(tcg_res, tcg_op1, tcg_op2, fpst); | |
9373 | break; | |
9374 | case 0x07: /* FRECPS */ | |
9375 | gen_helper_recpsf_f16(tcg_res, tcg_op1, tcg_op2, fpst); | |
9376 | break; | |
9377 | case 0x0f: /* FRSQRTS */ | |
9378 | gen_helper_rsqrtsf_f16(tcg_res, tcg_op1, tcg_op2, fpst); | |
9379 | break; | |
9380 | case 0x14: /* FCMGE (reg) */ | |
9381 | gen_helper_advsimd_cge_f16(tcg_res, tcg_op1, tcg_op2, fpst); | |
9382 | break; | |
9383 | case 0x15: /* FACGE */ | |
9384 | gen_helper_advsimd_acge_f16(tcg_res, tcg_op1, tcg_op2, fpst); | |
9385 | break; | |
9386 | case 0x1a: /* FABD */ | |
9387 | gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst); | |
9388 | tcg_gen_andi_i32(tcg_res, tcg_res, 0x7fff); | |
9389 | break; | |
9390 | case 0x1c: /* FCMGT (reg) */ | |
9391 | gen_helper_advsimd_cgt_f16(tcg_res, tcg_op1, tcg_op2, fpst); | |
9392 | break; | |
9393 | case 0x1d: /* FACGT */ | |
9394 | gen_helper_advsimd_acgt_f16(tcg_res, tcg_op1, tcg_op2, fpst); | |
9395 | break; | |
9396 | default: | |
9397 | g_assert_not_reached(); | |
9398 | } | |
9399 | ||
9400 | write_fp_sreg(s, rd, tcg_res); | |
9401 | ||
9402 | ||
9403 | tcg_temp_free_i32(tcg_res); | |
9404 | tcg_temp_free_i32(tcg_op1); | |
9405 | tcg_temp_free_i32(tcg_op2); | |
9406 | tcg_temp_free_ptr(fpst); | |
9407 | } | |
9408 | ||
d9061ec3 RH |
9409 | /* AdvSIMD scalar three same extra |
9410 | * 31 30 29 28 24 23 22 21 20 16 15 14 11 10 9 5 4 0 | |
9411 | * +-----+---+-----------+------+---+------+---+--------+---+----+----+ | |
9412 | * | 0 1 | U | 1 1 1 1 0 | size | 0 | Rm | 1 | opcode | 1 | Rn | Rd | | |
9413 | * +-----+---+-----------+------+---+------+---+--------+---+----+----+ | |
9414 | */ | |
9415 | static void disas_simd_scalar_three_reg_same_extra(DisasContext *s, | |
9416 | uint32_t insn) | |
9417 | { | |
9418 | int rd = extract32(insn, 0, 5); | |
9419 | int rn = extract32(insn, 5, 5); | |
9420 | int opcode = extract32(insn, 11, 4); | |
9421 | int rm = extract32(insn, 16, 5); | |
9422 | int size = extract32(insn, 22, 2); | |
9423 | bool u = extract32(insn, 29, 1); | |
9424 | TCGv_i32 ele1, ele2, ele3; | |
9425 | TCGv_i64 res; | |
962fcbf2 | 9426 | bool feature; |
d9061ec3 RH |
9427 | |
9428 | switch (u * 16 + opcode) { | |
9429 | case 0x10: /* SQRDMLAH (vector) */ | |
9430 | case 0x11: /* SQRDMLSH (vector) */ | |
9431 | if (size != 1 && size != 2) { | |
9432 | unallocated_encoding(s); | |
9433 | return; | |
9434 | } | |
962fcbf2 | 9435 | feature = dc_isar_feature(aa64_rdm, s); |
d9061ec3 RH |
9436 | break; |
9437 | default: | |
9438 | unallocated_encoding(s); | |
9439 | return; | |
9440 | } | |
962fcbf2 | 9441 | if (!feature) { |
d9061ec3 RH |
9442 | unallocated_encoding(s); |
9443 | return; | |
9444 | } | |
9445 | if (!fp_access_check(s)) { | |
9446 | return; | |
9447 | } | |
9448 | ||
9449 | /* Do a single operation on the lowest element in the vector. | |
9450 | * We use the standard Neon helpers and rely on 0 OP 0 == 0 | |
9451 | * with no side effects for all these operations. | |
9452 | * OPTME: special-purpose helpers would avoid doing some | |
9453 | * unnecessary work in the helper for the 16 bit cases. | |
9454 | */ | |
9455 | ele1 = tcg_temp_new_i32(); | |
9456 | ele2 = tcg_temp_new_i32(); | |
9457 | ele3 = tcg_temp_new_i32(); | |
9458 | ||
9459 | read_vec_element_i32(s, ele1, rn, 0, size); | |
9460 | read_vec_element_i32(s, ele2, rm, 0, size); | |
9461 | read_vec_element_i32(s, ele3, rd, 0, size); | |
9462 | ||
9463 | switch (opcode) { | |
9464 | case 0x0: /* SQRDMLAH */ | |
9465 | if (size == 1) { | |
9466 | gen_helper_neon_qrdmlah_s16(ele3, cpu_env, ele1, ele2, ele3); | |
9467 | } else { | |
9468 | gen_helper_neon_qrdmlah_s32(ele3, cpu_env, ele1, ele2, ele3); | |
9469 | } | |
9470 | break; | |
9471 | case 0x1: /* SQRDMLSH */ | |
9472 | if (size == 1) { | |
9473 | gen_helper_neon_qrdmlsh_s16(ele3, cpu_env, ele1, ele2, ele3); | |
9474 | } else { | |
9475 | gen_helper_neon_qrdmlsh_s32(ele3, cpu_env, ele1, ele2, ele3); | |
9476 | } | |
9477 | break; | |
9478 | default: | |
9479 | g_assert_not_reached(); | |
9480 | } | |
9481 | tcg_temp_free_i32(ele1); | |
9482 | tcg_temp_free_i32(ele2); | |
9483 | ||
9484 | res = tcg_temp_new_i64(); | |
9485 | tcg_gen_extu_i32_i64(res, ele3); | |
9486 | tcg_temp_free_i32(ele3); | |
9487 | ||
9488 | write_fp_dreg(s, rd, res); | |
9489 | tcg_temp_free_i64(res); | |
9490 | } | |
9491 | ||
effa8e06 | 9492 | static void handle_2misc_64(DisasContext *s, int opcode, bool u, |
04c7c6c2 PM |
9493 | TCGv_i64 tcg_rd, TCGv_i64 tcg_rn, |
9494 | TCGv_i32 tcg_rmode, TCGv_ptr tcg_fpstatus) | |
effa8e06 PM |
9495 | { |
9496 | /* Handle 64->64 opcodes which are shared between the scalar and | |
9497 | * vector 2-reg-misc groups. We cover every integer opcode where size == 3 | |
f93d0138 | 9498 | * is valid in either group and also the double-precision fp ops. |
04c7c6c2 PM |
9499 | * The caller only need provide tcg_rmode and tcg_fpstatus if the op |
9500 | * requires them. | |
effa8e06 PM |
9501 | */ |
9502 | TCGCond cond; | |
9503 | ||
9504 | switch (opcode) { | |
b05c3068 AB |
9505 | case 0x4: /* CLS, CLZ */ |
9506 | if (u) { | |
7539a012 | 9507 | tcg_gen_clzi_i64(tcg_rd, tcg_rn, 64); |
b05c3068 | 9508 | } else { |
bc21dbcc | 9509 | tcg_gen_clrsb_i64(tcg_rd, tcg_rn); |
b05c3068 AB |
9510 | } |
9511 | break; | |
86cbc418 PM |
9512 | case 0x5: /* NOT */ |
9513 | /* This opcode is shared with CNT and RBIT but we have earlier | |
9514 | * enforced that size == 3 if and only if this is the NOT insn. | |
9515 | */ | |
9516 | tcg_gen_not_i64(tcg_rd, tcg_rn); | |
9517 | break; | |
0a79bc87 AB |
9518 | case 0x7: /* SQABS, SQNEG */ |
9519 | if (u) { | |
9520 | gen_helper_neon_qneg_s64(tcg_rd, cpu_env, tcg_rn); | |
9521 | } else { | |
9522 | gen_helper_neon_qabs_s64(tcg_rd, cpu_env, tcg_rn); | |
9523 | } | |
9524 | break; | |
effa8e06 PM |
9525 | case 0xa: /* CMLT */ |
9526 | /* 64 bit integer comparison against zero, result is | |
9527 | * test ? (2^64 - 1) : 0. We implement via setcond(!test) and | |
9528 | * subtracting 1. | |
9529 | */ | |
9530 | cond = TCG_COND_LT; | |
9531 | do_cmop: | |
9532 | tcg_gen_setcondi_i64(cond, tcg_rd, tcg_rn, 0); | |
9533 | tcg_gen_neg_i64(tcg_rd, tcg_rd); | |
9534 | break; | |
9535 | case 0x8: /* CMGT, CMGE */ | |
9536 | cond = u ? TCG_COND_GE : TCG_COND_GT; | |
9537 | goto do_cmop; | |
9538 | case 0x9: /* CMEQ, CMLE */ | |
9539 | cond = u ? TCG_COND_LE : TCG_COND_EQ; | |
9540 | goto do_cmop; | |
9541 | case 0xb: /* ABS, NEG */ | |
9542 | if (u) { | |
9543 | tcg_gen_neg_i64(tcg_rd, tcg_rn); | |
9544 | } else { | |
4e027a71 | 9545 | tcg_gen_abs_i64(tcg_rd, tcg_rn); |
effa8e06 PM |
9546 | } |
9547 | break; | |
f93d0138 PM |
9548 | case 0x2f: /* FABS */ |
9549 | gen_helper_vfp_absd(tcg_rd, tcg_rn); | |
9550 | break; | |
9551 | case 0x6f: /* FNEG */ | |
9552 | gen_helper_vfp_negd(tcg_rd, tcg_rn); | |
9553 | break; | |
f612537e AB |
9554 | case 0x7f: /* FSQRT */ |
9555 | gen_helper_vfp_sqrtd(tcg_rd, tcg_rn, cpu_env); | |
9556 | break; | |
04c7c6c2 PM |
9557 | case 0x1a: /* FCVTNS */ |
9558 | case 0x1b: /* FCVTMS */ | |
9559 | case 0x1c: /* FCVTAS */ | |
9560 | case 0x3a: /* FCVTPS */ | |
9561 | case 0x3b: /* FCVTZS */ | |
9562 | { | |
9563 | TCGv_i32 tcg_shift = tcg_const_i32(0); | |
9564 | gen_helper_vfp_tosqd(tcg_rd, tcg_rn, tcg_shift, tcg_fpstatus); | |
9565 | tcg_temp_free_i32(tcg_shift); | |
9566 | break; | |
9567 | } | |
9568 | case 0x5a: /* FCVTNU */ | |
9569 | case 0x5b: /* FCVTMU */ | |
9570 | case 0x5c: /* FCVTAU */ | |
9571 | case 0x7a: /* FCVTPU */ | |
9572 | case 0x7b: /* FCVTZU */ | |
9573 | { | |
9574 | TCGv_i32 tcg_shift = tcg_const_i32(0); | |
9575 | gen_helper_vfp_touqd(tcg_rd, tcg_rn, tcg_shift, tcg_fpstatus); | |
9576 | tcg_temp_free_i32(tcg_shift); | |
9577 | break; | |
9578 | } | |
03df01ed PM |
9579 | case 0x18: /* FRINTN */ |
9580 | case 0x19: /* FRINTM */ | |
9581 | case 0x38: /* FRINTP */ | |
9582 | case 0x39: /* FRINTZ */ | |
9583 | case 0x58: /* FRINTA */ | |
9584 | case 0x79: /* FRINTI */ | |
9585 | gen_helper_rintd(tcg_rd, tcg_rn, tcg_fpstatus); | |
9586 | break; | |
9587 | case 0x59: /* FRINTX */ | |
9588 | gen_helper_rintd_exact(tcg_rd, tcg_rn, tcg_fpstatus); | |
9589 | break; | |
6bea2563 RH |
9590 | case 0x1e: /* FRINT32Z */ |
9591 | case 0x5e: /* FRINT32X */ | |
9592 | gen_helper_frint32_d(tcg_rd, tcg_rn, tcg_fpstatus); | |
9593 | break; | |
9594 | case 0x1f: /* FRINT64Z */ | |
9595 | case 0x5f: /* FRINT64X */ | |
9596 | gen_helper_frint64_d(tcg_rd, tcg_rn, tcg_fpstatus); | |
9597 | break; | |
effa8e06 PM |
9598 | default: |
9599 | g_assert_not_reached(); | |
9600 | } | |
9601 | } | |
9602 | ||
8908f4d1 AB |
9603 | static void handle_2misc_fcmp_zero(DisasContext *s, int opcode, |
9604 | bool is_scalar, bool is_u, bool is_q, | |
9605 | int size, int rn, int rd) | |
9606 | { | |
7d4dd1a7 | 9607 | bool is_double = (size == MO_64); |
8c6afa6a PM |
9608 | TCGv_ptr fpst; |
9609 | ||
9610 | if (!fp_access_check(s)) { | |
9611 | return; | |
9612 | } | |
9613 | ||
7d4dd1a7 | 9614 | fpst = get_fpstatus_ptr(size == MO_16); |
8908f4d1 AB |
9615 | |
9616 | if (is_double) { | |
9617 | TCGv_i64 tcg_op = tcg_temp_new_i64(); | |
9618 | TCGv_i64 tcg_zero = tcg_const_i64(0); | |
9619 | TCGv_i64 tcg_res = tcg_temp_new_i64(); | |
5de3fd04 | 9620 | NeonGenTwoDoubleOpFn *genfn; |
8908f4d1 AB |
9621 | bool swap = false; |
9622 | int pass; | |
9623 | ||
9624 | switch (opcode) { | |
9625 | case 0x2e: /* FCMLT (zero) */ | |
9626 | swap = true; | |
9627 | /* fallthrough */ | |
9628 | case 0x2c: /* FCMGT (zero) */ | |
9629 | genfn = gen_helper_neon_cgt_f64; | |
9630 | break; | |
9631 | case 0x2d: /* FCMEQ (zero) */ | |
9632 | genfn = gen_helper_neon_ceq_f64; | |
9633 | break; | |
9634 | case 0x6d: /* FCMLE (zero) */ | |
9635 | swap = true; | |
9636 | /* fall through */ | |
9637 | case 0x6c: /* FCMGE (zero) */ | |
9638 | genfn = gen_helper_neon_cge_f64; | |
9639 | break; | |
9640 | default: | |
9641 | g_assert_not_reached(); | |
9642 | } | |
9643 | ||
9644 | for (pass = 0; pass < (is_scalar ? 1 : 2); pass++) { | |
9645 | read_vec_element(s, tcg_op, rn, pass, MO_64); | |
9646 | if (swap) { | |
9647 | genfn(tcg_res, tcg_zero, tcg_op, fpst); | |
9648 | } else { | |
9649 | genfn(tcg_res, tcg_op, tcg_zero, fpst); | |
9650 | } | |
9651 | write_vec_element(s, tcg_res, rd, pass, MO_64); | |
9652 | } | |
8908f4d1 AB |
9653 | tcg_temp_free_i64(tcg_res); |
9654 | tcg_temp_free_i64(tcg_zero); | |
9655 | tcg_temp_free_i64(tcg_op); | |
4ff55bcb RH |
9656 | |
9657 | clear_vec_high(s, !is_scalar, rd); | |
8908f4d1 AB |
9658 | } else { |
9659 | TCGv_i32 tcg_op = tcg_temp_new_i32(); | |
9660 | TCGv_i32 tcg_zero = tcg_const_i32(0); | |
9661 | TCGv_i32 tcg_res = tcg_temp_new_i32(); | |
5de3fd04 | 9662 | NeonGenTwoSingleOpFn *genfn; |
8908f4d1 AB |
9663 | bool swap = false; |
9664 | int pass, maxpasses; | |
9665 | ||
7d4dd1a7 AB |
9666 | if (size == MO_16) { |
9667 | switch (opcode) { | |
9668 | case 0x2e: /* FCMLT (zero) */ | |
9669 | swap = true; | |
9670 | /* fall through */ | |
9671 | case 0x2c: /* FCMGT (zero) */ | |
9672 | genfn = gen_helper_advsimd_cgt_f16; | |
9673 | break; | |
9674 | case 0x2d: /* FCMEQ (zero) */ | |
9675 | genfn = gen_helper_advsimd_ceq_f16; | |
9676 | break; | |
9677 | case 0x6d: /* FCMLE (zero) */ | |
9678 | swap = true; | |
9679 | /* fall through */ | |
9680 | case 0x6c: /* FCMGE (zero) */ | |
9681 | genfn = gen_helper_advsimd_cge_f16; | |
9682 | break; | |
9683 | default: | |
9684 | g_assert_not_reached(); | |
9685 | } | |
9686 | } else { | |
9687 | switch (opcode) { | |
9688 | case 0x2e: /* FCMLT (zero) */ | |
9689 | swap = true; | |
9690 | /* fall through */ | |
9691 | case 0x2c: /* FCMGT (zero) */ | |
9692 | genfn = gen_helper_neon_cgt_f32; | |
9693 | break; | |
9694 | case 0x2d: /* FCMEQ (zero) */ | |
9695 | genfn = gen_helper_neon_ceq_f32; | |
9696 | break; | |
9697 | case 0x6d: /* FCMLE (zero) */ | |
9698 | swap = true; | |
9699 | /* fall through */ | |
9700 | case 0x6c: /* FCMGE (zero) */ | |
9701 | genfn = gen_helper_neon_cge_f32; | |
9702 | break; | |
9703 | default: | |
9704 | g_assert_not_reached(); | |
9705 | } | |
8908f4d1 AB |
9706 | } |
9707 | ||
9708 | if (is_scalar) { | |
9709 | maxpasses = 1; | |
9710 | } else { | |
7d4dd1a7 AB |
9711 | int vector_size = 8 << is_q; |
9712 | maxpasses = vector_size >> size; | |
8908f4d1 AB |
9713 | } |
9714 | ||
9715 | for (pass = 0; pass < maxpasses; pass++) { | |
7d4dd1a7 | 9716 | read_vec_element_i32(s, tcg_op, rn, pass, size); |
8908f4d1 AB |
9717 | if (swap) { |
9718 | genfn(tcg_res, tcg_zero, tcg_op, fpst); | |
9719 | } else { | |
9720 | genfn(tcg_res, tcg_op, tcg_zero, fpst); | |
9721 | } | |
9722 | if (is_scalar) { | |
9723 | write_fp_sreg(s, rd, tcg_res); | |
9724 | } else { | |
7d4dd1a7 | 9725 | write_vec_element_i32(s, tcg_res, rd, pass, size); |
8908f4d1 AB |
9726 | } |
9727 | } | |
9728 | tcg_temp_free_i32(tcg_res); | |
9729 | tcg_temp_free_i32(tcg_zero); | |
9730 | tcg_temp_free_i32(tcg_op); | |
4ff55bcb RH |
9731 | if (!is_scalar) { |
9732 | clear_vec_high(s, is_q, rd); | |
8908f4d1 AB |
9733 | } |
9734 | } | |
9735 | ||
9736 | tcg_temp_free_ptr(fpst); | |
9737 | } | |
9738 | ||
8f0c6758 AB |
9739 | static void handle_2misc_reciprocal(DisasContext *s, int opcode, |
9740 | bool is_scalar, bool is_u, bool is_q, | |
9741 | int size, int rn, int rd) | |
9742 | { | |
9743 | bool is_double = (size == 3); | |
d81ce0ef | 9744 | TCGv_ptr fpst = get_fpstatus_ptr(false); |
8f0c6758 AB |
9745 | |
9746 | if (is_double) { | |
9747 | TCGv_i64 tcg_op = tcg_temp_new_i64(); | |
9748 | TCGv_i64 tcg_res = tcg_temp_new_i64(); | |
9749 | int pass; | |
9750 | ||
9751 | for (pass = 0; pass < (is_scalar ? 1 : 2); pass++) { | |
9752 | read_vec_element(s, tcg_op, rn, pass, MO_64); | |
9753 | switch (opcode) { | |
b6d4443a AB |
9754 | case 0x3d: /* FRECPE */ |
9755 | gen_helper_recpe_f64(tcg_res, tcg_op, fpst); | |
9756 | break; | |
8f0c6758 AB |
9757 | case 0x3f: /* FRECPX */ |
9758 | gen_helper_frecpx_f64(tcg_res, tcg_op, fpst); | |
9759 | break; | |
c2fb418e AB |
9760 | case 0x7d: /* FRSQRTE */ |
9761 | gen_helper_rsqrte_f64(tcg_res, tcg_op, fpst); | |
9762 | break; | |
8f0c6758 AB |
9763 | default: |
9764 | g_assert_not_reached(); | |
9765 | } | |
9766 | write_vec_element(s, tcg_res, rd, pass, MO_64); | |
9767 | } | |
8f0c6758 AB |
9768 | tcg_temp_free_i64(tcg_res); |
9769 | tcg_temp_free_i64(tcg_op); | |
4ff55bcb | 9770 | clear_vec_high(s, !is_scalar, rd); |
8f0c6758 AB |
9771 | } else { |
9772 | TCGv_i32 tcg_op = tcg_temp_new_i32(); | |
9773 | TCGv_i32 tcg_res = tcg_temp_new_i32(); | |
9774 | int pass, maxpasses; | |
9775 | ||
9776 | if (is_scalar) { | |
9777 | maxpasses = 1; | |
9778 | } else { | |
9779 | maxpasses = is_q ? 4 : 2; | |
9780 | } | |
9781 | ||
9782 | for (pass = 0; pass < maxpasses; pass++) { | |
9783 | read_vec_element_i32(s, tcg_op, rn, pass, MO_32); | |
9784 | ||
9785 | switch (opcode) { | |
b6d4443a | 9786 | case 0x3c: /* URECPE */ |
fe6fb4be | 9787 | gen_helper_recpe_u32(tcg_res, tcg_op); |
b6d4443a AB |
9788 | break; |
9789 | case 0x3d: /* FRECPE */ | |
9790 | gen_helper_recpe_f32(tcg_res, tcg_op, fpst); | |
9791 | break; | |
8f0c6758 AB |
9792 | case 0x3f: /* FRECPX */ |
9793 | gen_helper_frecpx_f32(tcg_res, tcg_op, fpst); | |
9794 | break; | |
c2fb418e AB |
9795 | case 0x7d: /* FRSQRTE */ |
9796 | gen_helper_rsqrte_f32(tcg_res, tcg_op, fpst); | |
9797 | break; | |
8f0c6758 AB |
9798 | default: |
9799 | g_assert_not_reached(); | |
9800 | } | |
9801 | ||
9802 | if (is_scalar) { | |
9803 | write_fp_sreg(s, rd, tcg_res); | |
9804 | } else { | |
9805 | write_vec_element_i32(s, tcg_res, rd, pass, MO_32); | |
9806 | } | |
9807 | } | |
9808 | tcg_temp_free_i32(tcg_res); | |
9809 | tcg_temp_free_i32(tcg_op); | |
4ff55bcb RH |
9810 | if (!is_scalar) { |
9811 | clear_vec_high(s, is_q, rd); | |
8f0c6758 AB |
9812 | } |
9813 | } | |
9814 | tcg_temp_free_ptr(fpst); | |
9815 | } | |
9816 | ||
5201c136 AB |
9817 | static void handle_2misc_narrow(DisasContext *s, bool scalar, |
9818 | int opcode, bool u, bool is_q, | |
8b092ca9 AB |
9819 | int size, int rn, int rd) |
9820 | { | |
9821 | /* Handle 2-reg-misc ops which are narrowing (so each 2*size element | |
9822 | * in the source becomes a size element in the destination). | |
9823 | */ | |
9824 | int pass; | |
9825 | TCGv_i32 tcg_res[2]; | |
9826 | int destelt = is_q ? 2 : 0; | |
5201c136 | 9827 | int passes = scalar ? 1 : 2; |
8b092ca9 | 9828 | |
5201c136 AB |
9829 | if (scalar) { |
9830 | tcg_res[1] = tcg_const_i32(0); | |
9831 | } | |
9832 | ||
9833 | for (pass = 0; pass < passes; pass++) { | |
8b092ca9 AB |
9834 | TCGv_i64 tcg_op = tcg_temp_new_i64(); |
9835 | NeonGenNarrowFn *genfn = NULL; | |
9836 | NeonGenNarrowEnvFn *genenvfn = NULL; | |
9837 | ||
5201c136 AB |
9838 | if (scalar) { |
9839 | read_vec_element(s, tcg_op, rn, pass, size + 1); | |
9840 | } else { | |
9841 | read_vec_element(s, tcg_op, rn, pass, MO_64); | |
9842 | } | |
8b092ca9 AB |
9843 | tcg_res[pass] = tcg_temp_new_i32(); |
9844 | ||
9845 | switch (opcode) { | |
9846 | case 0x12: /* XTN, SQXTUN */ | |
9847 | { | |
9848 | static NeonGenNarrowFn * const xtnfns[3] = { | |
9849 | gen_helper_neon_narrow_u8, | |
9850 | gen_helper_neon_narrow_u16, | |
ecc7b3aa | 9851 | tcg_gen_extrl_i64_i32, |
8b092ca9 AB |
9852 | }; |
9853 | static NeonGenNarrowEnvFn * const sqxtunfns[3] = { | |
9854 | gen_helper_neon_unarrow_sat8, | |
9855 | gen_helper_neon_unarrow_sat16, | |
9856 | gen_helper_neon_unarrow_sat32, | |
9857 | }; | |
9858 | if (u) { | |
9859 | genenvfn = sqxtunfns[size]; | |
9860 | } else { | |
9861 | genfn = xtnfns[size]; | |
9862 | } | |
9863 | break; | |
9864 | } | |
9865 | case 0x14: /* SQXTN, UQXTN */ | |
9866 | { | |
9867 | static NeonGenNarrowEnvFn * const fns[3][2] = { | |
9868 | { gen_helper_neon_narrow_sat_s8, | |
9869 | gen_helper_neon_narrow_sat_u8 }, | |
9870 | { gen_helper_neon_narrow_sat_s16, | |
9871 | gen_helper_neon_narrow_sat_u16 }, | |
9872 | { gen_helper_neon_narrow_sat_s32, | |
9873 | gen_helper_neon_narrow_sat_u32 }, | |
9874 | }; | |
9875 | genenvfn = fns[size][u]; | |
9876 | break; | |
9877 | } | |
9878 | case 0x16: /* FCVTN, FCVTN2 */ | |
9879 | /* 32 bit to 16 bit or 64 bit to 32 bit float conversion */ | |
9880 | if (size == 2) { | |
9881 | gen_helper_vfp_fcvtsd(tcg_res[pass], tcg_op, cpu_env); | |
9882 | } else { | |
9883 | TCGv_i32 tcg_lo = tcg_temp_new_i32(); | |
9884 | TCGv_i32 tcg_hi = tcg_temp_new_i32(); | |
486624fc AB |
9885 | TCGv_ptr fpst = get_fpstatus_ptr(false); |
9886 | TCGv_i32 ahp = get_ahp_flag(); | |
9887 | ||
7cb36e18 | 9888 | tcg_gen_extr_i64_i32(tcg_lo, tcg_hi, tcg_op); |
486624fc AB |
9889 | gen_helper_vfp_fcvt_f32_to_f16(tcg_lo, tcg_lo, fpst, ahp); |
9890 | gen_helper_vfp_fcvt_f32_to_f16(tcg_hi, tcg_hi, fpst, ahp); | |
8b092ca9 AB |
9891 | tcg_gen_deposit_i32(tcg_res[pass], tcg_lo, tcg_hi, 16, 16); |
9892 | tcg_temp_free_i32(tcg_lo); | |
9893 | tcg_temp_free_i32(tcg_hi); | |
486624fc AB |
9894 | tcg_temp_free_ptr(fpst); |
9895 | tcg_temp_free_i32(ahp); | |
8b092ca9 AB |
9896 | } |
9897 | break; | |
5553955e PM |
9898 | case 0x56: /* FCVTXN, FCVTXN2 */ |
9899 | /* 64 bit to 32 bit float conversion | |
9900 | * with von Neumann rounding (round to odd) | |
9901 | */ | |
9902 | assert(size == 2); | |
9903 | gen_helper_fcvtx_f64_to_f32(tcg_res[pass], tcg_op, cpu_env); | |
9904 | break; | |
8b092ca9 AB |
9905 | default: |
9906 | g_assert_not_reached(); | |
9907 | } | |
9908 | ||
9909 | if (genfn) { | |
9910 | genfn(tcg_res[pass], tcg_op); | |
9911 | } else if (genenvfn) { | |
9912 | genenvfn(tcg_res[pass], cpu_env, tcg_op); | |
9913 | } | |
9914 | ||
9915 | tcg_temp_free_i64(tcg_op); | |
9916 | } | |
9917 | ||
9918 | for (pass = 0; pass < 2; pass++) { | |
9919 | write_vec_element_i32(s, tcg_res[pass], rd, destelt + pass, MO_32); | |
9920 | tcg_temp_free_i32(tcg_res[pass]); | |
9921 | } | |
4ff55bcb | 9922 | clear_vec_high(s, is_q, rd); |
8b092ca9 AB |
9923 | } |
9924 | ||
09e03735 AB |
9925 | /* Remaining saturating accumulating ops */ |
9926 | static void handle_2misc_satacc(DisasContext *s, bool is_scalar, bool is_u, | |
9927 | bool is_q, int size, int rn, int rd) | |
9928 | { | |
9929 | bool is_double = (size == 3); | |
9930 | ||
9931 | if (is_double) { | |
9932 | TCGv_i64 tcg_rn = tcg_temp_new_i64(); | |
9933 | TCGv_i64 tcg_rd = tcg_temp_new_i64(); | |
9934 | int pass; | |
9935 | ||
9936 | for (pass = 0; pass < (is_scalar ? 1 : 2); pass++) { | |
9937 | read_vec_element(s, tcg_rn, rn, pass, MO_64); | |
9938 | read_vec_element(s, tcg_rd, rd, pass, MO_64); | |
9939 | ||
9940 | if (is_u) { /* USQADD */ | |
9941 | gen_helper_neon_uqadd_s64(tcg_rd, cpu_env, tcg_rn, tcg_rd); | |
9942 | } else { /* SUQADD */ | |
9943 | gen_helper_neon_sqadd_u64(tcg_rd, cpu_env, tcg_rn, tcg_rd); | |
9944 | } | |
9945 | write_vec_element(s, tcg_rd, rd, pass, MO_64); | |
9946 | } | |
09e03735 AB |
9947 | tcg_temp_free_i64(tcg_rd); |
9948 | tcg_temp_free_i64(tcg_rn); | |
4ff55bcb | 9949 | clear_vec_high(s, !is_scalar, rd); |
09e03735 AB |
9950 | } else { |
9951 | TCGv_i32 tcg_rn = tcg_temp_new_i32(); | |
9952 | TCGv_i32 tcg_rd = tcg_temp_new_i32(); | |
9953 | int pass, maxpasses; | |
9954 | ||
9955 | if (is_scalar) { | |
9956 | maxpasses = 1; | |
9957 | } else { | |
9958 | maxpasses = is_q ? 4 : 2; | |
9959 | } | |
9960 | ||
9961 | for (pass = 0; pass < maxpasses; pass++) { | |
9962 | if (is_scalar) { | |
9963 | read_vec_element_i32(s, tcg_rn, rn, pass, size); | |
9964 | read_vec_element_i32(s, tcg_rd, rd, pass, size); | |
9965 | } else { | |
9966 | read_vec_element_i32(s, tcg_rn, rn, pass, MO_32); | |
9967 | read_vec_element_i32(s, tcg_rd, rd, pass, MO_32); | |
9968 | } | |
9969 | ||
9970 | if (is_u) { /* USQADD */ | |
9971 | switch (size) { | |
9972 | case 0: | |
9973 | gen_helper_neon_uqadd_s8(tcg_rd, cpu_env, tcg_rn, tcg_rd); | |
9974 | break; | |
9975 | case 1: | |
9976 | gen_helper_neon_uqadd_s16(tcg_rd, cpu_env, tcg_rn, tcg_rd); | |
9977 | break; | |
9978 | case 2: | |
9979 | gen_helper_neon_uqadd_s32(tcg_rd, cpu_env, tcg_rn, tcg_rd); | |
9980 | break; | |
9981 | default: | |
9982 | g_assert_not_reached(); | |
9983 | } | |
9984 | } else { /* SUQADD */ | |
9985 | switch (size) { | |
9986 | case 0: | |
9987 | gen_helper_neon_sqadd_u8(tcg_rd, cpu_env, tcg_rn, tcg_rd); | |
9988 | break; | |
9989 | case 1: | |
9990 | gen_helper_neon_sqadd_u16(tcg_rd, cpu_env, tcg_rn, tcg_rd); | |
9991 | break; | |
9992 | case 2: | |
9993 | gen_helper_neon_sqadd_u32(tcg_rd, cpu_env, tcg_rn, tcg_rd); | |
9994 | break; | |
9995 | default: | |
9996 | g_assert_not_reached(); | |
9997 | } | |
9998 | } | |
9999 | ||
10000 | if (is_scalar) { | |
10001 | TCGv_i64 tcg_zero = tcg_const_i64(0); | |
10002 | write_vec_element(s, tcg_zero, rd, 0, MO_64); | |
10003 | tcg_temp_free_i64(tcg_zero); | |
10004 | } | |
10005 | write_vec_element_i32(s, tcg_rd, rd, pass, MO_32); | |
10006 | } | |
09e03735 AB |
10007 | tcg_temp_free_i32(tcg_rd); |
10008 | tcg_temp_free_i32(tcg_rn); | |
4ff55bcb | 10009 | clear_vec_high(s, is_q, rd); |
09e03735 AB |
10010 | } |
10011 | } | |
10012 | ||
4ce31af4 | 10013 | /* AdvSIMD scalar two reg misc |
384b26fb AB |
10014 | * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0 |
10015 | * +-----+---+-----------+------+-----------+--------+-----+------+------+ | |
10016 | * | 0 1 | U | 1 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd | | |
10017 | * +-----+---+-----------+------+-----------+--------+-----+------+------+ | |
10018 | */ | |
10019 | static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn) | |
10020 | { | |
effa8e06 PM |
10021 | int rd = extract32(insn, 0, 5); |
10022 | int rn = extract32(insn, 5, 5); | |
10023 | int opcode = extract32(insn, 12, 5); | |
10024 | int size = extract32(insn, 22, 2); | |
10025 | bool u = extract32(insn, 29, 1); | |
04c7c6c2 PM |
10026 | bool is_fcvt = false; |
10027 | int rmode; | |
10028 | TCGv_i32 tcg_rmode; | |
10029 | TCGv_ptr tcg_fpstatus; | |
effa8e06 PM |
10030 | |
10031 | switch (opcode) { | |
09e03735 | 10032 | case 0x3: /* USQADD / SUQADD*/ |
8c6afa6a PM |
10033 | if (!fp_access_check(s)) { |
10034 | return; | |
10035 | } | |
09e03735 AB |
10036 | handle_2misc_satacc(s, true, u, false, size, rn, rd); |
10037 | return; | |
0a79bc87 AB |
10038 | case 0x7: /* SQABS / SQNEG */ |
10039 | break; | |
effa8e06 PM |
10040 | case 0xa: /* CMLT */ |
10041 | if (u) { | |
10042 | unallocated_encoding(s); | |
10043 | return; | |
10044 | } | |
10045 | /* fall through */ | |
10046 | case 0x8: /* CMGT, CMGE */ | |
10047 | case 0x9: /* CMEQ, CMLE */ | |
10048 | case 0xb: /* ABS, NEG */ | |
10049 | if (size != 3) { | |
10050 | unallocated_encoding(s); | |
10051 | return; | |
10052 | } | |
10053 | break; | |
5201c136 | 10054 | case 0x12: /* SQXTUN */ |
e44a90c5 | 10055 | if (!u) { |
5201c136 AB |
10056 | unallocated_encoding(s); |
10057 | return; | |
10058 | } | |
10059 | /* fall through */ | |
10060 | case 0x14: /* SQXTN, UQXTN */ | |
10061 | if (size == 3) { | |
10062 | unallocated_encoding(s); | |
10063 | return; | |
10064 | } | |
8c6afa6a PM |
10065 | if (!fp_access_check(s)) { |
10066 | return; | |
10067 | } | |
5201c136 AB |
10068 | handle_2misc_narrow(s, true, opcode, u, false, size, rn, rd); |
10069 | return; | |
8908f4d1 AB |
10070 | case 0xc ... 0xf: |
10071 | case 0x16 ... 0x1d: | |
10072 | case 0x1f: | |
10073 | /* Floating point: U, size[1] and opcode indicate operation; | |
10074 | * size[0] indicates single or double precision. | |
10075 | */ | |
10076 | opcode |= (extract32(size, 1, 1) << 5) | (u << 6); | |
10077 | size = extract32(size, 0, 1) ? 3 : 2; | |
10078 | switch (opcode) { | |
10079 | case 0x2c: /* FCMGT (zero) */ | |
10080 | case 0x2d: /* FCMEQ (zero) */ | |
10081 | case 0x2e: /* FCMLT (zero) */ | |
10082 | case 0x6c: /* FCMGE (zero) */ | |
10083 | case 0x6d: /* FCMLE (zero) */ | |
10084 | handle_2misc_fcmp_zero(s, opcode, true, u, true, size, rn, rd); | |
10085 | return; | |
10113b69 AB |
10086 | case 0x1d: /* SCVTF */ |
10087 | case 0x5d: /* UCVTF */ | |
10088 | { | |
10089 | bool is_signed = (opcode == 0x1d); | |
8c6afa6a PM |
10090 | if (!fp_access_check(s)) { |
10091 | return; | |
10092 | } | |
10113b69 AB |
10093 | handle_simd_intfp_conv(s, rd, rn, 1, is_signed, 0, size); |
10094 | return; | |
10095 | } | |
b6d4443a | 10096 | case 0x3d: /* FRECPE */ |
8f0c6758 | 10097 | case 0x3f: /* FRECPX */ |
c2fb418e | 10098 | case 0x7d: /* FRSQRTE */ |
8c6afa6a PM |
10099 | if (!fp_access_check(s)) { |
10100 | return; | |
10101 | } | |
8f0c6758 AB |
10102 | handle_2misc_reciprocal(s, opcode, true, u, true, size, rn, rd); |
10103 | return; | |
8908f4d1 AB |
10104 | case 0x1a: /* FCVTNS */ |
10105 | case 0x1b: /* FCVTMS */ | |
8908f4d1 AB |
10106 | case 0x3a: /* FCVTPS */ |
10107 | case 0x3b: /* FCVTZS */ | |
8908f4d1 AB |
10108 | case 0x5a: /* FCVTNU */ |
10109 | case 0x5b: /* FCVTMU */ | |
8908f4d1 AB |
10110 | case 0x7a: /* FCVTPU */ |
10111 | case 0x7b: /* FCVTZU */ | |
04c7c6c2 PM |
10112 | is_fcvt = true; |
10113 | rmode = extract32(opcode, 5, 1) | (extract32(opcode, 0, 1) << 1); | |
10114 | break; | |
10115 | case 0x1c: /* FCVTAS */ | |
10116 | case 0x5c: /* FCVTAU */ | |
10117 | /* TIEAWAY doesn't fit in the usual rounding mode encoding */ | |
10118 | is_fcvt = true; | |
10119 | rmode = FPROUNDING_TIEAWAY; | |
10120 | break; | |
04c7c6c2 | 10121 | case 0x56: /* FCVTXN, FCVTXN2 */ |
5553955e PM |
10122 | if (size == 2) { |
10123 | unallocated_encoding(s); | |
10124 | return; | |
10125 | } | |
8c6afa6a PM |
10126 | if (!fp_access_check(s)) { |
10127 | return; | |
10128 | } | |
5553955e PM |
10129 | handle_2misc_narrow(s, true, opcode, u, false, size - 1, rn, rd); |
10130 | return; | |
8908f4d1 AB |
10131 | default: |
10132 | unallocated_encoding(s); | |
10133 | return; | |
10134 | } | |
10135 | break; | |
effa8e06 | 10136 | default: |
09e03735 | 10137 | unallocated_encoding(s); |
effa8e06 PM |
10138 | return; |
10139 | } | |
10140 | ||
8c6afa6a PM |
10141 | if (!fp_access_check(s)) { |
10142 | return; | |
10143 | } | |
10144 | ||
04c7c6c2 PM |
10145 | if (is_fcvt) { |
10146 | tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode)); | |
d81ce0ef | 10147 | tcg_fpstatus = get_fpstatus_ptr(false); |
9b049916 | 10148 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); |
04c7c6c2 | 10149 | } else { |
f764718d RH |
10150 | tcg_rmode = NULL; |
10151 | tcg_fpstatus = NULL; | |
04c7c6c2 PM |
10152 | } |
10153 | ||
effa8e06 PM |
10154 | if (size == 3) { |
10155 | TCGv_i64 tcg_rn = read_fp_dreg(s, rn); | |
10156 | TCGv_i64 tcg_rd = tcg_temp_new_i64(); | |
10157 | ||
04c7c6c2 | 10158 | handle_2misc_64(s, opcode, u, tcg_rd, tcg_rn, tcg_rmode, tcg_fpstatus); |
effa8e06 PM |
10159 | write_fp_dreg(s, rd, tcg_rd); |
10160 | tcg_temp_free_i64(tcg_rd); | |
10161 | tcg_temp_free_i64(tcg_rn); | |
0a79bc87 AB |
10162 | } else { |
10163 | TCGv_i32 tcg_rn = tcg_temp_new_i32(); | |
04c7c6c2 PM |
10164 | TCGv_i32 tcg_rd = tcg_temp_new_i32(); |
10165 | ||
0a79bc87 AB |
10166 | read_vec_element_i32(s, tcg_rn, rn, 0, size); |
10167 | ||
04c7c6c2 | 10168 | switch (opcode) { |
0a79bc87 AB |
10169 | case 0x7: /* SQABS, SQNEG */ |
10170 | { | |
10171 | NeonGenOneOpEnvFn *genfn; | |
10172 | static NeonGenOneOpEnvFn * const fns[3][2] = { | |
10173 | { gen_helper_neon_qabs_s8, gen_helper_neon_qneg_s8 }, | |
10174 | { gen_helper_neon_qabs_s16, gen_helper_neon_qneg_s16 }, | |
10175 | { gen_helper_neon_qabs_s32, gen_helper_neon_qneg_s32 }, | |
10176 | }; | |
10177 | genfn = fns[size][u]; | |
10178 | genfn(tcg_rd, cpu_env, tcg_rn); | |
10179 | break; | |
10180 | } | |
04c7c6c2 PM |
10181 | case 0x1a: /* FCVTNS */ |
10182 | case 0x1b: /* FCVTMS */ | |
10183 | case 0x1c: /* FCVTAS */ | |
10184 | case 0x3a: /* FCVTPS */ | |
10185 | case 0x3b: /* FCVTZS */ | |
10186 | { | |
10187 | TCGv_i32 tcg_shift = tcg_const_i32(0); | |
10188 | gen_helper_vfp_tosls(tcg_rd, tcg_rn, tcg_shift, tcg_fpstatus); | |
10189 | tcg_temp_free_i32(tcg_shift); | |
10190 | break; | |
10191 | } | |
10192 | case 0x5a: /* FCVTNU */ | |
10193 | case 0x5b: /* FCVTMU */ | |
10194 | case 0x5c: /* FCVTAU */ | |
10195 | case 0x7a: /* FCVTPU */ | |
10196 | case 0x7b: /* FCVTZU */ | |
10197 | { | |
10198 | TCGv_i32 tcg_shift = tcg_const_i32(0); | |
10199 | gen_helper_vfp_touls(tcg_rd, tcg_rn, tcg_shift, tcg_fpstatus); | |
10200 | tcg_temp_free_i32(tcg_shift); | |
10201 | break; | |
10202 | } | |
10203 | default: | |
10204 | g_assert_not_reached(); | |
10205 | } | |
10206 | ||
10207 | write_fp_sreg(s, rd, tcg_rd); | |
10208 | tcg_temp_free_i32(tcg_rd); | |
10209 | tcg_temp_free_i32(tcg_rn); | |
effa8e06 | 10210 | } |
04c7c6c2 PM |
10211 | |
10212 | if (is_fcvt) { | |
9b049916 | 10213 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); |
04c7c6c2 PM |
10214 | tcg_temp_free_i32(tcg_rmode); |
10215 | tcg_temp_free_ptr(tcg_fpstatus); | |
10216 | } | |
384b26fb AB |
10217 | } |
10218 | ||
4d1cef84 AB |
10219 | /* SSHR[RA]/USHR[RA] - Vector shift right (optional rounding/accumulate) */ |
10220 | static void handle_vec_simd_shri(DisasContext *s, bool is_q, bool is_u, | |
10221 | int immh, int immb, int opcode, int rn, int rd) | |
10222 | { | |
10223 | int size = 32 - clz32(immh) - 1; | |
10224 | int immhb = immh << 3 | immb; | |
10225 | int shift = 2 * (8 << size) - immhb; | |
3f08f0bc | 10226 | GVecGen2iFn *gvec_fn; |
4d1cef84 AB |
10227 | |
10228 | if (extract32(immh, 3, 1) && !is_q) { | |
10229 | unallocated_encoding(s); | |
10230 | return; | |
10231 | } | |
8dae4697 | 10232 | tcg_debug_assert(size <= 3); |
4d1cef84 | 10233 | |
8c6afa6a PM |
10234 | if (!fp_access_check(s)) { |
10235 | return; | |
10236 | } | |
10237 | ||
4d1cef84 AB |
10238 | switch (opcode) { |
10239 | case 0x02: /* SSRA / USRA (accumulate) */ | |
3f08f0bc RH |
10240 | gvec_fn = is_u ? gen_gvec_usra : gen_gvec_ssra; |
10241 | break; | |
893ab054 | 10242 | |
cdb45a60 | 10243 | case 0x08: /* SRI */ |
3f08f0bc RH |
10244 | gvec_fn = gen_gvec_sri; |
10245 | break; | |
cdb45a60 RH |
10246 | |
10247 | case 0x00: /* SSHR / USHR */ | |
10248 | if (is_u) { | |
10249 | if (shift == 8 << size) { | |
10250 | /* Shift count the same size as element size produces zero. */ | |
8711e71f RH |
10251 | tcg_gen_gvec_dup_imm(size, vec_full_reg_offset(s, rd), |
10252 | is_q ? 16 : 8, vec_full_reg_size(s), 0); | |
3f08f0bc | 10253 | return; |
cdb45a60 | 10254 | } |
3f08f0bc | 10255 | gvec_fn = tcg_gen_gvec_shri; |
cdb45a60 RH |
10256 | } else { |
10257 | /* Shift count the same size as element size produces all sign. */ | |
10258 | if (shift == 8 << size) { | |
10259 | shift -= 1; | |
10260 | } | |
3f08f0bc | 10261 | gvec_fn = tcg_gen_gvec_sari; |
cdb45a60 | 10262 | } |
3f08f0bc | 10263 | break; |
cdb45a60 | 10264 | |
4d1cef84 | 10265 | case 0x04: /* SRSHR / URSHR (rounding) */ |
3f08f0bc RH |
10266 | gvec_fn = is_u ? gen_gvec_urshr : gen_gvec_srshr; |
10267 | break; | |
6ccd48d4 | 10268 | |
4d1cef84 | 10269 | case 0x06: /* SRSRA / URSRA (accum + rounding) */ |
3f08f0bc RH |
10270 | gvec_fn = is_u ? gen_gvec_ursra : gen_gvec_srsra; |
10271 | break; | |
6ccd48d4 | 10272 | |
cdb45a60 RH |
10273 | default: |
10274 | g_assert_not_reached(); | |
4d1cef84 AB |
10275 | } |
10276 | ||
3f08f0bc | 10277 | gen_gvec_fn2i(s, is_q, rd, rn, shift, gvec_fn, size); |
cdb45a60 | 10278 | } |
4d1cef84 | 10279 | |
4d1cef84 AB |
10280 | /* SHL/SLI - Vector shift left */ |
10281 | static void handle_vec_simd_shli(DisasContext *s, bool is_q, bool insert, | |
cdb45a60 | 10282 | int immh, int immb, int opcode, int rn, int rd) |
4d1cef84 AB |
10283 | { |
10284 | int size = 32 - clz32(immh) - 1; | |
10285 | int immhb = immh << 3 | immb; | |
10286 | int shift = immhb - (8 << size); | |
4d1cef84 | 10287 | |
f6c98f91 PM |
10288 | /* Range of size is limited by decode: immh is a non-zero 4 bit field */ |
10289 | assert(size >= 0 && size <= 3); | |
4d1cef84 | 10290 | |
f6c98f91 | 10291 | if (extract32(immh, 3, 1) && !is_q) { |
4d1cef84 AB |
10292 | unallocated_encoding(s); |
10293 | return; | |
10294 | } | |
10295 | ||
8c6afa6a PM |
10296 | if (!fp_access_check(s)) { |
10297 | return; | |
10298 | } | |
10299 | ||
cdb45a60 | 10300 | if (insert) { |
893ab054 | 10301 | gen_gvec_fn2i(s, is_q, rd, rn, shift, gen_gvec_sli, size); |
cdb45a60 RH |
10302 | } else { |
10303 | gen_gvec_fn2i(s, is_q, rd, rn, shift, tcg_gen_gvec_shli, size); | |
4d1cef84 AB |
10304 | } |
10305 | } | |
10306 | ||
10307 | /* USHLL/SHLL - Vector shift left with widening */ | |
10308 | static void handle_vec_simd_wshli(DisasContext *s, bool is_q, bool is_u, | |
10309 | int immh, int immb, int opcode, int rn, int rd) | |
10310 | { | |
10311 | int size = 32 - clz32(immh) - 1; | |
10312 | int immhb = immh << 3 | immb; | |
10313 | int shift = immhb - (8 << size); | |
10314 | int dsize = 64; | |
10315 | int esize = 8 << size; | |
10316 | int elements = dsize/esize; | |
10317 | TCGv_i64 tcg_rn = new_tmp_a64(s); | |
10318 | TCGv_i64 tcg_rd = new_tmp_a64(s); | |
10319 | int i; | |
10320 | ||
10321 | if (size >= 3) { | |
10322 | unallocated_encoding(s); | |
10323 | return; | |
10324 | } | |
10325 | ||
8c6afa6a PM |
10326 | if (!fp_access_check(s)) { |
10327 | return; | |
10328 | } | |
10329 | ||
4d1cef84 AB |
10330 | /* For the LL variants the store is larger than the load, |
10331 | * so if rd == rn we would overwrite parts of our input. | |
10332 | * So load everything right now and use shifts in the main loop. | |
10333 | */ | |
10334 | read_vec_element(s, tcg_rn, rn, is_q ? 1 : 0, MO_64); | |
10335 | ||
10336 | for (i = 0; i < elements; i++) { | |
10337 | tcg_gen_shri_i64(tcg_rd, tcg_rn, i * esize); | |
10338 | ext_and_shift_reg(tcg_rd, tcg_rd, size | (!is_u << 2), 0); | |
10339 | tcg_gen_shli_i64(tcg_rd, tcg_rd, shift); | |
10340 | write_vec_element(s, tcg_rd, rd, i, size + 1); | |
10341 | } | |
10342 | } | |
10343 | ||
c1b876b2 AB |
10344 | /* SHRN/RSHRN - Shift right with narrowing (and potential rounding) */ |
10345 | static void handle_vec_simd_shrn(DisasContext *s, bool is_q, | |
10346 | int immh, int immb, int opcode, int rn, int rd) | |
10347 | { | |
10348 | int immhb = immh << 3 | immb; | |
10349 | int size = 32 - clz32(immh) - 1; | |
10350 | int dsize = 64; | |
10351 | int esize = 8 << size; | |
10352 | int elements = dsize/esize; | |
10353 | int shift = (2 * esize) - immhb; | |
10354 | bool round = extract32(opcode, 0, 1); | |
10355 | TCGv_i64 tcg_rn, tcg_rd, tcg_final; | |
10356 | TCGv_i64 tcg_round; | |
10357 | int i; | |
10358 | ||
10359 | if (extract32(immh, 3, 1)) { | |
10360 | unallocated_encoding(s); | |
10361 | return; | |
10362 | } | |
10363 | ||
8c6afa6a PM |
10364 | if (!fp_access_check(s)) { |
10365 | return; | |
10366 | } | |
10367 | ||
c1b876b2 AB |
10368 | tcg_rn = tcg_temp_new_i64(); |
10369 | tcg_rd = tcg_temp_new_i64(); | |
10370 | tcg_final = tcg_temp_new_i64(); | |
10371 | read_vec_element(s, tcg_final, rd, is_q ? 1 : 0, MO_64); | |
10372 | ||
10373 | if (round) { | |
10374 | uint64_t round_const = 1ULL << (shift - 1); | |
10375 | tcg_round = tcg_const_i64(round_const); | |
10376 | } else { | |
f764718d | 10377 | tcg_round = NULL; |
c1b876b2 AB |
10378 | } |
10379 | ||
10380 | for (i = 0; i < elements; i++) { | |
10381 | read_vec_element(s, tcg_rn, rn, i, size+1); | |
10382 | handle_shri_with_rndacc(tcg_rd, tcg_rn, tcg_round, | |
10383 | false, true, size+1, shift); | |
10384 | ||
10385 | tcg_gen_deposit_i64(tcg_final, tcg_final, tcg_rd, esize * i, esize); | |
10386 | } | |
10387 | ||
10388 | if (!is_q) { | |
c1b876b2 AB |
10389 | write_vec_element(s, tcg_final, rd, 0, MO_64); |
10390 | } else { | |
10391 | write_vec_element(s, tcg_final, rd, 1, MO_64); | |
10392 | } | |
c1b876b2 AB |
10393 | if (round) { |
10394 | tcg_temp_free_i64(tcg_round); | |
10395 | } | |
10396 | tcg_temp_free_i64(tcg_rn); | |
10397 | tcg_temp_free_i64(tcg_rd); | |
10398 | tcg_temp_free_i64(tcg_final); | |
4ff55bcb RH |
10399 | |
10400 | clear_vec_high(s, is_q, rd); | |
c1b876b2 AB |
10401 | } |
10402 | ||
10403 | ||
4ce31af4 | 10404 | /* AdvSIMD shift by immediate |
384b26fb AB |
10405 | * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0 |
10406 | * +---+---+---+-------------+------+------+--------+---+------+------+ | |
10407 | * | 0 | Q | U | 0 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd | | |
10408 | * +---+---+---+-------------+------+------+--------+---+------+------+ | |
10409 | */ | |
10410 | static void disas_simd_shift_imm(DisasContext *s, uint32_t insn) | |
10411 | { | |
4d1cef84 AB |
10412 | int rd = extract32(insn, 0, 5); |
10413 | int rn = extract32(insn, 5, 5); | |
10414 | int opcode = extract32(insn, 11, 5); | |
10415 | int immb = extract32(insn, 16, 3); | |
10416 | int immh = extract32(insn, 19, 4); | |
10417 | bool is_u = extract32(insn, 29, 1); | |
10418 | bool is_q = extract32(insn, 30, 1); | |
10419 | ||
3944d58d RH |
10420 | /* data_proc_simd[] has sent immh == 0 to disas_simd_mod_imm. */ |
10421 | assert(immh != 0); | |
10422 | ||
4d1cef84 | 10423 | switch (opcode) { |
37a706ad PM |
10424 | case 0x08: /* SRI */ |
10425 | if (!is_u) { | |
10426 | unallocated_encoding(s); | |
10427 | return; | |
10428 | } | |
10429 | /* fall through */ | |
4d1cef84 AB |
10430 | case 0x00: /* SSHR / USHR */ |
10431 | case 0x02: /* SSRA / USRA (accumulate) */ | |
10432 | case 0x04: /* SRSHR / URSHR (rounding) */ | |
10433 | case 0x06: /* SRSRA / URSRA (accum + rounding) */ | |
10434 | handle_vec_simd_shri(s, is_q, is_u, immh, immb, opcode, rn, rd); | |
10435 | break; | |
10436 | case 0x0a: /* SHL / SLI */ | |
10437 | handle_vec_simd_shli(s, is_q, is_u, immh, immb, opcode, rn, rd); | |
10438 | break; | |
c1b876b2 AB |
10439 | case 0x10: /* SHRN */ |
10440 | case 0x11: /* RSHRN / SQRSHRUN */ | |
10441 | if (is_u) { | |
10442 | handle_vec_simd_sqshrn(s, false, is_q, false, true, immh, immb, | |
10443 | opcode, rn, rd); | |
10444 | } else { | |
10445 | handle_vec_simd_shrn(s, is_q, immh, immb, opcode, rn, rd); | |
10446 | } | |
10447 | break; | |
10448 | case 0x12: /* SQSHRN / UQSHRN */ | |
10449 | case 0x13: /* SQRSHRN / UQRSHRN */ | |
10450 | handle_vec_simd_sqshrn(s, false, is_q, is_u, is_u, immh, immb, | |
10451 | opcode, rn, rd); | |
10452 | break; | |
4d1cef84 AB |
10453 | case 0x14: /* SSHLL / USHLL */ |
10454 | handle_vec_simd_wshli(s, is_q, is_u, immh, immb, opcode, rn, rd); | |
10455 | break; | |
10113b69 AB |
10456 | case 0x1c: /* SCVTF / UCVTF */ |
10457 | handle_simd_shift_intfp_conv(s, false, is_q, is_u, immh, immb, | |
10458 | opcode, rn, rd); | |
10459 | break; | |
a566da1b | 10460 | case 0xc: /* SQSHLU */ |
a847f32c PM |
10461 | if (!is_u) { |
10462 | unallocated_encoding(s); | |
10463 | return; | |
10464 | } | |
10465 | handle_simd_qshl(s, false, is_q, false, true, immh, immb, rn, rd); | |
10466 | break; | |
a566da1b | 10467 | case 0xe: /* SQSHL, UQSHL */ |
a847f32c PM |
10468 | handle_simd_qshl(s, false, is_q, is_u, is_u, immh, immb, rn, rd); |
10469 | break; | |
10113b69 | 10470 | case 0x1f: /* FCVTZS/ FCVTZU */ |
2ed3ea11 | 10471 | handle_simd_shift_fpint_conv(s, false, is_q, is_u, immh, immb, rn, rd); |
10113b69 | 10472 | return; |
4d1cef84 | 10473 | default: |
a566da1b | 10474 | unallocated_encoding(s); |
4d1cef84 AB |
10475 | return; |
10476 | } | |
384b26fb AB |
10477 | } |
10478 | ||
70d7f984 PM |
10479 | /* Generate code to do a "long" addition or subtraction, ie one done in |
10480 | * TCGv_i64 on vector lanes twice the width specified by size. | |
10481 | */ | |
10482 | static void gen_neon_addl(int size, bool is_sub, TCGv_i64 tcg_res, | |
10483 | TCGv_i64 tcg_op1, TCGv_i64 tcg_op2) | |
10484 | { | |
10485 | static NeonGenTwo64OpFn * const fns[3][2] = { | |
10486 | { gen_helper_neon_addl_u16, gen_helper_neon_subl_u16 }, | |
10487 | { gen_helper_neon_addl_u32, gen_helper_neon_subl_u32 }, | |
10488 | { tcg_gen_add_i64, tcg_gen_sub_i64 }, | |
10489 | }; | |
10490 | NeonGenTwo64OpFn *genfn; | |
10491 | assert(size < 3); | |
10492 | ||
10493 | genfn = fns[size][is_sub]; | |
10494 | genfn(tcg_res, tcg_op1, tcg_op2); | |
10495 | } | |
10496 | ||
a08582f4 PM |
10497 | static void handle_3rd_widening(DisasContext *s, int is_q, int is_u, int size, |
10498 | int opcode, int rd, int rn, int rm) | |
10499 | { | |
10500 | /* 3-reg-different widening insns: 64 x 64 -> 128 */ | |
10501 | TCGv_i64 tcg_res[2]; | |
10502 | int pass, accop; | |
10503 | ||
10504 | tcg_res[0] = tcg_temp_new_i64(); | |
10505 | tcg_res[1] = tcg_temp_new_i64(); | |
10506 | ||
10507 | /* Does this op do an adding accumulate, a subtracting accumulate, | |
10508 | * or no accumulate at all? | |
10509 | */ | |
10510 | switch (opcode) { | |
10511 | case 5: | |
10512 | case 8: | |
10513 | case 9: | |
10514 | accop = 1; | |
10515 | break; | |
10516 | case 10: | |
10517 | case 11: | |
10518 | accop = -1; | |
10519 | break; | |
10520 | default: | |
10521 | accop = 0; | |
10522 | break; | |
10523 | } | |
10524 | ||
10525 | if (accop != 0) { | |
10526 | read_vec_element(s, tcg_res[0], rd, 0, MO_64); | |
10527 | read_vec_element(s, tcg_res[1], rd, 1, MO_64); | |
10528 | } | |
10529 | ||
10530 | /* size == 2 means two 32x32->64 operations; this is worth special | |
10531 | * casing because we can generally handle it inline. | |
10532 | */ | |
10533 | if (size == 2) { | |
10534 | for (pass = 0; pass < 2; pass++) { | |
10535 | TCGv_i64 tcg_op1 = tcg_temp_new_i64(); | |
10536 | TCGv_i64 tcg_op2 = tcg_temp_new_i64(); | |
10537 | TCGv_i64 tcg_passres; | |
14776ab5 | 10538 | MemOp memop = MO_32 | (is_u ? 0 : MO_SIGN); |
a08582f4 PM |
10539 | |
10540 | int elt = pass + is_q * 2; | |
10541 | ||
10542 | read_vec_element(s, tcg_op1, rn, elt, memop); | |
10543 | read_vec_element(s, tcg_op2, rm, elt, memop); | |
10544 | ||
10545 | if (accop == 0) { | |
10546 | tcg_passres = tcg_res[pass]; | |
10547 | } else { | |
10548 | tcg_passres = tcg_temp_new_i64(); | |
10549 | } | |
10550 | ||
10551 | switch (opcode) { | |
70d7f984 PM |
10552 | case 0: /* SADDL, SADDL2, UADDL, UADDL2 */ |
10553 | tcg_gen_add_i64(tcg_passres, tcg_op1, tcg_op2); | |
10554 | break; | |
10555 | case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */ | |
10556 | tcg_gen_sub_i64(tcg_passres, tcg_op1, tcg_op2); | |
10557 | break; | |
0ae39320 PM |
10558 | case 5: /* SABAL, SABAL2, UABAL, UABAL2 */ |
10559 | case 7: /* SABDL, SABDL2, UABDL, UABDL2 */ | |
10560 | { | |
10561 | TCGv_i64 tcg_tmp1 = tcg_temp_new_i64(); | |
10562 | TCGv_i64 tcg_tmp2 = tcg_temp_new_i64(); | |
10563 | ||
10564 | tcg_gen_sub_i64(tcg_tmp1, tcg_op1, tcg_op2); | |
10565 | tcg_gen_sub_i64(tcg_tmp2, tcg_op2, tcg_op1); | |
10566 | tcg_gen_movcond_i64(is_u ? TCG_COND_GEU : TCG_COND_GE, | |
10567 | tcg_passres, | |
10568 | tcg_op1, tcg_op2, tcg_tmp1, tcg_tmp2); | |
10569 | tcg_temp_free_i64(tcg_tmp1); | |
10570 | tcg_temp_free_i64(tcg_tmp2); | |
10571 | break; | |
10572 | } | |
a08582f4 PM |
10573 | case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */ |
10574 | case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */ | |
10575 | case 12: /* UMULL, UMULL2, SMULL, SMULL2 */ | |
10576 | tcg_gen_mul_i64(tcg_passres, tcg_op1, tcg_op2); | |
10577 | break; | |
70d7f984 PM |
10578 | case 9: /* SQDMLAL, SQDMLAL2 */ |
10579 | case 11: /* SQDMLSL, SQDMLSL2 */ | |
10580 | case 13: /* SQDMULL, SQDMULL2 */ | |
10581 | tcg_gen_mul_i64(tcg_passres, tcg_op1, tcg_op2); | |
10582 | gen_helper_neon_addl_saturate_s64(tcg_passres, cpu_env, | |
10583 | tcg_passres, tcg_passres); | |
10584 | break; | |
a08582f4 PM |
10585 | default: |
10586 | g_assert_not_reached(); | |
10587 | } | |
10588 | ||
70d7f984 PM |
10589 | if (opcode == 9 || opcode == 11) { |
10590 | /* saturating accumulate ops */ | |
10591 | if (accop < 0) { | |
10592 | tcg_gen_neg_i64(tcg_passres, tcg_passres); | |
10593 | } | |
10594 | gen_helper_neon_addl_saturate_s64(tcg_res[pass], cpu_env, | |
10595 | tcg_res[pass], tcg_passres); | |
10596 | } else if (accop > 0) { | |
a08582f4 | 10597 | tcg_gen_add_i64(tcg_res[pass], tcg_res[pass], tcg_passres); |
a08582f4 PM |
10598 | } else if (accop < 0) { |
10599 | tcg_gen_sub_i64(tcg_res[pass], tcg_res[pass], tcg_passres); | |
70d7f984 PM |
10600 | } |
10601 | ||
10602 | if (accop != 0) { | |
a08582f4 PM |
10603 | tcg_temp_free_i64(tcg_passres); |
10604 | } | |
10605 | ||
10606 | tcg_temp_free_i64(tcg_op1); | |
10607 | tcg_temp_free_i64(tcg_op2); | |
10608 | } | |
10609 | } else { | |
10610 | /* size 0 or 1, generally helper functions */ | |
10611 | for (pass = 0; pass < 2; pass++) { | |
10612 | TCGv_i32 tcg_op1 = tcg_temp_new_i32(); | |
10613 | TCGv_i32 tcg_op2 = tcg_temp_new_i32(); | |
10614 | TCGv_i64 tcg_passres; | |
10615 | int elt = pass + is_q * 2; | |
10616 | ||
10617 | read_vec_element_i32(s, tcg_op1, rn, elt, MO_32); | |
10618 | read_vec_element_i32(s, tcg_op2, rm, elt, MO_32); | |
10619 | ||
10620 | if (accop == 0) { | |
10621 | tcg_passres = tcg_res[pass]; | |
10622 | } else { | |
10623 | tcg_passres = tcg_temp_new_i64(); | |
10624 | } | |
10625 | ||
10626 | switch (opcode) { | |
70d7f984 PM |
10627 | case 0: /* SADDL, SADDL2, UADDL, UADDL2 */ |
10628 | case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */ | |
10629 | { | |
10630 | TCGv_i64 tcg_op2_64 = tcg_temp_new_i64(); | |
10631 | static NeonGenWidenFn * const widenfns[2][2] = { | |
10632 | { gen_helper_neon_widen_s8, gen_helper_neon_widen_u8 }, | |
10633 | { gen_helper_neon_widen_s16, gen_helper_neon_widen_u16 }, | |
10634 | }; | |
10635 | NeonGenWidenFn *widenfn = widenfns[size][is_u]; | |
10636 | ||
10637 | widenfn(tcg_op2_64, tcg_op2); | |
10638 | widenfn(tcg_passres, tcg_op1); | |
10639 | gen_neon_addl(size, (opcode == 2), tcg_passres, | |
10640 | tcg_passres, tcg_op2_64); | |
10641 | tcg_temp_free_i64(tcg_op2_64); | |
10642 | break; | |
10643 | } | |
0ae39320 PM |
10644 | case 5: /* SABAL, SABAL2, UABAL, UABAL2 */ |
10645 | case 7: /* SABDL, SABDL2, UABDL, UABDL2 */ | |
10646 | if (size == 0) { | |
10647 | if (is_u) { | |
10648 | gen_helper_neon_abdl_u16(tcg_passres, tcg_op1, tcg_op2); | |
10649 | } else { | |
10650 | gen_helper_neon_abdl_s16(tcg_passres, tcg_op1, tcg_op2); | |
10651 | } | |
10652 | } else { | |
10653 | if (is_u) { | |
10654 | gen_helper_neon_abdl_u32(tcg_passres, tcg_op1, tcg_op2); | |
10655 | } else { | |
10656 | gen_helper_neon_abdl_s32(tcg_passres, tcg_op1, tcg_op2); | |
10657 | } | |
10658 | } | |
10659 | break; | |
a08582f4 PM |
10660 | case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */ |
10661 | case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */ | |
10662 | case 12: /* UMULL, UMULL2, SMULL, SMULL2 */ | |
10663 | if (size == 0) { | |
10664 | if (is_u) { | |
10665 | gen_helper_neon_mull_u8(tcg_passres, tcg_op1, tcg_op2); | |
10666 | } else { | |
10667 | gen_helper_neon_mull_s8(tcg_passres, tcg_op1, tcg_op2); | |
10668 | } | |
10669 | } else { | |
10670 | if (is_u) { | |
10671 | gen_helper_neon_mull_u16(tcg_passres, tcg_op1, tcg_op2); | |
10672 | } else { | |
10673 | gen_helper_neon_mull_s16(tcg_passres, tcg_op1, tcg_op2); | |
10674 | } | |
10675 | } | |
10676 | break; | |
70d7f984 PM |
10677 | case 9: /* SQDMLAL, SQDMLAL2 */ |
10678 | case 11: /* SQDMLSL, SQDMLSL2 */ | |
10679 | case 13: /* SQDMULL, SQDMULL2 */ | |
10680 | assert(size == 1); | |
10681 | gen_helper_neon_mull_s16(tcg_passres, tcg_op1, tcg_op2); | |
10682 | gen_helper_neon_addl_saturate_s32(tcg_passres, cpu_env, | |
10683 | tcg_passres, tcg_passres); | |
10684 | break; | |
a08582f4 PM |
10685 | default: |
10686 | g_assert_not_reached(); | |
10687 | } | |
10688 | tcg_temp_free_i32(tcg_op1); | |
10689 | tcg_temp_free_i32(tcg_op2); | |
10690 | ||
70d7f984 PM |
10691 | if (accop != 0) { |
10692 | if (opcode == 9 || opcode == 11) { | |
10693 | /* saturating accumulate ops */ | |
10694 | if (accop < 0) { | |
10695 | gen_helper_neon_negl_u32(tcg_passres, tcg_passres); | |
10696 | } | |
10697 | gen_helper_neon_addl_saturate_s32(tcg_res[pass], cpu_env, | |
10698 | tcg_res[pass], | |
10699 | tcg_passres); | |
a08582f4 | 10700 | } else { |
70d7f984 PM |
10701 | gen_neon_addl(size, (accop < 0), tcg_res[pass], |
10702 | tcg_res[pass], tcg_passres); | |
a08582f4 PM |
10703 | } |
10704 | tcg_temp_free_i64(tcg_passres); | |
10705 | } | |
10706 | } | |
10707 | } | |
10708 | ||
10709 | write_vec_element(s, tcg_res[0], rd, 0, MO_64); | |
10710 | write_vec_element(s, tcg_res[1], rd, 1, MO_64); | |
10711 | tcg_temp_free_i64(tcg_res[0]); | |
10712 | tcg_temp_free_i64(tcg_res[1]); | |
10713 | } | |
10714 | ||
dfc15c7c PM |
10715 | static void handle_3rd_wide(DisasContext *s, int is_q, int is_u, int size, |
10716 | int opcode, int rd, int rn, int rm) | |
10717 | { | |
10718 | TCGv_i64 tcg_res[2]; | |
10719 | int part = is_q ? 2 : 0; | |
10720 | int pass; | |
10721 | ||
10722 | for (pass = 0; pass < 2; pass++) { | |
10723 | TCGv_i64 tcg_op1 = tcg_temp_new_i64(); | |
10724 | TCGv_i32 tcg_op2 = tcg_temp_new_i32(); | |
10725 | TCGv_i64 tcg_op2_wide = tcg_temp_new_i64(); | |
10726 | static NeonGenWidenFn * const widenfns[3][2] = { | |
10727 | { gen_helper_neon_widen_s8, gen_helper_neon_widen_u8 }, | |
10728 | { gen_helper_neon_widen_s16, gen_helper_neon_widen_u16 }, | |
10729 | { tcg_gen_ext_i32_i64, tcg_gen_extu_i32_i64 }, | |
10730 | }; | |
10731 | NeonGenWidenFn *widenfn = widenfns[size][is_u]; | |
10732 | ||
10733 | read_vec_element(s, tcg_op1, rn, pass, MO_64); | |
10734 | read_vec_element_i32(s, tcg_op2, rm, part + pass, MO_32); | |
10735 | widenfn(tcg_op2_wide, tcg_op2); | |
10736 | tcg_temp_free_i32(tcg_op2); | |
10737 | tcg_res[pass] = tcg_temp_new_i64(); | |
10738 | gen_neon_addl(size, (opcode == 3), | |
10739 | tcg_res[pass], tcg_op1, tcg_op2_wide); | |
10740 | tcg_temp_free_i64(tcg_op1); | |
10741 | tcg_temp_free_i64(tcg_op2_wide); | |
10742 | } | |
10743 | ||
10744 | for (pass = 0; pass < 2; pass++) { | |
10745 | write_vec_element(s, tcg_res[pass], rd, pass, MO_64); | |
10746 | tcg_temp_free_i64(tcg_res[pass]); | |
10747 | } | |
10748 | } | |
10749 | ||
e4b998d4 PM |
10750 | static void do_narrow_round_high_u32(TCGv_i32 res, TCGv_i64 in) |
10751 | { | |
10752 | tcg_gen_addi_i64(in, in, 1U << 31); | |
7cb36e18 | 10753 | tcg_gen_extrh_i64_i32(res, in); |
e4b998d4 PM |
10754 | } |
10755 | ||
10756 | static void handle_3rd_narrowing(DisasContext *s, int is_q, int is_u, int size, | |
10757 | int opcode, int rd, int rn, int rm) | |
10758 | { | |
10759 | TCGv_i32 tcg_res[2]; | |
10760 | int part = is_q ? 2 : 0; | |
10761 | int pass; | |
10762 | ||
10763 | for (pass = 0; pass < 2; pass++) { | |
10764 | TCGv_i64 tcg_op1 = tcg_temp_new_i64(); | |
10765 | TCGv_i64 tcg_op2 = tcg_temp_new_i64(); | |
10766 | TCGv_i64 tcg_wideres = tcg_temp_new_i64(); | |
10767 | static NeonGenNarrowFn * const narrowfns[3][2] = { | |
10768 | { gen_helper_neon_narrow_high_u8, | |
10769 | gen_helper_neon_narrow_round_high_u8 }, | |
10770 | { gen_helper_neon_narrow_high_u16, | |
10771 | gen_helper_neon_narrow_round_high_u16 }, | |
7cb36e18 | 10772 | { tcg_gen_extrh_i64_i32, do_narrow_round_high_u32 }, |
e4b998d4 PM |
10773 | }; |
10774 | NeonGenNarrowFn *gennarrow = narrowfns[size][is_u]; | |
10775 | ||
10776 | read_vec_element(s, tcg_op1, rn, pass, MO_64); | |
10777 | read_vec_element(s, tcg_op2, rm, pass, MO_64); | |
10778 | ||
10779 | gen_neon_addl(size, (opcode == 6), tcg_wideres, tcg_op1, tcg_op2); | |
10780 | ||
10781 | tcg_temp_free_i64(tcg_op1); | |
10782 | tcg_temp_free_i64(tcg_op2); | |
10783 | ||
10784 | tcg_res[pass] = tcg_temp_new_i32(); | |
10785 | gennarrow(tcg_res[pass], tcg_wideres); | |
10786 | tcg_temp_free_i64(tcg_wideres); | |
10787 | } | |
10788 | ||
10789 | for (pass = 0; pass < 2; pass++) { | |
10790 | write_vec_element_i32(s, tcg_res[pass], rd, pass + part, MO_32); | |
10791 | tcg_temp_free_i32(tcg_res[pass]); | |
10792 | } | |
4ff55bcb | 10793 | clear_vec_high(s, is_q, rd); |
e4b998d4 PM |
10794 | } |
10795 | ||
4ce31af4 | 10796 | /* AdvSIMD three different |
384b26fb AB |
10797 | * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0 |
10798 | * +---+---+---+-----------+------+---+------+--------+-----+------+------+ | |
10799 | * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd | | |
10800 | * +---+---+---+-----------+------+---+------+--------+-----+------+------+ | |
10801 | */ | |
10802 | static void disas_simd_three_reg_diff(DisasContext *s, uint32_t insn) | |
10803 | { | |
a08582f4 PM |
10804 | /* Instructions in this group fall into three basic classes |
10805 | * (in each case with the operation working on each element in | |
10806 | * the input vectors): | |
10807 | * (1) widening 64 x 64 -> 128 (with possibly Vd as an extra | |
10808 | * 128 bit input) | |
10809 | * (2) wide 64 x 128 -> 128 | |
10810 | * (3) narrowing 128 x 128 -> 64 | |
10811 | * Here we do initial decode, catch unallocated cases and | |
10812 | * dispatch to separate functions for each class. | |
10813 | */ | |
10814 | int is_q = extract32(insn, 30, 1); | |
10815 | int is_u = extract32(insn, 29, 1); | |
10816 | int size = extract32(insn, 22, 2); | |
10817 | int opcode = extract32(insn, 12, 4); | |
10818 | int rm = extract32(insn, 16, 5); | |
10819 | int rn = extract32(insn, 5, 5); | |
10820 | int rd = extract32(insn, 0, 5); | |
10821 | ||
10822 | switch (opcode) { | |
10823 | case 1: /* SADDW, SADDW2, UADDW, UADDW2 */ | |
10824 | case 3: /* SSUBW, SSUBW2, USUBW, USUBW2 */ | |
10825 | /* 64 x 128 -> 128 */ | |
dfc15c7c PM |
10826 | if (size == 3) { |
10827 | unallocated_encoding(s); | |
10828 | return; | |
10829 | } | |
8c6afa6a PM |
10830 | if (!fp_access_check(s)) { |
10831 | return; | |
10832 | } | |
dfc15c7c | 10833 | handle_3rd_wide(s, is_q, is_u, size, opcode, rd, rn, rm); |
a08582f4 PM |
10834 | break; |
10835 | case 4: /* ADDHN, ADDHN2, RADDHN, RADDHN2 */ | |
10836 | case 6: /* SUBHN, SUBHN2, RSUBHN, RSUBHN2 */ | |
10837 | /* 128 x 128 -> 64 */ | |
e4b998d4 PM |
10838 | if (size == 3) { |
10839 | unallocated_encoding(s); | |
10840 | return; | |
10841 | } | |
8c6afa6a PM |
10842 | if (!fp_access_check(s)) { |
10843 | return; | |
10844 | } | |
e4b998d4 | 10845 | handle_3rd_narrowing(s, is_q, is_u, size, opcode, rd, rn, rm); |
a08582f4 | 10846 | break; |
70d7f984 | 10847 | case 14: /* PMULL, PMULL2 */ |
e7e96fc5 | 10848 | if (is_u) { |
70d7f984 PM |
10849 | unallocated_encoding(s); |
10850 | return; | |
10851 | } | |
e7e96fc5 RH |
10852 | switch (size) { |
10853 | case 0: /* PMULL.P8 */ | |
10854 | if (!fp_access_check(s)) { | |
10855 | return; | |
10856 | } | |
10857 | /* The Q field specifies lo/hi half input for this insn. */ | |
10858 | gen_gvec_op3_ool(s, true, rd, rn, rm, is_q, | |
10859 | gen_helper_neon_pmull_h); | |
10860 | break; | |
10861 | ||
10862 | case 3: /* PMULL.P64 */ | |
962fcbf2 | 10863 | if (!dc_isar_feature(aa64_pmull, s)) { |
a984e42c PM |
10864 | unallocated_encoding(s); |
10865 | return; | |
10866 | } | |
8c6afa6a PM |
10867 | if (!fp_access_check(s)) { |
10868 | return; | |
10869 | } | |
b9ed510e RH |
10870 | /* The Q field specifies lo/hi half input for this insn. */ |
10871 | gen_gvec_op3_ool(s, true, rd, rn, rm, is_q, | |
10872 | gen_helper_gvec_pmull_q); | |
e7e96fc5 RH |
10873 | break; |
10874 | ||
10875 | default: | |
10876 | unallocated_encoding(s); | |
10877 | break; | |
a984e42c | 10878 | } |
e7e96fc5 | 10879 | return; |
13caf1fd PM |
10880 | case 9: /* SQDMLAL, SQDMLAL2 */ |
10881 | case 11: /* SQDMLSL, SQDMLSL2 */ | |
10882 | case 13: /* SQDMULL, SQDMULL2 */ | |
70d7f984 | 10883 | if (is_u || size == 0) { |
a08582f4 PM |
10884 | unallocated_encoding(s); |
10885 | return; | |
10886 | } | |
10887 | /* fall through */ | |
13caf1fd PM |
10888 | case 0: /* SADDL, SADDL2, UADDL, UADDL2 */ |
10889 | case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */ | |
13caf1fd PM |
10890 | case 5: /* SABAL, SABAL2, UABAL, UABAL2 */ |
10891 | case 7: /* SABDL, SABDL2, UABDL, UABDL2 */ | |
10892 | case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */ | |
10893 | case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */ | |
10894 | case 12: /* SMULL, SMULL2, UMULL, UMULL2 */ | |
a08582f4 PM |
10895 | /* 64 x 64 -> 128 */ |
10896 | if (size == 3) { | |
10897 | unallocated_encoding(s); | |
10898 | return; | |
10899 | } | |
8c6afa6a PM |
10900 | if (!fp_access_check(s)) { |
10901 | return; | |
10902 | } | |
10903 | ||
a08582f4 PM |
10904 | handle_3rd_widening(s, is_q, is_u, size, opcode, rd, rn, rm); |
10905 | break; | |
10906 | default: | |
10907 | /* opcode 15 not allocated */ | |
10908 | unallocated_encoding(s); | |
10909 | break; | |
10910 | } | |
384b26fb AB |
10911 | } |
10912 | ||
e1cea114 PM |
10913 | /* Logic op (opcode == 3) subgroup of C3.6.16. */ |
10914 | static void disas_simd_3same_logic(DisasContext *s, uint32_t insn) | |
10915 | { | |
956d272e PM |
10916 | int rd = extract32(insn, 0, 5); |
10917 | int rn = extract32(insn, 5, 5); | |
10918 | int rm = extract32(insn, 16, 5); | |
10919 | int size = extract32(insn, 22, 2); | |
10920 | bool is_u = extract32(insn, 29, 1); | |
10921 | bool is_q = extract32(insn, 30, 1); | |
956d272e | 10922 | |
8c6afa6a PM |
10923 | if (!fp_access_check(s)) { |
10924 | return; | |
10925 | } | |
10926 | ||
bc48092f RH |
10927 | switch (size + 4 * is_u) { |
10928 | case 0: /* AND */ | |
10929 | gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_and, 0); | |
10930 | return; | |
10931 | case 1: /* BIC */ | |
10932 | gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_andc, 0); | |
10933 | return; | |
10934 | case 2: /* ORR */ | |
2900847f | 10935 | gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_or, 0); |
bc48092f RH |
10936 | return; |
10937 | case 3: /* ORN */ | |
10938 | gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_orc, 0); | |
10939 | return; | |
10940 | case 4: /* EOR */ | |
10941 | gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_xor, 0); | |
10942 | return; | |
956d272e | 10943 | |
bc48092f | 10944 | case 5: /* BSL bitwise select */ |
3a7a2b4e | 10945 | gen_gvec_fn4(s, is_q, rd, rd, rn, rm, tcg_gen_gvec_bitsel, 0); |
bc48092f RH |
10946 | return; |
10947 | case 6: /* BIT, bitwise insert if true */ | |
3a7a2b4e | 10948 | gen_gvec_fn4(s, is_q, rd, rm, rn, rd, tcg_gen_gvec_bitsel, 0); |
bc48092f RH |
10949 | return; |
10950 | case 7: /* BIF, bitwise insert if false */ | |
3a7a2b4e | 10951 | gen_gvec_fn4(s, is_q, rd, rm, rd, rn, tcg_gen_gvec_bitsel, 0); |
bc48092f | 10952 | return; |
956d272e | 10953 | |
bc48092f RH |
10954 | default: |
10955 | g_assert_not_reached(); | |
956d272e | 10956 | } |
e1cea114 PM |
10957 | } |
10958 | ||
bc242f9b AB |
10959 | /* Pairwise op subgroup of C3.6.16. |
10960 | * | |
10961 | * This is called directly or via the handle_3same_float for float pairwise | |
10962 | * operations where the opcode and size are calculated differently. | |
10963 | */ | |
10964 | static void handle_simd_3same_pair(DisasContext *s, int is_q, int u, int opcode, | |
10965 | int size, int rn, int rm, int rd) | |
e1cea114 | 10966 | { |
bc242f9b | 10967 | TCGv_ptr fpst; |
0173a005 PM |
10968 | int pass; |
10969 | ||
bc242f9b AB |
10970 | /* Floating point operations need fpst */ |
10971 | if (opcode >= 0x58) { | |
d81ce0ef | 10972 | fpst = get_fpstatus_ptr(false); |
bc242f9b | 10973 | } else { |
f764718d | 10974 | fpst = NULL; |
0173a005 PM |
10975 | } |
10976 | ||
8c6afa6a PM |
10977 | if (!fp_access_check(s)) { |
10978 | return; | |
10979 | } | |
10980 | ||
0173a005 PM |
10981 | /* These operations work on the concatenated rm:rn, with each pair of |
10982 | * adjacent elements being operated on to produce an element in the result. | |
10983 | */ | |
10984 | if (size == 3) { | |
10985 | TCGv_i64 tcg_res[2]; | |
10986 | ||
10987 | for (pass = 0; pass < 2; pass++) { | |
10988 | TCGv_i64 tcg_op1 = tcg_temp_new_i64(); | |
10989 | TCGv_i64 tcg_op2 = tcg_temp_new_i64(); | |
10990 | int passreg = (pass == 0) ? rn : rm; | |
10991 | ||
10992 | read_vec_element(s, tcg_op1, passreg, 0, MO_64); | |
10993 | read_vec_element(s, tcg_op2, passreg, 1, MO_64); | |
10994 | tcg_res[pass] = tcg_temp_new_i64(); | |
10995 | ||
bc242f9b AB |
10996 | switch (opcode) { |
10997 | case 0x17: /* ADDP */ | |
10998 | tcg_gen_add_i64(tcg_res[pass], tcg_op1, tcg_op2); | |
10999 | break; | |
11000 | case 0x58: /* FMAXNMP */ | |
11001 | gen_helper_vfp_maxnumd(tcg_res[pass], tcg_op1, tcg_op2, fpst); | |
11002 | break; | |
11003 | case 0x5a: /* FADDP */ | |
11004 | gen_helper_vfp_addd(tcg_res[pass], tcg_op1, tcg_op2, fpst); | |
11005 | break; | |
11006 | case 0x5e: /* FMAXP */ | |
11007 | gen_helper_vfp_maxd(tcg_res[pass], tcg_op1, tcg_op2, fpst); | |
11008 | break; | |
11009 | case 0x78: /* FMINNMP */ | |
11010 | gen_helper_vfp_minnumd(tcg_res[pass], tcg_op1, tcg_op2, fpst); | |
11011 | break; | |
11012 | case 0x7e: /* FMINP */ | |
11013 | gen_helper_vfp_mind(tcg_res[pass], tcg_op1, tcg_op2, fpst); | |
11014 | break; | |
11015 | default: | |
11016 | g_assert_not_reached(); | |
11017 | } | |
0173a005 PM |
11018 | |
11019 | tcg_temp_free_i64(tcg_op1); | |
11020 | tcg_temp_free_i64(tcg_op2); | |
11021 | } | |
11022 | ||
11023 | for (pass = 0; pass < 2; pass++) { | |
11024 | write_vec_element(s, tcg_res[pass], rd, pass, MO_64); | |
11025 | tcg_temp_free_i64(tcg_res[pass]); | |
11026 | } | |
11027 | } else { | |
11028 | int maxpass = is_q ? 4 : 2; | |
11029 | TCGv_i32 tcg_res[4]; | |
11030 | ||
11031 | for (pass = 0; pass < maxpass; pass++) { | |
11032 | TCGv_i32 tcg_op1 = tcg_temp_new_i32(); | |
11033 | TCGv_i32 tcg_op2 = tcg_temp_new_i32(); | |
bc242f9b | 11034 | NeonGenTwoOpFn *genfn = NULL; |
0173a005 PM |
11035 | int passreg = pass < (maxpass / 2) ? rn : rm; |
11036 | int passelt = (is_q && (pass & 1)) ? 2 : 0; | |
11037 | ||
11038 | read_vec_element_i32(s, tcg_op1, passreg, passelt, MO_32); | |
11039 | read_vec_element_i32(s, tcg_op2, passreg, passelt + 1, MO_32); | |
11040 | tcg_res[pass] = tcg_temp_new_i32(); | |
11041 | ||
11042 | switch (opcode) { | |
11043 | case 0x17: /* ADDP */ | |
11044 | { | |
11045 | static NeonGenTwoOpFn * const fns[3] = { | |
11046 | gen_helper_neon_padd_u8, | |
11047 | gen_helper_neon_padd_u16, | |
11048 | tcg_gen_add_i32, | |
11049 | }; | |
11050 | genfn = fns[size]; | |
11051 | break; | |
11052 | } | |
11053 | case 0x14: /* SMAXP, UMAXP */ | |
11054 | { | |
11055 | static NeonGenTwoOpFn * const fns[3][2] = { | |
11056 | { gen_helper_neon_pmax_s8, gen_helper_neon_pmax_u8 }, | |
11057 | { gen_helper_neon_pmax_s16, gen_helper_neon_pmax_u16 }, | |
ecb8ab8d | 11058 | { tcg_gen_smax_i32, tcg_gen_umax_i32 }, |
0173a005 PM |
11059 | }; |
11060 | genfn = fns[size][u]; | |
11061 | break; | |
11062 | } | |
11063 | case 0x15: /* SMINP, UMINP */ | |
11064 | { | |
11065 | static NeonGenTwoOpFn * const fns[3][2] = { | |
11066 | { gen_helper_neon_pmin_s8, gen_helper_neon_pmin_u8 }, | |
11067 | { gen_helper_neon_pmin_s16, gen_helper_neon_pmin_u16 }, | |
ecb8ab8d | 11068 | { tcg_gen_smin_i32, tcg_gen_umin_i32 }, |
0173a005 PM |
11069 | }; |
11070 | genfn = fns[size][u]; | |
11071 | break; | |
11072 | } | |
bc242f9b AB |
11073 | /* The FP operations are all on single floats (32 bit) */ |
11074 | case 0x58: /* FMAXNMP */ | |
11075 | gen_helper_vfp_maxnums(tcg_res[pass], tcg_op1, tcg_op2, fpst); | |
11076 | break; | |
11077 | case 0x5a: /* FADDP */ | |
11078 | gen_helper_vfp_adds(tcg_res[pass], tcg_op1, tcg_op2, fpst); | |
11079 | break; | |
11080 | case 0x5e: /* FMAXP */ | |
11081 | gen_helper_vfp_maxs(tcg_res[pass], tcg_op1, tcg_op2, fpst); | |
11082 | break; | |
11083 | case 0x78: /* FMINNMP */ | |
11084 | gen_helper_vfp_minnums(tcg_res[pass], tcg_op1, tcg_op2, fpst); | |
11085 | break; | |
11086 | case 0x7e: /* FMINP */ | |
11087 | gen_helper_vfp_mins(tcg_res[pass], tcg_op1, tcg_op2, fpst); | |
11088 | break; | |
0173a005 PM |
11089 | default: |
11090 | g_assert_not_reached(); | |
11091 | } | |
11092 | ||
bc242f9b AB |
11093 | /* FP ops called directly, otherwise call now */ |
11094 | if (genfn) { | |
11095 | genfn(tcg_res[pass], tcg_op1, tcg_op2); | |
11096 | } | |
0173a005 PM |
11097 | |
11098 | tcg_temp_free_i32(tcg_op1); | |
11099 | tcg_temp_free_i32(tcg_op2); | |
11100 | } | |
11101 | ||
11102 | for (pass = 0; pass < maxpass; pass++) { | |
11103 | write_vec_element_i32(s, tcg_res[pass], rd, pass, MO_32); | |
11104 | tcg_temp_free_i32(tcg_res[pass]); | |
11105 | } | |
4ff55bcb | 11106 | clear_vec_high(s, is_q, rd); |
0173a005 | 11107 | } |
bc242f9b | 11108 | |
f764718d | 11109 | if (fpst) { |
bc242f9b AB |
11110 | tcg_temp_free_ptr(fpst); |
11111 | } | |
e1cea114 PM |
11112 | } |
11113 | ||
11114 | /* Floating point op subgroup of C3.6.16. */ | |
11115 | static void disas_simd_3same_float(DisasContext *s, uint32_t insn) | |
11116 | { | |
845ea09a PM |
11117 | /* For floating point ops, the U, size[1] and opcode bits |
11118 | * together indicate the operation. size[0] indicates single | |
11119 | * or double. | |
11120 | */ | |
11121 | int fpopcode = extract32(insn, 11, 5) | |
11122 | | (extract32(insn, 23, 1) << 5) | |
11123 | | (extract32(insn, 29, 1) << 6); | |
11124 | int is_q = extract32(insn, 30, 1); | |
11125 | int size = extract32(insn, 22, 1); | |
11126 | int rm = extract32(insn, 16, 5); | |
11127 | int rn = extract32(insn, 5, 5); | |
11128 | int rd = extract32(insn, 0, 5); | |
11129 | ||
11130 | int datasize = is_q ? 128 : 64; | |
11131 | int esize = 32 << size; | |
11132 | int elements = datasize / esize; | |
11133 | ||
11134 | if (size == 1 && !is_q) { | |
11135 | unallocated_encoding(s); | |
11136 | return; | |
11137 | } | |
11138 | ||
11139 | switch (fpopcode) { | |
11140 | case 0x58: /* FMAXNMP */ | |
11141 | case 0x5a: /* FADDP */ | |
11142 | case 0x5e: /* FMAXP */ | |
11143 | case 0x78: /* FMINNMP */ | |
11144 | case 0x7e: /* FMINP */ | |
bc242f9b AB |
11145 | if (size && !is_q) { |
11146 | unallocated_encoding(s); | |
11147 | return; | |
11148 | } | |
11149 | handle_simd_3same_pair(s, is_q, 0, fpopcode, size ? MO_64 : MO_32, | |
11150 | rn, rm, rd); | |
845ea09a PM |
11151 | return; |
11152 | case 0x1b: /* FMULX */ | |
845ea09a PM |
11153 | case 0x1f: /* FRECPS */ |
11154 | case 0x3f: /* FRSQRTS */ | |
845ea09a | 11155 | case 0x5d: /* FACGE */ |
845ea09a PM |
11156 | case 0x7d: /* FACGT */ |
11157 | case 0x19: /* FMLA */ | |
11158 | case 0x39: /* FMLS */ | |
845ea09a PM |
11159 | case 0x18: /* FMAXNM */ |
11160 | case 0x1a: /* FADD */ | |
8908f4d1 | 11161 | case 0x1c: /* FCMEQ */ |
845ea09a PM |
11162 | case 0x1e: /* FMAX */ |
11163 | case 0x38: /* FMINNM */ | |
11164 | case 0x3a: /* FSUB */ | |
11165 | case 0x3e: /* FMIN */ | |
11166 | case 0x5b: /* FMUL */ | |
8908f4d1 | 11167 | case 0x5c: /* FCMGE */ |
845ea09a PM |
11168 | case 0x5f: /* FDIV */ |
11169 | case 0x7a: /* FABD */ | |
8908f4d1 | 11170 | case 0x7c: /* FCMGT */ |
8c6afa6a PM |
11171 | if (!fp_access_check(s)) { |
11172 | return; | |
11173 | } | |
845ea09a PM |
11174 | handle_3same_float(s, size, elements, fpopcode, rd, rn, rm); |
11175 | return; | |
0caa5af8 RH |
11176 | |
11177 | case 0x1d: /* FMLAL */ | |
11178 | case 0x3d: /* FMLSL */ | |
11179 | case 0x59: /* FMLAL2 */ | |
11180 | case 0x79: /* FMLSL2 */ | |
11181 | if (size & 1 || !dc_isar_feature(aa64_fhm, s)) { | |
11182 | unallocated_encoding(s); | |
11183 | return; | |
11184 | } | |
11185 | if (fp_access_check(s)) { | |
11186 | int is_s = extract32(insn, 23, 1); | |
11187 | int is_2 = extract32(insn, 29, 1); | |
11188 | int data = (is_2 << 1) | is_s; | |
11189 | tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd), | |
11190 | vec_full_reg_offset(s, rn), | |
11191 | vec_full_reg_offset(s, rm), cpu_env, | |
11192 | is_q ? 16 : 8, vec_full_reg_size(s), | |
11193 | data, gen_helper_gvec_fmlal_a64); | |
11194 | } | |
11195 | return; | |
11196 | ||
845ea09a PM |
11197 | default: |
11198 | unallocated_encoding(s); | |
11199 | return; | |
11200 | } | |
e1cea114 PM |
11201 | } |
11202 | ||
11203 | /* Integer op subgroup of C3.6.16. */ | |
11204 | static void disas_simd_3same_int(DisasContext *s, uint32_t insn) | |
11205 | { | |
1f8a73af PM |
11206 | int is_q = extract32(insn, 30, 1); |
11207 | int u = extract32(insn, 29, 1); | |
11208 | int size = extract32(insn, 22, 2); | |
11209 | int opcode = extract32(insn, 11, 5); | |
11210 | int rm = extract32(insn, 16, 5); | |
11211 | int rn = extract32(insn, 5, 5); | |
11212 | int rd = extract32(insn, 0, 5); | |
11213 | int pass; | |
79d61de6 | 11214 | TCGCond cond; |
1f8a73af PM |
11215 | |
11216 | switch (opcode) { | |
11217 | case 0x13: /* MUL, PMUL */ | |
11218 | if (u && size != 0) { | |
11219 | unallocated_encoding(s); | |
11220 | return; | |
11221 | } | |
11222 | /* fall through */ | |
11223 | case 0x0: /* SHADD, UHADD */ | |
11224 | case 0x2: /* SRHADD, URHADD */ | |
11225 | case 0x4: /* SHSUB, UHSUB */ | |
11226 | case 0xc: /* SMAX, UMAX */ | |
11227 | case 0xd: /* SMIN, UMIN */ | |
11228 | case 0xe: /* SABD, UABD */ | |
11229 | case 0xf: /* SABA, UABA */ | |
11230 | case 0x12: /* MLA, MLS */ | |
11231 | if (size == 3) { | |
11232 | unallocated_encoding(s); | |
11233 | return; | |
11234 | } | |
8b12a0cf | 11235 | break; |
1f8a73af PM |
11236 | case 0x16: /* SQDMULH, SQRDMULH */ |
11237 | if (size == 0 || size == 3) { | |
11238 | unallocated_encoding(s); | |
11239 | return; | |
11240 | } | |
8b12a0cf | 11241 | break; |
1f8a73af PM |
11242 | default: |
11243 | if (size == 3 && !is_q) { | |
11244 | unallocated_encoding(s); | |
11245 | return; | |
11246 | } | |
11247 | break; | |
11248 | } | |
11249 | ||
8c6afa6a PM |
11250 | if (!fp_access_check(s)) { |
11251 | return; | |
11252 | } | |
11253 | ||
bc48092f | 11254 | switch (opcode) { |
89e68b57 | 11255 | case 0x01: /* SQADD, UQADD */ |
c7715b6b RH |
11256 | if (u) { |
11257 | gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_uqadd_qc, size); | |
11258 | } else { | |
11259 | gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_sqadd_qc, size); | |
11260 | } | |
89e68b57 RH |
11261 | return; |
11262 | case 0x05: /* SQSUB, UQSUB */ | |
c7715b6b RH |
11263 | if (u) { |
11264 | gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_uqsub_qc, size); | |
11265 | } else { | |
11266 | gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_sqsub_qc, size); | |
11267 | } | |
89e68b57 | 11268 | return; |
87b74e8b | 11269 | case 0x08: /* SSHL, USHL */ |
8161b753 RH |
11270 | if (u) { |
11271 | gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_ushl, size); | |
11272 | } else { | |
11273 | gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_sshl, size); | |
11274 | } | |
87b74e8b | 11275 | return; |
264d2a48 RH |
11276 | case 0x0c: /* SMAX, UMAX */ |
11277 | if (u) { | |
11278 | gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_umax, size); | |
11279 | } else { | |
11280 | gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_smax, size); | |
11281 | } | |
11282 | return; | |
11283 | case 0x0d: /* SMIN, UMIN */ | |
11284 | if (u) { | |
11285 | gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_umin, size); | |
11286 | } else { | |
11287 | gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_smin, size); | |
11288 | } | |
11289 | return; | |
50c160d4 RH |
11290 | case 0xe: /* SABD, UABD */ |
11291 | if (u) { | |
11292 | gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_uabd, size); | |
11293 | } else { | |
11294 | gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_sabd, size); | |
11295 | } | |
11296 | return; | |
cfdb2c0c RH |
11297 | case 0xf: /* SABA, UABA */ |
11298 | if (u) { | |
11299 | gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_uaba, size); | |
11300 | } else { | |
11301 | gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_saba, size); | |
11302 | } | |
11303 | return; | |
bc48092f RH |
11304 | case 0x10: /* ADD, SUB */ |
11305 | if (u) { | |
11306 | gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_sub, size); | |
11307 | } else { | |
11308 | gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_add, size); | |
11309 | } | |
11310 | return; | |
0c7c55c4 RH |
11311 | case 0x13: /* MUL, PMUL */ |
11312 | if (!u) { /* MUL */ | |
11313 | gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_mul, size); | |
a21bb78e RH |
11314 | } else { /* PMUL */ |
11315 | gen_gvec_op3_ool(s, is_q, rd, rn, rm, 0, gen_helper_gvec_pmul_b); | |
0c7c55c4 | 11316 | } |
a21bb78e | 11317 | return; |
0c7c55c4 RH |
11318 | case 0x12: /* MLA, MLS */ |
11319 | if (u) { | |
27106320 | 11320 | gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_mls, size); |
0c7c55c4 | 11321 | } else { |
27106320 | 11322 | gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_mla, size); |
0c7c55c4 RH |
11323 | } |
11324 | return; | |
79d61de6 RH |
11325 | case 0x11: |
11326 | if (!u) { /* CMTST */ | |
8161b753 | 11327 | gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_cmtst, size); |
79d61de6 RH |
11328 | return; |
11329 | } | |
11330 | /* else CMEQ */ | |
11331 | cond = TCG_COND_EQ; | |
11332 | goto do_gvec_cmp; | |
11333 | case 0x06: /* CMGT, CMHI */ | |
11334 | cond = u ? TCG_COND_GTU : TCG_COND_GT; | |
11335 | goto do_gvec_cmp; | |
11336 | case 0x07: /* CMGE, CMHS */ | |
11337 | cond = u ? TCG_COND_GEU : TCG_COND_GE; | |
11338 | do_gvec_cmp: | |
11339 | tcg_gen_gvec_cmp(cond, size, vec_full_reg_offset(s, rd), | |
11340 | vec_full_reg_offset(s, rn), | |
11341 | vec_full_reg_offset(s, rm), | |
11342 | is_q ? 16 : 8, vec_full_reg_size(s)); | |
11343 | return; | |
bc48092f RH |
11344 | } |
11345 | ||
1f8a73af | 11346 | if (size == 3) { |
220ad4ca PM |
11347 | assert(is_q); |
11348 | for (pass = 0; pass < 2; pass++) { | |
1f8a73af PM |
11349 | TCGv_i64 tcg_op1 = tcg_temp_new_i64(); |
11350 | TCGv_i64 tcg_op2 = tcg_temp_new_i64(); | |
11351 | TCGv_i64 tcg_res = tcg_temp_new_i64(); | |
11352 | ||
11353 | read_vec_element(s, tcg_op1, rn, pass, MO_64); | |
11354 | read_vec_element(s, tcg_op2, rm, pass, MO_64); | |
11355 | ||
11356 | handle_3same_64(s, opcode, u, tcg_res, tcg_op1, tcg_op2); | |
11357 | ||
11358 | write_vec_element(s, tcg_res, rd, pass, MO_64); | |
11359 | ||
11360 | tcg_temp_free_i64(tcg_res); | |
11361 | tcg_temp_free_i64(tcg_op1); | |
11362 | tcg_temp_free_i64(tcg_op2); | |
11363 | } | |
11364 | } else { | |
11365 | for (pass = 0; pass < (is_q ? 4 : 2); pass++) { | |
11366 | TCGv_i32 tcg_op1 = tcg_temp_new_i32(); | |
11367 | TCGv_i32 tcg_op2 = tcg_temp_new_i32(); | |
11368 | TCGv_i32 tcg_res = tcg_temp_new_i32(); | |
6d9571f7 PM |
11369 | NeonGenTwoOpFn *genfn = NULL; |
11370 | NeonGenTwoOpEnvFn *genenvfn = NULL; | |
1f8a73af PM |
11371 | |
11372 | read_vec_element_i32(s, tcg_op1, rn, pass, MO_32); | |
11373 | read_vec_element_i32(s, tcg_op2, rm, pass, MO_32); | |
11374 | ||
11375 | switch (opcode) { | |
8b12a0cf PM |
11376 | case 0x0: /* SHADD, UHADD */ |
11377 | { | |
11378 | static NeonGenTwoOpFn * const fns[3][2] = { | |
11379 | { gen_helper_neon_hadd_s8, gen_helper_neon_hadd_u8 }, | |
11380 | { gen_helper_neon_hadd_s16, gen_helper_neon_hadd_u16 }, | |
11381 | { gen_helper_neon_hadd_s32, gen_helper_neon_hadd_u32 }, | |
11382 | }; | |
11383 | genfn = fns[size][u]; | |
11384 | break; | |
11385 | } | |
8b12a0cf PM |
11386 | case 0x2: /* SRHADD, URHADD */ |
11387 | { | |
11388 | static NeonGenTwoOpFn * const fns[3][2] = { | |
11389 | { gen_helper_neon_rhadd_s8, gen_helper_neon_rhadd_u8 }, | |
11390 | { gen_helper_neon_rhadd_s16, gen_helper_neon_rhadd_u16 }, | |
11391 | { gen_helper_neon_rhadd_s32, gen_helper_neon_rhadd_u32 }, | |
11392 | }; | |
11393 | genfn = fns[size][u]; | |
11394 | break; | |
11395 | } | |
11396 | case 0x4: /* SHSUB, UHSUB */ | |
11397 | { | |
11398 | static NeonGenTwoOpFn * const fns[3][2] = { | |
11399 | { gen_helper_neon_hsub_s8, gen_helper_neon_hsub_u8 }, | |
11400 | { gen_helper_neon_hsub_s16, gen_helper_neon_hsub_u16 }, | |
11401 | { gen_helper_neon_hsub_s32, gen_helper_neon_hsub_u32 }, | |
11402 | }; | |
11403 | genfn = fns[size][u]; | |
11404 | break; | |
11405 | } | |
6d9571f7 PM |
11406 | case 0x9: /* SQSHL, UQSHL */ |
11407 | { | |
11408 | static NeonGenTwoOpEnvFn * const fns[3][2] = { | |
11409 | { gen_helper_neon_qshl_s8, gen_helper_neon_qshl_u8 }, | |
11410 | { gen_helper_neon_qshl_s16, gen_helper_neon_qshl_u16 }, | |
11411 | { gen_helper_neon_qshl_s32, gen_helper_neon_qshl_u32 }, | |
11412 | }; | |
11413 | genenvfn = fns[size][u]; | |
11414 | break; | |
11415 | } | |
11416 | case 0xa: /* SRSHL, URSHL */ | |
11417 | { | |
11418 | static NeonGenTwoOpFn * const fns[3][2] = { | |
11419 | { gen_helper_neon_rshl_s8, gen_helper_neon_rshl_u8 }, | |
11420 | { gen_helper_neon_rshl_s16, gen_helper_neon_rshl_u16 }, | |
11421 | { gen_helper_neon_rshl_s32, gen_helper_neon_rshl_u32 }, | |
11422 | }; | |
11423 | genfn = fns[size][u]; | |
11424 | break; | |
11425 | } | |
11426 | case 0xb: /* SQRSHL, UQRSHL */ | |
11427 | { | |
11428 | static NeonGenTwoOpEnvFn * const fns[3][2] = { | |
11429 | { gen_helper_neon_qrshl_s8, gen_helper_neon_qrshl_u8 }, | |
11430 | { gen_helper_neon_qrshl_s16, gen_helper_neon_qrshl_u16 }, | |
11431 | { gen_helper_neon_qrshl_s32, gen_helper_neon_qrshl_u32 }, | |
11432 | }; | |
11433 | genenvfn = fns[size][u]; | |
11434 | break; | |
11435 | } | |
8b12a0cf PM |
11436 | case 0x16: /* SQDMULH, SQRDMULH */ |
11437 | { | |
11438 | static NeonGenTwoOpEnvFn * const fns[2][2] = { | |
11439 | { gen_helper_neon_qdmulh_s16, gen_helper_neon_qrdmulh_s16 }, | |
11440 | { gen_helper_neon_qdmulh_s32, gen_helper_neon_qrdmulh_s32 }, | |
11441 | }; | |
11442 | assert(size == 1 || size == 2); | |
11443 | genenvfn = fns[size - 1][u]; | |
11444 | break; | |
11445 | } | |
1f8a73af PM |
11446 | default: |
11447 | g_assert_not_reached(); | |
11448 | } | |
11449 | ||
6d9571f7 PM |
11450 | if (genenvfn) { |
11451 | genenvfn(tcg_res, cpu_env, tcg_op1, tcg_op2); | |
11452 | } else { | |
11453 | genfn(tcg_res, tcg_op1, tcg_op2); | |
11454 | } | |
1f8a73af PM |
11455 | |
11456 | write_vec_element_i32(s, tcg_res, rd, pass, MO_32); | |
11457 | ||
11458 | tcg_temp_free_i32(tcg_res); | |
11459 | tcg_temp_free_i32(tcg_op1); | |
11460 | tcg_temp_free_i32(tcg_op2); | |
11461 | } | |
11462 | } | |
4ff55bcb | 11463 | clear_vec_high(s, is_q, rd); |
e1cea114 PM |
11464 | } |
11465 | ||
4ce31af4 | 11466 | /* AdvSIMD three same |
384b26fb AB |
11467 | * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0 |
11468 | * +---+---+---+-----------+------+---+------+--------+---+------+------+ | |
11469 | * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd | | |
11470 | * +---+---+---+-----------+------+---+------+--------+---+------+------+ | |
11471 | */ | |
11472 | static void disas_simd_three_reg_same(DisasContext *s, uint32_t insn) | |
11473 | { | |
e1cea114 PM |
11474 | int opcode = extract32(insn, 11, 5); |
11475 | ||
11476 | switch (opcode) { | |
11477 | case 0x3: /* logic ops */ | |
11478 | disas_simd_3same_logic(s, insn); | |
11479 | break; | |
11480 | case 0x17: /* ADDP */ | |
11481 | case 0x14: /* SMAXP, UMAXP */ | |
11482 | case 0x15: /* SMINP, UMINP */ | |
bc242f9b | 11483 | { |
e1cea114 | 11484 | /* Pairwise operations */ |
bc242f9b AB |
11485 | int is_q = extract32(insn, 30, 1); |
11486 | int u = extract32(insn, 29, 1); | |
11487 | int size = extract32(insn, 22, 2); | |
11488 | int rm = extract32(insn, 16, 5); | |
11489 | int rn = extract32(insn, 5, 5); | |
11490 | int rd = extract32(insn, 0, 5); | |
11491 | if (opcode == 0x17) { | |
11492 | if (u || (size == 3 && !is_q)) { | |
11493 | unallocated_encoding(s); | |
11494 | return; | |
11495 | } | |
11496 | } else { | |
11497 | if (size == 3) { | |
11498 | unallocated_encoding(s); | |
11499 | return; | |
11500 | } | |
11501 | } | |
11502 | handle_simd_3same_pair(s, is_q, u, opcode, size, rn, rm, rd); | |
e1cea114 | 11503 | break; |
bc242f9b | 11504 | } |
e1cea114 PM |
11505 | case 0x18 ... 0x31: |
11506 | /* floating point ops, sz[1] and U are part of opcode */ | |
11507 | disas_simd_3same_float(s, insn); | |
11508 | break; | |
11509 | default: | |
11510 | disas_simd_3same_int(s, insn); | |
11511 | break; | |
11512 | } | |
384b26fb AB |
11513 | } |
11514 | ||
376e8d6c AB |
11515 | /* |
11516 | * Advanced SIMD three same (ARMv8.2 FP16 variants) | |
11517 | * | |
11518 | * 31 30 29 28 24 23 22 21 20 16 15 14 13 11 10 9 5 4 0 | |
11519 | * +---+---+---+-----------+---------+------+-----+--------+---+------+------+ | |
11520 | * | 0 | Q | U | 0 1 1 1 0 | a | 1 0 | Rm | 0 0 | opcode | 1 | Rn | Rd | | |
11521 | * +---+---+---+-----------+---------+------+-----+--------+---+------+------+ | |
11522 | * | |
11523 | * This includes FMULX, FCMEQ (register), FRECPS, FRSQRTS, FCMGE | |
11524 | * (register), FACGE, FABD, FCMGT (register) and FACGT. | |
11525 | * | |
11526 | */ | |
11527 | static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn) | |
11528 | { | |
11529 | int opcode, fpopcode; | |
11530 | int is_q, u, a, rm, rn, rd; | |
11531 | int datasize, elements; | |
11532 | int pass; | |
11533 | TCGv_ptr fpst; | |
7a2c6e61 | 11534 | bool pairwise = false; |
376e8d6c | 11535 | |
5763190f | 11536 | if (!dc_isar_feature(aa64_fp16, s)) { |
376e8d6c AB |
11537 | unallocated_encoding(s); |
11538 | return; | |
11539 | } | |
11540 | ||
11541 | if (!fp_access_check(s)) { | |
11542 | return; | |
11543 | } | |
11544 | ||
11545 | /* For these floating point ops, the U, a and opcode bits | |
11546 | * together indicate the operation. | |
11547 | */ | |
11548 | opcode = extract32(insn, 11, 3); | |
11549 | u = extract32(insn, 29, 1); | |
11550 | a = extract32(insn, 23, 1); | |
11551 | is_q = extract32(insn, 30, 1); | |
11552 | rm = extract32(insn, 16, 5); | |
11553 | rn = extract32(insn, 5, 5); | |
11554 | rd = extract32(insn, 0, 5); | |
11555 | ||
11556 | fpopcode = opcode | (a << 3) | (u << 4); | |
11557 | datasize = is_q ? 128 : 64; | |
11558 | elements = datasize / 16; | |
11559 | ||
7a2c6e61 AB |
11560 | switch (fpopcode) { |
11561 | case 0x10: /* FMAXNMP */ | |
11562 | case 0x12: /* FADDP */ | |
11563 | case 0x16: /* FMAXP */ | |
11564 | case 0x18: /* FMINNMP */ | |
11565 | case 0x1e: /* FMINP */ | |
11566 | pairwise = true; | |
11567 | break; | |
11568 | } | |
11569 | ||
376e8d6c AB |
11570 | fpst = get_fpstatus_ptr(true); |
11571 | ||
7a2c6e61 AB |
11572 | if (pairwise) { |
11573 | int maxpass = is_q ? 8 : 4; | |
376e8d6c AB |
11574 | TCGv_i32 tcg_op1 = tcg_temp_new_i32(); |
11575 | TCGv_i32 tcg_op2 = tcg_temp_new_i32(); | |
7a2c6e61 | 11576 | TCGv_i32 tcg_res[8]; |
376e8d6c | 11577 | |
7a2c6e61 AB |
11578 | for (pass = 0; pass < maxpass; pass++) { |
11579 | int passreg = pass < (maxpass / 2) ? rn : rm; | |
11580 | int passelt = (pass << 1) & (maxpass - 1); | |
376e8d6c | 11581 | |
7a2c6e61 AB |
11582 | read_vec_element_i32(s, tcg_op1, passreg, passelt, MO_16); |
11583 | read_vec_element_i32(s, tcg_op2, passreg, passelt + 1, MO_16); | |
11584 | tcg_res[pass] = tcg_temp_new_i32(); | |
11585 | ||
11586 | switch (fpopcode) { | |
11587 | case 0x10: /* FMAXNMP */ | |
11588 | gen_helper_advsimd_maxnumh(tcg_res[pass], tcg_op1, tcg_op2, | |
11589 | fpst); | |
11590 | break; | |
11591 | case 0x12: /* FADDP */ | |
11592 | gen_helper_advsimd_addh(tcg_res[pass], tcg_op1, tcg_op2, fpst); | |
11593 | break; | |
11594 | case 0x16: /* FMAXP */ | |
11595 | gen_helper_advsimd_maxh(tcg_res[pass], tcg_op1, tcg_op2, fpst); | |
11596 | break; | |
11597 | case 0x18: /* FMINNMP */ | |
11598 | gen_helper_advsimd_minnumh(tcg_res[pass], tcg_op1, tcg_op2, | |
11599 | fpst); | |
11600 | break; | |
11601 | case 0x1e: /* FMINP */ | |
11602 | gen_helper_advsimd_minh(tcg_res[pass], tcg_op1, tcg_op2, fpst); | |
11603 | break; | |
11604 | default: | |
11605 | g_assert_not_reached(); | |
11606 | } | |
11607 | } | |
11608 | ||
11609 | for (pass = 0; pass < maxpass; pass++) { | |
11610 | write_vec_element_i32(s, tcg_res[pass], rd, pass, MO_16); | |
11611 | tcg_temp_free_i32(tcg_res[pass]); | |
376e8d6c AB |
11612 | } |
11613 | ||
376e8d6c AB |
11614 | tcg_temp_free_i32(tcg_op1); |
11615 | tcg_temp_free_i32(tcg_op2); | |
7a2c6e61 AB |
11616 | |
11617 | } else { | |
11618 | for (pass = 0; pass < elements; pass++) { | |
11619 | TCGv_i32 tcg_op1 = tcg_temp_new_i32(); | |
11620 | TCGv_i32 tcg_op2 = tcg_temp_new_i32(); | |
11621 | TCGv_i32 tcg_res = tcg_temp_new_i32(); | |
11622 | ||
11623 | read_vec_element_i32(s, tcg_op1, rn, pass, MO_16); | |
11624 | read_vec_element_i32(s, tcg_op2, rm, pass, MO_16); | |
11625 | ||
11626 | switch (fpopcode) { | |
11627 | case 0x0: /* FMAXNM */ | |
11628 | gen_helper_advsimd_maxnumh(tcg_res, tcg_op1, tcg_op2, fpst); | |
11629 | break; | |
11630 | case 0x1: /* FMLA */ | |
11631 | read_vec_element_i32(s, tcg_res, rd, pass, MO_16); | |
11632 | gen_helper_advsimd_muladdh(tcg_res, tcg_op1, tcg_op2, tcg_res, | |
11633 | fpst); | |
11634 | break; | |
11635 | case 0x2: /* FADD */ | |
11636 | gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst); | |
11637 | break; | |
11638 | case 0x3: /* FMULX */ | |
11639 | gen_helper_advsimd_mulxh(tcg_res, tcg_op1, tcg_op2, fpst); | |
11640 | break; | |
11641 | case 0x4: /* FCMEQ */ | |
11642 | gen_helper_advsimd_ceq_f16(tcg_res, tcg_op1, tcg_op2, fpst); | |
11643 | break; | |
11644 | case 0x6: /* FMAX */ | |
11645 | gen_helper_advsimd_maxh(tcg_res, tcg_op1, tcg_op2, fpst); | |
11646 | break; | |
11647 | case 0x7: /* FRECPS */ | |
11648 | gen_helper_recpsf_f16(tcg_res, tcg_op1, tcg_op2, fpst); | |
11649 | break; | |
11650 | case 0x8: /* FMINNM */ | |
11651 | gen_helper_advsimd_minnumh(tcg_res, tcg_op1, tcg_op2, fpst); | |
11652 | break; | |
11653 | case 0x9: /* FMLS */ | |
11654 | /* As usual for ARM, separate negation for fused multiply-add */ | |
11655 | tcg_gen_xori_i32(tcg_op1, tcg_op1, 0x8000); | |
11656 | read_vec_element_i32(s, tcg_res, rd, pass, MO_16); | |
11657 | gen_helper_advsimd_muladdh(tcg_res, tcg_op1, tcg_op2, tcg_res, | |
11658 | fpst); | |
11659 | break; | |
11660 | case 0xa: /* FSUB */ | |
11661 | gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst); | |
11662 | break; | |
11663 | case 0xe: /* FMIN */ | |
11664 | gen_helper_advsimd_minh(tcg_res, tcg_op1, tcg_op2, fpst); | |
11665 | break; | |
11666 | case 0xf: /* FRSQRTS */ | |
11667 | gen_helper_rsqrtsf_f16(tcg_res, tcg_op1, tcg_op2, fpst); | |
11668 | break; | |
11669 | case 0x13: /* FMUL */ | |
11670 | gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst); | |
11671 | break; | |
11672 | case 0x14: /* FCMGE */ | |
11673 | gen_helper_advsimd_cge_f16(tcg_res, tcg_op1, tcg_op2, fpst); | |
11674 | break; | |
11675 | case 0x15: /* FACGE */ | |
11676 | gen_helper_advsimd_acge_f16(tcg_res, tcg_op1, tcg_op2, fpst); | |
11677 | break; | |
11678 | case 0x17: /* FDIV */ | |
11679 | gen_helper_advsimd_divh(tcg_res, tcg_op1, tcg_op2, fpst); | |
11680 | break; | |
11681 | case 0x1a: /* FABD */ | |
11682 | gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst); | |
11683 | tcg_gen_andi_i32(tcg_res, tcg_res, 0x7fff); | |
11684 | break; | |
11685 | case 0x1c: /* FCMGT */ | |
11686 | gen_helper_advsimd_cgt_f16(tcg_res, tcg_op1, tcg_op2, fpst); | |
11687 | break; | |
11688 | case 0x1d: /* FACGT */ | |
11689 | gen_helper_advsimd_acgt_f16(tcg_res, tcg_op1, tcg_op2, fpst); | |
11690 | break; | |
11691 | default: | |
11692 | fprintf(stderr, "%s: insn %#04x, fpop %#2x @ %#" PRIx64 "\n", | |
43722a6d | 11693 | __func__, insn, fpopcode, s->pc_curr); |
7a2c6e61 AB |
11694 | g_assert_not_reached(); |
11695 | } | |
11696 | ||
11697 | write_vec_element_i32(s, tcg_res, rd, pass, MO_16); | |
11698 | tcg_temp_free_i32(tcg_res); | |
11699 | tcg_temp_free_i32(tcg_op1); | |
11700 | tcg_temp_free_i32(tcg_op2); | |
11701 | } | |
376e8d6c AB |
11702 | } |
11703 | ||
11704 | tcg_temp_free_ptr(fpst); | |
11705 | ||
11706 | clear_vec_high(s, is_q, rd); | |
11707 | } | |
11708 | ||
e7186d82 RH |
11709 | /* AdvSIMD three same extra |
11710 | * 31 30 29 28 24 23 22 21 20 16 15 14 11 10 9 5 4 0 | |
11711 | * +---+---+---+-----------+------+---+------+---+--------+---+----+----+ | |
11712 | * | 0 | Q | U | 0 1 1 1 0 | size | 0 | Rm | 1 | opcode | 1 | Rn | Rd | | |
11713 | * +---+---+---+-----------+------+---+------+---+--------+---+----+----+ | |
11714 | */ | |
11715 | static void disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn) | |
11716 | { | |
11717 | int rd = extract32(insn, 0, 5); | |
11718 | int rn = extract32(insn, 5, 5); | |
11719 | int opcode = extract32(insn, 11, 4); | |
11720 | int rm = extract32(insn, 16, 5); | |
11721 | int size = extract32(insn, 22, 2); | |
11722 | bool u = extract32(insn, 29, 1); | |
11723 | bool is_q = extract32(insn, 30, 1); | |
962fcbf2 RH |
11724 | bool feature; |
11725 | int rot; | |
e7186d82 RH |
11726 | |
11727 | switch (u * 16 + opcode) { | |
11728 | case 0x10: /* SQRDMLAH (vector) */ | |
11729 | case 0x11: /* SQRDMLSH (vector) */ | |
11730 | if (size != 1 && size != 2) { | |
11731 | unallocated_encoding(s); | |
11732 | return; | |
11733 | } | |
962fcbf2 | 11734 | feature = dc_isar_feature(aa64_rdm, s); |
e7186d82 | 11735 | break; |
26c470a7 RH |
11736 | case 0x02: /* SDOT (vector) */ |
11737 | case 0x12: /* UDOT (vector) */ | |
11738 | if (size != MO_32) { | |
11739 | unallocated_encoding(s); | |
11740 | return; | |
11741 | } | |
962fcbf2 | 11742 | feature = dc_isar_feature(aa64_dp, s); |
26c470a7 | 11743 | break; |
b8a4a96d RH |
11744 | case 0x18: /* FCMLA, #0 */ |
11745 | case 0x19: /* FCMLA, #90 */ | |
11746 | case 0x1a: /* FCMLA, #180 */ | |
11747 | case 0x1b: /* FCMLA, #270 */ | |
11748 | case 0x1c: /* FCADD, #90 */ | |
11749 | case 0x1e: /* FCADD, #270 */ | |
1695cd61 | 11750 | if (size == 0 |
5763190f | 11751 | || (size == 1 && !dc_isar_feature(aa64_fp16, s)) |
1695cd61 RH |
11752 | || (size == 3 && !is_q)) { |
11753 | unallocated_encoding(s); | |
11754 | return; | |
11755 | } | |
962fcbf2 | 11756 | feature = dc_isar_feature(aa64_fcma, s); |
1695cd61 | 11757 | break; |
e7186d82 RH |
11758 | default: |
11759 | unallocated_encoding(s); | |
11760 | return; | |
11761 | } | |
962fcbf2 | 11762 | if (!feature) { |
e7186d82 RH |
11763 | unallocated_encoding(s); |
11764 | return; | |
11765 | } | |
11766 | if (!fp_access_check(s)) { | |
11767 | return; | |
11768 | } | |
11769 | ||
11770 | switch (opcode) { | |
11771 | case 0x0: /* SQRDMLAH (vector) */ | |
146aa66c | 11772 | gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_sqrdmlah_qc, size); |
e7186d82 RH |
11773 | return; |
11774 | ||
11775 | case 0x1: /* SQRDMLSH (vector) */ | |
146aa66c | 11776 | gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_sqrdmlsh_qc, size); |
e7186d82 RH |
11777 | return; |
11778 | ||
26c470a7 RH |
11779 | case 0x2: /* SDOT / UDOT */ |
11780 | gen_gvec_op3_ool(s, is_q, rd, rn, rm, 0, | |
11781 | u ? gen_helper_gvec_udot_b : gen_helper_gvec_sdot_b); | |
11782 | return; | |
11783 | ||
d17b7cdc RH |
11784 | case 0x8: /* FCMLA, #0 */ |
11785 | case 0x9: /* FCMLA, #90 */ | |
11786 | case 0xa: /* FCMLA, #180 */ | |
11787 | case 0xb: /* FCMLA, #270 */ | |
11788 | rot = extract32(opcode, 0, 2); | |
11789 | switch (size) { | |
11790 | case 1: | |
11791 | gen_gvec_op3_fpst(s, is_q, rd, rn, rm, true, rot, | |
11792 | gen_helper_gvec_fcmlah); | |
11793 | break; | |
11794 | case 2: | |
11795 | gen_gvec_op3_fpst(s, is_q, rd, rn, rm, false, rot, | |
11796 | gen_helper_gvec_fcmlas); | |
11797 | break; | |
11798 | case 3: | |
11799 | gen_gvec_op3_fpst(s, is_q, rd, rn, rm, false, rot, | |
11800 | gen_helper_gvec_fcmlad); | |
11801 | break; | |
11802 | default: | |
11803 | g_assert_not_reached(); | |
11804 | } | |
11805 | return; | |
11806 | ||
1695cd61 RH |
11807 | case 0xc: /* FCADD, #90 */ |
11808 | case 0xe: /* FCADD, #270 */ | |
11809 | rot = extract32(opcode, 1, 1); | |
11810 | switch (size) { | |
11811 | case 1: | |
11812 | gen_gvec_op3_fpst(s, is_q, rd, rn, rm, size == 1, rot, | |
11813 | gen_helper_gvec_fcaddh); | |
11814 | break; | |
11815 | case 2: | |
11816 | gen_gvec_op3_fpst(s, is_q, rd, rn, rm, size == 1, rot, | |
11817 | gen_helper_gvec_fcadds); | |
11818 | break; | |
11819 | case 3: | |
11820 | gen_gvec_op3_fpst(s, is_q, rd, rn, rm, size == 1, rot, | |
11821 | gen_helper_gvec_fcaddd); | |
11822 | break; | |
11823 | default: | |
11824 | g_assert_not_reached(); | |
11825 | } | |
11826 | return; | |
11827 | ||
e7186d82 RH |
11828 | default: |
11829 | g_assert_not_reached(); | |
11830 | } | |
11831 | } | |
11832 | ||
931c8cc2 PM |
11833 | static void handle_2misc_widening(DisasContext *s, int opcode, bool is_q, |
11834 | int size, int rn, int rd) | |
11835 | { | |
11836 | /* Handle 2-reg-misc ops which are widening (so each size element | |
11837 | * in the source becomes a 2*size element in the destination. | |
11838 | * The only instruction like this is FCVTL. | |
11839 | */ | |
11840 | int pass; | |
11841 | ||
11842 | if (size == 3) { | |
11843 | /* 32 -> 64 bit fp conversion */ | |
11844 | TCGv_i64 tcg_res[2]; | |
11845 | int srcelt = is_q ? 2 : 0; | |
11846 | ||
11847 | for (pass = 0; pass < 2; pass++) { | |
11848 | TCGv_i32 tcg_op = tcg_temp_new_i32(); | |
11849 | tcg_res[pass] = tcg_temp_new_i64(); | |
11850 | ||
11851 | read_vec_element_i32(s, tcg_op, rn, srcelt + pass, MO_32); | |
11852 | gen_helper_vfp_fcvtds(tcg_res[pass], tcg_op, cpu_env); | |
11853 | tcg_temp_free_i32(tcg_op); | |
11854 | } | |
11855 | for (pass = 0; pass < 2; pass++) { | |
11856 | write_vec_element(s, tcg_res[pass], rd, pass, MO_64); | |
11857 | tcg_temp_free_i64(tcg_res[pass]); | |
11858 | } | |
11859 | } else { | |
11860 | /* 16 -> 32 bit fp conversion */ | |
11861 | int srcelt = is_q ? 4 : 0; | |
11862 | TCGv_i32 tcg_res[4]; | |
486624fc AB |
11863 | TCGv_ptr fpst = get_fpstatus_ptr(false); |
11864 | TCGv_i32 ahp = get_ahp_flag(); | |
931c8cc2 PM |
11865 | |
11866 | for (pass = 0; pass < 4; pass++) { | |
11867 | tcg_res[pass] = tcg_temp_new_i32(); | |
11868 | ||
11869 | read_vec_element_i32(s, tcg_res[pass], rn, srcelt + pass, MO_16); | |
11870 | gen_helper_vfp_fcvt_f16_to_f32(tcg_res[pass], tcg_res[pass], | |
486624fc | 11871 | fpst, ahp); |
931c8cc2 PM |
11872 | } |
11873 | for (pass = 0; pass < 4; pass++) { | |
11874 | write_vec_element_i32(s, tcg_res[pass], rd, pass, MO_32); | |
11875 | tcg_temp_free_i32(tcg_res[pass]); | |
11876 | } | |
486624fc AB |
11877 | |
11878 | tcg_temp_free_ptr(fpst); | |
11879 | tcg_temp_free_i32(ahp); | |
931c8cc2 PM |
11880 | } |
11881 | } | |
11882 | ||
39d82118 AB |
11883 | static void handle_rev(DisasContext *s, int opcode, bool u, |
11884 | bool is_q, int size, int rn, int rd) | |
11885 | { | |
11886 | int op = (opcode << 1) | u; | |
11887 | int opsz = op + size; | |
11888 | int grp_size = 3 - opsz; | |
11889 | int dsize = is_q ? 128 : 64; | |
11890 | int i; | |
11891 | ||
11892 | if (opsz >= 3) { | |
11893 | unallocated_encoding(s); | |
11894 | return; | |
11895 | } | |
11896 | ||
8c6afa6a PM |
11897 | if (!fp_access_check(s)) { |
11898 | return; | |
11899 | } | |
11900 | ||
39d82118 AB |
11901 | if (size == 0) { |
11902 | /* Special case bytes, use bswap op on each group of elements */ | |
11903 | int groups = dsize / (8 << grp_size); | |
11904 | ||
11905 | for (i = 0; i < groups; i++) { | |
11906 | TCGv_i64 tcg_tmp = tcg_temp_new_i64(); | |
11907 | ||
11908 | read_vec_element(s, tcg_tmp, rn, i, grp_size); | |
11909 | switch (grp_size) { | |
11910 | case MO_16: | |
11911 | tcg_gen_bswap16_i64(tcg_tmp, tcg_tmp); | |
11912 | break; | |
11913 | case MO_32: | |
11914 | tcg_gen_bswap32_i64(tcg_tmp, tcg_tmp); | |
11915 | break; | |
11916 | case MO_64: | |
11917 | tcg_gen_bswap64_i64(tcg_tmp, tcg_tmp); | |
11918 | break; | |
11919 | default: | |
11920 | g_assert_not_reached(); | |
11921 | } | |
11922 | write_vec_element(s, tcg_tmp, rd, i, grp_size); | |
11923 | tcg_temp_free_i64(tcg_tmp); | |
11924 | } | |
4ff55bcb | 11925 | clear_vec_high(s, is_q, rd); |
39d82118 AB |
11926 | } else { |
11927 | int revmask = (1 << grp_size) - 1; | |
11928 | int esize = 8 << size; | |
11929 | int elements = dsize / esize; | |
11930 | TCGv_i64 tcg_rn = tcg_temp_new_i64(); | |
11931 | TCGv_i64 tcg_rd = tcg_const_i64(0); | |
11932 | TCGv_i64 tcg_rd_hi = tcg_const_i64(0); | |
11933 | ||
11934 | for (i = 0; i < elements; i++) { | |
11935 | int e_rev = (i & 0xf) ^ revmask; | |
11936 | int off = e_rev * esize; | |
11937 | read_vec_element(s, tcg_rn, rn, i, size); | |
11938 | if (off >= 64) { | |
11939 | tcg_gen_deposit_i64(tcg_rd_hi, tcg_rd_hi, | |
11940 | tcg_rn, off - 64, esize); | |
11941 | } else { | |
11942 | tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_rn, off, esize); | |
11943 | } | |
11944 | } | |
11945 | write_vec_element(s, tcg_rd, rd, 0, MO_64); | |
11946 | write_vec_element(s, tcg_rd_hi, rd, 1, MO_64); | |
11947 | ||
11948 | tcg_temp_free_i64(tcg_rd_hi); | |
11949 | tcg_temp_free_i64(tcg_rd); | |
11950 | tcg_temp_free_i64(tcg_rn); | |
11951 | } | |
11952 | } | |
11953 | ||
6781fa11 PM |
11954 | static void handle_2misc_pairwise(DisasContext *s, int opcode, bool u, |
11955 | bool is_q, int size, int rn, int rd) | |
11956 | { | |
11957 | /* Implement the pairwise operations from 2-misc: | |
11958 | * SADDLP, UADDLP, SADALP, UADALP. | |
11959 | * These all add pairs of elements in the input to produce a | |
11960 | * double-width result element in the output (possibly accumulating). | |
11961 | */ | |
11962 | bool accum = (opcode == 0x6); | |
11963 | int maxpass = is_q ? 2 : 1; | |
11964 | int pass; | |
11965 | TCGv_i64 tcg_res[2]; | |
11966 | ||
11967 | if (size == 2) { | |
11968 | /* 32 + 32 -> 64 op */ | |
14776ab5 | 11969 | MemOp memop = size + (u ? 0 : MO_SIGN); |
6781fa11 PM |
11970 | |
11971 | for (pass = 0; pass < maxpass; pass++) { | |
11972 | TCGv_i64 tcg_op1 = tcg_temp_new_i64(); | |
11973 | TCGv_i64 tcg_op2 = tcg_temp_new_i64(); | |
11974 | ||
11975 | tcg_res[pass] = tcg_temp_new_i64(); | |
11976 | ||
11977 | read_vec_element(s, tcg_op1, rn, pass * 2, memop); | |
11978 | read_vec_element(s, tcg_op2, rn, pass * 2 + 1, memop); | |
11979 | tcg_gen_add_i64(tcg_res[pass], tcg_op1, tcg_op2); | |
11980 | if (accum) { | |
11981 | read_vec_element(s, tcg_op1, rd, pass, MO_64); | |
11982 | tcg_gen_add_i64(tcg_res[pass], tcg_res[pass], tcg_op1); | |
11983 | } | |
11984 | ||
11985 | tcg_temp_free_i64(tcg_op1); | |
11986 | tcg_temp_free_i64(tcg_op2); | |
11987 | } | |
11988 | } else { | |
11989 | for (pass = 0; pass < maxpass; pass++) { | |
11990 | TCGv_i64 tcg_op = tcg_temp_new_i64(); | |
039f4e80 PM |
11991 | NeonGenOne64OpFn *genfn; |
11992 | static NeonGenOne64OpFn * const fns[2][2] = { | |
6781fa11 PM |
11993 | { gen_helper_neon_addlp_s8, gen_helper_neon_addlp_u8 }, |
11994 | { gen_helper_neon_addlp_s16, gen_helper_neon_addlp_u16 }, | |
11995 | }; | |
11996 | ||
11997 | genfn = fns[size][u]; | |
11998 | ||
11999 | tcg_res[pass] = tcg_temp_new_i64(); | |
12000 | ||
12001 | read_vec_element(s, tcg_op, rn, pass, MO_64); | |
12002 | genfn(tcg_res[pass], tcg_op); | |
12003 | ||
12004 | if (accum) { | |
12005 | read_vec_element(s, tcg_op, rd, pass, MO_64); | |
12006 | if (size == 0) { | |
12007 | gen_helper_neon_addl_u16(tcg_res[pass], | |
12008 | tcg_res[pass], tcg_op); | |
12009 | } else { | |
12010 | gen_helper_neon_addl_u32(tcg_res[pass], | |
12011 | tcg_res[pass], tcg_op); | |
12012 | } | |
12013 | } | |
12014 | tcg_temp_free_i64(tcg_op); | |
12015 | } | |
12016 | } | |
12017 | if (!is_q) { | |
12018 | tcg_res[1] = tcg_const_i64(0); | |
12019 | } | |
12020 | for (pass = 0; pass < 2; pass++) { | |
12021 | write_vec_element(s, tcg_res[pass], rd, pass, MO_64); | |
12022 | tcg_temp_free_i64(tcg_res[pass]); | |
12023 | } | |
12024 | } | |
12025 | ||
73a81d10 PM |
12026 | static void handle_shll(DisasContext *s, bool is_q, int size, int rn, int rd) |
12027 | { | |
12028 | /* Implement SHLL and SHLL2 */ | |
12029 | int pass; | |
12030 | int part = is_q ? 2 : 0; | |
12031 | TCGv_i64 tcg_res[2]; | |
12032 | ||
12033 | for (pass = 0; pass < 2; pass++) { | |
12034 | static NeonGenWidenFn * const widenfns[3] = { | |
12035 | gen_helper_neon_widen_u8, | |
12036 | gen_helper_neon_widen_u16, | |
12037 | tcg_gen_extu_i32_i64, | |
12038 | }; | |
12039 | NeonGenWidenFn *widenfn = widenfns[size]; | |
12040 | TCGv_i32 tcg_op = tcg_temp_new_i32(); | |
12041 | ||
12042 | read_vec_element_i32(s, tcg_op, rn, part + pass, MO_32); | |
12043 | tcg_res[pass] = tcg_temp_new_i64(); | |
12044 | widenfn(tcg_res[pass], tcg_op); | |
12045 | tcg_gen_shli_i64(tcg_res[pass], tcg_res[pass], 8 << size); | |
12046 | ||
12047 | tcg_temp_free_i32(tcg_op); | |
12048 | } | |
12049 | ||
12050 | for (pass = 0; pass < 2; pass++) { | |
12051 | write_vec_element(s, tcg_res[pass], rd, pass, MO_64); | |
12052 | tcg_temp_free_i64(tcg_res[pass]); | |
12053 | } | |
12054 | } | |
12055 | ||
4ce31af4 | 12056 | /* AdvSIMD two reg misc |
384b26fb AB |
12057 | * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0 |
12058 | * +---+---+---+-----------+------+-----------+--------+-----+------+------+ | |
12059 | * | 0 | Q | U | 0 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd | | |
12060 | * +---+---+---+-----------+------+-----------+--------+-----+------+------+ | |
12061 | */ | |
12062 | static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn) | |
12063 | { | |
45aecc6d PM |
12064 | int size = extract32(insn, 22, 2); |
12065 | int opcode = extract32(insn, 12, 5); | |
12066 | bool u = extract32(insn, 29, 1); | |
12067 | bool is_q = extract32(insn, 30, 1); | |
94b6c911 PM |
12068 | int rn = extract32(insn, 5, 5); |
12069 | int rd = extract32(insn, 0, 5); | |
04c7c6c2 PM |
12070 | bool need_fpstatus = false; |
12071 | bool need_rmode = false; | |
12072 | int rmode = -1; | |
12073 | TCGv_i32 tcg_rmode; | |
12074 | TCGv_ptr tcg_fpstatus; | |
45aecc6d PM |
12075 | |
12076 | switch (opcode) { | |
12077 | case 0x0: /* REV64, REV32 */ | |
12078 | case 0x1: /* REV16 */ | |
39d82118 | 12079 | handle_rev(s, opcode, u, is_q, size, rn, rd); |
45aecc6d | 12080 | return; |
86cbc418 PM |
12081 | case 0x5: /* CNT, NOT, RBIT */ |
12082 | if (u && size == 0) { | |
377ef731 | 12083 | /* NOT */ |
86cbc418 PM |
12084 | break; |
12085 | } else if (u && size == 1) { | |
12086 | /* RBIT */ | |
12087 | break; | |
12088 | } else if (!u && size == 0) { | |
12089 | /* CNT */ | |
12090 | break; | |
45aecc6d | 12091 | } |
86cbc418 | 12092 | unallocated_encoding(s); |
45aecc6d | 12093 | return; |
d980fd59 PM |
12094 | case 0x12: /* XTN, XTN2, SQXTUN, SQXTUN2 */ |
12095 | case 0x14: /* SQXTN, SQXTN2, UQXTN, UQXTN2 */ | |
12096 | if (size == 3) { | |
12097 | unallocated_encoding(s); | |
12098 | return; | |
12099 | } | |
8c6afa6a PM |
12100 | if (!fp_access_check(s)) { |
12101 | return; | |
12102 | } | |
12103 | ||
5201c136 | 12104 | handle_2misc_narrow(s, false, opcode, u, is_q, size, rn, rd); |
d980fd59 | 12105 | return; |
45aecc6d | 12106 | case 0x4: /* CLS, CLZ */ |
b05c3068 AB |
12107 | if (size == 3) { |
12108 | unallocated_encoding(s); | |
12109 | return; | |
12110 | } | |
12111 | break; | |
12112 | case 0x2: /* SADDLP, UADDLP */ | |
45aecc6d | 12113 | case 0x6: /* SADALP, UADALP */ |
45aecc6d PM |
12114 | if (size == 3) { |
12115 | unallocated_encoding(s); | |
12116 | return; | |
12117 | } | |
8c6afa6a PM |
12118 | if (!fp_access_check(s)) { |
12119 | return; | |
12120 | } | |
6781fa11 | 12121 | handle_2misc_pairwise(s, opcode, u, is_q, size, rn, rd); |
45aecc6d PM |
12122 | return; |
12123 | case 0x13: /* SHLL, SHLL2 */ | |
12124 | if (u == 0 || size == 3) { | |
12125 | unallocated_encoding(s); | |
12126 | return; | |
12127 | } | |
8c6afa6a PM |
12128 | if (!fp_access_check(s)) { |
12129 | return; | |
12130 | } | |
73a81d10 | 12131 | handle_shll(s, is_q, size, rn, rd); |
45aecc6d PM |
12132 | return; |
12133 | case 0xa: /* CMLT */ | |
12134 | if (u == 1) { | |
12135 | unallocated_encoding(s); | |
12136 | return; | |
12137 | } | |
12138 | /* fall through */ | |
45aecc6d PM |
12139 | case 0x8: /* CMGT, CMGE */ |
12140 | case 0x9: /* CMEQ, CMLE */ | |
12141 | case 0xb: /* ABS, NEG */ | |
94b6c911 PM |
12142 | if (size == 3 && !is_q) { |
12143 | unallocated_encoding(s); | |
12144 | return; | |
12145 | } | |
12146 | break; | |
12147 | case 0x3: /* SUQADD, USQADD */ | |
09e03735 AB |
12148 | if (size == 3 && !is_q) { |
12149 | unallocated_encoding(s); | |
12150 | return; | |
12151 | } | |
8c6afa6a PM |
12152 | if (!fp_access_check(s)) { |
12153 | return; | |
12154 | } | |
09e03735 AB |
12155 | handle_2misc_satacc(s, false, u, is_q, size, rn, rd); |
12156 | return; | |
94b6c911 | 12157 | case 0x7: /* SQABS, SQNEG */ |
45aecc6d PM |
12158 | if (size == 3 && !is_q) { |
12159 | unallocated_encoding(s); | |
12160 | return; | |
12161 | } | |
0a79bc87 | 12162 | break; |
45aecc6d | 12163 | case 0xc ... 0xf: |
6bea2563 | 12164 | case 0x16 ... 0x1f: |
45aecc6d PM |
12165 | { |
12166 | /* Floating point: U, size[1] and opcode indicate operation; | |
12167 | * size[0] indicates single or double precision. | |
12168 | */ | |
10113b69 | 12169 | int is_double = extract32(size, 0, 1); |
45aecc6d | 12170 | opcode |= (extract32(size, 1, 1) << 5) | (u << 6); |
10113b69 | 12171 | size = is_double ? 3 : 2; |
45aecc6d | 12172 | switch (opcode) { |
f93d0138 PM |
12173 | case 0x2f: /* FABS */ |
12174 | case 0x6f: /* FNEG */ | |
12175 | if (size == 3 && !is_q) { | |
12176 | unallocated_encoding(s); | |
12177 | return; | |
12178 | } | |
12179 | break; | |
10113b69 AB |
12180 | case 0x1d: /* SCVTF */ |
12181 | case 0x5d: /* UCVTF */ | |
12182 | { | |
12183 | bool is_signed = (opcode == 0x1d) ? true : false; | |
12184 | int elements = is_double ? 2 : is_q ? 4 : 2; | |
12185 | if (is_double && !is_q) { | |
12186 | unallocated_encoding(s); | |
12187 | return; | |
12188 | } | |
8c6afa6a PM |
12189 | if (!fp_access_check(s)) { |
12190 | return; | |
12191 | } | |
10113b69 AB |
12192 | handle_simd_intfp_conv(s, rd, rn, elements, is_signed, 0, size); |
12193 | return; | |
12194 | } | |
8908f4d1 AB |
12195 | case 0x2c: /* FCMGT (zero) */ |
12196 | case 0x2d: /* FCMEQ (zero) */ | |
12197 | case 0x2e: /* FCMLT (zero) */ | |
12198 | case 0x6c: /* FCMGE (zero) */ | |
12199 | case 0x6d: /* FCMLE (zero) */ | |
12200 | if (size == 3 && !is_q) { | |
12201 | unallocated_encoding(s); | |
12202 | return; | |
12203 | } | |
12204 | handle_2misc_fcmp_zero(s, opcode, false, u, is_q, size, rn, rd); | |
12205 | return; | |
f612537e AB |
12206 | case 0x7f: /* FSQRT */ |
12207 | if (size == 3 && !is_q) { | |
12208 | unallocated_encoding(s); | |
12209 | return; | |
12210 | } | |
12211 | break; | |
04c7c6c2 PM |
12212 | case 0x1a: /* FCVTNS */ |
12213 | case 0x1b: /* FCVTMS */ | |
12214 | case 0x3a: /* FCVTPS */ | |
12215 | case 0x3b: /* FCVTZS */ | |
12216 | case 0x5a: /* FCVTNU */ | |
12217 | case 0x5b: /* FCVTMU */ | |
12218 | case 0x7a: /* FCVTPU */ | |
12219 | case 0x7b: /* FCVTZU */ | |
12220 | need_fpstatus = true; | |
12221 | need_rmode = true; | |
12222 | rmode = extract32(opcode, 5, 1) | (extract32(opcode, 0, 1) << 1); | |
12223 | if (size == 3 && !is_q) { | |
12224 | unallocated_encoding(s); | |
12225 | return; | |
12226 | } | |
12227 | break; | |
12228 | case 0x5c: /* FCVTAU */ | |
12229 | case 0x1c: /* FCVTAS */ | |
12230 | need_fpstatus = true; | |
12231 | need_rmode = true; | |
12232 | rmode = FPROUNDING_TIEAWAY; | |
12233 | if (size == 3 && !is_q) { | |
12234 | unallocated_encoding(s); | |
12235 | return; | |
12236 | } | |
12237 | break; | |
b6d4443a AB |
12238 | case 0x3c: /* URECPE */ |
12239 | if (size == 3) { | |
12240 | unallocated_encoding(s); | |
12241 | return; | |
12242 | } | |
12243 | /* fall through */ | |
12244 | case 0x3d: /* FRECPE */ | |
c2fb418e AB |
12245 | case 0x7d: /* FRSQRTE */ |
12246 | if (size == 3 && !is_q) { | |
12247 | unallocated_encoding(s); | |
12248 | return; | |
12249 | } | |
8c6afa6a PM |
12250 | if (!fp_access_check(s)) { |
12251 | return; | |
12252 | } | |
b6d4443a AB |
12253 | handle_2misc_reciprocal(s, opcode, false, u, is_q, size, rn, rd); |
12254 | return; | |
5553955e PM |
12255 | case 0x56: /* FCVTXN, FCVTXN2 */ |
12256 | if (size == 2) { | |
12257 | unallocated_encoding(s); | |
12258 | return; | |
12259 | } | |
12260 | /* fall through */ | |
45aecc6d | 12261 | case 0x16: /* FCVTN, FCVTN2 */ |
261a5b4d PM |
12262 | /* handle_2misc_narrow does a 2*size -> size operation, but these |
12263 | * instructions encode the source size rather than dest size. | |
12264 | */ | |
8c6afa6a PM |
12265 | if (!fp_access_check(s)) { |
12266 | return; | |
12267 | } | |
5201c136 | 12268 | handle_2misc_narrow(s, false, opcode, 0, is_q, size - 1, rn, rd); |
261a5b4d | 12269 | return; |
45aecc6d | 12270 | case 0x17: /* FCVTL, FCVTL2 */ |
8c6afa6a PM |
12271 | if (!fp_access_check(s)) { |
12272 | return; | |
12273 | } | |
931c8cc2 PM |
12274 | handle_2misc_widening(s, opcode, is_q, size, rn, rd); |
12275 | return; | |
45aecc6d PM |
12276 | case 0x18: /* FRINTN */ |
12277 | case 0x19: /* FRINTM */ | |
45aecc6d PM |
12278 | case 0x38: /* FRINTP */ |
12279 | case 0x39: /* FRINTZ */ | |
03df01ed PM |
12280 | need_rmode = true; |
12281 | rmode = extract32(opcode, 5, 1) | (extract32(opcode, 0, 1) << 1); | |
12282 | /* fall through */ | |
12283 | case 0x59: /* FRINTX */ | |
12284 | case 0x79: /* FRINTI */ | |
12285 | need_fpstatus = true; | |
12286 | if (size == 3 && !is_q) { | |
12287 | unallocated_encoding(s); | |
12288 | return; | |
12289 | } | |
12290 | break; | |
12291 | case 0x58: /* FRINTA */ | |
12292 | need_rmode = true; | |
12293 | rmode = FPROUNDING_TIEAWAY; | |
12294 | need_fpstatus = true; | |
12295 | if (size == 3 && !is_q) { | |
12296 | unallocated_encoding(s); | |
12297 | return; | |
12298 | } | |
12299 | break; | |
45aecc6d | 12300 | case 0x7c: /* URSQRTE */ |
c2fb418e AB |
12301 | if (size == 3) { |
12302 | unallocated_encoding(s); | |
12303 | return; | |
12304 | } | |
c2fb418e | 12305 | break; |
6bea2563 RH |
12306 | case 0x1e: /* FRINT32Z */ |
12307 | case 0x1f: /* FRINT64Z */ | |
12308 | need_rmode = true; | |
12309 | rmode = FPROUNDING_ZERO; | |
12310 | /* fall through */ | |
12311 | case 0x5e: /* FRINT32X */ | |
12312 | case 0x5f: /* FRINT64X */ | |
12313 | need_fpstatus = true; | |
12314 | if ((size == 3 && !is_q) || !dc_isar_feature(aa64_frint, s)) { | |
12315 | unallocated_encoding(s); | |
12316 | return; | |
12317 | } | |
12318 | break; | |
45aecc6d PM |
12319 | default: |
12320 | unallocated_encoding(s); | |
12321 | return; | |
12322 | } | |
12323 | break; | |
12324 | } | |
12325 | default: | |
12326 | unallocated_encoding(s); | |
12327 | return; | |
12328 | } | |
94b6c911 | 12329 | |
8c6afa6a PM |
12330 | if (!fp_access_check(s)) { |
12331 | return; | |
12332 | } | |
12333 | ||
9b049916 | 12334 | if (need_fpstatus || need_rmode) { |
d81ce0ef | 12335 | tcg_fpstatus = get_fpstatus_ptr(false); |
04c7c6c2 | 12336 | } else { |
f764718d | 12337 | tcg_fpstatus = NULL; |
04c7c6c2 PM |
12338 | } |
12339 | if (need_rmode) { | |
12340 | tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode)); | |
9b049916 | 12341 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); |
04c7c6c2 | 12342 | } else { |
f764718d | 12343 | tcg_rmode = NULL; |
04c7c6c2 PM |
12344 | } |
12345 | ||
377ef731 RH |
12346 | switch (opcode) { |
12347 | case 0x5: | |
12348 | if (u && size == 0) { /* NOT */ | |
12349 | gen_gvec_fn2(s, is_q, rd, rn, tcg_gen_gvec_not, 0); | |
12350 | return; | |
12351 | } | |
12352 | break; | |
6b375d35 | 12353 | case 0x8: /* CMGT, CMGE */ |
69d5e2bf RH |
12354 | if (u) { |
12355 | gen_gvec_fn2(s, is_q, rd, rn, gen_gvec_cge0, size); | |
12356 | } else { | |
12357 | gen_gvec_fn2(s, is_q, rd, rn, gen_gvec_cgt0, size); | |
12358 | } | |
6b375d35 RH |
12359 | return; |
12360 | case 0x9: /* CMEQ, CMLE */ | |
69d5e2bf RH |
12361 | if (u) { |
12362 | gen_gvec_fn2(s, is_q, rd, rn, gen_gvec_cle0, size); | |
12363 | } else { | |
12364 | gen_gvec_fn2(s, is_q, rd, rn, gen_gvec_ceq0, size); | |
12365 | } | |
6b375d35 RH |
12366 | return; |
12367 | case 0xa: /* CMLT */ | |
69d5e2bf | 12368 | gen_gvec_fn2(s, is_q, rd, rn, gen_gvec_clt0, size); |
6b375d35 | 12369 | return; |
377ef731 | 12370 | case 0xb: |
4e027a71 | 12371 | if (u) { /* ABS, NEG */ |
377ef731 | 12372 | gen_gvec_fn2(s, is_q, rd, rn, tcg_gen_gvec_neg, size); |
4e027a71 RH |
12373 | } else { |
12374 | gen_gvec_fn2(s, is_q, rd, rn, tcg_gen_gvec_abs, size); | |
377ef731 | 12375 | } |
4e027a71 | 12376 | return; |
377ef731 RH |
12377 | } |
12378 | ||
94b6c911 PM |
12379 | if (size == 3) { |
12380 | /* All 64-bit element operations can be shared with scalar 2misc */ | |
12381 | int pass; | |
12382 | ||
a8766e31 RH |
12383 | /* Coverity claims (size == 3 && !is_q) has been eliminated |
12384 | * from all paths leading to here. | |
12385 | */ | |
12386 | tcg_debug_assert(is_q); | |
12387 | for (pass = 0; pass < 2; pass++) { | |
94b6c911 PM |
12388 | TCGv_i64 tcg_op = tcg_temp_new_i64(); |
12389 | TCGv_i64 tcg_res = tcg_temp_new_i64(); | |
12390 | ||
12391 | read_vec_element(s, tcg_op, rn, pass, MO_64); | |
12392 | ||
04c7c6c2 PM |
12393 | handle_2misc_64(s, opcode, u, tcg_res, tcg_op, |
12394 | tcg_rmode, tcg_fpstatus); | |
94b6c911 PM |
12395 | |
12396 | write_vec_element(s, tcg_res, rd, pass, MO_64); | |
12397 | ||
12398 | tcg_temp_free_i64(tcg_res); | |
12399 | tcg_temp_free_i64(tcg_op); | |
12400 | } | |
12401 | } else { | |
12402 | int pass; | |
12403 | ||
12404 | for (pass = 0; pass < (is_q ? 4 : 2); pass++) { | |
12405 | TCGv_i32 tcg_op = tcg_temp_new_i32(); | |
12406 | TCGv_i32 tcg_res = tcg_temp_new_i32(); | |
94b6c911 PM |
12407 | |
12408 | read_vec_element_i32(s, tcg_op, rn, pass, MO_32); | |
12409 | ||
12410 | if (size == 2) { | |
12411 | /* Special cases for 32 bit elements */ | |
12412 | switch (opcode) { | |
b05c3068 AB |
12413 | case 0x4: /* CLS */ |
12414 | if (u) { | |
7539a012 | 12415 | tcg_gen_clzi_i32(tcg_res, tcg_op, 32); |
b05c3068 | 12416 | } else { |
bc21dbcc | 12417 | tcg_gen_clrsb_i32(tcg_res, tcg_op); |
b05c3068 AB |
12418 | } |
12419 | break; | |
0a79bc87 AB |
12420 | case 0x7: /* SQABS, SQNEG */ |
12421 | if (u) { | |
12422 | gen_helper_neon_qneg_s32(tcg_res, cpu_env, tcg_op); | |
12423 | } else { | |
12424 | gen_helper_neon_qabs_s32(tcg_res, cpu_env, tcg_op); | |
12425 | } | |
12426 | break; | |
f93d0138 PM |
12427 | case 0x2f: /* FABS */ |
12428 | gen_helper_vfp_abss(tcg_res, tcg_op); | |
12429 | break; | |
12430 | case 0x6f: /* FNEG */ | |
12431 | gen_helper_vfp_negs(tcg_res, tcg_op); | |
12432 | break; | |
f612537e AB |
12433 | case 0x7f: /* FSQRT */ |
12434 | gen_helper_vfp_sqrts(tcg_res, tcg_op, cpu_env); | |
12435 | break; | |
04c7c6c2 PM |
12436 | case 0x1a: /* FCVTNS */ |
12437 | case 0x1b: /* FCVTMS */ | |
12438 | case 0x1c: /* FCVTAS */ | |
12439 | case 0x3a: /* FCVTPS */ | |
12440 | case 0x3b: /* FCVTZS */ | |
12441 | { | |
12442 | TCGv_i32 tcg_shift = tcg_const_i32(0); | |
12443 | gen_helper_vfp_tosls(tcg_res, tcg_op, | |
12444 | tcg_shift, tcg_fpstatus); | |
12445 | tcg_temp_free_i32(tcg_shift); | |
12446 | break; | |
12447 | } | |
12448 | case 0x5a: /* FCVTNU */ | |
12449 | case 0x5b: /* FCVTMU */ | |
12450 | case 0x5c: /* FCVTAU */ | |
12451 | case 0x7a: /* FCVTPU */ | |
12452 | case 0x7b: /* FCVTZU */ | |
12453 | { | |
12454 | TCGv_i32 tcg_shift = tcg_const_i32(0); | |
12455 | gen_helper_vfp_touls(tcg_res, tcg_op, | |
12456 | tcg_shift, tcg_fpstatus); | |
12457 | tcg_temp_free_i32(tcg_shift); | |
12458 | break; | |
12459 | } | |
03df01ed PM |
12460 | case 0x18: /* FRINTN */ |
12461 | case 0x19: /* FRINTM */ | |
12462 | case 0x38: /* FRINTP */ | |
12463 | case 0x39: /* FRINTZ */ | |
12464 | case 0x58: /* FRINTA */ | |
12465 | case 0x79: /* FRINTI */ | |
12466 | gen_helper_rints(tcg_res, tcg_op, tcg_fpstatus); | |
12467 | break; | |
12468 | case 0x59: /* FRINTX */ | |
12469 | gen_helper_rints_exact(tcg_res, tcg_op, tcg_fpstatus); | |
12470 | break; | |
c2fb418e | 12471 | case 0x7c: /* URSQRTE */ |
fe6fb4be | 12472 | gen_helper_rsqrte_u32(tcg_res, tcg_op); |
c2fb418e | 12473 | break; |
6bea2563 RH |
12474 | case 0x1e: /* FRINT32Z */ |
12475 | case 0x5e: /* FRINT32X */ | |
12476 | gen_helper_frint32_s(tcg_res, tcg_op, tcg_fpstatus); | |
12477 | break; | |
12478 | case 0x1f: /* FRINT64Z */ | |
12479 | case 0x5f: /* FRINT64X */ | |
12480 | gen_helper_frint64_s(tcg_res, tcg_op, tcg_fpstatus); | |
12481 | break; | |
94b6c911 PM |
12482 | default: |
12483 | g_assert_not_reached(); | |
12484 | } | |
12485 | } else { | |
12486 | /* Use helpers for 8 and 16 bit elements */ | |
12487 | switch (opcode) { | |
86cbc418 PM |
12488 | case 0x5: /* CNT, RBIT */ |
12489 | /* For these two insns size is part of the opcode specifier | |
12490 | * (handled earlier); they always operate on byte elements. | |
12491 | */ | |
12492 | if (u) { | |
12493 | gen_helper_neon_rbit_u8(tcg_res, tcg_op); | |
12494 | } else { | |
12495 | gen_helper_neon_cnt_u8(tcg_res, tcg_op); | |
12496 | } | |
12497 | break; | |
0a79bc87 AB |
12498 | case 0x7: /* SQABS, SQNEG */ |
12499 | { | |
12500 | NeonGenOneOpEnvFn *genfn; | |
12501 | static NeonGenOneOpEnvFn * const fns[2][2] = { | |
12502 | { gen_helper_neon_qabs_s8, gen_helper_neon_qneg_s8 }, | |
12503 | { gen_helper_neon_qabs_s16, gen_helper_neon_qneg_s16 }, | |
12504 | }; | |
12505 | genfn = fns[size][u]; | |
12506 | genfn(tcg_res, cpu_env, tcg_op); | |
12507 | break; | |
12508 | } | |
b05c3068 AB |
12509 | case 0x4: /* CLS, CLZ */ |
12510 | if (u) { | |
12511 | if (size == 0) { | |
12512 | gen_helper_neon_clz_u8(tcg_res, tcg_op); | |
12513 | } else { | |
12514 | gen_helper_neon_clz_u16(tcg_res, tcg_op); | |
12515 | } | |
12516 | } else { | |
12517 | if (size == 0) { | |
12518 | gen_helper_neon_cls_s8(tcg_res, tcg_op); | |
12519 | } else { | |
12520 | gen_helper_neon_cls_s16(tcg_res, tcg_op); | |
12521 | } | |
12522 | } | |
12523 | break; | |
94b6c911 PM |
12524 | default: |
12525 | g_assert_not_reached(); | |
12526 | } | |
12527 | } | |
12528 | ||
12529 | write_vec_element_i32(s, tcg_res, rd, pass, MO_32); | |
12530 | ||
12531 | tcg_temp_free_i32(tcg_res); | |
12532 | tcg_temp_free_i32(tcg_op); | |
12533 | } | |
12534 | } | |
4ff55bcb | 12535 | clear_vec_high(s, is_q, rd); |
04c7c6c2 PM |
12536 | |
12537 | if (need_rmode) { | |
9b049916 | 12538 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); |
04c7c6c2 PM |
12539 | tcg_temp_free_i32(tcg_rmode); |
12540 | } | |
12541 | if (need_fpstatus) { | |
12542 | tcg_temp_free_ptr(tcg_fpstatus); | |
12543 | } | |
384b26fb AB |
12544 | } |
12545 | ||
5d432be6 AB |
12546 | /* AdvSIMD [scalar] two register miscellaneous (FP16) |
12547 | * | |
12548 | * 31 30 29 28 27 24 23 22 21 17 16 12 11 10 9 5 4 0 | |
12549 | * +---+---+---+---+---------+---+-------------+--------+-----+------+------+ | |
12550 | * | 0 | Q | U | S | 1 1 1 0 | a | 1 1 1 1 0 0 | opcode | 1 0 | Rn | Rd | | |
12551 | * +---+---+---+---+---------+---+-------------+--------+-----+------+------+ | |
12552 | * mask: 1000 1111 0111 1110 0000 1100 0000 0000 0x8f7e 0c00 | |
12553 | * val: 0000 1110 0111 1000 0000 1000 0000 0000 0x0e78 0800 | |
12554 | * | |
12555 | * This actually covers two groups where scalar access is governed by | |
12556 | * bit 28. A bunch of the instructions (float to integral) only exist | |
12557 | * in the vector form and are un-allocated for the scalar decode. Also | |
12558 | * in the scalar decode Q is always 1. | |
12559 | */ | |
12560 | static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn) | |
12561 | { | |
6109aea2 AB |
12562 | int fpop, opcode, a, u; |
12563 | int rn, rd; | |
12564 | bool is_q; | |
12565 | bool is_scalar; | |
12566 | bool only_in_vector = false; | |
12567 | ||
12568 | int pass; | |
12569 | TCGv_i32 tcg_rmode = NULL; | |
12570 | TCGv_ptr tcg_fpstatus = NULL; | |
12571 | bool need_rmode = false; | |
15f8a233 | 12572 | bool need_fpst = true; |
6109aea2 | 12573 | int rmode; |
5d432be6 | 12574 | |
5763190f | 12575 | if (!dc_isar_feature(aa64_fp16, s)) { |
5d432be6 AB |
12576 | unallocated_encoding(s); |
12577 | return; | |
12578 | } | |
12579 | ||
6109aea2 AB |
12580 | rd = extract32(insn, 0, 5); |
12581 | rn = extract32(insn, 5, 5); | |
5d432be6 | 12582 | |
5d432be6 | 12583 | a = extract32(insn, 23, 1); |
6109aea2 AB |
12584 | u = extract32(insn, 29, 1); |
12585 | is_scalar = extract32(insn, 28, 1); | |
12586 | is_q = extract32(insn, 30, 1); | |
12587 | ||
12588 | opcode = extract32(insn, 12, 5); | |
5d432be6 | 12589 | fpop = deposit32(opcode, 5, 1, a); |
6109aea2 | 12590 | fpop = deposit32(fpop, 6, 1, u); |
5d432be6 | 12591 | |
7d4dd1a7 AB |
12592 | rd = extract32(insn, 0, 5); |
12593 | rn = extract32(insn, 5, 5); | |
12594 | ||
5d432be6 | 12595 | switch (fpop) { |
93193190 AB |
12596 | case 0x1d: /* SCVTF */ |
12597 | case 0x5d: /* UCVTF */ | |
12598 | { | |
12599 | int elements; | |
12600 | ||
12601 | if (is_scalar) { | |
12602 | elements = 1; | |
12603 | } else { | |
12604 | elements = (is_q ? 8 : 4); | |
12605 | } | |
12606 | ||
12607 | if (!fp_access_check(s)) { | |
12608 | return; | |
12609 | } | |
12610 | handle_simd_intfp_conv(s, rd, rn, elements, !u, 0, MO_16); | |
12611 | return; | |
12612 | } | |
7d4dd1a7 AB |
12613 | break; |
12614 | case 0x2c: /* FCMGT (zero) */ | |
12615 | case 0x2d: /* FCMEQ (zero) */ | |
12616 | case 0x2e: /* FCMLT (zero) */ | |
12617 | case 0x6c: /* FCMGE (zero) */ | |
12618 | case 0x6d: /* FCMLE (zero) */ | |
12619 | handle_2misc_fcmp_zero(s, fpop, is_scalar, 0, is_q, MO_16, rn, rd); | |
12620 | return; | |
fbd06e1e | 12621 | case 0x3d: /* FRECPE */ |
98695028 | 12622 | case 0x3f: /* FRECPX */ |
fbd06e1e | 12623 | break; |
6109aea2 AB |
12624 | case 0x18: /* FRINTN */ |
12625 | need_rmode = true; | |
12626 | only_in_vector = true; | |
12627 | rmode = FPROUNDING_TIEEVEN; | |
12628 | break; | |
12629 | case 0x19: /* FRINTM */ | |
12630 | need_rmode = true; | |
12631 | only_in_vector = true; | |
12632 | rmode = FPROUNDING_NEGINF; | |
12633 | break; | |
12634 | case 0x38: /* FRINTP */ | |
12635 | need_rmode = true; | |
12636 | only_in_vector = true; | |
12637 | rmode = FPROUNDING_POSINF; | |
12638 | break; | |
12639 | case 0x39: /* FRINTZ */ | |
12640 | need_rmode = true; | |
12641 | only_in_vector = true; | |
12642 | rmode = FPROUNDING_ZERO; | |
12643 | break; | |
12644 | case 0x58: /* FRINTA */ | |
12645 | need_rmode = true; | |
12646 | only_in_vector = true; | |
12647 | rmode = FPROUNDING_TIEAWAY; | |
12648 | break; | |
12649 | case 0x59: /* FRINTX */ | |
12650 | case 0x79: /* FRINTI */ | |
12651 | only_in_vector = true; | |
12652 | /* current rounding mode */ | |
12653 | break; | |
2df58130 AB |
12654 | case 0x1a: /* FCVTNS */ |
12655 | need_rmode = true; | |
12656 | rmode = FPROUNDING_TIEEVEN; | |
12657 | break; | |
12658 | case 0x1b: /* FCVTMS */ | |
12659 | need_rmode = true; | |
12660 | rmode = FPROUNDING_NEGINF; | |
12661 | break; | |
12662 | case 0x1c: /* FCVTAS */ | |
12663 | need_rmode = true; | |
12664 | rmode = FPROUNDING_TIEAWAY; | |
12665 | break; | |
12666 | case 0x3a: /* FCVTPS */ | |
12667 | need_rmode = true; | |
12668 | rmode = FPROUNDING_POSINF; | |
12669 | break; | |
12670 | case 0x3b: /* FCVTZS */ | |
12671 | need_rmode = true; | |
12672 | rmode = FPROUNDING_ZERO; | |
12673 | break; | |
12674 | case 0x5a: /* FCVTNU */ | |
12675 | need_rmode = true; | |
12676 | rmode = FPROUNDING_TIEEVEN; | |
12677 | break; | |
12678 | case 0x5b: /* FCVTMU */ | |
12679 | need_rmode = true; | |
12680 | rmode = FPROUNDING_NEGINF; | |
12681 | break; | |
12682 | case 0x5c: /* FCVTAU */ | |
12683 | need_rmode = true; | |
12684 | rmode = FPROUNDING_TIEAWAY; | |
12685 | break; | |
12686 | case 0x7a: /* FCVTPU */ | |
12687 | need_rmode = true; | |
12688 | rmode = FPROUNDING_POSINF; | |
12689 | break; | |
12690 | case 0x7b: /* FCVTZU */ | |
12691 | need_rmode = true; | |
12692 | rmode = FPROUNDING_ZERO; | |
12693 | break; | |
15f8a233 AB |
12694 | case 0x2f: /* FABS */ |
12695 | case 0x6f: /* FNEG */ | |
12696 | need_fpst = false; | |
12697 | break; | |
c625ff95 | 12698 | case 0x7d: /* FRSQRTE */ |
b96a54c7 AB |
12699 | case 0x7f: /* FSQRT (vector) */ |
12700 | break; | |
5d432be6 AB |
12701 | default: |
12702 | fprintf(stderr, "%s: insn %#04x fpop %#2x\n", __func__, insn, fpop); | |
12703 | g_assert_not_reached(); | |
12704 | } | |
12705 | ||
6109aea2 AB |
12706 | |
12707 | /* Check additional constraints for the scalar encoding */ | |
12708 | if (is_scalar) { | |
12709 | if (!is_q) { | |
12710 | unallocated_encoding(s); | |
12711 | return; | |
12712 | } | |
12713 | /* FRINTxx is only in the vector form */ | |
12714 | if (only_in_vector) { | |
12715 | unallocated_encoding(s); | |
12716 | return; | |
12717 | } | |
12718 | } | |
12719 | ||
12720 | if (!fp_access_check(s)) { | |
12721 | return; | |
12722 | } | |
12723 | ||
15f8a233 | 12724 | if (need_rmode || need_fpst) { |
6109aea2 AB |
12725 | tcg_fpstatus = get_fpstatus_ptr(true); |
12726 | } | |
12727 | ||
12728 | if (need_rmode) { | |
12729 | tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode)); | |
12730 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); | |
12731 | } | |
12732 | ||
12733 | if (is_scalar) { | |
3d99d931 | 12734 | TCGv_i32 tcg_op = read_fp_hreg(s, rn); |
2df58130 AB |
12735 | TCGv_i32 tcg_res = tcg_temp_new_i32(); |
12736 | ||
2df58130 AB |
12737 | switch (fpop) { |
12738 | case 0x1a: /* FCVTNS */ | |
12739 | case 0x1b: /* FCVTMS */ | |
12740 | case 0x1c: /* FCVTAS */ | |
12741 | case 0x3a: /* FCVTPS */ | |
12742 | case 0x3b: /* FCVTZS */ | |
12743 | gen_helper_advsimd_f16tosinth(tcg_res, tcg_op, tcg_fpstatus); | |
12744 | break; | |
fbd06e1e AB |
12745 | case 0x3d: /* FRECPE */ |
12746 | gen_helper_recpe_f16(tcg_res, tcg_op, tcg_fpstatus); | |
12747 | break; | |
98695028 AB |
12748 | case 0x3f: /* FRECPX */ |
12749 | gen_helper_frecpx_f16(tcg_res, tcg_op, tcg_fpstatus); | |
12750 | break; | |
2df58130 AB |
12751 | case 0x5a: /* FCVTNU */ |
12752 | case 0x5b: /* FCVTMU */ | |
12753 | case 0x5c: /* FCVTAU */ | |
12754 | case 0x7a: /* FCVTPU */ | |
12755 | case 0x7b: /* FCVTZU */ | |
12756 | gen_helper_advsimd_f16touinth(tcg_res, tcg_op, tcg_fpstatus); | |
12757 | break; | |
15f8a233 AB |
12758 | case 0x6f: /* FNEG */ |
12759 | tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000); | |
12760 | break; | |
c625ff95 AB |
12761 | case 0x7d: /* FRSQRTE */ |
12762 | gen_helper_rsqrte_f16(tcg_res, tcg_op, tcg_fpstatus); | |
12763 | break; | |
2df58130 AB |
12764 | default: |
12765 | g_assert_not_reached(); | |
12766 | } | |
12767 | ||
12768 | /* limit any sign extension going on */ | |
12769 | tcg_gen_andi_i32(tcg_res, tcg_res, 0xffff); | |
12770 | write_fp_sreg(s, rd, tcg_res); | |
12771 | ||
12772 | tcg_temp_free_i32(tcg_res); | |
12773 | tcg_temp_free_i32(tcg_op); | |
6109aea2 AB |
12774 | } else { |
12775 | for (pass = 0; pass < (is_q ? 8 : 4); pass++) { | |
12776 | TCGv_i32 tcg_op = tcg_temp_new_i32(); | |
12777 | TCGv_i32 tcg_res = tcg_temp_new_i32(); | |
12778 | ||
12779 | read_vec_element_i32(s, tcg_op, rn, pass, MO_16); | |
12780 | ||
12781 | switch (fpop) { | |
2df58130 AB |
12782 | case 0x1a: /* FCVTNS */ |
12783 | case 0x1b: /* FCVTMS */ | |
12784 | case 0x1c: /* FCVTAS */ | |
12785 | case 0x3a: /* FCVTPS */ | |
12786 | case 0x3b: /* FCVTZS */ | |
12787 | gen_helper_advsimd_f16tosinth(tcg_res, tcg_op, tcg_fpstatus); | |
12788 | break; | |
fbd06e1e AB |
12789 | case 0x3d: /* FRECPE */ |
12790 | gen_helper_recpe_f16(tcg_res, tcg_op, tcg_fpstatus); | |
12791 | break; | |
2df58130 AB |
12792 | case 0x5a: /* FCVTNU */ |
12793 | case 0x5b: /* FCVTMU */ | |
12794 | case 0x5c: /* FCVTAU */ | |
12795 | case 0x7a: /* FCVTPU */ | |
12796 | case 0x7b: /* FCVTZU */ | |
12797 | gen_helper_advsimd_f16touinth(tcg_res, tcg_op, tcg_fpstatus); | |
12798 | break; | |
6109aea2 AB |
12799 | case 0x18: /* FRINTN */ |
12800 | case 0x19: /* FRINTM */ | |
12801 | case 0x38: /* FRINTP */ | |
12802 | case 0x39: /* FRINTZ */ | |
12803 | case 0x58: /* FRINTA */ | |
12804 | case 0x79: /* FRINTI */ | |
12805 | gen_helper_advsimd_rinth(tcg_res, tcg_op, tcg_fpstatus); | |
12806 | break; | |
12807 | case 0x59: /* FRINTX */ | |
12808 | gen_helper_advsimd_rinth_exact(tcg_res, tcg_op, tcg_fpstatus); | |
12809 | break; | |
15f8a233 AB |
12810 | case 0x2f: /* FABS */ |
12811 | tcg_gen_andi_i32(tcg_res, tcg_op, 0x7fff); | |
12812 | break; | |
12813 | case 0x6f: /* FNEG */ | |
12814 | tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000); | |
12815 | break; | |
c625ff95 AB |
12816 | case 0x7d: /* FRSQRTE */ |
12817 | gen_helper_rsqrte_f16(tcg_res, tcg_op, tcg_fpstatus); | |
12818 | break; | |
b96a54c7 AB |
12819 | case 0x7f: /* FSQRT */ |
12820 | gen_helper_sqrt_f16(tcg_res, tcg_op, tcg_fpstatus); | |
12821 | break; | |
6109aea2 AB |
12822 | default: |
12823 | g_assert_not_reached(); | |
12824 | } | |
12825 | ||
12826 | write_vec_element_i32(s, tcg_res, rd, pass, MO_16); | |
12827 | ||
12828 | tcg_temp_free_i32(tcg_res); | |
12829 | tcg_temp_free_i32(tcg_op); | |
12830 | } | |
12831 | ||
12832 | clear_vec_high(s, is_q, rd); | |
12833 | } | |
12834 | ||
12835 | if (tcg_rmode) { | |
12836 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); | |
12837 | tcg_temp_free_i32(tcg_rmode); | |
12838 | } | |
12839 | ||
12840 | if (tcg_fpstatus) { | |
12841 | tcg_temp_free_ptr(tcg_fpstatus); | |
12842 | } | |
5d432be6 AB |
12843 | } |
12844 | ||
4ce31af4 | 12845 | /* AdvSIMD scalar x indexed element |
9f82e0ff PM |
12846 | * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0 |
12847 | * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+ | |
12848 | * | 0 1 | U | 1 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd | | |
12849 | * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+ | |
4ce31af4 | 12850 | * AdvSIMD vector x indexed element |
384b26fb AB |
12851 | * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0 |
12852 | * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+ | |
12853 | * | 0 | Q | U | 0 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd | | |
12854 | * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+ | |
12855 | */ | |
9f82e0ff | 12856 | static void disas_simd_indexed(DisasContext *s, uint32_t insn) |
384b26fb | 12857 | { |
f5e51e7f PM |
12858 | /* This encoding has two kinds of instruction: |
12859 | * normal, where we perform elt x idxelt => elt for each | |
12860 | * element in the vector | |
12861 | * long, where we perform elt x idxelt and generate a result of | |
12862 | * double the width of the input element | |
12863 | * The long ops have a 'part' specifier (ie come in INSN, INSN2 pairs). | |
12864 | */ | |
9f82e0ff | 12865 | bool is_scalar = extract32(insn, 28, 1); |
f5e51e7f PM |
12866 | bool is_q = extract32(insn, 30, 1); |
12867 | bool u = extract32(insn, 29, 1); | |
12868 | int size = extract32(insn, 22, 2); | |
12869 | int l = extract32(insn, 21, 1); | |
12870 | int m = extract32(insn, 20, 1); | |
12871 | /* Note that the Rm field here is only 4 bits, not 5 as it usually is */ | |
12872 | int rm = extract32(insn, 16, 4); | |
12873 | int opcode = extract32(insn, 12, 4); | |
12874 | int h = extract32(insn, 11, 1); | |
12875 | int rn = extract32(insn, 5, 5); | |
12876 | int rd = extract32(insn, 0, 5); | |
12877 | bool is_long = false; | |
d17b7cdc | 12878 | int is_fp = 0; |
5d265064 | 12879 | bool is_fp16 = false; |
f5e51e7f PM |
12880 | int index; |
12881 | TCGv_ptr fpst; | |
12882 | ||
5f81b1de RH |
12883 | switch (16 * u + opcode) { |
12884 | case 0x08: /* MUL */ | |
12885 | case 0x10: /* MLA */ | |
12886 | case 0x14: /* MLS */ | |
12887 | if (is_scalar) { | |
f5e51e7f PM |
12888 | unallocated_encoding(s); |
12889 | return; | |
12890 | } | |
12891 | break; | |
5f81b1de RH |
12892 | case 0x02: /* SMLAL, SMLAL2 */ |
12893 | case 0x12: /* UMLAL, UMLAL2 */ | |
12894 | case 0x06: /* SMLSL, SMLSL2 */ | |
12895 | case 0x16: /* UMLSL, UMLSL2 */ | |
12896 | case 0x0a: /* SMULL, SMULL2 */ | |
12897 | case 0x1a: /* UMULL, UMULL2 */ | |
9f82e0ff PM |
12898 | if (is_scalar) { |
12899 | unallocated_encoding(s); | |
12900 | return; | |
12901 | } | |
f5e51e7f PM |
12902 | is_long = true; |
12903 | break; | |
5f81b1de RH |
12904 | case 0x03: /* SQDMLAL, SQDMLAL2 */ |
12905 | case 0x07: /* SQDMLSL, SQDMLSL2 */ | |
12906 | case 0x0b: /* SQDMULL, SQDMULL2 */ | |
f5e51e7f | 12907 | is_long = true; |
f5e51e7f | 12908 | break; |
5f81b1de RH |
12909 | case 0x0c: /* SQDMULH */ |
12910 | case 0x0d: /* SQRDMULH */ | |
9f82e0ff | 12911 | break; |
5f81b1de RH |
12912 | case 0x01: /* FMLA */ |
12913 | case 0x05: /* FMLS */ | |
12914 | case 0x09: /* FMUL */ | |
12915 | case 0x19: /* FMULX */ | |
d17b7cdc | 12916 | is_fp = 1; |
f5e51e7f | 12917 | break; |
d345df7a RH |
12918 | case 0x1d: /* SQRDMLAH */ |
12919 | case 0x1f: /* SQRDMLSH */ | |
962fcbf2 | 12920 | if (!dc_isar_feature(aa64_rdm, s)) { |
d345df7a RH |
12921 | unallocated_encoding(s); |
12922 | return; | |
12923 | } | |
12924 | break; | |
26c470a7 RH |
12925 | case 0x0e: /* SDOT */ |
12926 | case 0x1e: /* UDOT */ | |
4977986c | 12927 | if (is_scalar || size != MO_32 || !dc_isar_feature(aa64_dp, s)) { |
26c470a7 RH |
12928 | unallocated_encoding(s); |
12929 | return; | |
12930 | } | |
12931 | break; | |
d17b7cdc RH |
12932 | case 0x11: /* FCMLA #0 */ |
12933 | case 0x13: /* FCMLA #90 */ | |
12934 | case 0x15: /* FCMLA #180 */ | |
12935 | case 0x17: /* FCMLA #270 */ | |
4dfabb6d | 12936 | if (is_scalar || !dc_isar_feature(aa64_fcma, s)) { |
d17b7cdc RH |
12937 | unallocated_encoding(s); |
12938 | return; | |
12939 | } | |
12940 | is_fp = 2; | |
12941 | break; | |
0caa5af8 RH |
12942 | case 0x00: /* FMLAL */ |
12943 | case 0x04: /* FMLSL */ | |
12944 | case 0x18: /* FMLAL2 */ | |
12945 | case 0x1c: /* FMLSL2 */ | |
12946 | if (is_scalar || size != MO_32 || !dc_isar_feature(aa64_fhm, s)) { | |
12947 | unallocated_encoding(s); | |
12948 | return; | |
12949 | } | |
12950 | size = MO_16; | |
12951 | /* is_fp, but we pass cpu_env not fp_status. */ | |
12952 | break; | |
f5e51e7f PM |
12953 | default: |
12954 | unallocated_encoding(s); | |
12955 | return; | |
12956 | } | |
12957 | ||
d17b7cdc RH |
12958 | switch (is_fp) { |
12959 | case 1: /* normal fp */ | |
14776ab5 | 12960 | /* convert insn encoded size to MemOp size */ |
5d265064 | 12961 | switch (size) { |
449f264b | 12962 | case 0: /* half-precision */ |
5d265064 | 12963 | size = MO_16; |
d17b7cdc | 12964 | is_fp16 = true; |
449f264b RH |
12965 | break; |
12966 | case MO_32: /* single precision */ | |
12967 | case MO_64: /* double precision */ | |
12968 | break; | |
12969 | default: | |
5d265064 AB |
12970 | unallocated_encoding(s); |
12971 | return; | |
f5e51e7f | 12972 | } |
d17b7cdc RH |
12973 | break; |
12974 | ||
12975 | case 2: /* complex fp */ | |
12976 | /* Each indexable element is a complex pair. */ | |
eaefb97a | 12977 | size += 1; |
d17b7cdc RH |
12978 | switch (size) { |
12979 | case MO_32: | |
12980 | if (h && !is_q) { | |
12981 | unallocated_encoding(s); | |
12982 | return; | |
12983 | } | |
12984 | is_fp16 = true; | |
12985 | break; | |
12986 | case MO_64: | |
12987 | break; | |
12988 | default: | |
12989 | unallocated_encoding(s); | |
12990 | return; | |
12991 | } | |
12992 | break; | |
12993 | ||
12994 | default: /* integer */ | |
f5e51e7f | 12995 | switch (size) { |
449f264b RH |
12996 | case MO_8: |
12997 | case MO_64: | |
f5e51e7f PM |
12998 | unallocated_encoding(s); |
12999 | return; | |
13000 | } | |
d17b7cdc RH |
13001 | break; |
13002 | } | |
5763190f | 13003 | if (is_fp16 && !dc_isar_feature(aa64_fp16, s)) { |
d17b7cdc RH |
13004 | unallocated_encoding(s); |
13005 | return; | |
f5e51e7f PM |
13006 | } |
13007 | ||
14776ab5 | 13008 | /* Given MemOp size, adjust register and indexing. */ |
449f264b RH |
13009 | switch (size) { |
13010 | case MO_16: | |
13011 | index = h << 2 | l << 1 | m; | |
13012 | break; | |
13013 | case MO_32: | |
13014 | index = h << 1 | l; | |
13015 | rm |= m << 4; | |
13016 | break; | |
13017 | case MO_64: | |
13018 | if (l || !is_q) { | |
13019 | unallocated_encoding(s); | |
13020 | return; | |
13021 | } | |
13022 | index = h; | |
13023 | rm |= m << 4; | |
13024 | break; | |
13025 | default: | |
13026 | g_assert_not_reached(); | |
13027 | } | |
13028 | ||
8c6afa6a PM |
13029 | if (!fp_access_check(s)) { |
13030 | return; | |
13031 | } | |
13032 | ||
f5e51e7f | 13033 | if (is_fp) { |
5d265064 | 13034 | fpst = get_fpstatus_ptr(is_fp16); |
f5e51e7f | 13035 | } else { |
f764718d | 13036 | fpst = NULL; |
f5e51e7f PM |
13037 | } |
13038 | ||
d17b7cdc | 13039 | switch (16 * u + opcode) { |
26c470a7 RH |
13040 | case 0x0e: /* SDOT */ |
13041 | case 0x1e: /* UDOT */ | |
13042 | gen_gvec_op3_ool(s, is_q, rd, rn, rm, index, | |
13043 | u ? gen_helper_gvec_udot_idx_b | |
13044 | : gen_helper_gvec_sdot_idx_b); | |
13045 | return; | |
d17b7cdc RH |
13046 | case 0x11: /* FCMLA #0 */ |
13047 | case 0x13: /* FCMLA #90 */ | |
13048 | case 0x15: /* FCMLA #180 */ | |
13049 | case 0x17: /* FCMLA #270 */ | |
2cc99919 RH |
13050 | { |
13051 | int rot = extract32(insn, 13, 2); | |
13052 | int data = (index << 2) | rot; | |
13053 | tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd), | |
13054 | vec_full_reg_offset(s, rn), | |
13055 | vec_full_reg_offset(s, rm), fpst, | |
13056 | is_q ? 16 : 8, vec_full_reg_size(s), data, | |
13057 | size == MO_64 | |
13058 | ? gen_helper_gvec_fcmlas_idx | |
13059 | : gen_helper_gvec_fcmlah_idx); | |
13060 | tcg_temp_free_ptr(fpst); | |
13061 | } | |
d17b7cdc | 13062 | return; |
0caa5af8 RH |
13063 | |
13064 | case 0x00: /* FMLAL */ | |
13065 | case 0x04: /* FMLSL */ | |
13066 | case 0x18: /* FMLAL2 */ | |
13067 | case 0x1c: /* FMLSL2 */ | |
13068 | { | |
13069 | int is_s = extract32(opcode, 2, 1); | |
13070 | int is_2 = u; | |
13071 | int data = (index << 2) | (is_2 << 1) | is_s; | |
13072 | tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd), | |
13073 | vec_full_reg_offset(s, rn), | |
13074 | vec_full_reg_offset(s, rm), cpu_env, | |
13075 | is_q ? 16 : 8, vec_full_reg_size(s), | |
13076 | data, gen_helper_gvec_fmlal_idx_a64); | |
13077 | } | |
13078 | return; | |
d17b7cdc RH |
13079 | } |
13080 | ||
f5e51e7f PM |
13081 | if (size == 3) { |
13082 | TCGv_i64 tcg_idx = tcg_temp_new_i64(); | |
13083 | int pass; | |
13084 | ||
13085 | assert(is_fp && is_q && !is_long); | |
13086 | ||
13087 | read_vec_element(s, tcg_idx, rm, index, MO_64); | |
13088 | ||
9f82e0ff | 13089 | for (pass = 0; pass < (is_scalar ? 1 : 2); pass++) { |
f5e51e7f PM |
13090 | TCGv_i64 tcg_op = tcg_temp_new_i64(); |
13091 | TCGv_i64 tcg_res = tcg_temp_new_i64(); | |
13092 | ||
13093 | read_vec_element(s, tcg_op, rn, pass, MO_64); | |
13094 | ||
5f81b1de RH |
13095 | switch (16 * u + opcode) { |
13096 | case 0x05: /* FMLS */ | |
f5e51e7f PM |
13097 | /* As usual for ARM, separate negation for fused multiply-add */ |
13098 | gen_helper_vfp_negd(tcg_op, tcg_op); | |
13099 | /* fall through */ | |
5f81b1de | 13100 | case 0x01: /* FMLA */ |
f5e51e7f PM |
13101 | read_vec_element(s, tcg_res, rd, pass, MO_64); |
13102 | gen_helper_vfp_muladdd(tcg_res, tcg_op, tcg_idx, tcg_res, fpst); | |
13103 | break; | |
5f81b1de RH |
13104 | case 0x09: /* FMUL */ |
13105 | gen_helper_vfp_muld(tcg_res, tcg_op, tcg_idx, fpst); | |
13106 | break; | |
13107 | case 0x19: /* FMULX */ | |
13108 | gen_helper_vfp_mulxd(tcg_res, tcg_op, tcg_idx, fpst); | |
f5e51e7f PM |
13109 | break; |
13110 | default: | |
13111 | g_assert_not_reached(); | |
13112 | } | |
13113 | ||
13114 | write_vec_element(s, tcg_res, rd, pass, MO_64); | |
13115 | tcg_temp_free_i64(tcg_op); | |
13116 | tcg_temp_free_i64(tcg_res); | |
13117 | } | |
13118 | ||
13119 | tcg_temp_free_i64(tcg_idx); | |
4ff55bcb | 13120 | clear_vec_high(s, !is_scalar, rd); |
f5e51e7f | 13121 | } else if (!is_long) { |
9f82e0ff PM |
13122 | /* 32 bit floating point, or 16 or 32 bit integer. |
13123 | * For the 16 bit scalar case we use the usual Neon helpers and | |
13124 | * rely on the fact that 0 op 0 == 0 with no side effects. | |
13125 | */ | |
f5e51e7f | 13126 | TCGv_i32 tcg_idx = tcg_temp_new_i32(); |
9f82e0ff PM |
13127 | int pass, maxpasses; |
13128 | ||
13129 | if (is_scalar) { | |
13130 | maxpasses = 1; | |
13131 | } else { | |
13132 | maxpasses = is_q ? 4 : 2; | |
13133 | } | |
f5e51e7f PM |
13134 | |
13135 | read_vec_element_i32(s, tcg_idx, rm, index, size); | |
13136 | ||
9f82e0ff | 13137 | if (size == 1 && !is_scalar) { |
f5e51e7f PM |
13138 | /* The simplest way to handle the 16x16 indexed ops is to duplicate |
13139 | * the index into both halves of the 32 bit tcg_idx and then use | |
13140 | * the usual Neon helpers. | |
13141 | */ | |
13142 | tcg_gen_deposit_i32(tcg_idx, tcg_idx, tcg_idx, 16, 16); | |
13143 | } | |
13144 | ||
9f82e0ff | 13145 | for (pass = 0; pass < maxpasses; pass++) { |
f5e51e7f PM |
13146 | TCGv_i32 tcg_op = tcg_temp_new_i32(); |
13147 | TCGv_i32 tcg_res = tcg_temp_new_i32(); | |
13148 | ||
9f82e0ff | 13149 | read_vec_element_i32(s, tcg_op, rn, pass, is_scalar ? size : MO_32); |
f5e51e7f | 13150 | |
5f81b1de RH |
13151 | switch (16 * u + opcode) { |
13152 | case 0x08: /* MUL */ | |
13153 | case 0x10: /* MLA */ | |
13154 | case 0x14: /* MLS */ | |
f5e51e7f PM |
13155 | { |
13156 | static NeonGenTwoOpFn * const fns[2][2] = { | |
13157 | { gen_helper_neon_add_u16, gen_helper_neon_sub_u16 }, | |
13158 | { tcg_gen_add_i32, tcg_gen_sub_i32 }, | |
13159 | }; | |
13160 | NeonGenTwoOpFn *genfn; | |
13161 | bool is_sub = opcode == 0x4; | |
13162 | ||
13163 | if (size == 1) { | |
13164 | gen_helper_neon_mul_u16(tcg_res, tcg_op, tcg_idx); | |
13165 | } else { | |
13166 | tcg_gen_mul_i32(tcg_res, tcg_op, tcg_idx); | |
13167 | } | |
13168 | if (opcode == 0x8) { | |
13169 | break; | |
13170 | } | |
13171 | read_vec_element_i32(s, tcg_op, rd, pass, MO_32); | |
13172 | genfn = fns[size - 1][is_sub]; | |
13173 | genfn(tcg_res, tcg_op, tcg_res); | |
13174 | break; | |
13175 | } | |
5f81b1de RH |
13176 | case 0x05: /* FMLS */ |
13177 | case 0x01: /* FMLA */ | |
5d265064 AB |
13178 | read_vec_element_i32(s, tcg_res, rd, pass, |
13179 | is_scalar ? size : MO_32); | |
13180 | switch (size) { | |
13181 | case 1: | |
13182 | if (opcode == 0x5) { | |
13183 | /* As usual for ARM, separate negation for fused | |
13184 | * multiply-add */ | |
13185 | tcg_gen_xori_i32(tcg_op, tcg_op, 0x80008000); | |
13186 | } | |
6089030c AB |
13187 | if (is_scalar) { |
13188 | gen_helper_advsimd_muladdh(tcg_res, tcg_op, tcg_idx, | |
13189 | tcg_res, fpst); | |
13190 | } else { | |
13191 | gen_helper_advsimd_muladd2h(tcg_res, tcg_op, tcg_idx, | |
13192 | tcg_res, fpst); | |
13193 | } | |
5d265064 AB |
13194 | break; |
13195 | case 2: | |
13196 | if (opcode == 0x5) { | |
13197 | /* As usual for ARM, separate negation for | |
13198 | * fused multiply-add */ | |
13199 | tcg_gen_xori_i32(tcg_op, tcg_op, 0x80000000); | |
13200 | } | |
13201 | gen_helper_vfp_muladds(tcg_res, tcg_op, tcg_idx, | |
13202 | tcg_res, fpst); | |
13203 | break; | |
13204 | default: | |
13205 | g_assert_not_reached(); | |
13206 | } | |
f5e51e7f | 13207 | break; |
5f81b1de | 13208 | case 0x09: /* FMUL */ |
5d265064 AB |
13209 | switch (size) { |
13210 | case 1: | |
5f81b1de RH |
13211 | if (is_scalar) { |
13212 | gen_helper_advsimd_mulh(tcg_res, tcg_op, | |
13213 | tcg_idx, fpst); | |
5d265064 | 13214 | } else { |
5f81b1de RH |
13215 | gen_helper_advsimd_mul2h(tcg_res, tcg_op, |
13216 | tcg_idx, fpst); | |
5d265064 AB |
13217 | } |
13218 | break; | |
13219 | case 2: | |
5f81b1de RH |
13220 | gen_helper_vfp_muls(tcg_res, tcg_op, tcg_idx, fpst); |
13221 | break; | |
13222 | default: | |
13223 | g_assert_not_reached(); | |
13224 | } | |
13225 | break; | |
13226 | case 0x19: /* FMULX */ | |
13227 | switch (size) { | |
13228 | case 1: | |
13229 | if (is_scalar) { | |
13230 | gen_helper_advsimd_mulxh(tcg_res, tcg_op, | |
13231 | tcg_idx, fpst); | |
5d265064 | 13232 | } else { |
5f81b1de RH |
13233 | gen_helper_advsimd_mulx2h(tcg_res, tcg_op, |
13234 | tcg_idx, fpst); | |
5d265064 AB |
13235 | } |
13236 | break; | |
5f81b1de RH |
13237 | case 2: |
13238 | gen_helper_vfp_mulxs(tcg_res, tcg_op, tcg_idx, fpst); | |
13239 | break; | |
5d265064 AB |
13240 | default: |
13241 | g_assert_not_reached(); | |
f5e51e7f PM |
13242 | } |
13243 | break; | |
5f81b1de | 13244 | case 0x0c: /* SQDMULH */ |
f5e51e7f PM |
13245 | if (size == 1) { |
13246 | gen_helper_neon_qdmulh_s16(tcg_res, cpu_env, | |
13247 | tcg_op, tcg_idx); | |
13248 | } else { | |
13249 | gen_helper_neon_qdmulh_s32(tcg_res, cpu_env, | |
13250 | tcg_op, tcg_idx); | |
13251 | } | |
13252 | break; | |
5f81b1de | 13253 | case 0x0d: /* SQRDMULH */ |
f5e51e7f PM |
13254 | if (size == 1) { |
13255 | gen_helper_neon_qrdmulh_s16(tcg_res, cpu_env, | |
13256 | tcg_op, tcg_idx); | |
13257 | } else { | |
13258 | gen_helper_neon_qrdmulh_s32(tcg_res, cpu_env, | |
13259 | tcg_op, tcg_idx); | |
13260 | } | |
13261 | break; | |
d345df7a RH |
13262 | case 0x1d: /* SQRDMLAH */ |
13263 | read_vec_element_i32(s, tcg_res, rd, pass, | |
13264 | is_scalar ? size : MO_32); | |
13265 | if (size == 1) { | |
13266 | gen_helper_neon_qrdmlah_s16(tcg_res, cpu_env, | |
13267 | tcg_op, tcg_idx, tcg_res); | |
13268 | } else { | |
13269 | gen_helper_neon_qrdmlah_s32(tcg_res, cpu_env, | |
13270 | tcg_op, tcg_idx, tcg_res); | |
13271 | } | |
13272 | break; | |
13273 | case 0x1f: /* SQRDMLSH */ | |
13274 | read_vec_element_i32(s, tcg_res, rd, pass, | |
13275 | is_scalar ? size : MO_32); | |
13276 | if (size == 1) { | |
13277 | gen_helper_neon_qrdmlsh_s16(tcg_res, cpu_env, | |
13278 | tcg_op, tcg_idx, tcg_res); | |
13279 | } else { | |
13280 | gen_helper_neon_qrdmlsh_s32(tcg_res, cpu_env, | |
13281 | tcg_op, tcg_idx, tcg_res); | |
13282 | } | |
13283 | break; | |
f5e51e7f PM |
13284 | default: |
13285 | g_assert_not_reached(); | |
13286 | } | |
13287 | ||
9f82e0ff PM |
13288 | if (is_scalar) { |
13289 | write_fp_sreg(s, rd, tcg_res); | |
13290 | } else { | |
13291 | write_vec_element_i32(s, tcg_res, rd, pass, MO_32); | |
13292 | } | |
13293 | ||
f5e51e7f PM |
13294 | tcg_temp_free_i32(tcg_op); |
13295 | tcg_temp_free_i32(tcg_res); | |
13296 | } | |
13297 | ||
13298 | tcg_temp_free_i32(tcg_idx); | |
4ff55bcb | 13299 | clear_vec_high(s, is_q, rd); |
f5e51e7f PM |
13300 | } else { |
13301 | /* long ops: 16x16->32 or 32x32->64 */ | |
c44ad1fd PM |
13302 | TCGv_i64 tcg_res[2]; |
13303 | int pass; | |
13304 | bool satop = extract32(opcode, 0, 1); | |
14776ab5 | 13305 | MemOp memop = MO_32; |
c44ad1fd PM |
13306 | |
13307 | if (satop || !u) { | |
13308 | memop |= MO_SIGN; | |
13309 | } | |
13310 | ||
13311 | if (size == 2) { | |
13312 | TCGv_i64 tcg_idx = tcg_temp_new_i64(); | |
13313 | ||
13314 | read_vec_element(s, tcg_idx, rm, index, memop); | |
13315 | ||
9f82e0ff | 13316 | for (pass = 0; pass < (is_scalar ? 1 : 2); pass++) { |
c44ad1fd PM |
13317 | TCGv_i64 tcg_op = tcg_temp_new_i64(); |
13318 | TCGv_i64 tcg_passres; | |
9f82e0ff | 13319 | int passelt; |
c44ad1fd | 13320 | |
9f82e0ff PM |
13321 | if (is_scalar) { |
13322 | passelt = 0; | |
13323 | } else { | |
13324 | passelt = pass + (is_q * 2); | |
13325 | } | |
13326 | ||
13327 | read_vec_element(s, tcg_op, rn, passelt, memop); | |
c44ad1fd PM |
13328 | |
13329 | tcg_res[pass] = tcg_temp_new_i64(); | |
13330 | ||
13331 | if (opcode == 0xa || opcode == 0xb) { | |
13332 | /* Non-accumulating ops */ | |
13333 | tcg_passres = tcg_res[pass]; | |
13334 | } else { | |
13335 | tcg_passres = tcg_temp_new_i64(); | |
13336 | } | |
13337 | ||
13338 | tcg_gen_mul_i64(tcg_passres, tcg_op, tcg_idx); | |
13339 | tcg_temp_free_i64(tcg_op); | |
13340 | ||
13341 | if (satop) { | |
13342 | /* saturating, doubling */ | |
13343 | gen_helper_neon_addl_saturate_s64(tcg_passres, cpu_env, | |
13344 | tcg_passres, tcg_passres); | |
13345 | } | |
13346 | ||
13347 | if (opcode == 0xa || opcode == 0xb) { | |
13348 | continue; | |
13349 | } | |
13350 | ||
13351 | /* Accumulating op: handle accumulate step */ | |
13352 | read_vec_element(s, tcg_res[pass], rd, pass, MO_64); | |
13353 | ||
13354 | switch (opcode) { | |
13355 | case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */ | |
13356 | tcg_gen_add_i64(tcg_res[pass], tcg_res[pass], tcg_passres); | |
13357 | break; | |
13358 | case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */ | |
13359 | tcg_gen_sub_i64(tcg_res[pass], tcg_res[pass], tcg_passres); | |
13360 | break; | |
13361 | case 0x7: /* SQDMLSL, SQDMLSL2 */ | |
13362 | tcg_gen_neg_i64(tcg_passres, tcg_passres); | |
13363 | /* fall through */ | |
13364 | case 0x3: /* SQDMLAL, SQDMLAL2 */ | |
13365 | gen_helper_neon_addl_saturate_s64(tcg_res[pass], cpu_env, | |
13366 | tcg_res[pass], | |
13367 | tcg_passres); | |
13368 | break; | |
13369 | default: | |
13370 | g_assert_not_reached(); | |
13371 | } | |
13372 | tcg_temp_free_i64(tcg_passres); | |
13373 | } | |
13374 | tcg_temp_free_i64(tcg_idx); | |
9f82e0ff | 13375 | |
4ff55bcb | 13376 | clear_vec_high(s, !is_scalar, rd); |
c44ad1fd PM |
13377 | } else { |
13378 | TCGv_i32 tcg_idx = tcg_temp_new_i32(); | |
13379 | ||
13380 | assert(size == 1); | |
13381 | read_vec_element_i32(s, tcg_idx, rm, index, size); | |
13382 | ||
9f82e0ff PM |
13383 | if (!is_scalar) { |
13384 | /* The simplest way to handle the 16x16 indexed ops is to | |
13385 | * duplicate the index into both halves of the 32 bit tcg_idx | |
13386 | * and then use the usual Neon helpers. | |
13387 | */ | |
13388 | tcg_gen_deposit_i32(tcg_idx, tcg_idx, tcg_idx, 16, 16); | |
13389 | } | |
c44ad1fd | 13390 | |
9f82e0ff | 13391 | for (pass = 0; pass < (is_scalar ? 1 : 2); pass++) { |
c44ad1fd PM |
13392 | TCGv_i32 tcg_op = tcg_temp_new_i32(); |
13393 | TCGv_i64 tcg_passres; | |
13394 | ||
9f82e0ff PM |
13395 | if (is_scalar) { |
13396 | read_vec_element_i32(s, tcg_op, rn, pass, size); | |
13397 | } else { | |
13398 | read_vec_element_i32(s, tcg_op, rn, | |
13399 | pass + (is_q * 2), MO_32); | |
13400 | } | |
13401 | ||
c44ad1fd PM |
13402 | tcg_res[pass] = tcg_temp_new_i64(); |
13403 | ||
13404 | if (opcode == 0xa || opcode == 0xb) { | |
13405 | /* Non-accumulating ops */ | |
13406 | tcg_passres = tcg_res[pass]; | |
13407 | } else { | |
13408 | tcg_passres = tcg_temp_new_i64(); | |
13409 | } | |
13410 | ||
13411 | if (memop & MO_SIGN) { | |
13412 | gen_helper_neon_mull_s16(tcg_passres, tcg_op, tcg_idx); | |
13413 | } else { | |
13414 | gen_helper_neon_mull_u16(tcg_passres, tcg_op, tcg_idx); | |
13415 | } | |
13416 | if (satop) { | |
13417 | gen_helper_neon_addl_saturate_s32(tcg_passres, cpu_env, | |
13418 | tcg_passres, tcg_passres); | |
13419 | } | |
13420 | tcg_temp_free_i32(tcg_op); | |
13421 | ||
13422 | if (opcode == 0xa || opcode == 0xb) { | |
13423 | continue; | |
13424 | } | |
13425 | ||
13426 | /* Accumulating op: handle accumulate step */ | |
13427 | read_vec_element(s, tcg_res[pass], rd, pass, MO_64); | |
13428 | ||
13429 | switch (opcode) { | |
13430 | case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */ | |
13431 | gen_helper_neon_addl_u32(tcg_res[pass], tcg_res[pass], | |
13432 | tcg_passres); | |
13433 | break; | |
13434 | case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */ | |
13435 | gen_helper_neon_subl_u32(tcg_res[pass], tcg_res[pass], | |
13436 | tcg_passres); | |
13437 | break; | |
13438 | case 0x7: /* SQDMLSL, SQDMLSL2 */ | |
13439 | gen_helper_neon_negl_u32(tcg_passres, tcg_passres); | |
13440 | /* fall through */ | |
13441 | case 0x3: /* SQDMLAL, SQDMLAL2 */ | |
13442 | gen_helper_neon_addl_saturate_s32(tcg_res[pass], cpu_env, | |
13443 | tcg_res[pass], | |
13444 | tcg_passres); | |
13445 | break; | |
13446 | default: | |
13447 | g_assert_not_reached(); | |
13448 | } | |
13449 | tcg_temp_free_i64(tcg_passres); | |
13450 | } | |
13451 | tcg_temp_free_i32(tcg_idx); | |
9f82e0ff PM |
13452 | |
13453 | if (is_scalar) { | |
13454 | tcg_gen_ext32u_i64(tcg_res[0], tcg_res[0]); | |
13455 | } | |
13456 | } | |
13457 | ||
13458 | if (is_scalar) { | |
13459 | tcg_res[1] = tcg_const_i64(0); | |
c44ad1fd PM |
13460 | } |
13461 | ||
13462 | for (pass = 0; pass < 2; pass++) { | |
13463 | write_vec_element(s, tcg_res[pass], rd, pass, MO_64); | |
13464 | tcg_temp_free_i64(tcg_res[pass]); | |
13465 | } | |
f5e51e7f PM |
13466 | } |
13467 | ||
f764718d | 13468 | if (fpst) { |
f5e51e7f PM |
13469 | tcg_temp_free_ptr(fpst); |
13470 | } | |
384b26fb AB |
13471 | } |
13472 | ||
4ce31af4 | 13473 | /* Crypto AES |
384b26fb AB |
13474 | * 31 24 23 22 21 17 16 12 11 10 9 5 4 0 |
13475 | * +-----------------+------+-----------+--------+-----+------+------+ | |
13476 | * | 0 1 0 0 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd | | |
13477 | * +-----------------+------+-----------+--------+-----+------+------+ | |
13478 | */ | |
13479 | static void disas_crypto_aes(DisasContext *s, uint32_t insn) | |
13480 | { | |
5acc765c PM |
13481 | int size = extract32(insn, 22, 2); |
13482 | int opcode = extract32(insn, 12, 5); | |
13483 | int rn = extract32(insn, 5, 5); | |
13484 | int rd = extract32(insn, 0, 5); | |
13485 | int decrypt; | |
a04b68e1 RH |
13486 | gen_helper_gvec_2 *genfn2 = NULL; |
13487 | gen_helper_gvec_3 *genfn3 = NULL; | |
5acc765c | 13488 | |
962fcbf2 | 13489 | if (!dc_isar_feature(aa64_aes, s) || size != 0) { |
5acc765c PM |
13490 | unallocated_encoding(s); |
13491 | return; | |
13492 | } | |
13493 | ||
13494 | switch (opcode) { | |
13495 | case 0x4: /* AESE */ | |
13496 | decrypt = 0; | |
a04b68e1 | 13497 | genfn3 = gen_helper_crypto_aese; |
5acc765c PM |
13498 | break; |
13499 | case 0x6: /* AESMC */ | |
13500 | decrypt = 0; | |
a04b68e1 | 13501 | genfn2 = gen_helper_crypto_aesmc; |
5acc765c PM |
13502 | break; |
13503 | case 0x5: /* AESD */ | |
13504 | decrypt = 1; | |
a04b68e1 | 13505 | genfn3 = gen_helper_crypto_aese; |
5acc765c PM |
13506 | break; |
13507 | case 0x7: /* AESIMC */ | |
13508 | decrypt = 1; | |
a04b68e1 | 13509 | genfn2 = gen_helper_crypto_aesmc; |
5acc765c PM |
13510 | break; |
13511 | default: | |
13512 | unallocated_encoding(s); | |
13513 | return; | |
13514 | } | |
13515 | ||
a4f5c5b7 NR |
13516 | if (!fp_access_check(s)) { |
13517 | return; | |
13518 | } | |
a04b68e1 RH |
13519 | if (genfn2) { |
13520 | gen_gvec_op2_ool(s, true, rd, rn, decrypt, genfn2); | |
13521 | } else { | |
13522 | gen_gvec_op3_ool(s, true, rd, rd, rn, decrypt, genfn3); | |
13523 | } | |
384b26fb AB |
13524 | } |
13525 | ||
4ce31af4 | 13526 | /* Crypto three-reg SHA |
384b26fb AB |
13527 | * 31 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0 |
13528 | * +-----------------+------+---+------+---+--------+-----+------+------+ | |
13529 | * | 0 1 0 1 1 1 1 0 | size | 0 | Rm | 0 | opcode | 0 0 | Rn | Rd | | |
13530 | * +-----------------+------+---+------+---+--------+-----+------+------+ | |
13531 | */ | |
13532 | static void disas_crypto_three_reg_sha(DisasContext *s, uint32_t insn) | |
13533 | { | |
be56f04e PM |
13534 | int size = extract32(insn, 22, 2); |
13535 | int opcode = extract32(insn, 12, 3); | |
13536 | int rm = extract32(insn, 16, 5); | |
13537 | int rn = extract32(insn, 5, 5); | |
13538 | int rd = extract32(insn, 0, 5); | |
effa992f | 13539 | gen_helper_gvec_3 *genfn; |
962fcbf2 | 13540 | bool feature; |
be56f04e PM |
13541 | |
13542 | if (size != 0) { | |
13543 | unallocated_encoding(s); | |
13544 | return; | |
13545 | } | |
13546 | ||
13547 | switch (opcode) { | |
13548 | case 0: /* SHA1C */ | |
afc8b7d3 RH |
13549 | genfn = gen_helper_crypto_sha1c; |
13550 | feature = dc_isar_feature(aa64_sha1, s); | |
13551 | break; | |
be56f04e | 13552 | case 1: /* SHA1P */ |
afc8b7d3 RH |
13553 | genfn = gen_helper_crypto_sha1p; |
13554 | feature = dc_isar_feature(aa64_sha1, s); | |
13555 | break; | |
be56f04e | 13556 | case 2: /* SHA1M */ |
afc8b7d3 RH |
13557 | genfn = gen_helper_crypto_sha1m; |
13558 | feature = dc_isar_feature(aa64_sha1, s); | |
13559 | break; | |
be56f04e | 13560 | case 3: /* SHA1SU0 */ |
afc8b7d3 | 13561 | genfn = gen_helper_crypto_sha1su0; |
962fcbf2 | 13562 | feature = dc_isar_feature(aa64_sha1, s); |
be56f04e PM |
13563 | break; |
13564 | case 4: /* SHA256H */ | |
13565 | genfn = gen_helper_crypto_sha256h; | |
962fcbf2 | 13566 | feature = dc_isar_feature(aa64_sha256, s); |
be56f04e PM |
13567 | break; |
13568 | case 5: /* SHA256H2 */ | |
13569 | genfn = gen_helper_crypto_sha256h2; | |
962fcbf2 | 13570 | feature = dc_isar_feature(aa64_sha256, s); |
be56f04e PM |
13571 | break; |
13572 | case 6: /* SHA256SU1 */ | |
13573 | genfn = gen_helper_crypto_sha256su1; | |
962fcbf2 | 13574 | feature = dc_isar_feature(aa64_sha256, s); |
be56f04e PM |
13575 | break; |
13576 | default: | |
13577 | unallocated_encoding(s); | |
13578 | return; | |
13579 | } | |
13580 | ||
962fcbf2 | 13581 | if (!feature) { |
be56f04e PM |
13582 | unallocated_encoding(s); |
13583 | return; | |
13584 | } | |
13585 | ||
a4f5c5b7 NR |
13586 | if (!fp_access_check(s)) { |
13587 | return; | |
13588 | } | |
afc8b7d3 | 13589 | gen_gvec_op3_ool(s, true, rd, rn, rm, 0, genfn); |
384b26fb AB |
13590 | } |
13591 | ||
4ce31af4 | 13592 | /* Crypto two-reg SHA |
384b26fb AB |
13593 | * 31 24 23 22 21 17 16 12 11 10 9 5 4 0 |
13594 | * +-----------------+------+-----------+--------+-----+------+------+ | |
13595 | * | 0 1 0 1 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd | | |
13596 | * +-----------------+------+-----------+--------+-----+------+------+ | |
13597 | */ | |
13598 | static void disas_crypto_two_reg_sha(DisasContext *s, uint32_t insn) | |
13599 | { | |
f6fe04d5 PM |
13600 | int size = extract32(insn, 22, 2); |
13601 | int opcode = extract32(insn, 12, 5); | |
13602 | int rn = extract32(insn, 5, 5); | |
13603 | int rd = extract32(insn, 0, 5); | |
effa992f | 13604 | gen_helper_gvec_2 *genfn; |
962fcbf2 | 13605 | bool feature; |
f6fe04d5 PM |
13606 | |
13607 | if (size != 0) { | |
13608 | unallocated_encoding(s); | |
13609 | return; | |
13610 | } | |
13611 | ||
13612 | switch (opcode) { | |
13613 | case 0: /* SHA1H */ | |
962fcbf2 | 13614 | feature = dc_isar_feature(aa64_sha1, s); |
f6fe04d5 PM |
13615 | genfn = gen_helper_crypto_sha1h; |
13616 | break; | |
13617 | case 1: /* SHA1SU1 */ | |
962fcbf2 | 13618 | feature = dc_isar_feature(aa64_sha1, s); |
f6fe04d5 PM |
13619 | genfn = gen_helper_crypto_sha1su1; |
13620 | break; | |
13621 | case 2: /* SHA256SU0 */ | |
962fcbf2 | 13622 | feature = dc_isar_feature(aa64_sha256, s); |
f6fe04d5 PM |
13623 | genfn = gen_helper_crypto_sha256su0; |
13624 | break; | |
13625 | default: | |
13626 | unallocated_encoding(s); | |
13627 | return; | |
13628 | } | |
13629 | ||
962fcbf2 | 13630 | if (!feature) { |
f6fe04d5 PM |
13631 | unallocated_encoding(s); |
13632 | return; | |
13633 | } | |
13634 | ||
a4f5c5b7 NR |
13635 | if (!fp_access_check(s)) { |
13636 | return; | |
13637 | } | |
effa992f | 13638 | gen_gvec_op2_ool(s, true, rd, rn, 0, genfn); |
384b26fb AB |
13639 | } |
13640 | ||
1738860d RH |
13641 | static void gen_rax1_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m) |
13642 | { | |
13643 | tcg_gen_rotli_i64(d, m, 1); | |
13644 | tcg_gen_xor_i64(d, d, n); | |
13645 | } | |
13646 | ||
13647 | static void gen_rax1_vec(unsigned vece, TCGv_vec d, TCGv_vec n, TCGv_vec m) | |
13648 | { | |
13649 | tcg_gen_rotli_vec(vece, d, m, 1); | |
13650 | tcg_gen_xor_vec(vece, d, d, n); | |
13651 | } | |
13652 | ||
13653 | void gen_gvec_rax1(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, | |
13654 | uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz) | |
13655 | { | |
13656 | static const TCGOpcode vecop_list[] = { INDEX_op_rotli_vec, 0 }; | |
13657 | static const GVecGen3 op = { | |
13658 | .fni8 = gen_rax1_i64, | |
13659 | .fniv = gen_rax1_vec, | |
13660 | .opt_opc = vecop_list, | |
13661 | .fno = gen_helper_crypto_rax1, | |
13662 | .vece = MO_64, | |
13663 | }; | |
13664 | tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, opr_sz, max_sz, &op); | |
13665 | } | |
13666 | ||
90b827d1 AB |
13667 | /* Crypto three-reg SHA512 |
13668 | * 31 21 20 16 15 14 13 12 11 10 9 5 4 0 | |
13669 | * +-----------------------+------+---+---+-----+--------+------+------+ | |
13670 | * | 1 1 0 0 1 1 1 0 0 1 1 | Rm | 1 | O | 0 0 | opcode | Rn | Rd | | |
13671 | * +-----------------------+------+---+---+-----+--------+------+------+ | |
13672 | */ | |
13673 | static void disas_crypto_three_reg_sha512(DisasContext *s, uint32_t insn) | |
13674 | { | |
13675 | int opcode = extract32(insn, 10, 2); | |
13676 | int o = extract32(insn, 14, 1); | |
13677 | int rm = extract32(insn, 16, 5); | |
13678 | int rn = extract32(insn, 5, 5); | |
13679 | int rd = extract32(insn, 0, 5); | |
962fcbf2 | 13680 | bool feature; |
a04b68e1 | 13681 | gen_helper_gvec_3 *oolfn = NULL; |
1738860d | 13682 | GVecGen3Fn *gvecfn = NULL; |
90b827d1 AB |
13683 | |
13684 | if (o == 0) { | |
13685 | switch (opcode) { | |
13686 | case 0: /* SHA512H */ | |
962fcbf2 | 13687 | feature = dc_isar_feature(aa64_sha512, s); |
aaffebd6 | 13688 | oolfn = gen_helper_crypto_sha512h; |
90b827d1 AB |
13689 | break; |
13690 | case 1: /* SHA512H2 */ | |
962fcbf2 | 13691 | feature = dc_isar_feature(aa64_sha512, s); |
aaffebd6 | 13692 | oolfn = gen_helper_crypto_sha512h2; |
90b827d1 AB |
13693 | break; |
13694 | case 2: /* SHA512SU1 */ | |
962fcbf2 | 13695 | feature = dc_isar_feature(aa64_sha512, s); |
aaffebd6 | 13696 | oolfn = gen_helper_crypto_sha512su1; |
90b827d1 | 13697 | break; |
cd270ade | 13698 | case 3: /* RAX1 */ |
962fcbf2 | 13699 | feature = dc_isar_feature(aa64_sha3, s); |
1738860d | 13700 | gvecfn = gen_gvec_rax1; |
cd270ade | 13701 | break; |
c7a5e791 PN |
13702 | default: |
13703 | g_assert_not_reached(); | |
90b827d1 AB |
13704 | } |
13705 | } else { | |
80d6f4c6 AB |
13706 | switch (opcode) { |
13707 | case 0: /* SM3PARTW1 */ | |
962fcbf2 | 13708 | feature = dc_isar_feature(aa64_sm3, s); |
aaffebd6 | 13709 | oolfn = gen_helper_crypto_sm3partw1; |
80d6f4c6 AB |
13710 | break; |
13711 | case 1: /* SM3PARTW2 */ | |
962fcbf2 | 13712 | feature = dc_isar_feature(aa64_sm3, s); |
aaffebd6 | 13713 | oolfn = gen_helper_crypto_sm3partw2; |
80d6f4c6 | 13714 | break; |
b6577bcd | 13715 | case 2: /* SM4EKEY */ |
962fcbf2 | 13716 | feature = dc_isar_feature(aa64_sm4, s); |
a04b68e1 | 13717 | oolfn = gen_helper_crypto_sm4ekey; |
b6577bcd | 13718 | break; |
80d6f4c6 AB |
13719 | default: |
13720 | unallocated_encoding(s); | |
13721 | return; | |
13722 | } | |
90b827d1 AB |
13723 | } |
13724 | ||
962fcbf2 | 13725 | if (!feature) { |
90b827d1 AB |
13726 | unallocated_encoding(s); |
13727 | return; | |
13728 | } | |
13729 | ||
13730 | if (!fp_access_check(s)) { | |
13731 | return; | |
13732 | } | |
13733 | ||
a04b68e1 RH |
13734 | if (oolfn) { |
13735 | gen_gvec_op3_ool(s, true, rd, rn, rm, 0, oolfn); | |
1738860d | 13736 | } else { |
aaffebd6 | 13737 | gen_gvec_fn3(s, true, rd, rn, rm, gvecfn, MO_64); |
90b827d1 AB |
13738 | } |
13739 | } | |
13740 | ||
13741 | /* Crypto two-reg SHA512 | |
13742 | * 31 12 11 10 9 5 4 0 | |
13743 | * +-----------------------------------------+--------+------+------+ | |
13744 | * | 1 1 0 0 1 1 1 0 1 1 0 0 0 0 0 0 1 0 0 0 | opcode | Rn | Rd | | |
13745 | * +-----------------------------------------+--------+------+------+ | |
13746 | */ | |
13747 | static void disas_crypto_two_reg_sha512(DisasContext *s, uint32_t insn) | |
13748 | { | |
13749 | int opcode = extract32(insn, 10, 2); | |
13750 | int rn = extract32(insn, 5, 5); | |
13751 | int rd = extract32(insn, 0, 5); | |
962fcbf2 | 13752 | bool feature; |
90b827d1 AB |
13753 | |
13754 | switch (opcode) { | |
13755 | case 0: /* SHA512SU0 */ | |
962fcbf2 | 13756 | feature = dc_isar_feature(aa64_sha512, s); |
90b827d1 | 13757 | break; |
b6577bcd | 13758 | case 1: /* SM4E */ |
962fcbf2 | 13759 | feature = dc_isar_feature(aa64_sm4, s); |
b6577bcd | 13760 | break; |
90b827d1 AB |
13761 | default: |
13762 | unallocated_encoding(s); | |
13763 | return; | |
13764 | } | |
13765 | ||
962fcbf2 | 13766 | if (!feature) { |
90b827d1 AB |
13767 | unallocated_encoding(s); |
13768 | return; | |
13769 | } | |
13770 | ||
13771 | if (!fp_access_check(s)) { | |
13772 | return; | |
13773 | } | |
13774 | ||
aaffebd6 RH |
13775 | switch (opcode) { |
13776 | case 0: /* SHA512SU0 */ | |
13777 | gen_gvec_op2_ool(s, true, rd, rn, 0, gen_helper_crypto_sha512su0); | |
13778 | break; | |
13779 | case 1: /* SM4E */ | |
13780 | gen_gvec_op3_ool(s, true, rd, rd, rn, 0, gen_helper_crypto_sm4e); | |
13781 | break; | |
13782 | default: | |
13783 | g_assert_not_reached(); | |
a04b68e1 | 13784 | } |
90b827d1 AB |
13785 | } |
13786 | ||
cd270ade AB |
13787 | /* Crypto four-register |
13788 | * 31 23 22 21 20 16 15 14 10 9 5 4 0 | |
13789 | * +-------------------+-----+------+---+------+------+------+ | |
13790 | * | 1 1 0 0 1 1 1 0 0 | Op0 | Rm | 0 | Ra | Rn | Rd | | |
13791 | * +-------------------+-----+------+---+------+------+------+ | |
13792 | */ | |
13793 | static void disas_crypto_four_reg(DisasContext *s, uint32_t insn) | |
13794 | { | |
13795 | int op0 = extract32(insn, 21, 2); | |
13796 | int rm = extract32(insn, 16, 5); | |
13797 | int ra = extract32(insn, 10, 5); | |
13798 | int rn = extract32(insn, 5, 5); | |
13799 | int rd = extract32(insn, 0, 5); | |
962fcbf2 | 13800 | bool feature; |
cd270ade AB |
13801 | |
13802 | switch (op0) { | |
13803 | case 0: /* EOR3 */ | |
13804 | case 1: /* BCAX */ | |
962fcbf2 | 13805 | feature = dc_isar_feature(aa64_sha3, s); |
cd270ade | 13806 | break; |
80d6f4c6 | 13807 | case 2: /* SM3SS1 */ |
962fcbf2 | 13808 | feature = dc_isar_feature(aa64_sm3, s); |
80d6f4c6 | 13809 | break; |
cd270ade AB |
13810 | default: |
13811 | unallocated_encoding(s); | |
13812 | return; | |
13813 | } | |
13814 | ||
962fcbf2 | 13815 | if (!feature) { |
cd270ade AB |
13816 | unallocated_encoding(s); |
13817 | return; | |
13818 | } | |
13819 | ||
13820 | if (!fp_access_check(s)) { | |
13821 | return; | |
13822 | } | |
13823 | ||
13824 | if (op0 < 2) { | |
13825 | TCGv_i64 tcg_op1, tcg_op2, tcg_op3, tcg_res[2]; | |
13826 | int pass; | |
13827 | ||
13828 | tcg_op1 = tcg_temp_new_i64(); | |
13829 | tcg_op2 = tcg_temp_new_i64(); | |
13830 | tcg_op3 = tcg_temp_new_i64(); | |
13831 | tcg_res[0] = tcg_temp_new_i64(); | |
13832 | tcg_res[1] = tcg_temp_new_i64(); | |
13833 | ||
13834 | for (pass = 0; pass < 2; pass++) { | |
13835 | read_vec_element(s, tcg_op1, rn, pass, MO_64); | |
13836 | read_vec_element(s, tcg_op2, rm, pass, MO_64); | |
13837 | read_vec_element(s, tcg_op3, ra, pass, MO_64); | |
13838 | ||
13839 | if (op0 == 0) { | |
13840 | /* EOR3 */ | |
13841 | tcg_gen_xor_i64(tcg_res[pass], tcg_op2, tcg_op3); | |
13842 | } else { | |
13843 | /* BCAX */ | |
13844 | tcg_gen_andc_i64(tcg_res[pass], tcg_op2, tcg_op3); | |
13845 | } | |
13846 | tcg_gen_xor_i64(tcg_res[pass], tcg_res[pass], tcg_op1); | |
13847 | } | |
13848 | write_vec_element(s, tcg_res[0], rd, 0, MO_64); | |
13849 | write_vec_element(s, tcg_res[1], rd, 1, MO_64); | |
13850 | ||
13851 | tcg_temp_free_i64(tcg_op1); | |
13852 | tcg_temp_free_i64(tcg_op2); | |
13853 | tcg_temp_free_i64(tcg_op3); | |
13854 | tcg_temp_free_i64(tcg_res[0]); | |
13855 | tcg_temp_free_i64(tcg_res[1]); | |
13856 | } else { | |
80d6f4c6 AB |
13857 | TCGv_i32 tcg_op1, tcg_op2, tcg_op3, tcg_res, tcg_zero; |
13858 | ||
13859 | tcg_op1 = tcg_temp_new_i32(); | |
13860 | tcg_op2 = tcg_temp_new_i32(); | |
13861 | tcg_op3 = tcg_temp_new_i32(); | |
13862 | tcg_res = tcg_temp_new_i32(); | |
13863 | tcg_zero = tcg_const_i32(0); | |
13864 | ||
13865 | read_vec_element_i32(s, tcg_op1, rn, 3, MO_32); | |
13866 | read_vec_element_i32(s, tcg_op2, rm, 3, MO_32); | |
13867 | read_vec_element_i32(s, tcg_op3, ra, 3, MO_32); | |
13868 | ||
13869 | tcg_gen_rotri_i32(tcg_res, tcg_op1, 20); | |
13870 | tcg_gen_add_i32(tcg_res, tcg_res, tcg_op2); | |
13871 | tcg_gen_add_i32(tcg_res, tcg_res, tcg_op3); | |
13872 | tcg_gen_rotri_i32(tcg_res, tcg_res, 25); | |
13873 | ||
13874 | write_vec_element_i32(s, tcg_zero, rd, 0, MO_32); | |
13875 | write_vec_element_i32(s, tcg_zero, rd, 1, MO_32); | |
13876 | write_vec_element_i32(s, tcg_zero, rd, 2, MO_32); | |
13877 | write_vec_element_i32(s, tcg_res, rd, 3, MO_32); | |
13878 | ||
13879 | tcg_temp_free_i32(tcg_op1); | |
13880 | tcg_temp_free_i32(tcg_op2); | |
13881 | tcg_temp_free_i32(tcg_op3); | |
13882 | tcg_temp_free_i32(tcg_res); | |
13883 | tcg_temp_free_i32(tcg_zero); | |
cd270ade AB |
13884 | } |
13885 | } | |
13886 | ||
13887 | /* Crypto XAR | |
13888 | * 31 21 20 16 15 10 9 5 4 0 | |
13889 | * +-----------------------+------+--------+------+------+ | |
13890 | * | 1 1 0 0 1 1 1 0 1 0 0 | Rm | imm6 | Rn | Rd | | |
13891 | * +-----------------------+------+--------+------+------+ | |
13892 | */ | |
13893 | static void disas_crypto_xar(DisasContext *s, uint32_t insn) | |
13894 | { | |
13895 | int rm = extract32(insn, 16, 5); | |
13896 | int imm6 = extract32(insn, 10, 6); | |
13897 | int rn = extract32(insn, 5, 5); | |
13898 | int rd = extract32(insn, 0, 5); | |
13899 | TCGv_i64 tcg_op1, tcg_op2, tcg_res[2]; | |
13900 | int pass; | |
13901 | ||
962fcbf2 | 13902 | if (!dc_isar_feature(aa64_sha3, s)) { |
cd270ade AB |
13903 | unallocated_encoding(s); |
13904 | return; | |
13905 | } | |
13906 | ||
13907 | if (!fp_access_check(s)) { | |
13908 | return; | |
13909 | } | |
13910 | ||
13911 | tcg_op1 = tcg_temp_new_i64(); | |
13912 | tcg_op2 = tcg_temp_new_i64(); | |
13913 | tcg_res[0] = tcg_temp_new_i64(); | |
13914 | tcg_res[1] = tcg_temp_new_i64(); | |
13915 | ||
13916 | for (pass = 0; pass < 2; pass++) { | |
13917 | read_vec_element(s, tcg_op1, rn, pass, MO_64); | |
13918 | read_vec_element(s, tcg_op2, rm, pass, MO_64); | |
13919 | ||
13920 | tcg_gen_xor_i64(tcg_res[pass], tcg_op1, tcg_op2); | |
13921 | tcg_gen_rotri_i64(tcg_res[pass], tcg_res[pass], imm6); | |
13922 | } | |
13923 | write_vec_element(s, tcg_res[0], rd, 0, MO_64); | |
13924 | write_vec_element(s, tcg_res[1], rd, 1, MO_64); | |
13925 | ||
13926 | tcg_temp_free_i64(tcg_op1); | |
13927 | tcg_temp_free_i64(tcg_op2); | |
13928 | tcg_temp_free_i64(tcg_res[0]); | |
13929 | tcg_temp_free_i64(tcg_res[1]); | |
13930 | } | |
13931 | ||
80d6f4c6 AB |
13932 | /* Crypto three-reg imm2 |
13933 | * 31 21 20 16 15 14 13 12 11 10 9 5 4 0 | |
13934 | * +-----------------------+------+-----+------+--------+------+------+ | |
13935 | * | 1 1 0 0 1 1 1 0 0 1 0 | Rm | 1 0 | imm2 | opcode | Rn | Rd | | |
13936 | * +-----------------------+------+-----+------+--------+------+------+ | |
13937 | */ | |
13938 | static void disas_crypto_three_reg_imm2(DisasContext *s, uint32_t insn) | |
13939 | { | |
43fa36c9 RH |
13940 | static gen_helper_gvec_3 * const fns[4] = { |
13941 | gen_helper_crypto_sm3tt1a, gen_helper_crypto_sm3tt1b, | |
13942 | gen_helper_crypto_sm3tt2a, gen_helper_crypto_sm3tt2b, | |
13943 | }; | |
80d6f4c6 AB |
13944 | int opcode = extract32(insn, 10, 2); |
13945 | int imm2 = extract32(insn, 12, 2); | |
13946 | int rm = extract32(insn, 16, 5); | |
13947 | int rn = extract32(insn, 5, 5); | |
13948 | int rd = extract32(insn, 0, 5); | |
80d6f4c6 | 13949 | |
962fcbf2 | 13950 | if (!dc_isar_feature(aa64_sm3, s)) { |
80d6f4c6 AB |
13951 | unallocated_encoding(s); |
13952 | return; | |
13953 | } | |
13954 | ||
13955 | if (!fp_access_check(s)) { | |
13956 | return; | |
13957 | } | |
13958 | ||
43fa36c9 | 13959 | gen_gvec_op3_ool(s, true, rd, rn, rm, imm2, fns[opcode]); |
80d6f4c6 AB |
13960 | } |
13961 | ||
384b26fb AB |
13962 | /* C3.6 Data processing - SIMD, inc Crypto |
13963 | * | |
13964 | * As the decode gets a little complex we are using a table based | |
13965 | * approach for this part of the decode. | |
13966 | */ | |
13967 | static const AArch64DecodeTable data_proc_simd[] = { | |
13968 | /* pattern , mask , fn */ | |
13969 | { 0x0e200400, 0x9f200400, disas_simd_three_reg_same }, | |
e7186d82 | 13970 | { 0x0e008400, 0x9f208400, disas_simd_three_reg_same_extra }, |
384b26fb AB |
13971 | { 0x0e200000, 0x9f200c00, disas_simd_three_reg_diff }, |
13972 | { 0x0e200800, 0x9f3e0c00, disas_simd_two_reg_misc }, | |
13973 | { 0x0e300800, 0x9f3e0c00, disas_simd_across_lanes }, | |
13974 | { 0x0e000400, 0x9fe08400, disas_simd_copy }, | |
9f82e0ff | 13975 | { 0x0f000000, 0x9f000400, disas_simd_indexed }, /* vector indexed */ |
384b26fb AB |
13976 | /* simd_mod_imm decode is a subset of simd_shift_imm, so must precede it */ |
13977 | { 0x0f000400, 0x9ff80400, disas_simd_mod_imm }, | |
13978 | { 0x0f000400, 0x9f800400, disas_simd_shift_imm }, | |
13979 | { 0x0e000000, 0xbf208c00, disas_simd_tb }, | |
13980 | { 0x0e000800, 0xbf208c00, disas_simd_zip_trn }, | |
13981 | { 0x2e000000, 0xbf208400, disas_simd_ext }, | |
13982 | { 0x5e200400, 0xdf200400, disas_simd_scalar_three_reg_same }, | |
d9061ec3 | 13983 | { 0x5e008400, 0xdf208400, disas_simd_scalar_three_reg_same_extra }, |
384b26fb AB |
13984 | { 0x5e200000, 0xdf200c00, disas_simd_scalar_three_reg_diff }, |
13985 | { 0x5e200800, 0xdf3e0c00, disas_simd_scalar_two_reg_misc }, | |
13986 | { 0x5e300800, 0xdf3e0c00, disas_simd_scalar_pairwise }, | |
13987 | { 0x5e000400, 0xdfe08400, disas_simd_scalar_copy }, | |
9f82e0ff | 13988 | { 0x5f000000, 0xdf000400, disas_simd_indexed }, /* scalar indexed */ |
384b26fb AB |
13989 | { 0x5f000400, 0xdf800400, disas_simd_scalar_shift_imm }, |
13990 | { 0x4e280800, 0xff3e0c00, disas_crypto_aes }, | |
13991 | { 0x5e000000, 0xff208c00, disas_crypto_three_reg_sha }, | |
13992 | { 0x5e280800, 0xff3e0c00, disas_crypto_two_reg_sha }, | |
90b827d1 AB |
13993 | { 0xce608000, 0xffe0b000, disas_crypto_three_reg_sha512 }, |
13994 | { 0xcec08000, 0xfffff000, disas_crypto_two_reg_sha512 }, | |
cd270ade AB |
13995 | { 0xce000000, 0xff808000, disas_crypto_four_reg }, |
13996 | { 0xce800000, 0xffe00000, disas_crypto_xar }, | |
80d6f4c6 | 13997 | { 0xce408000, 0xffe0c000, disas_crypto_three_reg_imm2 }, |
376e8d6c | 13998 | { 0x0e400400, 0x9f60c400, disas_simd_three_reg_same_fp16 }, |
5d432be6 | 13999 | { 0x0e780800, 0x8f7e0c00, disas_simd_two_reg_misc_fp16 }, |
7c93b774 | 14000 | { 0x5e400400, 0xdf60c400, disas_simd_scalar_three_reg_same_fp16 }, |
384b26fb AB |
14001 | { 0x00000000, 0x00000000, NULL } |
14002 | }; | |
14003 | ||
faa0ba46 PM |
14004 | static void disas_data_proc_simd(DisasContext *s, uint32_t insn) |
14005 | { | |
14006 | /* Note that this is called with all non-FP cases from | |
14007 | * table C3-6 so it must UNDEF for entries not specifically | |
14008 | * allocated to instructions in that table. | |
14009 | */ | |
384b26fb AB |
14010 | AArch64DecodeFn *fn = lookup_disas_fn(&data_proc_simd[0], insn); |
14011 | if (fn) { | |
14012 | fn(s, insn); | |
14013 | } else { | |
14014 | unallocated_encoding(s); | |
14015 | } | |
faa0ba46 PM |
14016 | } |
14017 | ||
ad7ee8a2 CF |
14018 | /* C3.6 Data processing - SIMD and floating point */ |
14019 | static void disas_data_proc_simd_fp(DisasContext *s, uint32_t insn) | |
14020 | { | |
faa0ba46 PM |
14021 | if (extract32(insn, 28, 1) == 1 && extract32(insn, 30, 1) == 0) { |
14022 | disas_data_proc_fp(s, insn); | |
14023 | } else { | |
14024 | /* SIMD, including crypto */ | |
14025 | disas_data_proc_simd(s, insn); | |
14026 | } | |
ad7ee8a2 CF |
14027 | } |
14028 | ||
51bf0d7a RH |
14029 | /** |
14030 | * is_guarded_page: | |
14031 | * @env: The cpu environment | |
14032 | * @s: The DisasContext | |
14033 | * | |
14034 | * Return true if the page is guarded. | |
14035 | */ | |
14036 | static bool is_guarded_page(CPUARMState *env, DisasContext *s) | |
14037 | { | |
14038 | #ifdef CONFIG_USER_ONLY | |
14039 | return false; /* FIXME */ | |
14040 | #else | |
14041 | uint64_t addr = s->base.pc_first; | |
14042 | int mmu_idx = arm_to_core_mmu_idx(s->mmu_idx); | |
14043 | unsigned int index = tlb_index(env, mmu_idx, addr); | |
14044 | CPUTLBEntry *entry = tlb_entry(env, mmu_idx, addr); | |
14045 | ||
14046 | /* | |
14047 | * We test this immediately after reading an insn, which means | |
14048 | * that any normal page must be in the TLB. The only exception | |
14049 | * would be for executing from flash or device memory, which | |
14050 | * does not retain the TLB entry. | |
14051 | * | |
14052 | * FIXME: Assume false for those, for now. We could use | |
14053 | * arm_cpu_get_phys_page_attrs_debug to re-read the page | |
14054 | * table entry even for that case. | |
14055 | */ | |
14056 | return (tlb_hit(entry->addr_code, addr) && | |
a40ec84e | 14057 | env_tlb(env)->d[mmu_idx].iotlb[index].attrs.target_tlb_bit0); |
51bf0d7a RH |
14058 | #endif |
14059 | } | |
14060 | ||
14061 | /** | |
14062 | * btype_destination_ok: | |
14063 | * @insn: The instruction at the branch destination | |
14064 | * @bt: SCTLR_ELx.BT | |
14065 | * @btype: PSTATE.BTYPE, and is non-zero | |
14066 | * | |
14067 | * On a guarded page, there are a limited number of insns | |
14068 | * that may be present at the branch target: | |
14069 | * - branch target identifiers, | |
14070 | * - paciasp, pacibsp, | |
14071 | * - BRK insn | |
14072 | * - HLT insn | |
14073 | * Anything else causes a Branch Target Exception. | |
14074 | * | |
14075 | * Return true if the branch is compatible, false to raise BTITRAP. | |
14076 | */ | |
14077 | static bool btype_destination_ok(uint32_t insn, bool bt, int btype) | |
14078 | { | |
14079 | if ((insn & 0xfffff01fu) == 0xd503201fu) { | |
14080 | /* HINT space */ | |
14081 | switch (extract32(insn, 5, 7)) { | |
14082 | case 0b011001: /* PACIASP */ | |
14083 | case 0b011011: /* PACIBSP */ | |
14084 | /* | |
14085 | * If SCTLR_ELx.BT, then PACI*SP are not compatible | |
14086 | * with btype == 3. Otherwise all btype are ok. | |
14087 | */ | |
14088 | return !bt || btype != 3; | |
14089 | case 0b100000: /* BTI */ | |
14090 | /* Not compatible with any btype. */ | |
14091 | return false; | |
14092 | case 0b100010: /* BTI c */ | |
14093 | /* Not compatible with btype == 3 */ | |
14094 | return btype != 3; | |
14095 | case 0b100100: /* BTI j */ | |
14096 | /* Not compatible with btype == 2 */ | |
14097 | return btype != 2; | |
14098 | case 0b100110: /* BTI jc */ | |
14099 | /* Compatible with any btype. */ | |
14100 | return true; | |
14101 | } | |
14102 | } else { | |
14103 | switch (insn & 0xffe0001fu) { | |
14104 | case 0xd4200000u: /* BRK */ | |
14105 | case 0xd4400000u: /* HLT */ | |
14106 | /* Give priority to the breakpoint exception. */ | |
14107 | return true; | |
14108 | } | |
14109 | } | |
14110 | return false; | |
14111 | } | |
14112 | ||
ad7ee8a2 | 14113 | /* C3.1 A64 instruction index by encoding */ |
40f860cd | 14114 | static void disas_a64_insn(CPUARMState *env, DisasContext *s) |
14ade10f AG |
14115 | { |
14116 | uint32_t insn; | |
14117 | ||
a0415916 RH |
14118 | s->pc_curr = s->base.pc_next; |
14119 | insn = arm_ldl_code(env, s->base.pc_next, s->sctlr_b); | |
14ade10f | 14120 | s->insn = insn; |
a0415916 | 14121 | s->base.pc_next += 4; |
14ade10f | 14122 | |
90e49638 PM |
14123 | s->fp_access_checked = false; |
14124 | ||
51bf0d7a RH |
14125 | if (dc_isar_feature(aa64_bti, s)) { |
14126 | if (s->base.num_insns == 1) { | |
14127 | /* | |
14128 | * At the first insn of the TB, compute s->guarded_page. | |
14129 | * We delayed computing this until successfully reading | |
14130 | * the first insn of the TB, above. This (mostly) ensures | |
14131 | * that the softmmu tlb entry has been populated, and the | |
14132 | * page table GP bit is available. | |
14133 | * | |
14134 | * Note that we need to compute this even if btype == 0, | |
14135 | * because this value is used for BR instructions later | |
14136 | * where ENV is not available. | |
14137 | */ | |
14138 | s->guarded_page = is_guarded_page(env, s); | |
14139 | ||
14140 | /* First insn can have btype set to non-zero. */ | |
14141 | tcg_debug_assert(s->btype >= 0); | |
14142 | ||
14143 | /* | |
14144 | * Note that the Branch Target Exception has fairly high | |
14145 | * priority -- below debugging exceptions but above most | |
14146 | * everything else. This allows us to handle this now | |
14147 | * instead of waiting until the insn is otherwise decoded. | |
14148 | */ | |
14149 | if (s->btype != 0 | |
14150 | && s->guarded_page | |
14151 | && !btype_destination_ok(insn, s->bt, s->btype)) { | |
a767fac8 RH |
14152 | gen_exception_insn(s, s->pc_curr, EXCP_UDEF, |
14153 | syn_btitrap(s->btype), | |
51bf0d7a RH |
14154 | default_exception_el(s)); |
14155 | return; | |
14156 | } | |
14157 | } else { | |
14158 | /* Not the first insn: btype must be 0. */ | |
14159 | tcg_debug_assert(s->btype == 0); | |
14160 | } | |
14161 | } | |
14162 | ||
ad7ee8a2 | 14163 | switch (extract32(insn, 25, 4)) { |
38388f7e | 14164 | case 0x0: case 0x1: case 0x3: /* UNALLOCATED */ |
14ade10f AG |
14165 | unallocated_encoding(s); |
14166 | break; | |
38388f7e | 14167 | case 0x2: |
cd208a1c | 14168 | if (!dc_isar_feature(aa64_sve, s) || !disas_sve(s, insn)) { |
38388f7e RH |
14169 | unallocated_encoding(s); |
14170 | } | |
14171 | break; | |
ad7ee8a2 CF |
14172 | case 0x8: case 0x9: /* Data processing - immediate */ |
14173 | disas_data_proc_imm(s, insn); | |
14174 | break; | |
14175 | case 0xa: case 0xb: /* Branch, exception generation and system insns */ | |
14176 | disas_b_exc_sys(s, insn); | |
14177 | break; | |
14178 | case 0x4: | |
14179 | case 0x6: | |
14180 | case 0xc: | |
14181 | case 0xe: /* Loads and stores */ | |
14182 | disas_ldst(s, insn); | |
14183 | break; | |
14184 | case 0x5: | |
14185 | case 0xd: /* Data processing - register */ | |
14186 | disas_data_proc_reg(s, insn); | |
14187 | break; | |
14188 | case 0x7: | |
14189 | case 0xf: /* Data processing - SIMD and floating point */ | |
14190 | disas_data_proc_simd_fp(s, insn); | |
14191 | break; | |
14192 | default: | |
14193 | assert(FALSE); /* all 15 cases should be handled above */ | |
14194 | break; | |
14ade10f | 14195 | } |
11e169de AG |
14196 | |
14197 | /* if we allocated any temporaries, free them here */ | |
14198 | free_tmp_a64(s); | |
51bf0d7a RH |
14199 | |
14200 | /* | |
14201 | * After execution of most insns, btype is reset to 0. | |
14202 | * Note that we set btype == -1 when the insn sets btype. | |
14203 | */ | |
14204 | if (s->btype > 0 && s->base.is_jmp != DISAS_NORETURN) { | |
14205 | reset_btype(s); | |
14206 | } | |
40f860cd | 14207 | } |
14ade10f | 14208 | |
b542683d EC |
14209 | static void aarch64_tr_init_disas_context(DisasContextBase *dcbase, |
14210 | CPUState *cpu) | |
40f860cd | 14211 | { |
dcba3a8d | 14212 | DisasContext *dc = container_of(dcbase, DisasContext, base); |
5c039906 | 14213 | CPUARMState *env = cpu->env_ptr; |
2fc0cc0e | 14214 | ARMCPU *arm_cpu = env_archcpu(env); |
aad821ac RH |
14215 | uint32_t tb_flags = dc->base.tb->flags; |
14216 | int bound, core_mmu_idx; | |
40f860cd | 14217 | |
962fcbf2 | 14218 | dc->isar = &arm_cpu->isar; |
40f860cd PM |
14219 | dc->condjmp = 0; |
14220 | ||
14221 | dc->aarch64 = 1; | |
cef9ee70 SS |
14222 | /* If we are coming from secure EL0 in a system with a 32-bit EL3, then |
14223 | * there is no secure EL1, so we route exceptions to EL3. | |
14224 | */ | |
14225 | dc->secure_routed_to_el3 = arm_feature(env, ARM_FEATURE_EL3) && | |
14226 | !arm_el_is_aa64(env, 3); | |
40f860cd | 14227 | dc->thumb = 0; |
f9fd40eb | 14228 | dc->sctlr_b = 0; |
aad821ac | 14229 | dc->be_data = FIELD_EX32(tb_flags, TBFLAG_ANY, BE_DATA) ? MO_BE : MO_LE; |
40f860cd PM |
14230 | dc->condexec_mask = 0; |
14231 | dc->condexec_cond = 0; | |
aad821ac | 14232 | core_mmu_idx = FIELD_EX32(tb_flags, TBFLAG_ANY, MMUIDX); |
20dc67c9 | 14233 | dc->mmu_idx = core_to_aa64_mmu_idx(core_mmu_idx); |
476a4692 | 14234 | dc->tbii = FIELD_EX32(tb_flags, TBFLAG_A64, TBII); |
4a9ee99d | 14235 | dc->tbid = FIELD_EX32(tb_flags, TBFLAG_A64, TBID); |
81ae05fa | 14236 | dc->tcma = FIELD_EX32(tb_flags, TBFLAG_A64, TCMA); |
c1e37810 | 14237 | dc->current_el = arm_mmu_idx_to_el(dc->mmu_idx); |
40f860cd | 14238 | #if !defined(CONFIG_USER_ONLY) |
c1e37810 | 14239 | dc->user = (dc->current_el == 0); |
40f860cd | 14240 | #endif |
aad821ac RH |
14241 | dc->fp_excp_el = FIELD_EX32(tb_flags, TBFLAG_ANY, FPEXC_EL); |
14242 | dc->sve_excp_el = FIELD_EX32(tb_flags, TBFLAG_A64, SVEEXC_EL); | |
14243 | dc->sve_len = (FIELD_EX32(tb_flags, TBFLAG_A64, ZCR_LEN) + 1) * 16; | |
0816ef1b | 14244 | dc->pauth_active = FIELD_EX32(tb_flags, TBFLAG_A64, PAUTH_ACTIVE); |
08f1434a RH |
14245 | dc->bt = FIELD_EX32(tb_flags, TBFLAG_A64, BT); |
14246 | dc->btype = FIELD_EX32(tb_flags, TBFLAG_A64, BTYPE); | |
cc28fc30 | 14247 | dc->unpriv = FIELD_EX32(tb_flags, TBFLAG_A64, UNPRIV); |
81ae05fa RH |
14248 | dc->ata = FIELD_EX32(tb_flags, TBFLAG_A64, ATA); |
14249 | dc->mte_active[0] = FIELD_EX32(tb_flags, TBFLAG_A64, MTE_ACTIVE); | |
14250 | dc->mte_active[1] = FIELD_EX32(tb_flags, TBFLAG_A64, MTE0_ACTIVE); | |
40f860cd PM |
14251 | dc->vec_len = 0; |
14252 | dc->vec_stride = 0; | |
5c039906 | 14253 | dc->cp_regs = arm_cpu->cp_regs; |
a984e42c | 14254 | dc->features = env->features; |
40f860cd | 14255 | |
7ea47fe7 PM |
14256 | /* Single step state. The code-generation logic here is: |
14257 | * SS_ACTIVE == 0: | |
14258 | * generate code with no special handling for single-stepping (except | |
14259 | * that anything that can make us go to SS_ACTIVE == 1 must end the TB; | |
14260 | * this happens anyway because those changes are all system register or | |
14261 | * PSTATE writes). | |
14262 | * SS_ACTIVE == 1, PSTATE.SS == 1: (active-not-pending) | |
14263 | * emit code for one insn | |
14264 | * emit code to clear PSTATE.SS | |
14265 | * emit code to generate software step exception for completed step | |
14266 | * end TB (as usual for having generated an exception) | |
14267 | * SS_ACTIVE == 1, PSTATE.SS == 0: (active-pending) | |
14268 | * emit code to generate a software step exception | |
14269 | * end the TB | |
14270 | */ | |
aad821ac RH |
14271 | dc->ss_active = FIELD_EX32(tb_flags, TBFLAG_ANY, SS_ACTIVE); |
14272 | dc->pstate_ss = FIELD_EX32(tb_flags, TBFLAG_ANY, PSTATE_SS); | |
7ea47fe7 | 14273 | dc->is_ldex = false; |
8bd587c1 | 14274 | dc->debug_target_el = FIELD_EX32(tb_flags, TBFLAG_ANY, DEBUG_TARGET_EL); |
7ea47fe7 | 14275 | |
dcc3a212 RH |
14276 | /* Bound the number of insns to execute to those left on the page. */ |
14277 | bound = -(dc->base.pc_first | TARGET_PAGE_MASK) / 4; | |
14278 | ||
14279 | /* If architectural single step active, limit to 1. */ | |
14280 | if (dc->ss_active) { | |
14281 | bound = 1; | |
14282 | } | |
b542683d | 14283 | dc->base.max_insns = MIN(dc->base.max_insns, bound); |
24299c89 | 14284 | |
11e169de | 14285 | init_tmp_a64_array(dc); |
5c039906 LV |
14286 | } |
14287 | ||
23169224 LV |
14288 | static void aarch64_tr_tb_start(DisasContextBase *db, CPUState *cpu) |
14289 | { | |
23169224 LV |
14290 | } |
14291 | ||
a68956ad LV |
14292 | static void aarch64_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) |
14293 | { | |
14294 | DisasContext *dc = container_of(dcbase, DisasContext, base); | |
14295 | ||
a0415916 | 14296 | tcg_gen_insn_start(dc->base.pc_next, 0, 0); |
15fa08f8 | 14297 | dc->insn_start = tcg_last_op(); |
a68956ad LV |
14298 | } |
14299 | ||
0cb56b37 LV |
14300 | static bool aarch64_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu, |
14301 | const CPUBreakpoint *bp) | |
14302 | { | |
14303 | DisasContext *dc = container_of(dcbase, DisasContext, base); | |
14304 | ||
14305 | if (bp->flags & BP_CPU) { | |
a0415916 | 14306 | gen_a64_set_pc_im(dc->base.pc_next); |
0cb56b37 LV |
14307 | gen_helper_check_breakpoints(cpu_env); |
14308 | /* End the TB early; it likely won't be executed */ | |
14309 | dc->base.is_jmp = DISAS_TOO_MANY; | |
14310 | } else { | |
aee828e7 | 14311 | gen_exception_internal_insn(dc, dc->base.pc_next, EXCP_DEBUG); |
0cb56b37 LV |
14312 | /* The address covered by the breakpoint must be |
14313 | included in [tb->pc, tb->pc + tb->size) in order | |
14314 | to for it to be properly cleared -- thus we | |
14315 | increment the PC here so that the logic setting | |
14316 | tb->size below does the right thing. */ | |
a0415916 | 14317 | dc->base.pc_next += 4; |
0cb56b37 LV |
14318 | dc->base.is_jmp = DISAS_NORETURN; |
14319 | } | |
14320 | ||
14321 | return true; | |
14322 | } | |
14323 | ||
24299c89 LV |
14324 | static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) |
14325 | { | |
14326 | DisasContext *dc = container_of(dcbase, DisasContext, base); | |
14327 | CPUARMState *env = cpu->env_ptr; | |
14328 | ||
14329 | if (dc->ss_active && !dc->pstate_ss) { | |
14330 | /* Singlestep state is Active-pending. | |
14331 | * If we're in this state at the start of a TB then either | |
14332 | * a) we just took an exception to an EL which is being debugged | |
14333 | * and this is the first insn in the exception handler | |
14334 | * b) debug exceptions were masked and we just unmasked them | |
14335 | * without changing EL (eg by clearing PSTATE.D) | |
14336 | * In either case we're going to take a swstep exception in the | |
14337 | * "did not step an insn" case, and so the syndrome ISV and EX | |
14338 | * bits should be zero. | |
14339 | */ | |
14340 | assert(dc->base.num_insns == 1); | |
c1d5f50f | 14341 | gen_swstep_exception(dc, 0, 0); |
24299c89 LV |
14342 | dc->base.is_jmp = DISAS_NORETURN; |
14343 | } else { | |
14344 | disas_a64_insn(env, dc); | |
14345 | } | |
14346 | ||
23169224 | 14347 | translator_loop_temp_check(&dc->base); |
24299c89 LV |
14348 | } |
14349 | ||
be407964 LV |
14350 | static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) |
14351 | { | |
14352 | DisasContext *dc = container_of(dcbase, DisasContext, base); | |
14353 | ||
14354 | if (unlikely(dc->base.singlestep_enabled || dc->ss_active)) { | |
14355 | /* Note that this means single stepping WFI doesn't halt the CPU. | |
14356 | * For conditional branch insns this is harmless unreachable code as | |
14357 | * gen_goto_tb() has already handled emitting the debug exception | |
14358 | * (and thus a tb-jump is not possible when singlestepping). | |
14359 | */ | |
14360 | switch (dc->base.is_jmp) { | |
14361 | default: | |
a0415916 | 14362 | gen_a64_set_pc_im(dc->base.pc_next); |
be407964 | 14363 | /* fall through */ |
dddbba99 | 14364 | case DISAS_EXIT: |
be407964 LV |
14365 | case DISAS_JUMP: |
14366 | if (dc->base.singlestep_enabled) { | |
14367 | gen_exception_internal(EXCP_DEBUG); | |
14368 | } else { | |
14369 | gen_step_complete_exception(dc); | |
14370 | } | |
14371 | break; | |
14372 | case DISAS_NORETURN: | |
14373 | break; | |
14374 | } | |
14375 | } else { | |
14376 | switch (dc->base.is_jmp) { | |
14377 | case DISAS_NEXT: | |
14378 | case DISAS_TOO_MANY: | |
a0415916 | 14379 | gen_goto_tb(dc, 1, dc->base.pc_next); |
be407964 LV |
14380 | break; |
14381 | default: | |
14407ec2 | 14382 | case DISAS_UPDATE_EXIT: |
a0415916 | 14383 | gen_a64_set_pc_im(dc->base.pc_next); |
be407964 | 14384 | /* fall through */ |
be407964 | 14385 | case DISAS_EXIT: |
07ea28b4 | 14386 | tcg_gen_exit_tb(NULL, 0); |
be407964 | 14387 | break; |
32983328 RH |
14388 | case DISAS_UPDATE_NOCHAIN: |
14389 | gen_a64_set_pc_im(dc->base.pc_next); | |
14390 | /* fall through */ | |
a75a52d6 VK |
14391 | case DISAS_JUMP: |
14392 | tcg_gen_lookup_and_goto_ptr(); | |
14393 | break; | |
be407964 LV |
14394 | case DISAS_NORETURN: |
14395 | case DISAS_SWI: | |
14396 | break; | |
14397 | case DISAS_WFE: | |
a0415916 | 14398 | gen_a64_set_pc_im(dc->base.pc_next); |
be407964 LV |
14399 | gen_helper_wfe(cpu_env); |
14400 | break; | |
14401 | case DISAS_YIELD: | |
a0415916 | 14402 | gen_a64_set_pc_im(dc->base.pc_next); |
be407964 LV |
14403 | gen_helper_yield(cpu_env); |
14404 | break; | |
14405 | case DISAS_WFI: | |
58803318 | 14406 | { |
be407964 LV |
14407 | /* This is a special case because we don't want to just halt the CPU |
14408 | * if trying to debug across a WFI. | |
14409 | */ | |
58803318 SS |
14410 | TCGv_i32 tmp = tcg_const_i32(4); |
14411 | ||
a0415916 | 14412 | gen_a64_set_pc_im(dc->base.pc_next); |
58803318 SS |
14413 | gen_helper_wfi(cpu_env, tmp); |
14414 | tcg_temp_free_i32(tmp); | |
be407964 LV |
14415 | /* The helper doesn't necessarily throw an exception, but we |
14416 | * must go back to the main loop to check for interrupts anyway. | |
14417 | */ | |
07ea28b4 | 14418 | tcg_gen_exit_tb(NULL, 0); |
be407964 LV |
14419 | break; |
14420 | } | |
58803318 | 14421 | } |
be407964 LV |
14422 | } |
14423 | } | |
14424 | ||
58350fa4 LV |
14425 | static void aarch64_tr_disas_log(const DisasContextBase *dcbase, |
14426 | CPUState *cpu) | |
14427 | { | |
14428 | DisasContext *dc = container_of(dcbase, DisasContext, base); | |
14429 | ||
14430 | qemu_log("IN: %s\n", lookup_symbol(dc->base.pc_first)); | |
1d48474d | 14431 | log_target_disas(cpu, dc->base.pc_first, dc->base.tb->size); |
58350fa4 LV |
14432 | } |
14433 | ||
23169224 LV |
14434 | const TranslatorOps aarch64_translator_ops = { |
14435 | .init_disas_context = aarch64_tr_init_disas_context, | |
14436 | .tb_start = aarch64_tr_tb_start, | |
14437 | .insn_start = aarch64_tr_insn_start, | |
14438 | .breakpoint_check = aarch64_tr_breakpoint_check, | |
14439 | .translate_insn = aarch64_tr_translate_insn, | |
14440 | .tb_stop = aarch64_tr_tb_stop, | |
14441 | .disas_log = aarch64_tr_disas_log, | |
14442 | }; |