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38388f7e RH |
1 | /* |
2 | * AArch64 SVE translation | |
3 | * | |
4 | * Copyright (c) 2018 Linaro, Ltd | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
50f57e09 | 9 | * version 2.1 of the License, or (at your option) any later version. |
38388f7e RH |
10 | * |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #include "qemu/osdep.h" | |
21 | #include "cpu.h" | |
22 | #include "exec/exec-all.h" | |
dcb32f1d PMD |
23 | #include "tcg/tcg-op.h" |
24 | #include "tcg/tcg-op-gvec.h" | |
25 | #include "tcg/tcg-gvec-desc.h" | |
38388f7e RH |
26 | #include "qemu/log.h" |
27 | #include "arm_ldst.h" | |
28 | #include "translate.h" | |
29 | #include "internals.h" | |
30 | #include "exec/helper-proto.h" | |
31 | #include "exec/helper-gen.h" | |
32 | #include "exec/log.h" | |
38388f7e | 33 | #include "translate-a64.h" |
cc48affe | 34 | #include "fpu/softfloat.h" |
38388f7e | 35 | |
757f9cff | 36 | |
9ee3a611 RH |
37 | typedef void GVecGen2sFn(unsigned, uint32_t, uint32_t, |
38 | TCGv_i64, uint32_t, uint32_t); | |
39 | ||
38cadeba RH |
40 | typedef void gen_helper_gvec_flags_3(TCGv_i32, TCGv_ptr, TCGv_ptr, |
41 | TCGv_ptr, TCGv_i32); | |
757f9cff RH |
42 | typedef void gen_helper_gvec_flags_4(TCGv_i32, TCGv_ptr, TCGv_ptr, |
43 | TCGv_ptr, TCGv_ptr, TCGv_i32); | |
44 | ||
c4e7c493 | 45 | typedef void gen_helper_gvec_mem(TCGv_env, TCGv_ptr, TCGv_i64, TCGv_i32); |
f6dbf62a RH |
46 | typedef void gen_helper_gvec_mem_scatter(TCGv_env, TCGv_ptr, TCGv_ptr, |
47 | TCGv_ptr, TCGv_i64, TCGv_i32); | |
c4e7c493 | 48 | |
ccd841c3 RH |
49 | /* |
50 | * Helpers for extracting complex instruction fields. | |
51 | */ | |
52 | ||
53 | /* See e.g. ASR (immediate, predicated). | |
54 | * Returns -1 for unallocated encoding; diagnose later. | |
55 | */ | |
451e4ffd | 56 | static int tszimm_esz(DisasContext *s, int x) |
ccd841c3 RH |
57 | { |
58 | x >>= 3; /* discard imm3 */ | |
59 | return 31 - clz32(x); | |
60 | } | |
61 | ||
451e4ffd | 62 | static int tszimm_shr(DisasContext *s, int x) |
ccd841c3 | 63 | { |
451e4ffd | 64 | return (16 << tszimm_esz(s, x)) - x; |
ccd841c3 RH |
65 | } |
66 | ||
67 | /* See e.g. LSL (immediate, predicated). */ | |
451e4ffd | 68 | static int tszimm_shl(DisasContext *s, int x) |
ccd841c3 | 69 | { |
451e4ffd | 70 | return x - (8 << tszimm_esz(s, x)); |
ccd841c3 RH |
71 | } |
72 | ||
f25a2361 | 73 | /* The SH bit is in bit 8. Extract the low 8 and shift. */ |
451e4ffd | 74 | static inline int expand_imm_sh8s(DisasContext *s, int x) |
f25a2361 RH |
75 | { |
76 | return (int8_t)x << (x & 0x100 ? 8 : 0); | |
77 | } | |
78 | ||
451e4ffd | 79 | static inline int expand_imm_sh8u(DisasContext *s, int x) |
6e6a157d RH |
80 | { |
81 | return (uint8_t)x << (x & 0x100 ? 8 : 0); | |
82 | } | |
83 | ||
c4e7c493 RH |
84 | /* Convert a 2-bit memory size (msz) to a 4-bit data type (dtype) |
85 | * with unsigned data. C.f. SVE Memory Contiguous Load Group. | |
86 | */ | |
451e4ffd | 87 | static inline int msz_dtype(DisasContext *s, int msz) |
c4e7c493 RH |
88 | { |
89 | static const uint8_t dtype[4] = { 0, 5, 10, 15 }; | |
90 | return dtype[msz]; | |
91 | } | |
92 | ||
38388f7e RH |
93 | /* |
94 | * Include the generated decoder. | |
95 | */ | |
96 | ||
139c1837 | 97 | #include "decode-sve.c.inc" |
38388f7e RH |
98 | |
99 | /* | |
100 | * Implement all of the translator functions referenced by the decoder. | |
101 | */ | |
102 | ||
d1822297 RH |
103 | /* Return the offset info CPUARMState of the predicate vector register Pn. |
104 | * Note for this purpose, FFR is P16. | |
105 | */ | |
106 | static inline int pred_full_reg_offset(DisasContext *s, int regno) | |
107 | { | |
108 | return offsetof(CPUARMState, vfp.pregs[regno]); | |
109 | } | |
110 | ||
111 | /* Return the byte size of the whole predicate register, VL / 64. */ | |
112 | static inline int pred_full_reg_size(DisasContext *s) | |
113 | { | |
114 | return s->sve_len >> 3; | |
115 | } | |
116 | ||
516e246a RH |
117 | /* Round up the size of a register to a size allowed by |
118 | * the tcg vector infrastructure. Any operation which uses this | |
119 | * size may assume that the bits above pred_full_reg_size are zero, | |
120 | * and must leave them the same way. | |
121 | * | |
122 | * Note that this is not needed for the vector registers as they | |
123 | * are always properly sized for tcg vectors. | |
124 | */ | |
125 | static int size_for_gvec(int size) | |
126 | { | |
127 | if (size <= 8) { | |
128 | return 8; | |
129 | } else { | |
130 | return QEMU_ALIGN_UP(size, 16); | |
131 | } | |
132 | } | |
133 | ||
134 | static int pred_gvec_reg_size(DisasContext *s) | |
135 | { | |
136 | return size_for_gvec(pred_full_reg_size(s)); | |
137 | } | |
138 | ||
40e32e5a | 139 | /* Invoke an out-of-line helper on 2 Zregs. */ |
c5edf07d | 140 | static bool gen_gvec_ool_zz(DisasContext *s, gen_helper_gvec_2 *fn, |
40e32e5a RH |
141 | int rd, int rn, int data) |
142 | { | |
c5edf07d RH |
143 | if (fn == NULL) { |
144 | return false; | |
145 | } | |
146 | if (sve_access_check(s)) { | |
147 | unsigned vsz = vec_full_reg_size(s); | |
148 | tcg_gen_gvec_2_ool(vec_full_reg_offset(s, rd), | |
149 | vec_full_reg_offset(s, rn), | |
150 | vsz, vsz, data, fn); | |
151 | } | |
152 | return true; | |
40e32e5a RH |
153 | } |
154 | ||
e645d1a1 | 155 | /* Invoke an out-of-line helper on 3 Zregs. */ |
913a8a00 | 156 | static bool gen_gvec_ool_zzz(DisasContext *s, gen_helper_gvec_3 *fn, |
e645d1a1 RH |
157 | int rd, int rn, int rm, int data) |
158 | { | |
913a8a00 RH |
159 | if (fn == NULL) { |
160 | return false; | |
161 | } | |
162 | if (sve_access_check(s)) { | |
163 | unsigned vsz = vec_full_reg_size(s); | |
164 | tcg_gen_gvec_3_ool(vec_full_reg_offset(s, rd), | |
165 | vec_full_reg_offset(s, rn), | |
166 | vec_full_reg_offset(s, rm), | |
167 | vsz, vsz, data, fn); | |
168 | } | |
169 | return true; | |
e645d1a1 RH |
170 | } |
171 | ||
84a272f5 RH |
172 | static bool gen_gvec_ool_arg_zzz(DisasContext *s, gen_helper_gvec_3 *fn, |
173 | arg_rrr_esz *a, int data) | |
174 | { | |
175 | return gen_gvec_ool_zzz(s, fn, a->rd, a->rn, a->rm, data); | |
176 | } | |
177 | ||
38650638 | 178 | /* Invoke an out-of-line helper on 4 Zregs. */ |
7ad416b1 | 179 | static bool gen_gvec_ool_zzzz(DisasContext *s, gen_helper_gvec_4 *fn, |
38650638 RH |
180 | int rd, int rn, int rm, int ra, int data) |
181 | { | |
7ad416b1 RH |
182 | if (fn == NULL) { |
183 | return false; | |
184 | } | |
185 | if (sve_access_check(s)) { | |
186 | unsigned vsz = vec_full_reg_size(s); | |
187 | tcg_gen_gvec_4_ool(vec_full_reg_offset(s, rd), | |
188 | vec_full_reg_offset(s, rn), | |
189 | vec_full_reg_offset(s, rm), | |
190 | vec_full_reg_offset(s, ra), | |
191 | vsz, vsz, data, fn); | |
192 | } | |
193 | return true; | |
38650638 RH |
194 | } |
195 | ||
cab79ac9 RH |
196 | static bool gen_gvec_ool_arg_zzzz(DisasContext *s, gen_helper_gvec_4 *fn, |
197 | arg_rrrr_esz *a, int data) | |
198 | { | |
199 | return gen_gvec_ool_zzzz(s, fn, a->rd, a->rn, a->rm, a->ra, data); | |
200 | } | |
201 | ||
e82d3536 RH |
202 | static bool gen_gvec_ool_arg_zzxz(DisasContext *s, gen_helper_gvec_4 *fn, |
203 | arg_rrxr_esz *a) | |
204 | { | |
205 | return gen_gvec_ool_zzzz(s, fn, a->rd, a->rn, a->rm, a->ra, a->index); | |
206 | } | |
207 | ||
41bf9b67 RH |
208 | /* Invoke an out-of-line helper on 4 Zregs, plus a pointer. */ |
209 | static bool gen_gvec_ptr_zzzz(DisasContext *s, gen_helper_gvec_4_ptr *fn, | |
210 | int rd, int rn, int rm, int ra, | |
211 | int data, TCGv_ptr ptr) | |
212 | { | |
213 | if (fn == NULL) { | |
214 | return false; | |
215 | } | |
216 | if (sve_access_check(s)) { | |
217 | unsigned vsz = vec_full_reg_size(s); | |
218 | tcg_gen_gvec_4_ptr(vec_full_reg_offset(s, rd), | |
219 | vec_full_reg_offset(s, rn), | |
220 | vec_full_reg_offset(s, rm), | |
221 | vec_full_reg_offset(s, ra), | |
222 | ptr, vsz, vsz, data, fn); | |
223 | } | |
224 | return true; | |
225 | } | |
226 | ||
227 | static bool gen_gvec_fpst_zzzz(DisasContext *s, gen_helper_gvec_4_ptr *fn, | |
228 | int rd, int rn, int rm, int ra, | |
229 | int data, ARMFPStatusFlavour flavour) | |
230 | { | |
231 | TCGv_ptr status = fpstatus_ptr(flavour); | |
232 | bool ret = gen_gvec_ptr_zzzz(s, fn, rd, rn, rm, ra, data, status); | |
233 | tcg_temp_free_ptr(status); | |
234 | return ret; | |
235 | } | |
236 | ||
96a461f7 | 237 | /* Invoke an out-of-line helper on 2 Zregs and a predicate. */ |
8fb27a21 | 238 | static bool gen_gvec_ool_zzp(DisasContext *s, gen_helper_gvec_3 *fn, |
96a461f7 RH |
239 | int rd, int rn, int pg, int data) |
240 | { | |
8fb27a21 RH |
241 | if (fn == NULL) { |
242 | return false; | |
243 | } | |
244 | if (sve_access_check(s)) { | |
245 | unsigned vsz = vec_full_reg_size(s); | |
246 | tcg_gen_gvec_3_ool(vec_full_reg_offset(s, rd), | |
247 | vec_full_reg_offset(s, rn), | |
248 | pred_full_reg_offset(s, pg), | |
249 | vsz, vsz, data, fn); | |
250 | } | |
251 | return true; | |
96a461f7 RH |
252 | } |
253 | ||
b051809a RH |
254 | static bool gen_gvec_ool_arg_zpz(DisasContext *s, gen_helper_gvec_3 *fn, |
255 | arg_rpr_esz *a, int data) | |
256 | { | |
257 | return gen_gvec_ool_zzp(s, fn, a->rd, a->rn, a->pg, data); | |
258 | } | |
259 | ||
afa2529c RH |
260 | static bool gen_gvec_ool_arg_zpzi(DisasContext *s, gen_helper_gvec_3 *fn, |
261 | arg_rpri_esz *a) | |
262 | { | |
263 | return gen_gvec_ool_zzp(s, fn, a->rd, a->rn, a->pg, a->imm); | |
264 | } | |
b051809a | 265 | |
36cbb7a8 | 266 | /* Invoke an out-of-line helper on 3 Zregs and a predicate. */ |
2a753d1e | 267 | static bool gen_gvec_ool_zzzp(DisasContext *s, gen_helper_gvec_4 *fn, |
36cbb7a8 RH |
268 | int rd, int rn, int rm, int pg, int data) |
269 | { | |
2a753d1e RH |
270 | if (fn == NULL) { |
271 | return false; | |
272 | } | |
273 | if (sve_access_check(s)) { | |
274 | unsigned vsz = vec_full_reg_size(s); | |
275 | tcg_gen_gvec_4_ool(vec_full_reg_offset(s, rd), | |
276 | vec_full_reg_offset(s, rn), | |
277 | vec_full_reg_offset(s, rm), | |
278 | pred_full_reg_offset(s, pg), | |
279 | vsz, vsz, data, fn); | |
280 | } | |
281 | return true; | |
36cbb7a8 | 282 | } |
f7d79c41 | 283 | |
312016c9 RH |
284 | static bool gen_gvec_ool_arg_zpzz(DisasContext *s, gen_helper_gvec_4 *fn, |
285 | arg_rprr_esz *a, int data) | |
286 | { | |
287 | return gen_gvec_ool_zzzp(s, fn, a->rd, a->rn, a->rm, a->pg, data); | |
288 | } | |
289 | ||
faf915e2 RH |
290 | /* Invoke a vector expander on two Zregs and an immediate. */ |
291 | static bool gen_gvec_fn_zzi(DisasContext *s, GVecGen2iFn *gvec_fn, | |
292 | int esz, int rd, int rn, uint64_t imm) | |
293 | { | |
294 | if (gvec_fn == NULL) { | |
295 | return false; | |
296 | } | |
297 | if (sve_access_check(s)) { | |
298 | unsigned vsz = vec_full_reg_size(s); | |
299 | gvec_fn(esz, vec_full_reg_offset(s, rd), | |
300 | vec_full_reg_offset(s, rn), imm, vsz, vsz); | |
301 | } | |
302 | return true; | |
303 | } | |
304 | ||
ada378f0 RH |
305 | static bool gen_gvec_fn_arg_zzi(DisasContext *s, GVecGen2iFn *gvec_fn, |
306 | arg_rri_esz *a) | |
307 | { | |
308 | if (a->esz < 0) { | |
309 | /* Invalid tsz encoding -- see tszimm_esz. */ | |
310 | return false; | |
311 | } | |
312 | return gen_gvec_fn_zzi(s, gvec_fn, a->esz, a->rd, a->rn, a->imm); | |
313 | } | |
314 | ||
39eea561 | 315 | /* Invoke a vector expander on three Zregs. */ |
50f6db5f | 316 | static bool gen_gvec_fn_zzz(DisasContext *s, GVecGen3Fn *gvec_fn, |
28c4da31 | 317 | int esz, int rd, int rn, int rm) |
38388f7e | 318 | { |
50f6db5f RH |
319 | if (gvec_fn == NULL) { |
320 | return false; | |
321 | } | |
322 | if (sve_access_check(s)) { | |
323 | unsigned vsz = vec_full_reg_size(s); | |
324 | gvec_fn(esz, vec_full_reg_offset(s, rd), | |
325 | vec_full_reg_offset(s, rn), | |
326 | vec_full_reg_offset(s, rm), vsz, vsz); | |
327 | } | |
328 | return true; | |
38388f7e RH |
329 | } |
330 | ||
cd54bbe6 RH |
331 | static bool gen_gvec_fn_arg_zzz(DisasContext *s, GVecGen3Fn *fn, |
332 | arg_rrr_esz *a) | |
333 | { | |
334 | return gen_gvec_fn_zzz(s, fn, a->esz, a->rd, a->rn, a->rm); | |
335 | } | |
336 | ||
911cdc6d | 337 | /* Invoke a vector expander on four Zregs. */ |
189876af RH |
338 | static bool gen_gvec_fn_arg_zzzz(DisasContext *s, GVecGen4Fn *gvec_fn, |
339 | arg_rrrr_esz *a) | |
911cdc6d | 340 | { |
189876af RH |
341 | if (gvec_fn == NULL) { |
342 | return false; | |
343 | } | |
344 | if (sve_access_check(s)) { | |
345 | unsigned vsz = vec_full_reg_size(s); | |
346 | gvec_fn(a->esz, vec_full_reg_offset(s, a->rd), | |
347 | vec_full_reg_offset(s, a->rn), | |
348 | vec_full_reg_offset(s, a->rm), | |
349 | vec_full_reg_offset(s, a->ra), vsz, vsz); | |
350 | } | |
351 | return true; | |
911cdc6d RH |
352 | } |
353 | ||
39eea561 RH |
354 | /* Invoke a vector move on two Zregs. */ |
355 | static bool do_mov_z(DisasContext *s, int rd, int rn) | |
38388f7e | 356 | { |
f7d79c41 | 357 | if (sve_access_check(s)) { |
5f730621 RH |
358 | unsigned vsz = vec_full_reg_size(s); |
359 | tcg_gen_gvec_mov(MO_8, vec_full_reg_offset(s, rd), | |
360 | vec_full_reg_offset(s, rn), vsz, vsz); | |
f7d79c41 RH |
361 | } |
362 | return true; | |
38388f7e RH |
363 | } |
364 | ||
d9d78dcc RH |
365 | /* Initialize a Zreg with replications of a 64-bit immediate. */ |
366 | static void do_dupi_z(DisasContext *s, int rd, uint64_t word) | |
367 | { | |
368 | unsigned vsz = vec_full_reg_size(s); | |
8711e71f | 369 | tcg_gen_gvec_dup_imm(MO_64, vec_full_reg_offset(s, rd), vsz, vsz, word); |
d9d78dcc RH |
370 | } |
371 | ||
516e246a | 372 | /* Invoke a vector expander on three Pregs. */ |
23e5fa5f | 373 | static bool gen_gvec_fn_ppp(DisasContext *s, GVecGen3Fn *gvec_fn, |
dd81a8d7 | 374 | int rd, int rn, int rm) |
516e246a | 375 | { |
23e5fa5f RH |
376 | if (sve_access_check(s)) { |
377 | unsigned psz = pred_gvec_reg_size(s); | |
378 | gvec_fn(MO_64, pred_full_reg_offset(s, rd), | |
379 | pred_full_reg_offset(s, rn), | |
380 | pred_full_reg_offset(s, rm), psz, psz); | |
381 | } | |
382 | return true; | |
516e246a RH |
383 | } |
384 | ||
385 | /* Invoke a vector move on two Pregs. */ | |
386 | static bool do_mov_p(DisasContext *s, int rd, int rn) | |
387 | { | |
d0b2df5a RH |
388 | if (sve_access_check(s)) { |
389 | unsigned psz = pred_gvec_reg_size(s); | |
390 | tcg_gen_gvec_mov(MO_8, pred_full_reg_offset(s, rd), | |
391 | pred_full_reg_offset(s, rn), psz, psz); | |
392 | } | |
393 | return true; | |
516e246a RH |
394 | } |
395 | ||
9e18d7a6 RH |
396 | /* Set the cpu flags as per a return from an SVE helper. */ |
397 | static void do_pred_flags(TCGv_i32 t) | |
398 | { | |
399 | tcg_gen_mov_i32(cpu_NF, t); | |
400 | tcg_gen_andi_i32(cpu_ZF, t, 2); | |
401 | tcg_gen_andi_i32(cpu_CF, t, 1); | |
402 | tcg_gen_movi_i32(cpu_VF, 0); | |
403 | } | |
404 | ||
405 | /* Subroutines computing the ARM PredTest psuedofunction. */ | |
406 | static void do_predtest1(TCGv_i64 d, TCGv_i64 g) | |
407 | { | |
408 | TCGv_i32 t = tcg_temp_new_i32(); | |
409 | ||
410 | gen_helper_sve_predtest1(t, d, g); | |
411 | do_pred_flags(t); | |
412 | tcg_temp_free_i32(t); | |
413 | } | |
414 | ||
415 | static void do_predtest(DisasContext *s, int dofs, int gofs, int words) | |
416 | { | |
417 | TCGv_ptr dptr = tcg_temp_new_ptr(); | |
418 | TCGv_ptr gptr = tcg_temp_new_ptr(); | |
392acacc | 419 | TCGv_i32 t = tcg_temp_new_i32(); |
9e18d7a6 RH |
420 | |
421 | tcg_gen_addi_ptr(dptr, cpu_env, dofs); | |
422 | tcg_gen_addi_ptr(gptr, cpu_env, gofs); | |
9e18d7a6 | 423 | |
392acacc | 424 | gen_helper_sve_predtest(t, dptr, gptr, tcg_constant_i32(words)); |
9e18d7a6 RH |
425 | tcg_temp_free_ptr(dptr); |
426 | tcg_temp_free_ptr(gptr); | |
427 | ||
428 | do_pred_flags(t); | |
429 | tcg_temp_free_i32(t); | |
430 | } | |
431 | ||
028e2a7b RH |
432 | /* For each element size, the bits within a predicate word that are active. */ |
433 | const uint64_t pred_esz_masks[4] = { | |
434 | 0xffffffffffffffffull, 0x5555555555555555ull, | |
435 | 0x1111111111111111ull, 0x0101010101010101ull | |
436 | }; | |
437 | ||
c437c59b RH |
438 | static bool trans_INVALID(DisasContext *s, arg_INVALID *a) |
439 | { | |
440 | unallocated_encoding(s); | |
441 | return true; | |
442 | } | |
443 | ||
39eea561 RH |
444 | /* |
445 | *** SVE Logical - Unpredicated Group | |
446 | */ | |
447 | ||
b262215b RH |
448 | TRANS_FEAT(AND_zzz, aa64_sve, gen_gvec_fn_arg_zzz, tcg_gen_gvec_and, a) |
449 | TRANS_FEAT(ORR_zzz, aa64_sve, gen_gvec_fn_arg_zzz, tcg_gen_gvec_or, a) | |
450 | TRANS_FEAT(EOR_zzz, aa64_sve, gen_gvec_fn_arg_zzz, tcg_gen_gvec_xor, a) | |
451 | TRANS_FEAT(BIC_zzz, aa64_sve, gen_gvec_fn_arg_zzz, tcg_gen_gvec_andc, a) | |
d1822297 | 452 | |
e6eba6e5 RH |
453 | static void gen_xar8_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m, int64_t sh) |
454 | { | |
455 | TCGv_i64 t = tcg_temp_new_i64(); | |
456 | uint64_t mask = dup_const(MO_8, 0xff >> sh); | |
457 | ||
458 | tcg_gen_xor_i64(t, n, m); | |
459 | tcg_gen_shri_i64(d, t, sh); | |
460 | tcg_gen_shli_i64(t, t, 8 - sh); | |
461 | tcg_gen_andi_i64(d, d, mask); | |
462 | tcg_gen_andi_i64(t, t, ~mask); | |
463 | tcg_gen_or_i64(d, d, t); | |
464 | tcg_temp_free_i64(t); | |
465 | } | |
466 | ||
467 | static void gen_xar16_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m, int64_t sh) | |
468 | { | |
469 | TCGv_i64 t = tcg_temp_new_i64(); | |
470 | uint64_t mask = dup_const(MO_16, 0xffff >> sh); | |
471 | ||
472 | tcg_gen_xor_i64(t, n, m); | |
473 | tcg_gen_shri_i64(d, t, sh); | |
474 | tcg_gen_shli_i64(t, t, 16 - sh); | |
475 | tcg_gen_andi_i64(d, d, mask); | |
476 | tcg_gen_andi_i64(t, t, ~mask); | |
477 | tcg_gen_or_i64(d, d, t); | |
478 | tcg_temp_free_i64(t); | |
479 | } | |
480 | ||
481 | static void gen_xar_i32(TCGv_i32 d, TCGv_i32 n, TCGv_i32 m, int32_t sh) | |
482 | { | |
483 | tcg_gen_xor_i32(d, n, m); | |
484 | tcg_gen_rotri_i32(d, d, sh); | |
485 | } | |
486 | ||
487 | static void gen_xar_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m, int64_t sh) | |
488 | { | |
489 | tcg_gen_xor_i64(d, n, m); | |
490 | tcg_gen_rotri_i64(d, d, sh); | |
491 | } | |
492 | ||
493 | static void gen_xar_vec(unsigned vece, TCGv_vec d, TCGv_vec n, | |
494 | TCGv_vec m, int64_t sh) | |
495 | { | |
496 | tcg_gen_xor_vec(vece, d, n, m); | |
497 | tcg_gen_rotri_vec(vece, d, d, sh); | |
498 | } | |
499 | ||
500 | void gen_gvec_xar(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, | |
501 | uint32_t rm_ofs, int64_t shift, | |
502 | uint32_t opr_sz, uint32_t max_sz) | |
503 | { | |
504 | static const TCGOpcode vecop[] = { INDEX_op_rotli_vec, 0 }; | |
505 | static const GVecGen3i ops[4] = { | |
506 | { .fni8 = gen_xar8_i64, | |
507 | .fniv = gen_xar_vec, | |
508 | .fno = gen_helper_sve2_xar_b, | |
509 | .opt_opc = vecop, | |
510 | .vece = MO_8 }, | |
511 | { .fni8 = gen_xar16_i64, | |
512 | .fniv = gen_xar_vec, | |
513 | .fno = gen_helper_sve2_xar_h, | |
514 | .opt_opc = vecop, | |
515 | .vece = MO_16 }, | |
516 | { .fni4 = gen_xar_i32, | |
517 | .fniv = gen_xar_vec, | |
518 | .fno = gen_helper_sve2_xar_s, | |
519 | .opt_opc = vecop, | |
520 | .vece = MO_32 }, | |
521 | { .fni8 = gen_xar_i64, | |
522 | .fniv = gen_xar_vec, | |
523 | .fno = gen_helper_gvec_xar_d, | |
524 | .opt_opc = vecop, | |
525 | .vece = MO_64 } | |
526 | }; | |
527 | int esize = 8 << vece; | |
528 | ||
529 | /* The SVE2 range is 1 .. esize; the AdvSIMD range is 0 .. esize-1. */ | |
530 | tcg_debug_assert(shift >= 0); | |
531 | tcg_debug_assert(shift <= esize); | |
532 | shift &= esize - 1; | |
533 | ||
534 | if (shift == 0) { | |
535 | /* xar with no rotate devolves to xor. */ | |
536 | tcg_gen_gvec_xor(vece, rd_ofs, rn_ofs, rm_ofs, opr_sz, max_sz); | |
537 | } else { | |
538 | tcg_gen_gvec_3i(rd_ofs, rn_ofs, rm_ofs, opr_sz, max_sz, | |
539 | shift, &ops[vece]); | |
540 | } | |
541 | } | |
542 | ||
543 | static bool trans_XAR(DisasContext *s, arg_rrri_esz *a) | |
544 | { | |
545 | if (a->esz < 0 || !dc_isar_feature(aa64_sve2, s)) { | |
546 | return false; | |
547 | } | |
548 | if (sve_access_check(s)) { | |
549 | unsigned vsz = vec_full_reg_size(s); | |
550 | gen_gvec_xar(a->esz, vec_full_reg_offset(s, a->rd), | |
551 | vec_full_reg_offset(s, a->rn), | |
552 | vec_full_reg_offset(s, a->rm), a->imm, vsz, vsz); | |
553 | } | |
554 | return true; | |
555 | } | |
556 | ||
911cdc6d RH |
557 | static void gen_eor3_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m, TCGv_i64 k) |
558 | { | |
559 | tcg_gen_xor_i64(d, n, m); | |
560 | tcg_gen_xor_i64(d, d, k); | |
561 | } | |
562 | ||
563 | static void gen_eor3_vec(unsigned vece, TCGv_vec d, TCGv_vec n, | |
564 | TCGv_vec m, TCGv_vec k) | |
565 | { | |
566 | tcg_gen_xor_vec(vece, d, n, m); | |
567 | tcg_gen_xor_vec(vece, d, d, k); | |
568 | } | |
569 | ||
570 | static void gen_eor3(unsigned vece, uint32_t d, uint32_t n, uint32_t m, | |
571 | uint32_t a, uint32_t oprsz, uint32_t maxsz) | |
572 | { | |
573 | static const GVecGen4 op = { | |
574 | .fni8 = gen_eor3_i64, | |
575 | .fniv = gen_eor3_vec, | |
576 | .fno = gen_helper_sve2_eor3, | |
577 | .vece = MO_64, | |
578 | .prefer_i64 = TCG_TARGET_REG_BITS == 64, | |
579 | }; | |
580 | tcg_gen_gvec_4(d, n, m, a, oprsz, maxsz, &op); | |
581 | } | |
582 | ||
b773a5c8 | 583 | TRANS_FEAT(EOR3, aa64_sve2, gen_gvec_fn_arg_zzzz, gen_eor3, a) |
911cdc6d RH |
584 | |
585 | static void gen_bcax_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m, TCGv_i64 k) | |
586 | { | |
587 | tcg_gen_andc_i64(d, m, k); | |
588 | tcg_gen_xor_i64(d, d, n); | |
589 | } | |
590 | ||
591 | static void gen_bcax_vec(unsigned vece, TCGv_vec d, TCGv_vec n, | |
592 | TCGv_vec m, TCGv_vec k) | |
593 | { | |
594 | tcg_gen_andc_vec(vece, d, m, k); | |
595 | tcg_gen_xor_vec(vece, d, d, n); | |
596 | } | |
597 | ||
598 | static void gen_bcax(unsigned vece, uint32_t d, uint32_t n, uint32_t m, | |
599 | uint32_t a, uint32_t oprsz, uint32_t maxsz) | |
600 | { | |
601 | static const GVecGen4 op = { | |
602 | .fni8 = gen_bcax_i64, | |
603 | .fniv = gen_bcax_vec, | |
604 | .fno = gen_helper_sve2_bcax, | |
605 | .vece = MO_64, | |
606 | .prefer_i64 = TCG_TARGET_REG_BITS == 64, | |
607 | }; | |
608 | tcg_gen_gvec_4(d, n, m, a, oprsz, maxsz, &op); | |
609 | } | |
610 | ||
b773a5c8 | 611 | TRANS_FEAT(BCAX, aa64_sve2, gen_gvec_fn_arg_zzzz, gen_bcax, a) |
911cdc6d RH |
612 | |
613 | static void gen_bsl(unsigned vece, uint32_t d, uint32_t n, uint32_t m, | |
614 | uint32_t a, uint32_t oprsz, uint32_t maxsz) | |
615 | { | |
616 | /* BSL differs from the generic bitsel in argument ordering. */ | |
617 | tcg_gen_gvec_bitsel(vece, d, a, n, m, oprsz, maxsz); | |
618 | } | |
619 | ||
b773a5c8 | 620 | TRANS_FEAT(BSL, aa64_sve2, gen_gvec_fn_arg_zzzz, gen_bsl, a) |
911cdc6d RH |
621 | |
622 | static void gen_bsl1n_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m, TCGv_i64 k) | |
623 | { | |
624 | tcg_gen_andc_i64(n, k, n); | |
625 | tcg_gen_andc_i64(m, m, k); | |
626 | tcg_gen_or_i64(d, n, m); | |
627 | } | |
628 | ||
629 | static void gen_bsl1n_vec(unsigned vece, TCGv_vec d, TCGv_vec n, | |
630 | TCGv_vec m, TCGv_vec k) | |
631 | { | |
632 | if (TCG_TARGET_HAS_bitsel_vec) { | |
633 | tcg_gen_not_vec(vece, n, n); | |
634 | tcg_gen_bitsel_vec(vece, d, k, n, m); | |
635 | } else { | |
636 | tcg_gen_andc_vec(vece, n, k, n); | |
637 | tcg_gen_andc_vec(vece, m, m, k); | |
638 | tcg_gen_or_vec(vece, d, n, m); | |
639 | } | |
640 | } | |
641 | ||
642 | static void gen_bsl1n(unsigned vece, uint32_t d, uint32_t n, uint32_t m, | |
643 | uint32_t a, uint32_t oprsz, uint32_t maxsz) | |
644 | { | |
645 | static const GVecGen4 op = { | |
646 | .fni8 = gen_bsl1n_i64, | |
647 | .fniv = gen_bsl1n_vec, | |
648 | .fno = gen_helper_sve2_bsl1n, | |
649 | .vece = MO_64, | |
650 | .prefer_i64 = TCG_TARGET_REG_BITS == 64, | |
651 | }; | |
652 | tcg_gen_gvec_4(d, n, m, a, oprsz, maxsz, &op); | |
653 | } | |
654 | ||
b773a5c8 | 655 | TRANS_FEAT(BSL1N, aa64_sve2, gen_gvec_fn_arg_zzzz, gen_bsl1n, a) |
911cdc6d RH |
656 | |
657 | static void gen_bsl2n_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m, TCGv_i64 k) | |
658 | { | |
659 | /* | |
660 | * Z[dn] = (n & k) | (~m & ~k) | |
661 | * = | ~(m | k) | |
662 | */ | |
663 | tcg_gen_and_i64(n, n, k); | |
664 | if (TCG_TARGET_HAS_orc_i64) { | |
665 | tcg_gen_or_i64(m, m, k); | |
666 | tcg_gen_orc_i64(d, n, m); | |
667 | } else { | |
668 | tcg_gen_nor_i64(m, m, k); | |
669 | tcg_gen_or_i64(d, n, m); | |
670 | } | |
671 | } | |
672 | ||
673 | static void gen_bsl2n_vec(unsigned vece, TCGv_vec d, TCGv_vec n, | |
674 | TCGv_vec m, TCGv_vec k) | |
675 | { | |
676 | if (TCG_TARGET_HAS_bitsel_vec) { | |
677 | tcg_gen_not_vec(vece, m, m); | |
678 | tcg_gen_bitsel_vec(vece, d, k, n, m); | |
679 | } else { | |
680 | tcg_gen_and_vec(vece, n, n, k); | |
681 | tcg_gen_or_vec(vece, m, m, k); | |
682 | tcg_gen_orc_vec(vece, d, n, m); | |
683 | } | |
684 | } | |
685 | ||
686 | static void gen_bsl2n(unsigned vece, uint32_t d, uint32_t n, uint32_t m, | |
687 | uint32_t a, uint32_t oprsz, uint32_t maxsz) | |
688 | { | |
689 | static const GVecGen4 op = { | |
690 | .fni8 = gen_bsl2n_i64, | |
691 | .fniv = gen_bsl2n_vec, | |
692 | .fno = gen_helper_sve2_bsl2n, | |
693 | .vece = MO_64, | |
694 | .prefer_i64 = TCG_TARGET_REG_BITS == 64, | |
695 | }; | |
696 | tcg_gen_gvec_4(d, n, m, a, oprsz, maxsz, &op); | |
697 | } | |
698 | ||
b773a5c8 | 699 | TRANS_FEAT(BSL2N, aa64_sve2, gen_gvec_fn_arg_zzzz, gen_bsl2n, a) |
911cdc6d RH |
700 | |
701 | static void gen_nbsl_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m, TCGv_i64 k) | |
702 | { | |
703 | tcg_gen_and_i64(n, n, k); | |
704 | tcg_gen_andc_i64(m, m, k); | |
705 | tcg_gen_nor_i64(d, n, m); | |
706 | } | |
707 | ||
708 | static void gen_nbsl_vec(unsigned vece, TCGv_vec d, TCGv_vec n, | |
709 | TCGv_vec m, TCGv_vec k) | |
710 | { | |
711 | tcg_gen_bitsel_vec(vece, d, k, n, m); | |
712 | tcg_gen_not_vec(vece, d, d); | |
713 | } | |
714 | ||
715 | static void gen_nbsl(unsigned vece, uint32_t d, uint32_t n, uint32_t m, | |
716 | uint32_t a, uint32_t oprsz, uint32_t maxsz) | |
717 | { | |
718 | static const GVecGen4 op = { | |
719 | .fni8 = gen_nbsl_i64, | |
720 | .fniv = gen_nbsl_vec, | |
721 | .fno = gen_helper_sve2_nbsl, | |
722 | .vece = MO_64, | |
723 | .prefer_i64 = TCG_TARGET_REG_BITS == 64, | |
724 | }; | |
725 | tcg_gen_gvec_4(d, n, m, a, oprsz, maxsz, &op); | |
726 | } | |
727 | ||
b773a5c8 | 728 | TRANS_FEAT(NBSL, aa64_sve2, gen_gvec_fn_arg_zzzz, gen_nbsl, a) |
911cdc6d | 729 | |
fea98f9c RH |
730 | /* |
731 | *** SVE Integer Arithmetic - Unpredicated Group | |
732 | */ | |
733 | ||
b262215b RH |
734 | TRANS_FEAT(ADD_zzz, aa64_sve, gen_gvec_fn_arg_zzz, tcg_gen_gvec_add, a) |
735 | TRANS_FEAT(SUB_zzz, aa64_sve, gen_gvec_fn_arg_zzz, tcg_gen_gvec_sub, a) | |
736 | TRANS_FEAT(SQADD_zzz, aa64_sve, gen_gvec_fn_arg_zzz, tcg_gen_gvec_ssadd, a) | |
737 | TRANS_FEAT(SQSUB_zzz, aa64_sve, gen_gvec_fn_arg_zzz, tcg_gen_gvec_sssub, a) | |
738 | TRANS_FEAT(UQADD_zzz, aa64_sve, gen_gvec_fn_arg_zzz, tcg_gen_gvec_usadd, a) | |
739 | TRANS_FEAT(UQSUB_zzz, aa64_sve, gen_gvec_fn_arg_zzz, tcg_gen_gvec_ussub, a) | |
fea98f9c | 740 | |
f97cfd59 RH |
741 | /* |
742 | *** SVE Integer Arithmetic - Binary Predicated Group | |
743 | */ | |
744 | ||
a2103582 RH |
745 | /* Select active elememnts from Zn and inactive elements from Zm, |
746 | * storing the result in Zd. | |
747 | */ | |
68cc4ee3 | 748 | static bool do_sel_z(DisasContext *s, int rd, int rn, int rm, int pg, int esz) |
a2103582 RH |
749 | { |
750 | static gen_helper_gvec_4 * const fns[4] = { | |
751 | gen_helper_sve_sel_zpzz_b, gen_helper_sve_sel_zpzz_h, | |
752 | gen_helper_sve_sel_zpzz_s, gen_helper_sve_sel_zpzz_d | |
753 | }; | |
68cc4ee3 | 754 | return gen_gvec_ool_zzzp(s, fns[esz], rd, rn, rm, pg, 0); |
a2103582 RH |
755 | } |
756 | ||
8e7acb24 RH |
757 | #define DO_ZPZZ(NAME, FEAT, name) \ |
758 | static gen_helper_gvec_4 * const name##_zpzz_fns[4] = { \ | |
759 | gen_helper_##name##_zpzz_b, gen_helper_##name##_zpzz_h, \ | |
760 | gen_helper_##name##_zpzz_s, gen_helper_##name##_zpzz_d, \ | |
f97cfd59 | 761 | }; \ |
8e7acb24 RH |
762 | TRANS_FEAT(NAME, FEAT, gen_gvec_ool_arg_zpzz, \ |
763 | name##_zpzz_fns[a->esz], a, 0) | |
764 | ||
765 | DO_ZPZZ(AND_zpzz, aa64_sve, sve_and) | |
766 | DO_ZPZZ(EOR_zpzz, aa64_sve, sve_eor) | |
767 | DO_ZPZZ(ORR_zpzz, aa64_sve, sve_orr) | |
768 | DO_ZPZZ(BIC_zpzz, aa64_sve, sve_bic) | |
769 | ||
770 | DO_ZPZZ(ADD_zpzz, aa64_sve, sve_add) | |
771 | DO_ZPZZ(SUB_zpzz, aa64_sve, sve_sub) | |
772 | ||
773 | DO_ZPZZ(SMAX_zpzz, aa64_sve, sve_smax) | |
774 | DO_ZPZZ(UMAX_zpzz, aa64_sve, sve_umax) | |
775 | DO_ZPZZ(SMIN_zpzz, aa64_sve, sve_smin) | |
776 | DO_ZPZZ(UMIN_zpzz, aa64_sve, sve_umin) | |
777 | DO_ZPZZ(SABD_zpzz, aa64_sve, sve_sabd) | |
778 | DO_ZPZZ(UABD_zpzz, aa64_sve, sve_uabd) | |
779 | ||
780 | DO_ZPZZ(MUL_zpzz, aa64_sve, sve_mul) | |
781 | DO_ZPZZ(SMULH_zpzz, aa64_sve, sve_smulh) | |
782 | DO_ZPZZ(UMULH_zpzz, aa64_sve, sve_umulh) | |
783 | ||
784 | DO_ZPZZ(ASR_zpzz, aa64_sve, sve_asr) | |
785 | DO_ZPZZ(LSR_zpzz, aa64_sve, sve_lsr) | |
786 | DO_ZPZZ(LSL_zpzz, aa64_sve, sve_lsl) | |
787 | ||
788 | static gen_helper_gvec_4 * const sdiv_fns[4] = { | |
789 | NULL, NULL, gen_helper_sve_sdiv_zpzz_s, gen_helper_sve_sdiv_zpzz_d | |
790 | }; | |
791 | TRANS_FEAT(SDIV_zpzz, aa64_sve, gen_gvec_ool_arg_zpzz, sdiv_fns[a->esz], a, 0) | |
f97cfd59 | 792 | |
8e7acb24 RH |
793 | static gen_helper_gvec_4 * const udiv_fns[4] = { |
794 | NULL, NULL, gen_helper_sve_udiv_zpzz_s, gen_helper_sve_udiv_zpzz_d | |
795 | }; | |
796 | TRANS_FEAT(UDIV_zpzz, aa64_sve, gen_gvec_ool_arg_zpzz, udiv_fns[a->esz], a, 0) | |
f97cfd59 | 797 | |
3a7be554 | 798 | static bool trans_SEL_zpzz(DisasContext *s, arg_rprr_esz *a) |
a2103582 | 799 | { |
68cc4ee3 | 800 | return do_sel_z(s, a->rd, a->rn, a->rm, a->pg, a->esz); |
a2103582 | 801 | } |
d3fe4a29 | 802 | |
afac6d04 RH |
803 | /* |
804 | *** SVE Integer Arithmetic - Unary Predicated Group | |
805 | */ | |
806 | ||
817bd5c9 RH |
807 | #define DO_ZPZ(NAME, FEAT, name) \ |
808 | static gen_helper_gvec_3 * const name##_fns[4] = { \ | |
809 | gen_helper_##name##_b, gen_helper_##name##_h, \ | |
810 | gen_helper_##name##_s, gen_helper_##name##_d, \ | |
afac6d04 | 811 | }; \ |
817bd5c9 RH |
812 | TRANS_FEAT(NAME, FEAT, gen_gvec_ool_arg_zpz, name##_fns[a->esz], a, 0) |
813 | ||
814 | DO_ZPZ(CLS, aa64_sve, sve_cls) | |
815 | DO_ZPZ(CLZ, aa64_sve, sve_clz) | |
816 | DO_ZPZ(CNT_zpz, aa64_sve, sve_cnt_zpz) | |
817 | DO_ZPZ(CNOT, aa64_sve, sve_cnot) | |
818 | DO_ZPZ(NOT_zpz, aa64_sve, sve_not_zpz) | |
819 | DO_ZPZ(ABS, aa64_sve, sve_abs) | |
820 | DO_ZPZ(NEG, aa64_sve, sve_neg) | |
821 | DO_ZPZ(RBIT, aa64_sve, sve_rbit) | |
822 | ||
823 | static gen_helper_gvec_3 * const fabs_fns[4] = { | |
824 | NULL, gen_helper_sve_fabs_h, | |
825 | gen_helper_sve_fabs_s, gen_helper_sve_fabs_d, | |
826 | }; | |
827 | TRANS_FEAT(FABS, aa64_sve, gen_gvec_ool_arg_zpz, fabs_fns[a->esz], a, 0) | |
afac6d04 | 828 | |
817bd5c9 RH |
829 | static gen_helper_gvec_3 * const fneg_fns[4] = { |
830 | NULL, gen_helper_sve_fneg_h, | |
831 | gen_helper_sve_fneg_s, gen_helper_sve_fneg_d, | |
832 | }; | |
833 | TRANS_FEAT(FNEG, aa64_sve, gen_gvec_ool_arg_zpz, fneg_fns[a->esz], a, 0) | |
afac6d04 | 834 | |
817bd5c9 RH |
835 | static gen_helper_gvec_3 * const sxtb_fns[4] = { |
836 | NULL, gen_helper_sve_sxtb_h, | |
837 | gen_helper_sve_sxtb_s, gen_helper_sve_sxtb_d, | |
838 | }; | |
839 | TRANS_FEAT(SXTB, aa64_sve, gen_gvec_ool_arg_zpz, sxtb_fns[a->esz], a, 0) | |
afac6d04 | 840 | |
817bd5c9 RH |
841 | static gen_helper_gvec_3 * const uxtb_fns[4] = { |
842 | NULL, gen_helper_sve_uxtb_h, | |
843 | gen_helper_sve_uxtb_s, gen_helper_sve_uxtb_d, | |
844 | }; | |
845 | TRANS_FEAT(UXTB, aa64_sve, gen_gvec_ool_arg_zpz, uxtb_fns[a->esz], a, 0) | |
afac6d04 | 846 | |
817bd5c9 RH |
847 | static gen_helper_gvec_3 * const sxth_fns[4] = { |
848 | NULL, NULL, gen_helper_sve_sxth_s, gen_helper_sve_sxth_d | |
849 | }; | |
850 | TRANS_FEAT(SXTH, aa64_sve, gen_gvec_ool_arg_zpz, sxth_fns[a->esz], a, 0) | |
afac6d04 | 851 | |
817bd5c9 RH |
852 | static gen_helper_gvec_3 * const uxth_fns[4] = { |
853 | NULL, NULL, gen_helper_sve_uxth_s, gen_helper_sve_uxth_d | |
854 | }; | |
855 | TRANS_FEAT(UXTH, aa64_sve, gen_gvec_ool_arg_zpz, uxth_fns[a->esz], a, 0) | |
afac6d04 | 856 | |
817bd5c9 RH |
857 | TRANS_FEAT(SXTW, aa64_sve, gen_gvec_ool_arg_zpz, |
858 | a->esz == 3 ? gen_helper_sve_sxtw_d : NULL, a, 0) | |
859 | TRANS_FEAT(UXTW, aa64_sve, gen_gvec_ool_arg_zpz, | |
860 | a->esz == 3 ? gen_helper_sve_uxtw_d : NULL, a, 0) | |
afac6d04 | 861 | |
047cec97 RH |
862 | /* |
863 | *** SVE Integer Reduction Group | |
864 | */ | |
865 | ||
866 | typedef void gen_helper_gvec_reduc(TCGv_i64, TCGv_ptr, TCGv_ptr, TCGv_i32); | |
867 | static bool do_vpz_ool(DisasContext *s, arg_rpr_esz *a, | |
868 | gen_helper_gvec_reduc *fn) | |
869 | { | |
870 | unsigned vsz = vec_full_reg_size(s); | |
871 | TCGv_ptr t_zn, t_pg; | |
872 | TCGv_i32 desc; | |
873 | TCGv_i64 temp; | |
874 | ||
875 | if (fn == NULL) { | |
876 | return false; | |
877 | } | |
878 | if (!sve_access_check(s)) { | |
879 | return true; | |
880 | } | |
881 | ||
c6a59b55 | 882 | desc = tcg_constant_i32(simd_desc(vsz, vsz, 0)); |
047cec97 RH |
883 | temp = tcg_temp_new_i64(); |
884 | t_zn = tcg_temp_new_ptr(); | |
885 | t_pg = tcg_temp_new_ptr(); | |
886 | ||
887 | tcg_gen_addi_ptr(t_zn, cpu_env, vec_full_reg_offset(s, a->rn)); | |
888 | tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, a->pg)); | |
889 | fn(temp, t_zn, t_pg, desc); | |
890 | tcg_temp_free_ptr(t_zn); | |
891 | tcg_temp_free_ptr(t_pg); | |
047cec97 RH |
892 | |
893 | write_fp_dreg(s, a->rd, temp); | |
894 | tcg_temp_free_i64(temp); | |
895 | return true; | |
896 | } | |
897 | ||
898 | #define DO_VPZ(NAME, name) \ | |
9ac24f1f | 899 | static gen_helper_gvec_reduc * const name##_fns[4] = { \ |
047cec97 RH |
900 | gen_helper_sve_##name##_b, gen_helper_sve_##name##_h, \ |
901 | gen_helper_sve_##name##_s, gen_helper_sve_##name##_d, \ | |
902 | }; \ | |
9ac24f1f | 903 | TRANS_FEAT(NAME, aa64_sve, do_vpz_ool, a, name##_fns[a->esz]) |
047cec97 RH |
904 | |
905 | DO_VPZ(ORV, orv) | |
906 | DO_VPZ(ANDV, andv) | |
907 | DO_VPZ(EORV, eorv) | |
908 | ||
909 | DO_VPZ(UADDV, uaddv) | |
910 | DO_VPZ(SMAXV, smaxv) | |
911 | DO_VPZ(UMAXV, umaxv) | |
912 | DO_VPZ(SMINV, sminv) | |
913 | DO_VPZ(UMINV, uminv) | |
914 | ||
9ac24f1f RH |
915 | static gen_helper_gvec_reduc * const saddv_fns[4] = { |
916 | gen_helper_sve_saddv_b, gen_helper_sve_saddv_h, | |
917 | gen_helper_sve_saddv_s, NULL | |
918 | }; | |
919 | TRANS_FEAT(SADDV, aa64_sve, do_vpz_ool, a, saddv_fns[a->esz]) | |
047cec97 RH |
920 | |
921 | #undef DO_VPZ | |
922 | ||
ccd841c3 RH |
923 | /* |
924 | *** SVE Shift by Immediate - Predicated Group | |
925 | */ | |
926 | ||
60245996 RH |
927 | /* |
928 | * Copy Zn into Zd, storing zeros into inactive elements. | |
929 | * If invert, store zeros into the active elements. | |
ccd841c3 | 930 | */ |
60245996 RH |
931 | static bool do_movz_zpz(DisasContext *s, int rd, int rn, int pg, |
932 | int esz, bool invert) | |
ccd841c3 | 933 | { |
60245996 RH |
934 | static gen_helper_gvec_3 * const fns[4] = { |
935 | gen_helper_sve_movz_b, gen_helper_sve_movz_h, | |
936 | gen_helper_sve_movz_s, gen_helper_sve_movz_d, | |
ccd841c3 | 937 | }; |
8fb27a21 | 938 | return gen_gvec_ool_zzp(s, fns[esz], rd, rn, pg, invert); |
ccd841c3 RH |
939 | } |
940 | ||
73c558a8 RH |
941 | static bool do_shift_zpzi(DisasContext *s, arg_rpri_esz *a, bool asr, |
942 | gen_helper_gvec_3 * const fns[4]) | |
ccd841c3 | 943 | { |
73c558a8 RH |
944 | int max; |
945 | ||
ccd841c3 RH |
946 | if (a->esz < 0) { |
947 | /* Invalid tsz encoding -- see tszimm_esz. */ | |
948 | return false; | |
949 | } | |
73c558a8 RH |
950 | |
951 | /* | |
952 | * Shift by element size is architecturally valid. | |
953 | * For arithmetic right-shift, it's the same as by one less. | |
954 | * For logical shifts and ASRD, it is a zeroing operation. | |
955 | */ | |
956 | max = 8 << a->esz; | |
957 | if (a->imm >= max) { | |
958 | if (asr) { | |
959 | a->imm = max - 1; | |
960 | } else { | |
961 | return do_movz_zpz(s, a->rd, a->rd, a->pg, a->esz, true); | |
962 | } | |
963 | } | |
afa2529c | 964 | return gen_gvec_ool_arg_zpzi(s, fns[a->esz], a); |
ccd841c3 RH |
965 | } |
966 | ||
5cccd1f1 RH |
967 | static gen_helper_gvec_3 * const asr_zpzi_fns[4] = { |
968 | gen_helper_sve_asr_zpzi_b, gen_helper_sve_asr_zpzi_h, | |
969 | gen_helper_sve_asr_zpzi_s, gen_helper_sve_asr_zpzi_d, | |
970 | }; | |
971 | TRANS_FEAT(ASR_zpzi, aa64_sve, do_shift_zpzi, a, true, asr_zpzi_fns) | |
73c558a8 | 972 | |
5cccd1f1 RH |
973 | static gen_helper_gvec_3 * const lsr_zpzi_fns[4] = { |
974 | gen_helper_sve_lsr_zpzi_b, gen_helper_sve_lsr_zpzi_h, | |
975 | gen_helper_sve_lsr_zpzi_s, gen_helper_sve_lsr_zpzi_d, | |
976 | }; | |
977 | TRANS_FEAT(LSR_zpzi, aa64_sve, do_shift_zpzi, a, false, lsr_zpzi_fns) | |
ccd841c3 | 978 | |
5cccd1f1 RH |
979 | static gen_helper_gvec_3 * const lsl_zpzi_fns[4] = { |
980 | gen_helper_sve_lsl_zpzi_b, gen_helper_sve_lsl_zpzi_h, | |
981 | gen_helper_sve_lsl_zpzi_s, gen_helper_sve_lsl_zpzi_d, | |
982 | }; | |
983 | TRANS_FEAT(LSL_zpzi, aa64_sve, do_shift_zpzi, a, false, lsl_zpzi_fns) | |
ccd841c3 | 984 | |
5cccd1f1 RH |
985 | static gen_helper_gvec_3 * const asrd_fns[4] = { |
986 | gen_helper_sve_asrd_b, gen_helper_sve_asrd_h, | |
987 | gen_helper_sve_asrd_s, gen_helper_sve_asrd_d, | |
988 | }; | |
989 | TRANS_FEAT(ASRD, aa64_sve, do_shift_zpzi, a, false, asrd_fns) | |
ccd841c3 | 990 | |
4df37e41 RH |
991 | static gen_helper_gvec_3 * const sqshl_zpzi_fns[4] = { |
992 | gen_helper_sve2_sqshl_zpzi_b, gen_helper_sve2_sqshl_zpzi_h, | |
993 | gen_helper_sve2_sqshl_zpzi_s, gen_helper_sve2_sqshl_zpzi_d, | |
994 | }; | |
995 | TRANS_FEAT(SQSHL_zpzi, aa64_sve2, gen_gvec_ool_arg_zpzi, | |
996 | a->esz < 0 ? NULL : sqshl_zpzi_fns[a->esz], a) | |
a5421b54 | 997 | |
4df37e41 RH |
998 | static gen_helper_gvec_3 * const uqshl_zpzi_fns[4] = { |
999 | gen_helper_sve2_uqshl_zpzi_b, gen_helper_sve2_uqshl_zpzi_h, | |
1000 | gen_helper_sve2_uqshl_zpzi_s, gen_helper_sve2_uqshl_zpzi_d, | |
1001 | }; | |
1002 | TRANS_FEAT(UQSHL_zpzi, aa64_sve2, gen_gvec_ool_arg_zpzi, | |
1003 | a->esz < 0 ? NULL : uqshl_zpzi_fns[a->esz], a) | |
a5421b54 | 1004 | |
4df37e41 RH |
1005 | static gen_helper_gvec_3 * const srshr_fns[4] = { |
1006 | gen_helper_sve2_srshr_b, gen_helper_sve2_srshr_h, | |
1007 | gen_helper_sve2_srshr_s, gen_helper_sve2_srshr_d, | |
1008 | }; | |
1009 | TRANS_FEAT(SRSHR, aa64_sve2, gen_gvec_ool_arg_zpzi, | |
1010 | a->esz < 0 ? NULL : srshr_fns[a->esz], a) | |
a5421b54 | 1011 | |
4df37e41 RH |
1012 | static gen_helper_gvec_3 * const urshr_fns[4] = { |
1013 | gen_helper_sve2_urshr_b, gen_helper_sve2_urshr_h, | |
1014 | gen_helper_sve2_urshr_s, gen_helper_sve2_urshr_d, | |
1015 | }; | |
1016 | TRANS_FEAT(URSHR, aa64_sve2, gen_gvec_ool_arg_zpzi, | |
1017 | a->esz < 0 ? NULL : urshr_fns[a->esz], a) | |
a5421b54 | 1018 | |
4df37e41 RH |
1019 | static gen_helper_gvec_3 * const sqshlu_fns[4] = { |
1020 | gen_helper_sve2_sqshlu_b, gen_helper_sve2_sqshlu_h, | |
1021 | gen_helper_sve2_sqshlu_s, gen_helper_sve2_sqshlu_d, | |
1022 | }; | |
1023 | TRANS_FEAT(SQSHLU, aa64_sve2, gen_gvec_ool_arg_zpzi, | |
1024 | a->esz < 0 ? NULL : sqshlu_fns[a->esz], a) | |
a5421b54 | 1025 | |
fe7f8dfb RH |
1026 | /* |
1027 | *** SVE Bitwise Shift - Predicated Group | |
1028 | */ | |
1029 | ||
1030 | #define DO_ZPZW(NAME, name) \ | |
8e7acb24 | 1031 | static gen_helper_gvec_4 * const name##_zpzw_fns[4] = { \ |
fe7f8dfb | 1032 | gen_helper_sve_##name##_zpzw_b, gen_helper_sve_##name##_zpzw_h, \ |
8e7acb24 | 1033 | gen_helper_sve_##name##_zpzw_s, NULL \ |
fe7f8dfb | 1034 | }; \ |
8e7acb24 RH |
1035 | TRANS_FEAT(NAME##_zpzw, aa64_sve, gen_gvec_ool_arg_zpzz, \ |
1036 | a->esz < 0 ? NULL : name##_zpzw_fns[a->esz], a, 0) | |
fe7f8dfb RH |
1037 | |
1038 | DO_ZPZW(ASR, asr) | |
1039 | DO_ZPZW(LSR, lsr) | |
1040 | DO_ZPZW(LSL, lsl) | |
1041 | ||
1042 | #undef DO_ZPZW | |
1043 | ||
d9d78dcc RH |
1044 | /* |
1045 | *** SVE Bitwise Shift - Unpredicated Group | |
1046 | */ | |
1047 | ||
1048 | static bool do_shift_imm(DisasContext *s, arg_rri_esz *a, bool asr, | |
1049 | void (*gvec_fn)(unsigned, uint32_t, uint32_t, | |
1050 | int64_t, uint32_t, uint32_t)) | |
1051 | { | |
1052 | if (a->esz < 0) { | |
1053 | /* Invalid tsz encoding -- see tszimm_esz. */ | |
1054 | return false; | |
1055 | } | |
1056 | if (sve_access_check(s)) { | |
1057 | unsigned vsz = vec_full_reg_size(s); | |
1058 | /* Shift by element size is architecturally valid. For | |
1059 | arithmetic right-shift, it's the same as by one less. | |
1060 | Otherwise it is a zeroing operation. */ | |
1061 | if (a->imm >= 8 << a->esz) { | |
1062 | if (asr) { | |
1063 | a->imm = (8 << a->esz) - 1; | |
1064 | } else { | |
1065 | do_dupi_z(s, a->rd, 0); | |
1066 | return true; | |
1067 | } | |
1068 | } | |
1069 | gvec_fn(a->esz, vec_full_reg_offset(s, a->rd), | |
1070 | vec_full_reg_offset(s, a->rn), a->imm, vsz, vsz); | |
1071 | } | |
1072 | return true; | |
1073 | } | |
1074 | ||
5e612f80 RH |
1075 | TRANS_FEAT(ASR_zzi, aa64_sve, do_shift_imm, a, true, tcg_gen_gvec_sari) |
1076 | TRANS_FEAT(LSR_zzi, aa64_sve, do_shift_imm, a, false, tcg_gen_gvec_shri) | |
1077 | TRANS_FEAT(LSL_zzi, aa64_sve, do_shift_imm, a, false, tcg_gen_gvec_shli) | |
d9d78dcc | 1078 | |
d9d78dcc | 1079 | #define DO_ZZW(NAME, name) \ |
32e2ad65 | 1080 | static gen_helper_gvec_3 * const name##_zzw_fns[4] = { \ |
d9d78dcc RH |
1081 | gen_helper_sve_##name##_zzw_b, gen_helper_sve_##name##_zzw_h, \ |
1082 | gen_helper_sve_##name##_zzw_s, NULL \ | |
1083 | }; \ | |
32e2ad65 RH |
1084 | TRANS_FEAT(NAME, aa64_sve, gen_gvec_ool_arg_zzz, \ |
1085 | name##_zzw_fns[a->esz], a, 0) | |
d9d78dcc | 1086 | |
32e2ad65 RH |
1087 | DO_ZZW(ASR_zzw, asr) |
1088 | DO_ZZW(LSR_zzw, lsr) | |
1089 | DO_ZZW(LSL_zzw, lsl) | |
d9d78dcc RH |
1090 | |
1091 | #undef DO_ZZW | |
1092 | ||
96a36e4a RH |
1093 | /* |
1094 | *** SVE Integer Multiply-Add Group | |
1095 | */ | |
1096 | ||
1097 | static bool do_zpzzz_ool(DisasContext *s, arg_rprrr_esz *a, | |
1098 | gen_helper_gvec_5 *fn) | |
1099 | { | |
1100 | if (sve_access_check(s)) { | |
1101 | unsigned vsz = vec_full_reg_size(s); | |
1102 | tcg_gen_gvec_5_ool(vec_full_reg_offset(s, a->rd), | |
1103 | vec_full_reg_offset(s, a->ra), | |
1104 | vec_full_reg_offset(s, a->rn), | |
1105 | vec_full_reg_offset(s, a->rm), | |
1106 | pred_full_reg_offset(s, a->pg), | |
1107 | vsz, vsz, 0, fn); | |
1108 | } | |
1109 | return true; | |
1110 | } | |
1111 | ||
dc67e645 RH |
1112 | static gen_helper_gvec_5 * const mla_fns[4] = { |
1113 | gen_helper_sve_mla_b, gen_helper_sve_mla_h, | |
1114 | gen_helper_sve_mla_s, gen_helper_sve_mla_d, | |
1115 | }; | |
1116 | TRANS_FEAT(MLA, aa64_sve, do_zpzzz_ool, a, mla_fns[a->esz]) | |
96a36e4a | 1117 | |
dc67e645 RH |
1118 | static gen_helper_gvec_5 * const mls_fns[4] = { |
1119 | gen_helper_sve_mls_b, gen_helper_sve_mls_h, | |
1120 | gen_helper_sve_mls_s, gen_helper_sve_mls_d, | |
1121 | }; | |
1122 | TRANS_FEAT(MLS, aa64_sve, do_zpzzz_ool, a, mls_fns[a->esz]) | |
96a36e4a | 1123 | |
9a56c9c3 RH |
1124 | /* |
1125 | *** SVE Index Generation Group | |
1126 | */ | |
1127 | ||
6687d05d | 1128 | static bool do_index(DisasContext *s, int esz, int rd, |
9a56c9c3 RH |
1129 | TCGv_i64 start, TCGv_i64 incr) |
1130 | { | |
6687d05d RH |
1131 | unsigned vsz; |
1132 | TCGv_i32 desc; | |
1133 | TCGv_ptr t_zd; | |
1134 | ||
1135 | if (!sve_access_check(s)) { | |
1136 | return true; | |
1137 | } | |
1138 | ||
1139 | vsz = vec_full_reg_size(s); | |
1140 | desc = tcg_constant_i32(simd_desc(vsz, vsz, 0)); | |
1141 | t_zd = tcg_temp_new_ptr(); | |
9a56c9c3 RH |
1142 | |
1143 | tcg_gen_addi_ptr(t_zd, cpu_env, vec_full_reg_offset(s, rd)); | |
1144 | if (esz == 3) { | |
1145 | gen_helper_sve_index_d(t_zd, start, incr, desc); | |
1146 | } else { | |
1147 | typedef void index_fn(TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32); | |
1148 | static index_fn * const fns[3] = { | |
1149 | gen_helper_sve_index_b, | |
1150 | gen_helper_sve_index_h, | |
1151 | gen_helper_sve_index_s, | |
1152 | }; | |
1153 | TCGv_i32 s32 = tcg_temp_new_i32(); | |
1154 | TCGv_i32 i32 = tcg_temp_new_i32(); | |
1155 | ||
1156 | tcg_gen_extrl_i64_i32(s32, start); | |
1157 | tcg_gen_extrl_i64_i32(i32, incr); | |
1158 | fns[esz](t_zd, s32, i32, desc); | |
1159 | ||
1160 | tcg_temp_free_i32(s32); | |
1161 | tcg_temp_free_i32(i32); | |
1162 | } | |
1163 | tcg_temp_free_ptr(t_zd); | |
6687d05d | 1164 | return true; |
9a56c9c3 RH |
1165 | } |
1166 | ||
9aa60c83 RH |
1167 | TRANS_FEAT(INDEX_ii, aa64_sve, do_index, a->esz, a->rd, |
1168 | tcg_constant_i64(a->imm1), tcg_constant_i64(a->imm2)) | |
1169 | TRANS_FEAT(INDEX_ir, aa64_sve, do_index, a->esz, a->rd, | |
1170 | tcg_constant_i64(a->imm), cpu_reg(s, a->rm)) | |
1171 | TRANS_FEAT(INDEX_ri, aa64_sve, do_index, a->esz, a->rd, | |
1172 | cpu_reg(s, a->rn), tcg_constant_i64(a->imm)) | |
1173 | TRANS_FEAT(INDEX_rr, aa64_sve, do_index, a->esz, a->rd, | |
1174 | cpu_reg(s, a->rn), cpu_reg(s, a->rm)) | |
9a56c9c3 | 1175 | |
96f922cc RH |
1176 | /* |
1177 | *** SVE Stack Allocation Group | |
1178 | */ | |
1179 | ||
3a7be554 | 1180 | static bool trans_ADDVL(DisasContext *s, arg_ADDVL *a) |
96f922cc | 1181 | { |
5de56742 AC |
1182 | if (sve_access_check(s)) { |
1183 | TCGv_i64 rd = cpu_reg_sp(s, a->rd); | |
1184 | TCGv_i64 rn = cpu_reg_sp(s, a->rn); | |
1185 | tcg_gen_addi_i64(rd, rn, a->imm * vec_full_reg_size(s)); | |
1186 | } | |
96f922cc RH |
1187 | return true; |
1188 | } | |
1189 | ||
3a7be554 | 1190 | static bool trans_ADDPL(DisasContext *s, arg_ADDPL *a) |
96f922cc | 1191 | { |
5de56742 AC |
1192 | if (sve_access_check(s)) { |
1193 | TCGv_i64 rd = cpu_reg_sp(s, a->rd); | |
1194 | TCGv_i64 rn = cpu_reg_sp(s, a->rn); | |
1195 | tcg_gen_addi_i64(rd, rn, a->imm * pred_full_reg_size(s)); | |
1196 | } | |
96f922cc RH |
1197 | return true; |
1198 | } | |
1199 | ||
3a7be554 | 1200 | static bool trans_RDVL(DisasContext *s, arg_RDVL *a) |
96f922cc | 1201 | { |
5de56742 AC |
1202 | if (sve_access_check(s)) { |
1203 | TCGv_i64 reg = cpu_reg(s, a->rd); | |
1204 | tcg_gen_movi_i64(reg, a->imm * vec_full_reg_size(s)); | |
1205 | } | |
96f922cc RH |
1206 | return true; |
1207 | } | |
1208 | ||
4b242d9c RH |
1209 | /* |
1210 | *** SVE Compute Vector Address Group | |
1211 | */ | |
1212 | ||
1213 | static bool do_adr(DisasContext *s, arg_rrri *a, gen_helper_gvec_3 *fn) | |
1214 | { | |
913a8a00 | 1215 | return gen_gvec_ool_zzz(s, fn, a->rd, a->rn, a->rm, a->imm); |
4b242d9c RH |
1216 | } |
1217 | ||
dcba3d67 RH |
1218 | TRANS_FEAT(ADR_p32, aa64_sve, do_adr, a, gen_helper_sve_adr_p32) |
1219 | TRANS_FEAT(ADR_p64, aa64_sve, do_adr, a, gen_helper_sve_adr_p64) | |
1220 | TRANS_FEAT(ADR_s32, aa64_sve, do_adr, a, gen_helper_sve_adr_s32) | |
1221 | TRANS_FEAT(ADR_u32, aa64_sve, do_adr, a, gen_helper_sve_adr_u32) | |
4b242d9c | 1222 | |
0762cd42 RH |
1223 | /* |
1224 | *** SVE Integer Misc - Unpredicated Group | |
1225 | */ | |
1226 | ||
0ea3cdbf RH |
1227 | static gen_helper_gvec_2 * const fexpa_fns[4] = { |
1228 | NULL, gen_helper_sve_fexpa_h, | |
1229 | gen_helper_sve_fexpa_s, gen_helper_sve_fexpa_d, | |
1230 | }; | |
1231 | TRANS_FEAT(FEXPA, aa64_sve, gen_gvec_ool_zz, | |
1232 | fexpa_fns[a->esz], a->rd, a->rn, 0) | |
0762cd42 | 1233 | |
32e2ad65 RH |
1234 | static gen_helper_gvec_3 * const ftssel_fns[4] = { |
1235 | NULL, gen_helper_sve_ftssel_h, | |
1236 | gen_helper_sve_ftssel_s, gen_helper_sve_ftssel_d, | |
1237 | }; | |
1238 | TRANS_FEAT(FTSSEL, aa64_sve, gen_gvec_ool_arg_zzz, ftssel_fns[a->esz], a, 0) | |
a1f233f2 | 1239 | |
516e246a RH |
1240 | /* |
1241 | *** SVE Predicate Logical Operations Group | |
1242 | */ | |
1243 | ||
1244 | static bool do_pppp_flags(DisasContext *s, arg_rprr_s *a, | |
1245 | const GVecGen4 *gvec_op) | |
1246 | { | |
1247 | if (!sve_access_check(s)) { | |
1248 | return true; | |
1249 | } | |
1250 | ||
1251 | unsigned psz = pred_gvec_reg_size(s); | |
1252 | int dofs = pred_full_reg_offset(s, a->rd); | |
1253 | int nofs = pred_full_reg_offset(s, a->rn); | |
1254 | int mofs = pred_full_reg_offset(s, a->rm); | |
1255 | int gofs = pred_full_reg_offset(s, a->pg); | |
1256 | ||
dd81a8d7 RH |
1257 | if (!a->s) { |
1258 | tcg_gen_gvec_4(dofs, nofs, mofs, gofs, psz, psz, gvec_op); | |
1259 | return true; | |
1260 | } | |
1261 | ||
516e246a RH |
1262 | if (psz == 8) { |
1263 | /* Do the operation and the flags generation in temps. */ | |
1264 | TCGv_i64 pd = tcg_temp_new_i64(); | |
1265 | TCGv_i64 pn = tcg_temp_new_i64(); | |
1266 | TCGv_i64 pm = tcg_temp_new_i64(); | |
1267 | TCGv_i64 pg = tcg_temp_new_i64(); | |
1268 | ||
1269 | tcg_gen_ld_i64(pn, cpu_env, nofs); | |
1270 | tcg_gen_ld_i64(pm, cpu_env, mofs); | |
1271 | tcg_gen_ld_i64(pg, cpu_env, gofs); | |
1272 | ||
1273 | gvec_op->fni8(pd, pn, pm, pg); | |
1274 | tcg_gen_st_i64(pd, cpu_env, dofs); | |
1275 | ||
1276 | do_predtest1(pd, pg); | |
1277 | ||
1278 | tcg_temp_free_i64(pd); | |
1279 | tcg_temp_free_i64(pn); | |
1280 | tcg_temp_free_i64(pm); | |
1281 | tcg_temp_free_i64(pg); | |
1282 | } else { | |
1283 | /* The operation and flags generation is large. The computation | |
1284 | * of the flags depends on the original contents of the guarding | |
1285 | * predicate. If the destination overwrites the guarding predicate, | |
1286 | * then the easiest way to get this right is to save a copy. | |
1287 | */ | |
1288 | int tofs = gofs; | |
1289 | if (a->rd == a->pg) { | |
1290 | tofs = offsetof(CPUARMState, vfp.preg_tmp); | |
1291 | tcg_gen_gvec_mov(0, tofs, gofs, psz, psz); | |
1292 | } | |
1293 | ||
1294 | tcg_gen_gvec_4(dofs, nofs, mofs, gofs, psz, psz, gvec_op); | |
1295 | do_predtest(s, dofs, tofs, psz / 8); | |
1296 | } | |
1297 | return true; | |
1298 | } | |
1299 | ||
1300 | static void gen_and_pg_i64(TCGv_i64 pd, TCGv_i64 pn, TCGv_i64 pm, TCGv_i64 pg) | |
1301 | { | |
1302 | tcg_gen_and_i64(pd, pn, pm); | |
1303 | tcg_gen_and_i64(pd, pd, pg); | |
1304 | } | |
1305 | ||
1306 | static void gen_and_pg_vec(unsigned vece, TCGv_vec pd, TCGv_vec pn, | |
1307 | TCGv_vec pm, TCGv_vec pg) | |
1308 | { | |
1309 | tcg_gen_and_vec(vece, pd, pn, pm); | |
1310 | tcg_gen_and_vec(vece, pd, pd, pg); | |
1311 | } | |
1312 | ||
3a7be554 | 1313 | static bool trans_AND_pppp(DisasContext *s, arg_rprr_s *a) |
516e246a RH |
1314 | { |
1315 | static const GVecGen4 op = { | |
1316 | .fni8 = gen_and_pg_i64, | |
1317 | .fniv = gen_and_pg_vec, | |
1318 | .fno = gen_helper_sve_and_pppp, | |
1319 | .prefer_i64 = TCG_TARGET_REG_BITS == 64, | |
1320 | }; | |
dd81a8d7 RH |
1321 | |
1322 | if (!a->s) { | |
dd81a8d7 RH |
1323 | if (a->rn == a->rm) { |
1324 | if (a->pg == a->rn) { | |
23e5fa5f | 1325 | return do_mov_p(s, a->rd, a->rn); |
dd81a8d7 | 1326 | } |
23e5fa5f | 1327 | return gen_gvec_fn_ppp(s, tcg_gen_gvec_and, a->rd, a->rn, a->pg); |
dd81a8d7 | 1328 | } else if (a->pg == a->rn || a->pg == a->rm) { |
23e5fa5f | 1329 | return gen_gvec_fn_ppp(s, tcg_gen_gvec_and, a->rd, a->rn, a->rm); |
516e246a | 1330 | } |
516e246a | 1331 | } |
dd81a8d7 | 1332 | return do_pppp_flags(s, a, &op); |
516e246a RH |
1333 | } |
1334 | ||
1335 | static void gen_bic_pg_i64(TCGv_i64 pd, TCGv_i64 pn, TCGv_i64 pm, TCGv_i64 pg) | |
1336 | { | |
1337 | tcg_gen_andc_i64(pd, pn, pm); | |
1338 | tcg_gen_and_i64(pd, pd, pg); | |
1339 | } | |
1340 | ||
1341 | static void gen_bic_pg_vec(unsigned vece, TCGv_vec pd, TCGv_vec pn, | |
1342 | TCGv_vec pm, TCGv_vec pg) | |
1343 | { | |
1344 | tcg_gen_andc_vec(vece, pd, pn, pm); | |
1345 | tcg_gen_and_vec(vece, pd, pd, pg); | |
1346 | } | |
1347 | ||
3a7be554 | 1348 | static bool trans_BIC_pppp(DisasContext *s, arg_rprr_s *a) |
516e246a RH |
1349 | { |
1350 | static const GVecGen4 op = { | |
1351 | .fni8 = gen_bic_pg_i64, | |
1352 | .fniv = gen_bic_pg_vec, | |
1353 | .fno = gen_helper_sve_bic_pppp, | |
1354 | .prefer_i64 = TCG_TARGET_REG_BITS == 64, | |
1355 | }; | |
dd81a8d7 RH |
1356 | |
1357 | if (!a->s && a->pg == a->rn) { | |
23e5fa5f | 1358 | return gen_gvec_fn_ppp(s, tcg_gen_gvec_andc, a->rd, a->rn, a->rm); |
516e246a | 1359 | } |
dd81a8d7 | 1360 | return do_pppp_flags(s, a, &op); |
516e246a RH |
1361 | } |
1362 | ||
1363 | static void gen_eor_pg_i64(TCGv_i64 pd, TCGv_i64 pn, TCGv_i64 pm, TCGv_i64 pg) | |
1364 | { | |
1365 | tcg_gen_xor_i64(pd, pn, pm); | |
1366 | tcg_gen_and_i64(pd, pd, pg); | |
1367 | } | |
1368 | ||
1369 | static void gen_eor_pg_vec(unsigned vece, TCGv_vec pd, TCGv_vec pn, | |
1370 | TCGv_vec pm, TCGv_vec pg) | |
1371 | { | |
1372 | tcg_gen_xor_vec(vece, pd, pn, pm); | |
1373 | tcg_gen_and_vec(vece, pd, pd, pg); | |
1374 | } | |
1375 | ||
3a7be554 | 1376 | static bool trans_EOR_pppp(DisasContext *s, arg_rprr_s *a) |
516e246a RH |
1377 | { |
1378 | static const GVecGen4 op = { | |
1379 | .fni8 = gen_eor_pg_i64, | |
1380 | .fniv = gen_eor_pg_vec, | |
1381 | .fno = gen_helper_sve_eor_pppp, | |
1382 | .prefer_i64 = TCG_TARGET_REG_BITS == 64, | |
1383 | }; | |
738b679c RH |
1384 | |
1385 | /* Alias NOT (predicate) is EOR Pd.B, Pg/Z, Pn.B, Pg.B */ | |
1386 | if (!a->s && a->pg == a->rm) { | |
1387 | return gen_gvec_fn_ppp(s, tcg_gen_gvec_andc, a->rd, a->pg, a->rn); | |
1388 | } | |
dd81a8d7 | 1389 | return do_pppp_flags(s, a, &op); |
516e246a RH |
1390 | } |
1391 | ||
3a7be554 | 1392 | static bool trans_SEL_pppp(DisasContext *s, arg_rprr_s *a) |
516e246a | 1393 | { |
516e246a RH |
1394 | if (a->s) { |
1395 | return false; | |
516e246a | 1396 | } |
d4bc6232 RH |
1397 | if (sve_access_check(s)) { |
1398 | unsigned psz = pred_gvec_reg_size(s); | |
1399 | tcg_gen_gvec_bitsel(MO_8, pred_full_reg_offset(s, a->rd), | |
1400 | pred_full_reg_offset(s, a->pg), | |
1401 | pred_full_reg_offset(s, a->rn), | |
1402 | pred_full_reg_offset(s, a->rm), psz, psz); | |
1403 | } | |
1404 | return true; | |
516e246a RH |
1405 | } |
1406 | ||
1407 | static void gen_orr_pg_i64(TCGv_i64 pd, TCGv_i64 pn, TCGv_i64 pm, TCGv_i64 pg) | |
1408 | { | |
1409 | tcg_gen_or_i64(pd, pn, pm); | |
1410 | tcg_gen_and_i64(pd, pd, pg); | |
1411 | } | |
1412 | ||
1413 | static void gen_orr_pg_vec(unsigned vece, TCGv_vec pd, TCGv_vec pn, | |
1414 | TCGv_vec pm, TCGv_vec pg) | |
1415 | { | |
1416 | tcg_gen_or_vec(vece, pd, pn, pm); | |
1417 | tcg_gen_and_vec(vece, pd, pd, pg); | |
1418 | } | |
1419 | ||
3a7be554 | 1420 | static bool trans_ORR_pppp(DisasContext *s, arg_rprr_s *a) |
516e246a RH |
1421 | { |
1422 | static const GVecGen4 op = { | |
1423 | .fni8 = gen_orr_pg_i64, | |
1424 | .fniv = gen_orr_pg_vec, | |
1425 | .fno = gen_helper_sve_orr_pppp, | |
1426 | .prefer_i64 = TCG_TARGET_REG_BITS == 64, | |
1427 | }; | |
dd81a8d7 RH |
1428 | |
1429 | if (!a->s && a->pg == a->rn && a->rn == a->rm) { | |
516e246a | 1430 | return do_mov_p(s, a->rd, a->rn); |
516e246a | 1431 | } |
dd81a8d7 | 1432 | return do_pppp_flags(s, a, &op); |
516e246a RH |
1433 | } |
1434 | ||
1435 | static void gen_orn_pg_i64(TCGv_i64 pd, TCGv_i64 pn, TCGv_i64 pm, TCGv_i64 pg) | |
1436 | { | |
1437 | tcg_gen_orc_i64(pd, pn, pm); | |
1438 | tcg_gen_and_i64(pd, pd, pg); | |
1439 | } | |
1440 | ||
1441 | static void gen_orn_pg_vec(unsigned vece, TCGv_vec pd, TCGv_vec pn, | |
1442 | TCGv_vec pm, TCGv_vec pg) | |
1443 | { | |
1444 | tcg_gen_orc_vec(vece, pd, pn, pm); | |
1445 | tcg_gen_and_vec(vece, pd, pd, pg); | |
1446 | } | |
1447 | ||
3a7be554 | 1448 | static bool trans_ORN_pppp(DisasContext *s, arg_rprr_s *a) |
516e246a RH |
1449 | { |
1450 | static const GVecGen4 op = { | |
1451 | .fni8 = gen_orn_pg_i64, | |
1452 | .fniv = gen_orn_pg_vec, | |
1453 | .fno = gen_helper_sve_orn_pppp, | |
1454 | .prefer_i64 = TCG_TARGET_REG_BITS == 64, | |
1455 | }; | |
dd81a8d7 | 1456 | return do_pppp_flags(s, a, &op); |
516e246a RH |
1457 | } |
1458 | ||
1459 | static void gen_nor_pg_i64(TCGv_i64 pd, TCGv_i64 pn, TCGv_i64 pm, TCGv_i64 pg) | |
1460 | { | |
1461 | tcg_gen_or_i64(pd, pn, pm); | |
1462 | tcg_gen_andc_i64(pd, pg, pd); | |
1463 | } | |
1464 | ||
1465 | static void gen_nor_pg_vec(unsigned vece, TCGv_vec pd, TCGv_vec pn, | |
1466 | TCGv_vec pm, TCGv_vec pg) | |
1467 | { | |
1468 | tcg_gen_or_vec(vece, pd, pn, pm); | |
1469 | tcg_gen_andc_vec(vece, pd, pg, pd); | |
1470 | } | |
1471 | ||
3a7be554 | 1472 | static bool trans_NOR_pppp(DisasContext *s, arg_rprr_s *a) |
516e246a RH |
1473 | { |
1474 | static const GVecGen4 op = { | |
1475 | .fni8 = gen_nor_pg_i64, | |
1476 | .fniv = gen_nor_pg_vec, | |
1477 | .fno = gen_helper_sve_nor_pppp, | |
1478 | .prefer_i64 = TCG_TARGET_REG_BITS == 64, | |
1479 | }; | |
dd81a8d7 | 1480 | return do_pppp_flags(s, a, &op); |
516e246a RH |
1481 | } |
1482 | ||
1483 | static void gen_nand_pg_i64(TCGv_i64 pd, TCGv_i64 pn, TCGv_i64 pm, TCGv_i64 pg) | |
1484 | { | |
1485 | tcg_gen_and_i64(pd, pn, pm); | |
1486 | tcg_gen_andc_i64(pd, pg, pd); | |
1487 | } | |
1488 | ||
1489 | static void gen_nand_pg_vec(unsigned vece, TCGv_vec pd, TCGv_vec pn, | |
1490 | TCGv_vec pm, TCGv_vec pg) | |
1491 | { | |
1492 | tcg_gen_and_vec(vece, pd, pn, pm); | |
1493 | tcg_gen_andc_vec(vece, pd, pg, pd); | |
1494 | } | |
1495 | ||
3a7be554 | 1496 | static bool trans_NAND_pppp(DisasContext *s, arg_rprr_s *a) |
516e246a RH |
1497 | { |
1498 | static const GVecGen4 op = { | |
1499 | .fni8 = gen_nand_pg_i64, | |
1500 | .fniv = gen_nand_pg_vec, | |
1501 | .fno = gen_helper_sve_nand_pppp, | |
1502 | .prefer_i64 = TCG_TARGET_REG_BITS == 64, | |
1503 | }; | |
dd81a8d7 | 1504 | return do_pppp_flags(s, a, &op); |
516e246a RH |
1505 | } |
1506 | ||
9e18d7a6 RH |
1507 | /* |
1508 | *** SVE Predicate Misc Group | |
1509 | */ | |
1510 | ||
3a7be554 | 1511 | static bool trans_PTEST(DisasContext *s, arg_PTEST *a) |
9e18d7a6 RH |
1512 | { |
1513 | if (sve_access_check(s)) { | |
1514 | int nofs = pred_full_reg_offset(s, a->rn); | |
1515 | int gofs = pred_full_reg_offset(s, a->pg); | |
1516 | int words = DIV_ROUND_UP(pred_full_reg_size(s), 8); | |
1517 | ||
1518 | if (words == 1) { | |
1519 | TCGv_i64 pn = tcg_temp_new_i64(); | |
1520 | TCGv_i64 pg = tcg_temp_new_i64(); | |
1521 | ||
1522 | tcg_gen_ld_i64(pn, cpu_env, nofs); | |
1523 | tcg_gen_ld_i64(pg, cpu_env, gofs); | |
1524 | do_predtest1(pn, pg); | |
1525 | ||
1526 | tcg_temp_free_i64(pn); | |
1527 | tcg_temp_free_i64(pg); | |
1528 | } else { | |
1529 | do_predtest(s, nofs, gofs, words); | |
1530 | } | |
1531 | } | |
1532 | return true; | |
1533 | } | |
1534 | ||
028e2a7b RH |
1535 | /* See the ARM pseudocode DecodePredCount. */ |
1536 | static unsigned decode_pred_count(unsigned fullsz, int pattern, int esz) | |
1537 | { | |
1538 | unsigned elements = fullsz >> esz; | |
1539 | unsigned bound; | |
1540 | ||
1541 | switch (pattern) { | |
1542 | case 0x0: /* POW2 */ | |
1543 | return pow2floor(elements); | |
1544 | case 0x1: /* VL1 */ | |
1545 | case 0x2: /* VL2 */ | |
1546 | case 0x3: /* VL3 */ | |
1547 | case 0x4: /* VL4 */ | |
1548 | case 0x5: /* VL5 */ | |
1549 | case 0x6: /* VL6 */ | |
1550 | case 0x7: /* VL7 */ | |
1551 | case 0x8: /* VL8 */ | |
1552 | bound = pattern; | |
1553 | break; | |
1554 | case 0x9: /* VL16 */ | |
1555 | case 0xa: /* VL32 */ | |
1556 | case 0xb: /* VL64 */ | |
1557 | case 0xc: /* VL128 */ | |
1558 | case 0xd: /* VL256 */ | |
1559 | bound = 16 << (pattern - 9); | |
1560 | break; | |
1561 | case 0x1d: /* MUL4 */ | |
1562 | return elements - elements % 4; | |
1563 | case 0x1e: /* MUL3 */ | |
1564 | return elements - elements % 3; | |
1565 | case 0x1f: /* ALL */ | |
1566 | return elements; | |
1567 | default: /* #uimm5 */ | |
1568 | return 0; | |
1569 | } | |
1570 | return elements >= bound ? bound : 0; | |
1571 | } | |
1572 | ||
1573 | /* This handles all of the predicate initialization instructions, | |
1574 | * PTRUE, PFALSE, SETFFR. For PFALSE, we will have set PAT == 32 | |
1575 | * so that decode_pred_count returns 0. For SETFFR, we will have | |
1576 | * set RD == 16 == FFR. | |
1577 | */ | |
1578 | static bool do_predset(DisasContext *s, int esz, int rd, int pat, bool setflag) | |
1579 | { | |
1580 | if (!sve_access_check(s)) { | |
1581 | return true; | |
1582 | } | |
1583 | ||
1584 | unsigned fullsz = vec_full_reg_size(s); | |
1585 | unsigned ofs = pred_full_reg_offset(s, rd); | |
1586 | unsigned numelem, setsz, i; | |
1587 | uint64_t word, lastword; | |
1588 | TCGv_i64 t; | |
1589 | ||
1590 | numelem = decode_pred_count(fullsz, pat, esz); | |
1591 | ||
1592 | /* Determine what we must store into each bit, and how many. */ | |
1593 | if (numelem == 0) { | |
1594 | lastword = word = 0; | |
1595 | setsz = fullsz; | |
1596 | } else { | |
1597 | setsz = numelem << esz; | |
1598 | lastword = word = pred_esz_masks[esz]; | |
1599 | if (setsz % 64) { | |
973558a3 | 1600 | lastword &= MAKE_64BIT_MASK(0, setsz % 64); |
028e2a7b RH |
1601 | } |
1602 | } | |
1603 | ||
1604 | t = tcg_temp_new_i64(); | |
1605 | if (fullsz <= 64) { | |
1606 | tcg_gen_movi_i64(t, lastword); | |
1607 | tcg_gen_st_i64(t, cpu_env, ofs); | |
1608 | goto done; | |
1609 | } | |
1610 | ||
1611 | if (word == lastword) { | |
1612 | unsigned maxsz = size_for_gvec(fullsz / 8); | |
1613 | unsigned oprsz = size_for_gvec(setsz / 8); | |
1614 | ||
1615 | if (oprsz * 8 == setsz) { | |
8711e71f | 1616 | tcg_gen_gvec_dup_imm(MO_64, ofs, oprsz, maxsz, word); |
028e2a7b RH |
1617 | goto done; |
1618 | } | |
028e2a7b RH |
1619 | } |
1620 | ||
1621 | setsz /= 8; | |
1622 | fullsz /= 8; | |
1623 | ||
1624 | tcg_gen_movi_i64(t, word); | |
973558a3 | 1625 | for (i = 0; i < QEMU_ALIGN_DOWN(setsz, 8); i += 8) { |
028e2a7b RH |
1626 | tcg_gen_st_i64(t, cpu_env, ofs + i); |
1627 | } | |
1628 | if (lastword != word) { | |
1629 | tcg_gen_movi_i64(t, lastword); | |
1630 | tcg_gen_st_i64(t, cpu_env, ofs + i); | |
1631 | i += 8; | |
1632 | } | |
1633 | if (i < fullsz) { | |
1634 | tcg_gen_movi_i64(t, 0); | |
1635 | for (; i < fullsz; i += 8) { | |
1636 | tcg_gen_st_i64(t, cpu_env, ofs + i); | |
1637 | } | |
1638 | } | |
1639 | ||
1640 | done: | |
1641 | tcg_temp_free_i64(t); | |
1642 | ||
1643 | /* PTRUES */ | |
1644 | if (setflag) { | |
1645 | tcg_gen_movi_i32(cpu_NF, -(word != 0)); | |
1646 | tcg_gen_movi_i32(cpu_CF, word == 0); | |
1647 | tcg_gen_movi_i32(cpu_VF, 0); | |
1648 | tcg_gen_mov_i32(cpu_ZF, cpu_NF); | |
1649 | } | |
1650 | return true; | |
1651 | } | |
1652 | ||
b03a8501 | 1653 | TRANS_FEAT(PTRUE, aa64_sve, do_predset, a->esz, a->rd, a->pat, a->s) |
028e2a7b | 1654 | |
b03a8501 RH |
1655 | /* Note pat == 31 is #all, to set all elements. */ |
1656 | TRANS_FEAT(SETFFR, aa64_sve, do_predset, 0, FFR_PRED_NUM, 31, false) | |
028e2a7b | 1657 | |
b03a8501 RH |
1658 | /* Note pat == 32 is #unimp, to set no elements. */ |
1659 | TRANS_FEAT(PFALSE, aa64_sve, do_predset, 0, a->rd, 32, false) | |
028e2a7b | 1660 | |
3a7be554 | 1661 | static bool trans_RDFFR_p(DisasContext *s, arg_RDFFR_p *a) |
028e2a7b RH |
1662 | { |
1663 | /* The path through do_pppp_flags is complicated enough to want to avoid | |
1664 | * duplication. Frob the arguments into the form of a predicated AND. | |
1665 | */ | |
1666 | arg_rprr_s alt_a = { | |
1667 | .rd = a->rd, .pg = a->pg, .s = a->s, | |
1668 | .rn = FFR_PRED_NUM, .rm = FFR_PRED_NUM, | |
1669 | }; | |
3a7be554 | 1670 | return trans_AND_pppp(s, &alt_a); |
028e2a7b RH |
1671 | } |
1672 | ||
ff502658 RH |
1673 | TRANS_FEAT(RDFFR, aa64_sve, do_mov_p, a->rd, FFR_PRED_NUM) |
1674 | TRANS_FEAT(WRFFR, aa64_sve, do_mov_p, FFR_PRED_NUM, a->rn) | |
028e2a7b RH |
1675 | |
1676 | static bool do_pfirst_pnext(DisasContext *s, arg_rr_esz *a, | |
1677 | void (*gen_fn)(TCGv_i32, TCGv_ptr, | |
1678 | TCGv_ptr, TCGv_i32)) | |
1679 | { | |
1680 | if (!sve_access_check(s)) { | |
1681 | return true; | |
1682 | } | |
1683 | ||
1684 | TCGv_ptr t_pd = tcg_temp_new_ptr(); | |
1685 | TCGv_ptr t_pg = tcg_temp_new_ptr(); | |
1686 | TCGv_i32 t; | |
86300b5d | 1687 | unsigned desc = 0; |
028e2a7b | 1688 | |
86300b5d RH |
1689 | desc = FIELD_DP32(desc, PREDDESC, OPRSZ, pred_full_reg_size(s)); |
1690 | desc = FIELD_DP32(desc, PREDDESC, ESZ, a->esz); | |
028e2a7b RH |
1691 | |
1692 | tcg_gen_addi_ptr(t_pd, cpu_env, pred_full_reg_offset(s, a->rd)); | |
1693 | tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, a->rn)); | |
392acacc | 1694 | t = tcg_temp_new_i32(); |
028e2a7b | 1695 | |
392acacc | 1696 | gen_fn(t, t_pd, t_pg, tcg_constant_i32(desc)); |
028e2a7b RH |
1697 | tcg_temp_free_ptr(t_pd); |
1698 | tcg_temp_free_ptr(t_pg); | |
1699 | ||
1700 | do_pred_flags(t); | |
1701 | tcg_temp_free_i32(t); | |
1702 | return true; | |
1703 | } | |
1704 | ||
d95040e3 RH |
1705 | TRANS_FEAT(PFIRST, aa64_sve, do_pfirst_pnext, a, gen_helper_sve_pfirst) |
1706 | TRANS_FEAT(PNEXT, aa64_sve, do_pfirst_pnext, a, gen_helper_sve_pnext) | |
028e2a7b | 1707 | |
24e82e68 RH |
1708 | /* |
1709 | *** SVE Element Count Group | |
1710 | */ | |
1711 | ||
1712 | /* Perform an inline saturating addition of a 32-bit value within | |
1713 | * a 64-bit register. The second operand is known to be positive, | |
1714 | * which halves the comparisions we must perform to bound the result. | |
1715 | */ | |
1716 | static void do_sat_addsub_32(TCGv_i64 reg, TCGv_i64 val, bool u, bool d) | |
1717 | { | |
1718 | int64_t ibound; | |
24e82e68 RH |
1719 | |
1720 | /* Use normal 64-bit arithmetic to detect 32-bit overflow. */ | |
1721 | if (u) { | |
1722 | tcg_gen_ext32u_i64(reg, reg); | |
1723 | } else { | |
1724 | tcg_gen_ext32s_i64(reg, reg); | |
1725 | } | |
1726 | if (d) { | |
1727 | tcg_gen_sub_i64(reg, reg, val); | |
1728 | ibound = (u ? 0 : INT32_MIN); | |
aa5b0b29 | 1729 | tcg_gen_smax_i64(reg, reg, tcg_constant_i64(ibound)); |
24e82e68 RH |
1730 | } else { |
1731 | tcg_gen_add_i64(reg, reg, val); | |
1732 | ibound = (u ? UINT32_MAX : INT32_MAX); | |
aa5b0b29 | 1733 | tcg_gen_smin_i64(reg, reg, tcg_constant_i64(ibound)); |
24e82e68 | 1734 | } |
24e82e68 RH |
1735 | } |
1736 | ||
1737 | /* Similarly with 64-bit values. */ | |
1738 | static void do_sat_addsub_64(TCGv_i64 reg, TCGv_i64 val, bool u, bool d) | |
1739 | { | |
1740 | TCGv_i64 t0 = tcg_temp_new_i64(); | |
24e82e68 RH |
1741 | TCGv_i64 t2; |
1742 | ||
1743 | if (u) { | |
1744 | if (d) { | |
1745 | tcg_gen_sub_i64(t0, reg, val); | |
35a1ec8e PMD |
1746 | t2 = tcg_constant_i64(0); |
1747 | tcg_gen_movcond_i64(TCG_COND_LTU, reg, reg, val, t2, t0); | |
24e82e68 RH |
1748 | } else { |
1749 | tcg_gen_add_i64(t0, reg, val); | |
35a1ec8e PMD |
1750 | t2 = tcg_constant_i64(-1); |
1751 | tcg_gen_movcond_i64(TCG_COND_LTU, reg, t0, reg, t2, t0); | |
24e82e68 RH |
1752 | } |
1753 | } else { | |
35a1ec8e | 1754 | TCGv_i64 t1 = tcg_temp_new_i64(); |
24e82e68 RH |
1755 | if (d) { |
1756 | /* Detect signed overflow for subtraction. */ | |
1757 | tcg_gen_xor_i64(t0, reg, val); | |
1758 | tcg_gen_sub_i64(t1, reg, val); | |
7a31e0c6 | 1759 | tcg_gen_xor_i64(reg, reg, t1); |
24e82e68 RH |
1760 | tcg_gen_and_i64(t0, t0, reg); |
1761 | ||
1762 | /* Bound the result. */ | |
1763 | tcg_gen_movi_i64(reg, INT64_MIN); | |
35a1ec8e | 1764 | t2 = tcg_constant_i64(0); |
24e82e68 RH |
1765 | tcg_gen_movcond_i64(TCG_COND_LT, reg, t0, t2, reg, t1); |
1766 | } else { | |
1767 | /* Detect signed overflow for addition. */ | |
1768 | tcg_gen_xor_i64(t0, reg, val); | |
1769 | tcg_gen_add_i64(reg, reg, val); | |
1770 | tcg_gen_xor_i64(t1, reg, val); | |
1771 | tcg_gen_andc_i64(t0, t1, t0); | |
1772 | ||
1773 | /* Bound the result. */ | |
1774 | tcg_gen_movi_i64(t1, INT64_MAX); | |
35a1ec8e | 1775 | t2 = tcg_constant_i64(0); |
24e82e68 RH |
1776 | tcg_gen_movcond_i64(TCG_COND_LT, reg, t0, t2, t1, reg); |
1777 | } | |
35a1ec8e | 1778 | tcg_temp_free_i64(t1); |
24e82e68 RH |
1779 | } |
1780 | tcg_temp_free_i64(t0); | |
24e82e68 RH |
1781 | } |
1782 | ||
1783 | /* Similarly with a vector and a scalar operand. */ | |
1784 | static void do_sat_addsub_vec(DisasContext *s, int esz, int rd, int rn, | |
1785 | TCGv_i64 val, bool u, bool d) | |
1786 | { | |
1787 | unsigned vsz = vec_full_reg_size(s); | |
1788 | TCGv_ptr dptr, nptr; | |
1789 | TCGv_i32 t32, desc; | |
1790 | TCGv_i64 t64; | |
1791 | ||
1792 | dptr = tcg_temp_new_ptr(); | |
1793 | nptr = tcg_temp_new_ptr(); | |
1794 | tcg_gen_addi_ptr(dptr, cpu_env, vec_full_reg_offset(s, rd)); | |
1795 | tcg_gen_addi_ptr(nptr, cpu_env, vec_full_reg_offset(s, rn)); | |
c6a59b55 | 1796 | desc = tcg_constant_i32(simd_desc(vsz, vsz, 0)); |
24e82e68 RH |
1797 | |
1798 | switch (esz) { | |
1799 | case MO_8: | |
1800 | t32 = tcg_temp_new_i32(); | |
1801 | tcg_gen_extrl_i64_i32(t32, val); | |
1802 | if (d) { | |
1803 | tcg_gen_neg_i32(t32, t32); | |
1804 | } | |
1805 | if (u) { | |
1806 | gen_helper_sve_uqaddi_b(dptr, nptr, t32, desc); | |
1807 | } else { | |
1808 | gen_helper_sve_sqaddi_b(dptr, nptr, t32, desc); | |
1809 | } | |
1810 | tcg_temp_free_i32(t32); | |
1811 | break; | |
1812 | ||
1813 | case MO_16: | |
1814 | t32 = tcg_temp_new_i32(); | |
1815 | tcg_gen_extrl_i64_i32(t32, val); | |
1816 | if (d) { | |
1817 | tcg_gen_neg_i32(t32, t32); | |
1818 | } | |
1819 | if (u) { | |
1820 | gen_helper_sve_uqaddi_h(dptr, nptr, t32, desc); | |
1821 | } else { | |
1822 | gen_helper_sve_sqaddi_h(dptr, nptr, t32, desc); | |
1823 | } | |
1824 | tcg_temp_free_i32(t32); | |
1825 | break; | |
1826 | ||
1827 | case MO_32: | |
1828 | t64 = tcg_temp_new_i64(); | |
1829 | if (d) { | |
1830 | tcg_gen_neg_i64(t64, val); | |
1831 | } else { | |
1832 | tcg_gen_mov_i64(t64, val); | |
1833 | } | |
1834 | if (u) { | |
1835 | gen_helper_sve_uqaddi_s(dptr, nptr, t64, desc); | |
1836 | } else { | |
1837 | gen_helper_sve_sqaddi_s(dptr, nptr, t64, desc); | |
1838 | } | |
1839 | tcg_temp_free_i64(t64); | |
1840 | break; | |
1841 | ||
1842 | case MO_64: | |
1843 | if (u) { | |
1844 | if (d) { | |
1845 | gen_helper_sve_uqsubi_d(dptr, nptr, val, desc); | |
1846 | } else { | |
1847 | gen_helper_sve_uqaddi_d(dptr, nptr, val, desc); | |
1848 | } | |
1849 | } else if (d) { | |
1850 | t64 = tcg_temp_new_i64(); | |
1851 | tcg_gen_neg_i64(t64, val); | |
1852 | gen_helper_sve_sqaddi_d(dptr, nptr, t64, desc); | |
1853 | tcg_temp_free_i64(t64); | |
1854 | } else { | |
1855 | gen_helper_sve_sqaddi_d(dptr, nptr, val, desc); | |
1856 | } | |
1857 | break; | |
1858 | ||
1859 | default: | |
1860 | g_assert_not_reached(); | |
1861 | } | |
1862 | ||
1863 | tcg_temp_free_ptr(dptr); | |
1864 | tcg_temp_free_ptr(nptr); | |
24e82e68 RH |
1865 | } |
1866 | ||
3a7be554 | 1867 | static bool trans_CNT_r(DisasContext *s, arg_CNT_r *a) |
24e82e68 RH |
1868 | { |
1869 | if (sve_access_check(s)) { | |
1870 | unsigned fullsz = vec_full_reg_size(s); | |
1871 | unsigned numelem = decode_pred_count(fullsz, a->pat, a->esz); | |
1872 | tcg_gen_movi_i64(cpu_reg(s, a->rd), numelem * a->imm); | |
1873 | } | |
1874 | return true; | |
1875 | } | |
1876 | ||
3a7be554 | 1877 | static bool trans_INCDEC_r(DisasContext *s, arg_incdec_cnt *a) |
24e82e68 RH |
1878 | { |
1879 | if (sve_access_check(s)) { | |
1880 | unsigned fullsz = vec_full_reg_size(s); | |
1881 | unsigned numelem = decode_pred_count(fullsz, a->pat, a->esz); | |
1882 | int inc = numelem * a->imm * (a->d ? -1 : 1); | |
1883 | TCGv_i64 reg = cpu_reg(s, a->rd); | |
1884 | ||
1885 | tcg_gen_addi_i64(reg, reg, inc); | |
1886 | } | |
1887 | return true; | |
1888 | } | |
1889 | ||
3a7be554 | 1890 | static bool trans_SINCDEC_r_32(DisasContext *s, arg_incdec_cnt *a) |
24e82e68 RH |
1891 | { |
1892 | if (!sve_access_check(s)) { | |
1893 | return true; | |
1894 | } | |
1895 | ||
1896 | unsigned fullsz = vec_full_reg_size(s); | |
1897 | unsigned numelem = decode_pred_count(fullsz, a->pat, a->esz); | |
1898 | int inc = numelem * a->imm; | |
1899 | TCGv_i64 reg = cpu_reg(s, a->rd); | |
1900 | ||
1901 | /* Use normal 64-bit arithmetic to detect 32-bit overflow. */ | |
1902 | if (inc == 0) { | |
1903 | if (a->u) { | |
1904 | tcg_gen_ext32u_i64(reg, reg); | |
1905 | } else { | |
1906 | tcg_gen_ext32s_i64(reg, reg); | |
1907 | } | |
1908 | } else { | |
d681f125 | 1909 | do_sat_addsub_32(reg, tcg_constant_i64(inc), a->u, a->d); |
24e82e68 RH |
1910 | } |
1911 | return true; | |
1912 | } | |
1913 | ||
3a7be554 | 1914 | static bool trans_SINCDEC_r_64(DisasContext *s, arg_incdec_cnt *a) |
24e82e68 RH |
1915 | { |
1916 | if (!sve_access_check(s)) { | |
1917 | return true; | |
1918 | } | |
1919 | ||
1920 | unsigned fullsz = vec_full_reg_size(s); | |
1921 | unsigned numelem = decode_pred_count(fullsz, a->pat, a->esz); | |
1922 | int inc = numelem * a->imm; | |
1923 | TCGv_i64 reg = cpu_reg(s, a->rd); | |
1924 | ||
1925 | if (inc != 0) { | |
d681f125 | 1926 | do_sat_addsub_64(reg, tcg_constant_i64(inc), a->u, a->d); |
24e82e68 RH |
1927 | } |
1928 | return true; | |
1929 | } | |
1930 | ||
3a7be554 | 1931 | static bool trans_INCDEC_v(DisasContext *s, arg_incdec2_cnt *a) |
24e82e68 RH |
1932 | { |
1933 | if (a->esz == 0) { | |
1934 | return false; | |
1935 | } | |
1936 | ||
1937 | unsigned fullsz = vec_full_reg_size(s); | |
1938 | unsigned numelem = decode_pred_count(fullsz, a->pat, a->esz); | |
1939 | int inc = numelem * a->imm; | |
1940 | ||
1941 | if (inc != 0) { | |
1942 | if (sve_access_check(s)) { | |
24e82e68 RH |
1943 | tcg_gen_gvec_adds(a->esz, vec_full_reg_offset(s, a->rd), |
1944 | vec_full_reg_offset(s, a->rn), | |
d681f125 RH |
1945 | tcg_constant_i64(a->d ? -inc : inc), |
1946 | fullsz, fullsz); | |
24e82e68 RH |
1947 | } |
1948 | } else { | |
1949 | do_mov_z(s, a->rd, a->rn); | |
1950 | } | |
1951 | return true; | |
1952 | } | |
1953 | ||
3a7be554 | 1954 | static bool trans_SINCDEC_v(DisasContext *s, arg_incdec2_cnt *a) |
24e82e68 RH |
1955 | { |
1956 | if (a->esz == 0) { | |
1957 | return false; | |
1958 | } | |
1959 | ||
1960 | unsigned fullsz = vec_full_reg_size(s); | |
1961 | unsigned numelem = decode_pred_count(fullsz, a->pat, a->esz); | |
1962 | int inc = numelem * a->imm; | |
1963 | ||
1964 | if (inc != 0) { | |
1965 | if (sve_access_check(s)) { | |
d681f125 RH |
1966 | do_sat_addsub_vec(s, a->esz, a->rd, a->rn, |
1967 | tcg_constant_i64(inc), a->u, a->d); | |
24e82e68 RH |
1968 | } |
1969 | } else { | |
1970 | do_mov_z(s, a->rd, a->rn); | |
1971 | } | |
1972 | return true; | |
1973 | } | |
1974 | ||
e1fa1164 RH |
1975 | /* |
1976 | *** SVE Bitwise Immediate Group | |
1977 | */ | |
1978 | ||
1979 | static bool do_zz_dbm(DisasContext *s, arg_rr_dbm *a, GVecGen2iFn *gvec_fn) | |
1980 | { | |
1981 | uint64_t imm; | |
1982 | if (!logic_imm_decode_wmask(&imm, extract32(a->dbm, 12, 1), | |
1983 | extract32(a->dbm, 0, 6), | |
1984 | extract32(a->dbm, 6, 6))) { | |
1985 | return false; | |
1986 | } | |
faf915e2 | 1987 | return gen_gvec_fn_zzi(s, gvec_fn, MO_64, a->rd, a->rn, imm); |
e1fa1164 RH |
1988 | } |
1989 | ||
15a314da RH |
1990 | TRANS_FEAT(AND_zzi, aa64_sve, do_zz_dbm, a, tcg_gen_gvec_andi) |
1991 | TRANS_FEAT(ORR_zzi, aa64_sve, do_zz_dbm, a, tcg_gen_gvec_ori) | |
1992 | TRANS_FEAT(EOR_zzi, aa64_sve, do_zz_dbm, a, tcg_gen_gvec_xori) | |
e1fa1164 | 1993 | |
3a7be554 | 1994 | static bool trans_DUPM(DisasContext *s, arg_DUPM *a) |
e1fa1164 RH |
1995 | { |
1996 | uint64_t imm; | |
1997 | if (!logic_imm_decode_wmask(&imm, extract32(a->dbm, 12, 1), | |
1998 | extract32(a->dbm, 0, 6), | |
1999 | extract32(a->dbm, 6, 6))) { | |
2000 | return false; | |
2001 | } | |
2002 | if (sve_access_check(s)) { | |
2003 | do_dupi_z(s, a->rd, imm); | |
2004 | } | |
2005 | return true; | |
2006 | } | |
2007 | ||
f25a2361 RH |
2008 | /* |
2009 | *** SVE Integer Wide Immediate - Predicated Group | |
2010 | */ | |
2011 | ||
2012 | /* Implement all merging copies. This is used for CPY (immediate), | |
2013 | * FCPY, CPY (scalar), CPY (SIMD&FP scalar). | |
2014 | */ | |
2015 | static void do_cpy_m(DisasContext *s, int esz, int rd, int rn, int pg, | |
2016 | TCGv_i64 val) | |
2017 | { | |
2018 | typedef void gen_cpy(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i64, TCGv_i32); | |
2019 | static gen_cpy * const fns[4] = { | |
2020 | gen_helper_sve_cpy_m_b, gen_helper_sve_cpy_m_h, | |
2021 | gen_helper_sve_cpy_m_s, gen_helper_sve_cpy_m_d, | |
2022 | }; | |
2023 | unsigned vsz = vec_full_reg_size(s); | |
c6a59b55 | 2024 | TCGv_i32 desc = tcg_constant_i32(simd_desc(vsz, vsz, 0)); |
f25a2361 RH |
2025 | TCGv_ptr t_zd = tcg_temp_new_ptr(); |
2026 | TCGv_ptr t_zn = tcg_temp_new_ptr(); | |
2027 | TCGv_ptr t_pg = tcg_temp_new_ptr(); | |
2028 | ||
2029 | tcg_gen_addi_ptr(t_zd, cpu_env, vec_full_reg_offset(s, rd)); | |
2030 | tcg_gen_addi_ptr(t_zn, cpu_env, vec_full_reg_offset(s, rn)); | |
2031 | tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, pg)); | |
2032 | ||
2033 | fns[esz](t_zd, t_zn, t_pg, val, desc); | |
2034 | ||
2035 | tcg_temp_free_ptr(t_zd); | |
2036 | tcg_temp_free_ptr(t_zn); | |
2037 | tcg_temp_free_ptr(t_pg); | |
f25a2361 RH |
2038 | } |
2039 | ||
3a7be554 | 2040 | static bool trans_FCPY(DisasContext *s, arg_FCPY *a) |
f25a2361 RH |
2041 | { |
2042 | if (a->esz == 0) { | |
2043 | return false; | |
2044 | } | |
2045 | if (sve_access_check(s)) { | |
2046 | /* Decode the VFP immediate. */ | |
2047 | uint64_t imm = vfp_expand_imm(a->esz, a->imm); | |
e152b48b | 2048 | do_cpy_m(s, a->esz, a->rd, a->rn, a->pg, tcg_constant_i64(imm)); |
f25a2361 RH |
2049 | } |
2050 | return true; | |
2051 | } | |
2052 | ||
3a7be554 | 2053 | static bool trans_CPY_m_i(DisasContext *s, arg_rpri_esz *a) |
f25a2361 | 2054 | { |
f25a2361 | 2055 | if (sve_access_check(s)) { |
e152b48b | 2056 | do_cpy_m(s, a->esz, a->rd, a->rn, a->pg, tcg_constant_i64(a->imm)); |
f25a2361 RH |
2057 | } |
2058 | return true; | |
2059 | } | |
2060 | ||
3a7be554 | 2061 | static bool trans_CPY_z_i(DisasContext *s, arg_CPY_z_i *a) |
f25a2361 RH |
2062 | { |
2063 | static gen_helper_gvec_2i * const fns[4] = { | |
2064 | gen_helper_sve_cpy_z_b, gen_helper_sve_cpy_z_h, | |
2065 | gen_helper_sve_cpy_z_s, gen_helper_sve_cpy_z_d, | |
2066 | }; | |
2067 | ||
f25a2361 RH |
2068 | if (sve_access_check(s)) { |
2069 | unsigned vsz = vec_full_reg_size(s); | |
f25a2361 RH |
2070 | tcg_gen_gvec_2i_ool(vec_full_reg_offset(s, a->rd), |
2071 | pred_full_reg_offset(s, a->pg), | |
e152b48b RH |
2072 | tcg_constant_i64(a->imm), |
2073 | vsz, vsz, 0, fns[a->esz]); | |
f25a2361 RH |
2074 | } |
2075 | return true; | |
2076 | } | |
2077 | ||
b94f8f60 RH |
2078 | /* |
2079 | *** SVE Permute Extract Group | |
2080 | */ | |
2081 | ||
75114792 | 2082 | static bool do_EXT(DisasContext *s, int rd, int rn, int rm, int imm) |
b94f8f60 RH |
2083 | { |
2084 | if (!sve_access_check(s)) { | |
2085 | return true; | |
2086 | } | |
2087 | ||
2088 | unsigned vsz = vec_full_reg_size(s); | |
75114792 | 2089 | unsigned n_ofs = imm >= vsz ? 0 : imm; |
b94f8f60 | 2090 | unsigned n_siz = vsz - n_ofs; |
75114792 SL |
2091 | unsigned d = vec_full_reg_offset(s, rd); |
2092 | unsigned n = vec_full_reg_offset(s, rn); | |
2093 | unsigned m = vec_full_reg_offset(s, rm); | |
b94f8f60 RH |
2094 | |
2095 | /* Use host vector move insns if we have appropriate sizes | |
2096 | * and no unfortunate overlap. | |
2097 | */ | |
2098 | if (m != d | |
2099 | && n_ofs == size_for_gvec(n_ofs) | |
2100 | && n_siz == size_for_gvec(n_siz) | |
2101 | && (d != n || n_siz <= n_ofs)) { | |
2102 | tcg_gen_gvec_mov(0, d, n + n_ofs, n_siz, n_siz); | |
2103 | if (n_ofs != 0) { | |
2104 | tcg_gen_gvec_mov(0, d + n_siz, m, n_ofs, n_ofs); | |
2105 | } | |
2106 | } else { | |
2107 | tcg_gen_gvec_3_ool(d, n, m, vsz, vsz, n_ofs, gen_helper_sve_ext); | |
2108 | } | |
2109 | return true; | |
2110 | } | |
2111 | ||
c799c115 RH |
2112 | TRANS_FEAT(EXT, aa64_sve, do_EXT, a->rd, a->rn, a->rm, a->imm) |
2113 | TRANS_FEAT(EXT_sve2, aa64_sve2, do_EXT, a->rd, a->rn, (a->rn + 1) % 32, a->imm) | |
75114792 | 2114 | |
30562ab7 RH |
2115 | /* |
2116 | *** SVE Permute - Unpredicated Group | |
2117 | */ | |
2118 | ||
3a7be554 | 2119 | static bool trans_DUP_s(DisasContext *s, arg_DUP_s *a) |
30562ab7 RH |
2120 | { |
2121 | if (sve_access_check(s)) { | |
2122 | unsigned vsz = vec_full_reg_size(s); | |
2123 | tcg_gen_gvec_dup_i64(a->esz, vec_full_reg_offset(s, a->rd), | |
2124 | vsz, vsz, cpu_reg_sp(s, a->rn)); | |
2125 | } | |
2126 | return true; | |
2127 | } | |
2128 | ||
3a7be554 | 2129 | static bool trans_DUP_x(DisasContext *s, arg_DUP_x *a) |
30562ab7 RH |
2130 | { |
2131 | if ((a->imm & 0x1f) == 0) { | |
2132 | return false; | |
2133 | } | |
2134 | if (sve_access_check(s)) { | |
2135 | unsigned vsz = vec_full_reg_size(s); | |
2136 | unsigned dofs = vec_full_reg_offset(s, a->rd); | |
2137 | unsigned esz, index; | |
2138 | ||
2139 | esz = ctz32(a->imm); | |
2140 | index = a->imm >> (esz + 1); | |
2141 | ||
2142 | if ((index << esz) < vsz) { | |
2143 | unsigned nofs = vec_reg_offset(s, a->rn, index, esz); | |
2144 | tcg_gen_gvec_dup_mem(esz, dofs, nofs, vsz, vsz); | |
2145 | } else { | |
7e17d50e RH |
2146 | /* |
2147 | * While dup_mem handles 128-bit elements, dup_imm does not. | |
2148 | * Thankfully element size doesn't matter for splatting zero. | |
2149 | */ | |
2150 | tcg_gen_gvec_dup_imm(MO_64, dofs, vsz, vsz, 0); | |
30562ab7 RH |
2151 | } |
2152 | } | |
2153 | return true; | |
2154 | } | |
2155 | ||
2156 | static void do_insr_i64(DisasContext *s, arg_rrr_esz *a, TCGv_i64 val) | |
2157 | { | |
2158 | typedef void gen_insr(TCGv_ptr, TCGv_ptr, TCGv_i64, TCGv_i32); | |
2159 | static gen_insr * const fns[4] = { | |
2160 | gen_helper_sve_insr_b, gen_helper_sve_insr_h, | |
2161 | gen_helper_sve_insr_s, gen_helper_sve_insr_d, | |
2162 | }; | |
2163 | unsigned vsz = vec_full_reg_size(s); | |
c6a59b55 | 2164 | TCGv_i32 desc = tcg_constant_i32(simd_desc(vsz, vsz, 0)); |
30562ab7 RH |
2165 | TCGv_ptr t_zd = tcg_temp_new_ptr(); |
2166 | TCGv_ptr t_zn = tcg_temp_new_ptr(); | |
2167 | ||
2168 | tcg_gen_addi_ptr(t_zd, cpu_env, vec_full_reg_offset(s, a->rd)); | |
2169 | tcg_gen_addi_ptr(t_zn, cpu_env, vec_full_reg_offset(s, a->rn)); | |
2170 | ||
2171 | fns[a->esz](t_zd, t_zn, val, desc); | |
2172 | ||
2173 | tcg_temp_free_ptr(t_zd); | |
2174 | tcg_temp_free_ptr(t_zn); | |
30562ab7 RH |
2175 | } |
2176 | ||
3a7be554 | 2177 | static bool trans_INSR_f(DisasContext *s, arg_rrr_esz *a) |
30562ab7 RH |
2178 | { |
2179 | if (sve_access_check(s)) { | |
2180 | TCGv_i64 t = tcg_temp_new_i64(); | |
2181 | tcg_gen_ld_i64(t, cpu_env, vec_reg_offset(s, a->rm, 0, MO_64)); | |
2182 | do_insr_i64(s, a, t); | |
2183 | tcg_temp_free_i64(t); | |
2184 | } | |
2185 | return true; | |
2186 | } | |
2187 | ||
3a7be554 | 2188 | static bool trans_INSR_r(DisasContext *s, arg_rrr_esz *a) |
30562ab7 RH |
2189 | { |
2190 | if (sve_access_check(s)) { | |
2191 | do_insr_i64(s, a, cpu_reg(s, a->rm)); | |
2192 | } | |
2193 | return true; | |
2194 | } | |
2195 | ||
0ea3cdbf RH |
2196 | static gen_helper_gvec_2 * const rev_fns[4] = { |
2197 | gen_helper_sve_rev_b, gen_helper_sve_rev_h, | |
2198 | gen_helper_sve_rev_s, gen_helper_sve_rev_d | |
2199 | }; | |
2200 | TRANS_FEAT(REV_v, aa64_sve, gen_gvec_ool_zz, rev_fns[a->esz], a->rd, a->rn, 0) | |
30562ab7 | 2201 | |
32e2ad65 RH |
2202 | static gen_helper_gvec_3 * const sve_tbl_fns[4] = { |
2203 | gen_helper_sve_tbl_b, gen_helper_sve_tbl_h, | |
2204 | gen_helper_sve_tbl_s, gen_helper_sve_tbl_d | |
2205 | }; | |
2206 | TRANS_FEAT(TBL, aa64_sve, gen_gvec_ool_arg_zzz, sve_tbl_fns[a->esz], a, 0) | |
30562ab7 | 2207 | |
5f425b92 RH |
2208 | static gen_helper_gvec_4 * const sve2_tbl_fns[4] = { |
2209 | gen_helper_sve2_tbl_b, gen_helper_sve2_tbl_h, | |
2210 | gen_helper_sve2_tbl_s, gen_helper_sve2_tbl_d | |
2211 | }; | |
2212 | TRANS_FEAT(TBL_sve2, aa64_sve2, gen_gvec_ool_zzzz, sve2_tbl_fns[a->esz], | |
2213 | a->rd, a->rn, (a->rn + 1) % 32, a->rm, 0) | |
80a712a2 | 2214 | |
32e2ad65 RH |
2215 | static gen_helper_gvec_3 * const tbx_fns[4] = { |
2216 | gen_helper_sve2_tbx_b, gen_helper_sve2_tbx_h, | |
2217 | gen_helper_sve2_tbx_s, gen_helper_sve2_tbx_d | |
2218 | }; | |
2219 | TRANS_FEAT(TBX, aa64_sve2, gen_gvec_ool_arg_zzz, tbx_fns[a->esz], a, 0) | |
80a712a2 | 2220 | |
3a7be554 | 2221 | static bool trans_UNPK(DisasContext *s, arg_UNPK *a) |
30562ab7 RH |
2222 | { |
2223 | static gen_helper_gvec_2 * const fns[4][2] = { | |
2224 | { NULL, NULL }, | |
2225 | { gen_helper_sve_sunpk_h, gen_helper_sve_uunpk_h }, | |
2226 | { gen_helper_sve_sunpk_s, gen_helper_sve_uunpk_s }, | |
2227 | { gen_helper_sve_sunpk_d, gen_helper_sve_uunpk_d }, | |
2228 | }; | |
2229 | ||
2230 | if (a->esz == 0) { | |
2231 | return false; | |
2232 | } | |
2233 | if (sve_access_check(s)) { | |
2234 | unsigned vsz = vec_full_reg_size(s); | |
2235 | tcg_gen_gvec_2_ool(vec_full_reg_offset(s, a->rd), | |
2236 | vec_full_reg_offset(s, a->rn) | |
2237 | + (a->h ? vsz / 2 : 0), | |
2238 | vsz, vsz, 0, fns[a->esz][a->u]); | |
2239 | } | |
2240 | return true; | |
2241 | } | |
2242 | ||
d731d8cb RH |
2243 | /* |
2244 | *** SVE Permute - Predicates Group | |
2245 | */ | |
2246 | ||
2247 | static bool do_perm_pred3(DisasContext *s, arg_rrr_esz *a, bool high_odd, | |
2248 | gen_helper_gvec_3 *fn) | |
2249 | { | |
2250 | if (!sve_access_check(s)) { | |
2251 | return true; | |
2252 | } | |
2253 | ||
2254 | unsigned vsz = pred_full_reg_size(s); | |
2255 | ||
d731d8cb RH |
2256 | TCGv_ptr t_d = tcg_temp_new_ptr(); |
2257 | TCGv_ptr t_n = tcg_temp_new_ptr(); | |
2258 | TCGv_ptr t_m = tcg_temp_new_ptr(); | |
f9b0fcce | 2259 | uint32_t desc = 0; |
d731d8cb | 2260 | |
f9b0fcce RH |
2261 | desc = FIELD_DP32(desc, PREDDESC, OPRSZ, vsz); |
2262 | desc = FIELD_DP32(desc, PREDDESC, ESZ, a->esz); | |
2263 | desc = FIELD_DP32(desc, PREDDESC, DATA, high_odd); | |
d731d8cb RH |
2264 | |
2265 | tcg_gen_addi_ptr(t_d, cpu_env, pred_full_reg_offset(s, a->rd)); | |
2266 | tcg_gen_addi_ptr(t_n, cpu_env, pred_full_reg_offset(s, a->rn)); | |
2267 | tcg_gen_addi_ptr(t_m, cpu_env, pred_full_reg_offset(s, a->rm)); | |
d731d8cb | 2268 | |
c6a59b55 | 2269 | fn(t_d, t_n, t_m, tcg_constant_i32(desc)); |
d731d8cb RH |
2270 | |
2271 | tcg_temp_free_ptr(t_d); | |
2272 | tcg_temp_free_ptr(t_n); | |
2273 | tcg_temp_free_ptr(t_m); | |
d731d8cb RH |
2274 | return true; |
2275 | } | |
2276 | ||
2277 | static bool do_perm_pred2(DisasContext *s, arg_rr_esz *a, bool high_odd, | |
2278 | gen_helper_gvec_2 *fn) | |
2279 | { | |
2280 | if (!sve_access_check(s)) { | |
2281 | return true; | |
2282 | } | |
2283 | ||
2284 | unsigned vsz = pred_full_reg_size(s); | |
2285 | TCGv_ptr t_d = tcg_temp_new_ptr(); | |
2286 | TCGv_ptr t_n = tcg_temp_new_ptr(); | |
70acaafe | 2287 | uint32_t desc = 0; |
d731d8cb RH |
2288 | |
2289 | tcg_gen_addi_ptr(t_d, cpu_env, pred_full_reg_offset(s, a->rd)); | |
2290 | tcg_gen_addi_ptr(t_n, cpu_env, pred_full_reg_offset(s, a->rn)); | |
2291 | ||
70acaafe RH |
2292 | desc = FIELD_DP32(desc, PREDDESC, OPRSZ, vsz); |
2293 | desc = FIELD_DP32(desc, PREDDESC, ESZ, a->esz); | |
2294 | desc = FIELD_DP32(desc, PREDDESC, DATA, high_odd); | |
d731d8cb | 2295 | |
c6a59b55 | 2296 | fn(t_d, t_n, tcg_constant_i32(desc)); |
d731d8cb | 2297 | |
d731d8cb RH |
2298 | tcg_temp_free_ptr(t_d); |
2299 | tcg_temp_free_ptr(t_n); | |
2300 | return true; | |
2301 | } | |
2302 | ||
bdb349f5 RH |
2303 | TRANS_FEAT(ZIP1_p, aa64_sve, do_perm_pred3, a, 0, gen_helper_sve_zip_p) |
2304 | TRANS_FEAT(ZIP2_p, aa64_sve, do_perm_pred3, a, 1, gen_helper_sve_zip_p) | |
2305 | TRANS_FEAT(UZP1_p, aa64_sve, do_perm_pred3, a, 0, gen_helper_sve_uzp_p) | |
2306 | TRANS_FEAT(UZP2_p, aa64_sve, do_perm_pred3, a, 1, gen_helper_sve_uzp_p) | |
2307 | TRANS_FEAT(TRN1_p, aa64_sve, do_perm_pred3, a, 0, gen_helper_sve_trn_p) | |
2308 | TRANS_FEAT(TRN2_p, aa64_sve, do_perm_pred3, a, 1, gen_helper_sve_trn_p) | |
d731d8cb | 2309 | |
1d0fce4b RH |
2310 | TRANS_FEAT(REV_p, aa64_sve, do_perm_pred2, a, 0, gen_helper_sve_rev_p) |
2311 | TRANS_FEAT(PUNPKLO, aa64_sve, do_perm_pred2, a, 0, gen_helper_sve_punpk_p) | |
2312 | TRANS_FEAT(PUNPKHI, aa64_sve, do_perm_pred2, a, 1, gen_helper_sve_punpk_p) | |
d731d8cb | 2313 | |
234b48e9 RH |
2314 | /* |
2315 | *** SVE Permute - Interleaving Group | |
2316 | */ | |
2317 | ||
a95b9618 RH |
2318 | static gen_helper_gvec_3 * const zip_fns[4] = { |
2319 | gen_helper_sve_zip_b, gen_helper_sve_zip_h, | |
2320 | gen_helper_sve_zip_s, gen_helper_sve_zip_d, | |
2321 | }; | |
2322 | TRANS_FEAT(ZIP1_z, aa64_sve, gen_gvec_ool_arg_zzz, | |
2323 | zip_fns[a->esz], a, 0) | |
2324 | TRANS_FEAT(ZIP2_z, aa64_sve, gen_gvec_ool_arg_zzz, | |
2325 | zip_fns[a->esz], a, vec_full_reg_size(s) / 2) | |
2326 | ||
2327 | TRANS_FEAT(ZIP1_q, aa64_sve_f64mm, gen_gvec_ool_arg_zzz, | |
2328 | gen_helper_sve2_zip_q, a, 0) | |
2329 | TRANS_FEAT(ZIP2_q, aa64_sve_f64mm, gen_gvec_ool_arg_zzz, | |
2330 | gen_helper_sve2_zip_q, a, | |
2331 | QEMU_ALIGN_DOWN(vec_full_reg_size(s), 32) / 2) | |
74b64b25 | 2332 | |
234b48e9 RH |
2333 | static gen_helper_gvec_3 * const uzp_fns[4] = { |
2334 | gen_helper_sve_uzp_b, gen_helper_sve_uzp_h, | |
2335 | gen_helper_sve_uzp_s, gen_helper_sve_uzp_d, | |
2336 | }; | |
2337 | ||
32e2ad65 RH |
2338 | TRANS_FEAT(UZP1_z, aa64_sve, gen_gvec_ool_arg_zzz, |
2339 | uzp_fns[a->esz], a, 0) | |
2340 | TRANS_FEAT(UZP2_z, aa64_sve, gen_gvec_ool_arg_zzz, | |
2341 | uzp_fns[a->esz], a, 1 << a->esz) | |
234b48e9 | 2342 | |
32e2ad65 RH |
2343 | TRANS_FEAT(UZP1_q, aa64_sve_f64mm, gen_gvec_ool_arg_zzz, |
2344 | gen_helper_sve2_uzp_q, a, 0) | |
2345 | TRANS_FEAT(UZP2_q, aa64_sve_f64mm, gen_gvec_ool_arg_zzz, | |
2346 | gen_helper_sve2_uzp_q, a, 16) | |
74b64b25 | 2347 | |
234b48e9 RH |
2348 | static gen_helper_gvec_3 * const trn_fns[4] = { |
2349 | gen_helper_sve_trn_b, gen_helper_sve_trn_h, | |
2350 | gen_helper_sve_trn_s, gen_helper_sve_trn_d, | |
2351 | }; | |
2352 | ||
32e2ad65 RH |
2353 | TRANS_FEAT(TRN1_z, aa64_sve, gen_gvec_ool_arg_zzz, |
2354 | trn_fns[a->esz], a, 0) | |
2355 | TRANS_FEAT(TRN2_z, aa64_sve, gen_gvec_ool_arg_zzz, | |
2356 | trn_fns[a->esz], a, 1 << a->esz) | |
234b48e9 | 2357 | |
32e2ad65 RH |
2358 | TRANS_FEAT(TRN1_q, aa64_sve_f64mm, gen_gvec_ool_arg_zzz, |
2359 | gen_helper_sve2_trn_q, a, 0) | |
2360 | TRANS_FEAT(TRN2_q, aa64_sve_f64mm, gen_gvec_ool_arg_zzz, | |
2361 | gen_helper_sve2_trn_q, a, 16) | |
74b64b25 | 2362 | |
3ca879ae RH |
2363 | /* |
2364 | *** SVE Permute Vector - Predicated Group | |
2365 | */ | |
2366 | ||
817bd5c9 RH |
2367 | static gen_helper_gvec_3 * const compact_fns[4] = { |
2368 | NULL, NULL, gen_helper_sve_compact_s, gen_helper_sve_compact_d | |
2369 | }; | |
2370 | TRANS_FEAT(COMPACT, aa64_sve, gen_gvec_ool_arg_zpz, compact_fns[a->esz], a, 0) | |
3ca879ae | 2371 | |
ef23cb72 RH |
2372 | /* Call the helper that computes the ARM LastActiveElement pseudocode |
2373 | * function, scaled by the element size. This includes the not found | |
2374 | * indication; e.g. not found for esz=3 is -8. | |
2375 | */ | |
2376 | static void find_last_active(DisasContext *s, TCGv_i32 ret, int esz, int pg) | |
2377 | { | |
2378 | /* Predicate sizes may be smaller and cannot use simd_desc. We cannot | |
2379 | * round up, as we do elsewhere, because we need the exact size. | |
2380 | */ | |
2381 | TCGv_ptr t_p = tcg_temp_new_ptr(); | |
2acbfbe4 | 2382 | unsigned desc = 0; |
ef23cb72 | 2383 | |
2acbfbe4 RH |
2384 | desc = FIELD_DP32(desc, PREDDESC, OPRSZ, pred_full_reg_size(s)); |
2385 | desc = FIELD_DP32(desc, PREDDESC, ESZ, esz); | |
ef23cb72 RH |
2386 | |
2387 | tcg_gen_addi_ptr(t_p, cpu_env, pred_full_reg_offset(s, pg)); | |
ef23cb72 | 2388 | |
c6a59b55 | 2389 | gen_helper_sve_last_active_element(ret, t_p, tcg_constant_i32(desc)); |
ef23cb72 | 2390 | |
ef23cb72 RH |
2391 | tcg_temp_free_ptr(t_p); |
2392 | } | |
2393 | ||
2394 | /* Increment LAST to the offset of the next element in the vector, | |
2395 | * wrapping around to 0. | |
2396 | */ | |
2397 | static void incr_last_active(DisasContext *s, TCGv_i32 last, int esz) | |
2398 | { | |
2399 | unsigned vsz = vec_full_reg_size(s); | |
2400 | ||
2401 | tcg_gen_addi_i32(last, last, 1 << esz); | |
2402 | if (is_power_of_2(vsz)) { | |
2403 | tcg_gen_andi_i32(last, last, vsz - 1); | |
2404 | } else { | |
4b308bd5 RH |
2405 | TCGv_i32 max = tcg_constant_i32(vsz); |
2406 | TCGv_i32 zero = tcg_constant_i32(0); | |
ef23cb72 | 2407 | tcg_gen_movcond_i32(TCG_COND_GEU, last, last, max, zero, last); |
ef23cb72 RH |
2408 | } |
2409 | } | |
2410 | ||
2411 | /* If LAST < 0, set LAST to the offset of the last element in the vector. */ | |
2412 | static void wrap_last_active(DisasContext *s, TCGv_i32 last, int esz) | |
2413 | { | |
2414 | unsigned vsz = vec_full_reg_size(s); | |
2415 | ||
2416 | if (is_power_of_2(vsz)) { | |
2417 | tcg_gen_andi_i32(last, last, vsz - 1); | |
2418 | } else { | |
4b308bd5 RH |
2419 | TCGv_i32 max = tcg_constant_i32(vsz - (1 << esz)); |
2420 | TCGv_i32 zero = tcg_constant_i32(0); | |
ef23cb72 | 2421 | tcg_gen_movcond_i32(TCG_COND_LT, last, last, zero, max, last); |
ef23cb72 RH |
2422 | } |
2423 | } | |
2424 | ||
2425 | /* Load an unsigned element of ESZ from BASE+OFS. */ | |
2426 | static TCGv_i64 load_esz(TCGv_ptr base, int ofs, int esz) | |
2427 | { | |
2428 | TCGv_i64 r = tcg_temp_new_i64(); | |
2429 | ||
2430 | switch (esz) { | |
2431 | case 0: | |
2432 | tcg_gen_ld8u_i64(r, base, ofs); | |
2433 | break; | |
2434 | case 1: | |
2435 | tcg_gen_ld16u_i64(r, base, ofs); | |
2436 | break; | |
2437 | case 2: | |
2438 | tcg_gen_ld32u_i64(r, base, ofs); | |
2439 | break; | |
2440 | case 3: | |
2441 | tcg_gen_ld_i64(r, base, ofs); | |
2442 | break; | |
2443 | default: | |
2444 | g_assert_not_reached(); | |
2445 | } | |
2446 | return r; | |
2447 | } | |
2448 | ||
2449 | /* Load an unsigned element of ESZ from RM[LAST]. */ | |
2450 | static TCGv_i64 load_last_active(DisasContext *s, TCGv_i32 last, | |
2451 | int rm, int esz) | |
2452 | { | |
2453 | TCGv_ptr p = tcg_temp_new_ptr(); | |
2454 | TCGv_i64 r; | |
2455 | ||
2456 | /* Convert offset into vector into offset into ENV. | |
2457 | * The final adjustment for the vector register base | |
2458 | * is added via constant offset to the load. | |
2459 | */ | |
e03b5686 | 2460 | #if HOST_BIG_ENDIAN |
ef23cb72 RH |
2461 | /* Adjust for element ordering. See vec_reg_offset. */ |
2462 | if (esz < 3) { | |
2463 | tcg_gen_xori_i32(last, last, 8 - (1 << esz)); | |
2464 | } | |
2465 | #endif | |
2466 | tcg_gen_ext_i32_ptr(p, last); | |
2467 | tcg_gen_add_ptr(p, p, cpu_env); | |
2468 | ||
2469 | r = load_esz(p, vec_full_reg_offset(s, rm), esz); | |
2470 | tcg_temp_free_ptr(p); | |
2471 | ||
2472 | return r; | |
2473 | } | |
2474 | ||
2475 | /* Compute CLAST for a Zreg. */ | |
2476 | static bool do_clast_vector(DisasContext *s, arg_rprr_esz *a, bool before) | |
2477 | { | |
2478 | TCGv_i32 last; | |
2479 | TCGLabel *over; | |
2480 | TCGv_i64 ele; | |
2481 | unsigned vsz, esz = a->esz; | |
2482 | ||
2483 | if (!sve_access_check(s)) { | |
2484 | return true; | |
2485 | } | |
2486 | ||
2487 | last = tcg_temp_local_new_i32(); | |
2488 | over = gen_new_label(); | |
2489 | ||
2490 | find_last_active(s, last, esz, a->pg); | |
2491 | ||
2492 | /* There is of course no movcond for a 2048-bit vector, | |
2493 | * so we must branch over the actual store. | |
2494 | */ | |
2495 | tcg_gen_brcondi_i32(TCG_COND_LT, last, 0, over); | |
2496 | ||
2497 | if (!before) { | |
2498 | incr_last_active(s, last, esz); | |
2499 | } | |
2500 | ||
2501 | ele = load_last_active(s, last, a->rm, esz); | |
2502 | tcg_temp_free_i32(last); | |
2503 | ||
2504 | vsz = vec_full_reg_size(s); | |
2505 | tcg_gen_gvec_dup_i64(esz, vec_full_reg_offset(s, a->rd), vsz, vsz, ele); | |
2506 | tcg_temp_free_i64(ele); | |
2507 | ||
2508 | /* If this insn used MOVPRFX, we may need a second move. */ | |
2509 | if (a->rd != a->rn) { | |
2510 | TCGLabel *done = gen_new_label(); | |
2511 | tcg_gen_br(done); | |
2512 | ||
2513 | gen_set_label(over); | |
2514 | do_mov_z(s, a->rd, a->rn); | |
2515 | ||
2516 | gen_set_label(done); | |
2517 | } else { | |
2518 | gen_set_label(over); | |
2519 | } | |
2520 | return true; | |
2521 | } | |
2522 | ||
db7fa5d8 RH |
2523 | TRANS_FEAT(CLASTA_z, aa64_sve, do_clast_vector, a, false) |
2524 | TRANS_FEAT(CLASTB_z, aa64_sve, do_clast_vector, a, true) | |
ef23cb72 RH |
2525 | |
2526 | /* Compute CLAST for a scalar. */ | |
2527 | static void do_clast_scalar(DisasContext *s, int esz, int pg, int rm, | |
2528 | bool before, TCGv_i64 reg_val) | |
2529 | { | |
2530 | TCGv_i32 last = tcg_temp_new_i32(); | |
053552d3 | 2531 | TCGv_i64 ele, cmp; |
ef23cb72 RH |
2532 | |
2533 | find_last_active(s, last, esz, pg); | |
2534 | ||
2535 | /* Extend the original value of last prior to incrementing. */ | |
2536 | cmp = tcg_temp_new_i64(); | |
2537 | tcg_gen_ext_i32_i64(cmp, last); | |
2538 | ||
2539 | if (!before) { | |
2540 | incr_last_active(s, last, esz); | |
2541 | } | |
2542 | ||
2543 | /* The conceit here is that while last < 0 indicates not found, after | |
2544 | * adjusting for cpu_env->vfp.zregs[rm], it is still a valid address | |
2545 | * from which we can load garbage. We then discard the garbage with | |
2546 | * a conditional move. | |
2547 | */ | |
2548 | ele = load_last_active(s, last, rm, esz); | |
2549 | tcg_temp_free_i32(last); | |
2550 | ||
053552d3 RH |
2551 | tcg_gen_movcond_i64(TCG_COND_GE, reg_val, cmp, tcg_constant_i64(0), |
2552 | ele, reg_val); | |
ef23cb72 | 2553 | |
ef23cb72 RH |
2554 | tcg_temp_free_i64(cmp); |
2555 | tcg_temp_free_i64(ele); | |
2556 | } | |
2557 | ||
2558 | /* Compute CLAST for a Vreg. */ | |
2559 | static bool do_clast_fp(DisasContext *s, arg_rpr_esz *a, bool before) | |
2560 | { | |
2561 | if (sve_access_check(s)) { | |
2562 | int esz = a->esz; | |
2563 | int ofs = vec_reg_offset(s, a->rd, 0, esz); | |
2564 | TCGv_i64 reg = load_esz(cpu_env, ofs, esz); | |
2565 | ||
2566 | do_clast_scalar(s, esz, a->pg, a->rn, before, reg); | |
2567 | write_fp_dreg(s, a->rd, reg); | |
2568 | tcg_temp_free_i64(reg); | |
2569 | } | |
2570 | return true; | |
2571 | } | |
2572 | ||
ac4fb247 RH |
2573 | TRANS_FEAT(CLASTA_v, aa64_sve, do_clast_fp, a, false) |
2574 | TRANS_FEAT(CLASTB_v, aa64_sve, do_clast_fp, a, true) | |
ef23cb72 RH |
2575 | |
2576 | /* Compute CLAST for a Xreg. */ | |
2577 | static bool do_clast_general(DisasContext *s, arg_rpr_esz *a, bool before) | |
2578 | { | |
2579 | TCGv_i64 reg; | |
2580 | ||
2581 | if (!sve_access_check(s)) { | |
2582 | return true; | |
2583 | } | |
2584 | ||
2585 | reg = cpu_reg(s, a->rd); | |
2586 | switch (a->esz) { | |
2587 | case 0: | |
2588 | tcg_gen_ext8u_i64(reg, reg); | |
2589 | break; | |
2590 | case 1: | |
2591 | tcg_gen_ext16u_i64(reg, reg); | |
2592 | break; | |
2593 | case 2: | |
2594 | tcg_gen_ext32u_i64(reg, reg); | |
2595 | break; | |
2596 | case 3: | |
2597 | break; | |
2598 | default: | |
2599 | g_assert_not_reached(); | |
2600 | } | |
2601 | ||
2602 | do_clast_scalar(s, a->esz, a->pg, a->rn, before, reg); | |
2603 | return true; | |
2604 | } | |
2605 | ||
c673404a RH |
2606 | TRANS_FEAT(CLASTA_r, aa64_sve, do_clast_general, a, false) |
2607 | TRANS_FEAT(CLASTB_r, aa64_sve, do_clast_general, a, true) | |
ef23cb72 RH |
2608 | |
2609 | /* Compute LAST for a scalar. */ | |
2610 | static TCGv_i64 do_last_scalar(DisasContext *s, int esz, | |
2611 | int pg, int rm, bool before) | |
2612 | { | |
2613 | TCGv_i32 last = tcg_temp_new_i32(); | |
2614 | TCGv_i64 ret; | |
2615 | ||
2616 | find_last_active(s, last, esz, pg); | |
2617 | if (before) { | |
2618 | wrap_last_active(s, last, esz); | |
2619 | } else { | |
2620 | incr_last_active(s, last, esz); | |
2621 | } | |
2622 | ||
2623 | ret = load_last_active(s, last, rm, esz); | |
2624 | tcg_temp_free_i32(last); | |
2625 | return ret; | |
2626 | } | |
2627 | ||
2628 | /* Compute LAST for a Vreg. */ | |
2629 | static bool do_last_fp(DisasContext *s, arg_rpr_esz *a, bool before) | |
2630 | { | |
2631 | if (sve_access_check(s)) { | |
2632 | TCGv_i64 val = do_last_scalar(s, a->esz, a->pg, a->rn, before); | |
2633 | write_fp_dreg(s, a->rd, val); | |
2634 | tcg_temp_free_i64(val); | |
2635 | } | |
2636 | return true; | |
2637 | } | |
2638 | ||
75de9fd4 RH |
2639 | TRANS_FEAT(LASTA_v, aa64_sve, do_last_fp, a, false) |
2640 | TRANS_FEAT(LASTB_v, aa64_sve, do_last_fp, a, true) | |
ef23cb72 RH |
2641 | |
2642 | /* Compute LAST for a Xreg. */ | |
2643 | static bool do_last_general(DisasContext *s, arg_rpr_esz *a, bool before) | |
2644 | { | |
2645 | if (sve_access_check(s)) { | |
2646 | TCGv_i64 val = do_last_scalar(s, a->esz, a->pg, a->rn, before); | |
2647 | tcg_gen_mov_i64(cpu_reg(s, a->rd), val); | |
2648 | tcg_temp_free_i64(val); | |
2649 | } | |
2650 | return true; | |
2651 | } | |
2652 | ||
884c5a80 RH |
2653 | TRANS_FEAT(LASTA_r, aa64_sve, do_last_general, a, false) |
2654 | TRANS_FEAT(LASTB_r, aa64_sve, do_last_general, a, true) | |
ef23cb72 | 2655 | |
3a7be554 | 2656 | static bool trans_CPY_m_r(DisasContext *s, arg_rpr_esz *a) |
792a5578 RH |
2657 | { |
2658 | if (sve_access_check(s)) { | |
2659 | do_cpy_m(s, a->esz, a->rd, a->rd, a->pg, cpu_reg_sp(s, a->rn)); | |
2660 | } | |
2661 | return true; | |
2662 | } | |
2663 | ||
3a7be554 | 2664 | static bool trans_CPY_m_v(DisasContext *s, arg_rpr_esz *a) |
792a5578 RH |
2665 | { |
2666 | if (sve_access_check(s)) { | |
2667 | int ofs = vec_reg_offset(s, a->rn, 0, a->esz); | |
2668 | TCGv_i64 t = load_esz(cpu_env, ofs, a->esz); | |
2669 | do_cpy_m(s, a->esz, a->rd, a->rd, a->pg, t); | |
2670 | tcg_temp_free_i64(t); | |
2671 | } | |
2672 | return true; | |
2673 | } | |
2674 | ||
817bd5c9 RH |
2675 | static gen_helper_gvec_3 * const revb_fns[4] = { |
2676 | NULL, gen_helper_sve_revb_h, | |
2677 | gen_helper_sve_revb_s, gen_helper_sve_revb_d, | |
2678 | }; | |
2679 | TRANS_FEAT(REVB, aa64_sve, gen_gvec_ool_arg_zpz, revb_fns[a->esz], a, 0) | |
dae8fb90 | 2680 | |
817bd5c9 RH |
2681 | static gen_helper_gvec_3 * const revh_fns[4] = { |
2682 | NULL, NULL, gen_helper_sve_revh_s, gen_helper_sve_revh_d, | |
2683 | }; | |
2684 | TRANS_FEAT(REVH, aa64_sve, gen_gvec_ool_arg_zpz, revh_fns[a->esz], a, 0) | |
dae8fb90 | 2685 | |
817bd5c9 RH |
2686 | TRANS_FEAT(REVW, aa64_sve, gen_gvec_ool_arg_zpz, |
2687 | a->esz == 3 ? gen_helper_sve_revw_d : NULL, a, 0) | |
dae8fb90 | 2688 | |
897ebd70 RH |
2689 | TRANS_FEAT(SPLICE, aa64_sve, gen_gvec_ool_arg_zpzz, |
2690 | gen_helper_sve_splice, a, a->esz) | |
b48ff240 | 2691 | |
897ebd70 RH |
2692 | TRANS_FEAT(SPLICE_sve2, aa64_sve2, gen_gvec_ool_zzzp, gen_helper_sve_splice, |
2693 | a->rd, a->rn, (a->rn + 1) % 32, a->pg, a->esz) | |
75114792 | 2694 | |
757f9cff RH |
2695 | /* |
2696 | *** SVE Integer Compare - Vectors Group | |
2697 | */ | |
2698 | ||
2699 | static bool do_ppzz_flags(DisasContext *s, arg_rprr_esz *a, | |
2700 | gen_helper_gvec_flags_4 *gen_fn) | |
2701 | { | |
2702 | TCGv_ptr pd, zn, zm, pg; | |
2703 | unsigned vsz; | |
2704 | TCGv_i32 t; | |
2705 | ||
2706 | if (gen_fn == NULL) { | |
2707 | return false; | |
2708 | } | |
2709 | if (!sve_access_check(s)) { | |
2710 | return true; | |
2711 | } | |
2712 | ||
2713 | vsz = vec_full_reg_size(s); | |
392acacc | 2714 | t = tcg_temp_new_i32(); |
757f9cff RH |
2715 | pd = tcg_temp_new_ptr(); |
2716 | zn = tcg_temp_new_ptr(); | |
2717 | zm = tcg_temp_new_ptr(); | |
2718 | pg = tcg_temp_new_ptr(); | |
2719 | ||
2720 | tcg_gen_addi_ptr(pd, cpu_env, pred_full_reg_offset(s, a->rd)); | |
2721 | tcg_gen_addi_ptr(zn, cpu_env, vec_full_reg_offset(s, a->rn)); | |
2722 | tcg_gen_addi_ptr(zm, cpu_env, vec_full_reg_offset(s, a->rm)); | |
2723 | tcg_gen_addi_ptr(pg, cpu_env, pred_full_reg_offset(s, a->pg)); | |
2724 | ||
392acacc | 2725 | gen_fn(t, pd, zn, zm, pg, tcg_constant_i32(simd_desc(vsz, vsz, 0))); |
757f9cff RH |
2726 | |
2727 | tcg_temp_free_ptr(pd); | |
2728 | tcg_temp_free_ptr(zn); | |
2729 | tcg_temp_free_ptr(zm); | |
2730 | tcg_temp_free_ptr(pg); | |
2731 | ||
2732 | do_pred_flags(t); | |
2733 | ||
2734 | tcg_temp_free_i32(t); | |
2735 | return true; | |
2736 | } | |
2737 | ||
2738 | #define DO_PPZZ(NAME, name) \ | |
671bdb2e RH |
2739 | static gen_helper_gvec_flags_4 * const name##_ppzz_fns[4] = { \ |
2740 | gen_helper_sve_##name##_ppzz_b, gen_helper_sve_##name##_ppzz_h, \ | |
2741 | gen_helper_sve_##name##_ppzz_s, gen_helper_sve_##name##_ppzz_d, \ | |
2742 | }; \ | |
2743 | TRANS_FEAT(NAME##_ppzz, aa64_sve, do_ppzz_flags, \ | |
2744 | a, name##_ppzz_fns[a->esz]) | |
757f9cff RH |
2745 | |
2746 | DO_PPZZ(CMPEQ, cmpeq) | |
2747 | DO_PPZZ(CMPNE, cmpne) | |
2748 | DO_PPZZ(CMPGT, cmpgt) | |
2749 | DO_PPZZ(CMPGE, cmpge) | |
2750 | DO_PPZZ(CMPHI, cmphi) | |
2751 | DO_PPZZ(CMPHS, cmphs) | |
2752 | ||
2753 | #undef DO_PPZZ | |
2754 | ||
2755 | #define DO_PPZW(NAME, name) \ | |
671bdb2e RH |
2756 | static gen_helper_gvec_flags_4 * const name##_ppzw_fns[4] = { \ |
2757 | gen_helper_sve_##name##_ppzw_b, gen_helper_sve_##name##_ppzw_h, \ | |
2758 | gen_helper_sve_##name##_ppzw_s, NULL \ | |
2759 | }; \ | |
2760 | TRANS_FEAT(NAME##_ppzw, aa64_sve, do_ppzz_flags, \ | |
2761 | a, name##_ppzw_fns[a->esz]) | |
757f9cff RH |
2762 | |
2763 | DO_PPZW(CMPEQ, cmpeq) | |
2764 | DO_PPZW(CMPNE, cmpne) | |
2765 | DO_PPZW(CMPGT, cmpgt) | |
2766 | DO_PPZW(CMPGE, cmpge) | |
2767 | DO_PPZW(CMPHI, cmphi) | |
2768 | DO_PPZW(CMPHS, cmphs) | |
2769 | DO_PPZW(CMPLT, cmplt) | |
2770 | DO_PPZW(CMPLE, cmple) | |
2771 | DO_PPZW(CMPLO, cmplo) | |
2772 | DO_PPZW(CMPLS, cmpls) | |
2773 | ||
2774 | #undef DO_PPZW | |
2775 | ||
38cadeba RH |
2776 | /* |
2777 | *** SVE Integer Compare - Immediate Groups | |
2778 | */ | |
2779 | ||
2780 | static bool do_ppzi_flags(DisasContext *s, arg_rpri_esz *a, | |
2781 | gen_helper_gvec_flags_3 *gen_fn) | |
2782 | { | |
2783 | TCGv_ptr pd, zn, pg; | |
2784 | unsigned vsz; | |
2785 | TCGv_i32 t; | |
2786 | ||
2787 | if (gen_fn == NULL) { | |
2788 | return false; | |
2789 | } | |
2790 | if (!sve_access_check(s)) { | |
2791 | return true; | |
2792 | } | |
2793 | ||
2794 | vsz = vec_full_reg_size(s); | |
392acacc | 2795 | t = tcg_temp_new_i32(); |
38cadeba RH |
2796 | pd = tcg_temp_new_ptr(); |
2797 | zn = tcg_temp_new_ptr(); | |
2798 | pg = tcg_temp_new_ptr(); | |
2799 | ||
2800 | tcg_gen_addi_ptr(pd, cpu_env, pred_full_reg_offset(s, a->rd)); | |
2801 | tcg_gen_addi_ptr(zn, cpu_env, vec_full_reg_offset(s, a->rn)); | |
2802 | tcg_gen_addi_ptr(pg, cpu_env, pred_full_reg_offset(s, a->pg)); | |
2803 | ||
392acacc | 2804 | gen_fn(t, pd, zn, pg, tcg_constant_i32(simd_desc(vsz, vsz, a->imm))); |
38cadeba RH |
2805 | |
2806 | tcg_temp_free_ptr(pd); | |
2807 | tcg_temp_free_ptr(zn); | |
2808 | tcg_temp_free_ptr(pg); | |
2809 | ||
2810 | do_pred_flags(t); | |
2811 | ||
2812 | tcg_temp_free_i32(t); | |
2813 | return true; | |
2814 | } | |
2815 | ||
2816 | #define DO_PPZI(NAME, name) \ | |
9c545be6 | 2817 | static gen_helper_gvec_flags_3 * const name##_ppzi_fns[4] = { \ |
38cadeba RH |
2818 | gen_helper_sve_##name##_ppzi_b, gen_helper_sve_##name##_ppzi_h, \ |
2819 | gen_helper_sve_##name##_ppzi_s, gen_helper_sve_##name##_ppzi_d, \ | |
2820 | }; \ | |
9c545be6 RH |
2821 | TRANS_FEAT(NAME##_ppzi, aa64_sve, do_ppzi_flags, a, \ |
2822 | name##_ppzi_fns[a->esz]) | |
38cadeba RH |
2823 | |
2824 | DO_PPZI(CMPEQ, cmpeq) | |
2825 | DO_PPZI(CMPNE, cmpne) | |
2826 | DO_PPZI(CMPGT, cmpgt) | |
2827 | DO_PPZI(CMPGE, cmpge) | |
2828 | DO_PPZI(CMPHI, cmphi) | |
2829 | DO_PPZI(CMPHS, cmphs) | |
2830 | DO_PPZI(CMPLT, cmplt) | |
2831 | DO_PPZI(CMPLE, cmple) | |
2832 | DO_PPZI(CMPLO, cmplo) | |
2833 | DO_PPZI(CMPLS, cmpls) | |
2834 | ||
2835 | #undef DO_PPZI | |
2836 | ||
35da316f RH |
2837 | /* |
2838 | *** SVE Partition Break Group | |
2839 | */ | |
2840 | ||
2841 | static bool do_brk3(DisasContext *s, arg_rprr_s *a, | |
2842 | gen_helper_gvec_4 *fn, gen_helper_gvec_flags_4 *fn_s) | |
2843 | { | |
2844 | if (!sve_access_check(s)) { | |
2845 | return true; | |
2846 | } | |
2847 | ||
2848 | unsigned vsz = pred_full_reg_size(s); | |
2849 | ||
2850 | /* Predicate sizes may be smaller and cannot use simd_desc. */ | |
2851 | TCGv_ptr d = tcg_temp_new_ptr(); | |
2852 | TCGv_ptr n = tcg_temp_new_ptr(); | |
2853 | TCGv_ptr m = tcg_temp_new_ptr(); | |
2854 | TCGv_ptr g = tcg_temp_new_ptr(); | |
93418f1c | 2855 | TCGv_i32 desc = tcg_constant_i32(FIELD_DP32(0, PREDDESC, OPRSZ, vsz)); |
35da316f RH |
2856 | |
2857 | tcg_gen_addi_ptr(d, cpu_env, pred_full_reg_offset(s, a->rd)); | |
2858 | tcg_gen_addi_ptr(n, cpu_env, pred_full_reg_offset(s, a->rn)); | |
2859 | tcg_gen_addi_ptr(m, cpu_env, pred_full_reg_offset(s, a->rm)); | |
2860 | tcg_gen_addi_ptr(g, cpu_env, pred_full_reg_offset(s, a->pg)); | |
2861 | ||
2862 | if (a->s) { | |
93418f1c RH |
2863 | TCGv_i32 t = tcg_temp_new_i32(); |
2864 | fn_s(t, d, n, m, g, desc); | |
35da316f | 2865 | do_pred_flags(t); |
93418f1c | 2866 | tcg_temp_free_i32(t); |
35da316f | 2867 | } else { |
93418f1c | 2868 | fn(d, n, m, g, desc); |
35da316f RH |
2869 | } |
2870 | tcg_temp_free_ptr(d); | |
2871 | tcg_temp_free_ptr(n); | |
2872 | tcg_temp_free_ptr(m); | |
2873 | tcg_temp_free_ptr(g); | |
35da316f RH |
2874 | return true; |
2875 | } | |
2876 | ||
2877 | static bool do_brk2(DisasContext *s, arg_rpr_s *a, | |
2878 | gen_helper_gvec_3 *fn, gen_helper_gvec_flags_3 *fn_s) | |
2879 | { | |
2880 | if (!sve_access_check(s)) { | |
2881 | return true; | |
2882 | } | |
2883 | ||
2884 | unsigned vsz = pred_full_reg_size(s); | |
2885 | ||
2886 | /* Predicate sizes may be smaller and cannot use simd_desc. */ | |
2887 | TCGv_ptr d = tcg_temp_new_ptr(); | |
2888 | TCGv_ptr n = tcg_temp_new_ptr(); | |
2889 | TCGv_ptr g = tcg_temp_new_ptr(); | |
93418f1c | 2890 | TCGv_i32 desc = tcg_constant_i32(FIELD_DP32(0, PREDDESC, OPRSZ, vsz)); |
35da316f RH |
2891 | |
2892 | tcg_gen_addi_ptr(d, cpu_env, pred_full_reg_offset(s, a->rd)); | |
2893 | tcg_gen_addi_ptr(n, cpu_env, pred_full_reg_offset(s, a->rn)); | |
2894 | tcg_gen_addi_ptr(g, cpu_env, pred_full_reg_offset(s, a->pg)); | |
2895 | ||
2896 | if (a->s) { | |
93418f1c RH |
2897 | TCGv_i32 t = tcg_temp_new_i32(); |
2898 | fn_s(t, d, n, g, desc); | |
35da316f | 2899 | do_pred_flags(t); |
93418f1c | 2900 | tcg_temp_free_i32(t); |
35da316f | 2901 | } else { |
93418f1c | 2902 | fn(d, n, g, desc); |
35da316f RH |
2903 | } |
2904 | tcg_temp_free_ptr(d); | |
2905 | tcg_temp_free_ptr(n); | |
2906 | tcg_temp_free_ptr(g); | |
35da316f RH |
2907 | return true; |
2908 | } | |
2909 | ||
2224d24d RH |
2910 | TRANS_FEAT(BRKPA, aa64_sve, do_brk3, a, |
2911 | gen_helper_sve_brkpa, gen_helper_sve_brkpas) | |
2912 | TRANS_FEAT(BRKPB, aa64_sve, do_brk3, a, | |
2913 | gen_helper_sve_brkpb, gen_helper_sve_brkpbs) | |
2914 | ||
2915 | TRANS_FEAT(BRKA_m, aa64_sve, do_brk2, a, | |
2916 | gen_helper_sve_brka_m, gen_helper_sve_brkas_m) | |
2917 | TRANS_FEAT(BRKB_m, aa64_sve, do_brk2, a, | |
2918 | gen_helper_sve_brkb_m, gen_helper_sve_brkbs_m) | |
2919 | ||
2920 | TRANS_FEAT(BRKA_z, aa64_sve, do_brk2, a, | |
2921 | gen_helper_sve_brka_z, gen_helper_sve_brkas_z) | |
2922 | TRANS_FEAT(BRKB_z, aa64_sve, do_brk2, a, | |
2923 | gen_helper_sve_brkb_z, gen_helper_sve_brkbs_z) | |
2924 | ||
2925 | TRANS_FEAT(BRKN, aa64_sve, do_brk2, a, | |
2926 | gen_helper_sve_brkn, gen_helper_sve_brkns) | |
35da316f | 2927 | |
9ee3a611 RH |
2928 | /* |
2929 | *** SVE Predicate Count Group | |
2930 | */ | |
2931 | ||
2932 | static void do_cntp(DisasContext *s, TCGv_i64 val, int esz, int pn, int pg) | |
2933 | { | |
2934 | unsigned psz = pred_full_reg_size(s); | |
2935 | ||
2936 | if (psz <= 8) { | |
2937 | uint64_t psz_mask; | |
2938 | ||
2939 | tcg_gen_ld_i64(val, cpu_env, pred_full_reg_offset(s, pn)); | |
2940 | if (pn != pg) { | |
2941 | TCGv_i64 g = tcg_temp_new_i64(); | |
2942 | tcg_gen_ld_i64(g, cpu_env, pred_full_reg_offset(s, pg)); | |
2943 | tcg_gen_and_i64(val, val, g); | |
2944 | tcg_temp_free_i64(g); | |
2945 | } | |
2946 | ||
2947 | /* Reduce the pred_esz_masks value simply to reduce the | |
2948 | * size of the code generated here. | |
2949 | */ | |
2950 | psz_mask = MAKE_64BIT_MASK(0, psz * 8); | |
2951 | tcg_gen_andi_i64(val, val, pred_esz_masks[esz] & psz_mask); | |
2952 | ||
2953 | tcg_gen_ctpop_i64(val, val); | |
2954 | } else { | |
2955 | TCGv_ptr t_pn = tcg_temp_new_ptr(); | |
2956 | TCGv_ptr t_pg = tcg_temp_new_ptr(); | |
f556a201 | 2957 | unsigned desc = 0; |
9ee3a611 | 2958 | |
f556a201 RH |
2959 | desc = FIELD_DP32(desc, PREDDESC, OPRSZ, psz); |
2960 | desc = FIELD_DP32(desc, PREDDESC, ESZ, esz); | |
9ee3a611 RH |
2961 | |
2962 | tcg_gen_addi_ptr(t_pn, cpu_env, pred_full_reg_offset(s, pn)); | |
2963 | tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, pg)); | |
9ee3a611 | 2964 | |
c6a59b55 | 2965 | gen_helper_sve_cntp(val, t_pn, t_pg, tcg_constant_i32(desc)); |
9ee3a611 RH |
2966 | tcg_temp_free_ptr(t_pn); |
2967 | tcg_temp_free_ptr(t_pg); | |
9ee3a611 RH |
2968 | } |
2969 | } | |
2970 | ||
3a7be554 | 2971 | static bool trans_CNTP(DisasContext *s, arg_CNTP *a) |
9ee3a611 RH |
2972 | { |
2973 | if (sve_access_check(s)) { | |
2974 | do_cntp(s, cpu_reg(s, a->rd), a->esz, a->rn, a->pg); | |
2975 | } | |
2976 | return true; | |
2977 | } | |
2978 | ||
3a7be554 | 2979 | static bool trans_INCDECP_r(DisasContext *s, arg_incdec_pred *a) |
9ee3a611 RH |
2980 | { |
2981 | if (sve_access_check(s)) { | |
2982 | TCGv_i64 reg = cpu_reg(s, a->rd); | |
2983 | TCGv_i64 val = tcg_temp_new_i64(); | |
2984 | ||
2985 | do_cntp(s, val, a->esz, a->pg, a->pg); | |
2986 | if (a->d) { | |
2987 | tcg_gen_sub_i64(reg, reg, val); | |
2988 | } else { | |
2989 | tcg_gen_add_i64(reg, reg, val); | |
2990 | } | |
2991 | tcg_temp_free_i64(val); | |
2992 | } | |
2993 | return true; | |
2994 | } | |
2995 | ||
3a7be554 | 2996 | static bool trans_INCDECP_z(DisasContext *s, arg_incdec2_pred *a) |
9ee3a611 RH |
2997 | { |
2998 | if (a->esz == 0) { | |
2999 | return false; | |
3000 | } | |
3001 | if (sve_access_check(s)) { | |
3002 | unsigned vsz = vec_full_reg_size(s); | |
3003 | TCGv_i64 val = tcg_temp_new_i64(); | |
3004 | GVecGen2sFn *gvec_fn = a->d ? tcg_gen_gvec_subs : tcg_gen_gvec_adds; | |
3005 | ||
3006 | do_cntp(s, val, a->esz, a->pg, a->pg); | |
3007 | gvec_fn(a->esz, vec_full_reg_offset(s, a->rd), | |
3008 | vec_full_reg_offset(s, a->rn), val, vsz, vsz); | |
3009 | } | |
3010 | return true; | |
3011 | } | |
3012 | ||
3a7be554 | 3013 | static bool trans_SINCDECP_r_32(DisasContext *s, arg_incdec_pred *a) |
9ee3a611 RH |
3014 | { |
3015 | if (sve_access_check(s)) { | |
3016 | TCGv_i64 reg = cpu_reg(s, a->rd); | |
3017 | TCGv_i64 val = tcg_temp_new_i64(); | |
3018 | ||
3019 | do_cntp(s, val, a->esz, a->pg, a->pg); | |
3020 | do_sat_addsub_32(reg, val, a->u, a->d); | |
3021 | } | |
3022 | return true; | |
3023 | } | |
3024 | ||
3a7be554 | 3025 | static bool trans_SINCDECP_r_64(DisasContext *s, arg_incdec_pred *a) |
9ee3a611 RH |
3026 | { |
3027 | if (sve_access_check(s)) { | |
3028 | TCGv_i64 reg = cpu_reg(s, a->rd); | |
3029 | TCGv_i64 val = tcg_temp_new_i64(); | |
3030 | ||
3031 | do_cntp(s, val, a->esz, a->pg, a->pg); | |
3032 | do_sat_addsub_64(reg, val, a->u, a->d); | |
3033 | } | |
3034 | return true; | |
3035 | } | |
3036 | ||
3a7be554 | 3037 | static bool trans_SINCDECP_z(DisasContext *s, arg_incdec2_pred *a) |
9ee3a611 RH |
3038 | { |
3039 | if (a->esz == 0) { | |
3040 | return false; | |
3041 | } | |
3042 | if (sve_access_check(s)) { | |
3043 | TCGv_i64 val = tcg_temp_new_i64(); | |
3044 | do_cntp(s, val, a->esz, a->pg, a->pg); | |
3045 | do_sat_addsub_vec(s, a->esz, a->rd, a->rn, val, a->u, a->d); | |
3046 | } | |
3047 | return true; | |
3048 | } | |
3049 | ||
caf1cefc RH |
3050 | /* |
3051 | *** SVE Integer Compare Scalars Group | |
3052 | */ | |
3053 | ||
3a7be554 | 3054 | static bool trans_CTERM(DisasContext *s, arg_CTERM *a) |
caf1cefc RH |
3055 | { |
3056 | if (!sve_access_check(s)) { | |
3057 | return true; | |
3058 | } | |
3059 | ||
3060 | TCGCond cond = (a->ne ? TCG_COND_NE : TCG_COND_EQ); | |
3061 | TCGv_i64 rn = read_cpu_reg(s, a->rn, a->sf); | |
3062 | TCGv_i64 rm = read_cpu_reg(s, a->rm, a->sf); | |
3063 | TCGv_i64 cmp = tcg_temp_new_i64(); | |
3064 | ||
3065 | tcg_gen_setcond_i64(cond, cmp, rn, rm); | |
3066 | tcg_gen_extrl_i64_i32(cpu_NF, cmp); | |
3067 | tcg_temp_free_i64(cmp); | |
3068 | ||
3069 | /* VF = !NF & !CF. */ | |
3070 | tcg_gen_xori_i32(cpu_VF, cpu_NF, 1); | |
3071 | tcg_gen_andc_i32(cpu_VF, cpu_VF, cpu_CF); | |
3072 | ||
3073 | /* Both NF and VF actually look at bit 31. */ | |
3074 | tcg_gen_neg_i32(cpu_NF, cpu_NF); | |
3075 | tcg_gen_neg_i32(cpu_VF, cpu_VF); | |
3076 | return true; | |
3077 | } | |
3078 | ||
3a7be554 | 3079 | static bool trans_WHILE(DisasContext *s, arg_WHILE *a) |
caf1cefc | 3080 | { |
bbd0968c | 3081 | TCGv_i64 op0, op1, t0, t1, tmax; |
4481bbf2 | 3082 | TCGv_i32 t2; |
caf1cefc | 3083 | TCGv_ptr ptr; |
e610906c RH |
3084 | unsigned vsz = vec_full_reg_size(s); |
3085 | unsigned desc = 0; | |
caf1cefc | 3086 | TCGCond cond; |
34688dbc RH |
3087 | uint64_t maxval; |
3088 | /* Note that GE/HS has a->eq == 0 and GT/HI has a->eq == 1. */ | |
3089 | bool eq = a->eq == a->lt; | |
caf1cefc | 3090 | |
34688dbc RH |
3091 | /* The greater-than conditions are all SVE2. */ |
3092 | if (!a->lt && !dc_isar_feature(aa64_sve2, s)) { | |
3093 | return false; | |
3094 | } | |
bbd0968c RH |
3095 | if (!sve_access_check(s)) { |
3096 | return true; | |
3097 | } | |
3098 | ||
3099 | op0 = read_cpu_reg(s, a->rn, 1); | |
3100 | op1 = read_cpu_reg(s, a->rm, 1); | |
3101 | ||
caf1cefc RH |
3102 | if (!a->sf) { |
3103 | if (a->u) { | |
3104 | tcg_gen_ext32u_i64(op0, op0); | |
3105 | tcg_gen_ext32u_i64(op1, op1); | |
3106 | } else { | |
3107 | tcg_gen_ext32s_i64(op0, op0); | |
3108 | tcg_gen_ext32s_i64(op1, op1); | |
3109 | } | |
3110 | } | |
3111 | ||
3112 | /* For the helper, compress the different conditions into a computation | |
3113 | * of how many iterations for which the condition is true. | |
caf1cefc | 3114 | */ |
bbd0968c RH |
3115 | t0 = tcg_temp_new_i64(); |
3116 | t1 = tcg_temp_new_i64(); | |
34688dbc RH |
3117 | |
3118 | if (a->lt) { | |
3119 | tcg_gen_sub_i64(t0, op1, op0); | |
3120 | if (a->u) { | |
3121 | maxval = a->sf ? UINT64_MAX : UINT32_MAX; | |
3122 | cond = eq ? TCG_COND_LEU : TCG_COND_LTU; | |
3123 | } else { | |
3124 | maxval = a->sf ? INT64_MAX : INT32_MAX; | |
3125 | cond = eq ? TCG_COND_LE : TCG_COND_LT; | |
3126 | } | |
3127 | } else { | |
3128 | tcg_gen_sub_i64(t0, op0, op1); | |
3129 | if (a->u) { | |
3130 | maxval = 0; | |
3131 | cond = eq ? TCG_COND_GEU : TCG_COND_GTU; | |
3132 | } else { | |
3133 | maxval = a->sf ? INT64_MIN : INT32_MIN; | |
3134 | cond = eq ? TCG_COND_GE : TCG_COND_GT; | |
3135 | } | |
3136 | } | |
caf1cefc | 3137 | |
4481bbf2 | 3138 | tmax = tcg_constant_i64(vsz >> a->esz); |
34688dbc | 3139 | if (eq) { |
caf1cefc RH |
3140 | /* Equality means one more iteration. */ |
3141 | tcg_gen_addi_i64(t0, t0, 1); | |
bbd0968c | 3142 | |
34688dbc RH |
3143 | /* |
3144 | * For the less-than while, if op1 is maxval (and the only time | |
3145 | * the addition above could overflow), then we produce an all-true | |
3146 | * predicate by setting the count to the vector length. This is | |
3147 | * because the pseudocode is described as an increment + compare | |
3148 | * loop, and the maximum integer would always compare true. | |
3149 | * Similarly, the greater-than while has the same issue with the | |
3150 | * minimum integer due to the decrement + compare loop. | |
bbd0968c | 3151 | */ |
34688dbc | 3152 | tcg_gen_movi_i64(t1, maxval); |
bbd0968c | 3153 | tcg_gen_movcond_i64(TCG_COND_EQ, t0, op1, t1, tmax, t0); |
caf1cefc RH |
3154 | } |
3155 | ||
bbd0968c RH |
3156 | /* Bound to the maximum. */ |
3157 | tcg_gen_umin_i64(t0, t0, tmax); | |
bbd0968c RH |
3158 | |
3159 | /* Set the count to zero if the condition is false. */ | |
caf1cefc RH |
3160 | tcg_gen_movi_i64(t1, 0); |
3161 | tcg_gen_movcond_i64(cond, t0, op0, op1, t0, t1); | |
bbd0968c | 3162 | tcg_temp_free_i64(t1); |
caf1cefc | 3163 | |
bbd0968c | 3164 | /* Since we're bounded, pass as a 32-bit type. */ |
caf1cefc RH |
3165 | t2 = tcg_temp_new_i32(); |
3166 | tcg_gen_extrl_i64_i32(t2, t0); | |
3167 | tcg_temp_free_i64(t0); | |
bbd0968c RH |
3168 | |
3169 | /* Scale elements to bits. */ | |
3170 | tcg_gen_shli_i32(t2, t2, a->esz); | |
caf1cefc | 3171 | |
e610906c RH |
3172 | desc = FIELD_DP32(desc, PREDDESC, OPRSZ, vsz / 8); |
3173 | desc = FIELD_DP32(desc, PREDDESC, ESZ, a->esz); | |
caf1cefc RH |
3174 | |
3175 | ptr = tcg_temp_new_ptr(); | |
3176 | tcg_gen_addi_ptr(ptr, cpu_env, pred_full_reg_offset(s, a->rd)); | |
3177 | ||
34688dbc | 3178 | if (a->lt) { |
4481bbf2 | 3179 | gen_helper_sve_whilel(t2, ptr, t2, tcg_constant_i32(desc)); |
34688dbc | 3180 | } else { |
4481bbf2 | 3181 | gen_helper_sve_whileg(t2, ptr, t2, tcg_constant_i32(desc)); |
34688dbc | 3182 | } |
caf1cefc RH |
3183 | do_pred_flags(t2); |
3184 | ||
3185 | tcg_temp_free_ptr(ptr); | |
3186 | tcg_temp_free_i32(t2); | |
caf1cefc RH |
3187 | return true; |
3188 | } | |
3189 | ||
14f6dad1 RH |
3190 | static bool trans_WHILE_ptr(DisasContext *s, arg_WHILE_ptr *a) |
3191 | { | |
3192 | TCGv_i64 op0, op1, diff, t1, tmax; | |
4481bbf2 | 3193 | TCGv_i32 t2; |
14f6dad1 RH |
3194 | TCGv_ptr ptr; |
3195 | unsigned vsz = vec_full_reg_size(s); | |
3196 | unsigned desc = 0; | |
3197 | ||
3198 | if (!dc_isar_feature(aa64_sve2, s)) { | |
3199 | return false; | |
3200 | } | |
3201 | if (!sve_access_check(s)) { | |
3202 | return true; | |
3203 | } | |
3204 | ||
3205 | op0 = read_cpu_reg(s, a->rn, 1); | |
3206 | op1 = read_cpu_reg(s, a->rm, 1); | |
3207 | ||
4481bbf2 | 3208 | tmax = tcg_constant_i64(vsz); |
14f6dad1 RH |
3209 | diff = tcg_temp_new_i64(); |
3210 | ||
3211 | if (a->rw) { | |
3212 | /* WHILERW */ | |
3213 | /* diff = abs(op1 - op0), noting that op0/1 are unsigned. */ | |
3214 | t1 = tcg_temp_new_i64(); | |
3215 | tcg_gen_sub_i64(diff, op0, op1); | |
3216 | tcg_gen_sub_i64(t1, op1, op0); | |
3217 | tcg_gen_movcond_i64(TCG_COND_GEU, diff, op0, op1, diff, t1); | |
3218 | tcg_temp_free_i64(t1); | |
3219 | /* Round down to a multiple of ESIZE. */ | |
3220 | tcg_gen_andi_i64(diff, diff, -1 << a->esz); | |
3221 | /* If op1 == op0, diff == 0, and the condition is always true. */ | |
3222 | tcg_gen_movcond_i64(TCG_COND_EQ, diff, op0, op1, tmax, diff); | |
3223 | } else { | |
3224 | /* WHILEWR */ | |
3225 | tcg_gen_sub_i64(diff, op1, op0); | |
3226 | /* Round down to a multiple of ESIZE. */ | |
3227 | tcg_gen_andi_i64(diff, diff, -1 << a->esz); | |
3228 | /* If op0 >= op1, diff <= 0, the condition is always true. */ | |
3229 | tcg_gen_movcond_i64(TCG_COND_GEU, diff, op0, op1, tmax, diff); | |
3230 | } | |
3231 | ||
3232 | /* Bound to the maximum. */ | |
3233 | tcg_gen_umin_i64(diff, diff, tmax); | |
14f6dad1 RH |
3234 | |
3235 | /* Since we're bounded, pass as a 32-bit type. */ | |
3236 | t2 = tcg_temp_new_i32(); | |
3237 | tcg_gen_extrl_i64_i32(t2, diff); | |
3238 | tcg_temp_free_i64(diff); | |
3239 | ||
3240 | desc = FIELD_DP32(desc, PREDDESC, OPRSZ, vsz / 8); | |
3241 | desc = FIELD_DP32(desc, PREDDESC, ESZ, a->esz); | |
14f6dad1 RH |
3242 | |
3243 | ptr = tcg_temp_new_ptr(); | |
3244 | tcg_gen_addi_ptr(ptr, cpu_env, pred_full_reg_offset(s, a->rd)); | |
3245 | ||
4481bbf2 | 3246 | gen_helper_sve_whilel(t2, ptr, t2, tcg_constant_i32(desc)); |
14f6dad1 RH |
3247 | do_pred_flags(t2); |
3248 | ||
3249 | tcg_temp_free_ptr(ptr); | |
3250 | tcg_temp_free_i32(t2); | |
14f6dad1 RH |
3251 | return true; |
3252 | } | |
3253 | ||
ed491961 RH |
3254 | /* |
3255 | *** SVE Integer Wide Immediate - Unpredicated Group | |
3256 | */ | |
3257 | ||
3a7be554 | 3258 | static bool trans_FDUP(DisasContext *s, arg_FDUP *a) |
ed491961 RH |
3259 | { |
3260 | if (a->esz == 0) { | |
3261 | return false; | |
3262 | } | |
3263 | if (sve_access_check(s)) { | |
3264 | unsigned vsz = vec_full_reg_size(s); | |
3265 | int dofs = vec_full_reg_offset(s, a->rd); | |
3266 | uint64_t imm; | |
3267 | ||
3268 | /* Decode the VFP immediate. */ | |
3269 | imm = vfp_expand_imm(a->esz, a->imm); | |
8711e71f | 3270 | tcg_gen_gvec_dup_imm(a->esz, dofs, vsz, vsz, imm); |
ed491961 RH |
3271 | } |
3272 | return true; | |
3273 | } | |
3274 | ||
3a7be554 | 3275 | static bool trans_DUP_i(DisasContext *s, arg_DUP_i *a) |
ed491961 | 3276 | { |
ed491961 RH |
3277 | if (sve_access_check(s)) { |
3278 | unsigned vsz = vec_full_reg_size(s); | |
3279 | int dofs = vec_full_reg_offset(s, a->rd); | |
8711e71f | 3280 | tcg_gen_gvec_dup_imm(a->esz, dofs, vsz, vsz, a->imm); |
ed491961 RH |
3281 | } |
3282 | return true; | |
3283 | } | |
3284 | ||
48ca613d | 3285 | TRANS_FEAT(ADD_zzi, aa64_sve, gen_gvec_fn_arg_zzi, tcg_gen_gvec_addi, a) |
6e6a157d | 3286 | |
3a7be554 | 3287 | static bool trans_SUB_zzi(DisasContext *s, arg_rri_esz *a) |
6e6a157d RH |
3288 | { |
3289 | a->imm = -a->imm; | |
3a7be554 | 3290 | return trans_ADD_zzi(s, a); |
6e6a157d RH |
3291 | } |
3292 | ||
3a7be554 | 3293 | static bool trans_SUBR_zzi(DisasContext *s, arg_rri_esz *a) |
6e6a157d | 3294 | { |
53229a77 | 3295 | static const TCGOpcode vecop_list[] = { INDEX_op_sub_vec, 0 }; |
6e6a157d RH |
3296 | static const GVecGen2s op[4] = { |
3297 | { .fni8 = tcg_gen_vec_sub8_i64, | |
3298 | .fniv = tcg_gen_sub_vec, | |
3299 | .fno = gen_helper_sve_subri_b, | |
53229a77 | 3300 | .opt_opc = vecop_list, |
6e6a157d RH |
3301 | .vece = MO_8, |
3302 | .scalar_first = true }, | |
3303 | { .fni8 = tcg_gen_vec_sub16_i64, | |
3304 | .fniv = tcg_gen_sub_vec, | |
3305 | .fno = gen_helper_sve_subri_h, | |
53229a77 | 3306 | .opt_opc = vecop_list, |
6e6a157d RH |
3307 | .vece = MO_16, |
3308 | .scalar_first = true }, | |
3309 | { .fni4 = tcg_gen_sub_i32, | |
3310 | .fniv = tcg_gen_sub_vec, | |
3311 | .fno = gen_helper_sve_subri_s, | |
53229a77 | 3312 | .opt_opc = vecop_list, |
6e6a157d RH |
3313 | .vece = MO_32, |
3314 | .scalar_first = true }, | |
3315 | { .fni8 = tcg_gen_sub_i64, | |
3316 | .fniv = tcg_gen_sub_vec, | |
3317 | .fno = gen_helper_sve_subri_d, | |
53229a77 | 3318 | .opt_opc = vecop_list, |
6e6a157d RH |
3319 | .prefer_i64 = TCG_TARGET_REG_BITS == 64, |
3320 | .vece = MO_64, | |
3321 | .scalar_first = true } | |
3322 | }; | |
3323 | ||
6e6a157d RH |
3324 | if (sve_access_check(s)) { |
3325 | unsigned vsz = vec_full_reg_size(s); | |
6e6a157d RH |
3326 | tcg_gen_gvec_2s(vec_full_reg_offset(s, a->rd), |
3327 | vec_full_reg_offset(s, a->rn), | |
9fff3fcc | 3328 | vsz, vsz, tcg_constant_i64(a->imm), &op[a->esz]); |
6e6a157d RH |
3329 | } |
3330 | return true; | |
3331 | } | |
3332 | ||
fa4bd72c | 3333 | TRANS_FEAT(MUL_zzi, aa64_sve, gen_gvec_fn_arg_zzi, tcg_gen_gvec_muli, a) |
6e6a157d | 3334 | |
3a7be554 | 3335 | static bool do_zzi_sat(DisasContext *s, arg_rri_esz *a, bool u, bool d) |
6e6a157d | 3336 | { |
6e6a157d | 3337 | if (sve_access_check(s)) { |
138a1f7b RH |
3338 | do_sat_addsub_vec(s, a->esz, a->rd, a->rn, |
3339 | tcg_constant_i64(a->imm), u, d); | |
6e6a157d RH |
3340 | } |
3341 | return true; | |
3342 | } | |
3343 | ||
17b54d1c RH |
3344 | TRANS_FEAT(SQADD_zzi, aa64_sve, do_zzi_sat, a, false, false) |
3345 | TRANS_FEAT(UQADD_zzi, aa64_sve, do_zzi_sat, a, true, false) | |
3346 | TRANS_FEAT(SQSUB_zzi, aa64_sve, do_zzi_sat, a, false, true) | |
3347 | TRANS_FEAT(UQSUB_zzi, aa64_sve, do_zzi_sat, a, true, true) | |
6e6a157d RH |
3348 | |
3349 | static bool do_zzi_ool(DisasContext *s, arg_rri_esz *a, gen_helper_gvec_2i *fn) | |
3350 | { | |
3351 | if (sve_access_check(s)) { | |
3352 | unsigned vsz = vec_full_reg_size(s); | |
6e6a157d RH |
3353 | tcg_gen_gvec_2i_ool(vec_full_reg_offset(s, a->rd), |
3354 | vec_full_reg_offset(s, a->rn), | |
138a1f7b | 3355 | tcg_constant_i64(a->imm), vsz, vsz, 0, fn); |
6e6a157d RH |
3356 | } |
3357 | return true; | |
3358 | } | |
3359 | ||
3360 | #define DO_ZZI(NAME, name) \ | |
ef4a3958 | 3361 | static gen_helper_gvec_2i * const name##i_fns[4] = { \ |
6e6a157d RH |
3362 | gen_helper_sve_##name##i_b, gen_helper_sve_##name##i_h, \ |
3363 | gen_helper_sve_##name##i_s, gen_helper_sve_##name##i_d, \ | |
3364 | }; \ | |
ef4a3958 | 3365 | TRANS_FEAT(NAME##_zzi, aa64_sve, do_zzi_ool, a, name##i_fns[a->esz]) |
6e6a157d RH |
3366 | |
3367 | DO_ZZI(SMAX, smax) | |
3368 | DO_ZZI(UMAX, umax) | |
3369 | DO_ZZI(SMIN, smin) | |
3370 | DO_ZZI(UMIN, umin) | |
3371 | ||
3372 | #undef DO_ZZI | |
3373 | ||
5f425b92 RH |
3374 | static gen_helper_gvec_4 * const dot_fns[2][2] = { |
3375 | { gen_helper_gvec_sdot_b, gen_helper_gvec_sdot_h }, | |
3376 | { gen_helper_gvec_udot_b, gen_helper_gvec_udot_h } | |
3377 | }; | |
3378 | TRANS_FEAT(DOT_zzzz, aa64_sve, gen_gvec_ool_zzzz, | |
3379 | dot_fns[a->u][a->sz], a->rd, a->rn, a->rm, a->ra, 0) | |
d730ecaa | 3380 | |
814d4c52 RH |
3381 | /* |
3382 | * SVE Multiply - Indexed | |
3383 | */ | |
3384 | ||
f3500a25 RH |
3385 | TRANS_FEAT(SDOT_zzxw_s, aa64_sve, gen_gvec_ool_arg_zzxz, |
3386 | gen_helper_gvec_sdot_idx_b, a) | |
3387 | TRANS_FEAT(SDOT_zzxw_d, aa64_sve, gen_gvec_ool_arg_zzxz, | |
3388 | gen_helper_gvec_sdot_idx_h, a) | |
3389 | TRANS_FEAT(UDOT_zzxw_s, aa64_sve, gen_gvec_ool_arg_zzxz, | |
3390 | gen_helper_gvec_udot_idx_b, a) | |
3391 | TRANS_FEAT(UDOT_zzxw_d, aa64_sve, gen_gvec_ool_arg_zzxz, | |
3392 | gen_helper_gvec_udot_idx_h, a) | |
3393 | ||
3394 | TRANS_FEAT(SUDOT_zzxw_s, aa64_sve_i8mm, gen_gvec_ool_arg_zzxz, | |
3395 | gen_helper_gvec_sudot_idx_b, a) | |
3396 | TRANS_FEAT(USDOT_zzxw_s, aa64_sve_i8mm, gen_gvec_ool_arg_zzxz, | |
3397 | gen_helper_gvec_usdot_idx_b, a) | |
16fcfdc7 | 3398 | |
814d4c52 | 3399 | #define DO_SVE2_RRX(NAME, FUNC) \ |
af031f64 RH |
3400 | TRANS_FEAT(NAME, aa64_sve, gen_gvec_ool_zzz, FUNC, \ |
3401 | a->rd, a->rn, a->rm, a->index) | |
814d4c52 | 3402 | |
af031f64 RH |
3403 | DO_SVE2_RRX(MUL_zzx_h, gen_helper_gvec_mul_idx_h) |
3404 | DO_SVE2_RRX(MUL_zzx_s, gen_helper_gvec_mul_idx_s) | |
3405 | DO_SVE2_RRX(MUL_zzx_d, gen_helper_gvec_mul_idx_d) | |
814d4c52 | 3406 | |
af031f64 RH |
3407 | DO_SVE2_RRX(SQDMULH_zzx_h, gen_helper_sve2_sqdmulh_idx_h) |
3408 | DO_SVE2_RRX(SQDMULH_zzx_s, gen_helper_sve2_sqdmulh_idx_s) | |
3409 | DO_SVE2_RRX(SQDMULH_zzx_d, gen_helper_sve2_sqdmulh_idx_d) | |
1aee2d70 | 3410 | |
af031f64 RH |
3411 | DO_SVE2_RRX(SQRDMULH_zzx_h, gen_helper_sve2_sqrdmulh_idx_h) |
3412 | DO_SVE2_RRX(SQRDMULH_zzx_s, gen_helper_sve2_sqrdmulh_idx_s) | |
3413 | DO_SVE2_RRX(SQRDMULH_zzx_d, gen_helper_sve2_sqrdmulh_idx_d) | |
1aee2d70 | 3414 | |
814d4c52 RH |
3415 | #undef DO_SVE2_RRX |
3416 | ||
b95f5eeb | 3417 | #define DO_SVE2_RRX_TB(NAME, FUNC, TOP) \ |
af031f64 RH |
3418 | TRANS_FEAT(NAME, aa64_sve, gen_gvec_ool_zzz, FUNC, \ |
3419 | a->rd, a->rn, a->rm, (a->index << 1) | TOP) | |
3420 | ||
3421 | DO_SVE2_RRX_TB(SQDMULLB_zzx_s, gen_helper_sve2_sqdmull_idx_s, false) | |
3422 | DO_SVE2_RRX_TB(SQDMULLB_zzx_d, gen_helper_sve2_sqdmull_idx_d, false) | |
3423 | DO_SVE2_RRX_TB(SQDMULLT_zzx_s, gen_helper_sve2_sqdmull_idx_s, true) | |
3424 | DO_SVE2_RRX_TB(SQDMULLT_zzx_d, gen_helper_sve2_sqdmull_idx_d, true) | |
3425 | ||
3426 | DO_SVE2_RRX_TB(SMULLB_zzx_s, gen_helper_sve2_smull_idx_s, false) | |
3427 | DO_SVE2_RRX_TB(SMULLB_zzx_d, gen_helper_sve2_smull_idx_d, false) | |
3428 | DO_SVE2_RRX_TB(SMULLT_zzx_s, gen_helper_sve2_smull_idx_s, true) | |
3429 | DO_SVE2_RRX_TB(SMULLT_zzx_d, gen_helper_sve2_smull_idx_d, true) | |
3430 | ||
3431 | DO_SVE2_RRX_TB(UMULLB_zzx_s, gen_helper_sve2_umull_idx_s, false) | |
3432 | DO_SVE2_RRX_TB(UMULLB_zzx_d, gen_helper_sve2_umull_idx_d, false) | |
3433 | DO_SVE2_RRX_TB(UMULLT_zzx_s, gen_helper_sve2_umull_idx_s, true) | |
3434 | DO_SVE2_RRX_TB(UMULLT_zzx_d, gen_helper_sve2_umull_idx_d, true) | |
d3949c4c | 3435 | |
b95f5eeb RH |
3436 | #undef DO_SVE2_RRX_TB |
3437 | ||
8a02aac7 | 3438 | #define DO_SVE2_RRXR(NAME, FUNC) \ |
8681eb76 | 3439 | TRANS_FEAT(NAME, aa64_sve2, gen_gvec_ool_arg_zzxz, FUNC, a) |
8a02aac7 | 3440 | |
8681eb76 RH |
3441 | DO_SVE2_RRXR(MLA_zzxz_h, gen_helper_gvec_mla_idx_h) |
3442 | DO_SVE2_RRXR(MLA_zzxz_s, gen_helper_gvec_mla_idx_s) | |
3443 | DO_SVE2_RRXR(MLA_zzxz_d, gen_helper_gvec_mla_idx_d) | |
8a02aac7 | 3444 | |
8681eb76 RH |
3445 | DO_SVE2_RRXR(MLS_zzxz_h, gen_helper_gvec_mls_idx_h) |
3446 | DO_SVE2_RRXR(MLS_zzxz_s, gen_helper_gvec_mls_idx_s) | |
3447 | DO_SVE2_RRXR(MLS_zzxz_d, gen_helper_gvec_mls_idx_d) | |
8a02aac7 | 3448 | |
8681eb76 RH |
3449 | DO_SVE2_RRXR(SQRDMLAH_zzxz_h, gen_helper_sve2_sqrdmlah_idx_h) |
3450 | DO_SVE2_RRXR(SQRDMLAH_zzxz_s, gen_helper_sve2_sqrdmlah_idx_s) | |
3451 | DO_SVE2_RRXR(SQRDMLAH_zzxz_d, gen_helper_sve2_sqrdmlah_idx_d) | |
75d6d5fc | 3452 | |
8681eb76 RH |
3453 | DO_SVE2_RRXR(SQRDMLSH_zzxz_h, gen_helper_sve2_sqrdmlsh_idx_h) |
3454 | DO_SVE2_RRXR(SQRDMLSH_zzxz_s, gen_helper_sve2_sqrdmlsh_idx_s) | |
3455 | DO_SVE2_RRXR(SQRDMLSH_zzxz_d, gen_helper_sve2_sqrdmlsh_idx_d) | |
75d6d5fc | 3456 | |
8a02aac7 RH |
3457 | #undef DO_SVE2_RRXR |
3458 | ||
c5c455d7 | 3459 | #define DO_SVE2_RRXR_TB(NAME, FUNC, TOP) \ |
8681eb76 RH |
3460 | TRANS_FEAT(NAME, aa64_sve2, gen_gvec_ool_zzzz, FUNC, \ |
3461 | a->rd, a->rn, a->rm, a->ra, (a->index << 1) | TOP) | |
3462 | ||
3463 | DO_SVE2_RRXR_TB(SQDMLALB_zzxw_s, gen_helper_sve2_sqdmlal_idx_s, false) | |
3464 | DO_SVE2_RRXR_TB(SQDMLALB_zzxw_d, gen_helper_sve2_sqdmlal_idx_d, false) | |
3465 | DO_SVE2_RRXR_TB(SQDMLALT_zzxw_s, gen_helper_sve2_sqdmlal_idx_s, true) | |
3466 | DO_SVE2_RRXR_TB(SQDMLALT_zzxw_d, gen_helper_sve2_sqdmlal_idx_d, true) | |
3467 | ||
3468 | DO_SVE2_RRXR_TB(SQDMLSLB_zzxw_s, gen_helper_sve2_sqdmlsl_idx_s, false) | |
3469 | DO_SVE2_RRXR_TB(SQDMLSLB_zzxw_d, gen_helper_sve2_sqdmlsl_idx_d, false) | |
3470 | DO_SVE2_RRXR_TB(SQDMLSLT_zzxw_s, gen_helper_sve2_sqdmlsl_idx_s, true) | |
3471 | DO_SVE2_RRXR_TB(SQDMLSLT_zzxw_d, gen_helper_sve2_sqdmlsl_idx_d, true) | |
3472 | ||
3473 | DO_SVE2_RRXR_TB(SMLALB_zzxw_s, gen_helper_sve2_smlal_idx_s, false) | |
3474 | DO_SVE2_RRXR_TB(SMLALB_zzxw_d, gen_helper_sve2_smlal_idx_d, false) | |
3475 | DO_SVE2_RRXR_TB(SMLALT_zzxw_s, gen_helper_sve2_smlal_idx_s, true) | |
3476 | DO_SVE2_RRXR_TB(SMLALT_zzxw_d, gen_helper_sve2_smlal_idx_d, true) | |
3477 | ||
3478 | DO_SVE2_RRXR_TB(UMLALB_zzxw_s, gen_helper_sve2_umlal_idx_s, false) | |
3479 | DO_SVE2_RRXR_TB(UMLALB_zzxw_d, gen_helper_sve2_umlal_idx_d, false) | |
3480 | DO_SVE2_RRXR_TB(UMLALT_zzxw_s, gen_helper_sve2_umlal_idx_s, true) | |
3481 | DO_SVE2_RRXR_TB(UMLALT_zzxw_d, gen_helper_sve2_umlal_idx_d, true) | |
3482 | ||
3483 | DO_SVE2_RRXR_TB(SMLSLB_zzxw_s, gen_helper_sve2_smlsl_idx_s, false) | |
3484 | DO_SVE2_RRXR_TB(SMLSLB_zzxw_d, gen_helper_sve2_smlsl_idx_d, false) | |
3485 | DO_SVE2_RRXR_TB(SMLSLT_zzxw_s, gen_helper_sve2_smlsl_idx_s, true) | |
3486 | DO_SVE2_RRXR_TB(SMLSLT_zzxw_d, gen_helper_sve2_smlsl_idx_d, true) | |
3487 | ||
3488 | DO_SVE2_RRXR_TB(UMLSLB_zzxw_s, gen_helper_sve2_umlsl_idx_s, false) | |
3489 | DO_SVE2_RRXR_TB(UMLSLB_zzxw_d, gen_helper_sve2_umlsl_idx_d, false) | |
3490 | DO_SVE2_RRXR_TB(UMLSLT_zzxw_s, gen_helper_sve2_umlsl_idx_s, true) | |
3491 | DO_SVE2_RRXR_TB(UMLSLT_zzxw_d, gen_helper_sve2_umlsl_idx_d, true) | |
c5c455d7 RH |
3492 | |
3493 | #undef DO_SVE2_RRXR_TB | |
3494 | ||
3b787ed8 | 3495 | #define DO_SVE2_RRXR_ROT(NAME, FUNC) \ |
8681eb76 RH |
3496 | TRANS_FEAT(NAME, aa64_sve2, gen_gvec_ool_zzzz, FUNC, \ |
3497 | a->rd, a->rn, a->rm, a->ra, (a->index << 2) | a->rot) | |
3b787ed8 RH |
3498 | |
3499 | DO_SVE2_RRXR_ROT(CMLA_zzxz_h, gen_helper_sve2_cmla_idx_h) | |
3500 | DO_SVE2_RRXR_ROT(CMLA_zzxz_s, gen_helper_sve2_cmla_idx_s) | |
3501 | ||
3502 | DO_SVE2_RRXR_ROT(SQRDCMLAH_zzxz_h, gen_helper_sve2_sqrdcmlah_idx_h) | |
3503 | DO_SVE2_RRXR_ROT(SQRDCMLAH_zzxz_s, gen_helper_sve2_sqrdcmlah_idx_s) | |
3504 | ||
21068f39 RH |
3505 | DO_SVE2_RRXR_ROT(CDOT_zzxw_s, gen_helper_sve2_cdot_idx_s) |
3506 | DO_SVE2_RRXR_ROT(CDOT_zzxw_d, gen_helper_sve2_cdot_idx_d) | |
3507 | ||
3b787ed8 RH |
3508 | #undef DO_SVE2_RRXR_ROT |
3509 | ||
ca40a6e6 RH |
3510 | /* |
3511 | *** SVE Floating Point Multiply-Add Indexed Group | |
3512 | */ | |
3513 | ||
0a82d963 | 3514 | static bool do_FMLA_zzxz(DisasContext *s, arg_rrxr_esz *a, bool sub) |
ca40a6e6 | 3515 | { |
41bf9b67 RH |
3516 | static gen_helper_gvec_4_ptr * const fns[4] = { |
3517 | NULL, | |
ca40a6e6 RH |
3518 | gen_helper_gvec_fmla_idx_h, |
3519 | gen_helper_gvec_fmla_idx_s, | |
3520 | gen_helper_gvec_fmla_idx_d, | |
3521 | }; | |
41bf9b67 RH |
3522 | return gen_gvec_fpst_zzzz(s, fns[a->esz], a->rd, a->rn, a->rm, a->ra, |
3523 | (a->index << 1) | sub, | |
3524 | a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR); | |
ca40a6e6 RH |
3525 | } |
3526 | ||
0a82d963 RH |
3527 | static bool trans_FMLA_zzxz(DisasContext *s, arg_FMLA_zzxz *a) |
3528 | { | |
3529 | return do_FMLA_zzxz(s, a, false); | |
3530 | } | |
3531 | ||
3532 | static bool trans_FMLS_zzxz(DisasContext *s, arg_FMLA_zzxz *a) | |
3533 | { | |
3534 | return do_FMLA_zzxz(s, a, true); | |
3535 | } | |
3536 | ||
ca40a6e6 RH |
3537 | /* |
3538 | *** SVE Floating Point Multiply Indexed Group | |
3539 | */ | |
3540 | ||
3a7be554 | 3541 | static bool trans_FMUL_zzx(DisasContext *s, arg_FMUL_zzx *a) |
ca40a6e6 RH |
3542 | { |
3543 | static gen_helper_gvec_3_ptr * const fns[3] = { | |
3544 | gen_helper_gvec_fmul_idx_h, | |
3545 | gen_helper_gvec_fmul_idx_s, | |
3546 | gen_helper_gvec_fmul_idx_d, | |
3547 | }; | |
3548 | ||
3549 | if (sve_access_check(s)) { | |
3550 | unsigned vsz = vec_full_reg_size(s); | |
cdfb22bb | 3551 | TCGv_ptr status = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR); |
ca40a6e6 RH |
3552 | tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, a->rd), |
3553 | vec_full_reg_offset(s, a->rn), | |
3554 | vec_full_reg_offset(s, a->rm), | |
3555 | status, vsz, vsz, a->index, fns[a->esz - 1]); | |
3556 | tcg_temp_free_ptr(status); | |
3557 | } | |
3558 | return true; | |
3559 | } | |
3560 | ||
23fbe79f RH |
3561 | /* |
3562 | *** SVE Floating Point Fast Reduction Group | |
3563 | */ | |
3564 | ||
3565 | typedef void gen_helper_fp_reduce(TCGv_i64, TCGv_ptr, TCGv_ptr, | |
3566 | TCGv_ptr, TCGv_i32); | |
3567 | ||
3568 | static void do_reduce(DisasContext *s, arg_rpr_esz *a, | |
3569 | gen_helper_fp_reduce *fn) | |
3570 | { | |
3571 | unsigned vsz = vec_full_reg_size(s); | |
3572 | unsigned p2vsz = pow2ceil(vsz); | |
c6a59b55 | 3573 | TCGv_i32 t_desc = tcg_constant_i32(simd_desc(vsz, vsz, p2vsz)); |
23fbe79f RH |
3574 | TCGv_ptr t_zn, t_pg, status; |
3575 | TCGv_i64 temp; | |
3576 | ||
3577 | temp = tcg_temp_new_i64(); | |
3578 | t_zn = tcg_temp_new_ptr(); | |
3579 | t_pg = tcg_temp_new_ptr(); | |
3580 | ||
3581 | tcg_gen_addi_ptr(t_zn, cpu_env, vec_full_reg_offset(s, a->rn)); | |
3582 | tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, a->pg)); | |
cdfb22bb | 3583 | status = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR); |
23fbe79f RH |
3584 | |
3585 | fn(temp, t_zn, t_pg, status, t_desc); | |
3586 | tcg_temp_free_ptr(t_zn); | |
3587 | tcg_temp_free_ptr(t_pg); | |
3588 | tcg_temp_free_ptr(status); | |
23fbe79f RH |
3589 | |
3590 | write_fp_dreg(s, a->rd, temp); | |
3591 | tcg_temp_free_i64(temp); | |
3592 | } | |
3593 | ||
3594 | #define DO_VPZ(NAME, name) \ | |
3a7be554 | 3595 | static bool trans_##NAME(DisasContext *s, arg_rpr_esz *a) \ |
23fbe79f RH |
3596 | { \ |
3597 | static gen_helper_fp_reduce * const fns[3] = { \ | |
3598 | gen_helper_sve_##name##_h, \ | |
3599 | gen_helper_sve_##name##_s, \ | |
3600 | gen_helper_sve_##name##_d, \ | |
3601 | }; \ | |
3602 | if (a->esz == 0) { \ | |
3603 | return false; \ | |
3604 | } \ | |
3605 | if (sve_access_check(s)) { \ | |
3606 | do_reduce(s, a, fns[a->esz - 1]); \ | |
3607 | } \ | |
3608 | return true; \ | |
3609 | } | |
3610 | ||
3611 | DO_VPZ(FADDV, faddv) | |
3612 | DO_VPZ(FMINNMV, fminnmv) | |
3613 | DO_VPZ(FMAXNMV, fmaxnmv) | |
3614 | DO_VPZ(FMINV, fminv) | |
3615 | DO_VPZ(FMAXV, fmaxv) | |
3616 | ||
3887c038 RH |
3617 | /* |
3618 | *** SVE Floating Point Unary Operations - Unpredicated Group | |
3619 | */ | |
3620 | ||
3621 | static void do_zz_fp(DisasContext *s, arg_rr_esz *a, gen_helper_gvec_2_ptr *fn) | |
3622 | { | |
3623 | unsigned vsz = vec_full_reg_size(s); | |
cdfb22bb | 3624 | TCGv_ptr status = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR); |
3887c038 RH |
3625 | |
3626 | tcg_gen_gvec_2_ptr(vec_full_reg_offset(s, a->rd), | |
3627 | vec_full_reg_offset(s, a->rn), | |
3628 | status, vsz, vsz, 0, fn); | |
3629 | tcg_temp_free_ptr(status); | |
3630 | } | |
3631 | ||
3a7be554 | 3632 | static bool trans_FRECPE(DisasContext *s, arg_rr_esz *a) |
3887c038 RH |
3633 | { |
3634 | static gen_helper_gvec_2_ptr * const fns[3] = { | |
3635 | gen_helper_gvec_frecpe_h, | |
3636 | gen_helper_gvec_frecpe_s, | |
3637 | gen_helper_gvec_frecpe_d, | |
3638 | }; | |
3639 | if (a->esz == 0) { | |
3640 | return false; | |
3641 | } | |
3642 | if (sve_access_check(s)) { | |
3643 | do_zz_fp(s, a, fns[a->esz - 1]); | |
3644 | } | |
3645 | return true; | |
3646 | } | |
3647 | ||
3a7be554 | 3648 | static bool trans_FRSQRTE(DisasContext *s, arg_rr_esz *a) |
3887c038 RH |
3649 | { |
3650 | static gen_helper_gvec_2_ptr * const fns[3] = { | |
3651 | gen_helper_gvec_frsqrte_h, | |
3652 | gen_helper_gvec_frsqrte_s, | |
3653 | gen_helper_gvec_frsqrte_d, | |
3654 | }; | |
3655 | if (a->esz == 0) { | |
3656 | return false; | |
3657 | } | |
3658 | if (sve_access_check(s)) { | |
3659 | do_zz_fp(s, a, fns[a->esz - 1]); | |
3660 | } | |
3661 | return true; | |
3662 | } | |
3663 | ||
4d2e2a03 RH |
3664 | /* |
3665 | *** SVE Floating Point Compare with Zero Group | |
3666 | */ | |
3667 | ||
3668 | static void do_ppz_fp(DisasContext *s, arg_rpr_esz *a, | |
3669 | gen_helper_gvec_3_ptr *fn) | |
3670 | { | |
3671 | unsigned vsz = vec_full_reg_size(s); | |
cdfb22bb | 3672 | TCGv_ptr status = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR); |
4d2e2a03 RH |
3673 | |
3674 | tcg_gen_gvec_3_ptr(pred_full_reg_offset(s, a->rd), | |
3675 | vec_full_reg_offset(s, a->rn), | |
3676 | pred_full_reg_offset(s, a->pg), | |
3677 | status, vsz, vsz, 0, fn); | |
3678 | tcg_temp_free_ptr(status); | |
3679 | } | |
3680 | ||
3681 | #define DO_PPZ(NAME, name) \ | |
3a7be554 | 3682 | static bool trans_##NAME(DisasContext *s, arg_rpr_esz *a) \ |
4d2e2a03 RH |
3683 | { \ |
3684 | static gen_helper_gvec_3_ptr * const fns[3] = { \ | |
3685 | gen_helper_sve_##name##_h, \ | |
3686 | gen_helper_sve_##name##_s, \ | |
3687 | gen_helper_sve_##name##_d, \ | |
3688 | }; \ | |
3689 | if (a->esz == 0) { \ | |
3690 | return false; \ | |
3691 | } \ | |
3692 | if (sve_access_check(s)) { \ | |
3693 | do_ppz_fp(s, a, fns[a->esz - 1]); \ | |
3694 | } \ | |
3695 | return true; \ | |
3696 | } | |
3697 | ||
3698 | DO_PPZ(FCMGE_ppz0, fcmge0) | |
3699 | DO_PPZ(FCMGT_ppz0, fcmgt0) | |
3700 | DO_PPZ(FCMLE_ppz0, fcmle0) | |
3701 | DO_PPZ(FCMLT_ppz0, fcmlt0) | |
3702 | DO_PPZ(FCMEQ_ppz0, fcmeq0) | |
3703 | DO_PPZ(FCMNE_ppz0, fcmne0) | |
3704 | ||
3705 | #undef DO_PPZ | |
3706 | ||
67fcd9ad RH |
3707 | /* |
3708 | *** SVE floating-point trig multiply-add coefficient | |
3709 | */ | |
3710 | ||
3a7be554 | 3711 | static bool trans_FTMAD(DisasContext *s, arg_FTMAD *a) |
67fcd9ad RH |
3712 | { |
3713 | static gen_helper_gvec_3_ptr * const fns[3] = { | |
3714 | gen_helper_sve_ftmad_h, | |
3715 | gen_helper_sve_ftmad_s, | |
3716 | gen_helper_sve_ftmad_d, | |
3717 | }; | |
3718 | ||
3719 | if (a->esz == 0) { | |
3720 | return false; | |
3721 | } | |
3722 | if (sve_access_check(s)) { | |
3723 | unsigned vsz = vec_full_reg_size(s); | |
cdfb22bb | 3724 | TCGv_ptr status = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR); |
67fcd9ad RH |
3725 | tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, a->rd), |
3726 | vec_full_reg_offset(s, a->rn), | |
3727 | vec_full_reg_offset(s, a->rm), | |
3728 | status, vsz, vsz, a->imm, fns[a->esz - 1]); | |
3729 | tcg_temp_free_ptr(status); | |
3730 | } | |
3731 | return true; | |
3732 | } | |
3733 | ||
7f9ddf64 RH |
3734 | /* |
3735 | *** SVE Floating Point Accumulating Reduction Group | |
3736 | */ | |
3737 | ||
3a7be554 | 3738 | static bool trans_FADDA(DisasContext *s, arg_rprr_esz *a) |
7f9ddf64 RH |
3739 | { |
3740 | typedef void fadda_fn(TCGv_i64, TCGv_i64, TCGv_ptr, | |
3741 | TCGv_ptr, TCGv_ptr, TCGv_i32); | |
3742 | static fadda_fn * const fns[3] = { | |
3743 | gen_helper_sve_fadda_h, | |
3744 | gen_helper_sve_fadda_s, | |
3745 | gen_helper_sve_fadda_d, | |
3746 | }; | |
3747 | unsigned vsz = vec_full_reg_size(s); | |
3748 | TCGv_ptr t_rm, t_pg, t_fpst; | |
3749 | TCGv_i64 t_val; | |
3750 | TCGv_i32 t_desc; | |
3751 | ||
3752 | if (a->esz == 0) { | |
3753 | return false; | |
3754 | } | |
3755 | if (!sve_access_check(s)) { | |
3756 | return true; | |
3757 | } | |
3758 | ||
3759 | t_val = load_esz(cpu_env, vec_reg_offset(s, a->rn, 0, a->esz), a->esz); | |
3760 | t_rm = tcg_temp_new_ptr(); | |
3761 | t_pg = tcg_temp_new_ptr(); | |
3762 | tcg_gen_addi_ptr(t_rm, cpu_env, vec_full_reg_offset(s, a->rm)); | |
3763 | tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, a->pg)); | |
cdfb22bb | 3764 | t_fpst = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR); |
c6a59b55 | 3765 | t_desc = tcg_constant_i32(simd_desc(vsz, vsz, 0)); |
7f9ddf64 RH |
3766 | |
3767 | fns[a->esz - 1](t_val, t_val, t_rm, t_pg, t_fpst, t_desc); | |
3768 | ||
7f9ddf64 RH |
3769 | tcg_temp_free_ptr(t_fpst); |
3770 | tcg_temp_free_ptr(t_pg); | |
3771 | tcg_temp_free_ptr(t_rm); | |
3772 | ||
3773 | write_fp_dreg(s, a->rd, t_val); | |
3774 | tcg_temp_free_i64(t_val); | |
3775 | return true; | |
3776 | } | |
3777 | ||
29b80469 RH |
3778 | /* |
3779 | *** SVE Floating Point Arithmetic - Unpredicated Group | |
3780 | */ | |
3781 | ||
3782 | static bool do_zzz_fp(DisasContext *s, arg_rrr_esz *a, | |
3783 | gen_helper_gvec_3_ptr *fn) | |
3784 | { | |
3785 | if (fn == NULL) { | |
3786 | return false; | |
3787 | } | |
3788 | if (sve_access_check(s)) { | |
3789 | unsigned vsz = vec_full_reg_size(s); | |
cdfb22bb | 3790 | TCGv_ptr status = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR); |
29b80469 RH |
3791 | tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, a->rd), |
3792 | vec_full_reg_offset(s, a->rn), | |
3793 | vec_full_reg_offset(s, a->rm), | |
3794 | status, vsz, vsz, 0, fn); | |
3795 | tcg_temp_free_ptr(status); | |
3796 | } | |
3797 | return true; | |
3798 | } | |
3799 | ||
3800 | ||
3801 | #define DO_FP3(NAME, name) \ | |
3a7be554 | 3802 | static bool trans_##NAME(DisasContext *s, arg_rrr_esz *a) \ |
29b80469 RH |
3803 | { \ |
3804 | static gen_helper_gvec_3_ptr * const fns[4] = { \ | |
3805 | NULL, gen_helper_gvec_##name##_h, \ | |
3806 | gen_helper_gvec_##name##_s, gen_helper_gvec_##name##_d \ | |
3807 | }; \ | |
3808 | return do_zzz_fp(s, a, fns[a->esz]); \ | |
3809 | } | |
3810 | ||
3811 | DO_FP3(FADD_zzz, fadd) | |
3812 | DO_FP3(FSUB_zzz, fsub) | |
3813 | DO_FP3(FMUL_zzz, fmul) | |
3814 | DO_FP3(FTSMUL, ftsmul) | |
3815 | DO_FP3(FRECPS, recps) | |
3816 | DO_FP3(FRSQRTS, rsqrts) | |
3817 | ||
3818 | #undef DO_FP3 | |
3819 | ||
ec3b87c2 RH |
3820 | /* |
3821 | *** SVE Floating Point Arithmetic - Predicated Group | |
3822 | */ | |
3823 | ||
3824 | static bool do_zpzz_fp(DisasContext *s, arg_rprr_esz *a, | |
3825 | gen_helper_gvec_4_ptr *fn) | |
3826 | { | |
3827 | if (fn == NULL) { | |
3828 | return false; | |
3829 | } | |
3830 | if (sve_access_check(s)) { | |
3831 | unsigned vsz = vec_full_reg_size(s); | |
cdfb22bb | 3832 | TCGv_ptr status = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR); |
ec3b87c2 RH |
3833 | tcg_gen_gvec_4_ptr(vec_full_reg_offset(s, a->rd), |
3834 | vec_full_reg_offset(s, a->rn), | |
3835 | vec_full_reg_offset(s, a->rm), | |
3836 | pred_full_reg_offset(s, a->pg), | |
3837 | status, vsz, vsz, 0, fn); | |
3838 | tcg_temp_free_ptr(status); | |
3839 | } | |
3840 | return true; | |
3841 | } | |
3842 | ||
3843 | #define DO_FP3(NAME, name) \ | |
3a7be554 | 3844 | static bool trans_##NAME(DisasContext *s, arg_rprr_esz *a) \ |
ec3b87c2 RH |
3845 | { \ |
3846 | static gen_helper_gvec_4_ptr * const fns[4] = { \ | |
3847 | NULL, gen_helper_sve_##name##_h, \ | |
3848 | gen_helper_sve_##name##_s, gen_helper_sve_##name##_d \ | |
3849 | }; \ | |
3850 | return do_zpzz_fp(s, a, fns[a->esz]); \ | |
3851 | } | |
3852 | ||
3853 | DO_FP3(FADD_zpzz, fadd) | |
3854 | DO_FP3(FSUB_zpzz, fsub) | |
3855 | DO_FP3(FMUL_zpzz, fmul) | |
3856 | DO_FP3(FMIN_zpzz, fmin) | |
3857 | DO_FP3(FMAX_zpzz, fmax) | |
3858 | DO_FP3(FMINNM_zpzz, fminnum) | |
3859 | DO_FP3(FMAXNM_zpzz, fmaxnum) | |
3860 | DO_FP3(FABD, fabd) | |
3861 | DO_FP3(FSCALE, fscalbn) | |
3862 | DO_FP3(FDIV, fdiv) | |
3863 | DO_FP3(FMULX, fmulx) | |
3864 | ||
3865 | #undef DO_FP3 | |
8092c6a3 | 3866 | |
cc48affe RH |
3867 | typedef void gen_helper_sve_fp2scalar(TCGv_ptr, TCGv_ptr, TCGv_ptr, |
3868 | TCGv_i64, TCGv_ptr, TCGv_i32); | |
3869 | ||
3870 | static void do_fp_scalar(DisasContext *s, int zd, int zn, int pg, bool is_fp16, | |
3871 | TCGv_i64 scalar, gen_helper_sve_fp2scalar *fn) | |
3872 | { | |
3873 | unsigned vsz = vec_full_reg_size(s); | |
3874 | TCGv_ptr t_zd, t_zn, t_pg, status; | |
3875 | TCGv_i32 desc; | |
3876 | ||
3877 | t_zd = tcg_temp_new_ptr(); | |
3878 | t_zn = tcg_temp_new_ptr(); | |
3879 | t_pg = tcg_temp_new_ptr(); | |
3880 | tcg_gen_addi_ptr(t_zd, cpu_env, vec_full_reg_offset(s, zd)); | |
3881 | tcg_gen_addi_ptr(t_zn, cpu_env, vec_full_reg_offset(s, zn)); | |
3882 | tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, pg)); | |
3883 | ||
cdfb22bb | 3884 | status = fpstatus_ptr(is_fp16 ? FPST_FPCR_F16 : FPST_FPCR); |
c6a59b55 | 3885 | desc = tcg_constant_i32(simd_desc(vsz, vsz, 0)); |
cc48affe RH |
3886 | fn(t_zd, t_zn, t_pg, scalar, status, desc); |
3887 | ||
cc48affe RH |
3888 | tcg_temp_free_ptr(status); |
3889 | tcg_temp_free_ptr(t_pg); | |
3890 | tcg_temp_free_ptr(t_zn); | |
3891 | tcg_temp_free_ptr(t_zd); | |
3892 | } | |
3893 | ||
3894 | static void do_fp_imm(DisasContext *s, arg_rpri_esz *a, uint64_t imm, | |
3895 | gen_helper_sve_fp2scalar *fn) | |
3896 | { | |
138a1f7b RH |
3897 | do_fp_scalar(s, a->rd, a->rn, a->pg, a->esz == MO_16, |
3898 | tcg_constant_i64(imm), fn); | |
cc48affe RH |
3899 | } |
3900 | ||
3901 | #define DO_FP_IMM(NAME, name, const0, const1) \ | |
3a7be554 | 3902 | static bool trans_##NAME##_zpzi(DisasContext *s, arg_rpri_esz *a) \ |
cc48affe RH |
3903 | { \ |
3904 | static gen_helper_sve_fp2scalar * const fns[3] = { \ | |
3905 | gen_helper_sve_##name##_h, \ | |
3906 | gen_helper_sve_##name##_s, \ | |
3907 | gen_helper_sve_##name##_d \ | |
3908 | }; \ | |
3909 | static uint64_t const val[3][2] = { \ | |
3910 | { float16_##const0, float16_##const1 }, \ | |
3911 | { float32_##const0, float32_##const1 }, \ | |
3912 | { float64_##const0, float64_##const1 }, \ | |
3913 | }; \ | |
3914 | if (a->esz == 0) { \ | |
3915 | return false; \ | |
3916 | } \ | |
3917 | if (sve_access_check(s)) { \ | |
3918 | do_fp_imm(s, a, val[a->esz - 1][a->imm], fns[a->esz - 1]); \ | |
3919 | } \ | |
3920 | return true; \ | |
3921 | } | |
3922 | ||
cc48affe RH |
3923 | DO_FP_IMM(FADD, fadds, half, one) |
3924 | DO_FP_IMM(FSUB, fsubs, half, one) | |
3925 | DO_FP_IMM(FMUL, fmuls, half, two) | |
3926 | DO_FP_IMM(FSUBR, fsubrs, half, one) | |
3927 | DO_FP_IMM(FMAXNM, fmaxnms, zero, one) | |
3928 | DO_FP_IMM(FMINNM, fminnms, zero, one) | |
3929 | DO_FP_IMM(FMAX, fmaxs, zero, one) | |
3930 | DO_FP_IMM(FMIN, fmins, zero, one) | |
3931 | ||
3932 | #undef DO_FP_IMM | |
3933 | ||
abfdefd5 RH |
3934 | static bool do_fp_cmp(DisasContext *s, arg_rprr_esz *a, |
3935 | gen_helper_gvec_4_ptr *fn) | |
3936 | { | |
3937 | if (fn == NULL) { | |
3938 | return false; | |
3939 | } | |
3940 | if (sve_access_check(s)) { | |
3941 | unsigned vsz = vec_full_reg_size(s); | |
cdfb22bb | 3942 | TCGv_ptr status = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR); |
abfdefd5 RH |
3943 | tcg_gen_gvec_4_ptr(pred_full_reg_offset(s, a->rd), |
3944 | vec_full_reg_offset(s, a->rn), | |
3945 | vec_full_reg_offset(s, a->rm), | |
3946 | pred_full_reg_offset(s, a->pg), | |
3947 | status, vsz, vsz, 0, fn); | |
3948 | tcg_temp_free_ptr(status); | |
3949 | } | |
3950 | return true; | |
3951 | } | |
3952 | ||
3953 | #define DO_FPCMP(NAME, name) \ | |
3a7be554 | 3954 | static bool trans_##NAME##_ppzz(DisasContext *s, arg_rprr_esz *a) \ |
abfdefd5 RH |
3955 | { \ |
3956 | static gen_helper_gvec_4_ptr * const fns[4] = { \ | |
3957 | NULL, gen_helper_sve_##name##_h, \ | |
3958 | gen_helper_sve_##name##_s, gen_helper_sve_##name##_d \ | |
3959 | }; \ | |
3960 | return do_fp_cmp(s, a, fns[a->esz]); \ | |
3961 | } | |
3962 | ||
3963 | DO_FPCMP(FCMGE, fcmge) | |
3964 | DO_FPCMP(FCMGT, fcmgt) | |
3965 | DO_FPCMP(FCMEQ, fcmeq) | |
3966 | DO_FPCMP(FCMNE, fcmne) | |
3967 | DO_FPCMP(FCMUO, fcmuo) | |
3968 | DO_FPCMP(FACGE, facge) | |
3969 | DO_FPCMP(FACGT, facgt) | |
3970 | ||
3971 | #undef DO_FPCMP | |
3972 | ||
3a7be554 | 3973 | static bool trans_FCADD(DisasContext *s, arg_FCADD *a) |
76a9d9cd RH |
3974 | { |
3975 | static gen_helper_gvec_4_ptr * const fns[3] = { | |
3976 | gen_helper_sve_fcadd_h, | |
3977 | gen_helper_sve_fcadd_s, | |
3978 | gen_helper_sve_fcadd_d | |
3979 | }; | |
3980 | ||
3981 | if (a->esz == 0) { | |
3982 | return false; | |
3983 | } | |
3984 | if (sve_access_check(s)) { | |
3985 | unsigned vsz = vec_full_reg_size(s); | |
cdfb22bb | 3986 | TCGv_ptr status = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR); |
76a9d9cd RH |
3987 | tcg_gen_gvec_4_ptr(vec_full_reg_offset(s, a->rd), |
3988 | vec_full_reg_offset(s, a->rn), | |
3989 | vec_full_reg_offset(s, a->rm), | |
3990 | pred_full_reg_offset(s, a->pg), | |
3991 | status, vsz, vsz, a->rot, fns[a->esz - 1]); | |
3992 | tcg_temp_free_ptr(status); | |
3993 | } | |
3994 | return true; | |
3995 | } | |
3996 | ||
08975da9 RH |
3997 | static bool do_fmla(DisasContext *s, arg_rprrr_esz *a, |
3998 | gen_helper_gvec_5_ptr *fn) | |
6ceabaad | 3999 | { |
08975da9 | 4000 | if (a->esz == 0) { |
6ceabaad RH |
4001 | return false; |
4002 | } | |
08975da9 RH |
4003 | if (sve_access_check(s)) { |
4004 | unsigned vsz = vec_full_reg_size(s); | |
cdfb22bb | 4005 | TCGv_ptr status = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR); |
08975da9 RH |
4006 | tcg_gen_gvec_5_ptr(vec_full_reg_offset(s, a->rd), |
4007 | vec_full_reg_offset(s, a->rn), | |
4008 | vec_full_reg_offset(s, a->rm), | |
4009 | vec_full_reg_offset(s, a->ra), | |
4010 | pred_full_reg_offset(s, a->pg), | |
4011 | status, vsz, vsz, 0, fn); | |
4012 | tcg_temp_free_ptr(status); | |
6ceabaad | 4013 | } |
6ceabaad RH |
4014 | return true; |
4015 | } | |
4016 | ||
4017 | #define DO_FMLA(NAME, name) \ | |
3a7be554 | 4018 | static bool trans_##NAME(DisasContext *s, arg_rprrr_esz *a) \ |
6ceabaad | 4019 | { \ |
08975da9 | 4020 | static gen_helper_gvec_5_ptr * const fns[4] = { \ |
6ceabaad RH |
4021 | NULL, gen_helper_sve_##name##_h, \ |
4022 | gen_helper_sve_##name##_s, gen_helper_sve_##name##_d \ | |
4023 | }; \ | |
4024 | return do_fmla(s, a, fns[a->esz]); \ | |
4025 | } | |
4026 | ||
4027 | DO_FMLA(FMLA_zpzzz, fmla_zpzzz) | |
4028 | DO_FMLA(FMLS_zpzzz, fmls_zpzzz) | |
4029 | DO_FMLA(FNMLA_zpzzz, fnmla_zpzzz) | |
4030 | DO_FMLA(FNMLS_zpzzz, fnmls_zpzzz) | |
4031 | ||
4032 | #undef DO_FMLA | |
4033 | ||
3a7be554 | 4034 | static bool trans_FCMLA_zpzzz(DisasContext *s, arg_FCMLA_zpzzz *a) |
05f48bab | 4035 | { |
08975da9 RH |
4036 | static gen_helper_gvec_5_ptr * const fns[4] = { |
4037 | NULL, | |
05f48bab RH |
4038 | gen_helper_sve_fcmla_zpzzz_h, |
4039 | gen_helper_sve_fcmla_zpzzz_s, | |
4040 | gen_helper_sve_fcmla_zpzzz_d, | |
4041 | }; | |
4042 | ||
4043 | if (a->esz == 0) { | |
4044 | return false; | |
4045 | } | |
4046 | if (sve_access_check(s)) { | |
4047 | unsigned vsz = vec_full_reg_size(s); | |
cdfb22bb | 4048 | TCGv_ptr status = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR); |
08975da9 RH |
4049 | tcg_gen_gvec_5_ptr(vec_full_reg_offset(s, a->rd), |
4050 | vec_full_reg_offset(s, a->rn), | |
4051 | vec_full_reg_offset(s, a->rm), | |
4052 | vec_full_reg_offset(s, a->ra), | |
4053 | pred_full_reg_offset(s, a->pg), | |
4054 | status, vsz, vsz, a->rot, fns[a->esz]); | |
4055 | tcg_temp_free_ptr(status); | |
05f48bab RH |
4056 | } |
4057 | return true; | |
4058 | } | |
4059 | ||
3a7be554 | 4060 | static bool trans_FCMLA_zzxz(DisasContext *s, arg_FCMLA_zzxz *a) |
18fc2405 | 4061 | { |
41bf9b67 RH |
4062 | static gen_helper_gvec_4_ptr * const fns[4] = { |
4063 | NULL, | |
18fc2405 RH |
4064 | gen_helper_gvec_fcmlah_idx, |
4065 | gen_helper_gvec_fcmlas_idx, | |
41bf9b67 | 4066 | NULL, |
18fc2405 RH |
4067 | }; |
4068 | ||
18fc2405 | 4069 | tcg_debug_assert(a->rd == a->ra); |
41bf9b67 RH |
4070 | |
4071 | return gen_gvec_fpst_zzzz(s, fns[a->esz], a->rd, a->rn, a->rm, a->ra, | |
4072 | a->index * 4 + a->rot, | |
4073 | a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR); | |
18fc2405 RH |
4074 | } |
4075 | ||
8092c6a3 RH |
4076 | /* |
4077 | *** SVE Floating Point Unary Operations Predicated Group | |
4078 | */ | |
4079 | ||
4080 | static bool do_zpz_ptr(DisasContext *s, int rd, int rn, int pg, | |
4081 | bool is_fp16, gen_helper_gvec_3_ptr *fn) | |
4082 | { | |
4083 | if (sve_access_check(s)) { | |
4084 | unsigned vsz = vec_full_reg_size(s); | |
cdfb22bb | 4085 | TCGv_ptr status = fpstatus_ptr(is_fp16 ? FPST_FPCR_F16 : FPST_FPCR); |
8092c6a3 RH |
4086 | tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd), |
4087 | vec_full_reg_offset(s, rn), | |
4088 | pred_full_reg_offset(s, pg), | |
4089 | status, vsz, vsz, 0, fn); | |
4090 | tcg_temp_free_ptr(status); | |
4091 | } | |
4092 | return true; | |
4093 | } | |
4094 | ||
3a7be554 | 4095 | static bool trans_FCVT_sh(DisasContext *s, arg_rpr_esz *a) |
46d33d1e | 4096 | { |
e4ab5124 | 4097 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvt_sh); |
46d33d1e RH |
4098 | } |
4099 | ||
3a7be554 | 4100 | static bool trans_FCVT_hs(DisasContext *s, arg_rpr_esz *a) |
46d33d1e RH |
4101 | { |
4102 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvt_hs); | |
4103 | } | |
4104 | ||
d29b17ca RH |
4105 | static bool trans_BFCVT(DisasContext *s, arg_rpr_esz *a) |
4106 | { | |
4107 | if (!dc_isar_feature(aa64_sve_bf16, s)) { | |
4108 | return false; | |
4109 | } | |
4110 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_bfcvt); | |
4111 | } | |
4112 | ||
3a7be554 | 4113 | static bool trans_FCVT_dh(DisasContext *s, arg_rpr_esz *a) |
46d33d1e | 4114 | { |
e4ab5124 | 4115 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvt_dh); |
46d33d1e RH |
4116 | } |
4117 | ||
3a7be554 | 4118 | static bool trans_FCVT_hd(DisasContext *s, arg_rpr_esz *a) |
46d33d1e RH |
4119 | { |
4120 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvt_hd); | |
4121 | } | |
4122 | ||
3a7be554 | 4123 | static bool trans_FCVT_ds(DisasContext *s, arg_rpr_esz *a) |
46d33d1e RH |
4124 | { |
4125 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvt_ds); | |
4126 | } | |
4127 | ||
3a7be554 | 4128 | static bool trans_FCVT_sd(DisasContext *s, arg_rpr_esz *a) |
46d33d1e RH |
4129 | { |
4130 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvt_sd); | |
4131 | } | |
4132 | ||
3a7be554 | 4133 | static bool trans_FCVTZS_hh(DisasContext *s, arg_rpr_esz *a) |
df4de1af RH |
4134 | { |
4135 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_fcvtzs_hh); | |
4136 | } | |
4137 | ||
3a7be554 | 4138 | static bool trans_FCVTZU_hh(DisasContext *s, arg_rpr_esz *a) |
df4de1af RH |
4139 | { |
4140 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_fcvtzu_hh); | |
4141 | } | |
4142 | ||
3a7be554 | 4143 | static bool trans_FCVTZS_hs(DisasContext *s, arg_rpr_esz *a) |
df4de1af RH |
4144 | { |
4145 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_fcvtzs_hs); | |
4146 | } | |
4147 | ||
3a7be554 | 4148 | static bool trans_FCVTZU_hs(DisasContext *s, arg_rpr_esz *a) |
df4de1af RH |
4149 | { |
4150 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_fcvtzu_hs); | |
4151 | } | |
4152 | ||
3a7be554 | 4153 | static bool trans_FCVTZS_hd(DisasContext *s, arg_rpr_esz *a) |
df4de1af RH |
4154 | { |
4155 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_fcvtzs_hd); | |
4156 | } | |
4157 | ||
3a7be554 | 4158 | static bool trans_FCVTZU_hd(DisasContext *s, arg_rpr_esz *a) |
df4de1af RH |
4159 | { |
4160 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_fcvtzu_hd); | |
4161 | } | |
4162 | ||
3a7be554 | 4163 | static bool trans_FCVTZS_ss(DisasContext *s, arg_rpr_esz *a) |
df4de1af RH |
4164 | { |
4165 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvtzs_ss); | |
4166 | } | |
4167 | ||
3a7be554 | 4168 | static bool trans_FCVTZU_ss(DisasContext *s, arg_rpr_esz *a) |
df4de1af RH |
4169 | { |
4170 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvtzu_ss); | |
4171 | } | |
4172 | ||
3a7be554 | 4173 | static bool trans_FCVTZS_sd(DisasContext *s, arg_rpr_esz *a) |
df4de1af RH |
4174 | { |
4175 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvtzs_sd); | |
4176 | } | |
4177 | ||
3a7be554 | 4178 | static bool trans_FCVTZU_sd(DisasContext *s, arg_rpr_esz *a) |
df4de1af RH |
4179 | { |
4180 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvtzu_sd); | |
4181 | } | |
4182 | ||
3a7be554 | 4183 | static bool trans_FCVTZS_ds(DisasContext *s, arg_rpr_esz *a) |
df4de1af RH |
4184 | { |
4185 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvtzs_ds); | |
4186 | } | |
4187 | ||
3a7be554 | 4188 | static bool trans_FCVTZU_ds(DisasContext *s, arg_rpr_esz *a) |
df4de1af RH |
4189 | { |
4190 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvtzu_ds); | |
4191 | } | |
4192 | ||
3a7be554 | 4193 | static bool trans_FCVTZS_dd(DisasContext *s, arg_rpr_esz *a) |
df4de1af RH |
4194 | { |
4195 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvtzs_dd); | |
4196 | } | |
4197 | ||
3a7be554 | 4198 | static bool trans_FCVTZU_dd(DisasContext *s, arg_rpr_esz *a) |
df4de1af RH |
4199 | { |
4200 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvtzu_dd); | |
4201 | } | |
4202 | ||
cda3c753 RH |
4203 | static gen_helper_gvec_3_ptr * const frint_fns[3] = { |
4204 | gen_helper_sve_frint_h, | |
4205 | gen_helper_sve_frint_s, | |
4206 | gen_helper_sve_frint_d | |
4207 | }; | |
4208 | ||
3a7be554 | 4209 | static bool trans_FRINTI(DisasContext *s, arg_rpr_esz *a) |
cda3c753 RH |
4210 | { |
4211 | if (a->esz == 0) { | |
4212 | return false; | |
4213 | } | |
4214 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, a->esz == MO_16, | |
4215 | frint_fns[a->esz - 1]); | |
4216 | } | |
4217 | ||
3a7be554 | 4218 | static bool trans_FRINTX(DisasContext *s, arg_rpr_esz *a) |
cda3c753 RH |
4219 | { |
4220 | static gen_helper_gvec_3_ptr * const fns[3] = { | |
4221 | gen_helper_sve_frintx_h, | |
4222 | gen_helper_sve_frintx_s, | |
4223 | gen_helper_sve_frintx_d | |
4224 | }; | |
4225 | if (a->esz == 0) { | |
4226 | return false; | |
4227 | } | |
4228 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, a->esz == MO_16, fns[a->esz - 1]); | |
4229 | } | |
4230 | ||
95365277 SL |
4231 | static bool do_frint_mode(DisasContext *s, arg_rpr_esz *a, |
4232 | int mode, gen_helper_gvec_3_ptr *fn) | |
cda3c753 | 4233 | { |
cda3c753 RH |
4234 | if (sve_access_check(s)) { |
4235 | unsigned vsz = vec_full_reg_size(s); | |
4236 | TCGv_i32 tmode = tcg_const_i32(mode); | |
cdfb22bb | 4237 | TCGv_ptr status = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR); |
cda3c753 RH |
4238 | |
4239 | gen_helper_set_rmode(tmode, tmode, status); | |
4240 | ||
4241 | tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, a->rd), | |
4242 | vec_full_reg_offset(s, a->rn), | |
4243 | pred_full_reg_offset(s, a->pg), | |
95365277 | 4244 | status, vsz, vsz, 0, fn); |
cda3c753 RH |
4245 | |
4246 | gen_helper_set_rmode(tmode, tmode, status); | |
4247 | tcg_temp_free_i32(tmode); | |
4248 | tcg_temp_free_ptr(status); | |
4249 | } | |
4250 | return true; | |
4251 | } | |
4252 | ||
3a7be554 | 4253 | static bool trans_FRINTN(DisasContext *s, arg_rpr_esz *a) |
cda3c753 | 4254 | { |
95365277 SL |
4255 | if (a->esz == 0) { |
4256 | return false; | |
4257 | } | |
4258 | return do_frint_mode(s, a, float_round_nearest_even, frint_fns[a->esz - 1]); | |
cda3c753 RH |
4259 | } |
4260 | ||
3a7be554 | 4261 | static bool trans_FRINTP(DisasContext *s, arg_rpr_esz *a) |
cda3c753 | 4262 | { |
95365277 SL |
4263 | if (a->esz == 0) { |
4264 | return false; | |
4265 | } | |
4266 | return do_frint_mode(s, a, float_round_up, frint_fns[a->esz - 1]); | |
cda3c753 RH |
4267 | } |
4268 | ||
3a7be554 | 4269 | static bool trans_FRINTM(DisasContext *s, arg_rpr_esz *a) |
cda3c753 | 4270 | { |
95365277 SL |
4271 | if (a->esz == 0) { |
4272 | return false; | |
4273 | } | |
4274 | return do_frint_mode(s, a, float_round_down, frint_fns[a->esz - 1]); | |
cda3c753 RH |
4275 | } |
4276 | ||
3a7be554 | 4277 | static bool trans_FRINTZ(DisasContext *s, arg_rpr_esz *a) |
cda3c753 | 4278 | { |
95365277 SL |
4279 | if (a->esz == 0) { |
4280 | return false; | |
4281 | } | |
4282 | return do_frint_mode(s, a, float_round_to_zero, frint_fns[a->esz - 1]); | |
cda3c753 RH |
4283 | } |
4284 | ||
3a7be554 | 4285 | static bool trans_FRINTA(DisasContext *s, arg_rpr_esz *a) |
cda3c753 | 4286 | { |
95365277 SL |
4287 | if (a->esz == 0) { |
4288 | return false; | |
4289 | } | |
4290 | return do_frint_mode(s, a, float_round_ties_away, frint_fns[a->esz - 1]); | |
cda3c753 RH |
4291 | } |
4292 | ||
3a7be554 | 4293 | static bool trans_FRECPX(DisasContext *s, arg_rpr_esz *a) |
ec5b375b RH |
4294 | { |
4295 | static gen_helper_gvec_3_ptr * const fns[3] = { | |
4296 | gen_helper_sve_frecpx_h, | |
4297 | gen_helper_sve_frecpx_s, | |
4298 | gen_helper_sve_frecpx_d | |
4299 | }; | |
4300 | if (a->esz == 0) { | |
4301 | return false; | |
4302 | } | |
4303 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, a->esz == MO_16, fns[a->esz - 1]); | |
4304 | } | |
4305 | ||
3a7be554 | 4306 | static bool trans_FSQRT(DisasContext *s, arg_rpr_esz *a) |
ec5b375b RH |
4307 | { |
4308 | static gen_helper_gvec_3_ptr * const fns[3] = { | |
4309 | gen_helper_sve_fsqrt_h, | |
4310 | gen_helper_sve_fsqrt_s, | |
4311 | gen_helper_sve_fsqrt_d | |
4312 | }; | |
4313 | if (a->esz == 0) { | |
4314 | return false; | |
4315 | } | |
4316 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, a->esz == MO_16, fns[a->esz - 1]); | |
4317 | } | |
4318 | ||
3a7be554 | 4319 | static bool trans_SCVTF_hh(DisasContext *s, arg_rpr_esz *a) |
8092c6a3 RH |
4320 | { |
4321 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_scvt_hh); | |
4322 | } | |
4323 | ||
3a7be554 | 4324 | static bool trans_SCVTF_sh(DisasContext *s, arg_rpr_esz *a) |
8092c6a3 RH |
4325 | { |
4326 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_scvt_sh); | |
4327 | } | |
4328 | ||
3a7be554 | 4329 | static bool trans_SCVTF_dh(DisasContext *s, arg_rpr_esz *a) |
8092c6a3 RH |
4330 | { |
4331 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_scvt_dh); | |
4332 | } | |
4333 | ||
3a7be554 | 4334 | static bool trans_SCVTF_ss(DisasContext *s, arg_rpr_esz *a) |
8092c6a3 RH |
4335 | { |
4336 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_scvt_ss); | |
4337 | } | |
4338 | ||
3a7be554 | 4339 | static bool trans_SCVTF_ds(DisasContext *s, arg_rpr_esz *a) |
8092c6a3 RH |
4340 | { |
4341 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_scvt_ds); | |
4342 | } | |
4343 | ||
3a7be554 | 4344 | static bool trans_SCVTF_sd(DisasContext *s, arg_rpr_esz *a) |
8092c6a3 RH |
4345 | { |
4346 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_scvt_sd); | |
4347 | } | |
4348 | ||
3a7be554 | 4349 | static bool trans_SCVTF_dd(DisasContext *s, arg_rpr_esz *a) |
8092c6a3 RH |
4350 | { |
4351 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_scvt_dd); | |
4352 | } | |
4353 | ||
3a7be554 | 4354 | static bool trans_UCVTF_hh(DisasContext *s, arg_rpr_esz *a) |
8092c6a3 RH |
4355 | { |
4356 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_ucvt_hh); | |
4357 | } | |
4358 | ||
3a7be554 | 4359 | static bool trans_UCVTF_sh(DisasContext *s, arg_rpr_esz *a) |
8092c6a3 RH |
4360 | { |
4361 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_ucvt_sh); | |
4362 | } | |
4363 | ||
3a7be554 | 4364 | static bool trans_UCVTF_dh(DisasContext *s, arg_rpr_esz *a) |
8092c6a3 RH |
4365 | { |
4366 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_ucvt_dh); | |
4367 | } | |
4368 | ||
3a7be554 | 4369 | static bool trans_UCVTF_ss(DisasContext *s, arg_rpr_esz *a) |
8092c6a3 RH |
4370 | { |
4371 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_ucvt_ss); | |
4372 | } | |
4373 | ||
3a7be554 | 4374 | static bool trans_UCVTF_ds(DisasContext *s, arg_rpr_esz *a) |
8092c6a3 RH |
4375 | { |
4376 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_ucvt_ds); | |
4377 | } | |
4378 | ||
3a7be554 | 4379 | static bool trans_UCVTF_sd(DisasContext *s, arg_rpr_esz *a) |
8092c6a3 RH |
4380 | { |
4381 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_ucvt_sd); | |
4382 | } | |
4383 | ||
3a7be554 | 4384 | static bool trans_UCVTF_dd(DisasContext *s, arg_rpr_esz *a) |
8092c6a3 RH |
4385 | { |
4386 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_ucvt_dd); | |
4387 | } | |
4388 | ||
d1822297 RH |
4389 | /* |
4390 | *** SVE Memory - 32-bit Gather and Unsized Contiguous Group | |
4391 | */ | |
4392 | ||
4393 | /* Subroutine loading a vector register at VOFS of LEN bytes. | |
4394 | * The load should begin at the address Rn + IMM. | |
4395 | */ | |
4396 | ||
19f2acc9 | 4397 | static void do_ldr(DisasContext *s, uint32_t vofs, int len, int rn, int imm) |
d1822297 | 4398 | { |
19f2acc9 RH |
4399 | int len_align = QEMU_ALIGN_DOWN(len, 8); |
4400 | int len_remain = len % 8; | |
4401 | int nparts = len / 8 + ctpop8(len_remain); | |
d1822297 | 4402 | int midx = get_mem_index(s); |
b2aa8879 | 4403 | TCGv_i64 dirty_addr, clean_addr, t0, t1; |
d1822297 | 4404 | |
b2aa8879 RH |
4405 | dirty_addr = tcg_temp_new_i64(); |
4406 | tcg_gen_addi_i64(dirty_addr, cpu_reg_sp(s, rn), imm); | |
33e74c31 | 4407 | clean_addr = gen_mte_checkN(s, dirty_addr, false, rn != 31, len); |
b2aa8879 | 4408 | tcg_temp_free_i64(dirty_addr); |
d1822297 | 4409 | |
b2aa8879 RH |
4410 | /* |
4411 | * Note that unpredicated load/store of vector/predicate registers | |
d1822297 | 4412 | * are defined as a stream of bytes, which equates to little-endian |
b2aa8879 | 4413 | * operations on larger quantities. |
d1822297 RH |
4414 | * Attempt to keep code expansion to a minimum by limiting the |
4415 | * amount of unrolling done. | |
4416 | */ | |
4417 | if (nparts <= 4) { | |
4418 | int i; | |
4419 | ||
b2aa8879 | 4420 | t0 = tcg_temp_new_i64(); |
d1822297 | 4421 | for (i = 0; i < len_align; i += 8) { |
fc313c64 | 4422 | tcg_gen_qemu_ld_i64(t0, clean_addr, midx, MO_LEUQ); |
d1822297 | 4423 | tcg_gen_st_i64(t0, cpu_env, vofs + i); |
d8227b09 | 4424 | tcg_gen_addi_i64(clean_addr, clean_addr, 8); |
d1822297 | 4425 | } |
b2aa8879 | 4426 | tcg_temp_free_i64(t0); |
d1822297 RH |
4427 | } else { |
4428 | TCGLabel *loop = gen_new_label(); | |
4429 | TCGv_ptr tp, i = tcg_const_local_ptr(0); | |
4430 | ||
b2aa8879 RH |
4431 | /* Copy the clean address into a local temp, live across the loop. */ |
4432 | t0 = clean_addr; | |
4b4dc975 | 4433 | clean_addr = new_tmp_a64_local(s); |
b2aa8879 | 4434 | tcg_gen_mov_i64(clean_addr, t0); |
d1822297 | 4435 | |
b2aa8879 | 4436 | gen_set_label(loop); |
d1822297 | 4437 | |
b2aa8879 | 4438 | t0 = tcg_temp_new_i64(); |
fc313c64 | 4439 | tcg_gen_qemu_ld_i64(t0, clean_addr, midx, MO_LEUQ); |
b2aa8879 | 4440 | tcg_gen_addi_i64(clean_addr, clean_addr, 8); |
d1822297 | 4441 | |
b2aa8879 | 4442 | tp = tcg_temp_new_ptr(); |
d1822297 RH |
4443 | tcg_gen_add_ptr(tp, cpu_env, i); |
4444 | tcg_gen_addi_ptr(i, i, 8); | |
4445 | tcg_gen_st_i64(t0, tp, vofs); | |
4446 | tcg_temp_free_ptr(tp); | |
b2aa8879 | 4447 | tcg_temp_free_i64(t0); |
d1822297 RH |
4448 | |
4449 | tcg_gen_brcondi_ptr(TCG_COND_LTU, i, len_align, loop); | |
4450 | tcg_temp_free_ptr(i); | |
4451 | } | |
4452 | ||
b2aa8879 RH |
4453 | /* |
4454 | * Predicate register loads can be any multiple of 2. | |
d1822297 RH |
4455 | * Note that we still store the entire 64-bit unit into cpu_env. |
4456 | */ | |
4457 | if (len_remain) { | |
b2aa8879 | 4458 | t0 = tcg_temp_new_i64(); |
d1822297 RH |
4459 | switch (len_remain) { |
4460 | case 2: | |
4461 | case 4: | |
4462 | case 8: | |
b2aa8879 RH |
4463 | tcg_gen_qemu_ld_i64(t0, clean_addr, midx, |
4464 | MO_LE | ctz32(len_remain)); | |
d1822297 RH |
4465 | break; |
4466 | ||
4467 | case 6: | |
4468 | t1 = tcg_temp_new_i64(); | |
b2aa8879 RH |
4469 | tcg_gen_qemu_ld_i64(t0, clean_addr, midx, MO_LEUL); |
4470 | tcg_gen_addi_i64(clean_addr, clean_addr, 4); | |
4471 | tcg_gen_qemu_ld_i64(t1, clean_addr, midx, MO_LEUW); | |
d1822297 RH |
4472 | tcg_gen_deposit_i64(t0, t0, t1, 32, 32); |
4473 | tcg_temp_free_i64(t1); | |
4474 | break; | |
4475 | ||
4476 | default: | |
4477 | g_assert_not_reached(); | |
4478 | } | |
4479 | tcg_gen_st_i64(t0, cpu_env, vofs + len_align); | |
b2aa8879 | 4480 | tcg_temp_free_i64(t0); |
d1822297 | 4481 | } |
d1822297 RH |
4482 | } |
4483 | ||
5047c204 | 4484 | /* Similarly for stores. */ |
19f2acc9 | 4485 | static void do_str(DisasContext *s, uint32_t vofs, int len, int rn, int imm) |
5047c204 | 4486 | { |
19f2acc9 RH |
4487 | int len_align = QEMU_ALIGN_DOWN(len, 8); |
4488 | int len_remain = len % 8; | |
4489 | int nparts = len / 8 + ctpop8(len_remain); | |
5047c204 | 4490 | int midx = get_mem_index(s); |
bba87d0a | 4491 | TCGv_i64 dirty_addr, clean_addr, t0; |
5047c204 | 4492 | |
bba87d0a RH |
4493 | dirty_addr = tcg_temp_new_i64(); |
4494 | tcg_gen_addi_i64(dirty_addr, cpu_reg_sp(s, rn), imm); | |
33e74c31 | 4495 | clean_addr = gen_mte_checkN(s, dirty_addr, false, rn != 31, len); |
bba87d0a | 4496 | tcg_temp_free_i64(dirty_addr); |
5047c204 RH |
4497 | |
4498 | /* Note that unpredicated load/store of vector/predicate registers | |
4499 | * are defined as a stream of bytes, which equates to little-endian | |
4500 | * operations on larger quantities. There is no nice way to force | |
4501 | * a little-endian store for aarch64_be-linux-user out of line. | |
4502 | * | |
4503 | * Attempt to keep code expansion to a minimum by limiting the | |
4504 | * amount of unrolling done. | |
4505 | */ | |
4506 | if (nparts <= 4) { | |
4507 | int i; | |
4508 | ||
bba87d0a | 4509 | t0 = tcg_temp_new_i64(); |
5047c204 RH |
4510 | for (i = 0; i < len_align; i += 8) { |
4511 | tcg_gen_ld_i64(t0, cpu_env, vofs + i); | |
fc313c64 | 4512 | tcg_gen_qemu_st_i64(t0, clean_addr, midx, MO_LEUQ); |
d8227b09 | 4513 | tcg_gen_addi_i64(clean_addr, clean_addr, 8); |
5047c204 | 4514 | } |
bba87d0a | 4515 | tcg_temp_free_i64(t0); |
5047c204 RH |
4516 | } else { |
4517 | TCGLabel *loop = gen_new_label(); | |
bba87d0a | 4518 | TCGv_ptr tp, i = tcg_const_local_ptr(0); |
5047c204 | 4519 | |
bba87d0a RH |
4520 | /* Copy the clean address into a local temp, live across the loop. */ |
4521 | t0 = clean_addr; | |
4b4dc975 | 4522 | clean_addr = new_tmp_a64_local(s); |
bba87d0a | 4523 | tcg_gen_mov_i64(clean_addr, t0); |
5047c204 | 4524 | |
bba87d0a | 4525 | gen_set_label(loop); |
5047c204 | 4526 | |
bba87d0a RH |
4527 | t0 = tcg_temp_new_i64(); |
4528 | tp = tcg_temp_new_ptr(); | |
4529 | tcg_gen_add_ptr(tp, cpu_env, i); | |
4530 | tcg_gen_ld_i64(t0, tp, vofs); | |
5047c204 | 4531 | tcg_gen_addi_ptr(i, i, 8); |
bba87d0a RH |
4532 | tcg_temp_free_ptr(tp); |
4533 | ||
fc313c64 | 4534 | tcg_gen_qemu_st_i64(t0, clean_addr, midx, MO_LEUQ); |
bba87d0a RH |
4535 | tcg_gen_addi_i64(clean_addr, clean_addr, 8); |
4536 | tcg_temp_free_i64(t0); | |
5047c204 RH |
4537 | |
4538 | tcg_gen_brcondi_ptr(TCG_COND_LTU, i, len_align, loop); | |
4539 | tcg_temp_free_ptr(i); | |
4540 | } | |
4541 | ||
4542 | /* Predicate register stores can be any multiple of 2. */ | |
4543 | if (len_remain) { | |
bba87d0a | 4544 | t0 = tcg_temp_new_i64(); |
5047c204 | 4545 | tcg_gen_ld_i64(t0, cpu_env, vofs + len_align); |
5047c204 RH |
4546 | |
4547 | switch (len_remain) { | |
4548 | case 2: | |
4549 | case 4: | |
4550 | case 8: | |
bba87d0a RH |
4551 | tcg_gen_qemu_st_i64(t0, clean_addr, midx, |
4552 | MO_LE | ctz32(len_remain)); | |
5047c204 RH |
4553 | break; |
4554 | ||
4555 | case 6: | |
bba87d0a RH |
4556 | tcg_gen_qemu_st_i64(t0, clean_addr, midx, MO_LEUL); |
4557 | tcg_gen_addi_i64(clean_addr, clean_addr, 4); | |
5047c204 | 4558 | tcg_gen_shri_i64(t0, t0, 32); |
bba87d0a | 4559 | tcg_gen_qemu_st_i64(t0, clean_addr, midx, MO_LEUW); |
5047c204 RH |
4560 | break; |
4561 | ||
4562 | default: | |
4563 | g_assert_not_reached(); | |
4564 | } | |
bba87d0a | 4565 | tcg_temp_free_i64(t0); |
5047c204 | 4566 | } |
5047c204 RH |
4567 | } |
4568 | ||
3a7be554 | 4569 | static bool trans_LDR_zri(DisasContext *s, arg_rri *a) |
d1822297 RH |
4570 | { |
4571 | if (sve_access_check(s)) { | |
4572 | int size = vec_full_reg_size(s); | |
4573 | int off = vec_full_reg_offset(s, a->rd); | |
4574 | do_ldr(s, off, size, a->rn, a->imm * size); | |
4575 | } | |
4576 | return true; | |
4577 | } | |
4578 | ||
3a7be554 | 4579 | static bool trans_LDR_pri(DisasContext *s, arg_rri *a) |
d1822297 RH |
4580 | { |
4581 | if (sve_access_check(s)) { | |
4582 | int size = pred_full_reg_size(s); | |
4583 | int off = pred_full_reg_offset(s, a->rd); | |
4584 | do_ldr(s, off, size, a->rn, a->imm * size); | |
4585 | } | |
4586 | return true; | |
4587 | } | |
c4e7c493 | 4588 | |
3a7be554 | 4589 | static bool trans_STR_zri(DisasContext *s, arg_rri *a) |
5047c204 RH |
4590 | { |
4591 | if (sve_access_check(s)) { | |
4592 | int size = vec_full_reg_size(s); | |
4593 | int off = vec_full_reg_offset(s, a->rd); | |
4594 | do_str(s, off, size, a->rn, a->imm * size); | |
4595 | } | |
4596 | return true; | |
4597 | } | |
4598 | ||
3a7be554 | 4599 | static bool trans_STR_pri(DisasContext *s, arg_rri *a) |
5047c204 RH |
4600 | { |
4601 | if (sve_access_check(s)) { | |
4602 | int size = pred_full_reg_size(s); | |
4603 | int off = pred_full_reg_offset(s, a->rd); | |
4604 | do_str(s, off, size, a->rn, a->imm * size); | |
4605 | } | |
4606 | return true; | |
4607 | } | |
4608 | ||
c4e7c493 RH |
4609 | /* |
4610 | *** SVE Memory - Contiguous Load Group | |
4611 | */ | |
4612 | ||
4613 | /* The memory mode of the dtype. */ | |
14776ab5 | 4614 | static const MemOp dtype_mop[16] = { |
c4e7c493 RH |
4615 | MO_UB, MO_UB, MO_UB, MO_UB, |
4616 | MO_SL, MO_UW, MO_UW, MO_UW, | |
4617 | MO_SW, MO_SW, MO_UL, MO_UL, | |
fc313c64 | 4618 | MO_SB, MO_SB, MO_SB, MO_UQ |
c4e7c493 RH |
4619 | }; |
4620 | ||
4621 | #define dtype_msz(x) (dtype_mop[x] & MO_SIZE) | |
4622 | ||
4623 | /* The vector element size of dtype. */ | |
4624 | static const uint8_t dtype_esz[16] = { | |
4625 | 0, 1, 2, 3, | |
4626 | 3, 1, 2, 3, | |
4627 | 3, 2, 2, 3, | |
4628 | 3, 2, 1, 3 | |
4629 | }; | |
4630 | ||
4631 | static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr, | |
206adacf RH |
4632 | int dtype, uint32_t mte_n, bool is_write, |
4633 | gen_helper_gvec_mem *fn) | |
c4e7c493 RH |
4634 | { |
4635 | unsigned vsz = vec_full_reg_size(s); | |
4636 | TCGv_ptr t_pg; | |
206adacf | 4637 | int desc = 0; |
c4e7c493 | 4638 | |
206adacf RH |
4639 | /* |
4640 | * For e.g. LD4, there are not enough arguments to pass all 4 | |
c4e7c493 RH |
4641 | * registers as pointers, so encode the regno into the data field. |
4642 | * For consistency, do this even for LD1. | |
4643 | */ | |
9473d0ec | 4644 | if (s->mte_active[0]) { |
206adacf RH |
4645 | int msz = dtype_msz(dtype); |
4646 | ||
4647 | desc = FIELD_DP32(desc, MTEDESC, MIDX, get_mem_index(s)); | |
4648 | desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid); | |
4649 | desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma); | |
4650 | desc = FIELD_DP32(desc, MTEDESC, WRITE, is_write); | |
28f32503 | 4651 | desc = FIELD_DP32(desc, MTEDESC, SIZEM1, (mte_n << msz) - 1); |
206adacf | 4652 | desc <<= SVE_MTEDESC_SHIFT; |
9473d0ec RH |
4653 | } else { |
4654 | addr = clean_data_tbi(s, addr); | |
206adacf | 4655 | } |
9473d0ec | 4656 | |
206adacf | 4657 | desc = simd_desc(vsz, vsz, zt | desc); |
c4e7c493 RH |
4658 | t_pg = tcg_temp_new_ptr(); |
4659 | ||
4660 | tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, pg)); | |
c6a59b55 | 4661 | fn(cpu_env, t_pg, addr, tcg_constant_i32(desc)); |
c4e7c493 RH |
4662 | |
4663 | tcg_temp_free_ptr(t_pg); | |
c4e7c493 RH |
4664 | } |
4665 | ||
c182c6db RH |
4666 | /* Indexed by [mte][be][dtype][nreg] */ |
4667 | static gen_helper_gvec_mem * const ldr_fns[2][2][16][4] = { | |
4668 | { /* mte inactive, little-endian */ | |
4669 | { { gen_helper_sve_ld1bb_r, gen_helper_sve_ld2bb_r, | |
4670 | gen_helper_sve_ld3bb_r, gen_helper_sve_ld4bb_r }, | |
4671 | { gen_helper_sve_ld1bhu_r, NULL, NULL, NULL }, | |
4672 | { gen_helper_sve_ld1bsu_r, NULL, NULL, NULL }, | |
4673 | { gen_helper_sve_ld1bdu_r, NULL, NULL, NULL }, | |
4674 | ||
4675 | { gen_helper_sve_ld1sds_le_r, NULL, NULL, NULL }, | |
4676 | { gen_helper_sve_ld1hh_le_r, gen_helper_sve_ld2hh_le_r, | |
4677 | gen_helper_sve_ld3hh_le_r, gen_helper_sve_ld4hh_le_r }, | |
4678 | { gen_helper_sve_ld1hsu_le_r, NULL, NULL, NULL }, | |
4679 | { gen_helper_sve_ld1hdu_le_r, NULL, NULL, NULL }, | |
4680 | ||
4681 | { gen_helper_sve_ld1hds_le_r, NULL, NULL, NULL }, | |
4682 | { gen_helper_sve_ld1hss_le_r, NULL, NULL, NULL }, | |
4683 | { gen_helper_sve_ld1ss_le_r, gen_helper_sve_ld2ss_le_r, | |
4684 | gen_helper_sve_ld3ss_le_r, gen_helper_sve_ld4ss_le_r }, | |
4685 | { gen_helper_sve_ld1sdu_le_r, NULL, NULL, NULL }, | |
4686 | ||
4687 | { gen_helper_sve_ld1bds_r, NULL, NULL, NULL }, | |
4688 | { gen_helper_sve_ld1bss_r, NULL, NULL, NULL }, | |
4689 | { gen_helper_sve_ld1bhs_r, NULL, NULL, NULL }, | |
4690 | { gen_helper_sve_ld1dd_le_r, gen_helper_sve_ld2dd_le_r, | |
4691 | gen_helper_sve_ld3dd_le_r, gen_helper_sve_ld4dd_le_r } }, | |
4692 | ||
4693 | /* mte inactive, big-endian */ | |
4694 | { { gen_helper_sve_ld1bb_r, gen_helper_sve_ld2bb_r, | |
4695 | gen_helper_sve_ld3bb_r, gen_helper_sve_ld4bb_r }, | |
4696 | { gen_helper_sve_ld1bhu_r, NULL, NULL, NULL }, | |
4697 | { gen_helper_sve_ld1bsu_r, NULL, NULL, NULL }, | |
4698 | { gen_helper_sve_ld1bdu_r, NULL, NULL, NULL }, | |
4699 | ||
4700 | { gen_helper_sve_ld1sds_be_r, NULL, NULL, NULL }, | |
4701 | { gen_helper_sve_ld1hh_be_r, gen_helper_sve_ld2hh_be_r, | |
4702 | gen_helper_sve_ld3hh_be_r, gen_helper_sve_ld4hh_be_r }, | |
4703 | { gen_helper_sve_ld1hsu_be_r, NULL, NULL, NULL }, | |
4704 | { gen_helper_sve_ld1hdu_be_r, NULL, NULL, NULL }, | |
4705 | ||
4706 | { gen_helper_sve_ld1hds_be_r, NULL, NULL, NULL }, | |
4707 | { gen_helper_sve_ld1hss_be_r, NULL, NULL, NULL }, | |
4708 | { gen_helper_sve_ld1ss_be_r, gen_helper_sve_ld2ss_be_r, | |
4709 | gen_helper_sve_ld3ss_be_r, gen_helper_sve_ld4ss_be_r }, | |
4710 | { gen_helper_sve_ld1sdu_be_r, NULL, NULL, NULL }, | |
4711 | ||
4712 | { gen_helper_sve_ld1bds_r, NULL, NULL, NULL }, | |
4713 | { gen_helper_sve_ld1bss_r, NULL, NULL, NULL }, | |
4714 | { gen_helper_sve_ld1bhs_r, NULL, NULL, NULL }, | |
4715 | { gen_helper_sve_ld1dd_be_r, gen_helper_sve_ld2dd_be_r, | |
4716 | gen_helper_sve_ld3dd_be_r, gen_helper_sve_ld4dd_be_r } } }, | |
4717 | ||
4718 | { /* mte active, little-endian */ | |
4719 | { { gen_helper_sve_ld1bb_r_mte, | |
4720 | gen_helper_sve_ld2bb_r_mte, | |
4721 | gen_helper_sve_ld3bb_r_mte, | |
4722 | gen_helper_sve_ld4bb_r_mte }, | |
4723 | { gen_helper_sve_ld1bhu_r_mte, NULL, NULL, NULL }, | |
4724 | { gen_helper_sve_ld1bsu_r_mte, NULL, NULL, NULL }, | |
4725 | { gen_helper_sve_ld1bdu_r_mte, NULL, NULL, NULL }, | |
4726 | ||
4727 | { gen_helper_sve_ld1sds_le_r_mte, NULL, NULL, NULL }, | |
4728 | { gen_helper_sve_ld1hh_le_r_mte, | |
4729 | gen_helper_sve_ld2hh_le_r_mte, | |
4730 | gen_helper_sve_ld3hh_le_r_mte, | |
4731 | gen_helper_sve_ld4hh_le_r_mte }, | |
4732 | { gen_helper_sve_ld1hsu_le_r_mte, NULL, NULL, NULL }, | |
4733 | { gen_helper_sve_ld1hdu_le_r_mte, NULL, NULL, NULL }, | |
4734 | ||
4735 | { gen_helper_sve_ld1hds_le_r_mte, NULL, NULL, NULL }, | |
4736 | { gen_helper_sve_ld1hss_le_r_mte, NULL, NULL, NULL }, | |
4737 | { gen_helper_sve_ld1ss_le_r_mte, | |
4738 | gen_helper_sve_ld2ss_le_r_mte, | |
4739 | gen_helper_sve_ld3ss_le_r_mte, | |
4740 | gen_helper_sve_ld4ss_le_r_mte }, | |
4741 | { gen_helper_sve_ld1sdu_le_r_mte, NULL, NULL, NULL }, | |
4742 | ||
4743 | { gen_helper_sve_ld1bds_r_mte, NULL, NULL, NULL }, | |
4744 | { gen_helper_sve_ld1bss_r_mte, NULL, NULL, NULL }, | |
4745 | { gen_helper_sve_ld1bhs_r_mte, NULL, NULL, NULL }, | |
4746 | { gen_helper_sve_ld1dd_le_r_mte, | |
4747 | gen_helper_sve_ld2dd_le_r_mte, | |
4748 | gen_helper_sve_ld3dd_le_r_mte, | |
4749 | gen_helper_sve_ld4dd_le_r_mte } }, | |
4750 | ||
4751 | /* mte active, big-endian */ | |
4752 | { { gen_helper_sve_ld1bb_r_mte, | |
4753 | gen_helper_sve_ld2bb_r_mte, | |
4754 | gen_helper_sve_ld3bb_r_mte, | |
4755 | gen_helper_sve_ld4bb_r_mte }, | |
4756 | { gen_helper_sve_ld1bhu_r_mte, NULL, NULL, NULL }, | |
4757 | { gen_helper_sve_ld1bsu_r_mte, NULL, NULL, NULL }, | |
4758 | { gen_helper_sve_ld1bdu_r_mte, NULL, NULL, NULL }, | |
4759 | ||
4760 | { gen_helper_sve_ld1sds_be_r_mte, NULL, NULL, NULL }, | |
4761 | { gen_helper_sve_ld1hh_be_r_mte, | |
4762 | gen_helper_sve_ld2hh_be_r_mte, | |
4763 | gen_helper_sve_ld3hh_be_r_mte, | |
4764 | gen_helper_sve_ld4hh_be_r_mte }, | |
4765 | { gen_helper_sve_ld1hsu_be_r_mte, NULL, NULL, NULL }, | |
4766 | { gen_helper_sve_ld1hdu_be_r_mte, NULL, NULL, NULL }, | |
4767 | ||
4768 | { gen_helper_sve_ld1hds_be_r_mte, NULL, NULL, NULL }, | |
4769 | { gen_helper_sve_ld1hss_be_r_mte, NULL, NULL, NULL }, | |
4770 | { gen_helper_sve_ld1ss_be_r_mte, | |
4771 | gen_helper_sve_ld2ss_be_r_mte, | |
4772 | gen_helper_sve_ld3ss_be_r_mte, | |
4773 | gen_helper_sve_ld4ss_be_r_mte }, | |
4774 | { gen_helper_sve_ld1sdu_be_r_mte, NULL, NULL, NULL }, | |
4775 | ||
4776 | { gen_helper_sve_ld1bds_r_mte, NULL, NULL, NULL }, | |
4777 | { gen_helper_sve_ld1bss_r_mte, NULL, NULL, NULL }, | |
4778 | { gen_helper_sve_ld1bhs_r_mte, NULL, NULL, NULL }, | |
4779 | { gen_helper_sve_ld1dd_be_r_mte, | |
4780 | gen_helper_sve_ld2dd_be_r_mte, | |
4781 | gen_helper_sve_ld3dd_be_r_mte, | |
4782 | gen_helper_sve_ld4dd_be_r_mte } } }, | |
4783 | }; | |
4784 | ||
c4e7c493 RH |
4785 | static void do_ld_zpa(DisasContext *s, int zt, int pg, |
4786 | TCGv_i64 addr, int dtype, int nreg) | |
4787 | { | |
206adacf | 4788 | gen_helper_gvec_mem *fn |
c182c6db | 4789 | = ldr_fns[s->mte_active[0]][s->be_data == MO_BE][dtype][nreg]; |
c4e7c493 | 4790 | |
206adacf RH |
4791 | /* |
4792 | * While there are holes in the table, they are not | |
c4e7c493 RH |
4793 | * accessible via the instruction encoding. |
4794 | */ | |
4795 | assert(fn != NULL); | |
206adacf | 4796 | do_mem_zpa(s, zt, pg, addr, dtype, nreg, false, fn); |
c4e7c493 RH |
4797 | } |
4798 | ||
3a7be554 | 4799 | static bool trans_LD_zprr(DisasContext *s, arg_rprr_load *a) |
c4e7c493 RH |
4800 | { |
4801 | if (a->rm == 31) { | |
4802 | return false; | |
4803 | } | |
4804 | if (sve_access_check(s)) { | |
4805 | TCGv_i64 addr = new_tmp_a64(s); | |
50ef1cbf | 4806 | tcg_gen_shli_i64(addr, cpu_reg(s, a->rm), dtype_msz(a->dtype)); |
c4e7c493 RH |
4807 | tcg_gen_add_i64(addr, addr, cpu_reg_sp(s, a->rn)); |
4808 | do_ld_zpa(s, a->rd, a->pg, addr, a->dtype, a->nreg); | |
4809 | } | |
4810 | return true; | |
4811 | } | |
4812 | ||
3a7be554 | 4813 | static bool trans_LD_zpri(DisasContext *s, arg_rpri_load *a) |
c4e7c493 RH |
4814 | { |
4815 | if (sve_access_check(s)) { | |
4816 | int vsz = vec_full_reg_size(s); | |
4817 | int elements = vsz >> dtype_esz[a->dtype]; | |
4818 | TCGv_i64 addr = new_tmp_a64(s); | |
4819 | ||
4820 | tcg_gen_addi_i64(addr, cpu_reg_sp(s, a->rn), | |
4821 | (a->imm * elements * (a->nreg + 1)) | |
4822 | << dtype_msz(a->dtype)); | |
4823 | do_ld_zpa(s, a->rd, a->pg, addr, a->dtype, a->nreg); | |
4824 | } | |
4825 | return true; | |
4826 | } | |
e2654d75 | 4827 | |
3a7be554 | 4828 | static bool trans_LDFF1_zprr(DisasContext *s, arg_rprr_load *a) |
e2654d75 | 4829 | { |
aa13f7c3 RH |
4830 | static gen_helper_gvec_mem * const fns[2][2][16] = { |
4831 | { /* mte inactive, little-endian */ | |
4832 | { gen_helper_sve_ldff1bb_r, | |
4833 | gen_helper_sve_ldff1bhu_r, | |
4834 | gen_helper_sve_ldff1bsu_r, | |
4835 | gen_helper_sve_ldff1bdu_r, | |
4836 | ||
4837 | gen_helper_sve_ldff1sds_le_r, | |
4838 | gen_helper_sve_ldff1hh_le_r, | |
4839 | gen_helper_sve_ldff1hsu_le_r, | |
4840 | gen_helper_sve_ldff1hdu_le_r, | |
4841 | ||
4842 | gen_helper_sve_ldff1hds_le_r, | |
4843 | gen_helper_sve_ldff1hss_le_r, | |
4844 | gen_helper_sve_ldff1ss_le_r, | |
4845 | gen_helper_sve_ldff1sdu_le_r, | |
4846 | ||
4847 | gen_helper_sve_ldff1bds_r, | |
4848 | gen_helper_sve_ldff1bss_r, | |
4849 | gen_helper_sve_ldff1bhs_r, | |
4850 | gen_helper_sve_ldff1dd_le_r }, | |
4851 | ||
4852 | /* mte inactive, big-endian */ | |
4853 | { gen_helper_sve_ldff1bb_r, | |
4854 | gen_helper_sve_ldff1bhu_r, | |
4855 | gen_helper_sve_ldff1bsu_r, | |
4856 | gen_helper_sve_ldff1bdu_r, | |
4857 | ||
4858 | gen_helper_sve_ldff1sds_be_r, | |
4859 | gen_helper_sve_ldff1hh_be_r, | |
4860 | gen_helper_sve_ldff1hsu_be_r, | |
4861 | gen_helper_sve_ldff1hdu_be_r, | |
4862 | ||
4863 | gen_helper_sve_ldff1hds_be_r, | |
4864 | gen_helper_sve_ldff1hss_be_r, | |
4865 | gen_helper_sve_ldff1ss_be_r, | |
4866 | gen_helper_sve_ldff1sdu_be_r, | |
4867 | ||
4868 | gen_helper_sve_ldff1bds_r, | |
4869 | gen_helper_sve_ldff1bss_r, | |
4870 | gen_helper_sve_ldff1bhs_r, | |
4871 | gen_helper_sve_ldff1dd_be_r } }, | |
4872 | ||
4873 | { /* mte active, little-endian */ | |
4874 | { gen_helper_sve_ldff1bb_r_mte, | |
4875 | gen_helper_sve_ldff1bhu_r_mte, | |
4876 | gen_helper_sve_ldff1bsu_r_mte, | |
4877 | gen_helper_sve_ldff1bdu_r_mte, | |
4878 | ||
4879 | gen_helper_sve_ldff1sds_le_r_mte, | |
4880 | gen_helper_sve_ldff1hh_le_r_mte, | |
4881 | gen_helper_sve_ldff1hsu_le_r_mte, | |
4882 | gen_helper_sve_ldff1hdu_le_r_mte, | |
4883 | ||
4884 | gen_helper_sve_ldff1hds_le_r_mte, | |
4885 | gen_helper_sve_ldff1hss_le_r_mte, | |
4886 | gen_helper_sve_ldff1ss_le_r_mte, | |
4887 | gen_helper_sve_ldff1sdu_le_r_mte, | |
4888 | ||
4889 | gen_helper_sve_ldff1bds_r_mte, | |
4890 | gen_helper_sve_ldff1bss_r_mte, | |
4891 | gen_helper_sve_ldff1bhs_r_mte, | |
4892 | gen_helper_sve_ldff1dd_le_r_mte }, | |
4893 | ||
4894 | /* mte active, big-endian */ | |
4895 | { gen_helper_sve_ldff1bb_r_mte, | |
4896 | gen_helper_sve_ldff1bhu_r_mte, | |
4897 | gen_helper_sve_ldff1bsu_r_mte, | |
4898 | gen_helper_sve_ldff1bdu_r_mte, | |
4899 | ||
4900 | gen_helper_sve_ldff1sds_be_r_mte, | |
4901 | gen_helper_sve_ldff1hh_be_r_mte, | |
4902 | gen_helper_sve_ldff1hsu_be_r_mte, | |
4903 | gen_helper_sve_ldff1hdu_be_r_mte, | |
4904 | ||
4905 | gen_helper_sve_ldff1hds_be_r_mte, | |
4906 | gen_helper_sve_ldff1hss_be_r_mte, | |
4907 | gen_helper_sve_ldff1ss_be_r_mte, | |
4908 | gen_helper_sve_ldff1sdu_be_r_mte, | |
4909 | ||
4910 | gen_helper_sve_ldff1bds_r_mte, | |
4911 | gen_helper_sve_ldff1bss_r_mte, | |
4912 | gen_helper_sve_ldff1bhs_r_mte, | |
4913 | gen_helper_sve_ldff1dd_be_r_mte } }, | |
e2654d75 RH |
4914 | }; |
4915 | ||
4916 | if (sve_access_check(s)) { | |
4917 | TCGv_i64 addr = new_tmp_a64(s); | |
4918 | tcg_gen_shli_i64(addr, cpu_reg(s, a->rm), dtype_msz(a->dtype)); | |
4919 | tcg_gen_add_i64(addr, addr, cpu_reg_sp(s, a->rn)); | |
aa13f7c3 RH |
4920 | do_mem_zpa(s, a->rd, a->pg, addr, a->dtype, 1, false, |
4921 | fns[s->mte_active[0]][s->be_data == MO_BE][a->dtype]); | |
e2654d75 RH |
4922 | } |
4923 | return true; | |
4924 | } | |
4925 | ||
3a7be554 | 4926 | static bool trans_LDNF1_zpri(DisasContext *s, arg_rpri_load *a) |
e2654d75 | 4927 | { |
aa13f7c3 RH |
4928 | static gen_helper_gvec_mem * const fns[2][2][16] = { |
4929 | { /* mte inactive, little-endian */ | |
4930 | { gen_helper_sve_ldnf1bb_r, | |
4931 | gen_helper_sve_ldnf1bhu_r, | |
4932 | gen_helper_sve_ldnf1bsu_r, | |
4933 | gen_helper_sve_ldnf1bdu_r, | |
4934 | ||
4935 | gen_helper_sve_ldnf1sds_le_r, | |
4936 | gen_helper_sve_ldnf1hh_le_r, | |
4937 | gen_helper_sve_ldnf1hsu_le_r, | |
4938 | gen_helper_sve_ldnf1hdu_le_r, | |
4939 | ||
4940 | gen_helper_sve_ldnf1hds_le_r, | |
4941 | gen_helper_sve_ldnf1hss_le_r, | |
4942 | gen_helper_sve_ldnf1ss_le_r, | |
4943 | gen_helper_sve_ldnf1sdu_le_r, | |
4944 | ||
4945 | gen_helper_sve_ldnf1bds_r, | |
4946 | gen_helper_sve_ldnf1bss_r, | |
4947 | gen_helper_sve_ldnf1bhs_r, | |
4948 | gen_helper_sve_ldnf1dd_le_r }, | |
4949 | ||
4950 | /* mte inactive, big-endian */ | |
4951 | { gen_helper_sve_ldnf1bb_r, | |
4952 | gen_helper_sve_ldnf1bhu_r, | |
4953 | gen_helper_sve_ldnf1bsu_r, | |
4954 | gen_helper_sve_ldnf1bdu_r, | |
4955 | ||
4956 | gen_helper_sve_ldnf1sds_be_r, | |
4957 | gen_helper_sve_ldnf1hh_be_r, | |
4958 | gen_helper_sve_ldnf1hsu_be_r, | |
4959 | gen_helper_sve_ldnf1hdu_be_r, | |
4960 | ||
4961 | gen_helper_sve_ldnf1hds_be_r, | |
4962 | gen_helper_sve_ldnf1hss_be_r, | |
4963 | gen_helper_sve_ldnf1ss_be_r, | |
4964 | gen_helper_sve_ldnf1sdu_be_r, | |
4965 | ||
4966 | gen_helper_sve_ldnf1bds_r, | |
4967 | gen_helper_sve_ldnf1bss_r, | |
4968 | gen_helper_sve_ldnf1bhs_r, | |
4969 | gen_helper_sve_ldnf1dd_be_r } }, | |
4970 | ||
4971 | { /* mte inactive, little-endian */ | |
4972 | { gen_helper_sve_ldnf1bb_r_mte, | |
4973 | gen_helper_sve_ldnf1bhu_r_mte, | |
4974 | gen_helper_sve_ldnf1bsu_r_mte, | |
4975 | gen_helper_sve_ldnf1bdu_r_mte, | |
4976 | ||
4977 | gen_helper_sve_ldnf1sds_le_r_mte, | |
4978 | gen_helper_sve_ldnf1hh_le_r_mte, | |
4979 | gen_helper_sve_ldnf1hsu_le_r_mte, | |
4980 | gen_helper_sve_ldnf1hdu_le_r_mte, | |
4981 | ||
4982 | gen_helper_sve_ldnf1hds_le_r_mte, | |
4983 | gen_helper_sve_ldnf1hss_le_r_mte, | |
4984 | gen_helper_sve_ldnf1ss_le_r_mte, | |
4985 | gen_helper_sve_ldnf1sdu_le_r_mte, | |
4986 | ||
4987 | gen_helper_sve_ldnf1bds_r_mte, | |
4988 | gen_helper_sve_ldnf1bss_r_mte, | |
4989 | gen_helper_sve_ldnf1bhs_r_mte, | |
4990 | gen_helper_sve_ldnf1dd_le_r_mte }, | |
4991 | ||
4992 | /* mte inactive, big-endian */ | |
4993 | { gen_helper_sve_ldnf1bb_r_mte, | |
4994 | gen_helper_sve_ldnf1bhu_r_mte, | |
4995 | gen_helper_sve_ldnf1bsu_r_mte, | |
4996 | gen_helper_sve_ldnf1bdu_r_mte, | |
4997 | ||
4998 | gen_helper_sve_ldnf1sds_be_r_mte, | |
4999 | gen_helper_sve_ldnf1hh_be_r_mte, | |
5000 | gen_helper_sve_ldnf1hsu_be_r_mte, | |
5001 | gen_helper_sve_ldnf1hdu_be_r_mte, | |
5002 | ||
5003 | gen_helper_sve_ldnf1hds_be_r_mte, | |
5004 | gen_helper_sve_ldnf1hss_be_r_mte, | |
5005 | gen_helper_sve_ldnf1ss_be_r_mte, | |
5006 | gen_helper_sve_ldnf1sdu_be_r_mte, | |
5007 | ||
5008 | gen_helper_sve_ldnf1bds_r_mte, | |
5009 | gen_helper_sve_ldnf1bss_r_mte, | |
5010 | gen_helper_sve_ldnf1bhs_r_mte, | |
5011 | gen_helper_sve_ldnf1dd_be_r_mte } }, | |
e2654d75 RH |
5012 | }; |
5013 | ||
5014 | if (sve_access_check(s)) { | |
5015 | int vsz = vec_full_reg_size(s); | |
5016 | int elements = vsz >> dtype_esz[a->dtype]; | |
5017 | int off = (a->imm * elements) << dtype_msz(a->dtype); | |
5018 | TCGv_i64 addr = new_tmp_a64(s); | |
5019 | ||
5020 | tcg_gen_addi_i64(addr, cpu_reg_sp(s, a->rn), off); | |
aa13f7c3 RH |
5021 | do_mem_zpa(s, a->rd, a->pg, addr, a->dtype, 1, false, |
5022 | fns[s->mte_active[0]][s->be_data == MO_BE][a->dtype]); | |
e2654d75 RH |
5023 | } |
5024 | return true; | |
5025 | } | |
1a039c7e | 5026 | |
c182c6db | 5027 | static void do_ldrq(DisasContext *s, int zt, int pg, TCGv_i64 addr, int dtype) |
05abe304 | 5028 | { |
05abe304 RH |
5029 | unsigned vsz = vec_full_reg_size(s); |
5030 | TCGv_ptr t_pg; | |
7924d239 | 5031 | int poff; |
05abe304 RH |
5032 | |
5033 | /* Load the first quadword using the normal predicated load helpers. */ | |
2a99ab2b RH |
5034 | poff = pred_full_reg_offset(s, pg); |
5035 | if (vsz > 16) { | |
5036 | /* | |
5037 | * Zero-extend the first 16 bits of the predicate into a temporary. | |
5038 | * This avoids triggering an assert making sure we don't have bits | |
5039 | * set within a predicate beyond VQ, but we have lowered VQ to 1 | |
5040 | * for this load operation. | |
5041 | */ | |
5042 | TCGv_i64 tmp = tcg_temp_new_i64(); | |
e03b5686 | 5043 | #if HOST_BIG_ENDIAN |
2a99ab2b RH |
5044 | poff += 6; |
5045 | #endif | |
5046 | tcg_gen_ld16u_i64(tmp, cpu_env, poff); | |
5047 | ||
5048 | poff = offsetof(CPUARMState, vfp.preg_tmp); | |
5049 | tcg_gen_st_i64(tmp, cpu_env, poff); | |
5050 | tcg_temp_free_i64(tmp); | |
5051 | } | |
5052 | ||
05abe304 | 5053 | t_pg = tcg_temp_new_ptr(); |
2a99ab2b | 5054 | tcg_gen_addi_ptr(t_pg, cpu_env, poff); |
05abe304 | 5055 | |
c182c6db RH |
5056 | gen_helper_gvec_mem *fn |
5057 | = ldr_fns[s->mte_active[0]][s->be_data == MO_BE][dtype][0]; | |
7924d239 | 5058 | fn(cpu_env, t_pg, addr, tcg_constant_i32(simd_desc(16, 16, zt))); |
05abe304 RH |
5059 | |
5060 | tcg_temp_free_ptr(t_pg); | |
05abe304 RH |
5061 | |
5062 | /* Replicate that first quadword. */ | |
5063 | if (vsz > 16) { | |
7924d239 RH |
5064 | int doff = vec_full_reg_offset(s, zt); |
5065 | tcg_gen_gvec_dup_mem(4, doff + 16, doff, vsz - 16, vsz - 16); | |
05abe304 RH |
5066 | } |
5067 | } | |
5068 | ||
3a7be554 | 5069 | static bool trans_LD1RQ_zprr(DisasContext *s, arg_rprr_load *a) |
05abe304 RH |
5070 | { |
5071 | if (a->rm == 31) { | |
5072 | return false; | |
5073 | } | |
5074 | if (sve_access_check(s)) { | |
5075 | int msz = dtype_msz(a->dtype); | |
5076 | TCGv_i64 addr = new_tmp_a64(s); | |
5077 | tcg_gen_shli_i64(addr, cpu_reg(s, a->rm), msz); | |
5078 | tcg_gen_add_i64(addr, addr, cpu_reg_sp(s, a->rn)); | |
c182c6db | 5079 | do_ldrq(s, a->rd, a->pg, addr, a->dtype); |
05abe304 RH |
5080 | } |
5081 | return true; | |
5082 | } | |
5083 | ||
3a7be554 | 5084 | static bool trans_LD1RQ_zpri(DisasContext *s, arg_rpri_load *a) |
05abe304 RH |
5085 | { |
5086 | if (sve_access_check(s)) { | |
5087 | TCGv_i64 addr = new_tmp_a64(s); | |
5088 | tcg_gen_addi_i64(addr, cpu_reg_sp(s, a->rn), a->imm * 16); | |
c182c6db | 5089 | do_ldrq(s, a->rd, a->pg, addr, a->dtype); |
05abe304 RH |
5090 | } |
5091 | return true; | |
5092 | } | |
5093 | ||
12c563f6 RH |
5094 | static void do_ldro(DisasContext *s, int zt, int pg, TCGv_i64 addr, int dtype) |
5095 | { | |
5096 | unsigned vsz = vec_full_reg_size(s); | |
5097 | unsigned vsz_r32; | |
5098 | TCGv_ptr t_pg; | |
5099 | int poff, doff; | |
5100 | ||
5101 | if (vsz < 32) { | |
5102 | /* | |
5103 | * Note that this UNDEFINED check comes after CheckSVEEnabled() | |
5104 | * in the ARM pseudocode, which is the sve_access_check() done | |
5105 | * in our caller. We should not now return false from the caller. | |
5106 | */ | |
5107 | unallocated_encoding(s); | |
5108 | return; | |
5109 | } | |
5110 | ||
5111 | /* Load the first octaword using the normal predicated load helpers. */ | |
5112 | ||
5113 | poff = pred_full_reg_offset(s, pg); | |
5114 | if (vsz > 32) { | |
5115 | /* | |
5116 | * Zero-extend the first 32 bits of the predicate into a temporary. | |
5117 | * This avoids triggering an assert making sure we don't have bits | |
5118 | * set within a predicate beyond VQ, but we have lowered VQ to 2 | |
5119 | * for this load operation. | |
5120 | */ | |
5121 | TCGv_i64 tmp = tcg_temp_new_i64(); | |
e03b5686 | 5122 | #if HOST_BIG_ENDIAN |
12c563f6 RH |
5123 | poff += 4; |
5124 | #endif | |
5125 | tcg_gen_ld32u_i64(tmp, cpu_env, poff); | |
5126 | ||
5127 | poff = offsetof(CPUARMState, vfp.preg_tmp); | |
5128 | tcg_gen_st_i64(tmp, cpu_env, poff); | |
5129 | tcg_temp_free_i64(tmp); | |
5130 | } | |
5131 | ||
5132 | t_pg = tcg_temp_new_ptr(); | |
5133 | tcg_gen_addi_ptr(t_pg, cpu_env, poff); | |
5134 | ||
5135 | gen_helper_gvec_mem *fn | |
5136 | = ldr_fns[s->mte_active[0]][s->be_data == MO_BE][dtype][0]; | |
5137 | fn(cpu_env, t_pg, addr, tcg_constant_i32(simd_desc(32, 32, zt))); | |
5138 | ||
5139 | tcg_temp_free_ptr(t_pg); | |
5140 | ||
5141 | /* | |
5142 | * Replicate that first octaword. | |
5143 | * The replication happens in units of 32; if the full vector size | |
5144 | * is not a multiple of 32, the final bits are zeroed. | |
5145 | */ | |
5146 | doff = vec_full_reg_offset(s, zt); | |
5147 | vsz_r32 = QEMU_ALIGN_DOWN(vsz, 32); | |
5148 | if (vsz >= 64) { | |
5149 | tcg_gen_gvec_dup_mem(5, doff + 32, doff, vsz_r32 - 32, vsz_r32 - 32); | |
5150 | } | |
5151 | vsz -= vsz_r32; | |
5152 | if (vsz) { | |
5153 | tcg_gen_gvec_dup_imm(MO_64, doff + vsz_r32, vsz, vsz, 0); | |
5154 | } | |
5155 | } | |
5156 | ||
5157 | static bool trans_LD1RO_zprr(DisasContext *s, arg_rprr_load *a) | |
5158 | { | |
5159 | if (!dc_isar_feature(aa64_sve_f64mm, s)) { | |
5160 | return false; | |
5161 | } | |
5162 | if (a->rm == 31) { | |
5163 | return false; | |
5164 | } | |
5165 | if (sve_access_check(s)) { | |
5166 | TCGv_i64 addr = new_tmp_a64(s); | |
5167 | tcg_gen_shli_i64(addr, cpu_reg(s, a->rm), dtype_msz(a->dtype)); | |
5168 | tcg_gen_add_i64(addr, addr, cpu_reg_sp(s, a->rn)); | |
5169 | do_ldro(s, a->rd, a->pg, addr, a->dtype); | |
5170 | } | |
5171 | return true; | |
5172 | } | |
5173 | ||
5174 | static bool trans_LD1RO_zpri(DisasContext *s, arg_rpri_load *a) | |
5175 | { | |
5176 | if (!dc_isar_feature(aa64_sve_f64mm, s)) { | |
5177 | return false; | |
5178 | } | |
5179 | if (sve_access_check(s)) { | |
5180 | TCGv_i64 addr = new_tmp_a64(s); | |
5181 | tcg_gen_addi_i64(addr, cpu_reg_sp(s, a->rn), a->imm * 32); | |
5182 | do_ldro(s, a->rd, a->pg, addr, a->dtype); | |
5183 | } | |
5184 | return true; | |
5185 | } | |
5186 | ||
68459864 | 5187 | /* Load and broadcast element. */ |
3a7be554 | 5188 | static bool trans_LD1R_zpri(DisasContext *s, arg_rpri_load *a) |
68459864 | 5189 | { |
68459864 RH |
5190 | unsigned vsz = vec_full_reg_size(s); |
5191 | unsigned psz = pred_full_reg_size(s); | |
5192 | unsigned esz = dtype_esz[a->dtype]; | |
d0e372b0 | 5193 | unsigned msz = dtype_msz(a->dtype); |
c0ed9166 | 5194 | TCGLabel *over; |
4ac430e1 | 5195 | TCGv_i64 temp, clean_addr; |
68459864 | 5196 | |
c0ed9166 RH |
5197 | if (!sve_access_check(s)) { |
5198 | return true; | |
5199 | } | |
5200 | ||
5201 | over = gen_new_label(); | |
5202 | ||
68459864 RH |
5203 | /* If the guarding predicate has no bits set, no load occurs. */ |
5204 | if (psz <= 8) { | |
5205 | /* Reduce the pred_esz_masks value simply to reduce the | |
5206 | * size of the code generated here. | |
5207 | */ | |
5208 | uint64_t psz_mask = MAKE_64BIT_MASK(0, psz * 8); | |
5209 | temp = tcg_temp_new_i64(); | |
5210 | tcg_gen_ld_i64(temp, cpu_env, pred_full_reg_offset(s, a->pg)); | |
5211 | tcg_gen_andi_i64(temp, temp, pred_esz_masks[esz] & psz_mask); | |
5212 | tcg_gen_brcondi_i64(TCG_COND_EQ, temp, 0, over); | |
5213 | tcg_temp_free_i64(temp); | |
5214 | } else { | |
5215 | TCGv_i32 t32 = tcg_temp_new_i32(); | |
5216 | find_last_active(s, t32, esz, a->pg); | |
5217 | tcg_gen_brcondi_i32(TCG_COND_LT, t32, 0, over); | |
5218 | tcg_temp_free_i32(t32); | |
5219 | } | |
5220 | ||
5221 | /* Load the data. */ | |
5222 | temp = tcg_temp_new_i64(); | |
d0e372b0 | 5223 | tcg_gen_addi_i64(temp, cpu_reg_sp(s, a->rn), a->imm << msz); |
4ac430e1 RH |
5224 | clean_addr = gen_mte_check1(s, temp, false, true, msz); |
5225 | ||
5226 | tcg_gen_qemu_ld_i64(temp, clean_addr, get_mem_index(s), | |
0ca0f872 | 5227 | finalize_memop(s, dtype_mop[a->dtype])); |
68459864 RH |
5228 | |
5229 | /* Broadcast to *all* elements. */ | |
5230 | tcg_gen_gvec_dup_i64(esz, vec_full_reg_offset(s, a->rd), | |
5231 | vsz, vsz, temp); | |
5232 | tcg_temp_free_i64(temp); | |
5233 | ||
5234 | /* Zero the inactive elements. */ | |
5235 | gen_set_label(over); | |
60245996 | 5236 | return do_movz_zpz(s, a->rd, a->rd, a->pg, esz, false); |
68459864 RH |
5237 | } |
5238 | ||
1a039c7e RH |
5239 | static void do_st_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr, |
5240 | int msz, int esz, int nreg) | |
5241 | { | |
71b9f394 RH |
5242 | static gen_helper_gvec_mem * const fn_single[2][2][4][4] = { |
5243 | { { { gen_helper_sve_st1bb_r, | |
5244 | gen_helper_sve_st1bh_r, | |
5245 | gen_helper_sve_st1bs_r, | |
5246 | gen_helper_sve_st1bd_r }, | |
5247 | { NULL, | |
5248 | gen_helper_sve_st1hh_le_r, | |
5249 | gen_helper_sve_st1hs_le_r, | |
5250 | gen_helper_sve_st1hd_le_r }, | |
5251 | { NULL, NULL, | |
5252 | gen_helper_sve_st1ss_le_r, | |
5253 | gen_helper_sve_st1sd_le_r }, | |
5254 | { NULL, NULL, NULL, | |
5255 | gen_helper_sve_st1dd_le_r } }, | |
5256 | { { gen_helper_sve_st1bb_r, | |
5257 | gen_helper_sve_st1bh_r, | |
5258 | gen_helper_sve_st1bs_r, | |
5259 | gen_helper_sve_st1bd_r }, | |
5260 | { NULL, | |
5261 | gen_helper_sve_st1hh_be_r, | |
5262 | gen_helper_sve_st1hs_be_r, | |
5263 | gen_helper_sve_st1hd_be_r }, | |
5264 | { NULL, NULL, | |
5265 | gen_helper_sve_st1ss_be_r, | |
5266 | gen_helper_sve_st1sd_be_r }, | |
5267 | { NULL, NULL, NULL, | |
5268 | gen_helper_sve_st1dd_be_r } } }, | |
5269 | ||
5270 | { { { gen_helper_sve_st1bb_r_mte, | |
5271 | gen_helper_sve_st1bh_r_mte, | |
5272 | gen_helper_sve_st1bs_r_mte, | |
5273 | gen_helper_sve_st1bd_r_mte }, | |
5274 | { NULL, | |
5275 | gen_helper_sve_st1hh_le_r_mte, | |
5276 | gen_helper_sve_st1hs_le_r_mte, | |
5277 | gen_helper_sve_st1hd_le_r_mte }, | |
5278 | { NULL, NULL, | |
5279 | gen_helper_sve_st1ss_le_r_mte, | |
5280 | gen_helper_sve_st1sd_le_r_mte }, | |
5281 | { NULL, NULL, NULL, | |
5282 | gen_helper_sve_st1dd_le_r_mte } }, | |
5283 | { { gen_helper_sve_st1bb_r_mte, | |
5284 | gen_helper_sve_st1bh_r_mte, | |
5285 | gen_helper_sve_st1bs_r_mte, | |
5286 | gen_helper_sve_st1bd_r_mte }, | |
5287 | { NULL, | |
5288 | gen_helper_sve_st1hh_be_r_mte, | |
5289 | gen_helper_sve_st1hs_be_r_mte, | |
5290 | gen_helper_sve_st1hd_be_r_mte }, | |
5291 | { NULL, NULL, | |
5292 | gen_helper_sve_st1ss_be_r_mte, | |
5293 | gen_helper_sve_st1sd_be_r_mte }, | |
5294 | { NULL, NULL, NULL, | |
5295 | gen_helper_sve_st1dd_be_r_mte } } }, | |
1a039c7e | 5296 | }; |
71b9f394 RH |
5297 | static gen_helper_gvec_mem * const fn_multiple[2][2][3][4] = { |
5298 | { { { gen_helper_sve_st2bb_r, | |
5299 | gen_helper_sve_st2hh_le_r, | |
5300 | gen_helper_sve_st2ss_le_r, | |
5301 | gen_helper_sve_st2dd_le_r }, | |
5302 | { gen_helper_sve_st3bb_r, | |
5303 | gen_helper_sve_st3hh_le_r, | |
5304 | gen_helper_sve_st3ss_le_r, | |
5305 | gen_helper_sve_st3dd_le_r }, | |
5306 | { gen_helper_sve_st4bb_r, | |
5307 | gen_helper_sve_st4hh_le_r, | |
5308 | gen_helper_sve_st4ss_le_r, | |
5309 | gen_helper_sve_st4dd_le_r } }, | |
5310 | { { gen_helper_sve_st2bb_r, | |
5311 | gen_helper_sve_st2hh_be_r, | |
5312 | gen_helper_sve_st2ss_be_r, | |
5313 | gen_helper_sve_st2dd_be_r }, | |
5314 | { gen_helper_sve_st3bb_r, | |
5315 | gen_helper_sve_st3hh_be_r, | |
5316 | gen_helper_sve_st3ss_be_r, | |
5317 | gen_helper_sve_st3dd_be_r }, | |
5318 | { gen_helper_sve_st4bb_r, | |
5319 | gen_helper_sve_st4hh_be_r, | |
5320 | gen_helper_sve_st4ss_be_r, | |
5321 | gen_helper_sve_st4dd_be_r } } }, | |
5322 | { { { gen_helper_sve_st2bb_r_mte, | |
5323 | gen_helper_sve_st2hh_le_r_mte, | |
5324 | gen_helper_sve_st2ss_le_r_mte, | |
5325 | gen_helper_sve_st2dd_le_r_mte }, | |
5326 | { gen_helper_sve_st3bb_r_mte, | |
5327 | gen_helper_sve_st3hh_le_r_mte, | |
5328 | gen_helper_sve_st3ss_le_r_mte, | |
5329 | gen_helper_sve_st3dd_le_r_mte }, | |
5330 | { gen_helper_sve_st4bb_r_mte, | |
5331 | gen_helper_sve_st4hh_le_r_mte, | |
5332 | gen_helper_sve_st4ss_le_r_mte, | |
5333 | gen_helper_sve_st4dd_le_r_mte } }, | |
5334 | { { gen_helper_sve_st2bb_r_mte, | |
5335 | gen_helper_sve_st2hh_be_r_mte, | |
5336 | gen_helper_sve_st2ss_be_r_mte, | |
5337 | gen_helper_sve_st2dd_be_r_mte }, | |
5338 | { gen_helper_sve_st3bb_r_mte, | |
5339 | gen_helper_sve_st3hh_be_r_mte, | |
5340 | gen_helper_sve_st3ss_be_r_mte, | |
5341 | gen_helper_sve_st3dd_be_r_mte }, | |
5342 | { gen_helper_sve_st4bb_r_mte, | |
5343 | gen_helper_sve_st4hh_be_r_mte, | |
5344 | gen_helper_sve_st4ss_be_r_mte, | |
5345 | gen_helper_sve_st4dd_be_r_mte } } }, | |
1a039c7e RH |
5346 | }; |
5347 | gen_helper_gvec_mem *fn; | |
28d57f2d | 5348 | int be = s->be_data == MO_BE; |
1a039c7e RH |
5349 | |
5350 | if (nreg == 0) { | |
5351 | /* ST1 */ | |
71b9f394 RH |
5352 | fn = fn_single[s->mte_active[0]][be][msz][esz]; |
5353 | nreg = 1; | |
1a039c7e RH |
5354 | } else { |
5355 | /* ST2, ST3, ST4 -- msz == esz, enforced by encoding */ | |
5356 | assert(msz == esz); | |
71b9f394 | 5357 | fn = fn_multiple[s->mte_active[0]][be][nreg - 1][msz]; |
1a039c7e RH |
5358 | } |
5359 | assert(fn != NULL); | |
71b9f394 | 5360 | do_mem_zpa(s, zt, pg, addr, msz_dtype(s, msz), nreg, true, fn); |
1a039c7e RH |
5361 | } |
5362 | ||
3a7be554 | 5363 | static bool trans_ST_zprr(DisasContext *s, arg_rprr_store *a) |
1a039c7e RH |
5364 | { |
5365 | if (a->rm == 31 || a->msz > a->esz) { | |
5366 | return false; | |
5367 | } | |
5368 | if (sve_access_check(s)) { | |
5369 | TCGv_i64 addr = new_tmp_a64(s); | |
50ef1cbf | 5370 | tcg_gen_shli_i64(addr, cpu_reg(s, a->rm), a->msz); |
1a039c7e RH |
5371 | tcg_gen_add_i64(addr, addr, cpu_reg_sp(s, a->rn)); |
5372 | do_st_zpa(s, a->rd, a->pg, addr, a->msz, a->esz, a->nreg); | |
5373 | } | |
5374 | return true; | |
5375 | } | |
5376 | ||
3a7be554 | 5377 | static bool trans_ST_zpri(DisasContext *s, arg_rpri_store *a) |
1a039c7e RH |
5378 | { |
5379 | if (a->msz > a->esz) { | |
5380 | return false; | |
5381 | } | |
5382 | if (sve_access_check(s)) { | |
5383 | int vsz = vec_full_reg_size(s); | |
5384 | int elements = vsz >> a->esz; | |
5385 | TCGv_i64 addr = new_tmp_a64(s); | |
5386 | ||
5387 | tcg_gen_addi_i64(addr, cpu_reg_sp(s, a->rn), | |
5388 | (a->imm * elements * (a->nreg + 1)) << a->msz); | |
5389 | do_st_zpa(s, a->rd, a->pg, addr, a->msz, a->esz, a->nreg); | |
5390 | } | |
5391 | return true; | |
5392 | } | |
f6dbf62a RH |
5393 | |
5394 | /* | |
5395 | *** SVE gather loads / scatter stores | |
5396 | */ | |
5397 | ||
500d0484 | 5398 | static void do_mem_zpz(DisasContext *s, int zt, int pg, int zm, |
d28d12f0 | 5399 | int scale, TCGv_i64 scalar, int msz, bool is_write, |
500d0484 | 5400 | gen_helper_gvec_mem_scatter *fn) |
f6dbf62a RH |
5401 | { |
5402 | unsigned vsz = vec_full_reg_size(s); | |
f6dbf62a RH |
5403 | TCGv_ptr t_zm = tcg_temp_new_ptr(); |
5404 | TCGv_ptr t_pg = tcg_temp_new_ptr(); | |
5405 | TCGv_ptr t_zt = tcg_temp_new_ptr(); | |
d28d12f0 | 5406 | int desc = 0; |
500d0484 | 5407 | |
d28d12f0 RH |
5408 | if (s->mte_active[0]) { |
5409 | desc = FIELD_DP32(desc, MTEDESC, MIDX, get_mem_index(s)); | |
5410 | desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid); | |
5411 | desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma); | |
5412 | desc = FIELD_DP32(desc, MTEDESC, WRITE, is_write); | |
28f32503 | 5413 | desc = FIELD_DP32(desc, MTEDESC, SIZEM1, (1 << msz) - 1); |
d28d12f0 RH |
5414 | desc <<= SVE_MTEDESC_SHIFT; |
5415 | } | |
cdecb3fc | 5416 | desc = simd_desc(vsz, vsz, desc | scale); |
f6dbf62a RH |
5417 | |
5418 | tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, pg)); | |
5419 | tcg_gen_addi_ptr(t_zm, cpu_env, vec_full_reg_offset(s, zm)); | |
5420 | tcg_gen_addi_ptr(t_zt, cpu_env, vec_full_reg_offset(s, zt)); | |
c6a59b55 | 5421 | fn(cpu_env, t_zt, t_pg, t_zm, scalar, tcg_constant_i32(desc)); |
f6dbf62a RH |
5422 | |
5423 | tcg_temp_free_ptr(t_zt); | |
5424 | tcg_temp_free_ptr(t_zm); | |
5425 | tcg_temp_free_ptr(t_pg); | |
f6dbf62a RH |
5426 | } |
5427 | ||
d28d12f0 RH |
5428 | /* Indexed by [mte][be][ff][xs][u][msz]. */ |
5429 | static gen_helper_gvec_mem_scatter * const | |
5430 | gather_load_fn32[2][2][2][2][2][3] = { | |
5431 | { /* MTE Inactive */ | |
5432 | { /* Little-endian */ | |
5433 | { { { gen_helper_sve_ldbss_zsu, | |
5434 | gen_helper_sve_ldhss_le_zsu, | |
5435 | NULL, }, | |
5436 | { gen_helper_sve_ldbsu_zsu, | |
5437 | gen_helper_sve_ldhsu_le_zsu, | |
5438 | gen_helper_sve_ldss_le_zsu, } }, | |
5439 | { { gen_helper_sve_ldbss_zss, | |
5440 | gen_helper_sve_ldhss_le_zss, | |
5441 | NULL, }, | |
5442 | { gen_helper_sve_ldbsu_zss, | |
5443 | gen_helper_sve_ldhsu_le_zss, | |
5444 | gen_helper_sve_ldss_le_zss, } } }, | |
5445 | ||
5446 | /* First-fault */ | |
5447 | { { { gen_helper_sve_ldffbss_zsu, | |
5448 | gen_helper_sve_ldffhss_le_zsu, | |
5449 | NULL, }, | |
5450 | { gen_helper_sve_ldffbsu_zsu, | |
5451 | gen_helper_sve_ldffhsu_le_zsu, | |
5452 | gen_helper_sve_ldffss_le_zsu, } }, | |
5453 | { { gen_helper_sve_ldffbss_zss, | |
5454 | gen_helper_sve_ldffhss_le_zss, | |
5455 | NULL, }, | |
5456 | { gen_helper_sve_ldffbsu_zss, | |
5457 | gen_helper_sve_ldffhsu_le_zss, | |
5458 | gen_helper_sve_ldffss_le_zss, } } } }, | |
5459 | ||
5460 | { /* Big-endian */ | |
5461 | { { { gen_helper_sve_ldbss_zsu, | |
5462 | gen_helper_sve_ldhss_be_zsu, | |
5463 | NULL, }, | |
5464 | { gen_helper_sve_ldbsu_zsu, | |
5465 | gen_helper_sve_ldhsu_be_zsu, | |
5466 | gen_helper_sve_ldss_be_zsu, } }, | |
5467 | { { gen_helper_sve_ldbss_zss, | |
5468 | gen_helper_sve_ldhss_be_zss, | |
5469 | NULL, }, | |
5470 | { gen_helper_sve_ldbsu_zss, | |
5471 | gen_helper_sve_ldhsu_be_zss, | |
5472 | gen_helper_sve_ldss_be_zss, } } }, | |
5473 | ||
5474 | /* First-fault */ | |
5475 | { { { gen_helper_sve_ldffbss_zsu, | |
5476 | gen_helper_sve_ldffhss_be_zsu, | |
5477 | NULL, }, | |
5478 | { gen_helper_sve_ldffbsu_zsu, | |
5479 | gen_helper_sve_ldffhsu_be_zsu, | |
5480 | gen_helper_sve_ldffss_be_zsu, } }, | |
5481 | { { gen_helper_sve_ldffbss_zss, | |
5482 | gen_helper_sve_ldffhss_be_zss, | |
5483 | NULL, }, | |
5484 | { gen_helper_sve_ldffbsu_zss, | |
5485 | gen_helper_sve_ldffhsu_be_zss, | |
5486 | gen_helper_sve_ldffss_be_zss, } } } } }, | |
5487 | { /* MTE Active */ | |
5488 | { /* Little-endian */ | |
5489 | { { { gen_helper_sve_ldbss_zsu_mte, | |
5490 | gen_helper_sve_ldhss_le_zsu_mte, | |
5491 | NULL, }, | |
5492 | { gen_helper_sve_ldbsu_zsu_mte, | |
5493 | gen_helper_sve_ldhsu_le_zsu_mte, | |
5494 | gen_helper_sve_ldss_le_zsu_mte, } }, | |
5495 | { { gen_helper_sve_ldbss_zss_mte, | |
5496 | gen_helper_sve_ldhss_le_zss_mte, | |
5497 | NULL, }, | |
5498 | { gen_helper_sve_ldbsu_zss_mte, | |
5499 | gen_helper_sve_ldhsu_le_zss_mte, | |
5500 | gen_helper_sve_ldss_le_zss_mte, } } }, | |
5501 | ||
5502 | /* First-fault */ | |
5503 | { { { gen_helper_sve_ldffbss_zsu_mte, | |
5504 | gen_helper_sve_ldffhss_le_zsu_mte, | |
5505 | NULL, }, | |
5506 | { gen_helper_sve_ldffbsu_zsu_mte, | |
5507 | gen_helper_sve_ldffhsu_le_zsu_mte, | |
5508 | gen_helper_sve_ldffss_le_zsu_mte, } }, | |
5509 | { { gen_helper_sve_ldffbss_zss_mte, | |
5510 | gen_helper_sve_ldffhss_le_zss_mte, | |
5511 | NULL, }, | |
5512 | { gen_helper_sve_ldffbsu_zss_mte, | |
5513 | gen_helper_sve_ldffhsu_le_zss_mte, | |
5514 | gen_helper_sve_ldffss_le_zss_mte, } } } }, | |
5515 | ||
5516 | { /* Big-endian */ | |
5517 | { { { gen_helper_sve_ldbss_zsu_mte, | |
5518 | gen_helper_sve_ldhss_be_zsu_mte, | |
5519 | NULL, }, | |
5520 | { gen_helper_sve_ldbsu_zsu_mte, | |
5521 | gen_helper_sve_ldhsu_be_zsu_mte, | |
5522 | gen_helper_sve_ldss_be_zsu_mte, } }, | |
5523 | { { gen_helper_sve_ldbss_zss_mte, | |
5524 | gen_helper_sve_ldhss_be_zss_mte, | |
5525 | NULL, }, | |
5526 | { gen_helper_sve_ldbsu_zss_mte, | |
5527 | gen_helper_sve_ldhsu_be_zss_mte, | |
5528 | gen_helper_sve_ldss_be_zss_mte, } } }, | |
5529 | ||
5530 | /* First-fault */ | |
5531 | { { { gen_helper_sve_ldffbss_zsu_mte, | |
5532 | gen_helper_sve_ldffhss_be_zsu_mte, | |
5533 | NULL, }, | |
5534 | { gen_helper_sve_ldffbsu_zsu_mte, | |
5535 | gen_helper_sve_ldffhsu_be_zsu_mte, | |
5536 | gen_helper_sve_ldffss_be_zsu_mte, } }, | |
5537 | { { gen_helper_sve_ldffbss_zss_mte, | |
5538 | gen_helper_sve_ldffhss_be_zss_mte, | |
5539 | NULL, }, | |
5540 | { gen_helper_sve_ldffbsu_zss_mte, | |
5541 | gen_helper_sve_ldffhsu_be_zss_mte, | |
5542 | gen_helper_sve_ldffss_be_zss_mte, } } } } }, | |
673e9fa6 RH |
5543 | }; |
5544 | ||
5545 | /* Note that we overload xs=2 to indicate 64-bit offset. */ | |
d28d12f0 RH |
5546 | static gen_helper_gvec_mem_scatter * const |
5547 | gather_load_fn64[2][2][2][3][2][4] = { | |
5548 | { /* MTE Inactive */ | |
5549 | { /* Little-endian */ | |
5550 | { { { gen_helper_sve_ldbds_zsu, | |
5551 | gen_helper_sve_ldhds_le_zsu, | |
5552 | gen_helper_sve_ldsds_le_zsu, | |
5553 | NULL, }, | |
5554 | { gen_helper_sve_ldbdu_zsu, | |
5555 | gen_helper_sve_ldhdu_le_zsu, | |
5556 | gen_helper_sve_ldsdu_le_zsu, | |
5557 | gen_helper_sve_lddd_le_zsu, } }, | |
5558 | { { gen_helper_sve_ldbds_zss, | |
5559 | gen_helper_sve_ldhds_le_zss, | |
5560 | gen_helper_sve_ldsds_le_zss, | |
5561 | NULL, }, | |
5562 | { gen_helper_sve_ldbdu_zss, | |
5563 | gen_helper_sve_ldhdu_le_zss, | |
5564 | gen_helper_sve_ldsdu_le_zss, | |
5565 | gen_helper_sve_lddd_le_zss, } }, | |
5566 | { { gen_helper_sve_ldbds_zd, | |
5567 | gen_helper_sve_ldhds_le_zd, | |
5568 | gen_helper_sve_ldsds_le_zd, | |
5569 | NULL, }, | |
5570 | { gen_helper_sve_ldbdu_zd, | |
5571 | gen_helper_sve_ldhdu_le_zd, | |
5572 | gen_helper_sve_ldsdu_le_zd, | |
5573 | gen_helper_sve_lddd_le_zd, } } }, | |
5574 | ||
5575 | /* First-fault */ | |
5576 | { { { gen_helper_sve_ldffbds_zsu, | |
5577 | gen_helper_sve_ldffhds_le_zsu, | |
5578 | gen_helper_sve_ldffsds_le_zsu, | |
5579 | NULL, }, | |
5580 | { gen_helper_sve_ldffbdu_zsu, | |
5581 | gen_helper_sve_ldffhdu_le_zsu, | |
5582 | gen_helper_sve_ldffsdu_le_zsu, | |
5583 | gen_helper_sve_ldffdd_le_zsu, } }, | |
5584 | { { gen_helper_sve_ldffbds_zss, | |
5585 | gen_helper_sve_ldffhds_le_zss, | |
5586 | gen_helper_sve_ldffsds_le_zss, | |
5587 | NULL, }, | |
5588 | { gen_helper_sve_ldffbdu_zss, | |
5589 | gen_helper_sve_ldffhdu_le_zss, | |
5590 | gen_helper_sve_ldffsdu_le_zss, | |
5591 | gen_helper_sve_ldffdd_le_zss, } }, | |
5592 | { { gen_helper_sve_ldffbds_zd, | |
5593 | gen_helper_sve_ldffhds_le_zd, | |
5594 | gen_helper_sve_ldffsds_le_zd, | |
5595 | NULL, }, | |
5596 | { gen_helper_sve_ldffbdu_zd, | |
5597 | gen_helper_sve_ldffhdu_le_zd, | |
5598 | gen_helper_sve_ldffsdu_le_zd, | |
5599 | gen_helper_sve_ldffdd_le_zd, } } } }, | |
5600 | { /* Big-endian */ | |
5601 | { { { gen_helper_sve_ldbds_zsu, | |
5602 | gen_helper_sve_ldhds_be_zsu, | |
5603 | gen_helper_sve_ldsds_be_zsu, | |
5604 | NULL, }, | |
5605 | { gen_helper_sve_ldbdu_zsu, | |
5606 | gen_helper_sve_ldhdu_be_zsu, | |
5607 | gen_helper_sve_ldsdu_be_zsu, | |
5608 | gen_helper_sve_lddd_be_zsu, } }, | |
5609 | { { gen_helper_sve_ldbds_zss, | |
5610 | gen_helper_sve_ldhds_be_zss, | |
5611 | gen_helper_sve_ldsds_be_zss, | |
5612 | NULL, }, | |
5613 | { gen_helper_sve_ldbdu_zss, | |
5614 | gen_helper_sve_ldhdu_be_zss, | |
5615 | gen_helper_sve_ldsdu_be_zss, | |
5616 | gen_helper_sve_lddd_be_zss, } }, | |
5617 | { { gen_helper_sve_ldbds_zd, | |
5618 | gen_helper_sve_ldhds_be_zd, | |
5619 | gen_helper_sve_ldsds_be_zd, | |
5620 | NULL, }, | |
5621 | { gen_helper_sve_ldbdu_zd, | |
5622 | gen_helper_sve_ldhdu_be_zd, | |
5623 | gen_helper_sve_ldsdu_be_zd, | |
5624 | gen_helper_sve_lddd_be_zd, } } }, | |
5625 | ||
5626 | /* First-fault */ | |
5627 | { { { gen_helper_sve_ldffbds_zsu, | |
5628 | gen_helper_sve_ldffhds_be_zsu, | |
5629 | gen_helper_sve_ldffsds_be_zsu, | |
5630 | NULL, }, | |
5631 | { gen_helper_sve_ldffbdu_zsu, | |
5632 | gen_helper_sve_ldffhdu_be_zsu, | |
5633 | gen_helper_sve_ldffsdu_be_zsu, | |
5634 | gen_helper_sve_ldffdd_be_zsu, } }, | |
5635 | { { gen_helper_sve_ldffbds_zss, | |
5636 | gen_helper_sve_ldffhds_be_zss, | |
5637 | gen_helper_sve_ldffsds_be_zss, | |
5638 | NULL, }, | |
5639 | { gen_helper_sve_ldffbdu_zss, | |
5640 | gen_helper_sve_ldffhdu_be_zss, | |
5641 | gen_helper_sve_ldffsdu_be_zss, | |
5642 | gen_helper_sve_ldffdd_be_zss, } }, | |
5643 | { { gen_helper_sve_ldffbds_zd, | |
5644 | gen_helper_sve_ldffhds_be_zd, | |
5645 | gen_helper_sve_ldffsds_be_zd, | |
5646 | NULL, }, | |
5647 | { gen_helper_sve_ldffbdu_zd, | |
5648 | gen_helper_sve_ldffhdu_be_zd, | |
5649 | gen_helper_sve_ldffsdu_be_zd, | |
5650 | gen_helper_sve_ldffdd_be_zd, } } } } }, | |
5651 | { /* MTE Active */ | |
5652 | { /* Little-endian */ | |
5653 | { { { gen_helper_sve_ldbds_zsu_mte, | |
5654 | gen_helper_sve_ldhds_le_zsu_mte, | |
5655 | gen_helper_sve_ldsds_le_zsu_mte, | |
5656 | NULL, }, | |
5657 | { gen_helper_sve_ldbdu_zsu_mte, | |
5658 | gen_helper_sve_ldhdu_le_zsu_mte, | |
5659 | gen_helper_sve_ldsdu_le_zsu_mte, | |
5660 | gen_helper_sve_lddd_le_zsu_mte, } }, | |
5661 | { { gen_helper_sve_ldbds_zss_mte, | |
5662 | gen_helper_sve_ldhds_le_zss_mte, | |
5663 | gen_helper_sve_ldsds_le_zss_mte, | |
5664 | NULL, }, | |
5665 | { gen_helper_sve_ldbdu_zss_mte, | |
5666 | gen_helper_sve_ldhdu_le_zss_mte, | |
5667 | gen_helper_sve_ldsdu_le_zss_mte, | |
5668 | gen_helper_sve_lddd_le_zss_mte, } }, | |
5669 | { { gen_helper_sve_ldbds_zd_mte, | |
5670 | gen_helper_sve_ldhds_le_zd_mte, | |
5671 | gen_helper_sve_ldsds_le_zd_mte, | |
5672 | NULL, }, | |
5673 | { gen_helper_sve_ldbdu_zd_mte, | |
5674 | gen_helper_sve_ldhdu_le_zd_mte, | |
5675 | gen_helper_sve_ldsdu_le_zd_mte, | |
5676 | gen_helper_sve_lddd_le_zd_mte, } } }, | |
5677 | ||
5678 | /* First-fault */ | |
5679 | { { { gen_helper_sve_ldffbds_zsu_mte, | |
5680 | gen_helper_sve_ldffhds_le_zsu_mte, | |
5681 | gen_helper_sve_ldffsds_le_zsu_mte, | |
5682 | NULL, }, | |
5683 | { gen_helper_sve_ldffbdu_zsu_mte, | |
5684 | gen_helper_sve_ldffhdu_le_zsu_mte, | |
5685 | gen_helper_sve_ldffsdu_le_zsu_mte, | |
5686 | gen_helper_sve_ldffdd_le_zsu_mte, } }, | |
5687 | { { gen_helper_sve_ldffbds_zss_mte, | |
5688 | gen_helper_sve_ldffhds_le_zss_mte, | |
5689 | gen_helper_sve_ldffsds_le_zss_mte, | |
5690 | NULL, }, | |
5691 | { gen_helper_sve_ldffbdu_zss_mte, | |
5692 | gen_helper_sve_ldffhdu_le_zss_mte, | |
5693 | gen_helper_sve_ldffsdu_le_zss_mte, | |
5694 | gen_helper_sve_ldffdd_le_zss_mte, } }, | |
5695 | { { gen_helper_sve_ldffbds_zd_mte, | |
5696 | gen_helper_sve_ldffhds_le_zd_mte, | |
5697 | gen_helper_sve_ldffsds_le_zd_mte, | |
5698 | NULL, }, | |
5699 | { gen_helper_sve_ldffbdu_zd_mte, | |
5700 | gen_helper_sve_ldffhdu_le_zd_mte, | |
5701 | gen_helper_sve_ldffsdu_le_zd_mte, | |
5702 | gen_helper_sve_ldffdd_le_zd_mte, } } } }, | |
5703 | { /* Big-endian */ | |
5704 | { { { gen_helper_sve_ldbds_zsu_mte, | |
5705 | gen_helper_sve_ldhds_be_zsu_mte, | |
5706 | gen_helper_sve_ldsds_be_zsu_mte, | |
5707 | NULL, }, | |
5708 | { gen_helper_sve_ldbdu_zsu_mte, | |
5709 | gen_helper_sve_ldhdu_be_zsu_mte, | |
5710 | gen_helper_sve_ldsdu_be_zsu_mte, | |
5711 | gen_helper_sve_lddd_be_zsu_mte, } }, | |
5712 | { { gen_helper_sve_ldbds_zss_mte, | |
5713 | gen_helper_sve_ldhds_be_zss_mte, | |
5714 | gen_helper_sve_ldsds_be_zss_mte, | |
5715 | NULL, }, | |
5716 | { gen_helper_sve_ldbdu_zss_mte, | |
5717 | gen_helper_sve_ldhdu_be_zss_mte, | |
5718 | gen_helper_sve_ldsdu_be_zss_mte, | |
5719 | gen_helper_sve_lddd_be_zss_mte, } }, | |
5720 | { { gen_helper_sve_ldbds_zd_mte, | |
5721 | gen_helper_sve_ldhds_be_zd_mte, | |
5722 | gen_helper_sve_ldsds_be_zd_mte, | |
5723 | NULL, }, | |
5724 | { gen_helper_sve_ldbdu_zd_mte, | |
5725 | gen_helper_sve_ldhdu_be_zd_mte, | |
5726 | gen_helper_sve_ldsdu_be_zd_mte, | |
5727 | gen_helper_sve_lddd_be_zd_mte, } } }, | |
5728 | ||
5729 | /* First-fault */ | |
5730 | { { { gen_helper_sve_ldffbds_zsu_mte, | |
5731 | gen_helper_sve_ldffhds_be_zsu_mte, | |
5732 | gen_helper_sve_ldffsds_be_zsu_mte, | |
5733 | NULL, }, | |
5734 | { gen_helper_sve_ldffbdu_zsu_mte, | |
5735 | gen_helper_sve_ldffhdu_be_zsu_mte, | |
5736 | gen_helper_sve_ldffsdu_be_zsu_mte, | |
5737 | gen_helper_sve_ldffdd_be_zsu_mte, } }, | |
5738 | { { gen_helper_sve_ldffbds_zss_mte, | |
5739 | gen_helper_sve_ldffhds_be_zss_mte, | |
5740 | gen_helper_sve_ldffsds_be_zss_mte, | |
5741 | NULL, }, | |
5742 | { gen_helper_sve_ldffbdu_zss_mte, | |
5743 | gen_helper_sve_ldffhdu_be_zss_mte, | |
5744 | gen_helper_sve_ldffsdu_be_zss_mte, | |
5745 | gen_helper_sve_ldffdd_be_zss_mte, } }, | |
5746 | { { gen_helper_sve_ldffbds_zd_mte, | |
5747 | gen_helper_sve_ldffhds_be_zd_mte, | |
5748 | gen_helper_sve_ldffsds_be_zd_mte, | |
5749 | NULL, }, | |
5750 | { gen_helper_sve_ldffbdu_zd_mte, | |
5751 | gen_helper_sve_ldffhdu_be_zd_mte, | |
5752 | gen_helper_sve_ldffsdu_be_zd_mte, | |
5753 | gen_helper_sve_ldffdd_be_zd_mte, } } } } }, | |
673e9fa6 RH |
5754 | }; |
5755 | ||
3a7be554 | 5756 | static bool trans_LD1_zprz(DisasContext *s, arg_LD1_zprz *a) |
673e9fa6 RH |
5757 | { |
5758 | gen_helper_gvec_mem_scatter *fn = NULL; | |
d28d12f0 RH |
5759 | bool be = s->be_data == MO_BE; |
5760 | bool mte = s->mte_active[0]; | |
673e9fa6 RH |
5761 | |
5762 | if (!sve_access_check(s)) { | |
5763 | return true; | |
5764 | } | |
5765 | ||
5766 | switch (a->esz) { | |
5767 | case MO_32: | |
d28d12f0 | 5768 | fn = gather_load_fn32[mte][be][a->ff][a->xs][a->u][a->msz]; |
673e9fa6 RH |
5769 | break; |
5770 | case MO_64: | |
d28d12f0 | 5771 | fn = gather_load_fn64[mte][be][a->ff][a->xs][a->u][a->msz]; |
673e9fa6 RH |
5772 | break; |
5773 | } | |
5774 | assert(fn != NULL); | |
5775 | ||
5776 | do_mem_zpz(s, a->rd, a->pg, a->rm, a->scale * a->msz, | |
d28d12f0 | 5777 | cpu_reg_sp(s, a->rn), a->msz, false, fn); |
673e9fa6 RH |
5778 | return true; |
5779 | } | |
5780 | ||
3a7be554 | 5781 | static bool trans_LD1_zpiz(DisasContext *s, arg_LD1_zpiz *a) |
673e9fa6 RH |
5782 | { |
5783 | gen_helper_gvec_mem_scatter *fn = NULL; | |
d28d12f0 RH |
5784 | bool be = s->be_data == MO_BE; |
5785 | bool mte = s->mte_active[0]; | |
673e9fa6 RH |
5786 | |
5787 | if (a->esz < a->msz || (a->esz == a->msz && !a->u)) { | |
5788 | return false; | |
5789 | } | |
5790 | if (!sve_access_check(s)) { | |
5791 | return true; | |
5792 | } | |
5793 | ||
5794 | switch (a->esz) { | |
5795 | case MO_32: | |
d28d12f0 | 5796 | fn = gather_load_fn32[mte][be][a->ff][0][a->u][a->msz]; |
673e9fa6 RH |
5797 | break; |
5798 | case MO_64: | |
d28d12f0 | 5799 | fn = gather_load_fn64[mte][be][a->ff][2][a->u][a->msz]; |
673e9fa6 RH |
5800 | break; |
5801 | } | |
5802 | assert(fn != NULL); | |
5803 | ||
5804 | /* Treat LD1_zpiz (zn[x] + imm) the same way as LD1_zprz (rn + zm[x]) | |
5805 | * by loading the immediate into the scalar parameter. | |
5806 | */ | |
2ccdf94f RH |
5807 | do_mem_zpz(s, a->rd, a->pg, a->rn, 0, |
5808 | tcg_constant_i64(a->imm << a->msz), a->msz, false, fn); | |
673e9fa6 RH |
5809 | return true; |
5810 | } | |
5811 | ||
cf327449 SL |
5812 | static bool trans_LDNT1_zprz(DisasContext *s, arg_LD1_zprz *a) |
5813 | { | |
b17ab470 RH |
5814 | gen_helper_gvec_mem_scatter *fn = NULL; |
5815 | bool be = s->be_data == MO_BE; | |
5816 | bool mte = s->mte_active[0]; | |
5817 | ||
5818 | if (a->esz < a->msz + !a->u) { | |
5819 | return false; | |
5820 | } | |
cf327449 SL |
5821 | if (!dc_isar_feature(aa64_sve2, s)) { |
5822 | return false; | |
5823 | } | |
b17ab470 RH |
5824 | if (!sve_access_check(s)) { |
5825 | return true; | |
5826 | } | |
5827 | ||
5828 | switch (a->esz) { | |
5829 | case MO_32: | |
5830 | fn = gather_load_fn32[mte][be][0][0][a->u][a->msz]; | |
5831 | break; | |
5832 | case MO_64: | |
5833 | fn = gather_load_fn64[mte][be][0][2][a->u][a->msz]; | |
5834 | break; | |
5835 | } | |
5836 | assert(fn != NULL); | |
5837 | ||
5838 | do_mem_zpz(s, a->rd, a->pg, a->rn, 0, | |
5839 | cpu_reg(s, a->rm), a->msz, false, fn); | |
5840 | return true; | |
cf327449 SL |
5841 | } |
5842 | ||
d28d12f0 RH |
5843 | /* Indexed by [mte][be][xs][msz]. */ |
5844 | static gen_helper_gvec_mem_scatter * const scatter_store_fn32[2][2][2][3] = { | |
5845 | { /* MTE Inactive */ | |
5846 | { /* Little-endian */ | |
5847 | { gen_helper_sve_stbs_zsu, | |
5848 | gen_helper_sve_sths_le_zsu, | |
5849 | gen_helper_sve_stss_le_zsu, }, | |
5850 | { gen_helper_sve_stbs_zss, | |
5851 | gen_helper_sve_sths_le_zss, | |
5852 | gen_helper_sve_stss_le_zss, } }, | |
5853 | { /* Big-endian */ | |
5854 | { gen_helper_sve_stbs_zsu, | |
5855 | gen_helper_sve_sths_be_zsu, | |
5856 | gen_helper_sve_stss_be_zsu, }, | |
5857 | { gen_helper_sve_stbs_zss, | |
5858 | gen_helper_sve_sths_be_zss, | |
5859 | gen_helper_sve_stss_be_zss, } } }, | |
5860 | { /* MTE Active */ | |
5861 | { /* Little-endian */ | |
5862 | { gen_helper_sve_stbs_zsu_mte, | |
5863 | gen_helper_sve_sths_le_zsu_mte, | |
5864 | gen_helper_sve_stss_le_zsu_mte, }, | |
5865 | { gen_helper_sve_stbs_zss_mte, | |
5866 | gen_helper_sve_sths_le_zss_mte, | |
5867 | gen_helper_sve_stss_le_zss_mte, } }, | |
5868 | { /* Big-endian */ | |
5869 | { gen_helper_sve_stbs_zsu_mte, | |
5870 | gen_helper_sve_sths_be_zsu_mte, | |
5871 | gen_helper_sve_stss_be_zsu_mte, }, | |
5872 | { gen_helper_sve_stbs_zss_mte, | |
5873 | gen_helper_sve_sths_be_zss_mte, | |
5874 | gen_helper_sve_stss_be_zss_mte, } } }, | |
408ecde9 RH |
5875 | }; |
5876 | ||
5877 | /* Note that we overload xs=2 to indicate 64-bit offset. */ | |
d28d12f0 RH |
5878 | static gen_helper_gvec_mem_scatter * const scatter_store_fn64[2][2][3][4] = { |
5879 | { /* MTE Inactive */ | |
5880 | { /* Little-endian */ | |
5881 | { gen_helper_sve_stbd_zsu, | |
5882 | gen_helper_sve_sthd_le_zsu, | |
5883 | gen_helper_sve_stsd_le_zsu, | |
5884 | gen_helper_sve_stdd_le_zsu, }, | |
5885 | { gen_helper_sve_stbd_zss, | |
5886 | gen_helper_sve_sthd_le_zss, | |
5887 | gen_helper_sve_stsd_le_zss, | |
5888 | gen_helper_sve_stdd_le_zss, }, | |
5889 | { gen_helper_sve_stbd_zd, | |
5890 | gen_helper_sve_sthd_le_zd, | |
5891 | gen_helper_sve_stsd_le_zd, | |
5892 | gen_helper_sve_stdd_le_zd, } }, | |
5893 | { /* Big-endian */ | |
5894 | { gen_helper_sve_stbd_zsu, | |
5895 | gen_helper_sve_sthd_be_zsu, | |
5896 | gen_helper_sve_stsd_be_zsu, | |
5897 | gen_helper_sve_stdd_be_zsu, }, | |
5898 | { gen_helper_sve_stbd_zss, | |
5899 | gen_helper_sve_sthd_be_zss, | |
5900 | gen_helper_sve_stsd_be_zss, | |
5901 | gen_helper_sve_stdd_be_zss, }, | |
5902 | { gen_helper_sve_stbd_zd, | |
5903 | gen_helper_sve_sthd_be_zd, | |
5904 | gen_helper_sve_stsd_be_zd, | |
5905 | gen_helper_sve_stdd_be_zd, } } }, | |
5906 | { /* MTE Inactive */ | |
5907 | { /* Little-endian */ | |
5908 | { gen_helper_sve_stbd_zsu_mte, | |
5909 | gen_helper_sve_sthd_le_zsu_mte, | |
5910 | gen_helper_sve_stsd_le_zsu_mte, | |
5911 | gen_helper_sve_stdd_le_zsu_mte, }, | |
5912 | { gen_helper_sve_stbd_zss_mte, | |
5913 | gen_helper_sve_sthd_le_zss_mte, | |
5914 | gen_helper_sve_stsd_le_zss_mte, | |
5915 | gen_helper_sve_stdd_le_zss_mte, }, | |
5916 | { gen_helper_sve_stbd_zd_mte, | |
5917 | gen_helper_sve_sthd_le_zd_mte, | |
5918 | gen_helper_sve_stsd_le_zd_mte, | |
5919 | gen_helper_sve_stdd_le_zd_mte, } }, | |
5920 | { /* Big-endian */ | |
5921 | { gen_helper_sve_stbd_zsu_mte, | |
5922 | gen_helper_sve_sthd_be_zsu_mte, | |
5923 | gen_helper_sve_stsd_be_zsu_mte, | |
5924 | gen_helper_sve_stdd_be_zsu_mte, }, | |
5925 | { gen_helper_sve_stbd_zss_mte, | |
5926 | gen_helper_sve_sthd_be_zss_mte, | |
5927 | gen_helper_sve_stsd_be_zss_mte, | |
5928 | gen_helper_sve_stdd_be_zss_mte, }, | |
5929 | { gen_helper_sve_stbd_zd_mte, | |
5930 | gen_helper_sve_sthd_be_zd_mte, | |
5931 | gen_helper_sve_stsd_be_zd_mte, | |
5932 | gen_helper_sve_stdd_be_zd_mte, } } }, | |
408ecde9 RH |
5933 | }; |
5934 | ||
3a7be554 | 5935 | static bool trans_ST1_zprz(DisasContext *s, arg_ST1_zprz *a) |
f6dbf62a | 5936 | { |
f6dbf62a | 5937 | gen_helper_gvec_mem_scatter *fn; |
d28d12f0 RH |
5938 | bool be = s->be_data == MO_BE; |
5939 | bool mte = s->mte_active[0]; | |
f6dbf62a RH |
5940 | |
5941 | if (a->esz < a->msz || (a->msz == 0 && a->scale)) { | |
5942 | return false; | |
5943 | } | |
5944 | if (!sve_access_check(s)) { | |
5945 | return true; | |
5946 | } | |
5947 | switch (a->esz) { | |
5948 | case MO_32: | |
d28d12f0 | 5949 | fn = scatter_store_fn32[mte][be][a->xs][a->msz]; |
f6dbf62a RH |
5950 | break; |
5951 | case MO_64: | |
d28d12f0 | 5952 | fn = scatter_store_fn64[mte][be][a->xs][a->msz]; |
f6dbf62a RH |
5953 | break; |
5954 | default: | |
5955 | g_assert_not_reached(); | |
5956 | } | |
5957 | do_mem_zpz(s, a->rd, a->pg, a->rm, a->scale * a->msz, | |
d28d12f0 | 5958 | cpu_reg_sp(s, a->rn), a->msz, true, fn); |
f6dbf62a RH |
5959 | return true; |
5960 | } | |
dec6cf6b | 5961 | |
3a7be554 | 5962 | static bool trans_ST1_zpiz(DisasContext *s, arg_ST1_zpiz *a) |
408ecde9 RH |
5963 | { |
5964 | gen_helper_gvec_mem_scatter *fn = NULL; | |
d28d12f0 RH |
5965 | bool be = s->be_data == MO_BE; |
5966 | bool mte = s->mte_active[0]; | |
408ecde9 RH |
5967 | |
5968 | if (a->esz < a->msz) { | |
5969 | return false; | |
5970 | } | |
5971 | if (!sve_access_check(s)) { | |
5972 | return true; | |
5973 | } | |
5974 | ||
5975 | switch (a->esz) { | |
5976 | case MO_32: | |
d28d12f0 | 5977 | fn = scatter_store_fn32[mte][be][0][a->msz]; |
408ecde9 RH |
5978 | break; |
5979 | case MO_64: | |
d28d12f0 | 5980 | fn = scatter_store_fn64[mte][be][2][a->msz]; |
408ecde9 RH |
5981 | break; |
5982 | } | |
5983 | assert(fn != NULL); | |
5984 | ||
5985 | /* Treat ST1_zpiz (zn[x] + imm) the same way as ST1_zprz (rn + zm[x]) | |
5986 | * by loading the immediate into the scalar parameter. | |
5987 | */ | |
2ccdf94f RH |
5988 | do_mem_zpz(s, a->rd, a->pg, a->rn, 0, |
5989 | tcg_constant_i64(a->imm << a->msz), a->msz, true, fn); | |
408ecde9 RH |
5990 | return true; |
5991 | } | |
5992 | ||
6ebca45f SL |
5993 | static bool trans_STNT1_zprz(DisasContext *s, arg_ST1_zprz *a) |
5994 | { | |
b17ab470 RH |
5995 | gen_helper_gvec_mem_scatter *fn; |
5996 | bool be = s->be_data == MO_BE; | |
5997 | bool mte = s->mte_active[0]; | |
5998 | ||
5999 | if (a->esz < a->msz) { | |
6000 | return false; | |
6001 | } | |
6ebca45f SL |
6002 | if (!dc_isar_feature(aa64_sve2, s)) { |
6003 | return false; | |
6004 | } | |
b17ab470 RH |
6005 | if (!sve_access_check(s)) { |
6006 | return true; | |
6007 | } | |
6008 | ||
6009 | switch (a->esz) { | |
6010 | case MO_32: | |
6011 | fn = scatter_store_fn32[mte][be][0][a->msz]; | |
6012 | break; | |
6013 | case MO_64: | |
6014 | fn = scatter_store_fn64[mte][be][2][a->msz]; | |
6015 | break; | |
6016 | default: | |
6017 | g_assert_not_reached(); | |
6018 | } | |
6019 | ||
6020 | do_mem_zpz(s, a->rd, a->pg, a->rn, 0, | |
6021 | cpu_reg(s, a->rm), a->msz, true, fn); | |
6022 | return true; | |
6ebca45f SL |
6023 | } |
6024 | ||
dec6cf6b RH |
6025 | /* |
6026 | * Prefetches | |
6027 | */ | |
6028 | ||
3a7be554 | 6029 | static bool trans_PRF(DisasContext *s, arg_PRF *a) |
dec6cf6b RH |
6030 | { |
6031 | /* Prefetch is a nop within QEMU. */ | |
2f95a3b0 | 6032 | (void)sve_access_check(s); |
dec6cf6b RH |
6033 | return true; |
6034 | } | |
6035 | ||
3a7be554 | 6036 | static bool trans_PRF_rr(DisasContext *s, arg_PRF_rr *a) |
dec6cf6b RH |
6037 | { |
6038 | if (a->rm == 31) { | |
6039 | return false; | |
6040 | } | |
6041 | /* Prefetch is a nop within QEMU. */ | |
2f95a3b0 | 6042 | (void)sve_access_check(s); |
dec6cf6b RH |
6043 | return true; |
6044 | } | |
a2103582 RH |
6045 | |
6046 | /* | |
6047 | * Move Prefix | |
6048 | * | |
6049 | * TODO: The implementation so far could handle predicated merging movprfx. | |
6050 | * The helper functions as written take an extra source register to | |
6051 | * use in the operation, but the result is only written when predication | |
6052 | * succeeds. For unpredicated movprfx, we need to rearrange the helpers | |
6053 | * to allow the final write back to the destination to be unconditional. | |
6054 | * For predicated zeroing movprfx, we need to rearrange the helpers to | |
6055 | * allow the final write back to zero inactives. | |
6056 | * | |
6057 | * In the meantime, just emit the moves. | |
6058 | */ | |
6059 | ||
3a7be554 | 6060 | static bool trans_MOVPRFX(DisasContext *s, arg_MOVPRFX *a) |
a2103582 RH |
6061 | { |
6062 | return do_mov_z(s, a->rd, a->rn); | |
6063 | } | |
6064 | ||
3a7be554 | 6065 | static bool trans_MOVPRFX_m(DisasContext *s, arg_rpr_esz *a) |
a2103582 | 6066 | { |
68cc4ee3 | 6067 | return do_sel_z(s, a->rd, a->rn, a->rd, a->pg, a->esz); |
a2103582 RH |
6068 | } |
6069 | ||
3a7be554 | 6070 | static bool trans_MOVPRFX_z(DisasContext *s, arg_rpr_esz *a) |
a2103582 | 6071 | { |
60245996 | 6072 | return do_movz_zpz(s, a->rd, a->rn, a->pg, a->esz, false); |
a2103582 | 6073 | } |
5dad1ba5 RH |
6074 | |
6075 | /* | |
6076 | * SVE2 Integer Multiply - Unpredicated | |
6077 | */ | |
6078 | ||
b262215b | 6079 | TRANS_FEAT(MUL_zzz, aa64_sve2, gen_gvec_fn_arg_zzz, tcg_gen_gvec_mul, a) |
5dad1ba5 | 6080 | |
bd394cf5 RH |
6081 | static gen_helper_gvec_3 * const smulh_zzz_fns[4] = { |
6082 | gen_helper_gvec_smulh_b, gen_helper_gvec_smulh_h, | |
6083 | gen_helper_gvec_smulh_s, gen_helper_gvec_smulh_d, | |
6084 | }; | |
6085 | TRANS_FEAT(SMULH_zzz, aa64_sve2, gen_gvec_ool_arg_zzz, | |
6086 | smulh_zzz_fns[a->esz], a, 0) | |
5dad1ba5 | 6087 | |
bd394cf5 RH |
6088 | static gen_helper_gvec_3 * const umulh_zzz_fns[4] = { |
6089 | gen_helper_gvec_umulh_b, gen_helper_gvec_umulh_h, | |
6090 | gen_helper_gvec_umulh_s, gen_helper_gvec_umulh_d, | |
6091 | }; | |
6092 | TRANS_FEAT(UMULH_zzz, aa64_sve2, gen_gvec_ool_arg_zzz, | |
6093 | umulh_zzz_fns[a->esz], a, 0) | |
5dad1ba5 | 6094 | |
bd394cf5 RH |
6095 | TRANS_FEAT(PMUL_zzz, aa64_sve2, gen_gvec_ool_arg_zzz, |
6096 | gen_helper_gvec_pmul_b, a, 0) | |
5dad1ba5 | 6097 | |
bd394cf5 RH |
6098 | static gen_helper_gvec_3 * const sqdmulh_zzz_fns[4] = { |
6099 | gen_helper_sve2_sqdmulh_b, gen_helper_sve2_sqdmulh_h, | |
6100 | gen_helper_sve2_sqdmulh_s, gen_helper_sve2_sqdmulh_d, | |
6101 | }; | |
6102 | TRANS_FEAT(SQDMULH_zzz, aa64_sve2, gen_gvec_ool_arg_zzz, | |
6103 | sqdmulh_zzz_fns[a->esz], a, 0) | |
169d7c58 | 6104 | |
bd394cf5 RH |
6105 | static gen_helper_gvec_3 * const sqrdmulh_zzz_fns[4] = { |
6106 | gen_helper_sve2_sqrdmulh_b, gen_helper_sve2_sqrdmulh_h, | |
6107 | gen_helper_sve2_sqrdmulh_s, gen_helper_sve2_sqrdmulh_d, | |
6108 | }; | |
6109 | TRANS_FEAT(SQRDMULH_zzz, aa64_sve2, gen_gvec_ool_arg_zzz, | |
6110 | sqrdmulh_zzz_fns[a->esz], a, 0) | |
169d7c58 | 6111 | |
d4b1e59d RH |
6112 | /* |
6113 | * SVE2 Integer - Predicated | |
6114 | */ | |
6115 | ||
5880bdc0 RH |
6116 | static gen_helper_gvec_4 * const sadlp_fns[4] = { |
6117 | NULL, gen_helper_sve2_sadalp_zpzz_h, | |
6118 | gen_helper_sve2_sadalp_zpzz_s, gen_helper_sve2_sadalp_zpzz_d, | |
6119 | }; | |
6120 | TRANS_FEAT(SADALP_zpzz, aa64_sve2, gen_gvec_ool_arg_zpzz, | |
6121 | sadlp_fns[a->esz], a, 0) | |
d4b1e59d | 6122 | |
5880bdc0 RH |
6123 | static gen_helper_gvec_4 * const uadlp_fns[4] = { |
6124 | NULL, gen_helper_sve2_uadalp_zpzz_h, | |
6125 | gen_helper_sve2_uadalp_zpzz_s, gen_helper_sve2_uadalp_zpzz_d, | |
6126 | }; | |
6127 | TRANS_FEAT(UADALP_zpzz, aa64_sve2, gen_gvec_ool_arg_zpzz, | |
6128 | uadlp_fns[a->esz], a, 0) | |
db366da8 RH |
6129 | |
6130 | /* | |
6131 | * SVE2 integer unary operations (predicated) | |
6132 | */ | |
6133 | ||
b2c00961 RH |
6134 | TRANS_FEAT(URECPE, aa64_sve2, gen_gvec_ool_arg_zpz, |
6135 | a->esz == 2 ? gen_helper_sve2_urecpe_s : NULL, a, 0) | |
db366da8 | 6136 | |
b2c00961 RH |
6137 | TRANS_FEAT(URSQRTE, aa64_sve2, gen_gvec_ool_arg_zpz, |
6138 | a->esz == 2 ? gen_helper_sve2_ursqrte_s : NULL, a, 0) | |
db366da8 | 6139 | |
b2c00961 RH |
6140 | static gen_helper_gvec_3 * const sqabs_fns[4] = { |
6141 | gen_helper_sve2_sqabs_b, gen_helper_sve2_sqabs_h, | |
6142 | gen_helper_sve2_sqabs_s, gen_helper_sve2_sqabs_d, | |
6143 | }; | |
6144 | TRANS_FEAT(SQABS, aa64_sve2, gen_gvec_ool_arg_zpz, sqabs_fns[a->esz], a, 0) | |
db366da8 | 6145 | |
b2c00961 RH |
6146 | static gen_helper_gvec_3 * const sqneg_fns[4] = { |
6147 | gen_helper_sve2_sqneg_b, gen_helper_sve2_sqneg_h, | |
6148 | gen_helper_sve2_sqneg_s, gen_helper_sve2_sqneg_d, | |
6149 | }; | |
6150 | TRANS_FEAT(SQNEG, aa64_sve2, gen_gvec_ool_arg_zpz, sqneg_fns[a->esz], a, 0) | |
45d9503d | 6151 | |
5880bdc0 RH |
6152 | DO_ZPZZ(SQSHL, aa64_sve2, sve2_sqshl) |
6153 | DO_ZPZZ(SQRSHL, aa64_sve2, sve2_sqrshl) | |
6154 | DO_ZPZZ(SRSHL, aa64_sve2, sve2_srshl) | |
45d9503d | 6155 | |
5880bdc0 RH |
6156 | DO_ZPZZ(UQSHL, aa64_sve2, sve2_uqshl) |
6157 | DO_ZPZZ(UQRSHL, aa64_sve2, sve2_uqrshl) | |
6158 | DO_ZPZZ(URSHL, aa64_sve2, sve2_urshl) | |
a47dc220 | 6159 | |
5880bdc0 RH |
6160 | DO_ZPZZ(SHADD, aa64_sve2, sve2_shadd) |
6161 | DO_ZPZZ(SRHADD, aa64_sve2, sve2_srhadd) | |
6162 | DO_ZPZZ(SHSUB, aa64_sve2, sve2_shsub) | |
a47dc220 | 6163 | |
5880bdc0 RH |
6164 | DO_ZPZZ(UHADD, aa64_sve2, sve2_uhadd) |
6165 | DO_ZPZZ(URHADD, aa64_sve2, sve2_urhadd) | |
6166 | DO_ZPZZ(UHSUB, aa64_sve2, sve2_uhsub) | |
8597dc8b | 6167 | |
5880bdc0 RH |
6168 | DO_ZPZZ(ADDP, aa64_sve2, sve2_addp) |
6169 | DO_ZPZZ(SMAXP, aa64_sve2, sve2_smaxp) | |
6170 | DO_ZPZZ(UMAXP, aa64_sve2, sve2_umaxp) | |
6171 | DO_ZPZZ(SMINP, aa64_sve2, sve2_sminp) | |
6172 | DO_ZPZZ(UMINP, aa64_sve2, sve2_uminp) | |
4f07fbeb | 6173 | |
5880bdc0 RH |
6174 | DO_ZPZZ(SQADD_zpzz, aa64_sve2, sve2_sqadd) |
6175 | DO_ZPZZ(UQADD_zpzz, aa64_sve2, sve2_uqadd) | |
6176 | DO_ZPZZ(SQSUB_zpzz, aa64_sve2, sve2_sqsub) | |
6177 | DO_ZPZZ(UQSUB_zpzz, aa64_sve2, sve2_uqsub) | |
6178 | DO_ZPZZ(SUQADD, aa64_sve2, sve2_suqadd) | |
6179 | DO_ZPZZ(USQADD, aa64_sve2, sve2_usqadd) | |
0ce1dda8 RH |
6180 | |
6181 | /* | |
6182 | * SVE2 Widening Integer Arithmetic | |
6183 | */ | |
6184 | ||
615f19fe RH |
6185 | static gen_helper_gvec_3 * const saddl_fns[4] = { |
6186 | NULL, gen_helper_sve2_saddl_h, | |
6187 | gen_helper_sve2_saddl_s, gen_helper_sve2_saddl_d, | |
6188 | }; | |
6189 | TRANS_FEAT(SADDLB, aa64_sve2, gen_gvec_ool_arg_zzz, | |
6190 | saddl_fns[a->esz], a, 0) | |
6191 | TRANS_FEAT(SADDLT, aa64_sve2, gen_gvec_ool_arg_zzz, | |
6192 | saddl_fns[a->esz], a, 3) | |
6193 | TRANS_FEAT(SADDLBT, aa64_sve2, gen_gvec_ool_arg_zzz, | |
6194 | saddl_fns[a->esz], a, 2) | |
6195 | ||
6196 | static gen_helper_gvec_3 * const ssubl_fns[4] = { | |
6197 | NULL, gen_helper_sve2_ssubl_h, | |
6198 | gen_helper_sve2_ssubl_s, gen_helper_sve2_ssubl_d, | |
6199 | }; | |
6200 | TRANS_FEAT(SSUBLB, aa64_sve2, gen_gvec_ool_arg_zzz, | |
6201 | ssubl_fns[a->esz], a, 0) | |
6202 | TRANS_FEAT(SSUBLT, aa64_sve2, gen_gvec_ool_arg_zzz, | |
6203 | ssubl_fns[a->esz], a, 3) | |
6204 | TRANS_FEAT(SSUBLBT, aa64_sve2, gen_gvec_ool_arg_zzz, | |
6205 | ssubl_fns[a->esz], a, 2) | |
6206 | TRANS_FEAT(SSUBLTB, aa64_sve2, gen_gvec_ool_arg_zzz, | |
6207 | ssubl_fns[a->esz], a, 1) | |
6208 | ||
6209 | static gen_helper_gvec_3 * const sabdl_fns[4] = { | |
6210 | NULL, gen_helper_sve2_sabdl_h, | |
6211 | gen_helper_sve2_sabdl_s, gen_helper_sve2_sabdl_d, | |
6212 | }; | |
6213 | TRANS_FEAT(SABDLB, aa64_sve2, gen_gvec_ool_arg_zzz, | |
6214 | sabdl_fns[a->esz], a, 0) | |
6215 | TRANS_FEAT(SABDLT, aa64_sve2, gen_gvec_ool_arg_zzz, | |
6216 | sabdl_fns[a->esz], a, 3) | |
6217 | ||
6218 | static gen_helper_gvec_3 * const uaddl_fns[4] = { | |
6219 | NULL, gen_helper_sve2_uaddl_h, | |
6220 | gen_helper_sve2_uaddl_s, gen_helper_sve2_uaddl_d, | |
6221 | }; | |
6222 | TRANS_FEAT(UADDLB, aa64_sve2, gen_gvec_ool_arg_zzz, | |
6223 | uaddl_fns[a->esz], a, 0) | |
6224 | TRANS_FEAT(UADDLT, aa64_sve2, gen_gvec_ool_arg_zzz, | |
6225 | uaddl_fns[a->esz], a, 3) | |
6226 | ||
6227 | static gen_helper_gvec_3 * const usubl_fns[4] = { | |
6228 | NULL, gen_helper_sve2_usubl_h, | |
6229 | gen_helper_sve2_usubl_s, gen_helper_sve2_usubl_d, | |
6230 | }; | |
6231 | TRANS_FEAT(USUBLB, aa64_sve2, gen_gvec_ool_arg_zzz, | |
6232 | usubl_fns[a->esz], a, 0) | |
6233 | TRANS_FEAT(USUBLT, aa64_sve2, gen_gvec_ool_arg_zzz, | |
6234 | usubl_fns[a->esz], a, 3) | |
6235 | ||
6236 | static gen_helper_gvec_3 * const uabdl_fns[4] = { | |
6237 | NULL, gen_helper_sve2_uabdl_h, | |
6238 | gen_helper_sve2_uabdl_s, gen_helper_sve2_uabdl_d, | |
6239 | }; | |
6240 | TRANS_FEAT(UABDLB, aa64_sve2, gen_gvec_ool_arg_zzz, | |
6241 | uabdl_fns[a->esz], a, 0) | |
6242 | TRANS_FEAT(UABDLT, aa64_sve2, gen_gvec_ool_arg_zzz, | |
6243 | uabdl_fns[a->esz], a, 3) | |
6244 | ||
6245 | static gen_helper_gvec_3 * const sqdmull_fns[4] = { | |
6246 | NULL, gen_helper_sve2_sqdmull_zzz_h, | |
6247 | gen_helper_sve2_sqdmull_zzz_s, gen_helper_sve2_sqdmull_zzz_d, | |
6248 | }; | |
6249 | TRANS_FEAT(SQDMULLB_zzz, aa64_sve2, gen_gvec_ool_arg_zzz, | |
6250 | sqdmull_fns[a->esz], a, 0) | |
6251 | TRANS_FEAT(SQDMULLT_zzz, aa64_sve2, gen_gvec_ool_arg_zzz, | |
6252 | sqdmull_fns[a->esz], a, 3) | |
6253 | ||
6254 | static gen_helper_gvec_3 * const smull_fns[4] = { | |
6255 | NULL, gen_helper_sve2_smull_zzz_h, | |
6256 | gen_helper_sve2_smull_zzz_s, gen_helper_sve2_smull_zzz_d, | |
6257 | }; | |
6258 | TRANS_FEAT(SMULLB_zzz, aa64_sve2, gen_gvec_ool_arg_zzz, | |
6259 | smull_fns[a->esz], a, 0) | |
6260 | TRANS_FEAT(SMULLT_zzz, aa64_sve2, gen_gvec_ool_arg_zzz, | |
6261 | smull_fns[a->esz], a, 3) | |
6262 | ||
6263 | static gen_helper_gvec_3 * const umull_fns[4] = { | |
6264 | NULL, gen_helper_sve2_umull_zzz_h, | |
6265 | gen_helper_sve2_umull_zzz_s, gen_helper_sve2_umull_zzz_d, | |
6266 | }; | |
6267 | TRANS_FEAT(UMULLB_zzz, aa64_sve2, gen_gvec_ool_arg_zzz, | |
6268 | umull_fns[a->esz], a, 0) | |
6269 | TRANS_FEAT(UMULLT_zzz, aa64_sve2, gen_gvec_ool_arg_zzz, | |
6270 | umull_fns[a->esz], a, 3) | |
6271 | ||
6272 | static gen_helper_gvec_3 * const eoril_fns[4] = { | |
6273 | gen_helper_sve2_eoril_b, gen_helper_sve2_eoril_h, | |
6274 | gen_helper_sve2_eoril_s, gen_helper_sve2_eoril_d, | |
6275 | }; | |
6276 | TRANS_FEAT(EORBT, aa64_sve2, gen_gvec_ool_arg_zzz, eoril_fns[a->esz], a, 2) | |
6277 | TRANS_FEAT(EORTB, aa64_sve2, gen_gvec_ool_arg_zzz, eoril_fns[a->esz], a, 1) | |
2df3ca55 | 6278 | |
e3a56131 RH |
6279 | static bool do_trans_pmull(DisasContext *s, arg_rrr_esz *a, bool sel) |
6280 | { | |
6281 | static gen_helper_gvec_3 * const fns[4] = { | |
6282 | gen_helper_gvec_pmull_q, gen_helper_sve2_pmull_h, | |
6283 | NULL, gen_helper_sve2_pmull_d, | |
6284 | }; | |
6285 | if (a->esz == 0 && !dc_isar_feature(aa64_sve2_pmull128, s)) { | |
6286 | return false; | |
6287 | } | |
615f19fe | 6288 | return gen_gvec_ool_arg_zzz(s, fns[a->esz], a, sel); |
e3a56131 RH |
6289 | } |
6290 | ||
615f19fe RH |
6291 | TRANS_FEAT(PMULLB, aa64_sve2, do_trans_pmull, a, false) |
6292 | TRANS_FEAT(PMULLT, aa64_sve2, do_trans_pmull, a, true) | |
e3a56131 | 6293 | |
615f19fe RH |
6294 | static gen_helper_gvec_3 * const saddw_fns[4] = { |
6295 | NULL, gen_helper_sve2_saddw_h, | |
6296 | gen_helper_sve2_saddw_s, gen_helper_sve2_saddw_d, | |
6297 | }; | |
6298 | TRANS_FEAT(SADDWB, aa64_sve2, gen_gvec_ool_arg_zzz, saddw_fns[a->esz], a, 0) | |
6299 | TRANS_FEAT(SADDWT, aa64_sve2, gen_gvec_ool_arg_zzz, saddw_fns[a->esz], a, 1) | |
e3a56131 | 6300 | |
615f19fe RH |
6301 | static gen_helper_gvec_3 * const ssubw_fns[4] = { |
6302 | NULL, gen_helper_sve2_ssubw_h, | |
6303 | gen_helper_sve2_ssubw_s, gen_helper_sve2_ssubw_d, | |
6304 | }; | |
6305 | TRANS_FEAT(SSUBWB, aa64_sve2, gen_gvec_ool_arg_zzz, ssubw_fns[a->esz], a, 0) | |
6306 | TRANS_FEAT(SSUBWT, aa64_sve2, gen_gvec_ool_arg_zzz, ssubw_fns[a->esz], a, 1) | |
81fccf09 | 6307 | |
615f19fe RH |
6308 | static gen_helper_gvec_3 * const uaddw_fns[4] = { |
6309 | NULL, gen_helper_sve2_uaddw_h, | |
6310 | gen_helper_sve2_uaddw_s, gen_helper_sve2_uaddw_d, | |
6311 | }; | |
6312 | TRANS_FEAT(UADDWB, aa64_sve2, gen_gvec_ool_arg_zzz, uaddw_fns[a->esz], a, 0) | |
6313 | TRANS_FEAT(UADDWT, aa64_sve2, gen_gvec_ool_arg_zzz, uaddw_fns[a->esz], a, 1) | |
81fccf09 | 6314 | |
615f19fe RH |
6315 | static gen_helper_gvec_3 * const usubw_fns[4] = { |
6316 | NULL, gen_helper_sve2_usubw_h, | |
6317 | gen_helper_sve2_usubw_s, gen_helper_sve2_usubw_d, | |
6318 | }; | |
6319 | TRANS_FEAT(USUBWB, aa64_sve2, gen_gvec_ool_arg_zzz, usubw_fns[a->esz], a, 0) | |
6320 | TRANS_FEAT(USUBWT, aa64_sve2, gen_gvec_ool_arg_zzz, usubw_fns[a->esz], a, 1) | |
4269fef1 RH |
6321 | |
6322 | static void gen_sshll_vec(unsigned vece, TCGv_vec d, TCGv_vec n, int64_t imm) | |
6323 | { | |
6324 | int top = imm & 1; | |
6325 | int shl = imm >> 1; | |
6326 | int halfbits = 4 << vece; | |
6327 | ||
6328 | if (top) { | |
6329 | if (shl == halfbits) { | |
6330 | TCGv_vec t = tcg_temp_new_vec_matching(d); | |
6331 | tcg_gen_dupi_vec(vece, t, MAKE_64BIT_MASK(halfbits, halfbits)); | |
6332 | tcg_gen_and_vec(vece, d, n, t); | |
6333 | tcg_temp_free_vec(t); | |
6334 | } else { | |
6335 | tcg_gen_sari_vec(vece, d, n, halfbits); | |
6336 | tcg_gen_shli_vec(vece, d, d, shl); | |
6337 | } | |
6338 | } else { | |
6339 | tcg_gen_shli_vec(vece, d, n, halfbits); | |
6340 | tcg_gen_sari_vec(vece, d, d, halfbits - shl); | |
6341 | } | |
6342 | } | |
6343 | ||
6344 | static void gen_ushll_i64(unsigned vece, TCGv_i64 d, TCGv_i64 n, int imm) | |
6345 | { | |
6346 | int halfbits = 4 << vece; | |
6347 | int top = imm & 1; | |
6348 | int shl = (imm >> 1); | |
6349 | int shift; | |
6350 | uint64_t mask; | |
6351 | ||
6352 | mask = MAKE_64BIT_MASK(0, halfbits); | |
6353 | mask <<= shl; | |
6354 | mask = dup_const(vece, mask); | |
6355 | ||
6356 | shift = shl - top * halfbits; | |
6357 | if (shift < 0) { | |
6358 | tcg_gen_shri_i64(d, n, -shift); | |
6359 | } else { | |
6360 | tcg_gen_shli_i64(d, n, shift); | |
6361 | } | |
6362 | tcg_gen_andi_i64(d, d, mask); | |
6363 | } | |
6364 | ||
6365 | static void gen_ushll16_i64(TCGv_i64 d, TCGv_i64 n, int64_t imm) | |
6366 | { | |
6367 | gen_ushll_i64(MO_16, d, n, imm); | |
6368 | } | |
6369 | ||
6370 | static void gen_ushll32_i64(TCGv_i64 d, TCGv_i64 n, int64_t imm) | |
6371 | { | |
6372 | gen_ushll_i64(MO_32, d, n, imm); | |
6373 | } | |
6374 | ||
6375 | static void gen_ushll64_i64(TCGv_i64 d, TCGv_i64 n, int64_t imm) | |
6376 | { | |
6377 | gen_ushll_i64(MO_64, d, n, imm); | |
6378 | } | |
6379 | ||
6380 | static void gen_ushll_vec(unsigned vece, TCGv_vec d, TCGv_vec n, int64_t imm) | |
6381 | { | |
6382 | int halfbits = 4 << vece; | |
6383 | int top = imm & 1; | |
6384 | int shl = imm >> 1; | |
6385 | ||
6386 | if (top) { | |
6387 | if (shl == halfbits) { | |
6388 | TCGv_vec t = tcg_temp_new_vec_matching(d); | |
6389 | tcg_gen_dupi_vec(vece, t, MAKE_64BIT_MASK(halfbits, halfbits)); | |
6390 | tcg_gen_and_vec(vece, d, n, t); | |
6391 | tcg_temp_free_vec(t); | |
6392 | } else { | |
6393 | tcg_gen_shri_vec(vece, d, n, halfbits); | |
6394 | tcg_gen_shli_vec(vece, d, d, shl); | |
6395 | } | |
6396 | } else { | |
6397 | if (shl == 0) { | |
6398 | TCGv_vec t = tcg_temp_new_vec_matching(d); | |
6399 | tcg_gen_dupi_vec(vece, t, MAKE_64BIT_MASK(0, halfbits)); | |
6400 | tcg_gen_and_vec(vece, d, n, t); | |
6401 | tcg_temp_free_vec(t); | |
6402 | } else { | |
6403 | tcg_gen_shli_vec(vece, d, n, halfbits); | |
6404 | tcg_gen_shri_vec(vece, d, d, halfbits - shl); | |
6405 | } | |
6406 | } | |
6407 | } | |
6408 | ||
6409 | static bool do_sve2_shll_tb(DisasContext *s, arg_rri_esz *a, | |
6410 | bool sel, bool uns) | |
6411 | { | |
6412 | static const TCGOpcode sshll_list[] = { | |
6413 | INDEX_op_shli_vec, INDEX_op_sari_vec, 0 | |
6414 | }; | |
6415 | static const TCGOpcode ushll_list[] = { | |
6416 | INDEX_op_shli_vec, INDEX_op_shri_vec, 0 | |
6417 | }; | |
6418 | static const GVecGen2i ops[2][3] = { | |
6419 | { { .fniv = gen_sshll_vec, | |
6420 | .opt_opc = sshll_list, | |
6421 | .fno = gen_helper_sve2_sshll_h, | |
6422 | .vece = MO_16 }, | |
6423 | { .fniv = gen_sshll_vec, | |
6424 | .opt_opc = sshll_list, | |
6425 | .fno = gen_helper_sve2_sshll_s, | |
6426 | .vece = MO_32 }, | |
6427 | { .fniv = gen_sshll_vec, | |
6428 | .opt_opc = sshll_list, | |
6429 | .fno = gen_helper_sve2_sshll_d, | |
6430 | .vece = MO_64 } }, | |
6431 | { { .fni8 = gen_ushll16_i64, | |
6432 | .fniv = gen_ushll_vec, | |
6433 | .opt_opc = ushll_list, | |
6434 | .fno = gen_helper_sve2_ushll_h, | |
6435 | .vece = MO_16 }, | |
6436 | { .fni8 = gen_ushll32_i64, | |
6437 | .fniv = gen_ushll_vec, | |
6438 | .opt_opc = ushll_list, | |
6439 | .fno = gen_helper_sve2_ushll_s, | |
6440 | .vece = MO_32 }, | |
6441 | { .fni8 = gen_ushll64_i64, | |
6442 | .fniv = gen_ushll_vec, | |
6443 | .opt_opc = ushll_list, | |
6444 | .fno = gen_helper_sve2_ushll_d, | |
6445 | .vece = MO_64 } }, | |
6446 | }; | |
6447 | ||
6448 | if (a->esz < 0 || a->esz > 2 || !dc_isar_feature(aa64_sve2, s)) { | |
6449 | return false; | |
6450 | } | |
6451 | if (sve_access_check(s)) { | |
6452 | unsigned vsz = vec_full_reg_size(s); | |
6453 | tcg_gen_gvec_2i(vec_full_reg_offset(s, a->rd), | |
6454 | vec_full_reg_offset(s, a->rn), | |
6455 | vsz, vsz, (a->imm << 1) | sel, | |
6456 | &ops[uns][a->esz]); | |
6457 | } | |
6458 | return true; | |
6459 | } | |
6460 | ||
6461 | static bool trans_SSHLLB(DisasContext *s, arg_rri_esz *a) | |
6462 | { | |
6463 | return do_sve2_shll_tb(s, a, false, false); | |
6464 | } | |
6465 | ||
6466 | static bool trans_SSHLLT(DisasContext *s, arg_rri_esz *a) | |
6467 | { | |
6468 | return do_sve2_shll_tb(s, a, true, false); | |
6469 | } | |
6470 | ||
6471 | static bool trans_USHLLB(DisasContext *s, arg_rri_esz *a) | |
6472 | { | |
6473 | return do_sve2_shll_tb(s, a, false, true); | |
6474 | } | |
6475 | ||
6476 | static bool trans_USHLLT(DisasContext *s, arg_rri_esz *a) | |
6477 | { | |
6478 | return do_sve2_shll_tb(s, a, true, true); | |
6479 | } | |
cb9c33b8 | 6480 | |
615f19fe RH |
6481 | static gen_helper_gvec_3 * const bext_fns[4] = { |
6482 | gen_helper_sve2_bext_b, gen_helper_sve2_bext_h, | |
6483 | gen_helper_sve2_bext_s, gen_helper_sve2_bext_d, | |
6484 | }; | |
6485 | TRANS_FEAT(BEXT, aa64_sve2_bitperm, gen_gvec_ool_arg_zzz, | |
6486 | bext_fns[a->esz], a, 0) | |
ed4a6387 | 6487 | |
615f19fe RH |
6488 | static gen_helper_gvec_3 * const bdep_fns[4] = { |
6489 | gen_helper_sve2_bdep_b, gen_helper_sve2_bdep_h, | |
6490 | gen_helper_sve2_bdep_s, gen_helper_sve2_bdep_d, | |
6491 | }; | |
6492 | TRANS_FEAT(BDEP, aa64_sve2_bitperm, gen_gvec_ool_arg_zzz, | |
6493 | bdep_fns[a->esz], a, 0) | |
ed4a6387 | 6494 | |
615f19fe RH |
6495 | static gen_helper_gvec_3 * const bgrp_fns[4] = { |
6496 | gen_helper_sve2_bgrp_b, gen_helper_sve2_bgrp_h, | |
6497 | gen_helper_sve2_bgrp_s, gen_helper_sve2_bgrp_d, | |
6498 | }; | |
6499 | TRANS_FEAT(BGRP, aa64_sve2_bitperm, gen_gvec_ool_arg_zzz, | |
6500 | bgrp_fns[a->esz], a, 0) | |
ed4a6387 | 6501 | |
615f19fe RH |
6502 | static gen_helper_gvec_3 * const cadd_fns[4] = { |
6503 | gen_helper_sve2_cadd_b, gen_helper_sve2_cadd_h, | |
6504 | gen_helper_sve2_cadd_s, gen_helper_sve2_cadd_d, | |
6505 | }; | |
6506 | TRANS_FEAT(CADD_rot90, aa64_sve2, gen_gvec_ool_arg_zzz, | |
6507 | cadd_fns[a->esz], a, 0) | |
6508 | TRANS_FEAT(CADD_rot270, aa64_sve2, gen_gvec_ool_arg_zzz, | |
6509 | cadd_fns[a->esz], a, 1) | |
6510 | ||
6511 | static gen_helper_gvec_3 * const sqcadd_fns[4] = { | |
6512 | gen_helper_sve2_sqcadd_b, gen_helper_sve2_sqcadd_h, | |
6513 | gen_helper_sve2_sqcadd_s, gen_helper_sve2_sqcadd_d, | |
6514 | }; | |
6515 | TRANS_FEAT(SQCADD_rot90, aa64_sve2, gen_gvec_ool_arg_zzz, | |
6516 | sqcadd_fns[a->esz], a, 0) | |
6517 | TRANS_FEAT(SQCADD_rot270, aa64_sve2, gen_gvec_ool_arg_zzz, | |
6518 | sqcadd_fns[a->esz], a, 1) | |
38650638 | 6519 | |
eeb4e84d RH |
6520 | static gen_helper_gvec_4 * const sabal_fns[4] = { |
6521 | NULL, gen_helper_sve2_sabal_h, | |
6522 | gen_helper_sve2_sabal_s, gen_helper_sve2_sabal_d, | |
6523 | }; | |
6524 | TRANS_FEAT(SABALB, aa64_sve2, gen_gvec_ool_arg_zzzz, sabal_fns[a->esz], a, 0) | |
6525 | TRANS_FEAT(SABALT, aa64_sve2, gen_gvec_ool_arg_zzzz, sabal_fns[a->esz], a, 1) | |
38650638 | 6526 | |
eeb4e84d RH |
6527 | static gen_helper_gvec_4 * const uabal_fns[4] = { |
6528 | NULL, gen_helper_sve2_uabal_h, | |
6529 | gen_helper_sve2_uabal_s, gen_helper_sve2_uabal_d, | |
6530 | }; | |
6531 | TRANS_FEAT(UABALB, aa64_sve2, gen_gvec_ool_arg_zzzz, uabal_fns[a->esz], a, 0) | |
6532 | TRANS_FEAT(UABALT, aa64_sve2, gen_gvec_ool_arg_zzzz, uabal_fns[a->esz], a, 1) | |
b8295dfb RH |
6533 | |
6534 | static bool do_adcl(DisasContext *s, arg_rrrr_esz *a, bool sel) | |
6535 | { | |
6536 | static gen_helper_gvec_4 * const fns[2] = { | |
6537 | gen_helper_sve2_adcl_s, | |
6538 | gen_helper_sve2_adcl_d, | |
6539 | }; | |
6540 | /* | |
6541 | * Note that in this case the ESZ field encodes both size and sign. | |
6542 | * Split out 'subtract' into bit 1 of the data field for the helper. | |
6543 | */ | |
eeb4e84d | 6544 | return gen_gvec_ool_arg_zzzz(s, fns[a->esz & 1], a, (a->esz & 2) | sel); |
b8295dfb RH |
6545 | } |
6546 | ||
eeb4e84d RH |
6547 | TRANS_FEAT(ADCLB, aa64_sve2, do_adcl, a, false) |
6548 | TRANS_FEAT(ADCLT, aa64_sve2, do_adcl, a, true) | |
a7e3a90e | 6549 | |
f2be26a5 RH |
6550 | TRANS_FEAT(SSRA, aa64_sve2, gen_gvec_fn_arg_zzi, gen_gvec_ssra, a) |
6551 | TRANS_FEAT(USRA, aa64_sve2, gen_gvec_fn_arg_zzi, gen_gvec_usra, a) | |
6552 | TRANS_FEAT(SRSRA, aa64_sve2, gen_gvec_fn_arg_zzi, gen_gvec_srsra, a) | |
6553 | TRANS_FEAT(URSRA, aa64_sve2, gen_gvec_fn_arg_zzi, gen_gvec_ursra, a) | |
6554 | TRANS_FEAT(SRI, aa64_sve2, gen_gvec_fn_arg_zzi, gen_gvec_sri, a) | |
6555 | TRANS_FEAT(SLI, aa64_sve2, gen_gvec_fn_arg_zzi, gen_gvec_sli, a) | |
289a1797 | 6556 | |
79828dcb RH |
6557 | TRANS_FEAT(SABA, aa64_sve2, gen_gvec_fn_arg_zzz, gen_gvec_saba, a) |
6558 | TRANS_FEAT(UABA, aa64_sve2, gen_gvec_fn_arg_zzz, gen_gvec_uaba, a) | |
5ff2838d RH |
6559 | |
6560 | static bool do_sve2_narrow_extract(DisasContext *s, arg_rri_esz *a, | |
6561 | const GVecGen2 ops[3]) | |
6562 | { | |
6563 | if (a->esz < 0 || a->esz > MO_32 || a->imm != 0 || | |
6564 | !dc_isar_feature(aa64_sve2, s)) { | |
6565 | return false; | |
6566 | } | |
6567 | if (sve_access_check(s)) { | |
6568 | unsigned vsz = vec_full_reg_size(s); | |
6569 | tcg_gen_gvec_2(vec_full_reg_offset(s, a->rd), | |
6570 | vec_full_reg_offset(s, a->rn), | |
6571 | vsz, vsz, &ops[a->esz]); | |
6572 | } | |
6573 | return true; | |
6574 | } | |
6575 | ||
6576 | static const TCGOpcode sqxtn_list[] = { | |
6577 | INDEX_op_shli_vec, INDEX_op_smin_vec, INDEX_op_smax_vec, 0 | |
6578 | }; | |
6579 | ||
6580 | static void gen_sqxtnb_vec(unsigned vece, TCGv_vec d, TCGv_vec n) | |
6581 | { | |
6582 | TCGv_vec t = tcg_temp_new_vec_matching(d); | |
6583 | int halfbits = 4 << vece; | |
6584 | int64_t mask = (1ull << halfbits) - 1; | |
6585 | int64_t min = -1ull << (halfbits - 1); | |
6586 | int64_t max = -min - 1; | |
6587 | ||
6588 | tcg_gen_dupi_vec(vece, t, min); | |
6589 | tcg_gen_smax_vec(vece, d, n, t); | |
6590 | tcg_gen_dupi_vec(vece, t, max); | |
6591 | tcg_gen_smin_vec(vece, d, d, t); | |
6592 | tcg_gen_dupi_vec(vece, t, mask); | |
6593 | tcg_gen_and_vec(vece, d, d, t); | |
6594 | tcg_temp_free_vec(t); | |
6595 | } | |
6596 | ||
6597 | static bool trans_SQXTNB(DisasContext *s, arg_rri_esz *a) | |
6598 | { | |
6599 | static const GVecGen2 ops[3] = { | |
6600 | { .fniv = gen_sqxtnb_vec, | |
6601 | .opt_opc = sqxtn_list, | |
6602 | .fno = gen_helper_sve2_sqxtnb_h, | |
6603 | .vece = MO_16 }, | |
6604 | { .fniv = gen_sqxtnb_vec, | |
6605 | .opt_opc = sqxtn_list, | |
6606 | .fno = gen_helper_sve2_sqxtnb_s, | |
6607 | .vece = MO_32 }, | |
6608 | { .fniv = gen_sqxtnb_vec, | |
6609 | .opt_opc = sqxtn_list, | |
6610 | .fno = gen_helper_sve2_sqxtnb_d, | |
6611 | .vece = MO_64 }, | |
6612 | }; | |
6613 | return do_sve2_narrow_extract(s, a, ops); | |
6614 | } | |
6615 | ||
6616 | static void gen_sqxtnt_vec(unsigned vece, TCGv_vec d, TCGv_vec n) | |
6617 | { | |
6618 | TCGv_vec t = tcg_temp_new_vec_matching(d); | |
6619 | int halfbits = 4 << vece; | |
6620 | int64_t mask = (1ull << halfbits) - 1; | |
6621 | int64_t min = -1ull << (halfbits - 1); | |
6622 | int64_t max = -min - 1; | |
6623 | ||
6624 | tcg_gen_dupi_vec(vece, t, min); | |
6625 | tcg_gen_smax_vec(vece, n, n, t); | |
6626 | tcg_gen_dupi_vec(vece, t, max); | |
6627 | tcg_gen_smin_vec(vece, n, n, t); | |
6628 | tcg_gen_shli_vec(vece, n, n, halfbits); | |
6629 | tcg_gen_dupi_vec(vece, t, mask); | |
6630 | tcg_gen_bitsel_vec(vece, d, t, d, n); | |
6631 | tcg_temp_free_vec(t); | |
6632 | } | |
6633 | ||
6634 | static bool trans_SQXTNT(DisasContext *s, arg_rri_esz *a) | |
6635 | { | |
6636 | static const GVecGen2 ops[3] = { | |
6637 | { .fniv = gen_sqxtnt_vec, | |
6638 | .opt_opc = sqxtn_list, | |
6639 | .load_dest = true, | |
6640 | .fno = gen_helper_sve2_sqxtnt_h, | |
6641 | .vece = MO_16 }, | |
6642 | { .fniv = gen_sqxtnt_vec, | |
6643 | .opt_opc = sqxtn_list, | |
6644 | .load_dest = true, | |
6645 | .fno = gen_helper_sve2_sqxtnt_s, | |
6646 | .vece = MO_32 }, | |
6647 | { .fniv = gen_sqxtnt_vec, | |
6648 | .opt_opc = sqxtn_list, | |
6649 | .load_dest = true, | |
6650 | .fno = gen_helper_sve2_sqxtnt_d, | |
6651 | .vece = MO_64 }, | |
6652 | }; | |
6653 | return do_sve2_narrow_extract(s, a, ops); | |
6654 | } | |
6655 | ||
6656 | static const TCGOpcode uqxtn_list[] = { | |
6657 | INDEX_op_shli_vec, INDEX_op_umin_vec, 0 | |
6658 | }; | |
6659 | ||
6660 | static void gen_uqxtnb_vec(unsigned vece, TCGv_vec d, TCGv_vec n) | |
6661 | { | |
6662 | TCGv_vec t = tcg_temp_new_vec_matching(d); | |
6663 | int halfbits = 4 << vece; | |
6664 | int64_t max = (1ull << halfbits) - 1; | |
6665 | ||
6666 | tcg_gen_dupi_vec(vece, t, max); | |
6667 | tcg_gen_umin_vec(vece, d, n, t); | |
6668 | tcg_temp_free_vec(t); | |
6669 | } | |
6670 | ||
6671 | static bool trans_UQXTNB(DisasContext *s, arg_rri_esz *a) | |
6672 | { | |
6673 | static const GVecGen2 ops[3] = { | |
6674 | { .fniv = gen_uqxtnb_vec, | |
6675 | .opt_opc = uqxtn_list, | |
6676 | .fno = gen_helper_sve2_uqxtnb_h, | |
6677 | .vece = MO_16 }, | |
6678 | { .fniv = gen_uqxtnb_vec, | |
6679 | .opt_opc = uqxtn_list, | |
6680 | .fno = gen_helper_sve2_uqxtnb_s, | |
6681 | .vece = MO_32 }, | |
6682 | { .fniv = gen_uqxtnb_vec, | |
6683 | .opt_opc = uqxtn_list, | |
6684 | .fno = gen_helper_sve2_uqxtnb_d, | |
6685 | .vece = MO_64 }, | |
6686 | }; | |
6687 | return do_sve2_narrow_extract(s, a, ops); | |
6688 | } | |
6689 | ||
6690 | static void gen_uqxtnt_vec(unsigned vece, TCGv_vec d, TCGv_vec n) | |
6691 | { | |
6692 | TCGv_vec t = tcg_temp_new_vec_matching(d); | |
6693 | int halfbits = 4 << vece; | |
6694 | int64_t max = (1ull << halfbits) - 1; | |
6695 | ||
6696 | tcg_gen_dupi_vec(vece, t, max); | |
6697 | tcg_gen_umin_vec(vece, n, n, t); | |
6698 | tcg_gen_shli_vec(vece, n, n, halfbits); | |
6699 | tcg_gen_bitsel_vec(vece, d, t, d, n); | |
6700 | tcg_temp_free_vec(t); | |
6701 | } | |
6702 | ||
6703 | static bool trans_UQXTNT(DisasContext *s, arg_rri_esz *a) | |
6704 | { | |
6705 | static const GVecGen2 ops[3] = { | |
6706 | { .fniv = gen_uqxtnt_vec, | |
6707 | .opt_opc = uqxtn_list, | |
6708 | .load_dest = true, | |
6709 | .fno = gen_helper_sve2_uqxtnt_h, | |
6710 | .vece = MO_16 }, | |
6711 | { .fniv = gen_uqxtnt_vec, | |
6712 | .opt_opc = uqxtn_list, | |
6713 | .load_dest = true, | |
6714 | .fno = gen_helper_sve2_uqxtnt_s, | |
6715 | .vece = MO_32 }, | |
6716 | { .fniv = gen_uqxtnt_vec, | |
6717 | .opt_opc = uqxtn_list, | |
6718 | .load_dest = true, | |
6719 | .fno = gen_helper_sve2_uqxtnt_d, | |
6720 | .vece = MO_64 }, | |
6721 | }; | |
6722 | return do_sve2_narrow_extract(s, a, ops); | |
6723 | } | |
6724 | ||
6725 | static const TCGOpcode sqxtun_list[] = { | |
6726 | INDEX_op_shli_vec, INDEX_op_umin_vec, INDEX_op_smax_vec, 0 | |
6727 | }; | |
6728 | ||
6729 | static void gen_sqxtunb_vec(unsigned vece, TCGv_vec d, TCGv_vec n) | |
6730 | { | |
6731 | TCGv_vec t = tcg_temp_new_vec_matching(d); | |
6732 | int halfbits = 4 << vece; | |
6733 | int64_t max = (1ull << halfbits) - 1; | |
6734 | ||
6735 | tcg_gen_dupi_vec(vece, t, 0); | |
6736 | tcg_gen_smax_vec(vece, d, n, t); | |
6737 | tcg_gen_dupi_vec(vece, t, max); | |
6738 | tcg_gen_umin_vec(vece, d, d, t); | |
6739 | tcg_temp_free_vec(t); | |
6740 | } | |
6741 | ||
6742 | static bool trans_SQXTUNB(DisasContext *s, arg_rri_esz *a) | |
6743 | { | |
6744 | static const GVecGen2 ops[3] = { | |
6745 | { .fniv = gen_sqxtunb_vec, | |
6746 | .opt_opc = sqxtun_list, | |
6747 | .fno = gen_helper_sve2_sqxtunb_h, | |
6748 | .vece = MO_16 }, | |
6749 | { .fniv = gen_sqxtunb_vec, | |
6750 | .opt_opc = sqxtun_list, | |
6751 | .fno = gen_helper_sve2_sqxtunb_s, | |
6752 | .vece = MO_32 }, | |
6753 | { .fniv = gen_sqxtunb_vec, | |
6754 | .opt_opc = sqxtun_list, | |
6755 | .fno = gen_helper_sve2_sqxtunb_d, | |
6756 | .vece = MO_64 }, | |
6757 | }; | |
6758 | return do_sve2_narrow_extract(s, a, ops); | |
6759 | } | |
6760 | ||
6761 | static void gen_sqxtunt_vec(unsigned vece, TCGv_vec d, TCGv_vec n) | |
6762 | { | |
6763 | TCGv_vec t = tcg_temp_new_vec_matching(d); | |
6764 | int halfbits = 4 << vece; | |
6765 | int64_t max = (1ull << halfbits) - 1; | |
6766 | ||
6767 | tcg_gen_dupi_vec(vece, t, 0); | |
6768 | tcg_gen_smax_vec(vece, n, n, t); | |
6769 | tcg_gen_dupi_vec(vece, t, max); | |
6770 | tcg_gen_umin_vec(vece, n, n, t); | |
6771 | tcg_gen_shli_vec(vece, n, n, halfbits); | |
6772 | tcg_gen_bitsel_vec(vece, d, t, d, n); | |
6773 | tcg_temp_free_vec(t); | |
6774 | } | |
6775 | ||
6776 | static bool trans_SQXTUNT(DisasContext *s, arg_rri_esz *a) | |
6777 | { | |
6778 | static const GVecGen2 ops[3] = { | |
6779 | { .fniv = gen_sqxtunt_vec, | |
6780 | .opt_opc = sqxtun_list, | |
6781 | .load_dest = true, | |
6782 | .fno = gen_helper_sve2_sqxtunt_h, | |
6783 | .vece = MO_16 }, | |
6784 | { .fniv = gen_sqxtunt_vec, | |
6785 | .opt_opc = sqxtun_list, | |
6786 | .load_dest = true, | |
6787 | .fno = gen_helper_sve2_sqxtunt_s, | |
6788 | .vece = MO_32 }, | |
6789 | { .fniv = gen_sqxtunt_vec, | |
6790 | .opt_opc = sqxtun_list, | |
6791 | .load_dest = true, | |
6792 | .fno = gen_helper_sve2_sqxtunt_d, | |
6793 | .vece = MO_64 }, | |
6794 | }; | |
6795 | return do_sve2_narrow_extract(s, a, ops); | |
46d111b2 RH |
6796 | } |
6797 | ||
6798 | static bool do_sve2_shr_narrow(DisasContext *s, arg_rri_esz *a, | |
6799 | const GVecGen2i ops[3]) | |
6800 | { | |
6801 | if (a->esz < 0 || a->esz > MO_32 || !dc_isar_feature(aa64_sve2, s)) { | |
6802 | return false; | |
6803 | } | |
6804 | assert(a->imm > 0 && a->imm <= (8 << a->esz)); | |
6805 | if (sve_access_check(s)) { | |
6806 | unsigned vsz = vec_full_reg_size(s); | |
6807 | tcg_gen_gvec_2i(vec_full_reg_offset(s, a->rd), | |
6808 | vec_full_reg_offset(s, a->rn), | |
6809 | vsz, vsz, a->imm, &ops[a->esz]); | |
6810 | } | |
6811 | return true; | |
6812 | } | |
6813 | ||
6814 | static void gen_shrnb_i64(unsigned vece, TCGv_i64 d, TCGv_i64 n, int shr) | |
6815 | { | |
6816 | int halfbits = 4 << vece; | |
6817 | uint64_t mask = dup_const(vece, MAKE_64BIT_MASK(0, halfbits)); | |
6818 | ||
6819 | tcg_gen_shri_i64(d, n, shr); | |
6820 | tcg_gen_andi_i64(d, d, mask); | |
6821 | } | |
6822 | ||
6823 | static void gen_shrnb16_i64(TCGv_i64 d, TCGv_i64 n, int64_t shr) | |
6824 | { | |
6825 | gen_shrnb_i64(MO_16, d, n, shr); | |
6826 | } | |
6827 | ||
6828 | static void gen_shrnb32_i64(TCGv_i64 d, TCGv_i64 n, int64_t shr) | |
6829 | { | |
6830 | gen_shrnb_i64(MO_32, d, n, shr); | |
6831 | } | |
6832 | ||
6833 | static void gen_shrnb64_i64(TCGv_i64 d, TCGv_i64 n, int64_t shr) | |
6834 | { | |
6835 | gen_shrnb_i64(MO_64, d, n, shr); | |
6836 | } | |
6837 | ||
6838 | static void gen_shrnb_vec(unsigned vece, TCGv_vec d, TCGv_vec n, int64_t shr) | |
6839 | { | |
6840 | TCGv_vec t = tcg_temp_new_vec_matching(d); | |
6841 | int halfbits = 4 << vece; | |
6842 | uint64_t mask = MAKE_64BIT_MASK(0, halfbits); | |
6843 | ||
6844 | tcg_gen_shri_vec(vece, n, n, shr); | |
6845 | tcg_gen_dupi_vec(vece, t, mask); | |
6846 | tcg_gen_and_vec(vece, d, n, t); | |
6847 | tcg_temp_free_vec(t); | |
6848 | } | |
6849 | ||
6850 | static bool trans_SHRNB(DisasContext *s, arg_rri_esz *a) | |
6851 | { | |
6852 | static const TCGOpcode vec_list[] = { INDEX_op_shri_vec, 0 }; | |
6853 | static const GVecGen2i ops[3] = { | |
6854 | { .fni8 = gen_shrnb16_i64, | |
6855 | .fniv = gen_shrnb_vec, | |
6856 | .opt_opc = vec_list, | |
6857 | .fno = gen_helper_sve2_shrnb_h, | |
6858 | .vece = MO_16 }, | |
6859 | { .fni8 = gen_shrnb32_i64, | |
6860 | .fniv = gen_shrnb_vec, | |
6861 | .opt_opc = vec_list, | |
6862 | .fno = gen_helper_sve2_shrnb_s, | |
6863 | .vece = MO_32 }, | |
6864 | { .fni8 = gen_shrnb64_i64, | |
6865 | .fniv = gen_shrnb_vec, | |
6866 | .opt_opc = vec_list, | |
6867 | .fno = gen_helper_sve2_shrnb_d, | |
6868 | .vece = MO_64 }, | |
6869 | }; | |
6870 | return do_sve2_shr_narrow(s, a, ops); | |
6871 | } | |
6872 | ||
6873 | static void gen_shrnt_i64(unsigned vece, TCGv_i64 d, TCGv_i64 n, int shr) | |
6874 | { | |
6875 | int halfbits = 4 << vece; | |
6876 | uint64_t mask = dup_const(vece, MAKE_64BIT_MASK(0, halfbits)); | |
6877 | ||
6878 | tcg_gen_shli_i64(n, n, halfbits - shr); | |
6879 | tcg_gen_andi_i64(n, n, ~mask); | |
6880 | tcg_gen_andi_i64(d, d, mask); | |
6881 | tcg_gen_or_i64(d, d, n); | |
6882 | } | |
6883 | ||
6884 | static void gen_shrnt16_i64(TCGv_i64 d, TCGv_i64 n, int64_t shr) | |
6885 | { | |
6886 | gen_shrnt_i64(MO_16, d, n, shr); | |
6887 | } | |
6888 | ||
6889 | static void gen_shrnt32_i64(TCGv_i64 d, TCGv_i64 n, int64_t shr) | |
6890 | { | |
6891 | gen_shrnt_i64(MO_32, d, n, shr); | |
6892 | } | |
6893 | ||
6894 | static void gen_shrnt64_i64(TCGv_i64 d, TCGv_i64 n, int64_t shr) | |
6895 | { | |
6896 | tcg_gen_shri_i64(n, n, shr); | |
6897 | tcg_gen_deposit_i64(d, d, n, 32, 32); | |
6898 | } | |
6899 | ||
6900 | static void gen_shrnt_vec(unsigned vece, TCGv_vec d, TCGv_vec n, int64_t shr) | |
6901 | { | |
6902 | TCGv_vec t = tcg_temp_new_vec_matching(d); | |
6903 | int halfbits = 4 << vece; | |
6904 | uint64_t mask = MAKE_64BIT_MASK(0, halfbits); | |
6905 | ||
6906 | tcg_gen_shli_vec(vece, n, n, halfbits - shr); | |
6907 | tcg_gen_dupi_vec(vece, t, mask); | |
6908 | tcg_gen_bitsel_vec(vece, d, t, d, n); | |
6909 | tcg_temp_free_vec(t); | |
6910 | } | |
6911 | ||
6912 | static bool trans_SHRNT(DisasContext *s, arg_rri_esz *a) | |
6913 | { | |
6914 | static const TCGOpcode vec_list[] = { INDEX_op_shli_vec, 0 }; | |
6915 | static const GVecGen2i ops[3] = { | |
6916 | { .fni8 = gen_shrnt16_i64, | |
6917 | .fniv = gen_shrnt_vec, | |
6918 | .opt_opc = vec_list, | |
6919 | .load_dest = true, | |
6920 | .fno = gen_helper_sve2_shrnt_h, | |
6921 | .vece = MO_16 }, | |
6922 | { .fni8 = gen_shrnt32_i64, | |
6923 | .fniv = gen_shrnt_vec, | |
6924 | .opt_opc = vec_list, | |
6925 | .load_dest = true, | |
6926 | .fno = gen_helper_sve2_shrnt_s, | |
6927 | .vece = MO_32 }, | |
6928 | { .fni8 = gen_shrnt64_i64, | |
6929 | .fniv = gen_shrnt_vec, | |
6930 | .opt_opc = vec_list, | |
6931 | .load_dest = true, | |
6932 | .fno = gen_helper_sve2_shrnt_d, | |
6933 | .vece = MO_64 }, | |
6934 | }; | |
6935 | return do_sve2_shr_narrow(s, a, ops); | |
6936 | } | |
6937 | ||
6938 | static bool trans_RSHRNB(DisasContext *s, arg_rri_esz *a) | |
6939 | { | |
6940 | static const GVecGen2i ops[3] = { | |
6941 | { .fno = gen_helper_sve2_rshrnb_h }, | |
6942 | { .fno = gen_helper_sve2_rshrnb_s }, | |
6943 | { .fno = gen_helper_sve2_rshrnb_d }, | |
6944 | }; | |
6945 | return do_sve2_shr_narrow(s, a, ops); | |
6946 | } | |
6947 | ||
6948 | static bool trans_RSHRNT(DisasContext *s, arg_rri_esz *a) | |
6949 | { | |
6950 | static const GVecGen2i ops[3] = { | |
6951 | { .fno = gen_helper_sve2_rshrnt_h }, | |
6952 | { .fno = gen_helper_sve2_rshrnt_s }, | |
6953 | { .fno = gen_helper_sve2_rshrnt_d }, | |
6954 | }; | |
6955 | return do_sve2_shr_narrow(s, a, ops); | |
81fd3e6e RH |
6956 | } |
6957 | ||
6958 | static void gen_sqshrunb_vec(unsigned vece, TCGv_vec d, | |
6959 | TCGv_vec n, int64_t shr) | |
6960 | { | |
6961 | TCGv_vec t = tcg_temp_new_vec_matching(d); | |
6962 | int halfbits = 4 << vece; | |
6963 | ||
6964 | tcg_gen_sari_vec(vece, n, n, shr); | |
6965 | tcg_gen_dupi_vec(vece, t, 0); | |
6966 | tcg_gen_smax_vec(vece, n, n, t); | |
6967 | tcg_gen_dupi_vec(vece, t, MAKE_64BIT_MASK(0, halfbits)); | |
6968 | tcg_gen_umin_vec(vece, d, n, t); | |
6969 | tcg_temp_free_vec(t); | |
6970 | } | |
6971 | ||
6972 | static bool trans_SQSHRUNB(DisasContext *s, arg_rri_esz *a) | |
6973 | { | |
6974 | static const TCGOpcode vec_list[] = { | |
6975 | INDEX_op_sari_vec, INDEX_op_smax_vec, INDEX_op_umin_vec, 0 | |
6976 | }; | |
6977 | static const GVecGen2i ops[3] = { | |
6978 | { .fniv = gen_sqshrunb_vec, | |
6979 | .opt_opc = vec_list, | |
6980 | .fno = gen_helper_sve2_sqshrunb_h, | |
6981 | .vece = MO_16 }, | |
6982 | { .fniv = gen_sqshrunb_vec, | |
6983 | .opt_opc = vec_list, | |
6984 | .fno = gen_helper_sve2_sqshrunb_s, | |
6985 | .vece = MO_32 }, | |
6986 | { .fniv = gen_sqshrunb_vec, | |
6987 | .opt_opc = vec_list, | |
6988 | .fno = gen_helper_sve2_sqshrunb_d, | |
6989 | .vece = MO_64 }, | |
6990 | }; | |
6991 | return do_sve2_shr_narrow(s, a, ops); | |
6992 | } | |
6993 | ||
6994 | static void gen_sqshrunt_vec(unsigned vece, TCGv_vec d, | |
6995 | TCGv_vec n, int64_t shr) | |
6996 | { | |
6997 | TCGv_vec t = tcg_temp_new_vec_matching(d); | |
6998 | int halfbits = 4 << vece; | |
6999 | ||
7000 | tcg_gen_sari_vec(vece, n, n, shr); | |
7001 | tcg_gen_dupi_vec(vece, t, 0); | |
7002 | tcg_gen_smax_vec(vece, n, n, t); | |
7003 | tcg_gen_dupi_vec(vece, t, MAKE_64BIT_MASK(0, halfbits)); | |
7004 | tcg_gen_umin_vec(vece, n, n, t); | |
7005 | tcg_gen_shli_vec(vece, n, n, halfbits); | |
7006 | tcg_gen_bitsel_vec(vece, d, t, d, n); | |
7007 | tcg_temp_free_vec(t); | |
7008 | } | |
7009 | ||
7010 | static bool trans_SQSHRUNT(DisasContext *s, arg_rri_esz *a) | |
7011 | { | |
7012 | static const TCGOpcode vec_list[] = { | |
7013 | INDEX_op_shli_vec, INDEX_op_sari_vec, | |
7014 | INDEX_op_smax_vec, INDEX_op_umin_vec, 0 | |
7015 | }; | |
7016 | static const GVecGen2i ops[3] = { | |
7017 | { .fniv = gen_sqshrunt_vec, | |
7018 | .opt_opc = vec_list, | |
7019 | .load_dest = true, | |
7020 | .fno = gen_helper_sve2_sqshrunt_h, | |
7021 | .vece = MO_16 }, | |
7022 | { .fniv = gen_sqshrunt_vec, | |
7023 | .opt_opc = vec_list, | |
7024 | .load_dest = true, | |
7025 | .fno = gen_helper_sve2_sqshrunt_s, | |
7026 | .vece = MO_32 }, | |
7027 | { .fniv = gen_sqshrunt_vec, | |
7028 | .opt_opc = vec_list, | |
7029 | .load_dest = true, | |
7030 | .fno = gen_helper_sve2_sqshrunt_d, | |
7031 | .vece = MO_64 }, | |
7032 | }; | |
7033 | return do_sve2_shr_narrow(s, a, ops); | |
7034 | } | |
7035 | ||
7036 | static bool trans_SQRSHRUNB(DisasContext *s, arg_rri_esz *a) | |
7037 | { | |
7038 | static const GVecGen2i ops[3] = { | |
7039 | { .fno = gen_helper_sve2_sqrshrunb_h }, | |
7040 | { .fno = gen_helper_sve2_sqrshrunb_s }, | |
7041 | { .fno = gen_helper_sve2_sqrshrunb_d }, | |
7042 | }; | |
7043 | return do_sve2_shr_narrow(s, a, ops); | |
7044 | } | |
7045 | ||
7046 | static bool trans_SQRSHRUNT(DisasContext *s, arg_rri_esz *a) | |
7047 | { | |
7048 | static const GVecGen2i ops[3] = { | |
7049 | { .fno = gen_helper_sve2_sqrshrunt_h }, | |
7050 | { .fno = gen_helper_sve2_sqrshrunt_s }, | |
7051 | { .fno = gen_helper_sve2_sqrshrunt_d }, | |
7052 | }; | |
7053 | return do_sve2_shr_narrow(s, a, ops); | |
c13418da RH |
7054 | } |
7055 | ||
743bb147 RH |
7056 | static void gen_sqshrnb_vec(unsigned vece, TCGv_vec d, |
7057 | TCGv_vec n, int64_t shr) | |
7058 | { | |
7059 | TCGv_vec t = tcg_temp_new_vec_matching(d); | |
7060 | int halfbits = 4 << vece; | |
7061 | int64_t max = MAKE_64BIT_MASK(0, halfbits - 1); | |
7062 | int64_t min = -max - 1; | |
7063 | ||
7064 | tcg_gen_sari_vec(vece, n, n, shr); | |
7065 | tcg_gen_dupi_vec(vece, t, min); | |
7066 | tcg_gen_smax_vec(vece, n, n, t); | |
7067 | tcg_gen_dupi_vec(vece, t, max); | |
7068 | tcg_gen_smin_vec(vece, n, n, t); | |
7069 | tcg_gen_dupi_vec(vece, t, MAKE_64BIT_MASK(0, halfbits)); | |
7070 | tcg_gen_and_vec(vece, d, n, t); | |
7071 | tcg_temp_free_vec(t); | |
7072 | } | |
7073 | ||
7074 | static bool trans_SQSHRNB(DisasContext *s, arg_rri_esz *a) | |
7075 | { | |
7076 | static const TCGOpcode vec_list[] = { | |
7077 | INDEX_op_sari_vec, INDEX_op_smax_vec, INDEX_op_smin_vec, 0 | |
7078 | }; | |
7079 | static const GVecGen2i ops[3] = { | |
7080 | { .fniv = gen_sqshrnb_vec, | |
7081 | .opt_opc = vec_list, | |
7082 | .fno = gen_helper_sve2_sqshrnb_h, | |
7083 | .vece = MO_16 }, | |
7084 | { .fniv = gen_sqshrnb_vec, | |
7085 | .opt_opc = vec_list, | |
7086 | .fno = gen_helper_sve2_sqshrnb_s, | |
7087 | .vece = MO_32 }, | |
7088 | { .fniv = gen_sqshrnb_vec, | |
7089 | .opt_opc = vec_list, | |
7090 | .fno = gen_helper_sve2_sqshrnb_d, | |
7091 | .vece = MO_64 }, | |
7092 | }; | |
7093 | return do_sve2_shr_narrow(s, a, ops); | |
7094 | } | |
7095 | ||
7096 | static void gen_sqshrnt_vec(unsigned vece, TCGv_vec d, | |
7097 | TCGv_vec n, int64_t shr) | |
7098 | { | |
7099 | TCGv_vec t = tcg_temp_new_vec_matching(d); | |
7100 | int halfbits = 4 << vece; | |
7101 | int64_t max = MAKE_64BIT_MASK(0, halfbits - 1); | |
7102 | int64_t min = -max - 1; | |
7103 | ||
7104 | tcg_gen_sari_vec(vece, n, n, shr); | |
7105 | tcg_gen_dupi_vec(vece, t, min); | |
7106 | tcg_gen_smax_vec(vece, n, n, t); | |
7107 | tcg_gen_dupi_vec(vece, t, max); | |
7108 | tcg_gen_smin_vec(vece, n, n, t); | |
7109 | tcg_gen_shli_vec(vece, n, n, halfbits); | |
7110 | tcg_gen_dupi_vec(vece, t, MAKE_64BIT_MASK(0, halfbits)); | |
7111 | tcg_gen_bitsel_vec(vece, d, t, d, n); | |
7112 | tcg_temp_free_vec(t); | |
7113 | } | |
7114 | ||
7115 | static bool trans_SQSHRNT(DisasContext *s, arg_rri_esz *a) | |
7116 | { | |
7117 | static const TCGOpcode vec_list[] = { | |
7118 | INDEX_op_shli_vec, INDEX_op_sari_vec, | |
7119 | INDEX_op_smax_vec, INDEX_op_smin_vec, 0 | |
7120 | }; | |
7121 | static const GVecGen2i ops[3] = { | |
7122 | { .fniv = gen_sqshrnt_vec, | |
7123 | .opt_opc = vec_list, | |
7124 | .load_dest = true, | |
7125 | .fno = gen_helper_sve2_sqshrnt_h, | |
7126 | .vece = MO_16 }, | |
7127 | { .fniv = gen_sqshrnt_vec, | |
7128 | .opt_opc = vec_list, | |
7129 | .load_dest = true, | |
7130 | .fno = gen_helper_sve2_sqshrnt_s, | |
7131 | .vece = MO_32 }, | |
7132 | { .fniv = gen_sqshrnt_vec, | |
7133 | .opt_opc = vec_list, | |
7134 | .load_dest = true, | |
7135 | .fno = gen_helper_sve2_sqshrnt_d, | |
7136 | .vece = MO_64 }, | |
7137 | }; | |
7138 | return do_sve2_shr_narrow(s, a, ops); | |
7139 | } | |
7140 | ||
7141 | static bool trans_SQRSHRNB(DisasContext *s, arg_rri_esz *a) | |
7142 | { | |
7143 | static const GVecGen2i ops[3] = { | |
7144 | { .fno = gen_helper_sve2_sqrshrnb_h }, | |
7145 | { .fno = gen_helper_sve2_sqrshrnb_s }, | |
7146 | { .fno = gen_helper_sve2_sqrshrnb_d }, | |
7147 | }; | |
7148 | return do_sve2_shr_narrow(s, a, ops); | |
7149 | } | |
7150 | ||
7151 | static bool trans_SQRSHRNT(DisasContext *s, arg_rri_esz *a) | |
7152 | { | |
7153 | static const GVecGen2i ops[3] = { | |
7154 | { .fno = gen_helper_sve2_sqrshrnt_h }, | |
7155 | { .fno = gen_helper_sve2_sqrshrnt_s }, | |
7156 | { .fno = gen_helper_sve2_sqrshrnt_d }, | |
7157 | }; | |
7158 | return do_sve2_shr_narrow(s, a, ops); | |
7159 | } | |
7160 | ||
c13418da RH |
7161 | static void gen_uqshrnb_vec(unsigned vece, TCGv_vec d, |
7162 | TCGv_vec n, int64_t shr) | |
7163 | { | |
7164 | TCGv_vec t = tcg_temp_new_vec_matching(d); | |
7165 | int halfbits = 4 << vece; | |
7166 | ||
7167 | tcg_gen_shri_vec(vece, n, n, shr); | |
7168 | tcg_gen_dupi_vec(vece, t, MAKE_64BIT_MASK(0, halfbits)); | |
7169 | tcg_gen_umin_vec(vece, d, n, t); | |
7170 | tcg_temp_free_vec(t); | |
7171 | } | |
7172 | ||
7173 | static bool trans_UQSHRNB(DisasContext *s, arg_rri_esz *a) | |
7174 | { | |
7175 | static const TCGOpcode vec_list[] = { | |
7176 | INDEX_op_shri_vec, INDEX_op_umin_vec, 0 | |
7177 | }; | |
7178 | static const GVecGen2i ops[3] = { | |
7179 | { .fniv = gen_uqshrnb_vec, | |
7180 | .opt_opc = vec_list, | |
7181 | .fno = gen_helper_sve2_uqshrnb_h, | |
7182 | .vece = MO_16 }, | |
7183 | { .fniv = gen_uqshrnb_vec, | |
7184 | .opt_opc = vec_list, | |
7185 | .fno = gen_helper_sve2_uqshrnb_s, | |
7186 | .vece = MO_32 }, | |
7187 | { .fniv = gen_uqshrnb_vec, | |
7188 | .opt_opc = vec_list, | |
7189 | .fno = gen_helper_sve2_uqshrnb_d, | |
7190 | .vece = MO_64 }, | |
7191 | }; | |
7192 | return do_sve2_shr_narrow(s, a, ops); | |
7193 | } | |
7194 | ||
7195 | static void gen_uqshrnt_vec(unsigned vece, TCGv_vec d, | |
7196 | TCGv_vec n, int64_t shr) | |
7197 | { | |
7198 | TCGv_vec t = tcg_temp_new_vec_matching(d); | |
7199 | int halfbits = 4 << vece; | |
7200 | ||
7201 | tcg_gen_shri_vec(vece, n, n, shr); | |
7202 | tcg_gen_dupi_vec(vece, t, MAKE_64BIT_MASK(0, halfbits)); | |
7203 | tcg_gen_umin_vec(vece, n, n, t); | |
7204 | tcg_gen_shli_vec(vece, n, n, halfbits); | |
7205 | tcg_gen_bitsel_vec(vece, d, t, d, n); | |
7206 | tcg_temp_free_vec(t); | |
7207 | } | |
7208 | ||
7209 | static bool trans_UQSHRNT(DisasContext *s, arg_rri_esz *a) | |
7210 | { | |
7211 | static const TCGOpcode vec_list[] = { | |
7212 | INDEX_op_shli_vec, INDEX_op_shri_vec, INDEX_op_umin_vec, 0 | |
7213 | }; | |
7214 | static const GVecGen2i ops[3] = { | |
7215 | { .fniv = gen_uqshrnt_vec, | |
7216 | .opt_opc = vec_list, | |
7217 | .load_dest = true, | |
7218 | .fno = gen_helper_sve2_uqshrnt_h, | |
7219 | .vece = MO_16 }, | |
7220 | { .fniv = gen_uqshrnt_vec, | |
7221 | .opt_opc = vec_list, | |
7222 | .load_dest = true, | |
7223 | .fno = gen_helper_sve2_uqshrnt_s, | |
7224 | .vece = MO_32 }, | |
7225 | { .fniv = gen_uqshrnt_vec, | |
7226 | .opt_opc = vec_list, | |
7227 | .load_dest = true, | |
7228 | .fno = gen_helper_sve2_uqshrnt_d, | |
7229 | .vece = MO_64 }, | |
7230 | }; | |
7231 | return do_sve2_shr_narrow(s, a, ops); | |
7232 | } | |
7233 | ||
7234 | static bool trans_UQRSHRNB(DisasContext *s, arg_rri_esz *a) | |
7235 | { | |
7236 | static const GVecGen2i ops[3] = { | |
7237 | { .fno = gen_helper_sve2_uqrshrnb_h }, | |
7238 | { .fno = gen_helper_sve2_uqrshrnb_s }, | |
7239 | { .fno = gen_helper_sve2_uqrshrnb_d }, | |
7240 | }; | |
7241 | return do_sve2_shr_narrow(s, a, ops); | |
7242 | } | |
7243 | ||
7244 | static bool trans_UQRSHRNT(DisasContext *s, arg_rri_esz *a) | |
7245 | { | |
7246 | static const GVecGen2i ops[3] = { | |
7247 | { .fno = gen_helper_sve2_uqrshrnt_h }, | |
7248 | { .fno = gen_helper_sve2_uqrshrnt_s }, | |
7249 | { .fno = gen_helper_sve2_uqrshrnt_d }, | |
7250 | }; | |
7251 | return do_sve2_shr_narrow(s, a, ops); | |
5ff2838d | 7252 | } |
b87dbeeb | 7253 | |
40d5ea50 | 7254 | #define DO_SVE2_ZZZ_NARROW(NAME, name) \ |
bd394cf5 | 7255 | static gen_helper_gvec_3 * const name##_fns[4] = { \ |
40d5ea50 SL |
7256 | NULL, gen_helper_sve2_##name##_h, \ |
7257 | gen_helper_sve2_##name##_s, gen_helper_sve2_##name##_d, \ | |
7258 | }; \ | |
bd394cf5 RH |
7259 | TRANS_FEAT(NAME, aa64_sve2, gen_gvec_ool_arg_zzz, \ |
7260 | name##_fns[a->esz], a, 0) | |
40d5ea50 SL |
7261 | |
7262 | DO_SVE2_ZZZ_NARROW(ADDHNB, addhnb) | |
7263 | DO_SVE2_ZZZ_NARROW(ADDHNT, addhnt) | |
0ea3ff02 SL |
7264 | DO_SVE2_ZZZ_NARROW(RADDHNB, raddhnb) |
7265 | DO_SVE2_ZZZ_NARROW(RADDHNT, raddhnt) | |
40d5ea50 | 7266 | |
c3cd6766 SL |
7267 | DO_SVE2_ZZZ_NARROW(SUBHNB, subhnb) |
7268 | DO_SVE2_ZZZ_NARROW(SUBHNT, subhnt) | |
e9443d10 SL |
7269 | DO_SVE2_ZZZ_NARROW(RSUBHNB, rsubhnb) |
7270 | DO_SVE2_ZZZ_NARROW(RSUBHNT, rsubhnt) | |
c3cd6766 | 7271 | |
ef75309b RH |
7272 | static gen_helper_gvec_flags_4 * const match_fns[4] = { |
7273 | gen_helper_sve2_match_ppzz_b, gen_helper_sve2_match_ppzz_h, NULL, NULL | |
7274 | }; | |
7275 | TRANS_FEAT(MATCH, aa64_sve2, do_ppzz_flags, a, match_fns[a->esz]) | |
e0ae6ec3 | 7276 | |
ef75309b RH |
7277 | static gen_helper_gvec_flags_4 * const nmatch_fns[4] = { |
7278 | gen_helper_sve2_nmatch_ppzz_b, gen_helper_sve2_nmatch_ppzz_h, NULL, NULL | |
7279 | }; | |
7280 | TRANS_FEAT(NMATCH, aa64_sve2, do_ppzz_flags, a, nmatch_fns[a->esz]) | |
e0ae6ec3 | 7281 | |
5880bdc0 RH |
7282 | static gen_helper_gvec_4 * const histcnt_fns[4] = { |
7283 | NULL, NULL, gen_helper_sve2_histcnt_s, gen_helper_sve2_histcnt_d | |
7284 | }; | |
7285 | TRANS_FEAT(HISTCNT, aa64_sve2, gen_gvec_ool_arg_zpzz, | |
7286 | histcnt_fns[a->esz], a, 0) | |
7d47ac94 | 7287 | |
bd394cf5 RH |
7288 | TRANS_FEAT(HISTSEG, aa64_sve2, gen_gvec_ool_arg_zzz, |
7289 | a->esz == 0 ? gen_helper_sve2_histseg : NULL, a, 0) | |
7d47ac94 | 7290 | |
b87dbeeb SL |
7291 | static bool do_sve2_zpzz_fp(DisasContext *s, arg_rprr_esz *a, |
7292 | gen_helper_gvec_4_ptr *fn) | |
7293 | { | |
7294 | if (!dc_isar_feature(aa64_sve2, s)) { | |
7295 | return false; | |
7296 | } | |
7297 | return do_zpzz_fp(s, a, fn); | |
7298 | } | |
7299 | ||
7300 | #define DO_SVE2_ZPZZ_FP(NAME, name) \ | |
7301 | static bool trans_##NAME(DisasContext *s, arg_rprr_esz *a) \ | |
7302 | { \ | |
7303 | static gen_helper_gvec_4_ptr * const fns[4] = { \ | |
7304 | NULL, gen_helper_sve2_##name##_zpzz_h, \ | |
7305 | gen_helper_sve2_##name##_zpzz_s, gen_helper_sve2_##name##_zpzz_d \ | |
7306 | }; \ | |
7307 | return do_sve2_zpzz_fp(s, a, fns[a->esz]); \ | |
7308 | } | |
7309 | ||
7310 | DO_SVE2_ZPZZ_FP(FADDP, faddp) | |
7311 | DO_SVE2_ZPZZ_FP(FMAXNMP, fmaxnmp) | |
7312 | DO_SVE2_ZPZZ_FP(FMINNMP, fminnmp) | |
7313 | DO_SVE2_ZPZZ_FP(FMAXP, fmaxp) | |
7314 | DO_SVE2_ZPZZ_FP(FMINP, fminp) | |
bfc9307e RH |
7315 | |
7316 | /* | |
7317 | * SVE Integer Multiply-Add (unpredicated) | |
7318 | */ | |
7319 | ||
25aee7cc RH |
7320 | TRANS_FEAT(FMMLA_s, aa64_sve_f32mm, gen_gvec_fpst_zzzz, gen_helper_fmmla_s, |
7321 | a->rd, a->rn, a->rm, a->ra, 0, FPST_FPCR) | |
7322 | TRANS_FEAT(FMMLA_d, aa64_sve_f64mm, gen_gvec_fpst_zzzz, gen_helper_fmmla_d, | |
7323 | a->rd, a->rn, a->rm, a->ra, 0, FPST_FPCR) | |
4f26756b | 7324 | |
eeb4e84d RH |
7325 | static gen_helper_gvec_4 * const sqdmlal_zzzw_fns[] = { |
7326 | NULL, gen_helper_sve2_sqdmlal_zzzw_h, | |
7327 | gen_helper_sve2_sqdmlal_zzzw_s, gen_helper_sve2_sqdmlal_zzzw_d, | |
7328 | }; | |
7329 | TRANS_FEAT(SQDMLALB_zzzw, aa64_sve2, gen_gvec_ool_arg_zzzz, | |
7330 | sqdmlal_zzzw_fns[a->esz], a, 0) | |
7331 | TRANS_FEAT(SQDMLALT_zzzw, aa64_sve2, gen_gvec_ool_arg_zzzz, | |
7332 | sqdmlal_zzzw_fns[a->esz], a, 3) | |
7333 | TRANS_FEAT(SQDMLALBT, aa64_sve2, gen_gvec_ool_arg_zzzz, | |
7334 | sqdmlal_zzzw_fns[a->esz], a, 2) | |
7335 | ||
7336 | static gen_helper_gvec_4 * const sqdmlsl_zzzw_fns[] = { | |
7337 | NULL, gen_helper_sve2_sqdmlsl_zzzw_h, | |
7338 | gen_helper_sve2_sqdmlsl_zzzw_s, gen_helper_sve2_sqdmlsl_zzzw_d, | |
7339 | }; | |
7340 | TRANS_FEAT(SQDMLSLB_zzzw, aa64_sve2, gen_gvec_ool_arg_zzzz, | |
7341 | sqdmlsl_zzzw_fns[a->esz], a, 0) | |
7342 | TRANS_FEAT(SQDMLSLT_zzzw, aa64_sve2, gen_gvec_ool_arg_zzzz, | |
7343 | sqdmlsl_zzzw_fns[a->esz], a, 3) | |
7344 | TRANS_FEAT(SQDMLSLBT, aa64_sve2, gen_gvec_ool_arg_zzzz, | |
7345 | sqdmlsl_zzzw_fns[a->esz], a, 2) | |
7346 | ||
7347 | static gen_helper_gvec_4 * const sqrdmlah_fns[] = { | |
7348 | gen_helper_sve2_sqrdmlah_b, gen_helper_sve2_sqrdmlah_h, | |
7349 | gen_helper_sve2_sqrdmlah_s, gen_helper_sve2_sqrdmlah_d, | |
7350 | }; | |
7351 | TRANS_FEAT(SQRDMLAH_zzzz, aa64_sve2, gen_gvec_ool_arg_zzzz, | |
7352 | sqrdmlah_fns[a->esz], a, 0) | |
45a32e80 | 7353 | |
eeb4e84d RH |
7354 | static gen_helper_gvec_4 * const sqrdmlsh_fns[] = { |
7355 | gen_helper_sve2_sqrdmlsh_b, gen_helper_sve2_sqrdmlsh_h, | |
7356 | gen_helper_sve2_sqrdmlsh_s, gen_helper_sve2_sqrdmlsh_d, | |
7357 | }; | |
7358 | TRANS_FEAT(SQRDMLSH_zzzz, aa64_sve2, gen_gvec_ool_arg_zzzz, | |
7359 | sqrdmlsh_fns[a->esz], a, 0) | |
45a32e80 | 7360 | |
eeb4e84d RH |
7361 | static gen_helper_gvec_4 * const smlal_zzzw_fns[] = { |
7362 | NULL, gen_helper_sve2_smlal_zzzw_h, | |
7363 | gen_helper_sve2_smlal_zzzw_s, gen_helper_sve2_smlal_zzzw_d, | |
7364 | }; | |
7365 | TRANS_FEAT(SMLALB_zzzw, aa64_sve2, gen_gvec_ool_arg_zzzz, | |
7366 | smlal_zzzw_fns[a->esz], a, 0) | |
7367 | TRANS_FEAT(SMLALT_zzzw, aa64_sve2, gen_gvec_ool_arg_zzzz, | |
7368 | smlal_zzzw_fns[a->esz], a, 1) | |
7369 | ||
7370 | static gen_helper_gvec_4 * const umlal_zzzw_fns[] = { | |
7371 | NULL, gen_helper_sve2_umlal_zzzw_h, | |
7372 | gen_helper_sve2_umlal_zzzw_s, gen_helper_sve2_umlal_zzzw_d, | |
7373 | }; | |
7374 | TRANS_FEAT(UMLALB_zzzw, aa64_sve2, gen_gvec_ool_arg_zzzz, | |
7375 | umlal_zzzw_fns[a->esz], a, 0) | |
7376 | TRANS_FEAT(UMLALT_zzzw, aa64_sve2, gen_gvec_ool_arg_zzzz, | |
7377 | umlal_zzzw_fns[a->esz], a, 1) | |
7378 | ||
7379 | static gen_helper_gvec_4 * const smlsl_zzzw_fns[] = { | |
7380 | NULL, gen_helper_sve2_smlsl_zzzw_h, | |
7381 | gen_helper_sve2_smlsl_zzzw_s, gen_helper_sve2_smlsl_zzzw_d, | |
7382 | }; | |
7383 | TRANS_FEAT(SMLSLB_zzzw, aa64_sve2, gen_gvec_ool_arg_zzzz, | |
7384 | smlsl_zzzw_fns[a->esz], a, 0) | |
7385 | TRANS_FEAT(SMLSLT_zzzw, aa64_sve2, gen_gvec_ool_arg_zzzz, | |
7386 | smlsl_zzzw_fns[a->esz], a, 1) | |
7387 | ||
7388 | static gen_helper_gvec_4 * const umlsl_zzzw_fns[] = { | |
7389 | NULL, gen_helper_sve2_umlsl_zzzw_h, | |
7390 | gen_helper_sve2_umlsl_zzzw_s, gen_helper_sve2_umlsl_zzzw_d, | |
7391 | }; | |
7392 | TRANS_FEAT(UMLSLB_zzzw, aa64_sve2, gen_gvec_ool_arg_zzzz, | |
7393 | umlsl_zzzw_fns[a->esz], a, 0) | |
7394 | TRANS_FEAT(UMLSLT_zzzw, aa64_sve2, gen_gvec_ool_arg_zzzz, | |
7395 | umlsl_zzzw_fns[a->esz], a, 1) | |
d782d3ca | 7396 | |
5f425b92 RH |
7397 | static gen_helper_gvec_4 * const cmla_fns[] = { |
7398 | gen_helper_sve2_cmla_zzzz_b, gen_helper_sve2_cmla_zzzz_h, | |
7399 | gen_helper_sve2_cmla_zzzz_s, gen_helper_sve2_cmla_zzzz_d, | |
7400 | }; | |
7401 | TRANS_FEAT(CMLA_zzzz, aa64_sve2, gen_gvec_ool_zzzz, | |
7402 | cmla_fns[a->esz], a->rd, a->rn, a->rm, a->ra, a->rot) | |
21068f39 | 7403 | |
5f425b92 RH |
7404 | static gen_helper_gvec_4 * const cdot_fns[] = { |
7405 | NULL, NULL, gen_helper_sve2_cdot_zzzz_s, gen_helper_sve2_cdot_zzzz_d | |
7406 | }; | |
7407 | TRANS_FEAT(CDOT_zzzz, aa64_sve2, gen_gvec_ool_zzzz, | |
7408 | cdot_fns[a->esz], a->rd, a->rn, a->rm, a->ra, a->rot) | |
d782d3ca | 7409 | |
5f425b92 RH |
7410 | static gen_helper_gvec_4 * const sqrdcmlah_fns[] = { |
7411 | gen_helper_sve2_sqrdcmlah_zzzz_b, gen_helper_sve2_sqrdcmlah_zzzz_h, | |
7412 | gen_helper_sve2_sqrdcmlah_zzzz_s, gen_helper_sve2_sqrdcmlah_zzzz_d, | |
7413 | }; | |
7414 | TRANS_FEAT(SQRDCMLAH_zzzz, aa64_sve2, gen_gvec_ool_zzzz, | |
7415 | sqrdcmlah_fns[a->esz], a->rd, a->rn, a->rm, a->ra, a->rot) | |
6a98cb2a | 7416 | |
8740d694 RH |
7417 | TRANS_FEAT(USDOT_zzzz, aa64_sve_i8mm, gen_gvec_ool_arg_zzzz, |
7418 | a->esz == 2 ? gen_helper_gvec_usdot_b : NULL, a, 0) | |
b2bcd1be | 7419 | |
0ea3cdbf RH |
7420 | TRANS_FEAT(AESMC, aa64_sve2_aes, gen_gvec_ool_zz, |
7421 | gen_helper_crypto_aesmc, a->rd, a->rd, a->decrypt) | |
3cc7a88e | 7422 | |
32e2ad65 RH |
7423 | TRANS_FEAT(AESE, aa64_sve2_aes, gen_gvec_ool_arg_zzz, |
7424 | gen_helper_crypto_aese, a, false) | |
7425 | TRANS_FEAT(AESD, aa64_sve2_aes, gen_gvec_ool_arg_zzz, | |
7426 | gen_helper_crypto_aese, a, true) | |
3cc7a88e | 7427 | |
32e2ad65 RH |
7428 | TRANS_FEAT(SM4E, aa64_sve2_sm4, gen_gvec_ool_arg_zzz, |
7429 | gen_helper_crypto_sm4e, a, 0) | |
7430 | TRANS_FEAT(SM4EKEY, aa64_sve2_sm4, gen_gvec_ool_arg_zzz, | |
7431 | gen_helper_crypto_sm4ekey, a, 0) | |
3358eb3f | 7432 | |
2aa469ff | 7433 | TRANS_FEAT(RAX1, aa64_sve2_sha3, gen_gvec_fn_arg_zzz, gen_gvec_rax1, a) |
5c1b7226 RH |
7434 | |
7435 | static bool trans_FCVTNT_sh(DisasContext *s, arg_rpr_esz *a) | |
7436 | { | |
7437 | if (!dc_isar_feature(aa64_sve2, s)) { | |
7438 | return false; | |
7439 | } | |
7440 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve2_fcvtnt_sh); | |
7441 | } | |
7442 | ||
d29b17ca RH |
7443 | static bool trans_BFCVTNT(DisasContext *s, arg_rpr_esz *a) |
7444 | { | |
7445 | if (!dc_isar_feature(aa64_sve_bf16, s)) { | |
7446 | return false; | |
7447 | } | |
7448 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_bfcvtnt); | |
7449 | } | |
7450 | ||
5c1b7226 RH |
7451 | static bool trans_FCVTNT_ds(DisasContext *s, arg_rpr_esz *a) |
7452 | { | |
7453 | if (!dc_isar_feature(aa64_sve2, s)) { | |
7454 | return false; | |
7455 | } | |
7456 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve2_fcvtnt_ds); | |
7457 | } | |
83c2523f SL |
7458 | |
7459 | static bool trans_FCVTLT_hs(DisasContext *s, arg_rpr_esz *a) | |
7460 | { | |
7461 | if (!dc_isar_feature(aa64_sve2, s)) { | |
7462 | return false; | |
7463 | } | |
7464 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve2_fcvtlt_hs); | |
7465 | } | |
7466 | ||
7467 | static bool trans_FCVTLT_sd(DisasContext *s, arg_rpr_esz *a) | |
7468 | { | |
7469 | if (!dc_isar_feature(aa64_sve2, s)) { | |
7470 | return false; | |
7471 | } | |
7472 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve2_fcvtlt_sd); | |
7473 | } | |
95365277 SL |
7474 | |
7475 | static bool trans_FCVTX_ds(DisasContext *s, arg_rpr_esz *a) | |
7476 | { | |
7477 | if (!dc_isar_feature(aa64_sve2, s)) { | |
7478 | return false; | |
7479 | } | |
7480 | return do_frint_mode(s, a, float_round_to_odd, gen_helper_sve_fcvt_ds); | |
7481 | } | |
7482 | ||
7483 | static bool trans_FCVTXNT_ds(DisasContext *s, arg_rpr_esz *a) | |
7484 | { | |
7485 | if (!dc_isar_feature(aa64_sve2, s)) { | |
7486 | return false; | |
7487 | } | |
7488 | return do_frint_mode(s, a, float_round_to_odd, gen_helper_sve2_fcvtnt_ds); | |
7489 | } | |
631be02e SL |
7490 | |
7491 | static bool trans_FLOGB(DisasContext *s, arg_rpr_esz *a) | |
7492 | { | |
7493 | static gen_helper_gvec_3_ptr * const fns[] = { | |
7494 | NULL, gen_helper_flogb_h, | |
7495 | gen_helper_flogb_s, gen_helper_flogb_d | |
7496 | }; | |
7497 | ||
7498 | if (!dc_isar_feature(aa64_sve2, s) || fns[a->esz] == NULL) { | |
7499 | return false; | |
7500 | } | |
7501 | if (sve_access_check(s)) { | |
7502 | TCGv_ptr status = | |
7503 | fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR); | |
7504 | unsigned vsz = vec_full_reg_size(s); | |
7505 | ||
7506 | tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, a->rd), | |
7507 | vec_full_reg_offset(s, a->rn), | |
7508 | pred_full_reg_offset(s, a->pg), | |
7509 | status, vsz, vsz, 0, fns[a->esz]); | |
7510 | tcg_temp_free_ptr(status); | |
7511 | } | |
7512 | return true; | |
7513 | } | |
50d102bd SL |
7514 | |
7515 | static bool do_FMLAL_zzzw(DisasContext *s, arg_rrrr_esz *a, bool sub, bool sel) | |
7516 | { | |
7517 | if (!dc_isar_feature(aa64_sve2, s)) { | |
7518 | return false; | |
7519 | } | |
41bf9b67 RH |
7520 | return gen_gvec_ptr_zzzz(s, gen_helper_sve2_fmlal_zzzw_s, |
7521 | a->rd, a->rn, a->rm, a->ra, | |
7522 | (sel << 1) | sub, cpu_env); | |
50d102bd SL |
7523 | } |
7524 | ||
7525 | static bool trans_FMLALB_zzzw(DisasContext *s, arg_rrrr_esz *a) | |
7526 | { | |
7527 | return do_FMLAL_zzzw(s, a, false, false); | |
7528 | } | |
7529 | ||
7530 | static bool trans_FMLALT_zzzw(DisasContext *s, arg_rrrr_esz *a) | |
7531 | { | |
7532 | return do_FMLAL_zzzw(s, a, false, true); | |
7533 | } | |
7534 | ||
7535 | static bool trans_FMLSLB_zzzw(DisasContext *s, arg_rrrr_esz *a) | |
7536 | { | |
7537 | return do_FMLAL_zzzw(s, a, true, false); | |
7538 | } | |
7539 | ||
7540 | static bool trans_FMLSLT_zzzw(DisasContext *s, arg_rrrr_esz *a) | |
7541 | { | |
7542 | return do_FMLAL_zzzw(s, a, true, true); | |
7543 | } | |
7544 | ||
7545 | static bool do_FMLAL_zzxw(DisasContext *s, arg_rrxr_esz *a, bool sub, bool sel) | |
7546 | { | |
7547 | if (!dc_isar_feature(aa64_sve2, s)) { | |
7548 | return false; | |
7549 | } | |
41bf9b67 RH |
7550 | return gen_gvec_ptr_zzzz(s, gen_helper_sve2_fmlal_zzxw_s, |
7551 | a->rd, a->rn, a->rm, a->ra, | |
7552 | (a->index << 2) | (sel << 1) | sub, cpu_env); | |
50d102bd SL |
7553 | } |
7554 | ||
7555 | static bool trans_FMLALB_zzxw(DisasContext *s, arg_rrxr_esz *a) | |
7556 | { | |
7557 | return do_FMLAL_zzxw(s, a, false, false); | |
7558 | } | |
7559 | ||
7560 | static bool trans_FMLALT_zzxw(DisasContext *s, arg_rrxr_esz *a) | |
7561 | { | |
7562 | return do_FMLAL_zzxw(s, a, false, true); | |
7563 | } | |
7564 | ||
7565 | static bool trans_FMLSLB_zzxw(DisasContext *s, arg_rrxr_esz *a) | |
7566 | { | |
7567 | return do_FMLAL_zzxw(s, a, true, false); | |
7568 | } | |
7569 | ||
7570 | static bool trans_FMLSLT_zzxw(DisasContext *s, arg_rrxr_esz *a) | |
7571 | { | |
7572 | return do_FMLAL_zzxw(s, a, true, true); | |
7573 | } | |
2323c5ff | 7574 | |
eec05e4e RH |
7575 | TRANS_FEAT(SMMLA, aa64_sve_i8mm, gen_gvec_ool_arg_zzzz, |
7576 | gen_helper_gvec_smmla_b, a, 0) | |
7577 | TRANS_FEAT(USMMLA, aa64_sve_i8mm, gen_gvec_ool_arg_zzzz, | |
7578 | gen_helper_gvec_usmmla_b, a, 0) | |
7579 | TRANS_FEAT(UMMLA, aa64_sve_i8mm, gen_gvec_ool_arg_zzzz, | |
7580 | gen_helper_gvec_ummla_b, a, 0) | |
cb8657f7 | 7581 | |
eec05e4e RH |
7582 | TRANS_FEAT(BFDOT_zzzz, aa64_sve_bf16, gen_gvec_ool_arg_zzzz, |
7583 | gen_helper_gvec_bfdot, a, 0) | |
f3500a25 RH |
7584 | TRANS_FEAT(BFDOT_zzxz, aa64_sve_bf16, gen_gvec_ool_arg_zzxz, |
7585 | gen_helper_gvec_bfdot_idx, a) | |
81266a1f | 7586 | |
eec05e4e RH |
7587 | TRANS_FEAT(BFMMLA, aa64_sve_bf16, gen_gvec_ool_arg_zzzz, |
7588 | gen_helper_gvec_bfmmla, a, 0) | |
5693887f RH |
7589 | |
7590 | static bool do_BFMLAL_zzzw(DisasContext *s, arg_rrrr_esz *a, bool sel) | |
7591 | { | |
7592 | if (!dc_isar_feature(aa64_sve_bf16, s)) { | |
7593 | return false; | |
7594 | } | |
41bf9b67 RH |
7595 | return gen_gvec_fpst_zzzz(s, gen_helper_gvec_bfmlal, |
7596 | a->rd, a->rn, a->rm, a->ra, sel, FPST_FPCR); | |
5693887f RH |
7597 | } |
7598 | ||
7599 | static bool trans_BFMLALB_zzzw(DisasContext *s, arg_rrrr_esz *a) | |
7600 | { | |
7601 | return do_BFMLAL_zzzw(s, a, false); | |
7602 | } | |
7603 | ||
7604 | static bool trans_BFMLALT_zzzw(DisasContext *s, arg_rrrr_esz *a) | |
7605 | { | |
7606 | return do_BFMLAL_zzzw(s, a, true); | |
7607 | } | |
458d0ab6 RH |
7608 | |
7609 | static bool do_BFMLAL_zzxw(DisasContext *s, arg_rrxr_esz *a, bool sel) | |
7610 | { | |
7611 | if (!dc_isar_feature(aa64_sve_bf16, s)) { | |
7612 | return false; | |
7613 | } | |
41bf9b67 RH |
7614 | return gen_gvec_fpst_zzzz(s, gen_helper_gvec_bfmlal_idx, |
7615 | a->rd, a->rn, a->rm, a->ra, | |
7616 | (a->index << 1) | sel, FPST_FPCR); | |
458d0ab6 RH |
7617 | } |
7618 | ||
7619 | static bool trans_BFMLALB_zzxw(DisasContext *s, arg_rrxr_esz *a) | |
7620 | { | |
7621 | return do_BFMLAL_zzxw(s, a, false); | |
7622 | } | |
7623 | ||
7624 | static bool trans_BFMLALT_zzxw(DisasContext *s, arg_rrxr_esz *a) | |
7625 | { | |
7626 | return do_BFMLAL_zzxw(s, a, true); | |
7627 | } |