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38388f7e RH |
1 | /* |
2 | * AArch64 SVE translation | |
3 | * | |
4 | * Copyright (c) 2018 Linaro, Ltd | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
50f57e09 | 9 | * version 2.1 of the License, or (at your option) any later version. |
38388f7e RH |
10 | * |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #include "qemu/osdep.h" | |
21 | #include "cpu.h" | |
22 | #include "exec/exec-all.h" | |
dcb32f1d PMD |
23 | #include "tcg/tcg-op.h" |
24 | #include "tcg/tcg-op-gvec.h" | |
25 | #include "tcg/tcg-gvec-desc.h" | |
38388f7e RH |
26 | #include "qemu/log.h" |
27 | #include "arm_ldst.h" | |
28 | #include "translate.h" | |
29 | #include "internals.h" | |
30 | #include "exec/helper-proto.h" | |
31 | #include "exec/helper-gen.h" | |
32 | #include "exec/log.h" | |
38388f7e | 33 | #include "translate-a64.h" |
cc48affe | 34 | #include "fpu/softfloat.h" |
38388f7e | 35 | |
757f9cff | 36 | |
9ee3a611 RH |
37 | typedef void GVecGen2sFn(unsigned, uint32_t, uint32_t, |
38 | TCGv_i64, uint32_t, uint32_t); | |
39 | ||
38cadeba RH |
40 | typedef void gen_helper_gvec_flags_3(TCGv_i32, TCGv_ptr, TCGv_ptr, |
41 | TCGv_ptr, TCGv_i32); | |
757f9cff RH |
42 | typedef void gen_helper_gvec_flags_4(TCGv_i32, TCGv_ptr, TCGv_ptr, |
43 | TCGv_ptr, TCGv_ptr, TCGv_i32); | |
44 | ||
c4e7c493 | 45 | typedef void gen_helper_gvec_mem(TCGv_env, TCGv_ptr, TCGv_i64, TCGv_i32); |
f6dbf62a RH |
46 | typedef void gen_helper_gvec_mem_scatter(TCGv_env, TCGv_ptr, TCGv_ptr, |
47 | TCGv_ptr, TCGv_i64, TCGv_i32); | |
c4e7c493 | 48 | |
ccd841c3 RH |
49 | /* |
50 | * Helpers for extracting complex instruction fields. | |
51 | */ | |
52 | ||
53 | /* See e.g. ASR (immediate, predicated). | |
54 | * Returns -1 for unallocated encoding; diagnose later. | |
55 | */ | |
451e4ffd | 56 | static int tszimm_esz(DisasContext *s, int x) |
ccd841c3 RH |
57 | { |
58 | x >>= 3; /* discard imm3 */ | |
59 | return 31 - clz32(x); | |
60 | } | |
61 | ||
451e4ffd | 62 | static int tszimm_shr(DisasContext *s, int x) |
ccd841c3 | 63 | { |
451e4ffd | 64 | return (16 << tszimm_esz(s, x)) - x; |
ccd841c3 RH |
65 | } |
66 | ||
67 | /* See e.g. LSL (immediate, predicated). */ | |
451e4ffd | 68 | static int tszimm_shl(DisasContext *s, int x) |
ccd841c3 | 69 | { |
451e4ffd | 70 | return x - (8 << tszimm_esz(s, x)); |
ccd841c3 RH |
71 | } |
72 | ||
f25a2361 | 73 | /* The SH bit is in bit 8. Extract the low 8 and shift. */ |
451e4ffd | 74 | static inline int expand_imm_sh8s(DisasContext *s, int x) |
f25a2361 RH |
75 | { |
76 | return (int8_t)x << (x & 0x100 ? 8 : 0); | |
77 | } | |
78 | ||
451e4ffd | 79 | static inline int expand_imm_sh8u(DisasContext *s, int x) |
6e6a157d RH |
80 | { |
81 | return (uint8_t)x << (x & 0x100 ? 8 : 0); | |
82 | } | |
83 | ||
c4e7c493 RH |
84 | /* Convert a 2-bit memory size (msz) to a 4-bit data type (dtype) |
85 | * with unsigned data. C.f. SVE Memory Contiguous Load Group. | |
86 | */ | |
451e4ffd | 87 | static inline int msz_dtype(DisasContext *s, int msz) |
c4e7c493 RH |
88 | { |
89 | static const uint8_t dtype[4] = { 0, 5, 10, 15 }; | |
90 | return dtype[msz]; | |
91 | } | |
92 | ||
38388f7e RH |
93 | /* |
94 | * Include the generated decoder. | |
95 | */ | |
96 | ||
139c1837 | 97 | #include "decode-sve.c.inc" |
38388f7e RH |
98 | |
99 | /* | |
100 | * Implement all of the translator functions referenced by the decoder. | |
101 | */ | |
102 | ||
d1822297 RH |
103 | /* Return the offset info CPUARMState of the predicate vector register Pn. |
104 | * Note for this purpose, FFR is P16. | |
105 | */ | |
106 | static inline int pred_full_reg_offset(DisasContext *s, int regno) | |
107 | { | |
108 | return offsetof(CPUARMState, vfp.pregs[regno]); | |
109 | } | |
110 | ||
111 | /* Return the byte size of the whole predicate register, VL / 64. */ | |
112 | static inline int pred_full_reg_size(DisasContext *s) | |
113 | { | |
114 | return s->sve_len >> 3; | |
115 | } | |
116 | ||
516e246a RH |
117 | /* Round up the size of a register to a size allowed by |
118 | * the tcg vector infrastructure. Any operation which uses this | |
119 | * size may assume that the bits above pred_full_reg_size are zero, | |
120 | * and must leave them the same way. | |
121 | * | |
122 | * Note that this is not needed for the vector registers as they | |
123 | * are always properly sized for tcg vectors. | |
124 | */ | |
125 | static int size_for_gvec(int size) | |
126 | { | |
127 | if (size <= 8) { | |
128 | return 8; | |
129 | } else { | |
130 | return QEMU_ALIGN_UP(size, 16); | |
131 | } | |
132 | } | |
133 | ||
134 | static int pred_gvec_reg_size(DisasContext *s) | |
135 | { | |
136 | return size_for_gvec(pred_full_reg_size(s)); | |
137 | } | |
138 | ||
40e32e5a RH |
139 | /* Invoke an out-of-line helper on 2 Zregs. */ |
140 | static void gen_gvec_ool_zz(DisasContext *s, gen_helper_gvec_2 *fn, | |
141 | int rd, int rn, int data) | |
142 | { | |
143 | unsigned vsz = vec_full_reg_size(s); | |
144 | tcg_gen_gvec_2_ool(vec_full_reg_offset(s, rd), | |
145 | vec_full_reg_offset(s, rn), | |
146 | vsz, vsz, data, fn); | |
147 | } | |
148 | ||
e645d1a1 RH |
149 | /* Invoke an out-of-line helper on 3 Zregs. */ |
150 | static void gen_gvec_ool_zzz(DisasContext *s, gen_helper_gvec_3 *fn, | |
151 | int rd, int rn, int rm, int data) | |
152 | { | |
153 | unsigned vsz = vec_full_reg_size(s); | |
154 | tcg_gen_gvec_3_ool(vec_full_reg_offset(s, rd), | |
155 | vec_full_reg_offset(s, rn), | |
156 | vec_full_reg_offset(s, rm), | |
157 | vsz, vsz, data, fn); | |
158 | } | |
159 | ||
38650638 RH |
160 | /* Invoke an out-of-line helper on 4 Zregs. */ |
161 | static void gen_gvec_ool_zzzz(DisasContext *s, gen_helper_gvec_4 *fn, | |
162 | int rd, int rn, int rm, int ra, int data) | |
163 | { | |
164 | unsigned vsz = vec_full_reg_size(s); | |
165 | tcg_gen_gvec_4_ool(vec_full_reg_offset(s, rd), | |
166 | vec_full_reg_offset(s, rn), | |
167 | vec_full_reg_offset(s, rm), | |
168 | vec_full_reg_offset(s, ra), | |
169 | vsz, vsz, data, fn); | |
170 | } | |
171 | ||
96a461f7 RH |
172 | /* Invoke an out-of-line helper on 2 Zregs and a predicate. */ |
173 | static void gen_gvec_ool_zzp(DisasContext *s, gen_helper_gvec_3 *fn, | |
174 | int rd, int rn, int pg, int data) | |
175 | { | |
176 | unsigned vsz = vec_full_reg_size(s); | |
177 | tcg_gen_gvec_3_ool(vec_full_reg_offset(s, rd), | |
178 | vec_full_reg_offset(s, rn), | |
179 | pred_full_reg_offset(s, pg), | |
180 | vsz, vsz, data, fn); | |
181 | } | |
182 | ||
36cbb7a8 RH |
183 | /* Invoke an out-of-line helper on 3 Zregs and a predicate. */ |
184 | static void gen_gvec_ool_zzzp(DisasContext *s, gen_helper_gvec_4 *fn, | |
185 | int rd, int rn, int rm, int pg, int data) | |
186 | { | |
187 | unsigned vsz = vec_full_reg_size(s); | |
188 | tcg_gen_gvec_4_ool(vec_full_reg_offset(s, rd), | |
189 | vec_full_reg_offset(s, rn), | |
190 | vec_full_reg_offset(s, rm), | |
191 | pred_full_reg_offset(s, pg), | |
192 | vsz, vsz, data, fn); | |
193 | } | |
f7d79c41 | 194 | |
36cbb7a8 | 195 | /* Invoke a vector expander on two Zregs. */ |
f7d79c41 RH |
196 | static void gen_gvec_fn_zz(DisasContext *s, GVecGen2Fn *gvec_fn, |
197 | int esz, int rd, int rn) | |
38388f7e | 198 | { |
f7d79c41 RH |
199 | unsigned vsz = vec_full_reg_size(s); |
200 | gvec_fn(esz, vec_full_reg_offset(s, rd), | |
201 | vec_full_reg_offset(s, rn), vsz, vsz); | |
38388f7e RH |
202 | } |
203 | ||
39eea561 | 204 | /* Invoke a vector expander on three Zregs. */ |
28c4da31 RH |
205 | static void gen_gvec_fn_zzz(DisasContext *s, GVecGen3Fn *gvec_fn, |
206 | int esz, int rd, int rn, int rm) | |
38388f7e | 207 | { |
28c4da31 RH |
208 | unsigned vsz = vec_full_reg_size(s); |
209 | gvec_fn(esz, vec_full_reg_offset(s, rd), | |
210 | vec_full_reg_offset(s, rn), | |
211 | vec_full_reg_offset(s, rm), vsz, vsz); | |
38388f7e RH |
212 | } |
213 | ||
911cdc6d RH |
214 | /* Invoke a vector expander on four Zregs. */ |
215 | static void gen_gvec_fn_zzzz(DisasContext *s, GVecGen4Fn *gvec_fn, | |
216 | int esz, int rd, int rn, int rm, int ra) | |
217 | { | |
218 | unsigned vsz = vec_full_reg_size(s); | |
219 | gvec_fn(esz, vec_full_reg_offset(s, rd), | |
220 | vec_full_reg_offset(s, rn), | |
221 | vec_full_reg_offset(s, rm), | |
222 | vec_full_reg_offset(s, ra), vsz, vsz); | |
223 | } | |
224 | ||
39eea561 RH |
225 | /* Invoke a vector move on two Zregs. */ |
226 | static bool do_mov_z(DisasContext *s, int rd, int rn) | |
38388f7e | 227 | { |
f7d79c41 RH |
228 | if (sve_access_check(s)) { |
229 | gen_gvec_fn_zz(s, tcg_gen_gvec_mov, MO_8, rd, rn); | |
230 | } | |
231 | return true; | |
38388f7e RH |
232 | } |
233 | ||
d9d78dcc RH |
234 | /* Initialize a Zreg with replications of a 64-bit immediate. */ |
235 | static void do_dupi_z(DisasContext *s, int rd, uint64_t word) | |
236 | { | |
237 | unsigned vsz = vec_full_reg_size(s); | |
8711e71f | 238 | tcg_gen_gvec_dup_imm(MO_64, vec_full_reg_offset(s, rd), vsz, vsz, word); |
d9d78dcc RH |
239 | } |
240 | ||
516e246a | 241 | /* Invoke a vector expander on three Pregs. */ |
dd81a8d7 RH |
242 | static void gen_gvec_fn_ppp(DisasContext *s, GVecGen3Fn *gvec_fn, |
243 | int rd, int rn, int rm) | |
516e246a | 244 | { |
dd81a8d7 RH |
245 | unsigned psz = pred_gvec_reg_size(s); |
246 | gvec_fn(MO_64, pred_full_reg_offset(s, rd), | |
247 | pred_full_reg_offset(s, rn), | |
248 | pred_full_reg_offset(s, rm), psz, psz); | |
516e246a RH |
249 | } |
250 | ||
251 | /* Invoke a vector move on two Pregs. */ | |
252 | static bool do_mov_p(DisasContext *s, int rd, int rn) | |
253 | { | |
d0b2df5a RH |
254 | if (sve_access_check(s)) { |
255 | unsigned psz = pred_gvec_reg_size(s); | |
256 | tcg_gen_gvec_mov(MO_8, pred_full_reg_offset(s, rd), | |
257 | pred_full_reg_offset(s, rn), psz, psz); | |
258 | } | |
259 | return true; | |
516e246a RH |
260 | } |
261 | ||
9e18d7a6 RH |
262 | /* Set the cpu flags as per a return from an SVE helper. */ |
263 | static void do_pred_flags(TCGv_i32 t) | |
264 | { | |
265 | tcg_gen_mov_i32(cpu_NF, t); | |
266 | tcg_gen_andi_i32(cpu_ZF, t, 2); | |
267 | tcg_gen_andi_i32(cpu_CF, t, 1); | |
268 | tcg_gen_movi_i32(cpu_VF, 0); | |
269 | } | |
270 | ||
271 | /* Subroutines computing the ARM PredTest psuedofunction. */ | |
272 | static void do_predtest1(TCGv_i64 d, TCGv_i64 g) | |
273 | { | |
274 | TCGv_i32 t = tcg_temp_new_i32(); | |
275 | ||
276 | gen_helper_sve_predtest1(t, d, g); | |
277 | do_pred_flags(t); | |
278 | tcg_temp_free_i32(t); | |
279 | } | |
280 | ||
281 | static void do_predtest(DisasContext *s, int dofs, int gofs, int words) | |
282 | { | |
283 | TCGv_ptr dptr = tcg_temp_new_ptr(); | |
284 | TCGv_ptr gptr = tcg_temp_new_ptr(); | |
392acacc | 285 | TCGv_i32 t = tcg_temp_new_i32(); |
9e18d7a6 RH |
286 | |
287 | tcg_gen_addi_ptr(dptr, cpu_env, dofs); | |
288 | tcg_gen_addi_ptr(gptr, cpu_env, gofs); | |
9e18d7a6 | 289 | |
392acacc | 290 | gen_helper_sve_predtest(t, dptr, gptr, tcg_constant_i32(words)); |
9e18d7a6 RH |
291 | tcg_temp_free_ptr(dptr); |
292 | tcg_temp_free_ptr(gptr); | |
293 | ||
294 | do_pred_flags(t); | |
295 | tcg_temp_free_i32(t); | |
296 | } | |
297 | ||
028e2a7b RH |
298 | /* For each element size, the bits within a predicate word that are active. */ |
299 | const uint64_t pred_esz_masks[4] = { | |
300 | 0xffffffffffffffffull, 0x5555555555555555ull, | |
301 | 0x1111111111111111ull, 0x0101010101010101ull | |
302 | }; | |
303 | ||
39eea561 RH |
304 | /* |
305 | *** SVE Logical - Unpredicated Group | |
306 | */ | |
307 | ||
28c4da31 RH |
308 | static bool do_zzz_fn(DisasContext *s, arg_rrr_esz *a, GVecGen3Fn *gvec_fn) |
309 | { | |
310 | if (sve_access_check(s)) { | |
311 | gen_gvec_fn_zzz(s, gvec_fn, a->esz, a->rd, a->rn, a->rm); | |
312 | } | |
313 | return true; | |
314 | } | |
315 | ||
3a7be554 | 316 | static bool trans_AND_zzz(DisasContext *s, arg_rrr_esz *a) |
39eea561 | 317 | { |
28c4da31 | 318 | return do_zzz_fn(s, a, tcg_gen_gvec_and); |
39eea561 RH |
319 | } |
320 | ||
3a7be554 | 321 | static bool trans_ORR_zzz(DisasContext *s, arg_rrr_esz *a) |
39eea561 | 322 | { |
28c4da31 | 323 | return do_zzz_fn(s, a, tcg_gen_gvec_or); |
39eea561 RH |
324 | } |
325 | ||
3a7be554 | 326 | static bool trans_EOR_zzz(DisasContext *s, arg_rrr_esz *a) |
39eea561 | 327 | { |
28c4da31 | 328 | return do_zzz_fn(s, a, tcg_gen_gvec_xor); |
39eea561 RH |
329 | } |
330 | ||
3a7be554 | 331 | static bool trans_BIC_zzz(DisasContext *s, arg_rrr_esz *a) |
38388f7e | 332 | { |
28c4da31 | 333 | return do_zzz_fn(s, a, tcg_gen_gvec_andc); |
38388f7e | 334 | } |
d1822297 | 335 | |
e6eba6e5 RH |
336 | static void gen_xar8_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m, int64_t sh) |
337 | { | |
338 | TCGv_i64 t = tcg_temp_new_i64(); | |
339 | uint64_t mask = dup_const(MO_8, 0xff >> sh); | |
340 | ||
341 | tcg_gen_xor_i64(t, n, m); | |
342 | tcg_gen_shri_i64(d, t, sh); | |
343 | tcg_gen_shli_i64(t, t, 8 - sh); | |
344 | tcg_gen_andi_i64(d, d, mask); | |
345 | tcg_gen_andi_i64(t, t, ~mask); | |
346 | tcg_gen_or_i64(d, d, t); | |
347 | tcg_temp_free_i64(t); | |
348 | } | |
349 | ||
350 | static void gen_xar16_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m, int64_t sh) | |
351 | { | |
352 | TCGv_i64 t = tcg_temp_new_i64(); | |
353 | uint64_t mask = dup_const(MO_16, 0xffff >> sh); | |
354 | ||
355 | tcg_gen_xor_i64(t, n, m); | |
356 | tcg_gen_shri_i64(d, t, sh); | |
357 | tcg_gen_shli_i64(t, t, 16 - sh); | |
358 | tcg_gen_andi_i64(d, d, mask); | |
359 | tcg_gen_andi_i64(t, t, ~mask); | |
360 | tcg_gen_or_i64(d, d, t); | |
361 | tcg_temp_free_i64(t); | |
362 | } | |
363 | ||
364 | static void gen_xar_i32(TCGv_i32 d, TCGv_i32 n, TCGv_i32 m, int32_t sh) | |
365 | { | |
366 | tcg_gen_xor_i32(d, n, m); | |
367 | tcg_gen_rotri_i32(d, d, sh); | |
368 | } | |
369 | ||
370 | static void gen_xar_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m, int64_t sh) | |
371 | { | |
372 | tcg_gen_xor_i64(d, n, m); | |
373 | tcg_gen_rotri_i64(d, d, sh); | |
374 | } | |
375 | ||
376 | static void gen_xar_vec(unsigned vece, TCGv_vec d, TCGv_vec n, | |
377 | TCGv_vec m, int64_t sh) | |
378 | { | |
379 | tcg_gen_xor_vec(vece, d, n, m); | |
380 | tcg_gen_rotri_vec(vece, d, d, sh); | |
381 | } | |
382 | ||
383 | void gen_gvec_xar(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, | |
384 | uint32_t rm_ofs, int64_t shift, | |
385 | uint32_t opr_sz, uint32_t max_sz) | |
386 | { | |
387 | static const TCGOpcode vecop[] = { INDEX_op_rotli_vec, 0 }; | |
388 | static const GVecGen3i ops[4] = { | |
389 | { .fni8 = gen_xar8_i64, | |
390 | .fniv = gen_xar_vec, | |
391 | .fno = gen_helper_sve2_xar_b, | |
392 | .opt_opc = vecop, | |
393 | .vece = MO_8 }, | |
394 | { .fni8 = gen_xar16_i64, | |
395 | .fniv = gen_xar_vec, | |
396 | .fno = gen_helper_sve2_xar_h, | |
397 | .opt_opc = vecop, | |
398 | .vece = MO_16 }, | |
399 | { .fni4 = gen_xar_i32, | |
400 | .fniv = gen_xar_vec, | |
401 | .fno = gen_helper_sve2_xar_s, | |
402 | .opt_opc = vecop, | |
403 | .vece = MO_32 }, | |
404 | { .fni8 = gen_xar_i64, | |
405 | .fniv = gen_xar_vec, | |
406 | .fno = gen_helper_gvec_xar_d, | |
407 | .opt_opc = vecop, | |
408 | .vece = MO_64 } | |
409 | }; | |
410 | int esize = 8 << vece; | |
411 | ||
412 | /* The SVE2 range is 1 .. esize; the AdvSIMD range is 0 .. esize-1. */ | |
413 | tcg_debug_assert(shift >= 0); | |
414 | tcg_debug_assert(shift <= esize); | |
415 | shift &= esize - 1; | |
416 | ||
417 | if (shift == 0) { | |
418 | /* xar with no rotate devolves to xor. */ | |
419 | tcg_gen_gvec_xor(vece, rd_ofs, rn_ofs, rm_ofs, opr_sz, max_sz); | |
420 | } else { | |
421 | tcg_gen_gvec_3i(rd_ofs, rn_ofs, rm_ofs, opr_sz, max_sz, | |
422 | shift, &ops[vece]); | |
423 | } | |
424 | } | |
425 | ||
426 | static bool trans_XAR(DisasContext *s, arg_rrri_esz *a) | |
427 | { | |
428 | if (a->esz < 0 || !dc_isar_feature(aa64_sve2, s)) { | |
429 | return false; | |
430 | } | |
431 | if (sve_access_check(s)) { | |
432 | unsigned vsz = vec_full_reg_size(s); | |
433 | gen_gvec_xar(a->esz, vec_full_reg_offset(s, a->rd), | |
434 | vec_full_reg_offset(s, a->rn), | |
435 | vec_full_reg_offset(s, a->rm), a->imm, vsz, vsz); | |
436 | } | |
437 | return true; | |
438 | } | |
439 | ||
911cdc6d RH |
440 | static bool do_sve2_zzzz_fn(DisasContext *s, arg_rrrr_esz *a, GVecGen4Fn *fn) |
441 | { | |
442 | if (!dc_isar_feature(aa64_sve2, s)) { | |
443 | return false; | |
444 | } | |
445 | if (sve_access_check(s)) { | |
446 | gen_gvec_fn_zzzz(s, fn, a->esz, a->rd, a->rn, a->rm, a->ra); | |
447 | } | |
448 | return true; | |
449 | } | |
450 | ||
451 | static void gen_eor3_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m, TCGv_i64 k) | |
452 | { | |
453 | tcg_gen_xor_i64(d, n, m); | |
454 | tcg_gen_xor_i64(d, d, k); | |
455 | } | |
456 | ||
457 | static void gen_eor3_vec(unsigned vece, TCGv_vec d, TCGv_vec n, | |
458 | TCGv_vec m, TCGv_vec k) | |
459 | { | |
460 | tcg_gen_xor_vec(vece, d, n, m); | |
461 | tcg_gen_xor_vec(vece, d, d, k); | |
462 | } | |
463 | ||
464 | static void gen_eor3(unsigned vece, uint32_t d, uint32_t n, uint32_t m, | |
465 | uint32_t a, uint32_t oprsz, uint32_t maxsz) | |
466 | { | |
467 | static const GVecGen4 op = { | |
468 | .fni8 = gen_eor3_i64, | |
469 | .fniv = gen_eor3_vec, | |
470 | .fno = gen_helper_sve2_eor3, | |
471 | .vece = MO_64, | |
472 | .prefer_i64 = TCG_TARGET_REG_BITS == 64, | |
473 | }; | |
474 | tcg_gen_gvec_4(d, n, m, a, oprsz, maxsz, &op); | |
475 | } | |
476 | ||
477 | static bool trans_EOR3(DisasContext *s, arg_rrrr_esz *a) | |
478 | { | |
479 | return do_sve2_zzzz_fn(s, a, gen_eor3); | |
480 | } | |
481 | ||
482 | static void gen_bcax_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m, TCGv_i64 k) | |
483 | { | |
484 | tcg_gen_andc_i64(d, m, k); | |
485 | tcg_gen_xor_i64(d, d, n); | |
486 | } | |
487 | ||
488 | static void gen_bcax_vec(unsigned vece, TCGv_vec d, TCGv_vec n, | |
489 | TCGv_vec m, TCGv_vec k) | |
490 | { | |
491 | tcg_gen_andc_vec(vece, d, m, k); | |
492 | tcg_gen_xor_vec(vece, d, d, n); | |
493 | } | |
494 | ||
495 | static void gen_bcax(unsigned vece, uint32_t d, uint32_t n, uint32_t m, | |
496 | uint32_t a, uint32_t oprsz, uint32_t maxsz) | |
497 | { | |
498 | static const GVecGen4 op = { | |
499 | .fni8 = gen_bcax_i64, | |
500 | .fniv = gen_bcax_vec, | |
501 | .fno = gen_helper_sve2_bcax, | |
502 | .vece = MO_64, | |
503 | .prefer_i64 = TCG_TARGET_REG_BITS == 64, | |
504 | }; | |
505 | tcg_gen_gvec_4(d, n, m, a, oprsz, maxsz, &op); | |
506 | } | |
507 | ||
508 | static bool trans_BCAX(DisasContext *s, arg_rrrr_esz *a) | |
509 | { | |
510 | return do_sve2_zzzz_fn(s, a, gen_bcax); | |
511 | } | |
512 | ||
513 | static void gen_bsl(unsigned vece, uint32_t d, uint32_t n, uint32_t m, | |
514 | uint32_t a, uint32_t oprsz, uint32_t maxsz) | |
515 | { | |
516 | /* BSL differs from the generic bitsel in argument ordering. */ | |
517 | tcg_gen_gvec_bitsel(vece, d, a, n, m, oprsz, maxsz); | |
518 | } | |
519 | ||
520 | static bool trans_BSL(DisasContext *s, arg_rrrr_esz *a) | |
521 | { | |
522 | return do_sve2_zzzz_fn(s, a, gen_bsl); | |
523 | } | |
524 | ||
525 | static void gen_bsl1n_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m, TCGv_i64 k) | |
526 | { | |
527 | tcg_gen_andc_i64(n, k, n); | |
528 | tcg_gen_andc_i64(m, m, k); | |
529 | tcg_gen_or_i64(d, n, m); | |
530 | } | |
531 | ||
532 | static void gen_bsl1n_vec(unsigned vece, TCGv_vec d, TCGv_vec n, | |
533 | TCGv_vec m, TCGv_vec k) | |
534 | { | |
535 | if (TCG_TARGET_HAS_bitsel_vec) { | |
536 | tcg_gen_not_vec(vece, n, n); | |
537 | tcg_gen_bitsel_vec(vece, d, k, n, m); | |
538 | } else { | |
539 | tcg_gen_andc_vec(vece, n, k, n); | |
540 | tcg_gen_andc_vec(vece, m, m, k); | |
541 | tcg_gen_or_vec(vece, d, n, m); | |
542 | } | |
543 | } | |
544 | ||
545 | static void gen_bsl1n(unsigned vece, uint32_t d, uint32_t n, uint32_t m, | |
546 | uint32_t a, uint32_t oprsz, uint32_t maxsz) | |
547 | { | |
548 | static const GVecGen4 op = { | |
549 | .fni8 = gen_bsl1n_i64, | |
550 | .fniv = gen_bsl1n_vec, | |
551 | .fno = gen_helper_sve2_bsl1n, | |
552 | .vece = MO_64, | |
553 | .prefer_i64 = TCG_TARGET_REG_BITS == 64, | |
554 | }; | |
555 | tcg_gen_gvec_4(d, n, m, a, oprsz, maxsz, &op); | |
556 | } | |
557 | ||
558 | static bool trans_BSL1N(DisasContext *s, arg_rrrr_esz *a) | |
559 | { | |
560 | return do_sve2_zzzz_fn(s, a, gen_bsl1n); | |
561 | } | |
562 | ||
563 | static void gen_bsl2n_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m, TCGv_i64 k) | |
564 | { | |
565 | /* | |
566 | * Z[dn] = (n & k) | (~m & ~k) | |
567 | * = | ~(m | k) | |
568 | */ | |
569 | tcg_gen_and_i64(n, n, k); | |
570 | if (TCG_TARGET_HAS_orc_i64) { | |
571 | tcg_gen_or_i64(m, m, k); | |
572 | tcg_gen_orc_i64(d, n, m); | |
573 | } else { | |
574 | tcg_gen_nor_i64(m, m, k); | |
575 | tcg_gen_or_i64(d, n, m); | |
576 | } | |
577 | } | |
578 | ||
579 | static void gen_bsl2n_vec(unsigned vece, TCGv_vec d, TCGv_vec n, | |
580 | TCGv_vec m, TCGv_vec k) | |
581 | { | |
582 | if (TCG_TARGET_HAS_bitsel_vec) { | |
583 | tcg_gen_not_vec(vece, m, m); | |
584 | tcg_gen_bitsel_vec(vece, d, k, n, m); | |
585 | } else { | |
586 | tcg_gen_and_vec(vece, n, n, k); | |
587 | tcg_gen_or_vec(vece, m, m, k); | |
588 | tcg_gen_orc_vec(vece, d, n, m); | |
589 | } | |
590 | } | |
591 | ||
592 | static void gen_bsl2n(unsigned vece, uint32_t d, uint32_t n, uint32_t m, | |
593 | uint32_t a, uint32_t oprsz, uint32_t maxsz) | |
594 | { | |
595 | static const GVecGen4 op = { | |
596 | .fni8 = gen_bsl2n_i64, | |
597 | .fniv = gen_bsl2n_vec, | |
598 | .fno = gen_helper_sve2_bsl2n, | |
599 | .vece = MO_64, | |
600 | .prefer_i64 = TCG_TARGET_REG_BITS == 64, | |
601 | }; | |
602 | tcg_gen_gvec_4(d, n, m, a, oprsz, maxsz, &op); | |
603 | } | |
604 | ||
605 | static bool trans_BSL2N(DisasContext *s, arg_rrrr_esz *a) | |
606 | { | |
607 | return do_sve2_zzzz_fn(s, a, gen_bsl2n); | |
608 | } | |
609 | ||
610 | static void gen_nbsl_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m, TCGv_i64 k) | |
611 | { | |
612 | tcg_gen_and_i64(n, n, k); | |
613 | tcg_gen_andc_i64(m, m, k); | |
614 | tcg_gen_nor_i64(d, n, m); | |
615 | } | |
616 | ||
617 | static void gen_nbsl_vec(unsigned vece, TCGv_vec d, TCGv_vec n, | |
618 | TCGv_vec m, TCGv_vec k) | |
619 | { | |
620 | tcg_gen_bitsel_vec(vece, d, k, n, m); | |
621 | tcg_gen_not_vec(vece, d, d); | |
622 | } | |
623 | ||
624 | static void gen_nbsl(unsigned vece, uint32_t d, uint32_t n, uint32_t m, | |
625 | uint32_t a, uint32_t oprsz, uint32_t maxsz) | |
626 | { | |
627 | static const GVecGen4 op = { | |
628 | .fni8 = gen_nbsl_i64, | |
629 | .fniv = gen_nbsl_vec, | |
630 | .fno = gen_helper_sve2_nbsl, | |
631 | .vece = MO_64, | |
632 | .prefer_i64 = TCG_TARGET_REG_BITS == 64, | |
633 | }; | |
634 | tcg_gen_gvec_4(d, n, m, a, oprsz, maxsz, &op); | |
635 | } | |
636 | ||
637 | static bool trans_NBSL(DisasContext *s, arg_rrrr_esz *a) | |
638 | { | |
639 | return do_sve2_zzzz_fn(s, a, gen_nbsl); | |
640 | } | |
641 | ||
fea98f9c RH |
642 | /* |
643 | *** SVE Integer Arithmetic - Unpredicated Group | |
644 | */ | |
645 | ||
3a7be554 | 646 | static bool trans_ADD_zzz(DisasContext *s, arg_rrr_esz *a) |
fea98f9c | 647 | { |
28c4da31 | 648 | return do_zzz_fn(s, a, tcg_gen_gvec_add); |
fea98f9c RH |
649 | } |
650 | ||
3a7be554 | 651 | static bool trans_SUB_zzz(DisasContext *s, arg_rrr_esz *a) |
fea98f9c | 652 | { |
28c4da31 | 653 | return do_zzz_fn(s, a, tcg_gen_gvec_sub); |
fea98f9c RH |
654 | } |
655 | ||
3a7be554 | 656 | static bool trans_SQADD_zzz(DisasContext *s, arg_rrr_esz *a) |
fea98f9c | 657 | { |
28c4da31 | 658 | return do_zzz_fn(s, a, tcg_gen_gvec_ssadd); |
fea98f9c RH |
659 | } |
660 | ||
3a7be554 | 661 | static bool trans_SQSUB_zzz(DisasContext *s, arg_rrr_esz *a) |
fea98f9c | 662 | { |
28c4da31 | 663 | return do_zzz_fn(s, a, tcg_gen_gvec_sssub); |
fea98f9c RH |
664 | } |
665 | ||
3a7be554 | 666 | static bool trans_UQADD_zzz(DisasContext *s, arg_rrr_esz *a) |
fea98f9c | 667 | { |
28c4da31 | 668 | return do_zzz_fn(s, a, tcg_gen_gvec_usadd); |
fea98f9c RH |
669 | } |
670 | ||
3a7be554 | 671 | static bool trans_UQSUB_zzz(DisasContext *s, arg_rrr_esz *a) |
fea98f9c | 672 | { |
28c4da31 | 673 | return do_zzz_fn(s, a, tcg_gen_gvec_ussub); |
fea98f9c RH |
674 | } |
675 | ||
f97cfd59 RH |
676 | /* |
677 | *** SVE Integer Arithmetic - Binary Predicated Group | |
678 | */ | |
679 | ||
680 | static bool do_zpzz_ool(DisasContext *s, arg_rprr_esz *a, gen_helper_gvec_4 *fn) | |
681 | { | |
f97cfd59 RH |
682 | if (fn == NULL) { |
683 | return false; | |
684 | } | |
685 | if (sve_access_check(s)) { | |
36cbb7a8 | 686 | gen_gvec_ool_zzzp(s, fn, a->rd, a->rn, a->rm, a->pg, 0); |
f97cfd59 RH |
687 | } |
688 | return true; | |
689 | } | |
690 | ||
a2103582 RH |
691 | /* Select active elememnts from Zn and inactive elements from Zm, |
692 | * storing the result in Zd. | |
693 | */ | |
694 | static void do_sel_z(DisasContext *s, int rd, int rn, int rm, int pg, int esz) | |
695 | { | |
696 | static gen_helper_gvec_4 * const fns[4] = { | |
697 | gen_helper_sve_sel_zpzz_b, gen_helper_sve_sel_zpzz_h, | |
698 | gen_helper_sve_sel_zpzz_s, gen_helper_sve_sel_zpzz_d | |
699 | }; | |
36cbb7a8 | 700 | gen_gvec_ool_zzzp(s, fns[esz], rd, rn, rm, pg, 0); |
a2103582 RH |
701 | } |
702 | ||
f97cfd59 | 703 | #define DO_ZPZZ(NAME, name) \ |
3a7be554 | 704 | static bool trans_##NAME##_zpzz(DisasContext *s, arg_rprr_esz *a) \ |
f97cfd59 RH |
705 | { \ |
706 | static gen_helper_gvec_4 * const fns[4] = { \ | |
707 | gen_helper_sve_##name##_zpzz_b, gen_helper_sve_##name##_zpzz_h, \ | |
708 | gen_helper_sve_##name##_zpzz_s, gen_helper_sve_##name##_zpzz_d, \ | |
709 | }; \ | |
710 | return do_zpzz_ool(s, a, fns[a->esz]); \ | |
711 | } | |
712 | ||
713 | DO_ZPZZ(AND, and) | |
714 | DO_ZPZZ(EOR, eor) | |
715 | DO_ZPZZ(ORR, orr) | |
716 | DO_ZPZZ(BIC, bic) | |
717 | ||
718 | DO_ZPZZ(ADD, add) | |
719 | DO_ZPZZ(SUB, sub) | |
720 | ||
721 | DO_ZPZZ(SMAX, smax) | |
722 | DO_ZPZZ(UMAX, umax) | |
723 | DO_ZPZZ(SMIN, smin) | |
724 | DO_ZPZZ(UMIN, umin) | |
725 | DO_ZPZZ(SABD, sabd) | |
726 | DO_ZPZZ(UABD, uabd) | |
727 | ||
728 | DO_ZPZZ(MUL, mul) | |
729 | DO_ZPZZ(SMULH, smulh) | |
730 | DO_ZPZZ(UMULH, umulh) | |
731 | ||
27721dbb RH |
732 | DO_ZPZZ(ASR, asr) |
733 | DO_ZPZZ(LSR, lsr) | |
734 | DO_ZPZZ(LSL, lsl) | |
735 | ||
3a7be554 | 736 | static bool trans_SDIV_zpzz(DisasContext *s, arg_rprr_esz *a) |
f97cfd59 RH |
737 | { |
738 | static gen_helper_gvec_4 * const fns[4] = { | |
739 | NULL, NULL, gen_helper_sve_sdiv_zpzz_s, gen_helper_sve_sdiv_zpzz_d | |
740 | }; | |
741 | return do_zpzz_ool(s, a, fns[a->esz]); | |
742 | } | |
743 | ||
3a7be554 | 744 | static bool trans_UDIV_zpzz(DisasContext *s, arg_rprr_esz *a) |
f97cfd59 RH |
745 | { |
746 | static gen_helper_gvec_4 * const fns[4] = { | |
747 | NULL, NULL, gen_helper_sve_udiv_zpzz_s, gen_helper_sve_udiv_zpzz_d | |
748 | }; | |
749 | return do_zpzz_ool(s, a, fns[a->esz]); | |
750 | } | |
751 | ||
3a7be554 | 752 | static bool trans_SEL_zpzz(DisasContext *s, arg_rprr_esz *a) |
a2103582 RH |
753 | { |
754 | if (sve_access_check(s)) { | |
755 | do_sel_z(s, a->rd, a->rn, a->rm, a->pg, a->esz); | |
756 | } | |
757 | return true; | |
758 | } | |
d3fe4a29 | 759 | |
f97cfd59 RH |
760 | #undef DO_ZPZZ |
761 | ||
afac6d04 RH |
762 | /* |
763 | *** SVE Integer Arithmetic - Unary Predicated Group | |
764 | */ | |
765 | ||
766 | static bool do_zpz_ool(DisasContext *s, arg_rpr_esz *a, gen_helper_gvec_3 *fn) | |
767 | { | |
768 | if (fn == NULL) { | |
769 | return false; | |
770 | } | |
771 | if (sve_access_check(s)) { | |
96a461f7 | 772 | gen_gvec_ool_zzp(s, fn, a->rd, a->rn, a->pg, 0); |
afac6d04 RH |
773 | } |
774 | return true; | |
775 | } | |
776 | ||
777 | #define DO_ZPZ(NAME, name) \ | |
3a7be554 | 778 | static bool trans_##NAME(DisasContext *s, arg_rpr_esz *a) \ |
afac6d04 RH |
779 | { \ |
780 | static gen_helper_gvec_3 * const fns[4] = { \ | |
781 | gen_helper_sve_##name##_b, gen_helper_sve_##name##_h, \ | |
782 | gen_helper_sve_##name##_s, gen_helper_sve_##name##_d, \ | |
783 | }; \ | |
784 | return do_zpz_ool(s, a, fns[a->esz]); \ | |
785 | } | |
786 | ||
787 | DO_ZPZ(CLS, cls) | |
788 | DO_ZPZ(CLZ, clz) | |
789 | DO_ZPZ(CNT_zpz, cnt_zpz) | |
790 | DO_ZPZ(CNOT, cnot) | |
791 | DO_ZPZ(NOT_zpz, not_zpz) | |
792 | DO_ZPZ(ABS, abs) | |
793 | DO_ZPZ(NEG, neg) | |
794 | ||
3a7be554 | 795 | static bool trans_FABS(DisasContext *s, arg_rpr_esz *a) |
afac6d04 RH |
796 | { |
797 | static gen_helper_gvec_3 * const fns[4] = { | |
798 | NULL, | |
799 | gen_helper_sve_fabs_h, | |
800 | gen_helper_sve_fabs_s, | |
801 | gen_helper_sve_fabs_d | |
802 | }; | |
803 | return do_zpz_ool(s, a, fns[a->esz]); | |
804 | } | |
805 | ||
3a7be554 | 806 | static bool trans_FNEG(DisasContext *s, arg_rpr_esz *a) |
afac6d04 RH |
807 | { |
808 | static gen_helper_gvec_3 * const fns[4] = { | |
809 | NULL, | |
810 | gen_helper_sve_fneg_h, | |
811 | gen_helper_sve_fneg_s, | |
812 | gen_helper_sve_fneg_d | |
813 | }; | |
814 | return do_zpz_ool(s, a, fns[a->esz]); | |
815 | } | |
816 | ||
3a7be554 | 817 | static bool trans_SXTB(DisasContext *s, arg_rpr_esz *a) |
afac6d04 RH |
818 | { |
819 | static gen_helper_gvec_3 * const fns[4] = { | |
820 | NULL, | |
821 | gen_helper_sve_sxtb_h, | |
822 | gen_helper_sve_sxtb_s, | |
823 | gen_helper_sve_sxtb_d | |
824 | }; | |
825 | return do_zpz_ool(s, a, fns[a->esz]); | |
826 | } | |
827 | ||
3a7be554 | 828 | static bool trans_UXTB(DisasContext *s, arg_rpr_esz *a) |
afac6d04 RH |
829 | { |
830 | static gen_helper_gvec_3 * const fns[4] = { | |
831 | NULL, | |
832 | gen_helper_sve_uxtb_h, | |
833 | gen_helper_sve_uxtb_s, | |
834 | gen_helper_sve_uxtb_d | |
835 | }; | |
836 | return do_zpz_ool(s, a, fns[a->esz]); | |
837 | } | |
838 | ||
3a7be554 | 839 | static bool trans_SXTH(DisasContext *s, arg_rpr_esz *a) |
afac6d04 RH |
840 | { |
841 | static gen_helper_gvec_3 * const fns[4] = { | |
842 | NULL, NULL, | |
843 | gen_helper_sve_sxth_s, | |
844 | gen_helper_sve_sxth_d | |
845 | }; | |
846 | return do_zpz_ool(s, a, fns[a->esz]); | |
847 | } | |
848 | ||
3a7be554 | 849 | static bool trans_UXTH(DisasContext *s, arg_rpr_esz *a) |
afac6d04 RH |
850 | { |
851 | static gen_helper_gvec_3 * const fns[4] = { | |
852 | NULL, NULL, | |
853 | gen_helper_sve_uxth_s, | |
854 | gen_helper_sve_uxth_d | |
855 | }; | |
856 | return do_zpz_ool(s, a, fns[a->esz]); | |
857 | } | |
858 | ||
3a7be554 | 859 | static bool trans_SXTW(DisasContext *s, arg_rpr_esz *a) |
afac6d04 RH |
860 | { |
861 | return do_zpz_ool(s, a, a->esz == 3 ? gen_helper_sve_sxtw_d : NULL); | |
862 | } | |
863 | ||
3a7be554 | 864 | static bool trans_UXTW(DisasContext *s, arg_rpr_esz *a) |
afac6d04 RH |
865 | { |
866 | return do_zpz_ool(s, a, a->esz == 3 ? gen_helper_sve_uxtw_d : NULL); | |
867 | } | |
868 | ||
869 | #undef DO_ZPZ | |
870 | ||
047cec97 RH |
871 | /* |
872 | *** SVE Integer Reduction Group | |
873 | */ | |
874 | ||
875 | typedef void gen_helper_gvec_reduc(TCGv_i64, TCGv_ptr, TCGv_ptr, TCGv_i32); | |
876 | static bool do_vpz_ool(DisasContext *s, arg_rpr_esz *a, | |
877 | gen_helper_gvec_reduc *fn) | |
878 | { | |
879 | unsigned vsz = vec_full_reg_size(s); | |
880 | TCGv_ptr t_zn, t_pg; | |
881 | TCGv_i32 desc; | |
882 | TCGv_i64 temp; | |
883 | ||
884 | if (fn == NULL) { | |
885 | return false; | |
886 | } | |
887 | if (!sve_access_check(s)) { | |
888 | return true; | |
889 | } | |
890 | ||
891 | desc = tcg_const_i32(simd_desc(vsz, vsz, 0)); | |
892 | temp = tcg_temp_new_i64(); | |
893 | t_zn = tcg_temp_new_ptr(); | |
894 | t_pg = tcg_temp_new_ptr(); | |
895 | ||
896 | tcg_gen_addi_ptr(t_zn, cpu_env, vec_full_reg_offset(s, a->rn)); | |
897 | tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, a->pg)); | |
898 | fn(temp, t_zn, t_pg, desc); | |
899 | tcg_temp_free_ptr(t_zn); | |
900 | tcg_temp_free_ptr(t_pg); | |
901 | tcg_temp_free_i32(desc); | |
902 | ||
903 | write_fp_dreg(s, a->rd, temp); | |
904 | tcg_temp_free_i64(temp); | |
905 | return true; | |
906 | } | |
907 | ||
908 | #define DO_VPZ(NAME, name) \ | |
3a7be554 | 909 | static bool trans_##NAME(DisasContext *s, arg_rpr_esz *a) \ |
047cec97 RH |
910 | { \ |
911 | static gen_helper_gvec_reduc * const fns[4] = { \ | |
912 | gen_helper_sve_##name##_b, gen_helper_sve_##name##_h, \ | |
913 | gen_helper_sve_##name##_s, gen_helper_sve_##name##_d, \ | |
914 | }; \ | |
915 | return do_vpz_ool(s, a, fns[a->esz]); \ | |
916 | } | |
917 | ||
918 | DO_VPZ(ORV, orv) | |
919 | DO_VPZ(ANDV, andv) | |
920 | DO_VPZ(EORV, eorv) | |
921 | ||
922 | DO_VPZ(UADDV, uaddv) | |
923 | DO_VPZ(SMAXV, smaxv) | |
924 | DO_VPZ(UMAXV, umaxv) | |
925 | DO_VPZ(SMINV, sminv) | |
926 | DO_VPZ(UMINV, uminv) | |
927 | ||
3a7be554 | 928 | static bool trans_SADDV(DisasContext *s, arg_rpr_esz *a) |
047cec97 RH |
929 | { |
930 | static gen_helper_gvec_reduc * const fns[4] = { | |
931 | gen_helper_sve_saddv_b, gen_helper_sve_saddv_h, | |
932 | gen_helper_sve_saddv_s, NULL | |
933 | }; | |
934 | return do_vpz_ool(s, a, fns[a->esz]); | |
935 | } | |
936 | ||
937 | #undef DO_VPZ | |
938 | ||
ccd841c3 RH |
939 | /* |
940 | *** SVE Shift by Immediate - Predicated Group | |
941 | */ | |
942 | ||
60245996 RH |
943 | /* |
944 | * Copy Zn into Zd, storing zeros into inactive elements. | |
945 | * If invert, store zeros into the active elements. | |
ccd841c3 | 946 | */ |
60245996 RH |
947 | static bool do_movz_zpz(DisasContext *s, int rd, int rn, int pg, |
948 | int esz, bool invert) | |
ccd841c3 | 949 | { |
60245996 RH |
950 | static gen_helper_gvec_3 * const fns[4] = { |
951 | gen_helper_sve_movz_b, gen_helper_sve_movz_h, | |
952 | gen_helper_sve_movz_s, gen_helper_sve_movz_d, | |
ccd841c3 | 953 | }; |
60245996 | 954 | |
ccd841c3 | 955 | if (sve_access_check(s)) { |
96a461f7 | 956 | gen_gvec_ool_zzp(s, fns[esz], rd, rn, pg, invert); |
ccd841c3 RH |
957 | } |
958 | return true; | |
959 | } | |
960 | ||
961 | static bool do_zpzi_ool(DisasContext *s, arg_rpri_esz *a, | |
962 | gen_helper_gvec_3 *fn) | |
963 | { | |
964 | if (sve_access_check(s)) { | |
96a461f7 | 965 | gen_gvec_ool_zzp(s, fn, a->rd, a->rn, a->pg, a->imm); |
ccd841c3 RH |
966 | } |
967 | return true; | |
968 | } | |
969 | ||
3a7be554 | 970 | static bool trans_ASR_zpzi(DisasContext *s, arg_rpri_esz *a) |
ccd841c3 RH |
971 | { |
972 | static gen_helper_gvec_3 * const fns[4] = { | |
973 | gen_helper_sve_asr_zpzi_b, gen_helper_sve_asr_zpzi_h, | |
974 | gen_helper_sve_asr_zpzi_s, gen_helper_sve_asr_zpzi_d, | |
975 | }; | |
976 | if (a->esz < 0) { | |
977 | /* Invalid tsz encoding -- see tszimm_esz. */ | |
978 | return false; | |
979 | } | |
980 | /* Shift by element size is architecturally valid. For | |
981 | arithmetic right-shift, it's the same as by one less. */ | |
982 | a->imm = MIN(a->imm, (8 << a->esz) - 1); | |
983 | return do_zpzi_ool(s, a, fns[a->esz]); | |
984 | } | |
985 | ||
3a7be554 | 986 | static bool trans_LSR_zpzi(DisasContext *s, arg_rpri_esz *a) |
ccd841c3 RH |
987 | { |
988 | static gen_helper_gvec_3 * const fns[4] = { | |
989 | gen_helper_sve_lsr_zpzi_b, gen_helper_sve_lsr_zpzi_h, | |
990 | gen_helper_sve_lsr_zpzi_s, gen_helper_sve_lsr_zpzi_d, | |
991 | }; | |
992 | if (a->esz < 0) { | |
993 | return false; | |
994 | } | |
995 | /* Shift by element size is architecturally valid. | |
996 | For logical shifts, it is a zeroing operation. */ | |
997 | if (a->imm >= (8 << a->esz)) { | |
60245996 | 998 | return do_movz_zpz(s, a->rd, a->rd, a->pg, a->esz, true); |
ccd841c3 RH |
999 | } else { |
1000 | return do_zpzi_ool(s, a, fns[a->esz]); | |
1001 | } | |
1002 | } | |
1003 | ||
3a7be554 | 1004 | static bool trans_LSL_zpzi(DisasContext *s, arg_rpri_esz *a) |
ccd841c3 RH |
1005 | { |
1006 | static gen_helper_gvec_3 * const fns[4] = { | |
1007 | gen_helper_sve_lsl_zpzi_b, gen_helper_sve_lsl_zpzi_h, | |
1008 | gen_helper_sve_lsl_zpzi_s, gen_helper_sve_lsl_zpzi_d, | |
1009 | }; | |
1010 | if (a->esz < 0) { | |
1011 | return false; | |
1012 | } | |
1013 | /* Shift by element size is architecturally valid. | |
1014 | For logical shifts, it is a zeroing operation. */ | |
1015 | if (a->imm >= (8 << a->esz)) { | |
60245996 | 1016 | return do_movz_zpz(s, a->rd, a->rd, a->pg, a->esz, true); |
ccd841c3 RH |
1017 | } else { |
1018 | return do_zpzi_ool(s, a, fns[a->esz]); | |
1019 | } | |
1020 | } | |
1021 | ||
3a7be554 | 1022 | static bool trans_ASRD(DisasContext *s, arg_rpri_esz *a) |
ccd841c3 RH |
1023 | { |
1024 | static gen_helper_gvec_3 * const fns[4] = { | |
1025 | gen_helper_sve_asrd_b, gen_helper_sve_asrd_h, | |
1026 | gen_helper_sve_asrd_s, gen_helper_sve_asrd_d, | |
1027 | }; | |
1028 | if (a->esz < 0) { | |
1029 | return false; | |
1030 | } | |
1031 | /* Shift by element size is architecturally valid. For arithmetic | |
1032 | right shift for division, it is a zeroing operation. */ | |
1033 | if (a->imm >= (8 << a->esz)) { | |
60245996 | 1034 | return do_movz_zpz(s, a->rd, a->rd, a->pg, a->esz, true); |
ccd841c3 RH |
1035 | } else { |
1036 | return do_zpzi_ool(s, a, fns[a->esz]); | |
1037 | } | |
1038 | } | |
1039 | ||
a5421b54 SL |
1040 | static bool trans_SQSHL_zpzi(DisasContext *s, arg_rpri_esz *a) |
1041 | { | |
1042 | static gen_helper_gvec_3 * const fns[4] = { | |
1043 | gen_helper_sve2_sqshl_zpzi_b, gen_helper_sve2_sqshl_zpzi_h, | |
1044 | gen_helper_sve2_sqshl_zpzi_s, gen_helper_sve2_sqshl_zpzi_d, | |
1045 | }; | |
1046 | if (a->esz < 0 || !dc_isar_feature(aa64_sve2, s)) { | |
1047 | return false; | |
1048 | } | |
1049 | return do_zpzi_ool(s, a, fns[a->esz]); | |
1050 | } | |
1051 | ||
1052 | static bool trans_UQSHL_zpzi(DisasContext *s, arg_rpri_esz *a) | |
1053 | { | |
1054 | static gen_helper_gvec_3 * const fns[4] = { | |
1055 | gen_helper_sve2_uqshl_zpzi_b, gen_helper_sve2_uqshl_zpzi_h, | |
1056 | gen_helper_sve2_uqshl_zpzi_s, gen_helper_sve2_uqshl_zpzi_d, | |
1057 | }; | |
1058 | if (a->esz < 0 || !dc_isar_feature(aa64_sve2, s)) { | |
1059 | return false; | |
1060 | } | |
1061 | return do_zpzi_ool(s, a, fns[a->esz]); | |
1062 | } | |
1063 | ||
1064 | static bool trans_SRSHR(DisasContext *s, arg_rpri_esz *a) | |
1065 | { | |
1066 | static gen_helper_gvec_3 * const fns[4] = { | |
1067 | gen_helper_sve2_srshr_b, gen_helper_sve2_srshr_h, | |
1068 | gen_helper_sve2_srshr_s, gen_helper_sve2_srshr_d, | |
1069 | }; | |
1070 | if (a->esz < 0 || !dc_isar_feature(aa64_sve2, s)) { | |
1071 | return false; | |
1072 | } | |
1073 | return do_zpzi_ool(s, a, fns[a->esz]); | |
1074 | } | |
1075 | ||
1076 | static bool trans_URSHR(DisasContext *s, arg_rpri_esz *a) | |
1077 | { | |
1078 | static gen_helper_gvec_3 * const fns[4] = { | |
1079 | gen_helper_sve2_urshr_b, gen_helper_sve2_urshr_h, | |
1080 | gen_helper_sve2_urshr_s, gen_helper_sve2_urshr_d, | |
1081 | }; | |
1082 | if (a->esz < 0 || !dc_isar_feature(aa64_sve2, s)) { | |
1083 | return false; | |
1084 | } | |
1085 | return do_zpzi_ool(s, a, fns[a->esz]); | |
1086 | } | |
1087 | ||
1088 | static bool trans_SQSHLU(DisasContext *s, arg_rpri_esz *a) | |
1089 | { | |
1090 | static gen_helper_gvec_3 * const fns[4] = { | |
1091 | gen_helper_sve2_sqshlu_b, gen_helper_sve2_sqshlu_h, | |
1092 | gen_helper_sve2_sqshlu_s, gen_helper_sve2_sqshlu_d, | |
1093 | }; | |
1094 | if (a->esz < 0 || !dc_isar_feature(aa64_sve2, s)) { | |
1095 | return false; | |
1096 | } | |
1097 | return do_zpzi_ool(s, a, fns[a->esz]); | |
1098 | } | |
1099 | ||
fe7f8dfb RH |
1100 | /* |
1101 | *** SVE Bitwise Shift - Predicated Group | |
1102 | */ | |
1103 | ||
1104 | #define DO_ZPZW(NAME, name) \ | |
3a7be554 | 1105 | static bool trans_##NAME##_zpzw(DisasContext *s, arg_rprr_esz *a) \ |
fe7f8dfb RH |
1106 | { \ |
1107 | static gen_helper_gvec_4 * const fns[3] = { \ | |
1108 | gen_helper_sve_##name##_zpzw_b, gen_helper_sve_##name##_zpzw_h, \ | |
1109 | gen_helper_sve_##name##_zpzw_s, \ | |
1110 | }; \ | |
1111 | if (a->esz < 0 || a->esz >= 3) { \ | |
1112 | return false; \ | |
1113 | } \ | |
1114 | return do_zpzz_ool(s, a, fns[a->esz]); \ | |
1115 | } | |
1116 | ||
1117 | DO_ZPZW(ASR, asr) | |
1118 | DO_ZPZW(LSR, lsr) | |
1119 | DO_ZPZW(LSL, lsl) | |
1120 | ||
1121 | #undef DO_ZPZW | |
1122 | ||
d9d78dcc RH |
1123 | /* |
1124 | *** SVE Bitwise Shift - Unpredicated Group | |
1125 | */ | |
1126 | ||
1127 | static bool do_shift_imm(DisasContext *s, arg_rri_esz *a, bool asr, | |
1128 | void (*gvec_fn)(unsigned, uint32_t, uint32_t, | |
1129 | int64_t, uint32_t, uint32_t)) | |
1130 | { | |
1131 | if (a->esz < 0) { | |
1132 | /* Invalid tsz encoding -- see tszimm_esz. */ | |
1133 | return false; | |
1134 | } | |
1135 | if (sve_access_check(s)) { | |
1136 | unsigned vsz = vec_full_reg_size(s); | |
1137 | /* Shift by element size is architecturally valid. For | |
1138 | arithmetic right-shift, it's the same as by one less. | |
1139 | Otherwise it is a zeroing operation. */ | |
1140 | if (a->imm >= 8 << a->esz) { | |
1141 | if (asr) { | |
1142 | a->imm = (8 << a->esz) - 1; | |
1143 | } else { | |
1144 | do_dupi_z(s, a->rd, 0); | |
1145 | return true; | |
1146 | } | |
1147 | } | |
1148 | gvec_fn(a->esz, vec_full_reg_offset(s, a->rd), | |
1149 | vec_full_reg_offset(s, a->rn), a->imm, vsz, vsz); | |
1150 | } | |
1151 | return true; | |
1152 | } | |
1153 | ||
3a7be554 | 1154 | static bool trans_ASR_zzi(DisasContext *s, arg_rri_esz *a) |
d9d78dcc RH |
1155 | { |
1156 | return do_shift_imm(s, a, true, tcg_gen_gvec_sari); | |
1157 | } | |
1158 | ||
3a7be554 | 1159 | static bool trans_LSR_zzi(DisasContext *s, arg_rri_esz *a) |
d9d78dcc RH |
1160 | { |
1161 | return do_shift_imm(s, a, false, tcg_gen_gvec_shri); | |
1162 | } | |
1163 | ||
3a7be554 | 1164 | static bool trans_LSL_zzi(DisasContext *s, arg_rri_esz *a) |
d9d78dcc RH |
1165 | { |
1166 | return do_shift_imm(s, a, false, tcg_gen_gvec_shli); | |
1167 | } | |
1168 | ||
1169 | static bool do_zzw_ool(DisasContext *s, arg_rrr_esz *a, gen_helper_gvec_3 *fn) | |
1170 | { | |
1171 | if (fn == NULL) { | |
1172 | return false; | |
1173 | } | |
1174 | if (sve_access_check(s)) { | |
e645d1a1 | 1175 | gen_gvec_ool_zzz(s, fn, a->rd, a->rn, a->rm, 0); |
d9d78dcc RH |
1176 | } |
1177 | return true; | |
1178 | } | |
1179 | ||
1180 | #define DO_ZZW(NAME, name) \ | |
3a7be554 | 1181 | static bool trans_##NAME##_zzw(DisasContext *s, arg_rrr_esz *a) \ |
d9d78dcc RH |
1182 | { \ |
1183 | static gen_helper_gvec_3 * const fns[4] = { \ | |
1184 | gen_helper_sve_##name##_zzw_b, gen_helper_sve_##name##_zzw_h, \ | |
1185 | gen_helper_sve_##name##_zzw_s, NULL \ | |
1186 | }; \ | |
1187 | return do_zzw_ool(s, a, fns[a->esz]); \ | |
1188 | } | |
1189 | ||
1190 | DO_ZZW(ASR, asr) | |
1191 | DO_ZZW(LSR, lsr) | |
1192 | DO_ZZW(LSL, lsl) | |
1193 | ||
1194 | #undef DO_ZZW | |
1195 | ||
96a36e4a RH |
1196 | /* |
1197 | *** SVE Integer Multiply-Add Group | |
1198 | */ | |
1199 | ||
1200 | static bool do_zpzzz_ool(DisasContext *s, arg_rprrr_esz *a, | |
1201 | gen_helper_gvec_5 *fn) | |
1202 | { | |
1203 | if (sve_access_check(s)) { | |
1204 | unsigned vsz = vec_full_reg_size(s); | |
1205 | tcg_gen_gvec_5_ool(vec_full_reg_offset(s, a->rd), | |
1206 | vec_full_reg_offset(s, a->ra), | |
1207 | vec_full_reg_offset(s, a->rn), | |
1208 | vec_full_reg_offset(s, a->rm), | |
1209 | pred_full_reg_offset(s, a->pg), | |
1210 | vsz, vsz, 0, fn); | |
1211 | } | |
1212 | return true; | |
1213 | } | |
1214 | ||
1215 | #define DO_ZPZZZ(NAME, name) \ | |
3a7be554 | 1216 | static bool trans_##NAME(DisasContext *s, arg_rprrr_esz *a) \ |
96a36e4a RH |
1217 | { \ |
1218 | static gen_helper_gvec_5 * const fns[4] = { \ | |
1219 | gen_helper_sve_##name##_b, gen_helper_sve_##name##_h, \ | |
1220 | gen_helper_sve_##name##_s, gen_helper_sve_##name##_d, \ | |
1221 | }; \ | |
1222 | return do_zpzzz_ool(s, a, fns[a->esz]); \ | |
1223 | } | |
1224 | ||
1225 | DO_ZPZZZ(MLA, mla) | |
1226 | DO_ZPZZZ(MLS, mls) | |
1227 | ||
1228 | #undef DO_ZPZZZ | |
1229 | ||
9a56c9c3 RH |
1230 | /* |
1231 | *** SVE Index Generation Group | |
1232 | */ | |
1233 | ||
1234 | static void do_index(DisasContext *s, int esz, int rd, | |
1235 | TCGv_i64 start, TCGv_i64 incr) | |
1236 | { | |
1237 | unsigned vsz = vec_full_reg_size(s); | |
1238 | TCGv_i32 desc = tcg_const_i32(simd_desc(vsz, vsz, 0)); | |
1239 | TCGv_ptr t_zd = tcg_temp_new_ptr(); | |
1240 | ||
1241 | tcg_gen_addi_ptr(t_zd, cpu_env, vec_full_reg_offset(s, rd)); | |
1242 | if (esz == 3) { | |
1243 | gen_helper_sve_index_d(t_zd, start, incr, desc); | |
1244 | } else { | |
1245 | typedef void index_fn(TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32); | |
1246 | static index_fn * const fns[3] = { | |
1247 | gen_helper_sve_index_b, | |
1248 | gen_helper_sve_index_h, | |
1249 | gen_helper_sve_index_s, | |
1250 | }; | |
1251 | TCGv_i32 s32 = tcg_temp_new_i32(); | |
1252 | TCGv_i32 i32 = tcg_temp_new_i32(); | |
1253 | ||
1254 | tcg_gen_extrl_i64_i32(s32, start); | |
1255 | tcg_gen_extrl_i64_i32(i32, incr); | |
1256 | fns[esz](t_zd, s32, i32, desc); | |
1257 | ||
1258 | tcg_temp_free_i32(s32); | |
1259 | tcg_temp_free_i32(i32); | |
1260 | } | |
1261 | tcg_temp_free_ptr(t_zd); | |
1262 | tcg_temp_free_i32(desc); | |
1263 | } | |
1264 | ||
3a7be554 | 1265 | static bool trans_INDEX_ii(DisasContext *s, arg_INDEX_ii *a) |
9a56c9c3 RH |
1266 | { |
1267 | if (sve_access_check(s)) { | |
b0c3aece RH |
1268 | TCGv_i64 start = tcg_constant_i64(a->imm1); |
1269 | TCGv_i64 incr = tcg_constant_i64(a->imm2); | |
9a56c9c3 | 1270 | do_index(s, a->esz, a->rd, start, incr); |
9a56c9c3 RH |
1271 | } |
1272 | return true; | |
1273 | } | |
1274 | ||
3a7be554 | 1275 | static bool trans_INDEX_ir(DisasContext *s, arg_INDEX_ir *a) |
9a56c9c3 RH |
1276 | { |
1277 | if (sve_access_check(s)) { | |
b0c3aece | 1278 | TCGv_i64 start = tcg_constant_i64(a->imm); |
9a56c9c3 RH |
1279 | TCGv_i64 incr = cpu_reg(s, a->rm); |
1280 | do_index(s, a->esz, a->rd, start, incr); | |
9a56c9c3 RH |
1281 | } |
1282 | return true; | |
1283 | } | |
1284 | ||
3a7be554 | 1285 | static bool trans_INDEX_ri(DisasContext *s, arg_INDEX_ri *a) |
9a56c9c3 RH |
1286 | { |
1287 | if (sve_access_check(s)) { | |
1288 | TCGv_i64 start = cpu_reg(s, a->rn); | |
b0c3aece | 1289 | TCGv_i64 incr = tcg_constant_i64(a->imm); |
9a56c9c3 | 1290 | do_index(s, a->esz, a->rd, start, incr); |
9a56c9c3 RH |
1291 | } |
1292 | return true; | |
1293 | } | |
1294 | ||
3a7be554 | 1295 | static bool trans_INDEX_rr(DisasContext *s, arg_INDEX_rr *a) |
9a56c9c3 RH |
1296 | { |
1297 | if (sve_access_check(s)) { | |
1298 | TCGv_i64 start = cpu_reg(s, a->rn); | |
1299 | TCGv_i64 incr = cpu_reg(s, a->rm); | |
1300 | do_index(s, a->esz, a->rd, start, incr); | |
1301 | } | |
1302 | return true; | |
1303 | } | |
1304 | ||
96f922cc RH |
1305 | /* |
1306 | *** SVE Stack Allocation Group | |
1307 | */ | |
1308 | ||
3a7be554 | 1309 | static bool trans_ADDVL(DisasContext *s, arg_ADDVL *a) |
96f922cc | 1310 | { |
5de56742 AC |
1311 | if (sve_access_check(s)) { |
1312 | TCGv_i64 rd = cpu_reg_sp(s, a->rd); | |
1313 | TCGv_i64 rn = cpu_reg_sp(s, a->rn); | |
1314 | tcg_gen_addi_i64(rd, rn, a->imm * vec_full_reg_size(s)); | |
1315 | } | |
96f922cc RH |
1316 | return true; |
1317 | } | |
1318 | ||
3a7be554 | 1319 | static bool trans_ADDPL(DisasContext *s, arg_ADDPL *a) |
96f922cc | 1320 | { |
5de56742 AC |
1321 | if (sve_access_check(s)) { |
1322 | TCGv_i64 rd = cpu_reg_sp(s, a->rd); | |
1323 | TCGv_i64 rn = cpu_reg_sp(s, a->rn); | |
1324 | tcg_gen_addi_i64(rd, rn, a->imm * pred_full_reg_size(s)); | |
1325 | } | |
96f922cc RH |
1326 | return true; |
1327 | } | |
1328 | ||
3a7be554 | 1329 | static bool trans_RDVL(DisasContext *s, arg_RDVL *a) |
96f922cc | 1330 | { |
5de56742 AC |
1331 | if (sve_access_check(s)) { |
1332 | TCGv_i64 reg = cpu_reg(s, a->rd); | |
1333 | tcg_gen_movi_i64(reg, a->imm * vec_full_reg_size(s)); | |
1334 | } | |
96f922cc RH |
1335 | return true; |
1336 | } | |
1337 | ||
4b242d9c RH |
1338 | /* |
1339 | *** SVE Compute Vector Address Group | |
1340 | */ | |
1341 | ||
1342 | static bool do_adr(DisasContext *s, arg_rrri *a, gen_helper_gvec_3 *fn) | |
1343 | { | |
1344 | if (sve_access_check(s)) { | |
e645d1a1 | 1345 | gen_gvec_ool_zzz(s, fn, a->rd, a->rn, a->rm, a->imm); |
4b242d9c RH |
1346 | } |
1347 | return true; | |
1348 | } | |
1349 | ||
3a7be554 | 1350 | static bool trans_ADR_p32(DisasContext *s, arg_rrri *a) |
4b242d9c RH |
1351 | { |
1352 | return do_adr(s, a, gen_helper_sve_adr_p32); | |
1353 | } | |
1354 | ||
3a7be554 | 1355 | static bool trans_ADR_p64(DisasContext *s, arg_rrri *a) |
4b242d9c RH |
1356 | { |
1357 | return do_adr(s, a, gen_helper_sve_adr_p64); | |
1358 | } | |
1359 | ||
3a7be554 | 1360 | static bool trans_ADR_s32(DisasContext *s, arg_rrri *a) |
4b242d9c RH |
1361 | { |
1362 | return do_adr(s, a, gen_helper_sve_adr_s32); | |
1363 | } | |
1364 | ||
3a7be554 | 1365 | static bool trans_ADR_u32(DisasContext *s, arg_rrri *a) |
4b242d9c RH |
1366 | { |
1367 | return do_adr(s, a, gen_helper_sve_adr_u32); | |
1368 | } | |
1369 | ||
0762cd42 RH |
1370 | /* |
1371 | *** SVE Integer Misc - Unpredicated Group | |
1372 | */ | |
1373 | ||
3a7be554 | 1374 | static bool trans_FEXPA(DisasContext *s, arg_rr_esz *a) |
0762cd42 RH |
1375 | { |
1376 | static gen_helper_gvec_2 * const fns[4] = { | |
1377 | NULL, | |
1378 | gen_helper_sve_fexpa_h, | |
1379 | gen_helper_sve_fexpa_s, | |
1380 | gen_helper_sve_fexpa_d, | |
1381 | }; | |
1382 | if (a->esz == 0) { | |
1383 | return false; | |
1384 | } | |
1385 | if (sve_access_check(s)) { | |
40e32e5a | 1386 | gen_gvec_ool_zz(s, fns[a->esz], a->rd, a->rn, 0); |
0762cd42 RH |
1387 | } |
1388 | return true; | |
1389 | } | |
1390 | ||
3a7be554 | 1391 | static bool trans_FTSSEL(DisasContext *s, arg_rrr_esz *a) |
a1f233f2 RH |
1392 | { |
1393 | static gen_helper_gvec_3 * const fns[4] = { | |
1394 | NULL, | |
1395 | gen_helper_sve_ftssel_h, | |
1396 | gen_helper_sve_ftssel_s, | |
1397 | gen_helper_sve_ftssel_d, | |
1398 | }; | |
1399 | if (a->esz == 0) { | |
1400 | return false; | |
1401 | } | |
1402 | if (sve_access_check(s)) { | |
e645d1a1 | 1403 | gen_gvec_ool_zzz(s, fns[a->esz], a->rd, a->rn, a->rm, 0); |
a1f233f2 RH |
1404 | } |
1405 | return true; | |
1406 | } | |
1407 | ||
516e246a RH |
1408 | /* |
1409 | *** SVE Predicate Logical Operations Group | |
1410 | */ | |
1411 | ||
1412 | static bool do_pppp_flags(DisasContext *s, arg_rprr_s *a, | |
1413 | const GVecGen4 *gvec_op) | |
1414 | { | |
1415 | if (!sve_access_check(s)) { | |
1416 | return true; | |
1417 | } | |
1418 | ||
1419 | unsigned psz = pred_gvec_reg_size(s); | |
1420 | int dofs = pred_full_reg_offset(s, a->rd); | |
1421 | int nofs = pred_full_reg_offset(s, a->rn); | |
1422 | int mofs = pred_full_reg_offset(s, a->rm); | |
1423 | int gofs = pred_full_reg_offset(s, a->pg); | |
1424 | ||
dd81a8d7 RH |
1425 | if (!a->s) { |
1426 | tcg_gen_gvec_4(dofs, nofs, mofs, gofs, psz, psz, gvec_op); | |
1427 | return true; | |
1428 | } | |
1429 | ||
516e246a RH |
1430 | if (psz == 8) { |
1431 | /* Do the operation and the flags generation in temps. */ | |
1432 | TCGv_i64 pd = tcg_temp_new_i64(); | |
1433 | TCGv_i64 pn = tcg_temp_new_i64(); | |
1434 | TCGv_i64 pm = tcg_temp_new_i64(); | |
1435 | TCGv_i64 pg = tcg_temp_new_i64(); | |
1436 | ||
1437 | tcg_gen_ld_i64(pn, cpu_env, nofs); | |
1438 | tcg_gen_ld_i64(pm, cpu_env, mofs); | |
1439 | tcg_gen_ld_i64(pg, cpu_env, gofs); | |
1440 | ||
1441 | gvec_op->fni8(pd, pn, pm, pg); | |
1442 | tcg_gen_st_i64(pd, cpu_env, dofs); | |
1443 | ||
1444 | do_predtest1(pd, pg); | |
1445 | ||
1446 | tcg_temp_free_i64(pd); | |
1447 | tcg_temp_free_i64(pn); | |
1448 | tcg_temp_free_i64(pm); | |
1449 | tcg_temp_free_i64(pg); | |
1450 | } else { | |
1451 | /* The operation and flags generation is large. The computation | |
1452 | * of the flags depends on the original contents of the guarding | |
1453 | * predicate. If the destination overwrites the guarding predicate, | |
1454 | * then the easiest way to get this right is to save a copy. | |
1455 | */ | |
1456 | int tofs = gofs; | |
1457 | if (a->rd == a->pg) { | |
1458 | tofs = offsetof(CPUARMState, vfp.preg_tmp); | |
1459 | tcg_gen_gvec_mov(0, tofs, gofs, psz, psz); | |
1460 | } | |
1461 | ||
1462 | tcg_gen_gvec_4(dofs, nofs, mofs, gofs, psz, psz, gvec_op); | |
1463 | do_predtest(s, dofs, tofs, psz / 8); | |
1464 | } | |
1465 | return true; | |
1466 | } | |
1467 | ||
1468 | static void gen_and_pg_i64(TCGv_i64 pd, TCGv_i64 pn, TCGv_i64 pm, TCGv_i64 pg) | |
1469 | { | |
1470 | tcg_gen_and_i64(pd, pn, pm); | |
1471 | tcg_gen_and_i64(pd, pd, pg); | |
1472 | } | |
1473 | ||
1474 | static void gen_and_pg_vec(unsigned vece, TCGv_vec pd, TCGv_vec pn, | |
1475 | TCGv_vec pm, TCGv_vec pg) | |
1476 | { | |
1477 | tcg_gen_and_vec(vece, pd, pn, pm); | |
1478 | tcg_gen_and_vec(vece, pd, pd, pg); | |
1479 | } | |
1480 | ||
3a7be554 | 1481 | static bool trans_AND_pppp(DisasContext *s, arg_rprr_s *a) |
516e246a RH |
1482 | { |
1483 | static const GVecGen4 op = { | |
1484 | .fni8 = gen_and_pg_i64, | |
1485 | .fniv = gen_and_pg_vec, | |
1486 | .fno = gen_helper_sve_and_pppp, | |
1487 | .prefer_i64 = TCG_TARGET_REG_BITS == 64, | |
1488 | }; | |
dd81a8d7 RH |
1489 | |
1490 | if (!a->s) { | |
1491 | if (!sve_access_check(s)) { | |
1492 | return true; | |
1493 | } | |
1494 | if (a->rn == a->rm) { | |
1495 | if (a->pg == a->rn) { | |
1496 | do_mov_p(s, a->rd, a->rn); | |
1497 | } else { | |
1498 | gen_gvec_fn_ppp(s, tcg_gen_gvec_and, a->rd, a->rn, a->pg); | |
1499 | } | |
1500 | return true; | |
1501 | } else if (a->pg == a->rn || a->pg == a->rm) { | |
1502 | gen_gvec_fn_ppp(s, tcg_gen_gvec_and, a->rd, a->rn, a->rm); | |
1503 | return true; | |
516e246a | 1504 | } |
516e246a | 1505 | } |
dd81a8d7 | 1506 | return do_pppp_flags(s, a, &op); |
516e246a RH |
1507 | } |
1508 | ||
1509 | static void gen_bic_pg_i64(TCGv_i64 pd, TCGv_i64 pn, TCGv_i64 pm, TCGv_i64 pg) | |
1510 | { | |
1511 | tcg_gen_andc_i64(pd, pn, pm); | |
1512 | tcg_gen_and_i64(pd, pd, pg); | |
1513 | } | |
1514 | ||
1515 | static void gen_bic_pg_vec(unsigned vece, TCGv_vec pd, TCGv_vec pn, | |
1516 | TCGv_vec pm, TCGv_vec pg) | |
1517 | { | |
1518 | tcg_gen_andc_vec(vece, pd, pn, pm); | |
1519 | tcg_gen_and_vec(vece, pd, pd, pg); | |
1520 | } | |
1521 | ||
3a7be554 | 1522 | static bool trans_BIC_pppp(DisasContext *s, arg_rprr_s *a) |
516e246a RH |
1523 | { |
1524 | static const GVecGen4 op = { | |
1525 | .fni8 = gen_bic_pg_i64, | |
1526 | .fniv = gen_bic_pg_vec, | |
1527 | .fno = gen_helper_sve_bic_pppp, | |
1528 | .prefer_i64 = TCG_TARGET_REG_BITS == 64, | |
1529 | }; | |
dd81a8d7 RH |
1530 | |
1531 | if (!a->s && a->pg == a->rn) { | |
1532 | if (sve_access_check(s)) { | |
1533 | gen_gvec_fn_ppp(s, tcg_gen_gvec_andc, a->rd, a->rn, a->rm); | |
1534 | } | |
1535 | return true; | |
516e246a | 1536 | } |
dd81a8d7 | 1537 | return do_pppp_flags(s, a, &op); |
516e246a RH |
1538 | } |
1539 | ||
1540 | static void gen_eor_pg_i64(TCGv_i64 pd, TCGv_i64 pn, TCGv_i64 pm, TCGv_i64 pg) | |
1541 | { | |
1542 | tcg_gen_xor_i64(pd, pn, pm); | |
1543 | tcg_gen_and_i64(pd, pd, pg); | |
1544 | } | |
1545 | ||
1546 | static void gen_eor_pg_vec(unsigned vece, TCGv_vec pd, TCGv_vec pn, | |
1547 | TCGv_vec pm, TCGv_vec pg) | |
1548 | { | |
1549 | tcg_gen_xor_vec(vece, pd, pn, pm); | |
1550 | tcg_gen_and_vec(vece, pd, pd, pg); | |
1551 | } | |
1552 | ||
3a7be554 | 1553 | static bool trans_EOR_pppp(DisasContext *s, arg_rprr_s *a) |
516e246a RH |
1554 | { |
1555 | static const GVecGen4 op = { | |
1556 | .fni8 = gen_eor_pg_i64, | |
1557 | .fniv = gen_eor_pg_vec, | |
1558 | .fno = gen_helper_sve_eor_pppp, | |
1559 | .prefer_i64 = TCG_TARGET_REG_BITS == 64, | |
1560 | }; | |
dd81a8d7 | 1561 | return do_pppp_flags(s, a, &op); |
516e246a RH |
1562 | } |
1563 | ||
3a7be554 | 1564 | static bool trans_SEL_pppp(DisasContext *s, arg_rprr_s *a) |
516e246a | 1565 | { |
516e246a RH |
1566 | if (a->s) { |
1567 | return false; | |
516e246a | 1568 | } |
d4bc6232 RH |
1569 | if (sve_access_check(s)) { |
1570 | unsigned psz = pred_gvec_reg_size(s); | |
1571 | tcg_gen_gvec_bitsel(MO_8, pred_full_reg_offset(s, a->rd), | |
1572 | pred_full_reg_offset(s, a->pg), | |
1573 | pred_full_reg_offset(s, a->rn), | |
1574 | pred_full_reg_offset(s, a->rm), psz, psz); | |
1575 | } | |
1576 | return true; | |
516e246a RH |
1577 | } |
1578 | ||
1579 | static void gen_orr_pg_i64(TCGv_i64 pd, TCGv_i64 pn, TCGv_i64 pm, TCGv_i64 pg) | |
1580 | { | |
1581 | tcg_gen_or_i64(pd, pn, pm); | |
1582 | tcg_gen_and_i64(pd, pd, pg); | |
1583 | } | |
1584 | ||
1585 | static void gen_orr_pg_vec(unsigned vece, TCGv_vec pd, TCGv_vec pn, | |
1586 | TCGv_vec pm, TCGv_vec pg) | |
1587 | { | |
1588 | tcg_gen_or_vec(vece, pd, pn, pm); | |
1589 | tcg_gen_and_vec(vece, pd, pd, pg); | |
1590 | } | |
1591 | ||
3a7be554 | 1592 | static bool trans_ORR_pppp(DisasContext *s, arg_rprr_s *a) |
516e246a RH |
1593 | { |
1594 | static const GVecGen4 op = { | |
1595 | .fni8 = gen_orr_pg_i64, | |
1596 | .fniv = gen_orr_pg_vec, | |
1597 | .fno = gen_helper_sve_orr_pppp, | |
1598 | .prefer_i64 = TCG_TARGET_REG_BITS == 64, | |
1599 | }; | |
dd81a8d7 RH |
1600 | |
1601 | if (!a->s && a->pg == a->rn && a->rn == a->rm) { | |
516e246a | 1602 | return do_mov_p(s, a->rd, a->rn); |
516e246a | 1603 | } |
dd81a8d7 | 1604 | return do_pppp_flags(s, a, &op); |
516e246a RH |
1605 | } |
1606 | ||
1607 | static void gen_orn_pg_i64(TCGv_i64 pd, TCGv_i64 pn, TCGv_i64 pm, TCGv_i64 pg) | |
1608 | { | |
1609 | tcg_gen_orc_i64(pd, pn, pm); | |
1610 | tcg_gen_and_i64(pd, pd, pg); | |
1611 | } | |
1612 | ||
1613 | static void gen_orn_pg_vec(unsigned vece, TCGv_vec pd, TCGv_vec pn, | |
1614 | TCGv_vec pm, TCGv_vec pg) | |
1615 | { | |
1616 | tcg_gen_orc_vec(vece, pd, pn, pm); | |
1617 | tcg_gen_and_vec(vece, pd, pd, pg); | |
1618 | } | |
1619 | ||
3a7be554 | 1620 | static bool trans_ORN_pppp(DisasContext *s, arg_rprr_s *a) |
516e246a RH |
1621 | { |
1622 | static const GVecGen4 op = { | |
1623 | .fni8 = gen_orn_pg_i64, | |
1624 | .fniv = gen_orn_pg_vec, | |
1625 | .fno = gen_helper_sve_orn_pppp, | |
1626 | .prefer_i64 = TCG_TARGET_REG_BITS == 64, | |
1627 | }; | |
dd81a8d7 | 1628 | return do_pppp_flags(s, a, &op); |
516e246a RH |
1629 | } |
1630 | ||
1631 | static void gen_nor_pg_i64(TCGv_i64 pd, TCGv_i64 pn, TCGv_i64 pm, TCGv_i64 pg) | |
1632 | { | |
1633 | tcg_gen_or_i64(pd, pn, pm); | |
1634 | tcg_gen_andc_i64(pd, pg, pd); | |
1635 | } | |
1636 | ||
1637 | static void gen_nor_pg_vec(unsigned vece, TCGv_vec pd, TCGv_vec pn, | |
1638 | TCGv_vec pm, TCGv_vec pg) | |
1639 | { | |
1640 | tcg_gen_or_vec(vece, pd, pn, pm); | |
1641 | tcg_gen_andc_vec(vece, pd, pg, pd); | |
1642 | } | |
1643 | ||
3a7be554 | 1644 | static bool trans_NOR_pppp(DisasContext *s, arg_rprr_s *a) |
516e246a RH |
1645 | { |
1646 | static const GVecGen4 op = { | |
1647 | .fni8 = gen_nor_pg_i64, | |
1648 | .fniv = gen_nor_pg_vec, | |
1649 | .fno = gen_helper_sve_nor_pppp, | |
1650 | .prefer_i64 = TCG_TARGET_REG_BITS == 64, | |
1651 | }; | |
dd81a8d7 | 1652 | return do_pppp_flags(s, a, &op); |
516e246a RH |
1653 | } |
1654 | ||
1655 | static void gen_nand_pg_i64(TCGv_i64 pd, TCGv_i64 pn, TCGv_i64 pm, TCGv_i64 pg) | |
1656 | { | |
1657 | tcg_gen_and_i64(pd, pn, pm); | |
1658 | tcg_gen_andc_i64(pd, pg, pd); | |
1659 | } | |
1660 | ||
1661 | static void gen_nand_pg_vec(unsigned vece, TCGv_vec pd, TCGv_vec pn, | |
1662 | TCGv_vec pm, TCGv_vec pg) | |
1663 | { | |
1664 | tcg_gen_and_vec(vece, pd, pn, pm); | |
1665 | tcg_gen_andc_vec(vece, pd, pg, pd); | |
1666 | } | |
1667 | ||
3a7be554 | 1668 | static bool trans_NAND_pppp(DisasContext *s, arg_rprr_s *a) |
516e246a RH |
1669 | { |
1670 | static const GVecGen4 op = { | |
1671 | .fni8 = gen_nand_pg_i64, | |
1672 | .fniv = gen_nand_pg_vec, | |
1673 | .fno = gen_helper_sve_nand_pppp, | |
1674 | .prefer_i64 = TCG_TARGET_REG_BITS == 64, | |
1675 | }; | |
dd81a8d7 | 1676 | return do_pppp_flags(s, a, &op); |
516e246a RH |
1677 | } |
1678 | ||
9e18d7a6 RH |
1679 | /* |
1680 | *** SVE Predicate Misc Group | |
1681 | */ | |
1682 | ||
3a7be554 | 1683 | static bool trans_PTEST(DisasContext *s, arg_PTEST *a) |
9e18d7a6 RH |
1684 | { |
1685 | if (sve_access_check(s)) { | |
1686 | int nofs = pred_full_reg_offset(s, a->rn); | |
1687 | int gofs = pred_full_reg_offset(s, a->pg); | |
1688 | int words = DIV_ROUND_UP(pred_full_reg_size(s), 8); | |
1689 | ||
1690 | if (words == 1) { | |
1691 | TCGv_i64 pn = tcg_temp_new_i64(); | |
1692 | TCGv_i64 pg = tcg_temp_new_i64(); | |
1693 | ||
1694 | tcg_gen_ld_i64(pn, cpu_env, nofs); | |
1695 | tcg_gen_ld_i64(pg, cpu_env, gofs); | |
1696 | do_predtest1(pn, pg); | |
1697 | ||
1698 | tcg_temp_free_i64(pn); | |
1699 | tcg_temp_free_i64(pg); | |
1700 | } else { | |
1701 | do_predtest(s, nofs, gofs, words); | |
1702 | } | |
1703 | } | |
1704 | return true; | |
1705 | } | |
1706 | ||
028e2a7b RH |
1707 | /* See the ARM pseudocode DecodePredCount. */ |
1708 | static unsigned decode_pred_count(unsigned fullsz, int pattern, int esz) | |
1709 | { | |
1710 | unsigned elements = fullsz >> esz; | |
1711 | unsigned bound; | |
1712 | ||
1713 | switch (pattern) { | |
1714 | case 0x0: /* POW2 */ | |
1715 | return pow2floor(elements); | |
1716 | case 0x1: /* VL1 */ | |
1717 | case 0x2: /* VL2 */ | |
1718 | case 0x3: /* VL3 */ | |
1719 | case 0x4: /* VL4 */ | |
1720 | case 0x5: /* VL5 */ | |
1721 | case 0x6: /* VL6 */ | |
1722 | case 0x7: /* VL7 */ | |
1723 | case 0x8: /* VL8 */ | |
1724 | bound = pattern; | |
1725 | break; | |
1726 | case 0x9: /* VL16 */ | |
1727 | case 0xa: /* VL32 */ | |
1728 | case 0xb: /* VL64 */ | |
1729 | case 0xc: /* VL128 */ | |
1730 | case 0xd: /* VL256 */ | |
1731 | bound = 16 << (pattern - 9); | |
1732 | break; | |
1733 | case 0x1d: /* MUL4 */ | |
1734 | return elements - elements % 4; | |
1735 | case 0x1e: /* MUL3 */ | |
1736 | return elements - elements % 3; | |
1737 | case 0x1f: /* ALL */ | |
1738 | return elements; | |
1739 | default: /* #uimm5 */ | |
1740 | return 0; | |
1741 | } | |
1742 | return elements >= bound ? bound : 0; | |
1743 | } | |
1744 | ||
1745 | /* This handles all of the predicate initialization instructions, | |
1746 | * PTRUE, PFALSE, SETFFR. For PFALSE, we will have set PAT == 32 | |
1747 | * so that decode_pred_count returns 0. For SETFFR, we will have | |
1748 | * set RD == 16 == FFR. | |
1749 | */ | |
1750 | static bool do_predset(DisasContext *s, int esz, int rd, int pat, bool setflag) | |
1751 | { | |
1752 | if (!sve_access_check(s)) { | |
1753 | return true; | |
1754 | } | |
1755 | ||
1756 | unsigned fullsz = vec_full_reg_size(s); | |
1757 | unsigned ofs = pred_full_reg_offset(s, rd); | |
1758 | unsigned numelem, setsz, i; | |
1759 | uint64_t word, lastword; | |
1760 | TCGv_i64 t; | |
1761 | ||
1762 | numelem = decode_pred_count(fullsz, pat, esz); | |
1763 | ||
1764 | /* Determine what we must store into each bit, and how many. */ | |
1765 | if (numelem == 0) { | |
1766 | lastword = word = 0; | |
1767 | setsz = fullsz; | |
1768 | } else { | |
1769 | setsz = numelem << esz; | |
1770 | lastword = word = pred_esz_masks[esz]; | |
1771 | if (setsz % 64) { | |
973558a3 | 1772 | lastword &= MAKE_64BIT_MASK(0, setsz % 64); |
028e2a7b RH |
1773 | } |
1774 | } | |
1775 | ||
1776 | t = tcg_temp_new_i64(); | |
1777 | if (fullsz <= 64) { | |
1778 | tcg_gen_movi_i64(t, lastword); | |
1779 | tcg_gen_st_i64(t, cpu_env, ofs); | |
1780 | goto done; | |
1781 | } | |
1782 | ||
1783 | if (word == lastword) { | |
1784 | unsigned maxsz = size_for_gvec(fullsz / 8); | |
1785 | unsigned oprsz = size_for_gvec(setsz / 8); | |
1786 | ||
1787 | if (oprsz * 8 == setsz) { | |
8711e71f | 1788 | tcg_gen_gvec_dup_imm(MO_64, ofs, oprsz, maxsz, word); |
028e2a7b RH |
1789 | goto done; |
1790 | } | |
028e2a7b RH |
1791 | } |
1792 | ||
1793 | setsz /= 8; | |
1794 | fullsz /= 8; | |
1795 | ||
1796 | tcg_gen_movi_i64(t, word); | |
973558a3 | 1797 | for (i = 0; i < QEMU_ALIGN_DOWN(setsz, 8); i += 8) { |
028e2a7b RH |
1798 | tcg_gen_st_i64(t, cpu_env, ofs + i); |
1799 | } | |
1800 | if (lastword != word) { | |
1801 | tcg_gen_movi_i64(t, lastword); | |
1802 | tcg_gen_st_i64(t, cpu_env, ofs + i); | |
1803 | i += 8; | |
1804 | } | |
1805 | if (i < fullsz) { | |
1806 | tcg_gen_movi_i64(t, 0); | |
1807 | for (; i < fullsz; i += 8) { | |
1808 | tcg_gen_st_i64(t, cpu_env, ofs + i); | |
1809 | } | |
1810 | } | |
1811 | ||
1812 | done: | |
1813 | tcg_temp_free_i64(t); | |
1814 | ||
1815 | /* PTRUES */ | |
1816 | if (setflag) { | |
1817 | tcg_gen_movi_i32(cpu_NF, -(word != 0)); | |
1818 | tcg_gen_movi_i32(cpu_CF, word == 0); | |
1819 | tcg_gen_movi_i32(cpu_VF, 0); | |
1820 | tcg_gen_mov_i32(cpu_ZF, cpu_NF); | |
1821 | } | |
1822 | return true; | |
1823 | } | |
1824 | ||
3a7be554 | 1825 | static bool trans_PTRUE(DisasContext *s, arg_PTRUE *a) |
028e2a7b RH |
1826 | { |
1827 | return do_predset(s, a->esz, a->rd, a->pat, a->s); | |
1828 | } | |
1829 | ||
3a7be554 | 1830 | static bool trans_SETFFR(DisasContext *s, arg_SETFFR *a) |
028e2a7b RH |
1831 | { |
1832 | /* Note pat == 31 is #all, to set all elements. */ | |
1833 | return do_predset(s, 0, FFR_PRED_NUM, 31, false); | |
1834 | } | |
1835 | ||
3a7be554 | 1836 | static bool trans_PFALSE(DisasContext *s, arg_PFALSE *a) |
028e2a7b RH |
1837 | { |
1838 | /* Note pat == 32 is #unimp, to set no elements. */ | |
1839 | return do_predset(s, 0, a->rd, 32, false); | |
1840 | } | |
1841 | ||
3a7be554 | 1842 | static bool trans_RDFFR_p(DisasContext *s, arg_RDFFR_p *a) |
028e2a7b RH |
1843 | { |
1844 | /* The path through do_pppp_flags is complicated enough to want to avoid | |
1845 | * duplication. Frob the arguments into the form of a predicated AND. | |
1846 | */ | |
1847 | arg_rprr_s alt_a = { | |
1848 | .rd = a->rd, .pg = a->pg, .s = a->s, | |
1849 | .rn = FFR_PRED_NUM, .rm = FFR_PRED_NUM, | |
1850 | }; | |
3a7be554 | 1851 | return trans_AND_pppp(s, &alt_a); |
028e2a7b RH |
1852 | } |
1853 | ||
3a7be554 | 1854 | static bool trans_RDFFR(DisasContext *s, arg_RDFFR *a) |
028e2a7b RH |
1855 | { |
1856 | return do_mov_p(s, a->rd, FFR_PRED_NUM); | |
1857 | } | |
1858 | ||
3a7be554 | 1859 | static bool trans_WRFFR(DisasContext *s, arg_WRFFR *a) |
028e2a7b RH |
1860 | { |
1861 | return do_mov_p(s, FFR_PRED_NUM, a->rn); | |
1862 | } | |
1863 | ||
1864 | static bool do_pfirst_pnext(DisasContext *s, arg_rr_esz *a, | |
1865 | void (*gen_fn)(TCGv_i32, TCGv_ptr, | |
1866 | TCGv_ptr, TCGv_i32)) | |
1867 | { | |
1868 | if (!sve_access_check(s)) { | |
1869 | return true; | |
1870 | } | |
1871 | ||
1872 | TCGv_ptr t_pd = tcg_temp_new_ptr(); | |
1873 | TCGv_ptr t_pg = tcg_temp_new_ptr(); | |
1874 | TCGv_i32 t; | |
86300b5d | 1875 | unsigned desc = 0; |
028e2a7b | 1876 | |
86300b5d RH |
1877 | desc = FIELD_DP32(desc, PREDDESC, OPRSZ, pred_full_reg_size(s)); |
1878 | desc = FIELD_DP32(desc, PREDDESC, ESZ, a->esz); | |
028e2a7b RH |
1879 | |
1880 | tcg_gen_addi_ptr(t_pd, cpu_env, pred_full_reg_offset(s, a->rd)); | |
1881 | tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, a->rn)); | |
392acacc | 1882 | t = tcg_temp_new_i32(); |
028e2a7b | 1883 | |
392acacc | 1884 | gen_fn(t, t_pd, t_pg, tcg_constant_i32(desc)); |
028e2a7b RH |
1885 | tcg_temp_free_ptr(t_pd); |
1886 | tcg_temp_free_ptr(t_pg); | |
1887 | ||
1888 | do_pred_flags(t); | |
1889 | tcg_temp_free_i32(t); | |
1890 | return true; | |
1891 | } | |
1892 | ||
3a7be554 | 1893 | static bool trans_PFIRST(DisasContext *s, arg_rr_esz *a) |
028e2a7b RH |
1894 | { |
1895 | return do_pfirst_pnext(s, a, gen_helper_sve_pfirst); | |
1896 | } | |
1897 | ||
3a7be554 | 1898 | static bool trans_PNEXT(DisasContext *s, arg_rr_esz *a) |
028e2a7b RH |
1899 | { |
1900 | return do_pfirst_pnext(s, a, gen_helper_sve_pnext); | |
1901 | } | |
1902 | ||
24e82e68 RH |
1903 | /* |
1904 | *** SVE Element Count Group | |
1905 | */ | |
1906 | ||
1907 | /* Perform an inline saturating addition of a 32-bit value within | |
1908 | * a 64-bit register. The second operand is known to be positive, | |
1909 | * which halves the comparisions we must perform to bound the result. | |
1910 | */ | |
1911 | static void do_sat_addsub_32(TCGv_i64 reg, TCGv_i64 val, bool u, bool d) | |
1912 | { | |
1913 | int64_t ibound; | |
24e82e68 RH |
1914 | |
1915 | /* Use normal 64-bit arithmetic to detect 32-bit overflow. */ | |
1916 | if (u) { | |
1917 | tcg_gen_ext32u_i64(reg, reg); | |
1918 | } else { | |
1919 | tcg_gen_ext32s_i64(reg, reg); | |
1920 | } | |
1921 | if (d) { | |
1922 | tcg_gen_sub_i64(reg, reg, val); | |
1923 | ibound = (u ? 0 : INT32_MIN); | |
aa5b0b29 | 1924 | tcg_gen_smax_i64(reg, reg, tcg_constant_i64(ibound)); |
24e82e68 RH |
1925 | } else { |
1926 | tcg_gen_add_i64(reg, reg, val); | |
1927 | ibound = (u ? UINT32_MAX : INT32_MAX); | |
aa5b0b29 | 1928 | tcg_gen_smin_i64(reg, reg, tcg_constant_i64(ibound)); |
24e82e68 | 1929 | } |
24e82e68 RH |
1930 | } |
1931 | ||
1932 | /* Similarly with 64-bit values. */ | |
1933 | static void do_sat_addsub_64(TCGv_i64 reg, TCGv_i64 val, bool u, bool d) | |
1934 | { | |
1935 | TCGv_i64 t0 = tcg_temp_new_i64(); | |
24e82e68 RH |
1936 | TCGv_i64 t2; |
1937 | ||
1938 | if (u) { | |
1939 | if (d) { | |
1940 | tcg_gen_sub_i64(t0, reg, val); | |
35a1ec8e PMD |
1941 | t2 = tcg_constant_i64(0); |
1942 | tcg_gen_movcond_i64(TCG_COND_LTU, reg, reg, val, t2, t0); | |
24e82e68 RH |
1943 | } else { |
1944 | tcg_gen_add_i64(t0, reg, val); | |
35a1ec8e PMD |
1945 | t2 = tcg_constant_i64(-1); |
1946 | tcg_gen_movcond_i64(TCG_COND_LTU, reg, t0, reg, t2, t0); | |
24e82e68 RH |
1947 | } |
1948 | } else { | |
35a1ec8e | 1949 | TCGv_i64 t1 = tcg_temp_new_i64(); |
24e82e68 RH |
1950 | if (d) { |
1951 | /* Detect signed overflow for subtraction. */ | |
1952 | tcg_gen_xor_i64(t0, reg, val); | |
1953 | tcg_gen_sub_i64(t1, reg, val); | |
7a31e0c6 | 1954 | tcg_gen_xor_i64(reg, reg, t1); |
24e82e68 RH |
1955 | tcg_gen_and_i64(t0, t0, reg); |
1956 | ||
1957 | /* Bound the result. */ | |
1958 | tcg_gen_movi_i64(reg, INT64_MIN); | |
35a1ec8e | 1959 | t2 = tcg_constant_i64(0); |
24e82e68 RH |
1960 | tcg_gen_movcond_i64(TCG_COND_LT, reg, t0, t2, reg, t1); |
1961 | } else { | |
1962 | /* Detect signed overflow for addition. */ | |
1963 | tcg_gen_xor_i64(t0, reg, val); | |
1964 | tcg_gen_add_i64(reg, reg, val); | |
1965 | tcg_gen_xor_i64(t1, reg, val); | |
1966 | tcg_gen_andc_i64(t0, t1, t0); | |
1967 | ||
1968 | /* Bound the result. */ | |
1969 | tcg_gen_movi_i64(t1, INT64_MAX); | |
35a1ec8e | 1970 | t2 = tcg_constant_i64(0); |
24e82e68 RH |
1971 | tcg_gen_movcond_i64(TCG_COND_LT, reg, t0, t2, t1, reg); |
1972 | } | |
35a1ec8e | 1973 | tcg_temp_free_i64(t1); |
24e82e68 RH |
1974 | } |
1975 | tcg_temp_free_i64(t0); | |
24e82e68 RH |
1976 | } |
1977 | ||
1978 | /* Similarly with a vector and a scalar operand. */ | |
1979 | static void do_sat_addsub_vec(DisasContext *s, int esz, int rd, int rn, | |
1980 | TCGv_i64 val, bool u, bool d) | |
1981 | { | |
1982 | unsigned vsz = vec_full_reg_size(s); | |
1983 | TCGv_ptr dptr, nptr; | |
1984 | TCGv_i32 t32, desc; | |
1985 | TCGv_i64 t64; | |
1986 | ||
1987 | dptr = tcg_temp_new_ptr(); | |
1988 | nptr = tcg_temp_new_ptr(); | |
1989 | tcg_gen_addi_ptr(dptr, cpu_env, vec_full_reg_offset(s, rd)); | |
1990 | tcg_gen_addi_ptr(nptr, cpu_env, vec_full_reg_offset(s, rn)); | |
1991 | desc = tcg_const_i32(simd_desc(vsz, vsz, 0)); | |
1992 | ||
1993 | switch (esz) { | |
1994 | case MO_8: | |
1995 | t32 = tcg_temp_new_i32(); | |
1996 | tcg_gen_extrl_i64_i32(t32, val); | |
1997 | if (d) { | |
1998 | tcg_gen_neg_i32(t32, t32); | |
1999 | } | |
2000 | if (u) { | |
2001 | gen_helper_sve_uqaddi_b(dptr, nptr, t32, desc); | |
2002 | } else { | |
2003 | gen_helper_sve_sqaddi_b(dptr, nptr, t32, desc); | |
2004 | } | |
2005 | tcg_temp_free_i32(t32); | |
2006 | break; | |
2007 | ||
2008 | case MO_16: | |
2009 | t32 = tcg_temp_new_i32(); | |
2010 | tcg_gen_extrl_i64_i32(t32, val); | |
2011 | if (d) { | |
2012 | tcg_gen_neg_i32(t32, t32); | |
2013 | } | |
2014 | if (u) { | |
2015 | gen_helper_sve_uqaddi_h(dptr, nptr, t32, desc); | |
2016 | } else { | |
2017 | gen_helper_sve_sqaddi_h(dptr, nptr, t32, desc); | |
2018 | } | |
2019 | tcg_temp_free_i32(t32); | |
2020 | break; | |
2021 | ||
2022 | case MO_32: | |
2023 | t64 = tcg_temp_new_i64(); | |
2024 | if (d) { | |
2025 | tcg_gen_neg_i64(t64, val); | |
2026 | } else { | |
2027 | tcg_gen_mov_i64(t64, val); | |
2028 | } | |
2029 | if (u) { | |
2030 | gen_helper_sve_uqaddi_s(dptr, nptr, t64, desc); | |
2031 | } else { | |
2032 | gen_helper_sve_sqaddi_s(dptr, nptr, t64, desc); | |
2033 | } | |
2034 | tcg_temp_free_i64(t64); | |
2035 | break; | |
2036 | ||
2037 | case MO_64: | |
2038 | if (u) { | |
2039 | if (d) { | |
2040 | gen_helper_sve_uqsubi_d(dptr, nptr, val, desc); | |
2041 | } else { | |
2042 | gen_helper_sve_uqaddi_d(dptr, nptr, val, desc); | |
2043 | } | |
2044 | } else if (d) { | |
2045 | t64 = tcg_temp_new_i64(); | |
2046 | tcg_gen_neg_i64(t64, val); | |
2047 | gen_helper_sve_sqaddi_d(dptr, nptr, t64, desc); | |
2048 | tcg_temp_free_i64(t64); | |
2049 | } else { | |
2050 | gen_helper_sve_sqaddi_d(dptr, nptr, val, desc); | |
2051 | } | |
2052 | break; | |
2053 | ||
2054 | default: | |
2055 | g_assert_not_reached(); | |
2056 | } | |
2057 | ||
2058 | tcg_temp_free_ptr(dptr); | |
2059 | tcg_temp_free_ptr(nptr); | |
2060 | tcg_temp_free_i32(desc); | |
2061 | } | |
2062 | ||
3a7be554 | 2063 | static bool trans_CNT_r(DisasContext *s, arg_CNT_r *a) |
24e82e68 RH |
2064 | { |
2065 | if (sve_access_check(s)) { | |
2066 | unsigned fullsz = vec_full_reg_size(s); | |
2067 | unsigned numelem = decode_pred_count(fullsz, a->pat, a->esz); | |
2068 | tcg_gen_movi_i64(cpu_reg(s, a->rd), numelem * a->imm); | |
2069 | } | |
2070 | return true; | |
2071 | } | |
2072 | ||
3a7be554 | 2073 | static bool trans_INCDEC_r(DisasContext *s, arg_incdec_cnt *a) |
24e82e68 RH |
2074 | { |
2075 | if (sve_access_check(s)) { | |
2076 | unsigned fullsz = vec_full_reg_size(s); | |
2077 | unsigned numelem = decode_pred_count(fullsz, a->pat, a->esz); | |
2078 | int inc = numelem * a->imm * (a->d ? -1 : 1); | |
2079 | TCGv_i64 reg = cpu_reg(s, a->rd); | |
2080 | ||
2081 | tcg_gen_addi_i64(reg, reg, inc); | |
2082 | } | |
2083 | return true; | |
2084 | } | |
2085 | ||
3a7be554 | 2086 | static bool trans_SINCDEC_r_32(DisasContext *s, arg_incdec_cnt *a) |
24e82e68 RH |
2087 | { |
2088 | if (!sve_access_check(s)) { | |
2089 | return true; | |
2090 | } | |
2091 | ||
2092 | unsigned fullsz = vec_full_reg_size(s); | |
2093 | unsigned numelem = decode_pred_count(fullsz, a->pat, a->esz); | |
2094 | int inc = numelem * a->imm; | |
2095 | TCGv_i64 reg = cpu_reg(s, a->rd); | |
2096 | ||
2097 | /* Use normal 64-bit arithmetic to detect 32-bit overflow. */ | |
2098 | if (inc == 0) { | |
2099 | if (a->u) { | |
2100 | tcg_gen_ext32u_i64(reg, reg); | |
2101 | } else { | |
2102 | tcg_gen_ext32s_i64(reg, reg); | |
2103 | } | |
2104 | } else { | |
d681f125 | 2105 | do_sat_addsub_32(reg, tcg_constant_i64(inc), a->u, a->d); |
24e82e68 RH |
2106 | } |
2107 | return true; | |
2108 | } | |
2109 | ||
3a7be554 | 2110 | static bool trans_SINCDEC_r_64(DisasContext *s, arg_incdec_cnt *a) |
24e82e68 RH |
2111 | { |
2112 | if (!sve_access_check(s)) { | |
2113 | return true; | |
2114 | } | |
2115 | ||
2116 | unsigned fullsz = vec_full_reg_size(s); | |
2117 | unsigned numelem = decode_pred_count(fullsz, a->pat, a->esz); | |
2118 | int inc = numelem * a->imm; | |
2119 | TCGv_i64 reg = cpu_reg(s, a->rd); | |
2120 | ||
2121 | if (inc != 0) { | |
d681f125 | 2122 | do_sat_addsub_64(reg, tcg_constant_i64(inc), a->u, a->d); |
24e82e68 RH |
2123 | } |
2124 | return true; | |
2125 | } | |
2126 | ||
3a7be554 | 2127 | static bool trans_INCDEC_v(DisasContext *s, arg_incdec2_cnt *a) |
24e82e68 RH |
2128 | { |
2129 | if (a->esz == 0) { | |
2130 | return false; | |
2131 | } | |
2132 | ||
2133 | unsigned fullsz = vec_full_reg_size(s); | |
2134 | unsigned numelem = decode_pred_count(fullsz, a->pat, a->esz); | |
2135 | int inc = numelem * a->imm; | |
2136 | ||
2137 | if (inc != 0) { | |
2138 | if (sve_access_check(s)) { | |
24e82e68 RH |
2139 | tcg_gen_gvec_adds(a->esz, vec_full_reg_offset(s, a->rd), |
2140 | vec_full_reg_offset(s, a->rn), | |
d681f125 RH |
2141 | tcg_constant_i64(a->d ? -inc : inc), |
2142 | fullsz, fullsz); | |
24e82e68 RH |
2143 | } |
2144 | } else { | |
2145 | do_mov_z(s, a->rd, a->rn); | |
2146 | } | |
2147 | return true; | |
2148 | } | |
2149 | ||
3a7be554 | 2150 | static bool trans_SINCDEC_v(DisasContext *s, arg_incdec2_cnt *a) |
24e82e68 RH |
2151 | { |
2152 | if (a->esz == 0) { | |
2153 | return false; | |
2154 | } | |
2155 | ||
2156 | unsigned fullsz = vec_full_reg_size(s); | |
2157 | unsigned numelem = decode_pred_count(fullsz, a->pat, a->esz); | |
2158 | int inc = numelem * a->imm; | |
2159 | ||
2160 | if (inc != 0) { | |
2161 | if (sve_access_check(s)) { | |
d681f125 RH |
2162 | do_sat_addsub_vec(s, a->esz, a->rd, a->rn, |
2163 | tcg_constant_i64(inc), a->u, a->d); | |
24e82e68 RH |
2164 | } |
2165 | } else { | |
2166 | do_mov_z(s, a->rd, a->rn); | |
2167 | } | |
2168 | return true; | |
2169 | } | |
2170 | ||
e1fa1164 RH |
2171 | /* |
2172 | *** SVE Bitwise Immediate Group | |
2173 | */ | |
2174 | ||
2175 | static bool do_zz_dbm(DisasContext *s, arg_rr_dbm *a, GVecGen2iFn *gvec_fn) | |
2176 | { | |
2177 | uint64_t imm; | |
2178 | if (!logic_imm_decode_wmask(&imm, extract32(a->dbm, 12, 1), | |
2179 | extract32(a->dbm, 0, 6), | |
2180 | extract32(a->dbm, 6, 6))) { | |
2181 | return false; | |
2182 | } | |
2183 | if (sve_access_check(s)) { | |
2184 | unsigned vsz = vec_full_reg_size(s); | |
2185 | gvec_fn(MO_64, vec_full_reg_offset(s, a->rd), | |
2186 | vec_full_reg_offset(s, a->rn), imm, vsz, vsz); | |
2187 | } | |
2188 | return true; | |
2189 | } | |
2190 | ||
3a7be554 | 2191 | static bool trans_AND_zzi(DisasContext *s, arg_rr_dbm *a) |
e1fa1164 RH |
2192 | { |
2193 | return do_zz_dbm(s, a, tcg_gen_gvec_andi); | |
2194 | } | |
2195 | ||
3a7be554 | 2196 | static bool trans_ORR_zzi(DisasContext *s, arg_rr_dbm *a) |
e1fa1164 RH |
2197 | { |
2198 | return do_zz_dbm(s, a, tcg_gen_gvec_ori); | |
2199 | } | |
2200 | ||
3a7be554 | 2201 | static bool trans_EOR_zzi(DisasContext *s, arg_rr_dbm *a) |
e1fa1164 RH |
2202 | { |
2203 | return do_zz_dbm(s, a, tcg_gen_gvec_xori); | |
2204 | } | |
2205 | ||
3a7be554 | 2206 | static bool trans_DUPM(DisasContext *s, arg_DUPM *a) |
e1fa1164 RH |
2207 | { |
2208 | uint64_t imm; | |
2209 | if (!logic_imm_decode_wmask(&imm, extract32(a->dbm, 12, 1), | |
2210 | extract32(a->dbm, 0, 6), | |
2211 | extract32(a->dbm, 6, 6))) { | |
2212 | return false; | |
2213 | } | |
2214 | if (sve_access_check(s)) { | |
2215 | do_dupi_z(s, a->rd, imm); | |
2216 | } | |
2217 | return true; | |
2218 | } | |
2219 | ||
f25a2361 RH |
2220 | /* |
2221 | *** SVE Integer Wide Immediate - Predicated Group | |
2222 | */ | |
2223 | ||
2224 | /* Implement all merging copies. This is used for CPY (immediate), | |
2225 | * FCPY, CPY (scalar), CPY (SIMD&FP scalar). | |
2226 | */ | |
2227 | static void do_cpy_m(DisasContext *s, int esz, int rd, int rn, int pg, | |
2228 | TCGv_i64 val) | |
2229 | { | |
2230 | typedef void gen_cpy(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i64, TCGv_i32); | |
2231 | static gen_cpy * const fns[4] = { | |
2232 | gen_helper_sve_cpy_m_b, gen_helper_sve_cpy_m_h, | |
2233 | gen_helper_sve_cpy_m_s, gen_helper_sve_cpy_m_d, | |
2234 | }; | |
2235 | unsigned vsz = vec_full_reg_size(s); | |
2236 | TCGv_i32 desc = tcg_const_i32(simd_desc(vsz, vsz, 0)); | |
2237 | TCGv_ptr t_zd = tcg_temp_new_ptr(); | |
2238 | TCGv_ptr t_zn = tcg_temp_new_ptr(); | |
2239 | TCGv_ptr t_pg = tcg_temp_new_ptr(); | |
2240 | ||
2241 | tcg_gen_addi_ptr(t_zd, cpu_env, vec_full_reg_offset(s, rd)); | |
2242 | tcg_gen_addi_ptr(t_zn, cpu_env, vec_full_reg_offset(s, rn)); | |
2243 | tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, pg)); | |
2244 | ||
2245 | fns[esz](t_zd, t_zn, t_pg, val, desc); | |
2246 | ||
2247 | tcg_temp_free_ptr(t_zd); | |
2248 | tcg_temp_free_ptr(t_zn); | |
2249 | tcg_temp_free_ptr(t_pg); | |
2250 | tcg_temp_free_i32(desc); | |
2251 | } | |
2252 | ||
3a7be554 | 2253 | static bool trans_FCPY(DisasContext *s, arg_FCPY *a) |
f25a2361 RH |
2254 | { |
2255 | if (a->esz == 0) { | |
2256 | return false; | |
2257 | } | |
2258 | if (sve_access_check(s)) { | |
2259 | /* Decode the VFP immediate. */ | |
2260 | uint64_t imm = vfp_expand_imm(a->esz, a->imm); | |
e152b48b | 2261 | do_cpy_m(s, a->esz, a->rd, a->rn, a->pg, tcg_constant_i64(imm)); |
f25a2361 RH |
2262 | } |
2263 | return true; | |
2264 | } | |
2265 | ||
3a7be554 | 2266 | static bool trans_CPY_m_i(DisasContext *s, arg_rpri_esz *a) |
f25a2361 | 2267 | { |
3a7be554 | 2268 | if (a->esz == 0 && extract32(s->insn, 13, 1)) { |
f25a2361 RH |
2269 | return false; |
2270 | } | |
2271 | if (sve_access_check(s)) { | |
e152b48b | 2272 | do_cpy_m(s, a->esz, a->rd, a->rn, a->pg, tcg_constant_i64(a->imm)); |
f25a2361 RH |
2273 | } |
2274 | return true; | |
2275 | } | |
2276 | ||
3a7be554 | 2277 | static bool trans_CPY_z_i(DisasContext *s, arg_CPY_z_i *a) |
f25a2361 RH |
2278 | { |
2279 | static gen_helper_gvec_2i * const fns[4] = { | |
2280 | gen_helper_sve_cpy_z_b, gen_helper_sve_cpy_z_h, | |
2281 | gen_helper_sve_cpy_z_s, gen_helper_sve_cpy_z_d, | |
2282 | }; | |
2283 | ||
3a7be554 | 2284 | if (a->esz == 0 && extract32(s->insn, 13, 1)) { |
f25a2361 RH |
2285 | return false; |
2286 | } | |
2287 | if (sve_access_check(s)) { | |
2288 | unsigned vsz = vec_full_reg_size(s); | |
f25a2361 RH |
2289 | tcg_gen_gvec_2i_ool(vec_full_reg_offset(s, a->rd), |
2290 | pred_full_reg_offset(s, a->pg), | |
e152b48b RH |
2291 | tcg_constant_i64(a->imm), |
2292 | vsz, vsz, 0, fns[a->esz]); | |
f25a2361 RH |
2293 | } |
2294 | return true; | |
2295 | } | |
2296 | ||
b94f8f60 RH |
2297 | /* |
2298 | *** SVE Permute Extract Group | |
2299 | */ | |
2300 | ||
75114792 | 2301 | static bool do_EXT(DisasContext *s, int rd, int rn, int rm, int imm) |
b94f8f60 RH |
2302 | { |
2303 | if (!sve_access_check(s)) { | |
2304 | return true; | |
2305 | } | |
2306 | ||
2307 | unsigned vsz = vec_full_reg_size(s); | |
75114792 | 2308 | unsigned n_ofs = imm >= vsz ? 0 : imm; |
b94f8f60 | 2309 | unsigned n_siz = vsz - n_ofs; |
75114792 SL |
2310 | unsigned d = vec_full_reg_offset(s, rd); |
2311 | unsigned n = vec_full_reg_offset(s, rn); | |
2312 | unsigned m = vec_full_reg_offset(s, rm); | |
b94f8f60 RH |
2313 | |
2314 | /* Use host vector move insns if we have appropriate sizes | |
2315 | * and no unfortunate overlap. | |
2316 | */ | |
2317 | if (m != d | |
2318 | && n_ofs == size_for_gvec(n_ofs) | |
2319 | && n_siz == size_for_gvec(n_siz) | |
2320 | && (d != n || n_siz <= n_ofs)) { | |
2321 | tcg_gen_gvec_mov(0, d, n + n_ofs, n_siz, n_siz); | |
2322 | if (n_ofs != 0) { | |
2323 | tcg_gen_gvec_mov(0, d + n_siz, m, n_ofs, n_ofs); | |
2324 | } | |
2325 | } else { | |
2326 | tcg_gen_gvec_3_ool(d, n, m, vsz, vsz, n_ofs, gen_helper_sve_ext); | |
2327 | } | |
2328 | return true; | |
2329 | } | |
2330 | ||
75114792 SL |
2331 | static bool trans_EXT(DisasContext *s, arg_EXT *a) |
2332 | { | |
2333 | return do_EXT(s, a->rd, a->rn, a->rm, a->imm); | |
2334 | } | |
2335 | ||
2336 | static bool trans_EXT_sve2(DisasContext *s, arg_rri *a) | |
2337 | { | |
2338 | if (!dc_isar_feature(aa64_sve2, s)) { | |
2339 | return false; | |
2340 | } | |
2341 | return do_EXT(s, a->rd, a->rn, (a->rn + 1) % 32, a->imm); | |
2342 | } | |
2343 | ||
30562ab7 RH |
2344 | /* |
2345 | *** SVE Permute - Unpredicated Group | |
2346 | */ | |
2347 | ||
3a7be554 | 2348 | static bool trans_DUP_s(DisasContext *s, arg_DUP_s *a) |
30562ab7 RH |
2349 | { |
2350 | if (sve_access_check(s)) { | |
2351 | unsigned vsz = vec_full_reg_size(s); | |
2352 | tcg_gen_gvec_dup_i64(a->esz, vec_full_reg_offset(s, a->rd), | |
2353 | vsz, vsz, cpu_reg_sp(s, a->rn)); | |
2354 | } | |
2355 | return true; | |
2356 | } | |
2357 | ||
3a7be554 | 2358 | static bool trans_DUP_x(DisasContext *s, arg_DUP_x *a) |
30562ab7 RH |
2359 | { |
2360 | if ((a->imm & 0x1f) == 0) { | |
2361 | return false; | |
2362 | } | |
2363 | if (sve_access_check(s)) { | |
2364 | unsigned vsz = vec_full_reg_size(s); | |
2365 | unsigned dofs = vec_full_reg_offset(s, a->rd); | |
2366 | unsigned esz, index; | |
2367 | ||
2368 | esz = ctz32(a->imm); | |
2369 | index = a->imm >> (esz + 1); | |
2370 | ||
2371 | if ((index << esz) < vsz) { | |
2372 | unsigned nofs = vec_reg_offset(s, a->rn, index, esz); | |
2373 | tcg_gen_gvec_dup_mem(esz, dofs, nofs, vsz, vsz); | |
2374 | } else { | |
7e17d50e RH |
2375 | /* |
2376 | * While dup_mem handles 128-bit elements, dup_imm does not. | |
2377 | * Thankfully element size doesn't matter for splatting zero. | |
2378 | */ | |
2379 | tcg_gen_gvec_dup_imm(MO_64, dofs, vsz, vsz, 0); | |
30562ab7 RH |
2380 | } |
2381 | } | |
2382 | return true; | |
2383 | } | |
2384 | ||
2385 | static void do_insr_i64(DisasContext *s, arg_rrr_esz *a, TCGv_i64 val) | |
2386 | { | |
2387 | typedef void gen_insr(TCGv_ptr, TCGv_ptr, TCGv_i64, TCGv_i32); | |
2388 | static gen_insr * const fns[4] = { | |
2389 | gen_helper_sve_insr_b, gen_helper_sve_insr_h, | |
2390 | gen_helper_sve_insr_s, gen_helper_sve_insr_d, | |
2391 | }; | |
2392 | unsigned vsz = vec_full_reg_size(s); | |
2393 | TCGv_i32 desc = tcg_const_i32(simd_desc(vsz, vsz, 0)); | |
2394 | TCGv_ptr t_zd = tcg_temp_new_ptr(); | |
2395 | TCGv_ptr t_zn = tcg_temp_new_ptr(); | |
2396 | ||
2397 | tcg_gen_addi_ptr(t_zd, cpu_env, vec_full_reg_offset(s, a->rd)); | |
2398 | tcg_gen_addi_ptr(t_zn, cpu_env, vec_full_reg_offset(s, a->rn)); | |
2399 | ||
2400 | fns[a->esz](t_zd, t_zn, val, desc); | |
2401 | ||
2402 | tcg_temp_free_ptr(t_zd); | |
2403 | tcg_temp_free_ptr(t_zn); | |
2404 | tcg_temp_free_i32(desc); | |
2405 | } | |
2406 | ||
3a7be554 | 2407 | static bool trans_INSR_f(DisasContext *s, arg_rrr_esz *a) |
30562ab7 RH |
2408 | { |
2409 | if (sve_access_check(s)) { | |
2410 | TCGv_i64 t = tcg_temp_new_i64(); | |
2411 | tcg_gen_ld_i64(t, cpu_env, vec_reg_offset(s, a->rm, 0, MO_64)); | |
2412 | do_insr_i64(s, a, t); | |
2413 | tcg_temp_free_i64(t); | |
2414 | } | |
2415 | return true; | |
2416 | } | |
2417 | ||
3a7be554 | 2418 | static bool trans_INSR_r(DisasContext *s, arg_rrr_esz *a) |
30562ab7 RH |
2419 | { |
2420 | if (sve_access_check(s)) { | |
2421 | do_insr_i64(s, a, cpu_reg(s, a->rm)); | |
2422 | } | |
2423 | return true; | |
2424 | } | |
2425 | ||
3a7be554 | 2426 | static bool trans_REV_v(DisasContext *s, arg_rr_esz *a) |
30562ab7 RH |
2427 | { |
2428 | static gen_helper_gvec_2 * const fns[4] = { | |
2429 | gen_helper_sve_rev_b, gen_helper_sve_rev_h, | |
2430 | gen_helper_sve_rev_s, gen_helper_sve_rev_d | |
2431 | }; | |
2432 | ||
2433 | if (sve_access_check(s)) { | |
40e32e5a | 2434 | gen_gvec_ool_zz(s, fns[a->esz], a->rd, a->rn, 0); |
30562ab7 RH |
2435 | } |
2436 | return true; | |
2437 | } | |
2438 | ||
3a7be554 | 2439 | static bool trans_TBL(DisasContext *s, arg_rrr_esz *a) |
30562ab7 RH |
2440 | { |
2441 | static gen_helper_gvec_3 * const fns[4] = { | |
2442 | gen_helper_sve_tbl_b, gen_helper_sve_tbl_h, | |
2443 | gen_helper_sve_tbl_s, gen_helper_sve_tbl_d | |
2444 | }; | |
2445 | ||
2446 | if (sve_access_check(s)) { | |
e645d1a1 | 2447 | gen_gvec_ool_zzz(s, fns[a->esz], a->rd, a->rn, a->rm, 0); |
30562ab7 RH |
2448 | } |
2449 | return true; | |
2450 | } | |
2451 | ||
80a712a2 SL |
2452 | static bool trans_TBL_sve2(DisasContext *s, arg_rrr_esz *a) |
2453 | { | |
2454 | static gen_helper_gvec_4 * const fns[4] = { | |
2455 | gen_helper_sve2_tbl_b, gen_helper_sve2_tbl_h, | |
2456 | gen_helper_sve2_tbl_s, gen_helper_sve2_tbl_d | |
2457 | }; | |
2458 | ||
2459 | if (!dc_isar_feature(aa64_sve2, s)) { | |
2460 | return false; | |
2461 | } | |
2462 | if (sve_access_check(s)) { | |
2463 | gen_gvec_ool_zzzz(s, fns[a->esz], a->rd, a->rn, | |
2464 | (a->rn + 1) % 32, a->rm, 0); | |
2465 | } | |
2466 | return true; | |
2467 | } | |
2468 | ||
2469 | static bool trans_TBX(DisasContext *s, arg_rrr_esz *a) | |
2470 | { | |
2471 | static gen_helper_gvec_3 * const fns[4] = { | |
2472 | gen_helper_sve2_tbx_b, gen_helper_sve2_tbx_h, | |
2473 | gen_helper_sve2_tbx_s, gen_helper_sve2_tbx_d | |
2474 | }; | |
2475 | ||
2476 | if (!dc_isar_feature(aa64_sve2, s)) { | |
2477 | return false; | |
2478 | } | |
2479 | if (sve_access_check(s)) { | |
2480 | gen_gvec_ool_zzz(s, fns[a->esz], a->rd, a->rn, a->rm, 0); | |
2481 | } | |
2482 | return true; | |
2483 | } | |
2484 | ||
3a7be554 | 2485 | static bool trans_UNPK(DisasContext *s, arg_UNPK *a) |
30562ab7 RH |
2486 | { |
2487 | static gen_helper_gvec_2 * const fns[4][2] = { | |
2488 | { NULL, NULL }, | |
2489 | { gen_helper_sve_sunpk_h, gen_helper_sve_uunpk_h }, | |
2490 | { gen_helper_sve_sunpk_s, gen_helper_sve_uunpk_s }, | |
2491 | { gen_helper_sve_sunpk_d, gen_helper_sve_uunpk_d }, | |
2492 | }; | |
2493 | ||
2494 | if (a->esz == 0) { | |
2495 | return false; | |
2496 | } | |
2497 | if (sve_access_check(s)) { | |
2498 | unsigned vsz = vec_full_reg_size(s); | |
2499 | tcg_gen_gvec_2_ool(vec_full_reg_offset(s, a->rd), | |
2500 | vec_full_reg_offset(s, a->rn) | |
2501 | + (a->h ? vsz / 2 : 0), | |
2502 | vsz, vsz, 0, fns[a->esz][a->u]); | |
2503 | } | |
2504 | return true; | |
2505 | } | |
2506 | ||
d731d8cb RH |
2507 | /* |
2508 | *** SVE Permute - Predicates Group | |
2509 | */ | |
2510 | ||
2511 | static bool do_perm_pred3(DisasContext *s, arg_rrr_esz *a, bool high_odd, | |
2512 | gen_helper_gvec_3 *fn) | |
2513 | { | |
2514 | if (!sve_access_check(s)) { | |
2515 | return true; | |
2516 | } | |
2517 | ||
2518 | unsigned vsz = pred_full_reg_size(s); | |
2519 | ||
d731d8cb RH |
2520 | TCGv_ptr t_d = tcg_temp_new_ptr(); |
2521 | TCGv_ptr t_n = tcg_temp_new_ptr(); | |
2522 | TCGv_ptr t_m = tcg_temp_new_ptr(); | |
2523 | TCGv_i32 t_desc; | |
f9b0fcce | 2524 | uint32_t desc = 0; |
d731d8cb | 2525 | |
f9b0fcce RH |
2526 | desc = FIELD_DP32(desc, PREDDESC, OPRSZ, vsz); |
2527 | desc = FIELD_DP32(desc, PREDDESC, ESZ, a->esz); | |
2528 | desc = FIELD_DP32(desc, PREDDESC, DATA, high_odd); | |
d731d8cb RH |
2529 | |
2530 | tcg_gen_addi_ptr(t_d, cpu_env, pred_full_reg_offset(s, a->rd)); | |
2531 | tcg_gen_addi_ptr(t_n, cpu_env, pred_full_reg_offset(s, a->rn)); | |
2532 | tcg_gen_addi_ptr(t_m, cpu_env, pred_full_reg_offset(s, a->rm)); | |
2533 | t_desc = tcg_const_i32(desc); | |
2534 | ||
2535 | fn(t_d, t_n, t_m, t_desc); | |
2536 | ||
2537 | tcg_temp_free_ptr(t_d); | |
2538 | tcg_temp_free_ptr(t_n); | |
2539 | tcg_temp_free_ptr(t_m); | |
2540 | tcg_temp_free_i32(t_desc); | |
2541 | return true; | |
2542 | } | |
2543 | ||
2544 | static bool do_perm_pred2(DisasContext *s, arg_rr_esz *a, bool high_odd, | |
2545 | gen_helper_gvec_2 *fn) | |
2546 | { | |
2547 | if (!sve_access_check(s)) { | |
2548 | return true; | |
2549 | } | |
2550 | ||
2551 | unsigned vsz = pred_full_reg_size(s); | |
2552 | TCGv_ptr t_d = tcg_temp_new_ptr(); | |
2553 | TCGv_ptr t_n = tcg_temp_new_ptr(); | |
2554 | TCGv_i32 t_desc; | |
70acaafe | 2555 | uint32_t desc = 0; |
d731d8cb RH |
2556 | |
2557 | tcg_gen_addi_ptr(t_d, cpu_env, pred_full_reg_offset(s, a->rd)); | |
2558 | tcg_gen_addi_ptr(t_n, cpu_env, pred_full_reg_offset(s, a->rn)); | |
2559 | ||
70acaafe RH |
2560 | desc = FIELD_DP32(desc, PREDDESC, OPRSZ, vsz); |
2561 | desc = FIELD_DP32(desc, PREDDESC, ESZ, a->esz); | |
2562 | desc = FIELD_DP32(desc, PREDDESC, DATA, high_odd); | |
d731d8cb RH |
2563 | t_desc = tcg_const_i32(desc); |
2564 | ||
2565 | fn(t_d, t_n, t_desc); | |
2566 | ||
2567 | tcg_temp_free_i32(t_desc); | |
2568 | tcg_temp_free_ptr(t_d); | |
2569 | tcg_temp_free_ptr(t_n); | |
2570 | return true; | |
2571 | } | |
2572 | ||
3a7be554 | 2573 | static bool trans_ZIP1_p(DisasContext *s, arg_rrr_esz *a) |
d731d8cb RH |
2574 | { |
2575 | return do_perm_pred3(s, a, 0, gen_helper_sve_zip_p); | |
2576 | } | |
2577 | ||
3a7be554 | 2578 | static bool trans_ZIP2_p(DisasContext *s, arg_rrr_esz *a) |
d731d8cb RH |
2579 | { |
2580 | return do_perm_pred3(s, a, 1, gen_helper_sve_zip_p); | |
2581 | } | |
2582 | ||
3a7be554 | 2583 | static bool trans_UZP1_p(DisasContext *s, arg_rrr_esz *a) |
d731d8cb RH |
2584 | { |
2585 | return do_perm_pred3(s, a, 0, gen_helper_sve_uzp_p); | |
2586 | } | |
2587 | ||
3a7be554 | 2588 | static bool trans_UZP2_p(DisasContext *s, arg_rrr_esz *a) |
d731d8cb RH |
2589 | { |
2590 | return do_perm_pred3(s, a, 1, gen_helper_sve_uzp_p); | |
2591 | } | |
2592 | ||
3a7be554 | 2593 | static bool trans_TRN1_p(DisasContext *s, arg_rrr_esz *a) |
d731d8cb RH |
2594 | { |
2595 | return do_perm_pred3(s, a, 0, gen_helper_sve_trn_p); | |
2596 | } | |
2597 | ||
3a7be554 | 2598 | static bool trans_TRN2_p(DisasContext *s, arg_rrr_esz *a) |
d731d8cb RH |
2599 | { |
2600 | return do_perm_pred3(s, a, 1, gen_helper_sve_trn_p); | |
2601 | } | |
2602 | ||
3a7be554 | 2603 | static bool trans_REV_p(DisasContext *s, arg_rr_esz *a) |
d731d8cb RH |
2604 | { |
2605 | return do_perm_pred2(s, a, 0, gen_helper_sve_rev_p); | |
2606 | } | |
2607 | ||
3a7be554 | 2608 | static bool trans_PUNPKLO(DisasContext *s, arg_PUNPKLO *a) |
d731d8cb RH |
2609 | { |
2610 | return do_perm_pred2(s, a, 0, gen_helper_sve_punpk_p); | |
2611 | } | |
2612 | ||
3a7be554 | 2613 | static bool trans_PUNPKHI(DisasContext *s, arg_PUNPKHI *a) |
d731d8cb RH |
2614 | { |
2615 | return do_perm_pred2(s, a, 1, gen_helper_sve_punpk_p); | |
2616 | } | |
2617 | ||
234b48e9 RH |
2618 | /* |
2619 | *** SVE Permute - Interleaving Group | |
2620 | */ | |
2621 | ||
2622 | static bool do_zip(DisasContext *s, arg_rrr_esz *a, bool high) | |
2623 | { | |
2624 | static gen_helper_gvec_3 * const fns[4] = { | |
2625 | gen_helper_sve_zip_b, gen_helper_sve_zip_h, | |
2626 | gen_helper_sve_zip_s, gen_helper_sve_zip_d, | |
2627 | }; | |
2628 | ||
2629 | if (sve_access_check(s)) { | |
2630 | unsigned vsz = vec_full_reg_size(s); | |
2631 | unsigned high_ofs = high ? vsz / 2 : 0; | |
2632 | tcg_gen_gvec_3_ool(vec_full_reg_offset(s, a->rd), | |
2633 | vec_full_reg_offset(s, a->rn) + high_ofs, | |
2634 | vec_full_reg_offset(s, a->rm) + high_ofs, | |
2635 | vsz, vsz, 0, fns[a->esz]); | |
2636 | } | |
2637 | return true; | |
2638 | } | |
2639 | ||
2640 | static bool do_zzz_data_ool(DisasContext *s, arg_rrr_esz *a, int data, | |
2641 | gen_helper_gvec_3 *fn) | |
2642 | { | |
2643 | if (sve_access_check(s)) { | |
e645d1a1 | 2644 | gen_gvec_ool_zzz(s, fn, a->rd, a->rn, a->rm, data); |
234b48e9 RH |
2645 | } |
2646 | return true; | |
2647 | } | |
2648 | ||
3a7be554 | 2649 | static bool trans_ZIP1_z(DisasContext *s, arg_rrr_esz *a) |
234b48e9 RH |
2650 | { |
2651 | return do_zip(s, a, false); | |
2652 | } | |
2653 | ||
3a7be554 | 2654 | static bool trans_ZIP2_z(DisasContext *s, arg_rrr_esz *a) |
234b48e9 RH |
2655 | { |
2656 | return do_zip(s, a, true); | |
2657 | } | |
2658 | ||
74b64b25 RH |
2659 | static bool do_zip_q(DisasContext *s, arg_rrr_esz *a, bool high) |
2660 | { | |
2661 | if (!dc_isar_feature(aa64_sve_f64mm, s)) { | |
2662 | return false; | |
2663 | } | |
2664 | if (sve_access_check(s)) { | |
2665 | unsigned vsz = vec_full_reg_size(s); | |
2666 | unsigned high_ofs = high ? QEMU_ALIGN_DOWN(vsz, 32) / 2 : 0; | |
2667 | tcg_gen_gvec_3_ool(vec_full_reg_offset(s, a->rd), | |
2668 | vec_full_reg_offset(s, a->rn) + high_ofs, | |
2669 | vec_full_reg_offset(s, a->rm) + high_ofs, | |
2670 | vsz, vsz, 0, gen_helper_sve2_zip_q); | |
2671 | } | |
2672 | return true; | |
2673 | } | |
2674 | ||
2675 | static bool trans_ZIP1_q(DisasContext *s, arg_rrr_esz *a) | |
2676 | { | |
2677 | return do_zip_q(s, a, false); | |
2678 | } | |
2679 | ||
2680 | static bool trans_ZIP2_q(DisasContext *s, arg_rrr_esz *a) | |
2681 | { | |
2682 | return do_zip_q(s, a, true); | |
2683 | } | |
2684 | ||
234b48e9 RH |
2685 | static gen_helper_gvec_3 * const uzp_fns[4] = { |
2686 | gen_helper_sve_uzp_b, gen_helper_sve_uzp_h, | |
2687 | gen_helper_sve_uzp_s, gen_helper_sve_uzp_d, | |
2688 | }; | |
2689 | ||
3a7be554 | 2690 | static bool trans_UZP1_z(DisasContext *s, arg_rrr_esz *a) |
234b48e9 RH |
2691 | { |
2692 | return do_zzz_data_ool(s, a, 0, uzp_fns[a->esz]); | |
2693 | } | |
2694 | ||
3a7be554 | 2695 | static bool trans_UZP2_z(DisasContext *s, arg_rrr_esz *a) |
234b48e9 RH |
2696 | { |
2697 | return do_zzz_data_ool(s, a, 1 << a->esz, uzp_fns[a->esz]); | |
2698 | } | |
2699 | ||
74b64b25 RH |
2700 | static bool trans_UZP1_q(DisasContext *s, arg_rrr_esz *a) |
2701 | { | |
2702 | if (!dc_isar_feature(aa64_sve_f64mm, s)) { | |
2703 | return false; | |
2704 | } | |
2705 | return do_zzz_data_ool(s, a, 0, gen_helper_sve2_uzp_q); | |
2706 | } | |
2707 | ||
2708 | static bool trans_UZP2_q(DisasContext *s, arg_rrr_esz *a) | |
2709 | { | |
2710 | if (!dc_isar_feature(aa64_sve_f64mm, s)) { | |
2711 | return false; | |
2712 | } | |
2713 | return do_zzz_data_ool(s, a, 16, gen_helper_sve2_uzp_q); | |
2714 | } | |
2715 | ||
234b48e9 RH |
2716 | static gen_helper_gvec_3 * const trn_fns[4] = { |
2717 | gen_helper_sve_trn_b, gen_helper_sve_trn_h, | |
2718 | gen_helper_sve_trn_s, gen_helper_sve_trn_d, | |
2719 | }; | |
2720 | ||
3a7be554 | 2721 | static bool trans_TRN1_z(DisasContext *s, arg_rrr_esz *a) |
234b48e9 RH |
2722 | { |
2723 | return do_zzz_data_ool(s, a, 0, trn_fns[a->esz]); | |
2724 | } | |
2725 | ||
3a7be554 | 2726 | static bool trans_TRN2_z(DisasContext *s, arg_rrr_esz *a) |
234b48e9 RH |
2727 | { |
2728 | return do_zzz_data_ool(s, a, 1 << a->esz, trn_fns[a->esz]); | |
2729 | } | |
2730 | ||
74b64b25 RH |
2731 | static bool trans_TRN1_q(DisasContext *s, arg_rrr_esz *a) |
2732 | { | |
2733 | if (!dc_isar_feature(aa64_sve_f64mm, s)) { | |
2734 | return false; | |
2735 | } | |
2736 | return do_zzz_data_ool(s, a, 0, gen_helper_sve2_trn_q); | |
2737 | } | |
2738 | ||
2739 | static bool trans_TRN2_q(DisasContext *s, arg_rrr_esz *a) | |
2740 | { | |
2741 | if (!dc_isar_feature(aa64_sve_f64mm, s)) { | |
2742 | return false; | |
2743 | } | |
2744 | return do_zzz_data_ool(s, a, 16, gen_helper_sve2_trn_q); | |
2745 | } | |
2746 | ||
3ca879ae RH |
2747 | /* |
2748 | *** SVE Permute Vector - Predicated Group | |
2749 | */ | |
2750 | ||
3a7be554 | 2751 | static bool trans_COMPACT(DisasContext *s, arg_rpr_esz *a) |
3ca879ae RH |
2752 | { |
2753 | static gen_helper_gvec_3 * const fns[4] = { | |
2754 | NULL, NULL, gen_helper_sve_compact_s, gen_helper_sve_compact_d | |
2755 | }; | |
2756 | return do_zpz_ool(s, a, fns[a->esz]); | |
2757 | } | |
2758 | ||
ef23cb72 RH |
2759 | /* Call the helper that computes the ARM LastActiveElement pseudocode |
2760 | * function, scaled by the element size. This includes the not found | |
2761 | * indication; e.g. not found for esz=3 is -8. | |
2762 | */ | |
2763 | static void find_last_active(DisasContext *s, TCGv_i32 ret, int esz, int pg) | |
2764 | { | |
2765 | /* Predicate sizes may be smaller and cannot use simd_desc. We cannot | |
2766 | * round up, as we do elsewhere, because we need the exact size. | |
2767 | */ | |
2768 | TCGv_ptr t_p = tcg_temp_new_ptr(); | |
2769 | TCGv_i32 t_desc; | |
2acbfbe4 | 2770 | unsigned desc = 0; |
ef23cb72 | 2771 | |
2acbfbe4 RH |
2772 | desc = FIELD_DP32(desc, PREDDESC, OPRSZ, pred_full_reg_size(s)); |
2773 | desc = FIELD_DP32(desc, PREDDESC, ESZ, esz); | |
ef23cb72 RH |
2774 | |
2775 | tcg_gen_addi_ptr(t_p, cpu_env, pred_full_reg_offset(s, pg)); | |
2776 | t_desc = tcg_const_i32(desc); | |
2777 | ||
2778 | gen_helper_sve_last_active_element(ret, t_p, t_desc); | |
2779 | ||
2780 | tcg_temp_free_i32(t_desc); | |
2781 | tcg_temp_free_ptr(t_p); | |
2782 | } | |
2783 | ||
2784 | /* Increment LAST to the offset of the next element in the vector, | |
2785 | * wrapping around to 0. | |
2786 | */ | |
2787 | static void incr_last_active(DisasContext *s, TCGv_i32 last, int esz) | |
2788 | { | |
2789 | unsigned vsz = vec_full_reg_size(s); | |
2790 | ||
2791 | tcg_gen_addi_i32(last, last, 1 << esz); | |
2792 | if (is_power_of_2(vsz)) { | |
2793 | tcg_gen_andi_i32(last, last, vsz - 1); | |
2794 | } else { | |
4b308bd5 RH |
2795 | TCGv_i32 max = tcg_constant_i32(vsz); |
2796 | TCGv_i32 zero = tcg_constant_i32(0); | |
ef23cb72 | 2797 | tcg_gen_movcond_i32(TCG_COND_GEU, last, last, max, zero, last); |
ef23cb72 RH |
2798 | } |
2799 | } | |
2800 | ||
2801 | /* If LAST < 0, set LAST to the offset of the last element in the vector. */ | |
2802 | static void wrap_last_active(DisasContext *s, TCGv_i32 last, int esz) | |
2803 | { | |
2804 | unsigned vsz = vec_full_reg_size(s); | |
2805 | ||
2806 | if (is_power_of_2(vsz)) { | |
2807 | tcg_gen_andi_i32(last, last, vsz - 1); | |
2808 | } else { | |
4b308bd5 RH |
2809 | TCGv_i32 max = tcg_constant_i32(vsz - (1 << esz)); |
2810 | TCGv_i32 zero = tcg_constant_i32(0); | |
ef23cb72 | 2811 | tcg_gen_movcond_i32(TCG_COND_LT, last, last, zero, max, last); |
ef23cb72 RH |
2812 | } |
2813 | } | |
2814 | ||
2815 | /* Load an unsigned element of ESZ from BASE+OFS. */ | |
2816 | static TCGv_i64 load_esz(TCGv_ptr base, int ofs, int esz) | |
2817 | { | |
2818 | TCGv_i64 r = tcg_temp_new_i64(); | |
2819 | ||
2820 | switch (esz) { | |
2821 | case 0: | |
2822 | tcg_gen_ld8u_i64(r, base, ofs); | |
2823 | break; | |
2824 | case 1: | |
2825 | tcg_gen_ld16u_i64(r, base, ofs); | |
2826 | break; | |
2827 | case 2: | |
2828 | tcg_gen_ld32u_i64(r, base, ofs); | |
2829 | break; | |
2830 | case 3: | |
2831 | tcg_gen_ld_i64(r, base, ofs); | |
2832 | break; | |
2833 | default: | |
2834 | g_assert_not_reached(); | |
2835 | } | |
2836 | return r; | |
2837 | } | |
2838 | ||
2839 | /* Load an unsigned element of ESZ from RM[LAST]. */ | |
2840 | static TCGv_i64 load_last_active(DisasContext *s, TCGv_i32 last, | |
2841 | int rm, int esz) | |
2842 | { | |
2843 | TCGv_ptr p = tcg_temp_new_ptr(); | |
2844 | TCGv_i64 r; | |
2845 | ||
2846 | /* Convert offset into vector into offset into ENV. | |
2847 | * The final adjustment for the vector register base | |
2848 | * is added via constant offset to the load. | |
2849 | */ | |
e03b5686 | 2850 | #if HOST_BIG_ENDIAN |
ef23cb72 RH |
2851 | /* Adjust for element ordering. See vec_reg_offset. */ |
2852 | if (esz < 3) { | |
2853 | tcg_gen_xori_i32(last, last, 8 - (1 << esz)); | |
2854 | } | |
2855 | #endif | |
2856 | tcg_gen_ext_i32_ptr(p, last); | |
2857 | tcg_gen_add_ptr(p, p, cpu_env); | |
2858 | ||
2859 | r = load_esz(p, vec_full_reg_offset(s, rm), esz); | |
2860 | tcg_temp_free_ptr(p); | |
2861 | ||
2862 | return r; | |
2863 | } | |
2864 | ||
2865 | /* Compute CLAST for a Zreg. */ | |
2866 | static bool do_clast_vector(DisasContext *s, arg_rprr_esz *a, bool before) | |
2867 | { | |
2868 | TCGv_i32 last; | |
2869 | TCGLabel *over; | |
2870 | TCGv_i64 ele; | |
2871 | unsigned vsz, esz = a->esz; | |
2872 | ||
2873 | if (!sve_access_check(s)) { | |
2874 | return true; | |
2875 | } | |
2876 | ||
2877 | last = tcg_temp_local_new_i32(); | |
2878 | over = gen_new_label(); | |
2879 | ||
2880 | find_last_active(s, last, esz, a->pg); | |
2881 | ||
2882 | /* There is of course no movcond for a 2048-bit vector, | |
2883 | * so we must branch over the actual store. | |
2884 | */ | |
2885 | tcg_gen_brcondi_i32(TCG_COND_LT, last, 0, over); | |
2886 | ||
2887 | if (!before) { | |
2888 | incr_last_active(s, last, esz); | |
2889 | } | |
2890 | ||
2891 | ele = load_last_active(s, last, a->rm, esz); | |
2892 | tcg_temp_free_i32(last); | |
2893 | ||
2894 | vsz = vec_full_reg_size(s); | |
2895 | tcg_gen_gvec_dup_i64(esz, vec_full_reg_offset(s, a->rd), vsz, vsz, ele); | |
2896 | tcg_temp_free_i64(ele); | |
2897 | ||
2898 | /* If this insn used MOVPRFX, we may need a second move. */ | |
2899 | if (a->rd != a->rn) { | |
2900 | TCGLabel *done = gen_new_label(); | |
2901 | tcg_gen_br(done); | |
2902 | ||
2903 | gen_set_label(over); | |
2904 | do_mov_z(s, a->rd, a->rn); | |
2905 | ||
2906 | gen_set_label(done); | |
2907 | } else { | |
2908 | gen_set_label(over); | |
2909 | } | |
2910 | return true; | |
2911 | } | |
2912 | ||
3a7be554 | 2913 | static bool trans_CLASTA_z(DisasContext *s, arg_rprr_esz *a) |
ef23cb72 RH |
2914 | { |
2915 | return do_clast_vector(s, a, false); | |
2916 | } | |
2917 | ||
3a7be554 | 2918 | static bool trans_CLASTB_z(DisasContext *s, arg_rprr_esz *a) |
ef23cb72 RH |
2919 | { |
2920 | return do_clast_vector(s, a, true); | |
2921 | } | |
2922 | ||
2923 | /* Compute CLAST for a scalar. */ | |
2924 | static void do_clast_scalar(DisasContext *s, int esz, int pg, int rm, | |
2925 | bool before, TCGv_i64 reg_val) | |
2926 | { | |
2927 | TCGv_i32 last = tcg_temp_new_i32(); | |
053552d3 | 2928 | TCGv_i64 ele, cmp; |
ef23cb72 RH |
2929 | |
2930 | find_last_active(s, last, esz, pg); | |
2931 | ||
2932 | /* Extend the original value of last prior to incrementing. */ | |
2933 | cmp = tcg_temp_new_i64(); | |
2934 | tcg_gen_ext_i32_i64(cmp, last); | |
2935 | ||
2936 | if (!before) { | |
2937 | incr_last_active(s, last, esz); | |
2938 | } | |
2939 | ||
2940 | /* The conceit here is that while last < 0 indicates not found, after | |
2941 | * adjusting for cpu_env->vfp.zregs[rm], it is still a valid address | |
2942 | * from which we can load garbage. We then discard the garbage with | |
2943 | * a conditional move. | |
2944 | */ | |
2945 | ele = load_last_active(s, last, rm, esz); | |
2946 | tcg_temp_free_i32(last); | |
2947 | ||
053552d3 RH |
2948 | tcg_gen_movcond_i64(TCG_COND_GE, reg_val, cmp, tcg_constant_i64(0), |
2949 | ele, reg_val); | |
ef23cb72 | 2950 | |
ef23cb72 RH |
2951 | tcg_temp_free_i64(cmp); |
2952 | tcg_temp_free_i64(ele); | |
2953 | } | |
2954 | ||
2955 | /* Compute CLAST for a Vreg. */ | |
2956 | static bool do_clast_fp(DisasContext *s, arg_rpr_esz *a, bool before) | |
2957 | { | |
2958 | if (sve_access_check(s)) { | |
2959 | int esz = a->esz; | |
2960 | int ofs = vec_reg_offset(s, a->rd, 0, esz); | |
2961 | TCGv_i64 reg = load_esz(cpu_env, ofs, esz); | |
2962 | ||
2963 | do_clast_scalar(s, esz, a->pg, a->rn, before, reg); | |
2964 | write_fp_dreg(s, a->rd, reg); | |
2965 | tcg_temp_free_i64(reg); | |
2966 | } | |
2967 | return true; | |
2968 | } | |
2969 | ||
3a7be554 | 2970 | static bool trans_CLASTA_v(DisasContext *s, arg_rpr_esz *a) |
ef23cb72 RH |
2971 | { |
2972 | return do_clast_fp(s, a, false); | |
2973 | } | |
2974 | ||
3a7be554 | 2975 | static bool trans_CLASTB_v(DisasContext *s, arg_rpr_esz *a) |
ef23cb72 RH |
2976 | { |
2977 | return do_clast_fp(s, a, true); | |
2978 | } | |
2979 | ||
2980 | /* Compute CLAST for a Xreg. */ | |
2981 | static bool do_clast_general(DisasContext *s, arg_rpr_esz *a, bool before) | |
2982 | { | |
2983 | TCGv_i64 reg; | |
2984 | ||
2985 | if (!sve_access_check(s)) { | |
2986 | return true; | |
2987 | } | |
2988 | ||
2989 | reg = cpu_reg(s, a->rd); | |
2990 | switch (a->esz) { | |
2991 | case 0: | |
2992 | tcg_gen_ext8u_i64(reg, reg); | |
2993 | break; | |
2994 | case 1: | |
2995 | tcg_gen_ext16u_i64(reg, reg); | |
2996 | break; | |
2997 | case 2: | |
2998 | tcg_gen_ext32u_i64(reg, reg); | |
2999 | break; | |
3000 | case 3: | |
3001 | break; | |
3002 | default: | |
3003 | g_assert_not_reached(); | |
3004 | } | |
3005 | ||
3006 | do_clast_scalar(s, a->esz, a->pg, a->rn, before, reg); | |
3007 | return true; | |
3008 | } | |
3009 | ||
3a7be554 | 3010 | static bool trans_CLASTA_r(DisasContext *s, arg_rpr_esz *a) |
ef23cb72 RH |
3011 | { |
3012 | return do_clast_general(s, a, false); | |
3013 | } | |
3014 | ||
3a7be554 | 3015 | static bool trans_CLASTB_r(DisasContext *s, arg_rpr_esz *a) |
ef23cb72 RH |
3016 | { |
3017 | return do_clast_general(s, a, true); | |
3018 | } | |
3019 | ||
3020 | /* Compute LAST for a scalar. */ | |
3021 | static TCGv_i64 do_last_scalar(DisasContext *s, int esz, | |
3022 | int pg, int rm, bool before) | |
3023 | { | |
3024 | TCGv_i32 last = tcg_temp_new_i32(); | |
3025 | TCGv_i64 ret; | |
3026 | ||
3027 | find_last_active(s, last, esz, pg); | |
3028 | if (before) { | |
3029 | wrap_last_active(s, last, esz); | |
3030 | } else { | |
3031 | incr_last_active(s, last, esz); | |
3032 | } | |
3033 | ||
3034 | ret = load_last_active(s, last, rm, esz); | |
3035 | tcg_temp_free_i32(last); | |
3036 | return ret; | |
3037 | } | |
3038 | ||
3039 | /* Compute LAST for a Vreg. */ | |
3040 | static bool do_last_fp(DisasContext *s, arg_rpr_esz *a, bool before) | |
3041 | { | |
3042 | if (sve_access_check(s)) { | |
3043 | TCGv_i64 val = do_last_scalar(s, a->esz, a->pg, a->rn, before); | |
3044 | write_fp_dreg(s, a->rd, val); | |
3045 | tcg_temp_free_i64(val); | |
3046 | } | |
3047 | return true; | |
3048 | } | |
3049 | ||
3a7be554 | 3050 | static bool trans_LASTA_v(DisasContext *s, arg_rpr_esz *a) |
ef23cb72 RH |
3051 | { |
3052 | return do_last_fp(s, a, false); | |
3053 | } | |
3054 | ||
3a7be554 | 3055 | static bool trans_LASTB_v(DisasContext *s, arg_rpr_esz *a) |
ef23cb72 RH |
3056 | { |
3057 | return do_last_fp(s, a, true); | |
3058 | } | |
3059 | ||
3060 | /* Compute LAST for a Xreg. */ | |
3061 | static bool do_last_general(DisasContext *s, arg_rpr_esz *a, bool before) | |
3062 | { | |
3063 | if (sve_access_check(s)) { | |
3064 | TCGv_i64 val = do_last_scalar(s, a->esz, a->pg, a->rn, before); | |
3065 | tcg_gen_mov_i64(cpu_reg(s, a->rd), val); | |
3066 | tcg_temp_free_i64(val); | |
3067 | } | |
3068 | return true; | |
3069 | } | |
3070 | ||
3a7be554 | 3071 | static bool trans_LASTA_r(DisasContext *s, arg_rpr_esz *a) |
ef23cb72 RH |
3072 | { |
3073 | return do_last_general(s, a, false); | |
3074 | } | |
3075 | ||
3a7be554 | 3076 | static bool trans_LASTB_r(DisasContext *s, arg_rpr_esz *a) |
ef23cb72 RH |
3077 | { |
3078 | return do_last_general(s, a, true); | |
3079 | } | |
3080 | ||
3a7be554 | 3081 | static bool trans_CPY_m_r(DisasContext *s, arg_rpr_esz *a) |
792a5578 RH |
3082 | { |
3083 | if (sve_access_check(s)) { | |
3084 | do_cpy_m(s, a->esz, a->rd, a->rd, a->pg, cpu_reg_sp(s, a->rn)); | |
3085 | } | |
3086 | return true; | |
3087 | } | |
3088 | ||
3a7be554 | 3089 | static bool trans_CPY_m_v(DisasContext *s, arg_rpr_esz *a) |
792a5578 RH |
3090 | { |
3091 | if (sve_access_check(s)) { | |
3092 | int ofs = vec_reg_offset(s, a->rn, 0, a->esz); | |
3093 | TCGv_i64 t = load_esz(cpu_env, ofs, a->esz); | |
3094 | do_cpy_m(s, a->esz, a->rd, a->rd, a->pg, t); | |
3095 | tcg_temp_free_i64(t); | |
3096 | } | |
3097 | return true; | |
3098 | } | |
3099 | ||
3a7be554 | 3100 | static bool trans_REVB(DisasContext *s, arg_rpr_esz *a) |
dae8fb90 RH |
3101 | { |
3102 | static gen_helper_gvec_3 * const fns[4] = { | |
3103 | NULL, | |
3104 | gen_helper_sve_revb_h, | |
3105 | gen_helper_sve_revb_s, | |
3106 | gen_helper_sve_revb_d, | |
3107 | }; | |
3108 | return do_zpz_ool(s, a, fns[a->esz]); | |
3109 | } | |
3110 | ||
3a7be554 | 3111 | static bool trans_REVH(DisasContext *s, arg_rpr_esz *a) |
dae8fb90 RH |
3112 | { |
3113 | static gen_helper_gvec_3 * const fns[4] = { | |
3114 | NULL, | |
3115 | NULL, | |
3116 | gen_helper_sve_revh_s, | |
3117 | gen_helper_sve_revh_d, | |
3118 | }; | |
3119 | return do_zpz_ool(s, a, fns[a->esz]); | |
3120 | } | |
3121 | ||
3a7be554 | 3122 | static bool trans_REVW(DisasContext *s, arg_rpr_esz *a) |
dae8fb90 RH |
3123 | { |
3124 | return do_zpz_ool(s, a, a->esz == 3 ? gen_helper_sve_revw_d : NULL); | |
3125 | } | |
3126 | ||
3a7be554 | 3127 | static bool trans_RBIT(DisasContext *s, arg_rpr_esz *a) |
dae8fb90 RH |
3128 | { |
3129 | static gen_helper_gvec_3 * const fns[4] = { | |
3130 | gen_helper_sve_rbit_b, | |
3131 | gen_helper_sve_rbit_h, | |
3132 | gen_helper_sve_rbit_s, | |
3133 | gen_helper_sve_rbit_d, | |
3134 | }; | |
3135 | return do_zpz_ool(s, a, fns[a->esz]); | |
3136 | } | |
3137 | ||
3a7be554 | 3138 | static bool trans_SPLICE(DisasContext *s, arg_rprr_esz *a) |
b48ff240 RH |
3139 | { |
3140 | if (sve_access_check(s)) { | |
36cbb7a8 | 3141 | gen_gvec_ool_zzzp(s, gen_helper_sve_splice, |
dd701faf | 3142 | a->rd, a->rn, a->rm, a->pg, a->esz); |
b48ff240 RH |
3143 | } |
3144 | return true; | |
3145 | } | |
3146 | ||
75114792 SL |
3147 | static bool trans_SPLICE_sve2(DisasContext *s, arg_rpr_esz *a) |
3148 | { | |
3149 | if (!dc_isar_feature(aa64_sve2, s)) { | |
3150 | return false; | |
3151 | } | |
3152 | if (sve_access_check(s)) { | |
3153 | gen_gvec_ool_zzzp(s, gen_helper_sve_splice, | |
3154 | a->rd, a->rn, (a->rn + 1) % 32, a->pg, a->esz); | |
3155 | } | |
3156 | return true; | |
3157 | } | |
3158 | ||
757f9cff RH |
3159 | /* |
3160 | *** SVE Integer Compare - Vectors Group | |
3161 | */ | |
3162 | ||
3163 | static bool do_ppzz_flags(DisasContext *s, arg_rprr_esz *a, | |
3164 | gen_helper_gvec_flags_4 *gen_fn) | |
3165 | { | |
3166 | TCGv_ptr pd, zn, zm, pg; | |
3167 | unsigned vsz; | |
3168 | TCGv_i32 t; | |
3169 | ||
3170 | if (gen_fn == NULL) { | |
3171 | return false; | |
3172 | } | |
3173 | if (!sve_access_check(s)) { | |
3174 | return true; | |
3175 | } | |
3176 | ||
3177 | vsz = vec_full_reg_size(s); | |
392acacc | 3178 | t = tcg_temp_new_i32(); |
757f9cff RH |
3179 | pd = tcg_temp_new_ptr(); |
3180 | zn = tcg_temp_new_ptr(); | |
3181 | zm = tcg_temp_new_ptr(); | |
3182 | pg = tcg_temp_new_ptr(); | |
3183 | ||
3184 | tcg_gen_addi_ptr(pd, cpu_env, pred_full_reg_offset(s, a->rd)); | |
3185 | tcg_gen_addi_ptr(zn, cpu_env, vec_full_reg_offset(s, a->rn)); | |
3186 | tcg_gen_addi_ptr(zm, cpu_env, vec_full_reg_offset(s, a->rm)); | |
3187 | tcg_gen_addi_ptr(pg, cpu_env, pred_full_reg_offset(s, a->pg)); | |
3188 | ||
392acacc | 3189 | gen_fn(t, pd, zn, zm, pg, tcg_constant_i32(simd_desc(vsz, vsz, 0))); |
757f9cff RH |
3190 | |
3191 | tcg_temp_free_ptr(pd); | |
3192 | tcg_temp_free_ptr(zn); | |
3193 | tcg_temp_free_ptr(zm); | |
3194 | tcg_temp_free_ptr(pg); | |
3195 | ||
3196 | do_pred_flags(t); | |
3197 | ||
3198 | tcg_temp_free_i32(t); | |
3199 | return true; | |
3200 | } | |
3201 | ||
3202 | #define DO_PPZZ(NAME, name) \ | |
3a7be554 | 3203 | static bool trans_##NAME##_ppzz(DisasContext *s, arg_rprr_esz *a) \ |
757f9cff RH |
3204 | { \ |
3205 | static gen_helper_gvec_flags_4 * const fns[4] = { \ | |
3206 | gen_helper_sve_##name##_ppzz_b, gen_helper_sve_##name##_ppzz_h, \ | |
3207 | gen_helper_sve_##name##_ppzz_s, gen_helper_sve_##name##_ppzz_d, \ | |
3208 | }; \ | |
3209 | return do_ppzz_flags(s, a, fns[a->esz]); \ | |
3210 | } | |
3211 | ||
3212 | DO_PPZZ(CMPEQ, cmpeq) | |
3213 | DO_PPZZ(CMPNE, cmpne) | |
3214 | DO_PPZZ(CMPGT, cmpgt) | |
3215 | DO_PPZZ(CMPGE, cmpge) | |
3216 | DO_PPZZ(CMPHI, cmphi) | |
3217 | DO_PPZZ(CMPHS, cmphs) | |
3218 | ||
3219 | #undef DO_PPZZ | |
3220 | ||
3221 | #define DO_PPZW(NAME, name) \ | |
3a7be554 | 3222 | static bool trans_##NAME##_ppzw(DisasContext *s, arg_rprr_esz *a) \ |
757f9cff RH |
3223 | { \ |
3224 | static gen_helper_gvec_flags_4 * const fns[4] = { \ | |
3225 | gen_helper_sve_##name##_ppzw_b, gen_helper_sve_##name##_ppzw_h, \ | |
3226 | gen_helper_sve_##name##_ppzw_s, NULL \ | |
3227 | }; \ | |
3228 | return do_ppzz_flags(s, a, fns[a->esz]); \ | |
3229 | } | |
3230 | ||
3231 | DO_PPZW(CMPEQ, cmpeq) | |
3232 | DO_PPZW(CMPNE, cmpne) | |
3233 | DO_PPZW(CMPGT, cmpgt) | |
3234 | DO_PPZW(CMPGE, cmpge) | |
3235 | DO_PPZW(CMPHI, cmphi) | |
3236 | DO_PPZW(CMPHS, cmphs) | |
3237 | DO_PPZW(CMPLT, cmplt) | |
3238 | DO_PPZW(CMPLE, cmple) | |
3239 | DO_PPZW(CMPLO, cmplo) | |
3240 | DO_PPZW(CMPLS, cmpls) | |
3241 | ||
3242 | #undef DO_PPZW | |
3243 | ||
38cadeba RH |
3244 | /* |
3245 | *** SVE Integer Compare - Immediate Groups | |
3246 | */ | |
3247 | ||
3248 | static bool do_ppzi_flags(DisasContext *s, arg_rpri_esz *a, | |
3249 | gen_helper_gvec_flags_3 *gen_fn) | |
3250 | { | |
3251 | TCGv_ptr pd, zn, pg; | |
3252 | unsigned vsz; | |
3253 | TCGv_i32 t; | |
3254 | ||
3255 | if (gen_fn == NULL) { | |
3256 | return false; | |
3257 | } | |
3258 | if (!sve_access_check(s)) { | |
3259 | return true; | |
3260 | } | |
3261 | ||
3262 | vsz = vec_full_reg_size(s); | |
392acacc | 3263 | t = tcg_temp_new_i32(); |
38cadeba RH |
3264 | pd = tcg_temp_new_ptr(); |
3265 | zn = tcg_temp_new_ptr(); | |
3266 | pg = tcg_temp_new_ptr(); | |
3267 | ||
3268 | tcg_gen_addi_ptr(pd, cpu_env, pred_full_reg_offset(s, a->rd)); | |
3269 | tcg_gen_addi_ptr(zn, cpu_env, vec_full_reg_offset(s, a->rn)); | |
3270 | tcg_gen_addi_ptr(pg, cpu_env, pred_full_reg_offset(s, a->pg)); | |
3271 | ||
392acacc | 3272 | gen_fn(t, pd, zn, pg, tcg_constant_i32(simd_desc(vsz, vsz, a->imm))); |
38cadeba RH |
3273 | |
3274 | tcg_temp_free_ptr(pd); | |
3275 | tcg_temp_free_ptr(zn); | |
3276 | tcg_temp_free_ptr(pg); | |
3277 | ||
3278 | do_pred_flags(t); | |
3279 | ||
3280 | tcg_temp_free_i32(t); | |
3281 | return true; | |
3282 | } | |
3283 | ||
3284 | #define DO_PPZI(NAME, name) \ | |
3a7be554 | 3285 | static bool trans_##NAME##_ppzi(DisasContext *s, arg_rpri_esz *a) \ |
38cadeba RH |
3286 | { \ |
3287 | static gen_helper_gvec_flags_3 * const fns[4] = { \ | |
3288 | gen_helper_sve_##name##_ppzi_b, gen_helper_sve_##name##_ppzi_h, \ | |
3289 | gen_helper_sve_##name##_ppzi_s, gen_helper_sve_##name##_ppzi_d, \ | |
3290 | }; \ | |
3291 | return do_ppzi_flags(s, a, fns[a->esz]); \ | |
3292 | } | |
3293 | ||
3294 | DO_PPZI(CMPEQ, cmpeq) | |
3295 | DO_PPZI(CMPNE, cmpne) | |
3296 | DO_PPZI(CMPGT, cmpgt) | |
3297 | DO_PPZI(CMPGE, cmpge) | |
3298 | DO_PPZI(CMPHI, cmphi) | |
3299 | DO_PPZI(CMPHS, cmphs) | |
3300 | DO_PPZI(CMPLT, cmplt) | |
3301 | DO_PPZI(CMPLE, cmple) | |
3302 | DO_PPZI(CMPLO, cmplo) | |
3303 | DO_PPZI(CMPLS, cmpls) | |
3304 | ||
3305 | #undef DO_PPZI | |
3306 | ||
35da316f RH |
3307 | /* |
3308 | *** SVE Partition Break Group | |
3309 | */ | |
3310 | ||
3311 | static bool do_brk3(DisasContext *s, arg_rprr_s *a, | |
3312 | gen_helper_gvec_4 *fn, gen_helper_gvec_flags_4 *fn_s) | |
3313 | { | |
3314 | if (!sve_access_check(s)) { | |
3315 | return true; | |
3316 | } | |
3317 | ||
3318 | unsigned vsz = pred_full_reg_size(s); | |
3319 | ||
3320 | /* Predicate sizes may be smaller and cannot use simd_desc. */ | |
3321 | TCGv_ptr d = tcg_temp_new_ptr(); | |
3322 | TCGv_ptr n = tcg_temp_new_ptr(); | |
3323 | TCGv_ptr m = tcg_temp_new_ptr(); | |
3324 | TCGv_ptr g = tcg_temp_new_ptr(); | |
93418f1c | 3325 | TCGv_i32 desc = tcg_constant_i32(FIELD_DP32(0, PREDDESC, OPRSZ, vsz)); |
35da316f RH |
3326 | |
3327 | tcg_gen_addi_ptr(d, cpu_env, pred_full_reg_offset(s, a->rd)); | |
3328 | tcg_gen_addi_ptr(n, cpu_env, pred_full_reg_offset(s, a->rn)); | |
3329 | tcg_gen_addi_ptr(m, cpu_env, pred_full_reg_offset(s, a->rm)); | |
3330 | tcg_gen_addi_ptr(g, cpu_env, pred_full_reg_offset(s, a->pg)); | |
3331 | ||
3332 | if (a->s) { | |
93418f1c RH |
3333 | TCGv_i32 t = tcg_temp_new_i32(); |
3334 | fn_s(t, d, n, m, g, desc); | |
35da316f | 3335 | do_pred_flags(t); |
93418f1c | 3336 | tcg_temp_free_i32(t); |
35da316f | 3337 | } else { |
93418f1c | 3338 | fn(d, n, m, g, desc); |
35da316f RH |
3339 | } |
3340 | tcg_temp_free_ptr(d); | |
3341 | tcg_temp_free_ptr(n); | |
3342 | tcg_temp_free_ptr(m); | |
3343 | tcg_temp_free_ptr(g); | |
35da316f RH |
3344 | return true; |
3345 | } | |
3346 | ||
3347 | static bool do_brk2(DisasContext *s, arg_rpr_s *a, | |
3348 | gen_helper_gvec_3 *fn, gen_helper_gvec_flags_3 *fn_s) | |
3349 | { | |
3350 | if (!sve_access_check(s)) { | |
3351 | return true; | |
3352 | } | |
3353 | ||
3354 | unsigned vsz = pred_full_reg_size(s); | |
3355 | ||
3356 | /* Predicate sizes may be smaller and cannot use simd_desc. */ | |
3357 | TCGv_ptr d = tcg_temp_new_ptr(); | |
3358 | TCGv_ptr n = tcg_temp_new_ptr(); | |
3359 | TCGv_ptr g = tcg_temp_new_ptr(); | |
93418f1c | 3360 | TCGv_i32 desc = tcg_constant_i32(FIELD_DP32(0, PREDDESC, OPRSZ, vsz)); |
35da316f RH |
3361 | |
3362 | tcg_gen_addi_ptr(d, cpu_env, pred_full_reg_offset(s, a->rd)); | |
3363 | tcg_gen_addi_ptr(n, cpu_env, pred_full_reg_offset(s, a->rn)); | |
3364 | tcg_gen_addi_ptr(g, cpu_env, pred_full_reg_offset(s, a->pg)); | |
3365 | ||
3366 | if (a->s) { | |
93418f1c RH |
3367 | TCGv_i32 t = tcg_temp_new_i32(); |
3368 | fn_s(t, d, n, g, desc); | |
35da316f | 3369 | do_pred_flags(t); |
93418f1c | 3370 | tcg_temp_free_i32(t); |
35da316f | 3371 | } else { |
93418f1c | 3372 | fn(d, n, g, desc); |
35da316f RH |
3373 | } |
3374 | tcg_temp_free_ptr(d); | |
3375 | tcg_temp_free_ptr(n); | |
3376 | tcg_temp_free_ptr(g); | |
35da316f RH |
3377 | return true; |
3378 | } | |
3379 | ||
3a7be554 | 3380 | static bool trans_BRKPA(DisasContext *s, arg_rprr_s *a) |
35da316f RH |
3381 | { |
3382 | return do_brk3(s, a, gen_helper_sve_brkpa, gen_helper_sve_brkpas); | |
3383 | } | |
3384 | ||
3a7be554 | 3385 | static bool trans_BRKPB(DisasContext *s, arg_rprr_s *a) |
35da316f RH |
3386 | { |
3387 | return do_brk3(s, a, gen_helper_sve_brkpb, gen_helper_sve_brkpbs); | |
3388 | } | |
3389 | ||
3a7be554 | 3390 | static bool trans_BRKA_m(DisasContext *s, arg_rpr_s *a) |
35da316f RH |
3391 | { |
3392 | return do_brk2(s, a, gen_helper_sve_brka_m, gen_helper_sve_brkas_m); | |
3393 | } | |
3394 | ||
3a7be554 | 3395 | static bool trans_BRKB_m(DisasContext *s, arg_rpr_s *a) |
35da316f RH |
3396 | { |
3397 | return do_brk2(s, a, gen_helper_sve_brkb_m, gen_helper_sve_brkbs_m); | |
3398 | } | |
3399 | ||
3a7be554 | 3400 | static bool trans_BRKA_z(DisasContext *s, arg_rpr_s *a) |
35da316f RH |
3401 | { |
3402 | return do_brk2(s, a, gen_helper_sve_brka_z, gen_helper_sve_brkas_z); | |
3403 | } | |
3404 | ||
3a7be554 | 3405 | static bool trans_BRKB_z(DisasContext *s, arg_rpr_s *a) |
35da316f RH |
3406 | { |
3407 | return do_brk2(s, a, gen_helper_sve_brkb_z, gen_helper_sve_brkbs_z); | |
3408 | } | |
3409 | ||
3a7be554 | 3410 | static bool trans_BRKN(DisasContext *s, arg_rpr_s *a) |
35da316f RH |
3411 | { |
3412 | return do_brk2(s, a, gen_helper_sve_brkn, gen_helper_sve_brkns); | |
3413 | } | |
3414 | ||
9ee3a611 RH |
3415 | /* |
3416 | *** SVE Predicate Count Group | |
3417 | */ | |
3418 | ||
3419 | static void do_cntp(DisasContext *s, TCGv_i64 val, int esz, int pn, int pg) | |
3420 | { | |
3421 | unsigned psz = pred_full_reg_size(s); | |
3422 | ||
3423 | if (psz <= 8) { | |
3424 | uint64_t psz_mask; | |
3425 | ||
3426 | tcg_gen_ld_i64(val, cpu_env, pred_full_reg_offset(s, pn)); | |
3427 | if (pn != pg) { | |
3428 | TCGv_i64 g = tcg_temp_new_i64(); | |
3429 | tcg_gen_ld_i64(g, cpu_env, pred_full_reg_offset(s, pg)); | |
3430 | tcg_gen_and_i64(val, val, g); | |
3431 | tcg_temp_free_i64(g); | |
3432 | } | |
3433 | ||
3434 | /* Reduce the pred_esz_masks value simply to reduce the | |
3435 | * size of the code generated here. | |
3436 | */ | |
3437 | psz_mask = MAKE_64BIT_MASK(0, psz * 8); | |
3438 | tcg_gen_andi_i64(val, val, pred_esz_masks[esz] & psz_mask); | |
3439 | ||
3440 | tcg_gen_ctpop_i64(val, val); | |
3441 | } else { | |
3442 | TCGv_ptr t_pn = tcg_temp_new_ptr(); | |
3443 | TCGv_ptr t_pg = tcg_temp_new_ptr(); | |
f556a201 | 3444 | unsigned desc = 0; |
9ee3a611 RH |
3445 | TCGv_i32 t_desc; |
3446 | ||
f556a201 RH |
3447 | desc = FIELD_DP32(desc, PREDDESC, OPRSZ, psz); |
3448 | desc = FIELD_DP32(desc, PREDDESC, ESZ, esz); | |
9ee3a611 RH |
3449 | |
3450 | tcg_gen_addi_ptr(t_pn, cpu_env, pred_full_reg_offset(s, pn)); | |
3451 | tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, pg)); | |
3452 | t_desc = tcg_const_i32(desc); | |
3453 | ||
3454 | gen_helper_sve_cntp(val, t_pn, t_pg, t_desc); | |
3455 | tcg_temp_free_ptr(t_pn); | |
3456 | tcg_temp_free_ptr(t_pg); | |
3457 | tcg_temp_free_i32(t_desc); | |
3458 | } | |
3459 | } | |
3460 | ||
3a7be554 | 3461 | static bool trans_CNTP(DisasContext *s, arg_CNTP *a) |
9ee3a611 RH |
3462 | { |
3463 | if (sve_access_check(s)) { | |
3464 | do_cntp(s, cpu_reg(s, a->rd), a->esz, a->rn, a->pg); | |
3465 | } | |
3466 | return true; | |
3467 | } | |
3468 | ||
3a7be554 | 3469 | static bool trans_INCDECP_r(DisasContext *s, arg_incdec_pred *a) |
9ee3a611 RH |
3470 | { |
3471 | if (sve_access_check(s)) { | |
3472 | TCGv_i64 reg = cpu_reg(s, a->rd); | |
3473 | TCGv_i64 val = tcg_temp_new_i64(); | |
3474 | ||
3475 | do_cntp(s, val, a->esz, a->pg, a->pg); | |
3476 | if (a->d) { | |
3477 | tcg_gen_sub_i64(reg, reg, val); | |
3478 | } else { | |
3479 | tcg_gen_add_i64(reg, reg, val); | |
3480 | } | |
3481 | tcg_temp_free_i64(val); | |
3482 | } | |
3483 | return true; | |
3484 | } | |
3485 | ||
3a7be554 | 3486 | static bool trans_INCDECP_z(DisasContext *s, arg_incdec2_pred *a) |
9ee3a611 RH |
3487 | { |
3488 | if (a->esz == 0) { | |
3489 | return false; | |
3490 | } | |
3491 | if (sve_access_check(s)) { | |
3492 | unsigned vsz = vec_full_reg_size(s); | |
3493 | TCGv_i64 val = tcg_temp_new_i64(); | |
3494 | GVecGen2sFn *gvec_fn = a->d ? tcg_gen_gvec_subs : tcg_gen_gvec_adds; | |
3495 | ||
3496 | do_cntp(s, val, a->esz, a->pg, a->pg); | |
3497 | gvec_fn(a->esz, vec_full_reg_offset(s, a->rd), | |
3498 | vec_full_reg_offset(s, a->rn), val, vsz, vsz); | |
3499 | } | |
3500 | return true; | |
3501 | } | |
3502 | ||
3a7be554 | 3503 | static bool trans_SINCDECP_r_32(DisasContext *s, arg_incdec_pred *a) |
9ee3a611 RH |
3504 | { |
3505 | if (sve_access_check(s)) { | |
3506 | TCGv_i64 reg = cpu_reg(s, a->rd); | |
3507 | TCGv_i64 val = tcg_temp_new_i64(); | |
3508 | ||
3509 | do_cntp(s, val, a->esz, a->pg, a->pg); | |
3510 | do_sat_addsub_32(reg, val, a->u, a->d); | |
3511 | } | |
3512 | return true; | |
3513 | } | |
3514 | ||
3a7be554 | 3515 | static bool trans_SINCDECP_r_64(DisasContext *s, arg_incdec_pred *a) |
9ee3a611 RH |
3516 | { |
3517 | if (sve_access_check(s)) { | |
3518 | TCGv_i64 reg = cpu_reg(s, a->rd); | |
3519 | TCGv_i64 val = tcg_temp_new_i64(); | |
3520 | ||
3521 | do_cntp(s, val, a->esz, a->pg, a->pg); | |
3522 | do_sat_addsub_64(reg, val, a->u, a->d); | |
3523 | } | |
3524 | return true; | |
3525 | } | |
3526 | ||
3a7be554 | 3527 | static bool trans_SINCDECP_z(DisasContext *s, arg_incdec2_pred *a) |
9ee3a611 RH |
3528 | { |
3529 | if (a->esz == 0) { | |
3530 | return false; | |
3531 | } | |
3532 | if (sve_access_check(s)) { | |
3533 | TCGv_i64 val = tcg_temp_new_i64(); | |
3534 | do_cntp(s, val, a->esz, a->pg, a->pg); | |
3535 | do_sat_addsub_vec(s, a->esz, a->rd, a->rn, val, a->u, a->d); | |
3536 | } | |
3537 | return true; | |
3538 | } | |
3539 | ||
caf1cefc RH |
3540 | /* |
3541 | *** SVE Integer Compare Scalars Group | |
3542 | */ | |
3543 | ||
3a7be554 | 3544 | static bool trans_CTERM(DisasContext *s, arg_CTERM *a) |
caf1cefc RH |
3545 | { |
3546 | if (!sve_access_check(s)) { | |
3547 | return true; | |
3548 | } | |
3549 | ||
3550 | TCGCond cond = (a->ne ? TCG_COND_NE : TCG_COND_EQ); | |
3551 | TCGv_i64 rn = read_cpu_reg(s, a->rn, a->sf); | |
3552 | TCGv_i64 rm = read_cpu_reg(s, a->rm, a->sf); | |
3553 | TCGv_i64 cmp = tcg_temp_new_i64(); | |
3554 | ||
3555 | tcg_gen_setcond_i64(cond, cmp, rn, rm); | |
3556 | tcg_gen_extrl_i64_i32(cpu_NF, cmp); | |
3557 | tcg_temp_free_i64(cmp); | |
3558 | ||
3559 | /* VF = !NF & !CF. */ | |
3560 | tcg_gen_xori_i32(cpu_VF, cpu_NF, 1); | |
3561 | tcg_gen_andc_i32(cpu_VF, cpu_VF, cpu_CF); | |
3562 | ||
3563 | /* Both NF and VF actually look at bit 31. */ | |
3564 | tcg_gen_neg_i32(cpu_NF, cpu_NF); | |
3565 | tcg_gen_neg_i32(cpu_VF, cpu_VF); | |
3566 | return true; | |
3567 | } | |
3568 | ||
3a7be554 | 3569 | static bool trans_WHILE(DisasContext *s, arg_WHILE *a) |
caf1cefc | 3570 | { |
bbd0968c | 3571 | TCGv_i64 op0, op1, t0, t1, tmax; |
4481bbf2 | 3572 | TCGv_i32 t2; |
caf1cefc | 3573 | TCGv_ptr ptr; |
e610906c RH |
3574 | unsigned vsz = vec_full_reg_size(s); |
3575 | unsigned desc = 0; | |
caf1cefc | 3576 | TCGCond cond; |
34688dbc RH |
3577 | uint64_t maxval; |
3578 | /* Note that GE/HS has a->eq == 0 and GT/HI has a->eq == 1. */ | |
3579 | bool eq = a->eq == a->lt; | |
caf1cefc | 3580 | |
34688dbc RH |
3581 | /* The greater-than conditions are all SVE2. */ |
3582 | if (!a->lt && !dc_isar_feature(aa64_sve2, s)) { | |
3583 | return false; | |
3584 | } | |
bbd0968c RH |
3585 | if (!sve_access_check(s)) { |
3586 | return true; | |
3587 | } | |
3588 | ||
3589 | op0 = read_cpu_reg(s, a->rn, 1); | |
3590 | op1 = read_cpu_reg(s, a->rm, 1); | |
3591 | ||
caf1cefc RH |
3592 | if (!a->sf) { |
3593 | if (a->u) { | |
3594 | tcg_gen_ext32u_i64(op0, op0); | |
3595 | tcg_gen_ext32u_i64(op1, op1); | |
3596 | } else { | |
3597 | tcg_gen_ext32s_i64(op0, op0); | |
3598 | tcg_gen_ext32s_i64(op1, op1); | |
3599 | } | |
3600 | } | |
3601 | ||
3602 | /* For the helper, compress the different conditions into a computation | |
3603 | * of how many iterations for which the condition is true. | |
caf1cefc | 3604 | */ |
bbd0968c RH |
3605 | t0 = tcg_temp_new_i64(); |
3606 | t1 = tcg_temp_new_i64(); | |
34688dbc RH |
3607 | |
3608 | if (a->lt) { | |
3609 | tcg_gen_sub_i64(t0, op1, op0); | |
3610 | if (a->u) { | |
3611 | maxval = a->sf ? UINT64_MAX : UINT32_MAX; | |
3612 | cond = eq ? TCG_COND_LEU : TCG_COND_LTU; | |
3613 | } else { | |
3614 | maxval = a->sf ? INT64_MAX : INT32_MAX; | |
3615 | cond = eq ? TCG_COND_LE : TCG_COND_LT; | |
3616 | } | |
3617 | } else { | |
3618 | tcg_gen_sub_i64(t0, op0, op1); | |
3619 | if (a->u) { | |
3620 | maxval = 0; | |
3621 | cond = eq ? TCG_COND_GEU : TCG_COND_GTU; | |
3622 | } else { | |
3623 | maxval = a->sf ? INT64_MIN : INT32_MIN; | |
3624 | cond = eq ? TCG_COND_GE : TCG_COND_GT; | |
3625 | } | |
3626 | } | |
caf1cefc | 3627 | |
4481bbf2 | 3628 | tmax = tcg_constant_i64(vsz >> a->esz); |
34688dbc | 3629 | if (eq) { |
caf1cefc RH |
3630 | /* Equality means one more iteration. */ |
3631 | tcg_gen_addi_i64(t0, t0, 1); | |
bbd0968c | 3632 | |
34688dbc RH |
3633 | /* |
3634 | * For the less-than while, if op1 is maxval (and the only time | |
3635 | * the addition above could overflow), then we produce an all-true | |
3636 | * predicate by setting the count to the vector length. This is | |
3637 | * because the pseudocode is described as an increment + compare | |
3638 | * loop, and the maximum integer would always compare true. | |
3639 | * Similarly, the greater-than while has the same issue with the | |
3640 | * minimum integer due to the decrement + compare loop. | |
bbd0968c | 3641 | */ |
34688dbc | 3642 | tcg_gen_movi_i64(t1, maxval); |
bbd0968c | 3643 | tcg_gen_movcond_i64(TCG_COND_EQ, t0, op1, t1, tmax, t0); |
caf1cefc RH |
3644 | } |
3645 | ||
bbd0968c RH |
3646 | /* Bound to the maximum. */ |
3647 | tcg_gen_umin_i64(t0, t0, tmax); | |
bbd0968c RH |
3648 | |
3649 | /* Set the count to zero if the condition is false. */ | |
caf1cefc RH |
3650 | tcg_gen_movi_i64(t1, 0); |
3651 | tcg_gen_movcond_i64(cond, t0, op0, op1, t0, t1); | |
bbd0968c | 3652 | tcg_temp_free_i64(t1); |
caf1cefc | 3653 | |
bbd0968c | 3654 | /* Since we're bounded, pass as a 32-bit type. */ |
caf1cefc RH |
3655 | t2 = tcg_temp_new_i32(); |
3656 | tcg_gen_extrl_i64_i32(t2, t0); | |
3657 | tcg_temp_free_i64(t0); | |
bbd0968c RH |
3658 | |
3659 | /* Scale elements to bits. */ | |
3660 | tcg_gen_shli_i32(t2, t2, a->esz); | |
caf1cefc | 3661 | |
e610906c RH |
3662 | desc = FIELD_DP32(desc, PREDDESC, OPRSZ, vsz / 8); |
3663 | desc = FIELD_DP32(desc, PREDDESC, ESZ, a->esz); | |
caf1cefc RH |
3664 | |
3665 | ptr = tcg_temp_new_ptr(); | |
3666 | tcg_gen_addi_ptr(ptr, cpu_env, pred_full_reg_offset(s, a->rd)); | |
3667 | ||
34688dbc | 3668 | if (a->lt) { |
4481bbf2 | 3669 | gen_helper_sve_whilel(t2, ptr, t2, tcg_constant_i32(desc)); |
34688dbc | 3670 | } else { |
4481bbf2 | 3671 | gen_helper_sve_whileg(t2, ptr, t2, tcg_constant_i32(desc)); |
34688dbc | 3672 | } |
caf1cefc RH |
3673 | do_pred_flags(t2); |
3674 | ||
3675 | tcg_temp_free_ptr(ptr); | |
3676 | tcg_temp_free_i32(t2); | |
caf1cefc RH |
3677 | return true; |
3678 | } | |
3679 | ||
14f6dad1 RH |
3680 | static bool trans_WHILE_ptr(DisasContext *s, arg_WHILE_ptr *a) |
3681 | { | |
3682 | TCGv_i64 op0, op1, diff, t1, tmax; | |
4481bbf2 | 3683 | TCGv_i32 t2; |
14f6dad1 RH |
3684 | TCGv_ptr ptr; |
3685 | unsigned vsz = vec_full_reg_size(s); | |
3686 | unsigned desc = 0; | |
3687 | ||
3688 | if (!dc_isar_feature(aa64_sve2, s)) { | |
3689 | return false; | |
3690 | } | |
3691 | if (!sve_access_check(s)) { | |
3692 | return true; | |
3693 | } | |
3694 | ||
3695 | op0 = read_cpu_reg(s, a->rn, 1); | |
3696 | op1 = read_cpu_reg(s, a->rm, 1); | |
3697 | ||
4481bbf2 | 3698 | tmax = tcg_constant_i64(vsz); |
14f6dad1 RH |
3699 | diff = tcg_temp_new_i64(); |
3700 | ||
3701 | if (a->rw) { | |
3702 | /* WHILERW */ | |
3703 | /* diff = abs(op1 - op0), noting that op0/1 are unsigned. */ | |
3704 | t1 = tcg_temp_new_i64(); | |
3705 | tcg_gen_sub_i64(diff, op0, op1); | |
3706 | tcg_gen_sub_i64(t1, op1, op0); | |
3707 | tcg_gen_movcond_i64(TCG_COND_GEU, diff, op0, op1, diff, t1); | |
3708 | tcg_temp_free_i64(t1); | |
3709 | /* Round down to a multiple of ESIZE. */ | |
3710 | tcg_gen_andi_i64(diff, diff, -1 << a->esz); | |
3711 | /* If op1 == op0, diff == 0, and the condition is always true. */ | |
3712 | tcg_gen_movcond_i64(TCG_COND_EQ, diff, op0, op1, tmax, diff); | |
3713 | } else { | |
3714 | /* WHILEWR */ | |
3715 | tcg_gen_sub_i64(diff, op1, op0); | |
3716 | /* Round down to a multiple of ESIZE. */ | |
3717 | tcg_gen_andi_i64(diff, diff, -1 << a->esz); | |
3718 | /* If op0 >= op1, diff <= 0, the condition is always true. */ | |
3719 | tcg_gen_movcond_i64(TCG_COND_GEU, diff, op0, op1, tmax, diff); | |
3720 | } | |
3721 | ||
3722 | /* Bound to the maximum. */ | |
3723 | tcg_gen_umin_i64(diff, diff, tmax); | |
14f6dad1 RH |
3724 | |
3725 | /* Since we're bounded, pass as a 32-bit type. */ | |
3726 | t2 = tcg_temp_new_i32(); | |
3727 | tcg_gen_extrl_i64_i32(t2, diff); | |
3728 | tcg_temp_free_i64(diff); | |
3729 | ||
3730 | desc = FIELD_DP32(desc, PREDDESC, OPRSZ, vsz / 8); | |
3731 | desc = FIELD_DP32(desc, PREDDESC, ESZ, a->esz); | |
14f6dad1 RH |
3732 | |
3733 | ptr = tcg_temp_new_ptr(); | |
3734 | tcg_gen_addi_ptr(ptr, cpu_env, pred_full_reg_offset(s, a->rd)); | |
3735 | ||
4481bbf2 | 3736 | gen_helper_sve_whilel(t2, ptr, t2, tcg_constant_i32(desc)); |
14f6dad1 RH |
3737 | do_pred_flags(t2); |
3738 | ||
3739 | tcg_temp_free_ptr(ptr); | |
3740 | tcg_temp_free_i32(t2); | |
14f6dad1 RH |
3741 | return true; |
3742 | } | |
3743 | ||
ed491961 RH |
3744 | /* |
3745 | *** SVE Integer Wide Immediate - Unpredicated Group | |
3746 | */ | |
3747 | ||
3a7be554 | 3748 | static bool trans_FDUP(DisasContext *s, arg_FDUP *a) |
ed491961 RH |
3749 | { |
3750 | if (a->esz == 0) { | |
3751 | return false; | |
3752 | } | |
3753 | if (sve_access_check(s)) { | |
3754 | unsigned vsz = vec_full_reg_size(s); | |
3755 | int dofs = vec_full_reg_offset(s, a->rd); | |
3756 | uint64_t imm; | |
3757 | ||
3758 | /* Decode the VFP immediate. */ | |
3759 | imm = vfp_expand_imm(a->esz, a->imm); | |
8711e71f | 3760 | tcg_gen_gvec_dup_imm(a->esz, dofs, vsz, vsz, imm); |
ed491961 RH |
3761 | } |
3762 | return true; | |
3763 | } | |
3764 | ||
3a7be554 | 3765 | static bool trans_DUP_i(DisasContext *s, arg_DUP_i *a) |
ed491961 | 3766 | { |
3a7be554 | 3767 | if (a->esz == 0 && extract32(s->insn, 13, 1)) { |
ed491961 RH |
3768 | return false; |
3769 | } | |
3770 | if (sve_access_check(s)) { | |
3771 | unsigned vsz = vec_full_reg_size(s); | |
3772 | int dofs = vec_full_reg_offset(s, a->rd); | |
3773 | ||
8711e71f | 3774 | tcg_gen_gvec_dup_imm(a->esz, dofs, vsz, vsz, a->imm); |
ed491961 RH |
3775 | } |
3776 | return true; | |
3777 | } | |
3778 | ||
3a7be554 | 3779 | static bool trans_ADD_zzi(DisasContext *s, arg_rri_esz *a) |
6e6a157d | 3780 | { |
3a7be554 | 3781 | if (a->esz == 0 && extract32(s->insn, 13, 1)) { |
6e6a157d RH |
3782 | return false; |
3783 | } | |
3784 | if (sve_access_check(s)) { | |
3785 | unsigned vsz = vec_full_reg_size(s); | |
3786 | tcg_gen_gvec_addi(a->esz, vec_full_reg_offset(s, a->rd), | |
3787 | vec_full_reg_offset(s, a->rn), a->imm, vsz, vsz); | |
3788 | } | |
3789 | return true; | |
3790 | } | |
3791 | ||
3a7be554 | 3792 | static bool trans_SUB_zzi(DisasContext *s, arg_rri_esz *a) |
6e6a157d RH |
3793 | { |
3794 | a->imm = -a->imm; | |
3a7be554 | 3795 | return trans_ADD_zzi(s, a); |
6e6a157d RH |
3796 | } |
3797 | ||
3a7be554 | 3798 | static bool trans_SUBR_zzi(DisasContext *s, arg_rri_esz *a) |
6e6a157d | 3799 | { |
53229a77 | 3800 | static const TCGOpcode vecop_list[] = { INDEX_op_sub_vec, 0 }; |
6e6a157d RH |
3801 | static const GVecGen2s op[4] = { |
3802 | { .fni8 = tcg_gen_vec_sub8_i64, | |
3803 | .fniv = tcg_gen_sub_vec, | |
3804 | .fno = gen_helper_sve_subri_b, | |
53229a77 | 3805 | .opt_opc = vecop_list, |
6e6a157d RH |
3806 | .vece = MO_8, |
3807 | .scalar_first = true }, | |
3808 | { .fni8 = tcg_gen_vec_sub16_i64, | |
3809 | .fniv = tcg_gen_sub_vec, | |
3810 | .fno = gen_helper_sve_subri_h, | |
53229a77 | 3811 | .opt_opc = vecop_list, |
6e6a157d RH |
3812 | .vece = MO_16, |
3813 | .scalar_first = true }, | |
3814 | { .fni4 = tcg_gen_sub_i32, | |
3815 | .fniv = tcg_gen_sub_vec, | |
3816 | .fno = gen_helper_sve_subri_s, | |
53229a77 | 3817 | .opt_opc = vecop_list, |
6e6a157d RH |
3818 | .vece = MO_32, |
3819 | .scalar_first = true }, | |
3820 | { .fni8 = tcg_gen_sub_i64, | |
3821 | .fniv = tcg_gen_sub_vec, | |
3822 | .fno = gen_helper_sve_subri_d, | |
53229a77 | 3823 | .opt_opc = vecop_list, |
6e6a157d RH |
3824 | .prefer_i64 = TCG_TARGET_REG_BITS == 64, |
3825 | .vece = MO_64, | |
3826 | .scalar_first = true } | |
3827 | }; | |
3828 | ||
3a7be554 | 3829 | if (a->esz == 0 && extract32(s->insn, 13, 1)) { |
6e6a157d RH |
3830 | return false; |
3831 | } | |
3832 | if (sve_access_check(s)) { | |
3833 | unsigned vsz = vec_full_reg_size(s); | |
6e6a157d RH |
3834 | tcg_gen_gvec_2s(vec_full_reg_offset(s, a->rd), |
3835 | vec_full_reg_offset(s, a->rn), | |
9fff3fcc | 3836 | vsz, vsz, tcg_constant_i64(a->imm), &op[a->esz]); |
6e6a157d RH |
3837 | } |
3838 | return true; | |
3839 | } | |
3840 | ||
3a7be554 | 3841 | static bool trans_MUL_zzi(DisasContext *s, arg_rri_esz *a) |
6e6a157d RH |
3842 | { |
3843 | if (sve_access_check(s)) { | |
3844 | unsigned vsz = vec_full_reg_size(s); | |
3845 | tcg_gen_gvec_muli(a->esz, vec_full_reg_offset(s, a->rd), | |
3846 | vec_full_reg_offset(s, a->rn), a->imm, vsz, vsz); | |
3847 | } | |
3848 | return true; | |
3849 | } | |
3850 | ||
3a7be554 | 3851 | static bool do_zzi_sat(DisasContext *s, arg_rri_esz *a, bool u, bool d) |
6e6a157d | 3852 | { |
3a7be554 | 3853 | if (a->esz == 0 && extract32(s->insn, 13, 1)) { |
6e6a157d RH |
3854 | return false; |
3855 | } | |
3856 | if (sve_access_check(s)) { | |
138a1f7b RH |
3857 | do_sat_addsub_vec(s, a->esz, a->rd, a->rn, |
3858 | tcg_constant_i64(a->imm), u, d); | |
6e6a157d RH |
3859 | } |
3860 | return true; | |
3861 | } | |
3862 | ||
3a7be554 | 3863 | static bool trans_SQADD_zzi(DisasContext *s, arg_rri_esz *a) |
6e6a157d | 3864 | { |
3a7be554 | 3865 | return do_zzi_sat(s, a, false, false); |
6e6a157d RH |
3866 | } |
3867 | ||
3a7be554 | 3868 | static bool trans_UQADD_zzi(DisasContext *s, arg_rri_esz *a) |
6e6a157d | 3869 | { |
3a7be554 | 3870 | return do_zzi_sat(s, a, true, false); |
6e6a157d RH |
3871 | } |
3872 | ||
3a7be554 | 3873 | static bool trans_SQSUB_zzi(DisasContext *s, arg_rri_esz *a) |
6e6a157d | 3874 | { |
3a7be554 | 3875 | return do_zzi_sat(s, a, false, true); |
6e6a157d RH |
3876 | } |
3877 | ||
3a7be554 | 3878 | static bool trans_UQSUB_zzi(DisasContext *s, arg_rri_esz *a) |
6e6a157d | 3879 | { |
3a7be554 | 3880 | return do_zzi_sat(s, a, true, true); |
6e6a157d RH |
3881 | } |
3882 | ||
3883 | static bool do_zzi_ool(DisasContext *s, arg_rri_esz *a, gen_helper_gvec_2i *fn) | |
3884 | { | |
3885 | if (sve_access_check(s)) { | |
3886 | unsigned vsz = vec_full_reg_size(s); | |
6e6a157d RH |
3887 | tcg_gen_gvec_2i_ool(vec_full_reg_offset(s, a->rd), |
3888 | vec_full_reg_offset(s, a->rn), | |
138a1f7b | 3889 | tcg_constant_i64(a->imm), vsz, vsz, 0, fn); |
6e6a157d RH |
3890 | } |
3891 | return true; | |
3892 | } | |
3893 | ||
3894 | #define DO_ZZI(NAME, name) \ | |
3a7be554 | 3895 | static bool trans_##NAME##_zzi(DisasContext *s, arg_rri_esz *a) \ |
6e6a157d RH |
3896 | { \ |
3897 | static gen_helper_gvec_2i * const fns[4] = { \ | |
3898 | gen_helper_sve_##name##i_b, gen_helper_sve_##name##i_h, \ | |
3899 | gen_helper_sve_##name##i_s, gen_helper_sve_##name##i_d, \ | |
3900 | }; \ | |
3901 | return do_zzi_ool(s, a, fns[a->esz]); \ | |
3902 | } | |
3903 | ||
3904 | DO_ZZI(SMAX, smax) | |
3905 | DO_ZZI(UMAX, umax) | |
3906 | DO_ZZI(SMIN, smin) | |
3907 | DO_ZZI(UMIN, umin) | |
3908 | ||
3909 | #undef DO_ZZI | |
3910 | ||
bc2bd697 | 3911 | static bool trans_DOT_zzzz(DisasContext *s, arg_DOT_zzzz *a) |
d730ecaa | 3912 | { |
bc2bd697 | 3913 | static gen_helper_gvec_4 * const fns[2][2] = { |
d730ecaa RH |
3914 | { gen_helper_gvec_sdot_b, gen_helper_gvec_sdot_h }, |
3915 | { gen_helper_gvec_udot_b, gen_helper_gvec_udot_h } | |
3916 | }; | |
3917 | ||
3918 | if (sve_access_check(s)) { | |
bc2bd697 | 3919 | gen_gvec_ool_zzzz(s, fns[a->u][a->sz], a->rd, a->rn, a->rm, a->ra, 0); |
d730ecaa RH |
3920 | } |
3921 | return true; | |
3922 | } | |
3923 | ||
814d4c52 RH |
3924 | /* |
3925 | * SVE Multiply - Indexed | |
3926 | */ | |
3927 | ||
0a82d963 RH |
3928 | static bool do_zzxz_ool(DisasContext *s, arg_rrxr_esz *a, |
3929 | gen_helper_gvec_4 *fn) | |
16fcfdc7 | 3930 | { |
0a82d963 RH |
3931 | if (fn == NULL) { |
3932 | return false; | |
3933 | } | |
16fcfdc7 | 3934 | if (sve_access_check(s)) { |
0a82d963 | 3935 | gen_gvec_ool_zzzz(s, fn, a->rd, a->rn, a->rm, a->ra, a->index); |
16fcfdc7 RH |
3936 | } |
3937 | return true; | |
3938 | } | |
3939 | ||
0a82d963 RH |
3940 | #define DO_RRXR(NAME, FUNC) \ |
3941 | static bool NAME(DisasContext *s, arg_rrxr_esz *a) \ | |
3942 | { return do_zzxz_ool(s, a, FUNC); } | |
3943 | ||
3944 | DO_RRXR(trans_SDOT_zzxw_s, gen_helper_gvec_sdot_idx_b) | |
3945 | DO_RRXR(trans_SDOT_zzxw_d, gen_helper_gvec_sdot_idx_h) | |
3946 | DO_RRXR(trans_UDOT_zzxw_s, gen_helper_gvec_udot_idx_b) | |
3947 | DO_RRXR(trans_UDOT_zzxw_d, gen_helper_gvec_udot_idx_h) | |
3948 | ||
2867039a RH |
3949 | static bool trans_SUDOT_zzxw_s(DisasContext *s, arg_rrxr_esz *a) |
3950 | { | |
3951 | if (!dc_isar_feature(aa64_sve_i8mm, s)) { | |
3952 | return false; | |
3953 | } | |
3954 | return do_zzxz_ool(s, a, gen_helper_gvec_sudot_idx_b); | |
3955 | } | |
3956 | ||
3957 | static bool trans_USDOT_zzxw_s(DisasContext *s, arg_rrxr_esz *a) | |
3958 | { | |
3959 | if (!dc_isar_feature(aa64_sve_i8mm, s)) { | |
3960 | return false; | |
3961 | } | |
3962 | return do_zzxz_ool(s, a, gen_helper_gvec_usdot_idx_b); | |
3963 | } | |
3964 | ||
0a82d963 | 3965 | #undef DO_RRXR |
16fcfdc7 | 3966 | |
814d4c52 RH |
3967 | static bool do_sve2_zzz_data(DisasContext *s, int rd, int rn, int rm, int data, |
3968 | gen_helper_gvec_3 *fn) | |
3969 | { | |
3970 | if (fn == NULL || !dc_isar_feature(aa64_sve2, s)) { | |
3971 | return false; | |
3972 | } | |
3973 | if (sve_access_check(s)) { | |
3974 | unsigned vsz = vec_full_reg_size(s); | |
3975 | tcg_gen_gvec_3_ool(vec_full_reg_offset(s, rd), | |
3976 | vec_full_reg_offset(s, rn), | |
3977 | vec_full_reg_offset(s, rm), | |
3978 | vsz, vsz, data, fn); | |
3979 | } | |
3980 | return true; | |
3981 | } | |
3982 | ||
3983 | #define DO_SVE2_RRX(NAME, FUNC) \ | |
3984 | static bool NAME(DisasContext *s, arg_rrx_esz *a) \ | |
3985 | { return do_sve2_zzz_data(s, a->rd, a->rn, a->rm, a->index, FUNC); } | |
3986 | ||
3987 | DO_SVE2_RRX(trans_MUL_zzx_h, gen_helper_gvec_mul_idx_h) | |
3988 | DO_SVE2_RRX(trans_MUL_zzx_s, gen_helper_gvec_mul_idx_s) | |
3989 | DO_SVE2_RRX(trans_MUL_zzx_d, gen_helper_gvec_mul_idx_d) | |
3990 | ||
1aee2d70 RH |
3991 | DO_SVE2_RRX(trans_SQDMULH_zzx_h, gen_helper_sve2_sqdmulh_idx_h) |
3992 | DO_SVE2_RRX(trans_SQDMULH_zzx_s, gen_helper_sve2_sqdmulh_idx_s) | |
3993 | DO_SVE2_RRX(trans_SQDMULH_zzx_d, gen_helper_sve2_sqdmulh_idx_d) | |
3994 | ||
3995 | DO_SVE2_RRX(trans_SQRDMULH_zzx_h, gen_helper_sve2_sqrdmulh_idx_h) | |
3996 | DO_SVE2_RRX(trans_SQRDMULH_zzx_s, gen_helper_sve2_sqrdmulh_idx_s) | |
3997 | DO_SVE2_RRX(trans_SQRDMULH_zzx_d, gen_helper_sve2_sqrdmulh_idx_d) | |
3998 | ||
814d4c52 RH |
3999 | #undef DO_SVE2_RRX |
4000 | ||
b95f5eeb RH |
4001 | #define DO_SVE2_RRX_TB(NAME, FUNC, TOP) \ |
4002 | static bool NAME(DisasContext *s, arg_rrx_esz *a) \ | |
4003 | { \ | |
4004 | return do_sve2_zzz_data(s, a->rd, a->rn, a->rm, \ | |
4005 | (a->index << 1) | TOP, FUNC); \ | |
4006 | } | |
4007 | ||
4008 | DO_SVE2_RRX_TB(trans_SQDMULLB_zzx_s, gen_helper_sve2_sqdmull_idx_s, false) | |
4009 | DO_SVE2_RRX_TB(trans_SQDMULLB_zzx_d, gen_helper_sve2_sqdmull_idx_d, false) | |
4010 | DO_SVE2_RRX_TB(trans_SQDMULLT_zzx_s, gen_helper_sve2_sqdmull_idx_s, true) | |
4011 | DO_SVE2_RRX_TB(trans_SQDMULLT_zzx_d, gen_helper_sve2_sqdmull_idx_d, true) | |
4012 | ||
d3949c4c RH |
4013 | DO_SVE2_RRX_TB(trans_SMULLB_zzx_s, gen_helper_sve2_smull_idx_s, false) |
4014 | DO_SVE2_RRX_TB(trans_SMULLB_zzx_d, gen_helper_sve2_smull_idx_d, false) | |
4015 | DO_SVE2_RRX_TB(trans_SMULLT_zzx_s, gen_helper_sve2_smull_idx_s, true) | |
4016 | DO_SVE2_RRX_TB(trans_SMULLT_zzx_d, gen_helper_sve2_smull_idx_d, true) | |
4017 | ||
4018 | DO_SVE2_RRX_TB(trans_UMULLB_zzx_s, gen_helper_sve2_umull_idx_s, false) | |
4019 | DO_SVE2_RRX_TB(trans_UMULLB_zzx_d, gen_helper_sve2_umull_idx_d, false) | |
4020 | DO_SVE2_RRX_TB(trans_UMULLT_zzx_s, gen_helper_sve2_umull_idx_s, true) | |
4021 | DO_SVE2_RRX_TB(trans_UMULLT_zzx_d, gen_helper_sve2_umull_idx_d, true) | |
4022 | ||
b95f5eeb RH |
4023 | #undef DO_SVE2_RRX_TB |
4024 | ||
8a02aac7 RH |
4025 | static bool do_sve2_zzzz_data(DisasContext *s, int rd, int rn, int rm, int ra, |
4026 | int data, gen_helper_gvec_4 *fn) | |
4027 | { | |
4028 | if (fn == NULL || !dc_isar_feature(aa64_sve2, s)) { | |
4029 | return false; | |
4030 | } | |
4031 | if (sve_access_check(s)) { | |
4032 | unsigned vsz = vec_full_reg_size(s); | |
4033 | tcg_gen_gvec_4_ool(vec_full_reg_offset(s, rd), | |
4034 | vec_full_reg_offset(s, rn), | |
4035 | vec_full_reg_offset(s, rm), | |
4036 | vec_full_reg_offset(s, ra), | |
4037 | vsz, vsz, data, fn); | |
4038 | } | |
4039 | return true; | |
4040 | } | |
4041 | ||
4042 | #define DO_SVE2_RRXR(NAME, FUNC) \ | |
4043 | static bool NAME(DisasContext *s, arg_rrxr_esz *a) \ | |
4044 | { return do_sve2_zzzz_data(s, a->rd, a->rn, a->rm, a->ra, a->index, FUNC); } | |
4045 | ||
4046 | DO_SVE2_RRXR(trans_MLA_zzxz_h, gen_helper_gvec_mla_idx_h) | |
4047 | DO_SVE2_RRXR(trans_MLA_zzxz_s, gen_helper_gvec_mla_idx_s) | |
4048 | DO_SVE2_RRXR(trans_MLA_zzxz_d, gen_helper_gvec_mla_idx_d) | |
4049 | ||
4050 | DO_SVE2_RRXR(trans_MLS_zzxz_h, gen_helper_gvec_mls_idx_h) | |
4051 | DO_SVE2_RRXR(trans_MLS_zzxz_s, gen_helper_gvec_mls_idx_s) | |
4052 | DO_SVE2_RRXR(trans_MLS_zzxz_d, gen_helper_gvec_mls_idx_d) | |
4053 | ||
75d6d5fc RH |
4054 | DO_SVE2_RRXR(trans_SQRDMLAH_zzxz_h, gen_helper_sve2_sqrdmlah_idx_h) |
4055 | DO_SVE2_RRXR(trans_SQRDMLAH_zzxz_s, gen_helper_sve2_sqrdmlah_idx_s) | |
4056 | DO_SVE2_RRXR(trans_SQRDMLAH_zzxz_d, gen_helper_sve2_sqrdmlah_idx_d) | |
4057 | ||
4058 | DO_SVE2_RRXR(trans_SQRDMLSH_zzxz_h, gen_helper_sve2_sqrdmlsh_idx_h) | |
4059 | DO_SVE2_RRXR(trans_SQRDMLSH_zzxz_s, gen_helper_sve2_sqrdmlsh_idx_s) | |
4060 | DO_SVE2_RRXR(trans_SQRDMLSH_zzxz_d, gen_helper_sve2_sqrdmlsh_idx_d) | |
4061 | ||
8a02aac7 RH |
4062 | #undef DO_SVE2_RRXR |
4063 | ||
c5c455d7 RH |
4064 | #define DO_SVE2_RRXR_TB(NAME, FUNC, TOP) \ |
4065 | static bool NAME(DisasContext *s, arg_rrxr_esz *a) \ | |
4066 | { \ | |
4067 | return do_sve2_zzzz_data(s, a->rd, a->rn, a->rm, a->rd, \ | |
4068 | (a->index << 1) | TOP, FUNC); \ | |
4069 | } | |
4070 | ||
4071 | DO_SVE2_RRXR_TB(trans_SQDMLALB_zzxw_s, gen_helper_sve2_sqdmlal_idx_s, false) | |
4072 | DO_SVE2_RRXR_TB(trans_SQDMLALB_zzxw_d, gen_helper_sve2_sqdmlal_idx_d, false) | |
4073 | DO_SVE2_RRXR_TB(trans_SQDMLALT_zzxw_s, gen_helper_sve2_sqdmlal_idx_s, true) | |
4074 | DO_SVE2_RRXR_TB(trans_SQDMLALT_zzxw_d, gen_helper_sve2_sqdmlal_idx_d, true) | |
4075 | ||
4076 | DO_SVE2_RRXR_TB(trans_SQDMLSLB_zzxw_s, gen_helper_sve2_sqdmlsl_idx_s, false) | |
4077 | DO_SVE2_RRXR_TB(trans_SQDMLSLB_zzxw_d, gen_helper_sve2_sqdmlsl_idx_d, false) | |
4078 | DO_SVE2_RRXR_TB(trans_SQDMLSLT_zzxw_s, gen_helper_sve2_sqdmlsl_idx_s, true) | |
4079 | DO_SVE2_RRXR_TB(trans_SQDMLSLT_zzxw_d, gen_helper_sve2_sqdmlsl_idx_d, true) | |
d462469f RH |
4080 | |
4081 | DO_SVE2_RRXR_TB(trans_SMLALB_zzxw_s, gen_helper_sve2_smlal_idx_s, false) | |
4082 | DO_SVE2_RRXR_TB(trans_SMLALB_zzxw_d, gen_helper_sve2_smlal_idx_d, false) | |
4083 | DO_SVE2_RRXR_TB(trans_SMLALT_zzxw_s, gen_helper_sve2_smlal_idx_s, true) | |
4084 | DO_SVE2_RRXR_TB(trans_SMLALT_zzxw_d, gen_helper_sve2_smlal_idx_d, true) | |
4085 | ||
4086 | DO_SVE2_RRXR_TB(trans_UMLALB_zzxw_s, gen_helper_sve2_umlal_idx_s, false) | |
4087 | DO_SVE2_RRXR_TB(trans_UMLALB_zzxw_d, gen_helper_sve2_umlal_idx_d, false) | |
4088 | DO_SVE2_RRXR_TB(trans_UMLALT_zzxw_s, gen_helper_sve2_umlal_idx_s, true) | |
4089 | DO_SVE2_RRXR_TB(trans_UMLALT_zzxw_d, gen_helper_sve2_umlal_idx_d, true) | |
4090 | ||
4091 | DO_SVE2_RRXR_TB(trans_SMLSLB_zzxw_s, gen_helper_sve2_smlsl_idx_s, false) | |
4092 | DO_SVE2_RRXR_TB(trans_SMLSLB_zzxw_d, gen_helper_sve2_smlsl_idx_d, false) | |
4093 | DO_SVE2_RRXR_TB(trans_SMLSLT_zzxw_s, gen_helper_sve2_smlsl_idx_s, true) | |
4094 | DO_SVE2_RRXR_TB(trans_SMLSLT_zzxw_d, gen_helper_sve2_smlsl_idx_d, true) | |
4095 | ||
4096 | DO_SVE2_RRXR_TB(trans_UMLSLB_zzxw_s, gen_helper_sve2_umlsl_idx_s, false) | |
4097 | DO_SVE2_RRXR_TB(trans_UMLSLB_zzxw_d, gen_helper_sve2_umlsl_idx_d, false) | |
4098 | DO_SVE2_RRXR_TB(trans_UMLSLT_zzxw_s, gen_helper_sve2_umlsl_idx_s, true) | |
4099 | DO_SVE2_RRXR_TB(trans_UMLSLT_zzxw_d, gen_helper_sve2_umlsl_idx_d, true) | |
c5c455d7 RH |
4100 | |
4101 | #undef DO_SVE2_RRXR_TB | |
4102 | ||
3b787ed8 RH |
4103 | #define DO_SVE2_RRXR_ROT(NAME, FUNC) \ |
4104 | static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \ | |
4105 | { \ | |
4106 | return do_sve2_zzzz_data(s, a->rd, a->rn, a->rm, a->ra, \ | |
4107 | (a->index << 2) | a->rot, FUNC); \ | |
4108 | } | |
4109 | ||
4110 | DO_SVE2_RRXR_ROT(CMLA_zzxz_h, gen_helper_sve2_cmla_idx_h) | |
4111 | DO_SVE2_RRXR_ROT(CMLA_zzxz_s, gen_helper_sve2_cmla_idx_s) | |
4112 | ||
4113 | DO_SVE2_RRXR_ROT(SQRDCMLAH_zzxz_h, gen_helper_sve2_sqrdcmlah_idx_h) | |
4114 | DO_SVE2_RRXR_ROT(SQRDCMLAH_zzxz_s, gen_helper_sve2_sqrdcmlah_idx_s) | |
4115 | ||
21068f39 RH |
4116 | DO_SVE2_RRXR_ROT(CDOT_zzxw_s, gen_helper_sve2_cdot_idx_s) |
4117 | DO_SVE2_RRXR_ROT(CDOT_zzxw_d, gen_helper_sve2_cdot_idx_d) | |
4118 | ||
3b787ed8 RH |
4119 | #undef DO_SVE2_RRXR_ROT |
4120 | ||
ca40a6e6 RH |
4121 | /* |
4122 | *** SVE Floating Point Multiply-Add Indexed Group | |
4123 | */ | |
4124 | ||
0a82d963 | 4125 | static bool do_FMLA_zzxz(DisasContext *s, arg_rrxr_esz *a, bool sub) |
ca40a6e6 RH |
4126 | { |
4127 | static gen_helper_gvec_4_ptr * const fns[3] = { | |
4128 | gen_helper_gvec_fmla_idx_h, | |
4129 | gen_helper_gvec_fmla_idx_s, | |
4130 | gen_helper_gvec_fmla_idx_d, | |
4131 | }; | |
4132 | ||
4133 | if (sve_access_check(s)) { | |
4134 | unsigned vsz = vec_full_reg_size(s); | |
cdfb22bb | 4135 | TCGv_ptr status = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR); |
ca40a6e6 RH |
4136 | tcg_gen_gvec_4_ptr(vec_full_reg_offset(s, a->rd), |
4137 | vec_full_reg_offset(s, a->rn), | |
4138 | vec_full_reg_offset(s, a->rm), | |
4139 | vec_full_reg_offset(s, a->ra), | |
0a82d963 | 4140 | status, vsz, vsz, (a->index << 1) | sub, |
ca40a6e6 RH |
4141 | fns[a->esz - 1]); |
4142 | tcg_temp_free_ptr(status); | |
4143 | } | |
4144 | return true; | |
4145 | } | |
4146 | ||
0a82d963 RH |
4147 | static bool trans_FMLA_zzxz(DisasContext *s, arg_FMLA_zzxz *a) |
4148 | { | |
4149 | return do_FMLA_zzxz(s, a, false); | |
4150 | } | |
4151 | ||
4152 | static bool trans_FMLS_zzxz(DisasContext *s, arg_FMLA_zzxz *a) | |
4153 | { | |
4154 | return do_FMLA_zzxz(s, a, true); | |
4155 | } | |
4156 | ||
ca40a6e6 RH |
4157 | /* |
4158 | *** SVE Floating Point Multiply Indexed Group | |
4159 | */ | |
4160 | ||
3a7be554 | 4161 | static bool trans_FMUL_zzx(DisasContext *s, arg_FMUL_zzx *a) |
ca40a6e6 RH |
4162 | { |
4163 | static gen_helper_gvec_3_ptr * const fns[3] = { | |
4164 | gen_helper_gvec_fmul_idx_h, | |
4165 | gen_helper_gvec_fmul_idx_s, | |
4166 | gen_helper_gvec_fmul_idx_d, | |
4167 | }; | |
4168 | ||
4169 | if (sve_access_check(s)) { | |
4170 | unsigned vsz = vec_full_reg_size(s); | |
cdfb22bb | 4171 | TCGv_ptr status = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR); |
ca40a6e6 RH |
4172 | tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, a->rd), |
4173 | vec_full_reg_offset(s, a->rn), | |
4174 | vec_full_reg_offset(s, a->rm), | |
4175 | status, vsz, vsz, a->index, fns[a->esz - 1]); | |
4176 | tcg_temp_free_ptr(status); | |
4177 | } | |
4178 | return true; | |
4179 | } | |
4180 | ||
23fbe79f RH |
4181 | /* |
4182 | *** SVE Floating Point Fast Reduction Group | |
4183 | */ | |
4184 | ||
4185 | typedef void gen_helper_fp_reduce(TCGv_i64, TCGv_ptr, TCGv_ptr, | |
4186 | TCGv_ptr, TCGv_i32); | |
4187 | ||
4188 | static void do_reduce(DisasContext *s, arg_rpr_esz *a, | |
4189 | gen_helper_fp_reduce *fn) | |
4190 | { | |
4191 | unsigned vsz = vec_full_reg_size(s); | |
4192 | unsigned p2vsz = pow2ceil(vsz); | |
c648c9b7 | 4193 | TCGv_i32 t_desc = tcg_const_i32(simd_desc(vsz, vsz, p2vsz)); |
23fbe79f RH |
4194 | TCGv_ptr t_zn, t_pg, status; |
4195 | TCGv_i64 temp; | |
4196 | ||
4197 | temp = tcg_temp_new_i64(); | |
4198 | t_zn = tcg_temp_new_ptr(); | |
4199 | t_pg = tcg_temp_new_ptr(); | |
4200 | ||
4201 | tcg_gen_addi_ptr(t_zn, cpu_env, vec_full_reg_offset(s, a->rn)); | |
4202 | tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, a->pg)); | |
cdfb22bb | 4203 | status = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR); |
23fbe79f RH |
4204 | |
4205 | fn(temp, t_zn, t_pg, status, t_desc); | |
4206 | tcg_temp_free_ptr(t_zn); | |
4207 | tcg_temp_free_ptr(t_pg); | |
4208 | tcg_temp_free_ptr(status); | |
4209 | tcg_temp_free_i32(t_desc); | |
4210 | ||
4211 | write_fp_dreg(s, a->rd, temp); | |
4212 | tcg_temp_free_i64(temp); | |
4213 | } | |
4214 | ||
4215 | #define DO_VPZ(NAME, name) \ | |
3a7be554 | 4216 | static bool trans_##NAME(DisasContext *s, arg_rpr_esz *a) \ |
23fbe79f RH |
4217 | { \ |
4218 | static gen_helper_fp_reduce * const fns[3] = { \ | |
4219 | gen_helper_sve_##name##_h, \ | |
4220 | gen_helper_sve_##name##_s, \ | |
4221 | gen_helper_sve_##name##_d, \ | |
4222 | }; \ | |
4223 | if (a->esz == 0) { \ | |
4224 | return false; \ | |
4225 | } \ | |
4226 | if (sve_access_check(s)) { \ | |
4227 | do_reduce(s, a, fns[a->esz - 1]); \ | |
4228 | } \ | |
4229 | return true; \ | |
4230 | } | |
4231 | ||
4232 | DO_VPZ(FADDV, faddv) | |
4233 | DO_VPZ(FMINNMV, fminnmv) | |
4234 | DO_VPZ(FMAXNMV, fmaxnmv) | |
4235 | DO_VPZ(FMINV, fminv) | |
4236 | DO_VPZ(FMAXV, fmaxv) | |
4237 | ||
3887c038 RH |
4238 | /* |
4239 | *** SVE Floating Point Unary Operations - Unpredicated Group | |
4240 | */ | |
4241 | ||
4242 | static void do_zz_fp(DisasContext *s, arg_rr_esz *a, gen_helper_gvec_2_ptr *fn) | |
4243 | { | |
4244 | unsigned vsz = vec_full_reg_size(s); | |
cdfb22bb | 4245 | TCGv_ptr status = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR); |
3887c038 RH |
4246 | |
4247 | tcg_gen_gvec_2_ptr(vec_full_reg_offset(s, a->rd), | |
4248 | vec_full_reg_offset(s, a->rn), | |
4249 | status, vsz, vsz, 0, fn); | |
4250 | tcg_temp_free_ptr(status); | |
4251 | } | |
4252 | ||
3a7be554 | 4253 | static bool trans_FRECPE(DisasContext *s, arg_rr_esz *a) |
3887c038 RH |
4254 | { |
4255 | static gen_helper_gvec_2_ptr * const fns[3] = { | |
4256 | gen_helper_gvec_frecpe_h, | |
4257 | gen_helper_gvec_frecpe_s, | |
4258 | gen_helper_gvec_frecpe_d, | |
4259 | }; | |
4260 | if (a->esz == 0) { | |
4261 | return false; | |
4262 | } | |
4263 | if (sve_access_check(s)) { | |
4264 | do_zz_fp(s, a, fns[a->esz - 1]); | |
4265 | } | |
4266 | return true; | |
4267 | } | |
4268 | ||
3a7be554 | 4269 | static bool trans_FRSQRTE(DisasContext *s, arg_rr_esz *a) |
3887c038 RH |
4270 | { |
4271 | static gen_helper_gvec_2_ptr * const fns[3] = { | |
4272 | gen_helper_gvec_frsqrte_h, | |
4273 | gen_helper_gvec_frsqrte_s, | |
4274 | gen_helper_gvec_frsqrte_d, | |
4275 | }; | |
4276 | if (a->esz == 0) { | |
4277 | return false; | |
4278 | } | |
4279 | if (sve_access_check(s)) { | |
4280 | do_zz_fp(s, a, fns[a->esz - 1]); | |
4281 | } | |
4282 | return true; | |
4283 | } | |
4284 | ||
4d2e2a03 RH |
4285 | /* |
4286 | *** SVE Floating Point Compare with Zero Group | |
4287 | */ | |
4288 | ||
4289 | static void do_ppz_fp(DisasContext *s, arg_rpr_esz *a, | |
4290 | gen_helper_gvec_3_ptr *fn) | |
4291 | { | |
4292 | unsigned vsz = vec_full_reg_size(s); | |
cdfb22bb | 4293 | TCGv_ptr status = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR); |
4d2e2a03 RH |
4294 | |
4295 | tcg_gen_gvec_3_ptr(pred_full_reg_offset(s, a->rd), | |
4296 | vec_full_reg_offset(s, a->rn), | |
4297 | pred_full_reg_offset(s, a->pg), | |
4298 | status, vsz, vsz, 0, fn); | |
4299 | tcg_temp_free_ptr(status); | |
4300 | } | |
4301 | ||
4302 | #define DO_PPZ(NAME, name) \ | |
3a7be554 | 4303 | static bool trans_##NAME(DisasContext *s, arg_rpr_esz *a) \ |
4d2e2a03 RH |
4304 | { \ |
4305 | static gen_helper_gvec_3_ptr * const fns[3] = { \ | |
4306 | gen_helper_sve_##name##_h, \ | |
4307 | gen_helper_sve_##name##_s, \ | |
4308 | gen_helper_sve_##name##_d, \ | |
4309 | }; \ | |
4310 | if (a->esz == 0) { \ | |
4311 | return false; \ | |
4312 | } \ | |
4313 | if (sve_access_check(s)) { \ | |
4314 | do_ppz_fp(s, a, fns[a->esz - 1]); \ | |
4315 | } \ | |
4316 | return true; \ | |
4317 | } | |
4318 | ||
4319 | DO_PPZ(FCMGE_ppz0, fcmge0) | |
4320 | DO_PPZ(FCMGT_ppz0, fcmgt0) | |
4321 | DO_PPZ(FCMLE_ppz0, fcmle0) | |
4322 | DO_PPZ(FCMLT_ppz0, fcmlt0) | |
4323 | DO_PPZ(FCMEQ_ppz0, fcmeq0) | |
4324 | DO_PPZ(FCMNE_ppz0, fcmne0) | |
4325 | ||
4326 | #undef DO_PPZ | |
4327 | ||
67fcd9ad RH |
4328 | /* |
4329 | *** SVE floating-point trig multiply-add coefficient | |
4330 | */ | |
4331 | ||
3a7be554 | 4332 | static bool trans_FTMAD(DisasContext *s, arg_FTMAD *a) |
67fcd9ad RH |
4333 | { |
4334 | static gen_helper_gvec_3_ptr * const fns[3] = { | |
4335 | gen_helper_sve_ftmad_h, | |
4336 | gen_helper_sve_ftmad_s, | |
4337 | gen_helper_sve_ftmad_d, | |
4338 | }; | |
4339 | ||
4340 | if (a->esz == 0) { | |
4341 | return false; | |
4342 | } | |
4343 | if (sve_access_check(s)) { | |
4344 | unsigned vsz = vec_full_reg_size(s); | |
cdfb22bb | 4345 | TCGv_ptr status = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR); |
67fcd9ad RH |
4346 | tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, a->rd), |
4347 | vec_full_reg_offset(s, a->rn), | |
4348 | vec_full_reg_offset(s, a->rm), | |
4349 | status, vsz, vsz, a->imm, fns[a->esz - 1]); | |
4350 | tcg_temp_free_ptr(status); | |
4351 | } | |
4352 | return true; | |
4353 | } | |
4354 | ||
7f9ddf64 RH |
4355 | /* |
4356 | *** SVE Floating Point Accumulating Reduction Group | |
4357 | */ | |
4358 | ||
3a7be554 | 4359 | static bool trans_FADDA(DisasContext *s, arg_rprr_esz *a) |
7f9ddf64 RH |
4360 | { |
4361 | typedef void fadda_fn(TCGv_i64, TCGv_i64, TCGv_ptr, | |
4362 | TCGv_ptr, TCGv_ptr, TCGv_i32); | |
4363 | static fadda_fn * const fns[3] = { | |
4364 | gen_helper_sve_fadda_h, | |
4365 | gen_helper_sve_fadda_s, | |
4366 | gen_helper_sve_fadda_d, | |
4367 | }; | |
4368 | unsigned vsz = vec_full_reg_size(s); | |
4369 | TCGv_ptr t_rm, t_pg, t_fpst; | |
4370 | TCGv_i64 t_val; | |
4371 | TCGv_i32 t_desc; | |
4372 | ||
4373 | if (a->esz == 0) { | |
4374 | return false; | |
4375 | } | |
4376 | if (!sve_access_check(s)) { | |
4377 | return true; | |
4378 | } | |
4379 | ||
4380 | t_val = load_esz(cpu_env, vec_reg_offset(s, a->rn, 0, a->esz), a->esz); | |
4381 | t_rm = tcg_temp_new_ptr(); | |
4382 | t_pg = tcg_temp_new_ptr(); | |
4383 | tcg_gen_addi_ptr(t_rm, cpu_env, vec_full_reg_offset(s, a->rm)); | |
4384 | tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, a->pg)); | |
cdfb22bb | 4385 | t_fpst = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR); |
7f9ddf64 RH |
4386 | t_desc = tcg_const_i32(simd_desc(vsz, vsz, 0)); |
4387 | ||
4388 | fns[a->esz - 1](t_val, t_val, t_rm, t_pg, t_fpst, t_desc); | |
4389 | ||
4390 | tcg_temp_free_i32(t_desc); | |
4391 | tcg_temp_free_ptr(t_fpst); | |
4392 | tcg_temp_free_ptr(t_pg); | |
4393 | tcg_temp_free_ptr(t_rm); | |
4394 | ||
4395 | write_fp_dreg(s, a->rd, t_val); | |
4396 | tcg_temp_free_i64(t_val); | |
4397 | return true; | |
4398 | } | |
4399 | ||
29b80469 RH |
4400 | /* |
4401 | *** SVE Floating Point Arithmetic - Unpredicated Group | |
4402 | */ | |
4403 | ||
4404 | static bool do_zzz_fp(DisasContext *s, arg_rrr_esz *a, | |
4405 | gen_helper_gvec_3_ptr *fn) | |
4406 | { | |
4407 | if (fn == NULL) { | |
4408 | return false; | |
4409 | } | |
4410 | if (sve_access_check(s)) { | |
4411 | unsigned vsz = vec_full_reg_size(s); | |
cdfb22bb | 4412 | TCGv_ptr status = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR); |
29b80469 RH |
4413 | tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, a->rd), |
4414 | vec_full_reg_offset(s, a->rn), | |
4415 | vec_full_reg_offset(s, a->rm), | |
4416 | status, vsz, vsz, 0, fn); | |
4417 | tcg_temp_free_ptr(status); | |
4418 | } | |
4419 | return true; | |
4420 | } | |
4421 | ||
4422 | ||
4423 | #define DO_FP3(NAME, name) \ | |
3a7be554 | 4424 | static bool trans_##NAME(DisasContext *s, arg_rrr_esz *a) \ |
29b80469 RH |
4425 | { \ |
4426 | static gen_helper_gvec_3_ptr * const fns[4] = { \ | |
4427 | NULL, gen_helper_gvec_##name##_h, \ | |
4428 | gen_helper_gvec_##name##_s, gen_helper_gvec_##name##_d \ | |
4429 | }; \ | |
4430 | return do_zzz_fp(s, a, fns[a->esz]); \ | |
4431 | } | |
4432 | ||
4433 | DO_FP3(FADD_zzz, fadd) | |
4434 | DO_FP3(FSUB_zzz, fsub) | |
4435 | DO_FP3(FMUL_zzz, fmul) | |
4436 | DO_FP3(FTSMUL, ftsmul) | |
4437 | DO_FP3(FRECPS, recps) | |
4438 | DO_FP3(FRSQRTS, rsqrts) | |
4439 | ||
4440 | #undef DO_FP3 | |
4441 | ||
ec3b87c2 RH |
4442 | /* |
4443 | *** SVE Floating Point Arithmetic - Predicated Group | |
4444 | */ | |
4445 | ||
4446 | static bool do_zpzz_fp(DisasContext *s, arg_rprr_esz *a, | |
4447 | gen_helper_gvec_4_ptr *fn) | |
4448 | { | |
4449 | if (fn == NULL) { | |
4450 | return false; | |
4451 | } | |
4452 | if (sve_access_check(s)) { | |
4453 | unsigned vsz = vec_full_reg_size(s); | |
cdfb22bb | 4454 | TCGv_ptr status = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR); |
ec3b87c2 RH |
4455 | tcg_gen_gvec_4_ptr(vec_full_reg_offset(s, a->rd), |
4456 | vec_full_reg_offset(s, a->rn), | |
4457 | vec_full_reg_offset(s, a->rm), | |
4458 | pred_full_reg_offset(s, a->pg), | |
4459 | status, vsz, vsz, 0, fn); | |
4460 | tcg_temp_free_ptr(status); | |
4461 | } | |
4462 | return true; | |
4463 | } | |
4464 | ||
4465 | #define DO_FP3(NAME, name) \ | |
3a7be554 | 4466 | static bool trans_##NAME(DisasContext *s, arg_rprr_esz *a) \ |
ec3b87c2 RH |
4467 | { \ |
4468 | static gen_helper_gvec_4_ptr * const fns[4] = { \ | |
4469 | NULL, gen_helper_sve_##name##_h, \ | |
4470 | gen_helper_sve_##name##_s, gen_helper_sve_##name##_d \ | |
4471 | }; \ | |
4472 | return do_zpzz_fp(s, a, fns[a->esz]); \ | |
4473 | } | |
4474 | ||
4475 | DO_FP3(FADD_zpzz, fadd) | |
4476 | DO_FP3(FSUB_zpzz, fsub) | |
4477 | DO_FP3(FMUL_zpzz, fmul) | |
4478 | DO_FP3(FMIN_zpzz, fmin) | |
4479 | DO_FP3(FMAX_zpzz, fmax) | |
4480 | DO_FP3(FMINNM_zpzz, fminnum) | |
4481 | DO_FP3(FMAXNM_zpzz, fmaxnum) | |
4482 | DO_FP3(FABD, fabd) | |
4483 | DO_FP3(FSCALE, fscalbn) | |
4484 | DO_FP3(FDIV, fdiv) | |
4485 | DO_FP3(FMULX, fmulx) | |
4486 | ||
4487 | #undef DO_FP3 | |
8092c6a3 | 4488 | |
cc48affe RH |
4489 | typedef void gen_helper_sve_fp2scalar(TCGv_ptr, TCGv_ptr, TCGv_ptr, |
4490 | TCGv_i64, TCGv_ptr, TCGv_i32); | |
4491 | ||
4492 | static void do_fp_scalar(DisasContext *s, int zd, int zn, int pg, bool is_fp16, | |
4493 | TCGv_i64 scalar, gen_helper_sve_fp2scalar *fn) | |
4494 | { | |
4495 | unsigned vsz = vec_full_reg_size(s); | |
4496 | TCGv_ptr t_zd, t_zn, t_pg, status; | |
4497 | TCGv_i32 desc; | |
4498 | ||
4499 | t_zd = tcg_temp_new_ptr(); | |
4500 | t_zn = tcg_temp_new_ptr(); | |
4501 | t_pg = tcg_temp_new_ptr(); | |
4502 | tcg_gen_addi_ptr(t_zd, cpu_env, vec_full_reg_offset(s, zd)); | |
4503 | tcg_gen_addi_ptr(t_zn, cpu_env, vec_full_reg_offset(s, zn)); | |
4504 | tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, pg)); | |
4505 | ||
cdfb22bb | 4506 | status = fpstatus_ptr(is_fp16 ? FPST_FPCR_F16 : FPST_FPCR); |
cc48affe RH |
4507 | desc = tcg_const_i32(simd_desc(vsz, vsz, 0)); |
4508 | fn(t_zd, t_zn, t_pg, scalar, status, desc); | |
4509 | ||
4510 | tcg_temp_free_i32(desc); | |
4511 | tcg_temp_free_ptr(status); | |
4512 | tcg_temp_free_ptr(t_pg); | |
4513 | tcg_temp_free_ptr(t_zn); | |
4514 | tcg_temp_free_ptr(t_zd); | |
4515 | } | |
4516 | ||
4517 | static void do_fp_imm(DisasContext *s, arg_rpri_esz *a, uint64_t imm, | |
4518 | gen_helper_sve_fp2scalar *fn) | |
4519 | { | |
138a1f7b RH |
4520 | do_fp_scalar(s, a->rd, a->rn, a->pg, a->esz == MO_16, |
4521 | tcg_constant_i64(imm), fn); | |
cc48affe RH |
4522 | } |
4523 | ||
4524 | #define DO_FP_IMM(NAME, name, const0, const1) \ | |
3a7be554 | 4525 | static bool trans_##NAME##_zpzi(DisasContext *s, arg_rpri_esz *a) \ |
cc48affe RH |
4526 | { \ |
4527 | static gen_helper_sve_fp2scalar * const fns[3] = { \ | |
4528 | gen_helper_sve_##name##_h, \ | |
4529 | gen_helper_sve_##name##_s, \ | |
4530 | gen_helper_sve_##name##_d \ | |
4531 | }; \ | |
4532 | static uint64_t const val[3][2] = { \ | |
4533 | { float16_##const0, float16_##const1 }, \ | |
4534 | { float32_##const0, float32_##const1 }, \ | |
4535 | { float64_##const0, float64_##const1 }, \ | |
4536 | }; \ | |
4537 | if (a->esz == 0) { \ | |
4538 | return false; \ | |
4539 | } \ | |
4540 | if (sve_access_check(s)) { \ | |
4541 | do_fp_imm(s, a, val[a->esz - 1][a->imm], fns[a->esz - 1]); \ | |
4542 | } \ | |
4543 | return true; \ | |
4544 | } | |
4545 | ||
cc48affe RH |
4546 | DO_FP_IMM(FADD, fadds, half, one) |
4547 | DO_FP_IMM(FSUB, fsubs, half, one) | |
4548 | DO_FP_IMM(FMUL, fmuls, half, two) | |
4549 | DO_FP_IMM(FSUBR, fsubrs, half, one) | |
4550 | DO_FP_IMM(FMAXNM, fmaxnms, zero, one) | |
4551 | DO_FP_IMM(FMINNM, fminnms, zero, one) | |
4552 | DO_FP_IMM(FMAX, fmaxs, zero, one) | |
4553 | DO_FP_IMM(FMIN, fmins, zero, one) | |
4554 | ||
4555 | #undef DO_FP_IMM | |
4556 | ||
abfdefd5 RH |
4557 | static bool do_fp_cmp(DisasContext *s, arg_rprr_esz *a, |
4558 | gen_helper_gvec_4_ptr *fn) | |
4559 | { | |
4560 | if (fn == NULL) { | |
4561 | return false; | |
4562 | } | |
4563 | if (sve_access_check(s)) { | |
4564 | unsigned vsz = vec_full_reg_size(s); | |
cdfb22bb | 4565 | TCGv_ptr status = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR); |
abfdefd5 RH |
4566 | tcg_gen_gvec_4_ptr(pred_full_reg_offset(s, a->rd), |
4567 | vec_full_reg_offset(s, a->rn), | |
4568 | vec_full_reg_offset(s, a->rm), | |
4569 | pred_full_reg_offset(s, a->pg), | |
4570 | status, vsz, vsz, 0, fn); | |
4571 | tcg_temp_free_ptr(status); | |
4572 | } | |
4573 | return true; | |
4574 | } | |
4575 | ||
4576 | #define DO_FPCMP(NAME, name) \ | |
3a7be554 | 4577 | static bool trans_##NAME##_ppzz(DisasContext *s, arg_rprr_esz *a) \ |
abfdefd5 RH |
4578 | { \ |
4579 | static gen_helper_gvec_4_ptr * const fns[4] = { \ | |
4580 | NULL, gen_helper_sve_##name##_h, \ | |
4581 | gen_helper_sve_##name##_s, gen_helper_sve_##name##_d \ | |
4582 | }; \ | |
4583 | return do_fp_cmp(s, a, fns[a->esz]); \ | |
4584 | } | |
4585 | ||
4586 | DO_FPCMP(FCMGE, fcmge) | |
4587 | DO_FPCMP(FCMGT, fcmgt) | |
4588 | DO_FPCMP(FCMEQ, fcmeq) | |
4589 | DO_FPCMP(FCMNE, fcmne) | |
4590 | DO_FPCMP(FCMUO, fcmuo) | |
4591 | DO_FPCMP(FACGE, facge) | |
4592 | DO_FPCMP(FACGT, facgt) | |
4593 | ||
4594 | #undef DO_FPCMP | |
4595 | ||
3a7be554 | 4596 | static bool trans_FCADD(DisasContext *s, arg_FCADD *a) |
76a9d9cd RH |
4597 | { |
4598 | static gen_helper_gvec_4_ptr * const fns[3] = { | |
4599 | gen_helper_sve_fcadd_h, | |
4600 | gen_helper_sve_fcadd_s, | |
4601 | gen_helper_sve_fcadd_d | |
4602 | }; | |
4603 | ||
4604 | if (a->esz == 0) { | |
4605 | return false; | |
4606 | } | |
4607 | if (sve_access_check(s)) { | |
4608 | unsigned vsz = vec_full_reg_size(s); | |
cdfb22bb | 4609 | TCGv_ptr status = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR); |
76a9d9cd RH |
4610 | tcg_gen_gvec_4_ptr(vec_full_reg_offset(s, a->rd), |
4611 | vec_full_reg_offset(s, a->rn), | |
4612 | vec_full_reg_offset(s, a->rm), | |
4613 | pred_full_reg_offset(s, a->pg), | |
4614 | status, vsz, vsz, a->rot, fns[a->esz - 1]); | |
4615 | tcg_temp_free_ptr(status); | |
4616 | } | |
4617 | return true; | |
4618 | } | |
4619 | ||
08975da9 RH |
4620 | static bool do_fmla(DisasContext *s, arg_rprrr_esz *a, |
4621 | gen_helper_gvec_5_ptr *fn) | |
6ceabaad | 4622 | { |
08975da9 | 4623 | if (a->esz == 0) { |
6ceabaad RH |
4624 | return false; |
4625 | } | |
08975da9 RH |
4626 | if (sve_access_check(s)) { |
4627 | unsigned vsz = vec_full_reg_size(s); | |
cdfb22bb | 4628 | TCGv_ptr status = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR); |
08975da9 RH |
4629 | tcg_gen_gvec_5_ptr(vec_full_reg_offset(s, a->rd), |
4630 | vec_full_reg_offset(s, a->rn), | |
4631 | vec_full_reg_offset(s, a->rm), | |
4632 | vec_full_reg_offset(s, a->ra), | |
4633 | pred_full_reg_offset(s, a->pg), | |
4634 | status, vsz, vsz, 0, fn); | |
4635 | tcg_temp_free_ptr(status); | |
6ceabaad | 4636 | } |
6ceabaad RH |
4637 | return true; |
4638 | } | |
4639 | ||
4640 | #define DO_FMLA(NAME, name) \ | |
3a7be554 | 4641 | static bool trans_##NAME(DisasContext *s, arg_rprrr_esz *a) \ |
6ceabaad | 4642 | { \ |
08975da9 | 4643 | static gen_helper_gvec_5_ptr * const fns[4] = { \ |
6ceabaad RH |
4644 | NULL, gen_helper_sve_##name##_h, \ |
4645 | gen_helper_sve_##name##_s, gen_helper_sve_##name##_d \ | |
4646 | }; \ | |
4647 | return do_fmla(s, a, fns[a->esz]); \ | |
4648 | } | |
4649 | ||
4650 | DO_FMLA(FMLA_zpzzz, fmla_zpzzz) | |
4651 | DO_FMLA(FMLS_zpzzz, fmls_zpzzz) | |
4652 | DO_FMLA(FNMLA_zpzzz, fnmla_zpzzz) | |
4653 | DO_FMLA(FNMLS_zpzzz, fnmls_zpzzz) | |
4654 | ||
4655 | #undef DO_FMLA | |
4656 | ||
3a7be554 | 4657 | static bool trans_FCMLA_zpzzz(DisasContext *s, arg_FCMLA_zpzzz *a) |
05f48bab | 4658 | { |
08975da9 RH |
4659 | static gen_helper_gvec_5_ptr * const fns[4] = { |
4660 | NULL, | |
05f48bab RH |
4661 | gen_helper_sve_fcmla_zpzzz_h, |
4662 | gen_helper_sve_fcmla_zpzzz_s, | |
4663 | gen_helper_sve_fcmla_zpzzz_d, | |
4664 | }; | |
4665 | ||
4666 | if (a->esz == 0) { | |
4667 | return false; | |
4668 | } | |
4669 | if (sve_access_check(s)) { | |
4670 | unsigned vsz = vec_full_reg_size(s); | |
cdfb22bb | 4671 | TCGv_ptr status = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR); |
08975da9 RH |
4672 | tcg_gen_gvec_5_ptr(vec_full_reg_offset(s, a->rd), |
4673 | vec_full_reg_offset(s, a->rn), | |
4674 | vec_full_reg_offset(s, a->rm), | |
4675 | vec_full_reg_offset(s, a->ra), | |
4676 | pred_full_reg_offset(s, a->pg), | |
4677 | status, vsz, vsz, a->rot, fns[a->esz]); | |
4678 | tcg_temp_free_ptr(status); | |
05f48bab RH |
4679 | } |
4680 | return true; | |
4681 | } | |
4682 | ||
3a7be554 | 4683 | static bool trans_FCMLA_zzxz(DisasContext *s, arg_FCMLA_zzxz *a) |
18fc2405 | 4684 | { |
636ddeb1 | 4685 | static gen_helper_gvec_4_ptr * const fns[2] = { |
18fc2405 RH |
4686 | gen_helper_gvec_fcmlah_idx, |
4687 | gen_helper_gvec_fcmlas_idx, | |
4688 | }; | |
4689 | ||
4690 | tcg_debug_assert(a->esz == 1 || a->esz == 2); | |
4691 | tcg_debug_assert(a->rd == a->ra); | |
4692 | if (sve_access_check(s)) { | |
4693 | unsigned vsz = vec_full_reg_size(s); | |
cdfb22bb | 4694 | TCGv_ptr status = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR); |
636ddeb1 | 4695 | tcg_gen_gvec_4_ptr(vec_full_reg_offset(s, a->rd), |
18fc2405 RH |
4696 | vec_full_reg_offset(s, a->rn), |
4697 | vec_full_reg_offset(s, a->rm), | |
636ddeb1 | 4698 | vec_full_reg_offset(s, a->ra), |
18fc2405 RH |
4699 | status, vsz, vsz, |
4700 | a->index * 4 + a->rot, | |
4701 | fns[a->esz - 1]); | |
4702 | tcg_temp_free_ptr(status); | |
4703 | } | |
4704 | return true; | |
4705 | } | |
4706 | ||
8092c6a3 RH |
4707 | /* |
4708 | *** SVE Floating Point Unary Operations Predicated Group | |
4709 | */ | |
4710 | ||
4711 | static bool do_zpz_ptr(DisasContext *s, int rd, int rn, int pg, | |
4712 | bool is_fp16, gen_helper_gvec_3_ptr *fn) | |
4713 | { | |
4714 | if (sve_access_check(s)) { | |
4715 | unsigned vsz = vec_full_reg_size(s); | |
cdfb22bb | 4716 | TCGv_ptr status = fpstatus_ptr(is_fp16 ? FPST_FPCR_F16 : FPST_FPCR); |
8092c6a3 RH |
4717 | tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd), |
4718 | vec_full_reg_offset(s, rn), | |
4719 | pred_full_reg_offset(s, pg), | |
4720 | status, vsz, vsz, 0, fn); | |
4721 | tcg_temp_free_ptr(status); | |
4722 | } | |
4723 | return true; | |
4724 | } | |
4725 | ||
3a7be554 | 4726 | static bool trans_FCVT_sh(DisasContext *s, arg_rpr_esz *a) |
46d33d1e | 4727 | { |
e4ab5124 | 4728 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvt_sh); |
46d33d1e RH |
4729 | } |
4730 | ||
3a7be554 | 4731 | static bool trans_FCVT_hs(DisasContext *s, arg_rpr_esz *a) |
46d33d1e RH |
4732 | { |
4733 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvt_hs); | |
4734 | } | |
4735 | ||
d29b17ca RH |
4736 | static bool trans_BFCVT(DisasContext *s, arg_rpr_esz *a) |
4737 | { | |
4738 | if (!dc_isar_feature(aa64_sve_bf16, s)) { | |
4739 | return false; | |
4740 | } | |
4741 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_bfcvt); | |
4742 | } | |
4743 | ||
3a7be554 | 4744 | static bool trans_FCVT_dh(DisasContext *s, arg_rpr_esz *a) |
46d33d1e | 4745 | { |
e4ab5124 | 4746 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvt_dh); |
46d33d1e RH |
4747 | } |
4748 | ||
3a7be554 | 4749 | static bool trans_FCVT_hd(DisasContext *s, arg_rpr_esz *a) |
46d33d1e RH |
4750 | { |
4751 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvt_hd); | |
4752 | } | |
4753 | ||
3a7be554 | 4754 | static bool trans_FCVT_ds(DisasContext *s, arg_rpr_esz *a) |
46d33d1e RH |
4755 | { |
4756 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvt_ds); | |
4757 | } | |
4758 | ||
3a7be554 | 4759 | static bool trans_FCVT_sd(DisasContext *s, arg_rpr_esz *a) |
46d33d1e RH |
4760 | { |
4761 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvt_sd); | |
4762 | } | |
4763 | ||
3a7be554 | 4764 | static bool trans_FCVTZS_hh(DisasContext *s, arg_rpr_esz *a) |
df4de1af RH |
4765 | { |
4766 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_fcvtzs_hh); | |
4767 | } | |
4768 | ||
3a7be554 | 4769 | static bool trans_FCVTZU_hh(DisasContext *s, arg_rpr_esz *a) |
df4de1af RH |
4770 | { |
4771 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_fcvtzu_hh); | |
4772 | } | |
4773 | ||
3a7be554 | 4774 | static bool trans_FCVTZS_hs(DisasContext *s, arg_rpr_esz *a) |
df4de1af RH |
4775 | { |
4776 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_fcvtzs_hs); | |
4777 | } | |
4778 | ||
3a7be554 | 4779 | static bool trans_FCVTZU_hs(DisasContext *s, arg_rpr_esz *a) |
df4de1af RH |
4780 | { |
4781 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_fcvtzu_hs); | |
4782 | } | |
4783 | ||
3a7be554 | 4784 | static bool trans_FCVTZS_hd(DisasContext *s, arg_rpr_esz *a) |
df4de1af RH |
4785 | { |
4786 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_fcvtzs_hd); | |
4787 | } | |
4788 | ||
3a7be554 | 4789 | static bool trans_FCVTZU_hd(DisasContext *s, arg_rpr_esz *a) |
df4de1af RH |
4790 | { |
4791 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_fcvtzu_hd); | |
4792 | } | |
4793 | ||
3a7be554 | 4794 | static bool trans_FCVTZS_ss(DisasContext *s, arg_rpr_esz *a) |
df4de1af RH |
4795 | { |
4796 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvtzs_ss); | |
4797 | } | |
4798 | ||
3a7be554 | 4799 | static bool trans_FCVTZU_ss(DisasContext *s, arg_rpr_esz *a) |
df4de1af RH |
4800 | { |
4801 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvtzu_ss); | |
4802 | } | |
4803 | ||
3a7be554 | 4804 | static bool trans_FCVTZS_sd(DisasContext *s, arg_rpr_esz *a) |
df4de1af RH |
4805 | { |
4806 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvtzs_sd); | |
4807 | } | |
4808 | ||
3a7be554 | 4809 | static bool trans_FCVTZU_sd(DisasContext *s, arg_rpr_esz *a) |
df4de1af RH |
4810 | { |
4811 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvtzu_sd); | |
4812 | } | |
4813 | ||
3a7be554 | 4814 | static bool trans_FCVTZS_ds(DisasContext *s, arg_rpr_esz *a) |
df4de1af RH |
4815 | { |
4816 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvtzs_ds); | |
4817 | } | |
4818 | ||
3a7be554 | 4819 | static bool trans_FCVTZU_ds(DisasContext *s, arg_rpr_esz *a) |
df4de1af RH |
4820 | { |
4821 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvtzu_ds); | |
4822 | } | |
4823 | ||
3a7be554 | 4824 | static bool trans_FCVTZS_dd(DisasContext *s, arg_rpr_esz *a) |
df4de1af RH |
4825 | { |
4826 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvtzs_dd); | |
4827 | } | |
4828 | ||
3a7be554 | 4829 | static bool trans_FCVTZU_dd(DisasContext *s, arg_rpr_esz *a) |
df4de1af RH |
4830 | { |
4831 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvtzu_dd); | |
4832 | } | |
4833 | ||
cda3c753 RH |
4834 | static gen_helper_gvec_3_ptr * const frint_fns[3] = { |
4835 | gen_helper_sve_frint_h, | |
4836 | gen_helper_sve_frint_s, | |
4837 | gen_helper_sve_frint_d | |
4838 | }; | |
4839 | ||
3a7be554 | 4840 | static bool trans_FRINTI(DisasContext *s, arg_rpr_esz *a) |
cda3c753 RH |
4841 | { |
4842 | if (a->esz == 0) { | |
4843 | return false; | |
4844 | } | |
4845 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, a->esz == MO_16, | |
4846 | frint_fns[a->esz - 1]); | |
4847 | } | |
4848 | ||
3a7be554 | 4849 | static bool trans_FRINTX(DisasContext *s, arg_rpr_esz *a) |
cda3c753 RH |
4850 | { |
4851 | static gen_helper_gvec_3_ptr * const fns[3] = { | |
4852 | gen_helper_sve_frintx_h, | |
4853 | gen_helper_sve_frintx_s, | |
4854 | gen_helper_sve_frintx_d | |
4855 | }; | |
4856 | if (a->esz == 0) { | |
4857 | return false; | |
4858 | } | |
4859 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, a->esz == MO_16, fns[a->esz - 1]); | |
4860 | } | |
4861 | ||
95365277 SL |
4862 | static bool do_frint_mode(DisasContext *s, arg_rpr_esz *a, |
4863 | int mode, gen_helper_gvec_3_ptr *fn) | |
cda3c753 | 4864 | { |
cda3c753 RH |
4865 | if (sve_access_check(s)) { |
4866 | unsigned vsz = vec_full_reg_size(s); | |
4867 | TCGv_i32 tmode = tcg_const_i32(mode); | |
cdfb22bb | 4868 | TCGv_ptr status = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR); |
cda3c753 RH |
4869 | |
4870 | gen_helper_set_rmode(tmode, tmode, status); | |
4871 | ||
4872 | tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, a->rd), | |
4873 | vec_full_reg_offset(s, a->rn), | |
4874 | pred_full_reg_offset(s, a->pg), | |
95365277 | 4875 | status, vsz, vsz, 0, fn); |
cda3c753 RH |
4876 | |
4877 | gen_helper_set_rmode(tmode, tmode, status); | |
4878 | tcg_temp_free_i32(tmode); | |
4879 | tcg_temp_free_ptr(status); | |
4880 | } | |
4881 | return true; | |
4882 | } | |
4883 | ||
3a7be554 | 4884 | static bool trans_FRINTN(DisasContext *s, arg_rpr_esz *a) |
cda3c753 | 4885 | { |
95365277 SL |
4886 | if (a->esz == 0) { |
4887 | return false; | |
4888 | } | |
4889 | return do_frint_mode(s, a, float_round_nearest_even, frint_fns[a->esz - 1]); | |
cda3c753 RH |
4890 | } |
4891 | ||
3a7be554 | 4892 | static bool trans_FRINTP(DisasContext *s, arg_rpr_esz *a) |
cda3c753 | 4893 | { |
95365277 SL |
4894 | if (a->esz == 0) { |
4895 | return false; | |
4896 | } | |
4897 | return do_frint_mode(s, a, float_round_up, frint_fns[a->esz - 1]); | |
cda3c753 RH |
4898 | } |
4899 | ||
3a7be554 | 4900 | static bool trans_FRINTM(DisasContext *s, arg_rpr_esz *a) |
cda3c753 | 4901 | { |
95365277 SL |
4902 | if (a->esz == 0) { |
4903 | return false; | |
4904 | } | |
4905 | return do_frint_mode(s, a, float_round_down, frint_fns[a->esz - 1]); | |
cda3c753 RH |
4906 | } |
4907 | ||
3a7be554 | 4908 | static bool trans_FRINTZ(DisasContext *s, arg_rpr_esz *a) |
cda3c753 | 4909 | { |
95365277 SL |
4910 | if (a->esz == 0) { |
4911 | return false; | |
4912 | } | |
4913 | return do_frint_mode(s, a, float_round_to_zero, frint_fns[a->esz - 1]); | |
cda3c753 RH |
4914 | } |
4915 | ||
3a7be554 | 4916 | static bool trans_FRINTA(DisasContext *s, arg_rpr_esz *a) |
cda3c753 | 4917 | { |
95365277 SL |
4918 | if (a->esz == 0) { |
4919 | return false; | |
4920 | } | |
4921 | return do_frint_mode(s, a, float_round_ties_away, frint_fns[a->esz - 1]); | |
cda3c753 RH |
4922 | } |
4923 | ||
3a7be554 | 4924 | static bool trans_FRECPX(DisasContext *s, arg_rpr_esz *a) |
ec5b375b RH |
4925 | { |
4926 | static gen_helper_gvec_3_ptr * const fns[3] = { | |
4927 | gen_helper_sve_frecpx_h, | |
4928 | gen_helper_sve_frecpx_s, | |
4929 | gen_helper_sve_frecpx_d | |
4930 | }; | |
4931 | if (a->esz == 0) { | |
4932 | return false; | |
4933 | } | |
4934 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, a->esz == MO_16, fns[a->esz - 1]); | |
4935 | } | |
4936 | ||
3a7be554 | 4937 | static bool trans_FSQRT(DisasContext *s, arg_rpr_esz *a) |
ec5b375b RH |
4938 | { |
4939 | static gen_helper_gvec_3_ptr * const fns[3] = { | |
4940 | gen_helper_sve_fsqrt_h, | |
4941 | gen_helper_sve_fsqrt_s, | |
4942 | gen_helper_sve_fsqrt_d | |
4943 | }; | |
4944 | if (a->esz == 0) { | |
4945 | return false; | |
4946 | } | |
4947 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, a->esz == MO_16, fns[a->esz - 1]); | |
4948 | } | |
4949 | ||
3a7be554 | 4950 | static bool trans_SCVTF_hh(DisasContext *s, arg_rpr_esz *a) |
8092c6a3 RH |
4951 | { |
4952 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_scvt_hh); | |
4953 | } | |
4954 | ||
3a7be554 | 4955 | static bool trans_SCVTF_sh(DisasContext *s, arg_rpr_esz *a) |
8092c6a3 RH |
4956 | { |
4957 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_scvt_sh); | |
4958 | } | |
4959 | ||
3a7be554 | 4960 | static bool trans_SCVTF_dh(DisasContext *s, arg_rpr_esz *a) |
8092c6a3 RH |
4961 | { |
4962 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_scvt_dh); | |
4963 | } | |
4964 | ||
3a7be554 | 4965 | static bool trans_SCVTF_ss(DisasContext *s, arg_rpr_esz *a) |
8092c6a3 RH |
4966 | { |
4967 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_scvt_ss); | |
4968 | } | |
4969 | ||
3a7be554 | 4970 | static bool trans_SCVTF_ds(DisasContext *s, arg_rpr_esz *a) |
8092c6a3 RH |
4971 | { |
4972 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_scvt_ds); | |
4973 | } | |
4974 | ||
3a7be554 | 4975 | static bool trans_SCVTF_sd(DisasContext *s, arg_rpr_esz *a) |
8092c6a3 RH |
4976 | { |
4977 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_scvt_sd); | |
4978 | } | |
4979 | ||
3a7be554 | 4980 | static bool trans_SCVTF_dd(DisasContext *s, arg_rpr_esz *a) |
8092c6a3 RH |
4981 | { |
4982 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_scvt_dd); | |
4983 | } | |
4984 | ||
3a7be554 | 4985 | static bool trans_UCVTF_hh(DisasContext *s, arg_rpr_esz *a) |
8092c6a3 RH |
4986 | { |
4987 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_ucvt_hh); | |
4988 | } | |
4989 | ||
3a7be554 | 4990 | static bool trans_UCVTF_sh(DisasContext *s, arg_rpr_esz *a) |
8092c6a3 RH |
4991 | { |
4992 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_ucvt_sh); | |
4993 | } | |
4994 | ||
3a7be554 | 4995 | static bool trans_UCVTF_dh(DisasContext *s, arg_rpr_esz *a) |
8092c6a3 RH |
4996 | { |
4997 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_ucvt_dh); | |
4998 | } | |
4999 | ||
3a7be554 | 5000 | static bool trans_UCVTF_ss(DisasContext *s, arg_rpr_esz *a) |
8092c6a3 RH |
5001 | { |
5002 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_ucvt_ss); | |
5003 | } | |
5004 | ||
3a7be554 | 5005 | static bool trans_UCVTF_ds(DisasContext *s, arg_rpr_esz *a) |
8092c6a3 RH |
5006 | { |
5007 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_ucvt_ds); | |
5008 | } | |
5009 | ||
3a7be554 | 5010 | static bool trans_UCVTF_sd(DisasContext *s, arg_rpr_esz *a) |
8092c6a3 RH |
5011 | { |
5012 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_ucvt_sd); | |
5013 | } | |
5014 | ||
3a7be554 | 5015 | static bool trans_UCVTF_dd(DisasContext *s, arg_rpr_esz *a) |
8092c6a3 RH |
5016 | { |
5017 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_ucvt_dd); | |
5018 | } | |
5019 | ||
d1822297 RH |
5020 | /* |
5021 | *** SVE Memory - 32-bit Gather and Unsized Contiguous Group | |
5022 | */ | |
5023 | ||
5024 | /* Subroutine loading a vector register at VOFS of LEN bytes. | |
5025 | * The load should begin at the address Rn + IMM. | |
5026 | */ | |
5027 | ||
19f2acc9 | 5028 | static void do_ldr(DisasContext *s, uint32_t vofs, int len, int rn, int imm) |
d1822297 | 5029 | { |
19f2acc9 RH |
5030 | int len_align = QEMU_ALIGN_DOWN(len, 8); |
5031 | int len_remain = len % 8; | |
5032 | int nparts = len / 8 + ctpop8(len_remain); | |
d1822297 | 5033 | int midx = get_mem_index(s); |
b2aa8879 | 5034 | TCGv_i64 dirty_addr, clean_addr, t0, t1; |
d1822297 | 5035 | |
b2aa8879 RH |
5036 | dirty_addr = tcg_temp_new_i64(); |
5037 | tcg_gen_addi_i64(dirty_addr, cpu_reg_sp(s, rn), imm); | |
33e74c31 | 5038 | clean_addr = gen_mte_checkN(s, dirty_addr, false, rn != 31, len); |
b2aa8879 | 5039 | tcg_temp_free_i64(dirty_addr); |
d1822297 | 5040 | |
b2aa8879 RH |
5041 | /* |
5042 | * Note that unpredicated load/store of vector/predicate registers | |
d1822297 | 5043 | * are defined as a stream of bytes, which equates to little-endian |
b2aa8879 | 5044 | * operations on larger quantities. |
d1822297 RH |
5045 | * Attempt to keep code expansion to a minimum by limiting the |
5046 | * amount of unrolling done. | |
5047 | */ | |
5048 | if (nparts <= 4) { | |
5049 | int i; | |
5050 | ||
b2aa8879 | 5051 | t0 = tcg_temp_new_i64(); |
d1822297 | 5052 | for (i = 0; i < len_align; i += 8) { |
fc313c64 | 5053 | tcg_gen_qemu_ld_i64(t0, clean_addr, midx, MO_LEUQ); |
d1822297 | 5054 | tcg_gen_st_i64(t0, cpu_env, vofs + i); |
d8227b09 | 5055 | tcg_gen_addi_i64(clean_addr, clean_addr, 8); |
d1822297 | 5056 | } |
b2aa8879 | 5057 | tcg_temp_free_i64(t0); |
d1822297 RH |
5058 | } else { |
5059 | TCGLabel *loop = gen_new_label(); | |
5060 | TCGv_ptr tp, i = tcg_const_local_ptr(0); | |
5061 | ||
b2aa8879 RH |
5062 | /* Copy the clean address into a local temp, live across the loop. */ |
5063 | t0 = clean_addr; | |
4b4dc975 | 5064 | clean_addr = new_tmp_a64_local(s); |
b2aa8879 | 5065 | tcg_gen_mov_i64(clean_addr, t0); |
d1822297 | 5066 | |
b2aa8879 | 5067 | gen_set_label(loop); |
d1822297 | 5068 | |
b2aa8879 | 5069 | t0 = tcg_temp_new_i64(); |
fc313c64 | 5070 | tcg_gen_qemu_ld_i64(t0, clean_addr, midx, MO_LEUQ); |
b2aa8879 | 5071 | tcg_gen_addi_i64(clean_addr, clean_addr, 8); |
d1822297 | 5072 | |
b2aa8879 | 5073 | tp = tcg_temp_new_ptr(); |
d1822297 RH |
5074 | tcg_gen_add_ptr(tp, cpu_env, i); |
5075 | tcg_gen_addi_ptr(i, i, 8); | |
5076 | tcg_gen_st_i64(t0, tp, vofs); | |
5077 | tcg_temp_free_ptr(tp); | |
b2aa8879 | 5078 | tcg_temp_free_i64(t0); |
d1822297 RH |
5079 | |
5080 | tcg_gen_brcondi_ptr(TCG_COND_LTU, i, len_align, loop); | |
5081 | tcg_temp_free_ptr(i); | |
5082 | } | |
5083 | ||
b2aa8879 RH |
5084 | /* |
5085 | * Predicate register loads can be any multiple of 2. | |
d1822297 RH |
5086 | * Note that we still store the entire 64-bit unit into cpu_env. |
5087 | */ | |
5088 | if (len_remain) { | |
b2aa8879 | 5089 | t0 = tcg_temp_new_i64(); |
d1822297 RH |
5090 | switch (len_remain) { |
5091 | case 2: | |
5092 | case 4: | |
5093 | case 8: | |
b2aa8879 RH |
5094 | tcg_gen_qemu_ld_i64(t0, clean_addr, midx, |
5095 | MO_LE | ctz32(len_remain)); | |
d1822297 RH |
5096 | break; |
5097 | ||
5098 | case 6: | |
5099 | t1 = tcg_temp_new_i64(); | |
b2aa8879 RH |
5100 | tcg_gen_qemu_ld_i64(t0, clean_addr, midx, MO_LEUL); |
5101 | tcg_gen_addi_i64(clean_addr, clean_addr, 4); | |
5102 | tcg_gen_qemu_ld_i64(t1, clean_addr, midx, MO_LEUW); | |
d1822297 RH |
5103 | tcg_gen_deposit_i64(t0, t0, t1, 32, 32); |
5104 | tcg_temp_free_i64(t1); | |
5105 | break; | |
5106 | ||
5107 | default: | |
5108 | g_assert_not_reached(); | |
5109 | } | |
5110 | tcg_gen_st_i64(t0, cpu_env, vofs + len_align); | |
b2aa8879 | 5111 | tcg_temp_free_i64(t0); |
d1822297 | 5112 | } |
d1822297 RH |
5113 | } |
5114 | ||
5047c204 | 5115 | /* Similarly for stores. */ |
19f2acc9 | 5116 | static void do_str(DisasContext *s, uint32_t vofs, int len, int rn, int imm) |
5047c204 | 5117 | { |
19f2acc9 RH |
5118 | int len_align = QEMU_ALIGN_DOWN(len, 8); |
5119 | int len_remain = len % 8; | |
5120 | int nparts = len / 8 + ctpop8(len_remain); | |
5047c204 | 5121 | int midx = get_mem_index(s); |
bba87d0a | 5122 | TCGv_i64 dirty_addr, clean_addr, t0; |
5047c204 | 5123 | |
bba87d0a RH |
5124 | dirty_addr = tcg_temp_new_i64(); |
5125 | tcg_gen_addi_i64(dirty_addr, cpu_reg_sp(s, rn), imm); | |
33e74c31 | 5126 | clean_addr = gen_mte_checkN(s, dirty_addr, false, rn != 31, len); |
bba87d0a | 5127 | tcg_temp_free_i64(dirty_addr); |
5047c204 RH |
5128 | |
5129 | /* Note that unpredicated load/store of vector/predicate registers | |
5130 | * are defined as a stream of bytes, which equates to little-endian | |
5131 | * operations on larger quantities. There is no nice way to force | |
5132 | * a little-endian store for aarch64_be-linux-user out of line. | |
5133 | * | |
5134 | * Attempt to keep code expansion to a minimum by limiting the | |
5135 | * amount of unrolling done. | |
5136 | */ | |
5137 | if (nparts <= 4) { | |
5138 | int i; | |
5139 | ||
bba87d0a | 5140 | t0 = tcg_temp_new_i64(); |
5047c204 RH |
5141 | for (i = 0; i < len_align; i += 8) { |
5142 | tcg_gen_ld_i64(t0, cpu_env, vofs + i); | |
fc313c64 | 5143 | tcg_gen_qemu_st_i64(t0, clean_addr, midx, MO_LEUQ); |
d8227b09 | 5144 | tcg_gen_addi_i64(clean_addr, clean_addr, 8); |
5047c204 | 5145 | } |
bba87d0a | 5146 | tcg_temp_free_i64(t0); |
5047c204 RH |
5147 | } else { |
5148 | TCGLabel *loop = gen_new_label(); | |
bba87d0a | 5149 | TCGv_ptr tp, i = tcg_const_local_ptr(0); |
5047c204 | 5150 | |
bba87d0a RH |
5151 | /* Copy the clean address into a local temp, live across the loop. */ |
5152 | t0 = clean_addr; | |
4b4dc975 | 5153 | clean_addr = new_tmp_a64_local(s); |
bba87d0a | 5154 | tcg_gen_mov_i64(clean_addr, t0); |
5047c204 | 5155 | |
bba87d0a | 5156 | gen_set_label(loop); |
5047c204 | 5157 | |
bba87d0a RH |
5158 | t0 = tcg_temp_new_i64(); |
5159 | tp = tcg_temp_new_ptr(); | |
5160 | tcg_gen_add_ptr(tp, cpu_env, i); | |
5161 | tcg_gen_ld_i64(t0, tp, vofs); | |
5047c204 | 5162 | tcg_gen_addi_ptr(i, i, 8); |
bba87d0a RH |
5163 | tcg_temp_free_ptr(tp); |
5164 | ||
fc313c64 | 5165 | tcg_gen_qemu_st_i64(t0, clean_addr, midx, MO_LEUQ); |
bba87d0a RH |
5166 | tcg_gen_addi_i64(clean_addr, clean_addr, 8); |
5167 | tcg_temp_free_i64(t0); | |
5047c204 RH |
5168 | |
5169 | tcg_gen_brcondi_ptr(TCG_COND_LTU, i, len_align, loop); | |
5170 | tcg_temp_free_ptr(i); | |
5171 | } | |
5172 | ||
5173 | /* Predicate register stores can be any multiple of 2. */ | |
5174 | if (len_remain) { | |
bba87d0a | 5175 | t0 = tcg_temp_new_i64(); |
5047c204 | 5176 | tcg_gen_ld_i64(t0, cpu_env, vofs + len_align); |
5047c204 RH |
5177 | |
5178 | switch (len_remain) { | |
5179 | case 2: | |
5180 | case 4: | |
5181 | case 8: | |
bba87d0a RH |
5182 | tcg_gen_qemu_st_i64(t0, clean_addr, midx, |
5183 | MO_LE | ctz32(len_remain)); | |
5047c204 RH |
5184 | break; |
5185 | ||
5186 | case 6: | |
bba87d0a RH |
5187 | tcg_gen_qemu_st_i64(t0, clean_addr, midx, MO_LEUL); |
5188 | tcg_gen_addi_i64(clean_addr, clean_addr, 4); | |
5047c204 | 5189 | tcg_gen_shri_i64(t0, t0, 32); |
bba87d0a | 5190 | tcg_gen_qemu_st_i64(t0, clean_addr, midx, MO_LEUW); |
5047c204 RH |
5191 | break; |
5192 | ||
5193 | default: | |
5194 | g_assert_not_reached(); | |
5195 | } | |
bba87d0a | 5196 | tcg_temp_free_i64(t0); |
5047c204 | 5197 | } |
5047c204 RH |
5198 | } |
5199 | ||
3a7be554 | 5200 | static bool trans_LDR_zri(DisasContext *s, arg_rri *a) |
d1822297 RH |
5201 | { |
5202 | if (sve_access_check(s)) { | |
5203 | int size = vec_full_reg_size(s); | |
5204 | int off = vec_full_reg_offset(s, a->rd); | |
5205 | do_ldr(s, off, size, a->rn, a->imm * size); | |
5206 | } | |
5207 | return true; | |
5208 | } | |
5209 | ||
3a7be554 | 5210 | static bool trans_LDR_pri(DisasContext *s, arg_rri *a) |
d1822297 RH |
5211 | { |
5212 | if (sve_access_check(s)) { | |
5213 | int size = pred_full_reg_size(s); | |
5214 | int off = pred_full_reg_offset(s, a->rd); | |
5215 | do_ldr(s, off, size, a->rn, a->imm * size); | |
5216 | } | |
5217 | return true; | |
5218 | } | |
c4e7c493 | 5219 | |
3a7be554 | 5220 | static bool trans_STR_zri(DisasContext *s, arg_rri *a) |
5047c204 RH |
5221 | { |
5222 | if (sve_access_check(s)) { | |
5223 | int size = vec_full_reg_size(s); | |
5224 | int off = vec_full_reg_offset(s, a->rd); | |
5225 | do_str(s, off, size, a->rn, a->imm * size); | |
5226 | } | |
5227 | return true; | |
5228 | } | |
5229 | ||
3a7be554 | 5230 | static bool trans_STR_pri(DisasContext *s, arg_rri *a) |
5047c204 RH |
5231 | { |
5232 | if (sve_access_check(s)) { | |
5233 | int size = pred_full_reg_size(s); | |
5234 | int off = pred_full_reg_offset(s, a->rd); | |
5235 | do_str(s, off, size, a->rn, a->imm * size); | |
5236 | } | |
5237 | return true; | |
5238 | } | |
5239 | ||
c4e7c493 RH |
5240 | /* |
5241 | *** SVE Memory - Contiguous Load Group | |
5242 | */ | |
5243 | ||
5244 | /* The memory mode of the dtype. */ | |
14776ab5 | 5245 | static const MemOp dtype_mop[16] = { |
c4e7c493 RH |
5246 | MO_UB, MO_UB, MO_UB, MO_UB, |
5247 | MO_SL, MO_UW, MO_UW, MO_UW, | |
5248 | MO_SW, MO_SW, MO_UL, MO_UL, | |
fc313c64 | 5249 | MO_SB, MO_SB, MO_SB, MO_UQ |
c4e7c493 RH |
5250 | }; |
5251 | ||
5252 | #define dtype_msz(x) (dtype_mop[x] & MO_SIZE) | |
5253 | ||
5254 | /* The vector element size of dtype. */ | |
5255 | static const uint8_t dtype_esz[16] = { | |
5256 | 0, 1, 2, 3, | |
5257 | 3, 1, 2, 3, | |
5258 | 3, 2, 2, 3, | |
5259 | 3, 2, 1, 3 | |
5260 | }; | |
5261 | ||
5262 | static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr, | |
206adacf RH |
5263 | int dtype, uint32_t mte_n, bool is_write, |
5264 | gen_helper_gvec_mem *fn) | |
c4e7c493 RH |
5265 | { |
5266 | unsigned vsz = vec_full_reg_size(s); | |
5267 | TCGv_ptr t_pg; | |
500d0484 | 5268 | TCGv_i32 t_desc; |
206adacf | 5269 | int desc = 0; |
c4e7c493 | 5270 | |
206adacf RH |
5271 | /* |
5272 | * For e.g. LD4, there are not enough arguments to pass all 4 | |
c4e7c493 RH |
5273 | * registers as pointers, so encode the regno into the data field. |
5274 | * For consistency, do this even for LD1. | |
5275 | */ | |
9473d0ec | 5276 | if (s->mte_active[0]) { |
206adacf RH |
5277 | int msz = dtype_msz(dtype); |
5278 | ||
5279 | desc = FIELD_DP32(desc, MTEDESC, MIDX, get_mem_index(s)); | |
5280 | desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid); | |
5281 | desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma); | |
5282 | desc = FIELD_DP32(desc, MTEDESC, WRITE, is_write); | |
28f32503 | 5283 | desc = FIELD_DP32(desc, MTEDESC, SIZEM1, (mte_n << msz) - 1); |
206adacf | 5284 | desc <<= SVE_MTEDESC_SHIFT; |
9473d0ec RH |
5285 | } else { |
5286 | addr = clean_data_tbi(s, addr); | |
206adacf | 5287 | } |
9473d0ec | 5288 | |
206adacf | 5289 | desc = simd_desc(vsz, vsz, zt | desc); |
500d0484 | 5290 | t_desc = tcg_const_i32(desc); |
c4e7c493 RH |
5291 | t_pg = tcg_temp_new_ptr(); |
5292 | ||
5293 | tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, pg)); | |
500d0484 | 5294 | fn(cpu_env, t_pg, addr, t_desc); |
c4e7c493 RH |
5295 | |
5296 | tcg_temp_free_ptr(t_pg); | |
500d0484 | 5297 | tcg_temp_free_i32(t_desc); |
c4e7c493 RH |
5298 | } |
5299 | ||
c182c6db RH |
5300 | /* Indexed by [mte][be][dtype][nreg] */ |
5301 | static gen_helper_gvec_mem * const ldr_fns[2][2][16][4] = { | |
5302 | { /* mte inactive, little-endian */ | |
5303 | { { gen_helper_sve_ld1bb_r, gen_helper_sve_ld2bb_r, | |
5304 | gen_helper_sve_ld3bb_r, gen_helper_sve_ld4bb_r }, | |
5305 | { gen_helper_sve_ld1bhu_r, NULL, NULL, NULL }, | |
5306 | { gen_helper_sve_ld1bsu_r, NULL, NULL, NULL }, | |
5307 | { gen_helper_sve_ld1bdu_r, NULL, NULL, NULL }, | |
5308 | ||
5309 | { gen_helper_sve_ld1sds_le_r, NULL, NULL, NULL }, | |
5310 | { gen_helper_sve_ld1hh_le_r, gen_helper_sve_ld2hh_le_r, | |
5311 | gen_helper_sve_ld3hh_le_r, gen_helper_sve_ld4hh_le_r }, | |
5312 | { gen_helper_sve_ld1hsu_le_r, NULL, NULL, NULL }, | |
5313 | { gen_helper_sve_ld1hdu_le_r, NULL, NULL, NULL }, | |
5314 | ||
5315 | { gen_helper_sve_ld1hds_le_r, NULL, NULL, NULL }, | |
5316 | { gen_helper_sve_ld1hss_le_r, NULL, NULL, NULL }, | |
5317 | { gen_helper_sve_ld1ss_le_r, gen_helper_sve_ld2ss_le_r, | |
5318 | gen_helper_sve_ld3ss_le_r, gen_helper_sve_ld4ss_le_r }, | |
5319 | { gen_helper_sve_ld1sdu_le_r, NULL, NULL, NULL }, | |
5320 | ||
5321 | { gen_helper_sve_ld1bds_r, NULL, NULL, NULL }, | |
5322 | { gen_helper_sve_ld1bss_r, NULL, NULL, NULL }, | |
5323 | { gen_helper_sve_ld1bhs_r, NULL, NULL, NULL }, | |
5324 | { gen_helper_sve_ld1dd_le_r, gen_helper_sve_ld2dd_le_r, | |
5325 | gen_helper_sve_ld3dd_le_r, gen_helper_sve_ld4dd_le_r } }, | |
5326 | ||
5327 | /* mte inactive, big-endian */ | |
5328 | { { gen_helper_sve_ld1bb_r, gen_helper_sve_ld2bb_r, | |
5329 | gen_helper_sve_ld3bb_r, gen_helper_sve_ld4bb_r }, | |
5330 | { gen_helper_sve_ld1bhu_r, NULL, NULL, NULL }, | |
5331 | { gen_helper_sve_ld1bsu_r, NULL, NULL, NULL }, | |
5332 | { gen_helper_sve_ld1bdu_r, NULL, NULL, NULL }, | |
5333 | ||
5334 | { gen_helper_sve_ld1sds_be_r, NULL, NULL, NULL }, | |
5335 | { gen_helper_sve_ld1hh_be_r, gen_helper_sve_ld2hh_be_r, | |
5336 | gen_helper_sve_ld3hh_be_r, gen_helper_sve_ld4hh_be_r }, | |
5337 | { gen_helper_sve_ld1hsu_be_r, NULL, NULL, NULL }, | |
5338 | { gen_helper_sve_ld1hdu_be_r, NULL, NULL, NULL }, | |
5339 | ||
5340 | { gen_helper_sve_ld1hds_be_r, NULL, NULL, NULL }, | |
5341 | { gen_helper_sve_ld1hss_be_r, NULL, NULL, NULL }, | |
5342 | { gen_helper_sve_ld1ss_be_r, gen_helper_sve_ld2ss_be_r, | |
5343 | gen_helper_sve_ld3ss_be_r, gen_helper_sve_ld4ss_be_r }, | |
5344 | { gen_helper_sve_ld1sdu_be_r, NULL, NULL, NULL }, | |
5345 | ||
5346 | { gen_helper_sve_ld1bds_r, NULL, NULL, NULL }, | |
5347 | { gen_helper_sve_ld1bss_r, NULL, NULL, NULL }, | |
5348 | { gen_helper_sve_ld1bhs_r, NULL, NULL, NULL }, | |
5349 | { gen_helper_sve_ld1dd_be_r, gen_helper_sve_ld2dd_be_r, | |
5350 | gen_helper_sve_ld3dd_be_r, gen_helper_sve_ld4dd_be_r } } }, | |
5351 | ||
5352 | { /* mte active, little-endian */ | |
5353 | { { gen_helper_sve_ld1bb_r_mte, | |
5354 | gen_helper_sve_ld2bb_r_mte, | |
5355 | gen_helper_sve_ld3bb_r_mte, | |
5356 | gen_helper_sve_ld4bb_r_mte }, | |
5357 | { gen_helper_sve_ld1bhu_r_mte, NULL, NULL, NULL }, | |
5358 | { gen_helper_sve_ld1bsu_r_mte, NULL, NULL, NULL }, | |
5359 | { gen_helper_sve_ld1bdu_r_mte, NULL, NULL, NULL }, | |
5360 | ||
5361 | { gen_helper_sve_ld1sds_le_r_mte, NULL, NULL, NULL }, | |
5362 | { gen_helper_sve_ld1hh_le_r_mte, | |
5363 | gen_helper_sve_ld2hh_le_r_mte, | |
5364 | gen_helper_sve_ld3hh_le_r_mte, | |
5365 | gen_helper_sve_ld4hh_le_r_mte }, | |
5366 | { gen_helper_sve_ld1hsu_le_r_mte, NULL, NULL, NULL }, | |
5367 | { gen_helper_sve_ld1hdu_le_r_mte, NULL, NULL, NULL }, | |
5368 | ||
5369 | { gen_helper_sve_ld1hds_le_r_mte, NULL, NULL, NULL }, | |
5370 | { gen_helper_sve_ld1hss_le_r_mte, NULL, NULL, NULL }, | |
5371 | { gen_helper_sve_ld1ss_le_r_mte, | |
5372 | gen_helper_sve_ld2ss_le_r_mte, | |
5373 | gen_helper_sve_ld3ss_le_r_mte, | |
5374 | gen_helper_sve_ld4ss_le_r_mte }, | |
5375 | { gen_helper_sve_ld1sdu_le_r_mte, NULL, NULL, NULL }, | |
5376 | ||
5377 | { gen_helper_sve_ld1bds_r_mte, NULL, NULL, NULL }, | |
5378 | { gen_helper_sve_ld1bss_r_mte, NULL, NULL, NULL }, | |
5379 | { gen_helper_sve_ld1bhs_r_mte, NULL, NULL, NULL }, | |
5380 | { gen_helper_sve_ld1dd_le_r_mte, | |
5381 | gen_helper_sve_ld2dd_le_r_mte, | |
5382 | gen_helper_sve_ld3dd_le_r_mte, | |
5383 | gen_helper_sve_ld4dd_le_r_mte } }, | |
5384 | ||
5385 | /* mte active, big-endian */ | |
5386 | { { gen_helper_sve_ld1bb_r_mte, | |
5387 | gen_helper_sve_ld2bb_r_mte, | |
5388 | gen_helper_sve_ld3bb_r_mte, | |
5389 | gen_helper_sve_ld4bb_r_mte }, | |
5390 | { gen_helper_sve_ld1bhu_r_mte, NULL, NULL, NULL }, | |
5391 | { gen_helper_sve_ld1bsu_r_mte, NULL, NULL, NULL }, | |
5392 | { gen_helper_sve_ld1bdu_r_mte, NULL, NULL, NULL }, | |
5393 | ||
5394 | { gen_helper_sve_ld1sds_be_r_mte, NULL, NULL, NULL }, | |
5395 | { gen_helper_sve_ld1hh_be_r_mte, | |
5396 | gen_helper_sve_ld2hh_be_r_mte, | |
5397 | gen_helper_sve_ld3hh_be_r_mte, | |
5398 | gen_helper_sve_ld4hh_be_r_mte }, | |
5399 | { gen_helper_sve_ld1hsu_be_r_mte, NULL, NULL, NULL }, | |
5400 | { gen_helper_sve_ld1hdu_be_r_mte, NULL, NULL, NULL }, | |
5401 | ||
5402 | { gen_helper_sve_ld1hds_be_r_mte, NULL, NULL, NULL }, | |
5403 | { gen_helper_sve_ld1hss_be_r_mte, NULL, NULL, NULL }, | |
5404 | { gen_helper_sve_ld1ss_be_r_mte, | |
5405 | gen_helper_sve_ld2ss_be_r_mte, | |
5406 | gen_helper_sve_ld3ss_be_r_mte, | |
5407 | gen_helper_sve_ld4ss_be_r_mte }, | |
5408 | { gen_helper_sve_ld1sdu_be_r_mte, NULL, NULL, NULL }, | |
5409 | ||
5410 | { gen_helper_sve_ld1bds_r_mte, NULL, NULL, NULL }, | |
5411 | { gen_helper_sve_ld1bss_r_mte, NULL, NULL, NULL }, | |
5412 | { gen_helper_sve_ld1bhs_r_mte, NULL, NULL, NULL }, | |
5413 | { gen_helper_sve_ld1dd_be_r_mte, | |
5414 | gen_helper_sve_ld2dd_be_r_mte, | |
5415 | gen_helper_sve_ld3dd_be_r_mte, | |
5416 | gen_helper_sve_ld4dd_be_r_mte } } }, | |
5417 | }; | |
5418 | ||
c4e7c493 RH |
5419 | static void do_ld_zpa(DisasContext *s, int zt, int pg, |
5420 | TCGv_i64 addr, int dtype, int nreg) | |
5421 | { | |
206adacf | 5422 | gen_helper_gvec_mem *fn |
c182c6db | 5423 | = ldr_fns[s->mte_active[0]][s->be_data == MO_BE][dtype][nreg]; |
c4e7c493 | 5424 | |
206adacf RH |
5425 | /* |
5426 | * While there are holes in the table, they are not | |
c4e7c493 RH |
5427 | * accessible via the instruction encoding. |
5428 | */ | |
5429 | assert(fn != NULL); | |
206adacf | 5430 | do_mem_zpa(s, zt, pg, addr, dtype, nreg, false, fn); |
c4e7c493 RH |
5431 | } |
5432 | ||
3a7be554 | 5433 | static bool trans_LD_zprr(DisasContext *s, arg_rprr_load *a) |
c4e7c493 RH |
5434 | { |
5435 | if (a->rm == 31) { | |
5436 | return false; | |
5437 | } | |
5438 | if (sve_access_check(s)) { | |
5439 | TCGv_i64 addr = new_tmp_a64(s); | |
50ef1cbf | 5440 | tcg_gen_shli_i64(addr, cpu_reg(s, a->rm), dtype_msz(a->dtype)); |
c4e7c493 RH |
5441 | tcg_gen_add_i64(addr, addr, cpu_reg_sp(s, a->rn)); |
5442 | do_ld_zpa(s, a->rd, a->pg, addr, a->dtype, a->nreg); | |
5443 | } | |
5444 | return true; | |
5445 | } | |
5446 | ||
3a7be554 | 5447 | static bool trans_LD_zpri(DisasContext *s, arg_rpri_load *a) |
c4e7c493 RH |
5448 | { |
5449 | if (sve_access_check(s)) { | |
5450 | int vsz = vec_full_reg_size(s); | |
5451 | int elements = vsz >> dtype_esz[a->dtype]; | |
5452 | TCGv_i64 addr = new_tmp_a64(s); | |
5453 | ||
5454 | tcg_gen_addi_i64(addr, cpu_reg_sp(s, a->rn), | |
5455 | (a->imm * elements * (a->nreg + 1)) | |
5456 | << dtype_msz(a->dtype)); | |
5457 | do_ld_zpa(s, a->rd, a->pg, addr, a->dtype, a->nreg); | |
5458 | } | |
5459 | return true; | |
5460 | } | |
e2654d75 | 5461 | |
3a7be554 | 5462 | static bool trans_LDFF1_zprr(DisasContext *s, arg_rprr_load *a) |
e2654d75 | 5463 | { |
aa13f7c3 RH |
5464 | static gen_helper_gvec_mem * const fns[2][2][16] = { |
5465 | { /* mte inactive, little-endian */ | |
5466 | { gen_helper_sve_ldff1bb_r, | |
5467 | gen_helper_sve_ldff1bhu_r, | |
5468 | gen_helper_sve_ldff1bsu_r, | |
5469 | gen_helper_sve_ldff1bdu_r, | |
5470 | ||
5471 | gen_helper_sve_ldff1sds_le_r, | |
5472 | gen_helper_sve_ldff1hh_le_r, | |
5473 | gen_helper_sve_ldff1hsu_le_r, | |
5474 | gen_helper_sve_ldff1hdu_le_r, | |
5475 | ||
5476 | gen_helper_sve_ldff1hds_le_r, | |
5477 | gen_helper_sve_ldff1hss_le_r, | |
5478 | gen_helper_sve_ldff1ss_le_r, | |
5479 | gen_helper_sve_ldff1sdu_le_r, | |
5480 | ||
5481 | gen_helper_sve_ldff1bds_r, | |
5482 | gen_helper_sve_ldff1bss_r, | |
5483 | gen_helper_sve_ldff1bhs_r, | |
5484 | gen_helper_sve_ldff1dd_le_r }, | |
5485 | ||
5486 | /* mte inactive, big-endian */ | |
5487 | { gen_helper_sve_ldff1bb_r, | |
5488 | gen_helper_sve_ldff1bhu_r, | |
5489 | gen_helper_sve_ldff1bsu_r, | |
5490 | gen_helper_sve_ldff1bdu_r, | |
5491 | ||
5492 | gen_helper_sve_ldff1sds_be_r, | |
5493 | gen_helper_sve_ldff1hh_be_r, | |
5494 | gen_helper_sve_ldff1hsu_be_r, | |
5495 | gen_helper_sve_ldff1hdu_be_r, | |
5496 | ||
5497 | gen_helper_sve_ldff1hds_be_r, | |
5498 | gen_helper_sve_ldff1hss_be_r, | |
5499 | gen_helper_sve_ldff1ss_be_r, | |
5500 | gen_helper_sve_ldff1sdu_be_r, | |
5501 | ||
5502 | gen_helper_sve_ldff1bds_r, | |
5503 | gen_helper_sve_ldff1bss_r, | |
5504 | gen_helper_sve_ldff1bhs_r, | |
5505 | gen_helper_sve_ldff1dd_be_r } }, | |
5506 | ||
5507 | { /* mte active, little-endian */ | |
5508 | { gen_helper_sve_ldff1bb_r_mte, | |
5509 | gen_helper_sve_ldff1bhu_r_mte, | |
5510 | gen_helper_sve_ldff1bsu_r_mte, | |
5511 | gen_helper_sve_ldff1bdu_r_mte, | |
5512 | ||
5513 | gen_helper_sve_ldff1sds_le_r_mte, | |
5514 | gen_helper_sve_ldff1hh_le_r_mte, | |
5515 | gen_helper_sve_ldff1hsu_le_r_mte, | |
5516 | gen_helper_sve_ldff1hdu_le_r_mte, | |
5517 | ||
5518 | gen_helper_sve_ldff1hds_le_r_mte, | |
5519 | gen_helper_sve_ldff1hss_le_r_mte, | |
5520 | gen_helper_sve_ldff1ss_le_r_mte, | |
5521 | gen_helper_sve_ldff1sdu_le_r_mte, | |
5522 | ||
5523 | gen_helper_sve_ldff1bds_r_mte, | |
5524 | gen_helper_sve_ldff1bss_r_mte, | |
5525 | gen_helper_sve_ldff1bhs_r_mte, | |
5526 | gen_helper_sve_ldff1dd_le_r_mte }, | |
5527 | ||
5528 | /* mte active, big-endian */ | |
5529 | { gen_helper_sve_ldff1bb_r_mte, | |
5530 | gen_helper_sve_ldff1bhu_r_mte, | |
5531 | gen_helper_sve_ldff1bsu_r_mte, | |
5532 | gen_helper_sve_ldff1bdu_r_mte, | |
5533 | ||
5534 | gen_helper_sve_ldff1sds_be_r_mte, | |
5535 | gen_helper_sve_ldff1hh_be_r_mte, | |
5536 | gen_helper_sve_ldff1hsu_be_r_mte, | |
5537 | gen_helper_sve_ldff1hdu_be_r_mte, | |
5538 | ||
5539 | gen_helper_sve_ldff1hds_be_r_mte, | |
5540 | gen_helper_sve_ldff1hss_be_r_mte, | |
5541 | gen_helper_sve_ldff1ss_be_r_mte, | |
5542 | gen_helper_sve_ldff1sdu_be_r_mte, | |
5543 | ||
5544 | gen_helper_sve_ldff1bds_r_mte, | |
5545 | gen_helper_sve_ldff1bss_r_mte, | |
5546 | gen_helper_sve_ldff1bhs_r_mte, | |
5547 | gen_helper_sve_ldff1dd_be_r_mte } }, | |
e2654d75 RH |
5548 | }; |
5549 | ||
5550 | if (sve_access_check(s)) { | |
5551 | TCGv_i64 addr = new_tmp_a64(s); | |
5552 | tcg_gen_shli_i64(addr, cpu_reg(s, a->rm), dtype_msz(a->dtype)); | |
5553 | tcg_gen_add_i64(addr, addr, cpu_reg_sp(s, a->rn)); | |
aa13f7c3 RH |
5554 | do_mem_zpa(s, a->rd, a->pg, addr, a->dtype, 1, false, |
5555 | fns[s->mte_active[0]][s->be_data == MO_BE][a->dtype]); | |
e2654d75 RH |
5556 | } |
5557 | return true; | |
5558 | } | |
5559 | ||
3a7be554 | 5560 | static bool trans_LDNF1_zpri(DisasContext *s, arg_rpri_load *a) |
e2654d75 | 5561 | { |
aa13f7c3 RH |
5562 | static gen_helper_gvec_mem * const fns[2][2][16] = { |
5563 | { /* mte inactive, little-endian */ | |
5564 | { gen_helper_sve_ldnf1bb_r, | |
5565 | gen_helper_sve_ldnf1bhu_r, | |
5566 | gen_helper_sve_ldnf1bsu_r, | |
5567 | gen_helper_sve_ldnf1bdu_r, | |
5568 | ||
5569 | gen_helper_sve_ldnf1sds_le_r, | |
5570 | gen_helper_sve_ldnf1hh_le_r, | |
5571 | gen_helper_sve_ldnf1hsu_le_r, | |
5572 | gen_helper_sve_ldnf1hdu_le_r, | |
5573 | ||
5574 | gen_helper_sve_ldnf1hds_le_r, | |
5575 | gen_helper_sve_ldnf1hss_le_r, | |
5576 | gen_helper_sve_ldnf1ss_le_r, | |
5577 | gen_helper_sve_ldnf1sdu_le_r, | |
5578 | ||
5579 | gen_helper_sve_ldnf1bds_r, | |
5580 | gen_helper_sve_ldnf1bss_r, | |
5581 | gen_helper_sve_ldnf1bhs_r, | |
5582 | gen_helper_sve_ldnf1dd_le_r }, | |
5583 | ||
5584 | /* mte inactive, big-endian */ | |
5585 | { gen_helper_sve_ldnf1bb_r, | |
5586 | gen_helper_sve_ldnf1bhu_r, | |
5587 | gen_helper_sve_ldnf1bsu_r, | |
5588 | gen_helper_sve_ldnf1bdu_r, | |
5589 | ||
5590 | gen_helper_sve_ldnf1sds_be_r, | |
5591 | gen_helper_sve_ldnf1hh_be_r, | |
5592 | gen_helper_sve_ldnf1hsu_be_r, | |
5593 | gen_helper_sve_ldnf1hdu_be_r, | |
5594 | ||
5595 | gen_helper_sve_ldnf1hds_be_r, | |
5596 | gen_helper_sve_ldnf1hss_be_r, | |
5597 | gen_helper_sve_ldnf1ss_be_r, | |
5598 | gen_helper_sve_ldnf1sdu_be_r, | |
5599 | ||
5600 | gen_helper_sve_ldnf1bds_r, | |
5601 | gen_helper_sve_ldnf1bss_r, | |
5602 | gen_helper_sve_ldnf1bhs_r, | |
5603 | gen_helper_sve_ldnf1dd_be_r } }, | |
5604 | ||
5605 | { /* mte inactive, little-endian */ | |
5606 | { gen_helper_sve_ldnf1bb_r_mte, | |
5607 | gen_helper_sve_ldnf1bhu_r_mte, | |
5608 | gen_helper_sve_ldnf1bsu_r_mte, | |
5609 | gen_helper_sve_ldnf1bdu_r_mte, | |
5610 | ||
5611 | gen_helper_sve_ldnf1sds_le_r_mte, | |
5612 | gen_helper_sve_ldnf1hh_le_r_mte, | |
5613 | gen_helper_sve_ldnf1hsu_le_r_mte, | |
5614 | gen_helper_sve_ldnf1hdu_le_r_mte, | |
5615 | ||
5616 | gen_helper_sve_ldnf1hds_le_r_mte, | |
5617 | gen_helper_sve_ldnf1hss_le_r_mte, | |
5618 | gen_helper_sve_ldnf1ss_le_r_mte, | |
5619 | gen_helper_sve_ldnf1sdu_le_r_mte, | |
5620 | ||
5621 | gen_helper_sve_ldnf1bds_r_mte, | |
5622 | gen_helper_sve_ldnf1bss_r_mte, | |
5623 | gen_helper_sve_ldnf1bhs_r_mte, | |
5624 | gen_helper_sve_ldnf1dd_le_r_mte }, | |
5625 | ||
5626 | /* mte inactive, big-endian */ | |
5627 | { gen_helper_sve_ldnf1bb_r_mte, | |
5628 | gen_helper_sve_ldnf1bhu_r_mte, | |
5629 | gen_helper_sve_ldnf1bsu_r_mte, | |
5630 | gen_helper_sve_ldnf1bdu_r_mte, | |
5631 | ||
5632 | gen_helper_sve_ldnf1sds_be_r_mte, | |
5633 | gen_helper_sve_ldnf1hh_be_r_mte, | |
5634 | gen_helper_sve_ldnf1hsu_be_r_mte, | |
5635 | gen_helper_sve_ldnf1hdu_be_r_mte, | |
5636 | ||
5637 | gen_helper_sve_ldnf1hds_be_r_mte, | |
5638 | gen_helper_sve_ldnf1hss_be_r_mte, | |
5639 | gen_helper_sve_ldnf1ss_be_r_mte, | |
5640 | gen_helper_sve_ldnf1sdu_be_r_mte, | |
5641 | ||
5642 | gen_helper_sve_ldnf1bds_r_mte, | |
5643 | gen_helper_sve_ldnf1bss_r_mte, | |
5644 | gen_helper_sve_ldnf1bhs_r_mte, | |
5645 | gen_helper_sve_ldnf1dd_be_r_mte } }, | |
e2654d75 RH |
5646 | }; |
5647 | ||
5648 | if (sve_access_check(s)) { | |
5649 | int vsz = vec_full_reg_size(s); | |
5650 | int elements = vsz >> dtype_esz[a->dtype]; | |
5651 | int off = (a->imm * elements) << dtype_msz(a->dtype); | |
5652 | TCGv_i64 addr = new_tmp_a64(s); | |
5653 | ||
5654 | tcg_gen_addi_i64(addr, cpu_reg_sp(s, a->rn), off); | |
aa13f7c3 RH |
5655 | do_mem_zpa(s, a->rd, a->pg, addr, a->dtype, 1, false, |
5656 | fns[s->mte_active[0]][s->be_data == MO_BE][a->dtype]); | |
e2654d75 RH |
5657 | } |
5658 | return true; | |
5659 | } | |
1a039c7e | 5660 | |
c182c6db | 5661 | static void do_ldrq(DisasContext *s, int zt, int pg, TCGv_i64 addr, int dtype) |
05abe304 | 5662 | { |
05abe304 RH |
5663 | unsigned vsz = vec_full_reg_size(s); |
5664 | TCGv_ptr t_pg; | |
7924d239 | 5665 | int poff; |
05abe304 RH |
5666 | |
5667 | /* Load the first quadword using the normal predicated load helpers. */ | |
2a99ab2b RH |
5668 | poff = pred_full_reg_offset(s, pg); |
5669 | if (vsz > 16) { | |
5670 | /* | |
5671 | * Zero-extend the first 16 bits of the predicate into a temporary. | |
5672 | * This avoids triggering an assert making sure we don't have bits | |
5673 | * set within a predicate beyond VQ, but we have lowered VQ to 1 | |
5674 | * for this load operation. | |
5675 | */ | |
5676 | TCGv_i64 tmp = tcg_temp_new_i64(); | |
e03b5686 | 5677 | #if HOST_BIG_ENDIAN |
2a99ab2b RH |
5678 | poff += 6; |
5679 | #endif | |
5680 | tcg_gen_ld16u_i64(tmp, cpu_env, poff); | |
5681 | ||
5682 | poff = offsetof(CPUARMState, vfp.preg_tmp); | |
5683 | tcg_gen_st_i64(tmp, cpu_env, poff); | |
5684 | tcg_temp_free_i64(tmp); | |
5685 | } | |
5686 | ||
05abe304 | 5687 | t_pg = tcg_temp_new_ptr(); |
2a99ab2b | 5688 | tcg_gen_addi_ptr(t_pg, cpu_env, poff); |
05abe304 | 5689 | |
c182c6db RH |
5690 | gen_helper_gvec_mem *fn |
5691 | = ldr_fns[s->mte_active[0]][s->be_data == MO_BE][dtype][0]; | |
7924d239 | 5692 | fn(cpu_env, t_pg, addr, tcg_constant_i32(simd_desc(16, 16, zt))); |
05abe304 RH |
5693 | |
5694 | tcg_temp_free_ptr(t_pg); | |
05abe304 RH |
5695 | |
5696 | /* Replicate that first quadword. */ | |
5697 | if (vsz > 16) { | |
7924d239 RH |
5698 | int doff = vec_full_reg_offset(s, zt); |
5699 | tcg_gen_gvec_dup_mem(4, doff + 16, doff, vsz - 16, vsz - 16); | |
05abe304 RH |
5700 | } |
5701 | } | |
5702 | ||
3a7be554 | 5703 | static bool trans_LD1RQ_zprr(DisasContext *s, arg_rprr_load *a) |
05abe304 RH |
5704 | { |
5705 | if (a->rm == 31) { | |
5706 | return false; | |
5707 | } | |
5708 | if (sve_access_check(s)) { | |
5709 | int msz = dtype_msz(a->dtype); | |
5710 | TCGv_i64 addr = new_tmp_a64(s); | |
5711 | tcg_gen_shli_i64(addr, cpu_reg(s, a->rm), msz); | |
5712 | tcg_gen_add_i64(addr, addr, cpu_reg_sp(s, a->rn)); | |
c182c6db | 5713 | do_ldrq(s, a->rd, a->pg, addr, a->dtype); |
05abe304 RH |
5714 | } |
5715 | return true; | |
5716 | } | |
5717 | ||
3a7be554 | 5718 | static bool trans_LD1RQ_zpri(DisasContext *s, arg_rpri_load *a) |
05abe304 RH |
5719 | { |
5720 | if (sve_access_check(s)) { | |
5721 | TCGv_i64 addr = new_tmp_a64(s); | |
5722 | tcg_gen_addi_i64(addr, cpu_reg_sp(s, a->rn), a->imm * 16); | |
c182c6db | 5723 | do_ldrq(s, a->rd, a->pg, addr, a->dtype); |
05abe304 RH |
5724 | } |
5725 | return true; | |
5726 | } | |
5727 | ||
12c563f6 RH |
5728 | static void do_ldro(DisasContext *s, int zt, int pg, TCGv_i64 addr, int dtype) |
5729 | { | |
5730 | unsigned vsz = vec_full_reg_size(s); | |
5731 | unsigned vsz_r32; | |
5732 | TCGv_ptr t_pg; | |
5733 | int poff, doff; | |
5734 | ||
5735 | if (vsz < 32) { | |
5736 | /* | |
5737 | * Note that this UNDEFINED check comes after CheckSVEEnabled() | |
5738 | * in the ARM pseudocode, which is the sve_access_check() done | |
5739 | * in our caller. We should not now return false from the caller. | |
5740 | */ | |
5741 | unallocated_encoding(s); | |
5742 | return; | |
5743 | } | |
5744 | ||
5745 | /* Load the first octaword using the normal predicated load helpers. */ | |
5746 | ||
5747 | poff = pred_full_reg_offset(s, pg); | |
5748 | if (vsz > 32) { | |
5749 | /* | |
5750 | * Zero-extend the first 32 bits of the predicate into a temporary. | |
5751 | * This avoids triggering an assert making sure we don't have bits | |
5752 | * set within a predicate beyond VQ, but we have lowered VQ to 2 | |
5753 | * for this load operation. | |
5754 | */ | |
5755 | TCGv_i64 tmp = tcg_temp_new_i64(); | |
e03b5686 | 5756 | #if HOST_BIG_ENDIAN |
12c563f6 RH |
5757 | poff += 4; |
5758 | #endif | |
5759 | tcg_gen_ld32u_i64(tmp, cpu_env, poff); | |
5760 | ||
5761 | poff = offsetof(CPUARMState, vfp.preg_tmp); | |
5762 | tcg_gen_st_i64(tmp, cpu_env, poff); | |
5763 | tcg_temp_free_i64(tmp); | |
5764 | } | |
5765 | ||
5766 | t_pg = tcg_temp_new_ptr(); | |
5767 | tcg_gen_addi_ptr(t_pg, cpu_env, poff); | |
5768 | ||
5769 | gen_helper_gvec_mem *fn | |
5770 | = ldr_fns[s->mte_active[0]][s->be_data == MO_BE][dtype][0]; | |
5771 | fn(cpu_env, t_pg, addr, tcg_constant_i32(simd_desc(32, 32, zt))); | |
5772 | ||
5773 | tcg_temp_free_ptr(t_pg); | |
5774 | ||
5775 | /* | |
5776 | * Replicate that first octaword. | |
5777 | * The replication happens in units of 32; if the full vector size | |
5778 | * is not a multiple of 32, the final bits are zeroed. | |
5779 | */ | |
5780 | doff = vec_full_reg_offset(s, zt); | |
5781 | vsz_r32 = QEMU_ALIGN_DOWN(vsz, 32); | |
5782 | if (vsz >= 64) { | |
5783 | tcg_gen_gvec_dup_mem(5, doff + 32, doff, vsz_r32 - 32, vsz_r32 - 32); | |
5784 | } | |
5785 | vsz -= vsz_r32; | |
5786 | if (vsz) { | |
5787 | tcg_gen_gvec_dup_imm(MO_64, doff + vsz_r32, vsz, vsz, 0); | |
5788 | } | |
5789 | } | |
5790 | ||
5791 | static bool trans_LD1RO_zprr(DisasContext *s, arg_rprr_load *a) | |
5792 | { | |
5793 | if (!dc_isar_feature(aa64_sve_f64mm, s)) { | |
5794 | return false; | |
5795 | } | |
5796 | if (a->rm == 31) { | |
5797 | return false; | |
5798 | } | |
5799 | if (sve_access_check(s)) { | |
5800 | TCGv_i64 addr = new_tmp_a64(s); | |
5801 | tcg_gen_shli_i64(addr, cpu_reg(s, a->rm), dtype_msz(a->dtype)); | |
5802 | tcg_gen_add_i64(addr, addr, cpu_reg_sp(s, a->rn)); | |
5803 | do_ldro(s, a->rd, a->pg, addr, a->dtype); | |
5804 | } | |
5805 | return true; | |
5806 | } | |
5807 | ||
5808 | static bool trans_LD1RO_zpri(DisasContext *s, arg_rpri_load *a) | |
5809 | { | |
5810 | if (!dc_isar_feature(aa64_sve_f64mm, s)) { | |
5811 | return false; | |
5812 | } | |
5813 | if (sve_access_check(s)) { | |
5814 | TCGv_i64 addr = new_tmp_a64(s); | |
5815 | tcg_gen_addi_i64(addr, cpu_reg_sp(s, a->rn), a->imm * 32); | |
5816 | do_ldro(s, a->rd, a->pg, addr, a->dtype); | |
5817 | } | |
5818 | return true; | |
5819 | } | |
5820 | ||
68459864 | 5821 | /* Load and broadcast element. */ |
3a7be554 | 5822 | static bool trans_LD1R_zpri(DisasContext *s, arg_rpri_load *a) |
68459864 | 5823 | { |
68459864 RH |
5824 | unsigned vsz = vec_full_reg_size(s); |
5825 | unsigned psz = pred_full_reg_size(s); | |
5826 | unsigned esz = dtype_esz[a->dtype]; | |
d0e372b0 | 5827 | unsigned msz = dtype_msz(a->dtype); |
c0ed9166 | 5828 | TCGLabel *over; |
4ac430e1 | 5829 | TCGv_i64 temp, clean_addr; |
68459864 | 5830 | |
c0ed9166 RH |
5831 | if (!sve_access_check(s)) { |
5832 | return true; | |
5833 | } | |
5834 | ||
5835 | over = gen_new_label(); | |
5836 | ||
68459864 RH |
5837 | /* If the guarding predicate has no bits set, no load occurs. */ |
5838 | if (psz <= 8) { | |
5839 | /* Reduce the pred_esz_masks value simply to reduce the | |
5840 | * size of the code generated here. | |
5841 | */ | |
5842 | uint64_t psz_mask = MAKE_64BIT_MASK(0, psz * 8); | |
5843 | temp = tcg_temp_new_i64(); | |
5844 | tcg_gen_ld_i64(temp, cpu_env, pred_full_reg_offset(s, a->pg)); | |
5845 | tcg_gen_andi_i64(temp, temp, pred_esz_masks[esz] & psz_mask); | |
5846 | tcg_gen_brcondi_i64(TCG_COND_EQ, temp, 0, over); | |
5847 | tcg_temp_free_i64(temp); | |
5848 | } else { | |
5849 | TCGv_i32 t32 = tcg_temp_new_i32(); | |
5850 | find_last_active(s, t32, esz, a->pg); | |
5851 | tcg_gen_brcondi_i32(TCG_COND_LT, t32, 0, over); | |
5852 | tcg_temp_free_i32(t32); | |
5853 | } | |
5854 | ||
5855 | /* Load the data. */ | |
5856 | temp = tcg_temp_new_i64(); | |
d0e372b0 | 5857 | tcg_gen_addi_i64(temp, cpu_reg_sp(s, a->rn), a->imm << msz); |
4ac430e1 RH |
5858 | clean_addr = gen_mte_check1(s, temp, false, true, msz); |
5859 | ||
5860 | tcg_gen_qemu_ld_i64(temp, clean_addr, get_mem_index(s), | |
0ca0f872 | 5861 | finalize_memop(s, dtype_mop[a->dtype])); |
68459864 RH |
5862 | |
5863 | /* Broadcast to *all* elements. */ | |
5864 | tcg_gen_gvec_dup_i64(esz, vec_full_reg_offset(s, a->rd), | |
5865 | vsz, vsz, temp); | |
5866 | tcg_temp_free_i64(temp); | |
5867 | ||
5868 | /* Zero the inactive elements. */ | |
5869 | gen_set_label(over); | |
60245996 | 5870 | return do_movz_zpz(s, a->rd, a->rd, a->pg, esz, false); |
68459864 RH |
5871 | } |
5872 | ||
1a039c7e RH |
5873 | static void do_st_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr, |
5874 | int msz, int esz, int nreg) | |
5875 | { | |
71b9f394 RH |
5876 | static gen_helper_gvec_mem * const fn_single[2][2][4][4] = { |
5877 | { { { gen_helper_sve_st1bb_r, | |
5878 | gen_helper_sve_st1bh_r, | |
5879 | gen_helper_sve_st1bs_r, | |
5880 | gen_helper_sve_st1bd_r }, | |
5881 | { NULL, | |
5882 | gen_helper_sve_st1hh_le_r, | |
5883 | gen_helper_sve_st1hs_le_r, | |
5884 | gen_helper_sve_st1hd_le_r }, | |
5885 | { NULL, NULL, | |
5886 | gen_helper_sve_st1ss_le_r, | |
5887 | gen_helper_sve_st1sd_le_r }, | |
5888 | { NULL, NULL, NULL, | |
5889 | gen_helper_sve_st1dd_le_r } }, | |
5890 | { { gen_helper_sve_st1bb_r, | |
5891 | gen_helper_sve_st1bh_r, | |
5892 | gen_helper_sve_st1bs_r, | |
5893 | gen_helper_sve_st1bd_r }, | |
5894 | { NULL, | |
5895 | gen_helper_sve_st1hh_be_r, | |
5896 | gen_helper_sve_st1hs_be_r, | |
5897 | gen_helper_sve_st1hd_be_r }, | |
5898 | { NULL, NULL, | |
5899 | gen_helper_sve_st1ss_be_r, | |
5900 | gen_helper_sve_st1sd_be_r }, | |
5901 | { NULL, NULL, NULL, | |
5902 | gen_helper_sve_st1dd_be_r } } }, | |
5903 | ||
5904 | { { { gen_helper_sve_st1bb_r_mte, | |
5905 | gen_helper_sve_st1bh_r_mte, | |
5906 | gen_helper_sve_st1bs_r_mte, | |
5907 | gen_helper_sve_st1bd_r_mte }, | |
5908 | { NULL, | |
5909 | gen_helper_sve_st1hh_le_r_mte, | |
5910 | gen_helper_sve_st1hs_le_r_mte, | |
5911 | gen_helper_sve_st1hd_le_r_mte }, | |
5912 | { NULL, NULL, | |
5913 | gen_helper_sve_st1ss_le_r_mte, | |
5914 | gen_helper_sve_st1sd_le_r_mte }, | |
5915 | { NULL, NULL, NULL, | |
5916 | gen_helper_sve_st1dd_le_r_mte } }, | |
5917 | { { gen_helper_sve_st1bb_r_mte, | |
5918 | gen_helper_sve_st1bh_r_mte, | |
5919 | gen_helper_sve_st1bs_r_mte, | |
5920 | gen_helper_sve_st1bd_r_mte }, | |
5921 | { NULL, | |
5922 | gen_helper_sve_st1hh_be_r_mte, | |
5923 | gen_helper_sve_st1hs_be_r_mte, | |
5924 | gen_helper_sve_st1hd_be_r_mte }, | |
5925 | { NULL, NULL, | |
5926 | gen_helper_sve_st1ss_be_r_mte, | |
5927 | gen_helper_sve_st1sd_be_r_mte }, | |
5928 | { NULL, NULL, NULL, | |
5929 | gen_helper_sve_st1dd_be_r_mte } } }, | |
1a039c7e | 5930 | }; |
71b9f394 RH |
5931 | static gen_helper_gvec_mem * const fn_multiple[2][2][3][4] = { |
5932 | { { { gen_helper_sve_st2bb_r, | |
5933 | gen_helper_sve_st2hh_le_r, | |
5934 | gen_helper_sve_st2ss_le_r, | |
5935 | gen_helper_sve_st2dd_le_r }, | |
5936 | { gen_helper_sve_st3bb_r, | |
5937 | gen_helper_sve_st3hh_le_r, | |
5938 | gen_helper_sve_st3ss_le_r, | |
5939 | gen_helper_sve_st3dd_le_r }, | |
5940 | { gen_helper_sve_st4bb_r, | |
5941 | gen_helper_sve_st4hh_le_r, | |
5942 | gen_helper_sve_st4ss_le_r, | |
5943 | gen_helper_sve_st4dd_le_r } }, | |
5944 | { { gen_helper_sve_st2bb_r, | |
5945 | gen_helper_sve_st2hh_be_r, | |
5946 | gen_helper_sve_st2ss_be_r, | |
5947 | gen_helper_sve_st2dd_be_r }, | |
5948 | { gen_helper_sve_st3bb_r, | |
5949 | gen_helper_sve_st3hh_be_r, | |
5950 | gen_helper_sve_st3ss_be_r, | |
5951 | gen_helper_sve_st3dd_be_r }, | |
5952 | { gen_helper_sve_st4bb_r, | |
5953 | gen_helper_sve_st4hh_be_r, | |
5954 | gen_helper_sve_st4ss_be_r, | |
5955 | gen_helper_sve_st4dd_be_r } } }, | |
5956 | { { { gen_helper_sve_st2bb_r_mte, | |
5957 | gen_helper_sve_st2hh_le_r_mte, | |
5958 | gen_helper_sve_st2ss_le_r_mte, | |
5959 | gen_helper_sve_st2dd_le_r_mte }, | |
5960 | { gen_helper_sve_st3bb_r_mte, | |
5961 | gen_helper_sve_st3hh_le_r_mte, | |
5962 | gen_helper_sve_st3ss_le_r_mte, | |
5963 | gen_helper_sve_st3dd_le_r_mte }, | |
5964 | { gen_helper_sve_st4bb_r_mte, | |
5965 | gen_helper_sve_st4hh_le_r_mte, | |
5966 | gen_helper_sve_st4ss_le_r_mte, | |
5967 | gen_helper_sve_st4dd_le_r_mte } }, | |
5968 | { { gen_helper_sve_st2bb_r_mte, | |
5969 | gen_helper_sve_st2hh_be_r_mte, | |
5970 | gen_helper_sve_st2ss_be_r_mte, | |
5971 | gen_helper_sve_st2dd_be_r_mte }, | |
5972 | { gen_helper_sve_st3bb_r_mte, | |
5973 | gen_helper_sve_st3hh_be_r_mte, | |
5974 | gen_helper_sve_st3ss_be_r_mte, | |
5975 | gen_helper_sve_st3dd_be_r_mte }, | |
5976 | { gen_helper_sve_st4bb_r_mte, | |
5977 | gen_helper_sve_st4hh_be_r_mte, | |
5978 | gen_helper_sve_st4ss_be_r_mte, | |
5979 | gen_helper_sve_st4dd_be_r_mte } } }, | |
1a039c7e RH |
5980 | }; |
5981 | gen_helper_gvec_mem *fn; | |
28d57f2d | 5982 | int be = s->be_data == MO_BE; |
1a039c7e RH |
5983 | |
5984 | if (nreg == 0) { | |
5985 | /* ST1 */ | |
71b9f394 RH |
5986 | fn = fn_single[s->mte_active[0]][be][msz][esz]; |
5987 | nreg = 1; | |
1a039c7e RH |
5988 | } else { |
5989 | /* ST2, ST3, ST4 -- msz == esz, enforced by encoding */ | |
5990 | assert(msz == esz); | |
71b9f394 | 5991 | fn = fn_multiple[s->mte_active[0]][be][nreg - 1][msz]; |
1a039c7e RH |
5992 | } |
5993 | assert(fn != NULL); | |
71b9f394 | 5994 | do_mem_zpa(s, zt, pg, addr, msz_dtype(s, msz), nreg, true, fn); |
1a039c7e RH |
5995 | } |
5996 | ||
3a7be554 | 5997 | static bool trans_ST_zprr(DisasContext *s, arg_rprr_store *a) |
1a039c7e RH |
5998 | { |
5999 | if (a->rm == 31 || a->msz > a->esz) { | |
6000 | return false; | |
6001 | } | |
6002 | if (sve_access_check(s)) { | |
6003 | TCGv_i64 addr = new_tmp_a64(s); | |
50ef1cbf | 6004 | tcg_gen_shli_i64(addr, cpu_reg(s, a->rm), a->msz); |
1a039c7e RH |
6005 | tcg_gen_add_i64(addr, addr, cpu_reg_sp(s, a->rn)); |
6006 | do_st_zpa(s, a->rd, a->pg, addr, a->msz, a->esz, a->nreg); | |
6007 | } | |
6008 | return true; | |
6009 | } | |
6010 | ||
3a7be554 | 6011 | static bool trans_ST_zpri(DisasContext *s, arg_rpri_store *a) |
1a039c7e RH |
6012 | { |
6013 | if (a->msz > a->esz) { | |
6014 | return false; | |
6015 | } | |
6016 | if (sve_access_check(s)) { | |
6017 | int vsz = vec_full_reg_size(s); | |
6018 | int elements = vsz >> a->esz; | |
6019 | TCGv_i64 addr = new_tmp_a64(s); | |
6020 | ||
6021 | tcg_gen_addi_i64(addr, cpu_reg_sp(s, a->rn), | |
6022 | (a->imm * elements * (a->nreg + 1)) << a->msz); | |
6023 | do_st_zpa(s, a->rd, a->pg, addr, a->msz, a->esz, a->nreg); | |
6024 | } | |
6025 | return true; | |
6026 | } | |
f6dbf62a RH |
6027 | |
6028 | /* | |
6029 | *** SVE gather loads / scatter stores | |
6030 | */ | |
6031 | ||
500d0484 | 6032 | static void do_mem_zpz(DisasContext *s, int zt, int pg, int zm, |
d28d12f0 | 6033 | int scale, TCGv_i64 scalar, int msz, bool is_write, |
500d0484 | 6034 | gen_helper_gvec_mem_scatter *fn) |
f6dbf62a RH |
6035 | { |
6036 | unsigned vsz = vec_full_reg_size(s); | |
f6dbf62a RH |
6037 | TCGv_ptr t_zm = tcg_temp_new_ptr(); |
6038 | TCGv_ptr t_pg = tcg_temp_new_ptr(); | |
6039 | TCGv_ptr t_zt = tcg_temp_new_ptr(); | |
500d0484 | 6040 | TCGv_i32 t_desc; |
d28d12f0 | 6041 | int desc = 0; |
500d0484 | 6042 | |
d28d12f0 RH |
6043 | if (s->mte_active[0]) { |
6044 | desc = FIELD_DP32(desc, MTEDESC, MIDX, get_mem_index(s)); | |
6045 | desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid); | |
6046 | desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma); | |
6047 | desc = FIELD_DP32(desc, MTEDESC, WRITE, is_write); | |
28f32503 | 6048 | desc = FIELD_DP32(desc, MTEDESC, SIZEM1, (1 << msz) - 1); |
d28d12f0 RH |
6049 | desc <<= SVE_MTEDESC_SHIFT; |
6050 | } | |
cdecb3fc | 6051 | desc = simd_desc(vsz, vsz, desc | scale); |
500d0484 | 6052 | t_desc = tcg_const_i32(desc); |
f6dbf62a RH |
6053 | |
6054 | tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, pg)); | |
6055 | tcg_gen_addi_ptr(t_zm, cpu_env, vec_full_reg_offset(s, zm)); | |
6056 | tcg_gen_addi_ptr(t_zt, cpu_env, vec_full_reg_offset(s, zt)); | |
500d0484 | 6057 | fn(cpu_env, t_zt, t_pg, t_zm, scalar, t_desc); |
f6dbf62a RH |
6058 | |
6059 | tcg_temp_free_ptr(t_zt); | |
6060 | tcg_temp_free_ptr(t_zm); | |
6061 | tcg_temp_free_ptr(t_pg); | |
500d0484 | 6062 | tcg_temp_free_i32(t_desc); |
f6dbf62a RH |
6063 | } |
6064 | ||
d28d12f0 RH |
6065 | /* Indexed by [mte][be][ff][xs][u][msz]. */ |
6066 | static gen_helper_gvec_mem_scatter * const | |
6067 | gather_load_fn32[2][2][2][2][2][3] = { | |
6068 | { /* MTE Inactive */ | |
6069 | { /* Little-endian */ | |
6070 | { { { gen_helper_sve_ldbss_zsu, | |
6071 | gen_helper_sve_ldhss_le_zsu, | |
6072 | NULL, }, | |
6073 | { gen_helper_sve_ldbsu_zsu, | |
6074 | gen_helper_sve_ldhsu_le_zsu, | |
6075 | gen_helper_sve_ldss_le_zsu, } }, | |
6076 | { { gen_helper_sve_ldbss_zss, | |
6077 | gen_helper_sve_ldhss_le_zss, | |
6078 | NULL, }, | |
6079 | { gen_helper_sve_ldbsu_zss, | |
6080 | gen_helper_sve_ldhsu_le_zss, | |
6081 | gen_helper_sve_ldss_le_zss, } } }, | |
6082 | ||
6083 | /* First-fault */ | |
6084 | { { { gen_helper_sve_ldffbss_zsu, | |
6085 | gen_helper_sve_ldffhss_le_zsu, | |
6086 | NULL, }, | |
6087 | { gen_helper_sve_ldffbsu_zsu, | |
6088 | gen_helper_sve_ldffhsu_le_zsu, | |
6089 | gen_helper_sve_ldffss_le_zsu, } }, | |
6090 | { { gen_helper_sve_ldffbss_zss, | |
6091 | gen_helper_sve_ldffhss_le_zss, | |
6092 | NULL, }, | |
6093 | { gen_helper_sve_ldffbsu_zss, | |
6094 | gen_helper_sve_ldffhsu_le_zss, | |
6095 | gen_helper_sve_ldffss_le_zss, } } } }, | |
6096 | ||
6097 | { /* Big-endian */ | |
6098 | { { { gen_helper_sve_ldbss_zsu, | |
6099 | gen_helper_sve_ldhss_be_zsu, | |
6100 | NULL, }, | |
6101 | { gen_helper_sve_ldbsu_zsu, | |
6102 | gen_helper_sve_ldhsu_be_zsu, | |
6103 | gen_helper_sve_ldss_be_zsu, } }, | |
6104 | { { gen_helper_sve_ldbss_zss, | |
6105 | gen_helper_sve_ldhss_be_zss, | |
6106 | NULL, }, | |
6107 | { gen_helper_sve_ldbsu_zss, | |
6108 | gen_helper_sve_ldhsu_be_zss, | |
6109 | gen_helper_sve_ldss_be_zss, } } }, | |
6110 | ||
6111 | /* First-fault */ | |
6112 | { { { gen_helper_sve_ldffbss_zsu, | |
6113 | gen_helper_sve_ldffhss_be_zsu, | |
6114 | NULL, }, | |
6115 | { gen_helper_sve_ldffbsu_zsu, | |
6116 | gen_helper_sve_ldffhsu_be_zsu, | |
6117 | gen_helper_sve_ldffss_be_zsu, } }, | |
6118 | { { gen_helper_sve_ldffbss_zss, | |
6119 | gen_helper_sve_ldffhss_be_zss, | |
6120 | NULL, }, | |
6121 | { gen_helper_sve_ldffbsu_zss, | |
6122 | gen_helper_sve_ldffhsu_be_zss, | |
6123 | gen_helper_sve_ldffss_be_zss, } } } } }, | |
6124 | { /* MTE Active */ | |
6125 | { /* Little-endian */ | |
6126 | { { { gen_helper_sve_ldbss_zsu_mte, | |
6127 | gen_helper_sve_ldhss_le_zsu_mte, | |
6128 | NULL, }, | |
6129 | { gen_helper_sve_ldbsu_zsu_mte, | |
6130 | gen_helper_sve_ldhsu_le_zsu_mte, | |
6131 | gen_helper_sve_ldss_le_zsu_mte, } }, | |
6132 | { { gen_helper_sve_ldbss_zss_mte, | |
6133 | gen_helper_sve_ldhss_le_zss_mte, | |
6134 | NULL, }, | |
6135 | { gen_helper_sve_ldbsu_zss_mte, | |
6136 | gen_helper_sve_ldhsu_le_zss_mte, | |
6137 | gen_helper_sve_ldss_le_zss_mte, } } }, | |
6138 | ||
6139 | /* First-fault */ | |
6140 | { { { gen_helper_sve_ldffbss_zsu_mte, | |
6141 | gen_helper_sve_ldffhss_le_zsu_mte, | |
6142 | NULL, }, | |
6143 | { gen_helper_sve_ldffbsu_zsu_mte, | |
6144 | gen_helper_sve_ldffhsu_le_zsu_mte, | |
6145 | gen_helper_sve_ldffss_le_zsu_mte, } }, | |
6146 | { { gen_helper_sve_ldffbss_zss_mte, | |
6147 | gen_helper_sve_ldffhss_le_zss_mte, | |
6148 | NULL, }, | |
6149 | { gen_helper_sve_ldffbsu_zss_mte, | |
6150 | gen_helper_sve_ldffhsu_le_zss_mte, | |
6151 | gen_helper_sve_ldffss_le_zss_mte, } } } }, | |
6152 | ||
6153 | { /* Big-endian */ | |
6154 | { { { gen_helper_sve_ldbss_zsu_mte, | |
6155 | gen_helper_sve_ldhss_be_zsu_mte, | |
6156 | NULL, }, | |
6157 | { gen_helper_sve_ldbsu_zsu_mte, | |
6158 | gen_helper_sve_ldhsu_be_zsu_mte, | |
6159 | gen_helper_sve_ldss_be_zsu_mte, } }, | |
6160 | { { gen_helper_sve_ldbss_zss_mte, | |
6161 | gen_helper_sve_ldhss_be_zss_mte, | |
6162 | NULL, }, | |
6163 | { gen_helper_sve_ldbsu_zss_mte, | |
6164 | gen_helper_sve_ldhsu_be_zss_mte, | |
6165 | gen_helper_sve_ldss_be_zss_mte, } } }, | |
6166 | ||
6167 | /* First-fault */ | |
6168 | { { { gen_helper_sve_ldffbss_zsu_mte, | |
6169 | gen_helper_sve_ldffhss_be_zsu_mte, | |
6170 | NULL, }, | |
6171 | { gen_helper_sve_ldffbsu_zsu_mte, | |
6172 | gen_helper_sve_ldffhsu_be_zsu_mte, | |
6173 | gen_helper_sve_ldffss_be_zsu_mte, } }, | |
6174 | { { gen_helper_sve_ldffbss_zss_mte, | |
6175 | gen_helper_sve_ldffhss_be_zss_mte, | |
6176 | NULL, }, | |
6177 | { gen_helper_sve_ldffbsu_zss_mte, | |
6178 | gen_helper_sve_ldffhsu_be_zss_mte, | |
6179 | gen_helper_sve_ldffss_be_zss_mte, } } } } }, | |
673e9fa6 RH |
6180 | }; |
6181 | ||
6182 | /* Note that we overload xs=2 to indicate 64-bit offset. */ | |
d28d12f0 RH |
6183 | static gen_helper_gvec_mem_scatter * const |
6184 | gather_load_fn64[2][2][2][3][2][4] = { | |
6185 | { /* MTE Inactive */ | |
6186 | { /* Little-endian */ | |
6187 | { { { gen_helper_sve_ldbds_zsu, | |
6188 | gen_helper_sve_ldhds_le_zsu, | |
6189 | gen_helper_sve_ldsds_le_zsu, | |
6190 | NULL, }, | |
6191 | { gen_helper_sve_ldbdu_zsu, | |
6192 | gen_helper_sve_ldhdu_le_zsu, | |
6193 | gen_helper_sve_ldsdu_le_zsu, | |
6194 | gen_helper_sve_lddd_le_zsu, } }, | |
6195 | { { gen_helper_sve_ldbds_zss, | |
6196 | gen_helper_sve_ldhds_le_zss, | |
6197 | gen_helper_sve_ldsds_le_zss, | |
6198 | NULL, }, | |
6199 | { gen_helper_sve_ldbdu_zss, | |
6200 | gen_helper_sve_ldhdu_le_zss, | |
6201 | gen_helper_sve_ldsdu_le_zss, | |
6202 | gen_helper_sve_lddd_le_zss, } }, | |
6203 | { { gen_helper_sve_ldbds_zd, | |
6204 | gen_helper_sve_ldhds_le_zd, | |
6205 | gen_helper_sve_ldsds_le_zd, | |
6206 | NULL, }, | |
6207 | { gen_helper_sve_ldbdu_zd, | |
6208 | gen_helper_sve_ldhdu_le_zd, | |
6209 | gen_helper_sve_ldsdu_le_zd, | |
6210 | gen_helper_sve_lddd_le_zd, } } }, | |
6211 | ||
6212 | /* First-fault */ | |
6213 | { { { gen_helper_sve_ldffbds_zsu, | |
6214 | gen_helper_sve_ldffhds_le_zsu, | |
6215 | gen_helper_sve_ldffsds_le_zsu, | |
6216 | NULL, }, | |
6217 | { gen_helper_sve_ldffbdu_zsu, | |
6218 | gen_helper_sve_ldffhdu_le_zsu, | |
6219 | gen_helper_sve_ldffsdu_le_zsu, | |
6220 | gen_helper_sve_ldffdd_le_zsu, } }, | |
6221 | { { gen_helper_sve_ldffbds_zss, | |
6222 | gen_helper_sve_ldffhds_le_zss, | |
6223 | gen_helper_sve_ldffsds_le_zss, | |
6224 | NULL, }, | |
6225 | { gen_helper_sve_ldffbdu_zss, | |
6226 | gen_helper_sve_ldffhdu_le_zss, | |
6227 | gen_helper_sve_ldffsdu_le_zss, | |
6228 | gen_helper_sve_ldffdd_le_zss, } }, | |
6229 | { { gen_helper_sve_ldffbds_zd, | |
6230 | gen_helper_sve_ldffhds_le_zd, | |
6231 | gen_helper_sve_ldffsds_le_zd, | |
6232 | NULL, }, | |
6233 | { gen_helper_sve_ldffbdu_zd, | |
6234 | gen_helper_sve_ldffhdu_le_zd, | |
6235 | gen_helper_sve_ldffsdu_le_zd, | |
6236 | gen_helper_sve_ldffdd_le_zd, } } } }, | |
6237 | { /* Big-endian */ | |
6238 | { { { gen_helper_sve_ldbds_zsu, | |
6239 | gen_helper_sve_ldhds_be_zsu, | |
6240 | gen_helper_sve_ldsds_be_zsu, | |
6241 | NULL, }, | |
6242 | { gen_helper_sve_ldbdu_zsu, | |
6243 | gen_helper_sve_ldhdu_be_zsu, | |
6244 | gen_helper_sve_ldsdu_be_zsu, | |
6245 | gen_helper_sve_lddd_be_zsu, } }, | |
6246 | { { gen_helper_sve_ldbds_zss, | |
6247 | gen_helper_sve_ldhds_be_zss, | |
6248 | gen_helper_sve_ldsds_be_zss, | |
6249 | NULL, }, | |
6250 | { gen_helper_sve_ldbdu_zss, | |
6251 | gen_helper_sve_ldhdu_be_zss, | |
6252 | gen_helper_sve_ldsdu_be_zss, | |
6253 | gen_helper_sve_lddd_be_zss, } }, | |
6254 | { { gen_helper_sve_ldbds_zd, | |
6255 | gen_helper_sve_ldhds_be_zd, | |
6256 | gen_helper_sve_ldsds_be_zd, | |
6257 | NULL, }, | |
6258 | { gen_helper_sve_ldbdu_zd, | |
6259 | gen_helper_sve_ldhdu_be_zd, | |
6260 | gen_helper_sve_ldsdu_be_zd, | |
6261 | gen_helper_sve_lddd_be_zd, } } }, | |
6262 | ||
6263 | /* First-fault */ | |
6264 | { { { gen_helper_sve_ldffbds_zsu, | |
6265 | gen_helper_sve_ldffhds_be_zsu, | |
6266 | gen_helper_sve_ldffsds_be_zsu, | |
6267 | NULL, }, | |
6268 | { gen_helper_sve_ldffbdu_zsu, | |
6269 | gen_helper_sve_ldffhdu_be_zsu, | |
6270 | gen_helper_sve_ldffsdu_be_zsu, | |
6271 | gen_helper_sve_ldffdd_be_zsu, } }, | |
6272 | { { gen_helper_sve_ldffbds_zss, | |
6273 | gen_helper_sve_ldffhds_be_zss, | |
6274 | gen_helper_sve_ldffsds_be_zss, | |
6275 | NULL, }, | |
6276 | { gen_helper_sve_ldffbdu_zss, | |
6277 | gen_helper_sve_ldffhdu_be_zss, | |
6278 | gen_helper_sve_ldffsdu_be_zss, | |
6279 | gen_helper_sve_ldffdd_be_zss, } }, | |
6280 | { { gen_helper_sve_ldffbds_zd, | |
6281 | gen_helper_sve_ldffhds_be_zd, | |
6282 | gen_helper_sve_ldffsds_be_zd, | |
6283 | NULL, }, | |
6284 | { gen_helper_sve_ldffbdu_zd, | |
6285 | gen_helper_sve_ldffhdu_be_zd, | |
6286 | gen_helper_sve_ldffsdu_be_zd, | |
6287 | gen_helper_sve_ldffdd_be_zd, } } } } }, | |
6288 | { /* MTE Active */ | |
6289 | { /* Little-endian */ | |
6290 | { { { gen_helper_sve_ldbds_zsu_mte, | |
6291 | gen_helper_sve_ldhds_le_zsu_mte, | |
6292 | gen_helper_sve_ldsds_le_zsu_mte, | |
6293 | NULL, }, | |
6294 | { gen_helper_sve_ldbdu_zsu_mte, | |
6295 | gen_helper_sve_ldhdu_le_zsu_mte, | |
6296 | gen_helper_sve_ldsdu_le_zsu_mte, | |
6297 | gen_helper_sve_lddd_le_zsu_mte, } }, | |
6298 | { { gen_helper_sve_ldbds_zss_mte, | |
6299 | gen_helper_sve_ldhds_le_zss_mte, | |
6300 | gen_helper_sve_ldsds_le_zss_mte, | |
6301 | NULL, }, | |
6302 | { gen_helper_sve_ldbdu_zss_mte, | |
6303 | gen_helper_sve_ldhdu_le_zss_mte, | |
6304 | gen_helper_sve_ldsdu_le_zss_mte, | |
6305 | gen_helper_sve_lddd_le_zss_mte, } }, | |
6306 | { { gen_helper_sve_ldbds_zd_mte, | |
6307 | gen_helper_sve_ldhds_le_zd_mte, | |
6308 | gen_helper_sve_ldsds_le_zd_mte, | |
6309 | NULL, }, | |
6310 | { gen_helper_sve_ldbdu_zd_mte, | |
6311 | gen_helper_sve_ldhdu_le_zd_mte, | |
6312 | gen_helper_sve_ldsdu_le_zd_mte, | |
6313 | gen_helper_sve_lddd_le_zd_mte, } } }, | |
6314 | ||
6315 | /* First-fault */ | |
6316 | { { { gen_helper_sve_ldffbds_zsu_mte, | |
6317 | gen_helper_sve_ldffhds_le_zsu_mte, | |
6318 | gen_helper_sve_ldffsds_le_zsu_mte, | |
6319 | NULL, }, | |
6320 | { gen_helper_sve_ldffbdu_zsu_mte, | |
6321 | gen_helper_sve_ldffhdu_le_zsu_mte, | |
6322 | gen_helper_sve_ldffsdu_le_zsu_mte, | |
6323 | gen_helper_sve_ldffdd_le_zsu_mte, } }, | |
6324 | { { gen_helper_sve_ldffbds_zss_mte, | |
6325 | gen_helper_sve_ldffhds_le_zss_mte, | |
6326 | gen_helper_sve_ldffsds_le_zss_mte, | |
6327 | NULL, }, | |
6328 | { gen_helper_sve_ldffbdu_zss_mte, | |
6329 | gen_helper_sve_ldffhdu_le_zss_mte, | |
6330 | gen_helper_sve_ldffsdu_le_zss_mte, | |
6331 | gen_helper_sve_ldffdd_le_zss_mte, } }, | |
6332 | { { gen_helper_sve_ldffbds_zd_mte, | |
6333 | gen_helper_sve_ldffhds_le_zd_mte, | |
6334 | gen_helper_sve_ldffsds_le_zd_mte, | |
6335 | NULL, }, | |
6336 | { gen_helper_sve_ldffbdu_zd_mte, | |
6337 | gen_helper_sve_ldffhdu_le_zd_mte, | |
6338 | gen_helper_sve_ldffsdu_le_zd_mte, | |
6339 | gen_helper_sve_ldffdd_le_zd_mte, } } } }, | |
6340 | { /* Big-endian */ | |
6341 | { { { gen_helper_sve_ldbds_zsu_mte, | |
6342 | gen_helper_sve_ldhds_be_zsu_mte, | |
6343 | gen_helper_sve_ldsds_be_zsu_mte, | |
6344 | NULL, }, | |
6345 | { gen_helper_sve_ldbdu_zsu_mte, | |
6346 | gen_helper_sve_ldhdu_be_zsu_mte, | |
6347 | gen_helper_sve_ldsdu_be_zsu_mte, | |
6348 | gen_helper_sve_lddd_be_zsu_mte, } }, | |
6349 | { { gen_helper_sve_ldbds_zss_mte, | |
6350 | gen_helper_sve_ldhds_be_zss_mte, | |
6351 | gen_helper_sve_ldsds_be_zss_mte, | |
6352 | NULL, }, | |
6353 | { gen_helper_sve_ldbdu_zss_mte, | |
6354 | gen_helper_sve_ldhdu_be_zss_mte, | |
6355 | gen_helper_sve_ldsdu_be_zss_mte, | |
6356 | gen_helper_sve_lddd_be_zss_mte, } }, | |
6357 | { { gen_helper_sve_ldbds_zd_mte, | |
6358 | gen_helper_sve_ldhds_be_zd_mte, | |
6359 | gen_helper_sve_ldsds_be_zd_mte, | |
6360 | NULL, }, | |
6361 | { gen_helper_sve_ldbdu_zd_mte, | |
6362 | gen_helper_sve_ldhdu_be_zd_mte, | |
6363 | gen_helper_sve_ldsdu_be_zd_mte, | |
6364 | gen_helper_sve_lddd_be_zd_mte, } } }, | |
6365 | ||
6366 | /* First-fault */ | |
6367 | { { { gen_helper_sve_ldffbds_zsu_mte, | |
6368 | gen_helper_sve_ldffhds_be_zsu_mte, | |
6369 | gen_helper_sve_ldffsds_be_zsu_mte, | |
6370 | NULL, }, | |
6371 | { gen_helper_sve_ldffbdu_zsu_mte, | |
6372 | gen_helper_sve_ldffhdu_be_zsu_mte, | |
6373 | gen_helper_sve_ldffsdu_be_zsu_mte, | |
6374 | gen_helper_sve_ldffdd_be_zsu_mte, } }, | |
6375 | { { gen_helper_sve_ldffbds_zss_mte, | |
6376 | gen_helper_sve_ldffhds_be_zss_mte, | |
6377 | gen_helper_sve_ldffsds_be_zss_mte, | |
6378 | NULL, }, | |
6379 | { gen_helper_sve_ldffbdu_zss_mte, | |
6380 | gen_helper_sve_ldffhdu_be_zss_mte, | |
6381 | gen_helper_sve_ldffsdu_be_zss_mte, | |
6382 | gen_helper_sve_ldffdd_be_zss_mte, } }, | |
6383 | { { gen_helper_sve_ldffbds_zd_mte, | |
6384 | gen_helper_sve_ldffhds_be_zd_mte, | |
6385 | gen_helper_sve_ldffsds_be_zd_mte, | |
6386 | NULL, }, | |
6387 | { gen_helper_sve_ldffbdu_zd_mte, | |
6388 | gen_helper_sve_ldffhdu_be_zd_mte, | |
6389 | gen_helper_sve_ldffsdu_be_zd_mte, | |
6390 | gen_helper_sve_ldffdd_be_zd_mte, } } } } }, | |
673e9fa6 RH |
6391 | }; |
6392 | ||
3a7be554 | 6393 | static bool trans_LD1_zprz(DisasContext *s, arg_LD1_zprz *a) |
673e9fa6 RH |
6394 | { |
6395 | gen_helper_gvec_mem_scatter *fn = NULL; | |
d28d12f0 RH |
6396 | bool be = s->be_data == MO_BE; |
6397 | bool mte = s->mte_active[0]; | |
673e9fa6 RH |
6398 | |
6399 | if (!sve_access_check(s)) { | |
6400 | return true; | |
6401 | } | |
6402 | ||
6403 | switch (a->esz) { | |
6404 | case MO_32: | |
d28d12f0 | 6405 | fn = gather_load_fn32[mte][be][a->ff][a->xs][a->u][a->msz]; |
673e9fa6 RH |
6406 | break; |
6407 | case MO_64: | |
d28d12f0 | 6408 | fn = gather_load_fn64[mte][be][a->ff][a->xs][a->u][a->msz]; |
673e9fa6 RH |
6409 | break; |
6410 | } | |
6411 | assert(fn != NULL); | |
6412 | ||
6413 | do_mem_zpz(s, a->rd, a->pg, a->rm, a->scale * a->msz, | |
d28d12f0 | 6414 | cpu_reg_sp(s, a->rn), a->msz, false, fn); |
673e9fa6 RH |
6415 | return true; |
6416 | } | |
6417 | ||
3a7be554 | 6418 | static bool trans_LD1_zpiz(DisasContext *s, arg_LD1_zpiz *a) |
673e9fa6 RH |
6419 | { |
6420 | gen_helper_gvec_mem_scatter *fn = NULL; | |
d28d12f0 RH |
6421 | bool be = s->be_data == MO_BE; |
6422 | bool mte = s->mte_active[0]; | |
673e9fa6 RH |
6423 | |
6424 | if (a->esz < a->msz || (a->esz == a->msz && !a->u)) { | |
6425 | return false; | |
6426 | } | |
6427 | if (!sve_access_check(s)) { | |
6428 | return true; | |
6429 | } | |
6430 | ||
6431 | switch (a->esz) { | |
6432 | case MO_32: | |
d28d12f0 | 6433 | fn = gather_load_fn32[mte][be][a->ff][0][a->u][a->msz]; |
673e9fa6 RH |
6434 | break; |
6435 | case MO_64: | |
d28d12f0 | 6436 | fn = gather_load_fn64[mte][be][a->ff][2][a->u][a->msz]; |
673e9fa6 RH |
6437 | break; |
6438 | } | |
6439 | assert(fn != NULL); | |
6440 | ||
6441 | /* Treat LD1_zpiz (zn[x] + imm) the same way as LD1_zprz (rn + zm[x]) | |
6442 | * by loading the immediate into the scalar parameter. | |
6443 | */ | |
2ccdf94f RH |
6444 | do_mem_zpz(s, a->rd, a->pg, a->rn, 0, |
6445 | tcg_constant_i64(a->imm << a->msz), a->msz, false, fn); | |
673e9fa6 RH |
6446 | return true; |
6447 | } | |
6448 | ||
cf327449 SL |
6449 | static bool trans_LDNT1_zprz(DisasContext *s, arg_LD1_zprz *a) |
6450 | { | |
b17ab470 RH |
6451 | gen_helper_gvec_mem_scatter *fn = NULL; |
6452 | bool be = s->be_data == MO_BE; | |
6453 | bool mte = s->mte_active[0]; | |
6454 | ||
6455 | if (a->esz < a->msz + !a->u) { | |
6456 | return false; | |
6457 | } | |
cf327449 SL |
6458 | if (!dc_isar_feature(aa64_sve2, s)) { |
6459 | return false; | |
6460 | } | |
b17ab470 RH |
6461 | if (!sve_access_check(s)) { |
6462 | return true; | |
6463 | } | |
6464 | ||
6465 | switch (a->esz) { | |
6466 | case MO_32: | |
6467 | fn = gather_load_fn32[mte][be][0][0][a->u][a->msz]; | |
6468 | break; | |
6469 | case MO_64: | |
6470 | fn = gather_load_fn64[mte][be][0][2][a->u][a->msz]; | |
6471 | break; | |
6472 | } | |
6473 | assert(fn != NULL); | |
6474 | ||
6475 | do_mem_zpz(s, a->rd, a->pg, a->rn, 0, | |
6476 | cpu_reg(s, a->rm), a->msz, false, fn); | |
6477 | return true; | |
cf327449 SL |
6478 | } |
6479 | ||
d28d12f0 RH |
6480 | /* Indexed by [mte][be][xs][msz]. */ |
6481 | static gen_helper_gvec_mem_scatter * const scatter_store_fn32[2][2][2][3] = { | |
6482 | { /* MTE Inactive */ | |
6483 | { /* Little-endian */ | |
6484 | { gen_helper_sve_stbs_zsu, | |
6485 | gen_helper_sve_sths_le_zsu, | |
6486 | gen_helper_sve_stss_le_zsu, }, | |
6487 | { gen_helper_sve_stbs_zss, | |
6488 | gen_helper_sve_sths_le_zss, | |
6489 | gen_helper_sve_stss_le_zss, } }, | |
6490 | { /* Big-endian */ | |
6491 | { gen_helper_sve_stbs_zsu, | |
6492 | gen_helper_sve_sths_be_zsu, | |
6493 | gen_helper_sve_stss_be_zsu, }, | |
6494 | { gen_helper_sve_stbs_zss, | |
6495 | gen_helper_sve_sths_be_zss, | |
6496 | gen_helper_sve_stss_be_zss, } } }, | |
6497 | { /* MTE Active */ | |
6498 | { /* Little-endian */ | |
6499 | { gen_helper_sve_stbs_zsu_mte, | |
6500 | gen_helper_sve_sths_le_zsu_mte, | |
6501 | gen_helper_sve_stss_le_zsu_mte, }, | |
6502 | { gen_helper_sve_stbs_zss_mte, | |
6503 | gen_helper_sve_sths_le_zss_mte, | |
6504 | gen_helper_sve_stss_le_zss_mte, } }, | |
6505 | { /* Big-endian */ | |
6506 | { gen_helper_sve_stbs_zsu_mte, | |
6507 | gen_helper_sve_sths_be_zsu_mte, | |
6508 | gen_helper_sve_stss_be_zsu_mte, }, | |
6509 | { gen_helper_sve_stbs_zss_mte, | |
6510 | gen_helper_sve_sths_be_zss_mte, | |
6511 | gen_helper_sve_stss_be_zss_mte, } } }, | |
408ecde9 RH |
6512 | }; |
6513 | ||
6514 | /* Note that we overload xs=2 to indicate 64-bit offset. */ | |
d28d12f0 RH |
6515 | static gen_helper_gvec_mem_scatter * const scatter_store_fn64[2][2][3][4] = { |
6516 | { /* MTE Inactive */ | |
6517 | { /* Little-endian */ | |
6518 | { gen_helper_sve_stbd_zsu, | |
6519 | gen_helper_sve_sthd_le_zsu, | |
6520 | gen_helper_sve_stsd_le_zsu, | |
6521 | gen_helper_sve_stdd_le_zsu, }, | |
6522 | { gen_helper_sve_stbd_zss, | |
6523 | gen_helper_sve_sthd_le_zss, | |
6524 | gen_helper_sve_stsd_le_zss, | |
6525 | gen_helper_sve_stdd_le_zss, }, | |
6526 | { gen_helper_sve_stbd_zd, | |
6527 | gen_helper_sve_sthd_le_zd, | |
6528 | gen_helper_sve_stsd_le_zd, | |
6529 | gen_helper_sve_stdd_le_zd, } }, | |
6530 | { /* Big-endian */ | |
6531 | { gen_helper_sve_stbd_zsu, | |
6532 | gen_helper_sve_sthd_be_zsu, | |
6533 | gen_helper_sve_stsd_be_zsu, | |
6534 | gen_helper_sve_stdd_be_zsu, }, | |
6535 | { gen_helper_sve_stbd_zss, | |
6536 | gen_helper_sve_sthd_be_zss, | |
6537 | gen_helper_sve_stsd_be_zss, | |
6538 | gen_helper_sve_stdd_be_zss, }, | |
6539 | { gen_helper_sve_stbd_zd, | |
6540 | gen_helper_sve_sthd_be_zd, | |
6541 | gen_helper_sve_stsd_be_zd, | |
6542 | gen_helper_sve_stdd_be_zd, } } }, | |
6543 | { /* MTE Inactive */ | |
6544 | { /* Little-endian */ | |
6545 | { gen_helper_sve_stbd_zsu_mte, | |
6546 | gen_helper_sve_sthd_le_zsu_mte, | |
6547 | gen_helper_sve_stsd_le_zsu_mte, | |
6548 | gen_helper_sve_stdd_le_zsu_mte, }, | |
6549 | { gen_helper_sve_stbd_zss_mte, | |
6550 | gen_helper_sve_sthd_le_zss_mte, | |
6551 | gen_helper_sve_stsd_le_zss_mte, | |
6552 | gen_helper_sve_stdd_le_zss_mte, }, | |
6553 | { gen_helper_sve_stbd_zd_mte, | |
6554 | gen_helper_sve_sthd_le_zd_mte, | |
6555 | gen_helper_sve_stsd_le_zd_mte, | |
6556 | gen_helper_sve_stdd_le_zd_mte, } }, | |
6557 | { /* Big-endian */ | |
6558 | { gen_helper_sve_stbd_zsu_mte, | |
6559 | gen_helper_sve_sthd_be_zsu_mte, | |
6560 | gen_helper_sve_stsd_be_zsu_mte, | |
6561 | gen_helper_sve_stdd_be_zsu_mte, }, | |
6562 | { gen_helper_sve_stbd_zss_mte, | |
6563 | gen_helper_sve_sthd_be_zss_mte, | |
6564 | gen_helper_sve_stsd_be_zss_mte, | |
6565 | gen_helper_sve_stdd_be_zss_mte, }, | |
6566 | { gen_helper_sve_stbd_zd_mte, | |
6567 | gen_helper_sve_sthd_be_zd_mte, | |
6568 | gen_helper_sve_stsd_be_zd_mte, | |
6569 | gen_helper_sve_stdd_be_zd_mte, } } }, | |
408ecde9 RH |
6570 | }; |
6571 | ||
3a7be554 | 6572 | static bool trans_ST1_zprz(DisasContext *s, arg_ST1_zprz *a) |
f6dbf62a | 6573 | { |
f6dbf62a | 6574 | gen_helper_gvec_mem_scatter *fn; |
d28d12f0 RH |
6575 | bool be = s->be_data == MO_BE; |
6576 | bool mte = s->mte_active[0]; | |
f6dbf62a RH |
6577 | |
6578 | if (a->esz < a->msz || (a->msz == 0 && a->scale)) { | |
6579 | return false; | |
6580 | } | |
6581 | if (!sve_access_check(s)) { | |
6582 | return true; | |
6583 | } | |
6584 | switch (a->esz) { | |
6585 | case MO_32: | |
d28d12f0 | 6586 | fn = scatter_store_fn32[mte][be][a->xs][a->msz]; |
f6dbf62a RH |
6587 | break; |
6588 | case MO_64: | |
d28d12f0 | 6589 | fn = scatter_store_fn64[mte][be][a->xs][a->msz]; |
f6dbf62a RH |
6590 | break; |
6591 | default: | |
6592 | g_assert_not_reached(); | |
6593 | } | |
6594 | do_mem_zpz(s, a->rd, a->pg, a->rm, a->scale * a->msz, | |
d28d12f0 | 6595 | cpu_reg_sp(s, a->rn), a->msz, true, fn); |
f6dbf62a RH |
6596 | return true; |
6597 | } | |
dec6cf6b | 6598 | |
3a7be554 | 6599 | static bool trans_ST1_zpiz(DisasContext *s, arg_ST1_zpiz *a) |
408ecde9 RH |
6600 | { |
6601 | gen_helper_gvec_mem_scatter *fn = NULL; | |
d28d12f0 RH |
6602 | bool be = s->be_data == MO_BE; |
6603 | bool mte = s->mte_active[0]; | |
408ecde9 RH |
6604 | |
6605 | if (a->esz < a->msz) { | |
6606 | return false; | |
6607 | } | |
6608 | if (!sve_access_check(s)) { | |
6609 | return true; | |
6610 | } | |
6611 | ||
6612 | switch (a->esz) { | |
6613 | case MO_32: | |
d28d12f0 | 6614 | fn = scatter_store_fn32[mte][be][0][a->msz]; |
408ecde9 RH |
6615 | break; |
6616 | case MO_64: | |
d28d12f0 | 6617 | fn = scatter_store_fn64[mte][be][2][a->msz]; |
408ecde9 RH |
6618 | break; |
6619 | } | |
6620 | assert(fn != NULL); | |
6621 | ||
6622 | /* Treat ST1_zpiz (zn[x] + imm) the same way as ST1_zprz (rn + zm[x]) | |
6623 | * by loading the immediate into the scalar parameter. | |
6624 | */ | |
2ccdf94f RH |
6625 | do_mem_zpz(s, a->rd, a->pg, a->rn, 0, |
6626 | tcg_constant_i64(a->imm << a->msz), a->msz, true, fn); | |
408ecde9 RH |
6627 | return true; |
6628 | } | |
6629 | ||
6ebca45f SL |
6630 | static bool trans_STNT1_zprz(DisasContext *s, arg_ST1_zprz *a) |
6631 | { | |
b17ab470 RH |
6632 | gen_helper_gvec_mem_scatter *fn; |
6633 | bool be = s->be_data == MO_BE; | |
6634 | bool mte = s->mte_active[0]; | |
6635 | ||
6636 | if (a->esz < a->msz) { | |
6637 | return false; | |
6638 | } | |
6ebca45f SL |
6639 | if (!dc_isar_feature(aa64_sve2, s)) { |
6640 | return false; | |
6641 | } | |
b17ab470 RH |
6642 | if (!sve_access_check(s)) { |
6643 | return true; | |
6644 | } | |
6645 | ||
6646 | switch (a->esz) { | |
6647 | case MO_32: | |
6648 | fn = scatter_store_fn32[mte][be][0][a->msz]; | |
6649 | break; | |
6650 | case MO_64: | |
6651 | fn = scatter_store_fn64[mte][be][2][a->msz]; | |
6652 | break; | |
6653 | default: | |
6654 | g_assert_not_reached(); | |
6655 | } | |
6656 | ||
6657 | do_mem_zpz(s, a->rd, a->pg, a->rn, 0, | |
6658 | cpu_reg(s, a->rm), a->msz, true, fn); | |
6659 | return true; | |
6ebca45f SL |
6660 | } |
6661 | ||
dec6cf6b RH |
6662 | /* |
6663 | * Prefetches | |
6664 | */ | |
6665 | ||
3a7be554 | 6666 | static bool trans_PRF(DisasContext *s, arg_PRF *a) |
dec6cf6b RH |
6667 | { |
6668 | /* Prefetch is a nop within QEMU. */ | |
2f95a3b0 | 6669 | (void)sve_access_check(s); |
dec6cf6b RH |
6670 | return true; |
6671 | } | |
6672 | ||
3a7be554 | 6673 | static bool trans_PRF_rr(DisasContext *s, arg_PRF_rr *a) |
dec6cf6b RH |
6674 | { |
6675 | if (a->rm == 31) { | |
6676 | return false; | |
6677 | } | |
6678 | /* Prefetch is a nop within QEMU. */ | |
2f95a3b0 | 6679 | (void)sve_access_check(s); |
dec6cf6b RH |
6680 | return true; |
6681 | } | |
a2103582 RH |
6682 | |
6683 | /* | |
6684 | * Move Prefix | |
6685 | * | |
6686 | * TODO: The implementation so far could handle predicated merging movprfx. | |
6687 | * The helper functions as written take an extra source register to | |
6688 | * use in the operation, but the result is only written when predication | |
6689 | * succeeds. For unpredicated movprfx, we need to rearrange the helpers | |
6690 | * to allow the final write back to the destination to be unconditional. | |
6691 | * For predicated zeroing movprfx, we need to rearrange the helpers to | |
6692 | * allow the final write back to zero inactives. | |
6693 | * | |
6694 | * In the meantime, just emit the moves. | |
6695 | */ | |
6696 | ||
3a7be554 | 6697 | static bool trans_MOVPRFX(DisasContext *s, arg_MOVPRFX *a) |
a2103582 RH |
6698 | { |
6699 | return do_mov_z(s, a->rd, a->rn); | |
6700 | } | |
6701 | ||
3a7be554 | 6702 | static bool trans_MOVPRFX_m(DisasContext *s, arg_rpr_esz *a) |
a2103582 RH |
6703 | { |
6704 | if (sve_access_check(s)) { | |
6705 | do_sel_z(s, a->rd, a->rn, a->rd, a->pg, a->esz); | |
6706 | } | |
6707 | return true; | |
6708 | } | |
6709 | ||
3a7be554 | 6710 | static bool trans_MOVPRFX_z(DisasContext *s, arg_rpr_esz *a) |
a2103582 | 6711 | { |
60245996 | 6712 | return do_movz_zpz(s, a->rd, a->rn, a->pg, a->esz, false); |
a2103582 | 6713 | } |
5dad1ba5 RH |
6714 | |
6715 | /* | |
6716 | * SVE2 Integer Multiply - Unpredicated | |
6717 | */ | |
6718 | ||
6719 | static bool trans_MUL_zzz(DisasContext *s, arg_rrr_esz *a) | |
6720 | { | |
6721 | if (!dc_isar_feature(aa64_sve2, s)) { | |
6722 | return false; | |
6723 | } | |
6724 | if (sve_access_check(s)) { | |
6725 | gen_gvec_fn_zzz(s, tcg_gen_gvec_mul, a->esz, a->rd, a->rn, a->rm); | |
6726 | } | |
6727 | return true; | |
6728 | } | |
6729 | ||
6730 | static bool do_sve2_zzz_ool(DisasContext *s, arg_rrr_esz *a, | |
6731 | gen_helper_gvec_3 *fn) | |
6732 | { | |
6733 | if (fn == NULL || !dc_isar_feature(aa64_sve2, s)) { | |
6734 | return false; | |
6735 | } | |
6736 | if (sve_access_check(s)) { | |
6737 | gen_gvec_ool_zzz(s, fn, a->rd, a->rn, a->rm, 0); | |
6738 | } | |
6739 | return true; | |
6740 | } | |
6741 | ||
6742 | static bool trans_SMULH_zzz(DisasContext *s, arg_rrr_esz *a) | |
6743 | { | |
6744 | static gen_helper_gvec_3 * const fns[4] = { | |
6745 | gen_helper_gvec_smulh_b, gen_helper_gvec_smulh_h, | |
6746 | gen_helper_gvec_smulh_s, gen_helper_gvec_smulh_d, | |
6747 | }; | |
6748 | return do_sve2_zzz_ool(s, a, fns[a->esz]); | |
6749 | } | |
6750 | ||
6751 | static bool trans_UMULH_zzz(DisasContext *s, arg_rrr_esz *a) | |
6752 | { | |
6753 | static gen_helper_gvec_3 * const fns[4] = { | |
6754 | gen_helper_gvec_umulh_b, gen_helper_gvec_umulh_h, | |
6755 | gen_helper_gvec_umulh_s, gen_helper_gvec_umulh_d, | |
6756 | }; | |
6757 | return do_sve2_zzz_ool(s, a, fns[a->esz]); | |
6758 | } | |
6759 | ||
6760 | static bool trans_PMUL_zzz(DisasContext *s, arg_rrr_esz *a) | |
6761 | { | |
6762 | return do_sve2_zzz_ool(s, a, gen_helper_gvec_pmul_b); | |
6763 | } | |
d4b1e59d | 6764 | |
169d7c58 RH |
6765 | static bool trans_SQDMULH_zzz(DisasContext *s, arg_rrr_esz *a) |
6766 | { | |
6767 | static gen_helper_gvec_3 * const fns[4] = { | |
6768 | gen_helper_sve2_sqdmulh_b, gen_helper_sve2_sqdmulh_h, | |
6769 | gen_helper_sve2_sqdmulh_s, gen_helper_sve2_sqdmulh_d, | |
6770 | }; | |
6771 | return do_sve2_zzz_ool(s, a, fns[a->esz]); | |
6772 | } | |
6773 | ||
6774 | static bool trans_SQRDMULH_zzz(DisasContext *s, arg_rrr_esz *a) | |
6775 | { | |
6776 | static gen_helper_gvec_3 * const fns[4] = { | |
6777 | gen_helper_sve2_sqrdmulh_b, gen_helper_sve2_sqrdmulh_h, | |
6778 | gen_helper_sve2_sqrdmulh_s, gen_helper_sve2_sqrdmulh_d, | |
6779 | }; | |
6780 | return do_sve2_zzz_ool(s, a, fns[a->esz]); | |
6781 | } | |
6782 | ||
d4b1e59d RH |
6783 | /* |
6784 | * SVE2 Integer - Predicated | |
6785 | */ | |
6786 | ||
6787 | static bool do_sve2_zpzz_ool(DisasContext *s, arg_rprr_esz *a, | |
6788 | gen_helper_gvec_4 *fn) | |
6789 | { | |
6790 | if (!dc_isar_feature(aa64_sve2, s)) { | |
6791 | return false; | |
6792 | } | |
6793 | return do_zpzz_ool(s, a, fn); | |
6794 | } | |
6795 | ||
6796 | static bool trans_SADALP_zpzz(DisasContext *s, arg_rprr_esz *a) | |
6797 | { | |
6798 | static gen_helper_gvec_4 * const fns[3] = { | |
6799 | gen_helper_sve2_sadalp_zpzz_h, | |
6800 | gen_helper_sve2_sadalp_zpzz_s, | |
6801 | gen_helper_sve2_sadalp_zpzz_d, | |
6802 | }; | |
6803 | if (a->esz == 0) { | |
6804 | return false; | |
6805 | } | |
6806 | return do_sve2_zpzz_ool(s, a, fns[a->esz - 1]); | |
6807 | } | |
6808 | ||
6809 | static bool trans_UADALP_zpzz(DisasContext *s, arg_rprr_esz *a) | |
6810 | { | |
6811 | static gen_helper_gvec_4 * const fns[3] = { | |
6812 | gen_helper_sve2_uadalp_zpzz_h, | |
6813 | gen_helper_sve2_uadalp_zpzz_s, | |
6814 | gen_helper_sve2_uadalp_zpzz_d, | |
6815 | }; | |
6816 | if (a->esz == 0) { | |
6817 | return false; | |
6818 | } | |
6819 | return do_sve2_zpzz_ool(s, a, fns[a->esz - 1]); | |
6820 | } | |
db366da8 RH |
6821 | |
6822 | /* | |
6823 | * SVE2 integer unary operations (predicated) | |
6824 | */ | |
6825 | ||
6826 | static bool do_sve2_zpz_ool(DisasContext *s, arg_rpr_esz *a, | |
6827 | gen_helper_gvec_3 *fn) | |
6828 | { | |
6829 | if (!dc_isar_feature(aa64_sve2, s)) { | |
6830 | return false; | |
6831 | } | |
6832 | return do_zpz_ool(s, a, fn); | |
6833 | } | |
6834 | ||
6835 | static bool trans_URECPE(DisasContext *s, arg_rpr_esz *a) | |
6836 | { | |
6837 | if (a->esz != 2) { | |
6838 | return false; | |
6839 | } | |
6840 | return do_sve2_zpz_ool(s, a, gen_helper_sve2_urecpe_s); | |
6841 | } | |
6842 | ||
6843 | static bool trans_URSQRTE(DisasContext *s, arg_rpr_esz *a) | |
6844 | { | |
6845 | if (a->esz != 2) { | |
6846 | return false; | |
6847 | } | |
6848 | return do_sve2_zpz_ool(s, a, gen_helper_sve2_ursqrte_s); | |
6849 | } | |
6850 | ||
6851 | static bool trans_SQABS(DisasContext *s, arg_rpr_esz *a) | |
6852 | { | |
6853 | static gen_helper_gvec_3 * const fns[4] = { | |
6854 | gen_helper_sve2_sqabs_b, gen_helper_sve2_sqabs_h, | |
6855 | gen_helper_sve2_sqabs_s, gen_helper_sve2_sqabs_d, | |
6856 | }; | |
6857 | return do_sve2_zpz_ool(s, a, fns[a->esz]); | |
6858 | } | |
6859 | ||
6860 | static bool trans_SQNEG(DisasContext *s, arg_rpr_esz *a) | |
6861 | { | |
6862 | static gen_helper_gvec_3 * const fns[4] = { | |
6863 | gen_helper_sve2_sqneg_b, gen_helper_sve2_sqneg_h, | |
6864 | gen_helper_sve2_sqneg_s, gen_helper_sve2_sqneg_d, | |
6865 | }; | |
6866 | return do_sve2_zpz_ool(s, a, fns[a->esz]); | |
6867 | } | |
45d9503d RH |
6868 | |
6869 | #define DO_SVE2_ZPZZ(NAME, name) \ | |
6870 | static bool trans_##NAME(DisasContext *s, arg_rprr_esz *a) \ | |
6871 | { \ | |
6872 | static gen_helper_gvec_4 * const fns[4] = { \ | |
6873 | gen_helper_sve2_##name##_zpzz_b, gen_helper_sve2_##name##_zpzz_h, \ | |
6874 | gen_helper_sve2_##name##_zpzz_s, gen_helper_sve2_##name##_zpzz_d, \ | |
6875 | }; \ | |
6876 | return do_sve2_zpzz_ool(s, a, fns[a->esz]); \ | |
6877 | } | |
6878 | ||
6879 | DO_SVE2_ZPZZ(SQSHL, sqshl) | |
6880 | DO_SVE2_ZPZZ(SQRSHL, sqrshl) | |
6881 | DO_SVE2_ZPZZ(SRSHL, srshl) | |
6882 | ||
6883 | DO_SVE2_ZPZZ(UQSHL, uqshl) | |
6884 | DO_SVE2_ZPZZ(UQRSHL, uqrshl) | |
6885 | DO_SVE2_ZPZZ(URSHL, urshl) | |
a47dc220 RH |
6886 | |
6887 | DO_SVE2_ZPZZ(SHADD, shadd) | |
6888 | DO_SVE2_ZPZZ(SRHADD, srhadd) | |
6889 | DO_SVE2_ZPZZ(SHSUB, shsub) | |
6890 | ||
6891 | DO_SVE2_ZPZZ(UHADD, uhadd) | |
6892 | DO_SVE2_ZPZZ(URHADD, urhadd) | |
6893 | DO_SVE2_ZPZZ(UHSUB, uhsub) | |
8597dc8b RH |
6894 | |
6895 | DO_SVE2_ZPZZ(ADDP, addp) | |
6896 | DO_SVE2_ZPZZ(SMAXP, smaxp) | |
6897 | DO_SVE2_ZPZZ(UMAXP, umaxp) | |
6898 | DO_SVE2_ZPZZ(SMINP, sminp) | |
6899 | DO_SVE2_ZPZZ(UMINP, uminp) | |
4f07fbeb RH |
6900 | |
6901 | DO_SVE2_ZPZZ(SQADD_zpzz, sqadd) | |
6902 | DO_SVE2_ZPZZ(UQADD_zpzz, uqadd) | |
6903 | DO_SVE2_ZPZZ(SQSUB_zpzz, sqsub) | |
6904 | DO_SVE2_ZPZZ(UQSUB_zpzz, uqsub) | |
6905 | DO_SVE2_ZPZZ(SUQADD, suqadd) | |
6906 | DO_SVE2_ZPZZ(USQADD, usqadd) | |
0ce1dda8 RH |
6907 | |
6908 | /* | |
6909 | * SVE2 Widening Integer Arithmetic | |
6910 | */ | |
6911 | ||
6912 | static bool do_sve2_zzw_ool(DisasContext *s, arg_rrr_esz *a, | |
6913 | gen_helper_gvec_3 *fn, int data) | |
6914 | { | |
6915 | if (fn == NULL || !dc_isar_feature(aa64_sve2, s)) { | |
6916 | return false; | |
6917 | } | |
6918 | if (sve_access_check(s)) { | |
6919 | unsigned vsz = vec_full_reg_size(s); | |
6920 | tcg_gen_gvec_3_ool(vec_full_reg_offset(s, a->rd), | |
6921 | vec_full_reg_offset(s, a->rn), | |
6922 | vec_full_reg_offset(s, a->rm), | |
6923 | vsz, vsz, data, fn); | |
6924 | } | |
6925 | return true; | |
6926 | } | |
6927 | ||
6928 | #define DO_SVE2_ZZZ_TB(NAME, name, SEL1, SEL2) \ | |
6929 | static bool trans_##NAME(DisasContext *s, arg_rrr_esz *a) \ | |
6930 | { \ | |
6931 | static gen_helper_gvec_3 * const fns[4] = { \ | |
6932 | NULL, gen_helper_sve2_##name##_h, \ | |
6933 | gen_helper_sve2_##name##_s, gen_helper_sve2_##name##_d, \ | |
6934 | }; \ | |
6935 | return do_sve2_zzw_ool(s, a, fns[a->esz], (SEL2 << 1) | SEL1); \ | |
6936 | } | |
6937 | ||
6938 | DO_SVE2_ZZZ_TB(SADDLB, saddl, false, false) | |
6939 | DO_SVE2_ZZZ_TB(SSUBLB, ssubl, false, false) | |
6940 | DO_SVE2_ZZZ_TB(SABDLB, sabdl, false, false) | |
6941 | ||
6942 | DO_SVE2_ZZZ_TB(UADDLB, uaddl, false, false) | |
6943 | DO_SVE2_ZZZ_TB(USUBLB, usubl, false, false) | |
6944 | DO_SVE2_ZZZ_TB(UABDLB, uabdl, false, false) | |
6945 | ||
6946 | DO_SVE2_ZZZ_TB(SADDLT, saddl, true, true) | |
6947 | DO_SVE2_ZZZ_TB(SSUBLT, ssubl, true, true) | |
6948 | DO_SVE2_ZZZ_TB(SABDLT, sabdl, true, true) | |
6949 | ||
6950 | DO_SVE2_ZZZ_TB(UADDLT, uaddl, true, true) | |
6951 | DO_SVE2_ZZZ_TB(USUBLT, usubl, true, true) | |
6952 | DO_SVE2_ZZZ_TB(UABDLT, uabdl, true, true) | |
daec426b RH |
6953 | |
6954 | DO_SVE2_ZZZ_TB(SADDLBT, saddl, false, true) | |
6955 | DO_SVE2_ZZZ_TB(SSUBLBT, ssubl, false, true) | |
6956 | DO_SVE2_ZZZ_TB(SSUBLTB, ssubl, true, false) | |
81fccf09 | 6957 | |
69ccc099 RH |
6958 | DO_SVE2_ZZZ_TB(SQDMULLB_zzz, sqdmull_zzz, false, false) |
6959 | DO_SVE2_ZZZ_TB(SQDMULLT_zzz, sqdmull_zzz, true, true) | |
6960 | ||
6961 | DO_SVE2_ZZZ_TB(SMULLB_zzz, smull_zzz, false, false) | |
6962 | DO_SVE2_ZZZ_TB(SMULLT_zzz, smull_zzz, true, true) | |
6963 | ||
6964 | DO_SVE2_ZZZ_TB(UMULLB_zzz, umull_zzz, false, false) | |
6965 | DO_SVE2_ZZZ_TB(UMULLT_zzz, umull_zzz, true, true) | |
6966 | ||
2df3ca55 RH |
6967 | static bool do_eor_tb(DisasContext *s, arg_rrr_esz *a, bool sel1) |
6968 | { | |
6969 | static gen_helper_gvec_3 * const fns[4] = { | |
6970 | gen_helper_sve2_eoril_b, gen_helper_sve2_eoril_h, | |
6971 | gen_helper_sve2_eoril_s, gen_helper_sve2_eoril_d, | |
6972 | }; | |
6973 | return do_sve2_zzw_ool(s, a, fns[a->esz], (!sel1 << 1) | sel1); | |
6974 | } | |
6975 | ||
6976 | static bool trans_EORBT(DisasContext *s, arg_rrr_esz *a) | |
6977 | { | |
6978 | return do_eor_tb(s, a, false); | |
6979 | } | |
6980 | ||
6981 | static bool trans_EORTB(DisasContext *s, arg_rrr_esz *a) | |
6982 | { | |
6983 | return do_eor_tb(s, a, true); | |
6984 | } | |
6985 | ||
e3a56131 RH |
6986 | static bool do_trans_pmull(DisasContext *s, arg_rrr_esz *a, bool sel) |
6987 | { | |
6988 | static gen_helper_gvec_3 * const fns[4] = { | |
6989 | gen_helper_gvec_pmull_q, gen_helper_sve2_pmull_h, | |
6990 | NULL, gen_helper_sve2_pmull_d, | |
6991 | }; | |
6992 | if (a->esz == 0 && !dc_isar_feature(aa64_sve2_pmull128, s)) { | |
6993 | return false; | |
6994 | } | |
6995 | return do_sve2_zzw_ool(s, a, fns[a->esz], sel); | |
6996 | } | |
6997 | ||
6998 | static bool trans_PMULLB(DisasContext *s, arg_rrr_esz *a) | |
6999 | { | |
7000 | return do_trans_pmull(s, a, false); | |
7001 | } | |
7002 | ||
7003 | static bool trans_PMULLT(DisasContext *s, arg_rrr_esz *a) | |
7004 | { | |
7005 | return do_trans_pmull(s, a, true); | |
7006 | } | |
7007 | ||
81fccf09 RH |
7008 | #define DO_SVE2_ZZZ_WTB(NAME, name, SEL2) \ |
7009 | static bool trans_##NAME(DisasContext *s, arg_rrr_esz *a) \ | |
7010 | { \ | |
7011 | static gen_helper_gvec_3 * const fns[4] = { \ | |
7012 | NULL, gen_helper_sve2_##name##_h, \ | |
7013 | gen_helper_sve2_##name##_s, gen_helper_sve2_##name##_d, \ | |
7014 | }; \ | |
7015 | return do_sve2_zzw_ool(s, a, fns[a->esz], SEL2); \ | |
7016 | } | |
7017 | ||
7018 | DO_SVE2_ZZZ_WTB(SADDWB, saddw, false) | |
7019 | DO_SVE2_ZZZ_WTB(SADDWT, saddw, true) | |
7020 | DO_SVE2_ZZZ_WTB(SSUBWB, ssubw, false) | |
7021 | DO_SVE2_ZZZ_WTB(SSUBWT, ssubw, true) | |
7022 | ||
7023 | DO_SVE2_ZZZ_WTB(UADDWB, uaddw, false) | |
7024 | DO_SVE2_ZZZ_WTB(UADDWT, uaddw, true) | |
7025 | DO_SVE2_ZZZ_WTB(USUBWB, usubw, false) | |
7026 | DO_SVE2_ZZZ_WTB(USUBWT, usubw, true) | |
4269fef1 RH |
7027 | |
7028 | static void gen_sshll_vec(unsigned vece, TCGv_vec d, TCGv_vec n, int64_t imm) | |
7029 | { | |
7030 | int top = imm & 1; | |
7031 | int shl = imm >> 1; | |
7032 | int halfbits = 4 << vece; | |
7033 | ||
7034 | if (top) { | |
7035 | if (shl == halfbits) { | |
7036 | TCGv_vec t = tcg_temp_new_vec_matching(d); | |
7037 | tcg_gen_dupi_vec(vece, t, MAKE_64BIT_MASK(halfbits, halfbits)); | |
7038 | tcg_gen_and_vec(vece, d, n, t); | |
7039 | tcg_temp_free_vec(t); | |
7040 | } else { | |
7041 | tcg_gen_sari_vec(vece, d, n, halfbits); | |
7042 | tcg_gen_shli_vec(vece, d, d, shl); | |
7043 | } | |
7044 | } else { | |
7045 | tcg_gen_shli_vec(vece, d, n, halfbits); | |
7046 | tcg_gen_sari_vec(vece, d, d, halfbits - shl); | |
7047 | } | |
7048 | } | |
7049 | ||
7050 | static void gen_ushll_i64(unsigned vece, TCGv_i64 d, TCGv_i64 n, int imm) | |
7051 | { | |
7052 | int halfbits = 4 << vece; | |
7053 | int top = imm & 1; | |
7054 | int shl = (imm >> 1); | |
7055 | int shift; | |
7056 | uint64_t mask; | |
7057 | ||
7058 | mask = MAKE_64BIT_MASK(0, halfbits); | |
7059 | mask <<= shl; | |
7060 | mask = dup_const(vece, mask); | |
7061 | ||
7062 | shift = shl - top * halfbits; | |
7063 | if (shift < 0) { | |
7064 | tcg_gen_shri_i64(d, n, -shift); | |
7065 | } else { | |
7066 | tcg_gen_shli_i64(d, n, shift); | |
7067 | } | |
7068 | tcg_gen_andi_i64(d, d, mask); | |
7069 | } | |
7070 | ||
7071 | static void gen_ushll16_i64(TCGv_i64 d, TCGv_i64 n, int64_t imm) | |
7072 | { | |
7073 | gen_ushll_i64(MO_16, d, n, imm); | |
7074 | } | |
7075 | ||
7076 | static void gen_ushll32_i64(TCGv_i64 d, TCGv_i64 n, int64_t imm) | |
7077 | { | |
7078 | gen_ushll_i64(MO_32, d, n, imm); | |
7079 | } | |
7080 | ||
7081 | static void gen_ushll64_i64(TCGv_i64 d, TCGv_i64 n, int64_t imm) | |
7082 | { | |
7083 | gen_ushll_i64(MO_64, d, n, imm); | |
7084 | } | |
7085 | ||
7086 | static void gen_ushll_vec(unsigned vece, TCGv_vec d, TCGv_vec n, int64_t imm) | |
7087 | { | |
7088 | int halfbits = 4 << vece; | |
7089 | int top = imm & 1; | |
7090 | int shl = imm >> 1; | |
7091 | ||
7092 | if (top) { | |
7093 | if (shl == halfbits) { | |
7094 | TCGv_vec t = tcg_temp_new_vec_matching(d); | |
7095 | tcg_gen_dupi_vec(vece, t, MAKE_64BIT_MASK(halfbits, halfbits)); | |
7096 | tcg_gen_and_vec(vece, d, n, t); | |
7097 | tcg_temp_free_vec(t); | |
7098 | } else { | |
7099 | tcg_gen_shri_vec(vece, d, n, halfbits); | |
7100 | tcg_gen_shli_vec(vece, d, d, shl); | |
7101 | } | |
7102 | } else { | |
7103 | if (shl == 0) { | |
7104 | TCGv_vec t = tcg_temp_new_vec_matching(d); | |
7105 | tcg_gen_dupi_vec(vece, t, MAKE_64BIT_MASK(0, halfbits)); | |
7106 | tcg_gen_and_vec(vece, d, n, t); | |
7107 | tcg_temp_free_vec(t); | |
7108 | } else { | |
7109 | tcg_gen_shli_vec(vece, d, n, halfbits); | |
7110 | tcg_gen_shri_vec(vece, d, d, halfbits - shl); | |
7111 | } | |
7112 | } | |
7113 | } | |
7114 | ||
7115 | static bool do_sve2_shll_tb(DisasContext *s, arg_rri_esz *a, | |
7116 | bool sel, bool uns) | |
7117 | { | |
7118 | static const TCGOpcode sshll_list[] = { | |
7119 | INDEX_op_shli_vec, INDEX_op_sari_vec, 0 | |
7120 | }; | |
7121 | static const TCGOpcode ushll_list[] = { | |
7122 | INDEX_op_shli_vec, INDEX_op_shri_vec, 0 | |
7123 | }; | |
7124 | static const GVecGen2i ops[2][3] = { | |
7125 | { { .fniv = gen_sshll_vec, | |
7126 | .opt_opc = sshll_list, | |
7127 | .fno = gen_helper_sve2_sshll_h, | |
7128 | .vece = MO_16 }, | |
7129 | { .fniv = gen_sshll_vec, | |
7130 | .opt_opc = sshll_list, | |
7131 | .fno = gen_helper_sve2_sshll_s, | |
7132 | .vece = MO_32 }, | |
7133 | { .fniv = gen_sshll_vec, | |
7134 | .opt_opc = sshll_list, | |
7135 | .fno = gen_helper_sve2_sshll_d, | |
7136 | .vece = MO_64 } }, | |
7137 | { { .fni8 = gen_ushll16_i64, | |
7138 | .fniv = gen_ushll_vec, | |
7139 | .opt_opc = ushll_list, | |
7140 | .fno = gen_helper_sve2_ushll_h, | |
7141 | .vece = MO_16 }, | |
7142 | { .fni8 = gen_ushll32_i64, | |
7143 | .fniv = gen_ushll_vec, | |
7144 | .opt_opc = ushll_list, | |
7145 | .fno = gen_helper_sve2_ushll_s, | |
7146 | .vece = MO_32 }, | |
7147 | { .fni8 = gen_ushll64_i64, | |
7148 | .fniv = gen_ushll_vec, | |
7149 | .opt_opc = ushll_list, | |
7150 | .fno = gen_helper_sve2_ushll_d, | |
7151 | .vece = MO_64 } }, | |
7152 | }; | |
7153 | ||
7154 | if (a->esz < 0 || a->esz > 2 || !dc_isar_feature(aa64_sve2, s)) { | |
7155 | return false; | |
7156 | } | |
7157 | if (sve_access_check(s)) { | |
7158 | unsigned vsz = vec_full_reg_size(s); | |
7159 | tcg_gen_gvec_2i(vec_full_reg_offset(s, a->rd), | |
7160 | vec_full_reg_offset(s, a->rn), | |
7161 | vsz, vsz, (a->imm << 1) | sel, | |
7162 | &ops[uns][a->esz]); | |
7163 | } | |
7164 | return true; | |
7165 | } | |
7166 | ||
7167 | static bool trans_SSHLLB(DisasContext *s, arg_rri_esz *a) | |
7168 | { | |
7169 | return do_sve2_shll_tb(s, a, false, false); | |
7170 | } | |
7171 | ||
7172 | static bool trans_SSHLLT(DisasContext *s, arg_rri_esz *a) | |
7173 | { | |
7174 | return do_sve2_shll_tb(s, a, true, false); | |
7175 | } | |
7176 | ||
7177 | static bool trans_USHLLB(DisasContext *s, arg_rri_esz *a) | |
7178 | { | |
7179 | return do_sve2_shll_tb(s, a, false, true); | |
7180 | } | |
7181 | ||
7182 | static bool trans_USHLLT(DisasContext *s, arg_rri_esz *a) | |
7183 | { | |
7184 | return do_sve2_shll_tb(s, a, true, true); | |
7185 | } | |
cb9c33b8 RH |
7186 | |
7187 | static bool trans_BEXT(DisasContext *s, arg_rrr_esz *a) | |
7188 | { | |
7189 | static gen_helper_gvec_3 * const fns[4] = { | |
7190 | gen_helper_sve2_bext_b, gen_helper_sve2_bext_h, | |
7191 | gen_helper_sve2_bext_s, gen_helper_sve2_bext_d, | |
7192 | }; | |
7193 | if (!dc_isar_feature(aa64_sve2_bitperm, s)) { | |
7194 | return false; | |
7195 | } | |
7196 | return do_sve2_zzw_ool(s, a, fns[a->esz], 0); | |
7197 | } | |
7198 | ||
7199 | static bool trans_BDEP(DisasContext *s, arg_rrr_esz *a) | |
7200 | { | |
7201 | static gen_helper_gvec_3 * const fns[4] = { | |
7202 | gen_helper_sve2_bdep_b, gen_helper_sve2_bdep_h, | |
7203 | gen_helper_sve2_bdep_s, gen_helper_sve2_bdep_d, | |
7204 | }; | |
7205 | if (!dc_isar_feature(aa64_sve2_bitperm, s)) { | |
7206 | return false; | |
7207 | } | |
7208 | return do_sve2_zzw_ool(s, a, fns[a->esz], 0); | |
7209 | } | |
7210 | ||
7211 | static bool trans_BGRP(DisasContext *s, arg_rrr_esz *a) | |
7212 | { | |
7213 | static gen_helper_gvec_3 * const fns[4] = { | |
7214 | gen_helper_sve2_bgrp_b, gen_helper_sve2_bgrp_h, | |
7215 | gen_helper_sve2_bgrp_s, gen_helper_sve2_bgrp_d, | |
7216 | }; | |
7217 | if (!dc_isar_feature(aa64_sve2_bitperm, s)) { | |
7218 | return false; | |
7219 | } | |
7220 | return do_sve2_zzw_ool(s, a, fns[a->esz], 0); | |
7221 | } | |
ed4a6387 RH |
7222 | |
7223 | static bool do_cadd(DisasContext *s, arg_rrr_esz *a, bool sq, bool rot) | |
7224 | { | |
7225 | static gen_helper_gvec_3 * const fns[2][4] = { | |
7226 | { gen_helper_sve2_cadd_b, gen_helper_sve2_cadd_h, | |
7227 | gen_helper_sve2_cadd_s, gen_helper_sve2_cadd_d }, | |
7228 | { gen_helper_sve2_sqcadd_b, gen_helper_sve2_sqcadd_h, | |
7229 | gen_helper_sve2_sqcadd_s, gen_helper_sve2_sqcadd_d }, | |
7230 | }; | |
7231 | return do_sve2_zzw_ool(s, a, fns[sq][a->esz], rot); | |
7232 | } | |
7233 | ||
7234 | static bool trans_CADD_rot90(DisasContext *s, arg_rrr_esz *a) | |
7235 | { | |
7236 | return do_cadd(s, a, false, false); | |
7237 | } | |
7238 | ||
7239 | static bool trans_CADD_rot270(DisasContext *s, arg_rrr_esz *a) | |
7240 | { | |
7241 | return do_cadd(s, a, false, true); | |
7242 | } | |
7243 | ||
7244 | static bool trans_SQCADD_rot90(DisasContext *s, arg_rrr_esz *a) | |
7245 | { | |
7246 | return do_cadd(s, a, true, false); | |
7247 | } | |
7248 | ||
7249 | static bool trans_SQCADD_rot270(DisasContext *s, arg_rrr_esz *a) | |
7250 | { | |
7251 | return do_cadd(s, a, true, true); | |
7252 | } | |
38650638 RH |
7253 | |
7254 | static bool do_sve2_zzzz_ool(DisasContext *s, arg_rrrr_esz *a, | |
7255 | gen_helper_gvec_4 *fn, int data) | |
7256 | { | |
7257 | if (fn == NULL || !dc_isar_feature(aa64_sve2, s)) { | |
7258 | return false; | |
7259 | } | |
7260 | if (sve_access_check(s)) { | |
7261 | gen_gvec_ool_zzzz(s, fn, a->rd, a->rn, a->rm, a->ra, data); | |
7262 | } | |
7263 | return true; | |
7264 | } | |
7265 | ||
7266 | static bool do_abal(DisasContext *s, arg_rrrr_esz *a, bool uns, bool sel) | |
7267 | { | |
7268 | static gen_helper_gvec_4 * const fns[2][4] = { | |
7269 | { NULL, gen_helper_sve2_sabal_h, | |
7270 | gen_helper_sve2_sabal_s, gen_helper_sve2_sabal_d }, | |
7271 | { NULL, gen_helper_sve2_uabal_h, | |
7272 | gen_helper_sve2_uabal_s, gen_helper_sve2_uabal_d }, | |
7273 | }; | |
7274 | return do_sve2_zzzz_ool(s, a, fns[uns][a->esz], sel); | |
7275 | } | |
7276 | ||
7277 | static bool trans_SABALB(DisasContext *s, arg_rrrr_esz *a) | |
7278 | { | |
7279 | return do_abal(s, a, false, false); | |
7280 | } | |
7281 | ||
7282 | static bool trans_SABALT(DisasContext *s, arg_rrrr_esz *a) | |
7283 | { | |
7284 | return do_abal(s, a, false, true); | |
7285 | } | |
7286 | ||
7287 | static bool trans_UABALB(DisasContext *s, arg_rrrr_esz *a) | |
7288 | { | |
7289 | return do_abal(s, a, true, false); | |
7290 | } | |
7291 | ||
7292 | static bool trans_UABALT(DisasContext *s, arg_rrrr_esz *a) | |
7293 | { | |
7294 | return do_abal(s, a, true, true); | |
7295 | } | |
b8295dfb RH |
7296 | |
7297 | static bool do_adcl(DisasContext *s, arg_rrrr_esz *a, bool sel) | |
7298 | { | |
7299 | static gen_helper_gvec_4 * const fns[2] = { | |
7300 | gen_helper_sve2_adcl_s, | |
7301 | gen_helper_sve2_adcl_d, | |
7302 | }; | |
7303 | /* | |
7304 | * Note that in this case the ESZ field encodes both size and sign. | |
7305 | * Split out 'subtract' into bit 1 of the data field for the helper. | |
7306 | */ | |
7307 | return do_sve2_zzzz_ool(s, a, fns[a->esz & 1], (a->esz & 2) | sel); | |
7308 | } | |
7309 | ||
7310 | static bool trans_ADCLB(DisasContext *s, arg_rrrr_esz *a) | |
7311 | { | |
7312 | return do_adcl(s, a, false); | |
7313 | } | |
7314 | ||
7315 | static bool trans_ADCLT(DisasContext *s, arg_rrrr_esz *a) | |
7316 | { | |
7317 | return do_adcl(s, a, true); | |
7318 | } | |
a7e3a90e RH |
7319 | |
7320 | static bool do_sve2_fn2i(DisasContext *s, arg_rri_esz *a, GVecGen2iFn *fn) | |
7321 | { | |
7322 | if (a->esz < 0 || !dc_isar_feature(aa64_sve2, s)) { | |
7323 | return false; | |
7324 | } | |
7325 | if (sve_access_check(s)) { | |
7326 | unsigned vsz = vec_full_reg_size(s); | |
7327 | unsigned rd_ofs = vec_full_reg_offset(s, a->rd); | |
7328 | unsigned rn_ofs = vec_full_reg_offset(s, a->rn); | |
7329 | fn(a->esz, rd_ofs, rn_ofs, a->imm, vsz, vsz); | |
7330 | } | |
7331 | return true; | |
7332 | } | |
7333 | ||
7334 | static bool trans_SSRA(DisasContext *s, arg_rri_esz *a) | |
7335 | { | |
7336 | return do_sve2_fn2i(s, a, gen_gvec_ssra); | |
7337 | } | |
7338 | ||
7339 | static bool trans_USRA(DisasContext *s, arg_rri_esz *a) | |
7340 | { | |
7341 | return do_sve2_fn2i(s, a, gen_gvec_usra); | |
7342 | } | |
7343 | ||
7344 | static bool trans_SRSRA(DisasContext *s, arg_rri_esz *a) | |
7345 | { | |
7346 | return do_sve2_fn2i(s, a, gen_gvec_srsra); | |
7347 | } | |
7348 | ||
7349 | static bool trans_URSRA(DisasContext *s, arg_rri_esz *a) | |
7350 | { | |
7351 | return do_sve2_fn2i(s, a, gen_gvec_ursra); | |
7352 | } | |
fc12b46a RH |
7353 | |
7354 | static bool trans_SRI(DisasContext *s, arg_rri_esz *a) | |
7355 | { | |
7356 | return do_sve2_fn2i(s, a, gen_gvec_sri); | |
7357 | } | |
7358 | ||
7359 | static bool trans_SLI(DisasContext *s, arg_rri_esz *a) | |
7360 | { | |
7361 | return do_sve2_fn2i(s, a, gen_gvec_sli); | |
7362 | } | |
289a1797 RH |
7363 | |
7364 | static bool do_sve2_fn_zzz(DisasContext *s, arg_rrr_esz *a, GVecGen3Fn *fn) | |
7365 | { | |
7366 | if (!dc_isar_feature(aa64_sve2, s)) { | |
7367 | return false; | |
7368 | } | |
7369 | if (sve_access_check(s)) { | |
7370 | gen_gvec_fn_zzz(s, fn, a->esz, a->rd, a->rn, a->rm); | |
7371 | } | |
7372 | return true; | |
7373 | } | |
7374 | ||
7375 | static bool trans_SABA(DisasContext *s, arg_rrr_esz *a) | |
7376 | { | |
7377 | return do_sve2_fn_zzz(s, a, gen_gvec_saba); | |
7378 | } | |
7379 | ||
7380 | static bool trans_UABA(DisasContext *s, arg_rrr_esz *a) | |
7381 | { | |
7382 | return do_sve2_fn_zzz(s, a, gen_gvec_uaba); | |
7383 | } | |
5ff2838d RH |
7384 | |
7385 | static bool do_sve2_narrow_extract(DisasContext *s, arg_rri_esz *a, | |
7386 | const GVecGen2 ops[3]) | |
7387 | { | |
7388 | if (a->esz < 0 || a->esz > MO_32 || a->imm != 0 || | |
7389 | !dc_isar_feature(aa64_sve2, s)) { | |
7390 | return false; | |
7391 | } | |
7392 | if (sve_access_check(s)) { | |
7393 | unsigned vsz = vec_full_reg_size(s); | |
7394 | tcg_gen_gvec_2(vec_full_reg_offset(s, a->rd), | |
7395 | vec_full_reg_offset(s, a->rn), | |
7396 | vsz, vsz, &ops[a->esz]); | |
7397 | } | |
7398 | return true; | |
7399 | } | |
7400 | ||
7401 | static const TCGOpcode sqxtn_list[] = { | |
7402 | INDEX_op_shli_vec, INDEX_op_smin_vec, INDEX_op_smax_vec, 0 | |
7403 | }; | |
7404 | ||
7405 | static void gen_sqxtnb_vec(unsigned vece, TCGv_vec d, TCGv_vec n) | |
7406 | { | |
7407 | TCGv_vec t = tcg_temp_new_vec_matching(d); | |
7408 | int halfbits = 4 << vece; | |
7409 | int64_t mask = (1ull << halfbits) - 1; | |
7410 | int64_t min = -1ull << (halfbits - 1); | |
7411 | int64_t max = -min - 1; | |
7412 | ||
7413 | tcg_gen_dupi_vec(vece, t, min); | |
7414 | tcg_gen_smax_vec(vece, d, n, t); | |
7415 | tcg_gen_dupi_vec(vece, t, max); | |
7416 | tcg_gen_smin_vec(vece, d, d, t); | |
7417 | tcg_gen_dupi_vec(vece, t, mask); | |
7418 | tcg_gen_and_vec(vece, d, d, t); | |
7419 | tcg_temp_free_vec(t); | |
7420 | } | |
7421 | ||
7422 | static bool trans_SQXTNB(DisasContext *s, arg_rri_esz *a) | |
7423 | { | |
7424 | static const GVecGen2 ops[3] = { | |
7425 | { .fniv = gen_sqxtnb_vec, | |
7426 | .opt_opc = sqxtn_list, | |
7427 | .fno = gen_helper_sve2_sqxtnb_h, | |
7428 | .vece = MO_16 }, | |
7429 | { .fniv = gen_sqxtnb_vec, | |
7430 | .opt_opc = sqxtn_list, | |
7431 | .fno = gen_helper_sve2_sqxtnb_s, | |
7432 | .vece = MO_32 }, | |
7433 | { .fniv = gen_sqxtnb_vec, | |
7434 | .opt_opc = sqxtn_list, | |
7435 | .fno = gen_helper_sve2_sqxtnb_d, | |
7436 | .vece = MO_64 }, | |
7437 | }; | |
7438 | return do_sve2_narrow_extract(s, a, ops); | |
7439 | } | |
7440 | ||
7441 | static void gen_sqxtnt_vec(unsigned vece, TCGv_vec d, TCGv_vec n) | |
7442 | { | |
7443 | TCGv_vec t = tcg_temp_new_vec_matching(d); | |
7444 | int halfbits = 4 << vece; | |
7445 | int64_t mask = (1ull << halfbits) - 1; | |
7446 | int64_t min = -1ull << (halfbits - 1); | |
7447 | int64_t max = -min - 1; | |
7448 | ||
7449 | tcg_gen_dupi_vec(vece, t, min); | |
7450 | tcg_gen_smax_vec(vece, n, n, t); | |
7451 | tcg_gen_dupi_vec(vece, t, max); | |
7452 | tcg_gen_smin_vec(vece, n, n, t); | |
7453 | tcg_gen_shli_vec(vece, n, n, halfbits); | |
7454 | tcg_gen_dupi_vec(vece, t, mask); | |
7455 | tcg_gen_bitsel_vec(vece, d, t, d, n); | |
7456 | tcg_temp_free_vec(t); | |
7457 | } | |
7458 | ||
7459 | static bool trans_SQXTNT(DisasContext *s, arg_rri_esz *a) | |
7460 | { | |
7461 | static const GVecGen2 ops[3] = { | |
7462 | { .fniv = gen_sqxtnt_vec, | |
7463 | .opt_opc = sqxtn_list, | |
7464 | .load_dest = true, | |
7465 | .fno = gen_helper_sve2_sqxtnt_h, | |
7466 | .vece = MO_16 }, | |
7467 | { .fniv = gen_sqxtnt_vec, | |
7468 | .opt_opc = sqxtn_list, | |
7469 | .load_dest = true, | |
7470 | .fno = gen_helper_sve2_sqxtnt_s, | |
7471 | .vece = MO_32 }, | |
7472 | { .fniv = gen_sqxtnt_vec, | |
7473 | .opt_opc = sqxtn_list, | |
7474 | .load_dest = true, | |
7475 | .fno = gen_helper_sve2_sqxtnt_d, | |
7476 | .vece = MO_64 }, | |
7477 | }; | |
7478 | return do_sve2_narrow_extract(s, a, ops); | |
7479 | } | |
7480 | ||
7481 | static const TCGOpcode uqxtn_list[] = { | |
7482 | INDEX_op_shli_vec, INDEX_op_umin_vec, 0 | |
7483 | }; | |
7484 | ||
7485 | static void gen_uqxtnb_vec(unsigned vece, TCGv_vec d, TCGv_vec n) | |
7486 | { | |
7487 | TCGv_vec t = tcg_temp_new_vec_matching(d); | |
7488 | int halfbits = 4 << vece; | |
7489 | int64_t max = (1ull << halfbits) - 1; | |
7490 | ||
7491 | tcg_gen_dupi_vec(vece, t, max); | |
7492 | tcg_gen_umin_vec(vece, d, n, t); | |
7493 | tcg_temp_free_vec(t); | |
7494 | } | |
7495 | ||
7496 | static bool trans_UQXTNB(DisasContext *s, arg_rri_esz *a) | |
7497 | { | |
7498 | static const GVecGen2 ops[3] = { | |
7499 | { .fniv = gen_uqxtnb_vec, | |
7500 | .opt_opc = uqxtn_list, | |
7501 | .fno = gen_helper_sve2_uqxtnb_h, | |
7502 | .vece = MO_16 }, | |
7503 | { .fniv = gen_uqxtnb_vec, | |
7504 | .opt_opc = uqxtn_list, | |
7505 | .fno = gen_helper_sve2_uqxtnb_s, | |
7506 | .vece = MO_32 }, | |
7507 | { .fniv = gen_uqxtnb_vec, | |
7508 | .opt_opc = uqxtn_list, | |
7509 | .fno = gen_helper_sve2_uqxtnb_d, | |
7510 | .vece = MO_64 }, | |
7511 | }; | |
7512 | return do_sve2_narrow_extract(s, a, ops); | |
7513 | } | |
7514 | ||
7515 | static void gen_uqxtnt_vec(unsigned vece, TCGv_vec d, TCGv_vec n) | |
7516 | { | |
7517 | TCGv_vec t = tcg_temp_new_vec_matching(d); | |
7518 | int halfbits = 4 << vece; | |
7519 | int64_t max = (1ull << halfbits) - 1; | |
7520 | ||
7521 | tcg_gen_dupi_vec(vece, t, max); | |
7522 | tcg_gen_umin_vec(vece, n, n, t); | |
7523 | tcg_gen_shli_vec(vece, n, n, halfbits); | |
7524 | tcg_gen_bitsel_vec(vece, d, t, d, n); | |
7525 | tcg_temp_free_vec(t); | |
7526 | } | |
7527 | ||
7528 | static bool trans_UQXTNT(DisasContext *s, arg_rri_esz *a) | |
7529 | { | |
7530 | static const GVecGen2 ops[3] = { | |
7531 | { .fniv = gen_uqxtnt_vec, | |
7532 | .opt_opc = uqxtn_list, | |
7533 | .load_dest = true, | |
7534 | .fno = gen_helper_sve2_uqxtnt_h, | |
7535 | .vece = MO_16 }, | |
7536 | { .fniv = gen_uqxtnt_vec, | |
7537 | .opt_opc = uqxtn_list, | |
7538 | .load_dest = true, | |
7539 | .fno = gen_helper_sve2_uqxtnt_s, | |
7540 | .vece = MO_32 }, | |
7541 | { .fniv = gen_uqxtnt_vec, | |
7542 | .opt_opc = uqxtn_list, | |
7543 | .load_dest = true, | |
7544 | .fno = gen_helper_sve2_uqxtnt_d, | |
7545 | .vece = MO_64 }, | |
7546 | }; | |
7547 | return do_sve2_narrow_extract(s, a, ops); | |
7548 | } | |
7549 | ||
7550 | static const TCGOpcode sqxtun_list[] = { | |
7551 | INDEX_op_shli_vec, INDEX_op_umin_vec, INDEX_op_smax_vec, 0 | |
7552 | }; | |
7553 | ||
7554 | static void gen_sqxtunb_vec(unsigned vece, TCGv_vec d, TCGv_vec n) | |
7555 | { | |
7556 | TCGv_vec t = tcg_temp_new_vec_matching(d); | |
7557 | int halfbits = 4 << vece; | |
7558 | int64_t max = (1ull << halfbits) - 1; | |
7559 | ||
7560 | tcg_gen_dupi_vec(vece, t, 0); | |
7561 | tcg_gen_smax_vec(vece, d, n, t); | |
7562 | tcg_gen_dupi_vec(vece, t, max); | |
7563 | tcg_gen_umin_vec(vece, d, d, t); | |
7564 | tcg_temp_free_vec(t); | |
7565 | } | |
7566 | ||
7567 | static bool trans_SQXTUNB(DisasContext *s, arg_rri_esz *a) | |
7568 | { | |
7569 | static const GVecGen2 ops[3] = { | |
7570 | { .fniv = gen_sqxtunb_vec, | |
7571 | .opt_opc = sqxtun_list, | |
7572 | .fno = gen_helper_sve2_sqxtunb_h, | |
7573 | .vece = MO_16 }, | |
7574 | { .fniv = gen_sqxtunb_vec, | |
7575 | .opt_opc = sqxtun_list, | |
7576 | .fno = gen_helper_sve2_sqxtunb_s, | |
7577 | .vece = MO_32 }, | |
7578 | { .fniv = gen_sqxtunb_vec, | |
7579 | .opt_opc = sqxtun_list, | |
7580 | .fno = gen_helper_sve2_sqxtunb_d, | |
7581 | .vece = MO_64 }, | |
7582 | }; | |
7583 | return do_sve2_narrow_extract(s, a, ops); | |
7584 | } | |
7585 | ||
7586 | static void gen_sqxtunt_vec(unsigned vece, TCGv_vec d, TCGv_vec n) | |
7587 | { | |
7588 | TCGv_vec t = tcg_temp_new_vec_matching(d); | |
7589 | int halfbits = 4 << vece; | |
7590 | int64_t max = (1ull << halfbits) - 1; | |
7591 | ||
7592 | tcg_gen_dupi_vec(vece, t, 0); | |
7593 | tcg_gen_smax_vec(vece, n, n, t); | |
7594 | tcg_gen_dupi_vec(vece, t, max); | |
7595 | tcg_gen_umin_vec(vece, n, n, t); | |
7596 | tcg_gen_shli_vec(vece, n, n, halfbits); | |
7597 | tcg_gen_bitsel_vec(vece, d, t, d, n); | |
7598 | tcg_temp_free_vec(t); | |
7599 | } | |
7600 | ||
7601 | static bool trans_SQXTUNT(DisasContext *s, arg_rri_esz *a) | |
7602 | { | |
7603 | static const GVecGen2 ops[3] = { | |
7604 | { .fniv = gen_sqxtunt_vec, | |
7605 | .opt_opc = sqxtun_list, | |
7606 | .load_dest = true, | |
7607 | .fno = gen_helper_sve2_sqxtunt_h, | |
7608 | .vece = MO_16 }, | |
7609 | { .fniv = gen_sqxtunt_vec, | |
7610 | .opt_opc = sqxtun_list, | |
7611 | .load_dest = true, | |
7612 | .fno = gen_helper_sve2_sqxtunt_s, | |
7613 | .vece = MO_32 }, | |
7614 | { .fniv = gen_sqxtunt_vec, | |
7615 | .opt_opc = sqxtun_list, | |
7616 | .load_dest = true, | |
7617 | .fno = gen_helper_sve2_sqxtunt_d, | |
7618 | .vece = MO_64 }, | |
7619 | }; | |
7620 | return do_sve2_narrow_extract(s, a, ops); | |
46d111b2 RH |
7621 | } |
7622 | ||
7623 | static bool do_sve2_shr_narrow(DisasContext *s, arg_rri_esz *a, | |
7624 | const GVecGen2i ops[3]) | |
7625 | { | |
7626 | if (a->esz < 0 || a->esz > MO_32 || !dc_isar_feature(aa64_sve2, s)) { | |
7627 | return false; | |
7628 | } | |
7629 | assert(a->imm > 0 && a->imm <= (8 << a->esz)); | |
7630 | if (sve_access_check(s)) { | |
7631 | unsigned vsz = vec_full_reg_size(s); | |
7632 | tcg_gen_gvec_2i(vec_full_reg_offset(s, a->rd), | |
7633 | vec_full_reg_offset(s, a->rn), | |
7634 | vsz, vsz, a->imm, &ops[a->esz]); | |
7635 | } | |
7636 | return true; | |
7637 | } | |
7638 | ||
7639 | static void gen_shrnb_i64(unsigned vece, TCGv_i64 d, TCGv_i64 n, int shr) | |
7640 | { | |
7641 | int halfbits = 4 << vece; | |
7642 | uint64_t mask = dup_const(vece, MAKE_64BIT_MASK(0, halfbits)); | |
7643 | ||
7644 | tcg_gen_shri_i64(d, n, shr); | |
7645 | tcg_gen_andi_i64(d, d, mask); | |
7646 | } | |
7647 | ||
7648 | static void gen_shrnb16_i64(TCGv_i64 d, TCGv_i64 n, int64_t shr) | |
7649 | { | |
7650 | gen_shrnb_i64(MO_16, d, n, shr); | |
7651 | } | |
7652 | ||
7653 | static void gen_shrnb32_i64(TCGv_i64 d, TCGv_i64 n, int64_t shr) | |
7654 | { | |
7655 | gen_shrnb_i64(MO_32, d, n, shr); | |
7656 | } | |
7657 | ||
7658 | static void gen_shrnb64_i64(TCGv_i64 d, TCGv_i64 n, int64_t shr) | |
7659 | { | |
7660 | gen_shrnb_i64(MO_64, d, n, shr); | |
7661 | } | |
7662 | ||
7663 | static void gen_shrnb_vec(unsigned vece, TCGv_vec d, TCGv_vec n, int64_t shr) | |
7664 | { | |
7665 | TCGv_vec t = tcg_temp_new_vec_matching(d); | |
7666 | int halfbits = 4 << vece; | |
7667 | uint64_t mask = MAKE_64BIT_MASK(0, halfbits); | |
7668 | ||
7669 | tcg_gen_shri_vec(vece, n, n, shr); | |
7670 | tcg_gen_dupi_vec(vece, t, mask); | |
7671 | tcg_gen_and_vec(vece, d, n, t); | |
7672 | tcg_temp_free_vec(t); | |
7673 | } | |
7674 | ||
7675 | static bool trans_SHRNB(DisasContext *s, arg_rri_esz *a) | |
7676 | { | |
7677 | static const TCGOpcode vec_list[] = { INDEX_op_shri_vec, 0 }; | |
7678 | static const GVecGen2i ops[3] = { | |
7679 | { .fni8 = gen_shrnb16_i64, | |
7680 | .fniv = gen_shrnb_vec, | |
7681 | .opt_opc = vec_list, | |
7682 | .fno = gen_helper_sve2_shrnb_h, | |
7683 | .vece = MO_16 }, | |
7684 | { .fni8 = gen_shrnb32_i64, | |
7685 | .fniv = gen_shrnb_vec, | |
7686 | .opt_opc = vec_list, | |
7687 | .fno = gen_helper_sve2_shrnb_s, | |
7688 | .vece = MO_32 }, | |
7689 | { .fni8 = gen_shrnb64_i64, | |
7690 | .fniv = gen_shrnb_vec, | |
7691 | .opt_opc = vec_list, | |
7692 | .fno = gen_helper_sve2_shrnb_d, | |
7693 | .vece = MO_64 }, | |
7694 | }; | |
7695 | return do_sve2_shr_narrow(s, a, ops); | |
7696 | } | |
7697 | ||
7698 | static void gen_shrnt_i64(unsigned vece, TCGv_i64 d, TCGv_i64 n, int shr) | |
7699 | { | |
7700 | int halfbits = 4 << vece; | |
7701 | uint64_t mask = dup_const(vece, MAKE_64BIT_MASK(0, halfbits)); | |
7702 | ||
7703 | tcg_gen_shli_i64(n, n, halfbits - shr); | |
7704 | tcg_gen_andi_i64(n, n, ~mask); | |
7705 | tcg_gen_andi_i64(d, d, mask); | |
7706 | tcg_gen_or_i64(d, d, n); | |
7707 | } | |
7708 | ||
7709 | static void gen_shrnt16_i64(TCGv_i64 d, TCGv_i64 n, int64_t shr) | |
7710 | { | |
7711 | gen_shrnt_i64(MO_16, d, n, shr); | |
7712 | } | |
7713 | ||
7714 | static void gen_shrnt32_i64(TCGv_i64 d, TCGv_i64 n, int64_t shr) | |
7715 | { | |
7716 | gen_shrnt_i64(MO_32, d, n, shr); | |
7717 | } | |
7718 | ||
7719 | static void gen_shrnt64_i64(TCGv_i64 d, TCGv_i64 n, int64_t shr) | |
7720 | { | |
7721 | tcg_gen_shri_i64(n, n, shr); | |
7722 | tcg_gen_deposit_i64(d, d, n, 32, 32); | |
7723 | } | |
7724 | ||
7725 | static void gen_shrnt_vec(unsigned vece, TCGv_vec d, TCGv_vec n, int64_t shr) | |
7726 | { | |
7727 | TCGv_vec t = tcg_temp_new_vec_matching(d); | |
7728 | int halfbits = 4 << vece; | |
7729 | uint64_t mask = MAKE_64BIT_MASK(0, halfbits); | |
7730 | ||
7731 | tcg_gen_shli_vec(vece, n, n, halfbits - shr); | |
7732 | tcg_gen_dupi_vec(vece, t, mask); | |
7733 | tcg_gen_bitsel_vec(vece, d, t, d, n); | |
7734 | tcg_temp_free_vec(t); | |
7735 | } | |
7736 | ||
7737 | static bool trans_SHRNT(DisasContext *s, arg_rri_esz *a) | |
7738 | { | |
7739 | static const TCGOpcode vec_list[] = { INDEX_op_shli_vec, 0 }; | |
7740 | static const GVecGen2i ops[3] = { | |
7741 | { .fni8 = gen_shrnt16_i64, | |
7742 | .fniv = gen_shrnt_vec, | |
7743 | .opt_opc = vec_list, | |
7744 | .load_dest = true, | |
7745 | .fno = gen_helper_sve2_shrnt_h, | |
7746 | .vece = MO_16 }, | |
7747 | { .fni8 = gen_shrnt32_i64, | |
7748 | .fniv = gen_shrnt_vec, | |
7749 | .opt_opc = vec_list, | |
7750 | .load_dest = true, | |
7751 | .fno = gen_helper_sve2_shrnt_s, | |
7752 | .vece = MO_32 }, | |
7753 | { .fni8 = gen_shrnt64_i64, | |
7754 | .fniv = gen_shrnt_vec, | |
7755 | .opt_opc = vec_list, | |
7756 | .load_dest = true, | |
7757 | .fno = gen_helper_sve2_shrnt_d, | |
7758 | .vece = MO_64 }, | |
7759 | }; | |
7760 | return do_sve2_shr_narrow(s, a, ops); | |
7761 | } | |
7762 | ||
7763 | static bool trans_RSHRNB(DisasContext *s, arg_rri_esz *a) | |
7764 | { | |
7765 | static const GVecGen2i ops[3] = { | |
7766 | { .fno = gen_helper_sve2_rshrnb_h }, | |
7767 | { .fno = gen_helper_sve2_rshrnb_s }, | |
7768 | { .fno = gen_helper_sve2_rshrnb_d }, | |
7769 | }; | |
7770 | return do_sve2_shr_narrow(s, a, ops); | |
7771 | } | |
7772 | ||
7773 | static bool trans_RSHRNT(DisasContext *s, arg_rri_esz *a) | |
7774 | { | |
7775 | static const GVecGen2i ops[3] = { | |
7776 | { .fno = gen_helper_sve2_rshrnt_h }, | |
7777 | { .fno = gen_helper_sve2_rshrnt_s }, | |
7778 | { .fno = gen_helper_sve2_rshrnt_d }, | |
7779 | }; | |
7780 | return do_sve2_shr_narrow(s, a, ops); | |
81fd3e6e RH |
7781 | } |
7782 | ||
7783 | static void gen_sqshrunb_vec(unsigned vece, TCGv_vec d, | |
7784 | TCGv_vec n, int64_t shr) | |
7785 | { | |
7786 | TCGv_vec t = tcg_temp_new_vec_matching(d); | |
7787 | int halfbits = 4 << vece; | |
7788 | ||
7789 | tcg_gen_sari_vec(vece, n, n, shr); | |
7790 | tcg_gen_dupi_vec(vece, t, 0); | |
7791 | tcg_gen_smax_vec(vece, n, n, t); | |
7792 | tcg_gen_dupi_vec(vece, t, MAKE_64BIT_MASK(0, halfbits)); | |
7793 | tcg_gen_umin_vec(vece, d, n, t); | |
7794 | tcg_temp_free_vec(t); | |
7795 | } | |
7796 | ||
7797 | static bool trans_SQSHRUNB(DisasContext *s, arg_rri_esz *a) | |
7798 | { | |
7799 | static const TCGOpcode vec_list[] = { | |
7800 | INDEX_op_sari_vec, INDEX_op_smax_vec, INDEX_op_umin_vec, 0 | |
7801 | }; | |
7802 | static const GVecGen2i ops[3] = { | |
7803 | { .fniv = gen_sqshrunb_vec, | |
7804 | .opt_opc = vec_list, | |
7805 | .fno = gen_helper_sve2_sqshrunb_h, | |
7806 | .vece = MO_16 }, | |
7807 | { .fniv = gen_sqshrunb_vec, | |
7808 | .opt_opc = vec_list, | |
7809 | .fno = gen_helper_sve2_sqshrunb_s, | |
7810 | .vece = MO_32 }, | |
7811 | { .fniv = gen_sqshrunb_vec, | |
7812 | .opt_opc = vec_list, | |
7813 | .fno = gen_helper_sve2_sqshrunb_d, | |
7814 | .vece = MO_64 }, | |
7815 | }; | |
7816 | return do_sve2_shr_narrow(s, a, ops); | |
7817 | } | |
7818 | ||
7819 | static void gen_sqshrunt_vec(unsigned vece, TCGv_vec d, | |
7820 | TCGv_vec n, int64_t shr) | |
7821 | { | |
7822 | TCGv_vec t = tcg_temp_new_vec_matching(d); | |
7823 | int halfbits = 4 << vece; | |
7824 | ||
7825 | tcg_gen_sari_vec(vece, n, n, shr); | |
7826 | tcg_gen_dupi_vec(vece, t, 0); | |
7827 | tcg_gen_smax_vec(vece, n, n, t); | |
7828 | tcg_gen_dupi_vec(vece, t, MAKE_64BIT_MASK(0, halfbits)); | |
7829 | tcg_gen_umin_vec(vece, n, n, t); | |
7830 | tcg_gen_shli_vec(vece, n, n, halfbits); | |
7831 | tcg_gen_bitsel_vec(vece, d, t, d, n); | |
7832 | tcg_temp_free_vec(t); | |
7833 | } | |
7834 | ||
7835 | static bool trans_SQSHRUNT(DisasContext *s, arg_rri_esz *a) | |
7836 | { | |
7837 | static const TCGOpcode vec_list[] = { | |
7838 | INDEX_op_shli_vec, INDEX_op_sari_vec, | |
7839 | INDEX_op_smax_vec, INDEX_op_umin_vec, 0 | |
7840 | }; | |
7841 | static const GVecGen2i ops[3] = { | |
7842 | { .fniv = gen_sqshrunt_vec, | |
7843 | .opt_opc = vec_list, | |
7844 | .load_dest = true, | |
7845 | .fno = gen_helper_sve2_sqshrunt_h, | |
7846 | .vece = MO_16 }, | |
7847 | { .fniv = gen_sqshrunt_vec, | |
7848 | .opt_opc = vec_list, | |
7849 | .load_dest = true, | |
7850 | .fno = gen_helper_sve2_sqshrunt_s, | |
7851 | .vece = MO_32 }, | |
7852 | { .fniv = gen_sqshrunt_vec, | |
7853 | .opt_opc = vec_list, | |
7854 | .load_dest = true, | |
7855 | .fno = gen_helper_sve2_sqshrunt_d, | |
7856 | .vece = MO_64 }, | |
7857 | }; | |
7858 | return do_sve2_shr_narrow(s, a, ops); | |
7859 | } | |
7860 | ||
7861 | static bool trans_SQRSHRUNB(DisasContext *s, arg_rri_esz *a) | |
7862 | { | |
7863 | static const GVecGen2i ops[3] = { | |
7864 | { .fno = gen_helper_sve2_sqrshrunb_h }, | |
7865 | { .fno = gen_helper_sve2_sqrshrunb_s }, | |
7866 | { .fno = gen_helper_sve2_sqrshrunb_d }, | |
7867 | }; | |
7868 | return do_sve2_shr_narrow(s, a, ops); | |
7869 | } | |
7870 | ||
7871 | static bool trans_SQRSHRUNT(DisasContext *s, arg_rri_esz *a) | |
7872 | { | |
7873 | static const GVecGen2i ops[3] = { | |
7874 | { .fno = gen_helper_sve2_sqrshrunt_h }, | |
7875 | { .fno = gen_helper_sve2_sqrshrunt_s }, | |
7876 | { .fno = gen_helper_sve2_sqrshrunt_d }, | |
7877 | }; | |
7878 | return do_sve2_shr_narrow(s, a, ops); | |
c13418da RH |
7879 | } |
7880 | ||
743bb147 RH |
7881 | static void gen_sqshrnb_vec(unsigned vece, TCGv_vec d, |
7882 | TCGv_vec n, int64_t shr) | |
7883 | { | |
7884 | TCGv_vec t = tcg_temp_new_vec_matching(d); | |
7885 | int halfbits = 4 << vece; | |
7886 | int64_t max = MAKE_64BIT_MASK(0, halfbits - 1); | |
7887 | int64_t min = -max - 1; | |
7888 | ||
7889 | tcg_gen_sari_vec(vece, n, n, shr); | |
7890 | tcg_gen_dupi_vec(vece, t, min); | |
7891 | tcg_gen_smax_vec(vece, n, n, t); | |
7892 | tcg_gen_dupi_vec(vece, t, max); | |
7893 | tcg_gen_smin_vec(vece, n, n, t); | |
7894 | tcg_gen_dupi_vec(vece, t, MAKE_64BIT_MASK(0, halfbits)); | |
7895 | tcg_gen_and_vec(vece, d, n, t); | |
7896 | tcg_temp_free_vec(t); | |
7897 | } | |
7898 | ||
7899 | static bool trans_SQSHRNB(DisasContext *s, arg_rri_esz *a) | |
7900 | { | |
7901 | static const TCGOpcode vec_list[] = { | |
7902 | INDEX_op_sari_vec, INDEX_op_smax_vec, INDEX_op_smin_vec, 0 | |
7903 | }; | |
7904 | static const GVecGen2i ops[3] = { | |
7905 | { .fniv = gen_sqshrnb_vec, | |
7906 | .opt_opc = vec_list, | |
7907 | .fno = gen_helper_sve2_sqshrnb_h, | |
7908 | .vece = MO_16 }, | |
7909 | { .fniv = gen_sqshrnb_vec, | |
7910 | .opt_opc = vec_list, | |
7911 | .fno = gen_helper_sve2_sqshrnb_s, | |
7912 | .vece = MO_32 }, | |
7913 | { .fniv = gen_sqshrnb_vec, | |
7914 | .opt_opc = vec_list, | |
7915 | .fno = gen_helper_sve2_sqshrnb_d, | |
7916 | .vece = MO_64 }, | |
7917 | }; | |
7918 | return do_sve2_shr_narrow(s, a, ops); | |
7919 | } | |
7920 | ||
7921 | static void gen_sqshrnt_vec(unsigned vece, TCGv_vec d, | |
7922 | TCGv_vec n, int64_t shr) | |
7923 | { | |
7924 | TCGv_vec t = tcg_temp_new_vec_matching(d); | |
7925 | int halfbits = 4 << vece; | |
7926 | int64_t max = MAKE_64BIT_MASK(0, halfbits - 1); | |
7927 | int64_t min = -max - 1; | |
7928 | ||
7929 | tcg_gen_sari_vec(vece, n, n, shr); | |
7930 | tcg_gen_dupi_vec(vece, t, min); | |
7931 | tcg_gen_smax_vec(vece, n, n, t); | |
7932 | tcg_gen_dupi_vec(vece, t, max); | |
7933 | tcg_gen_smin_vec(vece, n, n, t); | |
7934 | tcg_gen_shli_vec(vece, n, n, halfbits); | |
7935 | tcg_gen_dupi_vec(vece, t, MAKE_64BIT_MASK(0, halfbits)); | |
7936 | tcg_gen_bitsel_vec(vece, d, t, d, n); | |
7937 | tcg_temp_free_vec(t); | |
7938 | } | |
7939 | ||
7940 | static bool trans_SQSHRNT(DisasContext *s, arg_rri_esz *a) | |
7941 | { | |
7942 | static const TCGOpcode vec_list[] = { | |
7943 | INDEX_op_shli_vec, INDEX_op_sari_vec, | |
7944 | INDEX_op_smax_vec, INDEX_op_smin_vec, 0 | |
7945 | }; | |
7946 | static const GVecGen2i ops[3] = { | |
7947 | { .fniv = gen_sqshrnt_vec, | |
7948 | .opt_opc = vec_list, | |
7949 | .load_dest = true, | |
7950 | .fno = gen_helper_sve2_sqshrnt_h, | |
7951 | .vece = MO_16 }, | |
7952 | { .fniv = gen_sqshrnt_vec, | |
7953 | .opt_opc = vec_list, | |
7954 | .load_dest = true, | |
7955 | .fno = gen_helper_sve2_sqshrnt_s, | |
7956 | .vece = MO_32 }, | |
7957 | { .fniv = gen_sqshrnt_vec, | |
7958 | .opt_opc = vec_list, | |
7959 | .load_dest = true, | |
7960 | .fno = gen_helper_sve2_sqshrnt_d, | |
7961 | .vece = MO_64 }, | |
7962 | }; | |
7963 | return do_sve2_shr_narrow(s, a, ops); | |
7964 | } | |
7965 | ||
7966 | static bool trans_SQRSHRNB(DisasContext *s, arg_rri_esz *a) | |
7967 | { | |
7968 | static const GVecGen2i ops[3] = { | |
7969 | { .fno = gen_helper_sve2_sqrshrnb_h }, | |
7970 | { .fno = gen_helper_sve2_sqrshrnb_s }, | |
7971 | { .fno = gen_helper_sve2_sqrshrnb_d }, | |
7972 | }; | |
7973 | return do_sve2_shr_narrow(s, a, ops); | |
7974 | } | |
7975 | ||
7976 | static bool trans_SQRSHRNT(DisasContext *s, arg_rri_esz *a) | |
7977 | { | |
7978 | static const GVecGen2i ops[3] = { | |
7979 | { .fno = gen_helper_sve2_sqrshrnt_h }, | |
7980 | { .fno = gen_helper_sve2_sqrshrnt_s }, | |
7981 | { .fno = gen_helper_sve2_sqrshrnt_d }, | |
7982 | }; | |
7983 | return do_sve2_shr_narrow(s, a, ops); | |
7984 | } | |
7985 | ||
c13418da RH |
7986 | static void gen_uqshrnb_vec(unsigned vece, TCGv_vec d, |
7987 | TCGv_vec n, int64_t shr) | |
7988 | { | |
7989 | TCGv_vec t = tcg_temp_new_vec_matching(d); | |
7990 | int halfbits = 4 << vece; | |
7991 | ||
7992 | tcg_gen_shri_vec(vece, n, n, shr); | |
7993 | tcg_gen_dupi_vec(vece, t, MAKE_64BIT_MASK(0, halfbits)); | |
7994 | tcg_gen_umin_vec(vece, d, n, t); | |
7995 | tcg_temp_free_vec(t); | |
7996 | } | |
7997 | ||
7998 | static bool trans_UQSHRNB(DisasContext *s, arg_rri_esz *a) | |
7999 | { | |
8000 | static const TCGOpcode vec_list[] = { | |
8001 | INDEX_op_shri_vec, INDEX_op_umin_vec, 0 | |
8002 | }; | |
8003 | static const GVecGen2i ops[3] = { | |
8004 | { .fniv = gen_uqshrnb_vec, | |
8005 | .opt_opc = vec_list, | |
8006 | .fno = gen_helper_sve2_uqshrnb_h, | |
8007 | .vece = MO_16 }, | |
8008 | { .fniv = gen_uqshrnb_vec, | |
8009 | .opt_opc = vec_list, | |
8010 | .fno = gen_helper_sve2_uqshrnb_s, | |
8011 | .vece = MO_32 }, | |
8012 | { .fniv = gen_uqshrnb_vec, | |
8013 | .opt_opc = vec_list, | |
8014 | .fno = gen_helper_sve2_uqshrnb_d, | |
8015 | .vece = MO_64 }, | |
8016 | }; | |
8017 | return do_sve2_shr_narrow(s, a, ops); | |
8018 | } | |
8019 | ||
8020 | static void gen_uqshrnt_vec(unsigned vece, TCGv_vec d, | |
8021 | TCGv_vec n, int64_t shr) | |
8022 | { | |
8023 | TCGv_vec t = tcg_temp_new_vec_matching(d); | |
8024 | int halfbits = 4 << vece; | |
8025 | ||
8026 | tcg_gen_shri_vec(vece, n, n, shr); | |
8027 | tcg_gen_dupi_vec(vece, t, MAKE_64BIT_MASK(0, halfbits)); | |
8028 | tcg_gen_umin_vec(vece, n, n, t); | |
8029 | tcg_gen_shli_vec(vece, n, n, halfbits); | |
8030 | tcg_gen_bitsel_vec(vece, d, t, d, n); | |
8031 | tcg_temp_free_vec(t); | |
8032 | } | |
8033 | ||
8034 | static bool trans_UQSHRNT(DisasContext *s, arg_rri_esz *a) | |
8035 | { | |
8036 | static const TCGOpcode vec_list[] = { | |
8037 | INDEX_op_shli_vec, INDEX_op_shri_vec, INDEX_op_umin_vec, 0 | |
8038 | }; | |
8039 | static const GVecGen2i ops[3] = { | |
8040 | { .fniv = gen_uqshrnt_vec, | |
8041 | .opt_opc = vec_list, | |
8042 | .load_dest = true, | |
8043 | .fno = gen_helper_sve2_uqshrnt_h, | |
8044 | .vece = MO_16 }, | |
8045 | { .fniv = gen_uqshrnt_vec, | |
8046 | .opt_opc = vec_list, | |
8047 | .load_dest = true, | |
8048 | .fno = gen_helper_sve2_uqshrnt_s, | |
8049 | .vece = MO_32 }, | |
8050 | { .fniv = gen_uqshrnt_vec, | |
8051 | .opt_opc = vec_list, | |
8052 | .load_dest = true, | |
8053 | .fno = gen_helper_sve2_uqshrnt_d, | |
8054 | .vece = MO_64 }, | |
8055 | }; | |
8056 | return do_sve2_shr_narrow(s, a, ops); | |
8057 | } | |
8058 | ||
8059 | static bool trans_UQRSHRNB(DisasContext *s, arg_rri_esz *a) | |
8060 | { | |
8061 | static const GVecGen2i ops[3] = { | |
8062 | { .fno = gen_helper_sve2_uqrshrnb_h }, | |
8063 | { .fno = gen_helper_sve2_uqrshrnb_s }, | |
8064 | { .fno = gen_helper_sve2_uqrshrnb_d }, | |
8065 | }; | |
8066 | return do_sve2_shr_narrow(s, a, ops); | |
8067 | } | |
8068 | ||
8069 | static bool trans_UQRSHRNT(DisasContext *s, arg_rri_esz *a) | |
8070 | { | |
8071 | static const GVecGen2i ops[3] = { | |
8072 | { .fno = gen_helper_sve2_uqrshrnt_h }, | |
8073 | { .fno = gen_helper_sve2_uqrshrnt_s }, | |
8074 | { .fno = gen_helper_sve2_uqrshrnt_d }, | |
8075 | }; | |
8076 | return do_sve2_shr_narrow(s, a, ops); | |
5ff2838d | 8077 | } |
b87dbeeb | 8078 | |
40d5ea50 SL |
8079 | #define DO_SVE2_ZZZ_NARROW(NAME, name) \ |
8080 | static bool trans_##NAME(DisasContext *s, arg_rrr_esz *a) \ | |
8081 | { \ | |
8082 | static gen_helper_gvec_3 * const fns[4] = { \ | |
8083 | NULL, gen_helper_sve2_##name##_h, \ | |
8084 | gen_helper_sve2_##name##_s, gen_helper_sve2_##name##_d, \ | |
8085 | }; \ | |
8086 | return do_sve2_zzz_ool(s, a, fns[a->esz]); \ | |
8087 | } | |
8088 | ||
8089 | DO_SVE2_ZZZ_NARROW(ADDHNB, addhnb) | |
8090 | DO_SVE2_ZZZ_NARROW(ADDHNT, addhnt) | |
0ea3ff02 SL |
8091 | DO_SVE2_ZZZ_NARROW(RADDHNB, raddhnb) |
8092 | DO_SVE2_ZZZ_NARROW(RADDHNT, raddhnt) | |
40d5ea50 | 8093 | |
c3cd6766 SL |
8094 | DO_SVE2_ZZZ_NARROW(SUBHNB, subhnb) |
8095 | DO_SVE2_ZZZ_NARROW(SUBHNT, subhnt) | |
e9443d10 SL |
8096 | DO_SVE2_ZZZ_NARROW(RSUBHNB, rsubhnb) |
8097 | DO_SVE2_ZZZ_NARROW(RSUBHNT, rsubhnt) | |
c3cd6766 | 8098 | |
e0ae6ec3 SL |
8099 | static bool do_sve2_ppzz_flags(DisasContext *s, arg_rprr_esz *a, |
8100 | gen_helper_gvec_flags_4 *fn) | |
8101 | { | |
8102 | if (!dc_isar_feature(aa64_sve2, s)) { | |
8103 | return false; | |
8104 | } | |
8105 | return do_ppzz_flags(s, a, fn); | |
8106 | } | |
8107 | ||
8108 | #define DO_SVE2_PPZZ_MATCH(NAME, name) \ | |
8109 | static bool trans_##NAME(DisasContext *s, arg_rprr_esz *a) \ | |
8110 | { \ | |
8111 | static gen_helper_gvec_flags_4 * const fns[4] = { \ | |
8112 | gen_helper_sve2_##name##_ppzz_b, gen_helper_sve2_##name##_ppzz_h, \ | |
8113 | NULL, NULL \ | |
8114 | }; \ | |
8115 | return do_sve2_ppzz_flags(s, a, fns[a->esz]); \ | |
8116 | } | |
8117 | ||
8118 | DO_SVE2_PPZZ_MATCH(MATCH, match) | |
8119 | DO_SVE2_PPZZ_MATCH(NMATCH, nmatch) | |
8120 | ||
7d47ac94 SL |
8121 | static bool trans_HISTCNT(DisasContext *s, arg_rprr_esz *a) |
8122 | { | |
8123 | static gen_helper_gvec_4 * const fns[2] = { | |
8124 | gen_helper_sve2_histcnt_s, gen_helper_sve2_histcnt_d | |
8125 | }; | |
8126 | if (a->esz < 2) { | |
8127 | return false; | |
8128 | } | |
8129 | return do_sve2_zpzz_ool(s, a, fns[a->esz - 2]); | |
8130 | } | |
8131 | ||
8132 | static bool trans_HISTSEG(DisasContext *s, arg_rrr_esz *a) | |
8133 | { | |
8134 | if (a->esz != 0) { | |
8135 | return false; | |
8136 | } | |
8137 | return do_sve2_zzz_ool(s, a, gen_helper_sve2_histseg); | |
8138 | } | |
8139 | ||
b87dbeeb SL |
8140 | static bool do_sve2_zpzz_fp(DisasContext *s, arg_rprr_esz *a, |
8141 | gen_helper_gvec_4_ptr *fn) | |
8142 | { | |
8143 | if (!dc_isar_feature(aa64_sve2, s)) { | |
8144 | return false; | |
8145 | } | |
8146 | return do_zpzz_fp(s, a, fn); | |
8147 | } | |
8148 | ||
8149 | #define DO_SVE2_ZPZZ_FP(NAME, name) \ | |
8150 | static bool trans_##NAME(DisasContext *s, arg_rprr_esz *a) \ | |
8151 | { \ | |
8152 | static gen_helper_gvec_4_ptr * const fns[4] = { \ | |
8153 | NULL, gen_helper_sve2_##name##_zpzz_h, \ | |
8154 | gen_helper_sve2_##name##_zpzz_s, gen_helper_sve2_##name##_zpzz_d \ | |
8155 | }; \ | |
8156 | return do_sve2_zpzz_fp(s, a, fns[a->esz]); \ | |
8157 | } | |
8158 | ||
8159 | DO_SVE2_ZPZZ_FP(FADDP, faddp) | |
8160 | DO_SVE2_ZPZZ_FP(FMAXNMP, fmaxnmp) | |
8161 | DO_SVE2_ZPZZ_FP(FMINNMP, fminnmp) | |
8162 | DO_SVE2_ZPZZ_FP(FMAXP, fmaxp) | |
8163 | DO_SVE2_ZPZZ_FP(FMINP, fminp) | |
bfc9307e RH |
8164 | |
8165 | /* | |
8166 | * SVE Integer Multiply-Add (unpredicated) | |
8167 | */ | |
8168 | ||
4f26756b SL |
8169 | static bool trans_FMMLA(DisasContext *s, arg_rrrr_esz *a) |
8170 | { | |
8171 | gen_helper_gvec_4_ptr *fn; | |
8172 | ||
8173 | switch (a->esz) { | |
8174 | case MO_32: | |
8175 | if (!dc_isar_feature(aa64_sve_f32mm, s)) { | |
8176 | return false; | |
8177 | } | |
8178 | fn = gen_helper_fmmla_s; | |
8179 | break; | |
8180 | case MO_64: | |
8181 | if (!dc_isar_feature(aa64_sve_f64mm, s)) { | |
8182 | return false; | |
8183 | } | |
8184 | fn = gen_helper_fmmla_d; | |
8185 | break; | |
8186 | default: | |
8187 | return false; | |
8188 | } | |
8189 | ||
8190 | if (sve_access_check(s)) { | |
8191 | unsigned vsz = vec_full_reg_size(s); | |
8192 | TCGv_ptr status = fpstatus_ptr(FPST_FPCR); | |
8193 | tcg_gen_gvec_4_ptr(vec_full_reg_offset(s, a->rd), | |
8194 | vec_full_reg_offset(s, a->rn), | |
8195 | vec_full_reg_offset(s, a->rm), | |
8196 | vec_full_reg_offset(s, a->ra), | |
8197 | status, vsz, vsz, 0, fn); | |
8198 | tcg_temp_free_ptr(status); | |
8199 | } | |
8200 | return true; | |
8201 | } | |
8202 | ||
bfc9307e RH |
8203 | static bool do_sqdmlal_zzzw(DisasContext *s, arg_rrrr_esz *a, |
8204 | bool sel1, bool sel2) | |
8205 | { | |
8206 | static gen_helper_gvec_4 * const fns[] = { | |
8207 | NULL, gen_helper_sve2_sqdmlal_zzzw_h, | |
8208 | gen_helper_sve2_sqdmlal_zzzw_s, gen_helper_sve2_sqdmlal_zzzw_d, | |
8209 | }; | |
8210 | return do_sve2_zzzz_ool(s, a, fns[a->esz], (sel2 << 1) | sel1); | |
8211 | } | |
8212 | ||
8213 | static bool do_sqdmlsl_zzzw(DisasContext *s, arg_rrrr_esz *a, | |
8214 | bool sel1, bool sel2) | |
8215 | { | |
8216 | static gen_helper_gvec_4 * const fns[] = { | |
8217 | NULL, gen_helper_sve2_sqdmlsl_zzzw_h, | |
8218 | gen_helper_sve2_sqdmlsl_zzzw_s, gen_helper_sve2_sqdmlsl_zzzw_d, | |
8219 | }; | |
8220 | return do_sve2_zzzz_ool(s, a, fns[a->esz], (sel2 << 1) | sel1); | |
8221 | } | |
8222 | ||
8223 | static bool trans_SQDMLALB_zzzw(DisasContext *s, arg_rrrr_esz *a) | |
8224 | { | |
8225 | return do_sqdmlal_zzzw(s, a, false, false); | |
8226 | } | |
8227 | ||
8228 | static bool trans_SQDMLALT_zzzw(DisasContext *s, arg_rrrr_esz *a) | |
8229 | { | |
8230 | return do_sqdmlal_zzzw(s, a, true, true); | |
8231 | } | |
8232 | ||
8233 | static bool trans_SQDMLALBT(DisasContext *s, arg_rrrr_esz *a) | |
8234 | { | |
8235 | return do_sqdmlal_zzzw(s, a, false, true); | |
8236 | } | |
8237 | ||
8238 | static bool trans_SQDMLSLB_zzzw(DisasContext *s, arg_rrrr_esz *a) | |
8239 | { | |
8240 | return do_sqdmlsl_zzzw(s, a, false, false); | |
8241 | } | |
8242 | ||
8243 | static bool trans_SQDMLSLT_zzzw(DisasContext *s, arg_rrrr_esz *a) | |
8244 | { | |
8245 | return do_sqdmlsl_zzzw(s, a, true, true); | |
8246 | } | |
8247 | ||
8248 | static bool trans_SQDMLSLBT(DisasContext *s, arg_rrrr_esz *a) | |
8249 | { | |
8250 | return do_sqdmlsl_zzzw(s, a, false, true); | |
8251 | } | |
ab3ddf31 RH |
8252 | |
8253 | static bool trans_SQRDMLAH_zzzz(DisasContext *s, arg_rrrr_esz *a) | |
8254 | { | |
8255 | static gen_helper_gvec_4 * const fns[] = { | |
8256 | gen_helper_sve2_sqrdmlah_b, gen_helper_sve2_sqrdmlah_h, | |
8257 | gen_helper_sve2_sqrdmlah_s, gen_helper_sve2_sqrdmlah_d, | |
8258 | }; | |
8259 | return do_sve2_zzzz_ool(s, a, fns[a->esz], 0); | |
8260 | } | |
8261 | ||
8262 | static bool trans_SQRDMLSH_zzzz(DisasContext *s, arg_rrrr_esz *a) | |
8263 | { | |
8264 | static gen_helper_gvec_4 * const fns[] = { | |
8265 | gen_helper_sve2_sqrdmlsh_b, gen_helper_sve2_sqrdmlsh_h, | |
8266 | gen_helper_sve2_sqrdmlsh_s, gen_helper_sve2_sqrdmlsh_d, | |
8267 | }; | |
8268 | return do_sve2_zzzz_ool(s, a, fns[a->esz], 0); | |
8269 | } | |
45a32e80 RH |
8270 | |
8271 | static bool do_smlal_zzzw(DisasContext *s, arg_rrrr_esz *a, bool sel) | |
8272 | { | |
8273 | static gen_helper_gvec_4 * const fns[] = { | |
8274 | NULL, gen_helper_sve2_smlal_zzzw_h, | |
8275 | gen_helper_sve2_smlal_zzzw_s, gen_helper_sve2_smlal_zzzw_d, | |
8276 | }; | |
8277 | return do_sve2_zzzz_ool(s, a, fns[a->esz], sel); | |
8278 | } | |
8279 | ||
8280 | static bool trans_SMLALB_zzzw(DisasContext *s, arg_rrrr_esz *a) | |
8281 | { | |
8282 | return do_smlal_zzzw(s, a, false); | |
8283 | } | |
8284 | ||
8285 | static bool trans_SMLALT_zzzw(DisasContext *s, arg_rrrr_esz *a) | |
8286 | { | |
8287 | return do_smlal_zzzw(s, a, true); | |
8288 | } | |
8289 | ||
8290 | static bool do_umlal_zzzw(DisasContext *s, arg_rrrr_esz *a, bool sel) | |
8291 | { | |
8292 | static gen_helper_gvec_4 * const fns[] = { | |
8293 | NULL, gen_helper_sve2_umlal_zzzw_h, | |
8294 | gen_helper_sve2_umlal_zzzw_s, gen_helper_sve2_umlal_zzzw_d, | |
8295 | }; | |
8296 | return do_sve2_zzzz_ool(s, a, fns[a->esz], sel); | |
8297 | } | |
8298 | ||
8299 | static bool trans_UMLALB_zzzw(DisasContext *s, arg_rrrr_esz *a) | |
8300 | { | |
8301 | return do_umlal_zzzw(s, a, false); | |
8302 | } | |
8303 | ||
8304 | static bool trans_UMLALT_zzzw(DisasContext *s, arg_rrrr_esz *a) | |
8305 | { | |
8306 | return do_umlal_zzzw(s, a, true); | |
8307 | } | |
8308 | ||
8309 | static bool do_smlsl_zzzw(DisasContext *s, arg_rrrr_esz *a, bool sel) | |
8310 | { | |
8311 | static gen_helper_gvec_4 * const fns[] = { | |
8312 | NULL, gen_helper_sve2_smlsl_zzzw_h, | |
8313 | gen_helper_sve2_smlsl_zzzw_s, gen_helper_sve2_smlsl_zzzw_d, | |
8314 | }; | |
8315 | return do_sve2_zzzz_ool(s, a, fns[a->esz], sel); | |
8316 | } | |
8317 | ||
8318 | static bool trans_SMLSLB_zzzw(DisasContext *s, arg_rrrr_esz *a) | |
8319 | { | |
8320 | return do_smlsl_zzzw(s, a, false); | |
8321 | } | |
8322 | ||
8323 | static bool trans_SMLSLT_zzzw(DisasContext *s, arg_rrrr_esz *a) | |
8324 | { | |
8325 | return do_smlsl_zzzw(s, a, true); | |
8326 | } | |
8327 | ||
8328 | static bool do_umlsl_zzzw(DisasContext *s, arg_rrrr_esz *a, bool sel) | |
8329 | { | |
8330 | static gen_helper_gvec_4 * const fns[] = { | |
8331 | NULL, gen_helper_sve2_umlsl_zzzw_h, | |
8332 | gen_helper_sve2_umlsl_zzzw_s, gen_helper_sve2_umlsl_zzzw_d, | |
8333 | }; | |
8334 | return do_sve2_zzzz_ool(s, a, fns[a->esz], sel); | |
8335 | } | |
8336 | ||
8337 | static bool trans_UMLSLB_zzzw(DisasContext *s, arg_rrrr_esz *a) | |
8338 | { | |
8339 | return do_umlsl_zzzw(s, a, false); | |
8340 | } | |
8341 | ||
8342 | static bool trans_UMLSLT_zzzw(DisasContext *s, arg_rrrr_esz *a) | |
8343 | { | |
8344 | return do_umlsl_zzzw(s, a, true); | |
8345 | } | |
d782d3ca RH |
8346 | |
8347 | static bool trans_CMLA_zzzz(DisasContext *s, arg_CMLA_zzzz *a) | |
8348 | { | |
8349 | static gen_helper_gvec_4 * const fns[] = { | |
8350 | gen_helper_sve2_cmla_zzzz_b, gen_helper_sve2_cmla_zzzz_h, | |
8351 | gen_helper_sve2_cmla_zzzz_s, gen_helper_sve2_cmla_zzzz_d, | |
8352 | }; | |
8353 | ||
8354 | if (!dc_isar_feature(aa64_sve2, s)) { | |
8355 | return false; | |
8356 | } | |
8357 | if (sve_access_check(s)) { | |
8358 | gen_gvec_ool_zzzz(s, fns[a->esz], a->rd, a->rn, a->rm, a->ra, a->rot); | |
8359 | } | |
8360 | return true; | |
8361 | } | |
8362 | ||
21068f39 RH |
8363 | static bool trans_CDOT_zzzz(DisasContext *s, arg_CMLA_zzzz *a) |
8364 | { | |
8365 | if (!dc_isar_feature(aa64_sve2, s) || a->esz < MO_32) { | |
8366 | return false; | |
8367 | } | |
8368 | if (sve_access_check(s)) { | |
8369 | gen_helper_gvec_4 *fn = (a->esz == MO_32 | |
8370 | ? gen_helper_sve2_cdot_zzzz_s | |
8371 | : gen_helper_sve2_cdot_zzzz_d); | |
8372 | gen_gvec_ool_zzzz(s, fn, a->rd, a->rn, a->rm, a->ra, a->rot); | |
8373 | } | |
8374 | return true; | |
8375 | } | |
8376 | ||
d782d3ca RH |
8377 | static bool trans_SQRDCMLAH_zzzz(DisasContext *s, arg_SQRDCMLAH_zzzz *a) |
8378 | { | |
8379 | static gen_helper_gvec_4 * const fns[] = { | |
8380 | gen_helper_sve2_sqrdcmlah_zzzz_b, gen_helper_sve2_sqrdcmlah_zzzz_h, | |
8381 | gen_helper_sve2_sqrdcmlah_zzzz_s, gen_helper_sve2_sqrdcmlah_zzzz_d, | |
8382 | }; | |
8383 | ||
8384 | if (!dc_isar_feature(aa64_sve2, s)) { | |
8385 | return false; | |
8386 | } | |
8387 | if (sve_access_check(s)) { | |
8388 | gen_gvec_ool_zzzz(s, fns[a->esz], a->rd, a->rn, a->rm, a->ra, a->rot); | |
8389 | } | |
8390 | return true; | |
8391 | } | |
6a98cb2a RH |
8392 | |
8393 | static bool trans_USDOT_zzzz(DisasContext *s, arg_USDOT_zzzz *a) | |
8394 | { | |
8395 | if (a->esz != 2 || !dc_isar_feature(aa64_sve_i8mm, s)) { | |
8396 | return false; | |
8397 | } | |
8398 | if (sve_access_check(s)) { | |
8399 | unsigned vsz = vec_full_reg_size(s); | |
8400 | tcg_gen_gvec_4_ool(vec_full_reg_offset(s, a->rd), | |
8401 | vec_full_reg_offset(s, a->rn), | |
8402 | vec_full_reg_offset(s, a->rm), | |
8403 | vec_full_reg_offset(s, a->ra), | |
8404 | vsz, vsz, 0, gen_helper_gvec_usdot_b); | |
8405 | } | |
8406 | return true; | |
8407 | } | |
b2bcd1be RH |
8408 | |
8409 | static bool trans_AESMC(DisasContext *s, arg_AESMC *a) | |
8410 | { | |
8411 | if (!dc_isar_feature(aa64_sve2_aes, s)) { | |
8412 | return false; | |
8413 | } | |
8414 | if (sve_access_check(s)) { | |
8415 | gen_gvec_ool_zz(s, gen_helper_crypto_aesmc, a->rd, a->rd, a->decrypt); | |
8416 | } | |
8417 | return true; | |
8418 | } | |
3cc7a88e RH |
8419 | |
8420 | static bool do_aese(DisasContext *s, arg_rrr_esz *a, bool decrypt) | |
8421 | { | |
8422 | if (!dc_isar_feature(aa64_sve2_aes, s)) { | |
8423 | return false; | |
8424 | } | |
8425 | if (sve_access_check(s)) { | |
8426 | gen_gvec_ool_zzz(s, gen_helper_crypto_aese, | |
8427 | a->rd, a->rn, a->rm, decrypt); | |
8428 | } | |
8429 | return true; | |
8430 | } | |
8431 | ||
8432 | static bool trans_AESE(DisasContext *s, arg_rrr_esz *a) | |
8433 | { | |
8434 | return do_aese(s, a, false); | |
8435 | } | |
8436 | ||
8437 | static bool trans_AESD(DisasContext *s, arg_rrr_esz *a) | |
8438 | { | |
8439 | return do_aese(s, a, true); | |
8440 | } | |
8441 | ||
8442 | static bool do_sm4(DisasContext *s, arg_rrr_esz *a, gen_helper_gvec_3 *fn) | |
8443 | { | |
8444 | if (!dc_isar_feature(aa64_sve2_sm4, s)) { | |
8445 | return false; | |
8446 | } | |
8447 | if (sve_access_check(s)) { | |
8448 | gen_gvec_ool_zzz(s, fn, a->rd, a->rn, a->rm, 0); | |
8449 | } | |
8450 | return true; | |
8451 | } | |
8452 | ||
8453 | static bool trans_SM4E(DisasContext *s, arg_rrr_esz *a) | |
8454 | { | |
8455 | return do_sm4(s, a, gen_helper_crypto_sm4e); | |
8456 | } | |
3358eb3f RH |
8457 | |
8458 | static bool trans_SM4EKEY(DisasContext *s, arg_rrr_esz *a) | |
8459 | { | |
8460 | return do_sm4(s, a, gen_helper_crypto_sm4ekey); | |
8461 | } | |
8462 | ||
8463 | static bool trans_RAX1(DisasContext *s, arg_rrr_esz *a) | |
8464 | { | |
8465 | if (!dc_isar_feature(aa64_sve2_sha3, s)) { | |
8466 | return false; | |
8467 | } | |
8468 | if (sve_access_check(s)) { | |
8469 | gen_gvec_fn_zzz(s, gen_gvec_rax1, MO_64, a->rd, a->rn, a->rm); | |
8470 | } | |
8471 | return true; | |
8472 | } | |
5c1b7226 RH |
8473 | |
8474 | static bool trans_FCVTNT_sh(DisasContext *s, arg_rpr_esz *a) | |
8475 | { | |
8476 | if (!dc_isar_feature(aa64_sve2, s)) { | |
8477 | return false; | |
8478 | } | |
8479 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve2_fcvtnt_sh); | |
8480 | } | |
8481 | ||
d29b17ca RH |
8482 | static bool trans_BFCVTNT(DisasContext *s, arg_rpr_esz *a) |
8483 | { | |
8484 | if (!dc_isar_feature(aa64_sve_bf16, s)) { | |
8485 | return false; | |
8486 | } | |
8487 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_bfcvtnt); | |
8488 | } | |
8489 | ||
5c1b7226 RH |
8490 | static bool trans_FCVTNT_ds(DisasContext *s, arg_rpr_esz *a) |
8491 | { | |
8492 | if (!dc_isar_feature(aa64_sve2, s)) { | |
8493 | return false; | |
8494 | } | |
8495 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve2_fcvtnt_ds); | |
8496 | } | |
83c2523f SL |
8497 | |
8498 | static bool trans_FCVTLT_hs(DisasContext *s, arg_rpr_esz *a) | |
8499 | { | |
8500 | if (!dc_isar_feature(aa64_sve2, s)) { | |
8501 | return false; | |
8502 | } | |
8503 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve2_fcvtlt_hs); | |
8504 | } | |
8505 | ||
8506 | static bool trans_FCVTLT_sd(DisasContext *s, arg_rpr_esz *a) | |
8507 | { | |
8508 | if (!dc_isar_feature(aa64_sve2, s)) { | |
8509 | return false; | |
8510 | } | |
8511 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve2_fcvtlt_sd); | |
8512 | } | |
95365277 SL |
8513 | |
8514 | static bool trans_FCVTX_ds(DisasContext *s, arg_rpr_esz *a) | |
8515 | { | |
8516 | if (!dc_isar_feature(aa64_sve2, s)) { | |
8517 | return false; | |
8518 | } | |
8519 | return do_frint_mode(s, a, float_round_to_odd, gen_helper_sve_fcvt_ds); | |
8520 | } | |
8521 | ||
8522 | static bool trans_FCVTXNT_ds(DisasContext *s, arg_rpr_esz *a) | |
8523 | { | |
8524 | if (!dc_isar_feature(aa64_sve2, s)) { | |
8525 | return false; | |
8526 | } | |
8527 | return do_frint_mode(s, a, float_round_to_odd, gen_helper_sve2_fcvtnt_ds); | |
8528 | } | |
631be02e SL |
8529 | |
8530 | static bool trans_FLOGB(DisasContext *s, arg_rpr_esz *a) | |
8531 | { | |
8532 | static gen_helper_gvec_3_ptr * const fns[] = { | |
8533 | NULL, gen_helper_flogb_h, | |
8534 | gen_helper_flogb_s, gen_helper_flogb_d | |
8535 | }; | |
8536 | ||
8537 | if (!dc_isar_feature(aa64_sve2, s) || fns[a->esz] == NULL) { | |
8538 | return false; | |
8539 | } | |
8540 | if (sve_access_check(s)) { | |
8541 | TCGv_ptr status = | |
8542 | fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR); | |
8543 | unsigned vsz = vec_full_reg_size(s); | |
8544 | ||
8545 | tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, a->rd), | |
8546 | vec_full_reg_offset(s, a->rn), | |
8547 | pred_full_reg_offset(s, a->pg), | |
8548 | status, vsz, vsz, 0, fns[a->esz]); | |
8549 | tcg_temp_free_ptr(status); | |
8550 | } | |
8551 | return true; | |
8552 | } | |
50d102bd SL |
8553 | |
8554 | static bool do_FMLAL_zzzw(DisasContext *s, arg_rrrr_esz *a, bool sub, bool sel) | |
8555 | { | |
8556 | if (!dc_isar_feature(aa64_sve2, s)) { | |
8557 | return false; | |
8558 | } | |
8559 | if (sve_access_check(s)) { | |
8560 | unsigned vsz = vec_full_reg_size(s); | |
8561 | tcg_gen_gvec_4_ptr(vec_full_reg_offset(s, a->rd), | |
8562 | vec_full_reg_offset(s, a->rn), | |
8563 | vec_full_reg_offset(s, a->rm), | |
8564 | vec_full_reg_offset(s, a->ra), | |
8565 | cpu_env, vsz, vsz, (sel << 1) | sub, | |
8566 | gen_helper_sve2_fmlal_zzzw_s); | |
8567 | } | |
8568 | return true; | |
8569 | } | |
8570 | ||
8571 | static bool trans_FMLALB_zzzw(DisasContext *s, arg_rrrr_esz *a) | |
8572 | { | |
8573 | return do_FMLAL_zzzw(s, a, false, false); | |
8574 | } | |
8575 | ||
8576 | static bool trans_FMLALT_zzzw(DisasContext *s, arg_rrrr_esz *a) | |
8577 | { | |
8578 | return do_FMLAL_zzzw(s, a, false, true); | |
8579 | } | |
8580 | ||
8581 | static bool trans_FMLSLB_zzzw(DisasContext *s, arg_rrrr_esz *a) | |
8582 | { | |
8583 | return do_FMLAL_zzzw(s, a, true, false); | |
8584 | } | |
8585 | ||
8586 | static bool trans_FMLSLT_zzzw(DisasContext *s, arg_rrrr_esz *a) | |
8587 | { | |
8588 | return do_FMLAL_zzzw(s, a, true, true); | |
8589 | } | |
8590 | ||
8591 | static bool do_FMLAL_zzxw(DisasContext *s, arg_rrxr_esz *a, bool sub, bool sel) | |
8592 | { | |
8593 | if (!dc_isar_feature(aa64_sve2, s)) { | |
8594 | return false; | |
8595 | } | |
8596 | if (sve_access_check(s)) { | |
8597 | unsigned vsz = vec_full_reg_size(s); | |
8598 | tcg_gen_gvec_4_ptr(vec_full_reg_offset(s, a->rd), | |
8599 | vec_full_reg_offset(s, a->rn), | |
8600 | vec_full_reg_offset(s, a->rm), | |
8601 | vec_full_reg_offset(s, a->ra), | |
8602 | cpu_env, vsz, vsz, | |
8603 | (a->index << 2) | (sel << 1) | sub, | |
8604 | gen_helper_sve2_fmlal_zzxw_s); | |
8605 | } | |
8606 | return true; | |
8607 | } | |
8608 | ||
8609 | static bool trans_FMLALB_zzxw(DisasContext *s, arg_rrxr_esz *a) | |
8610 | { | |
8611 | return do_FMLAL_zzxw(s, a, false, false); | |
8612 | } | |
8613 | ||
8614 | static bool trans_FMLALT_zzxw(DisasContext *s, arg_rrxr_esz *a) | |
8615 | { | |
8616 | return do_FMLAL_zzxw(s, a, false, true); | |
8617 | } | |
8618 | ||
8619 | static bool trans_FMLSLB_zzxw(DisasContext *s, arg_rrxr_esz *a) | |
8620 | { | |
8621 | return do_FMLAL_zzxw(s, a, true, false); | |
8622 | } | |
8623 | ||
8624 | static bool trans_FMLSLT_zzxw(DisasContext *s, arg_rrxr_esz *a) | |
8625 | { | |
8626 | return do_FMLAL_zzxw(s, a, true, true); | |
8627 | } | |
2323c5ff RH |
8628 | |
8629 | static bool do_i8mm_zzzz_ool(DisasContext *s, arg_rrrr_esz *a, | |
8630 | gen_helper_gvec_4 *fn, int data) | |
8631 | { | |
8632 | if (!dc_isar_feature(aa64_sve_i8mm, s)) { | |
8633 | return false; | |
8634 | } | |
8635 | if (sve_access_check(s)) { | |
8636 | gen_gvec_ool_zzzz(s, fn, a->rd, a->rn, a->rm, a->ra, data); | |
8637 | } | |
8638 | return true; | |
8639 | } | |
8640 | ||
8641 | static bool trans_SMMLA(DisasContext *s, arg_rrrr_esz *a) | |
8642 | { | |
8643 | return do_i8mm_zzzz_ool(s, a, gen_helper_gvec_smmla_b, 0); | |
8644 | } | |
8645 | ||
8646 | static bool trans_USMMLA(DisasContext *s, arg_rrrr_esz *a) | |
8647 | { | |
8648 | return do_i8mm_zzzz_ool(s, a, gen_helper_gvec_usmmla_b, 0); | |
8649 | } | |
8650 | ||
8651 | static bool trans_UMMLA(DisasContext *s, arg_rrrr_esz *a) | |
8652 | { | |
8653 | return do_i8mm_zzzz_ool(s, a, gen_helper_gvec_ummla_b, 0); | |
8654 | } | |
cb8657f7 RH |
8655 | |
8656 | static bool trans_BFDOT_zzzz(DisasContext *s, arg_rrrr_esz *a) | |
8657 | { | |
8658 | if (!dc_isar_feature(aa64_sve_bf16, s)) { | |
8659 | return false; | |
8660 | } | |
8661 | if (sve_access_check(s)) { | |
8662 | gen_gvec_ool_zzzz(s, gen_helper_gvec_bfdot, | |
8663 | a->rd, a->rn, a->rm, a->ra, 0); | |
8664 | } | |
8665 | return true; | |
8666 | } | |
83914478 RH |
8667 | |
8668 | static bool trans_BFDOT_zzxz(DisasContext *s, arg_rrxr_esz *a) | |
8669 | { | |
8670 | if (!dc_isar_feature(aa64_sve_bf16, s)) { | |
8671 | return false; | |
8672 | } | |
8673 | if (sve_access_check(s)) { | |
8674 | gen_gvec_ool_zzzz(s, gen_helper_gvec_bfdot_idx, | |
8675 | a->rd, a->rn, a->rm, a->ra, a->index); | |
8676 | } | |
8677 | return true; | |
8678 | } | |
81266a1f RH |
8679 | |
8680 | static bool trans_BFMMLA(DisasContext *s, arg_rrrr_esz *a) | |
8681 | { | |
8682 | if (!dc_isar_feature(aa64_sve_bf16, s)) { | |
8683 | return false; | |
8684 | } | |
8685 | if (sve_access_check(s)) { | |
8686 | gen_gvec_ool_zzzz(s, gen_helper_gvec_bfmmla, | |
8687 | a->rd, a->rn, a->rm, a->ra, 0); | |
8688 | } | |
8689 | return true; | |
8690 | } | |
5693887f RH |
8691 | |
8692 | static bool do_BFMLAL_zzzw(DisasContext *s, arg_rrrr_esz *a, bool sel) | |
8693 | { | |
8694 | if (!dc_isar_feature(aa64_sve_bf16, s)) { | |
8695 | return false; | |
8696 | } | |
8697 | if (sve_access_check(s)) { | |
8698 | TCGv_ptr status = fpstatus_ptr(FPST_FPCR); | |
8699 | unsigned vsz = vec_full_reg_size(s); | |
8700 | ||
8701 | tcg_gen_gvec_4_ptr(vec_full_reg_offset(s, a->rd), | |
8702 | vec_full_reg_offset(s, a->rn), | |
8703 | vec_full_reg_offset(s, a->rm), | |
8704 | vec_full_reg_offset(s, a->ra), | |
8705 | status, vsz, vsz, sel, | |
8706 | gen_helper_gvec_bfmlal); | |
8707 | tcg_temp_free_ptr(status); | |
8708 | } | |
8709 | return true; | |
8710 | } | |
8711 | ||
8712 | static bool trans_BFMLALB_zzzw(DisasContext *s, arg_rrrr_esz *a) | |
8713 | { | |
8714 | return do_BFMLAL_zzzw(s, a, false); | |
8715 | } | |
8716 | ||
8717 | static bool trans_BFMLALT_zzzw(DisasContext *s, arg_rrrr_esz *a) | |
8718 | { | |
8719 | return do_BFMLAL_zzzw(s, a, true); | |
8720 | } | |
458d0ab6 RH |
8721 | |
8722 | static bool do_BFMLAL_zzxw(DisasContext *s, arg_rrxr_esz *a, bool sel) | |
8723 | { | |
8724 | if (!dc_isar_feature(aa64_sve_bf16, s)) { | |
8725 | return false; | |
8726 | } | |
8727 | if (sve_access_check(s)) { | |
8728 | TCGv_ptr status = fpstatus_ptr(FPST_FPCR); | |
8729 | unsigned vsz = vec_full_reg_size(s); | |
8730 | ||
8731 | tcg_gen_gvec_4_ptr(vec_full_reg_offset(s, a->rd), | |
8732 | vec_full_reg_offset(s, a->rn), | |
8733 | vec_full_reg_offset(s, a->rm), | |
8734 | vec_full_reg_offset(s, a->ra), | |
8735 | status, vsz, vsz, (a->index << 1) | sel, | |
8736 | gen_helper_gvec_bfmlal_idx); | |
8737 | tcg_temp_free_ptr(status); | |
8738 | } | |
8739 | return true; | |
8740 | } | |
8741 | ||
8742 | static bool trans_BFMLALB_zzxw(DisasContext *s, arg_rrxr_esz *a) | |
8743 | { | |
8744 | return do_BFMLAL_zzxw(s, a, false); | |
8745 | } | |
8746 | ||
8747 | static bool trans_BFMLALT_zzxw(DisasContext *s, arg_rrxr_esz *a) | |
8748 | { | |
8749 | return do_BFMLAL_zzxw(s, a, true); | |
8750 | } |