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38388f7e RH |
1 | /* |
2 | * AArch64 SVE translation | |
3 | * | |
4 | * Copyright (c) 2018 Linaro, Ltd | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #include "qemu/osdep.h" | |
21 | #include "cpu.h" | |
22 | #include "exec/exec-all.h" | |
23 | #include "tcg-op.h" | |
24 | #include "tcg-op-gvec.h" | |
028e2a7b | 25 | #include "tcg-gvec-desc.h" |
38388f7e RH |
26 | #include "qemu/log.h" |
27 | #include "arm_ldst.h" | |
28 | #include "translate.h" | |
29 | #include "internals.h" | |
30 | #include "exec/helper-proto.h" | |
31 | #include "exec/helper-gen.h" | |
32 | #include "exec/log.h" | |
33 | #include "trace-tcg.h" | |
34 | #include "translate-a64.h" | |
35 | ||
ccd841c3 RH |
36 | /* |
37 | * Helpers for extracting complex instruction fields. | |
38 | */ | |
39 | ||
40 | /* See e.g. ASR (immediate, predicated). | |
41 | * Returns -1 for unallocated encoding; diagnose later. | |
42 | */ | |
43 | static int tszimm_esz(int x) | |
44 | { | |
45 | x >>= 3; /* discard imm3 */ | |
46 | return 31 - clz32(x); | |
47 | } | |
48 | ||
49 | static int tszimm_shr(int x) | |
50 | { | |
51 | return (16 << tszimm_esz(x)) - x; | |
52 | } | |
53 | ||
54 | /* See e.g. LSL (immediate, predicated). */ | |
55 | static int tszimm_shl(int x) | |
56 | { | |
57 | return x - (8 << tszimm_esz(x)); | |
58 | } | |
59 | ||
38388f7e RH |
60 | /* |
61 | * Include the generated decoder. | |
62 | */ | |
63 | ||
64 | #include "decode-sve.inc.c" | |
65 | ||
66 | /* | |
67 | * Implement all of the translator functions referenced by the decoder. | |
68 | */ | |
69 | ||
d1822297 RH |
70 | /* Return the offset info CPUARMState of the predicate vector register Pn. |
71 | * Note for this purpose, FFR is P16. | |
72 | */ | |
73 | static inline int pred_full_reg_offset(DisasContext *s, int regno) | |
74 | { | |
75 | return offsetof(CPUARMState, vfp.pregs[regno]); | |
76 | } | |
77 | ||
78 | /* Return the byte size of the whole predicate register, VL / 64. */ | |
79 | static inline int pred_full_reg_size(DisasContext *s) | |
80 | { | |
81 | return s->sve_len >> 3; | |
82 | } | |
83 | ||
516e246a RH |
84 | /* Round up the size of a register to a size allowed by |
85 | * the tcg vector infrastructure. Any operation which uses this | |
86 | * size may assume that the bits above pred_full_reg_size are zero, | |
87 | * and must leave them the same way. | |
88 | * | |
89 | * Note that this is not needed for the vector registers as they | |
90 | * are always properly sized for tcg vectors. | |
91 | */ | |
92 | static int size_for_gvec(int size) | |
93 | { | |
94 | if (size <= 8) { | |
95 | return 8; | |
96 | } else { | |
97 | return QEMU_ALIGN_UP(size, 16); | |
98 | } | |
99 | } | |
100 | ||
101 | static int pred_gvec_reg_size(DisasContext *s) | |
102 | { | |
103 | return size_for_gvec(pred_full_reg_size(s)); | |
104 | } | |
105 | ||
39eea561 RH |
106 | /* Invoke a vector expander on two Zregs. */ |
107 | static bool do_vector2_z(DisasContext *s, GVecGen2Fn *gvec_fn, | |
108 | int esz, int rd, int rn) | |
38388f7e | 109 | { |
39eea561 RH |
110 | if (sve_access_check(s)) { |
111 | unsigned vsz = vec_full_reg_size(s); | |
112 | gvec_fn(esz, vec_full_reg_offset(s, rd), | |
113 | vec_full_reg_offset(s, rn), vsz, vsz); | |
114 | } | |
115 | return true; | |
38388f7e RH |
116 | } |
117 | ||
39eea561 RH |
118 | /* Invoke a vector expander on three Zregs. */ |
119 | static bool do_vector3_z(DisasContext *s, GVecGen3Fn *gvec_fn, | |
120 | int esz, int rd, int rn, int rm) | |
38388f7e | 121 | { |
39eea561 RH |
122 | if (sve_access_check(s)) { |
123 | unsigned vsz = vec_full_reg_size(s); | |
124 | gvec_fn(esz, vec_full_reg_offset(s, rd), | |
125 | vec_full_reg_offset(s, rn), | |
126 | vec_full_reg_offset(s, rm), vsz, vsz); | |
127 | } | |
128 | return true; | |
38388f7e RH |
129 | } |
130 | ||
39eea561 RH |
131 | /* Invoke a vector move on two Zregs. */ |
132 | static bool do_mov_z(DisasContext *s, int rd, int rn) | |
38388f7e | 133 | { |
39eea561 | 134 | return do_vector2_z(s, tcg_gen_gvec_mov, 0, rd, rn); |
38388f7e RH |
135 | } |
136 | ||
516e246a RH |
137 | /* Invoke a vector expander on two Pregs. */ |
138 | static bool do_vector2_p(DisasContext *s, GVecGen2Fn *gvec_fn, | |
139 | int esz, int rd, int rn) | |
140 | { | |
141 | if (sve_access_check(s)) { | |
142 | unsigned psz = pred_gvec_reg_size(s); | |
143 | gvec_fn(esz, pred_full_reg_offset(s, rd), | |
144 | pred_full_reg_offset(s, rn), psz, psz); | |
145 | } | |
146 | return true; | |
147 | } | |
148 | ||
149 | /* Invoke a vector expander on three Pregs. */ | |
150 | static bool do_vector3_p(DisasContext *s, GVecGen3Fn *gvec_fn, | |
151 | int esz, int rd, int rn, int rm) | |
152 | { | |
153 | if (sve_access_check(s)) { | |
154 | unsigned psz = pred_gvec_reg_size(s); | |
155 | gvec_fn(esz, pred_full_reg_offset(s, rd), | |
156 | pred_full_reg_offset(s, rn), | |
157 | pred_full_reg_offset(s, rm), psz, psz); | |
158 | } | |
159 | return true; | |
160 | } | |
161 | ||
162 | /* Invoke a vector operation on four Pregs. */ | |
163 | static bool do_vecop4_p(DisasContext *s, const GVecGen4 *gvec_op, | |
164 | int rd, int rn, int rm, int rg) | |
165 | { | |
166 | if (sve_access_check(s)) { | |
167 | unsigned psz = pred_gvec_reg_size(s); | |
168 | tcg_gen_gvec_4(pred_full_reg_offset(s, rd), | |
169 | pred_full_reg_offset(s, rn), | |
170 | pred_full_reg_offset(s, rm), | |
171 | pred_full_reg_offset(s, rg), | |
172 | psz, psz, gvec_op); | |
173 | } | |
174 | return true; | |
175 | } | |
176 | ||
177 | /* Invoke a vector move on two Pregs. */ | |
178 | static bool do_mov_p(DisasContext *s, int rd, int rn) | |
179 | { | |
180 | return do_vector2_p(s, tcg_gen_gvec_mov, 0, rd, rn); | |
181 | } | |
182 | ||
9e18d7a6 RH |
183 | /* Set the cpu flags as per a return from an SVE helper. */ |
184 | static void do_pred_flags(TCGv_i32 t) | |
185 | { | |
186 | tcg_gen_mov_i32(cpu_NF, t); | |
187 | tcg_gen_andi_i32(cpu_ZF, t, 2); | |
188 | tcg_gen_andi_i32(cpu_CF, t, 1); | |
189 | tcg_gen_movi_i32(cpu_VF, 0); | |
190 | } | |
191 | ||
192 | /* Subroutines computing the ARM PredTest psuedofunction. */ | |
193 | static void do_predtest1(TCGv_i64 d, TCGv_i64 g) | |
194 | { | |
195 | TCGv_i32 t = tcg_temp_new_i32(); | |
196 | ||
197 | gen_helper_sve_predtest1(t, d, g); | |
198 | do_pred_flags(t); | |
199 | tcg_temp_free_i32(t); | |
200 | } | |
201 | ||
202 | static void do_predtest(DisasContext *s, int dofs, int gofs, int words) | |
203 | { | |
204 | TCGv_ptr dptr = tcg_temp_new_ptr(); | |
205 | TCGv_ptr gptr = tcg_temp_new_ptr(); | |
206 | TCGv_i32 t; | |
207 | ||
208 | tcg_gen_addi_ptr(dptr, cpu_env, dofs); | |
209 | tcg_gen_addi_ptr(gptr, cpu_env, gofs); | |
210 | t = tcg_const_i32(words); | |
211 | ||
212 | gen_helper_sve_predtest(t, dptr, gptr, t); | |
213 | tcg_temp_free_ptr(dptr); | |
214 | tcg_temp_free_ptr(gptr); | |
215 | ||
216 | do_pred_flags(t); | |
217 | tcg_temp_free_i32(t); | |
218 | } | |
219 | ||
028e2a7b RH |
220 | /* For each element size, the bits within a predicate word that are active. */ |
221 | const uint64_t pred_esz_masks[4] = { | |
222 | 0xffffffffffffffffull, 0x5555555555555555ull, | |
223 | 0x1111111111111111ull, 0x0101010101010101ull | |
224 | }; | |
225 | ||
39eea561 RH |
226 | /* |
227 | *** SVE Logical - Unpredicated Group | |
228 | */ | |
229 | ||
230 | static bool trans_AND_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn) | |
231 | { | |
232 | return do_vector3_z(s, tcg_gen_gvec_and, 0, a->rd, a->rn, a->rm); | |
233 | } | |
234 | ||
235 | static bool trans_ORR_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn) | |
236 | { | |
237 | if (a->rn == a->rm) { /* MOV */ | |
238 | return do_mov_z(s, a->rd, a->rn); | |
239 | } else { | |
240 | return do_vector3_z(s, tcg_gen_gvec_or, 0, a->rd, a->rn, a->rm); | |
241 | } | |
242 | } | |
243 | ||
244 | static bool trans_EOR_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn) | |
245 | { | |
246 | return do_vector3_z(s, tcg_gen_gvec_xor, 0, a->rd, a->rn, a->rm); | |
247 | } | |
248 | ||
249 | static bool trans_BIC_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn) | |
38388f7e | 250 | { |
39eea561 | 251 | return do_vector3_z(s, tcg_gen_gvec_andc, 0, a->rd, a->rn, a->rm); |
38388f7e | 252 | } |
d1822297 | 253 | |
f97cfd59 RH |
254 | /* |
255 | *** SVE Integer Arithmetic - Binary Predicated Group | |
256 | */ | |
257 | ||
258 | static bool do_zpzz_ool(DisasContext *s, arg_rprr_esz *a, gen_helper_gvec_4 *fn) | |
259 | { | |
260 | unsigned vsz = vec_full_reg_size(s); | |
261 | if (fn == NULL) { | |
262 | return false; | |
263 | } | |
264 | if (sve_access_check(s)) { | |
265 | tcg_gen_gvec_4_ool(vec_full_reg_offset(s, a->rd), | |
266 | vec_full_reg_offset(s, a->rn), | |
267 | vec_full_reg_offset(s, a->rm), | |
268 | pred_full_reg_offset(s, a->pg), | |
269 | vsz, vsz, 0, fn); | |
270 | } | |
271 | return true; | |
272 | } | |
273 | ||
274 | #define DO_ZPZZ(NAME, name) \ | |
275 | static bool trans_##NAME##_zpzz(DisasContext *s, arg_rprr_esz *a, \ | |
276 | uint32_t insn) \ | |
277 | { \ | |
278 | static gen_helper_gvec_4 * const fns[4] = { \ | |
279 | gen_helper_sve_##name##_zpzz_b, gen_helper_sve_##name##_zpzz_h, \ | |
280 | gen_helper_sve_##name##_zpzz_s, gen_helper_sve_##name##_zpzz_d, \ | |
281 | }; \ | |
282 | return do_zpzz_ool(s, a, fns[a->esz]); \ | |
283 | } | |
284 | ||
285 | DO_ZPZZ(AND, and) | |
286 | DO_ZPZZ(EOR, eor) | |
287 | DO_ZPZZ(ORR, orr) | |
288 | DO_ZPZZ(BIC, bic) | |
289 | ||
290 | DO_ZPZZ(ADD, add) | |
291 | DO_ZPZZ(SUB, sub) | |
292 | ||
293 | DO_ZPZZ(SMAX, smax) | |
294 | DO_ZPZZ(UMAX, umax) | |
295 | DO_ZPZZ(SMIN, smin) | |
296 | DO_ZPZZ(UMIN, umin) | |
297 | DO_ZPZZ(SABD, sabd) | |
298 | DO_ZPZZ(UABD, uabd) | |
299 | ||
300 | DO_ZPZZ(MUL, mul) | |
301 | DO_ZPZZ(SMULH, smulh) | |
302 | DO_ZPZZ(UMULH, umulh) | |
303 | ||
27721dbb RH |
304 | DO_ZPZZ(ASR, asr) |
305 | DO_ZPZZ(LSR, lsr) | |
306 | DO_ZPZZ(LSL, lsl) | |
307 | ||
f97cfd59 RH |
308 | static bool trans_SDIV_zpzz(DisasContext *s, arg_rprr_esz *a, uint32_t insn) |
309 | { | |
310 | static gen_helper_gvec_4 * const fns[4] = { | |
311 | NULL, NULL, gen_helper_sve_sdiv_zpzz_s, gen_helper_sve_sdiv_zpzz_d | |
312 | }; | |
313 | return do_zpzz_ool(s, a, fns[a->esz]); | |
314 | } | |
315 | ||
316 | static bool trans_UDIV_zpzz(DisasContext *s, arg_rprr_esz *a, uint32_t insn) | |
317 | { | |
318 | static gen_helper_gvec_4 * const fns[4] = { | |
319 | NULL, NULL, gen_helper_sve_udiv_zpzz_s, gen_helper_sve_udiv_zpzz_d | |
320 | }; | |
321 | return do_zpzz_ool(s, a, fns[a->esz]); | |
322 | } | |
323 | ||
324 | #undef DO_ZPZZ | |
325 | ||
afac6d04 RH |
326 | /* |
327 | *** SVE Integer Arithmetic - Unary Predicated Group | |
328 | */ | |
329 | ||
330 | static bool do_zpz_ool(DisasContext *s, arg_rpr_esz *a, gen_helper_gvec_3 *fn) | |
331 | { | |
332 | if (fn == NULL) { | |
333 | return false; | |
334 | } | |
335 | if (sve_access_check(s)) { | |
336 | unsigned vsz = vec_full_reg_size(s); | |
337 | tcg_gen_gvec_3_ool(vec_full_reg_offset(s, a->rd), | |
338 | vec_full_reg_offset(s, a->rn), | |
339 | pred_full_reg_offset(s, a->pg), | |
340 | vsz, vsz, 0, fn); | |
341 | } | |
342 | return true; | |
343 | } | |
344 | ||
345 | #define DO_ZPZ(NAME, name) \ | |
346 | static bool trans_##NAME(DisasContext *s, arg_rpr_esz *a, uint32_t insn) \ | |
347 | { \ | |
348 | static gen_helper_gvec_3 * const fns[4] = { \ | |
349 | gen_helper_sve_##name##_b, gen_helper_sve_##name##_h, \ | |
350 | gen_helper_sve_##name##_s, gen_helper_sve_##name##_d, \ | |
351 | }; \ | |
352 | return do_zpz_ool(s, a, fns[a->esz]); \ | |
353 | } | |
354 | ||
355 | DO_ZPZ(CLS, cls) | |
356 | DO_ZPZ(CLZ, clz) | |
357 | DO_ZPZ(CNT_zpz, cnt_zpz) | |
358 | DO_ZPZ(CNOT, cnot) | |
359 | DO_ZPZ(NOT_zpz, not_zpz) | |
360 | DO_ZPZ(ABS, abs) | |
361 | DO_ZPZ(NEG, neg) | |
362 | ||
363 | static bool trans_FABS(DisasContext *s, arg_rpr_esz *a, uint32_t insn) | |
364 | { | |
365 | static gen_helper_gvec_3 * const fns[4] = { | |
366 | NULL, | |
367 | gen_helper_sve_fabs_h, | |
368 | gen_helper_sve_fabs_s, | |
369 | gen_helper_sve_fabs_d | |
370 | }; | |
371 | return do_zpz_ool(s, a, fns[a->esz]); | |
372 | } | |
373 | ||
374 | static bool trans_FNEG(DisasContext *s, arg_rpr_esz *a, uint32_t insn) | |
375 | { | |
376 | static gen_helper_gvec_3 * const fns[4] = { | |
377 | NULL, | |
378 | gen_helper_sve_fneg_h, | |
379 | gen_helper_sve_fneg_s, | |
380 | gen_helper_sve_fneg_d | |
381 | }; | |
382 | return do_zpz_ool(s, a, fns[a->esz]); | |
383 | } | |
384 | ||
385 | static bool trans_SXTB(DisasContext *s, arg_rpr_esz *a, uint32_t insn) | |
386 | { | |
387 | static gen_helper_gvec_3 * const fns[4] = { | |
388 | NULL, | |
389 | gen_helper_sve_sxtb_h, | |
390 | gen_helper_sve_sxtb_s, | |
391 | gen_helper_sve_sxtb_d | |
392 | }; | |
393 | return do_zpz_ool(s, a, fns[a->esz]); | |
394 | } | |
395 | ||
396 | static bool trans_UXTB(DisasContext *s, arg_rpr_esz *a, uint32_t insn) | |
397 | { | |
398 | static gen_helper_gvec_3 * const fns[4] = { | |
399 | NULL, | |
400 | gen_helper_sve_uxtb_h, | |
401 | gen_helper_sve_uxtb_s, | |
402 | gen_helper_sve_uxtb_d | |
403 | }; | |
404 | return do_zpz_ool(s, a, fns[a->esz]); | |
405 | } | |
406 | ||
407 | static bool trans_SXTH(DisasContext *s, arg_rpr_esz *a, uint32_t insn) | |
408 | { | |
409 | static gen_helper_gvec_3 * const fns[4] = { | |
410 | NULL, NULL, | |
411 | gen_helper_sve_sxth_s, | |
412 | gen_helper_sve_sxth_d | |
413 | }; | |
414 | return do_zpz_ool(s, a, fns[a->esz]); | |
415 | } | |
416 | ||
417 | static bool trans_UXTH(DisasContext *s, arg_rpr_esz *a, uint32_t insn) | |
418 | { | |
419 | static gen_helper_gvec_3 * const fns[4] = { | |
420 | NULL, NULL, | |
421 | gen_helper_sve_uxth_s, | |
422 | gen_helper_sve_uxth_d | |
423 | }; | |
424 | return do_zpz_ool(s, a, fns[a->esz]); | |
425 | } | |
426 | ||
427 | static bool trans_SXTW(DisasContext *s, arg_rpr_esz *a, uint32_t insn) | |
428 | { | |
429 | return do_zpz_ool(s, a, a->esz == 3 ? gen_helper_sve_sxtw_d : NULL); | |
430 | } | |
431 | ||
432 | static bool trans_UXTW(DisasContext *s, arg_rpr_esz *a, uint32_t insn) | |
433 | { | |
434 | return do_zpz_ool(s, a, a->esz == 3 ? gen_helper_sve_uxtw_d : NULL); | |
435 | } | |
436 | ||
437 | #undef DO_ZPZ | |
438 | ||
047cec97 RH |
439 | /* |
440 | *** SVE Integer Reduction Group | |
441 | */ | |
442 | ||
443 | typedef void gen_helper_gvec_reduc(TCGv_i64, TCGv_ptr, TCGv_ptr, TCGv_i32); | |
444 | static bool do_vpz_ool(DisasContext *s, arg_rpr_esz *a, | |
445 | gen_helper_gvec_reduc *fn) | |
446 | { | |
447 | unsigned vsz = vec_full_reg_size(s); | |
448 | TCGv_ptr t_zn, t_pg; | |
449 | TCGv_i32 desc; | |
450 | TCGv_i64 temp; | |
451 | ||
452 | if (fn == NULL) { | |
453 | return false; | |
454 | } | |
455 | if (!sve_access_check(s)) { | |
456 | return true; | |
457 | } | |
458 | ||
459 | desc = tcg_const_i32(simd_desc(vsz, vsz, 0)); | |
460 | temp = tcg_temp_new_i64(); | |
461 | t_zn = tcg_temp_new_ptr(); | |
462 | t_pg = tcg_temp_new_ptr(); | |
463 | ||
464 | tcg_gen_addi_ptr(t_zn, cpu_env, vec_full_reg_offset(s, a->rn)); | |
465 | tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, a->pg)); | |
466 | fn(temp, t_zn, t_pg, desc); | |
467 | tcg_temp_free_ptr(t_zn); | |
468 | tcg_temp_free_ptr(t_pg); | |
469 | tcg_temp_free_i32(desc); | |
470 | ||
471 | write_fp_dreg(s, a->rd, temp); | |
472 | tcg_temp_free_i64(temp); | |
473 | return true; | |
474 | } | |
475 | ||
476 | #define DO_VPZ(NAME, name) \ | |
477 | static bool trans_##NAME(DisasContext *s, arg_rpr_esz *a, uint32_t insn) \ | |
478 | { \ | |
479 | static gen_helper_gvec_reduc * const fns[4] = { \ | |
480 | gen_helper_sve_##name##_b, gen_helper_sve_##name##_h, \ | |
481 | gen_helper_sve_##name##_s, gen_helper_sve_##name##_d, \ | |
482 | }; \ | |
483 | return do_vpz_ool(s, a, fns[a->esz]); \ | |
484 | } | |
485 | ||
486 | DO_VPZ(ORV, orv) | |
487 | DO_VPZ(ANDV, andv) | |
488 | DO_VPZ(EORV, eorv) | |
489 | ||
490 | DO_VPZ(UADDV, uaddv) | |
491 | DO_VPZ(SMAXV, smaxv) | |
492 | DO_VPZ(UMAXV, umaxv) | |
493 | DO_VPZ(SMINV, sminv) | |
494 | DO_VPZ(UMINV, uminv) | |
495 | ||
496 | static bool trans_SADDV(DisasContext *s, arg_rpr_esz *a, uint32_t insn) | |
497 | { | |
498 | static gen_helper_gvec_reduc * const fns[4] = { | |
499 | gen_helper_sve_saddv_b, gen_helper_sve_saddv_h, | |
500 | gen_helper_sve_saddv_s, NULL | |
501 | }; | |
502 | return do_vpz_ool(s, a, fns[a->esz]); | |
503 | } | |
504 | ||
505 | #undef DO_VPZ | |
506 | ||
ccd841c3 RH |
507 | /* |
508 | *** SVE Shift by Immediate - Predicated Group | |
509 | */ | |
510 | ||
511 | /* Store zero into every active element of Zd. We will use this for two | |
512 | * and three-operand predicated instructions for which logic dictates a | |
513 | * zero result. | |
514 | */ | |
515 | static bool do_clr_zp(DisasContext *s, int rd, int pg, int esz) | |
516 | { | |
517 | static gen_helper_gvec_2 * const fns[4] = { | |
518 | gen_helper_sve_clr_b, gen_helper_sve_clr_h, | |
519 | gen_helper_sve_clr_s, gen_helper_sve_clr_d, | |
520 | }; | |
521 | if (sve_access_check(s)) { | |
522 | unsigned vsz = vec_full_reg_size(s); | |
523 | tcg_gen_gvec_2_ool(vec_full_reg_offset(s, rd), | |
524 | pred_full_reg_offset(s, pg), | |
525 | vsz, vsz, 0, fns[esz]); | |
526 | } | |
527 | return true; | |
528 | } | |
529 | ||
530 | static bool do_zpzi_ool(DisasContext *s, arg_rpri_esz *a, | |
531 | gen_helper_gvec_3 *fn) | |
532 | { | |
533 | if (sve_access_check(s)) { | |
534 | unsigned vsz = vec_full_reg_size(s); | |
535 | tcg_gen_gvec_3_ool(vec_full_reg_offset(s, a->rd), | |
536 | vec_full_reg_offset(s, a->rn), | |
537 | pred_full_reg_offset(s, a->pg), | |
538 | vsz, vsz, a->imm, fn); | |
539 | } | |
540 | return true; | |
541 | } | |
542 | ||
543 | static bool trans_ASR_zpzi(DisasContext *s, arg_rpri_esz *a, uint32_t insn) | |
544 | { | |
545 | static gen_helper_gvec_3 * const fns[4] = { | |
546 | gen_helper_sve_asr_zpzi_b, gen_helper_sve_asr_zpzi_h, | |
547 | gen_helper_sve_asr_zpzi_s, gen_helper_sve_asr_zpzi_d, | |
548 | }; | |
549 | if (a->esz < 0) { | |
550 | /* Invalid tsz encoding -- see tszimm_esz. */ | |
551 | return false; | |
552 | } | |
553 | /* Shift by element size is architecturally valid. For | |
554 | arithmetic right-shift, it's the same as by one less. */ | |
555 | a->imm = MIN(a->imm, (8 << a->esz) - 1); | |
556 | return do_zpzi_ool(s, a, fns[a->esz]); | |
557 | } | |
558 | ||
559 | static bool trans_LSR_zpzi(DisasContext *s, arg_rpri_esz *a, uint32_t insn) | |
560 | { | |
561 | static gen_helper_gvec_3 * const fns[4] = { | |
562 | gen_helper_sve_lsr_zpzi_b, gen_helper_sve_lsr_zpzi_h, | |
563 | gen_helper_sve_lsr_zpzi_s, gen_helper_sve_lsr_zpzi_d, | |
564 | }; | |
565 | if (a->esz < 0) { | |
566 | return false; | |
567 | } | |
568 | /* Shift by element size is architecturally valid. | |
569 | For logical shifts, it is a zeroing operation. */ | |
570 | if (a->imm >= (8 << a->esz)) { | |
571 | return do_clr_zp(s, a->rd, a->pg, a->esz); | |
572 | } else { | |
573 | return do_zpzi_ool(s, a, fns[a->esz]); | |
574 | } | |
575 | } | |
576 | ||
577 | static bool trans_LSL_zpzi(DisasContext *s, arg_rpri_esz *a, uint32_t insn) | |
578 | { | |
579 | static gen_helper_gvec_3 * const fns[4] = { | |
580 | gen_helper_sve_lsl_zpzi_b, gen_helper_sve_lsl_zpzi_h, | |
581 | gen_helper_sve_lsl_zpzi_s, gen_helper_sve_lsl_zpzi_d, | |
582 | }; | |
583 | if (a->esz < 0) { | |
584 | return false; | |
585 | } | |
586 | /* Shift by element size is architecturally valid. | |
587 | For logical shifts, it is a zeroing operation. */ | |
588 | if (a->imm >= (8 << a->esz)) { | |
589 | return do_clr_zp(s, a->rd, a->pg, a->esz); | |
590 | } else { | |
591 | return do_zpzi_ool(s, a, fns[a->esz]); | |
592 | } | |
593 | } | |
594 | ||
595 | static bool trans_ASRD(DisasContext *s, arg_rpri_esz *a, uint32_t insn) | |
596 | { | |
597 | static gen_helper_gvec_3 * const fns[4] = { | |
598 | gen_helper_sve_asrd_b, gen_helper_sve_asrd_h, | |
599 | gen_helper_sve_asrd_s, gen_helper_sve_asrd_d, | |
600 | }; | |
601 | if (a->esz < 0) { | |
602 | return false; | |
603 | } | |
604 | /* Shift by element size is architecturally valid. For arithmetic | |
605 | right shift for division, it is a zeroing operation. */ | |
606 | if (a->imm >= (8 << a->esz)) { | |
607 | return do_clr_zp(s, a->rd, a->pg, a->esz); | |
608 | } else { | |
609 | return do_zpzi_ool(s, a, fns[a->esz]); | |
610 | } | |
611 | } | |
612 | ||
fe7f8dfb RH |
613 | /* |
614 | *** SVE Bitwise Shift - Predicated Group | |
615 | */ | |
616 | ||
617 | #define DO_ZPZW(NAME, name) \ | |
618 | static bool trans_##NAME##_zpzw(DisasContext *s, arg_rprr_esz *a, \ | |
619 | uint32_t insn) \ | |
620 | { \ | |
621 | static gen_helper_gvec_4 * const fns[3] = { \ | |
622 | gen_helper_sve_##name##_zpzw_b, gen_helper_sve_##name##_zpzw_h, \ | |
623 | gen_helper_sve_##name##_zpzw_s, \ | |
624 | }; \ | |
625 | if (a->esz < 0 || a->esz >= 3) { \ | |
626 | return false; \ | |
627 | } \ | |
628 | return do_zpzz_ool(s, a, fns[a->esz]); \ | |
629 | } | |
630 | ||
631 | DO_ZPZW(ASR, asr) | |
632 | DO_ZPZW(LSR, lsr) | |
633 | DO_ZPZW(LSL, lsl) | |
634 | ||
635 | #undef DO_ZPZW | |
636 | ||
516e246a RH |
637 | /* |
638 | *** SVE Predicate Logical Operations Group | |
639 | */ | |
640 | ||
641 | static bool do_pppp_flags(DisasContext *s, arg_rprr_s *a, | |
642 | const GVecGen4 *gvec_op) | |
643 | { | |
644 | if (!sve_access_check(s)) { | |
645 | return true; | |
646 | } | |
647 | ||
648 | unsigned psz = pred_gvec_reg_size(s); | |
649 | int dofs = pred_full_reg_offset(s, a->rd); | |
650 | int nofs = pred_full_reg_offset(s, a->rn); | |
651 | int mofs = pred_full_reg_offset(s, a->rm); | |
652 | int gofs = pred_full_reg_offset(s, a->pg); | |
653 | ||
654 | if (psz == 8) { | |
655 | /* Do the operation and the flags generation in temps. */ | |
656 | TCGv_i64 pd = tcg_temp_new_i64(); | |
657 | TCGv_i64 pn = tcg_temp_new_i64(); | |
658 | TCGv_i64 pm = tcg_temp_new_i64(); | |
659 | TCGv_i64 pg = tcg_temp_new_i64(); | |
660 | ||
661 | tcg_gen_ld_i64(pn, cpu_env, nofs); | |
662 | tcg_gen_ld_i64(pm, cpu_env, mofs); | |
663 | tcg_gen_ld_i64(pg, cpu_env, gofs); | |
664 | ||
665 | gvec_op->fni8(pd, pn, pm, pg); | |
666 | tcg_gen_st_i64(pd, cpu_env, dofs); | |
667 | ||
668 | do_predtest1(pd, pg); | |
669 | ||
670 | tcg_temp_free_i64(pd); | |
671 | tcg_temp_free_i64(pn); | |
672 | tcg_temp_free_i64(pm); | |
673 | tcg_temp_free_i64(pg); | |
674 | } else { | |
675 | /* The operation and flags generation is large. The computation | |
676 | * of the flags depends on the original contents of the guarding | |
677 | * predicate. If the destination overwrites the guarding predicate, | |
678 | * then the easiest way to get this right is to save a copy. | |
679 | */ | |
680 | int tofs = gofs; | |
681 | if (a->rd == a->pg) { | |
682 | tofs = offsetof(CPUARMState, vfp.preg_tmp); | |
683 | tcg_gen_gvec_mov(0, tofs, gofs, psz, psz); | |
684 | } | |
685 | ||
686 | tcg_gen_gvec_4(dofs, nofs, mofs, gofs, psz, psz, gvec_op); | |
687 | do_predtest(s, dofs, tofs, psz / 8); | |
688 | } | |
689 | return true; | |
690 | } | |
691 | ||
692 | static void gen_and_pg_i64(TCGv_i64 pd, TCGv_i64 pn, TCGv_i64 pm, TCGv_i64 pg) | |
693 | { | |
694 | tcg_gen_and_i64(pd, pn, pm); | |
695 | tcg_gen_and_i64(pd, pd, pg); | |
696 | } | |
697 | ||
698 | static void gen_and_pg_vec(unsigned vece, TCGv_vec pd, TCGv_vec pn, | |
699 | TCGv_vec pm, TCGv_vec pg) | |
700 | { | |
701 | tcg_gen_and_vec(vece, pd, pn, pm); | |
702 | tcg_gen_and_vec(vece, pd, pd, pg); | |
703 | } | |
704 | ||
705 | static bool trans_AND_pppp(DisasContext *s, arg_rprr_s *a, uint32_t insn) | |
706 | { | |
707 | static const GVecGen4 op = { | |
708 | .fni8 = gen_and_pg_i64, | |
709 | .fniv = gen_and_pg_vec, | |
710 | .fno = gen_helper_sve_and_pppp, | |
711 | .prefer_i64 = TCG_TARGET_REG_BITS == 64, | |
712 | }; | |
713 | if (a->s) { | |
714 | return do_pppp_flags(s, a, &op); | |
715 | } else if (a->rn == a->rm) { | |
716 | if (a->pg == a->rn) { | |
717 | return do_mov_p(s, a->rd, a->rn); | |
718 | } else { | |
719 | return do_vector3_p(s, tcg_gen_gvec_and, 0, a->rd, a->rn, a->pg); | |
720 | } | |
721 | } else if (a->pg == a->rn || a->pg == a->rm) { | |
722 | return do_vector3_p(s, tcg_gen_gvec_and, 0, a->rd, a->rn, a->rm); | |
723 | } else { | |
724 | return do_vecop4_p(s, &op, a->rd, a->rn, a->rm, a->pg); | |
725 | } | |
726 | } | |
727 | ||
728 | static void gen_bic_pg_i64(TCGv_i64 pd, TCGv_i64 pn, TCGv_i64 pm, TCGv_i64 pg) | |
729 | { | |
730 | tcg_gen_andc_i64(pd, pn, pm); | |
731 | tcg_gen_and_i64(pd, pd, pg); | |
732 | } | |
733 | ||
734 | static void gen_bic_pg_vec(unsigned vece, TCGv_vec pd, TCGv_vec pn, | |
735 | TCGv_vec pm, TCGv_vec pg) | |
736 | { | |
737 | tcg_gen_andc_vec(vece, pd, pn, pm); | |
738 | tcg_gen_and_vec(vece, pd, pd, pg); | |
739 | } | |
740 | ||
741 | static bool trans_BIC_pppp(DisasContext *s, arg_rprr_s *a, uint32_t insn) | |
742 | { | |
743 | static const GVecGen4 op = { | |
744 | .fni8 = gen_bic_pg_i64, | |
745 | .fniv = gen_bic_pg_vec, | |
746 | .fno = gen_helper_sve_bic_pppp, | |
747 | .prefer_i64 = TCG_TARGET_REG_BITS == 64, | |
748 | }; | |
749 | if (a->s) { | |
750 | return do_pppp_flags(s, a, &op); | |
751 | } else if (a->pg == a->rn) { | |
752 | return do_vector3_p(s, tcg_gen_gvec_andc, 0, a->rd, a->rn, a->rm); | |
753 | } else { | |
754 | return do_vecop4_p(s, &op, a->rd, a->rn, a->rm, a->pg); | |
755 | } | |
756 | } | |
757 | ||
758 | static void gen_eor_pg_i64(TCGv_i64 pd, TCGv_i64 pn, TCGv_i64 pm, TCGv_i64 pg) | |
759 | { | |
760 | tcg_gen_xor_i64(pd, pn, pm); | |
761 | tcg_gen_and_i64(pd, pd, pg); | |
762 | } | |
763 | ||
764 | static void gen_eor_pg_vec(unsigned vece, TCGv_vec pd, TCGv_vec pn, | |
765 | TCGv_vec pm, TCGv_vec pg) | |
766 | { | |
767 | tcg_gen_xor_vec(vece, pd, pn, pm); | |
768 | tcg_gen_and_vec(vece, pd, pd, pg); | |
769 | } | |
770 | ||
771 | static bool trans_EOR_pppp(DisasContext *s, arg_rprr_s *a, uint32_t insn) | |
772 | { | |
773 | static const GVecGen4 op = { | |
774 | .fni8 = gen_eor_pg_i64, | |
775 | .fniv = gen_eor_pg_vec, | |
776 | .fno = gen_helper_sve_eor_pppp, | |
777 | .prefer_i64 = TCG_TARGET_REG_BITS == 64, | |
778 | }; | |
779 | if (a->s) { | |
780 | return do_pppp_flags(s, a, &op); | |
781 | } else { | |
782 | return do_vecop4_p(s, &op, a->rd, a->rn, a->rm, a->pg); | |
783 | } | |
784 | } | |
785 | ||
786 | static void gen_sel_pg_i64(TCGv_i64 pd, TCGv_i64 pn, TCGv_i64 pm, TCGv_i64 pg) | |
787 | { | |
788 | tcg_gen_and_i64(pn, pn, pg); | |
789 | tcg_gen_andc_i64(pm, pm, pg); | |
790 | tcg_gen_or_i64(pd, pn, pm); | |
791 | } | |
792 | ||
793 | static void gen_sel_pg_vec(unsigned vece, TCGv_vec pd, TCGv_vec pn, | |
794 | TCGv_vec pm, TCGv_vec pg) | |
795 | { | |
796 | tcg_gen_and_vec(vece, pn, pn, pg); | |
797 | tcg_gen_andc_vec(vece, pm, pm, pg); | |
798 | tcg_gen_or_vec(vece, pd, pn, pm); | |
799 | } | |
800 | ||
801 | static bool trans_SEL_pppp(DisasContext *s, arg_rprr_s *a, uint32_t insn) | |
802 | { | |
803 | static const GVecGen4 op = { | |
804 | .fni8 = gen_sel_pg_i64, | |
805 | .fniv = gen_sel_pg_vec, | |
806 | .fno = gen_helper_sve_sel_pppp, | |
807 | .prefer_i64 = TCG_TARGET_REG_BITS == 64, | |
808 | }; | |
809 | if (a->s) { | |
810 | return false; | |
811 | } else { | |
812 | return do_vecop4_p(s, &op, a->rd, a->rn, a->rm, a->pg); | |
813 | } | |
814 | } | |
815 | ||
816 | static void gen_orr_pg_i64(TCGv_i64 pd, TCGv_i64 pn, TCGv_i64 pm, TCGv_i64 pg) | |
817 | { | |
818 | tcg_gen_or_i64(pd, pn, pm); | |
819 | tcg_gen_and_i64(pd, pd, pg); | |
820 | } | |
821 | ||
822 | static void gen_orr_pg_vec(unsigned vece, TCGv_vec pd, TCGv_vec pn, | |
823 | TCGv_vec pm, TCGv_vec pg) | |
824 | { | |
825 | tcg_gen_or_vec(vece, pd, pn, pm); | |
826 | tcg_gen_and_vec(vece, pd, pd, pg); | |
827 | } | |
828 | ||
829 | static bool trans_ORR_pppp(DisasContext *s, arg_rprr_s *a, uint32_t insn) | |
830 | { | |
831 | static const GVecGen4 op = { | |
832 | .fni8 = gen_orr_pg_i64, | |
833 | .fniv = gen_orr_pg_vec, | |
834 | .fno = gen_helper_sve_orr_pppp, | |
835 | .prefer_i64 = TCG_TARGET_REG_BITS == 64, | |
836 | }; | |
837 | if (a->s) { | |
838 | return do_pppp_flags(s, a, &op); | |
839 | } else if (a->pg == a->rn && a->rn == a->rm) { | |
840 | return do_mov_p(s, a->rd, a->rn); | |
841 | } else { | |
842 | return do_vecop4_p(s, &op, a->rd, a->rn, a->rm, a->pg); | |
843 | } | |
844 | } | |
845 | ||
846 | static void gen_orn_pg_i64(TCGv_i64 pd, TCGv_i64 pn, TCGv_i64 pm, TCGv_i64 pg) | |
847 | { | |
848 | tcg_gen_orc_i64(pd, pn, pm); | |
849 | tcg_gen_and_i64(pd, pd, pg); | |
850 | } | |
851 | ||
852 | static void gen_orn_pg_vec(unsigned vece, TCGv_vec pd, TCGv_vec pn, | |
853 | TCGv_vec pm, TCGv_vec pg) | |
854 | { | |
855 | tcg_gen_orc_vec(vece, pd, pn, pm); | |
856 | tcg_gen_and_vec(vece, pd, pd, pg); | |
857 | } | |
858 | ||
859 | static bool trans_ORN_pppp(DisasContext *s, arg_rprr_s *a, uint32_t insn) | |
860 | { | |
861 | static const GVecGen4 op = { | |
862 | .fni8 = gen_orn_pg_i64, | |
863 | .fniv = gen_orn_pg_vec, | |
864 | .fno = gen_helper_sve_orn_pppp, | |
865 | .prefer_i64 = TCG_TARGET_REG_BITS == 64, | |
866 | }; | |
867 | if (a->s) { | |
868 | return do_pppp_flags(s, a, &op); | |
869 | } else { | |
870 | return do_vecop4_p(s, &op, a->rd, a->rn, a->rm, a->pg); | |
871 | } | |
872 | } | |
873 | ||
874 | static void gen_nor_pg_i64(TCGv_i64 pd, TCGv_i64 pn, TCGv_i64 pm, TCGv_i64 pg) | |
875 | { | |
876 | tcg_gen_or_i64(pd, pn, pm); | |
877 | tcg_gen_andc_i64(pd, pg, pd); | |
878 | } | |
879 | ||
880 | static void gen_nor_pg_vec(unsigned vece, TCGv_vec pd, TCGv_vec pn, | |
881 | TCGv_vec pm, TCGv_vec pg) | |
882 | { | |
883 | tcg_gen_or_vec(vece, pd, pn, pm); | |
884 | tcg_gen_andc_vec(vece, pd, pg, pd); | |
885 | } | |
886 | ||
887 | static bool trans_NOR_pppp(DisasContext *s, arg_rprr_s *a, uint32_t insn) | |
888 | { | |
889 | static const GVecGen4 op = { | |
890 | .fni8 = gen_nor_pg_i64, | |
891 | .fniv = gen_nor_pg_vec, | |
892 | .fno = gen_helper_sve_nor_pppp, | |
893 | .prefer_i64 = TCG_TARGET_REG_BITS == 64, | |
894 | }; | |
895 | if (a->s) { | |
896 | return do_pppp_flags(s, a, &op); | |
897 | } else { | |
898 | return do_vecop4_p(s, &op, a->rd, a->rn, a->rm, a->pg); | |
899 | } | |
900 | } | |
901 | ||
902 | static void gen_nand_pg_i64(TCGv_i64 pd, TCGv_i64 pn, TCGv_i64 pm, TCGv_i64 pg) | |
903 | { | |
904 | tcg_gen_and_i64(pd, pn, pm); | |
905 | tcg_gen_andc_i64(pd, pg, pd); | |
906 | } | |
907 | ||
908 | static void gen_nand_pg_vec(unsigned vece, TCGv_vec pd, TCGv_vec pn, | |
909 | TCGv_vec pm, TCGv_vec pg) | |
910 | { | |
911 | tcg_gen_and_vec(vece, pd, pn, pm); | |
912 | tcg_gen_andc_vec(vece, pd, pg, pd); | |
913 | } | |
914 | ||
915 | static bool trans_NAND_pppp(DisasContext *s, arg_rprr_s *a, uint32_t insn) | |
916 | { | |
917 | static const GVecGen4 op = { | |
918 | .fni8 = gen_nand_pg_i64, | |
919 | .fniv = gen_nand_pg_vec, | |
920 | .fno = gen_helper_sve_nand_pppp, | |
921 | .prefer_i64 = TCG_TARGET_REG_BITS == 64, | |
922 | }; | |
923 | if (a->s) { | |
924 | return do_pppp_flags(s, a, &op); | |
925 | } else { | |
926 | return do_vecop4_p(s, &op, a->rd, a->rn, a->rm, a->pg); | |
927 | } | |
928 | } | |
929 | ||
9e18d7a6 RH |
930 | /* |
931 | *** SVE Predicate Misc Group | |
932 | */ | |
933 | ||
934 | static bool trans_PTEST(DisasContext *s, arg_PTEST *a, uint32_t insn) | |
935 | { | |
936 | if (sve_access_check(s)) { | |
937 | int nofs = pred_full_reg_offset(s, a->rn); | |
938 | int gofs = pred_full_reg_offset(s, a->pg); | |
939 | int words = DIV_ROUND_UP(pred_full_reg_size(s), 8); | |
940 | ||
941 | if (words == 1) { | |
942 | TCGv_i64 pn = tcg_temp_new_i64(); | |
943 | TCGv_i64 pg = tcg_temp_new_i64(); | |
944 | ||
945 | tcg_gen_ld_i64(pn, cpu_env, nofs); | |
946 | tcg_gen_ld_i64(pg, cpu_env, gofs); | |
947 | do_predtest1(pn, pg); | |
948 | ||
949 | tcg_temp_free_i64(pn); | |
950 | tcg_temp_free_i64(pg); | |
951 | } else { | |
952 | do_predtest(s, nofs, gofs, words); | |
953 | } | |
954 | } | |
955 | return true; | |
956 | } | |
957 | ||
028e2a7b RH |
958 | /* See the ARM pseudocode DecodePredCount. */ |
959 | static unsigned decode_pred_count(unsigned fullsz, int pattern, int esz) | |
960 | { | |
961 | unsigned elements = fullsz >> esz; | |
962 | unsigned bound; | |
963 | ||
964 | switch (pattern) { | |
965 | case 0x0: /* POW2 */ | |
966 | return pow2floor(elements); | |
967 | case 0x1: /* VL1 */ | |
968 | case 0x2: /* VL2 */ | |
969 | case 0x3: /* VL3 */ | |
970 | case 0x4: /* VL4 */ | |
971 | case 0x5: /* VL5 */ | |
972 | case 0x6: /* VL6 */ | |
973 | case 0x7: /* VL7 */ | |
974 | case 0x8: /* VL8 */ | |
975 | bound = pattern; | |
976 | break; | |
977 | case 0x9: /* VL16 */ | |
978 | case 0xa: /* VL32 */ | |
979 | case 0xb: /* VL64 */ | |
980 | case 0xc: /* VL128 */ | |
981 | case 0xd: /* VL256 */ | |
982 | bound = 16 << (pattern - 9); | |
983 | break; | |
984 | case 0x1d: /* MUL4 */ | |
985 | return elements - elements % 4; | |
986 | case 0x1e: /* MUL3 */ | |
987 | return elements - elements % 3; | |
988 | case 0x1f: /* ALL */ | |
989 | return elements; | |
990 | default: /* #uimm5 */ | |
991 | return 0; | |
992 | } | |
993 | return elements >= bound ? bound : 0; | |
994 | } | |
995 | ||
996 | /* This handles all of the predicate initialization instructions, | |
997 | * PTRUE, PFALSE, SETFFR. For PFALSE, we will have set PAT == 32 | |
998 | * so that decode_pred_count returns 0. For SETFFR, we will have | |
999 | * set RD == 16 == FFR. | |
1000 | */ | |
1001 | static bool do_predset(DisasContext *s, int esz, int rd, int pat, bool setflag) | |
1002 | { | |
1003 | if (!sve_access_check(s)) { | |
1004 | return true; | |
1005 | } | |
1006 | ||
1007 | unsigned fullsz = vec_full_reg_size(s); | |
1008 | unsigned ofs = pred_full_reg_offset(s, rd); | |
1009 | unsigned numelem, setsz, i; | |
1010 | uint64_t word, lastword; | |
1011 | TCGv_i64 t; | |
1012 | ||
1013 | numelem = decode_pred_count(fullsz, pat, esz); | |
1014 | ||
1015 | /* Determine what we must store into each bit, and how many. */ | |
1016 | if (numelem == 0) { | |
1017 | lastword = word = 0; | |
1018 | setsz = fullsz; | |
1019 | } else { | |
1020 | setsz = numelem << esz; | |
1021 | lastword = word = pred_esz_masks[esz]; | |
1022 | if (setsz % 64) { | |
1023 | lastword &= ~(-1ull << (setsz % 64)); | |
1024 | } | |
1025 | } | |
1026 | ||
1027 | t = tcg_temp_new_i64(); | |
1028 | if (fullsz <= 64) { | |
1029 | tcg_gen_movi_i64(t, lastword); | |
1030 | tcg_gen_st_i64(t, cpu_env, ofs); | |
1031 | goto done; | |
1032 | } | |
1033 | ||
1034 | if (word == lastword) { | |
1035 | unsigned maxsz = size_for_gvec(fullsz / 8); | |
1036 | unsigned oprsz = size_for_gvec(setsz / 8); | |
1037 | ||
1038 | if (oprsz * 8 == setsz) { | |
1039 | tcg_gen_gvec_dup64i(ofs, oprsz, maxsz, word); | |
1040 | goto done; | |
1041 | } | |
1042 | if (oprsz * 8 == setsz + 8) { | |
1043 | tcg_gen_gvec_dup64i(ofs, oprsz, maxsz, word); | |
1044 | tcg_gen_movi_i64(t, 0); | |
1045 | tcg_gen_st_i64(t, cpu_env, ofs + oprsz - 8); | |
1046 | goto done; | |
1047 | } | |
1048 | } | |
1049 | ||
1050 | setsz /= 8; | |
1051 | fullsz /= 8; | |
1052 | ||
1053 | tcg_gen_movi_i64(t, word); | |
1054 | for (i = 0; i < setsz; i += 8) { | |
1055 | tcg_gen_st_i64(t, cpu_env, ofs + i); | |
1056 | } | |
1057 | if (lastword != word) { | |
1058 | tcg_gen_movi_i64(t, lastword); | |
1059 | tcg_gen_st_i64(t, cpu_env, ofs + i); | |
1060 | i += 8; | |
1061 | } | |
1062 | if (i < fullsz) { | |
1063 | tcg_gen_movi_i64(t, 0); | |
1064 | for (; i < fullsz; i += 8) { | |
1065 | tcg_gen_st_i64(t, cpu_env, ofs + i); | |
1066 | } | |
1067 | } | |
1068 | ||
1069 | done: | |
1070 | tcg_temp_free_i64(t); | |
1071 | ||
1072 | /* PTRUES */ | |
1073 | if (setflag) { | |
1074 | tcg_gen_movi_i32(cpu_NF, -(word != 0)); | |
1075 | tcg_gen_movi_i32(cpu_CF, word == 0); | |
1076 | tcg_gen_movi_i32(cpu_VF, 0); | |
1077 | tcg_gen_mov_i32(cpu_ZF, cpu_NF); | |
1078 | } | |
1079 | return true; | |
1080 | } | |
1081 | ||
1082 | static bool trans_PTRUE(DisasContext *s, arg_PTRUE *a, uint32_t insn) | |
1083 | { | |
1084 | return do_predset(s, a->esz, a->rd, a->pat, a->s); | |
1085 | } | |
1086 | ||
1087 | static bool trans_SETFFR(DisasContext *s, arg_SETFFR *a, uint32_t insn) | |
1088 | { | |
1089 | /* Note pat == 31 is #all, to set all elements. */ | |
1090 | return do_predset(s, 0, FFR_PRED_NUM, 31, false); | |
1091 | } | |
1092 | ||
1093 | static bool trans_PFALSE(DisasContext *s, arg_PFALSE *a, uint32_t insn) | |
1094 | { | |
1095 | /* Note pat == 32 is #unimp, to set no elements. */ | |
1096 | return do_predset(s, 0, a->rd, 32, false); | |
1097 | } | |
1098 | ||
1099 | static bool trans_RDFFR_p(DisasContext *s, arg_RDFFR_p *a, uint32_t insn) | |
1100 | { | |
1101 | /* The path through do_pppp_flags is complicated enough to want to avoid | |
1102 | * duplication. Frob the arguments into the form of a predicated AND. | |
1103 | */ | |
1104 | arg_rprr_s alt_a = { | |
1105 | .rd = a->rd, .pg = a->pg, .s = a->s, | |
1106 | .rn = FFR_PRED_NUM, .rm = FFR_PRED_NUM, | |
1107 | }; | |
1108 | return trans_AND_pppp(s, &alt_a, insn); | |
1109 | } | |
1110 | ||
1111 | static bool trans_RDFFR(DisasContext *s, arg_RDFFR *a, uint32_t insn) | |
1112 | { | |
1113 | return do_mov_p(s, a->rd, FFR_PRED_NUM); | |
1114 | } | |
1115 | ||
1116 | static bool trans_WRFFR(DisasContext *s, arg_WRFFR *a, uint32_t insn) | |
1117 | { | |
1118 | return do_mov_p(s, FFR_PRED_NUM, a->rn); | |
1119 | } | |
1120 | ||
1121 | static bool do_pfirst_pnext(DisasContext *s, arg_rr_esz *a, | |
1122 | void (*gen_fn)(TCGv_i32, TCGv_ptr, | |
1123 | TCGv_ptr, TCGv_i32)) | |
1124 | { | |
1125 | if (!sve_access_check(s)) { | |
1126 | return true; | |
1127 | } | |
1128 | ||
1129 | TCGv_ptr t_pd = tcg_temp_new_ptr(); | |
1130 | TCGv_ptr t_pg = tcg_temp_new_ptr(); | |
1131 | TCGv_i32 t; | |
1132 | unsigned desc; | |
1133 | ||
1134 | desc = DIV_ROUND_UP(pred_full_reg_size(s), 8); | |
1135 | desc = deposit32(desc, SIMD_DATA_SHIFT, 2, a->esz); | |
1136 | ||
1137 | tcg_gen_addi_ptr(t_pd, cpu_env, pred_full_reg_offset(s, a->rd)); | |
1138 | tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, a->rn)); | |
1139 | t = tcg_const_i32(desc); | |
1140 | ||
1141 | gen_fn(t, t_pd, t_pg, t); | |
1142 | tcg_temp_free_ptr(t_pd); | |
1143 | tcg_temp_free_ptr(t_pg); | |
1144 | ||
1145 | do_pred_flags(t); | |
1146 | tcg_temp_free_i32(t); | |
1147 | return true; | |
1148 | } | |
1149 | ||
1150 | static bool trans_PFIRST(DisasContext *s, arg_rr_esz *a, uint32_t insn) | |
1151 | { | |
1152 | return do_pfirst_pnext(s, a, gen_helper_sve_pfirst); | |
1153 | } | |
1154 | ||
1155 | static bool trans_PNEXT(DisasContext *s, arg_rr_esz *a, uint32_t insn) | |
1156 | { | |
1157 | return do_pfirst_pnext(s, a, gen_helper_sve_pnext); | |
1158 | } | |
1159 | ||
d1822297 RH |
1160 | /* |
1161 | *** SVE Memory - 32-bit Gather and Unsized Contiguous Group | |
1162 | */ | |
1163 | ||
1164 | /* Subroutine loading a vector register at VOFS of LEN bytes. | |
1165 | * The load should begin at the address Rn + IMM. | |
1166 | */ | |
1167 | ||
1168 | static void do_ldr(DisasContext *s, uint32_t vofs, uint32_t len, | |
1169 | int rn, int imm) | |
1170 | { | |
1171 | uint32_t len_align = QEMU_ALIGN_DOWN(len, 8); | |
1172 | uint32_t len_remain = len % 8; | |
1173 | uint32_t nparts = len / 8 + ctpop8(len_remain); | |
1174 | int midx = get_mem_index(s); | |
1175 | TCGv_i64 addr, t0, t1; | |
1176 | ||
1177 | addr = tcg_temp_new_i64(); | |
1178 | t0 = tcg_temp_new_i64(); | |
1179 | ||
1180 | /* Note that unpredicated load/store of vector/predicate registers | |
1181 | * are defined as a stream of bytes, which equates to little-endian | |
1182 | * operations on larger quantities. There is no nice way to force | |
1183 | * a little-endian load for aarch64_be-linux-user out of line. | |
1184 | * | |
1185 | * Attempt to keep code expansion to a minimum by limiting the | |
1186 | * amount of unrolling done. | |
1187 | */ | |
1188 | if (nparts <= 4) { | |
1189 | int i; | |
1190 | ||
1191 | for (i = 0; i < len_align; i += 8) { | |
1192 | tcg_gen_addi_i64(addr, cpu_reg_sp(s, rn), imm + i); | |
1193 | tcg_gen_qemu_ld_i64(t0, addr, midx, MO_LEQ); | |
1194 | tcg_gen_st_i64(t0, cpu_env, vofs + i); | |
1195 | } | |
1196 | } else { | |
1197 | TCGLabel *loop = gen_new_label(); | |
1198 | TCGv_ptr tp, i = tcg_const_local_ptr(0); | |
1199 | ||
1200 | gen_set_label(loop); | |
1201 | ||
1202 | /* Minimize the number of local temps that must be re-read from | |
1203 | * the stack each iteration. Instead, re-compute values other | |
1204 | * than the loop counter. | |
1205 | */ | |
1206 | tp = tcg_temp_new_ptr(); | |
1207 | tcg_gen_addi_ptr(tp, i, imm); | |
1208 | tcg_gen_extu_ptr_i64(addr, tp); | |
1209 | tcg_gen_add_i64(addr, addr, cpu_reg_sp(s, rn)); | |
1210 | ||
1211 | tcg_gen_qemu_ld_i64(t0, addr, midx, MO_LEQ); | |
1212 | ||
1213 | tcg_gen_add_ptr(tp, cpu_env, i); | |
1214 | tcg_gen_addi_ptr(i, i, 8); | |
1215 | tcg_gen_st_i64(t0, tp, vofs); | |
1216 | tcg_temp_free_ptr(tp); | |
1217 | ||
1218 | tcg_gen_brcondi_ptr(TCG_COND_LTU, i, len_align, loop); | |
1219 | tcg_temp_free_ptr(i); | |
1220 | } | |
1221 | ||
1222 | /* Predicate register loads can be any multiple of 2. | |
1223 | * Note that we still store the entire 64-bit unit into cpu_env. | |
1224 | */ | |
1225 | if (len_remain) { | |
1226 | tcg_gen_addi_i64(addr, cpu_reg_sp(s, rn), imm + len_align); | |
1227 | ||
1228 | switch (len_remain) { | |
1229 | case 2: | |
1230 | case 4: | |
1231 | case 8: | |
1232 | tcg_gen_qemu_ld_i64(t0, addr, midx, MO_LE | ctz32(len_remain)); | |
1233 | break; | |
1234 | ||
1235 | case 6: | |
1236 | t1 = tcg_temp_new_i64(); | |
1237 | tcg_gen_qemu_ld_i64(t0, addr, midx, MO_LEUL); | |
1238 | tcg_gen_addi_i64(addr, addr, 4); | |
1239 | tcg_gen_qemu_ld_i64(t1, addr, midx, MO_LEUW); | |
1240 | tcg_gen_deposit_i64(t0, t0, t1, 32, 32); | |
1241 | tcg_temp_free_i64(t1); | |
1242 | break; | |
1243 | ||
1244 | default: | |
1245 | g_assert_not_reached(); | |
1246 | } | |
1247 | tcg_gen_st_i64(t0, cpu_env, vofs + len_align); | |
1248 | } | |
1249 | tcg_temp_free_i64(addr); | |
1250 | tcg_temp_free_i64(t0); | |
1251 | } | |
1252 | ||
1253 | static bool trans_LDR_zri(DisasContext *s, arg_rri *a, uint32_t insn) | |
1254 | { | |
1255 | if (sve_access_check(s)) { | |
1256 | int size = vec_full_reg_size(s); | |
1257 | int off = vec_full_reg_offset(s, a->rd); | |
1258 | do_ldr(s, off, size, a->rn, a->imm * size); | |
1259 | } | |
1260 | return true; | |
1261 | } | |
1262 | ||
1263 | static bool trans_LDR_pri(DisasContext *s, arg_rri *a, uint32_t insn) | |
1264 | { | |
1265 | if (sve_access_check(s)) { | |
1266 | int size = pred_full_reg_size(s); | |
1267 | int off = pred_full_reg_offset(s, a->rd); | |
1268 | do_ldr(s, off, size, a->rn, a->imm * size); | |
1269 | } | |
1270 | return true; | |
1271 | } |