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38388f7e RH |
1 | /* |
2 | * AArch64 SVE translation | |
3 | * | |
4 | * Copyright (c) 2018 Linaro, Ltd | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
50f57e09 | 9 | * version 2.1 of the License, or (at your option) any later version. |
38388f7e RH |
10 | * |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #include "qemu/osdep.h" | |
21 | #include "cpu.h" | |
22 | #include "exec/exec-all.h" | |
dcb32f1d PMD |
23 | #include "tcg/tcg-op.h" |
24 | #include "tcg/tcg-op-gvec.h" | |
25 | #include "tcg/tcg-gvec-desc.h" | |
38388f7e RH |
26 | #include "qemu/log.h" |
27 | #include "arm_ldst.h" | |
28 | #include "translate.h" | |
29 | #include "internals.h" | |
30 | #include "exec/helper-proto.h" | |
31 | #include "exec/helper-gen.h" | |
32 | #include "exec/log.h" | |
38388f7e | 33 | #include "translate-a64.h" |
cc48affe | 34 | #include "fpu/softfloat.h" |
38388f7e | 35 | |
757f9cff | 36 | |
9ee3a611 RH |
37 | typedef void GVecGen2sFn(unsigned, uint32_t, uint32_t, |
38 | TCGv_i64, uint32_t, uint32_t); | |
39 | ||
38cadeba RH |
40 | typedef void gen_helper_gvec_flags_3(TCGv_i32, TCGv_ptr, TCGv_ptr, |
41 | TCGv_ptr, TCGv_i32); | |
757f9cff RH |
42 | typedef void gen_helper_gvec_flags_4(TCGv_i32, TCGv_ptr, TCGv_ptr, |
43 | TCGv_ptr, TCGv_ptr, TCGv_i32); | |
44 | ||
c4e7c493 | 45 | typedef void gen_helper_gvec_mem(TCGv_env, TCGv_ptr, TCGv_i64, TCGv_i32); |
f6dbf62a RH |
46 | typedef void gen_helper_gvec_mem_scatter(TCGv_env, TCGv_ptr, TCGv_ptr, |
47 | TCGv_ptr, TCGv_i64, TCGv_i32); | |
c4e7c493 | 48 | |
ccd841c3 RH |
49 | /* |
50 | * Helpers for extracting complex instruction fields. | |
51 | */ | |
52 | ||
53 | /* See e.g. ASR (immediate, predicated). | |
54 | * Returns -1 for unallocated encoding; diagnose later. | |
55 | */ | |
451e4ffd | 56 | static int tszimm_esz(DisasContext *s, int x) |
ccd841c3 RH |
57 | { |
58 | x >>= 3; /* discard imm3 */ | |
59 | return 31 - clz32(x); | |
60 | } | |
61 | ||
451e4ffd | 62 | static int tszimm_shr(DisasContext *s, int x) |
ccd841c3 | 63 | { |
451e4ffd | 64 | return (16 << tszimm_esz(s, x)) - x; |
ccd841c3 RH |
65 | } |
66 | ||
67 | /* See e.g. LSL (immediate, predicated). */ | |
451e4ffd | 68 | static int tszimm_shl(DisasContext *s, int x) |
ccd841c3 | 69 | { |
451e4ffd | 70 | return x - (8 << tszimm_esz(s, x)); |
ccd841c3 RH |
71 | } |
72 | ||
f25a2361 | 73 | /* The SH bit is in bit 8. Extract the low 8 and shift. */ |
451e4ffd | 74 | static inline int expand_imm_sh8s(DisasContext *s, int x) |
f25a2361 RH |
75 | { |
76 | return (int8_t)x << (x & 0x100 ? 8 : 0); | |
77 | } | |
78 | ||
451e4ffd | 79 | static inline int expand_imm_sh8u(DisasContext *s, int x) |
6e6a157d RH |
80 | { |
81 | return (uint8_t)x << (x & 0x100 ? 8 : 0); | |
82 | } | |
83 | ||
c4e7c493 RH |
84 | /* Convert a 2-bit memory size (msz) to a 4-bit data type (dtype) |
85 | * with unsigned data. C.f. SVE Memory Contiguous Load Group. | |
86 | */ | |
451e4ffd | 87 | static inline int msz_dtype(DisasContext *s, int msz) |
c4e7c493 RH |
88 | { |
89 | static const uint8_t dtype[4] = { 0, 5, 10, 15 }; | |
90 | return dtype[msz]; | |
91 | } | |
92 | ||
38388f7e RH |
93 | /* |
94 | * Include the generated decoder. | |
95 | */ | |
96 | ||
139c1837 | 97 | #include "decode-sve.c.inc" |
38388f7e RH |
98 | |
99 | /* | |
100 | * Implement all of the translator functions referenced by the decoder. | |
101 | */ | |
102 | ||
d1822297 RH |
103 | /* Return the offset info CPUARMState of the predicate vector register Pn. |
104 | * Note for this purpose, FFR is P16. | |
105 | */ | |
106 | static inline int pred_full_reg_offset(DisasContext *s, int regno) | |
107 | { | |
108 | return offsetof(CPUARMState, vfp.pregs[regno]); | |
109 | } | |
110 | ||
111 | /* Return the byte size of the whole predicate register, VL / 64. */ | |
112 | static inline int pred_full_reg_size(DisasContext *s) | |
113 | { | |
114 | return s->sve_len >> 3; | |
115 | } | |
116 | ||
516e246a RH |
117 | /* Round up the size of a register to a size allowed by |
118 | * the tcg vector infrastructure. Any operation which uses this | |
119 | * size may assume that the bits above pred_full_reg_size are zero, | |
120 | * and must leave them the same way. | |
121 | * | |
122 | * Note that this is not needed for the vector registers as they | |
123 | * are always properly sized for tcg vectors. | |
124 | */ | |
125 | static int size_for_gvec(int size) | |
126 | { | |
127 | if (size <= 8) { | |
128 | return 8; | |
129 | } else { | |
130 | return QEMU_ALIGN_UP(size, 16); | |
131 | } | |
132 | } | |
133 | ||
134 | static int pred_gvec_reg_size(DisasContext *s) | |
135 | { | |
136 | return size_for_gvec(pred_full_reg_size(s)); | |
137 | } | |
138 | ||
40e32e5a | 139 | /* Invoke an out-of-line helper on 2 Zregs. */ |
c5edf07d | 140 | static bool gen_gvec_ool_zz(DisasContext *s, gen_helper_gvec_2 *fn, |
40e32e5a RH |
141 | int rd, int rn, int data) |
142 | { | |
c5edf07d RH |
143 | if (fn == NULL) { |
144 | return false; | |
145 | } | |
146 | if (sve_access_check(s)) { | |
147 | unsigned vsz = vec_full_reg_size(s); | |
148 | tcg_gen_gvec_2_ool(vec_full_reg_offset(s, rd), | |
149 | vec_full_reg_offset(s, rn), | |
150 | vsz, vsz, data, fn); | |
151 | } | |
152 | return true; | |
40e32e5a RH |
153 | } |
154 | ||
e645d1a1 | 155 | /* Invoke an out-of-line helper on 3 Zregs. */ |
913a8a00 | 156 | static bool gen_gvec_ool_zzz(DisasContext *s, gen_helper_gvec_3 *fn, |
e645d1a1 RH |
157 | int rd, int rn, int rm, int data) |
158 | { | |
913a8a00 RH |
159 | if (fn == NULL) { |
160 | return false; | |
161 | } | |
162 | if (sve_access_check(s)) { | |
163 | unsigned vsz = vec_full_reg_size(s); | |
164 | tcg_gen_gvec_3_ool(vec_full_reg_offset(s, rd), | |
165 | vec_full_reg_offset(s, rn), | |
166 | vec_full_reg_offset(s, rm), | |
167 | vsz, vsz, data, fn); | |
168 | } | |
169 | return true; | |
e645d1a1 RH |
170 | } |
171 | ||
84a272f5 RH |
172 | static bool gen_gvec_ool_arg_zzz(DisasContext *s, gen_helper_gvec_3 *fn, |
173 | arg_rrr_esz *a, int data) | |
174 | { | |
175 | return gen_gvec_ool_zzz(s, fn, a->rd, a->rn, a->rm, data); | |
176 | } | |
177 | ||
38650638 | 178 | /* Invoke an out-of-line helper on 4 Zregs. */ |
7ad416b1 | 179 | static bool gen_gvec_ool_zzzz(DisasContext *s, gen_helper_gvec_4 *fn, |
38650638 RH |
180 | int rd, int rn, int rm, int ra, int data) |
181 | { | |
7ad416b1 RH |
182 | if (fn == NULL) { |
183 | return false; | |
184 | } | |
185 | if (sve_access_check(s)) { | |
186 | unsigned vsz = vec_full_reg_size(s); | |
187 | tcg_gen_gvec_4_ool(vec_full_reg_offset(s, rd), | |
188 | vec_full_reg_offset(s, rn), | |
189 | vec_full_reg_offset(s, rm), | |
190 | vec_full_reg_offset(s, ra), | |
191 | vsz, vsz, data, fn); | |
192 | } | |
193 | return true; | |
38650638 RH |
194 | } |
195 | ||
cab79ac9 RH |
196 | static bool gen_gvec_ool_arg_zzzz(DisasContext *s, gen_helper_gvec_4 *fn, |
197 | arg_rrrr_esz *a, int data) | |
198 | { | |
199 | return gen_gvec_ool_zzzz(s, fn, a->rd, a->rn, a->rm, a->ra, data); | |
200 | } | |
201 | ||
e82d3536 RH |
202 | static bool gen_gvec_ool_arg_zzxz(DisasContext *s, gen_helper_gvec_4 *fn, |
203 | arg_rrxr_esz *a) | |
204 | { | |
205 | return gen_gvec_ool_zzzz(s, fn, a->rd, a->rn, a->rm, a->ra, a->index); | |
206 | } | |
207 | ||
96a461f7 | 208 | /* Invoke an out-of-line helper on 2 Zregs and a predicate. */ |
8fb27a21 | 209 | static bool gen_gvec_ool_zzp(DisasContext *s, gen_helper_gvec_3 *fn, |
96a461f7 RH |
210 | int rd, int rn, int pg, int data) |
211 | { | |
8fb27a21 RH |
212 | if (fn == NULL) { |
213 | return false; | |
214 | } | |
215 | if (sve_access_check(s)) { | |
216 | unsigned vsz = vec_full_reg_size(s); | |
217 | tcg_gen_gvec_3_ool(vec_full_reg_offset(s, rd), | |
218 | vec_full_reg_offset(s, rn), | |
219 | pred_full_reg_offset(s, pg), | |
220 | vsz, vsz, data, fn); | |
221 | } | |
222 | return true; | |
96a461f7 RH |
223 | } |
224 | ||
b051809a RH |
225 | static bool gen_gvec_ool_arg_zpz(DisasContext *s, gen_helper_gvec_3 *fn, |
226 | arg_rpr_esz *a, int data) | |
227 | { | |
228 | return gen_gvec_ool_zzp(s, fn, a->rd, a->rn, a->pg, data); | |
229 | } | |
230 | ||
afa2529c RH |
231 | static bool gen_gvec_ool_arg_zpzi(DisasContext *s, gen_helper_gvec_3 *fn, |
232 | arg_rpri_esz *a) | |
233 | { | |
234 | return gen_gvec_ool_zzp(s, fn, a->rd, a->rn, a->pg, a->imm); | |
235 | } | |
b051809a | 236 | |
36cbb7a8 | 237 | /* Invoke an out-of-line helper on 3 Zregs and a predicate. */ |
2a753d1e | 238 | static bool gen_gvec_ool_zzzp(DisasContext *s, gen_helper_gvec_4 *fn, |
36cbb7a8 RH |
239 | int rd, int rn, int rm, int pg, int data) |
240 | { | |
2a753d1e RH |
241 | if (fn == NULL) { |
242 | return false; | |
243 | } | |
244 | if (sve_access_check(s)) { | |
245 | unsigned vsz = vec_full_reg_size(s); | |
246 | tcg_gen_gvec_4_ool(vec_full_reg_offset(s, rd), | |
247 | vec_full_reg_offset(s, rn), | |
248 | vec_full_reg_offset(s, rm), | |
249 | pred_full_reg_offset(s, pg), | |
250 | vsz, vsz, data, fn); | |
251 | } | |
252 | return true; | |
36cbb7a8 | 253 | } |
f7d79c41 | 254 | |
312016c9 RH |
255 | static bool gen_gvec_ool_arg_zpzz(DisasContext *s, gen_helper_gvec_4 *fn, |
256 | arg_rprr_esz *a, int data) | |
257 | { | |
258 | return gen_gvec_ool_zzzp(s, fn, a->rd, a->rn, a->rm, a->pg, data); | |
259 | } | |
260 | ||
faf915e2 RH |
261 | /* Invoke a vector expander on two Zregs and an immediate. */ |
262 | static bool gen_gvec_fn_zzi(DisasContext *s, GVecGen2iFn *gvec_fn, | |
263 | int esz, int rd, int rn, uint64_t imm) | |
264 | { | |
265 | if (gvec_fn == NULL) { | |
266 | return false; | |
267 | } | |
268 | if (sve_access_check(s)) { | |
269 | unsigned vsz = vec_full_reg_size(s); | |
270 | gvec_fn(esz, vec_full_reg_offset(s, rd), | |
271 | vec_full_reg_offset(s, rn), imm, vsz, vsz); | |
272 | } | |
273 | return true; | |
274 | } | |
275 | ||
39eea561 | 276 | /* Invoke a vector expander on three Zregs. */ |
50f6db5f | 277 | static bool gen_gvec_fn_zzz(DisasContext *s, GVecGen3Fn *gvec_fn, |
28c4da31 | 278 | int esz, int rd, int rn, int rm) |
38388f7e | 279 | { |
50f6db5f RH |
280 | if (gvec_fn == NULL) { |
281 | return false; | |
282 | } | |
283 | if (sve_access_check(s)) { | |
284 | unsigned vsz = vec_full_reg_size(s); | |
285 | gvec_fn(esz, vec_full_reg_offset(s, rd), | |
286 | vec_full_reg_offset(s, rn), | |
287 | vec_full_reg_offset(s, rm), vsz, vsz); | |
288 | } | |
289 | return true; | |
38388f7e RH |
290 | } |
291 | ||
cd54bbe6 RH |
292 | static bool gen_gvec_fn_arg_zzz(DisasContext *s, GVecGen3Fn *fn, |
293 | arg_rrr_esz *a) | |
294 | { | |
295 | return gen_gvec_fn_zzz(s, fn, a->esz, a->rd, a->rn, a->rm); | |
296 | } | |
297 | ||
911cdc6d | 298 | /* Invoke a vector expander on four Zregs. */ |
189876af RH |
299 | static bool gen_gvec_fn_arg_zzzz(DisasContext *s, GVecGen4Fn *gvec_fn, |
300 | arg_rrrr_esz *a) | |
911cdc6d | 301 | { |
189876af RH |
302 | if (gvec_fn == NULL) { |
303 | return false; | |
304 | } | |
305 | if (sve_access_check(s)) { | |
306 | unsigned vsz = vec_full_reg_size(s); | |
307 | gvec_fn(a->esz, vec_full_reg_offset(s, a->rd), | |
308 | vec_full_reg_offset(s, a->rn), | |
309 | vec_full_reg_offset(s, a->rm), | |
310 | vec_full_reg_offset(s, a->ra), vsz, vsz); | |
311 | } | |
312 | return true; | |
911cdc6d RH |
313 | } |
314 | ||
39eea561 RH |
315 | /* Invoke a vector move on two Zregs. */ |
316 | static bool do_mov_z(DisasContext *s, int rd, int rn) | |
38388f7e | 317 | { |
f7d79c41 | 318 | if (sve_access_check(s)) { |
5f730621 RH |
319 | unsigned vsz = vec_full_reg_size(s); |
320 | tcg_gen_gvec_mov(MO_8, vec_full_reg_offset(s, rd), | |
321 | vec_full_reg_offset(s, rn), vsz, vsz); | |
f7d79c41 RH |
322 | } |
323 | return true; | |
38388f7e RH |
324 | } |
325 | ||
d9d78dcc RH |
326 | /* Initialize a Zreg with replications of a 64-bit immediate. */ |
327 | static void do_dupi_z(DisasContext *s, int rd, uint64_t word) | |
328 | { | |
329 | unsigned vsz = vec_full_reg_size(s); | |
8711e71f | 330 | tcg_gen_gvec_dup_imm(MO_64, vec_full_reg_offset(s, rd), vsz, vsz, word); |
d9d78dcc RH |
331 | } |
332 | ||
516e246a | 333 | /* Invoke a vector expander on three Pregs. */ |
dd81a8d7 RH |
334 | static void gen_gvec_fn_ppp(DisasContext *s, GVecGen3Fn *gvec_fn, |
335 | int rd, int rn, int rm) | |
516e246a | 336 | { |
dd81a8d7 RH |
337 | unsigned psz = pred_gvec_reg_size(s); |
338 | gvec_fn(MO_64, pred_full_reg_offset(s, rd), | |
339 | pred_full_reg_offset(s, rn), | |
340 | pred_full_reg_offset(s, rm), psz, psz); | |
516e246a RH |
341 | } |
342 | ||
343 | /* Invoke a vector move on two Pregs. */ | |
344 | static bool do_mov_p(DisasContext *s, int rd, int rn) | |
345 | { | |
d0b2df5a RH |
346 | if (sve_access_check(s)) { |
347 | unsigned psz = pred_gvec_reg_size(s); | |
348 | tcg_gen_gvec_mov(MO_8, pred_full_reg_offset(s, rd), | |
349 | pred_full_reg_offset(s, rn), psz, psz); | |
350 | } | |
351 | return true; | |
516e246a RH |
352 | } |
353 | ||
9e18d7a6 RH |
354 | /* Set the cpu flags as per a return from an SVE helper. */ |
355 | static void do_pred_flags(TCGv_i32 t) | |
356 | { | |
357 | tcg_gen_mov_i32(cpu_NF, t); | |
358 | tcg_gen_andi_i32(cpu_ZF, t, 2); | |
359 | tcg_gen_andi_i32(cpu_CF, t, 1); | |
360 | tcg_gen_movi_i32(cpu_VF, 0); | |
361 | } | |
362 | ||
363 | /* Subroutines computing the ARM PredTest psuedofunction. */ | |
364 | static void do_predtest1(TCGv_i64 d, TCGv_i64 g) | |
365 | { | |
366 | TCGv_i32 t = tcg_temp_new_i32(); | |
367 | ||
368 | gen_helper_sve_predtest1(t, d, g); | |
369 | do_pred_flags(t); | |
370 | tcg_temp_free_i32(t); | |
371 | } | |
372 | ||
373 | static void do_predtest(DisasContext *s, int dofs, int gofs, int words) | |
374 | { | |
375 | TCGv_ptr dptr = tcg_temp_new_ptr(); | |
376 | TCGv_ptr gptr = tcg_temp_new_ptr(); | |
392acacc | 377 | TCGv_i32 t = tcg_temp_new_i32(); |
9e18d7a6 RH |
378 | |
379 | tcg_gen_addi_ptr(dptr, cpu_env, dofs); | |
380 | tcg_gen_addi_ptr(gptr, cpu_env, gofs); | |
9e18d7a6 | 381 | |
392acacc | 382 | gen_helper_sve_predtest(t, dptr, gptr, tcg_constant_i32(words)); |
9e18d7a6 RH |
383 | tcg_temp_free_ptr(dptr); |
384 | tcg_temp_free_ptr(gptr); | |
385 | ||
386 | do_pred_flags(t); | |
387 | tcg_temp_free_i32(t); | |
388 | } | |
389 | ||
028e2a7b RH |
390 | /* For each element size, the bits within a predicate word that are active. */ |
391 | const uint64_t pred_esz_masks[4] = { | |
392 | 0xffffffffffffffffull, 0x5555555555555555ull, | |
393 | 0x1111111111111111ull, 0x0101010101010101ull | |
394 | }; | |
395 | ||
39eea561 RH |
396 | /* |
397 | *** SVE Logical - Unpredicated Group | |
398 | */ | |
399 | ||
b262215b RH |
400 | TRANS_FEAT(AND_zzz, aa64_sve, gen_gvec_fn_arg_zzz, tcg_gen_gvec_and, a) |
401 | TRANS_FEAT(ORR_zzz, aa64_sve, gen_gvec_fn_arg_zzz, tcg_gen_gvec_or, a) | |
402 | TRANS_FEAT(EOR_zzz, aa64_sve, gen_gvec_fn_arg_zzz, tcg_gen_gvec_xor, a) | |
403 | TRANS_FEAT(BIC_zzz, aa64_sve, gen_gvec_fn_arg_zzz, tcg_gen_gvec_andc, a) | |
d1822297 | 404 | |
e6eba6e5 RH |
405 | static void gen_xar8_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m, int64_t sh) |
406 | { | |
407 | TCGv_i64 t = tcg_temp_new_i64(); | |
408 | uint64_t mask = dup_const(MO_8, 0xff >> sh); | |
409 | ||
410 | tcg_gen_xor_i64(t, n, m); | |
411 | tcg_gen_shri_i64(d, t, sh); | |
412 | tcg_gen_shli_i64(t, t, 8 - sh); | |
413 | tcg_gen_andi_i64(d, d, mask); | |
414 | tcg_gen_andi_i64(t, t, ~mask); | |
415 | tcg_gen_or_i64(d, d, t); | |
416 | tcg_temp_free_i64(t); | |
417 | } | |
418 | ||
419 | static void gen_xar16_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m, int64_t sh) | |
420 | { | |
421 | TCGv_i64 t = tcg_temp_new_i64(); | |
422 | uint64_t mask = dup_const(MO_16, 0xffff >> sh); | |
423 | ||
424 | tcg_gen_xor_i64(t, n, m); | |
425 | tcg_gen_shri_i64(d, t, sh); | |
426 | tcg_gen_shli_i64(t, t, 16 - sh); | |
427 | tcg_gen_andi_i64(d, d, mask); | |
428 | tcg_gen_andi_i64(t, t, ~mask); | |
429 | tcg_gen_or_i64(d, d, t); | |
430 | tcg_temp_free_i64(t); | |
431 | } | |
432 | ||
433 | static void gen_xar_i32(TCGv_i32 d, TCGv_i32 n, TCGv_i32 m, int32_t sh) | |
434 | { | |
435 | tcg_gen_xor_i32(d, n, m); | |
436 | tcg_gen_rotri_i32(d, d, sh); | |
437 | } | |
438 | ||
439 | static void gen_xar_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m, int64_t sh) | |
440 | { | |
441 | tcg_gen_xor_i64(d, n, m); | |
442 | tcg_gen_rotri_i64(d, d, sh); | |
443 | } | |
444 | ||
445 | static void gen_xar_vec(unsigned vece, TCGv_vec d, TCGv_vec n, | |
446 | TCGv_vec m, int64_t sh) | |
447 | { | |
448 | tcg_gen_xor_vec(vece, d, n, m); | |
449 | tcg_gen_rotri_vec(vece, d, d, sh); | |
450 | } | |
451 | ||
452 | void gen_gvec_xar(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, | |
453 | uint32_t rm_ofs, int64_t shift, | |
454 | uint32_t opr_sz, uint32_t max_sz) | |
455 | { | |
456 | static const TCGOpcode vecop[] = { INDEX_op_rotli_vec, 0 }; | |
457 | static const GVecGen3i ops[4] = { | |
458 | { .fni8 = gen_xar8_i64, | |
459 | .fniv = gen_xar_vec, | |
460 | .fno = gen_helper_sve2_xar_b, | |
461 | .opt_opc = vecop, | |
462 | .vece = MO_8 }, | |
463 | { .fni8 = gen_xar16_i64, | |
464 | .fniv = gen_xar_vec, | |
465 | .fno = gen_helper_sve2_xar_h, | |
466 | .opt_opc = vecop, | |
467 | .vece = MO_16 }, | |
468 | { .fni4 = gen_xar_i32, | |
469 | .fniv = gen_xar_vec, | |
470 | .fno = gen_helper_sve2_xar_s, | |
471 | .opt_opc = vecop, | |
472 | .vece = MO_32 }, | |
473 | { .fni8 = gen_xar_i64, | |
474 | .fniv = gen_xar_vec, | |
475 | .fno = gen_helper_gvec_xar_d, | |
476 | .opt_opc = vecop, | |
477 | .vece = MO_64 } | |
478 | }; | |
479 | int esize = 8 << vece; | |
480 | ||
481 | /* The SVE2 range is 1 .. esize; the AdvSIMD range is 0 .. esize-1. */ | |
482 | tcg_debug_assert(shift >= 0); | |
483 | tcg_debug_assert(shift <= esize); | |
484 | shift &= esize - 1; | |
485 | ||
486 | if (shift == 0) { | |
487 | /* xar with no rotate devolves to xor. */ | |
488 | tcg_gen_gvec_xor(vece, rd_ofs, rn_ofs, rm_ofs, opr_sz, max_sz); | |
489 | } else { | |
490 | tcg_gen_gvec_3i(rd_ofs, rn_ofs, rm_ofs, opr_sz, max_sz, | |
491 | shift, &ops[vece]); | |
492 | } | |
493 | } | |
494 | ||
495 | static bool trans_XAR(DisasContext *s, arg_rrri_esz *a) | |
496 | { | |
497 | if (a->esz < 0 || !dc_isar_feature(aa64_sve2, s)) { | |
498 | return false; | |
499 | } | |
500 | if (sve_access_check(s)) { | |
501 | unsigned vsz = vec_full_reg_size(s); | |
502 | gen_gvec_xar(a->esz, vec_full_reg_offset(s, a->rd), | |
503 | vec_full_reg_offset(s, a->rn), | |
504 | vec_full_reg_offset(s, a->rm), a->imm, vsz, vsz); | |
505 | } | |
506 | return true; | |
507 | } | |
508 | ||
911cdc6d RH |
509 | static void gen_eor3_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m, TCGv_i64 k) |
510 | { | |
511 | tcg_gen_xor_i64(d, n, m); | |
512 | tcg_gen_xor_i64(d, d, k); | |
513 | } | |
514 | ||
515 | static void gen_eor3_vec(unsigned vece, TCGv_vec d, TCGv_vec n, | |
516 | TCGv_vec m, TCGv_vec k) | |
517 | { | |
518 | tcg_gen_xor_vec(vece, d, n, m); | |
519 | tcg_gen_xor_vec(vece, d, d, k); | |
520 | } | |
521 | ||
522 | static void gen_eor3(unsigned vece, uint32_t d, uint32_t n, uint32_t m, | |
523 | uint32_t a, uint32_t oprsz, uint32_t maxsz) | |
524 | { | |
525 | static const GVecGen4 op = { | |
526 | .fni8 = gen_eor3_i64, | |
527 | .fniv = gen_eor3_vec, | |
528 | .fno = gen_helper_sve2_eor3, | |
529 | .vece = MO_64, | |
530 | .prefer_i64 = TCG_TARGET_REG_BITS == 64, | |
531 | }; | |
532 | tcg_gen_gvec_4(d, n, m, a, oprsz, maxsz, &op); | |
533 | } | |
534 | ||
b773a5c8 | 535 | TRANS_FEAT(EOR3, aa64_sve2, gen_gvec_fn_arg_zzzz, gen_eor3, a) |
911cdc6d RH |
536 | |
537 | static void gen_bcax_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m, TCGv_i64 k) | |
538 | { | |
539 | tcg_gen_andc_i64(d, m, k); | |
540 | tcg_gen_xor_i64(d, d, n); | |
541 | } | |
542 | ||
543 | static void gen_bcax_vec(unsigned vece, TCGv_vec d, TCGv_vec n, | |
544 | TCGv_vec m, TCGv_vec k) | |
545 | { | |
546 | tcg_gen_andc_vec(vece, d, m, k); | |
547 | tcg_gen_xor_vec(vece, d, d, n); | |
548 | } | |
549 | ||
550 | static void gen_bcax(unsigned vece, uint32_t d, uint32_t n, uint32_t m, | |
551 | uint32_t a, uint32_t oprsz, uint32_t maxsz) | |
552 | { | |
553 | static const GVecGen4 op = { | |
554 | .fni8 = gen_bcax_i64, | |
555 | .fniv = gen_bcax_vec, | |
556 | .fno = gen_helper_sve2_bcax, | |
557 | .vece = MO_64, | |
558 | .prefer_i64 = TCG_TARGET_REG_BITS == 64, | |
559 | }; | |
560 | tcg_gen_gvec_4(d, n, m, a, oprsz, maxsz, &op); | |
561 | } | |
562 | ||
b773a5c8 | 563 | TRANS_FEAT(BCAX, aa64_sve2, gen_gvec_fn_arg_zzzz, gen_bcax, a) |
911cdc6d RH |
564 | |
565 | static void gen_bsl(unsigned vece, uint32_t d, uint32_t n, uint32_t m, | |
566 | uint32_t a, uint32_t oprsz, uint32_t maxsz) | |
567 | { | |
568 | /* BSL differs from the generic bitsel in argument ordering. */ | |
569 | tcg_gen_gvec_bitsel(vece, d, a, n, m, oprsz, maxsz); | |
570 | } | |
571 | ||
b773a5c8 | 572 | TRANS_FEAT(BSL, aa64_sve2, gen_gvec_fn_arg_zzzz, gen_bsl, a) |
911cdc6d RH |
573 | |
574 | static void gen_bsl1n_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m, TCGv_i64 k) | |
575 | { | |
576 | tcg_gen_andc_i64(n, k, n); | |
577 | tcg_gen_andc_i64(m, m, k); | |
578 | tcg_gen_or_i64(d, n, m); | |
579 | } | |
580 | ||
581 | static void gen_bsl1n_vec(unsigned vece, TCGv_vec d, TCGv_vec n, | |
582 | TCGv_vec m, TCGv_vec k) | |
583 | { | |
584 | if (TCG_TARGET_HAS_bitsel_vec) { | |
585 | tcg_gen_not_vec(vece, n, n); | |
586 | tcg_gen_bitsel_vec(vece, d, k, n, m); | |
587 | } else { | |
588 | tcg_gen_andc_vec(vece, n, k, n); | |
589 | tcg_gen_andc_vec(vece, m, m, k); | |
590 | tcg_gen_or_vec(vece, d, n, m); | |
591 | } | |
592 | } | |
593 | ||
594 | static void gen_bsl1n(unsigned vece, uint32_t d, uint32_t n, uint32_t m, | |
595 | uint32_t a, uint32_t oprsz, uint32_t maxsz) | |
596 | { | |
597 | static const GVecGen4 op = { | |
598 | .fni8 = gen_bsl1n_i64, | |
599 | .fniv = gen_bsl1n_vec, | |
600 | .fno = gen_helper_sve2_bsl1n, | |
601 | .vece = MO_64, | |
602 | .prefer_i64 = TCG_TARGET_REG_BITS == 64, | |
603 | }; | |
604 | tcg_gen_gvec_4(d, n, m, a, oprsz, maxsz, &op); | |
605 | } | |
606 | ||
b773a5c8 | 607 | TRANS_FEAT(BSL1N, aa64_sve2, gen_gvec_fn_arg_zzzz, gen_bsl1n, a) |
911cdc6d RH |
608 | |
609 | static void gen_bsl2n_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m, TCGv_i64 k) | |
610 | { | |
611 | /* | |
612 | * Z[dn] = (n & k) | (~m & ~k) | |
613 | * = | ~(m | k) | |
614 | */ | |
615 | tcg_gen_and_i64(n, n, k); | |
616 | if (TCG_TARGET_HAS_orc_i64) { | |
617 | tcg_gen_or_i64(m, m, k); | |
618 | tcg_gen_orc_i64(d, n, m); | |
619 | } else { | |
620 | tcg_gen_nor_i64(m, m, k); | |
621 | tcg_gen_or_i64(d, n, m); | |
622 | } | |
623 | } | |
624 | ||
625 | static void gen_bsl2n_vec(unsigned vece, TCGv_vec d, TCGv_vec n, | |
626 | TCGv_vec m, TCGv_vec k) | |
627 | { | |
628 | if (TCG_TARGET_HAS_bitsel_vec) { | |
629 | tcg_gen_not_vec(vece, m, m); | |
630 | tcg_gen_bitsel_vec(vece, d, k, n, m); | |
631 | } else { | |
632 | tcg_gen_and_vec(vece, n, n, k); | |
633 | tcg_gen_or_vec(vece, m, m, k); | |
634 | tcg_gen_orc_vec(vece, d, n, m); | |
635 | } | |
636 | } | |
637 | ||
638 | static void gen_bsl2n(unsigned vece, uint32_t d, uint32_t n, uint32_t m, | |
639 | uint32_t a, uint32_t oprsz, uint32_t maxsz) | |
640 | { | |
641 | static const GVecGen4 op = { | |
642 | .fni8 = gen_bsl2n_i64, | |
643 | .fniv = gen_bsl2n_vec, | |
644 | .fno = gen_helper_sve2_bsl2n, | |
645 | .vece = MO_64, | |
646 | .prefer_i64 = TCG_TARGET_REG_BITS == 64, | |
647 | }; | |
648 | tcg_gen_gvec_4(d, n, m, a, oprsz, maxsz, &op); | |
649 | } | |
650 | ||
b773a5c8 | 651 | TRANS_FEAT(BSL2N, aa64_sve2, gen_gvec_fn_arg_zzzz, gen_bsl2n, a) |
911cdc6d RH |
652 | |
653 | static void gen_nbsl_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m, TCGv_i64 k) | |
654 | { | |
655 | tcg_gen_and_i64(n, n, k); | |
656 | tcg_gen_andc_i64(m, m, k); | |
657 | tcg_gen_nor_i64(d, n, m); | |
658 | } | |
659 | ||
660 | static void gen_nbsl_vec(unsigned vece, TCGv_vec d, TCGv_vec n, | |
661 | TCGv_vec m, TCGv_vec k) | |
662 | { | |
663 | tcg_gen_bitsel_vec(vece, d, k, n, m); | |
664 | tcg_gen_not_vec(vece, d, d); | |
665 | } | |
666 | ||
667 | static void gen_nbsl(unsigned vece, uint32_t d, uint32_t n, uint32_t m, | |
668 | uint32_t a, uint32_t oprsz, uint32_t maxsz) | |
669 | { | |
670 | static const GVecGen4 op = { | |
671 | .fni8 = gen_nbsl_i64, | |
672 | .fniv = gen_nbsl_vec, | |
673 | .fno = gen_helper_sve2_nbsl, | |
674 | .vece = MO_64, | |
675 | .prefer_i64 = TCG_TARGET_REG_BITS == 64, | |
676 | }; | |
677 | tcg_gen_gvec_4(d, n, m, a, oprsz, maxsz, &op); | |
678 | } | |
679 | ||
b773a5c8 | 680 | TRANS_FEAT(NBSL, aa64_sve2, gen_gvec_fn_arg_zzzz, gen_nbsl, a) |
911cdc6d | 681 | |
fea98f9c RH |
682 | /* |
683 | *** SVE Integer Arithmetic - Unpredicated Group | |
684 | */ | |
685 | ||
b262215b RH |
686 | TRANS_FEAT(ADD_zzz, aa64_sve, gen_gvec_fn_arg_zzz, tcg_gen_gvec_add, a) |
687 | TRANS_FEAT(SUB_zzz, aa64_sve, gen_gvec_fn_arg_zzz, tcg_gen_gvec_sub, a) | |
688 | TRANS_FEAT(SQADD_zzz, aa64_sve, gen_gvec_fn_arg_zzz, tcg_gen_gvec_ssadd, a) | |
689 | TRANS_FEAT(SQSUB_zzz, aa64_sve, gen_gvec_fn_arg_zzz, tcg_gen_gvec_sssub, a) | |
690 | TRANS_FEAT(UQADD_zzz, aa64_sve, gen_gvec_fn_arg_zzz, tcg_gen_gvec_usadd, a) | |
691 | TRANS_FEAT(UQSUB_zzz, aa64_sve, gen_gvec_fn_arg_zzz, tcg_gen_gvec_ussub, a) | |
fea98f9c | 692 | |
f97cfd59 RH |
693 | /* |
694 | *** SVE Integer Arithmetic - Binary Predicated Group | |
695 | */ | |
696 | ||
a2103582 RH |
697 | /* Select active elememnts from Zn and inactive elements from Zm, |
698 | * storing the result in Zd. | |
699 | */ | |
700 | static void do_sel_z(DisasContext *s, int rd, int rn, int rm, int pg, int esz) | |
701 | { | |
702 | static gen_helper_gvec_4 * const fns[4] = { | |
703 | gen_helper_sve_sel_zpzz_b, gen_helper_sve_sel_zpzz_h, | |
704 | gen_helper_sve_sel_zpzz_s, gen_helper_sve_sel_zpzz_d | |
705 | }; | |
36cbb7a8 | 706 | gen_gvec_ool_zzzp(s, fns[esz], rd, rn, rm, pg, 0); |
a2103582 RH |
707 | } |
708 | ||
8e7acb24 RH |
709 | #define DO_ZPZZ(NAME, FEAT, name) \ |
710 | static gen_helper_gvec_4 * const name##_zpzz_fns[4] = { \ | |
711 | gen_helper_##name##_zpzz_b, gen_helper_##name##_zpzz_h, \ | |
712 | gen_helper_##name##_zpzz_s, gen_helper_##name##_zpzz_d, \ | |
f97cfd59 | 713 | }; \ |
8e7acb24 RH |
714 | TRANS_FEAT(NAME, FEAT, gen_gvec_ool_arg_zpzz, \ |
715 | name##_zpzz_fns[a->esz], a, 0) | |
716 | ||
717 | DO_ZPZZ(AND_zpzz, aa64_sve, sve_and) | |
718 | DO_ZPZZ(EOR_zpzz, aa64_sve, sve_eor) | |
719 | DO_ZPZZ(ORR_zpzz, aa64_sve, sve_orr) | |
720 | DO_ZPZZ(BIC_zpzz, aa64_sve, sve_bic) | |
721 | ||
722 | DO_ZPZZ(ADD_zpzz, aa64_sve, sve_add) | |
723 | DO_ZPZZ(SUB_zpzz, aa64_sve, sve_sub) | |
724 | ||
725 | DO_ZPZZ(SMAX_zpzz, aa64_sve, sve_smax) | |
726 | DO_ZPZZ(UMAX_zpzz, aa64_sve, sve_umax) | |
727 | DO_ZPZZ(SMIN_zpzz, aa64_sve, sve_smin) | |
728 | DO_ZPZZ(UMIN_zpzz, aa64_sve, sve_umin) | |
729 | DO_ZPZZ(SABD_zpzz, aa64_sve, sve_sabd) | |
730 | DO_ZPZZ(UABD_zpzz, aa64_sve, sve_uabd) | |
731 | ||
732 | DO_ZPZZ(MUL_zpzz, aa64_sve, sve_mul) | |
733 | DO_ZPZZ(SMULH_zpzz, aa64_sve, sve_smulh) | |
734 | DO_ZPZZ(UMULH_zpzz, aa64_sve, sve_umulh) | |
735 | ||
736 | DO_ZPZZ(ASR_zpzz, aa64_sve, sve_asr) | |
737 | DO_ZPZZ(LSR_zpzz, aa64_sve, sve_lsr) | |
738 | DO_ZPZZ(LSL_zpzz, aa64_sve, sve_lsl) | |
739 | ||
740 | static gen_helper_gvec_4 * const sdiv_fns[4] = { | |
741 | NULL, NULL, gen_helper_sve_sdiv_zpzz_s, gen_helper_sve_sdiv_zpzz_d | |
742 | }; | |
743 | TRANS_FEAT(SDIV_zpzz, aa64_sve, gen_gvec_ool_arg_zpzz, sdiv_fns[a->esz], a, 0) | |
f97cfd59 | 744 | |
8e7acb24 RH |
745 | static gen_helper_gvec_4 * const udiv_fns[4] = { |
746 | NULL, NULL, gen_helper_sve_udiv_zpzz_s, gen_helper_sve_udiv_zpzz_d | |
747 | }; | |
748 | TRANS_FEAT(UDIV_zpzz, aa64_sve, gen_gvec_ool_arg_zpzz, udiv_fns[a->esz], a, 0) | |
f97cfd59 | 749 | |
3a7be554 | 750 | static bool trans_SEL_zpzz(DisasContext *s, arg_rprr_esz *a) |
a2103582 RH |
751 | { |
752 | if (sve_access_check(s)) { | |
753 | do_sel_z(s, a->rd, a->rn, a->rm, a->pg, a->esz); | |
754 | } | |
755 | return true; | |
756 | } | |
d3fe4a29 | 757 | |
afac6d04 RH |
758 | /* |
759 | *** SVE Integer Arithmetic - Unary Predicated Group | |
760 | */ | |
761 | ||
817bd5c9 RH |
762 | #define DO_ZPZ(NAME, FEAT, name) \ |
763 | static gen_helper_gvec_3 * const name##_fns[4] = { \ | |
764 | gen_helper_##name##_b, gen_helper_##name##_h, \ | |
765 | gen_helper_##name##_s, gen_helper_##name##_d, \ | |
afac6d04 | 766 | }; \ |
817bd5c9 RH |
767 | TRANS_FEAT(NAME, FEAT, gen_gvec_ool_arg_zpz, name##_fns[a->esz], a, 0) |
768 | ||
769 | DO_ZPZ(CLS, aa64_sve, sve_cls) | |
770 | DO_ZPZ(CLZ, aa64_sve, sve_clz) | |
771 | DO_ZPZ(CNT_zpz, aa64_sve, sve_cnt_zpz) | |
772 | DO_ZPZ(CNOT, aa64_sve, sve_cnot) | |
773 | DO_ZPZ(NOT_zpz, aa64_sve, sve_not_zpz) | |
774 | DO_ZPZ(ABS, aa64_sve, sve_abs) | |
775 | DO_ZPZ(NEG, aa64_sve, sve_neg) | |
776 | DO_ZPZ(RBIT, aa64_sve, sve_rbit) | |
777 | ||
778 | static gen_helper_gvec_3 * const fabs_fns[4] = { | |
779 | NULL, gen_helper_sve_fabs_h, | |
780 | gen_helper_sve_fabs_s, gen_helper_sve_fabs_d, | |
781 | }; | |
782 | TRANS_FEAT(FABS, aa64_sve, gen_gvec_ool_arg_zpz, fabs_fns[a->esz], a, 0) | |
afac6d04 | 783 | |
817bd5c9 RH |
784 | static gen_helper_gvec_3 * const fneg_fns[4] = { |
785 | NULL, gen_helper_sve_fneg_h, | |
786 | gen_helper_sve_fneg_s, gen_helper_sve_fneg_d, | |
787 | }; | |
788 | TRANS_FEAT(FNEG, aa64_sve, gen_gvec_ool_arg_zpz, fneg_fns[a->esz], a, 0) | |
afac6d04 | 789 | |
817bd5c9 RH |
790 | static gen_helper_gvec_3 * const sxtb_fns[4] = { |
791 | NULL, gen_helper_sve_sxtb_h, | |
792 | gen_helper_sve_sxtb_s, gen_helper_sve_sxtb_d, | |
793 | }; | |
794 | TRANS_FEAT(SXTB, aa64_sve, gen_gvec_ool_arg_zpz, sxtb_fns[a->esz], a, 0) | |
afac6d04 | 795 | |
817bd5c9 RH |
796 | static gen_helper_gvec_3 * const uxtb_fns[4] = { |
797 | NULL, gen_helper_sve_uxtb_h, | |
798 | gen_helper_sve_uxtb_s, gen_helper_sve_uxtb_d, | |
799 | }; | |
800 | TRANS_FEAT(UXTB, aa64_sve, gen_gvec_ool_arg_zpz, uxtb_fns[a->esz], a, 0) | |
afac6d04 | 801 | |
817bd5c9 RH |
802 | static gen_helper_gvec_3 * const sxth_fns[4] = { |
803 | NULL, NULL, gen_helper_sve_sxth_s, gen_helper_sve_sxth_d | |
804 | }; | |
805 | TRANS_FEAT(SXTH, aa64_sve, gen_gvec_ool_arg_zpz, sxth_fns[a->esz], a, 0) | |
afac6d04 | 806 | |
817bd5c9 RH |
807 | static gen_helper_gvec_3 * const uxth_fns[4] = { |
808 | NULL, NULL, gen_helper_sve_uxth_s, gen_helper_sve_uxth_d | |
809 | }; | |
810 | TRANS_FEAT(UXTH, aa64_sve, gen_gvec_ool_arg_zpz, uxth_fns[a->esz], a, 0) | |
afac6d04 | 811 | |
817bd5c9 RH |
812 | TRANS_FEAT(SXTW, aa64_sve, gen_gvec_ool_arg_zpz, |
813 | a->esz == 3 ? gen_helper_sve_sxtw_d : NULL, a, 0) | |
814 | TRANS_FEAT(UXTW, aa64_sve, gen_gvec_ool_arg_zpz, | |
815 | a->esz == 3 ? gen_helper_sve_uxtw_d : NULL, a, 0) | |
afac6d04 | 816 | |
047cec97 RH |
817 | /* |
818 | *** SVE Integer Reduction Group | |
819 | */ | |
820 | ||
821 | typedef void gen_helper_gvec_reduc(TCGv_i64, TCGv_ptr, TCGv_ptr, TCGv_i32); | |
822 | static bool do_vpz_ool(DisasContext *s, arg_rpr_esz *a, | |
823 | gen_helper_gvec_reduc *fn) | |
824 | { | |
825 | unsigned vsz = vec_full_reg_size(s); | |
826 | TCGv_ptr t_zn, t_pg; | |
827 | TCGv_i32 desc; | |
828 | TCGv_i64 temp; | |
829 | ||
830 | if (fn == NULL) { | |
831 | return false; | |
832 | } | |
833 | if (!sve_access_check(s)) { | |
834 | return true; | |
835 | } | |
836 | ||
c6a59b55 | 837 | desc = tcg_constant_i32(simd_desc(vsz, vsz, 0)); |
047cec97 RH |
838 | temp = tcg_temp_new_i64(); |
839 | t_zn = tcg_temp_new_ptr(); | |
840 | t_pg = tcg_temp_new_ptr(); | |
841 | ||
842 | tcg_gen_addi_ptr(t_zn, cpu_env, vec_full_reg_offset(s, a->rn)); | |
843 | tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, a->pg)); | |
844 | fn(temp, t_zn, t_pg, desc); | |
845 | tcg_temp_free_ptr(t_zn); | |
846 | tcg_temp_free_ptr(t_pg); | |
047cec97 RH |
847 | |
848 | write_fp_dreg(s, a->rd, temp); | |
849 | tcg_temp_free_i64(temp); | |
850 | return true; | |
851 | } | |
852 | ||
853 | #define DO_VPZ(NAME, name) \ | |
3a7be554 | 854 | static bool trans_##NAME(DisasContext *s, arg_rpr_esz *a) \ |
047cec97 RH |
855 | { \ |
856 | static gen_helper_gvec_reduc * const fns[4] = { \ | |
857 | gen_helper_sve_##name##_b, gen_helper_sve_##name##_h, \ | |
858 | gen_helper_sve_##name##_s, gen_helper_sve_##name##_d, \ | |
859 | }; \ | |
860 | return do_vpz_ool(s, a, fns[a->esz]); \ | |
861 | } | |
862 | ||
863 | DO_VPZ(ORV, orv) | |
864 | DO_VPZ(ANDV, andv) | |
865 | DO_VPZ(EORV, eorv) | |
866 | ||
867 | DO_VPZ(UADDV, uaddv) | |
868 | DO_VPZ(SMAXV, smaxv) | |
869 | DO_VPZ(UMAXV, umaxv) | |
870 | DO_VPZ(SMINV, sminv) | |
871 | DO_VPZ(UMINV, uminv) | |
872 | ||
3a7be554 | 873 | static bool trans_SADDV(DisasContext *s, arg_rpr_esz *a) |
047cec97 RH |
874 | { |
875 | static gen_helper_gvec_reduc * const fns[4] = { | |
876 | gen_helper_sve_saddv_b, gen_helper_sve_saddv_h, | |
877 | gen_helper_sve_saddv_s, NULL | |
878 | }; | |
879 | return do_vpz_ool(s, a, fns[a->esz]); | |
880 | } | |
881 | ||
882 | #undef DO_VPZ | |
883 | ||
ccd841c3 RH |
884 | /* |
885 | *** SVE Shift by Immediate - Predicated Group | |
886 | */ | |
887 | ||
60245996 RH |
888 | /* |
889 | * Copy Zn into Zd, storing zeros into inactive elements. | |
890 | * If invert, store zeros into the active elements. | |
ccd841c3 | 891 | */ |
60245996 RH |
892 | static bool do_movz_zpz(DisasContext *s, int rd, int rn, int pg, |
893 | int esz, bool invert) | |
ccd841c3 | 894 | { |
60245996 RH |
895 | static gen_helper_gvec_3 * const fns[4] = { |
896 | gen_helper_sve_movz_b, gen_helper_sve_movz_h, | |
897 | gen_helper_sve_movz_s, gen_helper_sve_movz_d, | |
ccd841c3 | 898 | }; |
8fb27a21 | 899 | return gen_gvec_ool_zzp(s, fns[esz], rd, rn, pg, invert); |
ccd841c3 RH |
900 | } |
901 | ||
3a7be554 | 902 | static bool trans_ASR_zpzi(DisasContext *s, arg_rpri_esz *a) |
ccd841c3 RH |
903 | { |
904 | static gen_helper_gvec_3 * const fns[4] = { | |
905 | gen_helper_sve_asr_zpzi_b, gen_helper_sve_asr_zpzi_h, | |
906 | gen_helper_sve_asr_zpzi_s, gen_helper_sve_asr_zpzi_d, | |
907 | }; | |
908 | if (a->esz < 0) { | |
909 | /* Invalid tsz encoding -- see tszimm_esz. */ | |
910 | return false; | |
911 | } | |
912 | /* Shift by element size is architecturally valid. For | |
913 | arithmetic right-shift, it's the same as by one less. */ | |
914 | a->imm = MIN(a->imm, (8 << a->esz) - 1); | |
afa2529c | 915 | return gen_gvec_ool_arg_zpzi(s, fns[a->esz], a); |
ccd841c3 RH |
916 | } |
917 | ||
3a7be554 | 918 | static bool trans_LSR_zpzi(DisasContext *s, arg_rpri_esz *a) |
ccd841c3 RH |
919 | { |
920 | static gen_helper_gvec_3 * const fns[4] = { | |
921 | gen_helper_sve_lsr_zpzi_b, gen_helper_sve_lsr_zpzi_h, | |
922 | gen_helper_sve_lsr_zpzi_s, gen_helper_sve_lsr_zpzi_d, | |
923 | }; | |
924 | if (a->esz < 0) { | |
925 | return false; | |
926 | } | |
927 | /* Shift by element size is architecturally valid. | |
928 | For logical shifts, it is a zeroing operation. */ | |
929 | if (a->imm >= (8 << a->esz)) { | |
60245996 | 930 | return do_movz_zpz(s, a->rd, a->rd, a->pg, a->esz, true); |
ccd841c3 | 931 | } else { |
afa2529c | 932 | return gen_gvec_ool_arg_zpzi(s, fns[a->esz], a); |
ccd841c3 RH |
933 | } |
934 | } | |
935 | ||
3a7be554 | 936 | static bool trans_LSL_zpzi(DisasContext *s, arg_rpri_esz *a) |
ccd841c3 RH |
937 | { |
938 | static gen_helper_gvec_3 * const fns[4] = { | |
939 | gen_helper_sve_lsl_zpzi_b, gen_helper_sve_lsl_zpzi_h, | |
940 | gen_helper_sve_lsl_zpzi_s, gen_helper_sve_lsl_zpzi_d, | |
941 | }; | |
942 | if (a->esz < 0) { | |
943 | return false; | |
944 | } | |
945 | /* Shift by element size is architecturally valid. | |
946 | For logical shifts, it is a zeroing operation. */ | |
947 | if (a->imm >= (8 << a->esz)) { | |
60245996 | 948 | return do_movz_zpz(s, a->rd, a->rd, a->pg, a->esz, true); |
ccd841c3 | 949 | } else { |
afa2529c | 950 | return gen_gvec_ool_arg_zpzi(s, fns[a->esz], a); |
ccd841c3 RH |
951 | } |
952 | } | |
953 | ||
3a7be554 | 954 | static bool trans_ASRD(DisasContext *s, arg_rpri_esz *a) |
ccd841c3 RH |
955 | { |
956 | static gen_helper_gvec_3 * const fns[4] = { | |
957 | gen_helper_sve_asrd_b, gen_helper_sve_asrd_h, | |
958 | gen_helper_sve_asrd_s, gen_helper_sve_asrd_d, | |
959 | }; | |
960 | if (a->esz < 0) { | |
961 | return false; | |
962 | } | |
963 | /* Shift by element size is architecturally valid. For arithmetic | |
964 | right shift for division, it is a zeroing operation. */ | |
965 | if (a->imm >= (8 << a->esz)) { | |
60245996 | 966 | return do_movz_zpz(s, a->rd, a->rd, a->pg, a->esz, true); |
ccd841c3 | 967 | } else { |
afa2529c | 968 | return gen_gvec_ool_arg_zpzi(s, fns[a->esz], a); |
ccd841c3 RH |
969 | } |
970 | } | |
971 | ||
4df37e41 RH |
972 | static gen_helper_gvec_3 * const sqshl_zpzi_fns[4] = { |
973 | gen_helper_sve2_sqshl_zpzi_b, gen_helper_sve2_sqshl_zpzi_h, | |
974 | gen_helper_sve2_sqshl_zpzi_s, gen_helper_sve2_sqshl_zpzi_d, | |
975 | }; | |
976 | TRANS_FEAT(SQSHL_zpzi, aa64_sve2, gen_gvec_ool_arg_zpzi, | |
977 | a->esz < 0 ? NULL : sqshl_zpzi_fns[a->esz], a) | |
a5421b54 | 978 | |
4df37e41 RH |
979 | static gen_helper_gvec_3 * const uqshl_zpzi_fns[4] = { |
980 | gen_helper_sve2_uqshl_zpzi_b, gen_helper_sve2_uqshl_zpzi_h, | |
981 | gen_helper_sve2_uqshl_zpzi_s, gen_helper_sve2_uqshl_zpzi_d, | |
982 | }; | |
983 | TRANS_FEAT(UQSHL_zpzi, aa64_sve2, gen_gvec_ool_arg_zpzi, | |
984 | a->esz < 0 ? NULL : uqshl_zpzi_fns[a->esz], a) | |
a5421b54 | 985 | |
4df37e41 RH |
986 | static gen_helper_gvec_3 * const srshr_fns[4] = { |
987 | gen_helper_sve2_srshr_b, gen_helper_sve2_srshr_h, | |
988 | gen_helper_sve2_srshr_s, gen_helper_sve2_srshr_d, | |
989 | }; | |
990 | TRANS_FEAT(SRSHR, aa64_sve2, gen_gvec_ool_arg_zpzi, | |
991 | a->esz < 0 ? NULL : srshr_fns[a->esz], a) | |
a5421b54 | 992 | |
4df37e41 RH |
993 | static gen_helper_gvec_3 * const urshr_fns[4] = { |
994 | gen_helper_sve2_urshr_b, gen_helper_sve2_urshr_h, | |
995 | gen_helper_sve2_urshr_s, gen_helper_sve2_urshr_d, | |
996 | }; | |
997 | TRANS_FEAT(URSHR, aa64_sve2, gen_gvec_ool_arg_zpzi, | |
998 | a->esz < 0 ? NULL : urshr_fns[a->esz], a) | |
a5421b54 | 999 | |
4df37e41 RH |
1000 | static gen_helper_gvec_3 * const sqshlu_fns[4] = { |
1001 | gen_helper_sve2_sqshlu_b, gen_helper_sve2_sqshlu_h, | |
1002 | gen_helper_sve2_sqshlu_s, gen_helper_sve2_sqshlu_d, | |
1003 | }; | |
1004 | TRANS_FEAT(SQSHLU, aa64_sve2, gen_gvec_ool_arg_zpzi, | |
1005 | a->esz < 0 ? NULL : sqshlu_fns[a->esz], a) | |
a5421b54 | 1006 | |
fe7f8dfb RH |
1007 | /* |
1008 | *** SVE Bitwise Shift - Predicated Group | |
1009 | */ | |
1010 | ||
1011 | #define DO_ZPZW(NAME, name) \ | |
8e7acb24 | 1012 | static gen_helper_gvec_4 * const name##_zpzw_fns[4] = { \ |
fe7f8dfb | 1013 | gen_helper_sve_##name##_zpzw_b, gen_helper_sve_##name##_zpzw_h, \ |
8e7acb24 | 1014 | gen_helper_sve_##name##_zpzw_s, NULL \ |
fe7f8dfb | 1015 | }; \ |
8e7acb24 RH |
1016 | TRANS_FEAT(NAME##_zpzw, aa64_sve, gen_gvec_ool_arg_zpzz, \ |
1017 | a->esz < 0 ? NULL : name##_zpzw_fns[a->esz], a, 0) | |
fe7f8dfb RH |
1018 | |
1019 | DO_ZPZW(ASR, asr) | |
1020 | DO_ZPZW(LSR, lsr) | |
1021 | DO_ZPZW(LSL, lsl) | |
1022 | ||
1023 | #undef DO_ZPZW | |
1024 | ||
d9d78dcc RH |
1025 | /* |
1026 | *** SVE Bitwise Shift - Unpredicated Group | |
1027 | */ | |
1028 | ||
1029 | static bool do_shift_imm(DisasContext *s, arg_rri_esz *a, bool asr, | |
1030 | void (*gvec_fn)(unsigned, uint32_t, uint32_t, | |
1031 | int64_t, uint32_t, uint32_t)) | |
1032 | { | |
1033 | if (a->esz < 0) { | |
1034 | /* Invalid tsz encoding -- see tszimm_esz. */ | |
1035 | return false; | |
1036 | } | |
1037 | if (sve_access_check(s)) { | |
1038 | unsigned vsz = vec_full_reg_size(s); | |
1039 | /* Shift by element size is architecturally valid. For | |
1040 | arithmetic right-shift, it's the same as by one less. | |
1041 | Otherwise it is a zeroing operation. */ | |
1042 | if (a->imm >= 8 << a->esz) { | |
1043 | if (asr) { | |
1044 | a->imm = (8 << a->esz) - 1; | |
1045 | } else { | |
1046 | do_dupi_z(s, a->rd, 0); | |
1047 | return true; | |
1048 | } | |
1049 | } | |
1050 | gvec_fn(a->esz, vec_full_reg_offset(s, a->rd), | |
1051 | vec_full_reg_offset(s, a->rn), a->imm, vsz, vsz); | |
1052 | } | |
1053 | return true; | |
1054 | } | |
1055 | ||
3a7be554 | 1056 | static bool trans_ASR_zzi(DisasContext *s, arg_rri_esz *a) |
d9d78dcc RH |
1057 | { |
1058 | return do_shift_imm(s, a, true, tcg_gen_gvec_sari); | |
1059 | } | |
1060 | ||
3a7be554 | 1061 | static bool trans_LSR_zzi(DisasContext *s, arg_rri_esz *a) |
d9d78dcc RH |
1062 | { |
1063 | return do_shift_imm(s, a, false, tcg_gen_gvec_shri); | |
1064 | } | |
1065 | ||
3a7be554 | 1066 | static bool trans_LSL_zzi(DisasContext *s, arg_rri_esz *a) |
d9d78dcc RH |
1067 | { |
1068 | return do_shift_imm(s, a, false, tcg_gen_gvec_shli); | |
1069 | } | |
1070 | ||
d9d78dcc | 1071 | #define DO_ZZW(NAME, name) \ |
32e2ad65 | 1072 | static gen_helper_gvec_3 * const name##_zzw_fns[4] = { \ |
d9d78dcc RH |
1073 | gen_helper_sve_##name##_zzw_b, gen_helper_sve_##name##_zzw_h, \ |
1074 | gen_helper_sve_##name##_zzw_s, NULL \ | |
1075 | }; \ | |
32e2ad65 RH |
1076 | TRANS_FEAT(NAME, aa64_sve, gen_gvec_ool_arg_zzz, \ |
1077 | name##_zzw_fns[a->esz], a, 0) | |
d9d78dcc | 1078 | |
32e2ad65 RH |
1079 | DO_ZZW(ASR_zzw, asr) |
1080 | DO_ZZW(LSR_zzw, lsr) | |
1081 | DO_ZZW(LSL_zzw, lsl) | |
d9d78dcc RH |
1082 | |
1083 | #undef DO_ZZW | |
1084 | ||
96a36e4a RH |
1085 | /* |
1086 | *** SVE Integer Multiply-Add Group | |
1087 | */ | |
1088 | ||
1089 | static bool do_zpzzz_ool(DisasContext *s, arg_rprrr_esz *a, | |
1090 | gen_helper_gvec_5 *fn) | |
1091 | { | |
1092 | if (sve_access_check(s)) { | |
1093 | unsigned vsz = vec_full_reg_size(s); | |
1094 | tcg_gen_gvec_5_ool(vec_full_reg_offset(s, a->rd), | |
1095 | vec_full_reg_offset(s, a->ra), | |
1096 | vec_full_reg_offset(s, a->rn), | |
1097 | vec_full_reg_offset(s, a->rm), | |
1098 | pred_full_reg_offset(s, a->pg), | |
1099 | vsz, vsz, 0, fn); | |
1100 | } | |
1101 | return true; | |
1102 | } | |
1103 | ||
1104 | #define DO_ZPZZZ(NAME, name) \ | |
3a7be554 | 1105 | static bool trans_##NAME(DisasContext *s, arg_rprrr_esz *a) \ |
96a36e4a RH |
1106 | { \ |
1107 | static gen_helper_gvec_5 * const fns[4] = { \ | |
1108 | gen_helper_sve_##name##_b, gen_helper_sve_##name##_h, \ | |
1109 | gen_helper_sve_##name##_s, gen_helper_sve_##name##_d, \ | |
1110 | }; \ | |
1111 | return do_zpzzz_ool(s, a, fns[a->esz]); \ | |
1112 | } | |
1113 | ||
1114 | DO_ZPZZZ(MLA, mla) | |
1115 | DO_ZPZZZ(MLS, mls) | |
1116 | ||
1117 | #undef DO_ZPZZZ | |
1118 | ||
9a56c9c3 RH |
1119 | /* |
1120 | *** SVE Index Generation Group | |
1121 | */ | |
1122 | ||
1123 | static void do_index(DisasContext *s, int esz, int rd, | |
1124 | TCGv_i64 start, TCGv_i64 incr) | |
1125 | { | |
1126 | unsigned vsz = vec_full_reg_size(s); | |
c6a59b55 | 1127 | TCGv_i32 desc = tcg_constant_i32(simd_desc(vsz, vsz, 0)); |
9a56c9c3 RH |
1128 | TCGv_ptr t_zd = tcg_temp_new_ptr(); |
1129 | ||
1130 | tcg_gen_addi_ptr(t_zd, cpu_env, vec_full_reg_offset(s, rd)); | |
1131 | if (esz == 3) { | |
1132 | gen_helper_sve_index_d(t_zd, start, incr, desc); | |
1133 | } else { | |
1134 | typedef void index_fn(TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32); | |
1135 | static index_fn * const fns[3] = { | |
1136 | gen_helper_sve_index_b, | |
1137 | gen_helper_sve_index_h, | |
1138 | gen_helper_sve_index_s, | |
1139 | }; | |
1140 | TCGv_i32 s32 = tcg_temp_new_i32(); | |
1141 | TCGv_i32 i32 = tcg_temp_new_i32(); | |
1142 | ||
1143 | tcg_gen_extrl_i64_i32(s32, start); | |
1144 | tcg_gen_extrl_i64_i32(i32, incr); | |
1145 | fns[esz](t_zd, s32, i32, desc); | |
1146 | ||
1147 | tcg_temp_free_i32(s32); | |
1148 | tcg_temp_free_i32(i32); | |
1149 | } | |
1150 | tcg_temp_free_ptr(t_zd); | |
9a56c9c3 RH |
1151 | } |
1152 | ||
3a7be554 | 1153 | static bool trans_INDEX_ii(DisasContext *s, arg_INDEX_ii *a) |
9a56c9c3 RH |
1154 | { |
1155 | if (sve_access_check(s)) { | |
b0c3aece RH |
1156 | TCGv_i64 start = tcg_constant_i64(a->imm1); |
1157 | TCGv_i64 incr = tcg_constant_i64(a->imm2); | |
9a56c9c3 | 1158 | do_index(s, a->esz, a->rd, start, incr); |
9a56c9c3 RH |
1159 | } |
1160 | return true; | |
1161 | } | |
1162 | ||
3a7be554 | 1163 | static bool trans_INDEX_ir(DisasContext *s, arg_INDEX_ir *a) |
9a56c9c3 RH |
1164 | { |
1165 | if (sve_access_check(s)) { | |
b0c3aece | 1166 | TCGv_i64 start = tcg_constant_i64(a->imm); |
9a56c9c3 RH |
1167 | TCGv_i64 incr = cpu_reg(s, a->rm); |
1168 | do_index(s, a->esz, a->rd, start, incr); | |
9a56c9c3 RH |
1169 | } |
1170 | return true; | |
1171 | } | |
1172 | ||
3a7be554 | 1173 | static bool trans_INDEX_ri(DisasContext *s, arg_INDEX_ri *a) |
9a56c9c3 RH |
1174 | { |
1175 | if (sve_access_check(s)) { | |
1176 | TCGv_i64 start = cpu_reg(s, a->rn); | |
b0c3aece | 1177 | TCGv_i64 incr = tcg_constant_i64(a->imm); |
9a56c9c3 | 1178 | do_index(s, a->esz, a->rd, start, incr); |
9a56c9c3 RH |
1179 | } |
1180 | return true; | |
1181 | } | |
1182 | ||
3a7be554 | 1183 | static bool trans_INDEX_rr(DisasContext *s, arg_INDEX_rr *a) |
9a56c9c3 RH |
1184 | { |
1185 | if (sve_access_check(s)) { | |
1186 | TCGv_i64 start = cpu_reg(s, a->rn); | |
1187 | TCGv_i64 incr = cpu_reg(s, a->rm); | |
1188 | do_index(s, a->esz, a->rd, start, incr); | |
1189 | } | |
1190 | return true; | |
1191 | } | |
1192 | ||
96f922cc RH |
1193 | /* |
1194 | *** SVE Stack Allocation Group | |
1195 | */ | |
1196 | ||
3a7be554 | 1197 | static bool trans_ADDVL(DisasContext *s, arg_ADDVL *a) |
96f922cc | 1198 | { |
5de56742 AC |
1199 | if (sve_access_check(s)) { |
1200 | TCGv_i64 rd = cpu_reg_sp(s, a->rd); | |
1201 | TCGv_i64 rn = cpu_reg_sp(s, a->rn); | |
1202 | tcg_gen_addi_i64(rd, rn, a->imm * vec_full_reg_size(s)); | |
1203 | } | |
96f922cc RH |
1204 | return true; |
1205 | } | |
1206 | ||
3a7be554 | 1207 | static bool trans_ADDPL(DisasContext *s, arg_ADDPL *a) |
96f922cc | 1208 | { |
5de56742 AC |
1209 | if (sve_access_check(s)) { |
1210 | TCGv_i64 rd = cpu_reg_sp(s, a->rd); | |
1211 | TCGv_i64 rn = cpu_reg_sp(s, a->rn); | |
1212 | tcg_gen_addi_i64(rd, rn, a->imm * pred_full_reg_size(s)); | |
1213 | } | |
96f922cc RH |
1214 | return true; |
1215 | } | |
1216 | ||
3a7be554 | 1217 | static bool trans_RDVL(DisasContext *s, arg_RDVL *a) |
96f922cc | 1218 | { |
5de56742 AC |
1219 | if (sve_access_check(s)) { |
1220 | TCGv_i64 reg = cpu_reg(s, a->rd); | |
1221 | tcg_gen_movi_i64(reg, a->imm * vec_full_reg_size(s)); | |
1222 | } | |
96f922cc RH |
1223 | return true; |
1224 | } | |
1225 | ||
4b242d9c RH |
1226 | /* |
1227 | *** SVE Compute Vector Address Group | |
1228 | */ | |
1229 | ||
1230 | static bool do_adr(DisasContext *s, arg_rrri *a, gen_helper_gvec_3 *fn) | |
1231 | { | |
913a8a00 | 1232 | return gen_gvec_ool_zzz(s, fn, a->rd, a->rn, a->rm, a->imm); |
4b242d9c RH |
1233 | } |
1234 | ||
3a7be554 | 1235 | static bool trans_ADR_p32(DisasContext *s, arg_rrri *a) |
4b242d9c RH |
1236 | { |
1237 | return do_adr(s, a, gen_helper_sve_adr_p32); | |
1238 | } | |
1239 | ||
3a7be554 | 1240 | static bool trans_ADR_p64(DisasContext *s, arg_rrri *a) |
4b242d9c RH |
1241 | { |
1242 | return do_adr(s, a, gen_helper_sve_adr_p64); | |
1243 | } | |
1244 | ||
3a7be554 | 1245 | static bool trans_ADR_s32(DisasContext *s, arg_rrri *a) |
4b242d9c RH |
1246 | { |
1247 | return do_adr(s, a, gen_helper_sve_adr_s32); | |
1248 | } | |
1249 | ||
3a7be554 | 1250 | static bool trans_ADR_u32(DisasContext *s, arg_rrri *a) |
4b242d9c RH |
1251 | { |
1252 | return do_adr(s, a, gen_helper_sve_adr_u32); | |
1253 | } | |
1254 | ||
0762cd42 RH |
1255 | /* |
1256 | *** SVE Integer Misc - Unpredicated Group | |
1257 | */ | |
1258 | ||
0ea3cdbf RH |
1259 | static gen_helper_gvec_2 * const fexpa_fns[4] = { |
1260 | NULL, gen_helper_sve_fexpa_h, | |
1261 | gen_helper_sve_fexpa_s, gen_helper_sve_fexpa_d, | |
1262 | }; | |
1263 | TRANS_FEAT(FEXPA, aa64_sve, gen_gvec_ool_zz, | |
1264 | fexpa_fns[a->esz], a->rd, a->rn, 0) | |
0762cd42 | 1265 | |
32e2ad65 RH |
1266 | static gen_helper_gvec_3 * const ftssel_fns[4] = { |
1267 | NULL, gen_helper_sve_ftssel_h, | |
1268 | gen_helper_sve_ftssel_s, gen_helper_sve_ftssel_d, | |
1269 | }; | |
1270 | TRANS_FEAT(FTSSEL, aa64_sve, gen_gvec_ool_arg_zzz, ftssel_fns[a->esz], a, 0) | |
a1f233f2 | 1271 | |
516e246a RH |
1272 | /* |
1273 | *** SVE Predicate Logical Operations Group | |
1274 | */ | |
1275 | ||
1276 | static bool do_pppp_flags(DisasContext *s, arg_rprr_s *a, | |
1277 | const GVecGen4 *gvec_op) | |
1278 | { | |
1279 | if (!sve_access_check(s)) { | |
1280 | return true; | |
1281 | } | |
1282 | ||
1283 | unsigned psz = pred_gvec_reg_size(s); | |
1284 | int dofs = pred_full_reg_offset(s, a->rd); | |
1285 | int nofs = pred_full_reg_offset(s, a->rn); | |
1286 | int mofs = pred_full_reg_offset(s, a->rm); | |
1287 | int gofs = pred_full_reg_offset(s, a->pg); | |
1288 | ||
dd81a8d7 RH |
1289 | if (!a->s) { |
1290 | tcg_gen_gvec_4(dofs, nofs, mofs, gofs, psz, psz, gvec_op); | |
1291 | return true; | |
1292 | } | |
1293 | ||
516e246a RH |
1294 | if (psz == 8) { |
1295 | /* Do the operation and the flags generation in temps. */ | |
1296 | TCGv_i64 pd = tcg_temp_new_i64(); | |
1297 | TCGv_i64 pn = tcg_temp_new_i64(); | |
1298 | TCGv_i64 pm = tcg_temp_new_i64(); | |
1299 | TCGv_i64 pg = tcg_temp_new_i64(); | |
1300 | ||
1301 | tcg_gen_ld_i64(pn, cpu_env, nofs); | |
1302 | tcg_gen_ld_i64(pm, cpu_env, mofs); | |
1303 | tcg_gen_ld_i64(pg, cpu_env, gofs); | |
1304 | ||
1305 | gvec_op->fni8(pd, pn, pm, pg); | |
1306 | tcg_gen_st_i64(pd, cpu_env, dofs); | |
1307 | ||
1308 | do_predtest1(pd, pg); | |
1309 | ||
1310 | tcg_temp_free_i64(pd); | |
1311 | tcg_temp_free_i64(pn); | |
1312 | tcg_temp_free_i64(pm); | |
1313 | tcg_temp_free_i64(pg); | |
1314 | } else { | |
1315 | /* The operation and flags generation is large. The computation | |
1316 | * of the flags depends on the original contents of the guarding | |
1317 | * predicate. If the destination overwrites the guarding predicate, | |
1318 | * then the easiest way to get this right is to save a copy. | |
1319 | */ | |
1320 | int tofs = gofs; | |
1321 | if (a->rd == a->pg) { | |
1322 | tofs = offsetof(CPUARMState, vfp.preg_tmp); | |
1323 | tcg_gen_gvec_mov(0, tofs, gofs, psz, psz); | |
1324 | } | |
1325 | ||
1326 | tcg_gen_gvec_4(dofs, nofs, mofs, gofs, psz, psz, gvec_op); | |
1327 | do_predtest(s, dofs, tofs, psz / 8); | |
1328 | } | |
1329 | return true; | |
1330 | } | |
1331 | ||
1332 | static void gen_and_pg_i64(TCGv_i64 pd, TCGv_i64 pn, TCGv_i64 pm, TCGv_i64 pg) | |
1333 | { | |
1334 | tcg_gen_and_i64(pd, pn, pm); | |
1335 | tcg_gen_and_i64(pd, pd, pg); | |
1336 | } | |
1337 | ||
1338 | static void gen_and_pg_vec(unsigned vece, TCGv_vec pd, TCGv_vec pn, | |
1339 | TCGv_vec pm, TCGv_vec pg) | |
1340 | { | |
1341 | tcg_gen_and_vec(vece, pd, pn, pm); | |
1342 | tcg_gen_and_vec(vece, pd, pd, pg); | |
1343 | } | |
1344 | ||
3a7be554 | 1345 | static bool trans_AND_pppp(DisasContext *s, arg_rprr_s *a) |
516e246a RH |
1346 | { |
1347 | static const GVecGen4 op = { | |
1348 | .fni8 = gen_and_pg_i64, | |
1349 | .fniv = gen_and_pg_vec, | |
1350 | .fno = gen_helper_sve_and_pppp, | |
1351 | .prefer_i64 = TCG_TARGET_REG_BITS == 64, | |
1352 | }; | |
dd81a8d7 RH |
1353 | |
1354 | if (!a->s) { | |
1355 | if (!sve_access_check(s)) { | |
1356 | return true; | |
1357 | } | |
1358 | if (a->rn == a->rm) { | |
1359 | if (a->pg == a->rn) { | |
1360 | do_mov_p(s, a->rd, a->rn); | |
1361 | } else { | |
1362 | gen_gvec_fn_ppp(s, tcg_gen_gvec_and, a->rd, a->rn, a->pg); | |
1363 | } | |
1364 | return true; | |
1365 | } else if (a->pg == a->rn || a->pg == a->rm) { | |
1366 | gen_gvec_fn_ppp(s, tcg_gen_gvec_and, a->rd, a->rn, a->rm); | |
1367 | return true; | |
516e246a | 1368 | } |
516e246a | 1369 | } |
dd81a8d7 | 1370 | return do_pppp_flags(s, a, &op); |
516e246a RH |
1371 | } |
1372 | ||
1373 | static void gen_bic_pg_i64(TCGv_i64 pd, TCGv_i64 pn, TCGv_i64 pm, TCGv_i64 pg) | |
1374 | { | |
1375 | tcg_gen_andc_i64(pd, pn, pm); | |
1376 | tcg_gen_and_i64(pd, pd, pg); | |
1377 | } | |
1378 | ||
1379 | static void gen_bic_pg_vec(unsigned vece, TCGv_vec pd, TCGv_vec pn, | |
1380 | TCGv_vec pm, TCGv_vec pg) | |
1381 | { | |
1382 | tcg_gen_andc_vec(vece, pd, pn, pm); | |
1383 | tcg_gen_and_vec(vece, pd, pd, pg); | |
1384 | } | |
1385 | ||
3a7be554 | 1386 | static bool trans_BIC_pppp(DisasContext *s, arg_rprr_s *a) |
516e246a RH |
1387 | { |
1388 | static const GVecGen4 op = { | |
1389 | .fni8 = gen_bic_pg_i64, | |
1390 | .fniv = gen_bic_pg_vec, | |
1391 | .fno = gen_helper_sve_bic_pppp, | |
1392 | .prefer_i64 = TCG_TARGET_REG_BITS == 64, | |
1393 | }; | |
dd81a8d7 RH |
1394 | |
1395 | if (!a->s && a->pg == a->rn) { | |
1396 | if (sve_access_check(s)) { | |
1397 | gen_gvec_fn_ppp(s, tcg_gen_gvec_andc, a->rd, a->rn, a->rm); | |
1398 | } | |
1399 | return true; | |
516e246a | 1400 | } |
dd81a8d7 | 1401 | return do_pppp_flags(s, a, &op); |
516e246a RH |
1402 | } |
1403 | ||
1404 | static void gen_eor_pg_i64(TCGv_i64 pd, TCGv_i64 pn, TCGv_i64 pm, TCGv_i64 pg) | |
1405 | { | |
1406 | tcg_gen_xor_i64(pd, pn, pm); | |
1407 | tcg_gen_and_i64(pd, pd, pg); | |
1408 | } | |
1409 | ||
1410 | static void gen_eor_pg_vec(unsigned vece, TCGv_vec pd, TCGv_vec pn, | |
1411 | TCGv_vec pm, TCGv_vec pg) | |
1412 | { | |
1413 | tcg_gen_xor_vec(vece, pd, pn, pm); | |
1414 | tcg_gen_and_vec(vece, pd, pd, pg); | |
1415 | } | |
1416 | ||
3a7be554 | 1417 | static bool trans_EOR_pppp(DisasContext *s, arg_rprr_s *a) |
516e246a RH |
1418 | { |
1419 | static const GVecGen4 op = { | |
1420 | .fni8 = gen_eor_pg_i64, | |
1421 | .fniv = gen_eor_pg_vec, | |
1422 | .fno = gen_helper_sve_eor_pppp, | |
1423 | .prefer_i64 = TCG_TARGET_REG_BITS == 64, | |
1424 | }; | |
dd81a8d7 | 1425 | return do_pppp_flags(s, a, &op); |
516e246a RH |
1426 | } |
1427 | ||
3a7be554 | 1428 | static bool trans_SEL_pppp(DisasContext *s, arg_rprr_s *a) |
516e246a | 1429 | { |
516e246a RH |
1430 | if (a->s) { |
1431 | return false; | |
516e246a | 1432 | } |
d4bc6232 RH |
1433 | if (sve_access_check(s)) { |
1434 | unsigned psz = pred_gvec_reg_size(s); | |
1435 | tcg_gen_gvec_bitsel(MO_8, pred_full_reg_offset(s, a->rd), | |
1436 | pred_full_reg_offset(s, a->pg), | |
1437 | pred_full_reg_offset(s, a->rn), | |
1438 | pred_full_reg_offset(s, a->rm), psz, psz); | |
1439 | } | |
1440 | return true; | |
516e246a RH |
1441 | } |
1442 | ||
1443 | static void gen_orr_pg_i64(TCGv_i64 pd, TCGv_i64 pn, TCGv_i64 pm, TCGv_i64 pg) | |
1444 | { | |
1445 | tcg_gen_or_i64(pd, pn, pm); | |
1446 | tcg_gen_and_i64(pd, pd, pg); | |
1447 | } | |
1448 | ||
1449 | static void gen_orr_pg_vec(unsigned vece, TCGv_vec pd, TCGv_vec pn, | |
1450 | TCGv_vec pm, TCGv_vec pg) | |
1451 | { | |
1452 | tcg_gen_or_vec(vece, pd, pn, pm); | |
1453 | tcg_gen_and_vec(vece, pd, pd, pg); | |
1454 | } | |
1455 | ||
3a7be554 | 1456 | static bool trans_ORR_pppp(DisasContext *s, arg_rprr_s *a) |
516e246a RH |
1457 | { |
1458 | static const GVecGen4 op = { | |
1459 | .fni8 = gen_orr_pg_i64, | |
1460 | .fniv = gen_orr_pg_vec, | |
1461 | .fno = gen_helper_sve_orr_pppp, | |
1462 | .prefer_i64 = TCG_TARGET_REG_BITS == 64, | |
1463 | }; | |
dd81a8d7 RH |
1464 | |
1465 | if (!a->s && a->pg == a->rn && a->rn == a->rm) { | |
516e246a | 1466 | return do_mov_p(s, a->rd, a->rn); |
516e246a | 1467 | } |
dd81a8d7 | 1468 | return do_pppp_flags(s, a, &op); |
516e246a RH |
1469 | } |
1470 | ||
1471 | static void gen_orn_pg_i64(TCGv_i64 pd, TCGv_i64 pn, TCGv_i64 pm, TCGv_i64 pg) | |
1472 | { | |
1473 | tcg_gen_orc_i64(pd, pn, pm); | |
1474 | tcg_gen_and_i64(pd, pd, pg); | |
1475 | } | |
1476 | ||
1477 | static void gen_orn_pg_vec(unsigned vece, TCGv_vec pd, TCGv_vec pn, | |
1478 | TCGv_vec pm, TCGv_vec pg) | |
1479 | { | |
1480 | tcg_gen_orc_vec(vece, pd, pn, pm); | |
1481 | tcg_gen_and_vec(vece, pd, pd, pg); | |
1482 | } | |
1483 | ||
3a7be554 | 1484 | static bool trans_ORN_pppp(DisasContext *s, arg_rprr_s *a) |
516e246a RH |
1485 | { |
1486 | static const GVecGen4 op = { | |
1487 | .fni8 = gen_orn_pg_i64, | |
1488 | .fniv = gen_orn_pg_vec, | |
1489 | .fno = gen_helper_sve_orn_pppp, | |
1490 | .prefer_i64 = TCG_TARGET_REG_BITS == 64, | |
1491 | }; | |
dd81a8d7 | 1492 | return do_pppp_flags(s, a, &op); |
516e246a RH |
1493 | } |
1494 | ||
1495 | static void gen_nor_pg_i64(TCGv_i64 pd, TCGv_i64 pn, TCGv_i64 pm, TCGv_i64 pg) | |
1496 | { | |
1497 | tcg_gen_or_i64(pd, pn, pm); | |
1498 | tcg_gen_andc_i64(pd, pg, pd); | |
1499 | } | |
1500 | ||
1501 | static void gen_nor_pg_vec(unsigned vece, TCGv_vec pd, TCGv_vec pn, | |
1502 | TCGv_vec pm, TCGv_vec pg) | |
1503 | { | |
1504 | tcg_gen_or_vec(vece, pd, pn, pm); | |
1505 | tcg_gen_andc_vec(vece, pd, pg, pd); | |
1506 | } | |
1507 | ||
3a7be554 | 1508 | static bool trans_NOR_pppp(DisasContext *s, arg_rprr_s *a) |
516e246a RH |
1509 | { |
1510 | static const GVecGen4 op = { | |
1511 | .fni8 = gen_nor_pg_i64, | |
1512 | .fniv = gen_nor_pg_vec, | |
1513 | .fno = gen_helper_sve_nor_pppp, | |
1514 | .prefer_i64 = TCG_TARGET_REG_BITS == 64, | |
1515 | }; | |
dd81a8d7 | 1516 | return do_pppp_flags(s, a, &op); |
516e246a RH |
1517 | } |
1518 | ||
1519 | static void gen_nand_pg_i64(TCGv_i64 pd, TCGv_i64 pn, TCGv_i64 pm, TCGv_i64 pg) | |
1520 | { | |
1521 | tcg_gen_and_i64(pd, pn, pm); | |
1522 | tcg_gen_andc_i64(pd, pg, pd); | |
1523 | } | |
1524 | ||
1525 | static void gen_nand_pg_vec(unsigned vece, TCGv_vec pd, TCGv_vec pn, | |
1526 | TCGv_vec pm, TCGv_vec pg) | |
1527 | { | |
1528 | tcg_gen_and_vec(vece, pd, pn, pm); | |
1529 | tcg_gen_andc_vec(vece, pd, pg, pd); | |
1530 | } | |
1531 | ||
3a7be554 | 1532 | static bool trans_NAND_pppp(DisasContext *s, arg_rprr_s *a) |
516e246a RH |
1533 | { |
1534 | static const GVecGen4 op = { | |
1535 | .fni8 = gen_nand_pg_i64, | |
1536 | .fniv = gen_nand_pg_vec, | |
1537 | .fno = gen_helper_sve_nand_pppp, | |
1538 | .prefer_i64 = TCG_TARGET_REG_BITS == 64, | |
1539 | }; | |
dd81a8d7 | 1540 | return do_pppp_flags(s, a, &op); |
516e246a RH |
1541 | } |
1542 | ||
9e18d7a6 RH |
1543 | /* |
1544 | *** SVE Predicate Misc Group | |
1545 | */ | |
1546 | ||
3a7be554 | 1547 | static bool trans_PTEST(DisasContext *s, arg_PTEST *a) |
9e18d7a6 RH |
1548 | { |
1549 | if (sve_access_check(s)) { | |
1550 | int nofs = pred_full_reg_offset(s, a->rn); | |
1551 | int gofs = pred_full_reg_offset(s, a->pg); | |
1552 | int words = DIV_ROUND_UP(pred_full_reg_size(s), 8); | |
1553 | ||
1554 | if (words == 1) { | |
1555 | TCGv_i64 pn = tcg_temp_new_i64(); | |
1556 | TCGv_i64 pg = tcg_temp_new_i64(); | |
1557 | ||
1558 | tcg_gen_ld_i64(pn, cpu_env, nofs); | |
1559 | tcg_gen_ld_i64(pg, cpu_env, gofs); | |
1560 | do_predtest1(pn, pg); | |
1561 | ||
1562 | tcg_temp_free_i64(pn); | |
1563 | tcg_temp_free_i64(pg); | |
1564 | } else { | |
1565 | do_predtest(s, nofs, gofs, words); | |
1566 | } | |
1567 | } | |
1568 | return true; | |
1569 | } | |
1570 | ||
028e2a7b RH |
1571 | /* See the ARM pseudocode DecodePredCount. */ |
1572 | static unsigned decode_pred_count(unsigned fullsz, int pattern, int esz) | |
1573 | { | |
1574 | unsigned elements = fullsz >> esz; | |
1575 | unsigned bound; | |
1576 | ||
1577 | switch (pattern) { | |
1578 | case 0x0: /* POW2 */ | |
1579 | return pow2floor(elements); | |
1580 | case 0x1: /* VL1 */ | |
1581 | case 0x2: /* VL2 */ | |
1582 | case 0x3: /* VL3 */ | |
1583 | case 0x4: /* VL4 */ | |
1584 | case 0x5: /* VL5 */ | |
1585 | case 0x6: /* VL6 */ | |
1586 | case 0x7: /* VL7 */ | |
1587 | case 0x8: /* VL8 */ | |
1588 | bound = pattern; | |
1589 | break; | |
1590 | case 0x9: /* VL16 */ | |
1591 | case 0xa: /* VL32 */ | |
1592 | case 0xb: /* VL64 */ | |
1593 | case 0xc: /* VL128 */ | |
1594 | case 0xd: /* VL256 */ | |
1595 | bound = 16 << (pattern - 9); | |
1596 | break; | |
1597 | case 0x1d: /* MUL4 */ | |
1598 | return elements - elements % 4; | |
1599 | case 0x1e: /* MUL3 */ | |
1600 | return elements - elements % 3; | |
1601 | case 0x1f: /* ALL */ | |
1602 | return elements; | |
1603 | default: /* #uimm5 */ | |
1604 | return 0; | |
1605 | } | |
1606 | return elements >= bound ? bound : 0; | |
1607 | } | |
1608 | ||
1609 | /* This handles all of the predicate initialization instructions, | |
1610 | * PTRUE, PFALSE, SETFFR. For PFALSE, we will have set PAT == 32 | |
1611 | * so that decode_pred_count returns 0. For SETFFR, we will have | |
1612 | * set RD == 16 == FFR. | |
1613 | */ | |
1614 | static bool do_predset(DisasContext *s, int esz, int rd, int pat, bool setflag) | |
1615 | { | |
1616 | if (!sve_access_check(s)) { | |
1617 | return true; | |
1618 | } | |
1619 | ||
1620 | unsigned fullsz = vec_full_reg_size(s); | |
1621 | unsigned ofs = pred_full_reg_offset(s, rd); | |
1622 | unsigned numelem, setsz, i; | |
1623 | uint64_t word, lastword; | |
1624 | TCGv_i64 t; | |
1625 | ||
1626 | numelem = decode_pred_count(fullsz, pat, esz); | |
1627 | ||
1628 | /* Determine what we must store into each bit, and how many. */ | |
1629 | if (numelem == 0) { | |
1630 | lastword = word = 0; | |
1631 | setsz = fullsz; | |
1632 | } else { | |
1633 | setsz = numelem << esz; | |
1634 | lastword = word = pred_esz_masks[esz]; | |
1635 | if (setsz % 64) { | |
973558a3 | 1636 | lastword &= MAKE_64BIT_MASK(0, setsz % 64); |
028e2a7b RH |
1637 | } |
1638 | } | |
1639 | ||
1640 | t = tcg_temp_new_i64(); | |
1641 | if (fullsz <= 64) { | |
1642 | tcg_gen_movi_i64(t, lastword); | |
1643 | tcg_gen_st_i64(t, cpu_env, ofs); | |
1644 | goto done; | |
1645 | } | |
1646 | ||
1647 | if (word == lastword) { | |
1648 | unsigned maxsz = size_for_gvec(fullsz / 8); | |
1649 | unsigned oprsz = size_for_gvec(setsz / 8); | |
1650 | ||
1651 | if (oprsz * 8 == setsz) { | |
8711e71f | 1652 | tcg_gen_gvec_dup_imm(MO_64, ofs, oprsz, maxsz, word); |
028e2a7b RH |
1653 | goto done; |
1654 | } | |
028e2a7b RH |
1655 | } |
1656 | ||
1657 | setsz /= 8; | |
1658 | fullsz /= 8; | |
1659 | ||
1660 | tcg_gen_movi_i64(t, word); | |
973558a3 | 1661 | for (i = 0; i < QEMU_ALIGN_DOWN(setsz, 8); i += 8) { |
028e2a7b RH |
1662 | tcg_gen_st_i64(t, cpu_env, ofs + i); |
1663 | } | |
1664 | if (lastword != word) { | |
1665 | tcg_gen_movi_i64(t, lastword); | |
1666 | tcg_gen_st_i64(t, cpu_env, ofs + i); | |
1667 | i += 8; | |
1668 | } | |
1669 | if (i < fullsz) { | |
1670 | tcg_gen_movi_i64(t, 0); | |
1671 | for (; i < fullsz; i += 8) { | |
1672 | tcg_gen_st_i64(t, cpu_env, ofs + i); | |
1673 | } | |
1674 | } | |
1675 | ||
1676 | done: | |
1677 | tcg_temp_free_i64(t); | |
1678 | ||
1679 | /* PTRUES */ | |
1680 | if (setflag) { | |
1681 | tcg_gen_movi_i32(cpu_NF, -(word != 0)); | |
1682 | tcg_gen_movi_i32(cpu_CF, word == 0); | |
1683 | tcg_gen_movi_i32(cpu_VF, 0); | |
1684 | tcg_gen_mov_i32(cpu_ZF, cpu_NF); | |
1685 | } | |
1686 | return true; | |
1687 | } | |
1688 | ||
3a7be554 | 1689 | static bool trans_PTRUE(DisasContext *s, arg_PTRUE *a) |
028e2a7b RH |
1690 | { |
1691 | return do_predset(s, a->esz, a->rd, a->pat, a->s); | |
1692 | } | |
1693 | ||
3a7be554 | 1694 | static bool trans_SETFFR(DisasContext *s, arg_SETFFR *a) |
028e2a7b RH |
1695 | { |
1696 | /* Note pat == 31 is #all, to set all elements. */ | |
1697 | return do_predset(s, 0, FFR_PRED_NUM, 31, false); | |
1698 | } | |
1699 | ||
3a7be554 | 1700 | static bool trans_PFALSE(DisasContext *s, arg_PFALSE *a) |
028e2a7b RH |
1701 | { |
1702 | /* Note pat == 32 is #unimp, to set no elements. */ | |
1703 | return do_predset(s, 0, a->rd, 32, false); | |
1704 | } | |
1705 | ||
3a7be554 | 1706 | static bool trans_RDFFR_p(DisasContext *s, arg_RDFFR_p *a) |
028e2a7b RH |
1707 | { |
1708 | /* The path through do_pppp_flags is complicated enough to want to avoid | |
1709 | * duplication. Frob the arguments into the form of a predicated AND. | |
1710 | */ | |
1711 | arg_rprr_s alt_a = { | |
1712 | .rd = a->rd, .pg = a->pg, .s = a->s, | |
1713 | .rn = FFR_PRED_NUM, .rm = FFR_PRED_NUM, | |
1714 | }; | |
3a7be554 | 1715 | return trans_AND_pppp(s, &alt_a); |
028e2a7b RH |
1716 | } |
1717 | ||
3a7be554 | 1718 | static bool trans_RDFFR(DisasContext *s, arg_RDFFR *a) |
028e2a7b RH |
1719 | { |
1720 | return do_mov_p(s, a->rd, FFR_PRED_NUM); | |
1721 | } | |
1722 | ||
3a7be554 | 1723 | static bool trans_WRFFR(DisasContext *s, arg_WRFFR *a) |
028e2a7b RH |
1724 | { |
1725 | return do_mov_p(s, FFR_PRED_NUM, a->rn); | |
1726 | } | |
1727 | ||
1728 | static bool do_pfirst_pnext(DisasContext *s, arg_rr_esz *a, | |
1729 | void (*gen_fn)(TCGv_i32, TCGv_ptr, | |
1730 | TCGv_ptr, TCGv_i32)) | |
1731 | { | |
1732 | if (!sve_access_check(s)) { | |
1733 | return true; | |
1734 | } | |
1735 | ||
1736 | TCGv_ptr t_pd = tcg_temp_new_ptr(); | |
1737 | TCGv_ptr t_pg = tcg_temp_new_ptr(); | |
1738 | TCGv_i32 t; | |
86300b5d | 1739 | unsigned desc = 0; |
028e2a7b | 1740 | |
86300b5d RH |
1741 | desc = FIELD_DP32(desc, PREDDESC, OPRSZ, pred_full_reg_size(s)); |
1742 | desc = FIELD_DP32(desc, PREDDESC, ESZ, a->esz); | |
028e2a7b RH |
1743 | |
1744 | tcg_gen_addi_ptr(t_pd, cpu_env, pred_full_reg_offset(s, a->rd)); | |
1745 | tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, a->rn)); | |
392acacc | 1746 | t = tcg_temp_new_i32(); |
028e2a7b | 1747 | |
392acacc | 1748 | gen_fn(t, t_pd, t_pg, tcg_constant_i32(desc)); |
028e2a7b RH |
1749 | tcg_temp_free_ptr(t_pd); |
1750 | tcg_temp_free_ptr(t_pg); | |
1751 | ||
1752 | do_pred_flags(t); | |
1753 | tcg_temp_free_i32(t); | |
1754 | return true; | |
1755 | } | |
1756 | ||
3a7be554 | 1757 | static bool trans_PFIRST(DisasContext *s, arg_rr_esz *a) |
028e2a7b RH |
1758 | { |
1759 | return do_pfirst_pnext(s, a, gen_helper_sve_pfirst); | |
1760 | } | |
1761 | ||
3a7be554 | 1762 | static bool trans_PNEXT(DisasContext *s, arg_rr_esz *a) |
028e2a7b RH |
1763 | { |
1764 | return do_pfirst_pnext(s, a, gen_helper_sve_pnext); | |
1765 | } | |
1766 | ||
24e82e68 RH |
1767 | /* |
1768 | *** SVE Element Count Group | |
1769 | */ | |
1770 | ||
1771 | /* Perform an inline saturating addition of a 32-bit value within | |
1772 | * a 64-bit register. The second operand is known to be positive, | |
1773 | * which halves the comparisions we must perform to bound the result. | |
1774 | */ | |
1775 | static void do_sat_addsub_32(TCGv_i64 reg, TCGv_i64 val, bool u, bool d) | |
1776 | { | |
1777 | int64_t ibound; | |
24e82e68 RH |
1778 | |
1779 | /* Use normal 64-bit arithmetic to detect 32-bit overflow. */ | |
1780 | if (u) { | |
1781 | tcg_gen_ext32u_i64(reg, reg); | |
1782 | } else { | |
1783 | tcg_gen_ext32s_i64(reg, reg); | |
1784 | } | |
1785 | if (d) { | |
1786 | tcg_gen_sub_i64(reg, reg, val); | |
1787 | ibound = (u ? 0 : INT32_MIN); | |
aa5b0b29 | 1788 | tcg_gen_smax_i64(reg, reg, tcg_constant_i64(ibound)); |
24e82e68 RH |
1789 | } else { |
1790 | tcg_gen_add_i64(reg, reg, val); | |
1791 | ibound = (u ? UINT32_MAX : INT32_MAX); | |
aa5b0b29 | 1792 | tcg_gen_smin_i64(reg, reg, tcg_constant_i64(ibound)); |
24e82e68 | 1793 | } |
24e82e68 RH |
1794 | } |
1795 | ||
1796 | /* Similarly with 64-bit values. */ | |
1797 | static void do_sat_addsub_64(TCGv_i64 reg, TCGv_i64 val, bool u, bool d) | |
1798 | { | |
1799 | TCGv_i64 t0 = tcg_temp_new_i64(); | |
24e82e68 RH |
1800 | TCGv_i64 t2; |
1801 | ||
1802 | if (u) { | |
1803 | if (d) { | |
1804 | tcg_gen_sub_i64(t0, reg, val); | |
35a1ec8e PMD |
1805 | t2 = tcg_constant_i64(0); |
1806 | tcg_gen_movcond_i64(TCG_COND_LTU, reg, reg, val, t2, t0); | |
24e82e68 RH |
1807 | } else { |
1808 | tcg_gen_add_i64(t0, reg, val); | |
35a1ec8e PMD |
1809 | t2 = tcg_constant_i64(-1); |
1810 | tcg_gen_movcond_i64(TCG_COND_LTU, reg, t0, reg, t2, t0); | |
24e82e68 RH |
1811 | } |
1812 | } else { | |
35a1ec8e | 1813 | TCGv_i64 t1 = tcg_temp_new_i64(); |
24e82e68 RH |
1814 | if (d) { |
1815 | /* Detect signed overflow for subtraction. */ | |
1816 | tcg_gen_xor_i64(t0, reg, val); | |
1817 | tcg_gen_sub_i64(t1, reg, val); | |
7a31e0c6 | 1818 | tcg_gen_xor_i64(reg, reg, t1); |
24e82e68 RH |
1819 | tcg_gen_and_i64(t0, t0, reg); |
1820 | ||
1821 | /* Bound the result. */ | |
1822 | tcg_gen_movi_i64(reg, INT64_MIN); | |
35a1ec8e | 1823 | t2 = tcg_constant_i64(0); |
24e82e68 RH |
1824 | tcg_gen_movcond_i64(TCG_COND_LT, reg, t0, t2, reg, t1); |
1825 | } else { | |
1826 | /* Detect signed overflow for addition. */ | |
1827 | tcg_gen_xor_i64(t0, reg, val); | |
1828 | tcg_gen_add_i64(reg, reg, val); | |
1829 | tcg_gen_xor_i64(t1, reg, val); | |
1830 | tcg_gen_andc_i64(t0, t1, t0); | |
1831 | ||
1832 | /* Bound the result. */ | |
1833 | tcg_gen_movi_i64(t1, INT64_MAX); | |
35a1ec8e | 1834 | t2 = tcg_constant_i64(0); |
24e82e68 RH |
1835 | tcg_gen_movcond_i64(TCG_COND_LT, reg, t0, t2, t1, reg); |
1836 | } | |
35a1ec8e | 1837 | tcg_temp_free_i64(t1); |
24e82e68 RH |
1838 | } |
1839 | tcg_temp_free_i64(t0); | |
24e82e68 RH |
1840 | } |
1841 | ||
1842 | /* Similarly with a vector and a scalar operand. */ | |
1843 | static void do_sat_addsub_vec(DisasContext *s, int esz, int rd, int rn, | |
1844 | TCGv_i64 val, bool u, bool d) | |
1845 | { | |
1846 | unsigned vsz = vec_full_reg_size(s); | |
1847 | TCGv_ptr dptr, nptr; | |
1848 | TCGv_i32 t32, desc; | |
1849 | TCGv_i64 t64; | |
1850 | ||
1851 | dptr = tcg_temp_new_ptr(); | |
1852 | nptr = tcg_temp_new_ptr(); | |
1853 | tcg_gen_addi_ptr(dptr, cpu_env, vec_full_reg_offset(s, rd)); | |
1854 | tcg_gen_addi_ptr(nptr, cpu_env, vec_full_reg_offset(s, rn)); | |
c6a59b55 | 1855 | desc = tcg_constant_i32(simd_desc(vsz, vsz, 0)); |
24e82e68 RH |
1856 | |
1857 | switch (esz) { | |
1858 | case MO_8: | |
1859 | t32 = tcg_temp_new_i32(); | |
1860 | tcg_gen_extrl_i64_i32(t32, val); | |
1861 | if (d) { | |
1862 | tcg_gen_neg_i32(t32, t32); | |
1863 | } | |
1864 | if (u) { | |
1865 | gen_helper_sve_uqaddi_b(dptr, nptr, t32, desc); | |
1866 | } else { | |
1867 | gen_helper_sve_sqaddi_b(dptr, nptr, t32, desc); | |
1868 | } | |
1869 | tcg_temp_free_i32(t32); | |
1870 | break; | |
1871 | ||
1872 | case MO_16: | |
1873 | t32 = tcg_temp_new_i32(); | |
1874 | tcg_gen_extrl_i64_i32(t32, val); | |
1875 | if (d) { | |
1876 | tcg_gen_neg_i32(t32, t32); | |
1877 | } | |
1878 | if (u) { | |
1879 | gen_helper_sve_uqaddi_h(dptr, nptr, t32, desc); | |
1880 | } else { | |
1881 | gen_helper_sve_sqaddi_h(dptr, nptr, t32, desc); | |
1882 | } | |
1883 | tcg_temp_free_i32(t32); | |
1884 | break; | |
1885 | ||
1886 | case MO_32: | |
1887 | t64 = tcg_temp_new_i64(); | |
1888 | if (d) { | |
1889 | tcg_gen_neg_i64(t64, val); | |
1890 | } else { | |
1891 | tcg_gen_mov_i64(t64, val); | |
1892 | } | |
1893 | if (u) { | |
1894 | gen_helper_sve_uqaddi_s(dptr, nptr, t64, desc); | |
1895 | } else { | |
1896 | gen_helper_sve_sqaddi_s(dptr, nptr, t64, desc); | |
1897 | } | |
1898 | tcg_temp_free_i64(t64); | |
1899 | break; | |
1900 | ||
1901 | case MO_64: | |
1902 | if (u) { | |
1903 | if (d) { | |
1904 | gen_helper_sve_uqsubi_d(dptr, nptr, val, desc); | |
1905 | } else { | |
1906 | gen_helper_sve_uqaddi_d(dptr, nptr, val, desc); | |
1907 | } | |
1908 | } else if (d) { | |
1909 | t64 = tcg_temp_new_i64(); | |
1910 | tcg_gen_neg_i64(t64, val); | |
1911 | gen_helper_sve_sqaddi_d(dptr, nptr, t64, desc); | |
1912 | tcg_temp_free_i64(t64); | |
1913 | } else { | |
1914 | gen_helper_sve_sqaddi_d(dptr, nptr, val, desc); | |
1915 | } | |
1916 | break; | |
1917 | ||
1918 | default: | |
1919 | g_assert_not_reached(); | |
1920 | } | |
1921 | ||
1922 | tcg_temp_free_ptr(dptr); | |
1923 | tcg_temp_free_ptr(nptr); | |
24e82e68 RH |
1924 | } |
1925 | ||
3a7be554 | 1926 | static bool trans_CNT_r(DisasContext *s, arg_CNT_r *a) |
24e82e68 RH |
1927 | { |
1928 | if (sve_access_check(s)) { | |
1929 | unsigned fullsz = vec_full_reg_size(s); | |
1930 | unsigned numelem = decode_pred_count(fullsz, a->pat, a->esz); | |
1931 | tcg_gen_movi_i64(cpu_reg(s, a->rd), numelem * a->imm); | |
1932 | } | |
1933 | return true; | |
1934 | } | |
1935 | ||
3a7be554 | 1936 | static bool trans_INCDEC_r(DisasContext *s, arg_incdec_cnt *a) |
24e82e68 RH |
1937 | { |
1938 | if (sve_access_check(s)) { | |
1939 | unsigned fullsz = vec_full_reg_size(s); | |
1940 | unsigned numelem = decode_pred_count(fullsz, a->pat, a->esz); | |
1941 | int inc = numelem * a->imm * (a->d ? -1 : 1); | |
1942 | TCGv_i64 reg = cpu_reg(s, a->rd); | |
1943 | ||
1944 | tcg_gen_addi_i64(reg, reg, inc); | |
1945 | } | |
1946 | return true; | |
1947 | } | |
1948 | ||
3a7be554 | 1949 | static bool trans_SINCDEC_r_32(DisasContext *s, arg_incdec_cnt *a) |
24e82e68 RH |
1950 | { |
1951 | if (!sve_access_check(s)) { | |
1952 | return true; | |
1953 | } | |
1954 | ||
1955 | unsigned fullsz = vec_full_reg_size(s); | |
1956 | unsigned numelem = decode_pred_count(fullsz, a->pat, a->esz); | |
1957 | int inc = numelem * a->imm; | |
1958 | TCGv_i64 reg = cpu_reg(s, a->rd); | |
1959 | ||
1960 | /* Use normal 64-bit arithmetic to detect 32-bit overflow. */ | |
1961 | if (inc == 0) { | |
1962 | if (a->u) { | |
1963 | tcg_gen_ext32u_i64(reg, reg); | |
1964 | } else { | |
1965 | tcg_gen_ext32s_i64(reg, reg); | |
1966 | } | |
1967 | } else { | |
d681f125 | 1968 | do_sat_addsub_32(reg, tcg_constant_i64(inc), a->u, a->d); |
24e82e68 RH |
1969 | } |
1970 | return true; | |
1971 | } | |
1972 | ||
3a7be554 | 1973 | static bool trans_SINCDEC_r_64(DisasContext *s, arg_incdec_cnt *a) |
24e82e68 RH |
1974 | { |
1975 | if (!sve_access_check(s)) { | |
1976 | return true; | |
1977 | } | |
1978 | ||
1979 | unsigned fullsz = vec_full_reg_size(s); | |
1980 | unsigned numelem = decode_pred_count(fullsz, a->pat, a->esz); | |
1981 | int inc = numelem * a->imm; | |
1982 | TCGv_i64 reg = cpu_reg(s, a->rd); | |
1983 | ||
1984 | if (inc != 0) { | |
d681f125 | 1985 | do_sat_addsub_64(reg, tcg_constant_i64(inc), a->u, a->d); |
24e82e68 RH |
1986 | } |
1987 | return true; | |
1988 | } | |
1989 | ||
3a7be554 | 1990 | static bool trans_INCDEC_v(DisasContext *s, arg_incdec2_cnt *a) |
24e82e68 RH |
1991 | { |
1992 | if (a->esz == 0) { | |
1993 | return false; | |
1994 | } | |
1995 | ||
1996 | unsigned fullsz = vec_full_reg_size(s); | |
1997 | unsigned numelem = decode_pred_count(fullsz, a->pat, a->esz); | |
1998 | int inc = numelem * a->imm; | |
1999 | ||
2000 | if (inc != 0) { | |
2001 | if (sve_access_check(s)) { | |
24e82e68 RH |
2002 | tcg_gen_gvec_adds(a->esz, vec_full_reg_offset(s, a->rd), |
2003 | vec_full_reg_offset(s, a->rn), | |
d681f125 RH |
2004 | tcg_constant_i64(a->d ? -inc : inc), |
2005 | fullsz, fullsz); | |
24e82e68 RH |
2006 | } |
2007 | } else { | |
2008 | do_mov_z(s, a->rd, a->rn); | |
2009 | } | |
2010 | return true; | |
2011 | } | |
2012 | ||
3a7be554 | 2013 | static bool trans_SINCDEC_v(DisasContext *s, arg_incdec2_cnt *a) |
24e82e68 RH |
2014 | { |
2015 | if (a->esz == 0) { | |
2016 | return false; | |
2017 | } | |
2018 | ||
2019 | unsigned fullsz = vec_full_reg_size(s); | |
2020 | unsigned numelem = decode_pred_count(fullsz, a->pat, a->esz); | |
2021 | int inc = numelem * a->imm; | |
2022 | ||
2023 | if (inc != 0) { | |
2024 | if (sve_access_check(s)) { | |
d681f125 RH |
2025 | do_sat_addsub_vec(s, a->esz, a->rd, a->rn, |
2026 | tcg_constant_i64(inc), a->u, a->d); | |
24e82e68 RH |
2027 | } |
2028 | } else { | |
2029 | do_mov_z(s, a->rd, a->rn); | |
2030 | } | |
2031 | return true; | |
2032 | } | |
2033 | ||
e1fa1164 RH |
2034 | /* |
2035 | *** SVE Bitwise Immediate Group | |
2036 | */ | |
2037 | ||
2038 | static bool do_zz_dbm(DisasContext *s, arg_rr_dbm *a, GVecGen2iFn *gvec_fn) | |
2039 | { | |
2040 | uint64_t imm; | |
2041 | if (!logic_imm_decode_wmask(&imm, extract32(a->dbm, 12, 1), | |
2042 | extract32(a->dbm, 0, 6), | |
2043 | extract32(a->dbm, 6, 6))) { | |
2044 | return false; | |
2045 | } | |
faf915e2 | 2046 | return gen_gvec_fn_zzi(s, gvec_fn, MO_64, a->rd, a->rn, imm); |
e1fa1164 RH |
2047 | } |
2048 | ||
3a7be554 | 2049 | static bool trans_AND_zzi(DisasContext *s, arg_rr_dbm *a) |
e1fa1164 RH |
2050 | { |
2051 | return do_zz_dbm(s, a, tcg_gen_gvec_andi); | |
2052 | } | |
2053 | ||
3a7be554 | 2054 | static bool trans_ORR_zzi(DisasContext *s, arg_rr_dbm *a) |
e1fa1164 RH |
2055 | { |
2056 | return do_zz_dbm(s, a, tcg_gen_gvec_ori); | |
2057 | } | |
2058 | ||
3a7be554 | 2059 | static bool trans_EOR_zzi(DisasContext *s, arg_rr_dbm *a) |
e1fa1164 RH |
2060 | { |
2061 | return do_zz_dbm(s, a, tcg_gen_gvec_xori); | |
2062 | } | |
2063 | ||
3a7be554 | 2064 | static bool trans_DUPM(DisasContext *s, arg_DUPM *a) |
e1fa1164 RH |
2065 | { |
2066 | uint64_t imm; | |
2067 | if (!logic_imm_decode_wmask(&imm, extract32(a->dbm, 12, 1), | |
2068 | extract32(a->dbm, 0, 6), | |
2069 | extract32(a->dbm, 6, 6))) { | |
2070 | return false; | |
2071 | } | |
2072 | if (sve_access_check(s)) { | |
2073 | do_dupi_z(s, a->rd, imm); | |
2074 | } | |
2075 | return true; | |
2076 | } | |
2077 | ||
f25a2361 RH |
2078 | /* |
2079 | *** SVE Integer Wide Immediate - Predicated Group | |
2080 | */ | |
2081 | ||
2082 | /* Implement all merging copies. This is used for CPY (immediate), | |
2083 | * FCPY, CPY (scalar), CPY (SIMD&FP scalar). | |
2084 | */ | |
2085 | static void do_cpy_m(DisasContext *s, int esz, int rd, int rn, int pg, | |
2086 | TCGv_i64 val) | |
2087 | { | |
2088 | typedef void gen_cpy(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i64, TCGv_i32); | |
2089 | static gen_cpy * const fns[4] = { | |
2090 | gen_helper_sve_cpy_m_b, gen_helper_sve_cpy_m_h, | |
2091 | gen_helper_sve_cpy_m_s, gen_helper_sve_cpy_m_d, | |
2092 | }; | |
2093 | unsigned vsz = vec_full_reg_size(s); | |
c6a59b55 | 2094 | TCGv_i32 desc = tcg_constant_i32(simd_desc(vsz, vsz, 0)); |
f25a2361 RH |
2095 | TCGv_ptr t_zd = tcg_temp_new_ptr(); |
2096 | TCGv_ptr t_zn = tcg_temp_new_ptr(); | |
2097 | TCGv_ptr t_pg = tcg_temp_new_ptr(); | |
2098 | ||
2099 | tcg_gen_addi_ptr(t_zd, cpu_env, vec_full_reg_offset(s, rd)); | |
2100 | tcg_gen_addi_ptr(t_zn, cpu_env, vec_full_reg_offset(s, rn)); | |
2101 | tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, pg)); | |
2102 | ||
2103 | fns[esz](t_zd, t_zn, t_pg, val, desc); | |
2104 | ||
2105 | tcg_temp_free_ptr(t_zd); | |
2106 | tcg_temp_free_ptr(t_zn); | |
2107 | tcg_temp_free_ptr(t_pg); | |
f25a2361 RH |
2108 | } |
2109 | ||
3a7be554 | 2110 | static bool trans_FCPY(DisasContext *s, arg_FCPY *a) |
f25a2361 RH |
2111 | { |
2112 | if (a->esz == 0) { | |
2113 | return false; | |
2114 | } | |
2115 | if (sve_access_check(s)) { | |
2116 | /* Decode the VFP immediate. */ | |
2117 | uint64_t imm = vfp_expand_imm(a->esz, a->imm); | |
e152b48b | 2118 | do_cpy_m(s, a->esz, a->rd, a->rn, a->pg, tcg_constant_i64(imm)); |
f25a2361 RH |
2119 | } |
2120 | return true; | |
2121 | } | |
2122 | ||
3a7be554 | 2123 | static bool trans_CPY_m_i(DisasContext *s, arg_rpri_esz *a) |
f25a2361 | 2124 | { |
3a7be554 | 2125 | if (a->esz == 0 && extract32(s->insn, 13, 1)) { |
f25a2361 RH |
2126 | return false; |
2127 | } | |
2128 | if (sve_access_check(s)) { | |
e152b48b | 2129 | do_cpy_m(s, a->esz, a->rd, a->rn, a->pg, tcg_constant_i64(a->imm)); |
f25a2361 RH |
2130 | } |
2131 | return true; | |
2132 | } | |
2133 | ||
3a7be554 | 2134 | static bool trans_CPY_z_i(DisasContext *s, arg_CPY_z_i *a) |
f25a2361 RH |
2135 | { |
2136 | static gen_helper_gvec_2i * const fns[4] = { | |
2137 | gen_helper_sve_cpy_z_b, gen_helper_sve_cpy_z_h, | |
2138 | gen_helper_sve_cpy_z_s, gen_helper_sve_cpy_z_d, | |
2139 | }; | |
2140 | ||
3a7be554 | 2141 | if (a->esz == 0 && extract32(s->insn, 13, 1)) { |
f25a2361 RH |
2142 | return false; |
2143 | } | |
2144 | if (sve_access_check(s)) { | |
2145 | unsigned vsz = vec_full_reg_size(s); | |
f25a2361 RH |
2146 | tcg_gen_gvec_2i_ool(vec_full_reg_offset(s, a->rd), |
2147 | pred_full_reg_offset(s, a->pg), | |
e152b48b RH |
2148 | tcg_constant_i64(a->imm), |
2149 | vsz, vsz, 0, fns[a->esz]); | |
f25a2361 RH |
2150 | } |
2151 | return true; | |
2152 | } | |
2153 | ||
b94f8f60 RH |
2154 | /* |
2155 | *** SVE Permute Extract Group | |
2156 | */ | |
2157 | ||
75114792 | 2158 | static bool do_EXT(DisasContext *s, int rd, int rn, int rm, int imm) |
b94f8f60 RH |
2159 | { |
2160 | if (!sve_access_check(s)) { | |
2161 | return true; | |
2162 | } | |
2163 | ||
2164 | unsigned vsz = vec_full_reg_size(s); | |
75114792 | 2165 | unsigned n_ofs = imm >= vsz ? 0 : imm; |
b94f8f60 | 2166 | unsigned n_siz = vsz - n_ofs; |
75114792 SL |
2167 | unsigned d = vec_full_reg_offset(s, rd); |
2168 | unsigned n = vec_full_reg_offset(s, rn); | |
2169 | unsigned m = vec_full_reg_offset(s, rm); | |
b94f8f60 RH |
2170 | |
2171 | /* Use host vector move insns if we have appropriate sizes | |
2172 | * and no unfortunate overlap. | |
2173 | */ | |
2174 | if (m != d | |
2175 | && n_ofs == size_for_gvec(n_ofs) | |
2176 | && n_siz == size_for_gvec(n_siz) | |
2177 | && (d != n || n_siz <= n_ofs)) { | |
2178 | tcg_gen_gvec_mov(0, d, n + n_ofs, n_siz, n_siz); | |
2179 | if (n_ofs != 0) { | |
2180 | tcg_gen_gvec_mov(0, d + n_siz, m, n_ofs, n_ofs); | |
2181 | } | |
2182 | } else { | |
2183 | tcg_gen_gvec_3_ool(d, n, m, vsz, vsz, n_ofs, gen_helper_sve_ext); | |
2184 | } | |
2185 | return true; | |
2186 | } | |
2187 | ||
75114792 SL |
2188 | static bool trans_EXT(DisasContext *s, arg_EXT *a) |
2189 | { | |
2190 | return do_EXT(s, a->rd, a->rn, a->rm, a->imm); | |
2191 | } | |
2192 | ||
2193 | static bool trans_EXT_sve2(DisasContext *s, arg_rri *a) | |
2194 | { | |
2195 | if (!dc_isar_feature(aa64_sve2, s)) { | |
2196 | return false; | |
2197 | } | |
2198 | return do_EXT(s, a->rd, a->rn, (a->rn + 1) % 32, a->imm); | |
2199 | } | |
2200 | ||
30562ab7 RH |
2201 | /* |
2202 | *** SVE Permute - Unpredicated Group | |
2203 | */ | |
2204 | ||
3a7be554 | 2205 | static bool trans_DUP_s(DisasContext *s, arg_DUP_s *a) |
30562ab7 RH |
2206 | { |
2207 | if (sve_access_check(s)) { | |
2208 | unsigned vsz = vec_full_reg_size(s); | |
2209 | tcg_gen_gvec_dup_i64(a->esz, vec_full_reg_offset(s, a->rd), | |
2210 | vsz, vsz, cpu_reg_sp(s, a->rn)); | |
2211 | } | |
2212 | return true; | |
2213 | } | |
2214 | ||
3a7be554 | 2215 | static bool trans_DUP_x(DisasContext *s, arg_DUP_x *a) |
30562ab7 RH |
2216 | { |
2217 | if ((a->imm & 0x1f) == 0) { | |
2218 | return false; | |
2219 | } | |
2220 | if (sve_access_check(s)) { | |
2221 | unsigned vsz = vec_full_reg_size(s); | |
2222 | unsigned dofs = vec_full_reg_offset(s, a->rd); | |
2223 | unsigned esz, index; | |
2224 | ||
2225 | esz = ctz32(a->imm); | |
2226 | index = a->imm >> (esz + 1); | |
2227 | ||
2228 | if ((index << esz) < vsz) { | |
2229 | unsigned nofs = vec_reg_offset(s, a->rn, index, esz); | |
2230 | tcg_gen_gvec_dup_mem(esz, dofs, nofs, vsz, vsz); | |
2231 | } else { | |
7e17d50e RH |
2232 | /* |
2233 | * While dup_mem handles 128-bit elements, dup_imm does not. | |
2234 | * Thankfully element size doesn't matter for splatting zero. | |
2235 | */ | |
2236 | tcg_gen_gvec_dup_imm(MO_64, dofs, vsz, vsz, 0); | |
30562ab7 RH |
2237 | } |
2238 | } | |
2239 | return true; | |
2240 | } | |
2241 | ||
2242 | static void do_insr_i64(DisasContext *s, arg_rrr_esz *a, TCGv_i64 val) | |
2243 | { | |
2244 | typedef void gen_insr(TCGv_ptr, TCGv_ptr, TCGv_i64, TCGv_i32); | |
2245 | static gen_insr * const fns[4] = { | |
2246 | gen_helper_sve_insr_b, gen_helper_sve_insr_h, | |
2247 | gen_helper_sve_insr_s, gen_helper_sve_insr_d, | |
2248 | }; | |
2249 | unsigned vsz = vec_full_reg_size(s); | |
c6a59b55 | 2250 | TCGv_i32 desc = tcg_constant_i32(simd_desc(vsz, vsz, 0)); |
30562ab7 RH |
2251 | TCGv_ptr t_zd = tcg_temp_new_ptr(); |
2252 | TCGv_ptr t_zn = tcg_temp_new_ptr(); | |
2253 | ||
2254 | tcg_gen_addi_ptr(t_zd, cpu_env, vec_full_reg_offset(s, a->rd)); | |
2255 | tcg_gen_addi_ptr(t_zn, cpu_env, vec_full_reg_offset(s, a->rn)); | |
2256 | ||
2257 | fns[a->esz](t_zd, t_zn, val, desc); | |
2258 | ||
2259 | tcg_temp_free_ptr(t_zd); | |
2260 | tcg_temp_free_ptr(t_zn); | |
30562ab7 RH |
2261 | } |
2262 | ||
3a7be554 | 2263 | static bool trans_INSR_f(DisasContext *s, arg_rrr_esz *a) |
30562ab7 RH |
2264 | { |
2265 | if (sve_access_check(s)) { | |
2266 | TCGv_i64 t = tcg_temp_new_i64(); | |
2267 | tcg_gen_ld_i64(t, cpu_env, vec_reg_offset(s, a->rm, 0, MO_64)); | |
2268 | do_insr_i64(s, a, t); | |
2269 | tcg_temp_free_i64(t); | |
2270 | } | |
2271 | return true; | |
2272 | } | |
2273 | ||
3a7be554 | 2274 | static bool trans_INSR_r(DisasContext *s, arg_rrr_esz *a) |
30562ab7 RH |
2275 | { |
2276 | if (sve_access_check(s)) { | |
2277 | do_insr_i64(s, a, cpu_reg(s, a->rm)); | |
2278 | } | |
2279 | return true; | |
2280 | } | |
2281 | ||
0ea3cdbf RH |
2282 | static gen_helper_gvec_2 * const rev_fns[4] = { |
2283 | gen_helper_sve_rev_b, gen_helper_sve_rev_h, | |
2284 | gen_helper_sve_rev_s, gen_helper_sve_rev_d | |
2285 | }; | |
2286 | TRANS_FEAT(REV_v, aa64_sve, gen_gvec_ool_zz, rev_fns[a->esz], a->rd, a->rn, 0) | |
30562ab7 | 2287 | |
32e2ad65 RH |
2288 | static gen_helper_gvec_3 * const sve_tbl_fns[4] = { |
2289 | gen_helper_sve_tbl_b, gen_helper_sve_tbl_h, | |
2290 | gen_helper_sve_tbl_s, gen_helper_sve_tbl_d | |
2291 | }; | |
2292 | TRANS_FEAT(TBL, aa64_sve, gen_gvec_ool_arg_zzz, sve_tbl_fns[a->esz], a, 0) | |
30562ab7 | 2293 | |
5f425b92 RH |
2294 | static gen_helper_gvec_4 * const sve2_tbl_fns[4] = { |
2295 | gen_helper_sve2_tbl_b, gen_helper_sve2_tbl_h, | |
2296 | gen_helper_sve2_tbl_s, gen_helper_sve2_tbl_d | |
2297 | }; | |
2298 | TRANS_FEAT(TBL_sve2, aa64_sve2, gen_gvec_ool_zzzz, sve2_tbl_fns[a->esz], | |
2299 | a->rd, a->rn, (a->rn + 1) % 32, a->rm, 0) | |
80a712a2 | 2300 | |
32e2ad65 RH |
2301 | static gen_helper_gvec_3 * const tbx_fns[4] = { |
2302 | gen_helper_sve2_tbx_b, gen_helper_sve2_tbx_h, | |
2303 | gen_helper_sve2_tbx_s, gen_helper_sve2_tbx_d | |
2304 | }; | |
2305 | TRANS_FEAT(TBX, aa64_sve2, gen_gvec_ool_arg_zzz, tbx_fns[a->esz], a, 0) | |
80a712a2 | 2306 | |
3a7be554 | 2307 | static bool trans_UNPK(DisasContext *s, arg_UNPK *a) |
30562ab7 RH |
2308 | { |
2309 | static gen_helper_gvec_2 * const fns[4][2] = { | |
2310 | { NULL, NULL }, | |
2311 | { gen_helper_sve_sunpk_h, gen_helper_sve_uunpk_h }, | |
2312 | { gen_helper_sve_sunpk_s, gen_helper_sve_uunpk_s }, | |
2313 | { gen_helper_sve_sunpk_d, gen_helper_sve_uunpk_d }, | |
2314 | }; | |
2315 | ||
2316 | if (a->esz == 0) { | |
2317 | return false; | |
2318 | } | |
2319 | if (sve_access_check(s)) { | |
2320 | unsigned vsz = vec_full_reg_size(s); | |
2321 | tcg_gen_gvec_2_ool(vec_full_reg_offset(s, a->rd), | |
2322 | vec_full_reg_offset(s, a->rn) | |
2323 | + (a->h ? vsz / 2 : 0), | |
2324 | vsz, vsz, 0, fns[a->esz][a->u]); | |
2325 | } | |
2326 | return true; | |
2327 | } | |
2328 | ||
d731d8cb RH |
2329 | /* |
2330 | *** SVE Permute - Predicates Group | |
2331 | */ | |
2332 | ||
2333 | static bool do_perm_pred3(DisasContext *s, arg_rrr_esz *a, bool high_odd, | |
2334 | gen_helper_gvec_3 *fn) | |
2335 | { | |
2336 | if (!sve_access_check(s)) { | |
2337 | return true; | |
2338 | } | |
2339 | ||
2340 | unsigned vsz = pred_full_reg_size(s); | |
2341 | ||
d731d8cb RH |
2342 | TCGv_ptr t_d = tcg_temp_new_ptr(); |
2343 | TCGv_ptr t_n = tcg_temp_new_ptr(); | |
2344 | TCGv_ptr t_m = tcg_temp_new_ptr(); | |
f9b0fcce | 2345 | uint32_t desc = 0; |
d731d8cb | 2346 | |
f9b0fcce RH |
2347 | desc = FIELD_DP32(desc, PREDDESC, OPRSZ, vsz); |
2348 | desc = FIELD_DP32(desc, PREDDESC, ESZ, a->esz); | |
2349 | desc = FIELD_DP32(desc, PREDDESC, DATA, high_odd); | |
d731d8cb RH |
2350 | |
2351 | tcg_gen_addi_ptr(t_d, cpu_env, pred_full_reg_offset(s, a->rd)); | |
2352 | tcg_gen_addi_ptr(t_n, cpu_env, pred_full_reg_offset(s, a->rn)); | |
2353 | tcg_gen_addi_ptr(t_m, cpu_env, pred_full_reg_offset(s, a->rm)); | |
d731d8cb | 2354 | |
c6a59b55 | 2355 | fn(t_d, t_n, t_m, tcg_constant_i32(desc)); |
d731d8cb RH |
2356 | |
2357 | tcg_temp_free_ptr(t_d); | |
2358 | tcg_temp_free_ptr(t_n); | |
2359 | tcg_temp_free_ptr(t_m); | |
d731d8cb RH |
2360 | return true; |
2361 | } | |
2362 | ||
2363 | static bool do_perm_pred2(DisasContext *s, arg_rr_esz *a, bool high_odd, | |
2364 | gen_helper_gvec_2 *fn) | |
2365 | { | |
2366 | if (!sve_access_check(s)) { | |
2367 | return true; | |
2368 | } | |
2369 | ||
2370 | unsigned vsz = pred_full_reg_size(s); | |
2371 | TCGv_ptr t_d = tcg_temp_new_ptr(); | |
2372 | TCGv_ptr t_n = tcg_temp_new_ptr(); | |
70acaafe | 2373 | uint32_t desc = 0; |
d731d8cb RH |
2374 | |
2375 | tcg_gen_addi_ptr(t_d, cpu_env, pred_full_reg_offset(s, a->rd)); | |
2376 | tcg_gen_addi_ptr(t_n, cpu_env, pred_full_reg_offset(s, a->rn)); | |
2377 | ||
70acaafe RH |
2378 | desc = FIELD_DP32(desc, PREDDESC, OPRSZ, vsz); |
2379 | desc = FIELD_DP32(desc, PREDDESC, ESZ, a->esz); | |
2380 | desc = FIELD_DP32(desc, PREDDESC, DATA, high_odd); | |
d731d8cb | 2381 | |
c6a59b55 | 2382 | fn(t_d, t_n, tcg_constant_i32(desc)); |
d731d8cb | 2383 | |
d731d8cb RH |
2384 | tcg_temp_free_ptr(t_d); |
2385 | tcg_temp_free_ptr(t_n); | |
2386 | return true; | |
2387 | } | |
2388 | ||
3a7be554 | 2389 | static bool trans_ZIP1_p(DisasContext *s, arg_rrr_esz *a) |
d731d8cb RH |
2390 | { |
2391 | return do_perm_pred3(s, a, 0, gen_helper_sve_zip_p); | |
2392 | } | |
2393 | ||
3a7be554 | 2394 | static bool trans_ZIP2_p(DisasContext *s, arg_rrr_esz *a) |
d731d8cb RH |
2395 | { |
2396 | return do_perm_pred3(s, a, 1, gen_helper_sve_zip_p); | |
2397 | } | |
2398 | ||
3a7be554 | 2399 | static bool trans_UZP1_p(DisasContext *s, arg_rrr_esz *a) |
d731d8cb RH |
2400 | { |
2401 | return do_perm_pred3(s, a, 0, gen_helper_sve_uzp_p); | |
2402 | } | |
2403 | ||
3a7be554 | 2404 | static bool trans_UZP2_p(DisasContext *s, arg_rrr_esz *a) |
d731d8cb RH |
2405 | { |
2406 | return do_perm_pred3(s, a, 1, gen_helper_sve_uzp_p); | |
2407 | } | |
2408 | ||
3a7be554 | 2409 | static bool trans_TRN1_p(DisasContext *s, arg_rrr_esz *a) |
d731d8cb RH |
2410 | { |
2411 | return do_perm_pred3(s, a, 0, gen_helper_sve_trn_p); | |
2412 | } | |
2413 | ||
3a7be554 | 2414 | static bool trans_TRN2_p(DisasContext *s, arg_rrr_esz *a) |
d731d8cb RH |
2415 | { |
2416 | return do_perm_pred3(s, a, 1, gen_helper_sve_trn_p); | |
2417 | } | |
2418 | ||
3a7be554 | 2419 | static bool trans_REV_p(DisasContext *s, arg_rr_esz *a) |
d731d8cb RH |
2420 | { |
2421 | return do_perm_pred2(s, a, 0, gen_helper_sve_rev_p); | |
2422 | } | |
2423 | ||
3a7be554 | 2424 | static bool trans_PUNPKLO(DisasContext *s, arg_PUNPKLO *a) |
d731d8cb RH |
2425 | { |
2426 | return do_perm_pred2(s, a, 0, gen_helper_sve_punpk_p); | |
2427 | } | |
2428 | ||
3a7be554 | 2429 | static bool trans_PUNPKHI(DisasContext *s, arg_PUNPKHI *a) |
d731d8cb RH |
2430 | { |
2431 | return do_perm_pred2(s, a, 1, gen_helper_sve_punpk_p); | |
2432 | } | |
2433 | ||
234b48e9 RH |
2434 | /* |
2435 | *** SVE Permute - Interleaving Group | |
2436 | */ | |
2437 | ||
2438 | static bool do_zip(DisasContext *s, arg_rrr_esz *a, bool high) | |
2439 | { | |
2440 | static gen_helper_gvec_3 * const fns[4] = { | |
2441 | gen_helper_sve_zip_b, gen_helper_sve_zip_h, | |
2442 | gen_helper_sve_zip_s, gen_helper_sve_zip_d, | |
2443 | }; | |
2444 | ||
2445 | if (sve_access_check(s)) { | |
2446 | unsigned vsz = vec_full_reg_size(s); | |
2447 | unsigned high_ofs = high ? vsz / 2 : 0; | |
2448 | tcg_gen_gvec_3_ool(vec_full_reg_offset(s, a->rd), | |
2449 | vec_full_reg_offset(s, a->rn) + high_ofs, | |
2450 | vec_full_reg_offset(s, a->rm) + high_ofs, | |
2451 | vsz, vsz, 0, fns[a->esz]); | |
2452 | } | |
2453 | return true; | |
2454 | } | |
2455 | ||
3a7be554 | 2456 | static bool trans_ZIP1_z(DisasContext *s, arg_rrr_esz *a) |
234b48e9 RH |
2457 | { |
2458 | return do_zip(s, a, false); | |
2459 | } | |
2460 | ||
3a7be554 | 2461 | static bool trans_ZIP2_z(DisasContext *s, arg_rrr_esz *a) |
234b48e9 RH |
2462 | { |
2463 | return do_zip(s, a, true); | |
2464 | } | |
2465 | ||
74b64b25 RH |
2466 | static bool do_zip_q(DisasContext *s, arg_rrr_esz *a, bool high) |
2467 | { | |
2468 | if (!dc_isar_feature(aa64_sve_f64mm, s)) { | |
2469 | return false; | |
2470 | } | |
2471 | if (sve_access_check(s)) { | |
2472 | unsigned vsz = vec_full_reg_size(s); | |
2473 | unsigned high_ofs = high ? QEMU_ALIGN_DOWN(vsz, 32) / 2 : 0; | |
2474 | tcg_gen_gvec_3_ool(vec_full_reg_offset(s, a->rd), | |
2475 | vec_full_reg_offset(s, a->rn) + high_ofs, | |
2476 | vec_full_reg_offset(s, a->rm) + high_ofs, | |
2477 | vsz, vsz, 0, gen_helper_sve2_zip_q); | |
2478 | } | |
2479 | return true; | |
2480 | } | |
2481 | ||
2482 | static bool trans_ZIP1_q(DisasContext *s, arg_rrr_esz *a) | |
2483 | { | |
2484 | return do_zip_q(s, a, false); | |
2485 | } | |
2486 | ||
2487 | static bool trans_ZIP2_q(DisasContext *s, arg_rrr_esz *a) | |
2488 | { | |
2489 | return do_zip_q(s, a, true); | |
2490 | } | |
2491 | ||
234b48e9 RH |
2492 | static gen_helper_gvec_3 * const uzp_fns[4] = { |
2493 | gen_helper_sve_uzp_b, gen_helper_sve_uzp_h, | |
2494 | gen_helper_sve_uzp_s, gen_helper_sve_uzp_d, | |
2495 | }; | |
2496 | ||
32e2ad65 RH |
2497 | TRANS_FEAT(UZP1_z, aa64_sve, gen_gvec_ool_arg_zzz, |
2498 | uzp_fns[a->esz], a, 0) | |
2499 | TRANS_FEAT(UZP2_z, aa64_sve, gen_gvec_ool_arg_zzz, | |
2500 | uzp_fns[a->esz], a, 1 << a->esz) | |
234b48e9 | 2501 | |
32e2ad65 RH |
2502 | TRANS_FEAT(UZP1_q, aa64_sve_f64mm, gen_gvec_ool_arg_zzz, |
2503 | gen_helper_sve2_uzp_q, a, 0) | |
2504 | TRANS_FEAT(UZP2_q, aa64_sve_f64mm, gen_gvec_ool_arg_zzz, | |
2505 | gen_helper_sve2_uzp_q, a, 16) | |
74b64b25 | 2506 | |
234b48e9 RH |
2507 | static gen_helper_gvec_3 * const trn_fns[4] = { |
2508 | gen_helper_sve_trn_b, gen_helper_sve_trn_h, | |
2509 | gen_helper_sve_trn_s, gen_helper_sve_trn_d, | |
2510 | }; | |
2511 | ||
32e2ad65 RH |
2512 | TRANS_FEAT(TRN1_z, aa64_sve, gen_gvec_ool_arg_zzz, |
2513 | trn_fns[a->esz], a, 0) | |
2514 | TRANS_FEAT(TRN2_z, aa64_sve, gen_gvec_ool_arg_zzz, | |
2515 | trn_fns[a->esz], a, 1 << a->esz) | |
234b48e9 | 2516 | |
32e2ad65 RH |
2517 | TRANS_FEAT(TRN1_q, aa64_sve_f64mm, gen_gvec_ool_arg_zzz, |
2518 | gen_helper_sve2_trn_q, a, 0) | |
2519 | TRANS_FEAT(TRN2_q, aa64_sve_f64mm, gen_gvec_ool_arg_zzz, | |
2520 | gen_helper_sve2_trn_q, a, 16) | |
74b64b25 | 2521 | |
3ca879ae RH |
2522 | /* |
2523 | *** SVE Permute Vector - Predicated Group | |
2524 | */ | |
2525 | ||
817bd5c9 RH |
2526 | static gen_helper_gvec_3 * const compact_fns[4] = { |
2527 | NULL, NULL, gen_helper_sve_compact_s, gen_helper_sve_compact_d | |
2528 | }; | |
2529 | TRANS_FEAT(COMPACT, aa64_sve, gen_gvec_ool_arg_zpz, compact_fns[a->esz], a, 0) | |
3ca879ae | 2530 | |
ef23cb72 RH |
2531 | /* Call the helper that computes the ARM LastActiveElement pseudocode |
2532 | * function, scaled by the element size. This includes the not found | |
2533 | * indication; e.g. not found for esz=3 is -8. | |
2534 | */ | |
2535 | static void find_last_active(DisasContext *s, TCGv_i32 ret, int esz, int pg) | |
2536 | { | |
2537 | /* Predicate sizes may be smaller and cannot use simd_desc. We cannot | |
2538 | * round up, as we do elsewhere, because we need the exact size. | |
2539 | */ | |
2540 | TCGv_ptr t_p = tcg_temp_new_ptr(); | |
2acbfbe4 | 2541 | unsigned desc = 0; |
ef23cb72 | 2542 | |
2acbfbe4 RH |
2543 | desc = FIELD_DP32(desc, PREDDESC, OPRSZ, pred_full_reg_size(s)); |
2544 | desc = FIELD_DP32(desc, PREDDESC, ESZ, esz); | |
ef23cb72 RH |
2545 | |
2546 | tcg_gen_addi_ptr(t_p, cpu_env, pred_full_reg_offset(s, pg)); | |
ef23cb72 | 2547 | |
c6a59b55 | 2548 | gen_helper_sve_last_active_element(ret, t_p, tcg_constant_i32(desc)); |
ef23cb72 | 2549 | |
ef23cb72 RH |
2550 | tcg_temp_free_ptr(t_p); |
2551 | } | |
2552 | ||
2553 | /* Increment LAST to the offset of the next element in the vector, | |
2554 | * wrapping around to 0. | |
2555 | */ | |
2556 | static void incr_last_active(DisasContext *s, TCGv_i32 last, int esz) | |
2557 | { | |
2558 | unsigned vsz = vec_full_reg_size(s); | |
2559 | ||
2560 | tcg_gen_addi_i32(last, last, 1 << esz); | |
2561 | if (is_power_of_2(vsz)) { | |
2562 | tcg_gen_andi_i32(last, last, vsz - 1); | |
2563 | } else { | |
4b308bd5 RH |
2564 | TCGv_i32 max = tcg_constant_i32(vsz); |
2565 | TCGv_i32 zero = tcg_constant_i32(0); | |
ef23cb72 | 2566 | tcg_gen_movcond_i32(TCG_COND_GEU, last, last, max, zero, last); |
ef23cb72 RH |
2567 | } |
2568 | } | |
2569 | ||
2570 | /* If LAST < 0, set LAST to the offset of the last element in the vector. */ | |
2571 | static void wrap_last_active(DisasContext *s, TCGv_i32 last, int esz) | |
2572 | { | |
2573 | unsigned vsz = vec_full_reg_size(s); | |
2574 | ||
2575 | if (is_power_of_2(vsz)) { | |
2576 | tcg_gen_andi_i32(last, last, vsz - 1); | |
2577 | } else { | |
4b308bd5 RH |
2578 | TCGv_i32 max = tcg_constant_i32(vsz - (1 << esz)); |
2579 | TCGv_i32 zero = tcg_constant_i32(0); | |
ef23cb72 | 2580 | tcg_gen_movcond_i32(TCG_COND_LT, last, last, zero, max, last); |
ef23cb72 RH |
2581 | } |
2582 | } | |
2583 | ||
2584 | /* Load an unsigned element of ESZ from BASE+OFS. */ | |
2585 | static TCGv_i64 load_esz(TCGv_ptr base, int ofs, int esz) | |
2586 | { | |
2587 | TCGv_i64 r = tcg_temp_new_i64(); | |
2588 | ||
2589 | switch (esz) { | |
2590 | case 0: | |
2591 | tcg_gen_ld8u_i64(r, base, ofs); | |
2592 | break; | |
2593 | case 1: | |
2594 | tcg_gen_ld16u_i64(r, base, ofs); | |
2595 | break; | |
2596 | case 2: | |
2597 | tcg_gen_ld32u_i64(r, base, ofs); | |
2598 | break; | |
2599 | case 3: | |
2600 | tcg_gen_ld_i64(r, base, ofs); | |
2601 | break; | |
2602 | default: | |
2603 | g_assert_not_reached(); | |
2604 | } | |
2605 | return r; | |
2606 | } | |
2607 | ||
2608 | /* Load an unsigned element of ESZ from RM[LAST]. */ | |
2609 | static TCGv_i64 load_last_active(DisasContext *s, TCGv_i32 last, | |
2610 | int rm, int esz) | |
2611 | { | |
2612 | TCGv_ptr p = tcg_temp_new_ptr(); | |
2613 | TCGv_i64 r; | |
2614 | ||
2615 | /* Convert offset into vector into offset into ENV. | |
2616 | * The final adjustment for the vector register base | |
2617 | * is added via constant offset to the load. | |
2618 | */ | |
e03b5686 | 2619 | #if HOST_BIG_ENDIAN |
ef23cb72 RH |
2620 | /* Adjust for element ordering. See vec_reg_offset. */ |
2621 | if (esz < 3) { | |
2622 | tcg_gen_xori_i32(last, last, 8 - (1 << esz)); | |
2623 | } | |
2624 | #endif | |
2625 | tcg_gen_ext_i32_ptr(p, last); | |
2626 | tcg_gen_add_ptr(p, p, cpu_env); | |
2627 | ||
2628 | r = load_esz(p, vec_full_reg_offset(s, rm), esz); | |
2629 | tcg_temp_free_ptr(p); | |
2630 | ||
2631 | return r; | |
2632 | } | |
2633 | ||
2634 | /* Compute CLAST for a Zreg. */ | |
2635 | static bool do_clast_vector(DisasContext *s, arg_rprr_esz *a, bool before) | |
2636 | { | |
2637 | TCGv_i32 last; | |
2638 | TCGLabel *over; | |
2639 | TCGv_i64 ele; | |
2640 | unsigned vsz, esz = a->esz; | |
2641 | ||
2642 | if (!sve_access_check(s)) { | |
2643 | return true; | |
2644 | } | |
2645 | ||
2646 | last = tcg_temp_local_new_i32(); | |
2647 | over = gen_new_label(); | |
2648 | ||
2649 | find_last_active(s, last, esz, a->pg); | |
2650 | ||
2651 | /* There is of course no movcond for a 2048-bit vector, | |
2652 | * so we must branch over the actual store. | |
2653 | */ | |
2654 | tcg_gen_brcondi_i32(TCG_COND_LT, last, 0, over); | |
2655 | ||
2656 | if (!before) { | |
2657 | incr_last_active(s, last, esz); | |
2658 | } | |
2659 | ||
2660 | ele = load_last_active(s, last, a->rm, esz); | |
2661 | tcg_temp_free_i32(last); | |
2662 | ||
2663 | vsz = vec_full_reg_size(s); | |
2664 | tcg_gen_gvec_dup_i64(esz, vec_full_reg_offset(s, a->rd), vsz, vsz, ele); | |
2665 | tcg_temp_free_i64(ele); | |
2666 | ||
2667 | /* If this insn used MOVPRFX, we may need a second move. */ | |
2668 | if (a->rd != a->rn) { | |
2669 | TCGLabel *done = gen_new_label(); | |
2670 | tcg_gen_br(done); | |
2671 | ||
2672 | gen_set_label(over); | |
2673 | do_mov_z(s, a->rd, a->rn); | |
2674 | ||
2675 | gen_set_label(done); | |
2676 | } else { | |
2677 | gen_set_label(over); | |
2678 | } | |
2679 | return true; | |
2680 | } | |
2681 | ||
3a7be554 | 2682 | static bool trans_CLASTA_z(DisasContext *s, arg_rprr_esz *a) |
ef23cb72 RH |
2683 | { |
2684 | return do_clast_vector(s, a, false); | |
2685 | } | |
2686 | ||
3a7be554 | 2687 | static bool trans_CLASTB_z(DisasContext *s, arg_rprr_esz *a) |
ef23cb72 RH |
2688 | { |
2689 | return do_clast_vector(s, a, true); | |
2690 | } | |
2691 | ||
2692 | /* Compute CLAST for a scalar. */ | |
2693 | static void do_clast_scalar(DisasContext *s, int esz, int pg, int rm, | |
2694 | bool before, TCGv_i64 reg_val) | |
2695 | { | |
2696 | TCGv_i32 last = tcg_temp_new_i32(); | |
053552d3 | 2697 | TCGv_i64 ele, cmp; |
ef23cb72 RH |
2698 | |
2699 | find_last_active(s, last, esz, pg); | |
2700 | ||
2701 | /* Extend the original value of last prior to incrementing. */ | |
2702 | cmp = tcg_temp_new_i64(); | |
2703 | tcg_gen_ext_i32_i64(cmp, last); | |
2704 | ||
2705 | if (!before) { | |
2706 | incr_last_active(s, last, esz); | |
2707 | } | |
2708 | ||
2709 | /* The conceit here is that while last < 0 indicates not found, after | |
2710 | * adjusting for cpu_env->vfp.zregs[rm], it is still a valid address | |
2711 | * from which we can load garbage. We then discard the garbage with | |
2712 | * a conditional move. | |
2713 | */ | |
2714 | ele = load_last_active(s, last, rm, esz); | |
2715 | tcg_temp_free_i32(last); | |
2716 | ||
053552d3 RH |
2717 | tcg_gen_movcond_i64(TCG_COND_GE, reg_val, cmp, tcg_constant_i64(0), |
2718 | ele, reg_val); | |
ef23cb72 | 2719 | |
ef23cb72 RH |
2720 | tcg_temp_free_i64(cmp); |
2721 | tcg_temp_free_i64(ele); | |
2722 | } | |
2723 | ||
2724 | /* Compute CLAST for a Vreg. */ | |
2725 | static bool do_clast_fp(DisasContext *s, arg_rpr_esz *a, bool before) | |
2726 | { | |
2727 | if (sve_access_check(s)) { | |
2728 | int esz = a->esz; | |
2729 | int ofs = vec_reg_offset(s, a->rd, 0, esz); | |
2730 | TCGv_i64 reg = load_esz(cpu_env, ofs, esz); | |
2731 | ||
2732 | do_clast_scalar(s, esz, a->pg, a->rn, before, reg); | |
2733 | write_fp_dreg(s, a->rd, reg); | |
2734 | tcg_temp_free_i64(reg); | |
2735 | } | |
2736 | return true; | |
2737 | } | |
2738 | ||
3a7be554 | 2739 | static bool trans_CLASTA_v(DisasContext *s, arg_rpr_esz *a) |
ef23cb72 RH |
2740 | { |
2741 | return do_clast_fp(s, a, false); | |
2742 | } | |
2743 | ||
3a7be554 | 2744 | static bool trans_CLASTB_v(DisasContext *s, arg_rpr_esz *a) |
ef23cb72 RH |
2745 | { |
2746 | return do_clast_fp(s, a, true); | |
2747 | } | |
2748 | ||
2749 | /* Compute CLAST for a Xreg. */ | |
2750 | static bool do_clast_general(DisasContext *s, arg_rpr_esz *a, bool before) | |
2751 | { | |
2752 | TCGv_i64 reg; | |
2753 | ||
2754 | if (!sve_access_check(s)) { | |
2755 | return true; | |
2756 | } | |
2757 | ||
2758 | reg = cpu_reg(s, a->rd); | |
2759 | switch (a->esz) { | |
2760 | case 0: | |
2761 | tcg_gen_ext8u_i64(reg, reg); | |
2762 | break; | |
2763 | case 1: | |
2764 | tcg_gen_ext16u_i64(reg, reg); | |
2765 | break; | |
2766 | case 2: | |
2767 | tcg_gen_ext32u_i64(reg, reg); | |
2768 | break; | |
2769 | case 3: | |
2770 | break; | |
2771 | default: | |
2772 | g_assert_not_reached(); | |
2773 | } | |
2774 | ||
2775 | do_clast_scalar(s, a->esz, a->pg, a->rn, before, reg); | |
2776 | return true; | |
2777 | } | |
2778 | ||
3a7be554 | 2779 | static bool trans_CLASTA_r(DisasContext *s, arg_rpr_esz *a) |
ef23cb72 RH |
2780 | { |
2781 | return do_clast_general(s, a, false); | |
2782 | } | |
2783 | ||
3a7be554 | 2784 | static bool trans_CLASTB_r(DisasContext *s, arg_rpr_esz *a) |
ef23cb72 RH |
2785 | { |
2786 | return do_clast_general(s, a, true); | |
2787 | } | |
2788 | ||
2789 | /* Compute LAST for a scalar. */ | |
2790 | static TCGv_i64 do_last_scalar(DisasContext *s, int esz, | |
2791 | int pg, int rm, bool before) | |
2792 | { | |
2793 | TCGv_i32 last = tcg_temp_new_i32(); | |
2794 | TCGv_i64 ret; | |
2795 | ||
2796 | find_last_active(s, last, esz, pg); | |
2797 | if (before) { | |
2798 | wrap_last_active(s, last, esz); | |
2799 | } else { | |
2800 | incr_last_active(s, last, esz); | |
2801 | } | |
2802 | ||
2803 | ret = load_last_active(s, last, rm, esz); | |
2804 | tcg_temp_free_i32(last); | |
2805 | return ret; | |
2806 | } | |
2807 | ||
2808 | /* Compute LAST for a Vreg. */ | |
2809 | static bool do_last_fp(DisasContext *s, arg_rpr_esz *a, bool before) | |
2810 | { | |
2811 | if (sve_access_check(s)) { | |
2812 | TCGv_i64 val = do_last_scalar(s, a->esz, a->pg, a->rn, before); | |
2813 | write_fp_dreg(s, a->rd, val); | |
2814 | tcg_temp_free_i64(val); | |
2815 | } | |
2816 | return true; | |
2817 | } | |
2818 | ||
3a7be554 | 2819 | static bool trans_LASTA_v(DisasContext *s, arg_rpr_esz *a) |
ef23cb72 RH |
2820 | { |
2821 | return do_last_fp(s, a, false); | |
2822 | } | |
2823 | ||
3a7be554 | 2824 | static bool trans_LASTB_v(DisasContext *s, arg_rpr_esz *a) |
ef23cb72 RH |
2825 | { |
2826 | return do_last_fp(s, a, true); | |
2827 | } | |
2828 | ||
2829 | /* Compute LAST for a Xreg. */ | |
2830 | static bool do_last_general(DisasContext *s, arg_rpr_esz *a, bool before) | |
2831 | { | |
2832 | if (sve_access_check(s)) { | |
2833 | TCGv_i64 val = do_last_scalar(s, a->esz, a->pg, a->rn, before); | |
2834 | tcg_gen_mov_i64(cpu_reg(s, a->rd), val); | |
2835 | tcg_temp_free_i64(val); | |
2836 | } | |
2837 | return true; | |
2838 | } | |
2839 | ||
3a7be554 | 2840 | static bool trans_LASTA_r(DisasContext *s, arg_rpr_esz *a) |
ef23cb72 RH |
2841 | { |
2842 | return do_last_general(s, a, false); | |
2843 | } | |
2844 | ||
3a7be554 | 2845 | static bool trans_LASTB_r(DisasContext *s, arg_rpr_esz *a) |
ef23cb72 RH |
2846 | { |
2847 | return do_last_general(s, a, true); | |
2848 | } | |
2849 | ||
3a7be554 | 2850 | static bool trans_CPY_m_r(DisasContext *s, arg_rpr_esz *a) |
792a5578 RH |
2851 | { |
2852 | if (sve_access_check(s)) { | |
2853 | do_cpy_m(s, a->esz, a->rd, a->rd, a->pg, cpu_reg_sp(s, a->rn)); | |
2854 | } | |
2855 | return true; | |
2856 | } | |
2857 | ||
3a7be554 | 2858 | static bool trans_CPY_m_v(DisasContext *s, arg_rpr_esz *a) |
792a5578 RH |
2859 | { |
2860 | if (sve_access_check(s)) { | |
2861 | int ofs = vec_reg_offset(s, a->rn, 0, a->esz); | |
2862 | TCGv_i64 t = load_esz(cpu_env, ofs, a->esz); | |
2863 | do_cpy_m(s, a->esz, a->rd, a->rd, a->pg, t); | |
2864 | tcg_temp_free_i64(t); | |
2865 | } | |
2866 | return true; | |
2867 | } | |
2868 | ||
817bd5c9 RH |
2869 | static gen_helper_gvec_3 * const revb_fns[4] = { |
2870 | NULL, gen_helper_sve_revb_h, | |
2871 | gen_helper_sve_revb_s, gen_helper_sve_revb_d, | |
2872 | }; | |
2873 | TRANS_FEAT(REVB, aa64_sve, gen_gvec_ool_arg_zpz, revb_fns[a->esz], a, 0) | |
dae8fb90 | 2874 | |
817bd5c9 RH |
2875 | static gen_helper_gvec_3 * const revh_fns[4] = { |
2876 | NULL, NULL, gen_helper_sve_revh_s, gen_helper_sve_revh_d, | |
2877 | }; | |
2878 | TRANS_FEAT(REVH, aa64_sve, gen_gvec_ool_arg_zpz, revh_fns[a->esz], a, 0) | |
dae8fb90 | 2879 | |
817bd5c9 RH |
2880 | TRANS_FEAT(REVW, aa64_sve, gen_gvec_ool_arg_zpz, |
2881 | a->esz == 3 ? gen_helper_sve_revw_d : NULL, a, 0) | |
dae8fb90 | 2882 | |
3a7be554 | 2883 | static bool trans_SPLICE(DisasContext *s, arg_rprr_esz *a) |
b48ff240 | 2884 | { |
2a753d1e RH |
2885 | return gen_gvec_ool_zzzp(s, gen_helper_sve_splice, |
2886 | a->rd, a->rn, a->rm, a->pg, a->esz); | |
b48ff240 RH |
2887 | } |
2888 | ||
75114792 SL |
2889 | static bool trans_SPLICE_sve2(DisasContext *s, arg_rpr_esz *a) |
2890 | { | |
2891 | if (!dc_isar_feature(aa64_sve2, s)) { | |
2892 | return false; | |
2893 | } | |
2a753d1e RH |
2894 | return gen_gvec_ool_zzzp(s, gen_helper_sve_splice, |
2895 | a->rd, a->rn, (a->rn + 1) % 32, a->pg, a->esz); | |
75114792 SL |
2896 | } |
2897 | ||
757f9cff RH |
2898 | /* |
2899 | *** SVE Integer Compare - Vectors Group | |
2900 | */ | |
2901 | ||
2902 | static bool do_ppzz_flags(DisasContext *s, arg_rprr_esz *a, | |
2903 | gen_helper_gvec_flags_4 *gen_fn) | |
2904 | { | |
2905 | TCGv_ptr pd, zn, zm, pg; | |
2906 | unsigned vsz; | |
2907 | TCGv_i32 t; | |
2908 | ||
2909 | if (gen_fn == NULL) { | |
2910 | return false; | |
2911 | } | |
2912 | if (!sve_access_check(s)) { | |
2913 | return true; | |
2914 | } | |
2915 | ||
2916 | vsz = vec_full_reg_size(s); | |
392acacc | 2917 | t = tcg_temp_new_i32(); |
757f9cff RH |
2918 | pd = tcg_temp_new_ptr(); |
2919 | zn = tcg_temp_new_ptr(); | |
2920 | zm = tcg_temp_new_ptr(); | |
2921 | pg = tcg_temp_new_ptr(); | |
2922 | ||
2923 | tcg_gen_addi_ptr(pd, cpu_env, pred_full_reg_offset(s, a->rd)); | |
2924 | tcg_gen_addi_ptr(zn, cpu_env, vec_full_reg_offset(s, a->rn)); | |
2925 | tcg_gen_addi_ptr(zm, cpu_env, vec_full_reg_offset(s, a->rm)); | |
2926 | tcg_gen_addi_ptr(pg, cpu_env, pred_full_reg_offset(s, a->pg)); | |
2927 | ||
392acacc | 2928 | gen_fn(t, pd, zn, zm, pg, tcg_constant_i32(simd_desc(vsz, vsz, 0))); |
757f9cff RH |
2929 | |
2930 | tcg_temp_free_ptr(pd); | |
2931 | tcg_temp_free_ptr(zn); | |
2932 | tcg_temp_free_ptr(zm); | |
2933 | tcg_temp_free_ptr(pg); | |
2934 | ||
2935 | do_pred_flags(t); | |
2936 | ||
2937 | tcg_temp_free_i32(t); | |
2938 | return true; | |
2939 | } | |
2940 | ||
2941 | #define DO_PPZZ(NAME, name) \ | |
3a7be554 | 2942 | static bool trans_##NAME##_ppzz(DisasContext *s, arg_rprr_esz *a) \ |
757f9cff RH |
2943 | { \ |
2944 | static gen_helper_gvec_flags_4 * const fns[4] = { \ | |
2945 | gen_helper_sve_##name##_ppzz_b, gen_helper_sve_##name##_ppzz_h, \ | |
2946 | gen_helper_sve_##name##_ppzz_s, gen_helper_sve_##name##_ppzz_d, \ | |
2947 | }; \ | |
2948 | return do_ppzz_flags(s, a, fns[a->esz]); \ | |
2949 | } | |
2950 | ||
2951 | DO_PPZZ(CMPEQ, cmpeq) | |
2952 | DO_PPZZ(CMPNE, cmpne) | |
2953 | DO_PPZZ(CMPGT, cmpgt) | |
2954 | DO_PPZZ(CMPGE, cmpge) | |
2955 | DO_PPZZ(CMPHI, cmphi) | |
2956 | DO_PPZZ(CMPHS, cmphs) | |
2957 | ||
2958 | #undef DO_PPZZ | |
2959 | ||
2960 | #define DO_PPZW(NAME, name) \ | |
3a7be554 | 2961 | static bool trans_##NAME##_ppzw(DisasContext *s, arg_rprr_esz *a) \ |
757f9cff RH |
2962 | { \ |
2963 | static gen_helper_gvec_flags_4 * const fns[4] = { \ | |
2964 | gen_helper_sve_##name##_ppzw_b, gen_helper_sve_##name##_ppzw_h, \ | |
2965 | gen_helper_sve_##name##_ppzw_s, NULL \ | |
2966 | }; \ | |
2967 | return do_ppzz_flags(s, a, fns[a->esz]); \ | |
2968 | } | |
2969 | ||
2970 | DO_PPZW(CMPEQ, cmpeq) | |
2971 | DO_PPZW(CMPNE, cmpne) | |
2972 | DO_PPZW(CMPGT, cmpgt) | |
2973 | DO_PPZW(CMPGE, cmpge) | |
2974 | DO_PPZW(CMPHI, cmphi) | |
2975 | DO_PPZW(CMPHS, cmphs) | |
2976 | DO_PPZW(CMPLT, cmplt) | |
2977 | DO_PPZW(CMPLE, cmple) | |
2978 | DO_PPZW(CMPLO, cmplo) | |
2979 | DO_PPZW(CMPLS, cmpls) | |
2980 | ||
2981 | #undef DO_PPZW | |
2982 | ||
38cadeba RH |
2983 | /* |
2984 | *** SVE Integer Compare - Immediate Groups | |
2985 | */ | |
2986 | ||
2987 | static bool do_ppzi_flags(DisasContext *s, arg_rpri_esz *a, | |
2988 | gen_helper_gvec_flags_3 *gen_fn) | |
2989 | { | |
2990 | TCGv_ptr pd, zn, pg; | |
2991 | unsigned vsz; | |
2992 | TCGv_i32 t; | |
2993 | ||
2994 | if (gen_fn == NULL) { | |
2995 | return false; | |
2996 | } | |
2997 | if (!sve_access_check(s)) { | |
2998 | return true; | |
2999 | } | |
3000 | ||
3001 | vsz = vec_full_reg_size(s); | |
392acacc | 3002 | t = tcg_temp_new_i32(); |
38cadeba RH |
3003 | pd = tcg_temp_new_ptr(); |
3004 | zn = tcg_temp_new_ptr(); | |
3005 | pg = tcg_temp_new_ptr(); | |
3006 | ||
3007 | tcg_gen_addi_ptr(pd, cpu_env, pred_full_reg_offset(s, a->rd)); | |
3008 | tcg_gen_addi_ptr(zn, cpu_env, vec_full_reg_offset(s, a->rn)); | |
3009 | tcg_gen_addi_ptr(pg, cpu_env, pred_full_reg_offset(s, a->pg)); | |
3010 | ||
392acacc | 3011 | gen_fn(t, pd, zn, pg, tcg_constant_i32(simd_desc(vsz, vsz, a->imm))); |
38cadeba RH |
3012 | |
3013 | tcg_temp_free_ptr(pd); | |
3014 | tcg_temp_free_ptr(zn); | |
3015 | tcg_temp_free_ptr(pg); | |
3016 | ||
3017 | do_pred_flags(t); | |
3018 | ||
3019 | tcg_temp_free_i32(t); | |
3020 | return true; | |
3021 | } | |
3022 | ||
3023 | #define DO_PPZI(NAME, name) \ | |
3a7be554 | 3024 | static bool trans_##NAME##_ppzi(DisasContext *s, arg_rpri_esz *a) \ |
38cadeba RH |
3025 | { \ |
3026 | static gen_helper_gvec_flags_3 * const fns[4] = { \ | |
3027 | gen_helper_sve_##name##_ppzi_b, gen_helper_sve_##name##_ppzi_h, \ | |
3028 | gen_helper_sve_##name##_ppzi_s, gen_helper_sve_##name##_ppzi_d, \ | |
3029 | }; \ | |
3030 | return do_ppzi_flags(s, a, fns[a->esz]); \ | |
3031 | } | |
3032 | ||
3033 | DO_PPZI(CMPEQ, cmpeq) | |
3034 | DO_PPZI(CMPNE, cmpne) | |
3035 | DO_PPZI(CMPGT, cmpgt) | |
3036 | DO_PPZI(CMPGE, cmpge) | |
3037 | DO_PPZI(CMPHI, cmphi) | |
3038 | DO_PPZI(CMPHS, cmphs) | |
3039 | DO_PPZI(CMPLT, cmplt) | |
3040 | DO_PPZI(CMPLE, cmple) | |
3041 | DO_PPZI(CMPLO, cmplo) | |
3042 | DO_PPZI(CMPLS, cmpls) | |
3043 | ||
3044 | #undef DO_PPZI | |
3045 | ||
35da316f RH |
3046 | /* |
3047 | *** SVE Partition Break Group | |
3048 | */ | |
3049 | ||
3050 | static bool do_brk3(DisasContext *s, arg_rprr_s *a, | |
3051 | gen_helper_gvec_4 *fn, gen_helper_gvec_flags_4 *fn_s) | |
3052 | { | |
3053 | if (!sve_access_check(s)) { | |
3054 | return true; | |
3055 | } | |
3056 | ||
3057 | unsigned vsz = pred_full_reg_size(s); | |
3058 | ||
3059 | /* Predicate sizes may be smaller and cannot use simd_desc. */ | |
3060 | TCGv_ptr d = tcg_temp_new_ptr(); | |
3061 | TCGv_ptr n = tcg_temp_new_ptr(); | |
3062 | TCGv_ptr m = tcg_temp_new_ptr(); | |
3063 | TCGv_ptr g = tcg_temp_new_ptr(); | |
93418f1c | 3064 | TCGv_i32 desc = tcg_constant_i32(FIELD_DP32(0, PREDDESC, OPRSZ, vsz)); |
35da316f RH |
3065 | |
3066 | tcg_gen_addi_ptr(d, cpu_env, pred_full_reg_offset(s, a->rd)); | |
3067 | tcg_gen_addi_ptr(n, cpu_env, pred_full_reg_offset(s, a->rn)); | |
3068 | tcg_gen_addi_ptr(m, cpu_env, pred_full_reg_offset(s, a->rm)); | |
3069 | tcg_gen_addi_ptr(g, cpu_env, pred_full_reg_offset(s, a->pg)); | |
3070 | ||
3071 | if (a->s) { | |
93418f1c RH |
3072 | TCGv_i32 t = tcg_temp_new_i32(); |
3073 | fn_s(t, d, n, m, g, desc); | |
35da316f | 3074 | do_pred_flags(t); |
93418f1c | 3075 | tcg_temp_free_i32(t); |
35da316f | 3076 | } else { |
93418f1c | 3077 | fn(d, n, m, g, desc); |
35da316f RH |
3078 | } |
3079 | tcg_temp_free_ptr(d); | |
3080 | tcg_temp_free_ptr(n); | |
3081 | tcg_temp_free_ptr(m); | |
3082 | tcg_temp_free_ptr(g); | |
35da316f RH |
3083 | return true; |
3084 | } | |
3085 | ||
3086 | static bool do_brk2(DisasContext *s, arg_rpr_s *a, | |
3087 | gen_helper_gvec_3 *fn, gen_helper_gvec_flags_3 *fn_s) | |
3088 | { | |
3089 | if (!sve_access_check(s)) { | |
3090 | return true; | |
3091 | } | |
3092 | ||
3093 | unsigned vsz = pred_full_reg_size(s); | |
3094 | ||
3095 | /* Predicate sizes may be smaller and cannot use simd_desc. */ | |
3096 | TCGv_ptr d = tcg_temp_new_ptr(); | |
3097 | TCGv_ptr n = tcg_temp_new_ptr(); | |
3098 | TCGv_ptr g = tcg_temp_new_ptr(); | |
93418f1c | 3099 | TCGv_i32 desc = tcg_constant_i32(FIELD_DP32(0, PREDDESC, OPRSZ, vsz)); |
35da316f RH |
3100 | |
3101 | tcg_gen_addi_ptr(d, cpu_env, pred_full_reg_offset(s, a->rd)); | |
3102 | tcg_gen_addi_ptr(n, cpu_env, pred_full_reg_offset(s, a->rn)); | |
3103 | tcg_gen_addi_ptr(g, cpu_env, pred_full_reg_offset(s, a->pg)); | |
3104 | ||
3105 | if (a->s) { | |
93418f1c RH |
3106 | TCGv_i32 t = tcg_temp_new_i32(); |
3107 | fn_s(t, d, n, g, desc); | |
35da316f | 3108 | do_pred_flags(t); |
93418f1c | 3109 | tcg_temp_free_i32(t); |
35da316f | 3110 | } else { |
93418f1c | 3111 | fn(d, n, g, desc); |
35da316f RH |
3112 | } |
3113 | tcg_temp_free_ptr(d); | |
3114 | tcg_temp_free_ptr(n); | |
3115 | tcg_temp_free_ptr(g); | |
35da316f RH |
3116 | return true; |
3117 | } | |
3118 | ||
3a7be554 | 3119 | static bool trans_BRKPA(DisasContext *s, arg_rprr_s *a) |
35da316f RH |
3120 | { |
3121 | return do_brk3(s, a, gen_helper_sve_brkpa, gen_helper_sve_brkpas); | |
3122 | } | |
3123 | ||
3a7be554 | 3124 | static bool trans_BRKPB(DisasContext *s, arg_rprr_s *a) |
35da316f RH |
3125 | { |
3126 | return do_brk3(s, a, gen_helper_sve_brkpb, gen_helper_sve_brkpbs); | |
3127 | } | |
3128 | ||
3a7be554 | 3129 | static bool trans_BRKA_m(DisasContext *s, arg_rpr_s *a) |
35da316f RH |
3130 | { |
3131 | return do_brk2(s, a, gen_helper_sve_brka_m, gen_helper_sve_brkas_m); | |
3132 | } | |
3133 | ||
3a7be554 | 3134 | static bool trans_BRKB_m(DisasContext *s, arg_rpr_s *a) |
35da316f RH |
3135 | { |
3136 | return do_brk2(s, a, gen_helper_sve_brkb_m, gen_helper_sve_brkbs_m); | |
3137 | } | |
3138 | ||
3a7be554 | 3139 | static bool trans_BRKA_z(DisasContext *s, arg_rpr_s *a) |
35da316f RH |
3140 | { |
3141 | return do_brk2(s, a, gen_helper_sve_brka_z, gen_helper_sve_brkas_z); | |
3142 | } | |
3143 | ||
3a7be554 | 3144 | static bool trans_BRKB_z(DisasContext *s, arg_rpr_s *a) |
35da316f RH |
3145 | { |
3146 | return do_brk2(s, a, gen_helper_sve_brkb_z, gen_helper_sve_brkbs_z); | |
3147 | } | |
3148 | ||
3a7be554 | 3149 | static bool trans_BRKN(DisasContext *s, arg_rpr_s *a) |
35da316f RH |
3150 | { |
3151 | return do_brk2(s, a, gen_helper_sve_brkn, gen_helper_sve_brkns); | |
3152 | } | |
3153 | ||
9ee3a611 RH |
3154 | /* |
3155 | *** SVE Predicate Count Group | |
3156 | */ | |
3157 | ||
3158 | static void do_cntp(DisasContext *s, TCGv_i64 val, int esz, int pn, int pg) | |
3159 | { | |
3160 | unsigned psz = pred_full_reg_size(s); | |
3161 | ||
3162 | if (psz <= 8) { | |
3163 | uint64_t psz_mask; | |
3164 | ||
3165 | tcg_gen_ld_i64(val, cpu_env, pred_full_reg_offset(s, pn)); | |
3166 | if (pn != pg) { | |
3167 | TCGv_i64 g = tcg_temp_new_i64(); | |
3168 | tcg_gen_ld_i64(g, cpu_env, pred_full_reg_offset(s, pg)); | |
3169 | tcg_gen_and_i64(val, val, g); | |
3170 | tcg_temp_free_i64(g); | |
3171 | } | |
3172 | ||
3173 | /* Reduce the pred_esz_masks value simply to reduce the | |
3174 | * size of the code generated here. | |
3175 | */ | |
3176 | psz_mask = MAKE_64BIT_MASK(0, psz * 8); | |
3177 | tcg_gen_andi_i64(val, val, pred_esz_masks[esz] & psz_mask); | |
3178 | ||
3179 | tcg_gen_ctpop_i64(val, val); | |
3180 | } else { | |
3181 | TCGv_ptr t_pn = tcg_temp_new_ptr(); | |
3182 | TCGv_ptr t_pg = tcg_temp_new_ptr(); | |
f556a201 | 3183 | unsigned desc = 0; |
9ee3a611 | 3184 | |
f556a201 RH |
3185 | desc = FIELD_DP32(desc, PREDDESC, OPRSZ, psz); |
3186 | desc = FIELD_DP32(desc, PREDDESC, ESZ, esz); | |
9ee3a611 RH |
3187 | |
3188 | tcg_gen_addi_ptr(t_pn, cpu_env, pred_full_reg_offset(s, pn)); | |
3189 | tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, pg)); | |
9ee3a611 | 3190 | |
c6a59b55 | 3191 | gen_helper_sve_cntp(val, t_pn, t_pg, tcg_constant_i32(desc)); |
9ee3a611 RH |
3192 | tcg_temp_free_ptr(t_pn); |
3193 | tcg_temp_free_ptr(t_pg); | |
9ee3a611 RH |
3194 | } |
3195 | } | |
3196 | ||
3a7be554 | 3197 | static bool trans_CNTP(DisasContext *s, arg_CNTP *a) |
9ee3a611 RH |
3198 | { |
3199 | if (sve_access_check(s)) { | |
3200 | do_cntp(s, cpu_reg(s, a->rd), a->esz, a->rn, a->pg); | |
3201 | } | |
3202 | return true; | |
3203 | } | |
3204 | ||
3a7be554 | 3205 | static bool trans_INCDECP_r(DisasContext *s, arg_incdec_pred *a) |
9ee3a611 RH |
3206 | { |
3207 | if (sve_access_check(s)) { | |
3208 | TCGv_i64 reg = cpu_reg(s, a->rd); | |
3209 | TCGv_i64 val = tcg_temp_new_i64(); | |
3210 | ||
3211 | do_cntp(s, val, a->esz, a->pg, a->pg); | |
3212 | if (a->d) { | |
3213 | tcg_gen_sub_i64(reg, reg, val); | |
3214 | } else { | |
3215 | tcg_gen_add_i64(reg, reg, val); | |
3216 | } | |
3217 | tcg_temp_free_i64(val); | |
3218 | } | |
3219 | return true; | |
3220 | } | |
3221 | ||
3a7be554 | 3222 | static bool trans_INCDECP_z(DisasContext *s, arg_incdec2_pred *a) |
9ee3a611 RH |
3223 | { |
3224 | if (a->esz == 0) { | |
3225 | return false; | |
3226 | } | |
3227 | if (sve_access_check(s)) { | |
3228 | unsigned vsz = vec_full_reg_size(s); | |
3229 | TCGv_i64 val = tcg_temp_new_i64(); | |
3230 | GVecGen2sFn *gvec_fn = a->d ? tcg_gen_gvec_subs : tcg_gen_gvec_adds; | |
3231 | ||
3232 | do_cntp(s, val, a->esz, a->pg, a->pg); | |
3233 | gvec_fn(a->esz, vec_full_reg_offset(s, a->rd), | |
3234 | vec_full_reg_offset(s, a->rn), val, vsz, vsz); | |
3235 | } | |
3236 | return true; | |
3237 | } | |
3238 | ||
3a7be554 | 3239 | static bool trans_SINCDECP_r_32(DisasContext *s, arg_incdec_pred *a) |
9ee3a611 RH |
3240 | { |
3241 | if (sve_access_check(s)) { | |
3242 | TCGv_i64 reg = cpu_reg(s, a->rd); | |
3243 | TCGv_i64 val = tcg_temp_new_i64(); | |
3244 | ||
3245 | do_cntp(s, val, a->esz, a->pg, a->pg); | |
3246 | do_sat_addsub_32(reg, val, a->u, a->d); | |
3247 | } | |
3248 | return true; | |
3249 | } | |
3250 | ||
3a7be554 | 3251 | static bool trans_SINCDECP_r_64(DisasContext *s, arg_incdec_pred *a) |
9ee3a611 RH |
3252 | { |
3253 | if (sve_access_check(s)) { | |
3254 | TCGv_i64 reg = cpu_reg(s, a->rd); | |
3255 | TCGv_i64 val = tcg_temp_new_i64(); | |
3256 | ||
3257 | do_cntp(s, val, a->esz, a->pg, a->pg); | |
3258 | do_sat_addsub_64(reg, val, a->u, a->d); | |
3259 | } | |
3260 | return true; | |
3261 | } | |
3262 | ||
3a7be554 | 3263 | static bool trans_SINCDECP_z(DisasContext *s, arg_incdec2_pred *a) |
9ee3a611 RH |
3264 | { |
3265 | if (a->esz == 0) { | |
3266 | return false; | |
3267 | } | |
3268 | if (sve_access_check(s)) { | |
3269 | TCGv_i64 val = tcg_temp_new_i64(); | |
3270 | do_cntp(s, val, a->esz, a->pg, a->pg); | |
3271 | do_sat_addsub_vec(s, a->esz, a->rd, a->rn, val, a->u, a->d); | |
3272 | } | |
3273 | return true; | |
3274 | } | |
3275 | ||
caf1cefc RH |
3276 | /* |
3277 | *** SVE Integer Compare Scalars Group | |
3278 | */ | |
3279 | ||
3a7be554 | 3280 | static bool trans_CTERM(DisasContext *s, arg_CTERM *a) |
caf1cefc RH |
3281 | { |
3282 | if (!sve_access_check(s)) { | |
3283 | return true; | |
3284 | } | |
3285 | ||
3286 | TCGCond cond = (a->ne ? TCG_COND_NE : TCG_COND_EQ); | |
3287 | TCGv_i64 rn = read_cpu_reg(s, a->rn, a->sf); | |
3288 | TCGv_i64 rm = read_cpu_reg(s, a->rm, a->sf); | |
3289 | TCGv_i64 cmp = tcg_temp_new_i64(); | |
3290 | ||
3291 | tcg_gen_setcond_i64(cond, cmp, rn, rm); | |
3292 | tcg_gen_extrl_i64_i32(cpu_NF, cmp); | |
3293 | tcg_temp_free_i64(cmp); | |
3294 | ||
3295 | /* VF = !NF & !CF. */ | |
3296 | tcg_gen_xori_i32(cpu_VF, cpu_NF, 1); | |
3297 | tcg_gen_andc_i32(cpu_VF, cpu_VF, cpu_CF); | |
3298 | ||
3299 | /* Both NF and VF actually look at bit 31. */ | |
3300 | tcg_gen_neg_i32(cpu_NF, cpu_NF); | |
3301 | tcg_gen_neg_i32(cpu_VF, cpu_VF); | |
3302 | return true; | |
3303 | } | |
3304 | ||
3a7be554 | 3305 | static bool trans_WHILE(DisasContext *s, arg_WHILE *a) |
caf1cefc | 3306 | { |
bbd0968c | 3307 | TCGv_i64 op0, op1, t0, t1, tmax; |
4481bbf2 | 3308 | TCGv_i32 t2; |
caf1cefc | 3309 | TCGv_ptr ptr; |
e610906c RH |
3310 | unsigned vsz = vec_full_reg_size(s); |
3311 | unsigned desc = 0; | |
caf1cefc | 3312 | TCGCond cond; |
34688dbc RH |
3313 | uint64_t maxval; |
3314 | /* Note that GE/HS has a->eq == 0 and GT/HI has a->eq == 1. */ | |
3315 | bool eq = a->eq == a->lt; | |
caf1cefc | 3316 | |
34688dbc RH |
3317 | /* The greater-than conditions are all SVE2. */ |
3318 | if (!a->lt && !dc_isar_feature(aa64_sve2, s)) { | |
3319 | return false; | |
3320 | } | |
bbd0968c RH |
3321 | if (!sve_access_check(s)) { |
3322 | return true; | |
3323 | } | |
3324 | ||
3325 | op0 = read_cpu_reg(s, a->rn, 1); | |
3326 | op1 = read_cpu_reg(s, a->rm, 1); | |
3327 | ||
caf1cefc RH |
3328 | if (!a->sf) { |
3329 | if (a->u) { | |
3330 | tcg_gen_ext32u_i64(op0, op0); | |
3331 | tcg_gen_ext32u_i64(op1, op1); | |
3332 | } else { | |
3333 | tcg_gen_ext32s_i64(op0, op0); | |
3334 | tcg_gen_ext32s_i64(op1, op1); | |
3335 | } | |
3336 | } | |
3337 | ||
3338 | /* For the helper, compress the different conditions into a computation | |
3339 | * of how many iterations for which the condition is true. | |
caf1cefc | 3340 | */ |
bbd0968c RH |
3341 | t0 = tcg_temp_new_i64(); |
3342 | t1 = tcg_temp_new_i64(); | |
34688dbc RH |
3343 | |
3344 | if (a->lt) { | |
3345 | tcg_gen_sub_i64(t0, op1, op0); | |
3346 | if (a->u) { | |
3347 | maxval = a->sf ? UINT64_MAX : UINT32_MAX; | |
3348 | cond = eq ? TCG_COND_LEU : TCG_COND_LTU; | |
3349 | } else { | |
3350 | maxval = a->sf ? INT64_MAX : INT32_MAX; | |
3351 | cond = eq ? TCG_COND_LE : TCG_COND_LT; | |
3352 | } | |
3353 | } else { | |
3354 | tcg_gen_sub_i64(t0, op0, op1); | |
3355 | if (a->u) { | |
3356 | maxval = 0; | |
3357 | cond = eq ? TCG_COND_GEU : TCG_COND_GTU; | |
3358 | } else { | |
3359 | maxval = a->sf ? INT64_MIN : INT32_MIN; | |
3360 | cond = eq ? TCG_COND_GE : TCG_COND_GT; | |
3361 | } | |
3362 | } | |
caf1cefc | 3363 | |
4481bbf2 | 3364 | tmax = tcg_constant_i64(vsz >> a->esz); |
34688dbc | 3365 | if (eq) { |
caf1cefc RH |
3366 | /* Equality means one more iteration. */ |
3367 | tcg_gen_addi_i64(t0, t0, 1); | |
bbd0968c | 3368 | |
34688dbc RH |
3369 | /* |
3370 | * For the less-than while, if op1 is maxval (and the only time | |
3371 | * the addition above could overflow), then we produce an all-true | |
3372 | * predicate by setting the count to the vector length. This is | |
3373 | * because the pseudocode is described as an increment + compare | |
3374 | * loop, and the maximum integer would always compare true. | |
3375 | * Similarly, the greater-than while has the same issue with the | |
3376 | * minimum integer due to the decrement + compare loop. | |
bbd0968c | 3377 | */ |
34688dbc | 3378 | tcg_gen_movi_i64(t1, maxval); |
bbd0968c | 3379 | tcg_gen_movcond_i64(TCG_COND_EQ, t0, op1, t1, tmax, t0); |
caf1cefc RH |
3380 | } |
3381 | ||
bbd0968c RH |
3382 | /* Bound to the maximum. */ |
3383 | tcg_gen_umin_i64(t0, t0, tmax); | |
bbd0968c RH |
3384 | |
3385 | /* Set the count to zero if the condition is false. */ | |
caf1cefc RH |
3386 | tcg_gen_movi_i64(t1, 0); |
3387 | tcg_gen_movcond_i64(cond, t0, op0, op1, t0, t1); | |
bbd0968c | 3388 | tcg_temp_free_i64(t1); |
caf1cefc | 3389 | |
bbd0968c | 3390 | /* Since we're bounded, pass as a 32-bit type. */ |
caf1cefc RH |
3391 | t2 = tcg_temp_new_i32(); |
3392 | tcg_gen_extrl_i64_i32(t2, t0); | |
3393 | tcg_temp_free_i64(t0); | |
bbd0968c RH |
3394 | |
3395 | /* Scale elements to bits. */ | |
3396 | tcg_gen_shli_i32(t2, t2, a->esz); | |
caf1cefc | 3397 | |
e610906c RH |
3398 | desc = FIELD_DP32(desc, PREDDESC, OPRSZ, vsz / 8); |
3399 | desc = FIELD_DP32(desc, PREDDESC, ESZ, a->esz); | |
caf1cefc RH |
3400 | |
3401 | ptr = tcg_temp_new_ptr(); | |
3402 | tcg_gen_addi_ptr(ptr, cpu_env, pred_full_reg_offset(s, a->rd)); | |
3403 | ||
34688dbc | 3404 | if (a->lt) { |
4481bbf2 | 3405 | gen_helper_sve_whilel(t2, ptr, t2, tcg_constant_i32(desc)); |
34688dbc | 3406 | } else { |
4481bbf2 | 3407 | gen_helper_sve_whileg(t2, ptr, t2, tcg_constant_i32(desc)); |
34688dbc | 3408 | } |
caf1cefc RH |
3409 | do_pred_flags(t2); |
3410 | ||
3411 | tcg_temp_free_ptr(ptr); | |
3412 | tcg_temp_free_i32(t2); | |
caf1cefc RH |
3413 | return true; |
3414 | } | |
3415 | ||
14f6dad1 RH |
3416 | static bool trans_WHILE_ptr(DisasContext *s, arg_WHILE_ptr *a) |
3417 | { | |
3418 | TCGv_i64 op0, op1, diff, t1, tmax; | |
4481bbf2 | 3419 | TCGv_i32 t2; |
14f6dad1 RH |
3420 | TCGv_ptr ptr; |
3421 | unsigned vsz = vec_full_reg_size(s); | |
3422 | unsigned desc = 0; | |
3423 | ||
3424 | if (!dc_isar_feature(aa64_sve2, s)) { | |
3425 | return false; | |
3426 | } | |
3427 | if (!sve_access_check(s)) { | |
3428 | return true; | |
3429 | } | |
3430 | ||
3431 | op0 = read_cpu_reg(s, a->rn, 1); | |
3432 | op1 = read_cpu_reg(s, a->rm, 1); | |
3433 | ||
4481bbf2 | 3434 | tmax = tcg_constant_i64(vsz); |
14f6dad1 RH |
3435 | diff = tcg_temp_new_i64(); |
3436 | ||
3437 | if (a->rw) { | |
3438 | /* WHILERW */ | |
3439 | /* diff = abs(op1 - op0), noting that op0/1 are unsigned. */ | |
3440 | t1 = tcg_temp_new_i64(); | |
3441 | tcg_gen_sub_i64(diff, op0, op1); | |
3442 | tcg_gen_sub_i64(t1, op1, op0); | |
3443 | tcg_gen_movcond_i64(TCG_COND_GEU, diff, op0, op1, diff, t1); | |
3444 | tcg_temp_free_i64(t1); | |
3445 | /* Round down to a multiple of ESIZE. */ | |
3446 | tcg_gen_andi_i64(diff, diff, -1 << a->esz); | |
3447 | /* If op1 == op0, diff == 0, and the condition is always true. */ | |
3448 | tcg_gen_movcond_i64(TCG_COND_EQ, diff, op0, op1, tmax, diff); | |
3449 | } else { | |
3450 | /* WHILEWR */ | |
3451 | tcg_gen_sub_i64(diff, op1, op0); | |
3452 | /* Round down to a multiple of ESIZE. */ | |
3453 | tcg_gen_andi_i64(diff, diff, -1 << a->esz); | |
3454 | /* If op0 >= op1, diff <= 0, the condition is always true. */ | |
3455 | tcg_gen_movcond_i64(TCG_COND_GEU, diff, op0, op1, tmax, diff); | |
3456 | } | |
3457 | ||
3458 | /* Bound to the maximum. */ | |
3459 | tcg_gen_umin_i64(diff, diff, tmax); | |
14f6dad1 RH |
3460 | |
3461 | /* Since we're bounded, pass as a 32-bit type. */ | |
3462 | t2 = tcg_temp_new_i32(); | |
3463 | tcg_gen_extrl_i64_i32(t2, diff); | |
3464 | tcg_temp_free_i64(diff); | |
3465 | ||
3466 | desc = FIELD_DP32(desc, PREDDESC, OPRSZ, vsz / 8); | |
3467 | desc = FIELD_DP32(desc, PREDDESC, ESZ, a->esz); | |
14f6dad1 RH |
3468 | |
3469 | ptr = tcg_temp_new_ptr(); | |
3470 | tcg_gen_addi_ptr(ptr, cpu_env, pred_full_reg_offset(s, a->rd)); | |
3471 | ||
4481bbf2 | 3472 | gen_helper_sve_whilel(t2, ptr, t2, tcg_constant_i32(desc)); |
14f6dad1 RH |
3473 | do_pred_flags(t2); |
3474 | ||
3475 | tcg_temp_free_ptr(ptr); | |
3476 | tcg_temp_free_i32(t2); | |
14f6dad1 RH |
3477 | return true; |
3478 | } | |
3479 | ||
ed491961 RH |
3480 | /* |
3481 | *** SVE Integer Wide Immediate - Unpredicated Group | |
3482 | */ | |
3483 | ||
3a7be554 | 3484 | static bool trans_FDUP(DisasContext *s, arg_FDUP *a) |
ed491961 RH |
3485 | { |
3486 | if (a->esz == 0) { | |
3487 | return false; | |
3488 | } | |
3489 | if (sve_access_check(s)) { | |
3490 | unsigned vsz = vec_full_reg_size(s); | |
3491 | int dofs = vec_full_reg_offset(s, a->rd); | |
3492 | uint64_t imm; | |
3493 | ||
3494 | /* Decode the VFP immediate. */ | |
3495 | imm = vfp_expand_imm(a->esz, a->imm); | |
8711e71f | 3496 | tcg_gen_gvec_dup_imm(a->esz, dofs, vsz, vsz, imm); |
ed491961 RH |
3497 | } |
3498 | return true; | |
3499 | } | |
3500 | ||
3a7be554 | 3501 | static bool trans_DUP_i(DisasContext *s, arg_DUP_i *a) |
ed491961 | 3502 | { |
3a7be554 | 3503 | if (a->esz == 0 && extract32(s->insn, 13, 1)) { |
ed491961 RH |
3504 | return false; |
3505 | } | |
3506 | if (sve_access_check(s)) { | |
3507 | unsigned vsz = vec_full_reg_size(s); | |
3508 | int dofs = vec_full_reg_offset(s, a->rd); | |
3509 | ||
8711e71f | 3510 | tcg_gen_gvec_dup_imm(a->esz, dofs, vsz, vsz, a->imm); |
ed491961 RH |
3511 | } |
3512 | return true; | |
3513 | } | |
3514 | ||
3a7be554 | 3515 | static bool trans_ADD_zzi(DisasContext *s, arg_rri_esz *a) |
6e6a157d | 3516 | { |
3a7be554 | 3517 | if (a->esz == 0 && extract32(s->insn, 13, 1)) { |
6e6a157d RH |
3518 | return false; |
3519 | } | |
3520 | if (sve_access_check(s)) { | |
3521 | unsigned vsz = vec_full_reg_size(s); | |
3522 | tcg_gen_gvec_addi(a->esz, vec_full_reg_offset(s, a->rd), | |
3523 | vec_full_reg_offset(s, a->rn), a->imm, vsz, vsz); | |
3524 | } | |
3525 | return true; | |
3526 | } | |
3527 | ||
3a7be554 | 3528 | static bool trans_SUB_zzi(DisasContext *s, arg_rri_esz *a) |
6e6a157d RH |
3529 | { |
3530 | a->imm = -a->imm; | |
3a7be554 | 3531 | return trans_ADD_zzi(s, a); |
6e6a157d RH |
3532 | } |
3533 | ||
3a7be554 | 3534 | static bool trans_SUBR_zzi(DisasContext *s, arg_rri_esz *a) |
6e6a157d | 3535 | { |
53229a77 | 3536 | static const TCGOpcode vecop_list[] = { INDEX_op_sub_vec, 0 }; |
6e6a157d RH |
3537 | static const GVecGen2s op[4] = { |
3538 | { .fni8 = tcg_gen_vec_sub8_i64, | |
3539 | .fniv = tcg_gen_sub_vec, | |
3540 | .fno = gen_helper_sve_subri_b, | |
53229a77 | 3541 | .opt_opc = vecop_list, |
6e6a157d RH |
3542 | .vece = MO_8, |
3543 | .scalar_first = true }, | |
3544 | { .fni8 = tcg_gen_vec_sub16_i64, | |
3545 | .fniv = tcg_gen_sub_vec, | |
3546 | .fno = gen_helper_sve_subri_h, | |
53229a77 | 3547 | .opt_opc = vecop_list, |
6e6a157d RH |
3548 | .vece = MO_16, |
3549 | .scalar_first = true }, | |
3550 | { .fni4 = tcg_gen_sub_i32, | |
3551 | .fniv = tcg_gen_sub_vec, | |
3552 | .fno = gen_helper_sve_subri_s, | |
53229a77 | 3553 | .opt_opc = vecop_list, |
6e6a157d RH |
3554 | .vece = MO_32, |
3555 | .scalar_first = true }, | |
3556 | { .fni8 = tcg_gen_sub_i64, | |
3557 | .fniv = tcg_gen_sub_vec, | |
3558 | .fno = gen_helper_sve_subri_d, | |
53229a77 | 3559 | .opt_opc = vecop_list, |
6e6a157d RH |
3560 | .prefer_i64 = TCG_TARGET_REG_BITS == 64, |
3561 | .vece = MO_64, | |
3562 | .scalar_first = true } | |
3563 | }; | |
3564 | ||
3a7be554 | 3565 | if (a->esz == 0 && extract32(s->insn, 13, 1)) { |
6e6a157d RH |
3566 | return false; |
3567 | } | |
3568 | if (sve_access_check(s)) { | |
3569 | unsigned vsz = vec_full_reg_size(s); | |
6e6a157d RH |
3570 | tcg_gen_gvec_2s(vec_full_reg_offset(s, a->rd), |
3571 | vec_full_reg_offset(s, a->rn), | |
9fff3fcc | 3572 | vsz, vsz, tcg_constant_i64(a->imm), &op[a->esz]); |
6e6a157d RH |
3573 | } |
3574 | return true; | |
3575 | } | |
3576 | ||
3a7be554 | 3577 | static bool trans_MUL_zzi(DisasContext *s, arg_rri_esz *a) |
6e6a157d RH |
3578 | { |
3579 | if (sve_access_check(s)) { | |
3580 | unsigned vsz = vec_full_reg_size(s); | |
3581 | tcg_gen_gvec_muli(a->esz, vec_full_reg_offset(s, a->rd), | |
3582 | vec_full_reg_offset(s, a->rn), a->imm, vsz, vsz); | |
3583 | } | |
3584 | return true; | |
3585 | } | |
3586 | ||
3a7be554 | 3587 | static bool do_zzi_sat(DisasContext *s, arg_rri_esz *a, bool u, bool d) |
6e6a157d | 3588 | { |
3a7be554 | 3589 | if (a->esz == 0 && extract32(s->insn, 13, 1)) { |
6e6a157d RH |
3590 | return false; |
3591 | } | |
3592 | if (sve_access_check(s)) { | |
138a1f7b RH |
3593 | do_sat_addsub_vec(s, a->esz, a->rd, a->rn, |
3594 | tcg_constant_i64(a->imm), u, d); | |
6e6a157d RH |
3595 | } |
3596 | return true; | |
3597 | } | |
3598 | ||
3a7be554 | 3599 | static bool trans_SQADD_zzi(DisasContext *s, arg_rri_esz *a) |
6e6a157d | 3600 | { |
3a7be554 | 3601 | return do_zzi_sat(s, a, false, false); |
6e6a157d RH |
3602 | } |
3603 | ||
3a7be554 | 3604 | static bool trans_UQADD_zzi(DisasContext *s, arg_rri_esz *a) |
6e6a157d | 3605 | { |
3a7be554 | 3606 | return do_zzi_sat(s, a, true, false); |
6e6a157d RH |
3607 | } |
3608 | ||
3a7be554 | 3609 | static bool trans_SQSUB_zzi(DisasContext *s, arg_rri_esz *a) |
6e6a157d | 3610 | { |
3a7be554 | 3611 | return do_zzi_sat(s, a, false, true); |
6e6a157d RH |
3612 | } |
3613 | ||
3a7be554 | 3614 | static bool trans_UQSUB_zzi(DisasContext *s, arg_rri_esz *a) |
6e6a157d | 3615 | { |
3a7be554 | 3616 | return do_zzi_sat(s, a, true, true); |
6e6a157d RH |
3617 | } |
3618 | ||
3619 | static bool do_zzi_ool(DisasContext *s, arg_rri_esz *a, gen_helper_gvec_2i *fn) | |
3620 | { | |
3621 | if (sve_access_check(s)) { | |
3622 | unsigned vsz = vec_full_reg_size(s); | |
6e6a157d RH |
3623 | tcg_gen_gvec_2i_ool(vec_full_reg_offset(s, a->rd), |
3624 | vec_full_reg_offset(s, a->rn), | |
138a1f7b | 3625 | tcg_constant_i64(a->imm), vsz, vsz, 0, fn); |
6e6a157d RH |
3626 | } |
3627 | return true; | |
3628 | } | |
3629 | ||
3630 | #define DO_ZZI(NAME, name) \ | |
3a7be554 | 3631 | static bool trans_##NAME##_zzi(DisasContext *s, arg_rri_esz *a) \ |
6e6a157d RH |
3632 | { \ |
3633 | static gen_helper_gvec_2i * const fns[4] = { \ | |
3634 | gen_helper_sve_##name##i_b, gen_helper_sve_##name##i_h, \ | |
3635 | gen_helper_sve_##name##i_s, gen_helper_sve_##name##i_d, \ | |
3636 | }; \ | |
3637 | return do_zzi_ool(s, a, fns[a->esz]); \ | |
3638 | } | |
3639 | ||
3640 | DO_ZZI(SMAX, smax) | |
3641 | DO_ZZI(UMAX, umax) | |
3642 | DO_ZZI(SMIN, smin) | |
3643 | DO_ZZI(UMIN, umin) | |
3644 | ||
3645 | #undef DO_ZZI | |
3646 | ||
5f425b92 RH |
3647 | static gen_helper_gvec_4 * const dot_fns[2][2] = { |
3648 | { gen_helper_gvec_sdot_b, gen_helper_gvec_sdot_h }, | |
3649 | { gen_helper_gvec_udot_b, gen_helper_gvec_udot_h } | |
3650 | }; | |
3651 | TRANS_FEAT(DOT_zzzz, aa64_sve, gen_gvec_ool_zzzz, | |
3652 | dot_fns[a->u][a->sz], a->rd, a->rn, a->rm, a->ra, 0) | |
d730ecaa | 3653 | |
814d4c52 RH |
3654 | /* |
3655 | * SVE Multiply - Indexed | |
3656 | */ | |
3657 | ||
f3500a25 RH |
3658 | TRANS_FEAT(SDOT_zzxw_s, aa64_sve, gen_gvec_ool_arg_zzxz, |
3659 | gen_helper_gvec_sdot_idx_b, a) | |
3660 | TRANS_FEAT(SDOT_zzxw_d, aa64_sve, gen_gvec_ool_arg_zzxz, | |
3661 | gen_helper_gvec_sdot_idx_h, a) | |
3662 | TRANS_FEAT(UDOT_zzxw_s, aa64_sve, gen_gvec_ool_arg_zzxz, | |
3663 | gen_helper_gvec_udot_idx_b, a) | |
3664 | TRANS_FEAT(UDOT_zzxw_d, aa64_sve, gen_gvec_ool_arg_zzxz, | |
3665 | gen_helper_gvec_udot_idx_h, a) | |
3666 | ||
3667 | TRANS_FEAT(SUDOT_zzxw_s, aa64_sve_i8mm, gen_gvec_ool_arg_zzxz, | |
3668 | gen_helper_gvec_sudot_idx_b, a) | |
3669 | TRANS_FEAT(USDOT_zzxw_s, aa64_sve_i8mm, gen_gvec_ool_arg_zzxz, | |
3670 | gen_helper_gvec_usdot_idx_b, a) | |
16fcfdc7 | 3671 | |
814d4c52 | 3672 | #define DO_SVE2_RRX(NAME, FUNC) \ |
af031f64 RH |
3673 | TRANS_FEAT(NAME, aa64_sve, gen_gvec_ool_zzz, FUNC, \ |
3674 | a->rd, a->rn, a->rm, a->index) | |
814d4c52 | 3675 | |
af031f64 RH |
3676 | DO_SVE2_RRX(MUL_zzx_h, gen_helper_gvec_mul_idx_h) |
3677 | DO_SVE2_RRX(MUL_zzx_s, gen_helper_gvec_mul_idx_s) | |
3678 | DO_SVE2_RRX(MUL_zzx_d, gen_helper_gvec_mul_idx_d) | |
814d4c52 | 3679 | |
af031f64 RH |
3680 | DO_SVE2_RRX(SQDMULH_zzx_h, gen_helper_sve2_sqdmulh_idx_h) |
3681 | DO_SVE2_RRX(SQDMULH_zzx_s, gen_helper_sve2_sqdmulh_idx_s) | |
3682 | DO_SVE2_RRX(SQDMULH_zzx_d, gen_helper_sve2_sqdmulh_idx_d) | |
1aee2d70 | 3683 | |
af031f64 RH |
3684 | DO_SVE2_RRX(SQRDMULH_zzx_h, gen_helper_sve2_sqrdmulh_idx_h) |
3685 | DO_SVE2_RRX(SQRDMULH_zzx_s, gen_helper_sve2_sqrdmulh_idx_s) | |
3686 | DO_SVE2_RRX(SQRDMULH_zzx_d, gen_helper_sve2_sqrdmulh_idx_d) | |
1aee2d70 | 3687 | |
814d4c52 RH |
3688 | #undef DO_SVE2_RRX |
3689 | ||
b95f5eeb | 3690 | #define DO_SVE2_RRX_TB(NAME, FUNC, TOP) \ |
af031f64 RH |
3691 | TRANS_FEAT(NAME, aa64_sve, gen_gvec_ool_zzz, FUNC, \ |
3692 | a->rd, a->rn, a->rm, (a->index << 1) | TOP) | |
3693 | ||
3694 | DO_SVE2_RRX_TB(SQDMULLB_zzx_s, gen_helper_sve2_sqdmull_idx_s, false) | |
3695 | DO_SVE2_RRX_TB(SQDMULLB_zzx_d, gen_helper_sve2_sqdmull_idx_d, false) | |
3696 | DO_SVE2_RRX_TB(SQDMULLT_zzx_s, gen_helper_sve2_sqdmull_idx_s, true) | |
3697 | DO_SVE2_RRX_TB(SQDMULLT_zzx_d, gen_helper_sve2_sqdmull_idx_d, true) | |
3698 | ||
3699 | DO_SVE2_RRX_TB(SMULLB_zzx_s, gen_helper_sve2_smull_idx_s, false) | |
3700 | DO_SVE2_RRX_TB(SMULLB_zzx_d, gen_helper_sve2_smull_idx_d, false) | |
3701 | DO_SVE2_RRX_TB(SMULLT_zzx_s, gen_helper_sve2_smull_idx_s, true) | |
3702 | DO_SVE2_RRX_TB(SMULLT_zzx_d, gen_helper_sve2_smull_idx_d, true) | |
3703 | ||
3704 | DO_SVE2_RRX_TB(UMULLB_zzx_s, gen_helper_sve2_umull_idx_s, false) | |
3705 | DO_SVE2_RRX_TB(UMULLB_zzx_d, gen_helper_sve2_umull_idx_d, false) | |
3706 | DO_SVE2_RRX_TB(UMULLT_zzx_s, gen_helper_sve2_umull_idx_s, true) | |
3707 | DO_SVE2_RRX_TB(UMULLT_zzx_d, gen_helper_sve2_umull_idx_d, true) | |
d3949c4c | 3708 | |
b95f5eeb RH |
3709 | #undef DO_SVE2_RRX_TB |
3710 | ||
8a02aac7 | 3711 | #define DO_SVE2_RRXR(NAME, FUNC) \ |
8681eb76 | 3712 | TRANS_FEAT(NAME, aa64_sve2, gen_gvec_ool_arg_zzxz, FUNC, a) |
8a02aac7 | 3713 | |
8681eb76 RH |
3714 | DO_SVE2_RRXR(MLA_zzxz_h, gen_helper_gvec_mla_idx_h) |
3715 | DO_SVE2_RRXR(MLA_zzxz_s, gen_helper_gvec_mla_idx_s) | |
3716 | DO_SVE2_RRXR(MLA_zzxz_d, gen_helper_gvec_mla_idx_d) | |
8a02aac7 | 3717 | |
8681eb76 RH |
3718 | DO_SVE2_RRXR(MLS_zzxz_h, gen_helper_gvec_mls_idx_h) |
3719 | DO_SVE2_RRXR(MLS_zzxz_s, gen_helper_gvec_mls_idx_s) | |
3720 | DO_SVE2_RRXR(MLS_zzxz_d, gen_helper_gvec_mls_idx_d) | |
8a02aac7 | 3721 | |
8681eb76 RH |
3722 | DO_SVE2_RRXR(SQRDMLAH_zzxz_h, gen_helper_sve2_sqrdmlah_idx_h) |
3723 | DO_SVE2_RRXR(SQRDMLAH_zzxz_s, gen_helper_sve2_sqrdmlah_idx_s) | |
3724 | DO_SVE2_RRXR(SQRDMLAH_zzxz_d, gen_helper_sve2_sqrdmlah_idx_d) | |
75d6d5fc | 3725 | |
8681eb76 RH |
3726 | DO_SVE2_RRXR(SQRDMLSH_zzxz_h, gen_helper_sve2_sqrdmlsh_idx_h) |
3727 | DO_SVE2_RRXR(SQRDMLSH_zzxz_s, gen_helper_sve2_sqrdmlsh_idx_s) | |
3728 | DO_SVE2_RRXR(SQRDMLSH_zzxz_d, gen_helper_sve2_sqrdmlsh_idx_d) | |
75d6d5fc | 3729 | |
8a02aac7 RH |
3730 | #undef DO_SVE2_RRXR |
3731 | ||
c5c455d7 | 3732 | #define DO_SVE2_RRXR_TB(NAME, FUNC, TOP) \ |
8681eb76 RH |
3733 | TRANS_FEAT(NAME, aa64_sve2, gen_gvec_ool_zzzz, FUNC, \ |
3734 | a->rd, a->rn, a->rm, a->ra, (a->index << 1) | TOP) | |
3735 | ||
3736 | DO_SVE2_RRXR_TB(SQDMLALB_zzxw_s, gen_helper_sve2_sqdmlal_idx_s, false) | |
3737 | DO_SVE2_RRXR_TB(SQDMLALB_zzxw_d, gen_helper_sve2_sqdmlal_idx_d, false) | |
3738 | DO_SVE2_RRXR_TB(SQDMLALT_zzxw_s, gen_helper_sve2_sqdmlal_idx_s, true) | |
3739 | DO_SVE2_RRXR_TB(SQDMLALT_zzxw_d, gen_helper_sve2_sqdmlal_idx_d, true) | |
3740 | ||
3741 | DO_SVE2_RRXR_TB(SQDMLSLB_zzxw_s, gen_helper_sve2_sqdmlsl_idx_s, false) | |
3742 | DO_SVE2_RRXR_TB(SQDMLSLB_zzxw_d, gen_helper_sve2_sqdmlsl_idx_d, false) | |
3743 | DO_SVE2_RRXR_TB(SQDMLSLT_zzxw_s, gen_helper_sve2_sqdmlsl_idx_s, true) | |
3744 | DO_SVE2_RRXR_TB(SQDMLSLT_zzxw_d, gen_helper_sve2_sqdmlsl_idx_d, true) | |
3745 | ||
3746 | DO_SVE2_RRXR_TB(SMLALB_zzxw_s, gen_helper_sve2_smlal_idx_s, false) | |
3747 | DO_SVE2_RRXR_TB(SMLALB_zzxw_d, gen_helper_sve2_smlal_idx_d, false) | |
3748 | DO_SVE2_RRXR_TB(SMLALT_zzxw_s, gen_helper_sve2_smlal_idx_s, true) | |
3749 | DO_SVE2_RRXR_TB(SMLALT_zzxw_d, gen_helper_sve2_smlal_idx_d, true) | |
3750 | ||
3751 | DO_SVE2_RRXR_TB(UMLALB_zzxw_s, gen_helper_sve2_umlal_idx_s, false) | |
3752 | DO_SVE2_RRXR_TB(UMLALB_zzxw_d, gen_helper_sve2_umlal_idx_d, false) | |
3753 | DO_SVE2_RRXR_TB(UMLALT_zzxw_s, gen_helper_sve2_umlal_idx_s, true) | |
3754 | DO_SVE2_RRXR_TB(UMLALT_zzxw_d, gen_helper_sve2_umlal_idx_d, true) | |
3755 | ||
3756 | DO_SVE2_RRXR_TB(SMLSLB_zzxw_s, gen_helper_sve2_smlsl_idx_s, false) | |
3757 | DO_SVE2_RRXR_TB(SMLSLB_zzxw_d, gen_helper_sve2_smlsl_idx_d, false) | |
3758 | DO_SVE2_RRXR_TB(SMLSLT_zzxw_s, gen_helper_sve2_smlsl_idx_s, true) | |
3759 | DO_SVE2_RRXR_TB(SMLSLT_zzxw_d, gen_helper_sve2_smlsl_idx_d, true) | |
3760 | ||
3761 | DO_SVE2_RRXR_TB(UMLSLB_zzxw_s, gen_helper_sve2_umlsl_idx_s, false) | |
3762 | DO_SVE2_RRXR_TB(UMLSLB_zzxw_d, gen_helper_sve2_umlsl_idx_d, false) | |
3763 | DO_SVE2_RRXR_TB(UMLSLT_zzxw_s, gen_helper_sve2_umlsl_idx_s, true) | |
3764 | DO_SVE2_RRXR_TB(UMLSLT_zzxw_d, gen_helper_sve2_umlsl_idx_d, true) | |
c5c455d7 RH |
3765 | |
3766 | #undef DO_SVE2_RRXR_TB | |
3767 | ||
3b787ed8 | 3768 | #define DO_SVE2_RRXR_ROT(NAME, FUNC) \ |
8681eb76 RH |
3769 | TRANS_FEAT(NAME, aa64_sve2, gen_gvec_ool_zzzz, FUNC, \ |
3770 | a->rd, a->rn, a->rm, a->ra, (a->index << 2) | a->rot) | |
3b787ed8 RH |
3771 | |
3772 | DO_SVE2_RRXR_ROT(CMLA_zzxz_h, gen_helper_sve2_cmla_idx_h) | |
3773 | DO_SVE2_RRXR_ROT(CMLA_zzxz_s, gen_helper_sve2_cmla_idx_s) | |
3774 | ||
3775 | DO_SVE2_RRXR_ROT(SQRDCMLAH_zzxz_h, gen_helper_sve2_sqrdcmlah_idx_h) | |
3776 | DO_SVE2_RRXR_ROT(SQRDCMLAH_zzxz_s, gen_helper_sve2_sqrdcmlah_idx_s) | |
3777 | ||
21068f39 RH |
3778 | DO_SVE2_RRXR_ROT(CDOT_zzxw_s, gen_helper_sve2_cdot_idx_s) |
3779 | DO_SVE2_RRXR_ROT(CDOT_zzxw_d, gen_helper_sve2_cdot_idx_d) | |
3780 | ||
3b787ed8 RH |
3781 | #undef DO_SVE2_RRXR_ROT |
3782 | ||
ca40a6e6 RH |
3783 | /* |
3784 | *** SVE Floating Point Multiply-Add Indexed Group | |
3785 | */ | |
3786 | ||
0a82d963 | 3787 | static bool do_FMLA_zzxz(DisasContext *s, arg_rrxr_esz *a, bool sub) |
ca40a6e6 RH |
3788 | { |
3789 | static gen_helper_gvec_4_ptr * const fns[3] = { | |
3790 | gen_helper_gvec_fmla_idx_h, | |
3791 | gen_helper_gvec_fmla_idx_s, | |
3792 | gen_helper_gvec_fmla_idx_d, | |
3793 | }; | |
3794 | ||
3795 | if (sve_access_check(s)) { | |
3796 | unsigned vsz = vec_full_reg_size(s); | |
cdfb22bb | 3797 | TCGv_ptr status = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR); |
ca40a6e6 RH |
3798 | tcg_gen_gvec_4_ptr(vec_full_reg_offset(s, a->rd), |
3799 | vec_full_reg_offset(s, a->rn), | |
3800 | vec_full_reg_offset(s, a->rm), | |
3801 | vec_full_reg_offset(s, a->ra), | |
0a82d963 | 3802 | status, vsz, vsz, (a->index << 1) | sub, |
ca40a6e6 RH |
3803 | fns[a->esz - 1]); |
3804 | tcg_temp_free_ptr(status); | |
3805 | } | |
3806 | return true; | |
3807 | } | |
3808 | ||
0a82d963 RH |
3809 | static bool trans_FMLA_zzxz(DisasContext *s, arg_FMLA_zzxz *a) |
3810 | { | |
3811 | return do_FMLA_zzxz(s, a, false); | |
3812 | } | |
3813 | ||
3814 | static bool trans_FMLS_zzxz(DisasContext *s, arg_FMLA_zzxz *a) | |
3815 | { | |
3816 | return do_FMLA_zzxz(s, a, true); | |
3817 | } | |
3818 | ||
ca40a6e6 RH |
3819 | /* |
3820 | *** SVE Floating Point Multiply Indexed Group | |
3821 | */ | |
3822 | ||
3a7be554 | 3823 | static bool trans_FMUL_zzx(DisasContext *s, arg_FMUL_zzx *a) |
ca40a6e6 RH |
3824 | { |
3825 | static gen_helper_gvec_3_ptr * const fns[3] = { | |
3826 | gen_helper_gvec_fmul_idx_h, | |
3827 | gen_helper_gvec_fmul_idx_s, | |
3828 | gen_helper_gvec_fmul_idx_d, | |
3829 | }; | |
3830 | ||
3831 | if (sve_access_check(s)) { | |
3832 | unsigned vsz = vec_full_reg_size(s); | |
cdfb22bb | 3833 | TCGv_ptr status = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR); |
ca40a6e6 RH |
3834 | tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, a->rd), |
3835 | vec_full_reg_offset(s, a->rn), | |
3836 | vec_full_reg_offset(s, a->rm), | |
3837 | status, vsz, vsz, a->index, fns[a->esz - 1]); | |
3838 | tcg_temp_free_ptr(status); | |
3839 | } | |
3840 | return true; | |
3841 | } | |
3842 | ||
23fbe79f RH |
3843 | /* |
3844 | *** SVE Floating Point Fast Reduction Group | |
3845 | */ | |
3846 | ||
3847 | typedef void gen_helper_fp_reduce(TCGv_i64, TCGv_ptr, TCGv_ptr, | |
3848 | TCGv_ptr, TCGv_i32); | |
3849 | ||
3850 | static void do_reduce(DisasContext *s, arg_rpr_esz *a, | |
3851 | gen_helper_fp_reduce *fn) | |
3852 | { | |
3853 | unsigned vsz = vec_full_reg_size(s); | |
3854 | unsigned p2vsz = pow2ceil(vsz); | |
c6a59b55 | 3855 | TCGv_i32 t_desc = tcg_constant_i32(simd_desc(vsz, vsz, p2vsz)); |
23fbe79f RH |
3856 | TCGv_ptr t_zn, t_pg, status; |
3857 | TCGv_i64 temp; | |
3858 | ||
3859 | temp = tcg_temp_new_i64(); | |
3860 | t_zn = tcg_temp_new_ptr(); | |
3861 | t_pg = tcg_temp_new_ptr(); | |
3862 | ||
3863 | tcg_gen_addi_ptr(t_zn, cpu_env, vec_full_reg_offset(s, a->rn)); | |
3864 | tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, a->pg)); | |
cdfb22bb | 3865 | status = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR); |
23fbe79f RH |
3866 | |
3867 | fn(temp, t_zn, t_pg, status, t_desc); | |
3868 | tcg_temp_free_ptr(t_zn); | |
3869 | tcg_temp_free_ptr(t_pg); | |
3870 | tcg_temp_free_ptr(status); | |
23fbe79f RH |
3871 | |
3872 | write_fp_dreg(s, a->rd, temp); | |
3873 | tcg_temp_free_i64(temp); | |
3874 | } | |
3875 | ||
3876 | #define DO_VPZ(NAME, name) \ | |
3a7be554 | 3877 | static bool trans_##NAME(DisasContext *s, arg_rpr_esz *a) \ |
23fbe79f RH |
3878 | { \ |
3879 | static gen_helper_fp_reduce * const fns[3] = { \ | |
3880 | gen_helper_sve_##name##_h, \ | |
3881 | gen_helper_sve_##name##_s, \ | |
3882 | gen_helper_sve_##name##_d, \ | |
3883 | }; \ | |
3884 | if (a->esz == 0) { \ | |
3885 | return false; \ | |
3886 | } \ | |
3887 | if (sve_access_check(s)) { \ | |
3888 | do_reduce(s, a, fns[a->esz - 1]); \ | |
3889 | } \ | |
3890 | return true; \ | |
3891 | } | |
3892 | ||
3893 | DO_VPZ(FADDV, faddv) | |
3894 | DO_VPZ(FMINNMV, fminnmv) | |
3895 | DO_VPZ(FMAXNMV, fmaxnmv) | |
3896 | DO_VPZ(FMINV, fminv) | |
3897 | DO_VPZ(FMAXV, fmaxv) | |
3898 | ||
3887c038 RH |
3899 | /* |
3900 | *** SVE Floating Point Unary Operations - Unpredicated Group | |
3901 | */ | |
3902 | ||
3903 | static void do_zz_fp(DisasContext *s, arg_rr_esz *a, gen_helper_gvec_2_ptr *fn) | |
3904 | { | |
3905 | unsigned vsz = vec_full_reg_size(s); | |
cdfb22bb | 3906 | TCGv_ptr status = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR); |
3887c038 RH |
3907 | |
3908 | tcg_gen_gvec_2_ptr(vec_full_reg_offset(s, a->rd), | |
3909 | vec_full_reg_offset(s, a->rn), | |
3910 | status, vsz, vsz, 0, fn); | |
3911 | tcg_temp_free_ptr(status); | |
3912 | } | |
3913 | ||
3a7be554 | 3914 | static bool trans_FRECPE(DisasContext *s, arg_rr_esz *a) |
3887c038 RH |
3915 | { |
3916 | static gen_helper_gvec_2_ptr * const fns[3] = { | |
3917 | gen_helper_gvec_frecpe_h, | |
3918 | gen_helper_gvec_frecpe_s, | |
3919 | gen_helper_gvec_frecpe_d, | |
3920 | }; | |
3921 | if (a->esz == 0) { | |
3922 | return false; | |
3923 | } | |
3924 | if (sve_access_check(s)) { | |
3925 | do_zz_fp(s, a, fns[a->esz - 1]); | |
3926 | } | |
3927 | return true; | |
3928 | } | |
3929 | ||
3a7be554 | 3930 | static bool trans_FRSQRTE(DisasContext *s, arg_rr_esz *a) |
3887c038 RH |
3931 | { |
3932 | static gen_helper_gvec_2_ptr * const fns[3] = { | |
3933 | gen_helper_gvec_frsqrte_h, | |
3934 | gen_helper_gvec_frsqrte_s, | |
3935 | gen_helper_gvec_frsqrte_d, | |
3936 | }; | |
3937 | if (a->esz == 0) { | |
3938 | return false; | |
3939 | } | |
3940 | if (sve_access_check(s)) { | |
3941 | do_zz_fp(s, a, fns[a->esz - 1]); | |
3942 | } | |
3943 | return true; | |
3944 | } | |
3945 | ||
4d2e2a03 RH |
3946 | /* |
3947 | *** SVE Floating Point Compare with Zero Group | |
3948 | */ | |
3949 | ||
3950 | static void do_ppz_fp(DisasContext *s, arg_rpr_esz *a, | |
3951 | gen_helper_gvec_3_ptr *fn) | |
3952 | { | |
3953 | unsigned vsz = vec_full_reg_size(s); | |
cdfb22bb | 3954 | TCGv_ptr status = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR); |
4d2e2a03 RH |
3955 | |
3956 | tcg_gen_gvec_3_ptr(pred_full_reg_offset(s, a->rd), | |
3957 | vec_full_reg_offset(s, a->rn), | |
3958 | pred_full_reg_offset(s, a->pg), | |
3959 | status, vsz, vsz, 0, fn); | |
3960 | tcg_temp_free_ptr(status); | |
3961 | } | |
3962 | ||
3963 | #define DO_PPZ(NAME, name) \ | |
3a7be554 | 3964 | static bool trans_##NAME(DisasContext *s, arg_rpr_esz *a) \ |
4d2e2a03 RH |
3965 | { \ |
3966 | static gen_helper_gvec_3_ptr * const fns[3] = { \ | |
3967 | gen_helper_sve_##name##_h, \ | |
3968 | gen_helper_sve_##name##_s, \ | |
3969 | gen_helper_sve_##name##_d, \ | |
3970 | }; \ | |
3971 | if (a->esz == 0) { \ | |
3972 | return false; \ | |
3973 | } \ | |
3974 | if (sve_access_check(s)) { \ | |
3975 | do_ppz_fp(s, a, fns[a->esz - 1]); \ | |
3976 | } \ | |
3977 | return true; \ | |
3978 | } | |
3979 | ||
3980 | DO_PPZ(FCMGE_ppz0, fcmge0) | |
3981 | DO_PPZ(FCMGT_ppz0, fcmgt0) | |
3982 | DO_PPZ(FCMLE_ppz0, fcmle0) | |
3983 | DO_PPZ(FCMLT_ppz0, fcmlt0) | |
3984 | DO_PPZ(FCMEQ_ppz0, fcmeq0) | |
3985 | DO_PPZ(FCMNE_ppz0, fcmne0) | |
3986 | ||
3987 | #undef DO_PPZ | |
3988 | ||
67fcd9ad RH |
3989 | /* |
3990 | *** SVE floating-point trig multiply-add coefficient | |
3991 | */ | |
3992 | ||
3a7be554 | 3993 | static bool trans_FTMAD(DisasContext *s, arg_FTMAD *a) |
67fcd9ad RH |
3994 | { |
3995 | static gen_helper_gvec_3_ptr * const fns[3] = { | |
3996 | gen_helper_sve_ftmad_h, | |
3997 | gen_helper_sve_ftmad_s, | |
3998 | gen_helper_sve_ftmad_d, | |
3999 | }; | |
4000 | ||
4001 | if (a->esz == 0) { | |
4002 | return false; | |
4003 | } | |
4004 | if (sve_access_check(s)) { | |
4005 | unsigned vsz = vec_full_reg_size(s); | |
cdfb22bb | 4006 | TCGv_ptr status = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR); |
67fcd9ad RH |
4007 | tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, a->rd), |
4008 | vec_full_reg_offset(s, a->rn), | |
4009 | vec_full_reg_offset(s, a->rm), | |
4010 | status, vsz, vsz, a->imm, fns[a->esz - 1]); | |
4011 | tcg_temp_free_ptr(status); | |
4012 | } | |
4013 | return true; | |
4014 | } | |
4015 | ||
7f9ddf64 RH |
4016 | /* |
4017 | *** SVE Floating Point Accumulating Reduction Group | |
4018 | */ | |
4019 | ||
3a7be554 | 4020 | static bool trans_FADDA(DisasContext *s, arg_rprr_esz *a) |
7f9ddf64 RH |
4021 | { |
4022 | typedef void fadda_fn(TCGv_i64, TCGv_i64, TCGv_ptr, | |
4023 | TCGv_ptr, TCGv_ptr, TCGv_i32); | |
4024 | static fadda_fn * const fns[3] = { | |
4025 | gen_helper_sve_fadda_h, | |
4026 | gen_helper_sve_fadda_s, | |
4027 | gen_helper_sve_fadda_d, | |
4028 | }; | |
4029 | unsigned vsz = vec_full_reg_size(s); | |
4030 | TCGv_ptr t_rm, t_pg, t_fpst; | |
4031 | TCGv_i64 t_val; | |
4032 | TCGv_i32 t_desc; | |
4033 | ||
4034 | if (a->esz == 0) { | |
4035 | return false; | |
4036 | } | |
4037 | if (!sve_access_check(s)) { | |
4038 | return true; | |
4039 | } | |
4040 | ||
4041 | t_val = load_esz(cpu_env, vec_reg_offset(s, a->rn, 0, a->esz), a->esz); | |
4042 | t_rm = tcg_temp_new_ptr(); | |
4043 | t_pg = tcg_temp_new_ptr(); | |
4044 | tcg_gen_addi_ptr(t_rm, cpu_env, vec_full_reg_offset(s, a->rm)); | |
4045 | tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, a->pg)); | |
cdfb22bb | 4046 | t_fpst = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR); |
c6a59b55 | 4047 | t_desc = tcg_constant_i32(simd_desc(vsz, vsz, 0)); |
7f9ddf64 RH |
4048 | |
4049 | fns[a->esz - 1](t_val, t_val, t_rm, t_pg, t_fpst, t_desc); | |
4050 | ||
7f9ddf64 RH |
4051 | tcg_temp_free_ptr(t_fpst); |
4052 | tcg_temp_free_ptr(t_pg); | |
4053 | tcg_temp_free_ptr(t_rm); | |
4054 | ||
4055 | write_fp_dreg(s, a->rd, t_val); | |
4056 | tcg_temp_free_i64(t_val); | |
4057 | return true; | |
4058 | } | |
4059 | ||
29b80469 RH |
4060 | /* |
4061 | *** SVE Floating Point Arithmetic - Unpredicated Group | |
4062 | */ | |
4063 | ||
4064 | static bool do_zzz_fp(DisasContext *s, arg_rrr_esz *a, | |
4065 | gen_helper_gvec_3_ptr *fn) | |
4066 | { | |
4067 | if (fn == NULL) { | |
4068 | return false; | |
4069 | } | |
4070 | if (sve_access_check(s)) { | |
4071 | unsigned vsz = vec_full_reg_size(s); | |
cdfb22bb | 4072 | TCGv_ptr status = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR); |
29b80469 RH |
4073 | tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, a->rd), |
4074 | vec_full_reg_offset(s, a->rn), | |
4075 | vec_full_reg_offset(s, a->rm), | |
4076 | status, vsz, vsz, 0, fn); | |
4077 | tcg_temp_free_ptr(status); | |
4078 | } | |
4079 | return true; | |
4080 | } | |
4081 | ||
4082 | ||
4083 | #define DO_FP3(NAME, name) \ | |
3a7be554 | 4084 | static bool trans_##NAME(DisasContext *s, arg_rrr_esz *a) \ |
29b80469 RH |
4085 | { \ |
4086 | static gen_helper_gvec_3_ptr * const fns[4] = { \ | |
4087 | NULL, gen_helper_gvec_##name##_h, \ | |
4088 | gen_helper_gvec_##name##_s, gen_helper_gvec_##name##_d \ | |
4089 | }; \ | |
4090 | return do_zzz_fp(s, a, fns[a->esz]); \ | |
4091 | } | |
4092 | ||
4093 | DO_FP3(FADD_zzz, fadd) | |
4094 | DO_FP3(FSUB_zzz, fsub) | |
4095 | DO_FP3(FMUL_zzz, fmul) | |
4096 | DO_FP3(FTSMUL, ftsmul) | |
4097 | DO_FP3(FRECPS, recps) | |
4098 | DO_FP3(FRSQRTS, rsqrts) | |
4099 | ||
4100 | #undef DO_FP3 | |
4101 | ||
ec3b87c2 RH |
4102 | /* |
4103 | *** SVE Floating Point Arithmetic - Predicated Group | |
4104 | */ | |
4105 | ||
4106 | static bool do_zpzz_fp(DisasContext *s, arg_rprr_esz *a, | |
4107 | gen_helper_gvec_4_ptr *fn) | |
4108 | { | |
4109 | if (fn == NULL) { | |
4110 | return false; | |
4111 | } | |
4112 | if (sve_access_check(s)) { | |
4113 | unsigned vsz = vec_full_reg_size(s); | |
cdfb22bb | 4114 | TCGv_ptr status = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR); |
ec3b87c2 RH |
4115 | tcg_gen_gvec_4_ptr(vec_full_reg_offset(s, a->rd), |
4116 | vec_full_reg_offset(s, a->rn), | |
4117 | vec_full_reg_offset(s, a->rm), | |
4118 | pred_full_reg_offset(s, a->pg), | |
4119 | status, vsz, vsz, 0, fn); | |
4120 | tcg_temp_free_ptr(status); | |
4121 | } | |
4122 | return true; | |
4123 | } | |
4124 | ||
4125 | #define DO_FP3(NAME, name) \ | |
3a7be554 | 4126 | static bool trans_##NAME(DisasContext *s, arg_rprr_esz *a) \ |
ec3b87c2 RH |
4127 | { \ |
4128 | static gen_helper_gvec_4_ptr * const fns[4] = { \ | |
4129 | NULL, gen_helper_sve_##name##_h, \ | |
4130 | gen_helper_sve_##name##_s, gen_helper_sve_##name##_d \ | |
4131 | }; \ | |
4132 | return do_zpzz_fp(s, a, fns[a->esz]); \ | |
4133 | } | |
4134 | ||
4135 | DO_FP3(FADD_zpzz, fadd) | |
4136 | DO_FP3(FSUB_zpzz, fsub) | |
4137 | DO_FP3(FMUL_zpzz, fmul) | |
4138 | DO_FP3(FMIN_zpzz, fmin) | |
4139 | DO_FP3(FMAX_zpzz, fmax) | |
4140 | DO_FP3(FMINNM_zpzz, fminnum) | |
4141 | DO_FP3(FMAXNM_zpzz, fmaxnum) | |
4142 | DO_FP3(FABD, fabd) | |
4143 | DO_FP3(FSCALE, fscalbn) | |
4144 | DO_FP3(FDIV, fdiv) | |
4145 | DO_FP3(FMULX, fmulx) | |
4146 | ||
4147 | #undef DO_FP3 | |
8092c6a3 | 4148 | |
cc48affe RH |
4149 | typedef void gen_helper_sve_fp2scalar(TCGv_ptr, TCGv_ptr, TCGv_ptr, |
4150 | TCGv_i64, TCGv_ptr, TCGv_i32); | |
4151 | ||
4152 | static void do_fp_scalar(DisasContext *s, int zd, int zn, int pg, bool is_fp16, | |
4153 | TCGv_i64 scalar, gen_helper_sve_fp2scalar *fn) | |
4154 | { | |
4155 | unsigned vsz = vec_full_reg_size(s); | |
4156 | TCGv_ptr t_zd, t_zn, t_pg, status; | |
4157 | TCGv_i32 desc; | |
4158 | ||
4159 | t_zd = tcg_temp_new_ptr(); | |
4160 | t_zn = tcg_temp_new_ptr(); | |
4161 | t_pg = tcg_temp_new_ptr(); | |
4162 | tcg_gen_addi_ptr(t_zd, cpu_env, vec_full_reg_offset(s, zd)); | |
4163 | tcg_gen_addi_ptr(t_zn, cpu_env, vec_full_reg_offset(s, zn)); | |
4164 | tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, pg)); | |
4165 | ||
cdfb22bb | 4166 | status = fpstatus_ptr(is_fp16 ? FPST_FPCR_F16 : FPST_FPCR); |
c6a59b55 | 4167 | desc = tcg_constant_i32(simd_desc(vsz, vsz, 0)); |
cc48affe RH |
4168 | fn(t_zd, t_zn, t_pg, scalar, status, desc); |
4169 | ||
cc48affe RH |
4170 | tcg_temp_free_ptr(status); |
4171 | tcg_temp_free_ptr(t_pg); | |
4172 | tcg_temp_free_ptr(t_zn); | |
4173 | tcg_temp_free_ptr(t_zd); | |
4174 | } | |
4175 | ||
4176 | static void do_fp_imm(DisasContext *s, arg_rpri_esz *a, uint64_t imm, | |
4177 | gen_helper_sve_fp2scalar *fn) | |
4178 | { | |
138a1f7b RH |
4179 | do_fp_scalar(s, a->rd, a->rn, a->pg, a->esz == MO_16, |
4180 | tcg_constant_i64(imm), fn); | |
cc48affe RH |
4181 | } |
4182 | ||
4183 | #define DO_FP_IMM(NAME, name, const0, const1) \ | |
3a7be554 | 4184 | static bool trans_##NAME##_zpzi(DisasContext *s, arg_rpri_esz *a) \ |
cc48affe RH |
4185 | { \ |
4186 | static gen_helper_sve_fp2scalar * const fns[3] = { \ | |
4187 | gen_helper_sve_##name##_h, \ | |
4188 | gen_helper_sve_##name##_s, \ | |
4189 | gen_helper_sve_##name##_d \ | |
4190 | }; \ | |
4191 | static uint64_t const val[3][2] = { \ | |
4192 | { float16_##const0, float16_##const1 }, \ | |
4193 | { float32_##const0, float32_##const1 }, \ | |
4194 | { float64_##const0, float64_##const1 }, \ | |
4195 | }; \ | |
4196 | if (a->esz == 0) { \ | |
4197 | return false; \ | |
4198 | } \ | |
4199 | if (sve_access_check(s)) { \ | |
4200 | do_fp_imm(s, a, val[a->esz - 1][a->imm], fns[a->esz - 1]); \ | |
4201 | } \ | |
4202 | return true; \ | |
4203 | } | |
4204 | ||
cc48affe RH |
4205 | DO_FP_IMM(FADD, fadds, half, one) |
4206 | DO_FP_IMM(FSUB, fsubs, half, one) | |
4207 | DO_FP_IMM(FMUL, fmuls, half, two) | |
4208 | DO_FP_IMM(FSUBR, fsubrs, half, one) | |
4209 | DO_FP_IMM(FMAXNM, fmaxnms, zero, one) | |
4210 | DO_FP_IMM(FMINNM, fminnms, zero, one) | |
4211 | DO_FP_IMM(FMAX, fmaxs, zero, one) | |
4212 | DO_FP_IMM(FMIN, fmins, zero, one) | |
4213 | ||
4214 | #undef DO_FP_IMM | |
4215 | ||
abfdefd5 RH |
4216 | static bool do_fp_cmp(DisasContext *s, arg_rprr_esz *a, |
4217 | gen_helper_gvec_4_ptr *fn) | |
4218 | { | |
4219 | if (fn == NULL) { | |
4220 | return false; | |
4221 | } | |
4222 | if (sve_access_check(s)) { | |
4223 | unsigned vsz = vec_full_reg_size(s); | |
cdfb22bb | 4224 | TCGv_ptr status = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR); |
abfdefd5 RH |
4225 | tcg_gen_gvec_4_ptr(pred_full_reg_offset(s, a->rd), |
4226 | vec_full_reg_offset(s, a->rn), | |
4227 | vec_full_reg_offset(s, a->rm), | |
4228 | pred_full_reg_offset(s, a->pg), | |
4229 | status, vsz, vsz, 0, fn); | |
4230 | tcg_temp_free_ptr(status); | |
4231 | } | |
4232 | return true; | |
4233 | } | |
4234 | ||
4235 | #define DO_FPCMP(NAME, name) \ | |
3a7be554 | 4236 | static bool trans_##NAME##_ppzz(DisasContext *s, arg_rprr_esz *a) \ |
abfdefd5 RH |
4237 | { \ |
4238 | static gen_helper_gvec_4_ptr * const fns[4] = { \ | |
4239 | NULL, gen_helper_sve_##name##_h, \ | |
4240 | gen_helper_sve_##name##_s, gen_helper_sve_##name##_d \ | |
4241 | }; \ | |
4242 | return do_fp_cmp(s, a, fns[a->esz]); \ | |
4243 | } | |
4244 | ||
4245 | DO_FPCMP(FCMGE, fcmge) | |
4246 | DO_FPCMP(FCMGT, fcmgt) | |
4247 | DO_FPCMP(FCMEQ, fcmeq) | |
4248 | DO_FPCMP(FCMNE, fcmne) | |
4249 | DO_FPCMP(FCMUO, fcmuo) | |
4250 | DO_FPCMP(FACGE, facge) | |
4251 | DO_FPCMP(FACGT, facgt) | |
4252 | ||
4253 | #undef DO_FPCMP | |
4254 | ||
3a7be554 | 4255 | static bool trans_FCADD(DisasContext *s, arg_FCADD *a) |
76a9d9cd RH |
4256 | { |
4257 | static gen_helper_gvec_4_ptr * const fns[3] = { | |
4258 | gen_helper_sve_fcadd_h, | |
4259 | gen_helper_sve_fcadd_s, | |
4260 | gen_helper_sve_fcadd_d | |
4261 | }; | |
4262 | ||
4263 | if (a->esz == 0) { | |
4264 | return false; | |
4265 | } | |
4266 | if (sve_access_check(s)) { | |
4267 | unsigned vsz = vec_full_reg_size(s); | |
cdfb22bb | 4268 | TCGv_ptr status = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR); |
76a9d9cd RH |
4269 | tcg_gen_gvec_4_ptr(vec_full_reg_offset(s, a->rd), |
4270 | vec_full_reg_offset(s, a->rn), | |
4271 | vec_full_reg_offset(s, a->rm), | |
4272 | pred_full_reg_offset(s, a->pg), | |
4273 | status, vsz, vsz, a->rot, fns[a->esz - 1]); | |
4274 | tcg_temp_free_ptr(status); | |
4275 | } | |
4276 | return true; | |
4277 | } | |
4278 | ||
08975da9 RH |
4279 | static bool do_fmla(DisasContext *s, arg_rprrr_esz *a, |
4280 | gen_helper_gvec_5_ptr *fn) | |
6ceabaad | 4281 | { |
08975da9 | 4282 | if (a->esz == 0) { |
6ceabaad RH |
4283 | return false; |
4284 | } | |
08975da9 RH |
4285 | if (sve_access_check(s)) { |
4286 | unsigned vsz = vec_full_reg_size(s); | |
cdfb22bb | 4287 | TCGv_ptr status = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR); |
08975da9 RH |
4288 | tcg_gen_gvec_5_ptr(vec_full_reg_offset(s, a->rd), |
4289 | vec_full_reg_offset(s, a->rn), | |
4290 | vec_full_reg_offset(s, a->rm), | |
4291 | vec_full_reg_offset(s, a->ra), | |
4292 | pred_full_reg_offset(s, a->pg), | |
4293 | status, vsz, vsz, 0, fn); | |
4294 | tcg_temp_free_ptr(status); | |
6ceabaad | 4295 | } |
6ceabaad RH |
4296 | return true; |
4297 | } | |
4298 | ||
4299 | #define DO_FMLA(NAME, name) \ | |
3a7be554 | 4300 | static bool trans_##NAME(DisasContext *s, arg_rprrr_esz *a) \ |
6ceabaad | 4301 | { \ |
08975da9 | 4302 | static gen_helper_gvec_5_ptr * const fns[4] = { \ |
6ceabaad RH |
4303 | NULL, gen_helper_sve_##name##_h, \ |
4304 | gen_helper_sve_##name##_s, gen_helper_sve_##name##_d \ | |
4305 | }; \ | |
4306 | return do_fmla(s, a, fns[a->esz]); \ | |
4307 | } | |
4308 | ||
4309 | DO_FMLA(FMLA_zpzzz, fmla_zpzzz) | |
4310 | DO_FMLA(FMLS_zpzzz, fmls_zpzzz) | |
4311 | DO_FMLA(FNMLA_zpzzz, fnmla_zpzzz) | |
4312 | DO_FMLA(FNMLS_zpzzz, fnmls_zpzzz) | |
4313 | ||
4314 | #undef DO_FMLA | |
4315 | ||
3a7be554 | 4316 | static bool trans_FCMLA_zpzzz(DisasContext *s, arg_FCMLA_zpzzz *a) |
05f48bab | 4317 | { |
08975da9 RH |
4318 | static gen_helper_gvec_5_ptr * const fns[4] = { |
4319 | NULL, | |
05f48bab RH |
4320 | gen_helper_sve_fcmla_zpzzz_h, |
4321 | gen_helper_sve_fcmla_zpzzz_s, | |
4322 | gen_helper_sve_fcmla_zpzzz_d, | |
4323 | }; | |
4324 | ||
4325 | if (a->esz == 0) { | |
4326 | return false; | |
4327 | } | |
4328 | if (sve_access_check(s)) { | |
4329 | unsigned vsz = vec_full_reg_size(s); | |
cdfb22bb | 4330 | TCGv_ptr status = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR); |
08975da9 RH |
4331 | tcg_gen_gvec_5_ptr(vec_full_reg_offset(s, a->rd), |
4332 | vec_full_reg_offset(s, a->rn), | |
4333 | vec_full_reg_offset(s, a->rm), | |
4334 | vec_full_reg_offset(s, a->ra), | |
4335 | pred_full_reg_offset(s, a->pg), | |
4336 | status, vsz, vsz, a->rot, fns[a->esz]); | |
4337 | tcg_temp_free_ptr(status); | |
05f48bab RH |
4338 | } |
4339 | return true; | |
4340 | } | |
4341 | ||
3a7be554 | 4342 | static bool trans_FCMLA_zzxz(DisasContext *s, arg_FCMLA_zzxz *a) |
18fc2405 | 4343 | { |
636ddeb1 | 4344 | static gen_helper_gvec_4_ptr * const fns[2] = { |
18fc2405 RH |
4345 | gen_helper_gvec_fcmlah_idx, |
4346 | gen_helper_gvec_fcmlas_idx, | |
4347 | }; | |
4348 | ||
4349 | tcg_debug_assert(a->esz == 1 || a->esz == 2); | |
4350 | tcg_debug_assert(a->rd == a->ra); | |
4351 | if (sve_access_check(s)) { | |
4352 | unsigned vsz = vec_full_reg_size(s); | |
cdfb22bb | 4353 | TCGv_ptr status = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR); |
636ddeb1 | 4354 | tcg_gen_gvec_4_ptr(vec_full_reg_offset(s, a->rd), |
18fc2405 RH |
4355 | vec_full_reg_offset(s, a->rn), |
4356 | vec_full_reg_offset(s, a->rm), | |
636ddeb1 | 4357 | vec_full_reg_offset(s, a->ra), |
18fc2405 RH |
4358 | status, vsz, vsz, |
4359 | a->index * 4 + a->rot, | |
4360 | fns[a->esz - 1]); | |
4361 | tcg_temp_free_ptr(status); | |
4362 | } | |
4363 | return true; | |
4364 | } | |
4365 | ||
8092c6a3 RH |
4366 | /* |
4367 | *** SVE Floating Point Unary Operations Predicated Group | |
4368 | */ | |
4369 | ||
4370 | static bool do_zpz_ptr(DisasContext *s, int rd, int rn, int pg, | |
4371 | bool is_fp16, gen_helper_gvec_3_ptr *fn) | |
4372 | { | |
4373 | if (sve_access_check(s)) { | |
4374 | unsigned vsz = vec_full_reg_size(s); | |
cdfb22bb | 4375 | TCGv_ptr status = fpstatus_ptr(is_fp16 ? FPST_FPCR_F16 : FPST_FPCR); |
8092c6a3 RH |
4376 | tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd), |
4377 | vec_full_reg_offset(s, rn), | |
4378 | pred_full_reg_offset(s, pg), | |
4379 | status, vsz, vsz, 0, fn); | |
4380 | tcg_temp_free_ptr(status); | |
4381 | } | |
4382 | return true; | |
4383 | } | |
4384 | ||
3a7be554 | 4385 | static bool trans_FCVT_sh(DisasContext *s, arg_rpr_esz *a) |
46d33d1e | 4386 | { |
e4ab5124 | 4387 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvt_sh); |
46d33d1e RH |
4388 | } |
4389 | ||
3a7be554 | 4390 | static bool trans_FCVT_hs(DisasContext *s, arg_rpr_esz *a) |
46d33d1e RH |
4391 | { |
4392 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvt_hs); | |
4393 | } | |
4394 | ||
d29b17ca RH |
4395 | static bool trans_BFCVT(DisasContext *s, arg_rpr_esz *a) |
4396 | { | |
4397 | if (!dc_isar_feature(aa64_sve_bf16, s)) { | |
4398 | return false; | |
4399 | } | |
4400 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_bfcvt); | |
4401 | } | |
4402 | ||
3a7be554 | 4403 | static bool trans_FCVT_dh(DisasContext *s, arg_rpr_esz *a) |
46d33d1e | 4404 | { |
e4ab5124 | 4405 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvt_dh); |
46d33d1e RH |
4406 | } |
4407 | ||
3a7be554 | 4408 | static bool trans_FCVT_hd(DisasContext *s, arg_rpr_esz *a) |
46d33d1e RH |
4409 | { |
4410 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvt_hd); | |
4411 | } | |
4412 | ||
3a7be554 | 4413 | static bool trans_FCVT_ds(DisasContext *s, arg_rpr_esz *a) |
46d33d1e RH |
4414 | { |
4415 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvt_ds); | |
4416 | } | |
4417 | ||
3a7be554 | 4418 | static bool trans_FCVT_sd(DisasContext *s, arg_rpr_esz *a) |
46d33d1e RH |
4419 | { |
4420 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvt_sd); | |
4421 | } | |
4422 | ||
3a7be554 | 4423 | static bool trans_FCVTZS_hh(DisasContext *s, arg_rpr_esz *a) |
df4de1af RH |
4424 | { |
4425 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_fcvtzs_hh); | |
4426 | } | |
4427 | ||
3a7be554 | 4428 | static bool trans_FCVTZU_hh(DisasContext *s, arg_rpr_esz *a) |
df4de1af RH |
4429 | { |
4430 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_fcvtzu_hh); | |
4431 | } | |
4432 | ||
3a7be554 | 4433 | static bool trans_FCVTZS_hs(DisasContext *s, arg_rpr_esz *a) |
df4de1af RH |
4434 | { |
4435 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_fcvtzs_hs); | |
4436 | } | |
4437 | ||
3a7be554 | 4438 | static bool trans_FCVTZU_hs(DisasContext *s, arg_rpr_esz *a) |
df4de1af RH |
4439 | { |
4440 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_fcvtzu_hs); | |
4441 | } | |
4442 | ||
3a7be554 | 4443 | static bool trans_FCVTZS_hd(DisasContext *s, arg_rpr_esz *a) |
df4de1af RH |
4444 | { |
4445 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_fcvtzs_hd); | |
4446 | } | |
4447 | ||
3a7be554 | 4448 | static bool trans_FCVTZU_hd(DisasContext *s, arg_rpr_esz *a) |
df4de1af RH |
4449 | { |
4450 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_fcvtzu_hd); | |
4451 | } | |
4452 | ||
3a7be554 | 4453 | static bool trans_FCVTZS_ss(DisasContext *s, arg_rpr_esz *a) |
df4de1af RH |
4454 | { |
4455 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvtzs_ss); | |
4456 | } | |
4457 | ||
3a7be554 | 4458 | static bool trans_FCVTZU_ss(DisasContext *s, arg_rpr_esz *a) |
df4de1af RH |
4459 | { |
4460 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvtzu_ss); | |
4461 | } | |
4462 | ||
3a7be554 | 4463 | static bool trans_FCVTZS_sd(DisasContext *s, arg_rpr_esz *a) |
df4de1af RH |
4464 | { |
4465 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvtzs_sd); | |
4466 | } | |
4467 | ||
3a7be554 | 4468 | static bool trans_FCVTZU_sd(DisasContext *s, arg_rpr_esz *a) |
df4de1af RH |
4469 | { |
4470 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvtzu_sd); | |
4471 | } | |
4472 | ||
3a7be554 | 4473 | static bool trans_FCVTZS_ds(DisasContext *s, arg_rpr_esz *a) |
df4de1af RH |
4474 | { |
4475 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvtzs_ds); | |
4476 | } | |
4477 | ||
3a7be554 | 4478 | static bool trans_FCVTZU_ds(DisasContext *s, arg_rpr_esz *a) |
df4de1af RH |
4479 | { |
4480 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvtzu_ds); | |
4481 | } | |
4482 | ||
3a7be554 | 4483 | static bool trans_FCVTZS_dd(DisasContext *s, arg_rpr_esz *a) |
df4de1af RH |
4484 | { |
4485 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvtzs_dd); | |
4486 | } | |
4487 | ||
3a7be554 | 4488 | static bool trans_FCVTZU_dd(DisasContext *s, arg_rpr_esz *a) |
df4de1af RH |
4489 | { |
4490 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvtzu_dd); | |
4491 | } | |
4492 | ||
cda3c753 RH |
4493 | static gen_helper_gvec_3_ptr * const frint_fns[3] = { |
4494 | gen_helper_sve_frint_h, | |
4495 | gen_helper_sve_frint_s, | |
4496 | gen_helper_sve_frint_d | |
4497 | }; | |
4498 | ||
3a7be554 | 4499 | static bool trans_FRINTI(DisasContext *s, arg_rpr_esz *a) |
cda3c753 RH |
4500 | { |
4501 | if (a->esz == 0) { | |
4502 | return false; | |
4503 | } | |
4504 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, a->esz == MO_16, | |
4505 | frint_fns[a->esz - 1]); | |
4506 | } | |
4507 | ||
3a7be554 | 4508 | static bool trans_FRINTX(DisasContext *s, arg_rpr_esz *a) |
cda3c753 RH |
4509 | { |
4510 | static gen_helper_gvec_3_ptr * const fns[3] = { | |
4511 | gen_helper_sve_frintx_h, | |
4512 | gen_helper_sve_frintx_s, | |
4513 | gen_helper_sve_frintx_d | |
4514 | }; | |
4515 | if (a->esz == 0) { | |
4516 | return false; | |
4517 | } | |
4518 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, a->esz == MO_16, fns[a->esz - 1]); | |
4519 | } | |
4520 | ||
95365277 SL |
4521 | static bool do_frint_mode(DisasContext *s, arg_rpr_esz *a, |
4522 | int mode, gen_helper_gvec_3_ptr *fn) | |
cda3c753 | 4523 | { |
cda3c753 RH |
4524 | if (sve_access_check(s)) { |
4525 | unsigned vsz = vec_full_reg_size(s); | |
4526 | TCGv_i32 tmode = tcg_const_i32(mode); | |
cdfb22bb | 4527 | TCGv_ptr status = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR); |
cda3c753 RH |
4528 | |
4529 | gen_helper_set_rmode(tmode, tmode, status); | |
4530 | ||
4531 | tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, a->rd), | |
4532 | vec_full_reg_offset(s, a->rn), | |
4533 | pred_full_reg_offset(s, a->pg), | |
95365277 | 4534 | status, vsz, vsz, 0, fn); |
cda3c753 RH |
4535 | |
4536 | gen_helper_set_rmode(tmode, tmode, status); | |
4537 | tcg_temp_free_i32(tmode); | |
4538 | tcg_temp_free_ptr(status); | |
4539 | } | |
4540 | return true; | |
4541 | } | |
4542 | ||
3a7be554 | 4543 | static bool trans_FRINTN(DisasContext *s, arg_rpr_esz *a) |
cda3c753 | 4544 | { |
95365277 SL |
4545 | if (a->esz == 0) { |
4546 | return false; | |
4547 | } | |
4548 | return do_frint_mode(s, a, float_round_nearest_even, frint_fns[a->esz - 1]); | |
cda3c753 RH |
4549 | } |
4550 | ||
3a7be554 | 4551 | static bool trans_FRINTP(DisasContext *s, arg_rpr_esz *a) |
cda3c753 | 4552 | { |
95365277 SL |
4553 | if (a->esz == 0) { |
4554 | return false; | |
4555 | } | |
4556 | return do_frint_mode(s, a, float_round_up, frint_fns[a->esz - 1]); | |
cda3c753 RH |
4557 | } |
4558 | ||
3a7be554 | 4559 | static bool trans_FRINTM(DisasContext *s, arg_rpr_esz *a) |
cda3c753 | 4560 | { |
95365277 SL |
4561 | if (a->esz == 0) { |
4562 | return false; | |
4563 | } | |
4564 | return do_frint_mode(s, a, float_round_down, frint_fns[a->esz - 1]); | |
cda3c753 RH |
4565 | } |
4566 | ||
3a7be554 | 4567 | static bool trans_FRINTZ(DisasContext *s, arg_rpr_esz *a) |
cda3c753 | 4568 | { |
95365277 SL |
4569 | if (a->esz == 0) { |
4570 | return false; | |
4571 | } | |
4572 | return do_frint_mode(s, a, float_round_to_zero, frint_fns[a->esz - 1]); | |
cda3c753 RH |
4573 | } |
4574 | ||
3a7be554 | 4575 | static bool trans_FRINTA(DisasContext *s, arg_rpr_esz *a) |
cda3c753 | 4576 | { |
95365277 SL |
4577 | if (a->esz == 0) { |
4578 | return false; | |
4579 | } | |
4580 | return do_frint_mode(s, a, float_round_ties_away, frint_fns[a->esz - 1]); | |
cda3c753 RH |
4581 | } |
4582 | ||
3a7be554 | 4583 | static bool trans_FRECPX(DisasContext *s, arg_rpr_esz *a) |
ec5b375b RH |
4584 | { |
4585 | static gen_helper_gvec_3_ptr * const fns[3] = { | |
4586 | gen_helper_sve_frecpx_h, | |
4587 | gen_helper_sve_frecpx_s, | |
4588 | gen_helper_sve_frecpx_d | |
4589 | }; | |
4590 | if (a->esz == 0) { | |
4591 | return false; | |
4592 | } | |
4593 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, a->esz == MO_16, fns[a->esz - 1]); | |
4594 | } | |
4595 | ||
3a7be554 | 4596 | static bool trans_FSQRT(DisasContext *s, arg_rpr_esz *a) |
ec5b375b RH |
4597 | { |
4598 | static gen_helper_gvec_3_ptr * const fns[3] = { | |
4599 | gen_helper_sve_fsqrt_h, | |
4600 | gen_helper_sve_fsqrt_s, | |
4601 | gen_helper_sve_fsqrt_d | |
4602 | }; | |
4603 | if (a->esz == 0) { | |
4604 | return false; | |
4605 | } | |
4606 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, a->esz == MO_16, fns[a->esz - 1]); | |
4607 | } | |
4608 | ||
3a7be554 | 4609 | static bool trans_SCVTF_hh(DisasContext *s, arg_rpr_esz *a) |
8092c6a3 RH |
4610 | { |
4611 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_scvt_hh); | |
4612 | } | |
4613 | ||
3a7be554 | 4614 | static bool trans_SCVTF_sh(DisasContext *s, arg_rpr_esz *a) |
8092c6a3 RH |
4615 | { |
4616 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_scvt_sh); | |
4617 | } | |
4618 | ||
3a7be554 | 4619 | static bool trans_SCVTF_dh(DisasContext *s, arg_rpr_esz *a) |
8092c6a3 RH |
4620 | { |
4621 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_scvt_dh); | |
4622 | } | |
4623 | ||
3a7be554 | 4624 | static bool trans_SCVTF_ss(DisasContext *s, arg_rpr_esz *a) |
8092c6a3 RH |
4625 | { |
4626 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_scvt_ss); | |
4627 | } | |
4628 | ||
3a7be554 | 4629 | static bool trans_SCVTF_ds(DisasContext *s, arg_rpr_esz *a) |
8092c6a3 RH |
4630 | { |
4631 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_scvt_ds); | |
4632 | } | |
4633 | ||
3a7be554 | 4634 | static bool trans_SCVTF_sd(DisasContext *s, arg_rpr_esz *a) |
8092c6a3 RH |
4635 | { |
4636 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_scvt_sd); | |
4637 | } | |
4638 | ||
3a7be554 | 4639 | static bool trans_SCVTF_dd(DisasContext *s, arg_rpr_esz *a) |
8092c6a3 RH |
4640 | { |
4641 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_scvt_dd); | |
4642 | } | |
4643 | ||
3a7be554 | 4644 | static bool trans_UCVTF_hh(DisasContext *s, arg_rpr_esz *a) |
8092c6a3 RH |
4645 | { |
4646 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_ucvt_hh); | |
4647 | } | |
4648 | ||
3a7be554 | 4649 | static bool trans_UCVTF_sh(DisasContext *s, arg_rpr_esz *a) |
8092c6a3 RH |
4650 | { |
4651 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_ucvt_sh); | |
4652 | } | |
4653 | ||
3a7be554 | 4654 | static bool trans_UCVTF_dh(DisasContext *s, arg_rpr_esz *a) |
8092c6a3 RH |
4655 | { |
4656 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_ucvt_dh); | |
4657 | } | |
4658 | ||
3a7be554 | 4659 | static bool trans_UCVTF_ss(DisasContext *s, arg_rpr_esz *a) |
8092c6a3 RH |
4660 | { |
4661 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_ucvt_ss); | |
4662 | } | |
4663 | ||
3a7be554 | 4664 | static bool trans_UCVTF_ds(DisasContext *s, arg_rpr_esz *a) |
8092c6a3 RH |
4665 | { |
4666 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_ucvt_ds); | |
4667 | } | |
4668 | ||
3a7be554 | 4669 | static bool trans_UCVTF_sd(DisasContext *s, arg_rpr_esz *a) |
8092c6a3 RH |
4670 | { |
4671 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_ucvt_sd); | |
4672 | } | |
4673 | ||
3a7be554 | 4674 | static bool trans_UCVTF_dd(DisasContext *s, arg_rpr_esz *a) |
8092c6a3 RH |
4675 | { |
4676 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_ucvt_dd); | |
4677 | } | |
4678 | ||
d1822297 RH |
4679 | /* |
4680 | *** SVE Memory - 32-bit Gather and Unsized Contiguous Group | |
4681 | */ | |
4682 | ||
4683 | /* Subroutine loading a vector register at VOFS of LEN bytes. | |
4684 | * The load should begin at the address Rn + IMM. | |
4685 | */ | |
4686 | ||
19f2acc9 | 4687 | static void do_ldr(DisasContext *s, uint32_t vofs, int len, int rn, int imm) |
d1822297 | 4688 | { |
19f2acc9 RH |
4689 | int len_align = QEMU_ALIGN_DOWN(len, 8); |
4690 | int len_remain = len % 8; | |
4691 | int nparts = len / 8 + ctpop8(len_remain); | |
d1822297 | 4692 | int midx = get_mem_index(s); |
b2aa8879 | 4693 | TCGv_i64 dirty_addr, clean_addr, t0, t1; |
d1822297 | 4694 | |
b2aa8879 RH |
4695 | dirty_addr = tcg_temp_new_i64(); |
4696 | tcg_gen_addi_i64(dirty_addr, cpu_reg_sp(s, rn), imm); | |
33e74c31 | 4697 | clean_addr = gen_mte_checkN(s, dirty_addr, false, rn != 31, len); |
b2aa8879 | 4698 | tcg_temp_free_i64(dirty_addr); |
d1822297 | 4699 | |
b2aa8879 RH |
4700 | /* |
4701 | * Note that unpredicated load/store of vector/predicate registers | |
d1822297 | 4702 | * are defined as a stream of bytes, which equates to little-endian |
b2aa8879 | 4703 | * operations on larger quantities. |
d1822297 RH |
4704 | * Attempt to keep code expansion to a minimum by limiting the |
4705 | * amount of unrolling done. | |
4706 | */ | |
4707 | if (nparts <= 4) { | |
4708 | int i; | |
4709 | ||
b2aa8879 | 4710 | t0 = tcg_temp_new_i64(); |
d1822297 | 4711 | for (i = 0; i < len_align; i += 8) { |
fc313c64 | 4712 | tcg_gen_qemu_ld_i64(t0, clean_addr, midx, MO_LEUQ); |
d1822297 | 4713 | tcg_gen_st_i64(t0, cpu_env, vofs + i); |
d8227b09 | 4714 | tcg_gen_addi_i64(clean_addr, clean_addr, 8); |
d1822297 | 4715 | } |
b2aa8879 | 4716 | tcg_temp_free_i64(t0); |
d1822297 RH |
4717 | } else { |
4718 | TCGLabel *loop = gen_new_label(); | |
4719 | TCGv_ptr tp, i = tcg_const_local_ptr(0); | |
4720 | ||
b2aa8879 RH |
4721 | /* Copy the clean address into a local temp, live across the loop. */ |
4722 | t0 = clean_addr; | |
4b4dc975 | 4723 | clean_addr = new_tmp_a64_local(s); |
b2aa8879 | 4724 | tcg_gen_mov_i64(clean_addr, t0); |
d1822297 | 4725 | |
b2aa8879 | 4726 | gen_set_label(loop); |
d1822297 | 4727 | |
b2aa8879 | 4728 | t0 = tcg_temp_new_i64(); |
fc313c64 | 4729 | tcg_gen_qemu_ld_i64(t0, clean_addr, midx, MO_LEUQ); |
b2aa8879 | 4730 | tcg_gen_addi_i64(clean_addr, clean_addr, 8); |
d1822297 | 4731 | |
b2aa8879 | 4732 | tp = tcg_temp_new_ptr(); |
d1822297 RH |
4733 | tcg_gen_add_ptr(tp, cpu_env, i); |
4734 | tcg_gen_addi_ptr(i, i, 8); | |
4735 | tcg_gen_st_i64(t0, tp, vofs); | |
4736 | tcg_temp_free_ptr(tp); | |
b2aa8879 | 4737 | tcg_temp_free_i64(t0); |
d1822297 RH |
4738 | |
4739 | tcg_gen_brcondi_ptr(TCG_COND_LTU, i, len_align, loop); | |
4740 | tcg_temp_free_ptr(i); | |
4741 | } | |
4742 | ||
b2aa8879 RH |
4743 | /* |
4744 | * Predicate register loads can be any multiple of 2. | |
d1822297 RH |
4745 | * Note that we still store the entire 64-bit unit into cpu_env. |
4746 | */ | |
4747 | if (len_remain) { | |
b2aa8879 | 4748 | t0 = tcg_temp_new_i64(); |
d1822297 RH |
4749 | switch (len_remain) { |
4750 | case 2: | |
4751 | case 4: | |
4752 | case 8: | |
b2aa8879 RH |
4753 | tcg_gen_qemu_ld_i64(t0, clean_addr, midx, |
4754 | MO_LE | ctz32(len_remain)); | |
d1822297 RH |
4755 | break; |
4756 | ||
4757 | case 6: | |
4758 | t1 = tcg_temp_new_i64(); | |
b2aa8879 RH |
4759 | tcg_gen_qemu_ld_i64(t0, clean_addr, midx, MO_LEUL); |
4760 | tcg_gen_addi_i64(clean_addr, clean_addr, 4); | |
4761 | tcg_gen_qemu_ld_i64(t1, clean_addr, midx, MO_LEUW); | |
d1822297 RH |
4762 | tcg_gen_deposit_i64(t0, t0, t1, 32, 32); |
4763 | tcg_temp_free_i64(t1); | |
4764 | break; | |
4765 | ||
4766 | default: | |
4767 | g_assert_not_reached(); | |
4768 | } | |
4769 | tcg_gen_st_i64(t0, cpu_env, vofs + len_align); | |
b2aa8879 | 4770 | tcg_temp_free_i64(t0); |
d1822297 | 4771 | } |
d1822297 RH |
4772 | } |
4773 | ||
5047c204 | 4774 | /* Similarly for stores. */ |
19f2acc9 | 4775 | static void do_str(DisasContext *s, uint32_t vofs, int len, int rn, int imm) |
5047c204 | 4776 | { |
19f2acc9 RH |
4777 | int len_align = QEMU_ALIGN_DOWN(len, 8); |
4778 | int len_remain = len % 8; | |
4779 | int nparts = len / 8 + ctpop8(len_remain); | |
5047c204 | 4780 | int midx = get_mem_index(s); |
bba87d0a | 4781 | TCGv_i64 dirty_addr, clean_addr, t0; |
5047c204 | 4782 | |
bba87d0a RH |
4783 | dirty_addr = tcg_temp_new_i64(); |
4784 | tcg_gen_addi_i64(dirty_addr, cpu_reg_sp(s, rn), imm); | |
33e74c31 | 4785 | clean_addr = gen_mte_checkN(s, dirty_addr, false, rn != 31, len); |
bba87d0a | 4786 | tcg_temp_free_i64(dirty_addr); |
5047c204 RH |
4787 | |
4788 | /* Note that unpredicated load/store of vector/predicate registers | |
4789 | * are defined as a stream of bytes, which equates to little-endian | |
4790 | * operations on larger quantities. There is no nice way to force | |
4791 | * a little-endian store for aarch64_be-linux-user out of line. | |
4792 | * | |
4793 | * Attempt to keep code expansion to a minimum by limiting the | |
4794 | * amount of unrolling done. | |
4795 | */ | |
4796 | if (nparts <= 4) { | |
4797 | int i; | |
4798 | ||
bba87d0a | 4799 | t0 = tcg_temp_new_i64(); |
5047c204 RH |
4800 | for (i = 0; i < len_align; i += 8) { |
4801 | tcg_gen_ld_i64(t0, cpu_env, vofs + i); | |
fc313c64 | 4802 | tcg_gen_qemu_st_i64(t0, clean_addr, midx, MO_LEUQ); |
d8227b09 | 4803 | tcg_gen_addi_i64(clean_addr, clean_addr, 8); |
5047c204 | 4804 | } |
bba87d0a | 4805 | tcg_temp_free_i64(t0); |
5047c204 RH |
4806 | } else { |
4807 | TCGLabel *loop = gen_new_label(); | |
bba87d0a | 4808 | TCGv_ptr tp, i = tcg_const_local_ptr(0); |
5047c204 | 4809 | |
bba87d0a RH |
4810 | /* Copy the clean address into a local temp, live across the loop. */ |
4811 | t0 = clean_addr; | |
4b4dc975 | 4812 | clean_addr = new_tmp_a64_local(s); |
bba87d0a | 4813 | tcg_gen_mov_i64(clean_addr, t0); |
5047c204 | 4814 | |
bba87d0a | 4815 | gen_set_label(loop); |
5047c204 | 4816 | |
bba87d0a RH |
4817 | t0 = tcg_temp_new_i64(); |
4818 | tp = tcg_temp_new_ptr(); | |
4819 | tcg_gen_add_ptr(tp, cpu_env, i); | |
4820 | tcg_gen_ld_i64(t0, tp, vofs); | |
5047c204 | 4821 | tcg_gen_addi_ptr(i, i, 8); |
bba87d0a RH |
4822 | tcg_temp_free_ptr(tp); |
4823 | ||
fc313c64 | 4824 | tcg_gen_qemu_st_i64(t0, clean_addr, midx, MO_LEUQ); |
bba87d0a RH |
4825 | tcg_gen_addi_i64(clean_addr, clean_addr, 8); |
4826 | tcg_temp_free_i64(t0); | |
5047c204 RH |
4827 | |
4828 | tcg_gen_brcondi_ptr(TCG_COND_LTU, i, len_align, loop); | |
4829 | tcg_temp_free_ptr(i); | |
4830 | } | |
4831 | ||
4832 | /* Predicate register stores can be any multiple of 2. */ | |
4833 | if (len_remain) { | |
bba87d0a | 4834 | t0 = tcg_temp_new_i64(); |
5047c204 | 4835 | tcg_gen_ld_i64(t0, cpu_env, vofs + len_align); |
5047c204 RH |
4836 | |
4837 | switch (len_remain) { | |
4838 | case 2: | |
4839 | case 4: | |
4840 | case 8: | |
bba87d0a RH |
4841 | tcg_gen_qemu_st_i64(t0, clean_addr, midx, |
4842 | MO_LE | ctz32(len_remain)); | |
5047c204 RH |
4843 | break; |
4844 | ||
4845 | case 6: | |
bba87d0a RH |
4846 | tcg_gen_qemu_st_i64(t0, clean_addr, midx, MO_LEUL); |
4847 | tcg_gen_addi_i64(clean_addr, clean_addr, 4); | |
5047c204 | 4848 | tcg_gen_shri_i64(t0, t0, 32); |
bba87d0a | 4849 | tcg_gen_qemu_st_i64(t0, clean_addr, midx, MO_LEUW); |
5047c204 RH |
4850 | break; |
4851 | ||
4852 | default: | |
4853 | g_assert_not_reached(); | |
4854 | } | |
bba87d0a | 4855 | tcg_temp_free_i64(t0); |
5047c204 | 4856 | } |
5047c204 RH |
4857 | } |
4858 | ||
3a7be554 | 4859 | static bool trans_LDR_zri(DisasContext *s, arg_rri *a) |
d1822297 RH |
4860 | { |
4861 | if (sve_access_check(s)) { | |
4862 | int size = vec_full_reg_size(s); | |
4863 | int off = vec_full_reg_offset(s, a->rd); | |
4864 | do_ldr(s, off, size, a->rn, a->imm * size); | |
4865 | } | |
4866 | return true; | |
4867 | } | |
4868 | ||
3a7be554 | 4869 | static bool trans_LDR_pri(DisasContext *s, arg_rri *a) |
d1822297 RH |
4870 | { |
4871 | if (sve_access_check(s)) { | |
4872 | int size = pred_full_reg_size(s); | |
4873 | int off = pred_full_reg_offset(s, a->rd); | |
4874 | do_ldr(s, off, size, a->rn, a->imm * size); | |
4875 | } | |
4876 | return true; | |
4877 | } | |
c4e7c493 | 4878 | |
3a7be554 | 4879 | static bool trans_STR_zri(DisasContext *s, arg_rri *a) |
5047c204 RH |
4880 | { |
4881 | if (sve_access_check(s)) { | |
4882 | int size = vec_full_reg_size(s); | |
4883 | int off = vec_full_reg_offset(s, a->rd); | |
4884 | do_str(s, off, size, a->rn, a->imm * size); | |
4885 | } | |
4886 | return true; | |
4887 | } | |
4888 | ||
3a7be554 | 4889 | static bool trans_STR_pri(DisasContext *s, arg_rri *a) |
5047c204 RH |
4890 | { |
4891 | if (sve_access_check(s)) { | |
4892 | int size = pred_full_reg_size(s); | |
4893 | int off = pred_full_reg_offset(s, a->rd); | |
4894 | do_str(s, off, size, a->rn, a->imm * size); | |
4895 | } | |
4896 | return true; | |
4897 | } | |
4898 | ||
c4e7c493 RH |
4899 | /* |
4900 | *** SVE Memory - Contiguous Load Group | |
4901 | */ | |
4902 | ||
4903 | /* The memory mode of the dtype. */ | |
14776ab5 | 4904 | static const MemOp dtype_mop[16] = { |
c4e7c493 RH |
4905 | MO_UB, MO_UB, MO_UB, MO_UB, |
4906 | MO_SL, MO_UW, MO_UW, MO_UW, | |
4907 | MO_SW, MO_SW, MO_UL, MO_UL, | |
fc313c64 | 4908 | MO_SB, MO_SB, MO_SB, MO_UQ |
c4e7c493 RH |
4909 | }; |
4910 | ||
4911 | #define dtype_msz(x) (dtype_mop[x] & MO_SIZE) | |
4912 | ||
4913 | /* The vector element size of dtype. */ | |
4914 | static const uint8_t dtype_esz[16] = { | |
4915 | 0, 1, 2, 3, | |
4916 | 3, 1, 2, 3, | |
4917 | 3, 2, 2, 3, | |
4918 | 3, 2, 1, 3 | |
4919 | }; | |
4920 | ||
4921 | static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr, | |
206adacf RH |
4922 | int dtype, uint32_t mte_n, bool is_write, |
4923 | gen_helper_gvec_mem *fn) | |
c4e7c493 RH |
4924 | { |
4925 | unsigned vsz = vec_full_reg_size(s); | |
4926 | TCGv_ptr t_pg; | |
206adacf | 4927 | int desc = 0; |
c4e7c493 | 4928 | |
206adacf RH |
4929 | /* |
4930 | * For e.g. LD4, there are not enough arguments to pass all 4 | |
c4e7c493 RH |
4931 | * registers as pointers, so encode the regno into the data field. |
4932 | * For consistency, do this even for LD1. | |
4933 | */ | |
9473d0ec | 4934 | if (s->mte_active[0]) { |
206adacf RH |
4935 | int msz = dtype_msz(dtype); |
4936 | ||
4937 | desc = FIELD_DP32(desc, MTEDESC, MIDX, get_mem_index(s)); | |
4938 | desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid); | |
4939 | desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma); | |
4940 | desc = FIELD_DP32(desc, MTEDESC, WRITE, is_write); | |
28f32503 | 4941 | desc = FIELD_DP32(desc, MTEDESC, SIZEM1, (mte_n << msz) - 1); |
206adacf | 4942 | desc <<= SVE_MTEDESC_SHIFT; |
9473d0ec RH |
4943 | } else { |
4944 | addr = clean_data_tbi(s, addr); | |
206adacf | 4945 | } |
9473d0ec | 4946 | |
206adacf | 4947 | desc = simd_desc(vsz, vsz, zt | desc); |
c4e7c493 RH |
4948 | t_pg = tcg_temp_new_ptr(); |
4949 | ||
4950 | tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, pg)); | |
c6a59b55 | 4951 | fn(cpu_env, t_pg, addr, tcg_constant_i32(desc)); |
c4e7c493 RH |
4952 | |
4953 | tcg_temp_free_ptr(t_pg); | |
c4e7c493 RH |
4954 | } |
4955 | ||
c182c6db RH |
4956 | /* Indexed by [mte][be][dtype][nreg] */ |
4957 | static gen_helper_gvec_mem * const ldr_fns[2][2][16][4] = { | |
4958 | { /* mte inactive, little-endian */ | |
4959 | { { gen_helper_sve_ld1bb_r, gen_helper_sve_ld2bb_r, | |
4960 | gen_helper_sve_ld3bb_r, gen_helper_sve_ld4bb_r }, | |
4961 | { gen_helper_sve_ld1bhu_r, NULL, NULL, NULL }, | |
4962 | { gen_helper_sve_ld1bsu_r, NULL, NULL, NULL }, | |
4963 | { gen_helper_sve_ld1bdu_r, NULL, NULL, NULL }, | |
4964 | ||
4965 | { gen_helper_sve_ld1sds_le_r, NULL, NULL, NULL }, | |
4966 | { gen_helper_sve_ld1hh_le_r, gen_helper_sve_ld2hh_le_r, | |
4967 | gen_helper_sve_ld3hh_le_r, gen_helper_sve_ld4hh_le_r }, | |
4968 | { gen_helper_sve_ld1hsu_le_r, NULL, NULL, NULL }, | |
4969 | { gen_helper_sve_ld1hdu_le_r, NULL, NULL, NULL }, | |
4970 | ||
4971 | { gen_helper_sve_ld1hds_le_r, NULL, NULL, NULL }, | |
4972 | { gen_helper_sve_ld1hss_le_r, NULL, NULL, NULL }, | |
4973 | { gen_helper_sve_ld1ss_le_r, gen_helper_sve_ld2ss_le_r, | |
4974 | gen_helper_sve_ld3ss_le_r, gen_helper_sve_ld4ss_le_r }, | |
4975 | { gen_helper_sve_ld1sdu_le_r, NULL, NULL, NULL }, | |
4976 | ||
4977 | { gen_helper_sve_ld1bds_r, NULL, NULL, NULL }, | |
4978 | { gen_helper_sve_ld1bss_r, NULL, NULL, NULL }, | |
4979 | { gen_helper_sve_ld1bhs_r, NULL, NULL, NULL }, | |
4980 | { gen_helper_sve_ld1dd_le_r, gen_helper_sve_ld2dd_le_r, | |
4981 | gen_helper_sve_ld3dd_le_r, gen_helper_sve_ld4dd_le_r } }, | |
4982 | ||
4983 | /* mte inactive, big-endian */ | |
4984 | { { gen_helper_sve_ld1bb_r, gen_helper_sve_ld2bb_r, | |
4985 | gen_helper_sve_ld3bb_r, gen_helper_sve_ld4bb_r }, | |
4986 | { gen_helper_sve_ld1bhu_r, NULL, NULL, NULL }, | |
4987 | { gen_helper_sve_ld1bsu_r, NULL, NULL, NULL }, | |
4988 | { gen_helper_sve_ld1bdu_r, NULL, NULL, NULL }, | |
4989 | ||
4990 | { gen_helper_sve_ld1sds_be_r, NULL, NULL, NULL }, | |
4991 | { gen_helper_sve_ld1hh_be_r, gen_helper_sve_ld2hh_be_r, | |
4992 | gen_helper_sve_ld3hh_be_r, gen_helper_sve_ld4hh_be_r }, | |
4993 | { gen_helper_sve_ld1hsu_be_r, NULL, NULL, NULL }, | |
4994 | { gen_helper_sve_ld1hdu_be_r, NULL, NULL, NULL }, | |
4995 | ||
4996 | { gen_helper_sve_ld1hds_be_r, NULL, NULL, NULL }, | |
4997 | { gen_helper_sve_ld1hss_be_r, NULL, NULL, NULL }, | |
4998 | { gen_helper_sve_ld1ss_be_r, gen_helper_sve_ld2ss_be_r, | |
4999 | gen_helper_sve_ld3ss_be_r, gen_helper_sve_ld4ss_be_r }, | |
5000 | { gen_helper_sve_ld1sdu_be_r, NULL, NULL, NULL }, | |
5001 | ||
5002 | { gen_helper_sve_ld1bds_r, NULL, NULL, NULL }, | |
5003 | { gen_helper_sve_ld1bss_r, NULL, NULL, NULL }, | |
5004 | { gen_helper_sve_ld1bhs_r, NULL, NULL, NULL }, | |
5005 | { gen_helper_sve_ld1dd_be_r, gen_helper_sve_ld2dd_be_r, | |
5006 | gen_helper_sve_ld3dd_be_r, gen_helper_sve_ld4dd_be_r } } }, | |
5007 | ||
5008 | { /* mte active, little-endian */ | |
5009 | { { gen_helper_sve_ld1bb_r_mte, | |
5010 | gen_helper_sve_ld2bb_r_mte, | |
5011 | gen_helper_sve_ld3bb_r_mte, | |
5012 | gen_helper_sve_ld4bb_r_mte }, | |
5013 | { gen_helper_sve_ld1bhu_r_mte, NULL, NULL, NULL }, | |
5014 | { gen_helper_sve_ld1bsu_r_mte, NULL, NULL, NULL }, | |
5015 | { gen_helper_sve_ld1bdu_r_mte, NULL, NULL, NULL }, | |
5016 | ||
5017 | { gen_helper_sve_ld1sds_le_r_mte, NULL, NULL, NULL }, | |
5018 | { gen_helper_sve_ld1hh_le_r_mte, | |
5019 | gen_helper_sve_ld2hh_le_r_mte, | |
5020 | gen_helper_sve_ld3hh_le_r_mte, | |
5021 | gen_helper_sve_ld4hh_le_r_mte }, | |
5022 | { gen_helper_sve_ld1hsu_le_r_mte, NULL, NULL, NULL }, | |
5023 | { gen_helper_sve_ld1hdu_le_r_mte, NULL, NULL, NULL }, | |
5024 | ||
5025 | { gen_helper_sve_ld1hds_le_r_mte, NULL, NULL, NULL }, | |
5026 | { gen_helper_sve_ld1hss_le_r_mte, NULL, NULL, NULL }, | |
5027 | { gen_helper_sve_ld1ss_le_r_mte, | |
5028 | gen_helper_sve_ld2ss_le_r_mte, | |
5029 | gen_helper_sve_ld3ss_le_r_mte, | |
5030 | gen_helper_sve_ld4ss_le_r_mte }, | |
5031 | { gen_helper_sve_ld1sdu_le_r_mte, NULL, NULL, NULL }, | |
5032 | ||
5033 | { gen_helper_sve_ld1bds_r_mte, NULL, NULL, NULL }, | |
5034 | { gen_helper_sve_ld1bss_r_mte, NULL, NULL, NULL }, | |
5035 | { gen_helper_sve_ld1bhs_r_mte, NULL, NULL, NULL }, | |
5036 | { gen_helper_sve_ld1dd_le_r_mte, | |
5037 | gen_helper_sve_ld2dd_le_r_mte, | |
5038 | gen_helper_sve_ld3dd_le_r_mte, | |
5039 | gen_helper_sve_ld4dd_le_r_mte } }, | |
5040 | ||
5041 | /* mte active, big-endian */ | |
5042 | { { gen_helper_sve_ld1bb_r_mte, | |
5043 | gen_helper_sve_ld2bb_r_mte, | |
5044 | gen_helper_sve_ld3bb_r_mte, | |
5045 | gen_helper_sve_ld4bb_r_mte }, | |
5046 | { gen_helper_sve_ld1bhu_r_mte, NULL, NULL, NULL }, | |
5047 | { gen_helper_sve_ld1bsu_r_mte, NULL, NULL, NULL }, | |
5048 | { gen_helper_sve_ld1bdu_r_mte, NULL, NULL, NULL }, | |
5049 | ||
5050 | { gen_helper_sve_ld1sds_be_r_mte, NULL, NULL, NULL }, | |
5051 | { gen_helper_sve_ld1hh_be_r_mte, | |
5052 | gen_helper_sve_ld2hh_be_r_mte, | |
5053 | gen_helper_sve_ld3hh_be_r_mte, | |
5054 | gen_helper_sve_ld4hh_be_r_mte }, | |
5055 | { gen_helper_sve_ld1hsu_be_r_mte, NULL, NULL, NULL }, | |
5056 | { gen_helper_sve_ld1hdu_be_r_mte, NULL, NULL, NULL }, | |
5057 | ||
5058 | { gen_helper_sve_ld1hds_be_r_mte, NULL, NULL, NULL }, | |
5059 | { gen_helper_sve_ld1hss_be_r_mte, NULL, NULL, NULL }, | |
5060 | { gen_helper_sve_ld1ss_be_r_mte, | |
5061 | gen_helper_sve_ld2ss_be_r_mte, | |
5062 | gen_helper_sve_ld3ss_be_r_mte, | |
5063 | gen_helper_sve_ld4ss_be_r_mte }, | |
5064 | { gen_helper_sve_ld1sdu_be_r_mte, NULL, NULL, NULL }, | |
5065 | ||
5066 | { gen_helper_sve_ld1bds_r_mte, NULL, NULL, NULL }, | |
5067 | { gen_helper_sve_ld1bss_r_mte, NULL, NULL, NULL }, | |
5068 | { gen_helper_sve_ld1bhs_r_mte, NULL, NULL, NULL }, | |
5069 | { gen_helper_sve_ld1dd_be_r_mte, | |
5070 | gen_helper_sve_ld2dd_be_r_mte, | |
5071 | gen_helper_sve_ld3dd_be_r_mte, | |
5072 | gen_helper_sve_ld4dd_be_r_mte } } }, | |
5073 | }; | |
5074 | ||
c4e7c493 RH |
5075 | static void do_ld_zpa(DisasContext *s, int zt, int pg, |
5076 | TCGv_i64 addr, int dtype, int nreg) | |
5077 | { | |
206adacf | 5078 | gen_helper_gvec_mem *fn |
c182c6db | 5079 | = ldr_fns[s->mte_active[0]][s->be_data == MO_BE][dtype][nreg]; |
c4e7c493 | 5080 | |
206adacf RH |
5081 | /* |
5082 | * While there are holes in the table, they are not | |
c4e7c493 RH |
5083 | * accessible via the instruction encoding. |
5084 | */ | |
5085 | assert(fn != NULL); | |
206adacf | 5086 | do_mem_zpa(s, zt, pg, addr, dtype, nreg, false, fn); |
c4e7c493 RH |
5087 | } |
5088 | ||
3a7be554 | 5089 | static bool trans_LD_zprr(DisasContext *s, arg_rprr_load *a) |
c4e7c493 RH |
5090 | { |
5091 | if (a->rm == 31) { | |
5092 | return false; | |
5093 | } | |
5094 | if (sve_access_check(s)) { | |
5095 | TCGv_i64 addr = new_tmp_a64(s); | |
50ef1cbf | 5096 | tcg_gen_shli_i64(addr, cpu_reg(s, a->rm), dtype_msz(a->dtype)); |
c4e7c493 RH |
5097 | tcg_gen_add_i64(addr, addr, cpu_reg_sp(s, a->rn)); |
5098 | do_ld_zpa(s, a->rd, a->pg, addr, a->dtype, a->nreg); | |
5099 | } | |
5100 | return true; | |
5101 | } | |
5102 | ||
3a7be554 | 5103 | static bool trans_LD_zpri(DisasContext *s, arg_rpri_load *a) |
c4e7c493 RH |
5104 | { |
5105 | if (sve_access_check(s)) { | |
5106 | int vsz = vec_full_reg_size(s); | |
5107 | int elements = vsz >> dtype_esz[a->dtype]; | |
5108 | TCGv_i64 addr = new_tmp_a64(s); | |
5109 | ||
5110 | tcg_gen_addi_i64(addr, cpu_reg_sp(s, a->rn), | |
5111 | (a->imm * elements * (a->nreg + 1)) | |
5112 | << dtype_msz(a->dtype)); | |
5113 | do_ld_zpa(s, a->rd, a->pg, addr, a->dtype, a->nreg); | |
5114 | } | |
5115 | return true; | |
5116 | } | |
e2654d75 | 5117 | |
3a7be554 | 5118 | static bool trans_LDFF1_zprr(DisasContext *s, arg_rprr_load *a) |
e2654d75 | 5119 | { |
aa13f7c3 RH |
5120 | static gen_helper_gvec_mem * const fns[2][2][16] = { |
5121 | { /* mte inactive, little-endian */ | |
5122 | { gen_helper_sve_ldff1bb_r, | |
5123 | gen_helper_sve_ldff1bhu_r, | |
5124 | gen_helper_sve_ldff1bsu_r, | |
5125 | gen_helper_sve_ldff1bdu_r, | |
5126 | ||
5127 | gen_helper_sve_ldff1sds_le_r, | |
5128 | gen_helper_sve_ldff1hh_le_r, | |
5129 | gen_helper_sve_ldff1hsu_le_r, | |
5130 | gen_helper_sve_ldff1hdu_le_r, | |
5131 | ||
5132 | gen_helper_sve_ldff1hds_le_r, | |
5133 | gen_helper_sve_ldff1hss_le_r, | |
5134 | gen_helper_sve_ldff1ss_le_r, | |
5135 | gen_helper_sve_ldff1sdu_le_r, | |
5136 | ||
5137 | gen_helper_sve_ldff1bds_r, | |
5138 | gen_helper_sve_ldff1bss_r, | |
5139 | gen_helper_sve_ldff1bhs_r, | |
5140 | gen_helper_sve_ldff1dd_le_r }, | |
5141 | ||
5142 | /* mte inactive, big-endian */ | |
5143 | { gen_helper_sve_ldff1bb_r, | |
5144 | gen_helper_sve_ldff1bhu_r, | |
5145 | gen_helper_sve_ldff1bsu_r, | |
5146 | gen_helper_sve_ldff1bdu_r, | |
5147 | ||
5148 | gen_helper_sve_ldff1sds_be_r, | |
5149 | gen_helper_sve_ldff1hh_be_r, | |
5150 | gen_helper_sve_ldff1hsu_be_r, | |
5151 | gen_helper_sve_ldff1hdu_be_r, | |
5152 | ||
5153 | gen_helper_sve_ldff1hds_be_r, | |
5154 | gen_helper_sve_ldff1hss_be_r, | |
5155 | gen_helper_sve_ldff1ss_be_r, | |
5156 | gen_helper_sve_ldff1sdu_be_r, | |
5157 | ||
5158 | gen_helper_sve_ldff1bds_r, | |
5159 | gen_helper_sve_ldff1bss_r, | |
5160 | gen_helper_sve_ldff1bhs_r, | |
5161 | gen_helper_sve_ldff1dd_be_r } }, | |
5162 | ||
5163 | { /* mte active, little-endian */ | |
5164 | { gen_helper_sve_ldff1bb_r_mte, | |
5165 | gen_helper_sve_ldff1bhu_r_mte, | |
5166 | gen_helper_sve_ldff1bsu_r_mte, | |
5167 | gen_helper_sve_ldff1bdu_r_mte, | |
5168 | ||
5169 | gen_helper_sve_ldff1sds_le_r_mte, | |
5170 | gen_helper_sve_ldff1hh_le_r_mte, | |
5171 | gen_helper_sve_ldff1hsu_le_r_mte, | |
5172 | gen_helper_sve_ldff1hdu_le_r_mte, | |
5173 | ||
5174 | gen_helper_sve_ldff1hds_le_r_mte, | |
5175 | gen_helper_sve_ldff1hss_le_r_mte, | |
5176 | gen_helper_sve_ldff1ss_le_r_mte, | |
5177 | gen_helper_sve_ldff1sdu_le_r_mte, | |
5178 | ||
5179 | gen_helper_sve_ldff1bds_r_mte, | |
5180 | gen_helper_sve_ldff1bss_r_mte, | |
5181 | gen_helper_sve_ldff1bhs_r_mte, | |
5182 | gen_helper_sve_ldff1dd_le_r_mte }, | |
5183 | ||
5184 | /* mte active, big-endian */ | |
5185 | { gen_helper_sve_ldff1bb_r_mte, | |
5186 | gen_helper_sve_ldff1bhu_r_mte, | |
5187 | gen_helper_sve_ldff1bsu_r_mte, | |
5188 | gen_helper_sve_ldff1bdu_r_mte, | |
5189 | ||
5190 | gen_helper_sve_ldff1sds_be_r_mte, | |
5191 | gen_helper_sve_ldff1hh_be_r_mte, | |
5192 | gen_helper_sve_ldff1hsu_be_r_mte, | |
5193 | gen_helper_sve_ldff1hdu_be_r_mte, | |
5194 | ||
5195 | gen_helper_sve_ldff1hds_be_r_mte, | |
5196 | gen_helper_sve_ldff1hss_be_r_mte, | |
5197 | gen_helper_sve_ldff1ss_be_r_mte, | |
5198 | gen_helper_sve_ldff1sdu_be_r_mte, | |
5199 | ||
5200 | gen_helper_sve_ldff1bds_r_mte, | |
5201 | gen_helper_sve_ldff1bss_r_mte, | |
5202 | gen_helper_sve_ldff1bhs_r_mte, | |
5203 | gen_helper_sve_ldff1dd_be_r_mte } }, | |
e2654d75 RH |
5204 | }; |
5205 | ||
5206 | if (sve_access_check(s)) { | |
5207 | TCGv_i64 addr = new_tmp_a64(s); | |
5208 | tcg_gen_shli_i64(addr, cpu_reg(s, a->rm), dtype_msz(a->dtype)); | |
5209 | tcg_gen_add_i64(addr, addr, cpu_reg_sp(s, a->rn)); | |
aa13f7c3 RH |
5210 | do_mem_zpa(s, a->rd, a->pg, addr, a->dtype, 1, false, |
5211 | fns[s->mte_active[0]][s->be_data == MO_BE][a->dtype]); | |
e2654d75 RH |
5212 | } |
5213 | return true; | |
5214 | } | |
5215 | ||
3a7be554 | 5216 | static bool trans_LDNF1_zpri(DisasContext *s, arg_rpri_load *a) |
e2654d75 | 5217 | { |
aa13f7c3 RH |
5218 | static gen_helper_gvec_mem * const fns[2][2][16] = { |
5219 | { /* mte inactive, little-endian */ | |
5220 | { gen_helper_sve_ldnf1bb_r, | |
5221 | gen_helper_sve_ldnf1bhu_r, | |
5222 | gen_helper_sve_ldnf1bsu_r, | |
5223 | gen_helper_sve_ldnf1bdu_r, | |
5224 | ||
5225 | gen_helper_sve_ldnf1sds_le_r, | |
5226 | gen_helper_sve_ldnf1hh_le_r, | |
5227 | gen_helper_sve_ldnf1hsu_le_r, | |
5228 | gen_helper_sve_ldnf1hdu_le_r, | |
5229 | ||
5230 | gen_helper_sve_ldnf1hds_le_r, | |
5231 | gen_helper_sve_ldnf1hss_le_r, | |
5232 | gen_helper_sve_ldnf1ss_le_r, | |
5233 | gen_helper_sve_ldnf1sdu_le_r, | |
5234 | ||
5235 | gen_helper_sve_ldnf1bds_r, | |
5236 | gen_helper_sve_ldnf1bss_r, | |
5237 | gen_helper_sve_ldnf1bhs_r, | |
5238 | gen_helper_sve_ldnf1dd_le_r }, | |
5239 | ||
5240 | /* mte inactive, big-endian */ | |
5241 | { gen_helper_sve_ldnf1bb_r, | |
5242 | gen_helper_sve_ldnf1bhu_r, | |
5243 | gen_helper_sve_ldnf1bsu_r, | |
5244 | gen_helper_sve_ldnf1bdu_r, | |
5245 | ||
5246 | gen_helper_sve_ldnf1sds_be_r, | |
5247 | gen_helper_sve_ldnf1hh_be_r, | |
5248 | gen_helper_sve_ldnf1hsu_be_r, | |
5249 | gen_helper_sve_ldnf1hdu_be_r, | |
5250 | ||
5251 | gen_helper_sve_ldnf1hds_be_r, | |
5252 | gen_helper_sve_ldnf1hss_be_r, | |
5253 | gen_helper_sve_ldnf1ss_be_r, | |
5254 | gen_helper_sve_ldnf1sdu_be_r, | |
5255 | ||
5256 | gen_helper_sve_ldnf1bds_r, | |
5257 | gen_helper_sve_ldnf1bss_r, | |
5258 | gen_helper_sve_ldnf1bhs_r, | |
5259 | gen_helper_sve_ldnf1dd_be_r } }, | |
5260 | ||
5261 | { /* mte inactive, little-endian */ | |
5262 | { gen_helper_sve_ldnf1bb_r_mte, | |
5263 | gen_helper_sve_ldnf1bhu_r_mte, | |
5264 | gen_helper_sve_ldnf1bsu_r_mte, | |
5265 | gen_helper_sve_ldnf1bdu_r_mte, | |
5266 | ||
5267 | gen_helper_sve_ldnf1sds_le_r_mte, | |
5268 | gen_helper_sve_ldnf1hh_le_r_mte, | |
5269 | gen_helper_sve_ldnf1hsu_le_r_mte, | |
5270 | gen_helper_sve_ldnf1hdu_le_r_mte, | |
5271 | ||
5272 | gen_helper_sve_ldnf1hds_le_r_mte, | |
5273 | gen_helper_sve_ldnf1hss_le_r_mte, | |
5274 | gen_helper_sve_ldnf1ss_le_r_mte, | |
5275 | gen_helper_sve_ldnf1sdu_le_r_mte, | |
5276 | ||
5277 | gen_helper_sve_ldnf1bds_r_mte, | |
5278 | gen_helper_sve_ldnf1bss_r_mte, | |
5279 | gen_helper_sve_ldnf1bhs_r_mte, | |
5280 | gen_helper_sve_ldnf1dd_le_r_mte }, | |
5281 | ||
5282 | /* mte inactive, big-endian */ | |
5283 | { gen_helper_sve_ldnf1bb_r_mte, | |
5284 | gen_helper_sve_ldnf1bhu_r_mte, | |
5285 | gen_helper_sve_ldnf1bsu_r_mte, | |
5286 | gen_helper_sve_ldnf1bdu_r_mte, | |
5287 | ||
5288 | gen_helper_sve_ldnf1sds_be_r_mte, | |
5289 | gen_helper_sve_ldnf1hh_be_r_mte, | |
5290 | gen_helper_sve_ldnf1hsu_be_r_mte, | |
5291 | gen_helper_sve_ldnf1hdu_be_r_mte, | |
5292 | ||
5293 | gen_helper_sve_ldnf1hds_be_r_mte, | |
5294 | gen_helper_sve_ldnf1hss_be_r_mte, | |
5295 | gen_helper_sve_ldnf1ss_be_r_mte, | |
5296 | gen_helper_sve_ldnf1sdu_be_r_mte, | |
5297 | ||
5298 | gen_helper_sve_ldnf1bds_r_mte, | |
5299 | gen_helper_sve_ldnf1bss_r_mte, | |
5300 | gen_helper_sve_ldnf1bhs_r_mte, | |
5301 | gen_helper_sve_ldnf1dd_be_r_mte } }, | |
e2654d75 RH |
5302 | }; |
5303 | ||
5304 | if (sve_access_check(s)) { | |
5305 | int vsz = vec_full_reg_size(s); | |
5306 | int elements = vsz >> dtype_esz[a->dtype]; | |
5307 | int off = (a->imm * elements) << dtype_msz(a->dtype); | |
5308 | TCGv_i64 addr = new_tmp_a64(s); | |
5309 | ||
5310 | tcg_gen_addi_i64(addr, cpu_reg_sp(s, a->rn), off); | |
aa13f7c3 RH |
5311 | do_mem_zpa(s, a->rd, a->pg, addr, a->dtype, 1, false, |
5312 | fns[s->mte_active[0]][s->be_data == MO_BE][a->dtype]); | |
e2654d75 RH |
5313 | } |
5314 | return true; | |
5315 | } | |
1a039c7e | 5316 | |
c182c6db | 5317 | static void do_ldrq(DisasContext *s, int zt, int pg, TCGv_i64 addr, int dtype) |
05abe304 | 5318 | { |
05abe304 RH |
5319 | unsigned vsz = vec_full_reg_size(s); |
5320 | TCGv_ptr t_pg; | |
7924d239 | 5321 | int poff; |
05abe304 RH |
5322 | |
5323 | /* Load the first quadword using the normal predicated load helpers. */ | |
2a99ab2b RH |
5324 | poff = pred_full_reg_offset(s, pg); |
5325 | if (vsz > 16) { | |
5326 | /* | |
5327 | * Zero-extend the first 16 bits of the predicate into a temporary. | |
5328 | * This avoids triggering an assert making sure we don't have bits | |
5329 | * set within a predicate beyond VQ, but we have lowered VQ to 1 | |
5330 | * for this load operation. | |
5331 | */ | |
5332 | TCGv_i64 tmp = tcg_temp_new_i64(); | |
e03b5686 | 5333 | #if HOST_BIG_ENDIAN |
2a99ab2b RH |
5334 | poff += 6; |
5335 | #endif | |
5336 | tcg_gen_ld16u_i64(tmp, cpu_env, poff); | |
5337 | ||
5338 | poff = offsetof(CPUARMState, vfp.preg_tmp); | |
5339 | tcg_gen_st_i64(tmp, cpu_env, poff); | |
5340 | tcg_temp_free_i64(tmp); | |
5341 | } | |
5342 | ||
05abe304 | 5343 | t_pg = tcg_temp_new_ptr(); |
2a99ab2b | 5344 | tcg_gen_addi_ptr(t_pg, cpu_env, poff); |
05abe304 | 5345 | |
c182c6db RH |
5346 | gen_helper_gvec_mem *fn |
5347 | = ldr_fns[s->mte_active[0]][s->be_data == MO_BE][dtype][0]; | |
7924d239 | 5348 | fn(cpu_env, t_pg, addr, tcg_constant_i32(simd_desc(16, 16, zt))); |
05abe304 RH |
5349 | |
5350 | tcg_temp_free_ptr(t_pg); | |
05abe304 RH |
5351 | |
5352 | /* Replicate that first quadword. */ | |
5353 | if (vsz > 16) { | |
7924d239 RH |
5354 | int doff = vec_full_reg_offset(s, zt); |
5355 | tcg_gen_gvec_dup_mem(4, doff + 16, doff, vsz - 16, vsz - 16); | |
05abe304 RH |
5356 | } |
5357 | } | |
5358 | ||
3a7be554 | 5359 | static bool trans_LD1RQ_zprr(DisasContext *s, arg_rprr_load *a) |
05abe304 RH |
5360 | { |
5361 | if (a->rm == 31) { | |
5362 | return false; | |
5363 | } | |
5364 | if (sve_access_check(s)) { | |
5365 | int msz = dtype_msz(a->dtype); | |
5366 | TCGv_i64 addr = new_tmp_a64(s); | |
5367 | tcg_gen_shli_i64(addr, cpu_reg(s, a->rm), msz); | |
5368 | tcg_gen_add_i64(addr, addr, cpu_reg_sp(s, a->rn)); | |
c182c6db | 5369 | do_ldrq(s, a->rd, a->pg, addr, a->dtype); |
05abe304 RH |
5370 | } |
5371 | return true; | |
5372 | } | |
5373 | ||
3a7be554 | 5374 | static bool trans_LD1RQ_zpri(DisasContext *s, arg_rpri_load *a) |
05abe304 RH |
5375 | { |
5376 | if (sve_access_check(s)) { | |
5377 | TCGv_i64 addr = new_tmp_a64(s); | |
5378 | tcg_gen_addi_i64(addr, cpu_reg_sp(s, a->rn), a->imm * 16); | |
c182c6db | 5379 | do_ldrq(s, a->rd, a->pg, addr, a->dtype); |
05abe304 RH |
5380 | } |
5381 | return true; | |
5382 | } | |
5383 | ||
12c563f6 RH |
5384 | static void do_ldro(DisasContext *s, int zt, int pg, TCGv_i64 addr, int dtype) |
5385 | { | |
5386 | unsigned vsz = vec_full_reg_size(s); | |
5387 | unsigned vsz_r32; | |
5388 | TCGv_ptr t_pg; | |
5389 | int poff, doff; | |
5390 | ||
5391 | if (vsz < 32) { | |
5392 | /* | |
5393 | * Note that this UNDEFINED check comes after CheckSVEEnabled() | |
5394 | * in the ARM pseudocode, which is the sve_access_check() done | |
5395 | * in our caller. We should not now return false from the caller. | |
5396 | */ | |
5397 | unallocated_encoding(s); | |
5398 | return; | |
5399 | } | |
5400 | ||
5401 | /* Load the first octaword using the normal predicated load helpers. */ | |
5402 | ||
5403 | poff = pred_full_reg_offset(s, pg); | |
5404 | if (vsz > 32) { | |
5405 | /* | |
5406 | * Zero-extend the first 32 bits of the predicate into a temporary. | |
5407 | * This avoids triggering an assert making sure we don't have bits | |
5408 | * set within a predicate beyond VQ, but we have lowered VQ to 2 | |
5409 | * for this load operation. | |
5410 | */ | |
5411 | TCGv_i64 tmp = tcg_temp_new_i64(); | |
e03b5686 | 5412 | #if HOST_BIG_ENDIAN |
12c563f6 RH |
5413 | poff += 4; |
5414 | #endif | |
5415 | tcg_gen_ld32u_i64(tmp, cpu_env, poff); | |
5416 | ||
5417 | poff = offsetof(CPUARMState, vfp.preg_tmp); | |
5418 | tcg_gen_st_i64(tmp, cpu_env, poff); | |
5419 | tcg_temp_free_i64(tmp); | |
5420 | } | |
5421 | ||
5422 | t_pg = tcg_temp_new_ptr(); | |
5423 | tcg_gen_addi_ptr(t_pg, cpu_env, poff); | |
5424 | ||
5425 | gen_helper_gvec_mem *fn | |
5426 | = ldr_fns[s->mte_active[0]][s->be_data == MO_BE][dtype][0]; | |
5427 | fn(cpu_env, t_pg, addr, tcg_constant_i32(simd_desc(32, 32, zt))); | |
5428 | ||
5429 | tcg_temp_free_ptr(t_pg); | |
5430 | ||
5431 | /* | |
5432 | * Replicate that first octaword. | |
5433 | * The replication happens in units of 32; if the full vector size | |
5434 | * is not a multiple of 32, the final bits are zeroed. | |
5435 | */ | |
5436 | doff = vec_full_reg_offset(s, zt); | |
5437 | vsz_r32 = QEMU_ALIGN_DOWN(vsz, 32); | |
5438 | if (vsz >= 64) { | |
5439 | tcg_gen_gvec_dup_mem(5, doff + 32, doff, vsz_r32 - 32, vsz_r32 - 32); | |
5440 | } | |
5441 | vsz -= vsz_r32; | |
5442 | if (vsz) { | |
5443 | tcg_gen_gvec_dup_imm(MO_64, doff + vsz_r32, vsz, vsz, 0); | |
5444 | } | |
5445 | } | |
5446 | ||
5447 | static bool trans_LD1RO_zprr(DisasContext *s, arg_rprr_load *a) | |
5448 | { | |
5449 | if (!dc_isar_feature(aa64_sve_f64mm, s)) { | |
5450 | return false; | |
5451 | } | |
5452 | if (a->rm == 31) { | |
5453 | return false; | |
5454 | } | |
5455 | if (sve_access_check(s)) { | |
5456 | TCGv_i64 addr = new_tmp_a64(s); | |
5457 | tcg_gen_shli_i64(addr, cpu_reg(s, a->rm), dtype_msz(a->dtype)); | |
5458 | tcg_gen_add_i64(addr, addr, cpu_reg_sp(s, a->rn)); | |
5459 | do_ldro(s, a->rd, a->pg, addr, a->dtype); | |
5460 | } | |
5461 | return true; | |
5462 | } | |
5463 | ||
5464 | static bool trans_LD1RO_zpri(DisasContext *s, arg_rpri_load *a) | |
5465 | { | |
5466 | if (!dc_isar_feature(aa64_sve_f64mm, s)) { | |
5467 | return false; | |
5468 | } | |
5469 | if (sve_access_check(s)) { | |
5470 | TCGv_i64 addr = new_tmp_a64(s); | |
5471 | tcg_gen_addi_i64(addr, cpu_reg_sp(s, a->rn), a->imm * 32); | |
5472 | do_ldro(s, a->rd, a->pg, addr, a->dtype); | |
5473 | } | |
5474 | return true; | |
5475 | } | |
5476 | ||
68459864 | 5477 | /* Load and broadcast element. */ |
3a7be554 | 5478 | static bool trans_LD1R_zpri(DisasContext *s, arg_rpri_load *a) |
68459864 | 5479 | { |
68459864 RH |
5480 | unsigned vsz = vec_full_reg_size(s); |
5481 | unsigned psz = pred_full_reg_size(s); | |
5482 | unsigned esz = dtype_esz[a->dtype]; | |
d0e372b0 | 5483 | unsigned msz = dtype_msz(a->dtype); |
c0ed9166 | 5484 | TCGLabel *over; |
4ac430e1 | 5485 | TCGv_i64 temp, clean_addr; |
68459864 | 5486 | |
c0ed9166 RH |
5487 | if (!sve_access_check(s)) { |
5488 | return true; | |
5489 | } | |
5490 | ||
5491 | over = gen_new_label(); | |
5492 | ||
68459864 RH |
5493 | /* If the guarding predicate has no bits set, no load occurs. */ |
5494 | if (psz <= 8) { | |
5495 | /* Reduce the pred_esz_masks value simply to reduce the | |
5496 | * size of the code generated here. | |
5497 | */ | |
5498 | uint64_t psz_mask = MAKE_64BIT_MASK(0, psz * 8); | |
5499 | temp = tcg_temp_new_i64(); | |
5500 | tcg_gen_ld_i64(temp, cpu_env, pred_full_reg_offset(s, a->pg)); | |
5501 | tcg_gen_andi_i64(temp, temp, pred_esz_masks[esz] & psz_mask); | |
5502 | tcg_gen_brcondi_i64(TCG_COND_EQ, temp, 0, over); | |
5503 | tcg_temp_free_i64(temp); | |
5504 | } else { | |
5505 | TCGv_i32 t32 = tcg_temp_new_i32(); | |
5506 | find_last_active(s, t32, esz, a->pg); | |
5507 | tcg_gen_brcondi_i32(TCG_COND_LT, t32, 0, over); | |
5508 | tcg_temp_free_i32(t32); | |
5509 | } | |
5510 | ||
5511 | /* Load the data. */ | |
5512 | temp = tcg_temp_new_i64(); | |
d0e372b0 | 5513 | tcg_gen_addi_i64(temp, cpu_reg_sp(s, a->rn), a->imm << msz); |
4ac430e1 RH |
5514 | clean_addr = gen_mte_check1(s, temp, false, true, msz); |
5515 | ||
5516 | tcg_gen_qemu_ld_i64(temp, clean_addr, get_mem_index(s), | |
0ca0f872 | 5517 | finalize_memop(s, dtype_mop[a->dtype])); |
68459864 RH |
5518 | |
5519 | /* Broadcast to *all* elements. */ | |
5520 | tcg_gen_gvec_dup_i64(esz, vec_full_reg_offset(s, a->rd), | |
5521 | vsz, vsz, temp); | |
5522 | tcg_temp_free_i64(temp); | |
5523 | ||
5524 | /* Zero the inactive elements. */ | |
5525 | gen_set_label(over); | |
60245996 | 5526 | return do_movz_zpz(s, a->rd, a->rd, a->pg, esz, false); |
68459864 RH |
5527 | } |
5528 | ||
1a039c7e RH |
5529 | static void do_st_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr, |
5530 | int msz, int esz, int nreg) | |
5531 | { | |
71b9f394 RH |
5532 | static gen_helper_gvec_mem * const fn_single[2][2][4][4] = { |
5533 | { { { gen_helper_sve_st1bb_r, | |
5534 | gen_helper_sve_st1bh_r, | |
5535 | gen_helper_sve_st1bs_r, | |
5536 | gen_helper_sve_st1bd_r }, | |
5537 | { NULL, | |
5538 | gen_helper_sve_st1hh_le_r, | |
5539 | gen_helper_sve_st1hs_le_r, | |
5540 | gen_helper_sve_st1hd_le_r }, | |
5541 | { NULL, NULL, | |
5542 | gen_helper_sve_st1ss_le_r, | |
5543 | gen_helper_sve_st1sd_le_r }, | |
5544 | { NULL, NULL, NULL, | |
5545 | gen_helper_sve_st1dd_le_r } }, | |
5546 | { { gen_helper_sve_st1bb_r, | |
5547 | gen_helper_sve_st1bh_r, | |
5548 | gen_helper_sve_st1bs_r, | |
5549 | gen_helper_sve_st1bd_r }, | |
5550 | { NULL, | |
5551 | gen_helper_sve_st1hh_be_r, | |
5552 | gen_helper_sve_st1hs_be_r, | |
5553 | gen_helper_sve_st1hd_be_r }, | |
5554 | { NULL, NULL, | |
5555 | gen_helper_sve_st1ss_be_r, | |
5556 | gen_helper_sve_st1sd_be_r }, | |
5557 | { NULL, NULL, NULL, | |
5558 | gen_helper_sve_st1dd_be_r } } }, | |
5559 | ||
5560 | { { { gen_helper_sve_st1bb_r_mte, | |
5561 | gen_helper_sve_st1bh_r_mte, | |
5562 | gen_helper_sve_st1bs_r_mte, | |
5563 | gen_helper_sve_st1bd_r_mte }, | |
5564 | { NULL, | |
5565 | gen_helper_sve_st1hh_le_r_mte, | |
5566 | gen_helper_sve_st1hs_le_r_mte, | |
5567 | gen_helper_sve_st1hd_le_r_mte }, | |
5568 | { NULL, NULL, | |
5569 | gen_helper_sve_st1ss_le_r_mte, | |
5570 | gen_helper_sve_st1sd_le_r_mte }, | |
5571 | { NULL, NULL, NULL, | |
5572 | gen_helper_sve_st1dd_le_r_mte } }, | |
5573 | { { gen_helper_sve_st1bb_r_mte, | |
5574 | gen_helper_sve_st1bh_r_mte, | |
5575 | gen_helper_sve_st1bs_r_mte, | |
5576 | gen_helper_sve_st1bd_r_mte }, | |
5577 | { NULL, | |
5578 | gen_helper_sve_st1hh_be_r_mte, | |
5579 | gen_helper_sve_st1hs_be_r_mte, | |
5580 | gen_helper_sve_st1hd_be_r_mte }, | |
5581 | { NULL, NULL, | |
5582 | gen_helper_sve_st1ss_be_r_mte, | |
5583 | gen_helper_sve_st1sd_be_r_mte }, | |
5584 | { NULL, NULL, NULL, | |
5585 | gen_helper_sve_st1dd_be_r_mte } } }, | |
1a039c7e | 5586 | }; |
71b9f394 RH |
5587 | static gen_helper_gvec_mem * const fn_multiple[2][2][3][4] = { |
5588 | { { { gen_helper_sve_st2bb_r, | |
5589 | gen_helper_sve_st2hh_le_r, | |
5590 | gen_helper_sve_st2ss_le_r, | |
5591 | gen_helper_sve_st2dd_le_r }, | |
5592 | { gen_helper_sve_st3bb_r, | |
5593 | gen_helper_sve_st3hh_le_r, | |
5594 | gen_helper_sve_st3ss_le_r, | |
5595 | gen_helper_sve_st3dd_le_r }, | |
5596 | { gen_helper_sve_st4bb_r, | |
5597 | gen_helper_sve_st4hh_le_r, | |
5598 | gen_helper_sve_st4ss_le_r, | |
5599 | gen_helper_sve_st4dd_le_r } }, | |
5600 | { { gen_helper_sve_st2bb_r, | |
5601 | gen_helper_sve_st2hh_be_r, | |
5602 | gen_helper_sve_st2ss_be_r, | |
5603 | gen_helper_sve_st2dd_be_r }, | |
5604 | { gen_helper_sve_st3bb_r, | |
5605 | gen_helper_sve_st3hh_be_r, | |
5606 | gen_helper_sve_st3ss_be_r, | |
5607 | gen_helper_sve_st3dd_be_r }, | |
5608 | { gen_helper_sve_st4bb_r, | |
5609 | gen_helper_sve_st4hh_be_r, | |
5610 | gen_helper_sve_st4ss_be_r, | |
5611 | gen_helper_sve_st4dd_be_r } } }, | |
5612 | { { { gen_helper_sve_st2bb_r_mte, | |
5613 | gen_helper_sve_st2hh_le_r_mte, | |
5614 | gen_helper_sve_st2ss_le_r_mte, | |
5615 | gen_helper_sve_st2dd_le_r_mte }, | |
5616 | { gen_helper_sve_st3bb_r_mte, | |
5617 | gen_helper_sve_st3hh_le_r_mte, | |
5618 | gen_helper_sve_st3ss_le_r_mte, | |
5619 | gen_helper_sve_st3dd_le_r_mte }, | |
5620 | { gen_helper_sve_st4bb_r_mte, | |
5621 | gen_helper_sve_st4hh_le_r_mte, | |
5622 | gen_helper_sve_st4ss_le_r_mte, | |
5623 | gen_helper_sve_st4dd_le_r_mte } }, | |
5624 | { { gen_helper_sve_st2bb_r_mte, | |
5625 | gen_helper_sve_st2hh_be_r_mte, | |
5626 | gen_helper_sve_st2ss_be_r_mte, | |
5627 | gen_helper_sve_st2dd_be_r_mte }, | |
5628 | { gen_helper_sve_st3bb_r_mte, | |
5629 | gen_helper_sve_st3hh_be_r_mte, | |
5630 | gen_helper_sve_st3ss_be_r_mte, | |
5631 | gen_helper_sve_st3dd_be_r_mte }, | |
5632 | { gen_helper_sve_st4bb_r_mte, | |
5633 | gen_helper_sve_st4hh_be_r_mte, | |
5634 | gen_helper_sve_st4ss_be_r_mte, | |
5635 | gen_helper_sve_st4dd_be_r_mte } } }, | |
1a039c7e RH |
5636 | }; |
5637 | gen_helper_gvec_mem *fn; | |
28d57f2d | 5638 | int be = s->be_data == MO_BE; |
1a039c7e RH |
5639 | |
5640 | if (nreg == 0) { | |
5641 | /* ST1 */ | |
71b9f394 RH |
5642 | fn = fn_single[s->mte_active[0]][be][msz][esz]; |
5643 | nreg = 1; | |
1a039c7e RH |
5644 | } else { |
5645 | /* ST2, ST3, ST4 -- msz == esz, enforced by encoding */ | |
5646 | assert(msz == esz); | |
71b9f394 | 5647 | fn = fn_multiple[s->mte_active[0]][be][nreg - 1][msz]; |
1a039c7e RH |
5648 | } |
5649 | assert(fn != NULL); | |
71b9f394 | 5650 | do_mem_zpa(s, zt, pg, addr, msz_dtype(s, msz), nreg, true, fn); |
1a039c7e RH |
5651 | } |
5652 | ||
3a7be554 | 5653 | static bool trans_ST_zprr(DisasContext *s, arg_rprr_store *a) |
1a039c7e RH |
5654 | { |
5655 | if (a->rm == 31 || a->msz > a->esz) { | |
5656 | return false; | |
5657 | } | |
5658 | if (sve_access_check(s)) { | |
5659 | TCGv_i64 addr = new_tmp_a64(s); | |
50ef1cbf | 5660 | tcg_gen_shli_i64(addr, cpu_reg(s, a->rm), a->msz); |
1a039c7e RH |
5661 | tcg_gen_add_i64(addr, addr, cpu_reg_sp(s, a->rn)); |
5662 | do_st_zpa(s, a->rd, a->pg, addr, a->msz, a->esz, a->nreg); | |
5663 | } | |
5664 | return true; | |
5665 | } | |
5666 | ||
3a7be554 | 5667 | static bool trans_ST_zpri(DisasContext *s, arg_rpri_store *a) |
1a039c7e RH |
5668 | { |
5669 | if (a->msz > a->esz) { | |
5670 | return false; | |
5671 | } | |
5672 | if (sve_access_check(s)) { | |
5673 | int vsz = vec_full_reg_size(s); | |
5674 | int elements = vsz >> a->esz; | |
5675 | TCGv_i64 addr = new_tmp_a64(s); | |
5676 | ||
5677 | tcg_gen_addi_i64(addr, cpu_reg_sp(s, a->rn), | |
5678 | (a->imm * elements * (a->nreg + 1)) << a->msz); | |
5679 | do_st_zpa(s, a->rd, a->pg, addr, a->msz, a->esz, a->nreg); | |
5680 | } | |
5681 | return true; | |
5682 | } | |
f6dbf62a RH |
5683 | |
5684 | /* | |
5685 | *** SVE gather loads / scatter stores | |
5686 | */ | |
5687 | ||
500d0484 | 5688 | static void do_mem_zpz(DisasContext *s, int zt, int pg, int zm, |
d28d12f0 | 5689 | int scale, TCGv_i64 scalar, int msz, bool is_write, |
500d0484 | 5690 | gen_helper_gvec_mem_scatter *fn) |
f6dbf62a RH |
5691 | { |
5692 | unsigned vsz = vec_full_reg_size(s); | |
f6dbf62a RH |
5693 | TCGv_ptr t_zm = tcg_temp_new_ptr(); |
5694 | TCGv_ptr t_pg = tcg_temp_new_ptr(); | |
5695 | TCGv_ptr t_zt = tcg_temp_new_ptr(); | |
d28d12f0 | 5696 | int desc = 0; |
500d0484 | 5697 | |
d28d12f0 RH |
5698 | if (s->mte_active[0]) { |
5699 | desc = FIELD_DP32(desc, MTEDESC, MIDX, get_mem_index(s)); | |
5700 | desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid); | |
5701 | desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma); | |
5702 | desc = FIELD_DP32(desc, MTEDESC, WRITE, is_write); | |
28f32503 | 5703 | desc = FIELD_DP32(desc, MTEDESC, SIZEM1, (1 << msz) - 1); |
d28d12f0 RH |
5704 | desc <<= SVE_MTEDESC_SHIFT; |
5705 | } | |
cdecb3fc | 5706 | desc = simd_desc(vsz, vsz, desc | scale); |
f6dbf62a RH |
5707 | |
5708 | tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, pg)); | |
5709 | tcg_gen_addi_ptr(t_zm, cpu_env, vec_full_reg_offset(s, zm)); | |
5710 | tcg_gen_addi_ptr(t_zt, cpu_env, vec_full_reg_offset(s, zt)); | |
c6a59b55 | 5711 | fn(cpu_env, t_zt, t_pg, t_zm, scalar, tcg_constant_i32(desc)); |
f6dbf62a RH |
5712 | |
5713 | tcg_temp_free_ptr(t_zt); | |
5714 | tcg_temp_free_ptr(t_zm); | |
5715 | tcg_temp_free_ptr(t_pg); | |
f6dbf62a RH |
5716 | } |
5717 | ||
d28d12f0 RH |
5718 | /* Indexed by [mte][be][ff][xs][u][msz]. */ |
5719 | static gen_helper_gvec_mem_scatter * const | |
5720 | gather_load_fn32[2][2][2][2][2][3] = { | |
5721 | { /* MTE Inactive */ | |
5722 | { /* Little-endian */ | |
5723 | { { { gen_helper_sve_ldbss_zsu, | |
5724 | gen_helper_sve_ldhss_le_zsu, | |
5725 | NULL, }, | |
5726 | { gen_helper_sve_ldbsu_zsu, | |
5727 | gen_helper_sve_ldhsu_le_zsu, | |
5728 | gen_helper_sve_ldss_le_zsu, } }, | |
5729 | { { gen_helper_sve_ldbss_zss, | |
5730 | gen_helper_sve_ldhss_le_zss, | |
5731 | NULL, }, | |
5732 | { gen_helper_sve_ldbsu_zss, | |
5733 | gen_helper_sve_ldhsu_le_zss, | |
5734 | gen_helper_sve_ldss_le_zss, } } }, | |
5735 | ||
5736 | /* First-fault */ | |
5737 | { { { gen_helper_sve_ldffbss_zsu, | |
5738 | gen_helper_sve_ldffhss_le_zsu, | |
5739 | NULL, }, | |
5740 | { gen_helper_sve_ldffbsu_zsu, | |
5741 | gen_helper_sve_ldffhsu_le_zsu, | |
5742 | gen_helper_sve_ldffss_le_zsu, } }, | |
5743 | { { gen_helper_sve_ldffbss_zss, | |
5744 | gen_helper_sve_ldffhss_le_zss, | |
5745 | NULL, }, | |
5746 | { gen_helper_sve_ldffbsu_zss, | |
5747 | gen_helper_sve_ldffhsu_le_zss, | |
5748 | gen_helper_sve_ldffss_le_zss, } } } }, | |
5749 | ||
5750 | { /* Big-endian */ | |
5751 | { { { gen_helper_sve_ldbss_zsu, | |
5752 | gen_helper_sve_ldhss_be_zsu, | |
5753 | NULL, }, | |
5754 | { gen_helper_sve_ldbsu_zsu, | |
5755 | gen_helper_sve_ldhsu_be_zsu, | |
5756 | gen_helper_sve_ldss_be_zsu, } }, | |
5757 | { { gen_helper_sve_ldbss_zss, | |
5758 | gen_helper_sve_ldhss_be_zss, | |
5759 | NULL, }, | |
5760 | { gen_helper_sve_ldbsu_zss, | |
5761 | gen_helper_sve_ldhsu_be_zss, | |
5762 | gen_helper_sve_ldss_be_zss, } } }, | |
5763 | ||
5764 | /* First-fault */ | |
5765 | { { { gen_helper_sve_ldffbss_zsu, | |
5766 | gen_helper_sve_ldffhss_be_zsu, | |
5767 | NULL, }, | |
5768 | { gen_helper_sve_ldffbsu_zsu, | |
5769 | gen_helper_sve_ldffhsu_be_zsu, | |
5770 | gen_helper_sve_ldffss_be_zsu, } }, | |
5771 | { { gen_helper_sve_ldffbss_zss, | |
5772 | gen_helper_sve_ldffhss_be_zss, | |
5773 | NULL, }, | |
5774 | { gen_helper_sve_ldffbsu_zss, | |
5775 | gen_helper_sve_ldffhsu_be_zss, | |
5776 | gen_helper_sve_ldffss_be_zss, } } } } }, | |
5777 | { /* MTE Active */ | |
5778 | { /* Little-endian */ | |
5779 | { { { gen_helper_sve_ldbss_zsu_mte, | |
5780 | gen_helper_sve_ldhss_le_zsu_mte, | |
5781 | NULL, }, | |
5782 | { gen_helper_sve_ldbsu_zsu_mte, | |
5783 | gen_helper_sve_ldhsu_le_zsu_mte, | |
5784 | gen_helper_sve_ldss_le_zsu_mte, } }, | |
5785 | { { gen_helper_sve_ldbss_zss_mte, | |
5786 | gen_helper_sve_ldhss_le_zss_mte, | |
5787 | NULL, }, | |
5788 | { gen_helper_sve_ldbsu_zss_mte, | |
5789 | gen_helper_sve_ldhsu_le_zss_mte, | |
5790 | gen_helper_sve_ldss_le_zss_mte, } } }, | |
5791 | ||
5792 | /* First-fault */ | |
5793 | { { { gen_helper_sve_ldffbss_zsu_mte, | |
5794 | gen_helper_sve_ldffhss_le_zsu_mte, | |
5795 | NULL, }, | |
5796 | { gen_helper_sve_ldffbsu_zsu_mte, | |
5797 | gen_helper_sve_ldffhsu_le_zsu_mte, | |
5798 | gen_helper_sve_ldffss_le_zsu_mte, } }, | |
5799 | { { gen_helper_sve_ldffbss_zss_mte, | |
5800 | gen_helper_sve_ldffhss_le_zss_mte, | |
5801 | NULL, }, | |
5802 | { gen_helper_sve_ldffbsu_zss_mte, | |
5803 | gen_helper_sve_ldffhsu_le_zss_mte, | |
5804 | gen_helper_sve_ldffss_le_zss_mte, } } } }, | |
5805 | ||
5806 | { /* Big-endian */ | |
5807 | { { { gen_helper_sve_ldbss_zsu_mte, | |
5808 | gen_helper_sve_ldhss_be_zsu_mte, | |
5809 | NULL, }, | |
5810 | { gen_helper_sve_ldbsu_zsu_mte, | |
5811 | gen_helper_sve_ldhsu_be_zsu_mte, | |
5812 | gen_helper_sve_ldss_be_zsu_mte, } }, | |
5813 | { { gen_helper_sve_ldbss_zss_mte, | |
5814 | gen_helper_sve_ldhss_be_zss_mte, | |
5815 | NULL, }, | |
5816 | { gen_helper_sve_ldbsu_zss_mte, | |
5817 | gen_helper_sve_ldhsu_be_zss_mte, | |
5818 | gen_helper_sve_ldss_be_zss_mte, } } }, | |
5819 | ||
5820 | /* First-fault */ | |
5821 | { { { gen_helper_sve_ldffbss_zsu_mte, | |
5822 | gen_helper_sve_ldffhss_be_zsu_mte, | |
5823 | NULL, }, | |
5824 | { gen_helper_sve_ldffbsu_zsu_mte, | |
5825 | gen_helper_sve_ldffhsu_be_zsu_mte, | |
5826 | gen_helper_sve_ldffss_be_zsu_mte, } }, | |
5827 | { { gen_helper_sve_ldffbss_zss_mte, | |
5828 | gen_helper_sve_ldffhss_be_zss_mte, | |
5829 | NULL, }, | |
5830 | { gen_helper_sve_ldffbsu_zss_mte, | |
5831 | gen_helper_sve_ldffhsu_be_zss_mte, | |
5832 | gen_helper_sve_ldffss_be_zss_mte, } } } } }, | |
673e9fa6 RH |
5833 | }; |
5834 | ||
5835 | /* Note that we overload xs=2 to indicate 64-bit offset. */ | |
d28d12f0 RH |
5836 | static gen_helper_gvec_mem_scatter * const |
5837 | gather_load_fn64[2][2][2][3][2][4] = { | |
5838 | { /* MTE Inactive */ | |
5839 | { /* Little-endian */ | |
5840 | { { { gen_helper_sve_ldbds_zsu, | |
5841 | gen_helper_sve_ldhds_le_zsu, | |
5842 | gen_helper_sve_ldsds_le_zsu, | |
5843 | NULL, }, | |
5844 | { gen_helper_sve_ldbdu_zsu, | |
5845 | gen_helper_sve_ldhdu_le_zsu, | |
5846 | gen_helper_sve_ldsdu_le_zsu, | |
5847 | gen_helper_sve_lddd_le_zsu, } }, | |
5848 | { { gen_helper_sve_ldbds_zss, | |
5849 | gen_helper_sve_ldhds_le_zss, | |
5850 | gen_helper_sve_ldsds_le_zss, | |
5851 | NULL, }, | |
5852 | { gen_helper_sve_ldbdu_zss, | |
5853 | gen_helper_sve_ldhdu_le_zss, | |
5854 | gen_helper_sve_ldsdu_le_zss, | |
5855 | gen_helper_sve_lddd_le_zss, } }, | |
5856 | { { gen_helper_sve_ldbds_zd, | |
5857 | gen_helper_sve_ldhds_le_zd, | |
5858 | gen_helper_sve_ldsds_le_zd, | |
5859 | NULL, }, | |
5860 | { gen_helper_sve_ldbdu_zd, | |
5861 | gen_helper_sve_ldhdu_le_zd, | |
5862 | gen_helper_sve_ldsdu_le_zd, | |
5863 | gen_helper_sve_lddd_le_zd, } } }, | |
5864 | ||
5865 | /* First-fault */ | |
5866 | { { { gen_helper_sve_ldffbds_zsu, | |
5867 | gen_helper_sve_ldffhds_le_zsu, | |
5868 | gen_helper_sve_ldffsds_le_zsu, | |
5869 | NULL, }, | |
5870 | { gen_helper_sve_ldffbdu_zsu, | |
5871 | gen_helper_sve_ldffhdu_le_zsu, | |
5872 | gen_helper_sve_ldffsdu_le_zsu, | |
5873 | gen_helper_sve_ldffdd_le_zsu, } }, | |
5874 | { { gen_helper_sve_ldffbds_zss, | |
5875 | gen_helper_sve_ldffhds_le_zss, | |
5876 | gen_helper_sve_ldffsds_le_zss, | |
5877 | NULL, }, | |
5878 | { gen_helper_sve_ldffbdu_zss, | |
5879 | gen_helper_sve_ldffhdu_le_zss, | |
5880 | gen_helper_sve_ldffsdu_le_zss, | |
5881 | gen_helper_sve_ldffdd_le_zss, } }, | |
5882 | { { gen_helper_sve_ldffbds_zd, | |
5883 | gen_helper_sve_ldffhds_le_zd, | |
5884 | gen_helper_sve_ldffsds_le_zd, | |
5885 | NULL, }, | |
5886 | { gen_helper_sve_ldffbdu_zd, | |
5887 | gen_helper_sve_ldffhdu_le_zd, | |
5888 | gen_helper_sve_ldffsdu_le_zd, | |
5889 | gen_helper_sve_ldffdd_le_zd, } } } }, | |
5890 | { /* Big-endian */ | |
5891 | { { { gen_helper_sve_ldbds_zsu, | |
5892 | gen_helper_sve_ldhds_be_zsu, | |
5893 | gen_helper_sve_ldsds_be_zsu, | |
5894 | NULL, }, | |
5895 | { gen_helper_sve_ldbdu_zsu, | |
5896 | gen_helper_sve_ldhdu_be_zsu, | |
5897 | gen_helper_sve_ldsdu_be_zsu, | |
5898 | gen_helper_sve_lddd_be_zsu, } }, | |
5899 | { { gen_helper_sve_ldbds_zss, | |
5900 | gen_helper_sve_ldhds_be_zss, | |
5901 | gen_helper_sve_ldsds_be_zss, | |
5902 | NULL, }, | |
5903 | { gen_helper_sve_ldbdu_zss, | |
5904 | gen_helper_sve_ldhdu_be_zss, | |
5905 | gen_helper_sve_ldsdu_be_zss, | |
5906 | gen_helper_sve_lddd_be_zss, } }, | |
5907 | { { gen_helper_sve_ldbds_zd, | |
5908 | gen_helper_sve_ldhds_be_zd, | |
5909 | gen_helper_sve_ldsds_be_zd, | |
5910 | NULL, }, | |
5911 | { gen_helper_sve_ldbdu_zd, | |
5912 | gen_helper_sve_ldhdu_be_zd, | |
5913 | gen_helper_sve_ldsdu_be_zd, | |
5914 | gen_helper_sve_lddd_be_zd, } } }, | |
5915 | ||
5916 | /* First-fault */ | |
5917 | { { { gen_helper_sve_ldffbds_zsu, | |
5918 | gen_helper_sve_ldffhds_be_zsu, | |
5919 | gen_helper_sve_ldffsds_be_zsu, | |
5920 | NULL, }, | |
5921 | { gen_helper_sve_ldffbdu_zsu, | |
5922 | gen_helper_sve_ldffhdu_be_zsu, | |
5923 | gen_helper_sve_ldffsdu_be_zsu, | |
5924 | gen_helper_sve_ldffdd_be_zsu, } }, | |
5925 | { { gen_helper_sve_ldffbds_zss, | |
5926 | gen_helper_sve_ldffhds_be_zss, | |
5927 | gen_helper_sve_ldffsds_be_zss, | |
5928 | NULL, }, | |
5929 | { gen_helper_sve_ldffbdu_zss, | |
5930 | gen_helper_sve_ldffhdu_be_zss, | |
5931 | gen_helper_sve_ldffsdu_be_zss, | |
5932 | gen_helper_sve_ldffdd_be_zss, } }, | |
5933 | { { gen_helper_sve_ldffbds_zd, | |
5934 | gen_helper_sve_ldffhds_be_zd, | |
5935 | gen_helper_sve_ldffsds_be_zd, | |
5936 | NULL, }, | |
5937 | { gen_helper_sve_ldffbdu_zd, | |
5938 | gen_helper_sve_ldffhdu_be_zd, | |
5939 | gen_helper_sve_ldffsdu_be_zd, | |
5940 | gen_helper_sve_ldffdd_be_zd, } } } } }, | |
5941 | { /* MTE Active */ | |
5942 | { /* Little-endian */ | |
5943 | { { { gen_helper_sve_ldbds_zsu_mte, | |
5944 | gen_helper_sve_ldhds_le_zsu_mte, | |
5945 | gen_helper_sve_ldsds_le_zsu_mte, | |
5946 | NULL, }, | |
5947 | { gen_helper_sve_ldbdu_zsu_mte, | |
5948 | gen_helper_sve_ldhdu_le_zsu_mte, | |
5949 | gen_helper_sve_ldsdu_le_zsu_mte, | |
5950 | gen_helper_sve_lddd_le_zsu_mte, } }, | |
5951 | { { gen_helper_sve_ldbds_zss_mte, | |
5952 | gen_helper_sve_ldhds_le_zss_mte, | |
5953 | gen_helper_sve_ldsds_le_zss_mte, | |
5954 | NULL, }, | |
5955 | { gen_helper_sve_ldbdu_zss_mte, | |
5956 | gen_helper_sve_ldhdu_le_zss_mte, | |
5957 | gen_helper_sve_ldsdu_le_zss_mte, | |
5958 | gen_helper_sve_lddd_le_zss_mte, } }, | |
5959 | { { gen_helper_sve_ldbds_zd_mte, | |
5960 | gen_helper_sve_ldhds_le_zd_mte, | |
5961 | gen_helper_sve_ldsds_le_zd_mte, | |
5962 | NULL, }, | |
5963 | { gen_helper_sve_ldbdu_zd_mte, | |
5964 | gen_helper_sve_ldhdu_le_zd_mte, | |
5965 | gen_helper_sve_ldsdu_le_zd_mte, | |
5966 | gen_helper_sve_lddd_le_zd_mte, } } }, | |
5967 | ||
5968 | /* First-fault */ | |
5969 | { { { gen_helper_sve_ldffbds_zsu_mte, | |
5970 | gen_helper_sve_ldffhds_le_zsu_mte, | |
5971 | gen_helper_sve_ldffsds_le_zsu_mte, | |
5972 | NULL, }, | |
5973 | { gen_helper_sve_ldffbdu_zsu_mte, | |
5974 | gen_helper_sve_ldffhdu_le_zsu_mte, | |
5975 | gen_helper_sve_ldffsdu_le_zsu_mte, | |
5976 | gen_helper_sve_ldffdd_le_zsu_mte, } }, | |
5977 | { { gen_helper_sve_ldffbds_zss_mte, | |
5978 | gen_helper_sve_ldffhds_le_zss_mte, | |
5979 | gen_helper_sve_ldffsds_le_zss_mte, | |
5980 | NULL, }, | |
5981 | { gen_helper_sve_ldffbdu_zss_mte, | |
5982 | gen_helper_sve_ldffhdu_le_zss_mte, | |
5983 | gen_helper_sve_ldffsdu_le_zss_mte, | |
5984 | gen_helper_sve_ldffdd_le_zss_mte, } }, | |
5985 | { { gen_helper_sve_ldffbds_zd_mte, | |
5986 | gen_helper_sve_ldffhds_le_zd_mte, | |
5987 | gen_helper_sve_ldffsds_le_zd_mte, | |
5988 | NULL, }, | |
5989 | { gen_helper_sve_ldffbdu_zd_mte, | |
5990 | gen_helper_sve_ldffhdu_le_zd_mte, | |
5991 | gen_helper_sve_ldffsdu_le_zd_mte, | |
5992 | gen_helper_sve_ldffdd_le_zd_mte, } } } }, | |
5993 | { /* Big-endian */ | |
5994 | { { { gen_helper_sve_ldbds_zsu_mte, | |
5995 | gen_helper_sve_ldhds_be_zsu_mte, | |
5996 | gen_helper_sve_ldsds_be_zsu_mte, | |
5997 | NULL, }, | |
5998 | { gen_helper_sve_ldbdu_zsu_mte, | |
5999 | gen_helper_sve_ldhdu_be_zsu_mte, | |
6000 | gen_helper_sve_ldsdu_be_zsu_mte, | |
6001 | gen_helper_sve_lddd_be_zsu_mte, } }, | |
6002 | { { gen_helper_sve_ldbds_zss_mte, | |
6003 | gen_helper_sve_ldhds_be_zss_mte, | |
6004 | gen_helper_sve_ldsds_be_zss_mte, | |
6005 | NULL, }, | |
6006 | { gen_helper_sve_ldbdu_zss_mte, | |
6007 | gen_helper_sve_ldhdu_be_zss_mte, | |
6008 | gen_helper_sve_ldsdu_be_zss_mte, | |
6009 | gen_helper_sve_lddd_be_zss_mte, } }, | |
6010 | { { gen_helper_sve_ldbds_zd_mte, | |
6011 | gen_helper_sve_ldhds_be_zd_mte, | |
6012 | gen_helper_sve_ldsds_be_zd_mte, | |
6013 | NULL, }, | |
6014 | { gen_helper_sve_ldbdu_zd_mte, | |
6015 | gen_helper_sve_ldhdu_be_zd_mte, | |
6016 | gen_helper_sve_ldsdu_be_zd_mte, | |
6017 | gen_helper_sve_lddd_be_zd_mte, } } }, | |
6018 | ||
6019 | /* First-fault */ | |
6020 | { { { gen_helper_sve_ldffbds_zsu_mte, | |
6021 | gen_helper_sve_ldffhds_be_zsu_mte, | |
6022 | gen_helper_sve_ldffsds_be_zsu_mte, | |
6023 | NULL, }, | |
6024 | { gen_helper_sve_ldffbdu_zsu_mte, | |
6025 | gen_helper_sve_ldffhdu_be_zsu_mte, | |
6026 | gen_helper_sve_ldffsdu_be_zsu_mte, | |
6027 | gen_helper_sve_ldffdd_be_zsu_mte, } }, | |
6028 | { { gen_helper_sve_ldffbds_zss_mte, | |
6029 | gen_helper_sve_ldffhds_be_zss_mte, | |
6030 | gen_helper_sve_ldffsds_be_zss_mte, | |
6031 | NULL, }, | |
6032 | { gen_helper_sve_ldffbdu_zss_mte, | |
6033 | gen_helper_sve_ldffhdu_be_zss_mte, | |
6034 | gen_helper_sve_ldffsdu_be_zss_mte, | |
6035 | gen_helper_sve_ldffdd_be_zss_mte, } }, | |
6036 | { { gen_helper_sve_ldffbds_zd_mte, | |
6037 | gen_helper_sve_ldffhds_be_zd_mte, | |
6038 | gen_helper_sve_ldffsds_be_zd_mte, | |
6039 | NULL, }, | |
6040 | { gen_helper_sve_ldffbdu_zd_mte, | |
6041 | gen_helper_sve_ldffhdu_be_zd_mte, | |
6042 | gen_helper_sve_ldffsdu_be_zd_mte, | |
6043 | gen_helper_sve_ldffdd_be_zd_mte, } } } } }, | |
673e9fa6 RH |
6044 | }; |
6045 | ||
3a7be554 | 6046 | static bool trans_LD1_zprz(DisasContext *s, arg_LD1_zprz *a) |
673e9fa6 RH |
6047 | { |
6048 | gen_helper_gvec_mem_scatter *fn = NULL; | |
d28d12f0 RH |
6049 | bool be = s->be_data == MO_BE; |
6050 | bool mte = s->mte_active[0]; | |
673e9fa6 RH |
6051 | |
6052 | if (!sve_access_check(s)) { | |
6053 | return true; | |
6054 | } | |
6055 | ||
6056 | switch (a->esz) { | |
6057 | case MO_32: | |
d28d12f0 | 6058 | fn = gather_load_fn32[mte][be][a->ff][a->xs][a->u][a->msz]; |
673e9fa6 RH |
6059 | break; |
6060 | case MO_64: | |
d28d12f0 | 6061 | fn = gather_load_fn64[mte][be][a->ff][a->xs][a->u][a->msz]; |
673e9fa6 RH |
6062 | break; |
6063 | } | |
6064 | assert(fn != NULL); | |
6065 | ||
6066 | do_mem_zpz(s, a->rd, a->pg, a->rm, a->scale * a->msz, | |
d28d12f0 | 6067 | cpu_reg_sp(s, a->rn), a->msz, false, fn); |
673e9fa6 RH |
6068 | return true; |
6069 | } | |
6070 | ||
3a7be554 | 6071 | static bool trans_LD1_zpiz(DisasContext *s, arg_LD1_zpiz *a) |
673e9fa6 RH |
6072 | { |
6073 | gen_helper_gvec_mem_scatter *fn = NULL; | |
d28d12f0 RH |
6074 | bool be = s->be_data == MO_BE; |
6075 | bool mte = s->mte_active[0]; | |
673e9fa6 RH |
6076 | |
6077 | if (a->esz < a->msz || (a->esz == a->msz && !a->u)) { | |
6078 | return false; | |
6079 | } | |
6080 | if (!sve_access_check(s)) { | |
6081 | return true; | |
6082 | } | |
6083 | ||
6084 | switch (a->esz) { | |
6085 | case MO_32: | |
d28d12f0 | 6086 | fn = gather_load_fn32[mte][be][a->ff][0][a->u][a->msz]; |
673e9fa6 RH |
6087 | break; |
6088 | case MO_64: | |
d28d12f0 | 6089 | fn = gather_load_fn64[mte][be][a->ff][2][a->u][a->msz]; |
673e9fa6 RH |
6090 | break; |
6091 | } | |
6092 | assert(fn != NULL); | |
6093 | ||
6094 | /* Treat LD1_zpiz (zn[x] + imm) the same way as LD1_zprz (rn + zm[x]) | |
6095 | * by loading the immediate into the scalar parameter. | |
6096 | */ | |
2ccdf94f RH |
6097 | do_mem_zpz(s, a->rd, a->pg, a->rn, 0, |
6098 | tcg_constant_i64(a->imm << a->msz), a->msz, false, fn); | |
673e9fa6 RH |
6099 | return true; |
6100 | } | |
6101 | ||
cf327449 SL |
6102 | static bool trans_LDNT1_zprz(DisasContext *s, arg_LD1_zprz *a) |
6103 | { | |
b17ab470 RH |
6104 | gen_helper_gvec_mem_scatter *fn = NULL; |
6105 | bool be = s->be_data == MO_BE; | |
6106 | bool mte = s->mte_active[0]; | |
6107 | ||
6108 | if (a->esz < a->msz + !a->u) { | |
6109 | return false; | |
6110 | } | |
cf327449 SL |
6111 | if (!dc_isar_feature(aa64_sve2, s)) { |
6112 | return false; | |
6113 | } | |
b17ab470 RH |
6114 | if (!sve_access_check(s)) { |
6115 | return true; | |
6116 | } | |
6117 | ||
6118 | switch (a->esz) { | |
6119 | case MO_32: | |
6120 | fn = gather_load_fn32[mte][be][0][0][a->u][a->msz]; | |
6121 | break; | |
6122 | case MO_64: | |
6123 | fn = gather_load_fn64[mte][be][0][2][a->u][a->msz]; | |
6124 | break; | |
6125 | } | |
6126 | assert(fn != NULL); | |
6127 | ||
6128 | do_mem_zpz(s, a->rd, a->pg, a->rn, 0, | |
6129 | cpu_reg(s, a->rm), a->msz, false, fn); | |
6130 | return true; | |
cf327449 SL |
6131 | } |
6132 | ||
d28d12f0 RH |
6133 | /* Indexed by [mte][be][xs][msz]. */ |
6134 | static gen_helper_gvec_mem_scatter * const scatter_store_fn32[2][2][2][3] = { | |
6135 | { /* MTE Inactive */ | |
6136 | { /* Little-endian */ | |
6137 | { gen_helper_sve_stbs_zsu, | |
6138 | gen_helper_sve_sths_le_zsu, | |
6139 | gen_helper_sve_stss_le_zsu, }, | |
6140 | { gen_helper_sve_stbs_zss, | |
6141 | gen_helper_sve_sths_le_zss, | |
6142 | gen_helper_sve_stss_le_zss, } }, | |
6143 | { /* Big-endian */ | |
6144 | { gen_helper_sve_stbs_zsu, | |
6145 | gen_helper_sve_sths_be_zsu, | |
6146 | gen_helper_sve_stss_be_zsu, }, | |
6147 | { gen_helper_sve_stbs_zss, | |
6148 | gen_helper_sve_sths_be_zss, | |
6149 | gen_helper_sve_stss_be_zss, } } }, | |
6150 | { /* MTE Active */ | |
6151 | { /* Little-endian */ | |
6152 | { gen_helper_sve_stbs_zsu_mte, | |
6153 | gen_helper_sve_sths_le_zsu_mte, | |
6154 | gen_helper_sve_stss_le_zsu_mte, }, | |
6155 | { gen_helper_sve_stbs_zss_mte, | |
6156 | gen_helper_sve_sths_le_zss_mte, | |
6157 | gen_helper_sve_stss_le_zss_mte, } }, | |
6158 | { /* Big-endian */ | |
6159 | { gen_helper_sve_stbs_zsu_mte, | |
6160 | gen_helper_sve_sths_be_zsu_mte, | |
6161 | gen_helper_sve_stss_be_zsu_mte, }, | |
6162 | { gen_helper_sve_stbs_zss_mte, | |
6163 | gen_helper_sve_sths_be_zss_mte, | |
6164 | gen_helper_sve_stss_be_zss_mte, } } }, | |
408ecde9 RH |
6165 | }; |
6166 | ||
6167 | /* Note that we overload xs=2 to indicate 64-bit offset. */ | |
d28d12f0 RH |
6168 | static gen_helper_gvec_mem_scatter * const scatter_store_fn64[2][2][3][4] = { |
6169 | { /* MTE Inactive */ | |
6170 | { /* Little-endian */ | |
6171 | { gen_helper_sve_stbd_zsu, | |
6172 | gen_helper_sve_sthd_le_zsu, | |
6173 | gen_helper_sve_stsd_le_zsu, | |
6174 | gen_helper_sve_stdd_le_zsu, }, | |
6175 | { gen_helper_sve_stbd_zss, | |
6176 | gen_helper_sve_sthd_le_zss, | |
6177 | gen_helper_sve_stsd_le_zss, | |
6178 | gen_helper_sve_stdd_le_zss, }, | |
6179 | { gen_helper_sve_stbd_zd, | |
6180 | gen_helper_sve_sthd_le_zd, | |
6181 | gen_helper_sve_stsd_le_zd, | |
6182 | gen_helper_sve_stdd_le_zd, } }, | |
6183 | { /* Big-endian */ | |
6184 | { gen_helper_sve_stbd_zsu, | |
6185 | gen_helper_sve_sthd_be_zsu, | |
6186 | gen_helper_sve_stsd_be_zsu, | |
6187 | gen_helper_sve_stdd_be_zsu, }, | |
6188 | { gen_helper_sve_stbd_zss, | |
6189 | gen_helper_sve_sthd_be_zss, | |
6190 | gen_helper_sve_stsd_be_zss, | |
6191 | gen_helper_sve_stdd_be_zss, }, | |
6192 | { gen_helper_sve_stbd_zd, | |
6193 | gen_helper_sve_sthd_be_zd, | |
6194 | gen_helper_sve_stsd_be_zd, | |
6195 | gen_helper_sve_stdd_be_zd, } } }, | |
6196 | { /* MTE Inactive */ | |
6197 | { /* Little-endian */ | |
6198 | { gen_helper_sve_stbd_zsu_mte, | |
6199 | gen_helper_sve_sthd_le_zsu_mte, | |
6200 | gen_helper_sve_stsd_le_zsu_mte, | |
6201 | gen_helper_sve_stdd_le_zsu_mte, }, | |
6202 | { gen_helper_sve_stbd_zss_mte, | |
6203 | gen_helper_sve_sthd_le_zss_mte, | |
6204 | gen_helper_sve_stsd_le_zss_mte, | |
6205 | gen_helper_sve_stdd_le_zss_mte, }, | |
6206 | { gen_helper_sve_stbd_zd_mte, | |
6207 | gen_helper_sve_sthd_le_zd_mte, | |
6208 | gen_helper_sve_stsd_le_zd_mte, | |
6209 | gen_helper_sve_stdd_le_zd_mte, } }, | |
6210 | { /* Big-endian */ | |
6211 | { gen_helper_sve_stbd_zsu_mte, | |
6212 | gen_helper_sve_sthd_be_zsu_mte, | |
6213 | gen_helper_sve_stsd_be_zsu_mte, | |
6214 | gen_helper_sve_stdd_be_zsu_mte, }, | |
6215 | { gen_helper_sve_stbd_zss_mte, | |
6216 | gen_helper_sve_sthd_be_zss_mte, | |
6217 | gen_helper_sve_stsd_be_zss_mte, | |
6218 | gen_helper_sve_stdd_be_zss_mte, }, | |
6219 | { gen_helper_sve_stbd_zd_mte, | |
6220 | gen_helper_sve_sthd_be_zd_mte, | |
6221 | gen_helper_sve_stsd_be_zd_mte, | |
6222 | gen_helper_sve_stdd_be_zd_mte, } } }, | |
408ecde9 RH |
6223 | }; |
6224 | ||
3a7be554 | 6225 | static bool trans_ST1_zprz(DisasContext *s, arg_ST1_zprz *a) |
f6dbf62a | 6226 | { |
f6dbf62a | 6227 | gen_helper_gvec_mem_scatter *fn; |
d28d12f0 RH |
6228 | bool be = s->be_data == MO_BE; |
6229 | bool mte = s->mte_active[0]; | |
f6dbf62a RH |
6230 | |
6231 | if (a->esz < a->msz || (a->msz == 0 && a->scale)) { | |
6232 | return false; | |
6233 | } | |
6234 | if (!sve_access_check(s)) { | |
6235 | return true; | |
6236 | } | |
6237 | switch (a->esz) { | |
6238 | case MO_32: | |
d28d12f0 | 6239 | fn = scatter_store_fn32[mte][be][a->xs][a->msz]; |
f6dbf62a RH |
6240 | break; |
6241 | case MO_64: | |
d28d12f0 | 6242 | fn = scatter_store_fn64[mte][be][a->xs][a->msz]; |
f6dbf62a RH |
6243 | break; |
6244 | default: | |
6245 | g_assert_not_reached(); | |
6246 | } | |
6247 | do_mem_zpz(s, a->rd, a->pg, a->rm, a->scale * a->msz, | |
d28d12f0 | 6248 | cpu_reg_sp(s, a->rn), a->msz, true, fn); |
f6dbf62a RH |
6249 | return true; |
6250 | } | |
dec6cf6b | 6251 | |
3a7be554 | 6252 | static bool trans_ST1_zpiz(DisasContext *s, arg_ST1_zpiz *a) |
408ecde9 RH |
6253 | { |
6254 | gen_helper_gvec_mem_scatter *fn = NULL; | |
d28d12f0 RH |
6255 | bool be = s->be_data == MO_BE; |
6256 | bool mte = s->mte_active[0]; | |
408ecde9 RH |
6257 | |
6258 | if (a->esz < a->msz) { | |
6259 | return false; | |
6260 | } | |
6261 | if (!sve_access_check(s)) { | |
6262 | return true; | |
6263 | } | |
6264 | ||
6265 | switch (a->esz) { | |
6266 | case MO_32: | |
d28d12f0 | 6267 | fn = scatter_store_fn32[mte][be][0][a->msz]; |
408ecde9 RH |
6268 | break; |
6269 | case MO_64: | |
d28d12f0 | 6270 | fn = scatter_store_fn64[mte][be][2][a->msz]; |
408ecde9 RH |
6271 | break; |
6272 | } | |
6273 | assert(fn != NULL); | |
6274 | ||
6275 | /* Treat ST1_zpiz (zn[x] + imm) the same way as ST1_zprz (rn + zm[x]) | |
6276 | * by loading the immediate into the scalar parameter. | |
6277 | */ | |
2ccdf94f RH |
6278 | do_mem_zpz(s, a->rd, a->pg, a->rn, 0, |
6279 | tcg_constant_i64(a->imm << a->msz), a->msz, true, fn); | |
408ecde9 RH |
6280 | return true; |
6281 | } | |
6282 | ||
6ebca45f SL |
6283 | static bool trans_STNT1_zprz(DisasContext *s, arg_ST1_zprz *a) |
6284 | { | |
b17ab470 RH |
6285 | gen_helper_gvec_mem_scatter *fn; |
6286 | bool be = s->be_data == MO_BE; | |
6287 | bool mte = s->mte_active[0]; | |
6288 | ||
6289 | if (a->esz < a->msz) { | |
6290 | return false; | |
6291 | } | |
6ebca45f SL |
6292 | if (!dc_isar_feature(aa64_sve2, s)) { |
6293 | return false; | |
6294 | } | |
b17ab470 RH |
6295 | if (!sve_access_check(s)) { |
6296 | return true; | |
6297 | } | |
6298 | ||
6299 | switch (a->esz) { | |
6300 | case MO_32: | |
6301 | fn = scatter_store_fn32[mte][be][0][a->msz]; | |
6302 | break; | |
6303 | case MO_64: | |
6304 | fn = scatter_store_fn64[mte][be][2][a->msz]; | |
6305 | break; | |
6306 | default: | |
6307 | g_assert_not_reached(); | |
6308 | } | |
6309 | ||
6310 | do_mem_zpz(s, a->rd, a->pg, a->rn, 0, | |
6311 | cpu_reg(s, a->rm), a->msz, true, fn); | |
6312 | return true; | |
6ebca45f SL |
6313 | } |
6314 | ||
dec6cf6b RH |
6315 | /* |
6316 | * Prefetches | |
6317 | */ | |
6318 | ||
3a7be554 | 6319 | static bool trans_PRF(DisasContext *s, arg_PRF *a) |
dec6cf6b RH |
6320 | { |
6321 | /* Prefetch is a nop within QEMU. */ | |
2f95a3b0 | 6322 | (void)sve_access_check(s); |
dec6cf6b RH |
6323 | return true; |
6324 | } | |
6325 | ||
3a7be554 | 6326 | static bool trans_PRF_rr(DisasContext *s, arg_PRF_rr *a) |
dec6cf6b RH |
6327 | { |
6328 | if (a->rm == 31) { | |
6329 | return false; | |
6330 | } | |
6331 | /* Prefetch is a nop within QEMU. */ | |
2f95a3b0 | 6332 | (void)sve_access_check(s); |
dec6cf6b RH |
6333 | return true; |
6334 | } | |
a2103582 RH |
6335 | |
6336 | /* | |
6337 | * Move Prefix | |
6338 | * | |
6339 | * TODO: The implementation so far could handle predicated merging movprfx. | |
6340 | * The helper functions as written take an extra source register to | |
6341 | * use in the operation, but the result is only written when predication | |
6342 | * succeeds. For unpredicated movprfx, we need to rearrange the helpers | |
6343 | * to allow the final write back to the destination to be unconditional. | |
6344 | * For predicated zeroing movprfx, we need to rearrange the helpers to | |
6345 | * allow the final write back to zero inactives. | |
6346 | * | |
6347 | * In the meantime, just emit the moves. | |
6348 | */ | |
6349 | ||
3a7be554 | 6350 | static bool trans_MOVPRFX(DisasContext *s, arg_MOVPRFX *a) |
a2103582 RH |
6351 | { |
6352 | return do_mov_z(s, a->rd, a->rn); | |
6353 | } | |
6354 | ||
3a7be554 | 6355 | static bool trans_MOVPRFX_m(DisasContext *s, arg_rpr_esz *a) |
a2103582 RH |
6356 | { |
6357 | if (sve_access_check(s)) { | |
6358 | do_sel_z(s, a->rd, a->rn, a->rd, a->pg, a->esz); | |
6359 | } | |
6360 | return true; | |
6361 | } | |
6362 | ||
3a7be554 | 6363 | static bool trans_MOVPRFX_z(DisasContext *s, arg_rpr_esz *a) |
a2103582 | 6364 | { |
60245996 | 6365 | return do_movz_zpz(s, a->rd, a->rn, a->pg, a->esz, false); |
a2103582 | 6366 | } |
5dad1ba5 RH |
6367 | |
6368 | /* | |
6369 | * SVE2 Integer Multiply - Unpredicated | |
6370 | */ | |
6371 | ||
b262215b | 6372 | TRANS_FEAT(MUL_zzz, aa64_sve2, gen_gvec_fn_arg_zzz, tcg_gen_gvec_mul, a) |
5dad1ba5 | 6373 | |
bd394cf5 RH |
6374 | static gen_helper_gvec_3 * const smulh_zzz_fns[4] = { |
6375 | gen_helper_gvec_smulh_b, gen_helper_gvec_smulh_h, | |
6376 | gen_helper_gvec_smulh_s, gen_helper_gvec_smulh_d, | |
6377 | }; | |
6378 | TRANS_FEAT(SMULH_zzz, aa64_sve2, gen_gvec_ool_arg_zzz, | |
6379 | smulh_zzz_fns[a->esz], a, 0) | |
5dad1ba5 | 6380 | |
bd394cf5 RH |
6381 | static gen_helper_gvec_3 * const umulh_zzz_fns[4] = { |
6382 | gen_helper_gvec_umulh_b, gen_helper_gvec_umulh_h, | |
6383 | gen_helper_gvec_umulh_s, gen_helper_gvec_umulh_d, | |
6384 | }; | |
6385 | TRANS_FEAT(UMULH_zzz, aa64_sve2, gen_gvec_ool_arg_zzz, | |
6386 | umulh_zzz_fns[a->esz], a, 0) | |
5dad1ba5 | 6387 | |
bd394cf5 RH |
6388 | TRANS_FEAT(PMUL_zzz, aa64_sve2, gen_gvec_ool_arg_zzz, |
6389 | gen_helper_gvec_pmul_b, a, 0) | |
5dad1ba5 | 6390 | |
bd394cf5 RH |
6391 | static gen_helper_gvec_3 * const sqdmulh_zzz_fns[4] = { |
6392 | gen_helper_sve2_sqdmulh_b, gen_helper_sve2_sqdmulh_h, | |
6393 | gen_helper_sve2_sqdmulh_s, gen_helper_sve2_sqdmulh_d, | |
6394 | }; | |
6395 | TRANS_FEAT(SQDMULH_zzz, aa64_sve2, gen_gvec_ool_arg_zzz, | |
6396 | sqdmulh_zzz_fns[a->esz], a, 0) | |
169d7c58 | 6397 | |
bd394cf5 RH |
6398 | static gen_helper_gvec_3 * const sqrdmulh_zzz_fns[4] = { |
6399 | gen_helper_sve2_sqrdmulh_b, gen_helper_sve2_sqrdmulh_h, | |
6400 | gen_helper_sve2_sqrdmulh_s, gen_helper_sve2_sqrdmulh_d, | |
6401 | }; | |
6402 | TRANS_FEAT(SQRDMULH_zzz, aa64_sve2, gen_gvec_ool_arg_zzz, | |
6403 | sqrdmulh_zzz_fns[a->esz], a, 0) | |
169d7c58 | 6404 | |
d4b1e59d RH |
6405 | /* |
6406 | * SVE2 Integer - Predicated | |
6407 | */ | |
6408 | ||
5880bdc0 RH |
6409 | static gen_helper_gvec_4 * const sadlp_fns[4] = { |
6410 | NULL, gen_helper_sve2_sadalp_zpzz_h, | |
6411 | gen_helper_sve2_sadalp_zpzz_s, gen_helper_sve2_sadalp_zpzz_d, | |
6412 | }; | |
6413 | TRANS_FEAT(SADALP_zpzz, aa64_sve2, gen_gvec_ool_arg_zpzz, | |
6414 | sadlp_fns[a->esz], a, 0) | |
d4b1e59d | 6415 | |
5880bdc0 RH |
6416 | static gen_helper_gvec_4 * const uadlp_fns[4] = { |
6417 | NULL, gen_helper_sve2_uadalp_zpzz_h, | |
6418 | gen_helper_sve2_uadalp_zpzz_s, gen_helper_sve2_uadalp_zpzz_d, | |
6419 | }; | |
6420 | TRANS_FEAT(UADALP_zpzz, aa64_sve2, gen_gvec_ool_arg_zpzz, | |
6421 | uadlp_fns[a->esz], a, 0) | |
db366da8 RH |
6422 | |
6423 | /* | |
6424 | * SVE2 integer unary operations (predicated) | |
6425 | */ | |
6426 | ||
b2c00961 RH |
6427 | TRANS_FEAT(URECPE, aa64_sve2, gen_gvec_ool_arg_zpz, |
6428 | a->esz == 2 ? gen_helper_sve2_urecpe_s : NULL, a, 0) | |
db366da8 | 6429 | |
b2c00961 RH |
6430 | TRANS_FEAT(URSQRTE, aa64_sve2, gen_gvec_ool_arg_zpz, |
6431 | a->esz == 2 ? gen_helper_sve2_ursqrte_s : NULL, a, 0) | |
db366da8 | 6432 | |
b2c00961 RH |
6433 | static gen_helper_gvec_3 * const sqabs_fns[4] = { |
6434 | gen_helper_sve2_sqabs_b, gen_helper_sve2_sqabs_h, | |
6435 | gen_helper_sve2_sqabs_s, gen_helper_sve2_sqabs_d, | |
6436 | }; | |
6437 | TRANS_FEAT(SQABS, aa64_sve2, gen_gvec_ool_arg_zpz, sqabs_fns[a->esz], a, 0) | |
db366da8 | 6438 | |
b2c00961 RH |
6439 | static gen_helper_gvec_3 * const sqneg_fns[4] = { |
6440 | gen_helper_sve2_sqneg_b, gen_helper_sve2_sqneg_h, | |
6441 | gen_helper_sve2_sqneg_s, gen_helper_sve2_sqneg_d, | |
6442 | }; | |
6443 | TRANS_FEAT(SQNEG, aa64_sve2, gen_gvec_ool_arg_zpz, sqneg_fns[a->esz], a, 0) | |
45d9503d | 6444 | |
5880bdc0 RH |
6445 | DO_ZPZZ(SQSHL, aa64_sve2, sve2_sqshl) |
6446 | DO_ZPZZ(SQRSHL, aa64_sve2, sve2_sqrshl) | |
6447 | DO_ZPZZ(SRSHL, aa64_sve2, sve2_srshl) | |
45d9503d | 6448 | |
5880bdc0 RH |
6449 | DO_ZPZZ(UQSHL, aa64_sve2, sve2_uqshl) |
6450 | DO_ZPZZ(UQRSHL, aa64_sve2, sve2_uqrshl) | |
6451 | DO_ZPZZ(URSHL, aa64_sve2, sve2_urshl) | |
a47dc220 | 6452 | |
5880bdc0 RH |
6453 | DO_ZPZZ(SHADD, aa64_sve2, sve2_shadd) |
6454 | DO_ZPZZ(SRHADD, aa64_sve2, sve2_srhadd) | |
6455 | DO_ZPZZ(SHSUB, aa64_sve2, sve2_shsub) | |
a47dc220 | 6456 | |
5880bdc0 RH |
6457 | DO_ZPZZ(UHADD, aa64_sve2, sve2_uhadd) |
6458 | DO_ZPZZ(URHADD, aa64_sve2, sve2_urhadd) | |
6459 | DO_ZPZZ(UHSUB, aa64_sve2, sve2_uhsub) | |
8597dc8b | 6460 | |
5880bdc0 RH |
6461 | DO_ZPZZ(ADDP, aa64_sve2, sve2_addp) |
6462 | DO_ZPZZ(SMAXP, aa64_sve2, sve2_smaxp) | |
6463 | DO_ZPZZ(UMAXP, aa64_sve2, sve2_umaxp) | |
6464 | DO_ZPZZ(SMINP, aa64_sve2, sve2_sminp) | |
6465 | DO_ZPZZ(UMINP, aa64_sve2, sve2_uminp) | |
4f07fbeb | 6466 | |
5880bdc0 RH |
6467 | DO_ZPZZ(SQADD_zpzz, aa64_sve2, sve2_sqadd) |
6468 | DO_ZPZZ(UQADD_zpzz, aa64_sve2, sve2_uqadd) | |
6469 | DO_ZPZZ(SQSUB_zpzz, aa64_sve2, sve2_sqsub) | |
6470 | DO_ZPZZ(UQSUB_zpzz, aa64_sve2, sve2_uqsub) | |
6471 | DO_ZPZZ(SUQADD, aa64_sve2, sve2_suqadd) | |
6472 | DO_ZPZZ(USQADD, aa64_sve2, sve2_usqadd) | |
0ce1dda8 RH |
6473 | |
6474 | /* | |
6475 | * SVE2 Widening Integer Arithmetic | |
6476 | */ | |
6477 | ||
615f19fe RH |
6478 | static gen_helper_gvec_3 * const saddl_fns[4] = { |
6479 | NULL, gen_helper_sve2_saddl_h, | |
6480 | gen_helper_sve2_saddl_s, gen_helper_sve2_saddl_d, | |
6481 | }; | |
6482 | TRANS_FEAT(SADDLB, aa64_sve2, gen_gvec_ool_arg_zzz, | |
6483 | saddl_fns[a->esz], a, 0) | |
6484 | TRANS_FEAT(SADDLT, aa64_sve2, gen_gvec_ool_arg_zzz, | |
6485 | saddl_fns[a->esz], a, 3) | |
6486 | TRANS_FEAT(SADDLBT, aa64_sve2, gen_gvec_ool_arg_zzz, | |
6487 | saddl_fns[a->esz], a, 2) | |
6488 | ||
6489 | static gen_helper_gvec_3 * const ssubl_fns[4] = { | |
6490 | NULL, gen_helper_sve2_ssubl_h, | |
6491 | gen_helper_sve2_ssubl_s, gen_helper_sve2_ssubl_d, | |
6492 | }; | |
6493 | TRANS_FEAT(SSUBLB, aa64_sve2, gen_gvec_ool_arg_zzz, | |
6494 | ssubl_fns[a->esz], a, 0) | |
6495 | TRANS_FEAT(SSUBLT, aa64_sve2, gen_gvec_ool_arg_zzz, | |
6496 | ssubl_fns[a->esz], a, 3) | |
6497 | TRANS_FEAT(SSUBLBT, aa64_sve2, gen_gvec_ool_arg_zzz, | |
6498 | ssubl_fns[a->esz], a, 2) | |
6499 | TRANS_FEAT(SSUBLTB, aa64_sve2, gen_gvec_ool_arg_zzz, | |
6500 | ssubl_fns[a->esz], a, 1) | |
6501 | ||
6502 | static gen_helper_gvec_3 * const sabdl_fns[4] = { | |
6503 | NULL, gen_helper_sve2_sabdl_h, | |
6504 | gen_helper_sve2_sabdl_s, gen_helper_sve2_sabdl_d, | |
6505 | }; | |
6506 | TRANS_FEAT(SABDLB, aa64_sve2, gen_gvec_ool_arg_zzz, | |
6507 | sabdl_fns[a->esz], a, 0) | |
6508 | TRANS_FEAT(SABDLT, aa64_sve2, gen_gvec_ool_arg_zzz, | |
6509 | sabdl_fns[a->esz], a, 3) | |
6510 | ||
6511 | static gen_helper_gvec_3 * const uaddl_fns[4] = { | |
6512 | NULL, gen_helper_sve2_uaddl_h, | |
6513 | gen_helper_sve2_uaddl_s, gen_helper_sve2_uaddl_d, | |
6514 | }; | |
6515 | TRANS_FEAT(UADDLB, aa64_sve2, gen_gvec_ool_arg_zzz, | |
6516 | uaddl_fns[a->esz], a, 0) | |
6517 | TRANS_FEAT(UADDLT, aa64_sve2, gen_gvec_ool_arg_zzz, | |
6518 | uaddl_fns[a->esz], a, 3) | |
6519 | ||
6520 | static gen_helper_gvec_3 * const usubl_fns[4] = { | |
6521 | NULL, gen_helper_sve2_usubl_h, | |
6522 | gen_helper_sve2_usubl_s, gen_helper_sve2_usubl_d, | |
6523 | }; | |
6524 | TRANS_FEAT(USUBLB, aa64_sve2, gen_gvec_ool_arg_zzz, | |
6525 | usubl_fns[a->esz], a, 0) | |
6526 | TRANS_FEAT(USUBLT, aa64_sve2, gen_gvec_ool_arg_zzz, | |
6527 | usubl_fns[a->esz], a, 3) | |
6528 | ||
6529 | static gen_helper_gvec_3 * const uabdl_fns[4] = { | |
6530 | NULL, gen_helper_sve2_uabdl_h, | |
6531 | gen_helper_sve2_uabdl_s, gen_helper_sve2_uabdl_d, | |
6532 | }; | |
6533 | TRANS_FEAT(UABDLB, aa64_sve2, gen_gvec_ool_arg_zzz, | |
6534 | uabdl_fns[a->esz], a, 0) | |
6535 | TRANS_FEAT(UABDLT, aa64_sve2, gen_gvec_ool_arg_zzz, | |
6536 | uabdl_fns[a->esz], a, 3) | |
6537 | ||
6538 | static gen_helper_gvec_3 * const sqdmull_fns[4] = { | |
6539 | NULL, gen_helper_sve2_sqdmull_zzz_h, | |
6540 | gen_helper_sve2_sqdmull_zzz_s, gen_helper_sve2_sqdmull_zzz_d, | |
6541 | }; | |
6542 | TRANS_FEAT(SQDMULLB_zzz, aa64_sve2, gen_gvec_ool_arg_zzz, | |
6543 | sqdmull_fns[a->esz], a, 0) | |
6544 | TRANS_FEAT(SQDMULLT_zzz, aa64_sve2, gen_gvec_ool_arg_zzz, | |
6545 | sqdmull_fns[a->esz], a, 3) | |
6546 | ||
6547 | static gen_helper_gvec_3 * const smull_fns[4] = { | |
6548 | NULL, gen_helper_sve2_smull_zzz_h, | |
6549 | gen_helper_sve2_smull_zzz_s, gen_helper_sve2_smull_zzz_d, | |
6550 | }; | |
6551 | TRANS_FEAT(SMULLB_zzz, aa64_sve2, gen_gvec_ool_arg_zzz, | |
6552 | smull_fns[a->esz], a, 0) | |
6553 | TRANS_FEAT(SMULLT_zzz, aa64_sve2, gen_gvec_ool_arg_zzz, | |
6554 | smull_fns[a->esz], a, 3) | |
6555 | ||
6556 | static gen_helper_gvec_3 * const umull_fns[4] = { | |
6557 | NULL, gen_helper_sve2_umull_zzz_h, | |
6558 | gen_helper_sve2_umull_zzz_s, gen_helper_sve2_umull_zzz_d, | |
6559 | }; | |
6560 | TRANS_FEAT(UMULLB_zzz, aa64_sve2, gen_gvec_ool_arg_zzz, | |
6561 | umull_fns[a->esz], a, 0) | |
6562 | TRANS_FEAT(UMULLT_zzz, aa64_sve2, gen_gvec_ool_arg_zzz, | |
6563 | umull_fns[a->esz], a, 3) | |
6564 | ||
6565 | static gen_helper_gvec_3 * const eoril_fns[4] = { | |
6566 | gen_helper_sve2_eoril_b, gen_helper_sve2_eoril_h, | |
6567 | gen_helper_sve2_eoril_s, gen_helper_sve2_eoril_d, | |
6568 | }; | |
6569 | TRANS_FEAT(EORBT, aa64_sve2, gen_gvec_ool_arg_zzz, eoril_fns[a->esz], a, 2) | |
6570 | TRANS_FEAT(EORTB, aa64_sve2, gen_gvec_ool_arg_zzz, eoril_fns[a->esz], a, 1) | |
2df3ca55 | 6571 | |
e3a56131 RH |
6572 | static bool do_trans_pmull(DisasContext *s, arg_rrr_esz *a, bool sel) |
6573 | { | |
6574 | static gen_helper_gvec_3 * const fns[4] = { | |
6575 | gen_helper_gvec_pmull_q, gen_helper_sve2_pmull_h, | |
6576 | NULL, gen_helper_sve2_pmull_d, | |
6577 | }; | |
6578 | if (a->esz == 0 && !dc_isar_feature(aa64_sve2_pmull128, s)) { | |
6579 | return false; | |
6580 | } | |
615f19fe | 6581 | return gen_gvec_ool_arg_zzz(s, fns[a->esz], a, sel); |
e3a56131 RH |
6582 | } |
6583 | ||
615f19fe RH |
6584 | TRANS_FEAT(PMULLB, aa64_sve2, do_trans_pmull, a, false) |
6585 | TRANS_FEAT(PMULLT, aa64_sve2, do_trans_pmull, a, true) | |
e3a56131 | 6586 | |
615f19fe RH |
6587 | static gen_helper_gvec_3 * const saddw_fns[4] = { |
6588 | NULL, gen_helper_sve2_saddw_h, | |
6589 | gen_helper_sve2_saddw_s, gen_helper_sve2_saddw_d, | |
6590 | }; | |
6591 | TRANS_FEAT(SADDWB, aa64_sve2, gen_gvec_ool_arg_zzz, saddw_fns[a->esz], a, 0) | |
6592 | TRANS_FEAT(SADDWT, aa64_sve2, gen_gvec_ool_arg_zzz, saddw_fns[a->esz], a, 1) | |
e3a56131 | 6593 | |
615f19fe RH |
6594 | static gen_helper_gvec_3 * const ssubw_fns[4] = { |
6595 | NULL, gen_helper_sve2_ssubw_h, | |
6596 | gen_helper_sve2_ssubw_s, gen_helper_sve2_ssubw_d, | |
6597 | }; | |
6598 | TRANS_FEAT(SSUBWB, aa64_sve2, gen_gvec_ool_arg_zzz, ssubw_fns[a->esz], a, 0) | |
6599 | TRANS_FEAT(SSUBWT, aa64_sve2, gen_gvec_ool_arg_zzz, ssubw_fns[a->esz], a, 1) | |
81fccf09 | 6600 | |
615f19fe RH |
6601 | static gen_helper_gvec_3 * const uaddw_fns[4] = { |
6602 | NULL, gen_helper_sve2_uaddw_h, | |
6603 | gen_helper_sve2_uaddw_s, gen_helper_sve2_uaddw_d, | |
6604 | }; | |
6605 | TRANS_FEAT(UADDWB, aa64_sve2, gen_gvec_ool_arg_zzz, uaddw_fns[a->esz], a, 0) | |
6606 | TRANS_FEAT(UADDWT, aa64_sve2, gen_gvec_ool_arg_zzz, uaddw_fns[a->esz], a, 1) | |
81fccf09 | 6607 | |
615f19fe RH |
6608 | static gen_helper_gvec_3 * const usubw_fns[4] = { |
6609 | NULL, gen_helper_sve2_usubw_h, | |
6610 | gen_helper_sve2_usubw_s, gen_helper_sve2_usubw_d, | |
6611 | }; | |
6612 | TRANS_FEAT(USUBWB, aa64_sve2, gen_gvec_ool_arg_zzz, usubw_fns[a->esz], a, 0) | |
6613 | TRANS_FEAT(USUBWT, aa64_sve2, gen_gvec_ool_arg_zzz, usubw_fns[a->esz], a, 1) | |
4269fef1 RH |
6614 | |
6615 | static void gen_sshll_vec(unsigned vece, TCGv_vec d, TCGv_vec n, int64_t imm) | |
6616 | { | |
6617 | int top = imm & 1; | |
6618 | int shl = imm >> 1; | |
6619 | int halfbits = 4 << vece; | |
6620 | ||
6621 | if (top) { | |
6622 | if (shl == halfbits) { | |
6623 | TCGv_vec t = tcg_temp_new_vec_matching(d); | |
6624 | tcg_gen_dupi_vec(vece, t, MAKE_64BIT_MASK(halfbits, halfbits)); | |
6625 | tcg_gen_and_vec(vece, d, n, t); | |
6626 | tcg_temp_free_vec(t); | |
6627 | } else { | |
6628 | tcg_gen_sari_vec(vece, d, n, halfbits); | |
6629 | tcg_gen_shli_vec(vece, d, d, shl); | |
6630 | } | |
6631 | } else { | |
6632 | tcg_gen_shli_vec(vece, d, n, halfbits); | |
6633 | tcg_gen_sari_vec(vece, d, d, halfbits - shl); | |
6634 | } | |
6635 | } | |
6636 | ||
6637 | static void gen_ushll_i64(unsigned vece, TCGv_i64 d, TCGv_i64 n, int imm) | |
6638 | { | |
6639 | int halfbits = 4 << vece; | |
6640 | int top = imm & 1; | |
6641 | int shl = (imm >> 1); | |
6642 | int shift; | |
6643 | uint64_t mask; | |
6644 | ||
6645 | mask = MAKE_64BIT_MASK(0, halfbits); | |
6646 | mask <<= shl; | |
6647 | mask = dup_const(vece, mask); | |
6648 | ||
6649 | shift = shl - top * halfbits; | |
6650 | if (shift < 0) { | |
6651 | tcg_gen_shri_i64(d, n, -shift); | |
6652 | } else { | |
6653 | tcg_gen_shli_i64(d, n, shift); | |
6654 | } | |
6655 | tcg_gen_andi_i64(d, d, mask); | |
6656 | } | |
6657 | ||
6658 | static void gen_ushll16_i64(TCGv_i64 d, TCGv_i64 n, int64_t imm) | |
6659 | { | |
6660 | gen_ushll_i64(MO_16, d, n, imm); | |
6661 | } | |
6662 | ||
6663 | static void gen_ushll32_i64(TCGv_i64 d, TCGv_i64 n, int64_t imm) | |
6664 | { | |
6665 | gen_ushll_i64(MO_32, d, n, imm); | |
6666 | } | |
6667 | ||
6668 | static void gen_ushll64_i64(TCGv_i64 d, TCGv_i64 n, int64_t imm) | |
6669 | { | |
6670 | gen_ushll_i64(MO_64, d, n, imm); | |
6671 | } | |
6672 | ||
6673 | static void gen_ushll_vec(unsigned vece, TCGv_vec d, TCGv_vec n, int64_t imm) | |
6674 | { | |
6675 | int halfbits = 4 << vece; | |
6676 | int top = imm & 1; | |
6677 | int shl = imm >> 1; | |
6678 | ||
6679 | if (top) { | |
6680 | if (shl == halfbits) { | |
6681 | TCGv_vec t = tcg_temp_new_vec_matching(d); | |
6682 | tcg_gen_dupi_vec(vece, t, MAKE_64BIT_MASK(halfbits, halfbits)); | |
6683 | tcg_gen_and_vec(vece, d, n, t); | |
6684 | tcg_temp_free_vec(t); | |
6685 | } else { | |
6686 | tcg_gen_shri_vec(vece, d, n, halfbits); | |
6687 | tcg_gen_shli_vec(vece, d, d, shl); | |
6688 | } | |
6689 | } else { | |
6690 | if (shl == 0) { | |
6691 | TCGv_vec t = tcg_temp_new_vec_matching(d); | |
6692 | tcg_gen_dupi_vec(vece, t, MAKE_64BIT_MASK(0, halfbits)); | |
6693 | tcg_gen_and_vec(vece, d, n, t); | |
6694 | tcg_temp_free_vec(t); | |
6695 | } else { | |
6696 | tcg_gen_shli_vec(vece, d, n, halfbits); | |
6697 | tcg_gen_shri_vec(vece, d, d, halfbits - shl); | |
6698 | } | |
6699 | } | |
6700 | } | |
6701 | ||
6702 | static bool do_sve2_shll_tb(DisasContext *s, arg_rri_esz *a, | |
6703 | bool sel, bool uns) | |
6704 | { | |
6705 | static const TCGOpcode sshll_list[] = { | |
6706 | INDEX_op_shli_vec, INDEX_op_sari_vec, 0 | |
6707 | }; | |
6708 | static const TCGOpcode ushll_list[] = { | |
6709 | INDEX_op_shli_vec, INDEX_op_shri_vec, 0 | |
6710 | }; | |
6711 | static const GVecGen2i ops[2][3] = { | |
6712 | { { .fniv = gen_sshll_vec, | |
6713 | .opt_opc = sshll_list, | |
6714 | .fno = gen_helper_sve2_sshll_h, | |
6715 | .vece = MO_16 }, | |
6716 | { .fniv = gen_sshll_vec, | |
6717 | .opt_opc = sshll_list, | |
6718 | .fno = gen_helper_sve2_sshll_s, | |
6719 | .vece = MO_32 }, | |
6720 | { .fniv = gen_sshll_vec, | |
6721 | .opt_opc = sshll_list, | |
6722 | .fno = gen_helper_sve2_sshll_d, | |
6723 | .vece = MO_64 } }, | |
6724 | { { .fni8 = gen_ushll16_i64, | |
6725 | .fniv = gen_ushll_vec, | |
6726 | .opt_opc = ushll_list, | |
6727 | .fno = gen_helper_sve2_ushll_h, | |
6728 | .vece = MO_16 }, | |
6729 | { .fni8 = gen_ushll32_i64, | |
6730 | .fniv = gen_ushll_vec, | |
6731 | .opt_opc = ushll_list, | |
6732 | .fno = gen_helper_sve2_ushll_s, | |
6733 | .vece = MO_32 }, | |
6734 | { .fni8 = gen_ushll64_i64, | |
6735 | .fniv = gen_ushll_vec, | |
6736 | .opt_opc = ushll_list, | |
6737 | .fno = gen_helper_sve2_ushll_d, | |
6738 | .vece = MO_64 } }, | |
6739 | }; | |
6740 | ||
6741 | if (a->esz < 0 || a->esz > 2 || !dc_isar_feature(aa64_sve2, s)) { | |
6742 | return false; | |
6743 | } | |
6744 | if (sve_access_check(s)) { | |
6745 | unsigned vsz = vec_full_reg_size(s); | |
6746 | tcg_gen_gvec_2i(vec_full_reg_offset(s, a->rd), | |
6747 | vec_full_reg_offset(s, a->rn), | |
6748 | vsz, vsz, (a->imm << 1) | sel, | |
6749 | &ops[uns][a->esz]); | |
6750 | } | |
6751 | return true; | |
6752 | } | |
6753 | ||
6754 | static bool trans_SSHLLB(DisasContext *s, arg_rri_esz *a) | |
6755 | { | |
6756 | return do_sve2_shll_tb(s, a, false, false); | |
6757 | } | |
6758 | ||
6759 | static bool trans_SSHLLT(DisasContext *s, arg_rri_esz *a) | |
6760 | { | |
6761 | return do_sve2_shll_tb(s, a, true, false); | |
6762 | } | |
6763 | ||
6764 | static bool trans_USHLLB(DisasContext *s, arg_rri_esz *a) | |
6765 | { | |
6766 | return do_sve2_shll_tb(s, a, false, true); | |
6767 | } | |
6768 | ||
6769 | static bool trans_USHLLT(DisasContext *s, arg_rri_esz *a) | |
6770 | { | |
6771 | return do_sve2_shll_tb(s, a, true, true); | |
6772 | } | |
cb9c33b8 | 6773 | |
615f19fe RH |
6774 | static gen_helper_gvec_3 * const bext_fns[4] = { |
6775 | gen_helper_sve2_bext_b, gen_helper_sve2_bext_h, | |
6776 | gen_helper_sve2_bext_s, gen_helper_sve2_bext_d, | |
6777 | }; | |
6778 | TRANS_FEAT(BEXT, aa64_sve2_bitperm, gen_gvec_ool_arg_zzz, | |
6779 | bext_fns[a->esz], a, 0) | |
ed4a6387 | 6780 | |
615f19fe RH |
6781 | static gen_helper_gvec_3 * const bdep_fns[4] = { |
6782 | gen_helper_sve2_bdep_b, gen_helper_sve2_bdep_h, | |
6783 | gen_helper_sve2_bdep_s, gen_helper_sve2_bdep_d, | |
6784 | }; | |
6785 | TRANS_FEAT(BDEP, aa64_sve2_bitperm, gen_gvec_ool_arg_zzz, | |
6786 | bdep_fns[a->esz], a, 0) | |
ed4a6387 | 6787 | |
615f19fe RH |
6788 | static gen_helper_gvec_3 * const bgrp_fns[4] = { |
6789 | gen_helper_sve2_bgrp_b, gen_helper_sve2_bgrp_h, | |
6790 | gen_helper_sve2_bgrp_s, gen_helper_sve2_bgrp_d, | |
6791 | }; | |
6792 | TRANS_FEAT(BGRP, aa64_sve2_bitperm, gen_gvec_ool_arg_zzz, | |
6793 | bgrp_fns[a->esz], a, 0) | |
ed4a6387 | 6794 | |
615f19fe RH |
6795 | static gen_helper_gvec_3 * const cadd_fns[4] = { |
6796 | gen_helper_sve2_cadd_b, gen_helper_sve2_cadd_h, | |
6797 | gen_helper_sve2_cadd_s, gen_helper_sve2_cadd_d, | |
6798 | }; | |
6799 | TRANS_FEAT(CADD_rot90, aa64_sve2, gen_gvec_ool_arg_zzz, | |
6800 | cadd_fns[a->esz], a, 0) | |
6801 | TRANS_FEAT(CADD_rot270, aa64_sve2, gen_gvec_ool_arg_zzz, | |
6802 | cadd_fns[a->esz], a, 1) | |
6803 | ||
6804 | static gen_helper_gvec_3 * const sqcadd_fns[4] = { | |
6805 | gen_helper_sve2_sqcadd_b, gen_helper_sve2_sqcadd_h, | |
6806 | gen_helper_sve2_sqcadd_s, gen_helper_sve2_sqcadd_d, | |
6807 | }; | |
6808 | TRANS_FEAT(SQCADD_rot90, aa64_sve2, gen_gvec_ool_arg_zzz, | |
6809 | sqcadd_fns[a->esz], a, 0) | |
6810 | TRANS_FEAT(SQCADD_rot270, aa64_sve2, gen_gvec_ool_arg_zzz, | |
6811 | sqcadd_fns[a->esz], a, 1) | |
38650638 | 6812 | |
eeb4e84d RH |
6813 | static gen_helper_gvec_4 * const sabal_fns[4] = { |
6814 | NULL, gen_helper_sve2_sabal_h, | |
6815 | gen_helper_sve2_sabal_s, gen_helper_sve2_sabal_d, | |
6816 | }; | |
6817 | TRANS_FEAT(SABALB, aa64_sve2, gen_gvec_ool_arg_zzzz, sabal_fns[a->esz], a, 0) | |
6818 | TRANS_FEAT(SABALT, aa64_sve2, gen_gvec_ool_arg_zzzz, sabal_fns[a->esz], a, 1) | |
38650638 | 6819 | |
eeb4e84d RH |
6820 | static gen_helper_gvec_4 * const uabal_fns[4] = { |
6821 | NULL, gen_helper_sve2_uabal_h, | |
6822 | gen_helper_sve2_uabal_s, gen_helper_sve2_uabal_d, | |
6823 | }; | |
6824 | TRANS_FEAT(UABALB, aa64_sve2, gen_gvec_ool_arg_zzzz, uabal_fns[a->esz], a, 0) | |
6825 | TRANS_FEAT(UABALT, aa64_sve2, gen_gvec_ool_arg_zzzz, uabal_fns[a->esz], a, 1) | |
b8295dfb RH |
6826 | |
6827 | static bool do_adcl(DisasContext *s, arg_rrrr_esz *a, bool sel) | |
6828 | { | |
6829 | static gen_helper_gvec_4 * const fns[2] = { | |
6830 | gen_helper_sve2_adcl_s, | |
6831 | gen_helper_sve2_adcl_d, | |
6832 | }; | |
6833 | /* | |
6834 | * Note that in this case the ESZ field encodes both size and sign. | |
6835 | * Split out 'subtract' into bit 1 of the data field for the helper. | |
6836 | */ | |
eeb4e84d | 6837 | return gen_gvec_ool_arg_zzzz(s, fns[a->esz & 1], a, (a->esz & 2) | sel); |
b8295dfb RH |
6838 | } |
6839 | ||
eeb4e84d RH |
6840 | TRANS_FEAT(ADCLB, aa64_sve2, do_adcl, a, false) |
6841 | TRANS_FEAT(ADCLT, aa64_sve2, do_adcl, a, true) | |
a7e3a90e RH |
6842 | |
6843 | static bool do_sve2_fn2i(DisasContext *s, arg_rri_esz *a, GVecGen2iFn *fn) | |
6844 | { | |
6845 | if (a->esz < 0 || !dc_isar_feature(aa64_sve2, s)) { | |
6846 | return false; | |
6847 | } | |
faf915e2 | 6848 | return gen_gvec_fn_zzi(s, fn, a->esz, a->rd, a->rn, a->imm); |
a7e3a90e RH |
6849 | } |
6850 | ||
6851 | static bool trans_SSRA(DisasContext *s, arg_rri_esz *a) | |
6852 | { | |
6853 | return do_sve2_fn2i(s, a, gen_gvec_ssra); | |
6854 | } | |
6855 | ||
6856 | static bool trans_USRA(DisasContext *s, arg_rri_esz *a) | |
6857 | { | |
6858 | return do_sve2_fn2i(s, a, gen_gvec_usra); | |
6859 | } | |
6860 | ||
6861 | static bool trans_SRSRA(DisasContext *s, arg_rri_esz *a) | |
6862 | { | |
6863 | return do_sve2_fn2i(s, a, gen_gvec_srsra); | |
6864 | } | |
6865 | ||
6866 | static bool trans_URSRA(DisasContext *s, arg_rri_esz *a) | |
6867 | { | |
6868 | return do_sve2_fn2i(s, a, gen_gvec_ursra); | |
6869 | } | |
fc12b46a RH |
6870 | |
6871 | static bool trans_SRI(DisasContext *s, arg_rri_esz *a) | |
6872 | { | |
6873 | return do_sve2_fn2i(s, a, gen_gvec_sri); | |
6874 | } | |
6875 | ||
6876 | static bool trans_SLI(DisasContext *s, arg_rri_esz *a) | |
6877 | { | |
6878 | return do_sve2_fn2i(s, a, gen_gvec_sli); | |
6879 | } | |
289a1797 | 6880 | |
79828dcb RH |
6881 | TRANS_FEAT(SABA, aa64_sve2, gen_gvec_fn_arg_zzz, gen_gvec_saba, a) |
6882 | TRANS_FEAT(UABA, aa64_sve2, gen_gvec_fn_arg_zzz, gen_gvec_uaba, a) | |
5ff2838d RH |
6883 | |
6884 | static bool do_sve2_narrow_extract(DisasContext *s, arg_rri_esz *a, | |
6885 | const GVecGen2 ops[3]) | |
6886 | { | |
6887 | if (a->esz < 0 || a->esz > MO_32 || a->imm != 0 || | |
6888 | !dc_isar_feature(aa64_sve2, s)) { | |
6889 | return false; | |
6890 | } | |
6891 | if (sve_access_check(s)) { | |
6892 | unsigned vsz = vec_full_reg_size(s); | |
6893 | tcg_gen_gvec_2(vec_full_reg_offset(s, a->rd), | |
6894 | vec_full_reg_offset(s, a->rn), | |
6895 | vsz, vsz, &ops[a->esz]); | |
6896 | } | |
6897 | return true; | |
6898 | } | |
6899 | ||
6900 | static const TCGOpcode sqxtn_list[] = { | |
6901 | INDEX_op_shli_vec, INDEX_op_smin_vec, INDEX_op_smax_vec, 0 | |
6902 | }; | |
6903 | ||
6904 | static void gen_sqxtnb_vec(unsigned vece, TCGv_vec d, TCGv_vec n) | |
6905 | { | |
6906 | TCGv_vec t = tcg_temp_new_vec_matching(d); | |
6907 | int halfbits = 4 << vece; | |
6908 | int64_t mask = (1ull << halfbits) - 1; | |
6909 | int64_t min = -1ull << (halfbits - 1); | |
6910 | int64_t max = -min - 1; | |
6911 | ||
6912 | tcg_gen_dupi_vec(vece, t, min); | |
6913 | tcg_gen_smax_vec(vece, d, n, t); | |
6914 | tcg_gen_dupi_vec(vece, t, max); | |
6915 | tcg_gen_smin_vec(vece, d, d, t); | |
6916 | tcg_gen_dupi_vec(vece, t, mask); | |
6917 | tcg_gen_and_vec(vece, d, d, t); | |
6918 | tcg_temp_free_vec(t); | |
6919 | } | |
6920 | ||
6921 | static bool trans_SQXTNB(DisasContext *s, arg_rri_esz *a) | |
6922 | { | |
6923 | static const GVecGen2 ops[3] = { | |
6924 | { .fniv = gen_sqxtnb_vec, | |
6925 | .opt_opc = sqxtn_list, | |
6926 | .fno = gen_helper_sve2_sqxtnb_h, | |
6927 | .vece = MO_16 }, | |
6928 | { .fniv = gen_sqxtnb_vec, | |
6929 | .opt_opc = sqxtn_list, | |
6930 | .fno = gen_helper_sve2_sqxtnb_s, | |
6931 | .vece = MO_32 }, | |
6932 | { .fniv = gen_sqxtnb_vec, | |
6933 | .opt_opc = sqxtn_list, | |
6934 | .fno = gen_helper_sve2_sqxtnb_d, | |
6935 | .vece = MO_64 }, | |
6936 | }; | |
6937 | return do_sve2_narrow_extract(s, a, ops); | |
6938 | } | |
6939 | ||
6940 | static void gen_sqxtnt_vec(unsigned vece, TCGv_vec d, TCGv_vec n) | |
6941 | { | |
6942 | TCGv_vec t = tcg_temp_new_vec_matching(d); | |
6943 | int halfbits = 4 << vece; | |
6944 | int64_t mask = (1ull << halfbits) - 1; | |
6945 | int64_t min = -1ull << (halfbits - 1); | |
6946 | int64_t max = -min - 1; | |
6947 | ||
6948 | tcg_gen_dupi_vec(vece, t, min); | |
6949 | tcg_gen_smax_vec(vece, n, n, t); | |
6950 | tcg_gen_dupi_vec(vece, t, max); | |
6951 | tcg_gen_smin_vec(vece, n, n, t); | |
6952 | tcg_gen_shli_vec(vece, n, n, halfbits); | |
6953 | tcg_gen_dupi_vec(vece, t, mask); | |
6954 | tcg_gen_bitsel_vec(vece, d, t, d, n); | |
6955 | tcg_temp_free_vec(t); | |
6956 | } | |
6957 | ||
6958 | static bool trans_SQXTNT(DisasContext *s, arg_rri_esz *a) | |
6959 | { | |
6960 | static const GVecGen2 ops[3] = { | |
6961 | { .fniv = gen_sqxtnt_vec, | |
6962 | .opt_opc = sqxtn_list, | |
6963 | .load_dest = true, | |
6964 | .fno = gen_helper_sve2_sqxtnt_h, | |
6965 | .vece = MO_16 }, | |
6966 | { .fniv = gen_sqxtnt_vec, | |
6967 | .opt_opc = sqxtn_list, | |
6968 | .load_dest = true, | |
6969 | .fno = gen_helper_sve2_sqxtnt_s, | |
6970 | .vece = MO_32 }, | |
6971 | { .fniv = gen_sqxtnt_vec, | |
6972 | .opt_opc = sqxtn_list, | |
6973 | .load_dest = true, | |
6974 | .fno = gen_helper_sve2_sqxtnt_d, | |
6975 | .vece = MO_64 }, | |
6976 | }; | |
6977 | return do_sve2_narrow_extract(s, a, ops); | |
6978 | } | |
6979 | ||
6980 | static const TCGOpcode uqxtn_list[] = { | |
6981 | INDEX_op_shli_vec, INDEX_op_umin_vec, 0 | |
6982 | }; | |
6983 | ||
6984 | static void gen_uqxtnb_vec(unsigned vece, TCGv_vec d, TCGv_vec n) | |
6985 | { | |
6986 | TCGv_vec t = tcg_temp_new_vec_matching(d); | |
6987 | int halfbits = 4 << vece; | |
6988 | int64_t max = (1ull << halfbits) - 1; | |
6989 | ||
6990 | tcg_gen_dupi_vec(vece, t, max); | |
6991 | tcg_gen_umin_vec(vece, d, n, t); | |
6992 | tcg_temp_free_vec(t); | |
6993 | } | |
6994 | ||
6995 | static bool trans_UQXTNB(DisasContext *s, arg_rri_esz *a) | |
6996 | { | |
6997 | static const GVecGen2 ops[3] = { | |
6998 | { .fniv = gen_uqxtnb_vec, | |
6999 | .opt_opc = uqxtn_list, | |
7000 | .fno = gen_helper_sve2_uqxtnb_h, | |
7001 | .vece = MO_16 }, | |
7002 | { .fniv = gen_uqxtnb_vec, | |
7003 | .opt_opc = uqxtn_list, | |
7004 | .fno = gen_helper_sve2_uqxtnb_s, | |
7005 | .vece = MO_32 }, | |
7006 | { .fniv = gen_uqxtnb_vec, | |
7007 | .opt_opc = uqxtn_list, | |
7008 | .fno = gen_helper_sve2_uqxtnb_d, | |
7009 | .vece = MO_64 }, | |
7010 | }; | |
7011 | return do_sve2_narrow_extract(s, a, ops); | |
7012 | } | |
7013 | ||
7014 | static void gen_uqxtnt_vec(unsigned vece, TCGv_vec d, TCGv_vec n) | |
7015 | { | |
7016 | TCGv_vec t = tcg_temp_new_vec_matching(d); | |
7017 | int halfbits = 4 << vece; | |
7018 | int64_t max = (1ull << halfbits) - 1; | |
7019 | ||
7020 | tcg_gen_dupi_vec(vece, t, max); | |
7021 | tcg_gen_umin_vec(vece, n, n, t); | |
7022 | tcg_gen_shli_vec(vece, n, n, halfbits); | |
7023 | tcg_gen_bitsel_vec(vece, d, t, d, n); | |
7024 | tcg_temp_free_vec(t); | |
7025 | } | |
7026 | ||
7027 | static bool trans_UQXTNT(DisasContext *s, arg_rri_esz *a) | |
7028 | { | |
7029 | static const GVecGen2 ops[3] = { | |
7030 | { .fniv = gen_uqxtnt_vec, | |
7031 | .opt_opc = uqxtn_list, | |
7032 | .load_dest = true, | |
7033 | .fno = gen_helper_sve2_uqxtnt_h, | |
7034 | .vece = MO_16 }, | |
7035 | { .fniv = gen_uqxtnt_vec, | |
7036 | .opt_opc = uqxtn_list, | |
7037 | .load_dest = true, | |
7038 | .fno = gen_helper_sve2_uqxtnt_s, | |
7039 | .vece = MO_32 }, | |
7040 | { .fniv = gen_uqxtnt_vec, | |
7041 | .opt_opc = uqxtn_list, | |
7042 | .load_dest = true, | |
7043 | .fno = gen_helper_sve2_uqxtnt_d, | |
7044 | .vece = MO_64 }, | |
7045 | }; | |
7046 | return do_sve2_narrow_extract(s, a, ops); | |
7047 | } | |
7048 | ||
7049 | static const TCGOpcode sqxtun_list[] = { | |
7050 | INDEX_op_shli_vec, INDEX_op_umin_vec, INDEX_op_smax_vec, 0 | |
7051 | }; | |
7052 | ||
7053 | static void gen_sqxtunb_vec(unsigned vece, TCGv_vec d, TCGv_vec n) | |
7054 | { | |
7055 | TCGv_vec t = tcg_temp_new_vec_matching(d); | |
7056 | int halfbits = 4 << vece; | |
7057 | int64_t max = (1ull << halfbits) - 1; | |
7058 | ||
7059 | tcg_gen_dupi_vec(vece, t, 0); | |
7060 | tcg_gen_smax_vec(vece, d, n, t); | |
7061 | tcg_gen_dupi_vec(vece, t, max); | |
7062 | tcg_gen_umin_vec(vece, d, d, t); | |
7063 | tcg_temp_free_vec(t); | |
7064 | } | |
7065 | ||
7066 | static bool trans_SQXTUNB(DisasContext *s, arg_rri_esz *a) | |
7067 | { | |
7068 | static const GVecGen2 ops[3] = { | |
7069 | { .fniv = gen_sqxtunb_vec, | |
7070 | .opt_opc = sqxtun_list, | |
7071 | .fno = gen_helper_sve2_sqxtunb_h, | |
7072 | .vece = MO_16 }, | |
7073 | { .fniv = gen_sqxtunb_vec, | |
7074 | .opt_opc = sqxtun_list, | |
7075 | .fno = gen_helper_sve2_sqxtunb_s, | |
7076 | .vece = MO_32 }, | |
7077 | { .fniv = gen_sqxtunb_vec, | |
7078 | .opt_opc = sqxtun_list, | |
7079 | .fno = gen_helper_sve2_sqxtunb_d, | |
7080 | .vece = MO_64 }, | |
7081 | }; | |
7082 | return do_sve2_narrow_extract(s, a, ops); | |
7083 | } | |
7084 | ||
7085 | static void gen_sqxtunt_vec(unsigned vece, TCGv_vec d, TCGv_vec n) | |
7086 | { | |
7087 | TCGv_vec t = tcg_temp_new_vec_matching(d); | |
7088 | int halfbits = 4 << vece; | |
7089 | int64_t max = (1ull << halfbits) - 1; | |
7090 | ||
7091 | tcg_gen_dupi_vec(vece, t, 0); | |
7092 | tcg_gen_smax_vec(vece, n, n, t); | |
7093 | tcg_gen_dupi_vec(vece, t, max); | |
7094 | tcg_gen_umin_vec(vece, n, n, t); | |
7095 | tcg_gen_shli_vec(vece, n, n, halfbits); | |
7096 | tcg_gen_bitsel_vec(vece, d, t, d, n); | |
7097 | tcg_temp_free_vec(t); | |
7098 | } | |
7099 | ||
7100 | static bool trans_SQXTUNT(DisasContext *s, arg_rri_esz *a) | |
7101 | { | |
7102 | static const GVecGen2 ops[3] = { | |
7103 | { .fniv = gen_sqxtunt_vec, | |
7104 | .opt_opc = sqxtun_list, | |
7105 | .load_dest = true, | |
7106 | .fno = gen_helper_sve2_sqxtunt_h, | |
7107 | .vece = MO_16 }, | |
7108 | { .fniv = gen_sqxtunt_vec, | |
7109 | .opt_opc = sqxtun_list, | |
7110 | .load_dest = true, | |
7111 | .fno = gen_helper_sve2_sqxtunt_s, | |
7112 | .vece = MO_32 }, | |
7113 | { .fniv = gen_sqxtunt_vec, | |
7114 | .opt_opc = sqxtun_list, | |
7115 | .load_dest = true, | |
7116 | .fno = gen_helper_sve2_sqxtunt_d, | |
7117 | .vece = MO_64 }, | |
7118 | }; | |
7119 | return do_sve2_narrow_extract(s, a, ops); | |
46d111b2 RH |
7120 | } |
7121 | ||
7122 | static bool do_sve2_shr_narrow(DisasContext *s, arg_rri_esz *a, | |
7123 | const GVecGen2i ops[3]) | |
7124 | { | |
7125 | if (a->esz < 0 || a->esz > MO_32 || !dc_isar_feature(aa64_sve2, s)) { | |
7126 | return false; | |
7127 | } | |
7128 | assert(a->imm > 0 && a->imm <= (8 << a->esz)); | |
7129 | if (sve_access_check(s)) { | |
7130 | unsigned vsz = vec_full_reg_size(s); | |
7131 | tcg_gen_gvec_2i(vec_full_reg_offset(s, a->rd), | |
7132 | vec_full_reg_offset(s, a->rn), | |
7133 | vsz, vsz, a->imm, &ops[a->esz]); | |
7134 | } | |
7135 | return true; | |
7136 | } | |
7137 | ||
7138 | static void gen_shrnb_i64(unsigned vece, TCGv_i64 d, TCGv_i64 n, int shr) | |
7139 | { | |
7140 | int halfbits = 4 << vece; | |
7141 | uint64_t mask = dup_const(vece, MAKE_64BIT_MASK(0, halfbits)); | |
7142 | ||
7143 | tcg_gen_shri_i64(d, n, shr); | |
7144 | tcg_gen_andi_i64(d, d, mask); | |
7145 | } | |
7146 | ||
7147 | static void gen_shrnb16_i64(TCGv_i64 d, TCGv_i64 n, int64_t shr) | |
7148 | { | |
7149 | gen_shrnb_i64(MO_16, d, n, shr); | |
7150 | } | |
7151 | ||
7152 | static void gen_shrnb32_i64(TCGv_i64 d, TCGv_i64 n, int64_t shr) | |
7153 | { | |
7154 | gen_shrnb_i64(MO_32, d, n, shr); | |
7155 | } | |
7156 | ||
7157 | static void gen_shrnb64_i64(TCGv_i64 d, TCGv_i64 n, int64_t shr) | |
7158 | { | |
7159 | gen_shrnb_i64(MO_64, d, n, shr); | |
7160 | } | |
7161 | ||
7162 | static void gen_shrnb_vec(unsigned vece, TCGv_vec d, TCGv_vec n, int64_t shr) | |
7163 | { | |
7164 | TCGv_vec t = tcg_temp_new_vec_matching(d); | |
7165 | int halfbits = 4 << vece; | |
7166 | uint64_t mask = MAKE_64BIT_MASK(0, halfbits); | |
7167 | ||
7168 | tcg_gen_shri_vec(vece, n, n, shr); | |
7169 | tcg_gen_dupi_vec(vece, t, mask); | |
7170 | tcg_gen_and_vec(vece, d, n, t); | |
7171 | tcg_temp_free_vec(t); | |
7172 | } | |
7173 | ||
7174 | static bool trans_SHRNB(DisasContext *s, arg_rri_esz *a) | |
7175 | { | |
7176 | static const TCGOpcode vec_list[] = { INDEX_op_shri_vec, 0 }; | |
7177 | static const GVecGen2i ops[3] = { | |
7178 | { .fni8 = gen_shrnb16_i64, | |
7179 | .fniv = gen_shrnb_vec, | |
7180 | .opt_opc = vec_list, | |
7181 | .fno = gen_helper_sve2_shrnb_h, | |
7182 | .vece = MO_16 }, | |
7183 | { .fni8 = gen_shrnb32_i64, | |
7184 | .fniv = gen_shrnb_vec, | |
7185 | .opt_opc = vec_list, | |
7186 | .fno = gen_helper_sve2_shrnb_s, | |
7187 | .vece = MO_32 }, | |
7188 | { .fni8 = gen_shrnb64_i64, | |
7189 | .fniv = gen_shrnb_vec, | |
7190 | .opt_opc = vec_list, | |
7191 | .fno = gen_helper_sve2_shrnb_d, | |
7192 | .vece = MO_64 }, | |
7193 | }; | |
7194 | return do_sve2_shr_narrow(s, a, ops); | |
7195 | } | |
7196 | ||
7197 | static void gen_shrnt_i64(unsigned vece, TCGv_i64 d, TCGv_i64 n, int shr) | |
7198 | { | |
7199 | int halfbits = 4 << vece; | |
7200 | uint64_t mask = dup_const(vece, MAKE_64BIT_MASK(0, halfbits)); | |
7201 | ||
7202 | tcg_gen_shli_i64(n, n, halfbits - shr); | |
7203 | tcg_gen_andi_i64(n, n, ~mask); | |
7204 | tcg_gen_andi_i64(d, d, mask); | |
7205 | tcg_gen_or_i64(d, d, n); | |
7206 | } | |
7207 | ||
7208 | static void gen_shrnt16_i64(TCGv_i64 d, TCGv_i64 n, int64_t shr) | |
7209 | { | |
7210 | gen_shrnt_i64(MO_16, d, n, shr); | |
7211 | } | |
7212 | ||
7213 | static void gen_shrnt32_i64(TCGv_i64 d, TCGv_i64 n, int64_t shr) | |
7214 | { | |
7215 | gen_shrnt_i64(MO_32, d, n, shr); | |
7216 | } | |
7217 | ||
7218 | static void gen_shrnt64_i64(TCGv_i64 d, TCGv_i64 n, int64_t shr) | |
7219 | { | |
7220 | tcg_gen_shri_i64(n, n, shr); | |
7221 | tcg_gen_deposit_i64(d, d, n, 32, 32); | |
7222 | } | |
7223 | ||
7224 | static void gen_shrnt_vec(unsigned vece, TCGv_vec d, TCGv_vec n, int64_t shr) | |
7225 | { | |
7226 | TCGv_vec t = tcg_temp_new_vec_matching(d); | |
7227 | int halfbits = 4 << vece; | |
7228 | uint64_t mask = MAKE_64BIT_MASK(0, halfbits); | |
7229 | ||
7230 | tcg_gen_shli_vec(vece, n, n, halfbits - shr); | |
7231 | tcg_gen_dupi_vec(vece, t, mask); | |
7232 | tcg_gen_bitsel_vec(vece, d, t, d, n); | |
7233 | tcg_temp_free_vec(t); | |
7234 | } | |
7235 | ||
7236 | static bool trans_SHRNT(DisasContext *s, arg_rri_esz *a) | |
7237 | { | |
7238 | static const TCGOpcode vec_list[] = { INDEX_op_shli_vec, 0 }; | |
7239 | static const GVecGen2i ops[3] = { | |
7240 | { .fni8 = gen_shrnt16_i64, | |
7241 | .fniv = gen_shrnt_vec, | |
7242 | .opt_opc = vec_list, | |
7243 | .load_dest = true, | |
7244 | .fno = gen_helper_sve2_shrnt_h, | |
7245 | .vece = MO_16 }, | |
7246 | { .fni8 = gen_shrnt32_i64, | |
7247 | .fniv = gen_shrnt_vec, | |
7248 | .opt_opc = vec_list, | |
7249 | .load_dest = true, | |
7250 | .fno = gen_helper_sve2_shrnt_s, | |
7251 | .vece = MO_32 }, | |
7252 | { .fni8 = gen_shrnt64_i64, | |
7253 | .fniv = gen_shrnt_vec, | |
7254 | .opt_opc = vec_list, | |
7255 | .load_dest = true, | |
7256 | .fno = gen_helper_sve2_shrnt_d, | |
7257 | .vece = MO_64 }, | |
7258 | }; | |
7259 | return do_sve2_shr_narrow(s, a, ops); | |
7260 | } | |
7261 | ||
7262 | static bool trans_RSHRNB(DisasContext *s, arg_rri_esz *a) | |
7263 | { | |
7264 | static const GVecGen2i ops[3] = { | |
7265 | { .fno = gen_helper_sve2_rshrnb_h }, | |
7266 | { .fno = gen_helper_sve2_rshrnb_s }, | |
7267 | { .fno = gen_helper_sve2_rshrnb_d }, | |
7268 | }; | |
7269 | return do_sve2_shr_narrow(s, a, ops); | |
7270 | } | |
7271 | ||
7272 | static bool trans_RSHRNT(DisasContext *s, arg_rri_esz *a) | |
7273 | { | |
7274 | static const GVecGen2i ops[3] = { | |
7275 | { .fno = gen_helper_sve2_rshrnt_h }, | |
7276 | { .fno = gen_helper_sve2_rshrnt_s }, | |
7277 | { .fno = gen_helper_sve2_rshrnt_d }, | |
7278 | }; | |
7279 | return do_sve2_shr_narrow(s, a, ops); | |
81fd3e6e RH |
7280 | } |
7281 | ||
7282 | static void gen_sqshrunb_vec(unsigned vece, TCGv_vec d, | |
7283 | TCGv_vec n, int64_t shr) | |
7284 | { | |
7285 | TCGv_vec t = tcg_temp_new_vec_matching(d); | |
7286 | int halfbits = 4 << vece; | |
7287 | ||
7288 | tcg_gen_sari_vec(vece, n, n, shr); | |
7289 | tcg_gen_dupi_vec(vece, t, 0); | |
7290 | tcg_gen_smax_vec(vece, n, n, t); | |
7291 | tcg_gen_dupi_vec(vece, t, MAKE_64BIT_MASK(0, halfbits)); | |
7292 | tcg_gen_umin_vec(vece, d, n, t); | |
7293 | tcg_temp_free_vec(t); | |
7294 | } | |
7295 | ||
7296 | static bool trans_SQSHRUNB(DisasContext *s, arg_rri_esz *a) | |
7297 | { | |
7298 | static const TCGOpcode vec_list[] = { | |
7299 | INDEX_op_sari_vec, INDEX_op_smax_vec, INDEX_op_umin_vec, 0 | |
7300 | }; | |
7301 | static const GVecGen2i ops[3] = { | |
7302 | { .fniv = gen_sqshrunb_vec, | |
7303 | .opt_opc = vec_list, | |
7304 | .fno = gen_helper_sve2_sqshrunb_h, | |
7305 | .vece = MO_16 }, | |
7306 | { .fniv = gen_sqshrunb_vec, | |
7307 | .opt_opc = vec_list, | |
7308 | .fno = gen_helper_sve2_sqshrunb_s, | |
7309 | .vece = MO_32 }, | |
7310 | { .fniv = gen_sqshrunb_vec, | |
7311 | .opt_opc = vec_list, | |
7312 | .fno = gen_helper_sve2_sqshrunb_d, | |
7313 | .vece = MO_64 }, | |
7314 | }; | |
7315 | return do_sve2_shr_narrow(s, a, ops); | |
7316 | } | |
7317 | ||
7318 | static void gen_sqshrunt_vec(unsigned vece, TCGv_vec d, | |
7319 | TCGv_vec n, int64_t shr) | |
7320 | { | |
7321 | TCGv_vec t = tcg_temp_new_vec_matching(d); | |
7322 | int halfbits = 4 << vece; | |
7323 | ||
7324 | tcg_gen_sari_vec(vece, n, n, shr); | |
7325 | tcg_gen_dupi_vec(vece, t, 0); | |
7326 | tcg_gen_smax_vec(vece, n, n, t); | |
7327 | tcg_gen_dupi_vec(vece, t, MAKE_64BIT_MASK(0, halfbits)); | |
7328 | tcg_gen_umin_vec(vece, n, n, t); | |
7329 | tcg_gen_shli_vec(vece, n, n, halfbits); | |
7330 | tcg_gen_bitsel_vec(vece, d, t, d, n); | |
7331 | tcg_temp_free_vec(t); | |
7332 | } | |
7333 | ||
7334 | static bool trans_SQSHRUNT(DisasContext *s, arg_rri_esz *a) | |
7335 | { | |
7336 | static const TCGOpcode vec_list[] = { | |
7337 | INDEX_op_shli_vec, INDEX_op_sari_vec, | |
7338 | INDEX_op_smax_vec, INDEX_op_umin_vec, 0 | |
7339 | }; | |
7340 | static const GVecGen2i ops[3] = { | |
7341 | { .fniv = gen_sqshrunt_vec, | |
7342 | .opt_opc = vec_list, | |
7343 | .load_dest = true, | |
7344 | .fno = gen_helper_sve2_sqshrunt_h, | |
7345 | .vece = MO_16 }, | |
7346 | { .fniv = gen_sqshrunt_vec, | |
7347 | .opt_opc = vec_list, | |
7348 | .load_dest = true, | |
7349 | .fno = gen_helper_sve2_sqshrunt_s, | |
7350 | .vece = MO_32 }, | |
7351 | { .fniv = gen_sqshrunt_vec, | |
7352 | .opt_opc = vec_list, | |
7353 | .load_dest = true, | |
7354 | .fno = gen_helper_sve2_sqshrunt_d, | |
7355 | .vece = MO_64 }, | |
7356 | }; | |
7357 | return do_sve2_shr_narrow(s, a, ops); | |
7358 | } | |
7359 | ||
7360 | static bool trans_SQRSHRUNB(DisasContext *s, arg_rri_esz *a) | |
7361 | { | |
7362 | static const GVecGen2i ops[3] = { | |
7363 | { .fno = gen_helper_sve2_sqrshrunb_h }, | |
7364 | { .fno = gen_helper_sve2_sqrshrunb_s }, | |
7365 | { .fno = gen_helper_sve2_sqrshrunb_d }, | |
7366 | }; | |
7367 | return do_sve2_shr_narrow(s, a, ops); | |
7368 | } | |
7369 | ||
7370 | static bool trans_SQRSHRUNT(DisasContext *s, arg_rri_esz *a) | |
7371 | { | |
7372 | static const GVecGen2i ops[3] = { | |
7373 | { .fno = gen_helper_sve2_sqrshrunt_h }, | |
7374 | { .fno = gen_helper_sve2_sqrshrunt_s }, | |
7375 | { .fno = gen_helper_sve2_sqrshrunt_d }, | |
7376 | }; | |
7377 | return do_sve2_shr_narrow(s, a, ops); | |
c13418da RH |
7378 | } |
7379 | ||
743bb147 RH |
7380 | static void gen_sqshrnb_vec(unsigned vece, TCGv_vec d, |
7381 | TCGv_vec n, int64_t shr) | |
7382 | { | |
7383 | TCGv_vec t = tcg_temp_new_vec_matching(d); | |
7384 | int halfbits = 4 << vece; | |
7385 | int64_t max = MAKE_64BIT_MASK(0, halfbits - 1); | |
7386 | int64_t min = -max - 1; | |
7387 | ||
7388 | tcg_gen_sari_vec(vece, n, n, shr); | |
7389 | tcg_gen_dupi_vec(vece, t, min); | |
7390 | tcg_gen_smax_vec(vece, n, n, t); | |
7391 | tcg_gen_dupi_vec(vece, t, max); | |
7392 | tcg_gen_smin_vec(vece, n, n, t); | |
7393 | tcg_gen_dupi_vec(vece, t, MAKE_64BIT_MASK(0, halfbits)); | |
7394 | tcg_gen_and_vec(vece, d, n, t); | |
7395 | tcg_temp_free_vec(t); | |
7396 | } | |
7397 | ||
7398 | static bool trans_SQSHRNB(DisasContext *s, arg_rri_esz *a) | |
7399 | { | |
7400 | static const TCGOpcode vec_list[] = { | |
7401 | INDEX_op_sari_vec, INDEX_op_smax_vec, INDEX_op_smin_vec, 0 | |
7402 | }; | |
7403 | static const GVecGen2i ops[3] = { | |
7404 | { .fniv = gen_sqshrnb_vec, | |
7405 | .opt_opc = vec_list, | |
7406 | .fno = gen_helper_sve2_sqshrnb_h, | |
7407 | .vece = MO_16 }, | |
7408 | { .fniv = gen_sqshrnb_vec, | |
7409 | .opt_opc = vec_list, | |
7410 | .fno = gen_helper_sve2_sqshrnb_s, | |
7411 | .vece = MO_32 }, | |
7412 | { .fniv = gen_sqshrnb_vec, | |
7413 | .opt_opc = vec_list, | |
7414 | .fno = gen_helper_sve2_sqshrnb_d, | |
7415 | .vece = MO_64 }, | |
7416 | }; | |
7417 | return do_sve2_shr_narrow(s, a, ops); | |
7418 | } | |
7419 | ||
7420 | static void gen_sqshrnt_vec(unsigned vece, TCGv_vec d, | |
7421 | TCGv_vec n, int64_t shr) | |
7422 | { | |
7423 | TCGv_vec t = tcg_temp_new_vec_matching(d); | |
7424 | int halfbits = 4 << vece; | |
7425 | int64_t max = MAKE_64BIT_MASK(0, halfbits - 1); | |
7426 | int64_t min = -max - 1; | |
7427 | ||
7428 | tcg_gen_sari_vec(vece, n, n, shr); | |
7429 | tcg_gen_dupi_vec(vece, t, min); | |
7430 | tcg_gen_smax_vec(vece, n, n, t); | |
7431 | tcg_gen_dupi_vec(vece, t, max); | |
7432 | tcg_gen_smin_vec(vece, n, n, t); | |
7433 | tcg_gen_shli_vec(vece, n, n, halfbits); | |
7434 | tcg_gen_dupi_vec(vece, t, MAKE_64BIT_MASK(0, halfbits)); | |
7435 | tcg_gen_bitsel_vec(vece, d, t, d, n); | |
7436 | tcg_temp_free_vec(t); | |
7437 | } | |
7438 | ||
7439 | static bool trans_SQSHRNT(DisasContext *s, arg_rri_esz *a) | |
7440 | { | |
7441 | static const TCGOpcode vec_list[] = { | |
7442 | INDEX_op_shli_vec, INDEX_op_sari_vec, | |
7443 | INDEX_op_smax_vec, INDEX_op_smin_vec, 0 | |
7444 | }; | |
7445 | static const GVecGen2i ops[3] = { | |
7446 | { .fniv = gen_sqshrnt_vec, | |
7447 | .opt_opc = vec_list, | |
7448 | .load_dest = true, | |
7449 | .fno = gen_helper_sve2_sqshrnt_h, | |
7450 | .vece = MO_16 }, | |
7451 | { .fniv = gen_sqshrnt_vec, | |
7452 | .opt_opc = vec_list, | |
7453 | .load_dest = true, | |
7454 | .fno = gen_helper_sve2_sqshrnt_s, | |
7455 | .vece = MO_32 }, | |
7456 | { .fniv = gen_sqshrnt_vec, | |
7457 | .opt_opc = vec_list, | |
7458 | .load_dest = true, | |
7459 | .fno = gen_helper_sve2_sqshrnt_d, | |
7460 | .vece = MO_64 }, | |
7461 | }; | |
7462 | return do_sve2_shr_narrow(s, a, ops); | |
7463 | } | |
7464 | ||
7465 | static bool trans_SQRSHRNB(DisasContext *s, arg_rri_esz *a) | |
7466 | { | |
7467 | static const GVecGen2i ops[3] = { | |
7468 | { .fno = gen_helper_sve2_sqrshrnb_h }, | |
7469 | { .fno = gen_helper_sve2_sqrshrnb_s }, | |
7470 | { .fno = gen_helper_sve2_sqrshrnb_d }, | |
7471 | }; | |
7472 | return do_sve2_shr_narrow(s, a, ops); | |
7473 | } | |
7474 | ||
7475 | static bool trans_SQRSHRNT(DisasContext *s, arg_rri_esz *a) | |
7476 | { | |
7477 | static const GVecGen2i ops[3] = { | |
7478 | { .fno = gen_helper_sve2_sqrshrnt_h }, | |
7479 | { .fno = gen_helper_sve2_sqrshrnt_s }, | |
7480 | { .fno = gen_helper_sve2_sqrshrnt_d }, | |
7481 | }; | |
7482 | return do_sve2_shr_narrow(s, a, ops); | |
7483 | } | |
7484 | ||
c13418da RH |
7485 | static void gen_uqshrnb_vec(unsigned vece, TCGv_vec d, |
7486 | TCGv_vec n, int64_t shr) | |
7487 | { | |
7488 | TCGv_vec t = tcg_temp_new_vec_matching(d); | |
7489 | int halfbits = 4 << vece; | |
7490 | ||
7491 | tcg_gen_shri_vec(vece, n, n, shr); | |
7492 | tcg_gen_dupi_vec(vece, t, MAKE_64BIT_MASK(0, halfbits)); | |
7493 | tcg_gen_umin_vec(vece, d, n, t); | |
7494 | tcg_temp_free_vec(t); | |
7495 | } | |
7496 | ||
7497 | static bool trans_UQSHRNB(DisasContext *s, arg_rri_esz *a) | |
7498 | { | |
7499 | static const TCGOpcode vec_list[] = { | |
7500 | INDEX_op_shri_vec, INDEX_op_umin_vec, 0 | |
7501 | }; | |
7502 | static const GVecGen2i ops[3] = { | |
7503 | { .fniv = gen_uqshrnb_vec, | |
7504 | .opt_opc = vec_list, | |
7505 | .fno = gen_helper_sve2_uqshrnb_h, | |
7506 | .vece = MO_16 }, | |
7507 | { .fniv = gen_uqshrnb_vec, | |
7508 | .opt_opc = vec_list, | |
7509 | .fno = gen_helper_sve2_uqshrnb_s, | |
7510 | .vece = MO_32 }, | |
7511 | { .fniv = gen_uqshrnb_vec, | |
7512 | .opt_opc = vec_list, | |
7513 | .fno = gen_helper_sve2_uqshrnb_d, | |
7514 | .vece = MO_64 }, | |
7515 | }; | |
7516 | return do_sve2_shr_narrow(s, a, ops); | |
7517 | } | |
7518 | ||
7519 | static void gen_uqshrnt_vec(unsigned vece, TCGv_vec d, | |
7520 | TCGv_vec n, int64_t shr) | |
7521 | { | |
7522 | TCGv_vec t = tcg_temp_new_vec_matching(d); | |
7523 | int halfbits = 4 << vece; | |
7524 | ||
7525 | tcg_gen_shri_vec(vece, n, n, shr); | |
7526 | tcg_gen_dupi_vec(vece, t, MAKE_64BIT_MASK(0, halfbits)); | |
7527 | tcg_gen_umin_vec(vece, n, n, t); | |
7528 | tcg_gen_shli_vec(vece, n, n, halfbits); | |
7529 | tcg_gen_bitsel_vec(vece, d, t, d, n); | |
7530 | tcg_temp_free_vec(t); | |
7531 | } | |
7532 | ||
7533 | static bool trans_UQSHRNT(DisasContext *s, arg_rri_esz *a) | |
7534 | { | |
7535 | static const TCGOpcode vec_list[] = { | |
7536 | INDEX_op_shli_vec, INDEX_op_shri_vec, INDEX_op_umin_vec, 0 | |
7537 | }; | |
7538 | static const GVecGen2i ops[3] = { | |
7539 | { .fniv = gen_uqshrnt_vec, | |
7540 | .opt_opc = vec_list, | |
7541 | .load_dest = true, | |
7542 | .fno = gen_helper_sve2_uqshrnt_h, | |
7543 | .vece = MO_16 }, | |
7544 | { .fniv = gen_uqshrnt_vec, | |
7545 | .opt_opc = vec_list, | |
7546 | .load_dest = true, | |
7547 | .fno = gen_helper_sve2_uqshrnt_s, | |
7548 | .vece = MO_32 }, | |
7549 | { .fniv = gen_uqshrnt_vec, | |
7550 | .opt_opc = vec_list, | |
7551 | .load_dest = true, | |
7552 | .fno = gen_helper_sve2_uqshrnt_d, | |
7553 | .vece = MO_64 }, | |
7554 | }; | |
7555 | return do_sve2_shr_narrow(s, a, ops); | |
7556 | } | |
7557 | ||
7558 | static bool trans_UQRSHRNB(DisasContext *s, arg_rri_esz *a) | |
7559 | { | |
7560 | static const GVecGen2i ops[3] = { | |
7561 | { .fno = gen_helper_sve2_uqrshrnb_h }, | |
7562 | { .fno = gen_helper_sve2_uqrshrnb_s }, | |
7563 | { .fno = gen_helper_sve2_uqrshrnb_d }, | |
7564 | }; | |
7565 | return do_sve2_shr_narrow(s, a, ops); | |
7566 | } | |
7567 | ||
7568 | static bool trans_UQRSHRNT(DisasContext *s, arg_rri_esz *a) | |
7569 | { | |
7570 | static const GVecGen2i ops[3] = { | |
7571 | { .fno = gen_helper_sve2_uqrshrnt_h }, | |
7572 | { .fno = gen_helper_sve2_uqrshrnt_s }, | |
7573 | { .fno = gen_helper_sve2_uqrshrnt_d }, | |
7574 | }; | |
7575 | return do_sve2_shr_narrow(s, a, ops); | |
5ff2838d | 7576 | } |
b87dbeeb | 7577 | |
40d5ea50 | 7578 | #define DO_SVE2_ZZZ_NARROW(NAME, name) \ |
bd394cf5 | 7579 | static gen_helper_gvec_3 * const name##_fns[4] = { \ |
40d5ea50 SL |
7580 | NULL, gen_helper_sve2_##name##_h, \ |
7581 | gen_helper_sve2_##name##_s, gen_helper_sve2_##name##_d, \ | |
7582 | }; \ | |
bd394cf5 RH |
7583 | TRANS_FEAT(NAME, aa64_sve2, gen_gvec_ool_arg_zzz, \ |
7584 | name##_fns[a->esz], a, 0) | |
40d5ea50 SL |
7585 | |
7586 | DO_SVE2_ZZZ_NARROW(ADDHNB, addhnb) | |
7587 | DO_SVE2_ZZZ_NARROW(ADDHNT, addhnt) | |
0ea3ff02 SL |
7588 | DO_SVE2_ZZZ_NARROW(RADDHNB, raddhnb) |
7589 | DO_SVE2_ZZZ_NARROW(RADDHNT, raddhnt) | |
40d5ea50 | 7590 | |
c3cd6766 SL |
7591 | DO_SVE2_ZZZ_NARROW(SUBHNB, subhnb) |
7592 | DO_SVE2_ZZZ_NARROW(SUBHNT, subhnt) | |
e9443d10 SL |
7593 | DO_SVE2_ZZZ_NARROW(RSUBHNB, rsubhnb) |
7594 | DO_SVE2_ZZZ_NARROW(RSUBHNT, rsubhnt) | |
c3cd6766 | 7595 | |
e0ae6ec3 SL |
7596 | static bool do_sve2_ppzz_flags(DisasContext *s, arg_rprr_esz *a, |
7597 | gen_helper_gvec_flags_4 *fn) | |
7598 | { | |
7599 | if (!dc_isar_feature(aa64_sve2, s)) { | |
7600 | return false; | |
7601 | } | |
7602 | return do_ppzz_flags(s, a, fn); | |
7603 | } | |
7604 | ||
7605 | #define DO_SVE2_PPZZ_MATCH(NAME, name) \ | |
7606 | static bool trans_##NAME(DisasContext *s, arg_rprr_esz *a) \ | |
7607 | { \ | |
7608 | static gen_helper_gvec_flags_4 * const fns[4] = { \ | |
7609 | gen_helper_sve2_##name##_ppzz_b, gen_helper_sve2_##name##_ppzz_h, \ | |
7610 | NULL, NULL \ | |
7611 | }; \ | |
7612 | return do_sve2_ppzz_flags(s, a, fns[a->esz]); \ | |
7613 | } | |
7614 | ||
7615 | DO_SVE2_PPZZ_MATCH(MATCH, match) | |
7616 | DO_SVE2_PPZZ_MATCH(NMATCH, nmatch) | |
7617 | ||
5880bdc0 RH |
7618 | static gen_helper_gvec_4 * const histcnt_fns[4] = { |
7619 | NULL, NULL, gen_helper_sve2_histcnt_s, gen_helper_sve2_histcnt_d | |
7620 | }; | |
7621 | TRANS_FEAT(HISTCNT, aa64_sve2, gen_gvec_ool_arg_zpzz, | |
7622 | histcnt_fns[a->esz], a, 0) | |
7d47ac94 | 7623 | |
bd394cf5 RH |
7624 | TRANS_FEAT(HISTSEG, aa64_sve2, gen_gvec_ool_arg_zzz, |
7625 | a->esz == 0 ? gen_helper_sve2_histseg : NULL, a, 0) | |
7d47ac94 | 7626 | |
b87dbeeb SL |
7627 | static bool do_sve2_zpzz_fp(DisasContext *s, arg_rprr_esz *a, |
7628 | gen_helper_gvec_4_ptr *fn) | |
7629 | { | |
7630 | if (!dc_isar_feature(aa64_sve2, s)) { | |
7631 | return false; | |
7632 | } | |
7633 | return do_zpzz_fp(s, a, fn); | |
7634 | } | |
7635 | ||
7636 | #define DO_SVE2_ZPZZ_FP(NAME, name) \ | |
7637 | static bool trans_##NAME(DisasContext *s, arg_rprr_esz *a) \ | |
7638 | { \ | |
7639 | static gen_helper_gvec_4_ptr * const fns[4] = { \ | |
7640 | NULL, gen_helper_sve2_##name##_zpzz_h, \ | |
7641 | gen_helper_sve2_##name##_zpzz_s, gen_helper_sve2_##name##_zpzz_d \ | |
7642 | }; \ | |
7643 | return do_sve2_zpzz_fp(s, a, fns[a->esz]); \ | |
7644 | } | |
7645 | ||
7646 | DO_SVE2_ZPZZ_FP(FADDP, faddp) | |
7647 | DO_SVE2_ZPZZ_FP(FMAXNMP, fmaxnmp) | |
7648 | DO_SVE2_ZPZZ_FP(FMINNMP, fminnmp) | |
7649 | DO_SVE2_ZPZZ_FP(FMAXP, fmaxp) | |
7650 | DO_SVE2_ZPZZ_FP(FMINP, fminp) | |
bfc9307e RH |
7651 | |
7652 | /* | |
7653 | * SVE Integer Multiply-Add (unpredicated) | |
7654 | */ | |
7655 | ||
4f26756b SL |
7656 | static bool trans_FMMLA(DisasContext *s, arg_rrrr_esz *a) |
7657 | { | |
7658 | gen_helper_gvec_4_ptr *fn; | |
7659 | ||
7660 | switch (a->esz) { | |
7661 | case MO_32: | |
7662 | if (!dc_isar_feature(aa64_sve_f32mm, s)) { | |
7663 | return false; | |
7664 | } | |
7665 | fn = gen_helper_fmmla_s; | |
7666 | break; | |
7667 | case MO_64: | |
7668 | if (!dc_isar_feature(aa64_sve_f64mm, s)) { | |
7669 | return false; | |
7670 | } | |
7671 | fn = gen_helper_fmmla_d; | |
7672 | break; | |
7673 | default: | |
7674 | return false; | |
7675 | } | |
7676 | ||
7677 | if (sve_access_check(s)) { | |
7678 | unsigned vsz = vec_full_reg_size(s); | |
7679 | TCGv_ptr status = fpstatus_ptr(FPST_FPCR); | |
7680 | tcg_gen_gvec_4_ptr(vec_full_reg_offset(s, a->rd), | |
7681 | vec_full_reg_offset(s, a->rn), | |
7682 | vec_full_reg_offset(s, a->rm), | |
7683 | vec_full_reg_offset(s, a->ra), | |
7684 | status, vsz, vsz, 0, fn); | |
7685 | tcg_temp_free_ptr(status); | |
7686 | } | |
7687 | return true; | |
7688 | } | |
7689 | ||
eeb4e84d RH |
7690 | static gen_helper_gvec_4 * const sqdmlal_zzzw_fns[] = { |
7691 | NULL, gen_helper_sve2_sqdmlal_zzzw_h, | |
7692 | gen_helper_sve2_sqdmlal_zzzw_s, gen_helper_sve2_sqdmlal_zzzw_d, | |
7693 | }; | |
7694 | TRANS_FEAT(SQDMLALB_zzzw, aa64_sve2, gen_gvec_ool_arg_zzzz, | |
7695 | sqdmlal_zzzw_fns[a->esz], a, 0) | |
7696 | TRANS_FEAT(SQDMLALT_zzzw, aa64_sve2, gen_gvec_ool_arg_zzzz, | |
7697 | sqdmlal_zzzw_fns[a->esz], a, 3) | |
7698 | TRANS_FEAT(SQDMLALBT, aa64_sve2, gen_gvec_ool_arg_zzzz, | |
7699 | sqdmlal_zzzw_fns[a->esz], a, 2) | |
7700 | ||
7701 | static gen_helper_gvec_4 * const sqdmlsl_zzzw_fns[] = { | |
7702 | NULL, gen_helper_sve2_sqdmlsl_zzzw_h, | |
7703 | gen_helper_sve2_sqdmlsl_zzzw_s, gen_helper_sve2_sqdmlsl_zzzw_d, | |
7704 | }; | |
7705 | TRANS_FEAT(SQDMLSLB_zzzw, aa64_sve2, gen_gvec_ool_arg_zzzz, | |
7706 | sqdmlsl_zzzw_fns[a->esz], a, 0) | |
7707 | TRANS_FEAT(SQDMLSLT_zzzw, aa64_sve2, gen_gvec_ool_arg_zzzz, | |
7708 | sqdmlsl_zzzw_fns[a->esz], a, 3) | |
7709 | TRANS_FEAT(SQDMLSLBT, aa64_sve2, gen_gvec_ool_arg_zzzz, | |
7710 | sqdmlsl_zzzw_fns[a->esz], a, 2) | |
7711 | ||
7712 | static gen_helper_gvec_4 * const sqrdmlah_fns[] = { | |
7713 | gen_helper_sve2_sqrdmlah_b, gen_helper_sve2_sqrdmlah_h, | |
7714 | gen_helper_sve2_sqrdmlah_s, gen_helper_sve2_sqrdmlah_d, | |
7715 | }; | |
7716 | TRANS_FEAT(SQRDMLAH_zzzz, aa64_sve2, gen_gvec_ool_arg_zzzz, | |
7717 | sqrdmlah_fns[a->esz], a, 0) | |
45a32e80 | 7718 | |
eeb4e84d RH |
7719 | static gen_helper_gvec_4 * const sqrdmlsh_fns[] = { |
7720 | gen_helper_sve2_sqrdmlsh_b, gen_helper_sve2_sqrdmlsh_h, | |
7721 | gen_helper_sve2_sqrdmlsh_s, gen_helper_sve2_sqrdmlsh_d, | |
7722 | }; | |
7723 | TRANS_FEAT(SQRDMLSH_zzzz, aa64_sve2, gen_gvec_ool_arg_zzzz, | |
7724 | sqrdmlsh_fns[a->esz], a, 0) | |
45a32e80 | 7725 | |
eeb4e84d RH |
7726 | static gen_helper_gvec_4 * const smlal_zzzw_fns[] = { |
7727 | NULL, gen_helper_sve2_smlal_zzzw_h, | |
7728 | gen_helper_sve2_smlal_zzzw_s, gen_helper_sve2_smlal_zzzw_d, | |
7729 | }; | |
7730 | TRANS_FEAT(SMLALB_zzzw, aa64_sve2, gen_gvec_ool_arg_zzzz, | |
7731 | smlal_zzzw_fns[a->esz], a, 0) | |
7732 | TRANS_FEAT(SMLALT_zzzw, aa64_sve2, gen_gvec_ool_arg_zzzz, | |
7733 | smlal_zzzw_fns[a->esz], a, 1) | |
7734 | ||
7735 | static gen_helper_gvec_4 * const umlal_zzzw_fns[] = { | |
7736 | NULL, gen_helper_sve2_umlal_zzzw_h, | |
7737 | gen_helper_sve2_umlal_zzzw_s, gen_helper_sve2_umlal_zzzw_d, | |
7738 | }; | |
7739 | TRANS_FEAT(UMLALB_zzzw, aa64_sve2, gen_gvec_ool_arg_zzzz, | |
7740 | umlal_zzzw_fns[a->esz], a, 0) | |
7741 | TRANS_FEAT(UMLALT_zzzw, aa64_sve2, gen_gvec_ool_arg_zzzz, | |
7742 | umlal_zzzw_fns[a->esz], a, 1) | |
7743 | ||
7744 | static gen_helper_gvec_4 * const smlsl_zzzw_fns[] = { | |
7745 | NULL, gen_helper_sve2_smlsl_zzzw_h, | |
7746 | gen_helper_sve2_smlsl_zzzw_s, gen_helper_sve2_smlsl_zzzw_d, | |
7747 | }; | |
7748 | TRANS_FEAT(SMLSLB_zzzw, aa64_sve2, gen_gvec_ool_arg_zzzz, | |
7749 | smlsl_zzzw_fns[a->esz], a, 0) | |
7750 | TRANS_FEAT(SMLSLT_zzzw, aa64_sve2, gen_gvec_ool_arg_zzzz, | |
7751 | smlsl_zzzw_fns[a->esz], a, 1) | |
7752 | ||
7753 | static gen_helper_gvec_4 * const umlsl_zzzw_fns[] = { | |
7754 | NULL, gen_helper_sve2_umlsl_zzzw_h, | |
7755 | gen_helper_sve2_umlsl_zzzw_s, gen_helper_sve2_umlsl_zzzw_d, | |
7756 | }; | |
7757 | TRANS_FEAT(UMLSLB_zzzw, aa64_sve2, gen_gvec_ool_arg_zzzz, | |
7758 | umlsl_zzzw_fns[a->esz], a, 0) | |
7759 | TRANS_FEAT(UMLSLT_zzzw, aa64_sve2, gen_gvec_ool_arg_zzzz, | |
7760 | umlsl_zzzw_fns[a->esz], a, 1) | |
d782d3ca | 7761 | |
5f425b92 RH |
7762 | static gen_helper_gvec_4 * const cmla_fns[] = { |
7763 | gen_helper_sve2_cmla_zzzz_b, gen_helper_sve2_cmla_zzzz_h, | |
7764 | gen_helper_sve2_cmla_zzzz_s, gen_helper_sve2_cmla_zzzz_d, | |
7765 | }; | |
7766 | TRANS_FEAT(CMLA_zzzz, aa64_sve2, gen_gvec_ool_zzzz, | |
7767 | cmla_fns[a->esz], a->rd, a->rn, a->rm, a->ra, a->rot) | |
21068f39 | 7768 | |
5f425b92 RH |
7769 | static gen_helper_gvec_4 * const cdot_fns[] = { |
7770 | NULL, NULL, gen_helper_sve2_cdot_zzzz_s, gen_helper_sve2_cdot_zzzz_d | |
7771 | }; | |
7772 | TRANS_FEAT(CDOT_zzzz, aa64_sve2, gen_gvec_ool_zzzz, | |
7773 | cdot_fns[a->esz], a->rd, a->rn, a->rm, a->ra, a->rot) | |
d782d3ca | 7774 | |
5f425b92 RH |
7775 | static gen_helper_gvec_4 * const sqrdcmlah_fns[] = { |
7776 | gen_helper_sve2_sqrdcmlah_zzzz_b, gen_helper_sve2_sqrdcmlah_zzzz_h, | |
7777 | gen_helper_sve2_sqrdcmlah_zzzz_s, gen_helper_sve2_sqrdcmlah_zzzz_d, | |
7778 | }; | |
7779 | TRANS_FEAT(SQRDCMLAH_zzzz, aa64_sve2, gen_gvec_ool_zzzz, | |
7780 | sqrdcmlah_fns[a->esz], a->rd, a->rn, a->rm, a->ra, a->rot) | |
6a98cb2a | 7781 | |
8740d694 RH |
7782 | TRANS_FEAT(USDOT_zzzz, aa64_sve_i8mm, gen_gvec_ool_arg_zzzz, |
7783 | a->esz == 2 ? gen_helper_gvec_usdot_b : NULL, a, 0) | |
b2bcd1be | 7784 | |
0ea3cdbf RH |
7785 | TRANS_FEAT(AESMC, aa64_sve2_aes, gen_gvec_ool_zz, |
7786 | gen_helper_crypto_aesmc, a->rd, a->rd, a->decrypt) | |
3cc7a88e | 7787 | |
32e2ad65 RH |
7788 | TRANS_FEAT(AESE, aa64_sve2_aes, gen_gvec_ool_arg_zzz, |
7789 | gen_helper_crypto_aese, a, false) | |
7790 | TRANS_FEAT(AESD, aa64_sve2_aes, gen_gvec_ool_arg_zzz, | |
7791 | gen_helper_crypto_aese, a, true) | |
3cc7a88e | 7792 | |
32e2ad65 RH |
7793 | TRANS_FEAT(SM4E, aa64_sve2_sm4, gen_gvec_ool_arg_zzz, |
7794 | gen_helper_crypto_sm4e, a, 0) | |
7795 | TRANS_FEAT(SM4EKEY, aa64_sve2_sm4, gen_gvec_ool_arg_zzz, | |
7796 | gen_helper_crypto_sm4ekey, a, 0) | |
3358eb3f | 7797 | |
2aa469ff | 7798 | TRANS_FEAT(RAX1, aa64_sve2_sha3, gen_gvec_fn_arg_zzz, gen_gvec_rax1, a) |
5c1b7226 RH |
7799 | |
7800 | static bool trans_FCVTNT_sh(DisasContext *s, arg_rpr_esz *a) | |
7801 | { | |
7802 | if (!dc_isar_feature(aa64_sve2, s)) { | |
7803 | return false; | |
7804 | } | |
7805 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve2_fcvtnt_sh); | |
7806 | } | |
7807 | ||
d29b17ca RH |
7808 | static bool trans_BFCVTNT(DisasContext *s, arg_rpr_esz *a) |
7809 | { | |
7810 | if (!dc_isar_feature(aa64_sve_bf16, s)) { | |
7811 | return false; | |
7812 | } | |
7813 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_bfcvtnt); | |
7814 | } | |
7815 | ||
5c1b7226 RH |
7816 | static bool trans_FCVTNT_ds(DisasContext *s, arg_rpr_esz *a) |
7817 | { | |
7818 | if (!dc_isar_feature(aa64_sve2, s)) { | |
7819 | return false; | |
7820 | } | |
7821 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve2_fcvtnt_ds); | |
7822 | } | |
83c2523f SL |
7823 | |
7824 | static bool trans_FCVTLT_hs(DisasContext *s, arg_rpr_esz *a) | |
7825 | { | |
7826 | if (!dc_isar_feature(aa64_sve2, s)) { | |
7827 | return false; | |
7828 | } | |
7829 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve2_fcvtlt_hs); | |
7830 | } | |
7831 | ||
7832 | static bool trans_FCVTLT_sd(DisasContext *s, arg_rpr_esz *a) | |
7833 | { | |
7834 | if (!dc_isar_feature(aa64_sve2, s)) { | |
7835 | return false; | |
7836 | } | |
7837 | return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve2_fcvtlt_sd); | |
7838 | } | |
95365277 SL |
7839 | |
7840 | static bool trans_FCVTX_ds(DisasContext *s, arg_rpr_esz *a) | |
7841 | { | |
7842 | if (!dc_isar_feature(aa64_sve2, s)) { | |
7843 | return false; | |
7844 | } | |
7845 | return do_frint_mode(s, a, float_round_to_odd, gen_helper_sve_fcvt_ds); | |
7846 | } | |
7847 | ||
7848 | static bool trans_FCVTXNT_ds(DisasContext *s, arg_rpr_esz *a) | |
7849 | { | |
7850 | if (!dc_isar_feature(aa64_sve2, s)) { | |
7851 | return false; | |
7852 | } | |
7853 | return do_frint_mode(s, a, float_round_to_odd, gen_helper_sve2_fcvtnt_ds); | |
7854 | } | |
631be02e SL |
7855 | |
7856 | static bool trans_FLOGB(DisasContext *s, arg_rpr_esz *a) | |
7857 | { | |
7858 | static gen_helper_gvec_3_ptr * const fns[] = { | |
7859 | NULL, gen_helper_flogb_h, | |
7860 | gen_helper_flogb_s, gen_helper_flogb_d | |
7861 | }; | |
7862 | ||
7863 | if (!dc_isar_feature(aa64_sve2, s) || fns[a->esz] == NULL) { | |
7864 | return false; | |
7865 | } | |
7866 | if (sve_access_check(s)) { | |
7867 | TCGv_ptr status = | |
7868 | fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR); | |
7869 | unsigned vsz = vec_full_reg_size(s); | |
7870 | ||
7871 | tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, a->rd), | |
7872 | vec_full_reg_offset(s, a->rn), | |
7873 | pred_full_reg_offset(s, a->pg), | |
7874 | status, vsz, vsz, 0, fns[a->esz]); | |
7875 | tcg_temp_free_ptr(status); | |
7876 | } | |
7877 | return true; | |
7878 | } | |
50d102bd SL |
7879 | |
7880 | static bool do_FMLAL_zzzw(DisasContext *s, arg_rrrr_esz *a, bool sub, bool sel) | |
7881 | { | |
7882 | if (!dc_isar_feature(aa64_sve2, s)) { | |
7883 | return false; | |
7884 | } | |
7885 | if (sve_access_check(s)) { | |
7886 | unsigned vsz = vec_full_reg_size(s); | |
7887 | tcg_gen_gvec_4_ptr(vec_full_reg_offset(s, a->rd), | |
7888 | vec_full_reg_offset(s, a->rn), | |
7889 | vec_full_reg_offset(s, a->rm), | |
7890 | vec_full_reg_offset(s, a->ra), | |
7891 | cpu_env, vsz, vsz, (sel << 1) | sub, | |
7892 | gen_helper_sve2_fmlal_zzzw_s); | |
7893 | } | |
7894 | return true; | |
7895 | } | |
7896 | ||
7897 | static bool trans_FMLALB_zzzw(DisasContext *s, arg_rrrr_esz *a) | |
7898 | { | |
7899 | return do_FMLAL_zzzw(s, a, false, false); | |
7900 | } | |
7901 | ||
7902 | static bool trans_FMLALT_zzzw(DisasContext *s, arg_rrrr_esz *a) | |
7903 | { | |
7904 | return do_FMLAL_zzzw(s, a, false, true); | |
7905 | } | |
7906 | ||
7907 | static bool trans_FMLSLB_zzzw(DisasContext *s, arg_rrrr_esz *a) | |
7908 | { | |
7909 | return do_FMLAL_zzzw(s, a, true, false); | |
7910 | } | |
7911 | ||
7912 | static bool trans_FMLSLT_zzzw(DisasContext *s, arg_rrrr_esz *a) | |
7913 | { | |
7914 | return do_FMLAL_zzzw(s, a, true, true); | |
7915 | } | |
7916 | ||
7917 | static bool do_FMLAL_zzxw(DisasContext *s, arg_rrxr_esz *a, bool sub, bool sel) | |
7918 | { | |
7919 | if (!dc_isar_feature(aa64_sve2, s)) { | |
7920 | return false; | |
7921 | } | |
7922 | if (sve_access_check(s)) { | |
7923 | unsigned vsz = vec_full_reg_size(s); | |
7924 | tcg_gen_gvec_4_ptr(vec_full_reg_offset(s, a->rd), | |
7925 | vec_full_reg_offset(s, a->rn), | |
7926 | vec_full_reg_offset(s, a->rm), | |
7927 | vec_full_reg_offset(s, a->ra), | |
7928 | cpu_env, vsz, vsz, | |
7929 | (a->index << 2) | (sel << 1) | sub, | |
7930 | gen_helper_sve2_fmlal_zzxw_s); | |
7931 | } | |
7932 | return true; | |
7933 | } | |
7934 | ||
7935 | static bool trans_FMLALB_zzxw(DisasContext *s, arg_rrxr_esz *a) | |
7936 | { | |
7937 | return do_FMLAL_zzxw(s, a, false, false); | |
7938 | } | |
7939 | ||
7940 | static bool trans_FMLALT_zzxw(DisasContext *s, arg_rrxr_esz *a) | |
7941 | { | |
7942 | return do_FMLAL_zzxw(s, a, false, true); | |
7943 | } | |
7944 | ||
7945 | static bool trans_FMLSLB_zzxw(DisasContext *s, arg_rrxr_esz *a) | |
7946 | { | |
7947 | return do_FMLAL_zzxw(s, a, true, false); | |
7948 | } | |
7949 | ||
7950 | static bool trans_FMLSLT_zzxw(DisasContext *s, arg_rrxr_esz *a) | |
7951 | { | |
7952 | return do_FMLAL_zzxw(s, a, true, true); | |
7953 | } | |
2323c5ff | 7954 | |
eec05e4e RH |
7955 | TRANS_FEAT(SMMLA, aa64_sve_i8mm, gen_gvec_ool_arg_zzzz, |
7956 | gen_helper_gvec_smmla_b, a, 0) | |
7957 | TRANS_FEAT(USMMLA, aa64_sve_i8mm, gen_gvec_ool_arg_zzzz, | |
7958 | gen_helper_gvec_usmmla_b, a, 0) | |
7959 | TRANS_FEAT(UMMLA, aa64_sve_i8mm, gen_gvec_ool_arg_zzzz, | |
7960 | gen_helper_gvec_ummla_b, a, 0) | |
cb8657f7 | 7961 | |
eec05e4e RH |
7962 | TRANS_FEAT(BFDOT_zzzz, aa64_sve_bf16, gen_gvec_ool_arg_zzzz, |
7963 | gen_helper_gvec_bfdot, a, 0) | |
f3500a25 RH |
7964 | TRANS_FEAT(BFDOT_zzxz, aa64_sve_bf16, gen_gvec_ool_arg_zzxz, |
7965 | gen_helper_gvec_bfdot_idx, a) | |
81266a1f | 7966 | |
eec05e4e RH |
7967 | TRANS_FEAT(BFMMLA, aa64_sve_bf16, gen_gvec_ool_arg_zzzz, |
7968 | gen_helper_gvec_bfmmla, a, 0) | |
5693887f RH |
7969 | |
7970 | static bool do_BFMLAL_zzzw(DisasContext *s, arg_rrrr_esz *a, bool sel) | |
7971 | { | |
7972 | if (!dc_isar_feature(aa64_sve_bf16, s)) { | |
7973 | return false; | |
7974 | } | |
7975 | if (sve_access_check(s)) { | |
7976 | TCGv_ptr status = fpstatus_ptr(FPST_FPCR); | |
7977 | unsigned vsz = vec_full_reg_size(s); | |
7978 | ||
7979 | tcg_gen_gvec_4_ptr(vec_full_reg_offset(s, a->rd), | |
7980 | vec_full_reg_offset(s, a->rn), | |
7981 | vec_full_reg_offset(s, a->rm), | |
7982 | vec_full_reg_offset(s, a->ra), | |
7983 | status, vsz, vsz, sel, | |
7984 | gen_helper_gvec_bfmlal); | |
7985 | tcg_temp_free_ptr(status); | |
7986 | } | |
7987 | return true; | |
7988 | } | |
7989 | ||
7990 | static bool trans_BFMLALB_zzzw(DisasContext *s, arg_rrrr_esz *a) | |
7991 | { | |
7992 | return do_BFMLAL_zzzw(s, a, false); | |
7993 | } | |
7994 | ||
7995 | static bool trans_BFMLALT_zzzw(DisasContext *s, arg_rrrr_esz *a) | |
7996 | { | |
7997 | return do_BFMLAL_zzzw(s, a, true); | |
7998 | } | |
458d0ab6 RH |
7999 | |
8000 | static bool do_BFMLAL_zzxw(DisasContext *s, arg_rrxr_esz *a, bool sel) | |
8001 | { | |
8002 | if (!dc_isar_feature(aa64_sve_bf16, s)) { | |
8003 | return false; | |
8004 | } | |
8005 | if (sve_access_check(s)) { | |
8006 | TCGv_ptr status = fpstatus_ptr(FPST_FPCR); | |
8007 | unsigned vsz = vec_full_reg_size(s); | |
8008 | ||
8009 | tcg_gen_gvec_4_ptr(vec_full_reg_offset(s, a->rd), | |
8010 | vec_full_reg_offset(s, a->rn), | |
8011 | vec_full_reg_offset(s, a->rm), | |
8012 | vec_full_reg_offset(s, a->ra), | |
8013 | status, vsz, vsz, (a->index << 1) | sel, | |
8014 | gen_helper_gvec_bfmlal_idx); | |
8015 | tcg_temp_free_ptr(status); | |
8016 | } | |
8017 | return true; | |
8018 | } | |
8019 | ||
8020 | static bool trans_BFMLALB_zzxw(DisasContext *s, arg_rrxr_esz *a) | |
8021 | { | |
8022 | return do_BFMLAL_zzxw(s, a, false); | |
8023 | } | |
8024 | ||
8025 | static bool trans_BFMLALT_zzxw(DisasContext *s, arg_rrxr_esz *a) | |
8026 | { | |
8027 | return do_BFMLAL_zzxw(s, a, true); | |
8028 | } |