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37356079 RH |
1 | /* |
2 | * ARM VFP floating-point operations | |
3 | * | |
4 | * Copyright (c) 2003 Fabrice Bellard | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2.1 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #include "qemu/osdep.h" | |
37356079 RH |
21 | #include "cpu.h" |
22 | #include "exec/helper-proto.h" | |
37356079 | 23 | #include "internals.h" |
5a534314 | 24 | #include "cpu-features.h" |
4a15527c PMD |
25 | #ifdef CONFIG_TCG |
26 | #include "qemu/log.h" | |
27 | #include "fpu/softfloat.h" | |
28 | #endif | |
37356079 RH |
29 | |
30 | /* VFP support. We follow the convention used for VFP instructions: | |
31 | Single precision routines have a "s" suffix, double precision a | |
32 | "d" suffix. */ | |
33 | ||
4a15527c PMD |
34 | #ifdef CONFIG_TCG |
35 | ||
37356079 RH |
36 | /* Convert host exception flags to vfp form. */ |
37 | static inline int vfp_exceptbits_from_host(int host_bits) | |
38 | { | |
39 | int target_bits = 0; | |
40 | ||
9798ac71 | 41 | if (host_bits & float_flag_invalid) { |
37356079 | 42 | target_bits |= 1; |
9798ac71 PMD |
43 | } |
44 | if (host_bits & float_flag_divbyzero) { | |
37356079 | 45 | target_bits |= 2; |
9798ac71 PMD |
46 | } |
47 | if (host_bits & float_flag_overflow) { | |
37356079 | 48 | target_bits |= 4; |
9798ac71 PMD |
49 | } |
50 | if (host_bits & (float_flag_underflow | float_flag_output_denormal)) { | |
37356079 | 51 | target_bits |= 8; |
9798ac71 PMD |
52 | } |
53 | if (host_bits & float_flag_inexact) { | |
37356079 | 54 | target_bits |= 0x10; |
9798ac71 PMD |
55 | } |
56 | if (host_bits & float_flag_input_denormal) { | |
37356079 | 57 | target_bits |= 0x80; |
9798ac71 | 58 | } |
37356079 RH |
59 | return target_bits; |
60 | } | |
61 | ||
37356079 RH |
62 | /* Convert vfp exception flags to target form. */ |
63 | static inline int vfp_exceptbits_to_host(int target_bits) | |
64 | { | |
65 | int host_bits = 0; | |
66 | ||
9798ac71 | 67 | if (target_bits & 1) { |
37356079 | 68 | host_bits |= float_flag_invalid; |
9798ac71 PMD |
69 | } |
70 | if (target_bits & 2) { | |
37356079 | 71 | host_bits |= float_flag_divbyzero; |
9798ac71 PMD |
72 | } |
73 | if (target_bits & 4) { | |
37356079 | 74 | host_bits |= float_flag_overflow; |
9798ac71 PMD |
75 | } |
76 | if (target_bits & 8) { | |
37356079 | 77 | host_bits |= float_flag_underflow; |
9798ac71 PMD |
78 | } |
79 | if (target_bits & 0x10) { | |
37356079 | 80 | host_bits |= float_flag_inexact; |
9798ac71 PMD |
81 | } |
82 | if (target_bits & 0x80) { | |
37356079 | 83 | host_bits |= float_flag_input_denormal; |
9798ac71 | 84 | } |
37356079 RH |
85 | return host_bits; |
86 | } | |
87 | ||
0c6ad948 PMD |
88 | static uint32_t vfp_get_fpscr_from_host(CPUARMState *env) |
89 | { | |
90 | uint32_t i; | |
91 | ||
92 | i = get_float_exception_flags(&env->vfp.fp_status); | |
93 | i |= get_float_exception_flags(&env->vfp.standard_fp_status); | |
94 | /* FZ16 does not generate an input denormal exception. */ | |
95 | i |= (get_float_exception_flags(&env->vfp.fp_status_f16) | |
96 | & ~float_flag_input_denormal); | |
aaae563b PM |
97 | i |= (get_float_exception_flags(&env->vfp.standard_fp_status_f16) |
98 | & ~float_flag_input_denormal); | |
0c6ad948 PMD |
99 | return vfp_exceptbits_from_host(i); |
100 | } | |
101 | ||
e9d65282 PMD |
102 | static void vfp_set_fpscr_to_host(CPUARMState *env, uint32_t val) |
103 | { | |
104 | int i; | |
105 | uint32_t changed = env->vfp.xregs[ARM_VFP_FPSCR]; | |
106 | ||
107 | changed ^= val; | |
108 | if (changed & (3 << 22)) { | |
109 | i = (val >> 22) & 3; | |
110 | switch (i) { | |
111 | case FPROUNDING_TIEEVEN: | |
112 | i = float_round_nearest_even; | |
113 | break; | |
114 | case FPROUNDING_POSINF: | |
115 | i = float_round_up; | |
116 | break; | |
117 | case FPROUNDING_NEGINF: | |
118 | i = float_round_down; | |
119 | break; | |
120 | case FPROUNDING_ZERO: | |
121 | i = float_round_to_zero; | |
122 | break; | |
123 | } | |
124 | set_float_rounding_mode(i, &env->vfp.fp_status); | |
125 | set_float_rounding_mode(i, &env->vfp.fp_status_f16); | |
126 | } | |
127 | if (changed & FPCR_FZ16) { | |
128 | bool ftz_enabled = val & FPCR_FZ16; | |
129 | set_flush_to_zero(ftz_enabled, &env->vfp.fp_status_f16); | |
aaae563b | 130 | set_flush_to_zero(ftz_enabled, &env->vfp.standard_fp_status_f16); |
e9d65282 | 131 | set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status_f16); |
aaae563b | 132 | set_flush_inputs_to_zero(ftz_enabled, &env->vfp.standard_fp_status_f16); |
e9d65282 PMD |
133 | } |
134 | if (changed & FPCR_FZ) { | |
135 | bool ftz_enabled = val & FPCR_FZ; | |
136 | set_flush_to_zero(ftz_enabled, &env->vfp.fp_status); | |
137 | set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status); | |
138 | } | |
139 | if (changed & FPCR_DN) { | |
140 | bool dnan_enabled = val & FPCR_DN; | |
141 | set_default_nan_mode(dnan_enabled, &env->vfp.fp_status); | |
142 | set_default_nan_mode(dnan_enabled, &env->vfp.fp_status_f16); | |
143 | } | |
144 | ||
145 | /* | |
146 | * The exception flags are ORed together when we read fpscr so we | |
147 | * only need to preserve the current state in one of our | |
148 | * float_status values. | |
149 | */ | |
150 | i = vfp_exceptbits_to_host(val); | |
151 | set_float_exception_flags(i, &env->vfp.fp_status); | |
152 | set_float_exception_flags(0, &env->vfp.fp_status_f16); | |
153 | set_float_exception_flags(0, &env->vfp.standard_fp_status); | |
aaae563b | 154 | set_float_exception_flags(0, &env->vfp.standard_fp_status_f16); |
e9d65282 PMD |
155 | } |
156 | ||
4a15527c PMD |
157 | #else |
158 | ||
159 | static uint32_t vfp_get_fpscr_from_host(CPUARMState *env) | |
160 | { | |
161 | return 0; | |
162 | } | |
163 | ||
164 | static void vfp_set_fpscr_to_host(CPUARMState *env, uint32_t val) | |
165 | { | |
166 | } | |
167 | ||
168 | #endif | |
169 | ||
20e62dd8 PMD |
170 | uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env) |
171 | { | |
172 | uint32_t i, fpscr; | |
173 | ||
174 | fpscr = env->vfp.xregs[ARM_VFP_FPSCR] | |
175 | | (env->vfp.vec_len << 16) | |
176 | | (env->vfp.vec_stride << 20); | |
177 | ||
8128c8e8 PM |
178 | /* |
179 | * M-profile LTPSIZE overlaps A-profile Stride; whichever of the | |
180 | * two is not applicable to this CPU will always be zero. | |
181 | */ | |
182 | fpscr |= env->v7m.ltpsize << 16; | |
183 | ||
0c6ad948 | 184 | fpscr |= vfp_get_fpscr_from_host(env); |
20e62dd8 PMD |
185 | |
186 | i = env->vfp.qc[0] | env->vfp.qc[1] | env->vfp.qc[2] | env->vfp.qc[3]; | |
187 | fpscr |= i ? FPCR_QC : 0; | |
188 | ||
189 | return fpscr; | |
190 | } | |
191 | ||
192 | uint32_t vfp_get_fpscr(CPUARMState *env) | |
193 | { | |
194 | return HELPER(vfp_get_fpscr)(env); | |
195 | } | |
196 | ||
37356079 RH |
197 | void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val) |
198 | { | |
b26b5629 PM |
199 | ARMCPU *cpu = env_archcpu(env); |
200 | ||
37356079 | 201 | /* When ARMv8.2-FP16 is not supported, FZ16 is RES0. */ |
b26b5629 | 202 | if (!cpu_isar_feature(any_fp16, cpu)) { |
37356079 RH |
203 | val &= ~FPCR_FZ16; |
204 | } | |
205 | ||
d31e2ce6 PM |
206 | vfp_set_fpscr_to_host(env, val); |
207 | ||
208 | if (!arm_feature(env, ARM_FEATURE_M)) { | |
5bcf8ed9 | 209 | /* |
d31e2ce6 PM |
210 | * Short-vector length and stride; on M-profile these bits |
211 | * are used for different purposes. | |
212 | * We can't make this conditional be "if MVFR0.FPShVec != 0", | |
213 | * because in v7A no-short-vector-support cores still had to | |
214 | * allow Stride/Len to be written with the only effect that | |
215 | * some insns are required to UNDEF if the guest sets them. | |
5bcf8ed9 | 216 | */ |
d31e2ce6 PM |
217 | env->vfp.vec_len = extract32(val, 16, 3); |
218 | env->vfp.vec_stride = extract32(val, 20, 2); | |
b26b5629 PM |
219 | } else if (cpu_isar_feature(aa32_mve, cpu)) { |
220 | env->v7m.ltpsize = extract32(val, FPCR_LTPSIZE_SHIFT, | |
221 | FPCR_LTPSIZE_LENGTH); | |
5bcf8ed9 PM |
222 | } |
223 | ||
c485ce2c PM |
224 | if (arm_feature(env, ARM_FEATURE_NEON) || |
225 | cpu_isar_feature(aa32_mve, cpu)) { | |
d31e2ce6 PM |
226 | /* |
227 | * The bit we set within fpscr_q is arbitrary; the register as a | |
228 | * whole being zero/non-zero is what counts. | |
229 | * TODO: M-profile MVE also has a QC bit. | |
230 | */ | |
231 | env->vfp.qc[0] = val & FPCR_QC; | |
232 | env->vfp.qc[1] = 0; | |
233 | env->vfp.qc[2] = 0; | |
234 | env->vfp.qc[3] = 0; | |
235 | } | |
85795187 | 236 | |
37356079 RH |
237 | /* |
238 | * We don't implement trapped exception handling, so the | |
239 | * trap enable bits, IDE|IXE|UFE|OFE|DZE|IOE are all RAZ/WI (not RES0!) | |
240 | * | |
d31e2ce6 PM |
241 | * The exception flags IOC|DZC|OFC|UFC|IXC|IDC are stored in |
242 | * fp_status; QC, Len and Stride are stored separately earlier. | |
243 | * Clear out all of those and the RES0 bits: only NZCV, AHP, DN, | |
244 | * FZ, RMode and FZ16 are kept in vfp.xregs[FPSCR]. | |
37356079 RH |
245 | */ |
246 | env->vfp.xregs[ARM_VFP_FPSCR] = val & 0xf7c80000; | |
37356079 RH |
247 | } |
248 | ||
249 | void vfp_set_fpscr(CPUARMState *env, uint32_t val) | |
250 | { | |
251 | HELPER(vfp_set_fpscr)(env, val); | |
252 | } | |
253 | ||
4a15527c PMD |
254 | #ifdef CONFIG_TCG |
255 | ||
37356079 RH |
256 | #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p)) |
257 | ||
258 | #define VFP_BINOP(name) \ | |
120a0eb3 PM |
259 | dh_ctype_f16 VFP_HELPER(name, h)(dh_ctype_f16 a, dh_ctype_f16 b, void *fpstp) \ |
260 | { \ | |
261 | float_status *fpst = fpstp; \ | |
262 | return float16_ ## name(a, b, fpst); \ | |
263 | } \ | |
37356079 RH |
264 | float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \ |
265 | { \ | |
266 | float_status *fpst = fpstp; \ | |
267 | return float32_ ## name(a, b, fpst); \ | |
268 | } \ | |
269 | float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \ | |
270 | { \ | |
271 | float_status *fpst = fpstp; \ | |
272 | return float64_ ## name(a, b, fpst); \ | |
273 | } | |
274 | VFP_BINOP(add) | |
275 | VFP_BINOP(sub) | |
276 | VFP_BINOP(mul) | |
277 | VFP_BINOP(div) | |
278 | VFP_BINOP(min) | |
279 | VFP_BINOP(max) | |
280 | VFP_BINOP(minnum) | |
281 | VFP_BINOP(maxnum) | |
282 | #undef VFP_BINOP | |
283 | ||
e7cb0ded PM |
284 | dh_ctype_f16 VFP_HELPER(neg, h)(dh_ctype_f16 a) |
285 | { | |
286 | return float16_chs(a); | |
287 | } | |
288 | ||
37356079 RH |
289 | float32 VFP_HELPER(neg, s)(float32 a) |
290 | { | |
291 | return float32_chs(a); | |
292 | } | |
293 | ||
294 | float64 VFP_HELPER(neg, d)(float64 a) | |
295 | { | |
296 | return float64_chs(a); | |
297 | } | |
298 | ||
ce2d65a5 PM |
299 | dh_ctype_f16 VFP_HELPER(abs, h)(dh_ctype_f16 a) |
300 | { | |
301 | return float16_abs(a); | |
302 | } | |
303 | ||
37356079 RH |
304 | float32 VFP_HELPER(abs, s)(float32 a) |
305 | { | |
306 | return float32_abs(a); | |
307 | } | |
308 | ||
309 | float64 VFP_HELPER(abs, d)(float64 a) | |
310 | { | |
311 | return float64_abs(a); | |
312 | } | |
313 | ||
ce2d65a5 PM |
314 | dh_ctype_f16 VFP_HELPER(sqrt, h)(dh_ctype_f16 a, CPUARMState *env) |
315 | { | |
316 | return float16_sqrt(a, &env->vfp.fp_status_f16); | |
317 | } | |
318 | ||
37356079 RH |
319 | float32 VFP_HELPER(sqrt, s)(float32 a, CPUARMState *env) |
320 | { | |
321 | return float32_sqrt(a, &env->vfp.fp_status); | |
322 | } | |
323 | ||
324 | float64 VFP_HELPER(sqrt, d)(float64 a, CPUARMState *env) | |
325 | { | |
326 | return float64_sqrt(a, &env->vfp.fp_status); | |
327 | } | |
328 | ||
71bfd65c | 329 | static void softfloat_to_vfp_compare(CPUARMState *env, FloatRelation cmp) |
37356079 RH |
330 | { |
331 | uint32_t flags; | |
332 | switch (cmp) { | |
333 | case float_relation_equal: | |
334 | flags = 0x6; | |
335 | break; | |
336 | case float_relation_less: | |
337 | flags = 0x8; | |
338 | break; | |
339 | case float_relation_greater: | |
340 | flags = 0x2; | |
341 | break; | |
342 | case float_relation_unordered: | |
343 | flags = 0x3; | |
344 | break; | |
345 | default: | |
346 | g_assert_not_reached(); | |
347 | } | |
348 | env->vfp.xregs[ARM_VFP_FPSCR] = | |
349 | deposit32(env->vfp.xregs[ARM_VFP_FPSCR], 28, 4, flags); | |
350 | } | |
351 | ||
352 | /* XXX: check quiet/signaling case */ | |
1b88b054 PM |
353 | #define DO_VFP_cmp(P, FLOATTYPE, ARGTYPE, FPST) \ |
354 | void VFP_HELPER(cmp, P)(ARGTYPE a, ARGTYPE b, CPUARMState *env) \ | |
37356079 RH |
355 | { \ |
356 | softfloat_to_vfp_compare(env, \ | |
1b88b054 | 357 | FLOATTYPE ## _compare_quiet(a, b, &env->vfp.FPST)); \ |
37356079 | 358 | } \ |
1b88b054 | 359 | void VFP_HELPER(cmpe, P)(ARGTYPE a, ARGTYPE b, CPUARMState *env) \ |
37356079 RH |
360 | { \ |
361 | softfloat_to_vfp_compare(env, \ | |
1b88b054 | 362 | FLOATTYPE ## _compare(a, b, &env->vfp.FPST)); \ |
37356079 | 363 | } |
1b88b054 PM |
364 | DO_VFP_cmp(h, float16, dh_ctype_f16, fp_status_f16) |
365 | DO_VFP_cmp(s, float32, float32, fp_status) | |
366 | DO_VFP_cmp(d, float64, float64, fp_status) | |
37356079 RH |
367 | #undef DO_VFP_cmp |
368 | ||
369 | /* Integer to float and float to integer conversions */ | |
370 | ||
371 | #define CONV_ITOF(name, ftype, fsz, sign) \ | |
372 | ftype HELPER(name)(uint32_t x, void *fpstp) \ | |
373 | { \ | |
374 | float_status *fpst = fpstp; \ | |
375 | return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \ | |
376 | } | |
377 | ||
378 | #define CONV_FTOI(name, ftype, fsz, sign, round) \ | |
379 | sign##int32_t HELPER(name)(ftype x, void *fpstp) \ | |
380 | { \ | |
381 | float_status *fpst = fpstp; \ | |
382 | if (float##fsz##_is_any_nan(x)) { \ | |
383 | float_raise(float_flag_invalid, fpst); \ | |
384 | return 0; \ | |
385 | } \ | |
386 | return float##fsz##_to_##sign##int32##round(x, fpst); \ | |
387 | } | |
388 | ||
389 | #define FLOAT_CONVS(name, p, ftype, fsz, sign) \ | |
390 | CONV_ITOF(vfp_##name##to##p, ftype, fsz, sign) \ | |
391 | CONV_FTOI(vfp_to##name##p, ftype, fsz, sign, ) \ | |
392 | CONV_FTOI(vfp_to##name##z##p, ftype, fsz, sign, _round_to_zero) | |
393 | ||
394 | FLOAT_CONVS(si, h, uint32_t, 16, ) | |
395 | FLOAT_CONVS(si, s, float32, 32, ) | |
396 | FLOAT_CONVS(si, d, float64, 64, ) | |
397 | FLOAT_CONVS(ui, h, uint32_t, 16, u) | |
398 | FLOAT_CONVS(ui, s, float32, 32, u) | |
399 | FLOAT_CONVS(ui, d, float64, 64, u) | |
400 | ||
401 | #undef CONV_ITOF | |
402 | #undef CONV_FTOI | |
403 | #undef FLOAT_CONVS | |
404 | ||
405 | /* floating point conversion */ | |
406 | float64 VFP_HELPER(fcvtd, s)(float32 x, CPUARMState *env) | |
407 | { | |
408 | return float32_to_float64(x, &env->vfp.fp_status); | |
409 | } | |
410 | ||
411 | float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env) | |
412 | { | |
413 | return float64_to_float32(x, &env->vfp.fp_status); | |
414 | } | |
415 | ||
3a98ac40 RH |
416 | uint32_t HELPER(bfcvt)(float32 x, void *status) |
417 | { | |
418 | return float32_to_bfloat16(x, status); | |
419 | } | |
420 | ||
d29b17ca RH |
421 | uint32_t HELPER(bfcvt_pair)(uint64_t pair, void *status) |
422 | { | |
423 | bfloat16 lo = float32_to_bfloat16(extract64(pair, 0, 32), status); | |
424 | bfloat16 hi = float32_to_bfloat16(extract64(pair, 32, 32), status); | |
425 | return deposit32(lo, 16, 16, hi); | |
426 | } | |
427 | ||
61db12d9 PM |
428 | /* |
429 | * VFP3 fixed point conversion. The AArch32 versions of fix-to-float | |
430 | * must always round-to-nearest; the AArch64 ones honour the FPSCR | |
431 | * rounding mode. (For AArch32 Neon the standard-FPSCR is set to | |
432 | * round-to-nearest so either helper will work.) AArch32 float-to-fix | |
433 | * must round-to-zero. | |
434 | */ | |
5366f6ad PM |
435 | #define VFP_CONV_FIX_FLOAT(name, p, fsz, ftype, isz, itype) \ |
436 | ftype HELPER(vfp_##name##to##p)(uint##isz##_t x, uint32_t shift, \ | |
37356079 RH |
437 | void *fpstp) \ |
438 | { return itype##_to_##float##fsz##_scalbn(x, -shift, fpstp); } | |
439 | ||
61db12d9 PM |
440 | #define VFP_CONV_FIX_FLOAT_ROUND(name, p, fsz, ftype, isz, itype) \ |
441 | ftype HELPER(vfp_##name##to##p##_round_to_nearest)(uint##isz##_t x, \ | |
442 | uint32_t shift, \ | |
443 | void *fpstp) \ | |
444 | { \ | |
445 | ftype ret; \ | |
446 | float_status *fpst = fpstp; \ | |
447 | FloatRoundMode oldmode = fpst->float_rounding_mode; \ | |
448 | fpst->float_rounding_mode = float_round_nearest_even; \ | |
449 | ret = itype##_to_##float##fsz##_scalbn(x, -shift, fpstp); \ | |
450 | fpst->float_rounding_mode = oldmode; \ | |
451 | return ret; \ | |
452 | } | |
453 | ||
5366f6ad PM |
454 | #define VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, ftype, isz, itype, ROUND, suff) \ |
455 | uint##isz##_t HELPER(vfp_to##name##p##suff)(ftype x, uint32_t shift, \ | |
37356079 RH |
456 | void *fpst) \ |
457 | { \ | |
458 | if (unlikely(float##fsz##_is_any_nan(x))) { \ | |
459 | float_raise(float_flag_invalid, fpst); \ | |
460 | return 0; \ | |
461 | } \ | |
462 | return float##fsz##_to_##itype##_scalbn(x, ROUND, shift, fpst); \ | |
463 | } | |
464 | ||
5366f6ad PM |
465 | #define VFP_CONV_FIX(name, p, fsz, ftype, isz, itype) \ |
466 | VFP_CONV_FIX_FLOAT(name, p, fsz, ftype, isz, itype) \ | |
61db12d9 | 467 | VFP_CONV_FIX_FLOAT_ROUND(name, p, fsz, ftype, isz, itype) \ |
5366f6ad | 468 | VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, ftype, isz, itype, \ |
37356079 | 469 | float_round_to_zero, _round_to_zero) \ |
5366f6ad | 470 | VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, ftype, isz, itype, \ |
37356079 RH |
471 | get_float_rounding_mode(fpst), ) |
472 | ||
5366f6ad PM |
473 | #define VFP_CONV_FIX_A64(name, p, fsz, ftype, isz, itype) \ |
474 | VFP_CONV_FIX_FLOAT(name, p, fsz, ftype, isz, itype) \ | |
475 | VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, ftype, isz, itype, \ | |
37356079 RH |
476 | get_float_rounding_mode(fpst), ) |
477 | ||
5366f6ad PM |
478 | VFP_CONV_FIX(sh, d, 64, float64, 64, int16) |
479 | VFP_CONV_FIX(sl, d, 64, float64, 64, int32) | |
480 | VFP_CONV_FIX_A64(sq, d, 64, float64, 64, int64) | |
481 | VFP_CONV_FIX(uh, d, 64, float64, 64, uint16) | |
482 | VFP_CONV_FIX(ul, d, 64, float64, 64, uint32) | |
483 | VFP_CONV_FIX_A64(uq, d, 64, float64, 64, uint64) | |
484 | VFP_CONV_FIX(sh, s, 32, float32, 32, int16) | |
485 | VFP_CONV_FIX(sl, s, 32, float32, 32, int32) | |
486 | VFP_CONV_FIX_A64(sq, s, 32, float32, 64, int64) | |
487 | VFP_CONV_FIX(uh, s, 32, float32, 32, uint16) | |
488 | VFP_CONV_FIX(ul, s, 32, float32, 32, uint32) | |
489 | VFP_CONV_FIX_A64(uq, s, 32, float32, 64, uint64) | |
414ba270 PM |
490 | VFP_CONV_FIX(sh, h, 16, dh_ctype_f16, 32, int16) |
491 | VFP_CONV_FIX(sl, h, 16, dh_ctype_f16, 32, int32) | |
492 | VFP_CONV_FIX_A64(sq, h, 16, dh_ctype_f16, 64, int64) | |
493 | VFP_CONV_FIX(uh, h, 16, dh_ctype_f16, 32, uint16) | |
494 | VFP_CONV_FIX(ul, h, 16, dh_ctype_f16, 32, uint32) | |
495 | VFP_CONV_FIX_A64(uq, h, 16, dh_ctype_f16, 64, uint64) | |
37356079 RH |
496 | |
497 | #undef VFP_CONV_FIX | |
498 | #undef VFP_CONV_FIX_FLOAT | |
499 | #undef VFP_CONV_FLOAT_FIX_ROUND | |
500 | #undef VFP_CONV_FIX_A64 | |
501 | ||
37356079 RH |
502 | /* Set the current fp rounding mode and return the old one. |
503 | * The argument is a softfloat float_round_ value. | |
504 | */ | |
505 | uint32_t HELPER(set_rmode)(uint32_t rmode, void *fpstp) | |
506 | { | |
507 | float_status *fp_status = fpstp; | |
508 | ||
509 | uint32_t prev_rmode = get_float_rounding_mode(fp_status); | |
510 | set_float_rounding_mode(rmode, fp_status); | |
511 | ||
512 | return prev_rmode; | |
513 | } | |
514 | ||
37356079 RH |
515 | /* Half precision conversions. */ |
516 | float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, void *fpstp, uint32_t ahp_mode) | |
517 | { | |
518 | /* Squash FZ16 to 0 for the duration of conversion. In this case, | |
519 | * it would affect flushing input denormals. | |
520 | */ | |
521 | float_status *fpst = fpstp; | |
c120391c | 522 | bool save = get_flush_inputs_to_zero(fpst); |
37356079 RH |
523 | set_flush_inputs_to_zero(false, fpst); |
524 | float32 r = float16_to_float32(a, !ahp_mode, fpst); | |
525 | set_flush_inputs_to_zero(save, fpst); | |
526 | return r; | |
527 | } | |
528 | ||
529 | uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, void *fpstp, uint32_t ahp_mode) | |
530 | { | |
531 | /* Squash FZ16 to 0 for the duration of conversion. In this case, | |
532 | * it would affect flushing output denormals. | |
533 | */ | |
534 | float_status *fpst = fpstp; | |
c120391c | 535 | bool save = get_flush_to_zero(fpst); |
37356079 RH |
536 | set_flush_to_zero(false, fpst); |
537 | float16 r = float32_to_float16(a, !ahp_mode, fpst); | |
538 | set_flush_to_zero(save, fpst); | |
539 | return r; | |
540 | } | |
541 | ||
542 | float64 HELPER(vfp_fcvt_f16_to_f64)(uint32_t a, void *fpstp, uint32_t ahp_mode) | |
543 | { | |
544 | /* Squash FZ16 to 0 for the duration of conversion. In this case, | |
545 | * it would affect flushing input denormals. | |
546 | */ | |
547 | float_status *fpst = fpstp; | |
c120391c | 548 | bool save = get_flush_inputs_to_zero(fpst); |
37356079 RH |
549 | set_flush_inputs_to_zero(false, fpst); |
550 | float64 r = float16_to_float64(a, !ahp_mode, fpst); | |
551 | set_flush_inputs_to_zero(save, fpst); | |
552 | return r; | |
553 | } | |
554 | ||
555 | uint32_t HELPER(vfp_fcvt_f64_to_f16)(float64 a, void *fpstp, uint32_t ahp_mode) | |
556 | { | |
557 | /* Squash FZ16 to 0 for the duration of conversion. In this case, | |
558 | * it would affect flushing output denormals. | |
559 | */ | |
560 | float_status *fpst = fpstp; | |
c120391c | 561 | bool save = get_flush_to_zero(fpst); |
37356079 RH |
562 | set_flush_to_zero(false, fpst); |
563 | float16 r = float64_to_float16(a, !ahp_mode, fpst); | |
564 | set_flush_to_zero(save, fpst); | |
565 | return r; | |
566 | } | |
567 | ||
37356079 RH |
568 | /* NEON helpers. */ |
569 | ||
570 | /* Constants 256 and 512 are used in some helpers; we avoid relying on | |
571 | * int->float conversions at run-time. */ | |
572 | #define float64_256 make_float64(0x4070000000000000LL) | |
573 | #define float64_512 make_float64(0x4080000000000000LL) | |
574 | #define float16_maxnorm make_float16(0x7bff) | |
575 | #define float32_maxnorm make_float32(0x7f7fffff) | |
576 | #define float64_maxnorm make_float64(0x7fefffffffffffffLL) | |
577 | ||
578 | /* Reciprocal functions | |
579 | * | |
580 | * The algorithm that must be used to calculate the estimate | |
581 | * is specified by the ARM ARM, see FPRecipEstimate()/RecipEstimate | |
582 | */ | |
583 | ||
584 | /* See RecipEstimate() | |
585 | * | |
586 | * input is a 9 bit fixed point number | |
587 | * input range 256 .. 511 for a number from 0.5 <= x < 1.0. | |
588 | * result range 256 .. 511 for a number from 1.0 to 511/256. | |
589 | */ | |
590 | ||
591 | static int recip_estimate(int input) | |
592 | { | |
593 | int a, b, r; | |
594 | assert(256 <= input && input < 512); | |
595 | a = (input * 2) + 1; | |
596 | b = (1 << 19) / a; | |
597 | r = (b + 1) >> 1; | |
598 | assert(256 <= r && r < 512); | |
599 | return r; | |
600 | } | |
601 | ||
602 | /* | |
603 | * Common wrapper to call recip_estimate | |
604 | * | |
605 | * The parameters are exponent and 64 bit fraction (without implicit | |
606 | * bit) where the binary point is nominally at bit 52. Returns a | |
607 | * float64 which can then be rounded to the appropriate size by the | |
608 | * callee. | |
609 | */ | |
610 | ||
611 | static uint64_t call_recip_estimate(int *exp, int exp_off, uint64_t frac) | |
612 | { | |
613 | uint32_t scaled, estimate; | |
614 | uint64_t result_frac; | |
615 | int result_exp; | |
616 | ||
617 | /* Handle sub-normals */ | |
618 | if (*exp == 0) { | |
619 | if (extract64(frac, 51, 1) == 0) { | |
620 | *exp = -1; | |
621 | frac <<= 2; | |
622 | } else { | |
623 | frac <<= 1; | |
624 | } | |
625 | } | |
626 | ||
627 | /* scaled = UInt('1':fraction<51:44>) */ | |
628 | scaled = deposit32(1 << 8, 0, 8, extract64(frac, 44, 8)); | |
629 | estimate = recip_estimate(scaled); | |
630 | ||
631 | result_exp = exp_off - *exp; | |
632 | result_frac = deposit64(0, 44, 8, estimate); | |
633 | if (result_exp == 0) { | |
634 | result_frac = deposit64(result_frac >> 1, 51, 1, 1); | |
635 | } else if (result_exp == -1) { | |
636 | result_frac = deposit64(result_frac >> 2, 50, 2, 1); | |
637 | result_exp = 0; | |
638 | } | |
639 | ||
640 | *exp = result_exp; | |
641 | ||
642 | return result_frac; | |
643 | } | |
644 | ||
645 | static bool round_to_inf(float_status *fpst, bool sign_bit) | |
646 | { | |
647 | switch (fpst->float_rounding_mode) { | |
648 | case float_round_nearest_even: /* Round to Nearest */ | |
649 | return true; | |
650 | case float_round_up: /* Round to +Inf */ | |
651 | return !sign_bit; | |
652 | case float_round_down: /* Round to -Inf */ | |
653 | return sign_bit; | |
654 | case float_round_to_zero: /* Round to Zero */ | |
655 | return false; | |
3dede407 RH |
656 | default: |
657 | g_assert_not_reached(); | |
37356079 | 658 | } |
37356079 RH |
659 | } |
660 | ||
661 | uint32_t HELPER(recpe_f16)(uint32_t input, void *fpstp) | |
662 | { | |
663 | float_status *fpst = fpstp; | |
664 | float16 f16 = float16_squash_input_denormal(input, fpst); | |
665 | uint32_t f16_val = float16_val(f16); | |
666 | uint32_t f16_sign = float16_is_neg(f16); | |
667 | int f16_exp = extract32(f16_val, 10, 5); | |
668 | uint32_t f16_frac = extract32(f16_val, 0, 10); | |
669 | uint64_t f64_frac; | |
670 | ||
671 | if (float16_is_any_nan(f16)) { | |
672 | float16 nan = f16; | |
673 | if (float16_is_signaling_nan(f16, fpst)) { | |
674 | float_raise(float_flag_invalid, fpst); | |
103e7579 JK |
675 | if (!fpst->default_nan_mode) { |
676 | nan = float16_silence_nan(f16, fpst); | |
677 | } | |
37356079 RH |
678 | } |
679 | if (fpst->default_nan_mode) { | |
680 | nan = float16_default_nan(fpst); | |
681 | } | |
682 | return nan; | |
683 | } else if (float16_is_infinity(f16)) { | |
684 | return float16_set_sign(float16_zero, float16_is_neg(f16)); | |
685 | } else if (float16_is_zero(f16)) { | |
686 | float_raise(float_flag_divbyzero, fpst); | |
687 | return float16_set_sign(float16_infinity, float16_is_neg(f16)); | |
688 | } else if (float16_abs(f16) < (1 << 8)) { | |
689 | /* Abs(value) < 2.0^-16 */ | |
690 | float_raise(float_flag_overflow | float_flag_inexact, fpst); | |
691 | if (round_to_inf(fpst, f16_sign)) { | |
692 | return float16_set_sign(float16_infinity, f16_sign); | |
693 | } else { | |
694 | return float16_set_sign(float16_maxnorm, f16_sign); | |
695 | } | |
696 | } else if (f16_exp >= 29 && fpst->flush_to_zero) { | |
697 | float_raise(float_flag_underflow, fpst); | |
698 | return float16_set_sign(float16_zero, float16_is_neg(f16)); | |
699 | } | |
700 | ||
701 | f64_frac = call_recip_estimate(&f16_exp, 29, | |
702 | ((uint64_t) f16_frac) << (52 - 10)); | |
703 | ||
704 | /* result = sign : result_exp<4:0> : fraction<51:42> */ | |
705 | f16_val = deposit32(0, 15, 1, f16_sign); | |
706 | f16_val = deposit32(f16_val, 10, 5, f16_exp); | |
707 | f16_val = deposit32(f16_val, 0, 10, extract64(f64_frac, 52 - 10, 10)); | |
708 | return make_float16(f16_val); | |
709 | } | |
710 | ||
711 | float32 HELPER(recpe_f32)(float32 input, void *fpstp) | |
712 | { | |
713 | float_status *fpst = fpstp; | |
714 | float32 f32 = float32_squash_input_denormal(input, fpst); | |
715 | uint32_t f32_val = float32_val(f32); | |
716 | bool f32_sign = float32_is_neg(f32); | |
717 | int f32_exp = extract32(f32_val, 23, 8); | |
718 | uint32_t f32_frac = extract32(f32_val, 0, 23); | |
719 | uint64_t f64_frac; | |
720 | ||
721 | if (float32_is_any_nan(f32)) { | |
722 | float32 nan = f32; | |
723 | if (float32_is_signaling_nan(f32, fpst)) { | |
724 | float_raise(float_flag_invalid, fpst); | |
103e7579 JK |
725 | if (!fpst->default_nan_mode) { |
726 | nan = float32_silence_nan(f32, fpst); | |
727 | } | |
37356079 RH |
728 | } |
729 | if (fpst->default_nan_mode) { | |
730 | nan = float32_default_nan(fpst); | |
731 | } | |
732 | return nan; | |
733 | } else if (float32_is_infinity(f32)) { | |
734 | return float32_set_sign(float32_zero, float32_is_neg(f32)); | |
735 | } else if (float32_is_zero(f32)) { | |
736 | float_raise(float_flag_divbyzero, fpst); | |
737 | return float32_set_sign(float32_infinity, float32_is_neg(f32)); | |
738 | } else if (float32_abs(f32) < (1ULL << 21)) { | |
739 | /* Abs(value) < 2.0^-128 */ | |
740 | float_raise(float_flag_overflow | float_flag_inexact, fpst); | |
741 | if (round_to_inf(fpst, f32_sign)) { | |
742 | return float32_set_sign(float32_infinity, f32_sign); | |
743 | } else { | |
744 | return float32_set_sign(float32_maxnorm, f32_sign); | |
745 | } | |
746 | } else if (f32_exp >= 253 && fpst->flush_to_zero) { | |
747 | float_raise(float_flag_underflow, fpst); | |
748 | return float32_set_sign(float32_zero, float32_is_neg(f32)); | |
749 | } | |
750 | ||
751 | f64_frac = call_recip_estimate(&f32_exp, 253, | |
752 | ((uint64_t) f32_frac) << (52 - 23)); | |
753 | ||
754 | /* result = sign : result_exp<7:0> : fraction<51:29> */ | |
755 | f32_val = deposit32(0, 31, 1, f32_sign); | |
756 | f32_val = deposit32(f32_val, 23, 8, f32_exp); | |
757 | f32_val = deposit32(f32_val, 0, 23, extract64(f64_frac, 52 - 23, 23)); | |
758 | return make_float32(f32_val); | |
759 | } | |
760 | ||
761 | float64 HELPER(recpe_f64)(float64 input, void *fpstp) | |
762 | { | |
763 | float_status *fpst = fpstp; | |
764 | float64 f64 = float64_squash_input_denormal(input, fpst); | |
765 | uint64_t f64_val = float64_val(f64); | |
766 | bool f64_sign = float64_is_neg(f64); | |
767 | int f64_exp = extract64(f64_val, 52, 11); | |
768 | uint64_t f64_frac = extract64(f64_val, 0, 52); | |
769 | ||
770 | /* Deal with any special cases */ | |
771 | if (float64_is_any_nan(f64)) { | |
772 | float64 nan = f64; | |
773 | if (float64_is_signaling_nan(f64, fpst)) { | |
774 | float_raise(float_flag_invalid, fpst); | |
103e7579 JK |
775 | if (!fpst->default_nan_mode) { |
776 | nan = float64_silence_nan(f64, fpst); | |
777 | } | |
37356079 RH |
778 | } |
779 | if (fpst->default_nan_mode) { | |
780 | nan = float64_default_nan(fpst); | |
781 | } | |
782 | return nan; | |
783 | } else if (float64_is_infinity(f64)) { | |
784 | return float64_set_sign(float64_zero, float64_is_neg(f64)); | |
785 | } else if (float64_is_zero(f64)) { | |
786 | float_raise(float_flag_divbyzero, fpst); | |
787 | return float64_set_sign(float64_infinity, float64_is_neg(f64)); | |
788 | } else if ((f64_val & ~(1ULL << 63)) < (1ULL << 50)) { | |
789 | /* Abs(value) < 2.0^-1024 */ | |
790 | float_raise(float_flag_overflow | float_flag_inexact, fpst); | |
791 | if (round_to_inf(fpst, f64_sign)) { | |
792 | return float64_set_sign(float64_infinity, f64_sign); | |
793 | } else { | |
794 | return float64_set_sign(float64_maxnorm, f64_sign); | |
795 | } | |
796 | } else if (f64_exp >= 2045 && fpst->flush_to_zero) { | |
797 | float_raise(float_flag_underflow, fpst); | |
798 | return float64_set_sign(float64_zero, float64_is_neg(f64)); | |
799 | } | |
800 | ||
801 | f64_frac = call_recip_estimate(&f64_exp, 2045, f64_frac); | |
802 | ||
803 | /* result = sign : result_exp<10:0> : fraction<51:0>; */ | |
804 | f64_val = deposit64(0, 63, 1, f64_sign); | |
805 | f64_val = deposit64(f64_val, 52, 11, f64_exp); | |
806 | f64_val = deposit64(f64_val, 0, 52, f64_frac); | |
807 | return make_float64(f64_val); | |
808 | } | |
809 | ||
810 | /* The algorithm that must be used to calculate the estimate | |
811 | * is specified by the ARM ARM. | |
812 | */ | |
813 | ||
814 | static int do_recip_sqrt_estimate(int a) | |
815 | { | |
816 | int b, estimate; | |
817 | ||
818 | assert(128 <= a && a < 512); | |
819 | if (a < 256) { | |
820 | a = a * 2 + 1; | |
821 | } else { | |
822 | a = (a >> 1) << 1; | |
823 | a = (a + 1) * 2; | |
824 | } | |
825 | b = 512; | |
826 | while (a * (b + 1) * (b + 1) < (1 << 28)) { | |
827 | b += 1; | |
828 | } | |
829 | estimate = (b + 1) / 2; | |
830 | assert(256 <= estimate && estimate < 512); | |
831 | ||
832 | return estimate; | |
833 | } | |
834 | ||
835 | ||
836 | static uint64_t recip_sqrt_estimate(int *exp , int exp_off, uint64_t frac) | |
837 | { | |
838 | int estimate; | |
839 | uint32_t scaled; | |
840 | ||
841 | if (*exp == 0) { | |
842 | while (extract64(frac, 51, 1) == 0) { | |
843 | frac = frac << 1; | |
844 | *exp -= 1; | |
845 | } | |
846 | frac = extract64(frac, 0, 51) << 1; | |
847 | } | |
848 | ||
849 | if (*exp & 1) { | |
850 | /* scaled = UInt('01':fraction<51:45>) */ | |
851 | scaled = deposit32(1 << 7, 0, 7, extract64(frac, 45, 7)); | |
852 | } else { | |
853 | /* scaled = UInt('1':fraction<51:44>) */ | |
854 | scaled = deposit32(1 << 8, 0, 8, extract64(frac, 44, 8)); | |
855 | } | |
856 | estimate = do_recip_sqrt_estimate(scaled); | |
857 | ||
858 | *exp = (exp_off - *exp) / 2; | |
859 | return extract64(estimate, 0, 8) << 44; | |
860 | } | |
861 | ||
862 | uint32_t HELPER(rsqrte_f16)(uint32_t input, void *fpstp) | |
863 | { | |
864 | float_status *s = fpstp; | |
865 | float16 f16 = float16_squash_input_denormal(input, s); | |
866 | uint16_t val = float16_val(f16); | |
867 | bool f16_sign = float16_is_neg(f16); | |
868 | int f16_exp = extract32(val, 10, 5); | |
869 | uint16_t f16_frac = extract32(val, 0, 10); | |
870 | uint64_t f64_frac; | |
871 | ||
872 | if (float16_is_any_nan(f16)) { | |
873 | float16 nan = f16; | |
874 | if (float16_is_signaling_nan(f16, s)) { | |
875 | float_raise(float_flag_invalid, s); | |
103e7579 JK |
876 | if (!s->default_nan_mode) { |
877 | nan = float16_silence_nan(f16, fpstp); | |
878 | } | |
37356079 RH |
879 | } |
880 | if (s->default_nan_mode) { | |
881 | nan = float16_default_nan(s); | |
882 | } | |
883 | return nan; | |
884 | } else if (float16_is_zero(f16)) { | |
885 | float_raise(float_flag_divbyzero, s); | |
886 | return float16_set_sign(float16_infinity, f16_sign); | |
887 | } else if (f16_sign) { | |
888 | float_raise(float_flag_invalid, s); | |
889 | return float16_default_nan(s); | |
890 | } else if (float16_is_infinity(f16)) { | |
891 | return float16_zero; | |
892 | } | |
893 | ||
894 | /* Scale and normalize to a double-precision value between 0.25 and 1.0, | |
895 | * preserving the parity of the exponent. */ | |
896 | ||
897 | f64_frac = ((uint64_t) f16_frac) << (52 - 10); | |
898 | ||
899 | f64_frac = recip_sqrt_estimate(&f16_exp, 44, f64_frac); | |
900 | ||
901 | /* result = sign : result_exp<4:0> : estimate<7:0> : Zeros(2) */ | |
902 | val = deposit32(0, 15, 1, f16_sign); | |
903 | val = deposit32(val, 10, 5, f16_exp); | |
904 | val = deposit32(val, 2, 8, extract64(f64_frac, 52 - 8, 8)); | |
905 | return make_float16(val); | |
906 | } | |
907 | ||
908 | float32 HELPER(rsqrte_f32)(float32 input, void *fpstp) | |
909 | { | |
910 | float_status *s = fpstp; | |
911 | float32 f32 = float32_squash_input_denormal(input, s); | |
912 | uint32_t val = float32_val(f32); | |
913 | uint32_t f32_sign = float32_is_neg(f32); | |
914 | int f32_exp = extract32(val, 23, 8); | |
915 | uint32_t f32_frac = extract32(val, 0, 23); | |
916 | uint64_t f64_frac; | |
917 | ||
918 | if (float32_is_any_nan(f32)) { | |
919 | float32 nan = f32; | |
920 | if (float32_is_signaling_nan(f32, s)) { | |
921 | float_raise(float_flag_invalid, s); | |
103e7579 JK |
922 | if (!s->default_nan_mode) { |
923 | nan = float32_silence_nan(f32, fpstp); | |
924 | } | |
37356079 RH |
925 | } |
926 | if (s->default_nan_mode) { | |
927 | nan = float32_default_nan(s); | |
928 | } | |
929 | return nan; | |
930 | } else if (float32_is_zero(f32)) { | |
931 | float_raise(float_flag_divbyzero, s); | |
932 | return float32_set_sign(float32_infinity, float32_is_neg(f32)); | |
933 | } else if (float32_is_neg(f32)) { | |
934 | float_raise(float_flag_invalid, s); | |
935 | return float32_default_nan(s); | |
936 | } else if (float32_is_infinity(f32)) { | |
937 | return float32_zero; | |
938 | } | |
939 | ||
940 | /* Scale and normalize to a double-precision value between 0.25 and 1.0, | |
941 | * preserving the parity of the exponent. */ | |
942 | ||
943 | f64_frac = ((uint64_t) f32_frac) << 29; | |
944 | ||
945 | f64_frac = recip_sqrt_estimate(&f32_exp, 380, f64_frac); | |
946 | ||
947 | /* result = sign : result_exp<4:0> : estimate<7:0> : Zeros(15) */ | |
948 | val = deposit32(0, 31, 1, f32_sign); | |
949 | val = deposit32(val, 23, 8, f32_exp); | |
950 | val = deposit32(val, 15, 8, extract64(f64_frac, 52 - 8, 8)); | |
951 | return make_float32(val); | |
952 | } | |
953 | ||
954 | float64 HELPER(rsqrte_f64)(float64 input, void *fpstp) | |
955 | { | |
956 | float_status *s = fpstp; | |
957 | float64 f64 = float64_squash_input_denormal(input, s); | |
958 | uint64_t val = float64_val(f64); | |
959 | bool f64_sign = float64_is_neg(f64); | |
960 | int f64_exp = extract64(val, 52, 11); | |
961 | uint64_t f64_frac = extract64(val, 0, 52); | |
962 | ||
963 | if (float64_is_any_nan(f64)) { | |
964 | float64 nan = f64; | |
965 | if (float64_is_signaling_nan(f64, s)) { | |
966 | float_raise(float_flag_invalid, s); | |
103e7579 JK |
967 | if (!s->default_nan_mode) { |
968 | nan = float64_silence_nan(f64, fpstp); | |
969 | } | |
37356079 RH |
970 | } |
971 | if (s->default_nan_mode) { | |
972 | nan = float64_default_nan(s); | |
973 | } | |
974 | return nan; | |
975 | } else if (float64_is_zero(f64)) { | |
976 | float_raise(float_flag_divbyzero, s); | |
977 | return float64_set_sign(float64_infinity, float64_is_neg(f64)); | |
978 | } else if (float64_is_neg(f64)) { | |
979 | float_raise(float_flag_invalid, s); | |
980 | return float64_default_nan(s); | |
981 | } else if (float64_is_infinity(f64)) { | |
982 | return float64_zero; | |
983 | } | |
984 | ||
985 | f64_frac = recip_sqrt_estimate(&f64_exp, 3068, f64_frac); | |
986 | ||
987 | /* result = sign : result_exp<4:0> : estimate<7:0> : Zeros(44) */ | |
988 | val = deposit64(0, 61, 1, f64_sign); | |
989 | val = deposit64(val, 52, 11, f64_exp); | |
990 | val = deposit64(val, 44, 8, extract64(f64_frac, 52 - 8, 8)); | |
991 | return make_float64(val); | |
992 | } | |
993 | ||
fe6fb4be | 994 | uint32_t HELPER(recpe_u32)(uint32_t a) |
37356079 | 995 | { |
37356079 RH |
996 | int input, estimate; |
997 | ||
998 | if ((a & 0x80000000) == 0) { | |
999 | return 0xffffffff; | |
1000 | } | |
1001 | ||
1002 | input = extract32(a, 23, 9); | |
1003 | estimate = recip_estimate(input); | |
1004 | ||
1005 | return deposit32(0, (32 - 9), 9, estimate); | |
1006 | } | |
1007 | ||
fe6fb4be | 1008 | uint32_t HELPER(rsqrte_u32)(uint32_t a) |
37356079 RH |
1009 | { |
1010 | int estimate; | |
1011 | ||
1012 | if ((a & 0xc0000000) == 0) { | |
1013 | return 0xffffffff; | |
1014 | } | |
1015 | ||
1016 | estimate = do_recip_sqrt_estimate(extract32(a, 23, 9)); | |
1017 | ||
1018 | return deposit32(0, 23, 9, estimate); | |
1019 | } | |
1020 | ||
1021 | /* VFPv4 fused multiply-accumulate */ | |
9886fe28 PM |
1022 | dh_ctype_f16 VFP_HELPER(muladd, h)(dh_ctype_f16 a, dh_ctype_f16 b, |
1023 | dh_ctype_f16 c, void *fpstp) | |
1024 | { | |
1025 | float_status *fpst = fpstp; | |
1026 | return float16_muladd(a, b, c, 0, fpst); | |
1027 | } | |
1028 | ||
37356079 RH |
1029 | float32 VFP_HELPER(muladd, s)(float32 a, float32 b, float32 c, void *fpstp) |
1030 | { | |
1031 | float_status *fpst = fpstp; | |
1032 | return float32_muladd(a, b, c, 0, fpst); | |
1033 | } | |
1034 | ||
1035 | float64 VFP_HELPER(muladd, d)(float64 a, float64 b, float64 c, void *fpstp) | |
1036 | { | |
1037 | float_status *fpst = fpstp; | |
1038 | return float64_muladd(a, b, c, 0, fpst); | |
1039 | } | |
1040 | ||
1041 | /* ARMv8 round to integral */ | |
0a6f4b4c PM |
1042 | dh_ctype_f16 HELPER(rinth_exact)(dh_ctype_f16 x, void *fp_status) |
1043 | { | |
1044 | return float16_round_to_int(x, fp_status); | |
1045 | } | |
1046 | ||
37356079 RH |
1047 | float32 HELPER(rints_exact)(float32 x, void *fp_status) |
1048 | { | |
1049 | return float32_round_to_int(x, fp_status); | |
1050 | } | |
1051 | ||
1052 | float64 HELPER(rintd_exact)(float64 x, void *fp_status) | |
1053 | { | |
1054 | return float64_round_to_int(x, fp_status); | |
1055 | } | |
1056 | ||
0a6f4b4c PM |
1057 | dh_ctype_f16 HELPER(rinth)(dh_ctype_f16 x, void *fp_status) |
1058 | { | |
1059 | int old_flags = get_float_exception_flags(fp_status), new_flags; | |
1060 | float16 ret; | |
1061 | ||
1062 | ret = float16_round_to_int(x, fp_status); | |
1063 | ||
1064 | /* Suppress any inexact exceptions the conversion produced */ | |
1065 | if (!(old_flags & float_flag_inexact)) { | |
1066 | new_flags = get_float_exception_flags(fp_status); | |
1067 | set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status); | |
1068 | } | |
1069 | ||
1070 | return ret; | |
1071 | } | |
1072 | ||
37356079 RH |
1073 | float32 HELPER(rints)(float32 x, void *fp_status) |
1074 | { | |
1075 | int old_flags = get_float_exception_flags(fp_status), new_flags; | |
1076 | float32 ret; | |
1077 | ||
1078 | ret = float32_round_to_int(x, fp_status); | |
1079 | ||
1080 | /* Suppress any inexact exceptions the conversion produced */ | |
1081 | if (!(old_flags & float_flag_inexact)) { | |
1082 | new_flags = get_float_exception_flags(fp_status); | |
1083 | set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status); | |
1084 | } | |
1085 | ||
1086 | return ret; | |
1087 | } | |
1088 | ||
1089 | float64 HELPER(rintd)(float64 x, void *fp_status) | |
1090 | { | |
1091 | int old_flags = get_float_exception_flags(fp_status), new_flags; | |
1092 | float64 ret; | |
1093 | ||
1094 | ret = float64_round_to_int(x, fp_status); | |
1095 | ||
1096 | new_flags = get_float_exception_flags(fp_status); | |
1097 | ||
1098 | /* Suppress any inexact exceptions the conversion produced */ | |
1099 | if (!(old_flags & float_flag_inexact)) { | |
1100 | new_flags = get_float_exception_flags(fp_status); | |
1101 | set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status); | |
1102 | } | |
1103 | ||
1104 | return ret; | |
1105 | } | |
1106 | ||
1107 | /* Convert ARM rounding mode to softfloat */ | |
6ce21abd RH |
1108 | const FloatRoundMode arm_rmode_to_sf_map[] = { |
1109 | [FPROUNDING_TIEEVEN] = float_round_nearest_even, | |
1110 | [FPROUNDING_POSINF] = float_round_up, | |
1111 | [FPROUNDING_NEGINF] = float_round_down, | |
1112 | [FPROUNDING_ZERO] = float_round_to_zero, | |
1113 | [FPROUNDING_TIEAWAY] = float_round_ties_away, | |
1114 | [FPROUNDING_ODD] = float_round_to_odd, | |
1115 | }; | |
6c1f6f27 RH |
1116 | |
1117 | /* | |
1118 | * Implement float64 to int32_t conversion without saturation; | |
1119 | * the result is supplied modulo 2^32. | |
1120 | */ | |
1121 | uint64_t HELPER(fjcvtzs)(float64 value, void *vstatus) | |
1122 | { | |
1123 | float_status *status = vstatus; | |
34d03ad9 RH |
1124 | uint32_t inexact, frac; |
1125 | uint32_t e_old, e_new; | |
1126 | ||
1127 | e_old = get_float_exception_flags(status); | |
1128 | set_float_exception_flags(0, status); | |
1129 | frac = float64_to_int32_modulo(value, float_round_to_zero, status); | |
1130 | e_new = get_float_exception_flags(status); | |
1131 | set_float_exception_flags(e_old | e_new, status); | |
1132 | ||
1133 | if (value == float64_chs(float64_zero)) { | |
1134 | /* While not inexact for IEEE FP, -0.0 is inexact for JavaScript. */ | |
1135 | inexact = 1; | |
6c1f6f27 | 1136 | } else { |
34d03ad9 RH |
1137 | /* Normal inexact or overflow or NaN */ |
1138 | inexact = e_new & (float_flag_inexact | float_flag_invalid); | |
6c1f6f27 RH |
1139 | } |
1140 | ||
1141 | /* Pack the result and the env->ZF representation of Z together. */ | |
1142 | return deposit64(frac, 32, 32, inexact); | |
1143 | } | |
1144 | ||
1145 | uint32_t HELPER(vjcvt)(float64 value, CPUARMState *env) | |
1146 | { | |
1147 | uint64_t pair = HELPER(fjcvtzs)(value, &env->vfp.fp_status); | |
1148 | uint32_t result = pair; | |
1149 | uint32_t z = (pair >> 32) == 0; | |
1150 | ||
1151 | /* Store Z, clear NCV, in FPSCR.NZCV. */ | |
1152 | env->vfp.xregs[ARM_VFP_FPSCR] | |
1153 | = (env->vfp.xregs[ARM_VFP_FPSCR] & ~CPSR_NZCV) | (z * CPSR_Z); | |
1154 | ||
1155 | return result; | |
1156 | } | |
6bea2563 RH |
1157 | |
1158 | /* Round a float32 to an integer that fits in int32_t or int64_t. */ | |
1159 | static float32 frint_s(float32 f, float_status *fpst, int intsize) | |
1160 | { | |
1161 | int old_flags = get_float_exception_flags(fpst); | |
1162 | uint32_t exp = extract32(f, 23, 8); | |
1163 | ||
1164 | if (unlikely(exp == 0xff)) { | |
1165 | /* NaN or Inf. */ | |
1166 | goto overflow; | |
1167 | } | |
1168 | ||
1169 | /* Round and re-extract the exponent. */ | |
1170 | f = float32_round_to_int(f, fpst); | |
1171 | exp = extract32(f, 23, 8); | |
1172 | ||
1173 | /* Validate the range of the result. */ | |
1174 | if (exp < 126 + intsize) { | |
1175 | /* abs(F) <= INT{N}_MAX */ | |
1176 | return f; | |
1177 | } | |
1178 | if (exp == 126 + intsize) { | |
1179 | uint32_t sign = extract32(f, 31, 1); | |
1180 | uint32_t frac = extract32(f, 0, 23); | |
1181 | if (sign && frac == 0) { | |
1182 | /* F == INT{N}_MIN */ | |
1183 | return f; | |
1184 | } | |
1185 | } | |
1186 | ||
1187 | overflow: | |
1188 | /* | |
1189 | * Raise Invalid and return INT{N}_MIN as a float. Revert any | |
1190 | * inexact exception float32_round_to_int may have raised. | |
1191 | */ | |
1192 | set_float_exception_flags(old_flags | float_flag_invalid, fpst); | |
1193 | return (0x100u + 126u + intsize) << 23; | |
1194 | } | |
1195 | ||
1196 | float32 HELPER(frint32_s)(float32 f, void *fpst) | |
1197 | { | |
1198 | return frint_s(f, fpst, 32); | |
1199 | } | |
1200 | ||
1201 | float32 HELPER(frint64_s)(float32 f, void *fpst) | |
1202 | { | |
1203 | return frint_s(f, fpst, 64); | |
1204 | } | |
1205 | ||
1206 | /* Round a float64 to an integer that fits in int32_t or int64_t. */ | |
1207 | static float64 frint_d(float64 f, float_status *fpst, int intsize) | |
1208 | { | |
1209 | int old_flags = get_float_exception_flags(fpst); | |
1210 | uint32_t exp = extract64(f, 52, 11); | |
1211 | ||
1212 | if (unlikely(exp == 0x7ff)) { | |
1213 | /* NaN or Inf. */ | |
1214 | goto overflow; | |
1215 | } | |
1216 | ||
1217 | /* Round and re-extract the exponent. */ | |
1218 | f = float64_round_to_int(f, fpst); | |
1219 | exp = extract64(f, 52, 11); | |
1220 | ||
1221 | /* Validate the range of the result. */ | |
1222 | if (exp < 1022 + intsize) { | |
1223 | /* abs(F) <= INT{N}_MAX */ | |
1224 | return f; | |
1225 | } | |
1226 | if (exp == 1022 + intsize) { | |
1227 | uint64_t sign = extract64(f, 63, 1); | |
1228 | uint64_t frac = extract64(f, 0, 52); | |
1229 | if (sign && frac == 0) { | |
1230 | /* F == INT{N}_MIN */ | |
1231 | return f; | |
1232 | } | |
1233 | } | |
1234 | ||
1235 | overflow: | |
1236 | /* | |
1237 | * Raise Invalid and return INT{N}_MIN as a float. Revert any | |
1238 | * inexact exception float64_round_to_int may have raised. | |
1239 | */ | |
1240 | set_float_exception_flags(old_flags | float_flag_invalid, fpst); | |
1241 | return (uint64_t)(0x800 + 1022 + intsize) << 52; | |
1242 | } | |
1243 | ||
1244 | float64 HELPER(frint32_d)(float64 f, void *fpst) | |
1245 | { | |
1246 | return frint_d(f, fpst, 32); | |
1247 | } | |
1248 | ||
1249 | float64 HELPER(frint64_d)(float64 f, void *fpst) | |
1250 | { | |
1251 | return frint_d(f, fpst, 64); | |
1252 | } | |
4a15527c | 1253 | |
9ca1d776 MZ |
1254 | void HELPER(check_hcr_el2_trap)(CPUARMState *env, uint32_t rt, uint32_t reg) |
1255 | { | |
1256 | uint32_t syndrome; | |
1257 | ||
1258 | switch (reg) { | |
1259 | case ARM_VFP_MVFR0: | |
1260 | case ARM_VFP_MVFR1: | |
1261 | case ARM_VFP_MVFR2: | |
1262 | if (!(arm_hcr_el2_eff(env) & HCR_TID3)) { | |
1263 | return; | |
1264 | } | |
1265 | break; | |
1266 | case ARM_VFP_FPSID: | |
1267 | if (!(arm_hcr_el2_eff(env) & HCR_TID0)) { | |
1268 | return; | |
1269 | } | |
1270 | break; | |
1271 | default: | |
1272 | g_assert_not_reached(); | |
1273 | } | |
1274 | ||
1275 | syndrome = ((EC_FPIDTRAP << ARM_EL_EC_SHIFT) | |
1276 | | ARM_EL_IL | |
1277 | | (1 << 24) | (0xe << 20) | (7 << 14) | |
1278 | | (reg << 10) | (rt << 5) | 1); | |
1279 | ||
1280 | raise_exception(env, EXCP_HYP_TRAP, syndrome, 2); | |
1281 | } | |
1282 | ||
4a15527c | 1283 | #endif |