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37356079 RH |
1 | /* |
2 | * ARM VFP floating-point operations | |
3 | * | |
4 | * Copyright (c) 2003 Fabrice Bellard | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2.1 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #include "qemu/osdep.h" | |
21 | #include "qemu/log.h" | |
22 | #include "cpu.h" | |
23 | #include "exec/helper-proto.h" | |
24 | #include "fpu/softfloat.h" | |
25 | #include "internals.h" | |
26 | ||
27 | ||
28 | /* VFP support. We follow the convention used for VFP instructions: | |
29 | Single precision routines have a "s" suffix, double precision a | |
30 | "d" suffix. */ | |
31 | ||
32 | /* Convert host exception flags to vfp form. */ | |
33 | static inline int vfp_exceptbits_from_host(int host_bits) | |
34 | { | |
35 | int target_bits = 0; | |
36 | ||
37 | if (host_bits & float_flag_invalid) | |
38 | target_bits |= 1; | |
39 | if (host_bits & float_flag_divbyzero) | |
40 | target_bits |= 2; | |
41 | if (host_bits & float_flag_overflow) | |
42 | target_bits |= 4; | |
43 | if (host_bits & (float_flag_underflow | float_flag_output_denormal)) | |
44 | target_bits |= 8; | |
45 | if (host_bits & float_flag_inexact) | |
46 | target_bits |= 0x10; | |
47 | if (host_bits & float_flag_input_denormal) | |
48 | target_bits |= 0x80; | |
49 | return target_bits; | |
50 | } | |
51 | ||
52 | uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env) | |
53 | { | |
54 | uint32_t i, fpscr; | |
55 | ||
56 | fpscr = env->vfp.xregs[ARM_VFP_FPSCR] | |
57 | | (env->vfp.vec_len << 16) | |
58 | | (env->vfp.vec_stride << 20); | |
59 | ||
60 | i = get_float_exception_flags(&env->vfp.fp_status); | |
61 | i |= get_float_exception_flags(&env->vfp.standard_fp_status); | |
62 | /* FZ16 does not generate an input denormal exception. */ | |
63 | i |= (get_float_exception_flags(&env->vfp.fp_status_f16) | |
64 | & ~float_flag_input_denormal); | |
65 | fpscr |= vfp_exceptbits_from_host(i); | |
66 | ||
67 | i = env->vfp.qc[0] | env->vfp.qc[1] | env->vfp.qc[2] | env->vfp.qc[3]; | |
68 | fpscr |= i ? FPCR_QC : 0; | |
69 | ||
70 | return fpscr; | |
71 | } | |
72 | ||
73 | uint32_t vfp_get_fpscr(CPUARMState *env) | |
74 | { | |
75 | return HELPER(vfp_get_fpscr)(env); | |
76 | } | |
77 | ||
78 | /* Convert vfp exception flags to target form. */ | |
79 | static inline int vfp_exceptbits_to_host(int target_bits) | |
80 | { | |
81 | int host_bits = 0; | |
82 | ||
83 | if (target_bits & 1) | |
84 | host_bits |= float_flag_invalid; | |
85 | if (target_bits & 2) | |
86 | host_bits |= float_flag_divbyzero; | |
87 | if (target_bits & 4) | |
88 | host_bits |= float_flag_overflow; | |
89 | if (target_bits & 8) | |
90 | host_bits |= float_flag_underflow; | |
91 | if (target_bits & 0x10) | |
92 | host_bits |= float_flag_inexact; | |
93 | if (target_bits & 0x80) | |
94 | host_bits |= float_flag_input_denormal; | |
95 | return host_bits; | |
96 | } | |
97 | ||
98 | void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val) | |
99 | { | |
100 | int i; | |
101 | uint32_t changed = env->vfp.xregs[ARM_VFP_FPSCR]; | |
102 | ||
103 | /* When ARMv8.2-FP16 is not supported, FZ16 is RES0. */ | |
104 | if (!cpu_isar_feature(aa64_fp16, arm_env_get_cpu(env))) { | |
105 | val &= ~FPCR_FZ16; | |
106 | } | |
107 | ||
108 | /* | |
109 | * We don't implement trapped exception handling, so the | |
110 | * trap enable bits, IDE|IXE|UFE|OFE|DZE|IOE are all RAZ/WI (not RES0!) | |
111 | * | |
112 | * If we exclude the exception flags, IOC|DZC|OFC|UFC|IXC|IDC | |
113 | * (which are stored in fp_status), and the other RES0 bits | |
114 | * in between, then we clear all of the low 16 bits. | |
115 | */ | |
116 | env->vfp.xregs[ARM_VFP_FPSCR] = val & 0xf7c80000; | |
117 | env->vfp.vec_len = (val >> 16) & 7; | |
118 | env->vfp.vec_stride = (val >> 20) & 3; | |
119 | ||
120 | /* | |
121 | * The bit we set within fpscr_q is arbitrary; the register as a | |
122 | * whole being zero/non-zero is what counts. | |
123 | */ | |
124 | env->vfp.qc[0] = val & FPCR_QC; | |
125 | env->vfp.qc[1] = 0; | |
126 | env->vfp.qc[2] = 0; | |
127 | env->vfp.qc[3] = 0; | |
128 | ||
129 | changed ^= val; | |
130 | if (changed & (3 << 22)) { | |
131 | i = (val >> 22) & 3; | |
132 | switch (i) { | |
133 | case FPROUNDING_TIEEVEN: | |
134 | i = float_round_nearest_even; | |
135 | break; | |
136 | case FPROUNDING_POSINF: | |
137 | i = float_round_up; | |
138 | break; | |
139 | case FPROUNDING_NEGINF: | |
140 | i = float_round_down; | |
141 | break; | |
142 | case FPROUNDING_ZERO: | |
143 | i = float_round_to_zero; | |
144 | break; | |
145 | } | |
146 | set_float_rounding_mode(i, &env->vfp.fp_status); | |
147 | set_float_rounding_mode(i, &env->vfp.fp_status_f16); | |
148 | } | |
149 | if (changed & FPCR_FZ16) { | |
150 | bool ftz_enabled = val & FPCR_FZ16; | |
151 | set_flush_to_zero(ftz_enabled, &env->vfp.fp_status_f16); | |
152 | set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status_f16); | |
153 | } | |
154 | if (changed & FPCR_FZ) { | |
155 | bool ftz_enabled = val & FPCR_FZ; | |
156 | set_flush_to_zero(ftz_enabled, &env->vfp.fp_status); | |
157 | set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status); | |
158 | } | |
159 | if (changed & FPCR_DN) { | |
160 | bool dnan_enabled = val & FPCR_DN; | |
161 | set_default_nan_mode(dnan_enabled, &env->vfp.fp_status); | |
162 | set_default_nan_mode(dnan_enabled, &env->vfp.fp_status_f16); | |
163 | } | |
164 | ||
165 | /* The exception flags are ORed together when we read fpscr so we | |
166 | * only need to preserve the current state in one of our | |
167 | * float_status values. | |
168 | */ | |
169 | i = vfp_exceptbits_to_host(val); | |
170 | set_float_exception_flags(i, &env->vfp.fp_status); | |
171 | set_float_exception_flags(0, &env->vfp.fp_status_f16); | |
172 | set_float_exception_flags(0, &env->vfp.standard_fp_status); | |
173 | } | |
174 | ||
175 | void vfp_set_fpscr(CPUARMState *env, uint32_t val) | |
176 | { | |
177 | HELPER(vfp_set_fpscr)(env, val); | |
178 | } | |
179 | ||
180 | #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p)) | |
181 | ||
182 | #define VFP_BINOP(name) \ | |
183 | float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \ | |
184 | { \ | |
185 | float_status *fpst = fpstp; \ | |
186 | return float32_ ## name(a, b, fpst); \ | |
187 | } \ | |
188 | float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \ | |
189 | { \ | |
190 | float_status *fpst = fpstp; \ | |
191 | return float64_ ## name(a, b, fpst); \ | |
192 | } | |
193 | VFP_BINOP(add) | |
194 | VFP_BINOP(sub) | |
195 | VFP_BINOP(mul) | |
196 | VFP_BINOP(div) | |
197 | VFP_BINOP(min) | |
198 | VFP_BINOP(max) | |
199 | VFP_BINOP(minnum) | |
200 | VFP_BINOP(maxnum) | |
201 | #undef VFP_BINOP | |
202 | ||
203 | float32 VFP_HELPER(neg, s)(float32 a) | |
204 | { | |
205 | return float32_chs(a); | |
206 | } | |
207 | ||
208 | float64 VFP_HELPER(neg, d)(float64 a) | |
209 | { | |
210 | return float64_chs(a); | |
211 | } | |
212 | ||
213 | float32 VFP_HELPER(abs, s)(float32 a) | |
214 | { | |
215 | return float32_abs(a); | |
216 | } | |
217 | ||
218 | float64 VFP_HELPER(abs, d)(float64 a) | |
219 | { | |
220 | return float64_abs(a); | |
221 | } | |
222 | ||
223 | float32 VFP_HELPER(sqrt, s)(float32 a, CPUARMState *env) | |
224 | { | |
225 | return float32_sqrt(a, &env->vfp.fp_status); | |
226 | } | |
227 | ||
228 | float64 VFP_HELPER(sqrt, d)(float64 a, CPUARMState *env) | |
229 | { | |
230 | return float64_sqrt(a, &env->vfp.fp_status); | |
231 | } | |
232 | ||
233 | static void softfloat_to_vfp_compare(CPUARMState *env, int cmp) | |
234 | { | |
235 | uint32_t flags; | |
236 | switch (cmp) { | |
237 | case float_relation_equal: | |
238 | flags = 0x6; | |
239 | break; | |
240 | case float_relation_less: | |
241 | flags = 0x8; | |
242 | break; | |
243 | case float_relation_greater: | |
244 | flags = 0x2; | |
245 | break; | |
246 | case float_relation_unordered: | |
247 | flags = 0x3; | |
248 | break; | |
249 | default: | |
250 | g_assert_not_reached(); | |
251 | } | |
252 | env->vfp.xregs[ARM_VFP_FPSCR] = | |
253 | deposit32(env->vfp.xregs[ARM_VFP_FPSCR], 28, 4, flags); | |
254 | } | |
255 | ||
256 | /* XXX: check quiet/signaling case */ | |
257 | #define DO_VFP_cmp(p, type) \ | |
258 | void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env) \ | |
259 | { \ | |
260 | softfloat_to_vfp_compare(env, \ | |
261 | type ## _compare_quiet(a, b, &env->vfp.fp_status)); \ | |
262 | } \ | |
263 | void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \ | |
264 | { \ | |
265 | softfloat_to_vfp_compare(env, \ | |
266 | type ## _compare(a, b, &env->vfp.fp_status)); \ | |
267 | } | |
268 | DO_VFP_cmp(s, float32) | |
269 | DO_VFP_cmp(d, float64) | |
270 | #undef DO_VFP_cmp | |
271 | ||
272 | /* Integer to float and float to integer conversions */ | |
273 | ||
274 | #define CONV_ITOF(name, ftype, fsz, sign) \ | |
275 | ftype HELPER(name)(uint32_t x, void *fpstp) \ | |
276 | { \ | |
277 | float_status *fpst = fpstp; \ | |
278 | return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \ | |
279 | } | |
280 | ||
281 | #define CONV_FTOI(name, ftype, fsz, sign, round) \ | |
282 | sign##int32_t HELPER(name)(ftype x, void *fpstp) \ | |
283 | { \ | |
284 | float_status *fpst = fpstp; \ | |
285 | if (float##fsz##_is_any_nan(x)) { \ | |
286 | float_raise(float_flag_invalid, fpst); \ | |
287 | return 0; \ | |
288 | } \ | |
289 | return float##fsz##_to_##sign##int32##round(x, fpst); \ | |
290 | } | |
291 | ||
292 | #define FLOAT_CONVS(name, p, ftype, fsz, sign) \ | |
293 | CONV_ITOF(vfp_##name##to##p, ftype, fsz, sign) \ | |
294 | CONV_FTOI(vfp_to##name##p, ftype, fsz, sign, ) \ | |
295 | CONV_FTOI(vfp_to##name##z##p, ftype, fsz, sign, _round_to_zero) | |
296 | ||
297 | FLOAT_CONVS(si, h, uint32_t, 16, ) | |
298 | FLOAT_CONVS(si, s, float32, 32, ) | |
299 | FLOAT_CONVS(si, d, float64, 64, ) | |
300 | FLOAT_CONVS(ui, h, uint32_t, 16, u) | |
301 | FLOAT_CONVS(ui, s, float32, 32, u) | |
302 | FLOAT_CONVS(ui, d, float64, 64, u) | |
303 | ||
304 | #undef CONV_ITOF | |
305 | #undef CONV_FTOI | |
306 | #undef FLOAT_CONVS | |
307 | ||
308 | /* floating point conversion */ | |
309 | float64 VFP_HELPER(fcvtd, s)(float32 x, CPUARMState *env) | |
310 | { | |
311 | return float32_to_float64(x, &env->vfp.fp_status); | |
312 | } | |
313 | ||
314 | float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env) | |
315 | { | |
316 | return float64_to_float32(x, &env->vfp.fp_status); | |
317 | } | |
318 | ||
319 | /* VFP3 fixed point conversion. */ | |
320 | #define VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \ | |
321 | float##fsz HELPER(vfp_##name##to##p)(uint##isz##_t x, uint32_t shift, \ | |
322 | void *fpstp) \ | |
323 | { return itype##_to_##float##fsz##_scalbn(x, -shift, fpstp); } | |
324 | ||
325 | #define VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, ROUND, suff) \ | |
326 | uint##isz##_t HELPER(vfp_to##name##p##suff)(float##fsz x, uint32_t shift, \ | |
327 | void *fpst) \ | |
328 | { \ | |
329 | if (unlikely(float##fsz##_is_any_nan(x))) { \ | |
330 | float_raise(float_flag_invalid, fpst); \ | |
331 | return 0; \ | |
332 | } \ | |
333 | return float##fsz##_to_##itype##_scalbn(x, ROUND, shift, fpst); \ | |
334 | } | |
335 | ||
336 | #define VFP_CONV_FIX(name, p, fsz, isz, itype) \ | |
337 | VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \ | |
338 | VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, \ | |
339 | float_round_to_zero, _round_to_zero) \ | |
340 | VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, \ | |
341 | get_float_rounding_mode(fpst), ) | |
342 | ||
343 | #define VFP_CONV_FIX_A64(name, p, fsz, isz, itype) \ | |
344 | VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \ | |
345 | VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, \ | |
346 | get_float_rounding_mode(fpst), ) | |
347 | ||
348 | VFP_CONV_FIX(sh, d, 64, 64, int16) | |
349 | VFP_CONV_FIX(sl, d, 64, 64, int32) | |
350 | VFP_CONV_FIX_A64(sq, d, 64, 64, int64) | |
351 | VFP_CONV_FIX(uh, d, 64, 64, uint16) | |
352 | VFP_CONV_FIX(ul, d, 64, 64, uint32) | |
353 | VFP_CONV_FIX_A64(uq, d, 64, 64, uint64) | |
354 | VFP_CONV_FIX(sh, s, 32, 32, int16) | |
355 | VFP_CONV_FIX(sl, s, 32, 32, int32) | |
356 | VFP_CONV_FIX_A64(sq, s, 32, 64, int64) | |
357 | VFP_CONV_FIX(uh, s, 32, 32, uint16) | |
358 | VFP_CONV_FIX(ul, s, 32, 32, uint32) | |
359 | VFP_CONV_FIX_A64(uq, s, 32, 64, uint64) | |
360 | ||
361 | #undef VFP_CONV_FIX | |
362 | #undef VFP_CONV_FIX_FLOAT | |
363 | #undef VFP_CONV_FLOAT_FIX_ROUND | |
364 | #undef VFP_CONV_FIX_A64 | |
365 | ||
366 | uint32_t HELPER(vfp_sltoh)(uint32_t x, uint32_t shift, void *fpst) | |
367 | { | |
368 | return int32_to_float16_scalbn(x, -shift, fpst); | |
369 | } | |
370 | ||
371 | uint32_t HELPER(vfp_ultoh)(uint32_t x, uint32_t shift, void *fpst) | |
372 | { | |
373 | return uint32_to_float16_scalbn(x, -shift, fpst); | |
374 | } | |
375 | ||
376 | uint32_t HELPER(vfp_sqtoh)(uint64_t x, uint32_t shift, void *fpst) | |
377 | { | |
378 | return int64_to_float16_scalbn(x, -shift, fpst); | |
379 | } | |
380 | ||
381 | uint32_t HELPER(vfp_uqtoh)(uint64_t x, uint32_t shift, void *fpst) | |
382 | { | |
383 | return uint64_to_float16_scalbn(x, -shift, fpst); | |
384 | } | |
385 | ||
386 | uint32_t HELPER(vfp_toshh)(uint32_t x, uint32_t shift, void *fpst) | |
387 | { | |
388 | if (unlikely(float16_is_any_nan(x))) { | |
389 | float_raise(float_flag_invalid, fpst); | |
390 | return 0; | |
391 | } | |
392 | return float16_to_int16_scalbn(x, get_float_rounding_mode(fpst), | |
393 | shift, fpst); | |
394 | } | |
395 | ||
396 | uint32_t HELPER(vfp_touhh)(uint32_t x, uint32_t shift, void *fpst) | |
397 | { | |
398 | if (unlikely(float16_is_any_nan(x))) { | |
399 | float_raise(float_flag_invalid, fpst); | |
400 | return 0; | |
401 | } | |
402 | return float16_to_uint16_scalbn(x, get_float_rounding_mode(fpst), | |
403 | shift, fpst); | |
404 | } | |
405 | ||
406 | uint32_t HELPER(vfp_toslh)(uint32_t x, uint32_t shift, void *fpst) | |
407 | { | |
408 | if (unlikely(float16_is_any_nan(x))) { | |
409 | float_raise(float_flag_invalid, fpst); | |
410 | return 0; | |
411 | } | |
412 | return float16_to_int32_scalbn(x, get_float_rounding_mode(fpst), | |
413 | shift, fpst); | |
414 | } | |
415 | ||
416 | uint32_t HELPER(vfp_toulh)(uint32_t x, uint32_t shift, void *fpst) | |
417 | { | |
418 | if (unlikely(float16_is_any_nan(x))) { | |
419 | float_raise(float_flag_invalid, fpst); | |
420 | return 0; | |
421 | } | |
422 | return float16_to_uint32_scalbn(x, get_float_rounding_mode(fpst), | |
423 | shift, fpst); | |
424 | } | |
425 | ||
426 | uint64_t HELPER(vfp_tosqh)(uint32_t x, uint32_t shift, void *fpst) | |
427 | { | |
428 | if (unlikely(float16_is_any_nan(x))) { | |
429 | float_raise(float_flag_invalid, fpst); | |
430 | return 0; | |
431 | } | |
432 | return float16_to_int64_scalbn(x, get_float_rounding_mode(fpst), | |
433 | shift, fpst); | |
434 | } | |
435 | ||
436 | uint64_t HELPER(vfp_touqh)(uint32_t x, uint32_t shift, void *fpst) | |
437 | { | |
438 | if (unlikely(float16_is_any_nan(x))) { | |
439 | float_raise(float_flag_invalid, fpst); | |
440 | return 0; | |
441 | } | |
442 | return float16_to_uint64_scalbn(x, get_float_rounding_mode(fpst), | |
443 | shift, fpst); | |
444 | } | |
445 | ||
446 | /* Set the current fp rounding mode and return the old one. | |
447 | * The argument is a softfloat float_round_ value. | |
448 | */ | |
449 | uint32_t HELPER(set_rmode)(uint32_t rmode, void *fpstp) | |
450 | { | |
451 | float_status *fp_status = fpstp; | |
452 | ||
453 | uint32_t prev_rmode = get_float_rounding_mode(fp_status); | |
454 | set_float_rounding_mode(rmode, fp_status); | |
455 | ||
456 | return prev_rmode; | |
457 | } | |
458 | ||
459 | /* Set the current fp rounding mode in the standard fp status and return | |
460 | * the old one. This is for NEON instructions that need to change the | |
461 | * rounding mode but wish to use the standard FPSCR values for everything | |
462 | * else. Always set the rounding mode back to the correct value after | |
463 | * modifying it. | |
464 | * The argument is a softfloat float_round_ value. | |
465 | */ | |
466 | uint32_t HELPER(set_neon_rmode)(uint32_t rmode, CPUARMState *env) | |
467 | { | |
468 | float_status *fp_status = &env->vfp.standard_fp_status; | |
469 | ||
470 | uint32_t prev_rmode = get_float_rounding_mode(fp_status); | |
471 | set_float_rounding_mode(rmode, fp_status); | |
472 | ||
473 | return prev_rmode; | |
474 | } | |
475 | ||
476 | /* Half precision conversions. */ | |
477 | float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, void *fpstp, uint32_t ahp_mode) | |
478 | { | |
479 | /* Squash FZ16 to 0 for the duration of conversion. In this case, | |
480 | * it would affect flushing input denormals. | |
481 | */ | |
482 | float_status *fpst = fpstp; | |
483 | flag save = get_flush_inputs_to_zero(fpst); | |
484 | set_flush_inputs_to_zero(false, fpst); | |
485 | float32 r = float16_to_float32(a, !ahp_mode, fpst); | |
486 | set_flush_inputs_to_zero(save, fpst); | |
487 | return r; | |
488 | } | |
489 | ||
490 | uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, void *fpstp, uint32_t ahp_mode) | |
491 | { | |
492 | /* Squash FZ16 to 0 for the duration of conversion. In this case, | |
493 | * it would affect flushing output denormals. | |
494 | */ | |
495 | float_status *fpst = fpstp; | |
496 | flag save = get_flush_to_zero(fpst); | |
497 | set_flush_to_zero(false, fpst); | |
498 | float16 r = float32_to_float16(a, !ahp_mode, fpst); | |
499 | set_flush_to_zero(save, fpst); | |
500 | return r; | |
501 | } | |
502 | ||
503 | float64 HELPER(vfp_fcvt_f16_to_f64)(uint32_t a, void *fpstp, uint32_t ahp_mode) | |
504 | { | |
505 | /* Squash FZ16 to 0 for the duration of conversion. In this case, | |
506 | * it would affect flushing input denormals. | |
507 | */ | |
508 | float_status *fpst = fpstp; | |
509 | flag save = get_flush_inputs_to_zero(fpst); | |
510 | set_flush_inputs_to_zero(false, fpst); | |
511 | float64 r = float16_to_float64(a, !ahp_mode, fpst); | |
512 | set_flush_inputs_to_zero(save, fpst); | |
513 | return r; | |
514 | } | |
515 | ||
516 | uint32_t HELPER(vfp_fcvt_f64_to_f16)(float64 a, void *fpstp, uint32_t ahp_mode) | |
517 | { | |
518 | /* Squash FZ16 to 0 for the duration of conversion. In this case, | |
519 | * it would affect flushing output denormals. | |
520 | */ | |
521 | float_status *fpst = fpstp; | |
522 | flag save = get_flush_to_zero(fpst); | |
523 | set_flush_to_zero(false, fpst); | |
524 | float16 r = float64_to_float16(a, !ahp_mode, fpst); | |
525 | set_flush_to_zero(save, fpst); | |
526 | return r; | |
527 | } | |
528 | ||
529 | #define float32_two make_float32(0x40000000) | |
530 | #define float32_three make_float32(0x40400000) | |
531 | #define float32_one_point_five make_float32(0x3fc00000) | |
532 | ||
533 | float32 HELPER(recps_f32)(float32 a, float32 b, CPUARMState *env) | |
534 | { | |
535 | float_status *s = &env->vfp.standard_fp_status; | |
536 | if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) || | |
537 | (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) { | |
538 | if (!(float32_is_zero(a) || float32_is_zero(b))) { | |
539 | float_raise(float_flag_input_denormal, s); | |
540 | } | |
541 | return float32_two; | |
542 | } | |
543 | return float32_sub(float32_two, float32_mul(a, b, s), s); | |
544 | } | |
545 | ||
546 | float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUARMState *env) | |
547 | { | |
548 | float_status *s = &env->vfp.standard_fp_status; | |
549 | float32 product; | |
550 | if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) || | |
551 | (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) { | |
552 | if (!(float32_is_zero(a) || float32_is_zero(b))) { | |
553 | float_raise(float_flag_input_denormal, s); | |
554 | } | |
555 | return float32_one_point_five; | |
556 | } | |
557 | product = float32_mul(a, b, s); | |
558 | return float32_div(float32_sub(float32_three, product, s), float32_two, s); | |
559 | } | |
560 | ||
561 | /* NEON helpers. */ | |
562 | ||
563 | /* Constants 256 and 512 are used in some helpers; we avoid relying on | |
564 | * int->float conversions at run-time. */ | |
565 | #define float64_256 make_float64(0x4070000000000000LL) | |
566 | #define float64_512 make_float64(0x4080000000000000LL) | |
567 | #define float16_maxnorm make_float16(0x7bff) | |
568 | #define float32_maxnorm make_float32(0x7f7fffff) | |
569 | #define float64_maxnorm make_float64(0x7fefffffffffffffLL) | |
570 | ||
571 | /* Reciprocal functions | |
572 | * | |
573 | * The algorithm that must be used to calculate the estimate | |
574 | * is specified by the ARM ARM, see FPRecipEstimate()/RecipEstimate | |
575 | */ | |
576 | ||
577 | /* See RecipEstimate() | |
578 | * | |
579 | * input is a 9 bit fixed point number | |
580 | * input range 256 .. 511 for a number from 0.5 <= x < 1.0. | |
581 | * result range 256 .. 511 for a number from 1.0 to 511/256. | |
582 | */ | |
583 | ||
584 | static int recip_estimate(int input) | |
585 | { | |
586 | int a, b, r; | |
587 | assert(256 <= input && input < 512); | |
588 | a = (input * 2) + 1; | |
589 | b = (1 << 19) / a; | |
590 | r = (b + 1) >> 1; | |
591 | assert(256 <= r && r < 512); | |
592 | return r; | |
593 | } | |
594 | ||
595 | /* | |
596 | * Common wrapper to call recip_estimate | |
597 | * | |
598 | * The parameters are exponent and 64 bit fraction (without implicit | |
599 | * bit) where the binary point is nominally at bit 52. Returns a | |
600 | * float64 which can then be rounded to the appropriate size by the | |
601 | * callee. | |
602 | */ | |
603 | ||
604 | static uint64_t call_recip_estimate(int *exp, int exp_off, uint64_t frac) | |
605 | { | |
606 | uint32_t scaled, estimate; | |
607 | uint64_t result_frac; | |
608 | int result_exp; | |
609 | ||
610 | /* Handle sub-normals */ | |
611 | if (*exp == 0) { | |
612 | if (extract64(frac, 51, 1) == 0) { | |
613 | *exp = -1; | |
614 | frac <<= 2; | |
615 | } else { | |
616 | frac <<= 1; | |
617 | } | |
618 | } | |
619 | ||
620 | /* scaled = UInt('1':fraction<51:44>) */ | |
621 | scaled = deposit32(1 << 8, 0, 8, extract64(frac, 44, 8)); | |
622 | estimate = recip_estimate(scaled); | |
623 | ||
624 | result_exp = exp_off - *exp; | |
625 | result_frac = deposit64(0, 44, 8, estimate); | |
626 | if (result_exp == 0) { | |
627 | result_frac = deposit64(result_frac >> 1, 51, 1, 1); | |
628 | } else if (result_exp == -1) { | |
629 | result_frac = deposit64(result_frac >> 2, 50, 2, 1); | |
630 | result_exp = 0; | |
631 | } | |
632 | ||
633 | *exp = result_exp; | |
634 | ||
635 | return result_frac; | |
636 | } | |
637 | ||
638 | static bool round_to_inf(float_status *fpst, bool sign_bit) | |
639 | { | |
640 | switch (fpst->float_rounding_mode) { | |
641 | case float_round_nearest_even: /* Round to Nearest */ | |
642 | return true; | |
643 | case float_round_up: /* Round to +Inf */ | |
644 | return !sign_bit; | |
645 | case float_round_down: /* Round to -Inf */ | |
646 | return sign_bit; | |
647 | case float_round_to_zero: /* Round to Zero */ | |
648 | return false; | |
649 | } | |
650 | ||
651 | g_assert_not_reached(); | |
652 | } | |
653 | ||
654 | uint32_t HELPER(recpe_f16)(uint32_t input, void *fpstp) | |
655 | { | |
656 | float_status *fpst = fpstp; | |
657 | float16 f16 = float16_squash_input_denormal(input, fpst); | |
658 | uint32_t f16_val = float16_val(f16); | |
659 | uint32_t f16_sign = float16_is_neg(f16); | |
660 | int f16_exp = extract32(f16_val, 10, 5); | |
661 | uint32_t f16_frac = extract32(f16_val, 0, 10); | |
662 | uint64_t f64_frac; | |
663 | ||
664 | if (float16_is_any_nan(f16)) { | |
665 | float16 nan = f16; | |
666 | if (float16_is_signaling_nan(f16, fpst)) { | |
667 | float_raise(float_flag_invalid, fpst); | |
668 | nan = float16_silence_nan(f16, fpst); | |
669 | } | |
670 | if (fpst->default_nan_mode) { | |
671 | nan = float16_default_nan(fpst); | |
672 | } | |
673 | return nan; | |
674 | } else if (float16_is_infinity(f16)) { | |
675 | return float16_set_sign(float16_zero, float16_is_neg(f16)); | |
676 | } else if (float16_is_zero(f16)) { | |
677 | float_raise(float_flag_divbyzero, fpst); | |
678 | return float16_set_sign(float16_infinity, float16_is_neg(f16)); | |
679 | } else if (float16_abs(f16) < (1 << 8)) { | |
680 | /* Abs(value) < 2.0^-16 */ | |
681 | float_raise(float_flag_overflow | float_flag_inexact, fpst); | |
682 | if (round_to_inf(fpst, f16_sign)) { | |
683 | return float16_set_sign(float16_infinity, f16_sign); | |
684 | } else { | |
685 | return float16_set_sign(float16_maxnorm, f16_sign); | |
686 | } | |
687 | } else if (f16_exp >= 29 && fpst->flush_to_zero) { | |
688 | float_raise(float_flag_underflow, fpst); | |
689 | return float16_set_sign(float16_zero, float16_is_neg(f16)); | |
690 | } | |
691 | ||
692 | f64_frac = call_recip_estimate(&f16_exp, 29, | |
693 | ((uint64_t) f16_frac) << (52 - 10)); | |
694 | ||
695 | /* result = sign : result_exp<4:0> : fraction<51:42> */ | |
696 | f16_val = deposit32(0, 15, 1, f16_sign); | |
697 | f16_val = deposit32(f16_val, 10, 5, f16_exp); | |
698 | f16_val = deposit32(f16_val, 0, 10, extract64(f64_frac, 52 - 10, 10)); | |
699 | return make_float16(f16_val); | |
700 | } | |
701 | ||
702 | float32 HELPER(recpe_f32)(float32 input, void *fpstp) | |
703 | { | |
704 | float_status *fpst = fpstp; | |
705 | float32 f32 = float32_squash_input_denormal(input, fpst); | |
706 | uint32_t f32_val = float32_val(f32); | |
707 | bool f32_sign = float32_is_neg(f32); | |
708 | int f32_exp = extract32(f32_val, 23, 8); | |
709 | uint32_t f32_frac = extract32(f32_val, 0, 23); | |
710 | uint64_t f64_frac; | |
711 | ||
712 | if (float32_is_any_nan(f32)) { | |
713 | float32 nan = f32; | |
714 | if (float32_is_signaling_nan(f32, fpst)) { | |
715 | float_raise(float_flag_invalid, fpst); | |
716 | nan = float32_silence_nan(f32, fpst); | |
717 | } | |
718 | if (fpst->default_nan_mode) { | |
719 | nan = float32_default_nan(fpst); | |
720 | } | |
721 | return nan; | |
722 | } else if (float32_is_infinity(f32)) { | |
723 | return float32_set_sign(float32_zero, float32_is_neg(f32)); | |
724 | } else if (float32_is_zero(f32)) { | |
725 | float_raise(float_flag_divbyzero, fpst); | |
726 | return float32_set_sign(float32_infinity, float32_is_neg(f32)); | |
727 | } else if (float32_abs(f32) < (1ULL << 21)) { | |
728 | /* Abs(value) < 2.0^-128 */ | |
729 | float_raise(float_flag_overflow | float_flag_inexact, fpst); | |
730 | if (round_to_inf(fpst, f32_sign)) { | |
731 | return float32_set_sign(float32_infinity, f32_sign); | |
732 | } else { | |
733 | return float32_set_sign(float32_maxnorm, f32_sign); | |
734 | } | |
735 | } else if (f32_exp >= 253 && fpst->flush_to_zero) { | |
736 | float_raise(float_flag_underflow, fpst); | |
737 | return float32_set_sign(float32_zero, float32_is_neg(f32)); | |
738 | } | |
739 | ||
740 | f64_frac = call_recip_estimate(&f32_exp, 253, | |
741 | ((uint64_t) f32_frac) << (52 - 23)); | |
742 | ||
743 | /* result = sign : result_exp<7:0> : fraction<51:29> */ | |
744 | f32_val = deposit32(0, 31, 1, f32_sign); | |
745 | f32_val = deposit32(f32_val, 23, 8, f32_exp); | |
746 | f32_val = deposit32(f32_val, 0, 23, extract64(f64_frac, 52 - 23, 23)); | |
747 | return make_float32(f32_val); | |
748 | } | |
749 | ||
750 | float64 HELPER(recpe_f64)(float64 input, void *fpstp) | |
751 | { | |
752 | float_status *fpst = fpstp; | |
753 | float64 f64 = float64_squash_input_denormal(input, fpst); | |
754 | uint64_t f64_val = float64_val(f64); | |
755 | bool f64_sign = float64_is_neg(f64); | |
756 | int f64_exp = extract64(f64_val, 52, 11); | |
757 | uint64_t f64_frac = extract64(f64_val, 0, 52); | |
758 | ||
759 | /* Deal with any special cases */ | |
760 | if (float64_is_any_nan(f64)) { | |
761 | float64 nan = f64; | |
762 | if (float64_is_signaling_nan(f64, fpst)) { | |
763 | float_raise(float_flag_invalid, fpst); | |
764 | nan = float64_silence_nan(f64, fpst); | |
765 | } | |
766 | if (fpst->default_nan_mode) { | |
767 | nan = float64_default_nan(fpst); | |
768 | } | |
769 | return nan; | |
770 | } else if (float64_is_infinity(f64)) { | |
771 | return float64_set_sign(float64_zero, float64_is_neg(f64)); | |
772 | } else if (float64_is_zero(f64)) { | |
773 | float_raise(float_flag_divbyzero, fpst); | |
774 | return float64_set_sign(float64_infinity, float64_is_neg(f64)); | |
775 | } else if ((f64_val & ~(1ULL << 63)) < (1ULL << 50)) { | |
776 | /* Abs(value) < 2.0^-1024 */ | |
777 | float_raise(float_flag_overflow | float_flag_inexact, fpst); | |
778 | if (round_to_inf(fpst, f64_sign)) { | |
779 | return float64_set_sign(float64_infinity, f64_sign); | |
780 | } else { | |
781 | return float64_set_sign(float64_maxnorm, f64_sign); | |
782 | } | |
783 | } else if (f64_exp >= 2045 && fpst->flush_to_zero) { | |
784 | float_raise(float_flag_underflow, fpst); | |
785 | return float64_set_sign(float64_zero, float64_is_neg(f64)); | |
786 | } | |
787 | ||
788 | f64_frac = call_recip_estimate(&f64_exp, 2045, f64_frac); | |
789 | ||
790 | /* result = sign : result_exp<10:0> : fraction<51:0>; */ | |
791 | f64_val = deposit64(0, 63, 1, f64_sign); | |
792 | f64_val = deposit64(f64_val, 52, 11, f64_exp); | |
793 | f64_val = deposit64(f64_val, 0, 52, f64_frac); | |
794 | return make_float64(f64_val); | |
795 | } | |
796 | ||
797 | /* The algorithm that must be used to calculate the estimate | |
798 | * is specified by the ARM ARM. | |
799 | */ | |
800 | ||
801 | static int do_recip_sqrt_estimate(int a) | |
802 | { | |
803 | int b, estimate; | |
804 | ||
805 | assert(128 <= a && a < 512); | |
806 | if (a < 256) { | |
807 | a = a * 2 + 1; | |
808 | } else { | |
809 | a = (a >> 1) << 1; | |
810 | a = (a + 1) * 2; | |
811 | } | |
812 | b = 512; | |
813 | while (a * (b + 1) * (b + 1) < (1 << 28)) { | |
814 | b += 1; | |
815 | } | |
816 | estimate = (b + 1) / 2; | |
817 | assert(256 <= estimate && estimate < 512); | |
818 | ||
819 | return estimate; | |
820 | } | |
821 | ||
822 | ||
823 | static uint64_t recip_sqrt_estimate(int *exp , int exp_off, uint64_t frac) | |
824 | { | |
825 | int estimate; | |
826 | uint32_t scaled; | |
827 | ||
828 | if (*exp == 0) { | |
829 | while (extract64(frac, 51, 1) == 0) { | |
830 | frac = frac << 1; | |
831 | *exp -= 1; | |
832 | } | |
833 | frac = extract64(frac, 0, 51) << 1; | |
834 | } | |
835 | ||
836 | if (*exp & 1) { | |
837 | /* scaled = UInt('01':fraction<51:45>) */ | |
838 | scaled = deposit32(1 << 7, 0, 7, extract64(frac, 45, 7)); | |
839 | } else { | |
840 | /* scaled = UInt('1':fraction<51:44>) */ | |
841 | scaled = deposit32(1 << 8, 0, 8, extract64(frac, 44, 8)); | |
842 | } | |
843 | estimate = do_recip_sqrt_estimate(scaled); | |
844 | ||
845 | *exp = (exp_off - *exp) / 2; | |
846 | return extract64(estimate, 0, 8) << 44; | |
847 | } | |
848 | ||
849 | uint32_t HELPER(rsqrte_f16)(uint32_t input, void *fpstp) | |
850 | { | |
851 | float_status *s = fpstp; | |
852 | float16 f16 = float16_squash_input_denormal(input, s); | |
853 | uint16_t val = float16_val(f16); | |
854 | bool f16_sign = float16_is_neg(f16); | |
855 | int f16_exp = extract32(val, 10, 5); | |
856 | uint16_t f16_frac = extract32(val, 0, 10); | |
857 | uint64_t f64_frac; | |
858 | ||
859 | if (float16_is_any_nan(f16)) { | |
860 | float16 nan = f16; | |
861 | if (float16_is_signaling_nan(f16, s)) { | |
862 | float_raise(float_flag_invalid, s); | |
863 | nan = float16_silence_nan(f16, s); | |
864 | } | |
865 | if (s->default_nan_mode) { | |
866 | nan = float16_default_nan(s); | |
867 | } | |
868 | return nan; | |
869 | } else if (float16_is_zero(f16)) { | |
870 | float_raise(float_flag_divbyzero, s); | |
871 | return float16_set_sign(float16_infinity, f16_sign); | |
872 | } else if (f16_sign) { | |
873 | float_raise(float_flag_invalid, s); | |
874 | return float16_default_nan(s); | |
875 | } else if (float16_is_infinity(f16)) { | |
876 | return float16_zero; | |
877 | } | |
878 | ||
879 | /* Scale and normalize to a double-precision value between 0.25 and 1.0, | |
880 | * preserving the parity of the exponent. */ | |
881 | ||
882 | f64_frac = ((uint64_t) f16_frac) << (52 - 10); | |
883 | ||
884 | f64_frac = recip_sqrt_estimate(&f16_exp, 44, f64_frac); | |
885 | ||
886 | /* result = sign : result_exp<4:0> : estimate<7:0> : Zeros(2) */ | |
887 | val = deposit32(0, 15, 1, f16_sign); | |
888 | val = deposit32(val, 10, 5, f16_exp); | |
889 | val = deposit32(val, 2, 8, extract64(f64_frac, 52 - 8, 8)); | |
890 | return make_float16(val); | |
891 | } | |
892 | ||
893 | float32 HELPER(rsqrte_f32)(float32 input, void *fpstp) | |
894 | { | |
895 | float_status *s = fpstp; | |
896 | float32 f32 = float32_squash_input_denormal(input, s); | |
897 | uint32_t val = float32_val(f32); | |
898 | uint32_t f32_sign = float32_is_neg(f32); | |
899 | int f32_exp = extract32(val, 23, 8); | |
900 | uint32_t f32_frac = extract32(val, 0, 23); | |
901 | uint64_t f64_frac; | |
902 | ||
903 | if (float32_is_any_nan(f32)) { | |
904 | float32 nan = f32; | |
905 | if (float32_is_signaling_nan(f32, s)) { | |
906 | float_raise(float_flag_invalid, s); | |
907 | nan = float32_silence_nan(f32, s); | |
908 | } | |
909 | if (s->default_nan_mode) { | |
910 | nan = float32_default_nan(s); | |
911 | } | |
912 | return nan; | |
913 | } else if (float32_is_zero(f32)) { | |
914 | float_raise(float_flag_divbyzero, s); | |
915 | return float32_set_sign(float32_infinity, float32_is_neg(f32)); | |
916 | } else if (float32_is_neg(f32)) { | |
917 | float_raise(float_flag_invalid, s); | |
918 | return float32_default_nan(s); | |
919 | } else if (float32_is_infinity(f32)) { | |
920 | return float32_zero; | |
921 | } | |
922 | ||
923 | /* Scale and normalize to a double-precision value between 0.25 and 1.0, | |
924 | * preserving the parity of the exponent. */ | |
925 | ||
926 | f64_frac = ((uint64_t) f32_frac) << 29; | |
927 | ||
928 | f64_frac = recip_sqrt_estimate(&f32_exp, 380, f64_frac); | |
929 | ||
930 | /* result = sign : result_exp<4:0> : estimate<7:0> : Zeros(15) */ | |
931 | val = deposit32(0, 31, 1, f32_sign); | |
932 | val = deposit32(val, 23, 8, f32_exp); | |
933 | val = deposit32(val, 15, 8, extract64(f64_frac, 52 - 8, 8)); | |
934 | return make_float32(val); | |
935 | } | |
936 | ||
937 | float64 HELPER(rsqrte_f64)(float64 input, void *fpstp) | |
938 | { | |
939 | float_status *s = fpstp; | |
940 | float64 f64 = float64_squash_input_denormal(input, s); | |
941 | uint64_t val = float64_val(f64); | |
942 | bool f64_sign = float64_is_neg(f64); | |
943 | int f64_exp = extract64(val, 52, 11); | |
944 | uint64_t f64_frac = extract64(val, 0, 52); | |
945 | ||
946 | if (float64_is_any_nan(f64)) { | |
947 | float64 nan = f64; | |
948 | if (float64_is_signaling_nan(f64, s)) { | |
949 | float_raise(float_flag_invalid, s); | |
950 | nan = float64_silence_nan(f64, s); | |
951 | } | |
952 | if (s->default_nan_mode) { | |
953 | nan = float64_default_nan(s); | |
954 | } | |
955 | return nan; | |
956 | } else if (float64_is_zero(f64)) { | |
957 | float_raise(float_flag_divbyzero, s); | |
958 | return float64_set_sign(float64_infinity, float64_is_neg(f64)); | |
959 | } else if (float64_is_neg(f64)) { | |
960 | float_raise(float_flag_invalid, s); | |
961 | return float64_default_nan(s); | |
962 | } else if (float64_is_infinity(f64)) { | |
963 | return float64_zero; | |
964 | } | |
965 | ||
966 | f64_frac = recip_sqrt_estimate(&f64_exp, 3068, f64_frac); | |
967 | ||
968 | /* result = sign : result_exp<4:0> : estimate<7:0> : Zeros(44) */ | |
969 | val = deposit64(0, 61, 1, f64_sign); | |
970 | val = deposit64(val, 52, 11, f64_exp); | |
971 | val = deposit64(val, 44, 8, extract64(f64_frac, 52 - 8, 8)); | |
972 | return make_float64(val); | |
973 | } | |
974 | ||
975 | uint32_t HELPER(recpe_u32)(uint32_t a, void *fpstp) | |
976 | { | |
977 | /* float_status *s = fpstp; */ | |
978 | int input, estimate; | |
979 | ||
980 | if ((a & 0x80000000) == 0) { | |
981 | return 0xffffffff; | |
982 | } | |
983 | ||
984 | input = extract32(a, 23, 9); | |
985 | estimate = recip_estimate(input); | |
986 | ||
987 | return deposit32(0, (32 - 9), 9, estimate); | |
988 | } | |
989 | ||
990 | uint32_t HELPER(rsqrte_u32)(uint32_t a, void *fpstp) | |
991 | { | |
992 | int estimate; | |
993 | ||
994 | if ((a & 0xc0000000) == 0) { | |
995 | return 0xffffffff; | |
996 | } | |
997 | ||
998 | estimate = do_recip_sqrt_estimate(extract32(a, 23, 9)); | |
999 | ||
1000 | return deposit32(0, 23, 9, estimate); | |
1001 | } | |
1002 | ||
1003 | /* VFPv4 fused multiply-accumulate */ | |
1004 | float32 VFP_HELPER(muladd, s)(float32 a, float32 b, float32 c, void *fpstp) | |
1005 | { | |
1006 | float_status *fpst = fpstp; | |
1007 | return float32_muladd(a, b, c, 0, fpst); | |
1008 | } | |
1009 | ||
1010 | float64 VFP_HELPER(muladd, d)(float64 a, float64 b, float64 c, void *fpstp) | |
1011 | { | |
1012 | float_status *fpst = fpstp; | |
1013 | return float64_muladd(a, b, c, 0, fpst); | |
1014 | } | |
1015 | ||
1016 | /* ARMv8 round to integral */ | |
1017 | float32 HELPER(rints_exact)(float32 x, void *fp_status) | |
1018 | { | |
1019 | return float32_round_to_int(x, fp_status); | |
1020 | } | |
1021 | ||
1022 | float64 HELPER(rintd_exact)(float64 x, void *fp_status) | |
1023 | { | |
1024 | return float64_round_to_int(x, fp_status); | |
1025 | } | |
1026 | ||
1027 | float32 HELPER(rints)(float32 x, void *fp_status) | |
1028 | { | |
1029 | int old_flags = get_float_exception_flags(fp_status), new_flags; | |
1030 | float32 ret; | |
1031 | ||
1032 | ret = float32_round_to_int(x, fp_status); | |
1033 | ||
1034 | /* Suppress any inexact exceptions the conversion produced */ | |
1035 | if (!(old_flags & float_flag_inexact)) { | |
1036 | new_flags = get_float_exception_flags(fp_status); | |
1037 | set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status); | |
1038 | } | |
1039 | ||
1040 | return ret; | |
1041 | } | |
1042 | ||
1043 | float64 HELPER(rintd)(float64 x, void *fp_status) | |
1044 | { | |
1045 | int old_flags = get_float_exception_flags(fp_status), new_flags; | |
1046 | float64 ret; | |
1047 | ||
1048 | ret = float64_round_to_int(x, fp_status); | |
1049 | ||
1050 | new_flags = get_float_exception_flags(fp_status); | |
1051 | ||
1052 | /* Suppress any inexact exceptions the conversion produced */ | |
1053 | if (!(old_flags & float_flag_inexact)) { | |
1054 | new_flags = get_float_exception_flags(fp_status); | |
1055 | set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status); | |
1056 | } | |
1057 | ||
1058 | return ret; | |
1059 | } | |
1060 | ||
1061 | /* Convert ARM rounding mode to softfloat */ | |
1062 | int arm_rmode_to_sf(int rmode) | |
1063 | { | |
1064 | switch (rmode) { | |
1065 | case FPROUNDING_TIEAWAY: | |
1066 | rmode = float_round_ties_away; | |
1067 | break; | |
1068 | case FPROUNDING_ODD: | |
1069 | /* FIXME: add support for TIEAWAY and ODD */ | |
1070 | qemu_log_mask(LOG_UNIMP, "arm: unimplemented rounding mode: %d\n", | |
1071 | rmode); | |
1072 | /* fall through for now */ | |
1073 | case FPROUNDING_TIEEVEN: | |
1074 | default: | |
1075 | rmode = float_round_nearest_even; | |
1076 | break; | |
1077 | case FPROUNDING_POSINF: | |
1078 | rmode = float_round_up; | |
1079 | break; | |
1080 | case FPROUNDING_NEGINF: | |
1081 | rmode = float_round_down; | |
1082 | break; | |
1083 | case FPROUNDING_ZERO: | |
1084 | rmode = float_round_to_zero; | |
1085 | break; | |
1086 | } | |
1087 | return rmode; | |
1088 | } | |
6c1f6f27 RH |
1089 | |
1090 | /* | |
1091 | * Implement float64 to int32_t conversion without saturation; | |
1092 | * the result is supplied modulo 2^32. | |
1093 | */ | |
1094 | uint64_t HELPER(fjcvtzs)(float64 value, void *vstatus) | |
1095 | { | |
1096 | float_status *status = vstatus; | |
1097 | uint32_t exp, sign; | |
1098 | uint64_t frac; | |
1099 | uint32_t inexact = 1; /* !Z */ | |
1100 | ||
1101 | sign = extract64(value, 63, 1); | |
1102 | exp = extract64(value, 52, 11); | |
1103 | frac = extract64(value, 0, 52); | |
1104 | ||
1105 | if (exp == 0) { | |
1106 | /* While not inexact for IEEE FP, -0.0 is inexact for JavaScript. */ | |
1107 | inexact = sign; | |
1108 | if (frac != 0) { | |
1109 | if (status->flush_inputs_to_zero) { | |
1110 | float_raise(float_flag_input_denormal, status); | |
1111 | } else { | |
1112 | float_raise(float_flag_inexact, status); | |
1113 | inexact = 1; | |
1114 | } | |
1115 | } | |
1116 | frac = 0; | |
1117 | } else if (exp == 0x7ff) { | |
1118 | /* This operation raises Invalid for both NaN and overflow (Inf). */ | |
1119 | float_raise(float_flag_invalid, status); | |
1120 | frac = 0; | |
1121 | } else { | |
1122 | int true_exp = exp - 1023; | |
1123 | int shift = true_exp - 52; | |
1124 | ||
1125 | /* Restore implicit bit. */ | |
1126 | frac |= 1ull << 52; | |
1127 | ||
1128 | /* Shift the fraction into place. */ | |
1129 | if (shift >= 0) { | |
1130 | /* The number is so large we must shift the fraction left. */ | |
1131 | if (shift >= 64) { | |
1132 | /* The fraction is shifted out entirely. */ | |
1133 | frac = 0; | |
1134 | } else { | |
1135 | frac <<= shift; | |
1136 | } | |
1137 | } else if (shift > -64) { | |
1138 | /* Normal case -- shift right and notice if bits shift out. */ | |
1139 | inexact = (frac << (64 + shift)) != 0; | |
1140 | frac >>= -shift; | |
1141 | } else { | |
1142 | /* The fraction is shifted out entirely. */ | |
1143 | frac = 0; | |
1144 | } | |
1145 | ||
1146 | /* Notice overflow or inexact exceptions. */ | |
1147 | if (true_exp > 31 || frac > (sign ? 0x80000000ull : 0x7fffffff)) { | |
1148 | /* Overflow, for which this operation raises invalid. */ | |
1149 | float_raise(float_flag_invalid, status); | |
1150 | inexact = 1; | |
1151 | } else if (inexact) { | |
1152 | float_raise(float_flag_inexact, status); | |
1153 | } | |
1154 | ||
1155 | /* Honor the sign. */ | |
1156 | if (sign) { | |
1157 | frac = -frac; | |
1158 | } | |
1159 | } | |
1160 | ||
1161 | /* Pack the result and the env->ZF representation of Z together. */ | |
1162 | return deposit64(frac, 32, 32, inexact); | |
1163 | } | |
1164 | ||
1165 | uint32_t HELPER(vjcvt)(float64 value, CPUARMState *env) | |
1166 | { | |
1167 | uint64_t pair = HELPER(fjcvtzs)(value, &env->vfp.fp_status); | |
1168 | uint32_t result = pair; | |
1169 | uint32_t z = (pair >> 32) == 0; | |
1170 | ||
1171 | /* Store Z, clear NCV, in FPSCR.NZCV. */ | |
1172 | env->vfp.xregs[ARM_VFP_FPSCR] | |
1173 | = (env->vfp.xregs[ARM_VFP_FPSCR] & ~CPSR_NZCV) | (z * CPSR_Z); | |
1174 | ||
1175 | return result; | |
1176 | } | |
6bea2563 RH |
1177 | |
1178 | /* Round a float32 to an integer that fits in int32_t or int64_t. */ | |
1179 | static float32 frint_s(float32 f, float_status *fpst, int intsize) | |
1180 | { | |
1181 | int old_flags = get_float_exception_flags(fpst); | |
1182 | uint32_t exp = extract32(f, 23, 8); | |
1183 | ||
1184 | if (unlikely(exp == 0xff)) { | |
1185 | /* NaN or Inf. */ | |
1186 | goto overflow; | |
1187 | } | |
1188 | ||
1189 | /* Round and re-extract the exponent. */ | |
1190 | f = float32_round_to_int(f, fpst); | |
1191 | exp = extract32(f, 23, 8); | |
1192 | ||
1193 | /* Validate the range of the result. */ | |
1194 | if (exp < 126 + intsize) { | |
1195 | /* abs(F) <= INT{N}_MAX */ | |
1196 | return f; | |
1197 | } | |
1198 | if (exp == 126 + intsize) { | |
1199 | uint32_t sign = extract32(f, 31, 1); | |
1200 | uint32_t frac = extract32(f, 0, 23); | |
1201 | if (sign && frac == 0) { | |
1202 | /* F == INT{N}_MIN */ | |
1203 | return f; | |
1204 | } | |
1205 | } | |
1206 | ||
1207 | overflow: | |
1208 | /* | |
1209 | * Raise Invalid and return INT{N}_MIN as a float. Revert any | |
1210 | * inexact exception float32_round_to_int may have raised. | |
1211 | */ | |
1212 | set_float_exception_flags(old_flags | float_flag_invalid, fpst); | |
1213 | return (0x100u + 126u + intsize) << 23; | |
1214 | } | |
1215 | ||
1216 | float32 HELPER(frint32_s)(float32 f, void *fpst) | |
1217 | { | |
1218 | return frint_s(f, fpst, 32); | |
1219 | } | |
1220 | ||
1221 | float32 HELPER(frint64_s)(float32 f, void *fpst) | |
1222 | { | |
1223 | return frint_s(f, fpst, 64); | |
1224 | } | |
1225 | ||
1226 | /* Round a float64 to an integer that fits in int32_t or int64_t. */ | |
1227 | static float64 frint_d(float64 f, float_status *fpst, int intsize) | |
1228 | { | |
1229 | int old_flags = get_float_exception_flags(fpst); | |
1230 | uint32_t exp = extract64(f, 52, 11); | |
1231 | ||
1232 | if (unlikely(exp == 0x7ff)) { | |
1233 | /* NaN or Inf. */ | |
1234 | goto overflow; | |
1235 | } | |
1236 | ||
1237 | /* Round and re-extract the exponent. */ | |
1238 | f = float64_round_to_int(f, fpst); | |
1239 | exp = extract64(f, 52, 11); | |
1240 | ||
1241 | /* Validate the range of the result. */ | |
1242 | if (exp < 1022 + intsize) { | |
1243 | /* abs(F) <= INT{N}_MAX */ | |
1244 | return f; | |
1245 | } | |
1246 | if (exp == 1022 + intsize) { | |
1247 | uint64_t sign = extract64(f, 63, 1); | |
1248 | uint64_t frac = extract64(f, 0, 52); | |
1249 | if (sign && frac == 0) { | |
1250 | /* F == INT{N}_MIN */ | |
1251 | return f; | |
1252 | } | |
1253 | } | |
1254 | ||
1255 | overflow: | |
1256 | /* | |
1257 | * Raise Invalid and return INT{N}_MIN as a float. Revert any | |
1258 | * inexact exception float64_round_to_int may have raised. | |
1259 | */ | |
1260 | set_float_exception_flags(old_flags | float_flag_invalid, fpst); | |
1261 | return (uint64_t)(0x800 + 1022 + intsize) << 52; | |
1262 | } | |
1263 | ||
1264 | float64 HELPER(frint32_d)(float64 f, void *fpst) | |
1265 | { | |
1266 | return frint_d(f, fpst, 32); | |
1267 | } | |
1268 | ||
1269 | float64 HELPER(frint64_d)(float64 f, void *fpst) | |
1270 | { | |
1271 | return frint_d(f, fpst, 64); | |
1272 | } |