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e739a48e AF |
1 | /* |
2 | * QEMU CRIS CPU | |
3 | * | |
1c3b52fb AF |
4 | * Copyright (c) 2008 AXIS Communications AB |
5 | * Written by Edgar E. Iglesias. | |
6 | * | |
e739a48e AF |
7 | * Copyright (c) 2012 SUSE LINUX Products GmbH |
8 | * | |
9 | * This library is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU Lesser General Public | |
11 | * License as published by the Free Software Foundation; either | |
12 | * version 2.1 of the License, or (at your option) any later version. | |
13 | * | |
14 | * This library is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
17 | * Lesser General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU Lesser General Public | |
20 | * License along with this library; if not, see | |
21 | * <http://www.gnu.org/licenses/lgpl-2.1.html> | |
22 | */ | |
23 | ||
23b0d7df | 24 | #include "qemu/osdep.h" |
da34e65c | 25 | #include "qapi/error.h" |
0442428a | 26 | #include "qemu/qemu-print.h" |
e739a48e | 27 | #include "cpu.h" |
1c3b52fb | 28 | #include "mmu.h" |
e739a48e AF |
29 | |
30 | ||
f45748f1 AF |
31 | static void cris_cpu_set_pc(CPUState *cs, vaddr value) |
32 | { | |
33 | CRISCPU *cpu = CRIS_CPU(cs); | |
34 | ||
35 | cpu->env.pc = value; | |
36 | } | |
37 | ||
8c2e1b00 AF |
38 | static bool cris_cpu_has_work(CPUState *cs) |
39 | { | |
40 | return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI); | |
41 | } | |
42 | ||
781c67ca | 43 | static void cris_cpu_reset(DeviceState *dev) |
e739a48e | 44 | { |
781c67ca | 45 | CPUState *s = CPU(dev); |
e739a48e AF |
46 | CRISCPU *cpu = CRIS_CPU(s); |
47 | CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(cpu); | |
48 | CPUCRISState *env = &cpu->env; | |
1c3b52fb AF |
49 | uint32_t vr; |
50 | ||
781c67ca | 51 | ccc->parent_reset(dev); |
e739a48e | 52 | |
1c3b52fb | 53 | vr = env->pregs[PR_VR]; |
1f5c00cf | 54 | memset(env, 0, offsetof(CPUCRISState, end_reset_fields)); |
1c3b52fb | 55 | env->pregs[PR_VR] = vr; |
1c3b52fb AF |
56 | |
57 | #if defined(CONFIG_USER_ONLY) | |
58 | /* start in user mode with interrupts enabled. */ | |
59 | env->pregs[PR_CCS] |= U_FLAG | I_FLAG | P_FLAG; | |
60 | #else | |
61 | cris_mmu_init(env); | |
62 | env->pregs[PR_CCS] = 0; | |
63 | #endif | |
e739a48e AF |
64 | } |
65 | ||
6ae064fc AF |
66 | static ObjectClass *cris_cpu_class_by_name(const char *cpu_model) |
67 | { | |
68 | ObjectClass *oc; | |
69 | char *typename; | |
70 | ||
fd5d5afa EI |
71 | #if defined(CONFIG_USER_ONLY) |
72 | if (strcasecmp(cpu_model, "any") == 0) { | |
39364191 | 73 | return object_class_by_name(CRIS_CPU_TYPE_NAME("crisv32")); |
fd5d5afa EI |
74 | } |
75 | #endif | |
76 | ||
39364191 | 77 | typename = g_strdup_printf(CRIS_CPU_TYPE_NAME("%s"), cpu_model); |
6ae064fc AF |
78 | oc = object_class_by_name(typename); |
79 | g_free(typename); | |
80 | if (oc != NULL && (!object_class_dynamic_cast(oc, TYPE_CRIS_CPU) || | |
81 | object_class_is_abstract(oc))) { | |
82 | oc = NULL; | |
83 | } | |
84 | return oc; | |
85 | } | |
86 | ||
6ae064fc AF |
87 | /* Sort alphabetically by VR. */ |
88 | static gint cris_cpu_list_compare(gconstpointer a, gconstpointer b) | |
89 | { | |
90 | CRISCPUClass *ccc_a = CRIS_CPU_CLASS(a); | |
91 | CRISCPUClass *ccc_b = CRIS_CPU_CLASS(b); | |
92 | ||
93 | /* */ | |
94 | if (ccc_a->vr > ccc_b->vr) { | |
95 | return 1; | |
96 | } else if (ccc_a->vr < ccc_b->vr) { | |
97 | return -1; | |
98 | } else { | |
99 | return 0; | |
100 | } | |
101 | } | |
102 | ||
103 | static void cris_cpu_list_entry(gpointer data, gpointer user_data) | |
104 | { | |
105 | ObjectClass *oc = data; | |
6ae064fc AF |
106 | const char *typename = object_class_get_name(oc); |
107 | char *name; | |
108 | ||
39364191 | 109 | name = g_strndup(typename, strlen(typename) - strlen(CRIS_CPU_TYPE_SUFFIX)); |
0442428a | 110 | qemu_printf(" %s\n", name); |
6ae064fc AF |
111 | g_free(name); |
112 | } | |
113 | ||
0442428a | 114 | void cris_cpu_list(void) |
6ae064fc | 115 | { |
6ae064fc AF |
116 | GSList *list; |
117 | ||
118 | list = object_class_get_list(TYPE_CRIS_CPU, false); | |
119 | list = g_slist_sort(list, cris_cpu_list_compare); | |
0442428a MA |
120 | qemu_printf("Available CPUs:\n"); |
121 | g_slist_foreach(list, cris_cpu_list_entry, NULL); | |
6ae064fc AF |
122 | g_slist_free(list); |
123 | } | |
124 | ||
ca45f8b0 AF |
125 | static void cris_cpu_realizefn(DeviceState *dev, Error **errp) |
126 | { | |
14a10fc3 | 127 | CPUState *cs = CPU(dev); |
ca45f8b0 | 128 | CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(dev); |
ce5b1bbf LV |
129 | Error *local_err = NULL; |
130 | ||
131 | cpu_exec_realizefn(cs, &local_err); | |
132 | if (local_err != NULL) { | |
133 | error_propagate(errp, local_err); | |
134 | return; | |
135 | } | |
ca45f8b0 | 136 | |
14a10fc3 AF |
137 | cpu_reset(cs); |
138 | qemu_init_vcpu(cs); | |
ca45f8b0 AF |
139 | |
140 | ccc->parent_realize(dev, errp); | |
141 | } | |
142 | ||
3065839c EI |
143 | #ifndef CONFIG_USER_ONLY |
144 | static void cris_cpu_set_irq(void *opaque, int irq, int level) | |
145 | { | |
146 | CRISCPU *cpu = opaque; | |
147 | CPUState *cs = CPU(cpu); | |
148 | int type = irq == CRIS_CPU_IRQ ? CPU_INTERRUPT_HARD : CPU_INTERRUPT_NMI; | |
149 | ||
f4f64388 MAL |
150 | if (irq == CRIS_CPU_IRQ) { |
151 | /* | |
152 | * The PIC passes us the vector for the IRQ as the value it sends | |
153 | * over the qemu_irq line | |
154 | */ | |
155 | cpu->env.interrupt_vector = level; | |
156 | } | |
157 | ||
3065839c EI |
158 | if (level) { |
159 | cpu_interrupt(cs, type); | |
160 | } else { | |
161 | cpu_reset_interrupt(cs, type); | |
162 | } | |
163 | } | |
164 | #endif | |
165 | ||
6b625fde PC |
166 | static void cris_disas_set_info(CPUState *cpu, disassemble_info *info) |
167 | { | |
168 | CRISCPU *cc = CRIS_CPU(cpu); | |
169 | CPUCRISState *env = &cc->env; | |
170 | ||
171 | if (env->pregs[PR_VR] != 32) { | |
172 | info->mach = bfd_mach_cris_v0_v10; | |
173 | info->print_insn = print_insn_crisv10; | |
174 | } else { | |
175 | info->mach = bfd_mach_cris_v32; | |
176 | info->print_insn = print_insn_crisv32; | |
177 | } | |
178 | } | |
179 | ||
aa0d1267 AF |
180 | static void cris_cpu_initfn(Object *obj) |
181 | { | |
182 | CRISCPU *cpu = CRIS_CPU(obj); | |
6ae064fc | 183 | CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(obj); |
aa0d1267 AF |
184 | CPUCRISState *env = &cpu->env; |
185 | ||
7506ed90 | 186 | cpu_set_cpustate_pointers(cpu); |
d1a94fec | 187 | |
6ae064fc AF |
188 | env->pregs[PR_VR] = ccc->vr; |
189 | ||
3065839c EI |
190 | #ifndef CONFIG_USER_ONLY |
191 | /* IRQ and NMI lines. */ | |
192 | qdev_init_gpio_in(DEVICE(cpu), cris_cpu_set_irq, 2); | |
193 | #endif | |
aa0d1267 AF |
194 | } |
195 | ||
6ae064fc AF |
196 | static void crisv8_cpu_class_init(ObjectClass *oc, void *data) |
197 | { | |
b21bfeea | 198 | CPUClass *cc = CPU_CLASS(oc); |
6ae064fc AF |
199 | CRISCPUClass *ccc = CRIS_CPU_CLASS(oc); |
200 | ||
201 | ccc->vr = 8; | |
b21bfeea | 202 | cc->do_interrupt = crisv10_cpu_do_interrupt; |
90431220 | 203 | cc->gdb_read_register = crisv10_cpu_gdb_read_register; |
55c3ceef | 204 | cc->tcg_initialize = cris_initialize_crisv10_tcg; |
6ae064fc AF |
205 | } |
206 | ||
207 | static void crisv9_cpu_class_init(ObjectClass *oc, void *data) | |
208 | { | |
b21bfeea | 209 | CPUClass *cc = CPU_CLASS(oc); |
6ae064fc AF |
210 | CRISCPUClass *ccc = CRIS_CPU_CLASS(oc); |
211 | ||
212 | ccc->vr = 9; | |
b21bfeea | 213 | cc->do_interrupt = crisv10_cpu_do_interrupt; |
90431220 | 214 | cc->gdb_read_register = crisv10_cpu_gdb_read_register; |
55c3ceef | 215 | cc->tcg_initialize = cris_initialize_crisv10_tcg; |
6ae064fc AF |
216 | } |
217 | ||
218 | static void crisv10_cpu_class_init(ObjectClass *oc, void *data) | |
219 | { | |
b21bfeea | 220 | CPUClass *cc = CPU_CLASS(oc); |
6ae064fc AF |
221 | CRISCPUClass *ccc = CRIS_CPU_CLASS(oc); |
222 | ||
223 | ccc->vr = 10; | |
b21bfeea | 224 | cc->do_interrupt = crisv10_cpu_do_interrupt; |
90431220 | 225 | cc->gdb_read_register = crisv10_cpu_gdb_read_register; |
55c3ceef | 226 | cc->tcg_initialize = cris_initialize_crisv10_tcg; |
6ae064fc AF |
227 | } |
228 | ||
229 | static void crisv11_cpu_class_init(ObjectClass *oc, void *data) | |
230 | { | |
b21bfeea | 231 | CPUClass *cc = CPU_CLASS(oc); |
6ae064fc AF |
232 | CRISCPUClass *ccc = CRIS_CPU_CLASS(oc); |
233 | ||
234 | ccc->vr = 11; | |
b21bfeea | 235 | cc->do_interrupt = crisv10_cpu_do_interrupt; |
90431220 | 236 | cc->gdb_read_register = crisv10_cpu_gdb_read_register; |
55c3ceef | 237 | cc->tcg_initialize = cris_initialize_crisv10_tcg; |
6ae064fc AF |
238 | } |
239 | ||
ceffd34e RV |
240 | static void crisv17_cpu_class_init(ObjectClass *oc, void *data) |
241 | { | |
242 | CPUClass *cc = CPU_CLASS(oc); | |
243 | CRISCPUClass *ccc = CRIS_CPU_CLASS(oc); | |
244 | ||
245 | ccc->vr = 17; | |
246 | cc->do_interrupt = crisv10_cpu_do_interrupt; | |
247 | cc->gdb_read_register = crisv10_cpu_gdb_read_register; | |
55c3ceef | 248 | cc->tcg_initialize = cris_initialize_crisv10_tcg; |
ceffd34e RV |
249 | } |
250 | ||
6ae064fc AF |
251 | static void crisv32_cpu_class_init(ObjectClass *oc, void *data) |
252 | { | |
253 | CRISCPUClass *ccc = CRIS_CPU_CLASS(oc); | |
254 | ||
255 | ccc->vr = 32; | |
256 | } | |
257 | ||
e739a48e AF |
258 | static void cris_cpu_class_init(ObjectClass *oc, void *data) |
259 | { | |
ca45f8b0 | 260 | DeviceClass *dc = DEVICE_CLASS(oc); |
e739a48e AF |
261 | CPUClass *cc = CPU_CLASS(oc); |
262 | CRISCPUClass *ccc = CRIS_CPU_CLASS(oc); | |
263 | ||
bf853881 PMD |
264 | device_class_set_parent_realize(dc, cris_cpu_realizefn, |
265 | &ccc->parent_realize); | |
ca45f8b0 | 266 | |
781c67ca | 267 | device_class_set_parent_reset(dc, cris_cpu_reset, &ccc->parent_reset); |
6ae064fc AF |
268 | |
269 | cc->class_by_name = cris_cpu_class_by_name; | |
8c2e1b00 | 270 | cc->has_work = cris_cpu_has_work; |
97a8ea5a | 271 | cc->do_interrupt = cris_cpu_do_interrupt; |
5a1f7f44 | 272 | cc->cpu_exec_interrupt = cris_cpu_exec_interrupt; |
878096ee | 273 | cc->dump_state = cris_cpu_dump_state; |
f45748f1 | 274 | cc->set_pc = cris_cpu_set_pc; |
5b50e790 AF |
275 | cc->gdb_read_register = cris_cpu_gdb_read_register; |
276 | cc->gdb_write_register = cris_cpu_gdb_write_register; | |
c038ec93 RH |
277 | cc->tlb_fill = cris_cpu_tlb_fill; |
278 | #ifndef CONFIG_USER_ONLY | |
00b941e5 | 279 | cc->get_phys_page_debug = cris_cpu_get_phys_page_debug; |
16a1b6e9 | 280 | dc->vmsd = &vmstate_cris_cpu; |
00b941e5 | 281 | #endif |
a0e372f0 AF |
282 | |
283 | cc->gdb_num_core_regs = 49; | |
2472b6c0 | 284 | cc->gdb_stop_before_watchpoint = true; |
6b625fde PC |
285 | |
286 | cc->disas_set_info = cris_disas_set_info; | |
55c3ceef | 287 | cc->tcg_initialize = cris_initialize_tcg; |
e739a48e AF |
288 | } |
289 | ||
39364191 IM |
290 | #define DEFINE_CRIS_CPU_TYPE(cpu_model, initfn) \ |
291 | { \ | |
292 | .parent = TYPE_CRIS_CPU, \ | |
293 | .class_init = initfn, \ | |
294 | .name = CRIS_CPU_TYPE_NAME(cpu_model), \ | |
295 | } | |
e739a48e | 296 | |
39364191 IM |
297 | static const TypeInfo cris_cpu_model_type_infos[] = { |
298 | { | |
299 | .name = TYPE_CRIS_CPU, | |
300 | .parent = TYPE_CPU, | |
301 | .instance_size = sizeof(CRISCPU), | |
302 | .instance_init = cris_cpu_initfn, | |
303 | .abstract = true, | |
304 | .class_size = sizeof(CRISCPUClass), | |
305 | .class_init = cris_cpu_class_init, | |
306 | }, | |
307 | DEFINE_CRIS_CPU_TYPE("crisv8", crisv8_cpu_class_init), | |
308 | DEFINE_CRIS_CPU_TYPE("crisv9", crisv9_cpu_class_init), | |
309 | DEFINE_CRIS_CPU_TYPE("crisv10", crisv10_cpu_class_init), | |
310 | DEFINE_CRIS_CPU_TYPE("crisv11", crisv11_cpu_class_init), | |
311 | DEFINE_CRIS_CPU_TYPE("crisv17", crisv17_cpu_class_init), | |
312 | DEFINE_CRIS_CPU_TYPE("crisv32", crisv32_cpu_class_init), | |
313 | }; | |
e739a48e | 314 | |
39364191 | 315 | DEFINE_TYPES(cris_cpu_model_type_infos) |