[mirror_qemu.git] / target / cris / helper.c

/*
 *  CRIS helper routines.
 *
 *  Copyright (c) 2007 AXIS Communications AB
 *  Written by Edgar E. Iglesias.
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2.1 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#include "qemu/osdep.h"
#include "qemu/log.h"
#include "cpu.h"
#include "hw/core/tcg-cpu-ops.h"
#include "mmu.h"
#include "qemu/host-utils.h"
#include "exec/exec-all.h"
#include "exec/cpu_ldst.h"
#include "exec/helper-proto.h"


//#define CRIS_HELPER_DEBUG


#ifdef CRIS_HELPER_DEBUG
#define D(x) x
#define D_LOG(...) qemu_log(__VA_ARGS__)
#else
#define D(x)
#define D_LOG(...) do { } while (0)
#endif

static void cris_shift_ccs(CPUCRISState *env)
{
    uint32_t ccs;
    /* Apply the ccs shift.  */
    ccs = env->pregs[PR_CCS];
    ccs = ((ccs & 0xc0000000) | ((ccs << 12) >> 2)) & ~0x3ff;
    env->pregs[PR_CCS] = ccs;
}

bool cris_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
                       MMUAccessType access_type, int mmu_idx,
                       bool probe, uintptr_t retaddr)
{
    CRISCPU *cpu = CRIS_CPU(cs);
    CPUCRISState *env = &cpu->env;
    struct cris_mmu_result res;
    int prot, miss;
    target_ulong phy;

    miss = cris_mmu_translate(&res, env, address & TARGET_PAGE_MASK,
                              access_type, mmu_idx, 0);
    if (likely(!miss)) {
        /*
         * Mask off the cache selection bit. The ETRAX busses do not
         * see the top bit.
         */
        phy = res.phy & ~0x80000000;
        prot = res.prot;
        tlb_set_page(cs, address & TARGET_PAGE_MASK, phy,
                     prot, mmu_idx, TARGET_PAGE_SIZE);
        return true;
    }

    if (probe) {
        return false;
    }

    if (cs->exception_index == EXCP_BUSFAULT) {
        cpu_abort(cs, "CRIS: Illegal recursive bus fault."
                      "addr=%" VADDR_PRIx " access_type=%d\n",
                      address, access_type);
    }

    env->pregs[PR_EDA] = address;
    cs->exception_index = EXCP_BUSFAULT;
    env->fault_vector = res.bf_vec;
    if (retaddr) {
        if (cpu_restore_state(cs, retaddr)) {
            /* Evaluate flags after retranslation. */
            helper_top_evaluate_flags(env);
        }
    }
    cpu_loop_exit(cs);
}

void crisv10_cpu_do_interrupt(CPUState *cs)
{
    CRISCPU *cpu = CRIS_CPU(cs);
    CPUCRISState *env = &cpu->env;
    int ex_vec = -1;

    D_LOG("exception index=%d interrupt_req=%d\n",
          cs->exception_index,
          cs->interrupt_request);

    if (env->dslot) {
        /* CRISv10 never takes interrupts while in a delay-slot.  */
        cpu_abort(cs, "CRIS: Interrupt on delay-slot\n");
    }

    assert(!(env->pregs[PR_CCS] & PFIX_FLAG));
    switch (cs->exception_index) {
    case EXCP_BREAK:
        /* These exceptions are generated by the core itself.
           ERP should point to the insn following the brk.  */
        ex_vec = env->trap_vector;
        env->pregs[PRV10_BRP] = env->pc;
        break;

    case EXCP_NMI:
        /* NMI is hardwired to vector zero.  */
        ex_vec = 0;
        env->pregs[PR_CCS] &= ~M_FLAG_V10;
        env->pregs[PRV10_BRP] = env->pc;
        break;

    case EXCP_BUSFAULT:
        cpu_abort(cs, "Unhandled busfault");
        break;

    default:
        /* The interrupt controller gives us the vector.  */
        ex_vec = env->interrupt_vector;
        /* Normal interrupts are taken between
           TB's.  env->pc is valid here.  */
        env->pregs[PR_ERP] = env->pc;
        break;
    }

    if (env->pregs[PR_CCS] & U_FLAG) {
        /* Swap stack pointers.  */
        env->pregs[PR_USP] = env->regs[R_SP];
        env->regs[R_SP] = env->ksp;
    }

    /* Now that we are in kernel mode, load the handlers address.  */
    env->pc = cpu_ldl_code(env, env->pregs[PR_EBP] + ex_vec * 4);
    env->locked_irq = 1;
    env->pregs[PR_CCS] |= F_FLAG_V10; /* set F.  */

    qemu_log_mask(CPU_LOG_INT, "%s isr=%x vec=%x ccs=%x pid=%d erp=%x\n",
                  __func__, env->pc, ex_vec,
                  env->pregs[PR_CCS],
                  env->pregs[PR_PID],
                  env->pregs[PR_ERP]);
}

void cris_cpu_do_interrupt(CPUState *cs)
{
    CRISCPU *cpu = CRIS_CPU(cs);
    CPUCRISState *env = &cpu->env;
    int ex_vec = -1;

    D_LOG("exception index=%d interrupt_req=%d\n",
          cs->exception_index,
          cs->interrupt_request);

    switch (cs->exception_index) {
    case EXCP_BREAK:
        /* These exceptions are generated by the core itself.
           ERP should point to the insn following the brk.  */
        ex_vec = env->trap_vector;
        env->pregs[PR_ERP] = env->pc;
        break;

    case EXCP_NMI:
        /* NMI is hardwired to vector zero.  */
        ex_vec = 0;
        env->pregs[PR_CCS] &= ~M_FLAG_V32;
        env->pregs[PR_NRP] = env->pc;
        break;

    case EXCP_BUSFAULT:
        ex_vec = env->fault_vector;
        env->pregs[PR_ERP] = env->pc;
        break;

    default:
        /* The interrupt controller gives us the vector.  */
        ex_vec = env->interrupt_vector;
        /* Normal interrupts are taken between
           TB's.  env->pc is valid here.  */
        env->pregs[PR_ERP] = env->pc;
        break;
    }

    /* Fill in the IDX field.  */
    env->pregs[PR_EXS] = (ex_vec & 0xff) << 8;

    if (env->dslot) {
        D_LOG("excp isr=%x PC=%x ds=%d SP=%x"
              " ERP=%x pid=%x ccs=%x cc=%d %x\n",
              ex_vec, env->pc, env->dslot,
              env->regs[R_SP],
              env->pregs[PR_ERP], env->pregs[PR_PID],
              env->pregs[PR_CCS],
              env->cc_op, env->cc_mask);
        /* We loose the btarget, btaken state here so rexec the
           branch.  */
        env->pregs[PR_ERP] -= env->dslot;
        /* Exception starts with dslot cleared.  */
        env->dslot = 0;
    }

    if (env->pregs[PR_CCS] & U_FLAG) {
        /* Swap stack pointers.  */
        env->pregs[PR_USP] = env->regs[R_SP];
        env->regs[R_SP] = env->ksp;
    }

    /* Apply the CRIS CCS shift. Clears U if set.  */
    cris_shift_ccs(env);

    /* Now that we are in kernel mode, load the handlers address.
       This load may not fault, real hw leaves that behaviour as
       undefined.  */
    env->pc = cpu_ldl_code(env, env->pregs[PR_EBP] + ex_vec * 4);

    /* Clear the excption_index to avoid spurious hw_aborts for recursive
       bus faults.  */
    cs->exception_index = -1;

    D_LOG("%s isr=%x vec=%x ccs=%x pid=%d erp=%x\n",
          __func__, env->pc, ex_vec,
          env->pregs[PR_CCS],
          env->pregs[PR_PID],
          env->pregs[PR_ERP]);
}

hwaddr cris_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
{
    CRISCPU *cpu = CRIS_CPU(cs);
    uint32_t phy = addr;
    struct cris_mmu_result res;
    int miss;

    miss = cris_mmu_translate(&res, &cpu->env, addr, MMU_DATA_LOAD, 0, 1);
    /* If D TLB misses, try I TLB.  */
    if (miss) {
        miss = cris_mmu_translate(&res, &cpu->env, addr, MMU_INST_FETCH, 0, 1);
    }

    if (!miss) {
        phy = res.phy;
    }
    D(fprintf(stderr, "%s %x -> %x\n", __func__, addr, phy));
    return phy;
}

bool cris_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
{
    CPUClass *cc = CPU_GET_CLASS(cs);
    CRISCPU *cpu = CRIS_CPU(cs);
    CPUCRISState *env = &cpu->env;
    bool ret = false;

    if (interrupt_request & CPU_INTERRUPT_HARD
        && (env->pregs[PR_CCS] & I_FLAG)
        && !env->locked_irq) {
        cs->exception_index = EXCP_IRQ;
        cc->tcg_ops->do_interrupt(cs);
        ret = true;
    }
    if (interrupt_request & CPU_INTERRUPT_NMI) {
        unsigned int m_flag_archval;
        if (env->pregs[PR_VR] < 32) {
            m_flag_archval = M_FLAG_V10;
        } else {
            m_flag_archval = M_FLAG_V32;
        }
        if ((env->pregs[PR_CCS] & m_flag_archval)) {
            cs->exception_index = EXCP_NMI;
            cc->tcg_ops->do_interrupt(cs);
            ret = true;
        }
    }

    return ret;
}
Commit	Line	Data
81fdc5f8 TS	1	/*
	2	* CRIS helper routines.
	3	*
	4	* Copyright (c) 2007 AXIS Communications AB
	5	* Written by Edgar E. Iglesias.
	6	*
	7	* This library is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU Lesser General Public
	9	* License as published by the Free Software Foundation; either
bf1b52d1	10	* version 2.1 of the License, or (at your option) any later version.
81fdc5f8 TS	11	*
	12	* This library is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	* Lesser General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU Lesser General Public
8167ee88	18	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
81fdc5f8 TS	19	*/
81fdc5f8 TS	20
23b0d7df	21	#include "qemu/osdep.h"
cd617484	22	#include "qemu/log.h"
81fdc5f8	23	#include "cpu.h"
78271684	24	#include "hw/core/tcg-cpu-ops.h"
81fdc5f8	25	#include "mmu.h"
1de7afc9	26	#include "qemu/host-utils.h"
63c91552	27	#include "exec/exec-all.h"
f08b6170	28	#include "exec/cpu_ldst.h"
c038ec93	29	#include "exec/helper-proto.h"
81fdc5f8	30
d12d51d5 AL	31
	32	//#define CRIS_HELPER_DEBUG
	33
	34
	35	#ifdef CRIS_HELPER_DEBUG
	36	#define D(x) x
3f668b6c	37	#define D_LOG(...) qemu_log(__VA_ARGS__)
d12d51d5	38	#else
e62b5b13	39	#define D(x)
d12d51d5 AL	40	#define D_LOG(...) do { } while (0)
d12d51d5 AL	41	#endif
e62b5b13	42
a1170bfd	43	static void cris_shift_ccs(CPUCRISState *env)
e62b5b13	44	{
21317bc2 AF	45	uint32_t ccs;
	46	/* Apply the ccs shift. */
	47	ccs = env->pregs[PR_CCS];
	48	ccs = ((ccs & 0xc0000000) \| ((ccs << 12) >> 2)) & ~0x3ff;
	49	env->pregs[PR_CCS] = ccs;
e62b5b13 EI	50	}
e62b5b13 EI	51
c038ec93 RH	52	bool cris_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
	53	MMUAccessType access_type, int mmu_idx,
	54	bool probe, uintptr_t retaddr)
81fdc5f8	55	{
7510454e AF	56	CRISCPU *cpu = CRIS_CPU(cs);
7510454e AF	57	CPUCRISState *env = &cpu->env;
21317bc2 AF	58	struct cris_mmu_result res;
21317bc2 AF	59	int prot, miss;
21317bc2 AF	60	target_ulong phy;
21317bc2 AF	61
21317bc2	62	miss = cris_mmu_translate(&res, env, address & TARGET_PAGE_MASK,
c038ec93 RH	63	access_type, mmu_idx, 0);
c038ec93 RH	64	if (likely(!miss)) {
21317bc2 AF	65	/*
	66	* Mask off the cache selection bit. The ETRAX busses do not
	67	* see the top bit.
	68	*/
	69	phy = res.phy & ~0x80000000;
	70	prot = res.prot;
0c591eb0	71	tlb_set_page(cs, address & TARGET_PAGE_MASK, phy,
21317bc2	72	prot, mmu_idx, TARGET_PAGE_SIZE);
c038ec93 RH	73	return true;
	74	}
	75
	76	if (probe) {
	77	return false;
21317bc2	78	}
c038ec93 RH	79
	80	if (cs->exception_index == EXCP_BUSFAULT) {
	81	cpu_abort(cs, "CRIS: Illegal recursive bus fault."
	82	"addr=%" VADDR_PRIx " access_type=%d\n",
	83	address, access_type);
21317bc2	84	}
c038ec93 RH	85
	86	env->pregs[PR_EDA] = address;
	87	cs->exception_index = EXCP_BUSFAULT;
	88	env->fault_vector = res.bf_vec;
	89	if (retaddr) {
3d419a4d	90	if (cpu_restore_state(cs, retaddr)) {
c038ec93 RH	91	/* Evaluate flags after retranslation. */
	92	helper_top_evaluate_flags(env);
	93	}
	94	}
	95	cpu_loop_exit(cs);
	96	}
	97
b21bfeea	98	void crisv10_cpu_do_interrupt(CPUState *cs)
7a977356	99	{
b21bfeea AF	100	CRISCPU *cpu = CRIS_CPU(cs);
b21bfeea AF	101	CPUCRISState *env = &cpu->env;
21317bc2 AF	102	int ex_vec = -1;
	103
	104	D_LOG("exception index=%d interrupt_req=%d\n",
27103424	105	cs->exception_index,
259186a7	106	cs->interrupt_request);
21317bc2	107
d66433ff EI	108	if (env->dslot) {
d66433ff EI	109	/* CRISv10 never takes interrupts while in a delay-slot. */
a47dddd7	110	cpu_abort(cs, "CRIS: Interrupt on delay-slot\n");
d66433ff EI	111	}
d66433ff EI	112
21317bc2	113	assert(!(env->pregs[PR_CCS] & PFIX_FLAG));
27103424	114	switch (cs->exception_index) {
21317bc2	115	case EXCP_BREAK:
8b81968c	116	/* These exceptions are generated by the core itself.
21317bc2 AF	117	ERP should point to the insn following the brk. */
	118	ex_vec = env->trap_vector;
	119	env->pregs[PRV10_BRP] = env->pc;
	120	break;
	121
	122	case EXCP_NMI:
	123	/* NMI is hardwired to vector zero. */
	124	ex_vec = 0;
	125	env->pregs[PR_CCS] &= ~M_FLAG_V10;
	126	env->pregs[PRV10_BRP] = env->pc;
	127	break;
	128
	129	case EXCP_BUSFAULT:
a47dddd7	130	cpu_abort(cs, "Unhandled busfault");
21317bc2 AF	131	break;
	132
	133	default:
	134	/* The interrupt controller gives us the vector. */
	135	ex_vec = env->interrupt_vector;
	136	/* Normal interrupts are taken between
	137	TB's. env->pc is valid here. */
	138	env->pregs[PR_ERP] = env->pc;
	139	break;
	140	}
	141
	142	if (env->pregs[PR_CCS] & U_FLAG) {
	143	/* Swap stack pointers. */
	144	env->pregs[PR_USP] = env->regs[R_SP];
	145	env->regs[R_SP] = env->ksp;
	146	}
	147
	148	/* Now that we are in kernel mode, load the handlers address. */
	149	env->pc = cpu_ldl_code(env, env->pregs[PR_EBP] + ex_vec * 4);
	150	env->locked_irq = 1;
	151	env->pregs[PR_CCS] \|= F_FLAG_V10; /* set F. */
	152
	153	qemu_log_mask(CPU_LOG_INT, "%s isr=%x vec=%x ccs=%x pid=%d erp=%x\n",
	154	__func__, env->pc, ex_vec,
	155	env->pregs[PR_CCS],
	156	env->pregs[PR_PID],
	157	env->pregs[PR_ERP]);
7a977356 EI	158	}
7a977356 EI	159
97a8ea5a	160	void cris_cpu_do_interrupt(CPUState *cs)
81fdc5f8	161	{
97a8ea5a AF	162	CRISCPU *cpu = CRIS_CPU(cs);
97a8ea5a AF	163	CPUCRISState *env = &cpu->env;
21317bc2 AF	164	int ex_vec = -1;
21317bc2 AF	165
21317bc2	166	D_LOG("exception index=%d interrupt_req=%d\n",
27103424	167	cs->exception_index,
259186a7	168	cs->interrupt_request);
21317bc2	169
27103424	170	switch (cs->exception_index) {
21317bc2	171	case EXCP_BREAK:
8b81968c	172	/* These exceptions are generated by the core itself.
21317bc2 AF	173	ERP should point to the insn following the brk. */
	174	ex_vec = env->trap_vector;
	175	env->pregs[PR_ERP] = env->pc;
	176	break;
	177
	178	case EXCP_NMI:
	179	/* NMI is hardwired to vector zero. */
	180	ex_vec = 0;
	181	env->pregs[PR_CCS] &= ~M_FLAG_V32;
	182	env->pregs[PR_NRP] = env->pc;
	183	break;
	184
	185	case EXCP_BUSFAULT:
	186	ex_vec = env->fault_vector;
	187	env->pregs[PR_ERP] = env->pc;
	188	break;
	189
	190	default:
	191	/* The interrupt controller gives us the vector. */
	192	ex_vec = env->interrupt_vector;
	193	/* Normal interrupts are taken between
	194	TB's. env->pc is valid here. */
	195	env->pregs[PR_ERP] = env->pc;
	196	break;
	197	}
	198
	199	/* Fill in the IDX field. */
	200	env->pregs[PR_EXS] = (ex_vec & 0xff) << 8;
	201
	202	if (env->dslot) {
	203	D_LOG("excp isr=%x PC=%x ds=%d SP=%x"
	204	" ERP=%x pid=%x ccs=%x cc=%d %x\n",
	205	ex_vec, env->pc, env->dslot,
	206	env->regs[R_SP],
	207	env->pregs[PR_ERP], env->pregs[PR_PID],
	208	env->pregs[PR_CCS],
	209	env->cc_op, env->cc_mask);
	210	/* We loose the btarget, btaken state here so rexec the
	211	branch. */
	212	env->pregs[PR_ERP] -= env->dslot;
	213	/* Exception starts with dslot cleared. */
	214	env->dslot = 0;
	215	}
7d37435b	216
21317bc2 AF	217	if (env->pregs[PR_CCS] & U_FLAG) {
	218	/* Swap stack pointers. */
	219	env->pregs[PR_USP] = env->regs[R_SP];
	220	env->regs[R_SP] = env->ksp;
	221	}
	222
	223	/* Apply the CRIS CCS shift. Clears U if set. */
	224	cris_shift_ccs(env);
	225
	226	/* Now that we are in kernel mode, load the handlers address.
	227	This load may not fault, real hw leaves that behaviour as
	228	undefined. */
	229	env->pc = cpu_ldl_code(env, env->pregs[PR_EBP] + ex_vec * 4);
	230
8b81968c	231	/* Clear the excption_index to avoid spurious hw_aborts for recursive
21317bc2	232	bus faults. */
27103424	233	cs->exception_index = -1;
21317bc2 AF	234
	235	D_LOG("%s isr=%x vec=%x ccs=%x pid=%d erp=%x\n",
	236	__func__, env->pc, ex_vec,
	237	env->pregs[PR_CCS],
	238	env->pregs[PR_PID],
	239	env->pregs[PR_ERP]);
81fdc5f8 TS	240	}
81fdc5f8 TS	241
00b941e5	242	hwaddr cris_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
81fdc5f8	243	{
00b941e5	244	CRISCPU *cpu = CRIS_CPU(cs);
21317bc2 AF	245	uint32_t phy = addr;
	246	struct cris_mmu_result res;
	247	int miss;
	248
c0ff662f	249	miss = cris_mmu_translate(&res, &cpu->env, addr, MMU_DATA_LOAD, 0, 1);
21317bc2 AF	250	/* If D TLB misses, try I TLB. */
21317bc2 AF	251	if (miss) {
c0ff662f	252	miss = cris_mmu_translate(&res, &cpu->env, addr, MMU_INST_FETCH, 0, 1);
21317bc2 AF	253	}
	254
	255	if (!miss) {
	256	phy = res.phy;
	257	}
	258	D(fprintf(stderr, "%s %x -> %x\n", __func__, addr, phy));
	259	return phy;
81fdc5f8	260	}
5a1f7f44 RH	261
	262	bool cris_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
	263	{
	264	CPUClass *cc = CPU_GET_CLASS(cs);
	265	CRISCPU *cpu = CRIS_CPU(cs);
	266	CPUCRISState *env = &cpu->env;
	267	bool ret = false;
	268
	269	if (interrupt_request & CPU_INTERRUPT_HARD
	270	&& (env->pregs[PR_CCS] & I_FLAG)
	271	&& !env->locked_irq) {
	272	cs->exception_index = EXCP_IRQ;
78271684	273	cc->tcg_ops->do_interrupt(cs);
5a1f7f44 RH	274	ret = true;
	275	}
	276	if (interrupt_request & CPU_INTERRUPT_NMI) {
	277	unsigned int m_flag_archval;
	278	if (env->pregs[PR_VR] < 32) {
	279	m_flag_archval = M_FLAG_V10;
	280	} else {
	281	m_flag_archval = M_FLAG_V32;
	282	}
	283	if ((env->pregs[PR_CCS] & m_flag_archval)) {
	284	cs->exception_index = EXCP_NMI;
78271684	285	cc->tcg_ops->do_interrupt(cs);
5a1f7f44 RH	286	ret = true;
	287	}
	288	}
	289
	290	return ret;
	291	}