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1118d7fa | 1 | /* |
b9f0326b | 2 | * Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved. |
1118d7fa TS |
3 | * |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License as published by | |
6 | * the Free Software Foundation; either version 2 of the License, or | |
7 | * (at your option) any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, see <http://www.gnu.org/licenses/>. | |
16 | */ | |
17 | ||
18 | /* Keep this as the first attribute: */ | |
19 | DEF_ATTRIB(AA_DUMMY, "Dummy Zeroth Attribute", "", "") | |
20 | ||
21 | /* Misc */ | |
22 | DEF_ATTRIB(EXTENSION, "Extension instruction", "", "") | |
23 | ||
24 | DEF_ATTRIB(PRIV, "Not available in user or guest mode", "", "") | |
25 | DEF_ATTRIB(GUEST, "Not available in user mode", "", "") | |
26 | ||
27 | DEF_ATTRIB(FPOP, "Floating Point Operation", "", "") | |
28 | ||
29 | DEF_ATTRIB(EXTENDABLE, "Immediate may be extended", "", "") | |
30 | ||
31 | DEF_ATTRIB(ARCHV2, "V2 architecture", "", "") | |
32 | DEF_ATTRIB(ARCHV3, "V3 architecture", "", "") | |
33 | DEF_ATTRIB(ARCHV4, "V4 architecture", "", "") | |
34 | DEF_ATTRIB(ARCHV5, "V5 architecture", "", "") | |
35 | ||
36 | DEF_ATTRIB(SUBINSN, "sub-instruction", "", "") | |
37 | ||
38 | /* Load and Store attributes */ | |
39 | DEF_ATTRIB(LOAD, "Loads from memory", "", "") | |
40 | DEF_ATTRIB(STORE, "Stores to memory", "", "") | |
b772528a TS |
41 | DEF_ATTRIB(STOREIMMED, "Stores immed to memory", "", "") |
42 | DEF_ATTRIB(MEMSIZE_0B, "Memory width is 0 byte", "", "") | |
43 | DEF_ATTRIB(MEMSIZE_1B, "Memory width is 1 byte", "", "") | |
44 | DEF_ATTRIB(MEMSIZE_2B, "Memory width is 2 bytes", "", "") | |
45 | DEF_ATTRIB(MEMSIZE_4B, "Memory width is 4 bytes", "", "") | |
46 | DEF_ATTRIB(MEMSIZE_8B, "Memory width is 8 bytes", "", "") | |
4d13bb51 | 47 | DEF_ATTRIB(SCALAR_LOAD, "Load is scalar", "", "") |
e2be9a5c | 48 | DEF_ATTRIB(SCALAR_STORE, "Store is scalar", "", "") |
b772528a TS |
49 | DEF_ATTRIB(REGWRSIZE_1B, "Memory width is 1 byte", "", "") |
50 | DEF_ATTRIB(REGWRSIZE_2B, "Memory width is 2 bytes", "", "") | |
51 | DEF_ATTRIB(REGWRSIZE_4B, "Memory width is 4 bytes", "", "") | |
52 | DEF_ATTRIB(REGWRSIZE_8B, "Memory width is 8 bytes", "", "") | |
1118d7fa TS |
53 | DEF_ATTRIB(MEMLIKE, "Memory-like instruction", "", "") |
54 | DEF_ATTRIB(MEMLIKE_PACKET_RULES, "follows Memory-like packet rules", "", "") | |
406c74f2 TS |
55 | DEF_ATTRIB(RELEASE, "Releases a lock", "", "") |
56 | DEF_ATTRIB(ACQUIRE, "Acquires a lock", "", "") | |
57 | ||
58 | DEF_ATTRIB(RLS_INNER, "Store release inner visibility", "", "") | |
59 | DEF_ATTRIB(RLS_ALL_THREAD, "Store release among all threads", "", "") | |
60 | DEF_ATTRIB(RLS_SAME_THREAD, "Store release with the same thread", "", "") | |
1118d7fa | 61 | |
828a2107 TS |
62 | /* V6 Vector attributes */ |
63 | DEF_ATTRIB(CVI, "Executes on the HVX extension", "", "") | |
64 | ||
65 | DEF_ATTRIB(CVI_NEW, "New value memory instruction executes on HVX", "", "") | |
66 | DEF_ATTRIB(CVI_VM, "Memory instruction executes on HVX", "", "") | |
67 | DEF_ATTRIB(CVI_VP, "Permute instruction executes on HVX", "", "") | |
68 | DEF_ATTRIB(CVI_VP_VS, "Double vector permute/shft insn executes on HVX", "", "") | |
69 | DEF_ATTRIB(CVI_VX, "Multiply instruction executes on HVX", "", "") | |
70 | DEF_ATTRIB(CVI_VX_DV, "Double vector multiply insn executes on HVX", "", "") | |
71 | DEF_ATTRIB(CVI_VS, "Shift instruction executes on HVX", "", "") | |
b2f20c2c | 72 | DEF_ATTRIB(CVI_VS_3SRC, "This shift needs to borrow a source register", "", "") |
828a2107 TS |
73 | DEF_ATTRIB(CVI_VS_VX, "Permute/shift and multiply insn executes on HVX", "", "") |
74 | DEF_ATTRIB(CVI_VA, "ALU instruction executes on HVX", "", "") | |
75 | DEF_ATTRIB(CVI_VA_DV, "Double vector alu instruction executes on HVX", "", "") | |
76 | DEF_ATTRIB(CVI_4SLOT, "Consumes all the vector execution resources", "", "") | |
77 | DEF_ATTRIB(CVI_TMP, "Transient Memory Load not written to register", "", "") | |
b2f20c2c | 78 | DEF_ATTRIB(CVI_REMAP, "Register Renaming not written to register file", "", "") |
828a2107 TS |
79 | DEF_ATTRIB(CVI_GATHER, "CVI Gather operation", "", "") |
80 | DEF_ATTRIB(CVI_SCATTER, "CVI Scatter operation", "", "") | |
81 | DEF_ATTRIB(CVI_SCATTER_RELEASE, "CVI Store Release for scatter", "", "") | |
82 | DEF_ATTRIB(CVI_TMP_DST, "CVI instruction that doesn't write a register", "", "") | |
83 | DEF_ATTRIB(CVI_SLOT23, "Can execute in slot 2 or slot 3 (HVX)", "", "") | |
84 | ||
406c74f2 | 85 | DEF_ATTRIB(VTCM_ALLBANK_ACCESS, "Allocates in all VTCM schedulers.", "", "") |
1118d7fa TS |
86 | |
87 | /* Change-of-flow attributes */ | |
88 | DEF_ATTRIB(JUMP, "Jump-type instruction", "", "") | |
89 | DEF_ATTRIB(INDIRECT, "Absolute register jump", "", "") | |
90 | DEF_ATTRIB(CALL, "Function call instruction", "", "") | |
91 | DEF_ATTRIB(COF, "Change-of-flow instruction", "", "") | |
59958d89 | 92 | DEF_ATTRIB(HINTED_COF, "This instruction is a hinted change-of-flow", "", "") |
1118d7fa TS |
93 | DEF_ATTRIB(CONDEXEC, "May be cancelled by a predicate", "", "") |
94 | DEF_ATTRIB(DOTNEWVALUE, "Uses a register value generated in this pkt", "", "") | |
95 | DEF_ATTRIB(NEWCMPJUMP, "Compound compare and jump", "", "") | |
b772528a TS |
96 | DEF_ATTRIB(NVSTORE, "New-value store", "", "") |
97 | DEF_ATTRIB(MEMOP, "memop", "", "") | |
98 | ||
99 | DEF_ATTRIB(ROPS_2, "Compound instruction worth 2 RISC-ops", "", "") | |
100 | DEF_ATTRIB(ROPS_3, "Compound instruction worth 3 RISC-ops", "", "") | |
1118d7fa TS |
101 | |
102 | /* access to implicit registers */ | |
103 | DEF_ATTRIB(IMPLICIT_WRITES_LR, "Writes the link register", "", "UREG.LR") | |
104 | DEF_ATTRIB(IMPLICIT_WRITES_SP, "Writes the stack pointer", "", "UREG.SP") | |
105 | DEF_ATTRIB(IMPLICIT_WRITES_FP, "Writes the frame pointer", "", "UREG.FP") | |
106 | DEF_ATTRIB(IMPLICIT_WRITES_LC0, "Writes loop count for loop 0", "", "UREG.LC0") | |
107 | DEF_ATTRIB(IMPLICIT_WRITES_LC1, "Writes loop count for loop 1", "", "UREG.LC1") | |
108 | DEF_ATTRIB(IMPLICIT_WRITES_SA0, "Writes start addr for loop 0", "", "UREG.SA0") | |
109 | DEF_ATTRIB(IMPLICIT_WRITES_SA1, "Writes start addr for loop 1", "", "UREG.SA1") | |
110 | DEF_ATTRIB(IMPLICIT_WRITES_P0, "Writes Predicate 0", "", "UREG.P0") | |
111 | DEF_ATTRIB(IMPLICIT_WRITES_P1, "Writes Predicate 1", "", "UREG.P1") | |
112 | DEF_ATTRIB(IMPLICIT_WRITES_P2, "Writes Predicate 1", "", "UREG.P2") | |
113 | DEF_ATTRIB(IMPLICIT_WRITES_P3, "May write Predicate 3", "", "UREG.P3") | |
114 | DEF_ATTRIB(IMPLICIT_READS_PC, "Reads the PC register", "", "") | |
b9f0326b TS |
115 | DEF_ATTRIB(IMPLICIT_READS_P0, "Reads the P0 register", "", "") |
116 | DEF_ATTRIB(IMPLICIT_READS_P1, "Reads the P1 register", "", "") | |
117 | DEF_ATTRIB(IMPLICIT_READS_P2, "Reads the P2 register", "", "") | |
118 | DEF_ATTRIB(IMPLICIT_READS_P3, "Reads the P3 register", "", "") | |
b9dd6ff9 | 119 | DEF_ATTRIB(IMPLICIT_WRITES_USR, "May write USR", "", "") |
1118d7fa | 120 | DEF_ATTRIB(WRITES_PRED_REG, "Writes a predicate register", "", "") |
b772528a TS |
121 | DEF_ATTRIB(COMMUTES, "The operation is communitive", "", "") |
122 | DEF_ATTRIB(DEALLOCRET, "dealloc_return", "", "") | |
123 | DEF_ATTRIB(DEALLOCFRAME, "deallocframe", "", "") | |
1118d7fa TS |
124 | |
125 | DEF_ATTRIB(CRSLOT23, "Can execute in slot 2 or slot 3 (CR)", "", "") | |
126 | DEF_ATTRIB(IT_NOP, "nop instruction", "", "") | |
127 | DEF_ATTRIB(IT_EXTENDER, "constant extender instruction", "", "") | |
128 | ||
129 | ||
130 | /* Restrictions to make note of */ | |
b772528a TS |
131 | DEF_ATTRIB(RESTRICT_COF_MAX1, "One change-of-flow per packet", "", "") |
132 | DEF_ATTRIB(RESTRICT_NOPACKET, "Not allowed in a packet", "", "") | |
1118d7fa TS |
133 | DEF_ATTRIB(RESTRICT_SLOT0ONLY, "Must execute on slot0", "", "") |
134 | DEF_ATTRIB(RESTRICT_SLOT1ONLY, "Must execute on slot1", "", "") | |
135 | DEF_ATTRIB(RESTRICT_SLOT2ONLY, "Must execute on slot2", "", "") | |
136 | DEF_ATTRIB(RESTRICT_SLOT3ONLY, "Must execute on slot3", "", "") | |
137 | DEF_ATTRIB(RESTRICT_NOSLOT1, "No slot 1 instruction in parallel", "", "") | |
138 | DEF_ATTRIB(RESTRICT_PREFERSLOT0, "Try to encode into slot 0", "", "") | |
b772528a | 139 | DEF_ATTRIB(RESTRICT_PACKET_AXOK, "May exist with A-type or X-type", "", "") |
1118d7fa TS |
140 | |
141 | DEF_ATTRIB(ICOP, "Instruction cache op", "", "") | |
142 | ||
143 | DEF_ATTRIB(HWLOOP0_END, "Ends HW loop0", "", "") | |
144 | DEF_ATTRIB(HWLOOP1_END, "Ends HW loop1", "", "") | |
b772528a | 145 | DEF_ATTRIB(RET_TYPE, "return type", "", "") |
1118d7fa TS |
146 | DEF_ATTRIB(DCZEROA, "dczeroa type", "", "") |
147 | DEF_ATTRIB(ICFLUSHOP, "icflush op type", "", "") | |
148 | DEF_ATTRIB(DCFLUSHOP, "dcflush op type", "", "") | |
828a2107 | 149 | DEF_ATTRIB(L2FLUSHOP, "l2flush op type", "", "") |
1118d7fa TS |
150 | DEF_ATTRIB(DCFETCH, "dcfetch type", "", "") |
151 | ||
152 | DEF_ATTRIB(L2FETCH, "Instruction is l2fetch type", "", "") | |
153 | ||
154 | DEF_ATTRIB(ICINVA, "icinva", "", "") | |
155 | DEF_ATTRIB(DCCLEANINVA, "dccleaninva", "", "") | |
156 | ||
b2f20c2c TS |
157 | DEF_ATTRIB(NO_INTRINSIC, "Don't generate an intrisic", "", "") |
158 | ||
b772528a TS |
159 | /* Documentation Notes */ |
160 | DEF_ATTRIB(NOTE_CONDITIONAL, "can be conditionally executed", "", "") | |
161 | DEF_ATTRIB(NOTE_NEWVAL_SLOT0, "New-value oprnd must execute on slot 0", "", "") | |
162 | DEF_ATTRIB(NOTE_PRIV, "Monitor-level feature", "", "") | |
163 | DEF_ATTRIB(NOTE_NOPACKET, "solo instruction", "", "") | |
164 | DEF_ATTRIB(NOTE_AXOK, "May only be grouped with ALU32 or non-FP XTYPE.", "", "") | |
165 | DEF_ATTRIB(NOTE_LATEPRED, "The predicate can not be used as a .new", "", "") | |
166 | DEF_ATTRIB(NOTE_NVSLOT0, "Can execute only in slot 0 (ST)", "", "") | |
b2f20c2c TS |
167 | DEF_ATTRIB(NOTE_NOVP, "Cannot be paired with a HVX permute instruction", "", "") |
168 | DEF_ATTRIB(NOTE_VA_UNARY, "Combined with HVX ALU op (must be unary)", "", "") | |
b772528a | 169 | |
b2f20c2c TS |
170 | /* V6 MMVector Notes for Documentation */ |
171 | DEF_ATTRIB(NOTE_SHIFT_RESOURCE, "Uses the HVX shift resource.", "", "") | |
b772528a TS |
172 | /* Restrictions to make note of */ |
173 | DEF_ATTRIB(RESTRICT_NOSLOT1_STORE, "Packet must not have slot 1 store", "", "") | |
174 | DEF_ATTRIB(RESTRICT_LATEPRED, "Predicate can not be used as a .new.", "", "") | |
175 | ||
1118d7fa TS |
176 | /* Keep this as the last attribute: */ |
177 | DEF_ATTRIB(ZZ_LASTATTRIB, "Last attribute in the file", "", "") |