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45183ccd TS |
1 | /* |
2 | * Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License as published by | |
6 | * the Free Software Foundation; either version 2 of the License, or | |
7 | * (at your option) any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, see <http://www.gnu.org/licenses/>. | |
16 | */ | |
17 | ||
18 | #include "qemu/osdep.h" | |
45183ccd TS |
19 | #include "qemu/qemu-print.h" |
20 | #include "cpu.h" | |
21 | #include "internal.h" | |
22 | #include "exec/exec-all.h" | |
23 | #include "qapi/error.h" | |
24 | #include "hw/qdev-properties.h" | |
c0336c87 | 25 | #include "fpu/softfloat-helpers.h" |
ba445655 | 26 | #include "tcg/tcg.h" |
45183ccd TS |
27 | |
28 | static void hexagon_v67_cpu_init(Object *obj) | |
29 | { | |
30 | } | |
31 | ||
32 | static ObjectClass *hexagon_cpu_class_by_name(const char *cpu_model) | |
33 | { | |
34 | ObjectClass *oc; | |
35 | char *typename; | |
36 | char **cpuname; | |
37 | ||
38 | cpuname = g_strsplit(cpu_model, ",", 1); | |
39 | typename = g_strdup_printf(HEXAGON_CPU_TYPE_NAME("%s"), cpuname[0]); | |
40 | oc = object_class_by_name(typename); | |
41 | g_strfreev(cpuname); | |
42 | g_free(typename); | |
43 | if (!oc || !object_class_dynamic_cast(oc, TYPE_HEXAGON_CPU) || | |
44 | object_class_is_abstract(oc)) { | |
45 | return NULL; | |
46 | } | |
47 | return oc; | |
48 | } | |
49 | ||
50 | static Property hexagon_lldb_compat_property = | |
51 | DEFINE_PROP_BOOL("lldb-compat", HexagonCPU, lldb_compat, false); | |
52 | static Property hexagon_lldb_stack_adjust_property = | |
53 | DEFINE_PROP_UNSIGNED("lldb-stack-adjust", HexagonCPU, lldb_stack_adjust, | |
54 | 0, qdev_prop_uint32, target_ulong); | |
55 | ||
56 | const char * const hexagon_regnames[TOTAL_PER_THREAD_REGS] = { | |
57 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
58 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
59 | "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", | |
60 | "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", | |
61 | "sa0", "lc0", "sa1", "lc1", "p3_0", "c5", "m0", "m1", | |
62 | "usr", "pc", "ugp", "gp", "cs0", "cs1", "c14", "c15", | |
40438b67 | 63 | "c16", "c17", "c18", "c19", "pkt_cnt", "insn_cnt", "hvx_cnt", "c23", |
45183ccd TS |
64 | "c24", "c25", "c26", "c27", "c28", "c29", "c30", "c31", |
65 | }; | |
66 | ||
67 | /* | |
68 | * One of the main debugging techniques is to use "-d cpu" and compare against | |
69 | * LLDB output when single stepping. However, the target and qemu put the | |
70 | * stacks at different locations. This is used to compensate so the diff is | |
71 | * cleaner. | |
72 | */ | |
2d27cebb | 73 | static target_ulong adjust_stack_ptrs(CPUHexagonState *env, target_ulong addr) |
45183ccd | 74 | { |
7d9ab202 | 75 | HexagonCPU *cpu = env_archcpu(env); |
45183ccd TS |
76 | target_ulong stack_adjust = cpu->lldb_stack_adjust; |
77 | target_ulong stack_start = env->stack_start; | |
78 | target_ulong stack_size = 0x10000; | |
79 | ||
80 | if (stack_adjust == 0) { | |
81 | return addr; | |
82 | } | |
83 | ||
84 | if (stack_start + 0x1000 >= addr && addr >= (stack_start - stack_size)) { | |
85 | return addr - stack_adjust; | |
86 | } | |
87 | return addr; | |
88 | } | |
89 | ||
72895676 | 90 | /* HEX_REG_P3_0_ALIASED (aka C4) is an alias for the predicate registers */ |
2d27cebb | 91 | static target_ulong read_p3_0(CPUHexagonState *env) |
45183ccd TS |
92 | { |
93 | int32_t control_reg = 0; | |
94 | int i; | |
95 | for (i = NUM_PREGS - 1; i >= 0; i--) { | |
96 | control_reg <<= 8; | |
97 | control_reg |= env->pred[i] & 0xff; | |
98 | } | |
99 | return control_reg; | |
100 | } | |
101 | ||
102 | static void print_reg(FILE *f, CPUHexagonState *env, int regnum) | |
103 | { | |
104 | target_ulong value; | |
105 | ||
72895676 | 106 | if (regnum == HEX_REG_P3_0_ALIASED) { |
45183ccd TS |
107 | value = read_p3_0(env); |
108 | } else { | |
109 | value = regnum < 32 ? adjust_stack_ptrs(env, env->gpr[regnum]) | |
110 | : env->gpr[regnum]; | |
111 | } | |
112 | ||
113 | qemu_fprintf(f, " %s = 0x" TARGET_FMT_lx "\n", | |
114 | hexagon_regnames[regnum], value); | |
115 | } | |
116 | ||
a1559537 TS |
117 | static void print_vreg(FILE *f, CPUHexagonState *env, int regnum, |
118 | bool skip_if_zero) | |
119 | { | |
120 | if (skip_if_zero) { | |
121 | bool nonzero_found = false; | |
122 | for (int i = 0; i < MAX_VEC_SIZE_BYTES; i++) { | |
123 | if (env->VRegs[regnum].ub[i] != 0) { | |
124 | nonzero_found = true; | |
125 | break; | |
126 | } | |
127 | } | |
128 | if (!nonzero_found) { | |
129 | return; | |
130 | } | |
131 | } | |
132 | ||
133 | qemu_fprintf(f, " v%d = ( ", regnum); | |
134 | qemu_fprintf(f, "0x%02x", env->VRegs[regnum].ub[MAX_VEC_SIZE_BYTES - 1]); | |
135 | for (int i = MAX_VEC_SIZE_BYTES - 2; i >= 0; i--) { | |
136 | qemu_fprintf(f, ", 0x%02x", env->VRegs[regnum].ub[i]); | |
137 | } | |
138 | qemu_fprintf(f, " )\n"); | |
139 | } | |
140 | ||
141 | void hexagon_debug_vreg(CPUHexagonState *env, int regnum) | |
142 | { | |
143 | print_vreg(stdout, env, regnum, false); | |
144 | } | |
145 | ||
146 | static void print_qreg(FILE *f, CPUHexagonState *env, int regnum, | |
147 | bool skip_if_zero) | |
148 | { | |
149 | if (skip_if_zero) { | |
150 | bool nonzero_found = false; | |
151 | for (int i = 0; i < MAX_VEC_SIZE_BYTES / 8; i++) { | |
152 | if (env->QRegs[regnum].ub[i] != 0) { | |
153 | nonzero_found = true; | |
154 | break; | |
155 | } | |
156 | } | |
157 | if (!nonzero_found) { | |
158 | return; | |
159 | } | |
160 | } | |
161 | ||
162 | qemu_fprintf(f, " q%d = ( ", regnum); | |
163 | qemu_fprintf(f, "0x%02x", | |
164 | env->QRegs[regnum].ub[MAX_VEC_SIZE_BYTES / 8 - 1]); | |
165 | for (int i = MAX_VEC_SIZE_BYTES / 8 - 2; i >= 0; i--) { | |
166 | qemu_fprintf(f, ", 0x%02x", env->QRegs[regnum].ub[i]); | |
167 | } | |
168 | qemu_fprintf(f, " )\n"); | |
169 | } | |
170 | ||
171 | void hexagon_debug_qreg(CPUHexagonState *env, int regnum) | |
172 | { | |
173 | print_qreg(stdout, env, regnum, false); | |
174 | } | |
175 | ||
176 | static void hexagon_dump(CPUHexagonState *env, FILE *f, int flags) | |
45183ccd | 177 | { |
7d9ab202 | 178 | HexagonCPU *cpu = env_archcpu(env); |
45183ccd TS |
179 | |
180 | if (cpu->lldb_compat) { | |
181 | /* | |
182 | * When comparing with LLDB, it doesn't step through single-cycle | |
183 | * hardware loops the same way. So, we just skip them here | |
184 | */ | |
185 | if (env->gpr[HEX_REG_PC] == env->last_pc_dumped) { | |
186 | return; | |
187 | } | |
188 | env->last_pc_dumped = env->gpr[HEX_REG_PC]; | |
189 | } | |
190 | ||
191 | qemu_fprintf(f, "General Purpose Registers = {\n"); | |
192 | for (int i = 0; i < 32; i++) { | |
193 | print_reg(f, env, i); | |
194 | } | |
195 | print_reg(f, env, HEX_REG_SA0); | |
196 | print_reg(f, env, HEX_REG_LC0); | |
197 | print_reg(f, env, HEX_REG_SA1); | |
198 | print_reg(f, env, HEX_REG_LC1); | |
199 | print_reg(f, env, HEX_REG_M0); | |
200 | print_reg(f, env, HEX_REG_M1); | |
201 | print_reg(f, env, HEX_REG_USR); | |
72895676 | 202 | print_reg(f, env, HEX_REG_P3_0_ALIASED); |
45183ccd TS |
203 | print_reg(f, env, HEX_REG_GP); |
204 | print_reg(f, env, HEX_REG_UGP); | |
205 | print_reg(f, env, HEX_REG_PC); | |
206 | #ifdef CONFIG_USER_ONLY | |
207 | /* | |
208 | * Not modelled in user mode, print junk to minimize the diff's | |
209 | * with LLDB output | |
210 | */ | |
211 | qemu_fprintf(f, " cause = 0x000000db\n"); | |
212 | qemu_fprintf(f, " badva = 0x00000000\n"); | |
213 | qemu_fprintf(f, " cs0 = 0x00000000\n"); | |
214 | qemu_fprintf(f, " cs1 = 0x00000000\n"); | |
215 | #else | |
216 | print_reg(f, env, HEX_REG_CAUSE); | |
217 | print_reg(f, env, HEX_REG_BADVA); | |
218 | print_reg(f, env, HEX_REG_CS0); | |
219 | print_reg(f, env, HEX_REG_CS1); | |
220 | #endif | |
221 | qemu_fprintf(f, "}\n"); | |
a1559537 TS |
222 | |
223 | if (flags & CPU_DUMP_FPU) { | |
224 | qemu_fprintf(f, "Vector Registers = {\n"); | |
225 | for (int i = 0; i < NUM_VREGS; i++) { | |
226 | print_vreg(f, env, i, true); | |
227 | } | |
228 | for (int i = 0; i < NUM_QREGS; i++) { | |
229 | print_qreg(f, env, i, true); | |
230 | } | |
231 | qemu_fprintf(f, "}\n"); | |
232 | } | |
45183ccd TS |
233 | } |
234 | ||
235 | static void hexagon_dump_state(CPUState *cs, FILE *f, int flags) | |
236 | { | |
237 | HexagonCPU *cpu = HEXAGON_CPU(cs); | |
238 | CPUHexagonState *env = &cpu->env; | |
239 | ||
a1559537 | 240 | hexagon_dump(env, f, flags); |
45183ccd TS |
241 | } |
242 | ||
243 | void hexagon_debug(CPUHexagonState *env) | |
244 | { | |
a1559537 | 245 | hexagon_dump(env, stdout, CPU_DUMP_FPU); |
45183ccd TS |
246 | } |
247 | ||
248 | static void hexagon_cpu_set_pc(CPUState *cs, vaddr value) | |
249 | { | |
250 | HexagonCPU *cpu = HEXAGON_CPU(cs); | |
251 | CPUHexagonState *env = &cpu->env; | |
252 | env->gpr[HEX_REG_PC] = value; | |
253 | } | |
254 | ||
e4fdf9df RH |
255 | static vaddr hexagon_cpu_get_pc(CPUState *cs) |
256 | { | |
257 | HexagonCPU *cpu = HEXAGON_CPU(cs); | |
258 | CPUHexagonState *env = &cpu->env; | |
259 | return env->gpr[HEX_REG_PC]; | |
260 | } | |
261 | ||
45183ccd TS |
262 | static void hexagon_cpu_synchronize_from_tb(CPUState *cs, |
263 | const TranslationBlock *tb) | |
264 | { | |
265 | HexagonCPU *cpu = HEXAGON_CPU(cs); | |
266 | CPUHexagonState *env = &cpu->env; | |
ba445655 AJ |
267 | tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL)); |
268 | env->gpr[HEX_REG_PC] = tb->pc; | |
45183ccd TS |
269 | } |
270 | ||
271 | static bool hexagon_cpu_has_work(CPUState *cs) | |
272 | { | |
273 | return true; | |
274 | } | |
275 | ||
90157814 RH |
276 | static void hexagon_restore_state_to_opc(CPUState *cs, |
277 | const TranslationBlock *tb, | |
278 | const uint64_t *data) | |
45183ccd | 279 | { |
90157814 RH |
280 | HexagonCPU *cpu = HEXAGON_CPU(cs); |
281 | CPUHexagonState *env = &cpu->env; | |
282 | ||
45183ccd TS |
283 | env->gpr[HEX_REG_PC] = data[0]; |
284 | } | |
285 | ||
ab85156d | 286 | static void hexagon_cpu_reset_hold(Object *obj) |
45183ccd | 287 | { |
ab85156d | 288 | CPUState *cs = CPU(obj); |
45183ccd TS |
289 | HexagonCPU *cpu = HEXAGON_CPU(cs); |
290 | HexagonCPUClass *mcc = HEXAGON_CPU_GET_CLASS(cpu); | |
c0336c87 | 291 | CPUHexagonState *env = &cpu->env; |
45183ccd | 292 | |
ab85156d PM |
293 | if (mcc->parent_phases.hold) { |
294 | mcc->parent_phases.hold(obj); | |
295 | } | |
c0336c87 TS |
296 | |
297 | set_default_nan_mode(1, &env->fp_status); | |
298 | set_float_detect_tininess(float_tininess_before_rounding, &env->fp_status); | |
45183ccd TS |
299 | } |
300 | ||
301 | static void hexagon_cpu_disas_set_info(CPUState *s, disassemble_info *info) | |
302 | { | |
303 | info->print_insn = print_insn_hexagon; | |
304 | } | |
305 | ||
306 | static void hexagon_cpu_realize(DeviceState *dev, Error **errp) | |
307 | { | |
308 | CPUState *cs = CPU(dev); | |
309 | HexagonCPUClass *mcc = HEXAGON_CPU_GET_CLASS(dev); | |
310 | Error *local_err = NULL; | |
311 | ||
312 | cpu_exec_realizefn(cs, &local_err); | |
313 | if (local_err != NULL) { | |
314 | error_propagate(errp, local_err); | |
315 | return; | |
316 | } | |
317 | ||
318 | qemu_init_vcpu(cs); | |
319 | cpu_reset(cs); | |
320 | ||
321 | mcc->parent_realize(dev, errp); | |
322 | } | |
323 | ||
324 | static void hexagon_cpu_init(Object *obj) | |
325 | { | |
326 | HexagonCPU *cpu = HEXAGON_CPU(obj); | |
327 | ||
328 | cpu_set_cpustate_pointers(cpu); | |
329 | qdev_property_add_static(DEVICE(obj), &hexagon_lldb_compat_property); | |
330 | qdev_property_add_static(DEVICE(obj), &hexagon_lldb_stack_adjust_property); | |
331 | } | |
332 | ||
45183ccd TS |
333 | #include "hw/core/tcg-cpu-ops.h" |
334 | ||
11906557 | 335 | static const struct TCGCPUOps hexagon_tcg_ops = { |
45183ccd TS |
336 | .initialize = hexagon_translate_init, |
337 | .synchronize_from_tb = hexagon_cpu_synchronize_from_tb, | |
90157814 | 338 | .restore_state_to_opc = hexagon_restore_state_to_opc, |
45183ccd TS |
339 | }; |
340 | ||
341 | static void hexagon_cpu_class_init(ObjectClass *c, void *data) | |
342 | { | |
343 | HexagonCPUClass *mcc = HEXAGON_CPU_CLASS(c); | |
344 | CPUClass *cc = CPU_CLASS(c); | |
345 | DeviceClass *dc = DEVICE_CLASS(c); | |
ab85156d | 346 | ResettableClass *rc = RESETTABLE_CLASS(c); |
45183ccd TS |
347 | |
348 | device_class_set_parent_realize(dc, hexagon_cpu_realize, | |
349 | &mcc->parent_realize); | |
350 | ||
ab85156d PM |
351 | resettable_class_set_parent_phases(rc, NULL, hexagon_cpu_reset_hold, NULL, |
352 | &mcc->parent_phases); | |
45183ccd TS |
353 | |
354 | cc->class_by_name = hexagon_cpu_class_by_name; | |
355 | cc->has_work = hexagon_cpu_has_work; | |
356 | cc->dump_state = hexagon_dump_state; | |
357 | cc->set_pc = hexagon_cpu_set_pc; | |
e4fdf9df | 358 | cc->get_pc = hexagon_cpu_get_pc; |
45183ccd TS |
359 | cc->gdb_read_register = hexagon_gdb_read_register; |
360 | cc->gdb_write_register = hexagon_gdb_write_register; | |
a1559537 | 361 | cc->gdb_num_core_regs = TOTAL_PER_THREAD_REGS + NUM_VREGS + NUM_QREGS; |
45183ccd TS |
362 | cc->gdb_stop_before_watchpoint = true; |
363 | cc->disas_set_info = hexagon_cpu_disas_set_info; | |
364 | cc->tcg_ops = &hexagon_tcg_ops; | |
365 | } | |
366 | ||
367 | #define DEFINE_CPU(type_name, initfn) \ | |
368 | { \ | |
369 | .name = type_name, \ | |
370 | .parent = TYPE_HEXAGON_CPU, \ | |
371 | .instance_init = initfn \ | |
372 | } | |
373 | ||
374 | static const TypeInfo hexagon_cpu_type_infos[] = { | |
375 | { | |
376 | .name = TYPE_HEXAGON_CPU, | |
377 | .parent = TYPE_CPU, | |
378 | .instance_size = sizeof(HexagonCPU), | |
379 | .instance_init = hexagon_cpu_init, | |
380 | .abstract = true, | |
381 | .class_size = sizeof(HexagonCPUClass), | |
382 | .class_init = hexagon_cpu_class_init, | |
383 | }, | |
384 | DEFINE_CPU(TYPE_HEXAGON_CPU_V67, hexagon_v67_cpu_init), | |
385 | }; | |
386 | ||
387 | DEFINE_TYPES(hexagon_cpu_type_infos) |