]>
Commit | Line | Data |
---|---|---|
6542aa2e TS |
1 | /* |
2 | * Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License as published by | |
6 | * the Free Software Foundation; either version 2 of the License, or | |
7 | * (at your option) any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, see <http://www.gnu.org/licenses/>. | |
16 | */ | |
17 | ||
18 | #ifndef HEXAGON_GEN_TCG_H | |
19 | #define HEXAGON_GEN_TCG_H | |
20 | ||
21 | /* | |
22 | * Here is a primer to understand the tag names for load/store instructions | |
23 | * | |
24 | * Data types | |
25 | * b signed byte r0 = memb(r2+#0) | |
26 | * ub unsigned byte r0 = memub(r2+#0) | |
27 | * h signed half word (16 bits) r0 = memh(r2+#0) | |
28 | * uh unsigned half word r0 = memuh(r2+#0) | |
29 | * i integer (32 bits) r0 = memw(r2+#0) | |
30 | * d double word (64 bits) r1:0 = memd(r2+#0) | |
31 | * | |
32 | * Addressing modes | |
33 | * _io indirect with offset r0 = memw(r1+#4) | |
34 | * _ur absolute with register offset r0 = memw(r1<<#4+##variable) | |
35 | * _rr indirect with register offset r0 = memw(r1+r4<<#2) | |
36 | * gp global pointer relative r0 = memw(gp+#200) | |
37 | * _sp stack pointer relative r0 = memw(r29+#12) | |
38 | * _ap absolute set r0 = memw(r1=##variable) | |
39 | * _pr post increment register r0 = memw(r1++m1) | |
af7f1821 | 40 | * _pbr post increment bit reverse r0 = memw(r1++m1:brev) |
6542aa2e | 41 | * _pi post increment immediate r0 = memb(r1++#1) |
46ef47e2 TS |
42 | * _pci post increment circular immediate r0 = memw(r1++#4:circ(m0)) |
43 | * _pcr post increment circular register r0 = memw(r1++I:circ(m0)) | |
6542aa2e TS |
44 | */ |
45 | ||
46 | /* Macros for complex addressing modes */ | |
47 | #define GET_EA_ap \ | |
48 | do { \ | |
49 | fEA_IMM(UiV); \ | |
50 | tcg_gen_movi_tl(ReV, UiV); \ | |
51 | } while (0) | |
52 | #define GET_EA_pr \ | |
53 | do { \ | |
54 | fEA_REG(RxV); \ | |
55 | fPM_M(RxV, MuV); \ | |
56 | } while (0) | |
af7f1821 TS |
57 | #define GET_EA_pbr \ |
58 | do { \ | |
59 | gen_helper_fbrev(EA, RxV); \ | |
60 | tcg_gen_add_tl(RxV, RxV, MuV); \ | |
61 | } while (0) | |
6542aa2e TS |
62 | #define GET_EA_pi \ |
63 | do { \ | |
64 | fEA_REG(RxV); \ | |
65 | fPM_I(RxV, siV); \ | |
66 | } while (0) | |
46ef47e2 TS |
67 | #define GET_EA_pci \ |
68 | do { \ | |
f448397a | 69 | TCGv tcgv_siV = tcg_constant_tl(siV); \ |
46ef47e2 TS |
70 | tcg_gen_mov_tl(EA, RxV); \ |
71 | gen_helper_fcircadd(RxV, RxV, tcgv_siV, MuV, \ | |
72 | hex_gpr[HEX_REG_CS0 + MuN]); \ | |
46ef47e2 TS |
73 | } while (0) |
74 | #define GET_EA_pcr(SHIFT) \ | |
75 | do { \ | |
76 | TCGv ireg = tcg_temp_new(); \ | |
77 | tcg_gen_mov_tl(EA, RxV); \ | |
78 | gen_read_ireg(ireg, MuV, (SHIFT)); \ | |
79 | gen_helper_fcircadd(RxV, RxV, ireg, MuV, hex_gpr[HEX_REG_CS0 + MuN]); \ | |
80 | tcg_temp_free(ireg); \ | |
81 | } while (0) | |
6542aa2e TS |
82 | |
83 | /* Instructions with multiple definitions */ | |
84 | #define fGEN_TCG_LOAD_AP(RES, SIZE, SIGN) \ | |
85 | do { \ | |
86 | fMUST_IMMEXT(UiV); \ | |
87 | fEA_IMM(UiV); \ | |
88 | fLOAD(1, SIZE, SIGN, EA, RES); \ | |
89 | tcg_gen_movi_tl(ReV, UiV); \ | |
90 | } while (0) | |
91 | ||
92 | #define fGEN_TCG_L4_loadrub_ap(SHORTCODE) \ | |
93 | fGEN_TCG_LOAD_AP(RdV, 1, u) | |
94 | #define fGEN_TCG_L4_loadrb_ap(SHORTCODE) \ | |
95 | fGEN_TCG_LOAD_AP(RdV, 1, s) | |
96 | #define fGEN_TCG_L4_loadruh_ap(SHORTCODE) \ | |
97 | fGEN_TCG_LOAD_AP(RdV, 2, u) | |
98 | #define fGEN_TCG_L4_loadrh_ap(SHORTCODE) \ | |
99 | fGEN_TCG_LOAD_AP(RdV, 2, s) | |
100 | #define fGEN_TCG_L4_loadri_ap(SHORTCODE) \ | |
101 | fGEN_TCG_LOAD_AP(RdV, 4, u) | |
102 | #define fGEN_TCG_L4_loadrd_ap(SHORTCODE) \ | |
103 | fGEN_TCG_LOAD_AP(RddV, 8, u) | |
104 | ||
46ef47e2 TS |
105 | #define fGEN_TCG_L2_loadrub_pci(SHORTCODE) SHORTCODE |
106 | #define fGEN_TCG_L2_loadrb_pci(SHORTCODE) SHORTCODE | |
107 | #define fGEN_TCG_L2_loadruh_pci(SHORTCODE) SHORTCODE | |
108 | #define fGEN_TCG_L2_loadrh_pci(SHORTCODE) SHORTCODE | |
109 | #define fGEN_TCG_L2_loadri_pci(SHORTCODE) SHORTCODE | |
110 | #define fGEN_TCG_L2_loadrd_pci(SHORTCODE) SHORTCODE | |
111 | ||
112 | #define fGEN_TCG_LOAD_pcr(SHIFT, LOAD) \ | |
113 | do { \ | |
114 | TCGv ireg = tcg_temp_new(); \ | |
115 | tcg_gen_mov_tl(EA, RxV); \ | |
116 | gen_read_ireg(ireg, MuV, SHIFT); \ | |
117 | gen_helper_fcircadd(RxV, RxV, ireg, MuV, hex_gpr[HEX_REG_CS0 + MuN]); \ | |
118 | LOAD; \ | |
119 | tcg_temp_free(ireg); \ | |
120 | } while (0) | |
121 | ||
122 | #define fGEN_TCG_L2_loadrub_pcr(SHORTCODE) \ | |
123 | fGEN_TCG_LOAD_pcr(0, fLOAD(1, 1, u, EA, RdV)) | |
124 | #define fGEN_TCG_L2_loadrb_pcr(SHORTCODE) \ | |
125 | fGEN_TCG_LOAD_pcr(0, fLOAD(1, 1, s, EA, RdV)) | |
126 | #define fGEN_TCG_L2_loadruh_pcr(SHORTCODE) \ | |
127 | fGEN_TCG_LOAD_pcr(1, fLOAD(1, 2, u, EA, RdV)) | |
128 | #define fGEN_TCG_L2_loadrh_pcr(SHORTCODE) \ | |
129 | fGEN_TCG_LOAD_pcr(1, fLOAD(1, 2, s, EA, RdV)) | |
130 | #define fGEN_TCG_L2_loadri_pcr(SHORTCODE) \ | |
131 | fGEN_TCG_LOAD_pcr(2, fLOAD(1, 4, u, EA, RdV)) | |
132 | #define fGEN_TCG_L2_loadrd_pcr(SHORTCODE) \ | |
133 | fGEN_TCG_LOAD_pcr(3, fLOAD(1, 8, u, EA, RddV)) | |
134 | ||
6542aa2e | 135 | #define fGEN_TCG_L2_loadrub_pr(SHORTCODE) SHORTCODE |
af7f1821 | 136 | #define fGEN_TCG_L2_loadrub_pbr(SHORTCODE) SHORTCODE |
6542aa2e TS |
137 | #define fGEN_TCG_L2_loadrub_pi(SHORTCODE) SHORTCODE |
138 | #define fGEN_TCG_L2_loadrb_pr(SHORTCODE) SHORTCODE | |
af7f1821 | 139 | #define fGEN_TCG_L2_loadrb_pbr(SHORTCODE) SHORTCODE |
5f261764 | 140 | #define fGEN_TCG_L2_loadrb_pi(SHORTCODE) SHORTCODE |
6542aa2e | 141 | #define fGEN_TCG_L2_loadruh_pr(SHORTCODE) SHORTCODE |
af7f1821 | 142 | #define fGEN_TCG_L2_loadruh_pbr(SHORTCODE) SHORTCODE |
5f261764 | 143 | #define fGEN_TCG_L2_loadruh_pi(SHORTCODE) SHORTCODE |
6542aa2e | 144 | #define fGEN_TCG_L2_loadrh_pr(SHORTCODE) SHORTCODE |
af7f1821 | 145 | #define fGEN_TCG_L2_loadrh_pbr(SHORTCODE) SHORTCODE |
6542aa2e TS |
146 | #define fGEN_TCG_L2_loadrh_pi(SHORTCODE) SHORTCODE |
147 | #define fGEN_TCG_L2_loadri_pr(SHORTCODE) SHORTCODE | |
af7f1821 | 148 | #define fGEN_TCG_L2_loadri_pbr(SHORTCODE) SHORTCODE |
6542aa2e TS |
149 | #define fGEN_TCG_L2_loadri_pi(SHORTCODE) SHORTCODE |
150 | #define fGEN_TCG_L2_loadrd_pr(SHORTCODE) SHORTCODE | |
af7f1821 | 151 | #define fGEN_TCG_L2_loadrd_pbr(SHORTCODE) SHORTCODE |
6542aa2e TS |
152 | #define fGEN_TCG_L2_loadrd_pi(SHORTCODE) SHORTCODE |
153 | ||
0d0b91a8 TS |
154 | /* |
155 | * These instructions load 2 bytes and places them in | |
156 | * two halves of the destination register. | |
157 | * The GET_EA macro determines the addressing mode. | |
158 | * The SIGN argument determines whether to zero-extend or | |
159 | * sign-extend. | |
160 | */ | |
161 | #define fGEN_TCG_loadbXw2(GET_EA, SIGN) \ | |
162 | do { \ | |
163 | TCGv tmp = tcg_temp_new(); \ | |
164 | TCGv byte = tcg_temp_new(); \ | |
165 | GET_EA; \ | |
166 | fLOAD(1, 2, u, EA, tmp); \ | |
167 | tcg_gen_movi_tl(RdV, 0); \ | |
168 | for (int i = 0; i < 2; i++) { \ | |
169 | gen_set_half(i, RdV, gen_get_byte(byte, i, tmp, (SIGN))); \ | |
170 | } \ | |
171 | tcg_temp_free(tmp); \ | |
172 | tcg_temp_free(byte); \ | |
173 | } while (0) | |
174 | ||
175 | #define fGEN_TCG_L2_loadbzw2_io(SHORTCODE) \ | |
176 | fGEN_TCG_loadbXw2(fEA_RI(RsV, siV), false) | |
177 | #define fGEN_TCG_L4_loadbzw2_ur(SHORTCODE) \ | |
178 | fGEN_TCG_loadbXw2(fEA_IRs(UiV, RtV, uiV), false) | |
179 | #define fGEN_TCG_L2_loadbsw2_io(SHORTCODE) \ | |
180 | fGEN_TCG_loadbXw2(fEA_RI(RsV, siV), true) | |
181 | #define fGEN_TCG_L4_loadbsw2_ur(SHORTCODE) \ | |
182 | fGEN_TCG_loadbXw2(fEA_IRs(UiV, RtV, uiV), true) | |
183 | #define fGEN_TCG_L4_loadbzw2_ap(SHORTCODE) \ | |
184 | fGEN_TCG_loadbXw2(GET_EA_ap, false) | |
185 | #define fGEN_TCG_L2_loadbzw2_pr(SHORTCODE) \ | |
186 | fGEN_TCG_loadbXw2(GET_EA_pr, false) | |
187 | #define fGEN_TCG_L2_loadbzw2_pbr(SHORTCODE) \ | |
188 | fGEN_TCG_loadbXw2(GET_EA_pbr, false) | |
189 | #define fGEN_TCG_L2_loadbzw2_pi(SHORTCODE) \ | |
190 | fGEN_TCG_loadbXw2(GET_EA_pi, false) | |
191 | #define fGEN_TCG_L4_loadbsw2_ap(SHORTCODE) \ | |
192 | fGEN_TCG_loadbXw2(GET_EA_ap, true) | |
193 | #define fGEN_TCG_L2_loadbsw2_pr(SHORTCODE) \ | |
194 | fGEN_TCG_loadbXw2(GET_EA_pr, true) | |
195 | #define fGEN_TCG_L2_loadbsw2_pbr(SHORTCODE) \ | |
196 | fGEN_TCG_loadbXw2(GET_EA_pbr, true) | |
197 | #define fGEN_TCG_L2_loadbsw2_pi(SHORTCODE) \ | |
198 | fGEN_TCG_loadbXw2(GET_EA_pi, true) | |
199 | #define fGEN_TCG_L2_loadbzw2_pci(SHORTCODE) \ | |
200 | fGEN_TCG_loadbXw2(GET_EA_pci, false) | |
201 | #define fGEN_TCG_L2_loadbsw2_pci(SHORTCODE) \ | |
202 | fGEN_TCG_loadbXw2(GET_EA_pci, true) | |
203 | #define fGEN_TCG_L2_loadbzw2_pcr(SHORTCODE) \ | |
204 | fGEN_TCG_loadbXw2(GET_EA_pcr(1), false) | |
205 | #define fGEN_TCG_L2_loadbsw2_pcr(SHORTCODE) \ | |
206 | fGEN_TCG_loadbXw2(GET_EA_pcr(1), true) | |
207 | ||
208 | /* | |
209 | * These instructions load 4 bytes and places them in | |
210 | * four halves of the destination register pair. | |
211 | * The GET_EA macro determines the addressing mode. | |
212 | * The SIGN argument determines whether to zero-extend or | |
213 | * sign-extend. | |
214 | */ | |
215 | #define fGEN_TCG_loadbXw4(GET_EA, SIGN) \ | |
216 | do { \ | |
217 | TCGv tmp = tcg_temp_new(); \ | |
218 | TCGv byte = tcg_temp_new(); \ | |
219 | GET_EA; \ | |
220 | fLOAD(1, 4, u, EA, tmp); \ | |
221 | tcg_gen_movi_i64(RddV, 0); \ | |
222 | for (int i = 0; i < 4; i++) { \ | |
223 | gen_set_half_i64(i, RddV, gen_get_byte(byte, i, tmp, (SIGN))); \ | |
224 | } \ | |
225 | tcg_temp_free(tmp); \ | |
226 | tcg_temp_free(byte); \ | |
227 | } while (0) | |
228 | ||
229 | #define fGEN_TCG_L2_loadbzw4_io(SHORTCODE) \ | |
230 | fGEN_TCG_loadbXw4(fEA_RI(RsV, siV), false) | |
231 | #define fGEN_TCG_L4_loadbzw4_ur(SHORTCODE) \ | |
232 | fGEN_TCG_loadbXw4(fEA_IRs(UiV, RtV, uiV), false) | |
233 | #define fGEN_TCG_L2_loadbsw4_io(SHORTCODE) \ | |
234 | fGEN_TCG_loadbXw4(fEA_RI(RsV, siV), true) | |
235 | #define fGEN_TCG_L4_loadbsw4_ur(SHORTCODE) \ | |
236 | fGEN_TCG_loadbXw4(fEA_IRs(UiV, RtV, uiV), true) | |
237 | #define fGEN_TCG_L2_loadbzw4_pci(SHORTCODE) \ | |
238 | fGEN_TCG_loadbXw4(GET_EA_pci, false) | |
239 | #define fGEN_TCG_L2_loadbsw4_pci(SHORTCODE) \ | |
240 | fGEN_TCG_loadbXw4(GET_EA_pci, true) | |
241 | #define fGEN_TCG_L2_loadbzw4_pcr(SHORTCODE) \ | |
242 | fGEN_TCG_loadbXw4(GET_EA_pcr(2), false) | |
243 | #define fGEN_TCG_L2_loadbsw4_pcr(SHORTCODE) \ | |
244 | fGEN_TCG_loadbXw4(GET_EA_pcr(2), true) | |
245 | #define fGEN_TCG_L4_loadbzw4_ap(SHORTCODE) \ | |
246 | fGEN_TCG_loadbXw4(GET_EA_ap, false) | |
247 | #define fGEN_TCG_L2_loadbzw4_pr(SHORTCODE) \ | |
248 | fGEN_TCG_loadbXw4(GET_EA_pr, false) | |
249 | #define fGEN_TCG_L2_loadbzw4_pbr(SHORTCODE) \ | |
250 | fGEN_TCG_loadbXw4(GET_EA_pbr, false) | |
251 | #define fGEN_TCG_L2_loadbzw4_pi(SHORTCODE) \ | |
252 | fGEN_TCG_loadbXw4(GET_EA_pi, false) | |
253 | #define fGEN_TCG_L4_loadbsw4_ap(SHORTCODE) \ | |
254 | fGEN_TCG_loadbXw4(GET_EA_ap, true) | |
255 | #define fGEN_TCG_L2_loadbsw4_pr(SHORTCODE) \ | |
256 | fGEN_TCG_loadbXw4(GET_EA_pr, true) | |
257 | #define fGEN_TCG_L2_loadbsw4_pbr(SHORTCODE) \ | |
258 | fGEN_TCG_loadbXw4(GET_EA_pbr, true) | |
259 | #define fGEN_TCG_L2_loadbsw4_pi(SHORTCODE) \ | |
260 | fGEN_TCG_loadbXw4(GET_EA_pi, true) | |
261 | ||
7aa9ffab TS |
262 | /* |
263 | * These instructions load a half word, shift the destination right by 16 bits | |
264 | * and place the loaded value in the high half word of the destination pair. | |
265 | * The GET_EA macro determines the addressing mode. | |
266 | */ | |
267 | #define fGEN_TCG_loadalignh(GET_EA) \ | |
268 | do { \ | |
269 | TCGv tmp = tcg_temp_new(); \ | |
270 | TCGv_i64 tmp_i64 = tcg_temp_new_i64(); \ | |
271 | GET_EA; \ | |
272 | fLOAD(1, 2, u, EA, tmp); \ | |
273 | tcg_gen_extu_i32_i64(tmp_i64, tmp); \ | |
274 | tcg_gen_shri_i64(RyyV, RyyV, 16); \ | |
275 | tcg_gen_deposit_i64(RyyV, RyyV, tmp_i64, 48, 16); \ | |
276 | tcg_temp_free(tmp); \ | |
277 | tcg_temp_free_i64(tmp_i64); \ | |
278 | } while (0) | |
279 | ||
280 | #define fGEN_TCG_L4_loadalignh_ur(SHORTCODE) \ | |
281 | fGEN_TCG_loadalignh(fEA_IRs(UiV, RtV, uiV)) | |
282 | #define fGEN_TCG_L2_loadalignh_io(SHORTCODE) \ | |
283 | fGEN_TCG_loadalignh(fEA_RI(RsV, siV)) | |
284 | #define fGEN_TCG_L2_loadalignh_pci(SHORTCODE) \ | |
285 | fGEN_TCG_loadalignh(GET_EA_pci) | |
286 | #define fGEN_TCG_L2_loadalignh_pcr(SHORTCODE) \ | |
287 | fGEN_TCG_loadalignh(GET_EA_pcr(1)) | |
288 | #define fGEN_TCG_L4_loadalignh_ap(SHORTCODE) \ | |
289 | fGEN_TCG_loadalignh(GET_EA_ap) | |
290 | #define fGEN_TCG_L2_loadalignh_pr(SHORTCODE) \ | |
291 | fGEN_TCG_loadalignh(GET_EA_pr) | |
292 | #define fGEN_TCG_L2_loadalignh_pbr(SHORTCODE) \ | |
293 | fGEN_TCG_loadalignh(GET_EA_pbr) | |
294 | #define fGEN_TCG_L2_loadalignh_pi(SHORTCODE) \ | |
295 | fGEN_TCG_loadalignh(GET_EA_pi) | |
296 | ||
297 | /* Same as above, but loads a byte instead of half word */ | |
298 | #define fGEN_TCG_loadalignb(GET_EA) \ | |
299 | do { \ | |
300 | TCGv tmp = tcg_temp_new(); \ | |
301 | TCGv_i64 tmp_i64 = tcg_temp_new_i64(); \ | |
302 | GET_EA; \ | |
303 | fLOAD(1, 1, u, EA, tmp); \ | |
304 | tcg_gen_extu_i32_i64(tmp_i64, tmp); \ | |
305 | tcg_gen_shri_i64(RyyV, RyyV, 8); \ | |
306 | tcg_gen_deposit_i64(RyyV, RyyV, tmp_i64, 56, 8); \ | |
307 | tcg_temp_free(tmp); \ | |
308 | tcg_temp_free_i64(tmp_i64); \ | |
309 | } while (0) | |
310 | ||
311 | #define fGEN_TCG_L2_loadalignb_io(SHORTCODE) \ | |
312 | fGEN_TCG_loadalignb(fEA_RI(RsV, siV)) | |
313 | #define fGEN_TCG_L4_loadalignb_ur(SHORTCODE) \ | |
314 | fGEN_TCG_loadalignb(fEA_IRs(UiV, RtV, uiV)) | |
315 | #define fGEN_TCG_L2_loadalignb_pci(SHORTCODE) \ | |
316 | fGEN_TCG_loadalignb(GET_EA_pci) | |
317 | #define fGEN_TCG_L2_loadalignb_pcr(SHORTCODE) \ | |
318 | fGEN_TCG_loadalignb(GET_EA_pcr(0)) | |
319 | #define fGEN_TCG_L4_loadalignb_ap(SHORTCODE) \ | |
320 | fGEN_TCG_loadalignb(GET_EA_ap) | |
321 | #define fGEN_TCG_L2_loadalignb_pr(SHORTCODE) \ | |
322 | fGEN_TCG_loadalignb(GET_EA_pr) | |
323 | #define fGEN_TCG_L2_loadalignb_pbr(SHORTCODE) \ | |
324 | fGEN_TCG_loadalignb(GET_EA_pbr) | |
325 | #define fGEN_TCG_L2_loadalignb_pi(SHORTCODE) \ | |
326 | fGEN_TCG_loadalignb(GET_EA_pi) | |
327 | ||
6542aa2e TS |
328 | /* |
329 | * Predicated loads | |
330 | * Here is a primer to understand the tag names | |
331 | * | |
332 | * Predicate used | |
333 | * t true "old" value if (p0) r0 = memb(r2+#0) | |
334 | * f false "old" value if (!p0) r0 = memb(r2+#0) | |
335 | * tnew true "new" value if (p0.new) r0 = memb(r2+#0) | |
336 | * fnew false "new" value if (!p0.new) r0 = memb(r2+#0) | |
337 | */ | |
338 | #define fGEN_TCG_PRED_LOAD(GET_EA, PRED, SIZE, SIGN) \ | |
339 | do { \ | |
340 | TCGv LSB = tcg_temp_local_new(); \ | |
341 | TCGLabel *label = gen_new_label(); \ | |
342 | GET_EA; \ | |
343 | PRED; \ | |
344 | PRED_LOAD_CANCEL(LSB, EA); \ | |
345 | tcg_gen_movi_tl(RdV, 0); \ | |
346 | tcg_gen_brcondi_tl(TCG_COND_EQ, LSB, 0, label); \ | |
347 | fLOAD(1, SIZE, SIGN, EA, RdV); \ | |
348 | gen_set_label(label); \ | |
349 | tcg_temp_free(LSB); \ | |
350 | } while (0) | |
351 | ||
352 | #define fGEN_TCG_L2_ploadrubt_pi(SHORTCODE) \ | |
353 | fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBOLD(PtV), 1, u) | |
354 | #define fGEN_TCG_L2_ploadrubf_pi(SHORTCODE) \ | |
355 | fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBOLDNOT(PtV), 1, u) | |
356 | #define fGEN_TCG_L2_ploadrubtnew_pi(SHORTCODE) \ | |
357 | fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBNEW(PtN), 1, u) | |
358 | #define fGEN_TCG_L2_ploadrubfnew_pi(SHORTCODE) \ | |
359 | fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBNEWNOT(PtN), 1, u) | |
360 | #define fGEN_TCG_L2_ploadrbt_pi(SHORTCODE) \ | |
361 | fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBOLD(PtV), 1, s) | |
362 | #define fGEN_TCG_L2_ploadrbf_pi(SHORTCODE) \ | |
363 | fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBOLDNOT(PtV), 1, s) | |
364 | #define fGEN_TCG_L2_ploadrbtnew_pi(SHORTCODE) \ | |
365 | fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBNEW(PtN), 1, s) | |
366 | #define fGEN_TCG_L2_ploadrbfnew_pi(SHORTCODE) \ | |
367 | fGEN_TCG_PRED_LOAD({ fEA_REG(RxV); fPM_I(RxV, siV); }, \ | |
368 | fLSBNEWNOT(PtN), 1, s) | |
369 | ||
370 | #define fGEN_TCG_L2_ploadruht_pi(SHORTCODE) \ | |
371 | fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBOLD(PtV), 2, u) | |
372 | #define fGEN_TCG_L2_ploadruhf_pi(SHORTCODE) \ | |
373 | fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBOLDNOT(PtV), 2, u) | |
374 | #define fGEN_TCG_L2_ploadruhtnew_pi(SHORTCODE) \ | |
375 | fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBNEW(PtN), 2, u) | |
376 | #define fGEN_TCG_L2_ploadruhfnew_pi(SHORTCODE) \ | |
377 | fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBNEWNOT(PtN), 2, u) | |
378 | #define fGEN_TCG_L2_ploadrht_pi(SHORTCODE) \ | |
379 | fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBOLD(PtV), 2, s) | |
380 | #define fGEN_TCG_L2_ploadrhf_pi(SHORTCODE) \ | |
381 | fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBOLDNOT(PtV), 2, s) | |
382 | #define fGEN_TCG_L2_ploadrhtnew_pi(SHORTCODE) \ | |
383 | fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBNEW(PtN), 2, s) | |
384 | #define fGEN_TCG_L2_ploadrhfnew_pi(SHORTCODE) \ | |
385 | fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBNEWNOT(PtN), 2, s) | |
386 | ||
387 | #define fGEN_TCG_L2_ploadrit_pi(SHORTCODE) \ | |
388 | fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBOLD(PtV), 4, u) | |
389 | #define fGEN_TCG_L2_ploadrif_pi(SHORTCODE) \ | |
390 | fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBOLDNOT(PtV), 4, u) | |
391 | #define fGEN_TCG_L2_ploadritnew_pi(SHORTCODE) \ | |
392 | fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBNEW(PtN), 4, u) | |
393 | #define fGEN_TCG_L2_ploadrifnew_pi(SHORTCODE) \ | |
394 | fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBNEWNOT(PtN), 4, u) | |
395 | ||
396 | /* Predicated loads into a register pair */ | |
397 | #define fGEN_TCG_PRED_LOAD_PAIR(GET_EA, PRED) \ | |
398 | do { \ | |
399 | TCGv LSB = tcg_temp_local_new(); \ | |
400 | TCGLabel *label = gen_new_label(); \ | |
401 | GET_EA; \ | |
402 | PRED; \ | |
403 | PRED_LOAD_CANCEL(LSB, EA); \ | |
404 | tcg_gen_movi_i64(RddV, 0); \ | |
405 | tcg_gen_brcondi_tl(TCG_COND_EQ, LSB, 0, label); \ | |
406 | fLOAD(1, 8, u, EA, RddV); \ | |
407 | gen_set_label(label); \ | |
408 | tcg_temp_free(LSB); \ | |
409 | } while (0) | |
410 | ||
411 | #define fGEN_TCG_L2_ploadrdt_pi(SHORTCODE) \ | |
412 | fGEN_TCG_PRED_LOAD_PAIR(GET_EA_pi, fLSBOLD(PtV)) | |
413 | #define fGEN_TCG_L2_ploadrdf_pi(SHORTCODE) \ | |
414 | fGEN_TCG_PRED_LOAD_PAIR(GET_EA_pi, fLSBOLDNOT(PtV)) | |
415 | #define fGEN_TCG_L2_ploadrdtnew_pi(SHORTCODE) \ | |
416 | fGEN_TCG_PRED_LOAD_PAIR(GET_EA_pi, fLSBNEW(PtN)) | |
417 | #define fGEN_TCG_L2_ploadrdfnew_pi(SHORTCODE) \ | |
418 | fGEN_TCG_PRED_LOAD_PAIR(GET_EA_pi, fLSBNEWNOT(PtN)) | |
419 | ||
420 | /* load-locked and store-locked */ | |
421 | #define fGEN_TCG_L2_loadw_locked(SHORTCODE) \ | |
422 | SHORTCODE | |
423 | #define fGEN_TCG_L4_loadd_locked(SHORTCODE) \ | |
424 | SHORTCODE | |
425 | #define fGEN_TCG_S2_storew_locked(SHORTCODE) \ | |
88725336 | 426 | SHORTCODE |
6542aa2e | 427 | #define fGEN_TCG_S4_stored_locked(SHORTCODE) \ |
88725336 | 428 | SHORTCODE |
6542aa2e | 429 | |
46ef47e2 TS |
430 | #define fGEN_TCG_STORE(SHORTCODE) \ |
431 | do { \ | |
432 | TCGv HALF = tcg_temp_new(); \ | |
433 | TCGv BYTE = tcg_temp_new(); \ | |
434 | SHORTCODE; \ | |
435 | tcg_temp_free(HALF); \ | |
436 | tcg_temp_free(BYTE); \ | |
437 | } while (0) | |
438 | ||
439 | #define fGEN_TCG_STORE_pcr(SHIFT, STORE) \ | |
440 | do { \ | |
441 | TCGv ireg = tcg_temp_new(); \ | |
442 | TCGv HALF = tcg_temp_new(); \ | |
443 | TCGv BYTE = tcg_temp_new(); \ | |
444 | tcg_gen_mov_tl(EA, RxV); \ | |
445 | gen_read_ireg(ireg, MuV, SHIFT); \ | |
446 | gen_helper_fcircadd(RxV, RxV, ireg, MuV, hex_gpr[HEX_REG_CS0 + MuN]); \ | |
447 | STORE; \ | |
448 | tcg_temp_free(ireg); \ | |
449 | tcg_temp_free(HALF); \ | |
450 | tcg_temp_free(BYTE); \ | |
451 | } while (0) | |
452 | ||
af7f1821 TS |
453 | #define fGEN_TCG_S2_storerb_pbr(SHORTCODE) \ |
454 | fGEN_TCG_STORE(SHORTCODE) | |
46ef47e2 TS |
455 | #define fGEN_TCG_S2_storerb_pci(SHORTCODE) \ |
456 | fGEN_TCG_STORE(SHORTCODE) | |
457 | #define fGEN_TCG_S2_storerb_pcr(SHORTCODE) \ | |
458 | fGEN_TCG_STORE_pcr(0, fSTORE(1, 1, EA, fGETBYTE(0, RtV))) | |
459 | ||
af7f1821 TS |
460 | #define fGEN_TCG_S2_storerh_pbr(SHORTCODE) \ |
461 | fGEN_TCG_STORE(SHORTCODE) | |
46ef47e2 TS |
462 | #define fGEN_TCG_S2_storerh_pci(SHORTCODE) \ |
463 | fGEN_TCG_STORE(SHORTCODE) | |
464 | #define fGEN_TCG_S2_storerh_pcr(SHORTCODE) \ | |
465 | fGEN_TCG_STORE_pcr(1, fSTORE(1, 2, EA, fGETHALF(0, RtV))) | |
466 | ||
af7f1821 TS |
467 | #define fGEN_TCG_S2_storerf_pbr(SHORTCODE) \ |
468 | fGEN_TCG_STORE(SHORTCODE) | |
46ef47e2 TS |
469 | #define fGEN_TCG_S2_storerf_pci(SHORTCODE) \ |
470 | fGEN_TCG_STORE(SHORTCODE) | |
471 | #define fGEN_TCG_S2_storerf_pcr(SHORTCODE) \ | |
472 | fGEN_TCG_STORE_pcr(1, fSTORE(1, 2, EA, fGETHALF(1, RtV))) | |
473 | ||
af7f1821 TS |
474 | #define fGEN_TCG_S2_storeri_pbr(SHORTCODE) \ |
475 | fGEN_TCG_STORE(SHORTCODE) | |
46ef47e2 TS |
476 | #define fGEN_TCG_S2_storeri_pci(SHORTCODE) \ |
477 | fGEN_TCG_STORE(SHORTCODE) | |
478 | #define fGEN_TCG_S2_storeri_pcr(SHORTCODE) \ | |
479 | fGEN_TCG_STORE_pcr(2, fSTORE(1, 4, EA, RtV)) | |
480 | ||
af7f1821 TS |
481 | #define fGEN_TCG_S2_storerd_pbr(SHORTCODE) \ |
482 | fGEN_TCG_STORE(SHORTCODE) | |
46ef47e2 TS |
483 | #define fGEN_TCG_S2_storerd_pci(SHORTCODE) \ |
484 | fGEN_TCG_STORE(SHORTCODE) | |
485 | #define fGEN_TCG_S2_storerd_pcr(SHORTCODE) \ | |
486 | fGEN_TCG_STORE_pcr(3, fSTORE(1, 8, EA, RttV)) | |
487 | ||
af7f1821 TS |
488 | #define fGEN_TCG_S2_storerbnew_pbr(SHORTCODE) \ |
489 | fGEN_TCG_STORE(SHORTCODE) | |
46ef47e2 TS |
490 | #define fGEN_TCG_S2_storerbnew_pci(SHORTCODE) \ |
491 | fGEN_TCG_STORE(SHORTCODE) | |
492 | #define fGEN_TCG_S2_storerbnew_pcr(SHORTCODE) \ | |
493 | fGEN_TCG_STORE_pcr(0, fSTORE(1, 1, EA, fGETBYTE(0, NtN))) | |
494 | ||
af7f1821 TS |
495 | #define fGEN_TCG_S2_storerhnew_pbr(SHORTCODE) \ |
496 | fGEN_TCG_STORE(SHORTCODE) | |
46ef47e2 TS |
497 | #define fGEN_TCG_S2_storerhnew_pci(SHORTCODE) \ |
498 | fGEN_TCG_STORE(SHORTCODE) | |
499 | #define fGEN_TCG_S2_storerhnew_pcr(SHORTCODE) \ | |
500 | fGEN_TCG_STORE_pcr(1, fSTORE(1, 2, EA, fGETHALF(0, NtN))) | |
501 | ||
af7f1821 TS |
502 | #define fGEN_TCG_S2_storerinew_pbr(SHORTCODE) \ |
503 | fGEN_TCG_STORE(SHORTCODE) | |
46ef47e2 TS |
504 | #define fGEN_TCG_S2_storerinew_pci(SHORTCODE) \ |
505 | fGEN_TCG_STORE(SHORTCODE) | |
506 | #define fGEN_TCG_S2_storerinew_pcr(SHORTCODE) \ | |
507 | fGEN_TCG_STORE_pcr(2, fSTORE(1, 4, EA, NtN)) | |
508 | ||
d934c16d TS |
509 | /* |
510 | * Mathematical operations with more than one definition require | |
511 | * special handling | |
512 | */ | |
da74cd2d TS |
513 | #define fGEN_TCG_A5_ACS(SHORTCODE) \ |
514 | do { \ | |
515 | gen_helper_vacsh_pred(PeV, cpu_env, RxxV, RssV, RttV); \ | |
516 | gen_helper_vacsh_val(RxxV, cpu_env, RxxV, RssV, RttV); \ | |
517 | } while (0) | |
d934c16d TS |
518 | |
519 | /* | |
520 | * Approximate reciprocal | |
521 | * r3,p1 = sfrecipa(r0, r1) | |
522 | * | |
523 | * The helper packs the 2 32-bit results into a 64-bit value, | |
524 | * so unpack them into the proper results. | |
525 | */ | |
526 | #define fGEN_TCG_F2_sfrecipa(SHORTCODE) \ | |
527 | do { \ | |
528 | TCGv_i64 tmp = tcg_temp_new_i64(); \ | |
529 | gen_helper_sfrecipa(tmp, cpu_env, RsV, RtV); \ | |
530 | tcg_gen_extrh_i64_i32(RdV, tmp); \ | |
531 | tcg_gen_extrl_i64_i32(PeV, tmp); \ | |
532 | tcg_temp_free_i64(tmp); \ | |
533 | } while (0) | |
534 | ||
dd8705bd TS |
535 | /* |
536 | * Approximation of the reciprocal square root | |
537 | * r1,p0 = sfinvsqrta(r0) | |
538 | * | |
539 | * The helper packs the 2 32-bit results into a 64-bit value, | |
540 | * so unpack them into the proper results. | |
541 | */ | |
542 | #define fGEN_TCG_F2_sfinvsqrta(SHORTCODE) \ | |
543 | do { \ | |
544 | TCGv_i64 tmp = tcg_temp_new_i64(); \ | |
545 | gen_helper_sfinvsqrta(tmp, cpu_env, RsV); \ | |
546 | tcg_gen_extrh_i64_i32(RdV, tmp); \ | |
547 | tcg_gen_extrl_i64_i32(PeV, tmp); \ | |
548 | tcg_temp_free_i64(tmp); \ | |
549 | } while (0) | |
550 | ||
57d352ac TS |
551 | /* |
552 | * Add or subtract with carry. | |
553 | * Predicate register is used as an extra input and output. | |
554 | * r5:4 = add(r1:0, r3:2, p1):carry | |
555 | */ | |
556 | #define fGEN_TCG_A4_addp_c(SHORTCODE) \ | |
557 | do { \ | |
558 | TCGv_i64 carry = tcg_temp_new_i64(); \ | |
f448397a | 559 | TCGv_i64 zero = tcg_constant_i64(0); \ |
57d352ac TS |
560 | tcg_gen_extu_i32_i64(carry, PxV); \ |
561 | tcg_gen_andi_i64(carry, carry, 1); \ | |
562 | tcg_gen_add2_i64(RddV, carry, RssV, zero, carry, zero); \ | |
563 | tcg_gen_add2_i64(RddV, carry, RddV, carry, RttV, zero); \ | |
564 | tcg_gen_extrl_i64_i32(PxV, carry); \ | |
565 | gen_8bitsof(PxV, PxV); \ | |
566 | tcg_temp_free_i64(carry); \ | |
57d352ac TS |
567 | } while (0) |
568 | ||
569 | /* r5:4 = sub(r1:0, r3:2, p1):carry */ | |
570 | #define fGEN_TCG_A4_subp_c(SHORTCODE) \ | |
571 | do { \ | |
572 | TCGv_i64 carry = tcg_temp_new_i64(); \ | |
f448397a | 573 | TCGv_i64 zero = tcg_constant_i64(0); \ |
57d352ac TS |
574 | TCGv_i64 not_RttV = tcg_temp_new_i64(); \ |
575 | tcg_gen_extu_i32_i64(carry, PxV); \ | |
576 | tcg_gen_andi_i64(carry, carry, 1); \ | |
577 | tcg_gen_not_i64(not_RttV, RttV); \ | |
578 | tcg_gen_add2_i64(RddV, carry, RssV, zero, carry, zero); \ | |
579 | tcg_gen_add2_i64(RddV, carry, RddV, carry, not_RttV, zero); \ | |
580 | tcg_gen_extrl_i64_i32(PxV, carry); \ | |
581 | gen_8bitsof(PxV, PxV); \ | |
582 | tcg_temp_free_i64(carry); \ | |
57d352ac TS |
583 | tcg_temp_free_i64(not_RttV); \ |
584 | } while (0) | |
585 | ||
0a65d286 TS |
586 | /* |
587 | * Compare each of the 8 unsigned bytes | |
588 | * The minimum is placed in each byte of the destination. | |
589 | * Each bit of the predicate is set true if the bit from the first operand | |
590 | * is greater than the bit from the second operand. | |
591 | * r5:4,p1 = vminub(r1:0, r3:2) | |
592 | */ | |
593 | #define fGEN_TCG_A6_vminub_RdP(SHORTCODE) \ | |
594 | do { \ | |
595 | TCGv left = tcg_temp_new(); \ | |
596 | TCGv right = tcg_temp_new(); \ | |
597 | TCGv tmp = tcg_temp_new(); \ | |
598 | tcg_gen_movi_tl(PeV, 0); \ | |
599 | tcg_gen_movi_i64(RddV, 0); \ | |
600 | for (int i = 0; i < 8; i++) { \ | |
601 | gen_get_byte_i64(left, i, RttV, false); \ | |
602 | gen_get_byte_i64(right, i, RssV, false); \ | |
603 | tcg_gen_setcond_tl(TCG_COND_GT, tmp, left, right); \ | |
604 | tcg_gen_deposit_tl(PeV, PeV, tmp, i, 1); \ | |
605 | tcg_gen_umin_tl(tmp, left, right); \ | |
606 | gen_set_byte_i64(i, RddV, tmp); \ | |
607 | } \ | |
608 | tcg_temp_free(left); \ | |
609 | tcg_temp_free(right); \ | |
610 | tcg_temp_free(tmp); \ | |
611 | } while (0) | |
612 | ||
d9dcdf8a TS |
613 | /* Floating point */ |
614 | #define fGEN_TCG_F2_conv_sf2df(SHORTCODE) \ | |
615 | gen_helper_conv_sf2df(RddV, cpu_env, RsV) | |
616 | #define fGEN_TCG_F2_conv_df2sf(SHORTCODE) \ | |
617 | gen_helper_conv_df2sf(RdV, cpu_env, RssV) | |
618 | #define fGEN_TCG_F2_conv_uw2sf(SHORTCODE) \ | |
619 | gen_helper_conv_uw2sf(RdV, cpu_env, RsV) | |
620 | #define fGEN_TCG_F2_conv_uw2df(SHORTCODE) \ | |
621 | gen_helper_conv_uw2df(RddV, cpu_env, RsV) | |
622 | #define fGEN_TCG_F2_conv_w2sf(SHORTCODE) \ | |
623 | gen_helper_conv_w2sf(RdV, cpu_env, RsV) | |
624 | #define fGEN_TCG_F2_conv_w2df(SHORTCODE) \ | |
625 | gen_helper_conv_w2df(RddV, cpu_env, RsV) | |
626 | #define fGEN_TCG_F2_conv_ud2sf(SHORTCODE) \ | |
627 | gen_helper_conv_ud2sf(RdV, cpu_env, RssV) | |
628 | #define fGEN_TCG_F2_conv_ud2df(SHORTCODE) \ | |
629 | gen_helper_conv_ud2df(RddV, cpu_env, RssV) | |
630 | #define fGEN_TCG_F2_conv_d2sf(SHORTCODE) \ | |
631 | gen_helper_conv_d2sf(RdV, cpu_env, RssV) | |
632 | #define fGEN_TCG_F2_conv_d2df(SHORTCODE) \ | |
633 | gen_helper_conv_d2df(RddV, cpu_env, RssV) | |
634 | #define fGEN_TCG_F2_conv_sf2uw(SHORTCODE) \ | |
635 | gen_helper_conv_sf2uw(RdV, cpu_env, RsV) | |
636 | #define fGEN_TCG_F2_conv_sf2w(SHORTCODE) \ | |
637 | gen_helper_conv_sf2w(RdV, cpu_env, RsV) | |
638 | #define fGEN_TCG_F2_conv_sf2ud(SHORTCODE) \ | |
639 | gen_helper_conv_sf2ud(RddV, cpu_env, RsV) | |
640 | #define fGEN_TCG_F2_conv_sf2d(SHORTCODE) \ | |
641 | gen_helper_conv_sf2d(RddV, cpu_env, RsV) | |
642 | #define fGEN_TCG_F2_conv_df2uw(SHORTCODE) \ | |
643 | gen_helper_conv_df2uw(RdV, cpu_env, RssV) | |
644 | #define fGEN_TCG_F2_conv_df2w(SHORTCODE) \ | |
645 | gen_helper_conv_df2w(RdV, cpu_env, RssV) | |
646 | #define fGEN_TCG_F2_conv_df2ud(SHORTCODE) \ | |
647 | gen_helper_conv_df2ud(RddV, cpu_env, RssV) | |
648 | #define fGEN_TCG_F2_conv_df2d(SHORTCODE) \ | |
649 | gen_helper_conv_df2d(RddV, cpu_env, RssV) | |
650 | #define fGEN_TCG_F2_conv_sf2uw_chop(SHORTCODE) \ | |
651 | gen_helper_conv_sf2uw_chop(RdV, cpu_env, RsV) | |
652 | #define fGEN_TCG_F2_conv_sf2w_chop(SHORTCODE) \ | |
653 | gen_helper_conv_sf2w_chop(RdV, cpu_env, RsV) | |
654 | #define fGEN_TCG_F2_conv_sf2ud_chop(SHORTCODE) \ | |
655 | gen_helper_conv_sf2ud_chop(RddV, cpu_env, RsV) | |
656 | #define fGEN_TCG_F2_conv_sf2d_chop(SHORTCODE) \ | |
657 | gen_helper_conv_sf2d_chop(RddV, cpu_env, RsV) | |
658 | #define fGEN_TCG_F2_conv_df2uw_chop(SHORTCODE) \ | |
659 | gen_helper_conv_df2uw_chop(RdV, cpu_env, RssV) | |
660 | #define fGEN_TCG_F2_conv_df2w_chop(SHORTCODE) \ | |
661 | gen_helper_conv_df2w_chop(RdV, cpu_env, RssV) | |
662 | #define fGEN_TCG_F2_conv_df2ud_chop(SHORTCODE) \ | |
663 | gen_helper_conv_df2ud_chop(RddV, cpu_env, RssV) | |
664 | #define fGEN_TCG_F2_conv_df2d_chop(SHORTCODE) \ | |
665 | gen_helper_conv_df2d_chop(RddV, cpu_env, RssV) | |
666 | #define fGEN_TCG_F2_sfadd(SHORTCODE) \ | |
667 | gen_helper_sfadd(RdV, cpu_env, RsV, RtV) | |
668 | #define fGEN_TCG_F2_sfsub(SHORTCODE) \ | |
669 | gen_helper_sfsub(RdV, cpu_env, RsV, RtV) | |
670 | #define fGEN_TCG_F2_sfcmpeq(SHORTCODE) \ | |
671 | gen_helper_sfcmpeq(PdV, cpu_env, RsV, RtV) | |
672 | #define fGEN_TCG_F2_sfcmpgt(SHORTCODE) \ | |
673 | gen_helper_sfcmpgt(PdV, cpu_env, RsV, RtV) | |
674 | #define fGEN_TCG_F2_sfcmpge(SHORTCODE) \ | |
675 | gen_helper_sfcmpge(PdV, cpu_env, RsV, RtV) | |
676 | #define fGEN_TCG_F2_sfcmpuo(SHORTCODE) \ | |
677 | gen_helper_sfcmpuo(PdV, cpu_env, RsV, RtV) | |
678 | #define fGEN_TCG_F2_sfmax(SHORTCODE) \ | |
679 | gen_helper_sfmax(RdV, cpu_env, RsV, RtV) | |
680 | #define fGEN_TCG_F2_sfmin(SHORTCODE) \ | |
681 | gen_helper_sfmin(RdV, cpu_env, RsV, RtV) | |
682 | #define fGEN_TCG_F2_sfclass(SHORTCODE) \ | |
683 | do { \ | |
23803bbe | 684 | TCGv imm = tcg_constant_tl(uiV); \ |
d9dcdf8a | 685 | gen_helper_sfclass(PdV, cpu_env, RsV, imm); \ |
d9dcdf8a TS |
686 | } while (0) |
687 | #define fGEN_TCG_F2_sffixupn(SHORTCODE) \ | |
688 | gen_helper_sffixupn(RdV, cpu_env, RsV, RtV) | |
689 | #define fGEN_TCG_F2_sffixupd(SHORTCODE) \ | |
690 | gen_helper_sffixupd(RdV, cpu_env, RsV, RtV) | |
691 | #define fGEN_TCG_F2_sffixupr(SHORTCODE) \ | |
692 | gen_helper_sffixupr(RdV, cpu_env, RsV) | |
693 | #define fGEN_TCG_F2_dfadd(SHORTCODE) \ | |
694 | gen_helper_dfadd(RddV, cpu_env, RssV, RttV) | |
695 | #define fGEN_TCG_F2_dfsub(SHORTCODE) \ | |
696 | gen_helper_dfsub(RddV, cpu_env, RssV, RttV) | |
697 | #define fGEN_TCG_F2_dfmax(SHORTCODE) \ | |
698 | gen_helper_dfmax(RddV, cpu_env, RssV, RttV) | |
699 | #define fGEN_TCG_F2_dfmin(SHORTCODE) \ | |
700 | gen_helper_dfmin(RddV, cpu_env, RssV, RttV) | |
701 | #define fGEN_TCG_F2_dfcmpeq(SHORTCODE) \ | |
702 | gen_helper_dfcmpeq(PdV, cpu_env, RssV, RttV) | |
703 | #define fGEN_TCG_F2_dfcmpgt(SHORTCODE) \ | |
704 | gen_helper_dfcmpgt(PdV, cpu_env, RssV, RttV) | |
705 | #define fGEN_TCG_F2_dfcmpge(SHORTCODE) \ | |
706 | gen_helper_dfcmpge(PdV, cpu_env, RssV, RttV) | |
707 | #define fGEN_TCG_F2_dfcmpuo(SHORTCODE) \ | |
708 | gen_helper_dfcmpuo(PdV, cpu_env, RssV, RttV) | |
709 | #define fGEN_TCG_F2_dfclass(SHORTCODE) \ | |
710 | do { \ | |
23803bbe | 711 | TCGv imm = tcg_constant_tl(uiV); \ |
d9dcdf8a | 712 | gen_helper_dfclass(PdV, cpu_env, RssV, imm); \ |
d9dcdf8a TS |
713 | } while (0) |
714 | #define fGEN_TCG_F2_sfmpy(SHORTCODE) \ | |
715 | gen_helper_sfmpy(RdV, cpu_env, RsV, RtV) | |
716 | #define fGEN_TCG_F2_sffma(SHORTCODE) \ | |
717 | gen_helper_sffma(RxV, cpu_env, RxV, RsV, RtV) | |
718 | #define fGEN_TCG_F2_sffma_sc(SHORTCODE) \ | |
719 | gen_helper_sffma_sc(RxV, cpu_env, RxV, RsV, RtV, PuV) | |
720 | #define fGEN_TCG_F2_sffms(SHORTCODE) \ | |
721 | gen_helper_sffms(RxV, cpu_env, RxV, RsV, RtV) | |
722 | #define fGEN_TCG_F2_sffma_lib(SHORTCODE) \ | |
723 | gen_helper_sffma_lib(RxV, cpu_env, RxV, RsV, RtV) | |
724 | #define fGEN_TCG_F2_sffms_lib(SHORTCODE) \ | |
725 | gen_helper_sffms_lib(RxV, cpu_env, RxV, RsV, RtV) | |
726 | ||
727 | #define fGEN_TCG_F2_dfmpyfix(SHORTCODE) \ | |
728 | gen_helper_dfmpyfix(RddV, cpu_env, RssV, RttV) | |
729 | #define fGEN_TCG_F2_dfmpyhh(SHORTCODE) \ | |
730 | gen_helper_dfmpyhh(RxxV, cpu_env, RxxV, RssV, RttV) | |
731 | ||
a5a8d98c TS |
732 | /* Nothing to do for these in qemu, need to suppress compiler warnings */ |
733 | #define fGEN_TCG_Y4_l2fetch(SHORTCODE) \ | |
734 | do { \ | |
735 | RsV = RsV; \ | |
736 | RtV = RtV; \ | |
737 | } while (0) | |
738 | #define fGEN_TCG_Y5_l2fetch(SHORTCODE) \ | |
739 | do { \ | |
740 | RsV = RsV; \ | |
741 | } while (0) | |
742 | ||
6542aa2e | 743 | #endif |