[mirror_qemu.git] / target / hexagon / gen_tcg_hvx.h

/*
 *  Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved.
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; either version 2 of the License, or
 *  (at your option) any later version.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; if not, see <http://www.gnu.org/licenses/>.
 */

#ifndef HEXAGON_GEN_TCG_HVX_H
#define HEXAGON_GEN_TCG_HVX_H

/*
 * Histogram instructions
 *
 * Note that these instructions operate directly on the vector registers
 * and therefore happen after commit.
 *
 * The generate_<tag> function is called twice
 *     The first time is during the normal TCG generation
 *         ctx->pre_commit is true
 *         In the masked cases, we save the mask to the qtmp temporary
 *         Otherwise, there is nothing to do
 *     The second call is at the end of gen_commit_packet
 *         ctx->pre_commit is false
 *         Generate the call to the helper
 */

static inline void assert_vhist_tmp(DisasContext *ctx)
{
    /* vhist instructions require exactly one .tmp to be defined */
    g_assert(ctx->tmp_vregs_idx == 1);
}

#define fGEN_TCG_V6_vhist(SHORTCODE) \
    if (!ctx->pre_commit) { \
        assert_vhist_tmp(ctx); \
        gen_helper_vhist(cpu_env); \
    }
#define fGEN_TCG_V6_vhistq(SHORTCODE) \
    do { \
        if (ctx->pre_commit) { \
            intptr_t dstoff = offsetof(CPUHexagonState, qtmp); \
            tcg_gen_gvec_mov(MO_64, dstoff, QvV_off, \
                             sizeof(MMVector), sizeof(MMVector)); \
        } else { \
            assert_vhist_tmp(ctx); \
            gen_helper_vhistq(cpu_env); \
        } \
    } while (0)
#define fGEN_TCG_V6_vwhist256(SHORTCODE) \
    if (!ctx->pre_commit) { \
        assert_vhist_tmp(ctx); \
        gen_helper_vwhist256(cpu_env); \
    }
#define fGEN_TCG_V6_vwhist256q(SHORTCODE) \
    do { \
        if (ctx->pre_commit) { \
            intptr_t dstoff = offsetof(CPUHexagonState, qtmp); \
            tcg_gen_gvec_mov(MO_64, dstoff, QvV_off, \
                             sizeof(MMVector), sizeof(MMVector)); \
        } else { \
            assert_vhist_tmp(ctx); \
            gen_helper_vwhist256q(cpu_env); \
        } \
    } while (0)
#define fGEN_TCG_V6_vwhist256_sat(SHORTCODE) \
    if (!ctx->pre_commit) { \
        assert_vhist_tmp(ctx); \
        gen_helper_vwhist256_sat(cpu_env); \
    }
#define fGEN_TCG_V6_vwhist256q_sat(SHORTCODE) \
    do { \
        if (ctx->pre_commit) { \
            intptr_t dstoff = offsetof(CPUHexagonState, qtmp); \
            tcg_gen_gvec_mov(MO_64, dstoff, QvV_off, \
                             sizeof(MMVector), sizeof(MMVector)); \
        } else { \
            assert_vhist_tmp(ctx); \
            gen_helper_vwhist256q_sat(cpu_env); \
        } \
    } while (0)
#define fGEN_TCG_V6_vwhist128(SHORTCODE) \
    if (!ctx->pre_commit) { \
        assert_vhist_tmp(ctx); \
        gen_helper_vwhist128(cpu_env); \
    }
#define fGEN_TCG_V6_vwhist128q(SHORTCODE) \
    do { \
        if (ctx->pre_commit) { \
            intptr_t dstoff = offsetof(CPUHexagonState, qtmp); \
            tcg_gen_gvec_mov(MO_64, dstoff, QvV_off, \
                             sizeof(MMVector), sizeof(MMVector)); \
        } else { \
            assert_vhist_tmp(ctx); \
            gen_helper_vwhist128q(cpu_env); \
        } \
    } while (0)
#define fGEN_TCG_V6_vwhist128m(SHORTCODE) \
    if (!ctx->pre_commit) { \
        TCGv tcgv_uiV = tcg_constant_tl(uiV); \
        assert_vhist_tmp(ctx); \
        gen_helper_vwhist128m(cpu_env, tcgv_uiV); \
    }
#define fGEN_TCG_V6_vwhist128qm(SHORTCODE) \
    do { \
        if (ctx->pre_commit) { \
            intptr_t dstoff = offsetof(CPUHexagonState, qtmp); \
            tcg_gen_gvec_mov(MO_64, dstoff, QvV_off, \
                             sizeof(MMVector), sizeof(MMVector)); \
        } else { \
            TCGv tcgv_uiV = tcg_constant_tl(uiV); \
            assert_vhist_tmp(ctx); \
            gen_helper_vwhist128qm(cpu_env, tcgv_uiV); \
        } \
    } while (0)


#define fGEN_TCG_V6_vassign(SHORTCODE) \
    tcg_gen_gvec_mov(MO_64, VdV_off, VuV_off, \
                     sizeof(MMVector), sizeof(MMVector))

/* Vector conditional move */
#define fGEN_TCG_VEC_CMOV(PRED) \
    do { \
        TCGv lsb = tcg_temp_new(); \
        TCGLabel *false_label = gen_new_label(); \
        TCGLabel *end_label = gen_new_label(); \
        tcg_gen_andi_tl(lsb, PsV, 1); \
        tcg_gen_brcondi_tl(TCG_COND_NE, lsb, PRED, false_label); \
        tcg_temp_free(lsb); \
        tcg_gen_gvec_mov(MO_64, VdV_off, VuV_off, \
                         sizeof(MMVector), sizeof(MMVector)); \
        tcg_gen_br(end_label); \
        gen_set_label(false_label); \
        tcg_gen_ori_tl(hex_slot_cancelled, hex_slot_cancelled, \
                       1 << insn->slot); \
        gen_set_label(end_label); \
    } while (0)


/* Vector conditional move (true) */
#define fGEN_TCG_V6_vcmov(SHORTCODE) \
    fGEN_TCG_VEC_CMOV(1)

/* Vector conditional move (false) */
#define fGEN_TCG_V6_vncmov(SHORTCODE) \
    fGEN_TCG_VEC_CMOV(0)

/* Vector add - various forms */
#define fGEN_TCG_V6_vaddb(SHORTCODE) \
    tcg_gen_gvec_add(MO_8, VdV_off, VuV_off, VvV_off, \
                     sizeof(MMVector), sizeof(MMVector))

#define fGEN_TCG_V6_vaddh(SHORTCYDE) \
    tcg_gen_gvec_add(MO_16, VdV_off, VuV_off, VvV_off, \
                     sizeof(MMVector), sizeof(MMVector))

#define fGEN_TCG_V6_vaddw(SHORTCODE) \
    tcg_gen_gvec_add(MO_32, VdV_off, VuV_off, VvV_off, \
                     sizeof(MMVector), sizeof(MMVector))

#define fGEN_TCG_V6_vaddb_dv(SHORTCODE) \
    tcg_gen_gvec_add(MO_8, VddV_off, VuuV_off, VvvV_off, \
                     sizeof(MMVector) * 2, sizeof(MMVector) * 2)

#define fGEN_TCG_V6_vaddh_dv(SHORTCYDE) \
    tcg_gen_gvec_add(MO_16, VddV_off, VuuV_off, VvvV_off, \
                     sizeof(MMVector) * 2, sizeof(MMVector) * 2)

#define fGEN_TCG_V6_vaddw_dv(SHORTCODE) \
    tcg_gen_gvec_add(MO_32, VddV_off, VuuV_off, VvvV_off, \
                     sizeof(MMVector) * 2, sizeof(MMVector) * 2)

/* Vector sub - various forms */
#define fGEN_TCG_V6_vsubb(SHORTCODE) \
    tcg_gen_gvec_sub(MO_8, VdV_off, VuV_off, VvV_off, \
                     sizeof(MMVector), sizeof(MMVector))

#define fGEN_TCG_V6_vsubh(SHORTCODE) \
    tcg_gen_gvec_sub(MO_16, VdV_off, VuV_off, VvV_off, \
                     sizeof(MMVector), sizeof(MMVector))

#define fGEN_TCG_V6_vsubw(SHORTCODE) \
    tcg_gen_gvec_sub(MO_32, VdV_off, VuV_off, VvV_off, \
                     sizeof(MMVector), sizeof(MMVector))

#define fGEN_TCG_V6_vsubb_dv(SHORTCODE) \
    tcg_gen_gvec_sub(MO_8, VddV_off, VuuV_off, VvvV_off, \
                     sizeof(MMVector) * 2, sizeof(MMVector) * 2)

#define fGEN_TCG_V6_vsubh_dv(SHORTCODE) \
    tcg_gen_gvec_sub(MO_16, VddV_off, VuuV_off, VvvV_off, \
                     sizeof(MMVector) * 2, sizeof(MMVector) * 2)

#define fGEN_TCG_V6_vsubw_dv(SHORTCODE) \
    tcg_gen_gvec_sub(MO_32, VddV_off, VuuV_off, VvvV_off, \
                     sizeof(MMVector) * 2, sizeof(MMVector) * 2)

/* Vector shift right - various forms */
#define fGEN_TCG_V6_vasrh(SHORTCODE) \
    do { \
        TCGv shift = tcg_temp_new(); \
        tcg_gen_andi_tl(shift, RtV, 15); \
        tcg_gen_gvec_sars(MO_16, VdV_off, VuV_off, shift, \
                          sizeof(MMVector), sizeof(MMVector)); \
        tcg_temp_free(shift); \
    } while (0)

#define fGEN_TCG_V6_vasrh_acc(SHORTCODE) \
    do { \
        intptr_t tmpoff = offsetof(CPUHexagonState, vtmp); \
        TCGv shift = tcg_temp_new(); \
        tcg_gen_andi_tl(shift, RtV, 15); \
        tcg_gen_gvec_sars(MO_16, tmpoff, VuV_off, shift, \
                          sizeof(MMVector), sizeof(MMVector)); \
        tcg_gen_gvec_add(MO_16, VxV_off, VxV_off, tmpoff, \
                         sizeof(MMVector), sizeof(MMVector)); \
        tcg_temp_free(shift); \
    } while (0)

#define fGEN_TCG_V6_vasrw(SHORTCODE) \
    do { \
        TCGv shift = tcg_temp_new(); \
        tcg_gen_andi_tl(shift, RtV, 31); \
        tcg_gen_gvec_sars(MO_32, VdV_off, VuV_off, shift, \
                          sizeof(MMVector), sizeof(MMVector)); \
        tcg_temp_free(shift); \
    } while (0)

#define fGEN_TCG_V6_vasrw_acc(SHORTCODE) \
    do { \
        intptr_t tmpoff = offsetof(CPUHexagonState, vtmp); \
        TCGv shift = tcg_temp_new(); \
        tcg_gen_andi_tl(shift, RtV, 31); \
        tcg_gen_gvec_sars(MO_32, tmpoff, VuV_off, shift, \
                          sizeof(MMVector), sizeof(MMVector)); \
        tcg_gen_gvec_add(MO_32, VxV_off, VxV_off, tmpoff, \
                          sizeof(MMVector), sizeof(MMVector)); \
        tcg_temp_free(shift); \
    } while (0)

#define fGEN_TCG_V6_vlsrb(SHORTCODE) \
    do { \
        TCGv shift = tcg_temp_new(); \
        tcg_gen_andi_tl(shift, RtV, 7); \
        tcg_gen_gvec_shrs(MO_8, VdV_off, VuV_off, shift, \
                          sizeof(MMVector), sizeof(MMVector)); \
        tcg_temp_free(shift); \
    } while (0)

#define fGEN_TCG_V6_vlsrh(SHORTCODE) \
    do { \
        TCGv shift = tcg_temp_new(); \
        tcg_gen_andi_tl(shift, RtV, 15); \
        tcg_gen_gvec_shrs(MO_16, VdV_off, VuV_off, shift, \
                          sizeof(MMVector), sizeof(MMVector)); \
        tcg_temp_free(shift); \
    } while (0)

#define fGEN_TCG_V6_vlsrw(SHORTCODE) \
    do { \
        TCGv shift = tcg_temp_new(); \
        tcg_gen_andi_tl(shift, RtV, 31); \
        tcg_gen_gvec_shrs(MO_32, VdV_off, VuV_off, shift, \
                          sizeof(MMVector), sizeof(MMVector)); \
        tcg_temp_free(shift); \
    } while (0)

/* Vector shift left - various forms */
#define fGEN_TCG_V6_vaslb(SHORTCODE) \
    do { \
        TCGv shift = tcg_temp_new(); \
        tcg_gen_andi_tl(shift, RtV, 7); \
        tcg_gen_gvec_shls(MO_8, VdV_off, VuV_off, shift, \
                          sizeof(MMVector), sizeof(MMVector)); \
        tcg_temp_free(shift); \
    } while (0)

#define fGEN_TCG_V6_vaslh(SHORTCODE) \
    do { \
        TCGv shift = tcg_temp_new(); \
        tcg_gen_andi_tl(shift, RtV, 15); \
        tcg_gen_gvec_shls(MO_16, VdV_off, VuV_off, shift, \
                          sizeof(MMVector), sizeof(MMVector)); \
        tcg_temp_free(shift); \
    } while (0)

#define fGEN_TCG_V6_vaslh_acc(SHORTCODE) \
    do { \
        intptr_t tmpoff = offsetof(CPUHexagonState, vtmp); \
        TCGv shift = tcg_temp_new(); \
        tcg_gen_andi_tl(shift, RtV, 15); \
        tcg_gen_gvec_shls(MO_16, tmpoff, VuV_off, shift, \
                          sizeof(MMVector), sizeof(MMVector)); \
        tcg_gen_gvec_add(MO_16, VxV_off, VxV_off, tmpoff, \
                         sizeof(MMVector), sizeof(MMVector)); \
        tcg_temp_free(shift); \
    } while (0)

#define fGEN_TCG_V6_vaslw(SHORTCODE) \
    do { \
        TCGv shift = tcg_temp_new(); \
        tcg_gen_andi_tl(shift, RtV, 31); \
        tcg_gen_gvec_shls(MO_32, VdV_off, VuV_off, shift, \
                          sizeof(MMVector), sizeof(MMVector)); \
        tcg_temp_free(shift); \
    } while (0)

#define fGEN_TCG_V6_vaslw_acc(SHORTCODE) \
    do { \
        intptr_t tmpoff = offsetof(CPUHexagonState, vtmp); \
        TCGv shift = tcg_temp_new(); \
        tcg_gen_andi_tl(shift, RtV, 31); \
        tcg_gen_gvec_shls(MO_32, tmpoff, VuV_off, shift, \
                          sizeof(MMVector), sizeof(MMVector)); \
        tcg_gen_gvec_add(MO_32, VxV_off, VxV_off, tmpoff, \
                         sizeof(MMVector), sizeof(MMVector)); \
        tcg_temp_free(shift); \
    } while (0)

/* Vector max - various forms */
#define fGEN_TCG_V6_vmaxw(SHORTCODE) \
    tcg_gen_gvec_smax(MO_32, VdV_off, VuV_off, VvV_off, \
                      sizeof(MMVector), sizeof(MMVector))
#define fGEN_TCG_V6_vmaxh(SHORTCODE) \
    tcg_gen_gvec_smax(MO_16, VdV_off, VuV_off, VvV_off, \
                      sizeof(MMVector), sizeof(MMVector))
#define fGEN_TCG_V6_vmaxuh(SHORTCODE) \
    tcg_gen_gvec_umax(MO_16, VdV_off, VuV_off, VvV_off, \
                      sizeof(MMVector), sizeof(MMVector))
#define fGEN_TCG_V6_vmaxb(SHORTCODE) \
    tcg_gen_gvec_smax(MO_8, VdV_off, VuV_off, VvV_off, \
                      sizeof(MMVector), sizeof(MMVector))
#define fGEN_TCG_V6_vmaxub(SHORTCODE) \
    tcg_gen_gvec_umax(MO_8, VdV_off, VuV_off, VvV_off, \
                      sizeof(MMVector), sizeof(MMVector))

/* Vector min - various forms */
#define fGEN_TCG_V6_vminw(SHORTCODE) \
    tcg_gen_gvec_smin(MO_32, VdV_off, VuV_off, VvV_off, \
                      sizeof(MMVector), sizeof(MMVector))
#define fGEN_TCG_V6_vminh(SHORTCODE) \
    tcg_gen_gvec_smin(MO_16, VdV_off, VuV_off, VvV_off, \
                      sizeof(MMVector), sizeof(MMVector))
#define fGEN_TCG_V6_vminuh(SHORTCODE) \
    tcg_gen_gvec_umin(MO_16, VdV_off, VuV_off, VvV_off, \
                      sizeof(MMVector), sizeof(MMVector))
#define fGEN_TCG_V6_vminb(SHORTCODE) \
    tcg_gen_gvec_smin(MO_8, VdV_off, VuV_off, VvV_off, \
                      sizeof(MMVector), sizeof(MMVector))
#define fGEN_TCG_V6_vminub(SHORTCODE) \
    tcg_gen_gvec_umin(MO_8, VdV_off, VuV_off, VvV_off, \
                      sizeof(MMVector), sizeof(MMVector))

#endif
Commit	Line	Data
d51bcabe TS	1	/*
	2	* Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved.
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License as published by
	6	* the Free Software Foundation; either version 2 of the License, or
	7	* (at your option) any later version.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program; if not, see <http://www.gnu.org/licenses/>.
	16	*/
	17
	18	#ifndef HEXAGON_GEN_TCG_HVX_H
	19	#define HEXAGON_GEN_TCG_HVX_H
	20
7ba7657b TS	21	/*
	22	* Histogram instructions
	23	*
	24	* Note that these instructions operate directly on the vector registers
	25	* and therefore happen after commit.
	26	*
	27	* The generate_<tag> function is called twice
	28	* The first time is during the normal TCG generation
	29	* ctx->pre_commit is true
	30	* In the masked cases, we save the mask to the qtmp temporary
	31	* Otherwise, there is nothing to do
	32	* The second call is at the end of gen_commit_packet
	33	* ctx->pre_commit is false
	34	* Generate the call to the helper
	35	*/
	36
	37	static inline void assert_vhist_tmp(DisasContext *ctx)
	38	{
	39	/* vhist instructions require exactly one .tmp to be defined */
	40	g_assert(ctx->tmp_vregs_idx == 1);
	41	}
	42
	43	#define fGEN_TCG_V6_vhist(SHORTCODE) \
	44	if (!ctx->pre_commit) { \
	45	assert_vhist_tmp(ctx); \
	46	gen_helper_vhist(cpu_env); \
	47	}
	48	#define fGEN_TCG_V6_vhistq(SHORTCODE) \
	49	do { \
	50	if (ctx->pre_commit) { \
	51	intptr_t dstoff = offsetof(CPUHexagonState, qtmp); \
	52	tcg_gen_gvec_mov(MO_64, dstoff, QvV_off, \
	53	sizeof(MMVector), sizeof(MMVector)); \
	54	} else { \
	55	assert_vhist_tmp(ctx); \
	56	gen_helper_vhistq(cpu_env); \
	57	} \
	58	} while (0)
	59	#define fGEN_TCG_V6_vwhist256(SHORTCODE) \
	60	if (!ctx->pre_commit) { \
	61	assert_vhist_tmp(ctx); \
	62	gen_helper_vwhist256(cpu_env); \
	63	}
	64	#define fGEN_TCG_V6_vwhist256q(SHORTCODE) \
	65	do { \
	66	if (ctx->pre_commit) { \
	67	intptr_t dstoff = offsetof(CPUHexagonState, qtmp); \
	68	tcg_gen_gvec_mov(MO_64, dstoff, QvV_off, \
	69	sizeof(MMVector), sizeof(MMVector)); \
	70	} else { \
	71	assert_vhist_tmp(ctx); \
	72	gen_helper_vwhist256q(cpu_env); \
	73	} \
	74	} while (0)
	75	#define fGEN_TCG_V6_vwhist256_sat(SHORTCODE) \
	76	if (!ctx->pre_commit) { \
	77	assert_vhist_tmp(ctx); \
	78	gen_helper_vwhist256_sat(cpu_env); \
	79	}
	80	#define fGEN_TCG_V6_vwhist256q_sat(SHORTCODE) \
	81	do { \
	82	if (ctx->pre_commit) { \
	83	intptr_t dstoff = offsetof(CPUHexagonState, qtmp); \
	84	tcg_gen_gvec_mov(MO_64, dstoff, QvV_off, \
85	sizeof(MMVector), sizeof(MMVector)); \
86	} else { \
87	assert_vhist_tmp(ctx); \
88	gen_helper_vwhist256q_sat(cpu_env); \
89	} \
90	} while (0)
91	#define fGEN_TCG_V6_vwhist128(SHORTCODE) \
92	if (!ctx->pre_commit) { \
93	assert_vhist_tmp(ctx); \
94	gen_helper_vwhist128(cpu_env); \
95	}
96	#define fGEN_TCG_V6_vwhist128q(SHORTCODE) \
97	do { \
98	if (ctx->pre_commit) { \
99	intptr_t dstoff = offsetof(CPUHexagonState, qtmp); \
100	tcg_gen_gvec_mov(MO_64, dstoff, QvV_off, \
101	sizeof(MMVector), sizeof(MMVector)); \
102	} else { \
103	assert_vhist_tmp(ctx); \
104	gen_helper_vwhist128q(cpu_env); \
105	} \
106	} while (0)
107	#define fGEN_TCG_V6_vwhist128m(SHORTCODE) \
108	if (!ctx->pre_commit) { \
109	TCGv tcgv_uiV = tcg_constant_tl(uiV); \
110	assert_vhist_tmp(ctx); \
111	gen_helper_vwhist128m(cpu_env, tcgv_uiV); \
112	}
113	#define fGEN_TCG_V6_vwhist128qm(SHORTCODE) \
114	do { \
115	if (ctx->pre_commit) { \
116	intptr_t dstoff = offsetof(CPUHexagonState, qtmp); \
117	tcg_gen_gvec_mov(MO_64, dstoff, QvV_off, \
118	sizeof(MMVector), sizeof(MMVector)); \
119	} else { \
120	TCGv tcgv_uiV = tcg_constant_tl(uiV); \
121	assert_vhist_tmp(ctx); \
122	gen_helper_vwhist128qm(cpu_env, tcgv_uiV); \
123	} \
124	} while (0)
125
126
32488192 TS	127	#define fGEN_TCG_V6_vassign(SHORTCODE) \
	128	tcg_gen_gvec_mov(MO_64, VdV_off, VuV_off, \
	129	sizeof(MMVector), sizeof(MMVector))
	130
	131	/* Vector conditional move */
	132	#define fGEN_TCG_VEC_CMOV(PRED) \
	133	do { \
	134	TCGv lsb = tcg_temp_new(); \
	135	TCGLabel *false_label = gen_new_label(); \
	136	TCGLabel *end_label = gen_new_label(); \
	137	tcg_gen_andi_tl(lsb, PsV, 1); \
	138	tcg_gen_brcondi_tl(TCG_COND_NE, lsb, PRED, false_label); \
	139	tcg_temp_free(lsb); \
	140	tcg_gen_gvec_mov(MO_64, VdV_off, VuV_off, \
	141	sizeof(MMVector), sizeof(MMVector)); \
	142	tcg_gen_br(end_label); \
	143	gen_set_label(false_label); \
	144	tcg_gen_ori_tl(hex_slot_cancelled, hex_slot_cancelled, \
	145	1 << insn->slot); \
	146	gen_set_label(end_label); \
	147	} while (0)
	148
	149
	150	/* Vector conditional move (true) */
	151	#define fGEN_TCG_V6_vcmov(SHORTCODE) \
	152	fGEN_TCG_VEC_CMOV(1)
	153
	154	/* Vector conditional move (false) */
	155	#define fGEN_TCG_V6_vncmov(SHORTCODE) \
	156	fGEN_TCG_VEC_CMOV(0)
	157
928f0ce4 TS	158	/* Vector add - various forms */
	159	#define fGEN_TCG_V6_vaddb(SHORTCODE) \
	160	tcg_gen_gvec_add(MO_8, VdV_off, VuV_off, VvV_off, \
	161	sizeof(MMVector), sizeof(MMVector))
	162
	163	#define fGEN_TCG_V6_vaddh(SHORTCYDE) \
	164	tcg_gen_gvec_add(MO_16, VdV_off, VuV_off, VvV_off, \
	165	sizeof(MMVector), sizeof(MMVector))
	166
	167	#define fGEN_TCG_V6_vaddw(SHORTCODE) \
	168	tcg_gen_gvec_add(MO_32, VdV_off, VuV_off, VvV_off, \
	169	sizeof(MMVector), sizeof(MMVector))
	170
	171	#define fGEN_TCG_V6_vaddb_dv(SHORTCODE) \
	172	tcg_gen_gvec_add(MO_8, VddV_off, VuuV_off, VvvV_off, \
	173	sizeof(MMVector) * 2, sizeof(MMVector) * 2)
	174
	175	#define fGEN_TCG_V6_vaddh_dv(SHORTCYDE) \
	176	tcg_gen_gvec_add(MO_16, VddV_off, VuuV_off, VvvV_off, \
	177	sizeof(MMVector) * 2, sizeof(MMVector) * 2)
	178
	179	#define fGEN_TCG_V6_vaddw_dv(SHORTCODE) \
	180	tcg_gen_gvec_add(MO_32, VddV_off, VuuV_off, VvvV_off, \
	181	sizeof(MMVector) * 2, sizeof(MMVector) * 2)
	182
	183	/* Vector sub - various forms */
	184	#define fGEN_TCG_V6_vsubb(SHORTCODE) \
	185	tcg_gen_gvec_sub(MO_8, VdV_off, VuV_off, VvV_off, \
	186	sizeof(MMVector), sizeof(MMVector))
	187
	188	#define fGEN_TCG_V6_vsubh(SHORTCODE) \
	189	tcg_gen_gvec_sub(MO_16, VdV_off, VuV_off, VvV_off, \
	190	sizeof(MMVector), sizeof(MMVector))
	191
	192	#define fGEN_TCG_V6_vsubw(SHORTCODE) \
	193	tcg_gen_gvec_sub(MO_32, VdV_off, VuV_off, VvV_off, \
	194	sizeof(MMVector), sizeof(MMVector))
	195
	196	#define fGEN_TCG_V6_vsubb_dv(SHORTCODE) \
	197	tcg_gen_gvec_sub(MO_8, VddV_off, VuuV_off, VvvV_off, \
	198	sizeof(MMVector) * 2, sizeof(MMVector) * 2)
	199
	200	#define fGEN_TCG_V6_vsubh_dv(SHORTCODE) \
	201	tcg_gen_gvec_sub(MO_16, VddV_off, VuuV_off, VvvV_off, \
	202	sizeof(MMVector) * 2, sizeof(MMVector) * 2)
	203
	204	#define fGEN_TCG_V6_vsubw_dv(SHORTCODE) \
	205	tcg_gen_gvec_sub(MO_32, VddV_off, VuuV_off, VvvV_off, \
	206	sizeof(MMVector) * 2, sizeof(MMVector) * 2)
	207
8866635c TS	208	/* Vector shift right - various forms */
	209	#define fGEN_TCG_V6_vasrh(SHORTCODE) \
	210	do { \
	211	TCGv shift = tcg_temp_new(); \
	212	tcg_gen_andi_tl(shift, RtV, 15); \
	213	tcg_gen_gvec_sars(MO_16, VdV_off, VuV_off, shift, \
	214	sizeof(MMVector), sizeof(MMVector)); \
	215	tcg_temp_free(shift); \
	216	} while (0)
	217
	218	#define fGEN_TCG_V6_vasrh_acc(SHORTCODE) \
	219	do { \
	220	intptr_t tmpoff = offsetof(CPUHexagonState, vtmp); \
	221	TCGv shift = tcg_temp_new(); \
	222	tcg_gen_andi_tl(shift, RtV, 15); \
	223	tcg_gen_gvec_sars(MO_16, tmpoff, VuV_off, shift, \
	224	sizeof(MMVector), sizeof(MMVector)); \
	225	tcg_gen_gvec_add(MO_16, VxV_off, VxV_off, tmpoff, \
	226	sizeof(MMVector), sizeof(MMVector)); \
	227	tcg_temp_free(shift); \
	228	} while (0)
	229
	230	#define fGEN_TCG_V6_vasrw(SHORTCODE) \
	231	do { \
	232	TCGv shift = tcg_temp_new(); \
	233	tcg_gen_andi_tl(shift, RtV, 31); \
	234	tcg_gen_gvec_sars(MO_32, VdV_off, VuV_off, shift, \
	235	sizeof(MMVector), sizeof(MMVector)); \
	236	tcg_temp_free(shift); \
	237	} while (0)
	238
	239	#define fGEN_TCG_V6_vasrw_acc(SHORTCODE) \
	240	do { \
	241	intptr_t tmpoff = offsetof(CPUHexagonState, vtmp); \
	242	TCGv shift = tcg_temp_new(); \
	243	tcg_gen_andi_tl(shift, RtV, 31); \
	244	tcg_gen_gvec_sars(MO_32, tmpoff, VuV_off, shift, \
	245	sizeof(MMVector), sizeof(MMVector)); \
	246	tcg_gen_gvec_add(MO_32, VxV_off, VxV_off, tmpoff, \
	247	sizeof(MMVector), sizeof(MMVector)); \
	248	tcg_temp_free(shift); \
	249	} while (0)
	250
	251	#define fGEN_TCG_V6_vlsrb(SHORTCODE) \
	252	do { \
	253	TCGv shift = tcg_temp_new(); \
	254	tcg_gen_andi_tl(shift, RtV, 7); \
	255	tcg_gen_gvec_shrs(MO_8, VdV_off, VuV_off, shift, \
	256	sizeof(MMVector), sizeof(MMVector)); \
	257	tcg_temp_free(shift); \
	258	} while (0)
	259
	260	#define fGEN_TCG_V6_vlsrh(SHORTCODE) \
	261	do { \
	262	TCGv shift = tcg_temp_new(); \
	263	tcg_gen_andi_tl(shift, RtV, 15); \
	264	tcg_gen_gvec_shrs(MO_16, VdV_off, VuV_off, shift, \
	265	sizeof(MMVector), sizeof(MMVector)); \
	266	tcg_temp_free(shift); \
	267	} while (0)
	268
	269	#define fGEN_TCG_V6_vlsrw(SHORTCODE) \
	270	do { \
	271	TCGv shift = tcg_temp_new(); \
272	tcg_gen_andi_tl(shift, RtV, 31); \
273	tcg_gen_gvec_shrs(MO_32, VdV_off, VuV_off, shift, \
274	sizeof(MMVector), sizeof(MMVector)); \
275	tcg_temp_free(shift); \
276	} while (0)
277
278	/* Vector shift left - various forms */
279	#define fGEN_TCG_V6_vaslb(SHORTCODE) \
280	do { \
281	TCGv shift = tcg_temp_new(); \
282	tcg_gen_andi_tl(shift, RtV, 7); \
283	tcg_gen_gvec_shls(MO_8, VdV_off, VuV_off, shift, \
284	sizeof(MMVector), sizeof(MMVector)); \
285	tcg_temp_free(shift); \
286	} while (0)
287
288	#define fGEN_TCG_V6_vaslh(SHORTCODE) \
289	do { \
290	TCGv shift = tcg_temp_new(); \
291	tcg_gen_andi_tl(shift, RtV, 15); \
292	tcg_gen_gvec_shls(MO_16, VdV_off, VuV_off, shift, \
293	sizeof(MMVector), sizeof(MMVector)); \
294	tcg_temp_free(shift); \
295	} while (0)
296
297	#define fGEN_TCG_V6_vaslh_acc(SHORTCODE) \
298	do { \
299	intptr_t tmpoff = offsetof(CPUHexagonState, vtmp); \
300	TCGv shift = tcg_temp_new(); \
301	tcg_gen_andi_tl(shift, RtV, 15); \
302	tcg_gen_gvec_shls(MO_16, tmpoff, VuV_off, shift, \
303	sizeof(MMVector), sizeof(MMVector)); \
304	tcg_gen_gvec_add(MO_16, VxV_off, VxV_off, tmpoff, \
305	sizeof(MMVector), sizeof(MMVector)); \
306	tcg_temp_free(shift); \
307	} while (0)
308
309	#define fGEN_TCG_V6_vaslw(SHORTCODE) \
310	do { \
311	TCGv shift = tcg_temp_new(); \
312	tcg_gen_andi_tl(shift, RtV, 31); \
313	tcg_gen_gvec_shls(MO_32, VdV_off, VuV_off, shift, \
314	sizeof(MMVector), sizeof(MMVector)); \
315	tcg_temp_free(shift); \
316	} while (0)
317
318	#define fGEN_TCG_V6_vaslw_acc(SHORTCODE) \
319	do { \
320	intptr_t tmpoff = offsetof(CPUHexagonState, vtmp); \
321	TCGv shift = tcg_temp_new(); \
322	tcg_gen_andi_tl(shift, RtV, 31); \
323	tcg_gen_gvec_shls(MO_32, tmpoff, VuV_off, shift, \
324	sizeof(MMVector), sizeof(MMVector)); \
325	tcg_gen_gvec_add(MO_32, VxV_off, VxV_off, tmpoff, \
326	sizeof(MMVector), sizeof(MMVector)); \
327	tcg_temp_free(shift); \
328	} while (0)
329
2c8ffa8f TS	330	/* Vector max - various forms */
	331	#define fGEN_TCG_V6_vmaxw(SHORTCODE) \
	332	tcg_gen_gvec_smax(MO_32, VdV_off, VuV_off, VvV_off, \
	333	sizeof(MMVector), sizeof(MMVector))
	334	#define fGEN_TCG_V6_vmaxh(SHORTCODE) \
	335	tcg_gen_gvec_smax(MO_16, VdV_off, VuV_off, VvV_off, \
	336	sizeof(MMVector), sizeof(MMVector))
	337	#define fGEN_TCG_V6_vmaxuh(SHORTCODE) \
	338	tcg_gen_gvec_umax(MO_16, VdV_off, VuV_off, VvV_off, \
	339	sizeof(MMVector), sizeof(MMVector))
	340	#define fGEN_TCG_V6_vmaxb(SHORTCODE) \
	341	tcg_gen_gvec_smax(MO_8, VdV_off, VuV_off, VvV_off, \
	342	sizeof(MMVector), sizeof(MMVector))
	343	#define fGEN_TCG_V6_vmaxub(SHORTCODE) \
	344	tcg_gen_gvec_umax(MO_8, VdV_off, VuV_off, VvV_off, \
	345	sizeof(MMVector), sizeof(MMVector))
	346
	347	/* Vector min - various forms */
	348	#define fGEN_TCG_V6_vminw(SHORTCODE) \
	349	tcg_gen_gvec_smin(MO_32, VdV_off, VuV_off, VvV_off, \
	350	sizeof(MMVector), sizeof(MMVector))
	351	#define fGEN_TCG_V6_vminh(SHORTCODE) \
	352	tcg_gen_gvec_smin(MO_16, VdV_off, VuV_off, VvV_off, \
	353	sizeof(MMVector), sizeof(MMVector))
	354	#define fGEN_TCG_V6_vminuh(SHORTCODE) \
	355	tcg_gen_gvec_umin(MO_16, VdV_off, VuV_off, VvV_off, \
	356	sizeof(MMVector), sizeof(MMVector))
	357	#define fGEN_TCG_V6_vminb(SHORTCODE) \
	358	tcg_gen_gvec_smin(MO_8, VdV_off, VuV_off, VvV_off, \
	359	sizeof(MMVector), sizeof(MMVector))
	360	#define fGEN_TCG_V6_vminub(SHORTCODE) \
	361	tcg_gen_gvec_umin(MO_8, VdV_off, VuV_off, VvV_off, \
	362	sizeof(MMVector), sizeof(MMVector))
	363
d51bcabe	364	#endif