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a646e99c | 1 | /* |
5b0043c6 | 2 | * Copyright(c) 2019-2022 Qualcomm Innovation Center, Inc. All Rights Reserved. |
a646e99c TS |
3 | * |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License as published by | |
6 | * the Free Software Foundation; either version 2 of the License, or | |
7 | * (at your option) any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, see <http://www.gnu.org/licenses/>. | |
16 | */ | |
17 | ||
18 | #ifndef HEXAGON_MACROS_H | |
19 | #define HEXAGON_MACROS_H | |
20 | ||
21 | #include "cpu.h" | |
22 | #include "hex_regs.h" | |
23 | #include "reg_fields.h" | |
24 | ||
25 | #ifdef QEMU_GENERATE | |
26 | #define READ_REG(dest, NUM) gen_read_reg(dest, NUM) | |
a646e99c TS |
27 | #else |
28 | #define READ_REG(NUM) (env->gpr[(NUM)]) | |
29 | #define READ_PREG(NUM) (env->pred[NUM]) | |
30 | ||
31 | #define WRITE_RREG(NUM, VAL) log_reg_write(env, NUM, VAL, slot) | |
32 | #define WRITE_PREG(NUM, VAL) log_pred_write(env, NUM, VAL) | |
33 | #endif | |
34 | ||
35 | #define PCALIGN 4 | |
36 | #define PCALIGN_MASK (PCALIGN - 1) | |
37 | ||
38 | #define GET_FIELD(FIELD, REGIN) \ | |
39 | fEXTRACTU_BITS(REGIN, reg_field_info[FIELD].width, \ | |
40 | reg_field_info[FIELD].offset) | |
41 | ||
42 | #ifdef QEMU_GENERATE | |
43 | #define GET_USR_FIELD(FIELD, DST) \ | |
44 | tcg_gen_extract_tl(DST, hex_gpr[HEX_REG_USR], \ | |
45 | reg_field_info[FIELD].offset, \ | |
46 | reg_field_info[FIELD].width) | |
47 | ||
48 | #define TYPE_INT(X) __builtin_types_compatible_p(typeof(X), int) | |
49 | #define TYPE_TCGV(X) __builtin_types_compatible_p(typeof(X), TCGv) | |
50 | #define TYPE_TCGV_I64(X) __builtin_types_compatible_p(typeof(X), TCGv_i64) | |
51 | ||
52 | #define SET_USR_FIELD_FUNC(X) \ | |
53 | __builtin_choose_expr(TYPE_INT(X), \ | |
54 | gen_set_usr_fieldi, \ | |
55 | __builtin_choose_expr(TYPE_TCGV(X), \ | |
56 | gen_set_usr_field, (void)0)) | |
57 | #define SET_USR_FIELD(FIELD, VAL) \ | |
58 | SET_USR_FIELD_FUNC(VAL)(FIELD, VAL) | |
59 | #else | |
60 | #define GET_USR_FIELD(FIELD) \ | |
61 | fEXTRACTU_BITS(env->gpr[HEX_REG_USR], reg_field_info[FIELD].width, \ | |
62 | reg_field_info[FIELD].offset) | |
63 | ||
64 | #define SET_USR_FIELD(FIELD, VAL) \ | |
b9dd6ff9 | 65 | fINSERT_BITS(env->new_value[HEX_REG_USR], reg_field_info[FIELD].width, \ |
a646e99c TS |
66 | reg_field_info[FIELD].offset, (VAL)) |
67 | #endif | |
68 | ||
69 | #ifdef QEMU_GENERATE | |
70 | /* | |
71 | * Section 5.5 of the Hexagon V67 Programmer's Reference Manual | |
72 | * | |
73 | * Slot 1 store with slot 0 load | |
74 | * A slot 1 store operation with a slot 0 load operation can appear in a packet. | |
75 | * The packet attribute :mem_noshuf inhibits the instruction reordering that | |
76 | * would otherwise be done by the assembler. For example: | |
77 | * { | |
78 | * memw(R5) = R2 // slot 1 store | |
79 | * R3 = memh(R6) // slot 0 load | |
80 | * }:mem_noshuf | |
81 | * Unlike most packetized operations, these memory operations are not executed | |
82 | * in parallel (Section 3.3.1). Instead, the store instruction in Slot 1 | |
83 | * effectively executes first, followed by the load instruction in Slot 0. If | |
84 | * the addresses of the two operations are overlapping, the load will receive | |
85 | * the newly stored data. This feature is supported in processor versions | |
86 | * V65 or greater. | |
87 | * | |
88 | * | |
89 | * For qemu, we look for a load in slot 0 when there is a store in slot 1 | |
15fc6bad TS |
90 | * in the same packet. When we see this, we call a helper that probes the |
91 | * load to make sure it doesn't fault. Then, we process the store ahead of | |
92 | * the actual load. | |
93 | ||
a646e99c | 94 | */ |
15fc6bad | 95 | #define CHECK_NOSHUF(VA, SIZE) \ |
a646e99c | 96 | do { \ |
1e536334 | 97 | if (insn->slot == 0 && ctx->pkt->pkt_has_store_s1) { \ |
15fc6bad | 98 | probe_noshuf_load(VA, SIZE, ctx->mem_idx); \ |
1e536334 | 99 | process_store(ctx, 1); \ |
15fc6bad TS |
100 | } \ |
101 | } while (0) | |
102 | ||
103 | #define CHECK_NOSHUF_PRED(GET_EA, SIZE, PRED) \ | |
104 | do { \ | |
105 | TCGLabel *label = gen_new_label(); \ | |
106 | tcg_gen_brcondi_tl(TCG_COND_EQ, PRED, 0, label); \ | |
107 | GET_EA; \ | |
1e536334 | 108 | if (insn->slot == 0 && ctx->pkt->pkt_has_store_s1) { \ |
15fc6bad TS |
109 | probe_noshuf_load(EA, SIZE, ctx->mem_idx); \ |
110 | } \ | |
111 | gen_set_label(label); \ | |
1e536334 TS |
112 | if (insn->slot == 0 && ctx->pkt->pkt_has_store_s1) { \ |
113 | process_store(ctx, 1); \ | |
a646e99c TS |
114 | } \ |
115 | } while (0) | |
116 | ||
117 | #define MEM_LOAD1s(DST, VA) \ | |
118 | do { \ | |
15fc6bad | 119 | CHECK_NOSHUF(VA, 1); \ |
a646e99c TS |
120 | tcg_gen_qemu_ld8s(DST, VA, ctx->mem_idx); \ |
121 | } while (0) | |
122 | #define MEM_LOAD1u(DST, VA) \ | |
123 | do { \ | |
15fc6bad | 124 | CHECK_NOSHUF(VA, 1); \ |
a646e99c TS |
125 | tcg_gen_qemu_ld8u(DST, VA, ctx->mem_idx); \ |
126 | } while (0) | |
127 | #define MEM_LOAD2s(DST, VA) \ | |
128 | do { \ | |
15fc6bad | 129 | CHECK_NOSHUF(VA, 2); \ |
a646e99c TS |
130 | tcg_gen_qemu_ld16s(DST, VA, ctx->mem_idx); \ |
131 | } while (0) | |
132 | #define MEM_LOAD2u(DST, VA) \ | |
133 | do { \ | |
15fc6bad | 134 | CHECK_NOSHUF(VA, 2); \ |
a646e99c TS |
135 | tcg_gen_qemu_ld16u(DST, VA, ctx->mem_idx); \ |
136 | } while (0) | |
137 | #define MEM_LOAD4s(DST, VA) \ | |
138 | do { \ | |
15fc6bad | 139 | CHECK_NOSHUF(VA, 4); \ |
a646e99c TS |
140 | tcg_gen_qemu_ld32s(DST, VA, ctx->mem_idx); \ |
141 | } while (0) | |
142 | #define MEM_LOAD4u(DST, VA) \ | |
143 | do { \ | |
15fc6bad | 144 | CHECK_NOSHUF(VA, 4); \ |
a646e99c TS |
145 | tcg_gen_qemu_ld32s(DST, VA, ctx->mem_idx); \ |
146 | } while (0) | |
147 | #define MEM_LOAD8u(DST, VA) \ | |
148 | do { \ | |
15fc6bad | 149 | CHECK_NOSHUF(VA, 8); \ |
a646e99c TS |
150 | tcg_gen_qemu_ld64(DST, VA, ctx->mem_idx); \ |
151 | } while (0) | |
46ef47e2 TS |
152 | |
153 | #define MEM_STORE1_FUNC(X) \ | |
154 | __builtin_choose_expr(TYPE_INT(X), \ | |
155 | gen_store1i, \ | |
156 | __builtin_choose_expr(TYPE_TCGV(X), \ | |
157 | gen_store1, (void)0)) | |
158 | #define MEM_STORE1(VA, DATA, SLOT) \ | |
661ad999 | 159 | MEM_STORE1_FUNC(DATA)(cpu_env, VA, DATA, SLOT) |
46ef47e2 TS |
160 | |
161 | #define MEM_STORE2_FUNC(X) \ | |
162 | __builtin_choose_expr(TYPE_INT(X), \ | |
163 | gen_store2i, \ | |
164 | __builtin_choose_expr(TYPE_TCGV(X), \ | |
165 | gen_store2, (void)0)) | |
166 | #define MEM_STORE2(VA, DATA, SLOT) \ | |
661ad999 | 167 | MEM_STORE2_FUNC(DATA)(cpu_env, VA, DATA, SLOT) |
46ef47e2 TS |
168 | |
169 | #define MEM_STORE4_FUNC(X) \ | |
170 | __builtin_choose_expr(TYPE_INT(X), \ | |
171 | gen_store4i, \ | |
172 | __builtin_choose_expr(TYPE_TCGV(X), \ | |
173 | gen_store4, (void)0)) | |
174 | #define MEM_STORE4(VA, DATA, SLOT) \ | |
661ad999 | 175 | MEM_STORE4_FUNC(DATA)(cpu_env, VA, DATA, SLOT) |
46ef47e2 TS |
176 | |
177 | #define MEM_STORE8_FUNC(X) \ | |
178 | __builtin_choose_expr(TYPE_INT(X), \ | |
179 | gen_store8i, \ | |
180 | __builtin_choose_expr(TYPE_TCGV_I64(X), \ | |
181 | gen_store8, (void)0)) | |
182 | #define MEM_STORE8(VA, DATA, SLOT) \ | |
661ad999 | 183 | MEM_STORE8_FUNC(DATA)(cpu_env, VA, DATA, SLOT) |
a646e99c TS |
184 | #else |
185 | #define MEM_LOAD1s(VA) ((int8_t)mem_load1(env, slot, VA)) | |
186 | #define MEM_LOAD1u(VA) ((uint8_t)mem_load1(env, slot, VA)) | |
187 | #define MEM_LOAD2s(VA) ((int16_t)mem_load2(env, slot, VA)) | |
188 | #define MEM_LOAD2u(VA) ((uint16_t)mem_load2(env, slot, VA)) | |
189 | #define MEM_LOAD4s(VA) ((int32_t)mem_load4(env, slot, VA)) | |
190 | #define MEM_LOAD4u(VA) ((uint32_t)mem_load4(env, slot, VA)) | |
191 | #define MEM_LOAD8s(VA) ((int64_t)mem_load8(env, slot, VA)) | |
192 | #define MEM_LOAD8u(VA) ((uint64_t)mem_load8(env, slot, VA)) | |
193 | ||
194 | #define MEM_STORE1(VA, DATA, SLOT) log_store32(env, VA, DATA, 1, SLOT) | |
195 | #define MEM_STORE2(VA, DATA, SLOT) log_store32(env, VA, DATA, 2, SLOT) | |
196 | #define MEM_STORE4(VA, DATA, SLOT) log_store32(env, VA, DATA, 4, SLOT) | |
197 | #define MEM_STORE8(VA, DATA, SLOT) log_store64(env, VA, DATA, 8, SLOT) | |
198 | #endif | |
199 | ||
42659e04 NI |
200 | #ifdef QEMU_GENERATE |
201 | static inline void gen_cancel(uint32_t slot) | |
202 | { | |
203 | tcg_gen_ori_tl(hex_slot_cancelled, hex_slot_cancelled, 1 << slot); | |
204 | } | |
205 | ||
206 | #define CANCEL gen_cancel(slot); | |
207 | #else | |
a646e99c | 208 | #define CANCEL cancel_slot(env, slot) |
42659e04 | 209 | #endif |
a646e99c TS |
210 | |
211 | #define LOAD_CANCEL(EA) do { CANCEL; } while (0) | |
212 | ||
213 | #ifdef QEMU_GENERATE | |
d909808e | 214 | static inline void gen_pred_cancel(TCGv pred, uint32_t slot_num) |
a646e99c | 215 | { |
f448397a | 216 | TCGv slot_mask = tcg_temp_new(); |
a646e99c | 217 | TCGv tmp = tcg_temp_new(); |
23803bbe | 218 | TCGv zero = tcg_constant_tl(0); |
f448397a | 219 | tcg_gen_ori_tl(slot_mask, hex_slot_cancelled, 1 << slot_num); |
a646e99c TS |
220 | tcg_gen_andi_tl(tmp, pred, 1); |
221 | tcg_gen_movcond_tl(TCG_COND_EQ, hex_slot_cancelled, tmp, zero, | |
222 | slot_mask, hex_slot_cancelled); | |
a646e99c TS |
223 | } |
224 | #define PRED_LOAD_CANCEL(PRED, EA) \ | |
225 | gen_pred_cancel(PRED, insn->is_endloop ? 4 : insn->slot) | |
226 | #endif | |
227 | ||
228 | #define STORE_CANCEL(EA) { env->slot_cancelled |= (1 << slot); } | |
229 | ||
230 | #define fMAX(A, B) (((A) > (B)) ? (A) : (B)) | |
231 | ||
232 | #define fMIN(A, B) (((A) < (B)) ? (A) : (B)) | |
233 | ||
234 | #define fABS(A) (((A) < 0) ? (-(A)) : (A)) | |
235 | #define fINSERT_BITS(REG, WIDTH, OFFSET, INVAL) \ | |
236 | REG = ((WIDTH) ? deposit64(REG, (OFFSET), (WIDTH), (INVAL)) : REG) | |
237 | #define fEXTRACTU_BITS(INREG, WIDTH, OFFSET) \ | |
238 | ((WIDTH) ? extract64((INREG), (OFFSET), (WIDTH)) : 0LL) | |
239 | #define fEXTRACTU_BIDIR(INREG, WIDTH, OFFSET) \ | |
240 | (fZXTN(WIDTH, 32, fBIDIR_LSHIFTR((INREG), (OFFSET), 4_8))) | |
241 | #define fEXTRACTU_RANGE(INREG, HIBIT, LOWBIT) \ | |
242 | (((HIBIT) - (LOWBIT) + 1) ? \ | |
243 | extract64((INREG), (LOWBIT), ((HIBIT) - (LOWBIT) + 1)) : \ | |
244 | 0LL) | |
e628c015 TS |
245 | #define fINSERT_RANGE(INREG, HIBIT, LOWBIT, INVAL) \ |
246 | do { \ | |
247 | int width = ((HIBIT) - (LOWBIT) + 1); \ | |
248 | INREG = (width >= 0 ? \ | |
249 | deposit64((INREG), (LOWBIT), width, (INVAL)) : \ | |
250 | INREG); \ | |
251 | } while (0) | |
a646e99c TS |
252 | |
253 | #define f8BITSOF(VAL) ((VAL) ? 0xff : 0x00) | |
254 | ||
255 | #ifdef QEMU_GENERATE | |
256 | #define fLSBOLD(VAL) tcg_gen_andi_tl(LSB, (VAL), 1) | |
257 | #else | |
258 | #define fLSBOLD(VAL) ((VAL) & 1) | |
259 | #endif | |
260 | ||
261 | #ifdef QEMU_GENERATE | |
07c0f653 TS |
262 | #define fLSBNEW(PVAL) tcg_gen_andi_tl(LSB, (PVAL), 1) |
263 | #define fLSBNEW0 tcg_gen_andi_tl(LSB, hex_new_pred_value[0], 1) | |
264 | #define fLSBNEW1 tcg_gen_andi_tl(LSB, hex_new_pred_value[1], 1) | |
a646e99c | 265 | #else |
07c0f653 TS |
266 | #define fLSBNEW(PVAL) ((PVAL) & 1) |
267 | #define fLSBNEW0 (env->new_pred_value[0] & 1) | |
268 | #define fLSBNEW1 (env->new_pred_value[1] & 1) | |
a646e99c TS |
269 | #endif |
270 | ||
271 | #ifdef QEMU_GENERATE | |
a646e99c TS |
272 | #define fLSBOLDNOT(VAL) \ |
273 | do { \ | |
274 | tcg_gen_andi_tl(LSB, (VAL), 1); \ | |
275 | tcg_gen_xori_tl(LSB, LSB, 1); \ | |
276 | } while (0) | |
277 | #define fLSBNEWNOT(PNUM) \ | |
07c0f653 TS |
278 | do { \ |
279 | tcg_gen_andi_tl(LSB, (PNUM), 1); \ | |
280 | tcg_gen_xori_tl(LSB, LSB, 1); \ | |
281 | } while (0) | |
a646e99c TS |
282 | #else |
283 | #define fLSBNEWNOT(PNUM) (!fLSBNEW(PNUM)) | |
284 | #define fLSBOLDNOT(VAL) (!fLSBOLD(VAL)) | |
285 | #define fLSBNEW0NOT (!fLSBNEW0) | |
286 | #define fLSBNEW1NOT (!fLSBNEW1) | |
287 | #endif | |
288 | ||
289 | #define fNEWREG(VAL) ((int32_t)(VAL)) | |
290 | ||
291 | #define fNEWREG_ST(VAL) (VAL) | |
292 | ||
64458f48 TS |
293 | #define fVSATUVALN(N, VAL) \ |
294 | ({ \ | |
5b0043c6 | 295 | (((int64_t)(VAL)) < 0) ? 0 : ((1LL << (N)) - 1); \ |
64458f48 | 296 | }) |
a646e99c TS |
297 | #define fSATUVALN(N, VAL) \ |
298 | ({ \ | |
299 | fSET_OVERFLOW(); \ | |
300 | ((VAL) < 0) ? 0 : ((1LL << (N)) - 1); \ | |
301 | }) | |
302 | #define fSATVALN(N, VAL) \ | |
303 | ({ \ | |
304 | fSET_OVERFLOW(); \ | |
305 | ((VAL) < 0) ? (-(1LL << ((N) - 1))) : ((1LL << ((N) - 1)) - 1); \ | |
306 | }) | |
64458f48 TS |
307 | #define fVSATVALN(N, VAL) \ |
308 | ({ \ | |
309 | ((VAL) < 0) ? (-(1LL << ((N) - 1))) : ((1LL << ((N) - 1)) - 1); \ | |
310 | }) | |
a646e99c TS |
311 | #define fZXTN(N, M, VAL) (((N) != 0) ? extract64((VAL), 0, (N)) : 0LL) |
312 | #define fSXTN(N, M, VAL) (((N) != 0) ? sextract64((VAL), 0, (N)) : 0LL) | |
313 | #define fSATN(N, VAL) \ | |
314 | ((fSXTN(N, 64, VAL) == (VAL)) ? (VAL) : fSATVALN(N, VAL)) | |
64458f48 TS |
315 | #define fVSATN(N, VAL) \ |
316 | ((fSXTN(N, 64, VAL) == (VAL)) ? (VAL) : fVSATVALN(N, VAL)) | |
a646e99c TS |
317 | #define fADDSAT64(DST, A, B) \ |
318 | do { \ | |
319 | uint64_t __a = fCAST8u(A); \ | |
320 | uint64_t __b = fCAST8u(B); \ | |
321 | uint64_t __sum = __a + __b; \ | |
322 | uint64_t __xor = __a ^ __b; \ | |
323 | const uint64_t __mask = 0x8000000000000000ULL; \ | |
324 | if (__xor & __mask) { \ | |
325 | DST = __sum; \ | |
326 | } \ | |
327 | else if ((__a ^ __sum) & __mask) { \ | |
328 | if (__sum & __mask) { \ | |
329 | DST = 0x7FFFFFFFFFFFFFFFLL; \ | |
330 | fSET_OVERFLOW(); \ | |
331 | } else { \ | |
332 | DST = 0x8000000000000000LL; \ | |
333 | fSET_OVERFLOW(); \ | |
334 | } \ | |
335 | } else { \ | |
336 | DST = __sum; \ | |
337 | } \ | |
338 | } while (0) | |
64458f48 TS |
339 | #define fVSATUN(N, VAL) \ |
340 | ((fZXTN(N, 64, VAL) == (VAL)) ? (VAL) : fVSATUVALN(N, VAL)) | |
a646e99c TS |
341 | #define fSATUN(N, VAL) \ |
342 | ((fZXTN(N, 64, VAL) == (VAL)) ? (VAL) : fSATUVALN(N, VAL)) | |
343 | #define fSATH(VAL) (fSATN(16, VAL)) | |
344 | #define fSATUH(VAL) (fSATUN(16, VAL)) | |
64458f48 TS |
345 | #define fVSATH(VAL) (fVSATN(16, VAL)) |
346 | #define fVSATUH(VAL) (fVSATUN(16, VAL)) | |
a646e99c TS |
347 | #define fSATUB(VAL) (fSATUN(8, VAL)) |
348 | #define fSATB(VAL) (fSATN(8, VAL)) | |
64458f48 TS |
349 | #define fVSATUB(VAL) (fVSATUN(8, VAL)) |
350 | #define fVSATB(VAL) (fVSATN(8, VAL)) | |
a646e99c TS |
351 | #define fIMMEXT(IMM) (IMM = IMM) |
352 | #define fMUST_IMMEXT(IMM) fIMMEXT(IMM) | |
353 | ||
354 | #define fPCALIGN(IMM) IMM = (IMM & ~PCALIGN_MASK) | |
355 | ||
46ef47e2 TS |
356 | #ifdef QEMU_GENERATE |
357 | static inline TCGv gen_read_ireg(TCGv result, TCGv val, int shift) | |
358 | { | |
359 | /* | |
360 | * Section 2.2.4 of the Hexagon V67 Programmer's Reference Manual | |
361 | * | |
362 | * The "I" value from a modifier register is divided into two pieces | |
363 | * LSB bits 23:17 | |
364 | * MSB bits 31:28 | |
365 | * The value is signed | |
366 | * | |
367 | * At the end we shift the result according to the shift argument | |
368 | */ | |
369 | TCGv msb = tcg_temp_new(); | |
370 | TCGv lsb = tcg_temp_new(); | |
371 | ||
372 | tcg_gen_extract_tl(lsb, val, 17, 7); | |
373 | tcg_gen_sari_tl(msb, val, 21); | |
374 | tcg_gen_deposit_tl(result, msb, lsb, 0, 7); | |
375 | ||
376 | tcg_gen_shli_tl(result, result, shift); | |
46ef47e2 TS |
377 | return result; |
378 | } | |
379 | #define fREAD_IREG(VAL, SHIFT) gen_read_ireg(ireg, (VAL), (SHIFT)) | |
380 | #else | |
381 | #define fREAD_IREG(VAL) \ | |
382 | (fSXTN(11, 64, (((VAL) & 0xf0000000) >> 21) | ((VAL >> 17) & 0x7f))) | |
383 | #endif | |
384 | ||
a646e99c TS |
385 | #define fREAD_LR() (READ_REG(HEX_REG_LR)) |
386 | ||
387 | #define fWRITE_LR(A) WRITE_RREG(HEX_REG_LR, A) | |
388 | #define fWRITE_FP(A) WRITE_RREG(HEX_REG_FP, A) | |
389 | #define fWRITE_SP(A) WRITE_RREG(HEX_REG_SP, A) | |
390 | ||
391 | #define fREAD_SP() (READ_REG(HEX_REG_SP)) | |
392 | #define fREAD_LC0 (READ_REG(HEX_REG_LC0)) | |
393 | #define fREAD_LC1 (READ_REG(HEX_REG_LC1)) | |
394 | #define fREAD_SA0 (READ_REG(HEX_REG_SA0)) | |
395 | #define fREAD_SA1 (READ_REG(HEX_REG_SA1)) | |
396 | #define fREAD_FP() (READ_REG(HEX_REG_FP)) | |
397 | #ifdef FIXME | |
398 | /* Figure out how to get insn->extension_valid to helper */ | |
399 | #define fREAD_GP() \ | |
400 | (insn->extension_valid ? 0 : READ_REG(HEX_REG_GP)) | |
401 | #else | |
402 | #define fREAD_GP() READ_REG(HEX_REG_GP) | |
403 | #endif | |
40085901 | 404 | #define fREAD_PC() (PC) |
a646e99c | 405 | |
613653e5 | 406 | #define fREAD_NPC() (next_PC & (0xfffffffe)) |
a646e99c TS |
407 | |
408 | #define fREAD_P0() (READ_PREG(0)) | |
409 | #define fREAD_P3() (READ_PREG(3)) | |
410 | ||
411 | #define fCHECK_PCALIGN(A) | |
412 | ||
fb67c2bf | 413 | #define fWRITE_NPC(A) write_new_pc(env, pkt_has_multi_cof != 0, A) |
a646e99c TS |
414 | |
415 | #define fBRANCH(LOC, TYPE) fWRITE_NPC(LOC) | |
416 | #define fJUMPR(REGNO, TARGET, TYPE) fBRANCH(TARGET, COF_TYPE_JUMPR) | |
417 | #define fHINTJR(TARGET) { /* Not modelled in qemu */} | |
418 | #define fCALL(A) \ | |
419 | do { \ | |
420 | fWRITE_LR(fREAD_NPC()); \ | |
421 | fBRANCH(A, COF_TYPE_CALL); \ | |
422 | } while (0) | |
423 | #define fCALLR(A) \ | |
424 | do { \ | |
425 | fWRITE_LR(fREAD_NPC()); \ | |
426 | fBRANCH(A, COF_TYPE_CALLR); \ | |
427 | } while (0) | |
428 | #define fWRITE_LOOP_REGS0(START, COUNT) \ | |
429 | do { \ | |
430 | WRITE_RREG(HEX_REG_LC0, COUNT); \ | |
431 | WRITE_RREG(HEX_REG_SA0, START); \ | |
432 | } while (0) | |
433 | #define fWRITE_LOOP_REGS1(START, COUNT) \ | |
434 | do { \ | |
435 | WRITE_RREG(HEX_REG_LC1, COUNT); \ | |
436 | WRITE_RREG(HEX_REG_SA1, START);\ | |
437 | } while (0) | |
438 | #define fWRITE_LC0(VAL) WRITE_RREG(HEX_REG_LC0, VAL) | |
439 | #define fWRITE_LC1(VAL) WRITE_RREG(HEX_REG_LC1, VAL) | |
440 | ||
a646e99c TS |
441 | #define fSET_OVERFLOW() SET_USR_FIELD(USR_OVF, 1) |
442 | #define fSET_LPCFG(VAL) SET_USR_FIELD(USR_LPCFG, (VAL)) | |
443 | #define fGET_LPCFG (GET_USR_FIELD(USR_LPCFG)) | |
444 | #define fWRITE_P0(VAL) WRITE_PREG(0, VAL) | |
445 | #define fWRITE_P1(VAL) WRITE_PREG(1, VAL) | |
446 | #define fWRITE_P2(VAL) WRITE_PREG(2, VAL) | |
447 | #define fWRITE_P3(VAL) WRITE_PREG(3, VAL) | |
448 | #define fPART1(WORK) if (part1) { WORK; return; } | |
449 | #define fCAST4u(A) ((uint32_t)(A)) | |
450 | #define fCAST4s(A) ((int32_t)(A)) | |
451 | #define fCAST8u(A) ((uint64_t)(A)) | |
452 | #define fCAST8s(A) ((int64_t)(A)) | |
64458f48 TS |
453 | #define fCAST2_2s(A) ((int16_t)(A)) |
454 | #define fCAST2_2u(A) ((uint16_t)(A)) | |
a646e99c TS |
455 | #define fCAST4_4s(A) ((int32_t)(A)) |
456 | #define fCAST4_4u(A) ((uint32_t)(A)) | |
457 | #define fCAST4_8s(A) ((int64_t)((int32_t)(A))) | |
458 | #define fCAST4_8u(A) ((uint64_t)((uint32_t)(A))) | |
459 | #define fCAST8_8s(A) ((int64_t)(A)) | |
460 | #define fCAST8_8u(A) ((uint64_t)(A)) | |
461 | #define fCAST2_8s(A) ((int64_t)((int16_t)(A))) | |
462 | #define fCAST2_8u(A) ((uint64_t)((uint16_t)(A))) | |
463 | #define fZE8_16(A) ((int16_t)((uint8_t)(A))) | |
464 | #define fSE8_16(A) ((int16_t)((int8_t)(A))) | |
465 | #define fSE16_32(A) ((int32_t)((int16_t)(A))) | |
466 | #define fZE16_32(A) ((uint32_t)((uint16_t)(A))) | |
467 | #define fSE32_64(A) ((int64_t)((int32_t)(A))) | |
468 | #define fZE32_64(A) ((uint64_t)((uint32_t)(A))) | |
469 | #define fSE8_32(A) ((int32_t)((int8_t)(A))) | |
470 | #define fZE8_32(A) ((int32_t)((uint8_t)(A))) | |
471 | #define fMPY8UU(A, B) (int)(fZE8_16(A) * fZE8_16(B)) | |
472 | #define fMPY8US(A, B) (int)(fZE8_16(A) * fSE8_16(B)) | |
473 | #define fMPY8SU(A, B) (int)(fSE8_16(A) * fZE8_16(B)) | |
474 | #define fMPY8SS(A, B) (int)((short)(A) * (short)(B)) | |
475 | #define fMPY16SS(A, B) fSE32_64(fSE16_32(A) * fSE16_32(B)) | |
476 | #define fMPY16UU(A, B) fZE32_64(fZE16_32(A) * fZE16_32(B)) | |
477 | #define fMPY16SU(A, B) fSE32_64(fSE16_32(A) * fZE16_32(B)) | |
478 | #define fMPY16US(A, B) fMPY16SU(B, A) | |
479 | #define fMPY32SS(A, B) (fSE32_64(A) * fSE32_64(B)) | |
480 | #define fMPY32UU(A, B) (fZE32_64(A) * fZE32_64(B)) | |
481 | #define fMPY32SU(A, B) (fSE32_64(A) * fZE32_64(B)) | |
482 | #define fMPY3216SS(A, B) (fSE32_64(A) * fSXTN(16, 64, B)) | |
483 | #define fMPY3216SU(A, B) (fSE32_64(A) * fZXTN(16, 64, B)) | |
484 | #define fROUND(A) (A + 0x8000) | |
485 | #define fCLIP(DST, SRC, U) \ | |
486 | do { \ | |
487 | int32_t maxv = (1 << U) - 1; \ | |
488 | int32_t minv = -(1 << U); \ | |
489 | DST = fMIN(maxv, fMAX(SRC, minv)); \ | |
490 | } while (0) | |
491 | #define fCRND(A) ((((A) & 0x3) == 0x3) ? ((A) + 1) : ((A))) | |
492 | #define fRNDN(A, N) ((((N) == 0) ? (A) : (((fSE32_64(A)) + (1 << ((N) - 1)))))) | |
493 | #define fCRNDN(A, N) (conv_round(A, N)) | |
494 | #define fADD128(A, B) (int128_add(A, B)) | |
495 | #define fSUB128(A, B) (int128_sub(A, B)) | |
496 | #define fSHIFTR128(A, B) (int128_rshift(A, B)) | |
497 | #define fSHIFTL128(A, B) (int128_lshift(A, B)) | |
498 | #define fAND128(A, B) (int128_and(A, B)) | |
499 | #define fCAST8S_16S(A) (int128_exts64(A)) | |
500 | #define fCAST16S_8S(A) (int128_getlo(A)) | |
501 | ||
0d0b91a8 TS |
502 | #ifdef QEMU_GENERATE |
503 | #define fEA_RI(REG, IMM) tcg_gen_addi_tl(EA, REG, IMM) | |
504 | #define fEA_RRs(REG, REG2, SCALE) \ | |
505 | do { \ | |
506 | TCGv tmp = tcg_temp_new(); \ | |
507 | tcg_gen_shli_tl(tmp, REG2, SCALE); \ | |
508 | tcg_gen_add_tl(EA, REG, tmp); \ | |
0d0b91a8 TS |
509 | } while (0) |
510 | #define fEA_IRs(IMM, REG, SCALE) \ | |
511 | do { \ | |
512 | tcg_gen_shli_tl(EA, REG, SCALE); \ | |
513 | tcg_gen_addi_tl(EA, EA, IMM); \ | |
514 | } while (0) | |
515 | #else | |
a646e99c TS |
516 | #define fEA_RI(REG, IMM) \ |
517 | do { \ | |
518 | EA = REG + IMM; \ | |
519 | } while (0) | |
520 | #define fEA_RRs(REG, REG2, SCALE) \ | |
521 | do { \ | |
522 | EA = REG + (REG2 << SCALE); \ | |
523 | } while (0) | |
524 | #define fEA_IRs(IMM, REG, SCALE) \ | |
525 | do { \ | |
526 | EA = IMM + (REG << SCALE); \ | |
527 | } while (0) | |
0d0b91a8 | 528 | #endif |
a646e99c TS |
529 | |
530 | #ifdef QEMU_GENERATE | |
531 | #define fEA_IMM(IMM) tcg_gen_movi_tl(EA, IMM) | |
532 | #define fEA_REG(REG) tcg_gen_mov_tl(EA, REG) | |
af7f1821 | 533 | #define fEA_BREVR(REG) gen_helper_fbrev(EA, REG) |
a646e99c TS |
534 | #define fPM_I(REG, IMM) tcg_gen_addi_tl(REG, REG, IMM) |
535 | #define fPM_M(REG, MVAL) tcg_gen_add_tl(REG, REG, MVAL) | |
46ef47e2 TS |
536 | #define fPM_CIRI(REG, IMM, MVAL) \ |
537 | do { \ | |
f448397a | 538 | TCGv tcgv_siV = tcg_constant_tl(siV); \ |
46ef47e2 TS |
539 | gen_helper_fcircadd(REG, REG, tcgv_siV, MuV, \ |
540 | hex_gpr[HEX_REG_CS0 + MuN]); \ | |
46ef47e2 | 541 | } while (0) |
a646e99c TS |
542 | #else |
543 | #define fEA_IMM(IMM) do { EA = (IMM); } while (0) | |
544 | #define fEA_REG(REG) do { EA = (REG); } while (0) | |
545 | #define fEA_GPI(IMM) do { EA = (fREAD_GP() + (IMM)); } while (0) | |
546 | #define fPM_I(REG, IMM) do { REG = REG + (IMM); } while (0) | |
547 | #define fPM_M(REG, MVAL) do { REG = REG + (MVAL); } while (0) | |
548 | #endif | |
549 | #define fSCALE(N, A) (((int64_t)(A)) << N) | |
64458f48 | 550 | #define fVSATW(A) fVSATN(32, ((long long)A)) |
a646e99c | 551 | #define fSATW(A) fSATN(32, ((long long)A)) |
64458f48 | 552 | #define fVSAT(A) fVSATN(32, (A)) |
a646e99c TS |
553 | #define fSAT(A) fSATN(32, (A)) |
554 | #define fSAT_ORIG_SHL(A, ORIG_REG) \ | |
555 | ((((int32_t)((fSAT(A)) ^ ((int32_t)(ORIG_REG)))) < 0) \ | |
556 | ? fSATVALN(32, ((int32_t)(ORIG_REG))) \ | |
557 | : ((((ORIG_REG) > 0) && ((A) == 0)) ? fSATVALN(32, (ORIG_REG)) \ | |
558 | : fSAT(A))) | |
559 | #define fPASS(A) A | |
560 | #define fBIDIR_SHIFTL(SRC, SHAMT, REGSTYPE) \ | |
561 | (((SHAMT) < 0) ? ((fCAST##REGSTYPE(SRC) >> ((-(SHAMT)) - 1)) >> 1) \ | |
562 | : (fCAST##REGSTYPE(SRC) << (SHAMT))) | |
563 | #define fBIDIR_ASHIFTL(SRC, SHAMT, REGSTYPE) \ | |
564 | fBIDIR_SHIFTL(SRC, SHAMT, REGSTYPE##s) | |
565 | #define fBIDIR_LSHIFTL(SRC, SHAMT, REGSTYPE) \ | |
566 | fBIDIR_SHIFTL(SRC, SHAMT, REGSTYPE##u) | |
567 | #define fBIDIR_ASHIFTL_SAT(SRC, SHAMT, REGSTYPE) \ | |
568 | (((SHAMT) < 0) ? ((fCAST##REGSTYPE##s(SRC) >> ((-(SHAMT)) - 1)) >> 1) \ | |
569 | : fSAT_ORIG_SHL(fCAST##REGSTYPE##s(SRC) << (SHAMT), (SRC))) | |
570 | #define fBIDIR_SHIFTR(SRC, SHAMT, REGSTYPE) \ | |
571 | (((SHAMT) < 0) ? ((fCAST##REGSTYPE(SRC) << ((-(SHAMT)) - 1)) << 1) \ | |
572 | : (fCAST##REGSTYPE(SRC) >> (SHAMT))) | |
573 | #define fBIDIR_ASHIFTR(SRC, SHAMT, REGSTYPE) \ | |
574 | fBIDIR_SHIFTR(SRC, SHAMT, REGSTYPE##s) | |
575 | #define fBIDIR_LSHIFTR(SRC, SHAMT, REGSTYPE) \ | |
576 | fBIDIR_SHIFTR(SRC, SHAMT, REGSTYPE##u) | |
577 | #define fBIDIR_ASHIFTR_SAT(SRC, SHAMT, REGSTYPE) \ | |
578 | (((SHAMT) < 0) ? fSAT_ORIG_SHL((fCAST##REGSTYPE##s(SRC) \ | |
579 | << ((-(SHAMT)) - 1)) << 1, (SRC)) \ | |
580 | : (fCAST##REGSTYPE##s(SRC) >> (SHAMT))) | |
581 | #define fASHIFTR(SRC, SHAMT, REGSTYPE) (fCAST##REGSTYPE##s(SRC) >> (SHAMT)) | |
582 | #define fLSHIFTR(SRC, SHAMT, REGSTYPE) \ | |
66a1807b | 583 | (((SHAMT) >= (sizeof(SRC) * 8)) ? 0 : (fCAST##REGSTYPE##u(SRC) >> (SHAMT))) |
a646e99c TS |
584 | #define fROTL(SRC, SHAMT, REGSTYPE) \ |
585 | (((SHAMT) == 0) ? (SRC) : ((fCAST##REGSTYPE##u(SRC) << (SHAMT)) | \ | |
586 | ((fCAST##REGSTYPE##u(SRC) >> \ | |
587 | ((sizeof(SRC) * 8) - (SHAMT)))))) | |
588 | #define fROTR(SRC, SHAMT, REGSTYPE) \ | |
589 | (((SHAMT) == 0) ? (SRC) : ((fCAST##REGSTYPE##u(SRC) >> (SHAMT)) | \ | |
590 | ((fCAST##REGSTYPE##u(SRC) << \ | |
591 | ((sizeof(SRC) * 8) - (SHAMT)))))) | |
592 | #define fASHIFTL(SRC, SHAMT, REGSTYPE) \ | |
66a1807b | 593 | (((SHAMT) >= (sizeof(SRC) * 8)) ? 0 : (fCAST##REGSTYPE##s(SRC) << (SHAMT))) |
a646e99c TS |
594 | |
595 | #ifdef QEMU_GENERATE | |
596 | #define fLOAD(NUM, SIZE, SIGN, EA, DST) MEM_LOAD##SIZE##SIGN(DST, EA) | |
597 | #else | |
598 | #define fLOAD(NUM, SIZE, SIGN, EA, DST) \ | |
599 | DST = (size##SIZE##SIGN##_t)MEM_LOAD##SIZE##SIGN(EA) | |
600 | #endif | |
601 | ||
602 | #define fMEMOP(NUM, SIZE, SIGN, EA, FNTYPE, VALUE) | |
603 | ||
604 | #define fGET_FRAMEKEY() READ_REG(HEX_REG_FRAMEKEY) | |
605 | #define fFRAME_SCRAMBLE(VAL) ((VAL) ^ (fCAST8u(fGET_FRAMEKEY()) << 32)) | |
606 | #define fFRAME_UNSCRAMBLE(VAL) fFRAME_SCRAMBLE(VAL) | |
607 | ||
608 | #ifdef CONFIG_USER_ONLY | |
609 | #define fFRAMECHECK(ADDR, EA) do { } while (0) /* Not modelled in linux-user */ | |
610 | #else | |
611 | /* System mode not implemented yet */ | |
612 | #define fFRAMECHECK(ADDR, EA) g_assert_not_reached(); | |
613 | #endif | |
614 | ||
615 | #ifdef QEMU_GENERATE | |
616 | #define fLOAD_LOCKED(NUM, SIZE, SIGN, EA, DST) \ | |
617 | gen_load_locked##SIZE##SIGN(DST, EA, ctx->mem_idx); | |
618 | #endif | |
619 | ||
46ef47e2 TS |
620 | #ifdef QEMU_GENERATE |
621 | #define fSTORE(NUM, SIZE, EA, SRC) MEM_STORE##SIZE(EA, SRC, insn->slot) | |
622 | #else | |
a646e99c | 623 | #define fSTORE(NUM, SIZE, EA, SRC) MEM_STORE##SIZE(EA, SRC, slot) |
46ef47e2 | 624 | #endif |
a646e99c TS |
625 | |
626 | #ifdef QEMU_GENERATE | |
627 | #define fSTORE_LOCKED(NUM, SIZE, EA, SRC, PRED) \ | |
88725336 | 628 | gen_store_conditional##SIZE(ctx, PRED, EA, SRC); |
a646e99c TS |
629 | #endif |
630 | ||
46ef47e2 TS |
631 | #ifdef QEMU_GENERATE |
632 | #define GETBYTE_FUNC(X) \ | |
633 | __builtin_choose_expr(TYPE_TCGV(X), \ | |
634 | gen_get_byte, \ | |
635 | __builtin_choose_expr(TYPE_TCGV_I64(X), \ | |
636 | gen_get_byte_i64, (void)0)) | |
637 | #define fGETBYTE(N, SRC) GETBYTE_FUNC(SRC)(BYTE, N, SRC, true) | |
638 | #define fGETUBYTE(N, SRC) GETBYTE_FUNC(SRC)(BYTE, N, SRC, false) | |
639 | #else | |
a646e99c TS |
640 | #define fGETBYTE(N, SRC) ((int8_t)((SRC >> ((N) * 8)) & 0xff)) |
641 | #define fGETUBYTE(N, SRC) ((uint8_t)((SRC >> ((N) * 8)) & 0xff)) | |
46ef47e2 | 642 | #endif |
a646e99c TS |
643 | |
644 | #define fSETBYTE(N, DST, VAL) \ | |
645 | do { \ | |
646 | DST = (DST & ~(0x0ffLL << ((N) * 8))) | \ | |
647 | (((uint64_t)((VAL) & 0x0ffLL)) << ((N) * 8)); \ | |
648 | } while (0) | |
46ef47e2 TS |
649 | |
650 | #ifdef QEMU_GENERATE | |
651 | #define fGETHALF(N, SRC) gen_get_half(HALF, N, SRC, true) | |
652 | #define fGETUHALF(N, SRC) gen_get_half(HALF, N, SRC, false) | |
653 | #else | |
a646e99c TS |
654 | #define fGETHALF(N, SRC) ((int16_t)((SRC >> ((N) * 16)) & 0xffff)) |
655 | #define fGETUHALF(N, SRC) ((uint16_t)((SRC >> ((N) * 16)) & 0xffff)) | |
46ef47e2 | 656 | #endif |
a646e99c TS |
657 | #define fSETHALF(N, DST, VAL) \ |
658 | do { \ | |
659 | DST = (DST & ~(0x0ffffLL << ((N) * 16))) | \ | |
660 | (((uint64_t)((VAL) & 0x0ffff)) << ((N) * 16)); \ | |
661 | } while (0) | |
662 | #define fSETHALFw fSETHALF | |
663 | #define fSETHALFd fSETHALF | |
664 | ||
665 | #define fGETWORD(N, SRC) \ | |
666 | ((int64_t)((int32_t)((SRC >> ((N) * 32)) & 0x0ffffffffLL))) | |
667 | #define fGETUWORD(N, SRC) \ | |
668 | ((uint64_t)((uint32_t)((SRC >> ((N) * 32)) & 0x0ffffffffLL))) | |
669 | ||
670 | #define fSETWORD(N, DST, VAL) \ | |
671 | do { \ | |
672 | DST = (DST & ~(0x0ffffffffLL << ((N) * 32))) | \ | |
673 | (((VAL) & 0x0ffffffffLL) << ((N) * 32)); \ | |
674 | } while (0) | |
675 | ||
676 | #define fSETBIT(N, DST, VAL) \ | |
677 | do { \ | |
678 | DST = (DST & ~(1ULL << (N))) | (((uint64_t)(VAL)) << (N)); \ | |
679 | } while (0) | |
680 | ||
681 | #define fGETBIT(N, SRC) (((SRC) >> N) & 1) | |
682 | #define fSETBITS(HI, LO, DST, VAL) \ | |
683 | do { \ | |
684 | int j; \ | |
685 | for (j = LO; j <= HI; j++) { \ | |
686 | fSETBIT(j, DST, VAL); \ | |
687 | } \ | |
688 | } while (0) | |
64458f48 | 689 | #define fCOUNTONES_2(VAL) ctpop16(VAL) |
a646e99c TS |
690 | #define fCOUNTONES_4(VAL) ctpop32(VAL) |
691 | #define fCOUNTONES_8(VAL) ctpop64(VAL) | |
692 | #define fBREV_8(VAL) revbit64(VAL) | |
693 | #define fBREV_4(VAL) revbit32(VAL) | |
694 | #define fCL1_8(VAL) clo64(VAL) | |
695 | #define fCL1_4(VAL) clo32(VAL) | |
64458f48 | 696 | #define fCL1_2(VAL) (clz32(~(uint16_t)(VAL) & 0xffff) - 16) |
a646e99c TS |
697 | #define fINTERLEAVE(ODD, EVEN) interleave(ODD, EVEN) |
698 | #define fDEINTERLEAVE(MIXED) deinterleave(MIXED) | |
699 | #define fHIDE(A) A | |
700 | #define fCONSTLL(A) A##LL | |
701 | #define fECHO(A) (A) | |
702 | ||
703 | #define fTRAP(TRAPTYPE, IMM) helper_raise_exception(env, HEX_EXCP_TRAP0) | |
704 | #define fPAUSE(IMM) | |
705 | ||
706 | #define fALIGN_REG_FIELD_VALUE(FIELD, VAL) \ | |
707 | ((VAL) << reg_field_info[FIELD].offset) | |
708 | #define fGET_REG_FIELD_MASK(FIELD) \ | |
709 | (((1 << reg_field_info[FIELD].width) - 1) << reg_field_info[FIELD].offset) | |
710 | #define fREAD_REG_FIELD(REG, FIELD) \ | |
711 | fEXTRACTU_BITS(env->gpr[HEX_REG_##REG], \ | |
712 | reg_field_info[FIELD].width, \ | |
713 | reg_field_info[FIELD].offset) | |
714 | #define fGET_FIELD(VAL, FIELD) | |
715 | #define fSET_FIELD(VAL, FIELD, NEWVAL) | |
716 | #define fBARRIER() | |
717 | #define fSYNCH() | |
718 | #define fISYNC() | |
719 | #define fDCFETCH(REG) \ | |
720 | do { (void)REG; } while (0) /* Nothing to do in qemu */ | |
721 | #define fICINVA(REG) \ | |
722 | do { (void)REG; } while (0) /* Nothing to do in qemu */ | |
723 | #define fL2FETCH(ADDR, HEIGHT, WIDTH, STRIDE, FLAGS) | |
724 | #define fDCCLEANA(REG) \ | |
725 | do { (void)REG; } while (0) /* Nothing to do in qemu */ | |
726 | #define fDCCLEANINVA(REG) \ | |
727 | do { (void)REG; } while (0) /* Nothing to do in qemu */ | |
728 | ||
729 | #define fDCZEROA(REG) do { env->dczero_addr = (REG); } while (0) | |
730 | ||
731 | #define fBRANCH_SPECULATE_STALL(DOTNEWVAL, JUMP_COND, SPEC_DIR, HINTBITNUM, \ | |
732 | STRBITNUM) /* Nothing */ | |
733 | ||
734 | ||
735 | #endif |