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8b453a2b | 1 | /* |
10849c26 | 2 | * Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved. |
8b453a2b TS |
3 | * |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License as published by | |
6 | * the Free Software Foundation; either version 2 of the License, or | |
7 | * (at your option) any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, see <http://www.gnu.org/licenses/>. | |
16 | */ | |
17 | ||
18 | #define QEMU_GENERATE | |
19 | #include "qemu/osdep.h" | |
20 | #include "cpu.h" | |
21 | #include "tcg/tcg-op.h" | |
a82dd548 | 22 | #include "tcg/tcg-op-gvec.h" |
8b453a2b TS |
23 | #include "exec/cpu_ldst.h" |
24 | #include "exec/log.h" | |
25 | #include "internal.h" | |
26 | #include "attribs.h" | |
27 | #include "insn.h" | |
28 | #include "decode.h" | |
29 | #include "translate.h" | |
30 | #include "printinsn.h" | |
31 | ||
10849c26 TS |
32 | #include "analyze_funcs_generated.c.inc" |
33 | ||
34 | typedef void (*AnalyzeInsn)(DisasContext *ctx); | |
35 | static const AnalyzeInsn opcode_analyze[XX_LAST_OPCODE] = { | |
36 | #define OPCODE(X) [X] = analyze_##X | |
37 | #include "opcodes_def_generated.h.inc" | |
38 | #undef OPCODE | |
39 | }; | |
40 | ||
8b453a2b TS |
41 | TCGv hex_gpr[TOTAL_PER_THREAD_REGS]; |
42 | TCGv hex_pred[NUM_PREGS]; | |
8b453a2b TS |
43 | TCGv hex_this_PC; |
44 | TCGv hex_slot_cancelled; | |
45 | TCGv hex_branch_taken; | |
46 | TCGv hex_new_value[TOTAL_PER_THREAD_REGS]; | |
8b453a2b | 47 | TCGv hex_reg_written[TOTAL_PER_THREAD_REGS]; |
8b453a2b TS |
48 | TCGv hex_new_pred_value[NUM_PREGS]; |
49 | TCGv hex_pred_written; | |
50 | TCGv hex_store_addr[STORES_MAX]; | |
51 | TCGv hex_store_width[STORES_MAX]; | |
52 | TCGv hex_store_val32[STORES_MAX]; | |
53 | TCGv_i64 hex_store_val64[STORES_MAX]; | |
54 | TCGv hex_pkt_has_store_s1; | |
55 | TCGv hex_dczero_addr; | |
56 | TCGv hex_llsc_addr; | |
57 | TCGv hex_llsc_val; | |
58 | TCGv_i64 hex_llsc_val_i64; | |
a82dd548 TS |
59 | TCGv hex_vstore_addr[VSTORES_MAX]; |
60 | TCGv hex_vstore_size[VSTORES_MAX]; | |
61 | TCGv hex_vstore_pending[VSTORES_MAX]; | |
8b453a2b TS |
62 | |
63 | static const char * const hexagon_prednames[] = { | |
64 | "p0", "p1", "p2", "p3" | |
65 | }; | |
66 | ||
a82dd548 TS |
67 | intptr_t ctx_future_vreg_off(DisasContext *ctx, int regnum, |
68 | int num, bool alloc_ok) | |
69 | { | |
70 | intptr_t offset; | |
71 | ||
72 | /* See if it is already allocated */ | |
73 | for (int i = 0; i < ctx->future_vregs_idx; i++) { | |
74 | if (ctx->future_vregs_num[i] == regnum) { | |
75 | return offsetof(CPUHexagonState, future_VRegs[i]); | |
76 | } | |
77 | } | |
78 | ||
79 | g_assert(alloc_ok); | |
80 | offset = offsetof(CPUHexagonState, future_VRegs[ctx->future_vregs_idx]); | |
81 | for (int i = 0; i < num; i++) { | |
82 | ctx->future_vregs_num[ctx->future_vregs_idx + i] = regnum++; | |
83 | } | |
84 | ctx->future_vregs_idx += num; | |
85 | g_assert(ctx->future_vregs_idx <= VECTOR_TEMPS_MAX); | |
86 | return offset; | |
87 | } | |
88 | ||
89 | intptr_t ctx_tmp_vreg_off(DisasContext *ctx, int regnum, | |
90 | int num, bool alloc_ok) | |
91 | { | |
92 | intptr_t offset; | |
93 | ||
94 | /* See if it is already allocated */ | |
95 | for (int i = 0; i < ctx->tmp_vregs_idx; i++) { | |
96 | if (ctx->tmp_vregs_num[i] == regnum) { | |
97 | return offsetof(CPUHexagonState, tmp_VRegs[i]); | |
98 | } | |
99 | } | |
100 | ||
101 | g_assert(alloc_ok); | |
102 | offset = offsetof(CPUHexagonState, tmp_VRegs[ctx->tmp_vregs_idx]); | |
103 | for (int i = 0; i < num; i++) { | |
104 | ctx->tmp_vregs_num[ctx->tmp_vregs_idx + i] = regnum++; | |
105 | } | |
106 | ctx->tmp_vregs_idx += num; | |
107 | g_assert(ctx->tmp_vregs_idx <= VECTOR_TEMPS_MAX); | |
108 | return offset; | |
109 | } | |
110 | ||
743debbc | 111 | static void gen_exception_raw(int excp) |
8b453a2b | 112 | { |
23803bbe | 113 | gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp)); |
8b453a2b TS |
114 | } |
115 | ||
743debbc TS |
116 | static void gen_exec_counters(DisasContext *ctx) |
117 | { | |
118 | tcg_gen_addi_tl(hex_gpr[HEX_REG_QEMU_PKT_CNT], | |
119 | hex_gpr[HEX_REG_QEMU_PKT_CNT], ctx->num_packets); | |
120 | tcg_gen_addi_tl(hex_gpr[HEX_REG_QEMU_INSN_CNT], | |
121 | hex_gpr[HEX_REG_QEMU_INSN_CNT], ctx->num_insns); | |
a82dd548 TS |
122 | tcg_gen_addi_tl(hex_gpr[HEX_REG_QEMU_HVX_CNT], |
123 | hex_gpr[HEX_REG_QEMU_HVX_CNT], ctx->num_hvx_insns); | |
743debbc TS |
124 | } |
125 | ||
1b9a7f2a TS |
126 | static bool use_goto_tb(DisasContext *ctx, target_ulong dest) |
127 | { | |
128 | return translator_use_goto_tb(&ctx->base, dest); | |
129 | } | |
130 | ||
bee1fc56 MTB |
131 | static void gen_goto_tb(DisasContext *ctx, int idx, target_ulong dest, bool |
132 | move_to_pc) | |
1b9a7f2a TS |
133 | { |
134 | if (use_goto_tb(ctx, dest)) { | |
135 | tcg_gen_goto_tb(idx); | |
bee1fc56 MTB |
136 | if (move_to_pc) { |
137 | tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], dest); | |
138 | } | |
1b9a7f2a TS |
139 | tcg_gen_exit_tb(ctx->base.tb, idx); |
140 | } else { | |
bee1fc56 MTB |
141 | if (move_to_pc) { |
142 | tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], dest); | |
143 | } | |
1b9a7f2a TS |
144 | tcg_gen_lookup_and_goto_ptr(); |
145 | } | |
146 | } | |
147 | ||
743debbc | 148 | static void gen_end_tb(DisasContext *ctx) |
8b453a2b | 149 | { |
564b2040 TS |
150 | Packet *pkt = ctx->pkt; |
151 | ||
743debbc | 152 | gen_exec_counters(ctx); |
1b9a7f2a TS |
153 | |
154 | if (ctx->branch_cond != TCG_COND_NEVER) { | |
155 | if (ctx->branch_cond != TCG_COND_ALWAYS) { | |
156 | TCGLabel *skip = gen_new_label(); | |
157 | tcg_gen_brcondi_tl(ctx->branch_cond, hex_branch_taken, 0, skip); | |
bee1fc56 | 158 | gen_goto_tb(ctx, 0, ctx->branch_dest, true); |
1b9a7f2a | 159 | gen_set_label(skip); |
bee1fc56 | 160 | gen_goto_tb(ctx, 1, ctx->next_PC, false); |
1b9a7f2a | 161 | } else { |
bee1fc56 | 162 | gen_goto_tb(ctx, 0, ctx->branch_dest, true); |
1b9a7f2a | 163 | } |
564b2040 TS |
164 | } else if (ctx->is_tight_loop && |
165 | pkt->insn[pkt->num_insns - 1].opcode == J2_endloop0) { | |
166 | /* | |
167 | * When we're in a tight loop, we defer the endloop0 processing | |
168 | * to take advantage of direct block chaining | |
169 | */ | |
170 | TCGLabel *skip = gen_new_label(); | |
171 | tcg_gen_brcondi_tl(TCG_COND_LEU, hex_gpr[HEX_REG_LC0], 1, skip); | |
172 | tcg_gen_subi_tl(hex_gpr[HEX_REG_LC0], hex_gpr[HEX_REG_LC0], 1); | |
bee1fc56 | 173 | gen_goto_tb(ctx, 0, ctx->base.tb->pc, true); |
564b2040 | 174 | gen_set_label(skip); |
bee1fc56 | 175 | gen_goto_tb(ctx, 1, ctx->next_PC, false); |
1b9a7f2a TS |
176 | } else { |
177 | tcg_gen_lookup_and_goto_ptr(); | |
178 | } | |
179 | ||
743debbc TS |
180 | ctx->base.is_jmp = DISAS_NORETURN; |
181 | } | |
182 | ||
183 | static void gen_exception_end_tb(DisasContext *ctx, int excp) | |
184 | { | |
185 | gen_exec_counters(ctx); | |
613653e5 | 186 | tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], ctx->next_PC); |
743debbc TS |
187 | gen_exception_raw(excp); |
188 | ctx->base.is_jmp = DISAS_NORETURN; | |
189 | ||
8b453a2b TS |
190 | } |
191 | ||
8b453a2b TS |
192 | #define PACKET_BUFFER_LEN 1028 |
193 | static void print_pkt(Packet *pkt) | |
194 | { | |
195 | GString *buf = g_string_sized_new(PACKET_BUFFER_LEN); | |
196 | snprint_a_pkt_debug(buf, pkt); | |
197 | HEX_DEBUG_LOG("%s", buf->str); | |
198 | g_string_free(buf, true); | |
199 | } | |
85580a65 TS |
200 | #define HEX_DEBUG_PRINT_PKT(pkt) \ |
201 | do { \ | |
202 | if (HEX_DEBUG) { \ | |
203 | print_pkt(pkt); \ | |
204 | } \ | |
205 | } while (0) | |
8b453a2b TS |
206 | |
207 | static int read_packet_words(CPUHexagonState *env, DisasContext *ctx, | |
208 | uint32_t words[]) | |
209 | { | |
210 | bool found_end = false; | |
211 | int nwords, max_words; | |
212 | ||
213 | memset(words, 0, PACKET_WORDS_MAX * sizeof(uint32_t)); | |
214 | for (nwords = 0; !found_end && nwords < PACKET_WORDS_MAX; nwords++) { | |
a27c100c | 215 | words[nwords] = |
4e116893 IL |
216 | translator_ldl(env, &ctx->base, |
217 | ctx->base.pc_next + nwords * sizeof(uint32_t)); | |
8b453a2b TS |
218 | found_end = is_packet_end(words[nwords]); |
219 | } | |
220 | if (!found_end) { | |
221 | /* Read too many words without finding the end */ | |
222 | return 0; | |
223 | } | |
224 | ||
225 | /* Check for page boundary crossing */ | |
226 | max_words = -(ctx->base.pc_next | TARGET_PAGE_MASK) / sizeof(uint32_t); | |
227 | if (nwords > max_words) { | |
228 | /* We can only cross a page boundary at the beginning of a TB */ | |
229 | g_assert(ctx->base.num_insns == 1); | |
230 | } | |
231 | ||
232 | HEX_DEBUG_LOG("decode_packet: pc = 0x%x\n", ctx->base.pc_next); | |
233 | HEX_DEBUG_LOG(" words = { "); | |
234 | for (int i = 0; i < nwords; i++) { | |
235 | HEX_DEBUG_LOG("0x%x, ", words[i]); | |
236 | } | |
237 | HEX_DEBUG_LOG("}\n"); | |
238 | ||
239 | return nwords; | |
240 | } | |
241 | ||
25e1d87d | 242 | static G_GNUC_UNUSED bool check_for_attrib(Packet *pkt, int attrib) |
8b453a2b TS |
243 | { |
244 | for (int i = 0; i < pkt->num_insns; i++) { | |
245 | if (GET_ATTRIB(pkt->insn[i].opcode, attrib)) { | |
246 | return true; | |
247 | } | |
248 | } | |
249 | return false; | |
250 | } | |
251 | ||
8b453a2b TS |
252 | static bool need_slot_cancelled(Packet *pkt) |
253 | { | |
c2b33d0b | 254 | /* We only need slot_cancelled for conditional store instructions */ |
7b84fd04 TS |
255 | for (int i = 0; i < pkt->num_insns; i++) { |
256 | uint16_t opcode = pkt->insn[i].opcode; | |
257 | if (GET_ATTRIB(opcode, A_CONDEXEC) && | |
c2b33d0b | 258 | GET_ATTRIB(opcode, A_SCALAR_STORE)) { |
7b84fd04 TS |
259 | return true; |
260 | } | |
261 | } | |
262 | return false; | |
8b453a2b TS |
263 | } |
264 | ||
613653e5 TS |
265 | static bool need_next_PC(DisasContext *ctx) |
266 | { | |
267 | Packet *pkt = ctx->pkt; | |
268 | ||
269 | /* Check for conditional control flow or HW loop end */ | |
270 | for (int i = 0; i < pkt->num_insns; i++) { | |
271 | uint16_t opcode = pkt->insn[i].opcode; | |
272 | if (GET_ATTRIB(opcode, A_CONDEXEC) && GET_ATTRIB(opcode, A_COF)) { | |
273 | return true; | |
274 | } | |
275 | if (GET_ATTRIB(opcode, A_HWLOOP0_END) || | |
276 | GET_ATTRIB(opcode, A_HWLOOP1_END)) { | |
277 | return true; | |
278 | } | |
279 | } | |
280 | return false; | |
281 | } | |
282 | ||
10849c26 TS |
283 | /* |
284 | * The opcode_analyze functions mark most of the writes in a packet | |
285 | * However, there are some implicit writes marked as attributes | |
286 | * of the applicable instructions. | |
287 | */ | |
288 | static void mark_implicit_reg_write(DisasContext *ctx, int attrib, int rnum) | |
289 | { | |
290 | uint16_t opcode = ctx->insn->opcode; | |
291 | if (GET_ATTRIB(opcode, attrib)) { | |
292 | /* | |
293 | * USR is used to set overflow and FP exceptions, | |
294 | * so treat it as conditional | |
295 | */ | |
296 | bool is_predicated = GET_ATTRIB(opcode, A_CONDEXEC) || | |
297 | rnum == HEX_REG_USR; | |
298 | ||
299 | /* LC0/LC1 is conditionally written by endloop instructions */ | |
300 | if ((rnum == HEX_REG_LC0 || rnum == HEX_REG_LC1) && | |
301 | (opcode == J2_endloop0 || | |
302 | opcode == J2_endloop1 || | |
303 | opcode == J2_endloop01)) { | |
304 | is_predicated = true; | |
305 | } | |
306 | ||
307 | ctx_log_reg_write(ctx, rnum, is_predicated); | |
308 | } | |
309 | } | |
310 | ||
311 | static void mark_implicit_reg_writes(DisasContext *ctx) | |
312 | { | |
313 | mark_implicit_reg_write(ctx, A_IMPLICIT_WRITES_FP, HEX_REG_FP); | |
314 | mark_implicit_reg_write(ctx, A_IMPLICIT_WRITES_SP, HEX_REG_SP); | |
315 | mark_implicit_reg_write(ctx, A_IMPLICIT_WRITES_LR, HEX_REG_LR); | |
316 | mark_implicit_reg_write(ctx, A_IMPLICIT_WRITES_LC0, HEX_REG_LC0); | |
317 | mark_implicit_reg_write(ctx, A_IMPLICIT_WRITES_SA0, HEX_REG_SA0); | |
318 | mark_implicit_reg_write(ctx, A_IMPLICIT_WRITES_LC1, HEX_REG_LC1); | |
319 | mark_implicit_reg_write(ctx, A_IMPLICIT_WRITES_SA1, HEX_REG_SA1); | |
320 | mark_implicit_reg_write(ctx, A_IMPLICIT_WRITES_USR, HEX_REG_USR); | |
321 | mark_implicit_reg_write(ctx, A_FPOP, HEX_REG_USR); | |
322 | } | |
323 | ||
324 | static void mark_implicit_pred_write(DisasContext *ctx, int attrib, int pnum) | |
325 | { | |
326 | if (GET_ATTRIB(ctx->insn->opcode, attrib)) { | |
327 | ctx_log_pred_write(ctx, pnum); | |
328 | } | |
329 | } | |
330 | ||
331 | static void mark_implicit_pred_writes(DisasContext *ctx) | |
332 | { | |
333 | mark_implicit_pred_write(ctx, A_IMPLICIT_WRITES_P0, 0); | |
334 | mark_implicit_pred_write(ctx, A_IMPLICIT_WRITES_P1, 1); | |
335 | mark_implicit_pred_write(ctx, A_IMPLICIT_WRITES_P2, 2); | |
336 | mark_implicit_pred_write(ctx, A_IMPLICIT_WRITES_P3, 3); | |
337 | } | |
338 | ||
339 | static void analyze_packet(DisasContext *ctx) | |
340 | { | |
341 | Packet *pkt = ctx->pkt; | |
4d13bb51 | 342 | ctx->need_pkt_has_store_s1 = false; |
10849c26 TS |
343 | for (int i = 0; i < pkt->num_insns; i++) { |
344 | Insn *insn = &pkt->insn[i]; | |
345 | ctx->insn = insn; | |
346 | if (opcode_analyze[insn->opcode]) { | |
347 | opcode_analyze[insn->opcode](ctx); | |
348 | } | |
349 | mark_implicit_reg_writes(ctx); | |
350 | mark_implicit_pred_writes(ctx); | |
351 | } | |
352 | } | |
353 | ||
1e536334 | 354 | static void gen_start_packet(DisasContext *ctx) |
8b453a2b | 355 | { |
1e536334 | 356 | Packet *pkt = ctx->pkt; |
8b453a2b TS |
357 | target_ulong next_PC = ctx->base.pc_next + pkt->encod_pkt_size_in_bytes; |
358 | int i; | |
359 | ||
360 | /* Clear out the disassembly context */ | |
613653e5 | 361 | ctx->next_PC = next_PC; |
8b453a2b TS |
362 | ctx->reg_log_idx = 0; |
363 | bitmap_zero(ctx->regs_written, TOTAL_PER_THREAD_REGS); | |
10849c26 | 364 | bitmap_zero(ctx->predicated_regs, TOTAL_PER_THREAD_REGS); |
8b453a2b | 365 | ctx->preg_log_idx = 0; |
6c677c60 | 366 | bitmap_zero(ctx->pregs_written, NUM_PREGS); |
a82dd548 TS |
367 | ctx->future_vregs_idx = 0; |
368 | ctx->tmp_vregs_idx = 0; | |
369 | ctx->vreg_log_idx = 0; | |
370 | bitmap_zero(ctx->vregs_updated_tmp, NUM_VREGS); | |
371 | bitmap_zero(ctx->vregs_updated, NUM_VREGS); | |
372 | bitmap_zero(ctx->vregs_select, NUM_VREGS); | |
4d6f8420 TS |
373 | bitmap_zero(ctx->predicated_future_vregs, NUM_VREGS); |
374 | bitmap_zero(ctx->predicated_tmp_vregs, NUM_VREGS); | |
a82dd548 | 375 | ctx->qreg_log_idx = 0; |
8b453a2b TS |
376 | for (i = 0; i < STORES_MAX; i++) { |
377 | ctx->store_width[i] = 0; | |
378 | } | |
92cfa25f | 379 | ctx->s1_store_processed = false; |
a82dd548 | 380 | ctx->pre_commit = true; |
8b453a2b | 381 | |
10849c26 TS |
382 | analyze_packet(ctx); |
383 | ||
4d13bb51 TS |
384 | if (ctx->need_pkt_has_store_s1) { |
385 | tcg_gen_movi_tl(hex_pkt_has_store_s1, pkt->pkt_has_store_s1); | |
386 | } | |
387 | ||
10849c26 TS |
388 | /* |
389 | * pregs_written is used both in the analyze phase as well as the code | |
390 | * gen phase, so clear it again. | |
391 | */ | |
392 | bitmap_zero(ctx->pregs_written, NUM_PREGS); | |
393 | ||
85580a65 TS |
394 | if (HEX_DEBUG) { |
395 | /* Handy place to set a breakpoint before the packet executes */ | |
396 | gen_helper_debug_start_packet(cpu_env); | |
397 | tcg_gen_movi_tl(hex_this_PC, ctx->base.pc_next); | |
398 | } | |
8b453a2b TS |
399 | |
400 | /* Initialize the runtime state for packet semantics */ | |
8b453a2b TS |
401 | if (need_slot_cancelled(pkt)) { |
402 | tcg_gen_movi_tl(hex_slot_cancelled, 0); | |
403 | } | |
404 | if (pkt->pkt_has_cof) { | |
fb67c2bf TS |
405 | if (pkt->pkt_has_multi_cof) { |
406 | tcg_gen_movi_tl(hex_branch_taken, 0); | |
407 | } | |
613653e5 TS |
408 | if (need_next_PC(ctx)) { |
409 | tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], next_PC); | |
410 | } | |
8b453a2b | 411 | } |
25e1d87d | 412 | if (HEX_DEBUG) { |
8b453a2b TS |
413 | tcg_gen_movi_tl(hex_pred_written, 0); |
414 | } | |
a82dd548 | 415 | |
10849c26 TS |
416 | /* Preload the predicated registers into hex_new_value[i] */ |
417 | if (!bitmap_empty(ctx->predicated_regs, TOTAL_PER_THREAD_REGS)) { | |
418 | int i = find_first_bit(ctx->predicated_regs, TOTAL_PER_THREAD_REGS); | |
419 | while (i < TOTAL_PER_THREAD_REGS) { | |
420 | tcg_gen_mov_tl(hex_new_value[i], hex_gpr[i]); | |
421 | i = find_next_bit(ctx->predicated_regs, TOTAL_PER_THREAD_REGS, | |
422 | i + 1); | |
423 | } | |
424 | } | |
425 | ||
25e1d87d TS |
426 | /* |
427 | * Preload the predicated pred registers into hex_new_pred_value[pred_num] | |
428 | * Only endloop instructions conditionally write to pred registers | |
429 | */ | |
430 | if (pkt->pkt_has_endloop) { | |
431 | for (int i = 0; i < ctx->preg_log_idx; i++) { | |
432 | int pred_num = ctx->preg_log[i]; | |
433 | tcg_gen_mov_tl(hex_new_pred_value[pred_num], hex_pred[pred_num]); | |
434 | } | |
435 | } | |
436 | ||
4d6f8420 TS |
437 | /* Preload the predicated HVX registers into future_VRegs and tmp_VRegs */ |
438 | if (!bitmap_empty(ctx->predicated_future_vregs, NUM_VREGS)) { | |
439 | int i = find_first_bit(ctx->predicated_future_vregs, NUM_VREGS); | |
440 | while (i < NUM_VREGS) { | |
441 | const intptr_t VdV_off = | |
442 | ctx_future_vreg_off(ctx, i, 1, true); | |
443 | intptr_t src_off = offsetof(CPUHexagonState, VRegs[i]); | |
444 | tcg_gen_gvec_mov(MO_64, VdV_off, | |
445 | src_off, | |
446 | sizeof(MMVector), | |
447 | sizeof(MMVector)); | |
448 | i = find_next_bit(ctx->predicated_future_vregs, NUM_VREGS, i + 1); | |
449 | } | |
450 | } | |
451 | if (!bitmap_empty(ctx->predicated_tmp_vregs, NUM_VREGS)) { | |
452 | int i = find_first_bit(ctx->predicated_tmp_vregs, NUM_VREGS); | |
453 | while (i < NUM_VREGS) { | |
454 | const intptr_t VdV_off = | |
455 | ctx_tmp_vreg_off(ctx, i, 1, true); | |
456 | intptr_t src_off = offsetof(CPUHexagonState, VRegs[i]); | |
457 | tcg_gen_gvec_mov(MO_64, VdV_off, | |
458 | src_off, | |
459 | sizeof(MMVector), | |
460 | sizeof(MMVector)); | |
461 | i = find_next_bit(ctx->predicated_tmp_vregs, NUM_VREGS, i + 1); | |
462 | } | |
463 | } | |
a82dd548 TS |
464 | } |
465 | ||
1e536334 | 466 | bool is_gather_store_insn(DisasContext *ctx) |
a82dd548 | 467 | { |
1e536334 TS |
468 | Packet *pkt = ctx->pkt; |
469 | Insn *insn = ctx->insn; | |
a82dd548 TS |
470 | if (GET_ATTRIB(insn->opcode, A_CVI_NEW) && |
471 | insn->new_value_producer_slot == 1) { | |
472 | /* Look for gather instruction */ | |
473 | for (int i = 0; i < pkt->num_insns; i++) { | |
474 | Insn *in = &pkt->insn[i]; | |
475 | if (GET_ATTRIB(in->opcode, A_CVI_GATHER) && in->slot == 1) { | |
476 | return true; | |
477 | } | |
478 | } | |
479 | } | |
480 | return false; | |
8b453a2b TS |
481 | } |
482 | ||
1e536334 | 483 | static void mark_store_width(DisasContext *ctx) |
661ad999 | 484 | { |
1e536334 TS |
485 | uint16_t opcode = ctx->insn->opcode; |
486 | uint32_t slot = ctx->insn->slot; | |
661ad999 TS |
487 | uint8_t width = 0; |
488 | ||
489 | if (GET_ATTRIB(opcode, A_SCALAR_STORE)) { | |
406c74f2 TS |
490 | if (GET_ATTRIB(opcode, A_MEMSIZE_0B)) { |
491 | return; | |
492 | } | |
661ad999 TS |
493 | if (GET_ATTRIB(opcode, A_MEMSIZE_1B)) { |
494 | width |= 1; | |
495 | } | |
496 | if (GET_ATTRIB(opcode, A_MEMSIZE_2B)) { | |
497 | width |= 2; | |
498 | } | |
499 | if (GET_ATTRIB(opcode, A_MEMSIZE_4B)) { | |
500 | width |= 4; | |
501 | } | |
502 | if (GET_ATTRIB(opcode, A_MEMSIZE_8B)) { | |
503 | width |= 8; | |
504 | } | |
505 | tcg_debug_assert(is_power_of_2(width)); | |
506 | ctx->store_width[slot] = width; | |
507 | } | |
508 | } | |
509 | ||
1e536334 | 510 | static void gen_insn(DisasContext *ctx) |
8b453a2b | 511 | { |
1e536334 | 512 | if (ctx->insn->generate) { |
1e536334 | 513 | ctx->insn->generate(ctx); |
1e536334 | 514 | mark_store_width(ctx); |
8b453a2b | 515 | } else { |
743debbc | 516 | gen_exception_end_tb(ctx, HEX_EXCP_INVALID_OPCODE); |
8b453a2b TS |
517 | } |
518 | } | |
519 | ||
520 | /* | |
521 | * Helpers for generating the packet commit | |
522 | */ | |
523 | static void gen_reg_writes(DisasContext *ctx) | |
524 | { | |
525 | int i; | |
526 | ||
527 | for (i = 0; i < ctx->reg_log_idx; i++) { | |
528 | int reg_num = ctx->reg_log[i]; | |
529 | ||
530 | tcg_gen_mov_tl(hex_gpr[reg_num], hex_new_value[reg_num]); | |
564b2040 TS |
531 | |
532 | /* | |
533 | * ctx->is_tight_loop is set when SA0 points to the beginning of the TB. | |
534 | * If we write to SA0, we have to turn off tight loop handling. | |
535 | */ | |
536 | if (reg_num == HEX_REG_SA0) { | |
537 | ctx->is_tight_loop = false; | |
538 | } | |
8b453a2b TS |
539 | } |
540 | } | |
541 | ||
1e536334 | 542 | static void gen_pred_writes(DisasContext *ctx) |
8b453a2b | 543 | { |
8b453a2b TS |
544 | /* Early exit if the log is empty */ |
545 | if (!ctx->preg_log_idx) { | |
546 | return; | |
547 | } | |
548 | ||
25e1d87d TS |
549 | for (int i = 0; i < ctx->preg_log_idx; i++) { |
550 | int pred_num = ctx->preg_log[i]; | |
551 | tcg_gen_mov_tl(hex_pred[pred_num], hex_new_pred_value[pred_num]); | |
8b453a2b | 552 | } |
8b453a2b TS |
553 | } |
554 | ||
a27c100c | 555 | static void gen_check_store_width(DisasContext *ctx, int slot_num) |
8b453a2b | 556 | { |
85580a65 | 557 | if (HEX_DEBUG) { |
23803bbe PMD |
558 | TCGv slot = tcg_constant_tl(slot_num); |
559 | TCGv check = tcg_constant_tl(ctx->store_width[slot_num]); | |
85580a65 | 560 | gen_helper_debug_check_store_width(cpu_env, slot, check); |
85580a65 | 561 | } |
a27c100c | 562 | } |
8b453a2b TS |
563 | |
564 | static bool slot_is_predicated(Packet *pkt, int slot_num) | |
565 | { | |
566 | for (int i = 0; i < pkt->num_insns; i++) { | |
567 | if (pkt->insn[i].slot == slot_num) { | |
568 | return GET_ATTRIB(pkt->insn[i].opcode, A_CONDEXEC); | |
569 | } | |
570 | } | |
571 | /* If we get to here, we didn't find an instruction in the requested slot */ | |
572 | g_assert_not_reached(); | |
573 | } | |
574 | ||
1e536334 | 575 | void process_store(DisasContext *ctx, int slot_num) |
8b453a2b | 576 | { |
1e536334 | 577 | bool is_predicated = slot_is_predicated(ctx->pkt, slot_num); |
8b453a2b TS |
578 | TCGLabel *label_end = NULL; |
579 | ||
580 | /* | |
581 | * We may have already processed this store | |
582 | * See CHECK_NOSHUF in macros.h | |
583 | */ | |
584 | if (slot_num == 1 && ctx->s1_store_processed) { | |
585 | return; | |
586 | } | |
92cfa25f | 587 | ctx->s1_store_processed = true; |
8b453a2b TS |
588 | |
589 | if (is_predicated) { | |
590 | TCGv cancelled = tcg_temp_new(); | |
591 | label_end = gen_new_label(); | |
592 | ||
593 | /* Don't do anything if the slot was cancelled */ | |
594 | tcg_gen_extract_tl(cancelled, hex_slot_cancelled, slot_num, 1); | |
595 | tcg_gen_brcondi_tl(TCG_COND_NE, cancelled, 0, label_end); | |
8b453a2b TS |
596 | } |
597 | { | |
7a819de8 | 598 | TCGv address = tcg_temp_new(); |
8b453a2b TS |
599 | tcg_gen_mov_tl(address, hex_store_addr[slot_num]); |
600 | ||
601 | /* | |
602 | * If we know the width from the DisasContext, we can | |
603 | * generate much cleaner code. | |
604 | * Unfortunately, not all instructions execute the fSTORE | |
605 | * macro during code generation. Anything that uses the | |
606 | * generic helper will have this problem. Instructions | |
607 | * that use fWRAP to generate proper TCG code will be OK. | |
608 | */ | |
609 | switch (ctx->store_width[slot_num]) { | |
610 | case 1: | |
a27c100c | 611 | gen_check_store_width(ctx, slot_num); |
53b26d25 RH |
612 | tcg_gen_qemu_st_tl(hex_store_val32[slot_num], |
613 | hex_store_addr[slot_num], | |
614 | ctx->mem_idx, MO_UB); | |
8b453a2b TS |
615 | break; |
616 | case 2: | |
a27c100c | 617 | gen_check_store_width(ctx, slot_num); |
53b26d25 RH |
618 | tcg_gen_qemu_st_tl(hex_store_val32[slot_num], |
619 | hex_store_addr[slot_num], | |
620 | ctx->mem_idx, MO_TEUW); | |
8b453a2b TS |
621 | break; |
622 | case 4: | |
a27c100c | 623 | gen_check_store_width(ctx, slot_num); |
53b26d25 RH |
624 | tcg_gen_qemu_st_tl(hex_store_val32[slot_num], |
625 | hex_store_addr[slot_num], | |
626 | ctx->mem_idx, MO_TEUL); | |
8b453a2b TS |
627 | break; |
628 | case 8: | |
a27c100c | 629 | gen_check_store_width(ctx, slot_num); |
53b26d25 RH |
630 | tcg_gen_qemu_st_i64(hex_store_val64[slot_num], |
631 | hex_store_addr[slot_num], | |
632 | ctx->mem_idx, MO_TEUQ); | |
8b453a2b TS |
633 | break; |
634 | default: | |
635 | { | |
636 | /* | |
637 | * If we get to here, we don't know the width at | |
638 | * TCG generation time, we'll use a helper to | |
639 | * avoid branching based on the width at runtime. | |
640 | */ | |
23803bbe | 641 | TCGv slot = tcg_constant_tl(slot_num); |
8b453a2b | 642 | gen_helper_commit_store(cpu_env, slot); |
8b453a2b TS |
643 | } |
644 | } | |
8b453a2b TS |
645 | } |
646 | if (is_predicated) { | |
647 | gen_set_label(label_end); | |
648 | } | |
649 | } | |
650 | ||
1e536334 | 651 | static void process_store_log(DisasContext *ctx) |
8b453a2b TS |
652 | { |
653 | /* | |
654 | * When a packet has two stores, the hardware processes | |
c23b5764 | 655 | * slot 1 and then slot 0. This will be important when |
8b453a2b TS |
656 | * the memory accesses overlap. |
657 | */ | |
1e536334 | 658 | Packet *pkt = ctx->pkt; |
e2be9a5c TS |
659 | if (pkt->pkt_has_store_s1) { |
660 | g_assert(!pkt->pkt_has_dczeroa); | |
1e536334 | 661 | process_store(ctx, 1); |
8b453a2b | 662 | } |
e2be9a5c TS |
663 | if (pkt->pkt_has_store_s0) { |
664 | g_assert(!pkt->pkt_has_dczeroa); | |
1e536334 | 665 | process_store(ctx, 0); |
8b453a2b TS |
666 | } |
667 | } | |
668 | ||
669 | /* Zero out a 32-bit cache line */ | |
1e536334 | 670 | static void process_dczeroa(DisasContext *ctx) |
8b453a2b | 671 | { |
1e536334 | 672 | if (ctx->pkt->pkt_has_dczeroa) { |
8b453a2b TS |
673 | /* Store 32 bytes of zero starting at (addr & ~0x1f) */ |
674 | TCGv addr = tcg_temp_new(); | |
23803bbe | 675 | TCGv_i64 zero = tcg_constant_i64(0); |
8b453a2b TS |
676 | |
677 | tcg_gen_andi_tl(addr, hex_dczero_addr, ~0x1f); | |
53b26d25 | 678 | tcg_gen_qemu_st_i64(zero, addr, ctx->mem_idx, MO_UQ); |
8b453a2b | 679 | tcg_gen_addi_tl(addr, addr, 8); |
53b26d25 | 680 | tcg_gen_qemu_st_i64(zero, addr, ctx->mem_idx, MO_UQ); |
8b453a2b | 681 | tcg_gen_addi_tl(addr, addr, 8); |
53b26d25 | 682 | tcg_gen_qemu_st_i64(zero, addr, ctx->mem_idx, MO_UQ); |
8b453a2b | 683 | tcg_gen_addi_tl(addr, addr, 8); |
53b26d25 | 684 | tcg_gen_qemu_st_i64(zero, addr, ctx->mem_idx, MO_UQ); |
8b453a2b TS |
685 | } |
686 | } | |
687 | ||
a82dd548 TS |
688 | static bool pkt_has_hvx_store(Packet *pkt) |
689 | { | |
690 | int i; | |
691 | for (i = 0; i < pkt->num_insns; i++) { | |
692 | int opcode = pkt->insn[i].opcode; | |
693 | if (GET_ATTRIB(opcode, A_CVI) && GET_ATTRIB(opcode, A_STORE)) { | |
694 | return true; | |
695 | } | |
696 | } | |
697 | return false; | |
698 | } | |
699 | ||
1e536334 | 700 | static void gen_commit_hvx(DisasContext *ctx) |
a82dd548 TS |
701 | { |
702 | int i; | |
703 | ||
704 | /* | |
705 | * for (i = 0; i < ctx->vreg_log_idx; i++) { | |
706 | * int rnum = ctx->vreg_log[i]; | |
c2b33d0b | 707 | * env->VRegs[rnum] = env->future_VRegs[rnum]; |
a82dd548 TS |
708 | * } |
709 | */ | |
710 | for (i = 0; i < ctx->vreg_log_idx; i++) { | |
711 | int rnum = ctx->vreg_log[i]; | |
a82dd548 TS |
712 | intptr_t dstoff = offsetof(CPUHexagonState, VRegs[rnum]); |
713 | intptr_t srcoff = ctx_future_vreg_off(ctx, rnum, 1, false); | |
714 | size_t size = sizeof(MMVector); | |
715 | ||
c2b33d0b | 716 | tcg_gen_gvec_mov(MO_64, dstoff, srcoff, size, size); |
a82dd548 TS |
717 | } |
718 | ||
719 | /* | |
720 | * for (i = 0; i < ctx->qreg_log_idx; i++) { | |
721 | * int rnum = ctx->qreg_log[i]; | |
c2b33d0b | 722 | * env->QRegs[rnum] = env->future_QRegs[rnum]; |
a82dd548 TS |
723 | * } |
724 | */ | |
725 | for (i = 0; i < ctx->qreg_log_idx; i++) { | |
726 | int rnum = ctx->qreg_log[i]; | |
a82dd548 TS |
727 | intptr_t dstoff = offsetof(CPUHexagonState, QRegs[rnum]); |
728 | intptr_t srcoff = offsetof(CPUHexagonState, future_QRegs[rnum]); | |
729 | size_t size = sizeof(MMQReg); | |
730 | ||
c2b33d0b | 731 | tcg_gen_gvec_mov(MO_64, dstoff, srcoff, size, size); |
a82dd548 TS |
732 | } |
733 | ||
1e536334 | 734 | if (pkt_has_hvx_store(ctx->pkt)) { |
a82dd548 TS |
735 | gen_helper_commit_hvx_stores(cpu_env); |
736 | } | |
737 | } | |
738 | ||
1e536334 | 739 | static void update_exec_counters(DisasContext *ctx) |
8b453a2b | 740 | { |
1e536334 | 741 | Packet *pkt = ctx->pkt; |
8b453a2b TS |
742 | int num_insns = pkt->num_insns; |
743 | int num_real_insns = 0; | |
a82dd548 | 744 | int num_hvx_insns = 0; |
8b453a2b TS |
745 | |
746 | for (int i = 0; i < num_insns; i++) { | |
747 | if (!pkt->insn[i].is_endloop && | |
748 | !pkt->insn[i].part1 && | |
749 | !GET_ATTRIB(pkt->insn[i].opcode, A_IT_NOP)) { | |
750 | num_real_insns++; | |
751 | } | |
a82dd548 TS |
752 | if (GET_ATTRIB(pkt->insn[i].opcode, A_CVI)) { |
753 | num_hvx_insns++; | |
754 | } | |
8b453a2b TS |
755 | } |
756 | ||
757 | ctx->num_packets++; | |
758 | ctx->num_insns += num_real_insns; | |
a82dd548 | 759 | ctx->num_hvx_insns += num_hvx_insns; |
8b453a2b TS |
760 | } |
761 | ||
1e536334 | 762 | static void gen_commit_packet(DisasContext *ctx) |
8b453a2b | 763 | { |
c23b5764 TS |
764 | /* |
765 | * If there is more than one store in a packet, make sure they are all OK | |
766 | * before proceeding with the rest of the packet commit. | |
767 | * | |
768 | * dczeroa has to be the only store operation in the packet, so we go | |
769 | * ahead and process that first. | |
770 | * | |
a82dd548 TS |
771 | * When there is an HVX store, there can also be a scalar store in either |
772 | * slot 0 or slot1, so we create a mask for the helper to indicate what | |
773 | * work to do. | |
774 | * | |
c23b5764 TS |
775 | * When there are two scalar stores, we probe the one in slot 0. |
776 | * | |
777 | * Note that we don't call the probe helper for packets with only one | |
778 | * store. Therefore, we call process_store_log before anything else | |
779 | * involved in committing the packet. | |
780 | */ | |
1e536334 | 781 | Packet *pkt = ctx->pkt; |
c23b5764 TS |
782 | bool has_store_s0 = pkt->pkt_has_store_s0; |
783 | bool has_store_s1 = (pkt->pkt_has_store_s1 && !ctx->s1_store_processed); | |
a82dd548 | 784 | bool has_hvx_store = pkt_has_hvx_store(pkt); |
c23b5764 TS |
785 | if (pkt->pkt_has_dczeroa) { |
786 | /* | |
787 | * The dczeroa will be the store in slot 0, check that we don't have | |
a82dd548 | 788 | * a store in slot 1 or an HVX store. |
c23b5764 | 789 | */ |
e2be9a5c | 790 | g_assert(!has_store_s1 && !has_hvx_store); |
1e536334 | 791 | process_dczeroa(ctx); |
a82dd548 | 792 | } else if (has_hvx_store) { |
a82dd548 | 793 | if (!has_store_s0 && !has_store_s1) { |
2bda44e8 | 794 | TCGv mem_idx = tcg_constant_tl(ctx->mem_idx); |
a82dd548 TS |
795 | gen_helper_probe_hvx_stores(cpu_env, mem_idx); |
796 | } else { | |
797 | int mask = 0; | |
a82dd548 TS |
798 | |
799 | if (has_store_s0) { | |
7b84fd04 TS |
800 | mask = |
801 | FIELD_DP32(mask, PROBE_PKT_SCALAR_HVX_STORES, HAS_ST0, 1); | |
a82dd548 TS |
802 | } |
803 | if (has_store_s1) { | |
7b84fd04 TS |
804 | mask = |
805 | FIELD_DP32(mask, PROBE_PKT_SCALAR_HVX_STORES, HAS_ST1, 1); | |
a82dd548 TS |
806 | } |
807 | if (has_hvx_store) { | |
7b84fd04 TS |
808 | mask = |
809 | FIELD_DP32(mask, PROBE_PKT_SCALAR_HVX_STORES, | |
810 | HAS_HVX_STORES, 1); | |
811 | } | |
812 | if (has_store_s0 && slot_is_predicated(pkt, 0)) { | |
813 | mask = | |
814 | FIELD_DP32(mask, PROBE_PKT_SCALAR_HVX_STORES, | |
815 | S0_IS_PRED, 1); | |
816 | } | |
817 | if (has_store_s1 && slot_is_predicated(pkt, 1)) { | |
818 | mask = | |
819 | FIELD_DP32(mask, PROBE_PKT_SCALAR_HVX_STORES, | |
820 | S1_IS_PRED, 1); | |
a82dd548 | 821 | } |
2bda44e8 TS |
822 | mask = FIELD_DP32(mask, PROBE_PKT_SCALAR_HVX_STORES, MMU_IDX, |
823 | ctx->mem_idx); | |
824 | gen_helper_probe_pkt_scalar_hvx_stores(cpu_env, | |
825 | tcg_constant_tl(mask)); | |
a82dd548 | 826 | } |
c23b5764 TS |
827 | } else if (has_store_s0 && has_store_s1) { |
828 | /* | |
829 | * process_store_log will execute the slot 1 store first, | |
830 | * so we only have to probe the store in slot 0 | |
831 | */ | |
7b84fd04 TS |
832 | int args = 0; |
833 | args = | |
834 | FIELD_DP32(args, PROBE_PKT_SCALAR_STORE_S0, MMU_IDX, ctx->mem_idx); | |
835 | if (slot_is_predicated(pkt, 0)) { | |
836 | args = | |
837 | FIELD_DP32(args, PROBE_PKT_SCALAR_STORE_S0, IS_PREDICATED, 1); | |
838 | } | |
839 | TCGv args_tcgv = tcg_constant_tl(args); | |
840 | gen_helper_probe_pkt_scalar_store_s0(cpu_env, args_tcgv); | |
c23b5764 TS |
841 | } |
842 | ||
1e536334 | 843 | process_store_log(ctx); |
c23b5764 | 844 | |
8b453a2b | 845 | gen_reg_writes(ctx); |
1e536334 | 846 | gen_pred_writes(ctx); |
a82dd548 | 847 | if (pkt->pkt_has_hvx) { |
1e536334 | 848 | gen_commit_hvx(ctx); |
a82dd548 | 849 | } |
1e536334 | 850 | update_exec_counters(ctx); |
85580a65 | 851 | if (HEX_DEBUG) { |
8b453a2b | 852 | TCGv has_st0 = |
23803bbe | 853 | tcg_constant_tl(pkt->pkt_has_store_s0 && !pkt->pkt_has_dczeroa); |
8b453a2b | 854 | TCGv has_st1 = |
23803bbe | 855 | tcg_constant_tl(pkt->pkt_has_store_s1 && !pkt->pkt_has_dczeroa); |
8b453a2b TS |
856 | |
857 | /* Handy place to set a breakpoint at the end of execution */ | |
858 | gen_helper_debug_commit_end(cpu_env, has_st0, has_st1); | |
8b453a2b | 859 | } |
8b453a2b | 860 | |
a82dd548 TS |
861 | if (pkt->vhist_insn != NULL) { |
862 | ctx->pre_commit = false; | |
1e536334 TS |
863 | ctx->insn = pkt->vhist_insn; |
864 | pkt->vhist_insn->generate(ctx); | |
a82dd548 TS |
865 | } |
866 | ||
8b453a2b | 867 | if (pkt->pkt_has_cof) { |
743debbc | 868 | gen_end_tb(ctx); |
8b453a2b TS |
869 | } |
870 | } | |
871 | ||
872 | static void decode_and_translate_packet(CPUHexagonState *env, DisasContext *ctx) | |
873 | { | |
874 | uint32_t words[PACKET_WORDS_MAX]; | |
875 | int nwords; | |
876 | Packet pkt; | |
877 | int i; | |
878 | ||
879 | nwords = read_packet_words(env, ctx, words); | |
880 | if (!nwords) { | |
743debbc | 881 | gen_exception_end_tb(ctx, HEX_EXCP_INVALID_PACKET); |
8b453a2b TS |
882 | return; |
883 | } | |
884 | ||
885 | if (decode_packet(nwords, words, &pkt, false) > 0) { | |
40085901 | 886 | pkt.pc = ctx->base.pc_next; |
8b453a2b | 887 | HEX_DEBUG_PRINT_PKT(&pkt); |
1e536334 TS |
888 | ctx->pkt = &pkt; |
889 | gen_start_packet(ctx); | |
8b453a2b | 890 | for (i = 0; i < pkt.num_insns; i++) { |
1e536334 TS |
891 | ctx->insn = &pkt.insn[i]; |
892 | gen_insn(ctx); | |
8b453a2b | 893 | } |
1e536334 | 894 | gen_commit_packet(ctx); |
8b453a2b TS |
895 | ctx->base.pc_next += pkt.encod_pkt_size_in_bytes; |
896 | } else { | |
743debbc | 897 | gen_exception_end_tb(ctx, HEX_EXCP_INVALID_PACKET); |
8b453a2b TS |
898 | } |
899 | } | |
900 | ||
901 | static void hexagon_tr_init_disas_context(DisasContextBase *dcbase, | |
902 | CPUState *cs) | |
903 | { | |
904 | DisasContext *ctx = container_of(dcbase, DisasContext, base); | |
564b2040 | 905 | uint32_t hex_flags = dcbase->tb->flags; |
8b453a2b TS |
906 | |
907 | ctx->mem_idx = MMU_USER_IDX; | |
908 | ctx->num_packets = 0; | |
909 | ctx->num_insns = 0; | |
a82dd548 | 910 | ctx->num_hvx_insns = 0; |
1b9a7f2a | 911 | ctx->branch_cond = TCG_COND_NEVER; |
564b2040 | 912 | ctx->is_tight_loop = FIELD_EX32(hex_flags, TB_FLAGS, IS_TIGHT_LOOP); |
8b453a2b TS |
913 | } |
914 | ||
915 | static void hexagon_tr_tb_start(DisasContextBase *db, CPUState *cpu) | |
916 | { | |
917 | } | |
918 | ||
919 | static void hexagon_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) | |
920 | { | |
921 | DisasContext *ctx = container_of(dcbase, DisasContext, base); | |
922 | ||
923 | tcg_gen_insn_start(ctx->base.pc_next); | |
924 | } | |
925 | ||
8b453a2b TS |
926 | static bool pkt_crosses_page(CPUHexagonState *env, DisasContext *ctx) |
927 | { | |
928 | target_ulong page_start = ctx->base.pc_first & TARGET_PAGE_MASK; | |
929 | bool found_end = false; | |
930 | int nwords; | |
931 | ||
932 | for (nwords = 0; !found_end && nwords < PACKET_WORDS_MAX; nwords++) { | |
933 | uint32_t word = cpu_ldl_code(env, | |
934 | ctx->base.pc_next + nwords * sizeof(uint32_t)); | |
935 | found_end = is_packet_end(word); | |
936 | } | |
937 | uint32_t next_ptr = ctx->base.pc_next + nwords * sizeof(uint32_t); | |
938 | return found_end && next_ptr - page_start >= TARGET_PAGE_SIZE; | |
939 | } | |
940 | ||
941 | static void hexagon_tr_translate_packet(DisasContextBase *dcbase, CPUState *cpu) | |
942 | { | |
943 | DisasContext *ctx = container_of(dcbase, DisasContext, base); | |
944 | CPUHexagonState *env = cpu->env_ptr; | |
945 | ||
946 | decode_and_translate_packet(env, ctx); | |
947 | ||
948 | if (ctx->base.is_jmp == DISAS_NEXT) { | |
949 | target_ulong page_start = ctx->base.pc_first & TARGET_PAGE_MASK; | |
950 | target_ulong bytes_max = PACKET_WORDS_MAX * sizeof(target_ulong); | |
951 | ||
952 | if (ctx->base.pc_next - page_start >= TARGET_PAGE_SIZE || | |
953 | (ctx->base.pc_next - page_start >= TARGET_PAGE_SIZE - bytes_max && | |
954 | pkt_crosses_page(env, ctx))) { | |
955 | ctx->base.is_jmp = DISAS_TOO_MANY; | |
956 | } | |
957 | ||
958 | /* | |
959 | * The CPU log is used to compare against LLDB single stepping, | |
960 | * so end the TLB after every packet. | |
961 | */ | |
7d9ab202 | 962 | HexagonCPU *hex_cpu = env_archcpu(env); |
8b453a2b TS |
963 | if (hex_cpu->lldb_compat && qemu_loglevel_mask(CPU_LOG_TB_CPU)) { |
964 | ctx->base.is_jmp = DISAS_TOO_MANY; | |
965 | } | |
8b453a2b TS |
966 | } |
967 | } | |
968 | ||
969 | static void hexagon_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) | |
970 | { | |
971 | DisasContext *ctx = container_of(dcbase, DisasContext, base); | |
972 | ||
973 | switch (ctx->base.is_jmp) { | |
974 | case DISAS_TOO_MANY: | |
975 | gen_exec_counters(ctx); | |
976 | tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], ctx->base.pc_next); | |
db07bd02 | 977 | tcg_gen_exit_tb(NULL, 0); |
8b453a2b TS |
978 | break; |
979 | case DISAS_NORETURN: | |
8b453a2b TS |
980 | break; |
981 | default: | |
982 | g_assert_not_reached(); | |
983 | } | |
984 | } | |
985 | ||
8eb806a7 RH |
986 | static void hexagon_tr_disas_log(const DisasContextBase *dcbase, |
987 | CPUState *cpu, FILE *logfile) | |
8b453a2b | 988 | { |
8eb806a7 RH |
989 | fprintf(logfile, "IN: %s\n", lookup_symbol(dcbase->pc_first)); |
990 | target_disas(logfile, cpu, dcbase->pc_first, dcbase->tb->size); | |
8b453a2b TS |
991 | } |
992 | ||
993 | ||
994 | static const TranslatorOps hexagon_tr_ops = { | |
995 | .init_disas_context = hexagon_tr_init_disas_context, | |
996 | .tb_start = hexagon_tr_tb_start, | |
997 | .insn_start = hexagon_tr_insn_start, | |
8b453a2b TS |
998 | .translate_insn = hexagon_tr_translate_packet, |
999 | .tb_stop = hexagon_tr_tb_stop, | |
1000 | .disas_log = hexagon_tr_disas_log, | |
1001 | }; | |
1002 | ||
597f9b2d | 1003 | void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, |
306c8721 | 1004 | target_ulong pc, void *host_pc) |
8b453a2b TS |
1005 | { |
1006 | DisasContext ctx; | |
1007 | ||
306c8721 RH |
1008 | translator_loop(cs, tb, max_insns, pc, host_pc, |
1009 | &hexagon_tr_ops, &ctx.base); | |
8b453a2b TS |
1010 | } |
1011 | ||
1012 | #define NAME_LEN 64 | |
1013 | static char new_value_names[TOTAL_PER_THREAD_REGS][NAME_LEN]; | |
8b453a2b | 1014 | static char reg_written_names[TOTAL_PER_THREAD_REGS][NAME_LEN]; |
8b453a2b TS |
1015 | static char new_pred_value_names[NUM_PREGS][NAME_LEN]; |
1016 | static char store_addr_names[STORES_MAX][NAME_LEN]; | |
1017 | static char store_width_names[STORES_MAX][NAME_LEN]; | |
1018 | static char store_val32_names[STORES_MAX][NAME_LEN]; | |
1019 | static char store_val64_names[STORES_MAX][NAME_LEN]; | |
a82dd548 TS |
1020 | static char vstore_addr_names[VSTORES_MAX][NAME_LEN]; |
1021 | static char vstore_size_names[VSTORES_MAX][NAME_LEN]; | |
1022 | static char vstore_pending_names[VSTORES_MAX][NAME_LEN]; | |
8b453a2b TS |
1023 | |
1024 | void hexagon_translate_init(void) | |
1025 | { | |
1026 | int i; | |
1027 | ||
1028 | opcode_init(); | |
1029 | ||
8b453a2b TS |
1030 | for (i = 0; i < TOTAL_PER_THREAD_REGS; i++) { |
1031 | hex_gpr[i] = tcg_global_mem_new(cpu_env, | |
1032 | offsetof(CPUHexagonState, gpr[i]), | |
1033 | hexagon_regnames[i]); | |
1034 | ||
1035 | snprintf(new_value_names[i], NAME_LEN, "new_%s", hexagon_regnames[i]); | |
1036 | hex_new_value[i] = tcg_global_mem_new(cpu_env, | |
1037 | offsetof(CPUHexagonState, new_value[i]), | |
1038 | new_value_names[i]); | |
1039 | ||
85580a65 TS |
1040 | if (HEX_DEBUG) { |
1041 | snprintf(reg_written_names[i], NAME_LEN, "reg_written_%s", | |
1042 | hexagon_regnames[i]); | |
1043 | hex_reg_written[i] = tcg_global_mem_new(cpu_env, | |
1044 | offsetof(CPUHexagonState, reg_written[i]), | |
1045 | reg_written_names[i]); | |
1046 | } | |
8b453a2b TS |
1047 | } |
1048 | for (i = 0; i < NUM_PREGS; i++) { | |
1049 | hex_pred[i] = tcg_global_mem_new(cpu_env, | |
1050 | offsetof(CPUHexagonState, pred[i]), | |
1051 | hexagon_prednames[i]); | |
1052 | ||
1053 | snprintf(new_pred_value_names[i], NAME_LEN, "new_pred_%s", | |
1054 | hexagon_prednames[i]); | |
1055 | hex_new_pred_value[i] = tcg_global_mem_new(cpu_env, | |
1056 | offsetof(CPUHexagonState, new_pred_value[i]), | |
1057 | new_pred_value_names[i]); | |
1058 | } | |
1059 | hex_pred_written = tcg_global_mem_new(cpu_env, | |
1060 | offsetof(CPUHexagonState, pred_written), "pred_written"); | |
8b453a2b TS |
1061 | hex_this_PC = tcg_global_mem_new(cpu_env, |
1062 | offsetof(CPUHexagonState, this_PC), "this_PC"); | |
1063 | hex_slot_cancelled = tcg_global_mem_new(cpu_env, | |
1064 | offsetof(CPUHexagonState, slot_cancelled), "slot_cancelled"); | |
1065 | hex_branch_taken = tcg_global_mem_new(cpu_env, | |
1066 | offsetof(CPUHexagonState, branch_taken), "branch_taken"); | |
1067 | hex_pkt_has_store_s1 = tcg_global_mem_new(cpu_env, | |
1068 | offsetof(CPUHexagonState, pkt_has_store_s1), "pkt_has_store_s1"); | |
1069 | hex_dczero_addr = tcg_global_mem_new(cpu_env, | |
1070 | offsetof(CPUHexagonState, dczero_addr), "dczero_addr"); | |
1071 | hex_llsc_addr = tcg_global_mem_new(cpu_env, | |
1072 | offsetof(CPUHexagonState, llsc_addr), "llsc_addr"); | |
1073 | hex_llsc_val = tcg_global_mem_new(cpu_env, | |
1074 | offsetof(CPUHexagonState, llsc_val), "llsc_val"); | |
1075 | hex_llsc_val_i64 = tcg_global_mem_new_i64(cpu_env, | |
1076 | offsetof(CPUHexagonState, llsc_val_i64), "llsc_val_i64"); | |
1077 | for (i = 0; i < STORES_MAX; i++) { | |
1078 | snprintf(store_addr_names[i], NAME_LEN, "store_addr_%d", i); | |
1079 | hex_store_addr[i] = tcg_global_mem_new(cpu_env, | |
1080 | offsetof(CPUHexagonState, mem_log_stores[i].va), | |
1081 | store_addr_names[i]); | |
1082 | ||
1083 | snprintf(store_width_names[i], NAME_LEN, "store_width_%d", i); | |
1084 | hex_store_width[i] = tcg_global_mem_new(cpu_env, | |
1085 | offsetof(CPUHexagonState, mem_log_stores[i].width), | |
1086 | store_width_names[i]); | |
1087 | ||
1088 | snprintf(store_val32_names[i], NAME_LEN, "store_val32_%d", i); | |
1089 | hex_store_val32[i] = tcg_global_mem_new(cpu_env, | |
1090 | offsetof(CPUHexagonState, mem_log_stores[i].data32), | |
1091 | store_val32_names[i]); | |
1092 | ||
1093 | snprintf(store_val64_names[i], NAME_LEN, "store_val64_%d", i); | |
1094 | hex_store_val64[i] = tcg_global_mem_new_i64(cpu_env, | |
1095 | offsetof(CPUHexagonState, mem_log_stores[i].data64), | |
1096 | store_val64_names[i]); | |
1097 | } | |
a82dd548 TS |
1098 | for (int i = 0; i < VSTORES_MAX; i++) { |
1099 | snprintf(vstore_addr_names[i], NAME_LEN, "vstore_addr_%d", i); | |
1100 | hex_vstore_addr[i] = tcg_global_mem_new(cpu_env, | |
1101 | offsetof(CPUHexagonState, vstore[i].va), | |
1102 | vstore_addr_names[i]); | |
1103 | ||
1104 | snprintf(vstore_size_names[i], NAME_LEN, "vstore_size_%d", i); | |
1105 | hex_vstore_size[i] = tcg_global_mem_new(cpu_env, | |
1106 | offsetof(CPUHexagonState, vstore[i].size), | |
1107 | vstore_size_names[i]); | |
1108 | ||
1109 | snprintf(vstore_pending_names[i], NAME_LEN, "vstore_pending_%d", i); | |
1110 | hex_vstore_pending[i] = tcg_global_mem_new(cpu_env, | |
1111 | offsetof(CPUHexagonState, vstore_pending[i]), | |
1112 | vstore_pending_names[i]); | |
1113 | } | |
8b453a2b | 1114 | } |