]>
Commit | Line | Data |
---|---|---|
74433bf0 RH |
1 | /* |
2 | * PA-RISC cpu parameters for qemu. | |
3 | * | |
4 | * Copyright (c) 2016 Richard Henderson <rth@twiddle.net> | |
5 | * SPDX-License-Identifier: LGPL-2.0+ | |
6 | */ | |
7 | ||
8 | #ifndef HPPA_CPU_PARAM_H | |
4f31b54b | 9 | #define HPPA_CPU_PARAM_H |
74433bf0 RH |
10 | |
11 | #ifdef TARGET_HPPA64 | |
12 | # define TARGET_LONG_BITS 64 | |
13 | # define TARGET_REGISTER_BITS 64 | |
14 | # define TARGET_VIRT_ADDR_SPACE_BITS 64 | |
15 | # define TARGET_PHYS_ADDR_SPACE_BITS 64 | |
16 | #elif defined(CONFIG_USER_ONLY) | |
17 | # define TARGET_LONG_BITS 32 | |
18 | # define TARGET_REGISTER_BITS 32 | |
19 | # define TARGET_VIRT_ADDR_SPACE_BITS 32 | |
20 | # define TARGET_PHYS_ADDR_SPACE_BITS 32 | |
21 | #else | |
22 | /* | |
23 | * In order to form the GVA from space:offset, | |
24 | * we need a 64-bit virtual address space. | |
25 | */ | |
26 | # define TARGET_LONG_BITS 64 | |
27 | # define TARGET_REGISTER_BITS 32 | |
28 | # define TARGET_VIRT_ADDR_SPACE_BITS 64 | |
29 | # define TARGET_PHYS_ADDR_SPACE_BITS 32 | |
30 | #endif | |
31 | #define TARGET_PAGE_BITS 12 | |
32 | #define NB_MMU_MODES 5 | |
33 | ||
34 | #endif |