]> git.proxmox.com Git - mirror_qemu.git/blame - target/hppa/cpu.c
Merge tag 'mem-2022-10-28' of https://github.com/davidhildenbrand/qemu into staging
[mirror_qemu.git] / target / hppa / cpu.c
CommitLineData
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1/*
2 * QEMU HPPA CPU
3 *
4 * Copyright (c) 2016 Richard Henderson <rth@twiddle.net>
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see
18 * <http://www.gnu.org/licenses/lgpl-2.1.html>
19 */
20
21#include "qemu/osdep.h"
22#include "qapi/error.h"
0442428a 23#include "qemu/qemu-print.h"
b8012ecf 24#include "qemu/timer.h"
61766fe9 25#include "cpu.h"
0b8fa32f 26#include "qemu/module.h"
61766fe9 27#include "exec/exec-all.h"
24f91e81 28#include "fpu/softfloat.h"
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29
30
31static void hppa_cpu_set_pc(CPUState *cs, vaddr value)
32{
33 HPPACPU *cpu = HPPA_CPU(cs);
34
35 cpu->env.iaoq_f = value;
36 cpu->env.iaoq_b = value + 4;
37}
38
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39static vaddr hppa_cpu_get_pc(CPUState *cs)
40{
41 HPPACPU *cpu = HPPA_CPU(cs);
42
43 return cpu->env.iaoq_f;
44}
45
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46static void hppa_cpu_synchronize_from_tb(CPUState *cs,
47 const TranslationBlock *tb)
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48{
49 HPPACPU *cpu = HPPA_CPU(cs);
50
c301f34e 51#ifdef CONFIG_USER_ONLY
fbf59aad 52 cpu->env.iaoq_f = tb_pc(tb);
61766fe9 53 cpu->env.iaoq_b = tb->cs_base;
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54#else
55 /* Recover the IAOQ values from the GVA + PRIV. */
56 uint32_t priv = (tb->flags >> TB_FLAG_PRIV_SHIFT) & 3;
57 target_ulong cs_base = tb->cs_base;
58 target_ulong iasq_f = cs_base & ~0xffffffffull;
59 int32_t diff = cs_base;
60
61 cpu->env.iasq_f = iasq_f;
fbf59aad 62 cpu->env.iaoq_f = (tb_pc(tb) & ~iasq_f) + priv;
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63 if (diff) {
64 cpu->env.iaoq_b = cpu->env.iaoq_f + diff;
65 }
66#endif
67
3d68ee7b 68 cpu->env.psw_n = (tb->flags & PSW_N) != 0;
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69}
70
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71static void hppa_restore_state_to_opc(CPUState *cs,
72 const TranslationBlock *tb,
73 const uint64_t *data)
74{
75 HPPACPU *cpu = HPPA_CPU(cs);
76
77 cpu->env.iaoq_f = data[0];
78 if (data[1] != (target_ureg)-1) {
79 cpu->env.iaoq_b = data[1];
80 }
81 /*
82 * Since we were executing the instruction at IAOQ_F, and took some
83 * sort of action that provoked the cpu_restore_state, we can infer
84 * that the instruction was not nullified.
85 */
86 cpu->env.psw_n = 0;
87}
88
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89static bool hppa_cpu_has_work(CPUState *cs)
90{
4a4554c6 91 return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
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92}
93
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94static void hppa_cpu_disas_set_info(CPUState *cs, disassemble_info *info)
95{
96 info->mach = bfd_mach_hppa20;
97 info->print_insn = print_insn_hppa;
98}
99
8535dd70 100#ifndef CONFIG_USER_ONLY
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101static G_NORETURN
102void hppa_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
103 MMUAccessType access_type, int mmu_idx,
104 uintptr_t retaddr)
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105{
106 HPPACPU *cpu = HPPA_CPU(cs);
107 CPUHPPAState *env = &cpu->env;
108
109 cs->exception_index = EXCP_UNALIGN;
110 if (env->psw & PSW_Q) {
111 /* ??? Needs tweaking for hppa64. */
112 env->cr[CR_IOR] = addr;
113 env->cr[CR_ISR] = addr >> 32;
114 }
115
116 cpu_loop_exit_restore(cs, retaddr);
117}
8535dd70 118#endif /* CONFIG_USER_ONLY */
08aec8b5 119
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120static void hppa_cpu_realizefn(DeviceState *dev, Error **errp)
121{
122 CPUState *cs = CPU(dev);
123 HPPACPUClass *acc = HPPA_CPU_GET_CLASS(dev);
124 Error *local_err = NULL;
125
126 cpu_exec_realizefn(cs, &local_err);
127 if (local_err != NULL) {
128 error_propagate(errp, local_err);
129 return;
130 }
131
132 qemu_init_vcpu(cs);
133 acc->parent_realize(dev, errp);
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134
135#ifndef CONFIG_USER_ONLY
136 {
137 HPPACPU *cpu = HPPA_CPU(cs);
138 cpu->alarm_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
139 hppa_cpu_alarm_timer, cpu);
140 }
141#endif
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142}
143
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144static void hppa_cpu_initfn(Object *obj)
145{
146 CPUState *cs = CPU(obj);
147 HPPACPU *cpu = HPPA_CPU(obj);
148 CPUHPPAState *env = &cpu->env;
149
7506ed90 150 cpu_set_cpustate_pointers(cpu);
1a19da0d 151 cs->exception_index = -1;
61766fe9 152 cpu_hppa_loaded_fr0(env);
1a19da0d 153 cpu_hppa_put_psw(env, PSW_W);
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154}
155
8fc24ad5 156static ObjectClass *hppa_cpu_class_by_name(const char *cpu_model)
61766fe9 157{
8fc24ad5 158 return object_class_by_name(TYPE_HPPA_CPU);
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159}
160
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161#ifndef CONFIG_USER_ONLY
162#include "hw/core/sysemu-cpu-ops.h"
163
164static const struct SysemuCPUOps hppa_sysemu_ops = {
08928c6d 165 .get_phys_page_debug = hppa_cpu_get_phys_page_debug,
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166};
167#endif
168
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169#include "hw/core/tcg-cpu-ops.h"
170
11906557 171static const struct TCGCPUOps hppa_tcg_ops = {
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172 .initialize = hppa_translate_init,
173 .synchronize_from_tb = hppa_cpu_synchronize_from_tb,
e9cc3aca 174 .restore_state_to_opc = hppa_restore_state_to_opc,
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175
176#ifndef CONFIG_USER_ONLY
860e0b96 177 .tlb_fill = hppa_cpu_tlb_fill,
68fa1780 178 .cpu_exec_interrupt = hppa_cpu_exec_interrupt,
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179 .do_interrupt = hppa_cpu_do_interrupt,
180 .do_unaligned_access = hppa_cpu_do_unaligned_access,
181#endif /* !CONFIG_USER_ONLY */
182};
183
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184static void hppa_cpu_class_init(ObjectClass *oc, void *data)
185{
186 DeviceClass *dc = DEVICE_CLASS(oc);
187 CPUClass *cc = CPU_CLASS(oc);
188 HPPACPUClass *acc = HPPA_CPU_CLASS(oc);
189
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190 device_class_set_parent_realize(dc, hppa_cpu_realizefn,
191 &acc->parent_realize);
61766fe9 192
8fc24ad5 193 cc->class_by_name = hppa_cpu_class_by_name;
4f5f2548 194 cc->has_work = hppa_cpu_has_work;
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195 cc->dump_state = hppa_cpu_dump_state;
196 cc->set_pc = hppa_cpu_set_pc;
e4fdf9df 197 cc->get_pc = hppa_cpu_get_pc;
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198 cc->gdb_read_register = hppa_cpu_gdb_read_register;
199 cc->gdb_write_register = hppa_cpu_gdb_write_register;
3c7bef03 200#ifndef CONFIG_USER_ONLY
c643603a 201 dc->vmsd = &vmstate_hppa_cpu;
8b80bd28 202 cc->sysemu_ops = &hppa_sysemu_ops;
813dff13 203#endif
61766fe9 204 cc->disas_set_info = hppa_cpu_disas_set_info;
61766fe9 205 cc->gdb_num_core_regs = 128;
78271684 206 cc->tcg_ops = &hppa_tcg_ops;
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207}
208
209static const TypeInfo hppa_cpu_type_info = {
210 .name = TYPE_HPPA_CPU,
211 .parent = TYPE_CPU,
212 .instance_size = sizeof(HPPACPU),
213 .instance_init = hppa_cpu_initfn,
214 .abstract = false,
215 .class_size = sizeof(HPPACPUClass),
216 .class_init = hppa_cpu_class_init,
217};
218
219static void hppa_cpu_register_types(void)
220{
221 type_register_static(&hppa_cpu_type_info);
222}
223
224type_init(hppa_cpu_register_types)