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61766fe9 RH |
1 | /* |
2 | * QEMU HPPA CPU | |
3 | * | |
4 | * Copyright (c) 2016 Richard Henderson <rth@twiddle.net> | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2.1 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see | |
18 | * <http://www.gnu.org/licenses/lgpl-2.1.html> | |
19 | */ | |
20 | ||
21 | #include "qemu/osdep.h" | |
22 | #include "qapi/error.h" | |
23 | #include "cpu.h" | |
24 | #include "qemu-common.h" | |
61766fe9 RH |
25 | #include "exec/exec-all.h" |
26 | ||
27 | ||
28 | static void hppa_cpu_set_pc(CPUState *cs, vaddr value) | |
29 | { | |
30 | HPPACPU *cpu = HPPA_CPU(cs); | |
31 | ||
32 | cpu->env.iaoq_f = value; | |
33 | cpu->env.iaoq_b = value + 4; | |
34 | } | |
35 | ||
36 | static void hppa_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) | |
37 | { | |
38 | HPPACPU *cpu = HPPA_CPU(cs); | |
39 | ||
40 | cpu->env.iaoq_f = tb->pc; | |
41 | cpu->env.iaoq_b = tb->cs_base; | |
42 | cpu->env.psw_n = tb->flags & 1; | |
43 | } | |
44 | ||
45 | static void hppa_cpu_disas_set_info(CPUState *cs, disassemble_info *info) | |
46 | { | |
47 | info->mach = bfd_mach_hppa20; | |
48 | info->print_insn = print_insn_hppa; | |
49 | } | |
50 | ||
51 | static void hppa_cpu_realizefn(DeviceState *dev, Error **errp) | |
52 | { | |
53 | CPUState *cs = CPU(dev); | |
54 | HPPACPUClass *acc = HPPA_CPU_GET_CLASS(dev); | |
55 | Error *local_err = NULL; | |
56 | ||
57 | cpu_exec_realizefn(cs, &local_err); | |
58 | if (local_err != NULL) { | |
59 | error_propagate(errp, local_err); | |
60 | return; | |
61 | } | |
62 | ||
63 | qemu_init_vcpu(cs); | |
64 | acc->parent_realize(dev, errp); | |
65 | } | |
66 | ||
67 | /* Sort hppabetically by type name. */ | |
68 | static gint hppa_cpu_list_compare(gconstpointer a, gconstpointer b) | |
69 | { | |
70 | ObjectClass *class_a = (ObjectClass *)a; | |
71 | ObjectClass *class_b = (ObjectClass *)b; | |
72 | const char *name_a, *name_b; | |
73 | ||
74 | name_a = object_class_get_name(class_a); | |
75 | name_b = object_class_get_name(class_b); | |
76 | return strcmp(name_a, name_b); | |
77 | } | |
78 | ||
79 | static void hppa_cpu_list_entry(gpointer data, gpointer user_data) | |
80 | { | |
81 | ObjectClass *oc = data; | |
82 | CPUListState *s = user_data; | |
83 | ||
84 | (*s->cpu_fprintf)(s->file, " %s\n", object_class_get_name(oc)); | |
85 | } | |
86 | ||
87 | void hppa_cpu_list(FILE *f, fprintf_function cpu_fprintf) | |
88 | { | |
89 | CPUListState s = { | |
90 | .file = f, | |
91 | .cpu_fprintf = cpu_fprintf, | |
92 | }; | |
93 | GSList *list; | |
94 | ||
95 | list = object_class_get_list(TYPE_HPPA_CPU, false); | |
96 | list = g_slist_sort(list, hppa_cpu_list_compare); | |
97 | (*cpu_fprintf)(f, "Available CPUs:\n"); | |
98 | g_slist_foreach(list, hppa_cpu_list_entry, &s); | |
99 | g_slist_free(list); | |
100 | } | |
101 | ||
102 | static void hppa_cpu_initfn(Object *obj) | |
103 | { | |
104 | CPUState *cs = CPU(obj); | |
105 | HPPACPU *cpu = HPPA_CPU(obj); | |
106 | CPUHPPAState *env = &cpu->env; | |
107 | ||
108 | cs->env_ptr = env; | |
109 | cpu_hppa_loaded_fr0(env); | |
110 | set_snan_bit_is_one(true, &env->fp_status); | |
61766fe9 RH |
111 | } |
112 | ||
8fc24ad5 | 113 | static ObjectClass *hppa_cpu_class_by_name(const char *cpu_model) |
61766fe9 | 114 | { |
8fc24ad5 | 115 | return object_class_by_name(TYPE_HPPA_CPU); |
61766fe9 RH |
116 | } |
117 | ||
118 | static void hppa_cpu_class_init(ObjectClass *oc, void *data) | |
119 | { | |
120 | DeviceClass *dc = DEVICE_CLASS(oc); | |
121 | CPUClass *cc = CPU_CLASS(oc); | |
122 | HPPACPUClass *acc = HPPA_CPU_CLASS(oc); | |
123 | ||
124 | acc->parent_realize = dc->realize; | |
125 | dc->realize = hppa_cpu_realizefn; | |
126 | ||
8fc24ad5 | 127 | cc->class_by_name = hppa_cpu_class_by_name; |
61766fe9 RH |
128 | cc->do_interrupt = hppa_cpu_do_interrupt; |
129 | cc->cpu_exec_interrupt = hppa_cpu_exec_interrupt; | |
130 | cc->dump_state = hppa_cpu_dump_state; | |
131 | cc->set_pc = hppa_cpu_set_pc; | |
132 | cc->synchronize_from_tb = hppa_cpu_synchronize_from_tb; | |
133 | cc->gdb_read_register = hppa_cpu_gdb_read_register; | |
134 | cc->gdb_write_register = hppa_cpu_gdb_write_register; | |
813dff13 | 135 | #ifdef CONFIG_USER_ONLY |
61766fe9 | 136 | cc->handle_mmu_fault = hppa_cpu_handle_mmu_fault; |
813dff13 HD |
137 | #else |
138 | cc->get_phys_page_debug = hppa_cpu_get_phys_page_debug; | |
139 | #endif | |
140 | ||
61766fe9 | 141 | cc->disas_set_info = hppa_cpu_disas_set_info; |
55c3ceef | 142 | cc->tcg_initialize = hppa_translate_init; |
61766fe9 RH |
143 | |
144 | cc->gdb_num_core_regs = 128; | |
145 | } | |
146 | ||
147 | static const TypeInfo hppa_cpu_type_info = { | |
148 | .name = TYPE_HPPA_CPU, | |
149 | .parent = TYPE_CPU, | |
150 | .instance_size = sizeof(HPPACPU), | |
151 | .instance_init = hppa_cpu_initfn, | |
152 | .abstract = false, | |
153 | .class_size = sizeof(HPPACPUClass), | |
154 | .class_init = hppa_cpu_class_init, | |
155 | }; | |
156 | ||
157 | static void hppa_cpu_register_types(void) | |
158 | { | |
159 | type_register_static(&hppa_cpu_type_info); | |
160 | } | |
161 | ||
162 | type_init(hppa_cpu_register_types) |