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61766fe9 RH |
1 | /* |
2 | * QEMU HPPA CPU | |
3 | * | |
4 | * Copyright (c) 2016 Richard Henderson <rth@twiddle.net> | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2.1 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see | |
18 | * <http://www.gnu.org/licenses/lgpl-2.1.html> | |
19 | */ | |
20 | ||
21 | #include "qemu/osdep.h" | |
22 | #include "qapi/error.h" | |
0442428a | 23 | #include "qemu/qemu-print.h" |
b8012ecf | 24 | #include "qemu/timer.h" |
61766fe9 | 25 | #include "cpu.h" |
0b8fa32f | 26 | #include "qemu/module.h" |
61766fe9 | 27 | #include "exec/exec-all.h" |
24f91e81 | 28 | #include "fpu/softfloat.h" |
2554f80f | 29 | #include "tcg/tcg.h" |
61766fe9 RH |
30 | |
31 | static void hppa_cpu_set_pc(CPUState *cs, vaddr value) | |
32 | { | |
33 | HPPACPU *cpu = HPPA_CPU(cs); | |
34 | ||
35 | cpu->env.iaoq_f = value; | |
36 | cpu->env.iaoq_b = value + 4; | |
37 | } | |
38 | ||
e4fdf9df RH |
39 | static vaddr hppa_cpu_get_pc(CPUState *cs) |
40 | { | |
41 | HPPACPU *cpu = HPPA_CPU(cs); | |
42 | ||
43 | return cpu->env.iaoq_f; | |
44 | } | |
45 | ||
04a37d4c RH |
46 | static void hppa_cpu_synchronize_from_tb(CPUState *cs, |
47 | const TranslationBlock *tb) | |
61766fe9 RH |
48 | { |
49 | HPPACPU *cpu = HPPA_CPU(cs); | |
50 | ||
2554f80f AJ |
51 | tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL)); |
52 | ||
c301f34e | 53 | #ifdef CONFIG_USER_ONLY |
2554f80f | 54 | cpu->env.iaoq_f = tb->pc; |
61766fe9 | 55 | cpu->env.iaoq_b = tb->cs_base; |
c301f34e RH |
56 | #else |
57 | /* Recover the IAOQ values from the GVA + PRIV. */ | |
58 | uint32_t priv = (tb->flags >> TB_FLAG_PRIV_SHIFT) & 3; | |
59 | target_ulong cs_base = tb->cs_base; | |
60 | target_ulong iasq_f = cs_base & ~0xffffffffull; | |
61 | int32_t diff = cs_base; | |
62 | ||
63 | cpu->env.iasq_f = iasq_f; | |
2554f80f | 64 | cpu->env.iaoq_f = (tb->pc & ~iasq_f) + priv; |
c301f34e RH |
65 | if (diff) { |
66 | cpu->env.iaoq_b = cpu->env.iaoq_f + diff; | |
67 | } | |
68 | #endif | |
69 | ||
3d68ee7b | 70 | cpu->env.psw_n = (tb->flags & PSW_N) != 0; |
61766fe9 RH |
71 | } |
72 | ||
e9cc3aca RH |
73 | static void hppa_restore_state_to_opc(CPUState *cs, |
74 | const TranslationBlock *tb, | |
75 | const uint64_t *data) | |
76 | { | |
77 | HPPACPU *cpu = HPPA_CPU(cs); | |
78 | ||
79 | cpu->env.iaoq_f = data[0]; | |
c53e401e | 80 | if (data[1] != (target_ulong)-1) { |
e9cc3aca RH |
81 | cpu->env.iaoq_b = data[1]; |
82 | } | |
f5b5c857 | 83 | cpu->env.unwind_breg = data[2]; |
e9cc3aca RH |
84 | /* |
85 | * Since we were executing the instruction at IAOQ_F, and took some | |
86 | * sort of action that provoked the cpu_restore_state, we can infer | |
87 | * that the instruction was not nullified. | |
88 | */ | |
89 | cpu->env.psw_n = 0; | |
90 | } | |
91 | ||
4f5f2548 RH |
92 | static bool hppa_cpu_has_work(CPUState *cs) |
93 | { | |
4a4554c6 | 94 | return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI); |
4f5f2548 RH |
95 | } |
96 | ||
61766fe9 RH |
97 | static void hppa_cpu_disas_set_info(CPUState *cs, disassemble_info *info) |
98 | { | |
99 | info->mach = bfd_mach_hppa20; | |
100 | info->print_insn = print_insn_hppa; | |
101 | } | |
102 | ||
8535dd70 | 103 | #ifndef CONFIG_USER_ONLY |
8905770b MAL |
104 | static G_NORETURN |
105 | void hppa_cpu_do_unaligned_access(CPUState *cs, vaddr addr, | |
106 | MMUAccessType access_type, int mmu_idx, | |
107 | uintptr_t retaddr) | |
08aec8b5 RH |
108 | { |
109 | HPPACPU *cpu = HPPA_CPU(cs); | |
110 | CPUHPPAState *env = &cpu->env; | |
111 | ||
112 | cs->exception_index = EXCP_UNALIGN; | |
910ada02 | 113 | hppa_set_ior_and_isr(env, addr, MMU_IDX_MMU_DISABLED(mmu_idx)); |
08aec8b5 RH |
114 | |
115 | cpu_loop_exit_restore(cs, retaddr); | |
116 | } | |
8535dd70 | 117 | #endif /* CONFIG_USER_ONLY */ |
08aec8b5 | 118 | |
61766fe9 RH |
119 | static void hppa_cpu_realizefn(DeviceState *dev, Error **errp) |
120 | { | |
121 | CPUState *cs = CPU(dev); | |
122 | HPPACPUClass *acc = HPPA_CPU_GET_CLASS(dev); | |
123 | Error *local_err = NULL; | |
124 | ||
125 | cpu_exec_realizefn(cs, &local_err); | |
126 | if (local_err != NULL) { | |
127 | error_propagate(errp, local_err); | |
128 | return; | |
129 | } | |
130 | ||
131 | qemu_init_vcpu(cs); | |
132 | acc->parent_realize(dev, errp); | |
49c29d6c RH |
133 | |
134 | #ifndef CONFIG_USER_ONLY | |
135 | { | |
136 | HPPACPU *cpu = HPPA_CPU(cs); | |
d7553f35 | 137 | |
49c29d6c RH |
138 | cpu->alarm_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, |
139 | hppa_cpu_alarm_timer, cpu); | |
d7553f35 | 140 | hppa_ptlbe(&cpu->env); |
49c29d6c RH |
141 | } |
142 | #endif | |
61766fe9 RH |
143 | } |
144 | ||
61766fe9 RH |
145 | static void hppa_cpu_initfn(Object *obj) |
146 | { | |
147 | CPUState *cs = CPU(obj); | |
148 | HPPACPU *cpu = HPPA_CPU(obj); | |
149 | CPUHPPAState *env = &cpu->env; | |
150 | ||
1a19da0d | 151 | cs->exception_index = -1; |
61766fe9 | 152 | cpu_hppa_loaded_fr0(env); |
1a19da0d | 153 | cpu_hppa_put_psw(env, PSW_W); |
61766fe9 RH |
154 | } |
155 | ||
8fc24ad5 | 156 | static ObjectClass *hppa_cpu_class_by_name(const char *cpu_model) |
61766fe9 | 157 | { |
ca4c2008 RH |
158 | g_autofree char *typename = g_strconcat(cpu_model, "-cpu", NULL); |
159 | ObjectClass *oc = object_class_by_name(typename); | |
160 | ||
161 | if (oc && | |
162 | !object_class_is_abstract(oc) && | |
163 | object_class_dynamic_cast(oc, TYPE_HPPA_CPU)) { | |
164 | return oc; | |
165 | } | |
166 | return NULL; | |
61766fe9 RH |
167 | } |
168 | ||
d3ae32d4 RH |
169 | static void hppa_cpu_list_entry(gpointer data, gpointer user_data) |
170 | { | |
171 | ObjectClass *oc = data; | |
172 | CPUClass *cc = CPU_CLASS(oc); | |
173 | const char *tname = object_class_get_name(oc); | |
174 | g_autofree char *name = g_strndup(tname, strchr(tname, '-') - tname); | |
175 | ||
176 | if (cc->deprecation_note) { | |
177 | qemu_printf(" %s (deprecated)\n", name); | |
178 | } else { | |
179 | qemu_printf(" %s\n", name); | |
180 | } | |
181 | } | |
182 | ||
183 | void hppa_cpu_list(void) | |
184 | { | |
185 | GSList *list; | |
186 | ||
187 | list = object_class_get_list_sorted(TYPE_HPPA_CPU, false); | |
188 | qemu_printf("Available CPUs:\n"); | |
189 | g_slist_foreach(list, hppa_cpu_list_entry, NULL); | |
190 | g_slist_free(list); | |
191 | } | |
192 | ||
8b80bd28 PMD |
193 | #ifndef CONFIG_USER_ONLY |
194 | #include "hw/core/sysemu-cpu-ops.h" | |
195 | ||
196 | static const struct SysemuCPUOps hppa_sysemu_ops = { | |
08928c6d | 197 | .get_phys_page_debug = hppa_cpu_get_phys_page_debug, |
8b80bd28 PMD |
198 | }; |
199 | #endif | |
200 | ||
78271684 CF |
201 | #include "hw/core/tcg-cpu-ops.h" |
202 | ||
11906557 | 203 | static const struct TCGCPUOps hppa_tcg_ops = { |
78271684 CF |
204 | .initialize = hppa_translate_init, |
205 | .synchronize_from_tb = hppa_cpu_synchronize_from_tb, | |
e9cc3aca | 206 | .restore_state_to_opc = hppa_restore_state_to_opc, |
78271684 CF |
207 | |
208 | #ifndef CONFIG_USER_ONLY | |
860e0b96 | 209 | .tlb_fill = hppa_cpu_tlb_fill, |
68fa1780 | 210 | .cpu_exec_interrupt = hppa_cpu_exec_interrupt, |
78271684 CF |
211 | .do_interrupt = hppa_cpu_do_interrupt, |
212 | .do_unaligned_access = hppa_cpu_do_unaligned_access, | |
213 | #endif /* !CONFIG_USER_ONLY */ | |
214 | }; | |
215 | ||
61766fe9 RH |
216 | static void hppa_cpu_class_init(ObjectClass *oc, void *data) |
217 | { | |
218 | DeviceClass *dc = DEVICE_CLASS(oc); | |
219 | CPUClass *cc = CPU_CLASS(oc); | |
220 | HPPACPUClass *acc = HPPA_CPU_CLASS(oc); | |
221 | ||
bf853881 PMD |
222 | device_class_set_parent_realize(dc, hppa_cpu_realizefn, |
223 | &acc->parent_realize); | |
61766fe9 | 224 | |
8fc24ad5 | 225 | cc->class_by_name = hppa_cpu_class_by_name; |
4f5f2548 | 226 | cc->has_work = hppa_cpu_has_work; |
61766fe9 RH |
227 | cc->dump_state = hppa_cpu_dump_state; |
228 | cc->set_pc = hppa_cpu_set_pc; | |
e4fdf9df | 229 | cc->get_pc = hppa_cpu_get_pc; |
61766fe9 RH |
230 | cc->gdb_read_register = hppa_cpu_gdb_read_register; |
231 | cc->gdb_write_register = hppa_cpu_gdb_write_register; | |
3c7bef03 | 232 | #ifndef CONFIG_USER_ONLY |
c643603a | 233 | dc->vmsd = &vmstate_hppa_cpu; |
8b80bd28 | 234 | cc->sysemu_ops = &hppa_sysemu_ops; |
813dff13 | 235 | #endif |
61766fe9 | 236 | cc->disas_set_info = hppa_cpu_disas_set_info; |
61766fe9 | 237 | cc->gdb_num_core_regs = 128; |
78271684 | 238 | cc->tcg_ops = &hppa_tcg_ops; |
61766fe9 RH |
239 | } |
240 | ||
bd6243a3 RH |
241 | static const TypeInfo hppa_cpu_type_infos[] = { |
242 | { | |
243 | .name = TYPE_HPPA_CPU, | |
244 | .parent = TYPE_CPU, | |
245 | .instance_size = sizeof(HPPACPU), | |
246 | .instance_align = __alignof(HPPACPU), | |
247 | .instance_init = hppa_cpu_initfn, | |
248 | .abstract = false, | |
249 | .class_size = sizeof(HPPACPUClass), | |
250 | .class_init = hppa_cpu_class_init, | |
251 | }, | |
bd6243a3 RH |
252 | { |
253 | .name = TYPE_HPPA64_CPU, | |
254 | .parent = TYPE_HPPA_CPU, | |
255 | }, | |
61766fe9 RH |
256 | }; |
257 | ||
bd6243a3 | 258 | DEFINE_TYPES(hppa_cpu_type_infos) |