[mirror_qemu.git] / target / hppa / cpu.h

/*
 * PA-RISC emulation cpu definitions for qemu.
 *
 * Copyright (c) 2016 Richard Henderson <rth@twiddle.net>
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2.1 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#ifndef HPPA_CPU_H
#define HPPA_CPU_H

#include "cpu-qom.h"
#include "exec/cpu-defs.h"
#include "qemu/cpu-float.h"
#include "qemu/interval-tree.h"

/* PA-RISC 1.x processors have a strong memory model.  */
/* ??? While we do not yet implement PA-RISC 2.0, those processors have
   a weak memory model, but with TLB bits that force ordering on a per-page
   basis.  It's probably easier to fall back to a strong memory model.  */
#define TCG_GUEST_DEFAULT_MO        TCG_MO_ALL

#define MMU_KERNEL_IDX    7
#define MMU_KERNEL_P_IDX  8
#define MMU_PL1_IDX       9
#define MMU_PL1_P_IDX     10
#define MMU_PL2_IDX       11
#define MMU_PL2_P_IDX     12
#define MMU_USER_IDX      13
#define MMU_USER_P_IDX    14
#define MMU_PHYS_IDX      15

#define MMU_IDX_TO_PRIV(MIDX)       (((MIDX) - MMU_KERNEL_IDX) / 2)
#define MMU_IDX_TO_P(MIDX)          (((MIDX) - MMU_KERNEL_IDX) & 1)
#define PRIV_P_TO_MMU_IDX(PRIV, P)  ((PRIV) * 2 + !!(P) + MMU_KERNEL_IDX)

#define TARGET_INSN_START_EXTRA_WORDS 1

/* No need to flush MMU_PHYS_IDX  */
#define HPPA_MMU_FLUSH_MASK                             \
        (1 << MMU_KERNEL_IDX | 1 << MMU_KERNEL_P_IDX |  \
         1 << MMU_PL1_IDX    | 1 << MMU_PL1_P_IDX    |  \
         1 << MMU_PL2_IDX    | 1 << MMU_PL2_P_IDX    |  \
         1 << MMU_USER_IDX   | 1 << MMU_USER_P_IDX)

/* Indicies to flush for access_id changes. */
#define HPPA_MMU_FLUSH_P_MASK \
        (1 << MMU_KERNEL_P_IDX | 1 << MMU_PL1_P_IDX  |  \
         1 << MMU_PL2_P_IDX    | 1 << MMU_USER_P_IDX)

/* Hardware exceptions, interrupts, faults, and traps.  */
#define EXCP_HPMC                1  /* high priority machine check */
#define EXCP_POWER_FAIL          2
#define EXCP_RC                  3  /* recovery counter */
#define EXCP_EXT_INTERRUPT       4  /* external interrupt */
#define EXCP_LPMC                5  /* low priority machine check */
#define EXCP_ITLB_MISS           6  /* itlb miss / instruction page fault */
#define EXCP_IMP                 7  /* instruction memory protection trap */
#define EXCP_ILL                 8  /* illegal instruction trap */
#define EXCP_BREAK               9  /* break instruction */
#define EXCP_PRIV_OPR            10 /* privileged operation trap */
#define EXCP_PRIV_REG            11 /* privileged register trap */
#define EXCP_OVERFLOW            12 /* signed overflow trap */
#define EXCP_COND                13 /* trap-on-condition */
#define EXCP_ASSIST              14 /* assist exception trap */
#define EXCP_DTLB_MISS           15 /* dtlb miss / data page fault */
#define EXCP_NA_ITLB_MISS        16 /* non-access itlb miss */
#define EXCP_NA_DTLB_MISS        17 /* non-access dtlb miss */
#define EXCP_DMP                 18 /* data memory protection trap */
#define EXCP_DMB                 19 /* data memory break trap */
#define EXCP_TLB_DIRTY           20 /* tlb dirty bit trap */
#define EXCP_PAGE_REF            21 /* page reference trap */
#define EXCP_ASSIST_EMU          22 /* assist emulation trap */
#define EXCP_HPT                 23 /* high-privilege transfer trap */
#define EXCP_LPT                 24 /* low-privilege transfer trap */
#define EXCP_TB                  25 /* taken branch trap */
#define EXCP_DMAR                26 /* data memory access rights trap */
#define EXCP_DMPI                27 /* data memory protection id trap */
#define EXCP_UNALIGN             28 /* unaligned data reference trap */
#define EXCP_PER_INTERRUPT       29 /* performance monitor interrupt */

/* Exceptions for linux-user emulation.  */
#define EXCP_SYSCALL             30
#define EXCP_SYSCALL_LWS         31

/* Emulated hardware TOC button */
#define EXCP_TOC                 32 /* TOC = Transfer of control (NMI) */

#define CPU_INTERRUPT_NMI       CPU_INTERRUPT_TGT_EXT_3         /* TOC */

/* Taken from Linux kernel: arch/parisc/include/asm/psw.h */
#define PSW_I            0x00000001
#define PSW_D            0x00000002
#define PSW_P            0x00000004
#define PSW_Q            0x00000008
#define PSW_R            0x00000010
#define PSW_F            0x00000020
#define PSW_G            0x00000040 /* PA1.x only */
#define PSW_O            0x00000080 /* PA2.0 only */
#define PSW_CB           0x0000ff00
#define PSW_M            0x00010000
#define PSW_V            0x00020000
#define PSW_C            0x00040000
#define PSW_B            0x00080000
#define PSW_X            0x00100000
#define PSW_N            0x00200000
#define PSW_L            0x00400000
#define PSW_H            0x00800000
#define PSW_T            0x01000000
#define PSW_S            0x02000000
#define PSW_E            0x04000000
#define PSW_W            0x08000000 /* PA2.0 only */
#define PSW_Z            0x40000000 /* PA1.x only */
#define PSW_Y            0x80000000 /* PA1.x only */

#define PSW_SM (PSW_W | PSW_E | PSW_O | PSW_G | PSW_F \
               | PSW_R | PSW_Q | PSW_P | PSW_D | PSW_I)

/* ssm/rsm instructions number PSW_W and PSW_E differently */
#define PSW_SM_I         PSW_I      /* Enable External Interrupts */
#define PSW_SM_D         PSW_D
#define PSW_SM_P         PSW_P
#define PSW_SM_Q         PSW_Q      /* Enable Interrupt State Collection */
#define PSW_SM_R         PSW_R      /* Enable Recover Counter Trap */
#define PSW_SM_E         0x100
#define PSW_SM_W         0x200      /* PA2.0 only : Enable Wide Mode */

#define CR_RC            0
#define CR_PID1          8
#define CR_PID2          9
#define CR_PID3          12
#define CR_PID4          13
#define CR_SCRCCR        10
#define CR_SAR           11
#define CR_IVA           14
#define CR_EIEM          15
#define CR_IT            16
#define CR_IIASQ         17
#define CR_IIAOQ         18
#define CR_IIR           19
#define CR_ISR           20
#define CR_IOR           21
#define CR_IPSW          22
#define CR_EIRR          23

#if TARGET_REGISTER_BITS == 32
typedef uint32_t target_ureg;
typedef int32_t  target_sreg;
#define TREG_FMT_lx   "%08"PRIx32
#define TREG_FMT_ld   "%"PRId32
#else
typedef uint64_t target_ureg;
typedef int64_t  target_sreg;
#define TREG_FMT_lx   "%016"PRIx64
#define TREG_FMT_ld   "%"PRId64
#endif

typedef struct HPPATLBEntry {
    union {
        IntervalTreeNode itree;
        struct HPPATLBEntry *unused_next;
    };

    target_ureg pa;

    unsigned entry_valid : 1;

    unsigned u : 1;
    unsigned t : 1;
    unsigned d : 1;
    unsigned b : 1;
    unsigned ar_type : 3;
    unsigned ar_pl1 : 2;
    unsigned ar_pl2 : 2;
    unsigned access_id : 16;
} HPPATLBEntry;

typedef struct CPUArchState {
    target_ureg iaoq_f;      /* front */
    target_ureg iaoq_b;      /* back, aka next instruction */

    target_ureg gr[32];
    uint64_t fr[32];
    uint64_t sr[8];          /* stored shifted into place for gva */

    target_ureg psw;         /* All psw bits except the following:  */
    target_ureg psw_n;       /* boolean */
    target_sreg psw_v;       /* in most significant bit */

    /* Splitting the carry-borrow field into the MSB and "the rest", allows
     * for "the rest" to be deleted when it is unused, but the MSB is in use.
     * In addition, it's easier to compute carry-in for bit B+1 than it is to
     * compute carry-out for bit B (3 vs 4 insns for addition, assuming the
     * host has the appropriate add-with-carry insn to compute the msb).
     * Therefore the carry bits are stored as: cb_msb : cb & 0x11111110.
     */
    target_ureg psw_cb;      /* in least significant bit of next nibble */
    target_ureg psw_cb_msb;  /* boolean */

    uint64_t iasq_f;
    uint64_t iasq_b;

    uint32_t fr0_shadow;     /* flags, c, ca/cq, rm, d, enables */
    float_status fp_status;

    target_ureg cr[32];      /* control registers */
    target_ureg cr_back[2];  /* back of cr17/cr18 */
    target_ureg shadow[7];   /* shadow registers */

    /*
     * ??? The number of entries isn't specified by the architecture.
     * BTLBs are not supported in 64-bit machines.
     */
#define PA10_BTLB_FIXED         16
#define PA10_BTLB_VARIABLE      0
#define HPPA_TLB_ENTRIES        256

    /* Index for round-robin tlb eviction. */
    uint32_t tlb_last;

    /*
     * For pa1.x, the partial initialized, still invalid tlb entry
     * which has had ITLBA performed, but not yet ITLBP.
     */
    HPPATLBEntry *tlb_partial;

    /* Linked list of all invalid (unused) tlb entries. */
    HPPATLBEntry *tlb_unused;

    /* Root of the search tree for all valid tlb entries. */
    IntervalTreeRoot tlb_root;

    HPPATLBEntry tlb[HPPA_TLB_ENTRIES];
} CPUHPPAState;

/**
 * HPPACPU:
 * @env: #CPUHPPAState
 *
 * An HPPA CPU.
 */
struct ArchCPU {
    /*< private >*/
    CPUState parent_obj;
    /*< public >*/

    CPUHPPAState env;
    QEMUTimer *alarm_timer;
};

#include "exec/cpu-all.h"

static inline bool hppa_is_pa20(CPUHPPAState *env)
{
    return object_dynamic_cast(OBJECT(env_cpu(env)), TYPE_HPPA64_CPU) != NULL;
}

static inline int HPPA_BTLB_ENTRIES(CPUHPPAState *env)
{
    return hppa_is_pa20(env) ? 0 : PA10_BTLB_FIXED + PA10_BTLB_VARIABLE;
}

static inline int cpu_mmu_index(CPUHPPAState *env, bool ifetch)
{
#ifdef CONFIG_USER_ONLY
    return MMU_USER_IDX;
#else
    if (env->psw & (ifetch ? PSW_C : PSW_D)) {
        return PRIV_P_TO_MMU_IDX(env->iaoq_f & 3, env->psw & PSW_P);
    }
    return MMU_PHYS_IDX;  /* mmu disabled */
#endif
}

void hppa_translate_init(void);

#define CPU_RESOLVING_TYPE TYPE_HPPA_CPU

static inline target_ulong hppa_form_gva_psw(target_ureg psw, uint64_t spc,
                                             target_ureg off)
{
#ifdef CONFIG_USER_ONLY
    return off;
#else
    off &= psw & PSW_W ? MAKE_64BIT_MASK(0, 62) : MAKE_64BIT_MASK(0, 32);
    return spc | off;
#endif
}

static inline target_ulong hppa_form_gva(CPUHPPAState *env, uint64_t spc,
                                         target_ureg off)
{
    return hppa_form_gva_psw(env->psw, spc, off);
}

hwaddr hppa_abs_to_phys_pa2_w0(vaddr addr);
hwaddr hppa_abs_to_phys_pa2_w1(vaddr addr);

/*
 * Since PSW_{I,CB} will never need to be in tb->flags, reuse them.
 * TB_FLAG_SR_SAME indicates that SR4 through SR7 all contain the
 * same value.
 */
#define TB_FLAG_SR_SAME     PSW_I
#define TB_FLAG_PRIV_SHIFT  8
#define TB_FLAG_UNALIGN     0x400

static inline void cpu_get_tb_cpu_state(CPUHPPAState *env, vaddr *pc,
                                        uint64_t *cs_base, uint32_t *pflags)
{
    uint32_t flags = env->psw_n * PSW_N;

    /* TB lookup assumes that PC contains the complete virtual address.
       If we leave space+offset separate, we'll get ITLB misses to an
       incomplete virtual address.  This also means that we must separate
       out current cpu privilege from the low bits of IAOQ_F.  */
#ifdef CONFIG_USER_ONLY
    *pc = env->iaoq_f & -4;
    *cs_base = env->iaoq_b & -4;
    flags |= TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus;
#else
    /* ??? E, T, H, L, B bits need to be here, when implemented.  */
    flags |= env->psw & (PSW_W | PSW_C | PSW_D | PSW_P);
    flags |= (env->iaoq_f & 3) << TB_FLAG_PRIV_SHIFT;

    *pc = hppa_form_gva_psw(env->psw, (env->psw & PSW_C ? env->iasq_f : 0),
                            env->iaoq_f & -4);
    *cs_base = env->iasq_f;

    /* Insert a difference between IAOQ_B and IAOQ_F within the otherwise zero
       low 32-bits of CS_BASE.  This will succeed for all direct branches,
       which is the primary case we care about -- using goto_tb within a page.
       Failure is indicated by a zero difference.  */
    if (env->iasq_f == env->iasq_b) {
        target_sreg diff = env->iaoq_b - env->iaoq_f;
        if (TARGET_REGISTER_BITS == 32 || diff == (int32_t)diff) {
            *cs_base |= (uint32_t)diff;
        }
    }
    if ((env->sr[4] == env->sr[5])
        & (env->sr[4] == env->sr[6])
        & (env->sr[4] == env->sr[7])) {
        flags |= TB_FLAG_SR_SAME;
    }
#endif

    *pflags = flags;
}

target_ureg cpu_hppa_get_psw(CPUHPPAState *env);
void cpu_hppa_put_psw(CPUHPPAState *env, target_ureg);
void cpu_hppa_loaded_fr0(CPUHPPAState *env);

#ifdef CONFIG_USER_ONLY
static inline void cpu_hppa_change_prot_id(CPUHPPAState *env) { }
#else
void cpu_hppa_change_prot_id(CPUHPPAState *env);
#endif

int hppa_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
int hppa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
void hppa_cpu_dump_state(CPUState *cs, FILE *f, int);
#ifndef CONFIG_USER_ONLY
void hppa_ptlbe(CPUHPPAState *env);
hwaddr hppa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr);
bool hppa_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
                       MMUAccessType access_type, int mmu_idx,
                       bool probe, uintptr_t retaddr);
void hppa_cpu_do_interrupt(CPUState *cpu);
bool hppa_cpu_exec_interrupt(CPUState *cpu, int int_req);
int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx,
                              int type, hwaddr *pphys, int *pprot,
                              HPPATLBEntry **tlb_entry);
extern const MemoryRegionOps hppa_io_eir_ops;
extern const VMStateDescription vmstate_hppa_cpu;
void hppa_cpu_alarm_timer(void *);
int hppa_artype_for_page(CPUHPPAState *env, target_ulong vaddr);
#endif
G_NORETURN void hppa_dynamic_excp(CPUHPPAState *env, int excp, uintptr_t ra);

#define CPU_RESOLVING_TYPE TYPE_HPPA_CPU

#define cpu_list hppa_cpu_list
void hppa_cpu_list(void);

#endif /* HPPA_CPU_H */
Commit	Line	Data
61766fe9 RH	1	/*
	2	* PA-RISC emulation cpu definitions for qemu.
	3	*
	4	* Copyright (c) 2016 Richard Henderson <rth@twiddle.net>
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
d6ea4236	9	* version 2.1 of the License, or (at your option) any later version.
61766fe9 RH	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
	18	*/
	19
	20	#ifndef HPPA_CPU_H
	21	#define HPPA_CPU_H
	22
61766fe9	23	#include "cpu-qom.h"
74433bf0	24	#include "exec/cpu-defs.h"
69242e7e	25	#include "qemu/cpu-float.h"
66866cc7	26	#include "qemu/interval-tree.h"
61766fe9	27
7b93dab5 RH	28	/* PA-RISC 1.x processors have a strong memory model. */
	29	/* ??? While we do not yet implement PA-RISC 2.0, those processors have
	30	a weak memory model, but with TLB bits that force ordering on a per-page
	31	basis. It's probably easier to fall back to a strong memory model. */
	32	#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL
	33
bb67ec32 RH	34	#define MMU_KERNEL_IDX 7
	35	#define MMU_KERNEL_P_IDX 8
	36	#define MMU_PL1_IDX 9
	37	#define MMU_PL1_P_IDX 10
	38	#define MMU_PL2_IDX 11
	39	#define MMU_PL2_P_IDX 12
	40	#define MMU_USER_IDX 13
	41	#define MMU_USER_P_IDX 14
	42	#define MMU_PHYS_IDX 15
	43
	44	#define MMU_IDX_TO_PRIV(MIDX) (((MIDX) - MMU_KERNEL_IDX) / 2)
	45	#define MMU_IDX_TO_P(MIDX) (((MIDX) - MMU_KERNEL_IDX) & 1)
	46	#define PRIV_P_TO_MMU_IDX(PRIV, P) ((PRIV) * 2 + !!(P) + MMU_KERNEL_IDX)
c01e5dfb	47
61766fe9 RH	48	#define TARGET_INSN_START_EXTRA_WORDS 1
61766fe9 RH	49
88b7ad10 HD	50	/* No need to flush MMU_PHYS_IDX */
88b7ad10 HD	51	#define HPPA_MMU_FLUSH_MASK \
bb67ec32 RH	52	(1 << MMU_KERNEL_IDX \| 1 << MMU_KERNEL_P_IDX \| \
	53	1 << MMU_PL1_IDX \| 1 << MMU_PL1_P_IDX \| \
	54	1 << MMU_PL2_IDX \| 1 << MMU_PL2_P_IDX \| \
	55	1 << MMU_USER_IDX \| 1 << MMU_USER_P_IDX)
	56
	57	/* Indicies to flush for access_id changes. */
	58	#define HPPA_MMU_FLUSH_P_MASK \
	59	(1 << MMU_KERNEL_P_IDX \| 1 << MMU_PL1_P_IDX \| \
	60	1 << MMU_PL2_P_IDX \| 1 << MMU_USER_P_IDX)
88b7ad10	61
8b81968c	62	/* Hardware exceptions, interrupts, faults, and traps. */
2986721d RH	63	#define EXCP_HPMC 1 /* high priority machine check */
	64	#define EXCP_POWER_FAIL 2
	65	#define EXCP_RC 3 /* recovery counter */
	66	#define EXCP_EXT_INTERRUPT 4 /* external interrupt */
	67	#define EXCP_LPMC 5 /* low priority machine check */
	68	#define EXCP_ITLB_MISS 6 /* itlb miss / instruction page fault */
	69	#define EXCP_IMP 7 /* instruction memory protection trap */
	70	#define EXCP_ILL 8 /* illegal instruction trap */
	71	#define EXCP_BREAK 9 /* break instruction */
	72	#define EXCP_PRIV_OPR 10 /* privileged operation trap */
	73	#define EXCP_PRIV_REG 11 /* privileged register trap */
	74	#define EXCP_OVERFLOW 12 /* signed overflow trap */
	75	#define EXCP_COND 13 /* trap-on-condition */
	76	#define EXCP_ASSIST 14 /* assist exception trap */
	77	#define EXCP_DTLB_MISS 15 /* dtlb miss / data page fault */
	78	#define EXCP_NA_ITLB_MISS 16 /* non-access itlb miss */
	79	#define EXCP_NA_DTLB_MISS 17 /* non-access dtlb miss */
	80	#define EXCP_DMP 18 /* data memory protection trap */
	81	#define EXCP_DMB 19 /* data memory break trap */
	82	#define EXCP_TLB_DIRTY 20 /* tlb dirty bit trap */
	83	#define EXCP_PAGE_REF 21 /* page reference trap */
	84	#define EXCP_ASSIST_EMU 22 /* assist emulation trap */
	85	#define EXCP_HPT 23 /* high-privilege transfer trap */
	86	#define EXCP_LPT 24 /* low-privilege transfer trap */
	87	#define EXCP_TB 25 /* taken branch trap */
	88	#define EXCP_DMAR 26 /* data memory access rights trap */
	89	#define EXCP_DMPI 27 /* data memory protection id trap */
	90	#define EXCP_UNALIGN 28 /* unaligned data reference trap */
	91	#define EXCP_PER_INTERRUPT 29 /* performance monitor interrupt */
	92
	93	/* Exceptions for linux-user emulation. */
	94	#define EXCP_SYSCALL 30
	95	#define EXCP_SYSCALL_LWS 31
61766fe9	96
4a4554c6 HD	97	/* Emulated hardware TOC button */
	98	#define EXCP_TOC 32 /* TOC = Transfer of control (NMI) */
	99
	100	#define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3 /* TOC */
	101
fa57e327 RH	102	/* Taken from Linux kernel: arch/parisc/include/asm/psw.h */
	103	#define PSW_I 0x00000001
	104	#define PSW_D 0x00000002
	105	#define PSW_P 0x00000004
	106	#define PSW_Q 0x00000008
	107	#define PSW_R 0x00000010
	108	#define PSW_F 0x00000020
	109	#define PSW_G 0x00000040 /* PA1.x only */
	110	#define PSW_O 0x00000080 /* PA2.0 only */
	111	#define PSW_CB 0x0000ff00
	112	#define PSW_M 0x00010000
	113	#define PSW_V 0x00020000
	114	#define PSW_C 0x00040000
	115	#define PSW_B 0x00080000
	116	#define PSW_X 0x00100000
	117	#define PSW_N 0x00200000
	118	#define PSW_L 0x00400000
	119	#define PSW_H 0x00800000
	120	#define PSW_T 0x01000000
	121	#define PSW_S 0x02000000
	122	#define PSW_E 0x04000000
fa57e327	123	#define PSW_W 0x08000000 /* PA2.0 only */
fa57e327 RH	124	#define PSW_Z 0x40000000 /* PA1.x only */
	125	#define PSW_Y 0x80000000 /* PA1.x only */
	126
	127	#define PSW_SM (PSW_W \| PSW_E \| PSW_O \| PSW_G \| PSW_F \
	128	\| PSW_R \| PSW_Q \| PSW_P \| PSW_D \| PSW_I)
	129
	130	/* ssm/rsm instructions number PSW_W and PSW_E differently */
	131	#define PSW_SM_I PSW_I /* Enable External Interrupts */
	132	#define PSW_SM_D PSW_D
	133	#define PSW_SM_P PSW_P
	134	#define PSW_SM_Q PSW_Q /* Enable Interrupt State Collection */
	135	#define PSW_SM_R PSW_R /* Enable Recover Counter Trap */
fa57e327 RH	136	#define PSW_SM_E 0x100
fa57e327 RH	137	#define PSW_SM_W 0x200 /* PA2.0 only : Enable Wide Mode */
fa57e327	138
35136a77	139	#define CR_RC 0
d5de20bd SS	140	#define CR_PID1 8
	141	#define CR_PID2 9
	142	#define CR_PID3 12
	143	#define CR_PID4 13
35136a77 RH	144	#define CR_SCRCCR 10
	145	#define CR_SAR 11
	146	#define CR_IVA 14
	147	#define CR_EIEM 15
	148	#define CR_IT 16
	149	#define CR_IIASQ 17
	150	#define CR_IIAOQ 18
	151	#define CR_IIR 19
	152	#define CR_ISR 20
	153	#define CR_IOR 21
	154	#define CR_IPSW 22
	155	#define CR_EIRR 23
	156
eaa3783b RH	157	#if TARGET_REGISTER_BITS == 32
	158	typedef uint32_t target_ureg;
	159	typedef int32_t target_sreg;
	160	#define TREG_FMT_lx "%08"PRIx32
	161	#define TREG_FMT_ld "%"PRId32
	162	#else
	163	typedef uint64_t target_ureg;
	164	typedef int64_t target_sreg;
	165	#define TREG_FMT_lx "%016"PRIx64
	166	#define TREG_FMT_ld "%"PRId64
	167	#endif
	168
729cd350	169	typedef struct HPPATLBEntry {
d7553f35 RH	170	union {
	171	IntervalTreeNode itree;
	172	struct HPPATLBEntry *unused_next;
	173	};
66866cc7	174
650cdb2a	175	target_ureg pa;
f8cda28b RH	176
	177	unsigned entry_valid : 1;
	178
650cdb2a RH	179	unsigned u : 1;
	180	unsigned t : 1;
	181	unsigned d : 1;
	182	unsigned b : 1;
650cdb2a RH	183	unsigned ar_type : 3;
	184	unsigned ar_pl1 : 2;
	185	unsigned ar_pl2 : 2;
650cdb2a	186	unsigned access_id : 16;
729cd350	187	} HPPATLBEntry;
650cdb2a	188
1ea4a06a	189	typedef struct CPUArchState {
f8c0fd98 HD	190	target_ureg iaoq_f; /* front */
	191	target_ureg iaoq_b; /* back, aka next instruction */
	192
eaa3783b	193	target_ureg gr[32];
61766fe9	194	uint64_t fr[32];
33423472	195	uint64_t sr[8]; /* stored shifted into place for gva */
61766fe9	196
eaa3783b RH	197	target_ureg psw; /* All psw bits except the following: */
	198	target_ureg psw_n; /* boolean */
	199	target_sreg psw_v; /* in most significant bit */
61766fe9 RH	200
	201	/* Splitting the carry-borrow field into the MSB and "the rest", allows
	202	* for "the rest" to be deleted when it is unused, but the MSB is in use.
	203	* In addition, it's easier to compute carry-in for bit B+1 than it is to
	204	* compute carry-out for bit B (3 vs 4 insns for addition, assuming the
	205	* host has the appropriate add-with-carry insn to compute the msb).
	206	* Therefore the carry bits are stored as: cb_msb : cb & 0x11111110.
	207	*/
eaa3783b RH	208	target_ureg psw_cb; /* in least significant bit of next nibble */
eaa3783b RH	209	target_ureg psw_cb_msb; /* boolean */
61766fe9	210
c301f34e RH	211	uint64_t iasq_f;
c301f34e RH	212	uint64_t iasq_b;
61766fe9	213
61766fe9 RH	214	uint32_t fr0_shadow; /* flags, c, ca/cq, rm, d, enables */
	215	float_status fp_status;
	216
35136a77 RH	217	target_ureg cr[32]; /* control registers */
35136a77 RH	218	target_ureg cr_back[2]; /* back of cr17/cr18 */
f49b3537	219	target_ureg shadow[7]; /* shadow registers */
35136a77	220
9cf2112b RH	221	/*
	222	* ??? The number of entries isn't specified by the architecture.
	223	* BTLBs are not supported in 64-bit machines.
	224	*/
	225	#define PA10_BTLB_FIXED 16
	226	#define PA10_BTLB_VARIABLE 0
df5c6a50	227	#define HPPA_TLB_ENTRIES 256
df5c6a50	228
d7553f35	229	/* Index for round-robin tlb eviction. */
650cdb2a	230	uint32_t tlb_last;
d7553f35 RH	231
	232	/*
	233	* For pa1.x, the partial initialized, still invalid tlb entry
	234	* which has had ITLBA performed, but not yet ITLBP.
	235	*/
	236	HPPATLBEntry *tlb_partial;
	237
	238	/* Linked list of all invalid (unused) tlb entries. */
	239	HPPATLBEntry *tlb_unused;
	240
	241	/* Root of the search tree for all valid tlb entries. */
	242	IntervalTreeRoot tlb_root;
	243
	244	HPPATLBEntry tlb[HPPA_TLB_ENTRIES];
1ea4a06a	245	} CPUHPPAState;
61766fe9 RH	246
	247	/**
	248	* HPPACPU:
	249	* @env: #CPUHPPAState
	250	*
	251	* An HPPA CPU.
	252	*/
b36e239e	253	struct ArchCPU {
61766fe9 RH	254	/< private >/
	255	CPUState parent_obj;
	256	/< public >/
	257
	258	CPUHPPAState env;
49c29d6c	259	QEMUTimer *alarm_timer;
61766fe9 RH	260	};
61766fe9 RH	261
61766fe9 RH	262	#include "exec/cpu-all.h"
61766fe9 RH	263
bd6243a3 RH	264	static inline bool hppa_is_pa20(CPUHPPAState *env)
	265	{
	266	return object_dynamic_cast(OBJECT(env_cpu(env)), TYPE_HPPA64_CPU) != NULL;
	267	}
	268
9cf2112b RH	269	static inline int HPPA_BTLB_ENTRIES(CPUHPPAState *env)
	270	{
	271	return hppa_is_pa20(env) ? 0 : PA10_BTLB_FIXED + PA10_BTLB_VARIABLE;
	272	}
	273
61766fe9 RH	274	static inline int cpu_mmu_index(CPUHPPAState *env, bool ifetch)
61766fe9 RH	275	{
3d68ee7b RH	276	#ifdef CONFIG_USER_ONLY
	277	return MMU_USER_IDX;
	278	#else
	279	if (env->psw & (ifetch ? PSW_C : PSW_D)) {
bb67ec32	280	return PRIV_P_TO_MMU_IDX(env->iaoq_f & 3, env->psw & PSW_P);
3d68ee7b RH	281	}
	282	return MMU_PHYS_IDX; /* mmu disabled */
	283	#endif
61766fe9 RH	284	}
	285
	286	void hppa_translate_init(void);
	287
0dacec87	288	#define CPU_RESOLVING_TYPE TYPE_HPPA_CPU
61766fe9	289
c301f34e RH	290	static inline target_ulong hppa_form_gva_psw(target_ureg psw, uint64_t spc,
	291	target_ureg off)
	292	{
	293	#ifdef CONFIG_USER_ONLY
	294	return off;
	295	#else
698240d1	296	off &= psw & PSW_W ? MAKE_64BIT_MASK(0, 62) : MAKE_64BIT_MASK(0, 32);
c301f34e RH	297	return spc \| off;
	298	#endif
	299	}
	300
	301	static inline target_ulong hppa_form_gva(CPUHPPAState *env, uint64_t spc,
	302	target_ureg off)
	303	{
	304	return hppa_form_gva_psw(env->psw, spc, off);
	305	}
	306
ccdf741c RH	307	hwaddr hppa_abs_to_phys_pa2_w0(vaddr addr);
	308	hwaddr hppa_abs_to_phys_pa2_w1(vaddr addr);
	309
217d1a5e RH	310	/*
217d1a5e RH	311	* Since PSW_{I,CB} will never need to be in tb->flags, reuse them.
494737b7 RH	312	* TB_FLAG_SR_SAME indicates that SR4 through SR7 all contain the
	313	* same value.
	314	*/
	315	#define TB_FLAG_SR_SAME PSW_I
c301f34e	316	#define TB_FLAG_PRIV_SHIFT 8
217d1a5e	317	#define TB_FLAG_UNALIGN 0x400
c301f34e	318
bb5de525 AJ	319	static inline void cpu_get_tb_cpu_state(CPUHPPAState env, vaddr pc,
bb5de525 AJ	320	uint64_t cs_base, uint32_t pflags)
61766fe9	321	{
c301f34e RH	322	uint32_t flags = env->psw_n * PSW_N;
	323
	324	/* TB lookup assumes that PC contains the complete virtual address.
	325	If we leave space+offset separate, we'll get ITLB misses to an
	326	incomplete virtual address. This also means that we must separate
8b81968c	327	out current cpu privilege from the low bits of IAOQ_F. */
c301f34e	328	#ifdef CONFIG_USER_ONLY
ebd0e151 RH	329	*pc = env->iaoq_f & -4;
ebd0e151 RH	330	*cs_base = env->iaoq_b & -4;
217d1a5e	331	flags \|= TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus;
c301f34e	332	#else
bb67ec32 RH	333	/* ??? E, T, H, L, B bits need to be here, when implemented. */
bb67ec32 RH	334	flags \|= env->psw & (PSW_W \| PSW_C \| PSW_D \| PSW_P);
c301f34e RH	335	flags \|= (env->iaoq_f & 3) << TB_FLAG_PRIV_SHIFT;
c301f34e RH	336
698240d1 RH	337	*pc = hppa_form_gva_psw(env->psw, (env->psw & PSW_C ? env->iasq_f : 0),
698240d1 RH	338	env->iaoq_f & -4);
c301f34e RH	339	*cs_base = env->iasq_f;
	340
	341	/* Insert a difference between IAOQ_B and IAOQ_F within the otherwise zero
	342	low 32-bits of CS_BASE. This will succeed for all direct branches,
	343	which is the primary case we care about -- using goto_tb within a page.
	344	Failure is indicated by a zero difference. */
	345	if (env->iasq_f == env->iasq_b) {
	346	target_sreg diff = env->iaoq_b - env->iaoq_f;
	347	if (TARGET_REGISTER_BITS == 32 \|\| diff == (int32_t)diff) {
	348	*cs_base \|= (uint32_t)diff;
	349	}
	350	}
494737b7 RH	351	if ((env->sr[4] == env->sr[5])
	352	& (env->sr[4] == env->sr[6])
	353	& (env->sr[4] == env->sr[7])) {
	354	flags \|= TB_FLAG_SR_SAME;
	355	}
c301f34e RH	356	#endif
	357
	358	*pflags = flags;
61766fe9 RH	359	}
61766fe9 RH	360
eaa3783b RH	361	target_ureg cpu_hppa_get_psw(CPUHPPAState *env);
eaa3783b RH	362	void cpu_hppa_put_psw(CPUHPPAState *env, target_ureg);
61766fe9 RH	363	void cpu_hppa_loaded_fr0(CPUHPPAState *env);
61766fe9 RH	364
d5de20bd SS	365	#ifdef CONFIG_USER_ONLY
	366	static inline void cpu_hppa_change_prot_id(CPUHPPAState *env) { }
	367	#else
	368	void cpu_hppa_change_prot_id(CPUHPPAState *env);
	369	#endif
	370
a010bdbe	371	int hppa_cpu_gdb_read_register(CPUState cpu, GByteArray buf, int reg);
61766fe9	372	int hppa_cpu_gdb_write_register(CPUState cpu, uint8_t buf, int reg);
90c84c56	373	void hppa_cpu_dump_state(CPUState cs, FILE f, int);
860e0b96	374	#ifndef CONFIG_USER_ONLY
d7553f35	375	void hppa_ptlbe(CPUHPPAState *env);
6d2d454a	376	hwaddr hppa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr);
3c7bef03 RH	377	bool hppa_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
	378	MMUAccessType access_type, int mmu_idx,
	379	bool probe, uintptr_t retaddr);
68fa1780 PMD	380	void hppa_cpu_do_interrupt(CPUState *cpu);
68fa1780 PMD	381	bool hppa_cpu_exec_interrupt(CPUState *cpu, int int_req);
650cdb2a	382	int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx,
fa824d99	383	int type, hwaddr pphys, int pprot,
729cd350	384	HPPATLBEntry **tlb_entry);
4f5f2548	385	extern const MemoryRegionOps hppa_io_eir_ops;
8a9358cc	386	extern const VMStateDescription vmstate_hppa_cpu;
49c29d6c	387	void hppa_cpu_alarm_timer(void *);
43e05652	388	int hppa_artype_for_page(CPUHPPAState *env, target_ulong vaddr);
650cdb2a	389	#endif
8905770b	390	G_NORETURN void hppa_dynamic_excp(CPUHPPAState *env, int excp, uintptr_t ra);
61766fe9	391
d3ae32d4 RH	392	#define CPU_RESOLVING_TYPE TYPE_HPPA_CPU
	393
	394	#define cpu_list hppa_cpu_list
	395	void hppa_cpu_list(void);
	396
61766fe9	397	#endif /* HPPA_CPU_H */