[mirror_qemu.git] / target / hppa / cpu.h

/*
 * PA-RISC emulation cpu definitions for qemu.
 *
 * Copyright (c) 2016 Richard Henderson <rth@twiddle.net>
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2.1 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#ifndef HPPA_CPU_H
#define HPPA_CPU_H

#include "cpu-qom.h"
#include "exec/cpu-defs.h"
#include "qemu/cpu-float.h"

/* PA-RISC 1.x processors have a strong memory model.  */
/* ??? While we do not yet implement PA-RISC 2.0, those processors have
   a weak memory model, but with TLB bits that force ordering on a per-page
   basis.  It's probably easier to fall back to a strong memory model.  */
#define TCG_GUEST_DEFAULT_MO        TCG_MO_ALL

#define MMU_KERNEL_IDX   0
#define MMU_USER_IDX     3
#define MMU_PHYS_IDX     4
#define TARGET_INSN_START_EXTRA_WORDS 1

/* Hardware exceptions, interupts, faults, and traps.  */
#define EXCP_HPMC                1  /* high priority machine check */
#define EXCP_POWER_FAIL          2
#define EXCP_RC                  3  /* recovery counter */
#define EXCP_EXT_INTERRUPT       4  /* external interrupt */
#define EXCP_LPMC                5  /* low priority machine check */
#define EXCP_ITLB_MISS           6  /* itlb miss / instruction page fault */
#define EXCP_IMP                 7  /* instruction memory protection trap */
#define EXCP_ILL                 8  /* illegal instruction trap */
#define EXCP_BREAK               9  /* break instruction */
#define EXCP_PRIV_OPR            10 /* privileged operation trap */
#define EXCP_PRIV_REG            11 /* privileged register trap */
#define EXCP_OVERFLOW            12 /* signed overflow trap */
#define EXCP_COND                13 /* trap-on-condition */
#define EXCP_ASSIST              14 /* assist exception trap */
#define EXCP_DTLB_MISS           15 /* dtlb miss / data page fault */
#define EXCP_NA_ITLB_MISS        16 /* non-access itlb miss */
#define EXCP_NA_DTLB_MISS        17 /* non-access dtlb miss */
#define EXCP_DMP                 18 /* data memory protection trap */
#define EXCP_DMB                 19 /* data memory break trap */
#define EXCP_TLB_DIRTY           20 /* tlb dirty bit trap */
#define EXCP_PAGE_REF            21 /* page reference trap */
#define EXCP_ASSIST_EMU          22 /* assist emulation trap */
#define EXCP_HPT                 23 /* high-privilege transfer trap */
#define EXCP_LPT                 24 /* low-privilege transfer trap */
#define EXCP_TB                  25 /* taken branch trap */
#define EXCP_DMAR                26 /* data memory access rights trap */
#define EXCP_DMPI                27 /* data memory protection id trap */
#define EXCP_UNALIGN             28 /* unaligned data reference trap */
#define EXCP_PER_INTERRUPT       29 /* performance monitor interrupt */

/* Exceptions for linux-user emulation.  */
#define EXCP_SYSCALL             30
#define EXCP_SYSCALL_LWS         31

/* Emulated hardware TOC button */
#define EXCP_TOC                 32 /* TOC = Transfer of control (NMI) */

#define CPU_INTERRUPT_NMI       CPU_INTERRUPT_TGT_EXT_3         /* TOC */

/* Taken from Linux kernel: arch/parisc/include/asm/psw.h */
#define PSW_I            0x00000001
#define PSW_D            0x00000002
#define PSW_P            0x00000004
#define PSW_Q            0x00000008
#define PSW_R            0x00000010
#define PSW_F            0x00000020
#define PSW_G            0x00000040 /* PA1.x only */
#define PSW_O            0x00000080 /* PA2.0 only */
#define PSW_CB           0x0000ff00
#define PSW_M            0x00010000
#define PSW_V            0x00020000
#define PSW_C            0x00040000
#define PSW_B            0x00080000
#define PSW_X            0x00100000
#define PSW_N            0x00200000
#define PSW_L            0x00400000
#define PSW_H            0x00800000
#define PSW_T            0x01000000
#define PSW_S            0x02000000
#define PSW_E            0x04000000
#ifdef TARGET_HPPA64
#define PSW_W            0x08000000 /* PA2.0 only */
#else
#define PSW_W            0
#endif
#define PSW_Z            0x40000000 /* PA1.x only */
#define PSW_Y            0x80000000 /* PA1.x only */

#define PSW_SM (PSW_W | PSW_E | PSW_O | PSW_G | PSW_F \
               | PSW_R | PSW_Q | PSW_P | PSW_D | PSW_I)

/* ssm/rsm instructions number PSW_W and PSW_E differently */
#define PSW_SM_I         PSW_I      /* Enable External Interrupts */
#define PSW_SM_D         PSW_D
#define PSW_SM_P         PSW_P
#define PSW_SM_Q         PSW_Q      /* Enable Interrupt State Collection */
#define PSW_SM_R         PSW_R      /* Enable Recover Counter Trap */
#ifdef TARGET_HPPA64
#define PSW_SM_E         0x100
#define PSW_SM_W         0x200      /* PA2.0 only : Enable Wide Mode */
#else
#define PSW_SM_E         0
#define PSW_SM_W         0
#endif

#define CR_RC            0
#define CR_PID1          8
#define CR_PID2          9
#define CR_PID3          12
#define CR_PID4          13
#define CR_SCRCCR        10
#define CR_SAR           11
#define CR_IVA           14
#define CR_EIEM          15
#define CR_IT            16
#define CR_IIASQ         17
#define CR_IIAOQ         18
#define CR_IIR           19
#define CR_ISR           20
#define CR_IOR           21
#define CR_IPSW          22
#define CR_EIRR          23

#if TARGET_REGISTER_BITS == 32
typedef uint32_t target_ureg;
typedef int32_t  target_sreg;
#define TREG_FMT_lx   "%08"PRIx32
#define TREG_FMT_ld   "%"PRId32
#else
typedef uint64_t target_ureg;
typedef int64_t  target_sreg;
#define TREG_FMT_lx   "%016"PRIx64
#define TREG_FMT_ld   "%"PRId64
#endif

typedef struct {
    uint64_t va_b;
    uint64_t va_e;
    target_ureg pa;
    unsigned u : 1;
    unsigned t : 1;
    unsigned d : 1;
    unsigned b : 1;
    unsigned page_size : 4;
    unsigned ar_type : 3;
    unsigned ar_pl1 : 2;
    unsigned ar_pl2 : 2;
    unsigned entry_valid : 1;
    unsigned access_id : 16;
} hppa_tlb_entry;

typedef struct CPUArchState {
    target_ureg gr[32];
    uint64_t fr[32];
    uint64_t sr[8];          /* stored shifted into place for gva */

    target_ureg psw;         /* All psw bits except the following:  */
    target_ureg psw_n;       /* boolean */
    target_sreg psw_v;       /* in most significant bit */

    /* Splitting the carry-borrow field into the MSB and "the rest", allows
     * for "the rest" to be deleted when it is unused, but the MSB is in use.
     * In addition, it's easier to compute carry-in for bit B+1 than it is to
     * compute carry-out for bit B (3 vs 4 insns for addition, assuming the
     * host has the appropriate add-with-carry insn to compute the msb).
     * Therefore the carry bits are stored as: cb_msb : cb & 0x11111110.
     */
    target_ureg psw_cb;      /* in least significant bit of next nibble */
    target_ureg psw_cb_msb;  /* boolean */

    target_ureg iaoq_f;      /* front */
    target_ureg iaoq_b;      /* back, aka next instruction */
    uint64_t iasq_f;
    uint64_t iasq_b;

    uint32_t fr0_shadow;     /* flags, c, ca/cq, rm, d, enables */
    float_status fp_status;

    target_ureg cr[32];      /* control registers */
    target_ureg cr_back[2];  /* back of cr17/cr18 */
    target_ureg shadow[7];   /* shadow registers */

    /* ??? The number of entries isn't specified by the architecture.  */
#define HPPA_TLB_ENTRIES        256
#define HPPA_BTLB_ENTRIES       0

    /* ??? Implement a unified itlb/dtlb for the moment.  */
    /* ??? We should use a more intelligent data structure.  */
    hppa_tlb_entry tlb[HPPA_TLB_ENTRIES];
    uint32_t tlb_last;
} CPUHPPAState;

/**
 * HPPACPU:
 * @env: #CPUHPPAState
 *
 * An HPPA CPU.
 */
struct ArchCPU {
    /*< private >*/
    CPUState parent_obj;
    /*< public >*/

    CPUNegativeOffsetState neg;
    CPUHPPAState env;
    QEMUTimer *alarm_timer;
};

#include "exec/cpu-all.h"

static inline int cpu_mmu_index(CPUHPPAState *env, bool ifetch)
{
#ifdef CONFIG_USER_ONLY
    return MMU_USER_IDX;
#else
    if (env->psw & (ifetch ? PSW_C : PSW_D)) {
        return env->iaoq_f & 3;
    }
    return MMU_PHYS_IDX;  /* mmu disabled */
#endif
}

void hppa_translate_init(void);

#define CPU_RESOLVING_TYPE TYPE_HPPA_CPU

static inline target_ulong hppa_form_gva_psw(target_ureg psw, uint64_t spc,
                                             target_ureg off)
{
#ifdef CONFIG_USER_ONLY
    return off;
#else
    off &= (psw & PSW_W ? 0x3fffffffffffffffull : 0xffffffffull);
    return spc | off;
#endif
}

static inline target_ulong hppa_form_gva(CPUHPPAState *env, uint64_t spc,
                                         target_ureg off)
{
    return hppa_form_gva_psw(env->psw, spc, off);
}

/*
 * Since PSW_{I,CB} will never need to be in tb->flags, reuse them.
 * TB_FLAG_SR_SAME indicates that SR4 through SR7 all contain the
 * same value.
 */
#define TB_FLAG_SR_SAME     PSW_I
#define TB_FLAG_PRIV_SHIFT  8
#define TB_FLAG_UNALIGN     0x400

static inline void cpu_get_tb_cpu_state(CPUHPPAState *env, target_ulong *pc,
                                        target_ulong *cs_base,
                                        uint32_t *pflags)
{
    uint32_t flags = env->psw_n * PSW_N;

    /* TB lookup assumes that PC contains the complete virtual address.
       If we leave space+offset separate, we'll get ITLB misses to an
       incomplete virtual address.  This also means that we must separate
       out current cpu priviledge from the low bits of IAOQ_F.  */
#ifdef CONFIG_USER_ONLY
    *pc = env->iaoq_f & -4;
    *cs_base = env->iaoq_b & -4;
    flags |= TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus;
#else
    /* ??? E, T, H, L, B, P bits need to be here, when implemented.  */
    flags |= env->psw & (PSW_W | PSW_C | PSW_D);
    flags |= (env->iaoq_f & 3) << TB_FLAG_PRIV_SHIFT;

    *pc = (env->psw & PSW_C
           ? hppa_form_gva_psw(env->psw, env->iasq_f, env->iaoq_f & -4)
           : env->iaoq_f & -4);
    *cs_base = env->iasq_f;

    /* Insert a difference between IAOQ_B and IAOQ_F within the otherwise zero
       low 32-bits of CS_BASE.  This will succeed for all direct branches,
       which is the primary case we care about -- using goto_tb within a page.
       Failure is indicated by a zero difference.  */
    if (env->iasq_f == env->iasq_b) {
        target_sreg diff = env->iaoq_b - env->iaoq_f;
        if (TARGET_REGISTER_BITS == 32 || diff == (int32_t)diff) {
            *cs_base |= (uint32_t)diff;
        }
    }
    if ((env->sr[4] == env->sr[5])
        & (env->sr[4] == env->sr[6])
        & (env->sr[4] == env->sr[7])) {
        flags |= TB_FLAG_SR_SAME;
    }
#endif

    *pflags = flags;
}

target_ureg cpu_hppa_get_psw(CPUHPPAState *env);
void cpu_hppa_put_psw(CPUHPPAState *env, target_ureg);
void cpu_hppa_loaded_fr0(CPUHPPAState *env);

#ifdef CONFIG_USER_ONLY
static inline void cpu_hppa_change_prot_id(CPUHPPAState *env) { }
#else
void cpu_hppa_change_prot_id(CPUHPPAState *env);
#endif

int hppa_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
int hppa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
void hppa_cpu_dump_state(CPUState *cs, FILE *f, int);
#ifndef CONFIG_USER_ONLY
hwaddr hppa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr);
bool hppa_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
                       MMUAccessType access_type, int mmu_idx,
                       bool probe, uintptr_t retaddr);
void hppa_cpu_do_interrupt(CPUState *cpu);
bool hppa_cpu_exec_interrupt(CPUState *cpu, int int_req);
int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx,
                              int type, hwaddr *pphys, int *pprot);
extern const MemoryRegionOps hppa_io_eir_ops;
extern const VMStateDescription vmstate_hppa_cpu;
void hppa_cpu_alarm_timer(void *);
int hppa_artype_for_page(CPUHPPAState *env, target_ulong vaddr);
#endif
G_NORETURN void hppa_dynamic_excp(CPUHPPAState *env, int excp, uintptr_t ra);

#endif /* HPPA_CPU_H */
Commit	Line	Data
61766fe9 RH	1	/*
	2	* PA-RISC emulation cpu definitions for qemu.
	3	*
	4	* Copyright (c) 2016 Richard Henderson <rth@twiddle.net>
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
d6ea4236	9	* version 2.1 of the License, or (at your option) any later version.
61766fe9 RH	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
	18	*/
	19
	20	#ifndef HPPA_CPU_H
	21	#define HPPA_CPU_H
	22
61766fe9	23	#include "cpu-qom.h"
74433bf0	24	#include "exec/cpu-defs.h"
69242e7e	25	#include "qemu/cpu-float.h"
61766fe9	26
7b93dab5 RH	27	/* PA-RISC 1.x processors have a strong memory model. */
	28	/* ??? While we do not yet implement PA-RISC 2.0, those processors have
	29	a weak memory model, but with TLB bits that force ordering on a per-page
	30	basis. It's probably easier to fall back to a strong memory model. */
	31	#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL
	32
3d68ee7b RH	33	#define MMU_KERNEL_IDX 0
	34	#define MMU_USER_IDX 3
	35	#define MMU_PHYS_IDX 4
61766fe9 RH	36	#define TARGET_INSN_START_EXTRA_WORDS 1
61766fe9 RH	37
2986721d RH	38	/* Hardware exceptions, interupts, faults, and traps. */
	39	#define EXCP_HPMC 1 /* high priority machine check */
	40	#define EXCP_POWER_FAIL 2
	41	#define EXCP_RC 3 /* recovery counter */
	42	#define EXCP_EXT_INTERRUPT 4 /* external interrupt */
	43	#define EXCP_LPMC 5 /* low priority machine check */
	44	#define EXCP_ITLB_MISS 6 /* itlb miss / instruction page fault */
	45	#define EXCP_IMP 7 /* instruction memory protection trap */
	46	#define EXCP_ILL 8 /* illegal instruction trap */
	47	#define EXCP_BREAK 9 /* break instruction */
	48	#define EXCP_PRIV_OPR 10 /* privileged operation trap */
	49	#define EXCP_PRIV_REG 11 /* privileged register trap */
	50	#define EXCP_OVERFLOW 12 /* signed overflow trap */
	51	#define EXCP_COND 13 /* trap-on-condition */
	52	#define EXCP_ASSIST 14 /* assist exception trap */
	53	#define EXCP_DTLB_MISS 15 /* dtlb miss / data page fault */
	54	#define EXCP_NA_ITLB_MISS 16 /* non-access itlb miss */
	55	#define EXCP_NA_DTLB_MISS 17 /* non-access dtlb miss */
	56	#define EXCP_DMP 18 /* data memory protection trap */
	57	#define EXCP_DMB 19 /* data memory break trap */
	58	#define EXCP_TLB_DIRTY 20 /* tlb dirty bit trap */
	59	#define EXCP_PAGE_REF 21 /* page reference trap */
	60	#define EXCP_ASSIST_EMU 22 /* assist emulation trap */
	61	#define EXCP_HPT 23 /* high-privilege transfer trap */
	62	#define EXCP_LPT 24 /* low-privilege transfer trap */
	63	#define EXCP_TB 25 /* taken branch trap */
	64	#define EXCP_DMAR 26 /* data memory access rights trap */
	65	#define EXCP_DMPI 27 /* data memory protection id trap */
	66	#define EXCP_UNALIGN 28 /* unaligned data reference trap */
	67	#define EXCP_PER_INTERRUPT 29 /* performance monitor interrupt */
	68
	69	/* Exceptions for linux-user emulation. */
	70	#define EXCP_SYSCALL 30
	71	#define EXCP_SYSCALL_LWS 31
61766fe9	72
4a4554c6 HD	73	/* Emulated hardware TOC button */
	74	#define EXCP_TOC 32 /* TOC = Transfer of control (NMI) */
	75
	76	#define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3 /* TOC */
	77
fa57e327 RH	78	/* Taken from Linux kernel: arch/parisc/include/asm/psw.h */
	79	#define PSW_I 0x00000001
	80	#define PSW_D 0x00000002
	81	#define PSW_P 0x00000004
	82	#define PSW_Q 0x00000008
	83	#define PSW_R 0x00000010
	84	#define PSW_F 0x00000020
	85	#define PSW_G 0x00000040 /* PA1.x only */
	86	#define PSW_O 0x00000080 /* PA2.0 only */
	87	#define PSW_CB 0x0000ff00
	88	#define PSW_M 0x00010000
	89	#define PSW_V 0x00020000
	90	#define PSW_C 0x00040000
	91	#define PSW_B 0x00080000
	92	#define PSW_X 0x00100000
	93	#define PSW_N 0x00200000
	94	#define PSW_L 0x00400000
	95	#define PSW_H 0x00800000
	96	#define PSW_T 0x01000000
	97	#define PSW_S 0x02000000
	98	#define PSW_E 0x04000000
	99	#ifdef TARGET_HPPA64
	100	#define PSW_W 0x08000000 /* PA2.0 only */
	101	#else
	102	#define PSW_W 0
	103	#endif
	104	#define PSW_Z 0x40000000 /* PA1.x only */
	105	#define PSW_Y 0x80000000 /* PA1.x only */
	106
	107	#define PSW_SM (PSW_W \| PSW_E \| PSW_O \| PSW_G \| PSW_F \
	108	\| PSW_R \| PSW_Q \| PSW_P \| PSW_D \| PSW_I)
	109
	110	/* ssm/rsm instructions number PSW_W and PSW_E differently */
	111	#define PSW_SM_I PSW_I /* Enable External Interrupts */
	112	#define PSW_SM_D PSW_D
	113	#define PSW_SM_P PSW_P
	114	#define PSW_SM_Q PSW_Q /* Enable Interrupt State Collection */
	115	#define PSW_SM_R PSW_R /* Enable Recover Counter Trap */
	116	#ifdef TARGET_HPPA64
	117	#define PSW_SM_E 0x100
	118	#define PSW_SM_W 0x200 /* PA2.0 only : Enable Wide Mode */
	119	#else
	120	#define PSW_SM_E 0
	121	#define PSW_SM_W 0
	122	#endif
	123
35136a77	124	#define CR_RC 0
d5de20bd SS	125	#define CR_PID1 8
	126	#define CR_PID2 9
	127	#define CR_PID3 12
	128	#define CR_PID4 13
35136a77 RH	129	#define CR_SCRCCR 10
	130	#define CR_SAR 11
	131	#define CR_IVA 14
	132	#define CR_EIEM 15
	133	#define CR_IT 16
	134	#define CR_IIASQ 17
	135	#define CR_IIAOQ 18
	136	#define CR_IIR 19
	137	#define CR_ISR 20
	138	#define CR_IOR 21
	139	#define CR_IPSW 22
	140	#define CR_EIRR 23
	141
eaa3783b RH	142	#if TARGET_REGISTER_BITS == 32
	143	typedef uint32_t target_ureg;
	144	typedef int32_t target_sreg;
	145	#define TREG_FMT_lx "%08"PRIx32
	146	#define TREG_FMT_ld "%"PRId32
	147	#else
	148	typedef uint64_t target_ureg;
	149	typedef int64_t target_sreg;
	150	#define TREG_FMT_lx "%016"PRIx64
	151	#define TREG_FMT_ld "%"PRId64
	152	#endif
	153
650cdb2a RH	154	typedef struct {
	155	uint64_t va_b;
	156	uint64_t va_e;
	157	target_ureg pa;
	158	unsigned u : 1;
	159	unsigned t : 1;
	160	unsigned d : 1;
	161	unsigned b : 1;
	162	unsigned page_size : 4;
	163	unsigned ar_type : 3;
	164	unsigned ar_pl1 : 2;
	165	unsigned ar_pl2 : 2;
	166	unsigned entry_valid : 1;
	167	unsigned access_id : 16;
	168	} hppa_tlb_entry;
	169
1ea4a06a	170	typedef struct CPUArchState {
eaa3783b	171	target_ureg gr[32];
61766fe9	172	uint64_t fr[32];
33423472	173	uint64_t sr[8]; /* stored shifted into place for gva */
61766fe9	174
eaa3783b RH	175	target_ureg psw; /* All psw bits except the following: */
	176	target_ureg psw_n; /* boolean */
	177	target_sreg psw_v; /* in most significant bit */
61766fe9 RH	178
	179	/* Splitting the carry-borrow field into the MSB and "the rest", allows
	180	* for "the rest" to be deleted when it is unused, but the MSB is in use.
	181	* In addition, it's easier to compute carry-in for bit B+1 than it is to
	182	* compute carry-out for bit B (3 vs 4 insns for addition, assuming the
	183	* host has the appropriate add-with-carry insn to compute the msb).
	184	* Therefore the carry bits are stored as: cb_msb : cb & 0x11111110.
	185	*/
eaa3783b RH	186	target_ureg psw_cb; /* in least significant bit of next nibble */
eaa3783b RH	187	target_ureg psw_cb_msb; /* boolean */
61766fe9	188
eaa3783b RH	189	target_ureg iaoq_f; /* front */
eaa3783b RH	190	target_ureg iaoq_b; /* back, aka next instruction */
c301f34e RH	191	uint64_t iasq_f;
c301f34e RH	192	uint64_t iasq_b;
61766fe9	193
61766fe9 RH	194	uint32_t fr0_shadow; /* flags, c, ca/cq, rm, d, enables */
	195	float_status fp_status;
	196
35136a77 RH	197	target_ureg cr[32]; /* control registers */
35136a77 RH	198	target_ureg cr_back[2]; /* back of cr17/cr18 */
f49b3537	199	target_ureg shadow[7]; /* shadow registers */
35136a77	200
650cdb2a	201	/* ??? The number of entries isn't specified by the architecture. */
df5c6a50 HD	202	#define HPPA_TLB_ENTRIES 256
	203	#define HPPA_BTLB_ENTRIES 0
	204
650cdb2a RH	205	/* ??? Implement a unified itlb/dtlb for the moment. */
650cdb2a RH	206	/* ??? We should use a more intelligent data structure. */
df5c6a50	207	hppa_tlb_entry tlb[HPPA_TLB_ENTRIES];
650cdb2a	208	uint32_t tlb_last;
1ea4a06a	209	} CPUHPPAState;
61766fe9 RH	210
	211	/**
	212	* HPPACPU:
	213	* @env: #CPUHPPAState
	214	*
	215	* An HPPA CPU.
	216	*/
b36e239e	217	struct ArchCPU {
61766fe9 RH	218	/< private >/
	219	CPUState parent_obj;
	220	/< public >/
	221
5b146dc7	222	CPUNegativeOffsetState neg;
61766fe9	223	CPUHPPAState env;
49c29d6c	224	QEMUTimer *alarm_timer;
61766fe9 RH	225	};
61766fe9 RH	226
61766fe9 RH	227	#include "exec/cpu-all.h"
	228
	229	static inline int cpu_mmu_index(CPUHPPAState *env, bool ifetch)
	230	{
3d68ee7b RH	231	#ifdef CONFIG_USER_ONLY
	232	return MMU_USER_IDX;
	233	#else
	234	if (env->psw & (ifetch ? PSW_C : PSW_D)) {
	235	return env->iaoq_f & 3;
	236	}
	237	return MMU_PHYS_IDX; /* mmu disabled */
	238	#endif
61766fe9 RH	239	}
	240
	241	void hppa_translate_init(void);
	242
0dacec87	243	#define CPU_RESOLVING_TYPE TYPE_HPPA_CPU
61766fe9	244
c301f34e RH	245	static inline target_ulong hppa_form_gva_psw(target_ureg psw, uint64_t spc,
	246	target_ureg off)
	247	{
	248	#ifdef CONFIG_USER_ONLY
	249	return off;
	250	#else
	251	off &= (psw & PSW_W ? 0x3fffffffffffffffull : 0xffffffffull);
	252	return spc \| off;
	253	#endif
	254	}
	255
	256	static inline target_ulong hppa_form_gva(CPUHPPAState *env, uint64_t spc,
	257	target_ureg off)
	258	{
	259	return hppa_form_gva_psw(env->psw, spc, off);
	260	}
	261
217d1a5e RH	262	/*
217d1a5e RH	263	* Since PSW_{I,CB} will never need to be in tb->flags, reuse them.
494737b7 RH	264	* TB_FLAG_SR_SAME indicates that SR4 through SR7 all contain the
	265	* same value.
	266	*/
	267	#define TB_FLAG_SR_SAME PSW_I
c301f34e	268	#define TB_FLAG_PRIV_SHIFT 8
217d1a5e	269	#define TB_FLAG_UNALIGN 0x400
c301f34e	270
61766fe9 RH	271	static inline void cpu_get_tb_cpu_state(CPUHPPAState env, target_ulong pc,
	272	target_ulong *cs_base,
	273	uint32_t *pflags)
	274	{
c301f34e RH	275	uint32_t flags = env->psw_n * PSW_N;
	276
	277	/* TB lookup assumes that PC contains the complete virtual address.
	278	If we leave space+offset separate, we'll get ITLB misses to an
	279	incomplete virtual address. This also means that we must separate
	280	out current cpu priviledge from the low bits of IAOQ_F. */
	281	#ifdef CONFIG_USER_ONLY
ebd0e151 RH	282	*pc = env->iaoq_f & -4;
ebd0e151 RH	283	*cs_base = env->iaoq_b & -4;
217d1a5e	284	flags \|= TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus;
c301f34e	285	#else
3d68ee7b	286	/* ??? E, T, H, L, B, P bits need to be here, when implemented. */
c301f34e RH	287	flags \|= env->psw & (PSW_W \| PSW_C \| PSW_D);
	288	flags \|= (env->iaoq_f & 3) << TB_FLAG_PRIV_SHIFT;
	289
	290	*pc = (env->psw & PSW_C
	291	? hppa_form_gva_psw(env->psw, env->iasq_f, env->iaoq_f & -4)
	292	: env->iaoq_f & -4);
	293	*cs_base = env->iasq_f;
	294
	295	/* Insert a difference between IAOQ_B and IAOQ_F within the otherwise zero
	296	low 32-bits of CS_BASE. This will succeed for all direct branches,
	297	which is the primary case we care about -- using goto_tb within a page.
	298	Failure is indicated by a zero difference. */
	299	if (env->iasq_f == env->iasq_b) {
	300	target_sreg diff = env->iaoq_b - env->iaoq_f;
	301	if (TARGET_REGISTER_BITS == 32 \|\| diff == (int32_t)diff) {
	302	*cs_base \|= (uint32_t)diff;
	303	}
	304	}
494737b7 RH	305	if ((env->sr[4] == env->sr[5])
	306	& (env->sr[4] == env->sr[6])
	307	& (env->sr[4] == env->sr[7])) {
	308	flags \|= TB_FLAG_SR_SAME;
	309	}
c301f34e RH	310	#endif
	311
	312	*pflags = flags;
61766fe9 RH	313	}
61766fe9 RH	314
eaa3783b RH	315	target_ureg cpu_hppa_get_psw(CPUHPPAState *env);
eaa3783b RH	316	void cpu_hppa_put_psw(CPUHPPAState *env, target_ureg);
61766fe9 RH	317	void cpu_hppa_loaded_fr0(CPUHPPAState *env);
61766fe9 RH	318
d5de20bd SS	319	#ifdef CONFIG_USER_ONLY
	320	static inline void cpu_hppa_change_prot_id(CPUHPPAState *env) { }
	321	#else
	322	void cpu_hppa_change_prot_id(CPUHPPAState *env);
	323	#endif
	324
a010bdbe	325	int hppa_cpu_gdb_read_register(CPUState cpu, GByteArray buf, int reg);
61766fe9	326	int hppa_cpu_gdb_write_register(CPUState cpu, uint8_t buf, int reg);
90c84c56	327	void hppa_cpu_dump_state(CPUState cs, FILE f, int);
860e0b96	328	#ifndef CONFIG_USER_ONLY
6d2d454a	329	hwaddr hppa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr);
3c7bef03 RH	330	bool hppa_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
	331	MMUAccessType access_type, int mmu_idx,
	332	bool probe, uintptr_t retaddr);
68fa1780 PMD	333	void hppa_cpu_do_interrupt(CPUState *cpu);
68fa1780 PMD	334	bool hppa_cpu_exec_interrupt(CPUState *cpu, int int_req);
650cdb2a RH	335	int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx,
650cdb2a RH	336	int type, hwaddr pphys, int pprot);
4f5f2548	337	extern const MemoryRegionOps hppa_io_eir_ops;
8a9358cc	338	extern const VMStateDescription vmstate_hppa_cpu;
49c29d6c	339	void hppa_cpu_alarm_timer(void *);
43e05652	340	int hppa_artype_for_page(CPUHPPAState *env, target_ulong vaddr);
650cdb2a	341	#endif
8905770b	342	G_NORETURN void hppa_dynamic_excp(CPUHPPAState *env, int excp, uintptr_t ra);
61766fe9 RH	343
61766fe9 RH	344	#endif /* HPPA_CPU_H */