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61766fe9 RH |
1 | /* |
2 | * HPPA emulation cpu helpers for qemu. | |
3 | * | |
4 | * Copyright (c) 2016 Richard Henderson <rth@twiddle.net> | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
d6ea4236 | 9 | * version 2.1 of the License, or (at your option) any later version. |
61766fe9 RH |
10 | * |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #include "qemu/osdep.h" | |
cd617484 | 21 | #include "qemu/log.h" |
61766fe9 | 22 | #include "cpu.h" |
61766fe9 | 23 | #include "fpu/softfloat.h" |
d5de20bd | 24 | #include "exec/exec-all.h" |
61766fe9 | 25 | #include "exec/helper-proto.h" |
90c84c56 | 26 | #include "qemu/qemu-print.h" |
61766fe9 | 27 | |
c53e401e | 28 | target_ulong cpu_hppa_get_psw(CPUHPPAState *env) |
61766fe9 | 29 | { |
c53e401e RH |
30 | target_ulong psw; |
31 | target_ulong mask1 = (target_ulong)-1 / 0xf; | |
32 | target_ulong maskf = (target_ulong)-1 / 0xffff * 0xf; | |
61766fe9 RH |
33 | |
34 | /* Fold carry bits down to 8 consecutive bits. */ | |
931adff3 | 35 | /* ^^^b^^^c^^^d^^^e^^^f^^^g^^^h^^^i^^^j^^^k^^^l^^^m^^^n^^^o^^^p^^^^ */ |
931adff3 RH |
36 | psw = (env->psw_cb >> 4) & mask1; |
37 | /* .......b...c...d...e...f...g...h...i...j...k...l...m...n...o...p */ | |
61766fe9 | 38 | psw |= psw >> 3; |
931adff3 | 39 | /* .......b..bc..cd..de..ef..fg..gh..hi..ij..jk..kl..lm..mn..no..op */ |
931adff3 RH |
40 | psw |= psw >> 6; |
41 | psw &= maskf; | |
42 | /* .............bcd............efgh............ijkl............mnop */ | |
931adff3 RH |
43 | psw |= psw >> 12; |
44 | /* .............bcd.........bcdefgh........efghijkl........ijklmnop */ | |
c53e401e | 45 | psw |= env->psw_cb_msb << 39; |
931adff3 | 46 | /* .............bcd........abcdefgh........efghijkl........ijklmnop */ |
931adff3 RH |
47 | |
48 | /* For hppa64, the two 8-bit fields are discontiguous. */ | |
49 | if (hppa_is_pa20(env)) { | |
50 | psw = (psw & 0xff00000000ull) | ((psw & 0xff) << 8); | |
51 | } else { | |
52 | psw = (psw & 0xff) << 8; | |
53 | } | |
61766fe9 | 54 | |
fa57e327 RH |
55 | psw |= env->psw_n * PSW_N; |
56 | psw |= (env->psw_v < 0) * PSW_V; | |
57 | psw |= env->psw; | |
61766fe9 RH |
58 | |
59 | return psw; | |
60 | } | |
61 | ||
c53e401e | 62 | void cpu_hppa_put_psw(CPUHPPAState *env, target_ulong psw) |
61766fe9 | 63 | { |
931adff3 | 64 | uint64_t reserved; |
c53e401e | 65 | target_ulong cb = 0; |
61766fe9 | 66 | |
931adff3 RH |
67 | /* Do not allow reserved bits to be set. */ |
68 | if (hppa_is_pa20(env)) { | |
69 | reserved = MAKE_64BIT_MASK(40, 24) | MAKE_64BIT_MASK(28, 4); | |
70 | reserved |= PSW_G; /* PA1.x only */ | |
71 | reserved |= PSW_E; /* not implemented */ | |
72 | } else { | |
73 | reserved = MAKE_64BIT_MASK(32, 32) | MAKE_64BIT_MASK(28, 2); | |
74 | reserved |= PSW_O | PSW_W; /* PA2.0 only */ | |
75 | reserved |= PSW_E | PSW_Y | PSW_Z; /* not implemented */ | |
76 | } | |
77 | psw &= ~reserved; | |
78 | ||
fa57e327 RH |
79 | env->psw = psw & ~(PSW_N | PSW_V | PSW_CB); |
80 | env->psw_n = (psw / PSW_N) & 1; | |
81 | env->psw_v = -((psw / PSW_V) & 1); | |
61766fe9 | 82 | |
931adff3 RH |
83 | env->psw_cb_msb = (psw >> 39) & 1; |
84 | cb |= ((psw >> 38) & 1) << 60; | |
85 | cb |= ((psw >> 37) & 1) << 56; | |
86 | cb |= ((psw >> 36) & 1) << 52; | |
87 | cb |= ((psw >> 35) & 1) << 48; | |
88 | cb |= ((psw >> 34) & 1) << 44; | |
89 | cb |= ((psw >> 33) & 1) << 40; | |
90 | cb |= ((psw >> 32) & 1) << 36; | |
91 | cb |= ((psw >> 15) & 1) << 32; | |
61766fe9 RH |
92 | cb |= ((psw >> 14) & 1) << 28; |
93 | cb |= ((psw >> 13) & 1) << 24; | |
94 | cb |= ((psw >> 12) & 1) << 20; | |
95 | cb |= ((psw >> 11) & 1) << 16; | |
96 | cb |= ((psw >> 10) & 1) << 12; | |
97 | cb |= ((psw >> 9) & 1) << 8; | |
98 | cb |= ((psw >> 8) & 1) << 4; | |
99 | env->psw_cb = cb; | |
100 | } | |
101 | ||
90c84c56 | 102 | void hppa_cpu_dump_state(CPUState *cs, FILE *f, int flags) |
61766fe9 | 103 | { |
5718fe4c | 104 | CPUHPPAState *env = cpu_env(cs); |
c53e401e RH |
105 | target_ulong psw = cpu_hppa_get_psw(env); |
106 | target_ulong psw_cb; | |
fa57e327 | 107 | char psw_c[20]; |
5718fe4c RH |
108 | int i, w; |
109 | uint64_t m; | |
110 | ||
111 | if (hppa_is_pa20(env)) { | |
112 | w = 16; | |
113 | m = UINT64_MAX; | |
114 | } else { | |
115 | w = 8; | |
116 | m = UINT32_MAX; | |
117 | } | |
61766fe9 | 118 | |
770525f8 | 119 | qemu_fprintf(f, "IA_F " TARGET_FMT_lx " IA_B " TARGET_FMT_lx |
5718fe4c | 120 | " IIR %0*" PRIx64 "\n", |
90c84c56 | 121 | hppa_form_gva_psw(psw, env->iasq_f, env->iaoq_f), |
770525f8 | 122 | hppa_form_gva_psw(psw, env->iasq_b, env->iaoq_b), |
5718fe4c | 123 | w, m & env->cr[CR_IIR]); |
fa57e327 RH |
124 | |
125 | psw_c[0] = (psw & PSW_W ? 'W' : '-'); | |
126 | psw_c[1] = (psw & PSW_E ? 'E' : '-'); | |
127 | psw_c[2] = (psw & PSW_S ? 'S' : '-'); | |
128 | psw_c[3] = (psw & PSW_T ? 'T' : '-'); | |
129 | psw_c[4] = (psw & PSW_H ? 'H' : '-'); | |
130 | psw_c[5] = (psw & PSW_L ? 'L' : '-'); | |
131 | psw_c[6] = (psw & PSW_N ? 'N' : '-'); | |
132 | psw_c[7] = (psw & PSW_X ? 'X' : '-'); | |
133 | psw_c[8] = (psw & PSW_B ? 'B' : '-'); | |
134 | psw_c[9] = (psw & PSW_C ? 'C' : '-'); | |
135 | psw_c[10] = (psw & PSW_V ? 'V' : '-'); | |
136 | psw_c[11] = (psw & PSW_M ? 'M' : '-'); | |
137 | psw_c[12] = (psw & PSW_F ? 'F' : '-'); | |
138 | psw_c[13] = (psw & PSW_R ? 'R' : '-'); | |
139 | psw_c[14] = (psw & PSW_Q ? 'Q' : '-'); | |
140 | psw_c[15] = (psw & PSW_P ? 'P' : '-'); | |
141 | psw_c[16] = (psw & PSW_D ? 'D' : '-'); | |
142 | psw_c[17] = (psw & PSW_I ? 'I' : '-'); | |
143 | psw_c[18] = '\0'; | |
c53e401e RH |
144 | psw_cb = ((env->psw_cb >> 4) & 0x1111111111111111ull) |
145 | | (env->psw_cb_msb << 60); | |
fa57e327 | 146 | |
5718fe4c RH |
147 | qemu_fprintf(f, "PSW %0*" PRIx64 " CB %0*" PRIx64 " %s\n", |
148 | w, m & psw, w, m & psw_cb, psw_c); | |
fa57e327 RH |
149 | |
150 | for (i = 0; i < 32; i++) { | |
5718fe4c RH |
151 | qemu_fprintf(f, "GR%02d %0*" PRIx64 "%c", |
152 | i, w, m & env->gr[i], | |
90c84c56 | 153 | (i & 3) == 3 ? '\n' : ' '); |
33423472 RH |
154 | } |
155 | #ifndef CONFIG_USER_ONLY | |
156 | for (i = 0; i < 8; i++) { | |
90c84c56 MA |
157 | qemu_fprintf(f, "SR%02d %08x%c", i, (uint32_t)(env->sr[i] >> 32), |
158 | (i & 3) == 3 ? '\n' : ' '); | |
61766fe9 | 159 | } |
33423472 | 160 | #endif |
90c84c56 | 161 | qemu_fprintf(f, "\n"); |
61766fe9 RH |
162 | |
163 | /* ??? FR */ | |
164 | } |