]>
Commit | Line | Data |
---|---|---|
1a19da0d RH |
1 | /* |
2 | * HPPA interrupt helper routines | |
3 | * | |
4 | * Copyright (c) 2017 Richard Henderson | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
d6ea4236 | 9 | * version 2.1 of the License, or (at your option) any later version. |
1a19da0d RH |
10 | * |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #include "qemu/osdep.h" | |
21 | #include "qemu/main-loop.h" | |
0d114d0d | 22 | #include "qemu/log.h" |
1a19da0d | 23 | #include "cpu.h" |
1a19da0d | 24 | #include "exec/helper-proto.h" |
2e5b09fd | 25 | #include "hw/core/cpu.h" |
4a4554c6 | 26 | #include "hw/hppa/hppa_hardware.h" |
1a19da0d | 27 | |
4f5f2548 RH |
28 | static void eval_interrupt(HPPACPU *cpu) |
29 | { | |
30 | CPUState *cs = CPU(cpu); | |
31 | if (cpu->env.cr[CR_EIRR] & cpu->env.cr[CR_EIEM]) { | |
32 | cpu_interrupt(cs, CPU_INTERRUPT_HARD); | |
33 | } else { | |
34 | cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); | |
35 | } | |
36 | } | |
37 | ||
38 | /* Each CPU has a word mapped into the GSC bus. Anything on the GSC bus | |
39 | * can write to this word to raise an external interrupt on the target CPU. | |
40 | * This includes the system controler (DINO) for regular devices, or | |
41 | * another CPU for SMP interprocessor interrupts. | |
42 | */ | |
43 | static uint64_t io_eir_read(void *opaque, hwaddr addr, unsigned size) | |
44 | { | |
45 | HPPACPU *cpu = opaque; | |
46 | ||
47 | /* ??? What does a read of this register over the GSC bus do? */ | |
48 | return cpu->env.cr[CR_EIRR]; | |
49 | } | |
50 | ||
51 | static void io_eir_write(void *opaque, hwaddr addr, | |
52 | uint64_t data, unsigned size) | |
53 | { | |
54 | HPPACPU *cpu = opaque; | |
55 | int le_bit = ~data & (TARGET_REGISTER_BITS - 1); | |
56 | ||
57 | cpu->env.cr[CR_EIRR] |= (target_ureg)1 << le_bit; | |
58 | eval_interrupt(cpu); | |
59 | } | |
60 | ||
61 | const MemoryRegionOps hppa_io_eir_ops = { | |
62 | .read = io_eir_read, | |
63 | .write = io_eir_write, | |
64 | .valid.min_access_size = 4, | |
65 | .valid.max_access_size = 4, | |
66 | .impl.min_access_size = 4, | |
67 | .impl.max_access_size = 4, | |
68 | }; | |
69 | ||
49c29d6c RH |
70 | void hppa_cpu_alarm_timer(void *opaque) |
71 | { | |
72 | /* Raise interrupt 0. */ | |
73 | io_eir_write(opaque, 0, 0, 4); | |
74 | } | |
75 | ||
4f5f2548 RH |
76 | void HELPER(write_eirr)(CPUHPPAState *env, target_ureg val) |
77 | { | |
78 | env->cr[CR_EIRR] &= ~val; | |
79 | qemu_mutex_lock_iothread(); | |
25f32708 | 80 | eval_interrupt(env_archcpu(env)); |
4f5f2548 RH |
81 | qemu_mutex_unlock_iothread(); |
82 | } | |
83 | ||
84 | void HELPER(write_eiem)(CPUHPPAState *env, target_ureg val) | |
85 | { | |
86 | env->cr[CR_EIEM] = val; | |
87 | qemu_mutex_lock_iothread(); | |
25f32708 | 88 | eval_interrupt(env_archcpu(env)); |
4f5f2548 RH |
89 | qemu_mutex_unlock_iothread(); |
90 | } | |
1a19da0d RH |
91 | |
92 | void hppa_cpu_do_interrupt(CPUState *cs) | |
93 | { | |
94 | HPPACPU *cpu = HPPA_CPU(cs); | |
95 | CPUHPPAState *env = &cpu->env; | |
96 | int i = cs->exception_index; | |
97 | target_ureg iaoq_f = env->iaoq_f; | |
98 | target_ureg iaoq_b = env->iaoq_b; | |
c301f34e RH |
99 | uint64_t iasq_f = env->iasq_f; |
100 | uint64_t iasq_b = env->iasq_b; | |
1a19da0d | 101 | |
1a19da0d RH |
102 | target_ureg old_psw; |
103 | ||
104 | /* As documented in pa2.0 -- interruption handling. */ | |
105 | /* step 1 */ | |
106 | env->cr[CR_IPSW] = old_psw = cpu_hppa_get_psw(env); | |
107 | ||
108 | /* step 2 -- note PSW_W == 0 for !HPPA64. */ | |
109 | cpu_hppa_put_psw(env, PSW_W | (i == EXCP_HPMC ? PSW_M : 0)); | |
110 | ||
111 | /* step 3 */ | |
c301f34e RH |
112 | env->cr[CR_IIASQ] = iasq_f >> 32; |
113 | env->cr_back[0] = iasq_b >> 32; | |
1a19da0d RH |
114 | env->cr[CR_IIAOQ] = iaoq_f; |
115 | env->cr_back[1] = iaoq_b; | |
116 | ||
117 | if (old_psw & PSW_Q) { | |
118 | /* step 5 */ | |
119 | /* ISR and IOR will be set elsewhere. */ | |
120 | switch (i) { | |
121 | case EXCP_ILL: | |
122 | case EXCP_BREAK: | |
123 | case EXCP_PRIV_REG: | |
124 | case EXCP_PRIV_OPR: | |
125 | /* IIR set via translate.c. */ | |
126 | break; | |
127 | ||
128 | case EXCP_OVERFLOW: | |
129 | case EXCP_COND: | |
130 | case EXCP_ASSIST: | |
131 | case EXCP_DTLB_MISS: | |
132 | case EXCP_NA_ITLB_MISS: | |
133 | case EXCP_NA_DTLB_MISS: | |
134 | case EXCP_DMAR: | |
135 | case EXCP_DMPI: | |
136 | case EXCP_UNALIGN: | |
137 | case EXCP_DMP: | |
138 | case EXCP_DMB: | |
139 | case EXCP_TLB_DIRTY: | |
140 | case EXCP_PAGE_REF: | |
141 | case EXCP_ASSIST_EMU: | |
142 | { | |
143 | /* Avoid reading directly from the virtual address, lest we | |
144 | raise another exception from some sort of TLB issue. */ | |
650cdb2a RH |
145 | /* ??? An alternate fool-proof method would be to store the |
146 | instruction data into the unwind info. That's probably | |
147 | a bit too much in the way of extra storage required. */ | |
1a19da0d RH |
148 | vaddr vaddr; |
149 | hwaddr paddr; | |
150 | ||
151 | paddr = vaddr = iaoq_f & -4; | |
c301f34e | 152 | if (old_psw & PSW_C) { |
650cdb2a RH |
153 | int prot, t; |
154 | ||
155 | vaddr = hppa_form_gva_psw(old_psw, iasq_f, vaddr); | |
156 | t = hppa_get_physical_address(env, vaddr, MMU_KERNEL_IDX, | |
157 | 0, &paddr, &prot); | |
158 | if (t >= 0) { | |
159 | /* We can't re-load the instruction. */ | |
160 | env->cr[CR_IIR] = 0; | |
161 | break; | |
162 | } | |
c301f34e | 163 | } |
1a19da0d RH |
164 | env->cr[CR_IIR] = ldl_phys(cs->as, paddr); |
165 | } | |
166 | break; | |
167 | ||
168 | default: | |
169 | /* Other exceptions do not set IIR. */ | |
170 | break; | |
171 | } | |
172 | ||
173 | /* step 6 */ | |
174 | env->shadow[0] = env->gr[1]; | |
175 | env->shadow[1] = env->gr[8]; | |
176 | env->shadow[2] = env->gr[9]; | |
177 | env->shadow[3] = env->gr[16]; | |
178 | env->shadow[4] = env->gr[17]; | |
179 | env->shadow[5] = env->gr[24]; | |
180 | env->shadow[6] = env->gr[25]; | |
181 | } | |
182 | ||
183 | /* step 7 */ | |
4a4554c6 HD |
184 | if (i == EXCP_TOC) { |
185 | env->iaoq_f = FIRMWARE_START; | |
186 | /* help SeaBIOS and provide iaoq_b and iasq_back in shadow regs */ | |
187 | env->gr[24] = env->cr_back[0]; | |
188 | env->gr[25] = env->cr_back[1]; | |
189 | } else { | |
190 | env->iaoq_f = env->cr[CR_IVA] + 32 * i; | |
191 | } | |
1a19da0d | 192 | env->iaoq_b = env->iaoq_f + 4; |
c301f34e RH |
193 | env->iasq_f = 0; |
194 | env->iasq_b = 0; | |
1a19da0d RH |
195 | |
196 | if (qemu_loglevel_mask(CPU_LOG_INT)) { | |
197 | static const char * const names[] = { | |
198 | [EXCP_HPMC] = "high priority machine check", | |
199 | [EXCP_POWER_FAIL] = "power fail interrupt", | |
200 | [EXCP_RC] = "recovery counter trap", | |
201 | [EXCP_EXT_INTERRUPT] = "external interrupt", | |
202 | [EXCP_LPMC] = "low priority machine check", | |
203 | [EXCP_ITLB_MISS] = "instruction tlb miss fault", | |
204 | [EXCP_IMP] = "instruction memory protection trap", | |
205 | [EXCP_ILL] = "illegal instruction trap", | |
206 | [EXCP_BREAK] = "break instruction trap", | |
207 | [EXCP_PRIV_OPR] = "privileged operation trap", | |
208 | [EXCP_PRIV_REG] = "privileged register trap", | |
209 | [EXCP_OVERFLOW] = "overflow trap", | |
210 | [EXCP_COND] = "conditional trap", | |
211 | [EXCP_ASSIST] = "assist exception trap", | |
212 | [EXCP_DTLB_MISS] = "data tlb miss fault", | |
213 | [EXCP_NA_ITLB_MISS] = "non-access instruction tlb miss", | |
214 | [EXCP_NA_DTLB_MISS] = "non-access data tlb miss", | |
215 | [EXCP_DMP] = "data memory protection trap", | |
216 | [EXCP_DMB] = "data memory break trap", | |
217 | [EXCP_TLB_DIRTY] = "tlb dirty bit trap", | |
218 | [EXCP_PAGE_REF] = "page reference trap", | |
219 | [EXCP_ASSIST_EMU] = "assist emulation trap", | |
220 | [EXCP_HPT] = "high-privilege transfer trap", | |
221 | [EXCP_LPT] = "low-privilege transfer trap", | |
222 | [EXCP_TB] = "taken branch trap", | |
223 | [EXCP_DMAR] = "data memory access rights trap", | |
224 | [EXCP_DMPI] = "data memory protection id trap", | |
225 | [EXCP_UNALIGN] = "unaligned data reference trap", | |
226 | [EXCP_PER_INTERRUPT] = "performance monitor interrupt", | |
227 | [EXCP_SYSCALL] = "syscall", | |
228 | [EXCP_SYSCALL_LWS] = "syscall-lws", | |
4a4554c6 | 229 | [EXCP_TOC] = "TOC (transfer of control)", |
1a19da0d RH |
230 | }; |
231 | static int count; | |
232 | const char *name = NULL; | |
233 | char unknown[16]; | |
234 | ||
235 | if (i >= 0 && i < ARRAY_SIZE(names)) { | |
236 | name = names[i]; | |
237 | } | |
238 | if (!name) { | |
239 | snprintf(unknown, sizeof(unknown), "unknown %d", i); | |
240 | name = unknown; | |
241 | } | |
242 | qemu_log("INT %6d: %s @ " TARGET_FMT_lx "," TARGET_FMT_lx | |
243 | " -> " TREG_FMT_lx " " TARGET_FMT_lx "\n", | |
244 | ++count, name, | |
c301f34e RH |
245 | hppa_form_gva(env, iasq_f, iaoq_f), |
246 | hppa_form_gva(env, iasq_b, iaoq_b), | |
1a19da0d | 247 | env->iaoq_f, |
c301f34e RH |
248 | hppa_form_gva(env, (uint64_t)env->cr[CR_ISR] << 32, |
249 | env->cr[CR_IOR])); | |
1a19da0d RH |
250 | } |
251 | cs->exception_index = -1; | |
252 | } | |
253 | ||
254 | bool hppa_cpu_exec_interrupt(CPUState *cs, int interrupt_request) | |
255 | { | |
1a19da0d RH |
256 | HPPACPU *cpu = HPPA_CPU(cs); |
257 | CPUHPPAState *env = &cpu->env; | |
258 | ||
4a4554c6 HD |
259 | if (interrupt_request & CPU_INTERRUPT_NMI) { |
260 | /* Raise TOC (NMI) interrupt */ | |
261 | cpu_reset_interrupt(cs, CPU_INTERRUPT_NMI); | |
262 | cs->exception_index = EXCP_TOC; | |
263 | hppa_cpu_do_interrupt(cs); | |
264 | return true; | |
265 | } | |
266 | ||
1a19da0d RH |
267 | /* If interrupts are requested and enabled, raise them. */ |
268 | if ((env->psw & PSW_I) && (interrupt_request & CPU_INTERRUPT_HARD)) { | |
269 | cs->exception_index = EXCP_EXT_INTERRUPT; | |
270 | hppa_cpu_do_interrupt(cs); | |
271 | return true; | |
272 | } | |
1a19da0d RH |
273 | return false; |
274 | } |