[mirror_qemu.git] / target / i386 / gdbstub.c

/*
 * x86 gdb server stub
 *
 * Copyright (c) 2003-2005 Fabrice Bellard
 * Copyright (c) 2013 SUSE LINUX Products GmbH
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */
#include "qemu/osdep.h"
#include "cpu.h"
#include "exec/gdbstub.h"

#ifdef TARGET_X86_64
static const int gpr_map[16] = {
    R_EAX, R_EBX, R_ECX, R_EDX, R_ESI, R_EDI, R_EBP, R_ESP,
    8, 9, 10, 11, 12, 13, 14, 15
};
#else
#define gpr_map gpr_map32
#endif
static const int gpr_map32[8] = { 0, 1, 2, 3, 4, 5, 6, 7 };

/*
 * Keep these in sync with assignment to
 * gdb_num_core_regs in target/i386/cpu.c
 * and with the machine description
 */

/*
 * SEG: 6 segments, plus fs_base, gs_base, kernel_gs_base
 */

/*
 * general regs ----->  8 or 16
 */
#define IDX_NB_IP       1
#define IDX_NB_FLAGS    1
#define IDX_NB_SEG      (6 + 3)
#define IDX_NB_CTL      6
#define IDX_NB_FP       16
/*
 * fpu regs ----------> 8 or 16
 */
#define IDX_NB_MXCSR    1
/*
 *          total ----> 8+1+1+9+6+16+8+1=50 or 16+1+1+9+6+16+16+1=66
 */

#define IDX_IP_REG      CPU_NB_REGS
#define IDX_FLAGS_REG   (IDX_IP_REG + IDX_NB_IP)
#define IDX_SEG_REGS    (IDX_FLAGS_REG + IDX_NB_FLAGS)
#define IDX_CTL_REGS    (IDX_SEG_REGS + IDX_NB_SEG)
#define IDX_FP_REGS     (IDX_CTL_REGS + IDX_NB_CTL)
#define IDX_XMM_REGS    (IDX_FP_REGS + IDX_NB_FP)
#define IDX_MXCSR_REG   (IDX_XMM_REGS + CPU_NB_REGS)

#define IDX_CTL_CR0_REG     (IDX_CTL_REGS + 0)
#define IDX_CTL_CR2_REG     (IDX_CTL_REGS + 1)
#define IDX_CTL_CR3_REG     (IDX_CTL_REGS + 2)
#define IDX_CTL_CR4_REG     (IDX_CTL_REGS + 3)
#define IDX_CTL_CR8_REG     (IDX_CTL_REGS + 4)
#define IDX_CTL_EFER_REG    (IDX_CTL_REGS + 5)

#ifdef TARGET_X86_64
#define GDB_FORCE_64 1
#else
#define GDB_FORCE_64 0
#endif


int x86_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
{
    X86CPU *cpu = X86_CPU(cs);
    CPUX86State *env = &cpu->env;

    uint64_t tpr;

    /* N.B. GDB can't deal with changes in registers or sizes in the middle
       of a session. So if we're in 32-bit mode on a 64-bit cpu, still act
       as if we're on a 64-bit cpu. */

    if (n < CPU_NB_REGS) {
        if (TARGET_LONG_BITS == 64) {
            if (env->hflags & HF_CS64_MASK) {
                return gdb_get_reg64(mem_buf, env->regs[gpr_map[n]]);
            } else if (n < CPU_NB_REGS32) {
                return gdb_get_reg64(mem_buf,
                                     env->regs[gpr_map[n]] & 0xffffffffUL);
            } else {
                return gdb_get_regl(mem_buf, 0);
            }
        } else {
            return gdb_get_reg32(mem_buf, env->regs[gpr_map32[n]]);
        }
    } else if (n >= IDX_FP_REGS && n < IDX_FP_REGS + 8) {
        floatx80 *fp = (floatx80 *) &env->fpregs[n - IDX_FP_REGS];
        int len = gdb_get_reg64(mem_buf, cpu_to_le64(fp->low));
        len += gdb_get_reg16(mem_buf, cpu_to_le16(fp->high));
        return len;
    } else if (n >= IDX_XMM_REGS && n < IDX_XMM_REGS + CPU_NB_REGS) {
        n -= IDX_XMM_REGS;
        if (n < CPU_NB_REGS32 || TARGET_LONG_BITS == 64) {
            return gdb_get_reg128(mem_buf,
                                  env->xmm_regs[n].ZMM_Q(0),
                                  env->xmm_regs[n].ZMM_Q(1));
        }
    } else {
        switch (n) {
        case IDX_IP_REG:
            if (TARGET_LONG_BITS == 64) {
                if (env->hflags & HF_CS64_MASK) {
                    return gdb_get_reg64(mem_buf, env->eip);
                } else {
                    return gdb_get_reg64(mem_buf, env->eip & 0xffffffffUL);
                }
            } else {
                return gdb_get_reg32(mem_buf, env->eip);
            }
        case IDX_FLAGS_REG:
            return gdb_get_reg32(mem_buf, env->eflags);

        case IDX_SEG_REGS:
            return gdb_get_reg32(mem_buf, env->segs[R_CS].selector);
        case IDX_SEG_REGS + 1:
            return gdb_get_reg32(mem_buf, env->segs[R_SS].selector);
        case IDX_SEG_REGS + 2:
            return gdb_get_reg32(mem_buf, env->segs[R_DS].selector);
        case IDX_SEG_REGS + 3:
            return gdb_get_reg32(mem_buf, env->segs[R_ES].selector);
        case IDX_SEG_REGS + 4:
            return gdb_get_reg32(mem_buf, env->segs[R_FS].selector);
        case IDX_SEG_REGS + 5:
            return gdb_get_reg32(mem_buf, env->segs[R_GS].selector);

        case IDX_SEG_REGS + 6:
            if ((env->hflags & HF_CS64_MASK) || GDB_FORCE_64) {
                return gdb_get_reg64(mem_buf, env->segs[R_FS].base);
            }
            return gdb_get_reg32(mem_buf, env->segs[R_FS].base);

        case IDX_SEG_REGS + 7:
            if ((env->hflags & HF_CS64_MASK) || GDB_FORCE_64) {
                return gdb_get_reg64(mem_buf, env->segs[R_GS].base);
            }
            return gdb_get_reg32(mem_buf, env->segs[R_GS].base);

        case IDX_SEG_REGS + 8:
#ifdef TARGET_X86_64
            if ((env->hflags & HF_CS64_MASK) || GDB_FORCE_64) {
                return gdb_get_reg64(mem_buf, env->kernelgsbase);
            }
            return gdb_get_reg32(mem_buf, env->kernelgsbase);
#else
            return gdb_get_reg32(mem_buf, 0);
#endif

        case IDX_FP_REGS + 8:
            return gdb_get_reg32(mem_buf, env->fpuc);
        case IDX_FP_REGS + 9:
            return gdb_get_reg32(mem_buf, (env->fpus & ~0x3800) |
                                          (env->fpstt & 0x7) << 11);
        case IDX_FP_REGS + 10:
            return gdb_get_reg32(mem_buf, 0); /* ftag */
        case IDX_FP_REGS + 11:
            return gdb_get_reg32(mem_buf, 0); /* fiseg */
        case IDX_FP_REGS + 12:
            return gdb_get_reg32(mem_buf, 0); /* fioff */
        case IDX_FP_REGS + 13:
            return gdb_get_reg32(mem_buf, 0); /* foseg */
        case IDX_FP_REGS + 14:
            return gdb_get_reg32(mem_buf, 0); /* fooff */
        case IDX_FP_REGS + 15:
            return gdb_get_reg32(mem_buf, 0); /* fop */

        case IDX_MXCSR_REG:
            return gdb_get_reg32(mem_buf, env->mxcsr);

        case IDX_CTL_CR0_REG:
            if ((env->hflags & HF_CS64_MASK) || GDB_FORCE_64) {
                return gdb_get_reg64(mem_buf, env->cr[0]);
            }
            return gdb_get_reg32(mem_buf, env->cr[0]);

        case IDX_CTL_CR2_REG:
            if ((env->hflags & HF_CS64_MASK) || GDB_FORCE_64) {
                return gdb_get_reg64(mem_buf, env->cr[2]);
            }
            return gdb_get_reg32(mem_buf, env->cr[2]);

        case IDX_CTL_CR3_REG:
            if ((env->hflags & HF_CS64_MASK) || GDB_FORCE_64) {
                return gdb_get_reg64(mem_buf, env->cr[3]);
            }
            return gdb_get_reg32(mem_buf, env->cr[3]);

        case IDX_CTL_CR4_REG:
            if ((env->hflags & HF_CS64_MASK) || GDB_FORCE_64) {
                return gdb_get_reg64(mem_buf, env->cr[4]);
            }
            return gdb_get_reg32(mem_buf, env->cr[4]);

        case IDX_CTL_CR8_REG:
#ifdef CONFIG_SOFTMMU
            tpr = cpu_get_apic_tpr(cpu->apic_state);
#else
            tpr = 0;
#endif
            if ((env->hflags & HF_CS64_MASK) || GDB_FORCE_64) {
                return gdb_get_reg64(mem_buf, tpr);
            }
            return gdb_get_reg32(mem_buf, tpr);

        case IDX_CTL_EFER_REG:
            if ((env->hflags & HF_CS64_MASK) || GDB_FORCE_64) {
                return gdb_get_reg64(mem_buf, env->efer);
            }
            return gdb_get_reg32(mem_buf, env->efer);
        }
    }
    return 0;
}

static int x86_cpu_gdb_load_seg(X86CPU *cpu, int sreg, uint8_t *mem_buf)
{
    CPUX86State *env = &cpu->env;
    uint16_t selector = ldl_p(mem_buf);

    if (selector != env->segs[sreg].selector) {
#if defined(CONFIG_USER_ONLY)
        cpu_x86_load_seg(env, sreg, selector);
#else
        unsigned int limit, flags;
        target_ulong base;

        if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
            int dpl = (env->eflags & VM_MASK) ? 3 : 0;
            base = selector << 4;
            limit = 0xffff;
            flags = DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
                    DESC_A_MASK | (dpl << DESC_DPL_SHIFT);
        } else {
            if (!cpu_x86_get_descr_debug(env, selector, &base, &limit,
                                         &flags)) {
                return 4;
            }
        }
        cpu_x86_load_seg_cache(env, sreg, selector, base, limit, flags);
#endif
    }
    return 4;
}

int x86_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
{
    X86CPU *cpu = X86_CPU(cs);
    CPUX86State *env = &cpu->env;
    uint32_t tmp;

    /* N.B. GDB can't deal with changes in registers or sizes in the middle
       of a session. So if we're in 32-bit mode on a 64-bit cpu, still act
       as if we're on a 64-bit cpu. */

    if (n < CPU_NB_REGS) {
        if (TARGET_LONG_BITS == 64) {
            if (env->hflags & HF_CS64_MASK) {
                env->regs[gpr_map[n]] = ldtul_p(mem_buf);
            } else if (n < CPU_NB_REGS32) {
                env->regs[gpr_map[n]] = ldtul_p(mem_buf) & 0xffffffffUL;
            }
            return sizeof(target_ulong);
        } else if (n < CPU_NB_REGS32) {
            n = gpr_map32[n];
            env->regs[n] &= ~0xffffffffUL;
            env->regs[n] |= (uint32_t)ldl_p(mem_buf);
            return 4;
        }
    } else if (n >= IDX_FP_REGS && n < IDX_FP_REGS + 8) {
        floatx80 *fp = (floatx80 *) &env->fpregs[n - IDX_FP_REGS];
        fp->low = le64_to_cpu(* (uint64_t *) mem_buf);
        fp->high = le16_to_cpu(* (uint16_t *) (mem_buf + 8));
        return 10;
    } else if (n >= IDX_XMM_REGS && n < IDX_XMM_REGS + CPU_NB_REGS) {
        n -= IDX_XMM_REGS;
        if (n < CPU_NB_REGS32 || TARGET_LONG_BITS == 64) {
            env->xmm_regs[n].ZMM_Q(0) = ldq_p(mem_buf);
            env->xmm_regs[n].ZMM_Q(1) = ldq_p(mem_buf + 8);
            return 16;
        }
    } else {
        switch (n) {
        case IDX_IP_REG:
            if (TARGET_LONG_BITS == 64) {
                if (env->hflags & HF_CS64_MASK) {
                    env->eip = ldq_p(mem_buf);
                } else {
                    env->eip = ldq_p(mem_buf) & 0xffffffffUL;
                }
                return 8;
            } else {
                env->eip &= ~0xffffffffUL;
                env->eip |= (uint32_t)ldl_p(mem_buf);
                return 4;
            }
        case IDX_FLAGS_REG:
            env->eflags = ldl_p(mem_buf);
            return 4;

        case IDX_SEG_REGS:
            return x86_cpu_gdb_load_seg(cpu, R_CS, mem_buf);
        case IDX_SEG_REGS + 1:
            return x86_cpu_gdb_load_seg(cpu, R_SS, mem_buf);
        case IDX_SEG_REGS + 2:
            return x86_cpu_gdb_load_seg(cpu, R_DS, mem_buf);
        case IDX_SEG_REGS + 3:
            return x86_cpu_gdb_load_seg(cpu, R_ES, mem_buf);
        case IDX_SEG_REGS + 4:
            return x86_cpu_gdb_load_seg(cpu, R_FS, mem_buf);
        case IDX_SEG_REGS + 5:
            return x86_cpu_gdb_load_seg(cpu, R_GS, mem_buf);

        case IDX_SEG_REGS + 6:
            if (env->hflags & HF_CS64_MASK) {
                env->segs[R_FS].base = ldq_p(mem_buf);
                return 8;
            }
            env->segs[R_FS].base = ldl_p(mem_buf);
            return 4;

        case IDX_SEG_REGS + 7:
            if (env->hflags & HF_CS64_MASK) {
                env->segs[R_GS].base = ldq_p(mem_buf);
                return 8;
            }
            env->segs[R_GS].base = ldl_p(mem_buf);
            return 4;

        case IDX_SEG_REGS + 8:
#ifdef TARGET_X86_64
            if (env->hflags & HF_CS64_MASK) {
                env->kernelgsbase = ldq_p(mem_buf);
                return 8;
            }
            env->kernelgsbase = ldl_p(mem_buf);
#endif
            return 4;

        case IDX_FP_REGS + 8:
            cpu_set_fpuc(env, ldl_p(mem_buf));
            return 4;
        case IDX_FP_REGS + 9:
            tmp = ldl_p(mem_buf);
            env->fpstt = (tmp >> 11) & 7;
            env->fpus = tmp & ~0x3800;
            return 4;
        case IDX_FP_REGS + 10: /* ftag */
            return 4;
        case IDX_FP_REGS + 11: /* fiseg */
            return 4;
        case IDX_FP_REGS + 12: /* fioff */
            return 4;
        case IDX_FP_REGS + 13: /* foseg */
            return 4;
        case IDX_FP_REGS + 14: /* fooff */
            return 4;
        case IDX_FP_REGS + 15: /* fop */
            return 4;

        case IDX_MXCSR_REG:
            cpu_set_mxcsr(env, ldl_p(mem_buf));
            return 4;

        case IDX_CTL_CR0_REG:
            if (env->hflags & HF_CS64_MASK) {
                cpu_x86_update_cr0(env, ldq_p(mem_buf));
                return 8;
            }
            cpu_x86_update_cr0(env, ldl_p(mem_buf));
            return 4;

        case IDX_CTL_CR2_REG:
            if (env->hflags & HF_CS64_MASK) {
                env->cr[2] = ldq_p(mem_buf);
                return 8;
            }
            env->cr[2] = ldl_p(mem_buf);
            return 4;

        case IDX_CTL_CR3_REG:
            if (env->hflags & HF_CS64_MASK) {
                cpu_x86_update_cr3(env, ldq_p(mem_buf));
                return 8;
            }
            cpu_x86_update_cr3(env, ldl_p(mem_buf));
            return 4;

        case IDX_CTL_CR4_REG:
            if (env->hflags & HF_CS64_MASK) {
                cpu_x86_update_cr4(env, ldq_p(mem_buf));
                return 8;
            }
            cpu_x86_update_cr4(env, ldl_p(mem_buf));
            return 4;

        case IDX_CTL_CR8_REG:
            if (env->hflags & HF_CS64_MASK) {
#ifdef CONFIG_SOFTMMU
                cpu_set_apic_tpr(cpu->apic_state, ldq_p(mem_buf));
#endif
                return 8;
            }
#ifdef CONFIG_SOFTMMU
            cpu_set_apic_tpr(cpu->apic_state, ldl_p(mem_buf));
#endif
            return 4;

        case IDX_CTL_EFER_REG:
            if (env->hflags & HF_CS64_MASK) {
                cpu_load_efer(env, ldq_p(mem_buf));
                return 8;
            }
            cpu_load_efer(env, ldl_p(mem_buf));
            return 4;

        }
    }
    /* Unrecognised register.  */
    return 0;
}
Commit	Line	Data
f20f9df0 AF	1	/*
	2	* x86 gdb server stub
	3	*
	4	* Copyright (c) 2003-2005 Fabrice Bellard
	5	* Copyright (c) 2013 SUSE LINUX Products GmbH
	6	*
	7	* This library is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU Lesser General Public
	9	* License as published by the Free Software Foundation; either
	10	* version 2 of the License, or (at your option) any later version.
	11	*
	12	* This library is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	* Lesser General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU Lesser General Public
	18	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
	19	*/
b6a0aa05	20	#include "qemu/osdep.h"
33c11879	21	#include "cpu.h"
5b50e790	22	#include "exec/gdbstub.h"
f20f9df0 AF	23
	24	#ifdef TARGET_X86_64
	25	static const int gpr_map[16] = {
	26	R_EAX, R_EBX, R_ECX, R_EDX, R_ESI, R_EDI, R_EBP, R_ESP,
	27	8, 9, 10, 11, 12, 13, 14, 15
	28	};
	29	#else
	30	#define gpr_map gpr_map32
	31	#endif
	32	static const int gpr_map32[8] = { 0, 1, 2, 3, 4, 5, 6, 7 };
	33
7b0f97ba DG	34	/*
	35	* Keep these in sync with assignment to
	36	* gdb_num_core_regs in target/i386/cpu.c
	37	* and with the machine description
	38	*/
	39
	40	/*
	41	* SEG: 6 segments, plus fs_base, gs_base, kernel_gs_base
	42	*/
	43
	44	/*
	45	* general regs -----> 8 or 16
	46	*/
	47	#define IDX_NB_IP 1
	48	#define IDX_NB_FLAGS 1
	49	#define IDX_NB_SEG (6 + 3)
	50	#define IDX_NB_CTL 6
	51	#define IDX_NB_FP 16
	52	/*
	53	* fpu regs ----------> 8 or 16
	54	*/
	55	#define IDX_NB_MXCSR 1
	56	/*
	57	* total ----> 8+1+1+9+6+16+8+1=50 or 16+1+1+9+6+16+16+1=66
	58	*/
	59
f20f9df0	60	#define IDX_IP_REG CPU_NB_REGS
7b0f97ba DG	61	#define IDX_FLAGS_REG (IDX_IP_REG + IDX_NB_IP)
	62	#define IDX_SEG_REGS (IDX_FLAGS_REG + IDX_NB_FLAGS)
	63	#define IDX_CTL_REGS (IDX_SEG_REGS + IDX_NB_SEG)
	64	#define IDX_FP_REGS (IDX_CTL_REGS + IDX_NB_CTL)
	65	#define IDX_XMM_REGS (IDX_FP_REGS + IDX_NB_FP)
f20f9df0 AF	66	#define IDX_MXCSR_REG (IDX_XMM_REGS + CPU_NB_REGS)
f20f9df0 AF	67
7b0f97ba DG	68	#define IDX_CTL_CR0_REG (IDX_CTL_REGS + 0)
	69	#define IDX_CTL_CR2_REG (IDX_CTL_REGS + 1)
	70	#define IDX_CTL_CR3_REG (IDX_CTL_REGS + 2)
	71	#define IDX_CTL_CR4_REG (IDX_CTL_REGS + 3)
	72	#define IDX_CTL_CR8_REG (IDX_CTL_REGS + 4)
	73	#define IDX_CTL_EFER_REG (IDX_CTL_REGS + 5)
	74
	75	#ifdef TARGET_X86_64
	76	#define GDB_FORCE_64 1
	77	#else
	78	#define GDB_FORCE_64 0
	79	#endif
	80
	81
a010bdbe	82	int x86_cpu_gdb_read_register(CPUState cs, GByteArray mem_buf, int n)
f20f9df0	83	{
5b50e790 AF	84	X86CPU *cpu = X86_CPU(cs);
	85	CPUX86State *env = &cpu->env;
	86
7b0f97ba DG	87	uint64_t tpr;
7b0f97ba DG	88
e3592bc9 DE	89	/* N.B. GDB can't deal with changes in registers or sizes in the middle
	90	of a session. So if we're in 32-bit mode on a 64-bit cpu, still act
	91	as if we're on a 64-bit cpu. */
	92
f20f9df0	93	if (n < CPU_NB_REGS) {
e3592bc9 DE	94	if (TARGET_LONG_BITS == 64) {
	95	if (env->hflags & HF_CS64_MASK) {
	96	return gdb_get_reg64(mem_buf, env->regs[gpr_map[n]]);
	97	} else if (n < CPU_NB_REGS32) {
	98	return gdb_get_reg64(mem_buf,
	99	env->regs[gpr_map[n]] & 0xffffffffUL);
	100	} else {
b7b8756a	101	return gdb_get_regl(mem_buf, 0);
e3592bc9 DE	102	}
e3592bc9 DE	103	} else {
986a2998	104	return gdb_get_reg32(mem_buf, env->regs[gpr_map32[n]]);
f20f9df0 AF	105	}
f20f9df0 AF	106	} else if (n >= IDX_FP_REGS && n < IDX_FP_REGS + 8) {
b7b8756a AB	107	floatx80 fp = (floatx80 ) &env->fpregs[n - IDX_FP_REGS];
b7b8756a AB	108	int len = gdb_get_reg64(mem_buf, cpu_to_le64(fp->low));
bbc40fef	109	len += gdb_get_reg16(mem_buf, cpu_to_le16(fp->high));
b7b8756a	110	return len;
f20f9df0 AF	111	} else if (n >= IDX_XMM_REGS && n < IDX_XMM_REGS + CPU_NB_REGS) {
f20f9df0 AF	112	n -= IDX_XMM_REGS;
e3592bc9	113	if (n < CPU_NB_REGS32 \|\| TARGET_LONG_BITS == 64) {
b7b8756a AB	114	return gdb_get_reg128(mem_buf,
	115	env->xmm_regs[n].ZMM_Q(0),
	116	env->xmm_regs[n].ZMM_Q(1));
f20f9df0 AF	117	}
	118	} else {
	119	switch (n) {
	120	case IDX_IP_REG:
e3592bc9 DE	121	if (TARGET_LONG_BITS == 64) {
	122	if (env->hflags & HF_CS64_MASK) {
	123	return gdb_get_reg64(mem_buf, env->eip);
	124	} else {
	125	return gdb_get_reg64(mem_buf, env->eip & 0xffffffffUL);
	126	}
f20f9df0	127	} else {
986a2998	128	return gdb_get_reg32(mem_buf, env->eip);
f20f9df0 AF	129	}
f20f9df0 AF	130	case IDX_FLAGS_REG:
986a2998	131	return gdb_get_reg32(mem_buf, env->eflags);
f20f9df0 AF	132
f20f9df0 AF	133	case IDX_SEG_REGS:
986a2998	134	return gdb_get_reg32(mem_buf, env->segs[R_CS].selector);
f20f9df0	135	case IDX_SEG_REGS + 1:
986a2998	136	return gdb_get_reg32(mem_buf, env->segs[R_SS].selector);
f20f9df0	137	case IDX_SEG_REGS + 2:
986a2998	138	return gdb_get_reg32(mem_buf, env->segs[R_DS].selector);
f20f9df0	139	case IDX_SEG_REGS + 3:
986a2998	140	return gdb_get_reg32(mem_buf, env->segs[R_ES].selector);
f20f9df0	141	case IDX_SEG_REGS + 4:
986a2998	142	return gdb_get_reg32(mem_buf, env->segs[R_FS].selector);
f20f9df0	143	case IDX_SEG_REGS + 5:
986a2998	144	return gdb_get_reg32(mem_buf, env->segs[R_GS].selector);
f20f9df0	145
7b0f97ba DG	146	case IDX_SEG_REGS + 6:
	147	if ((env->hflags & HF_CS64_MASK) \|\| GDB_FORCE_64) {
	148	return gdb_get_reg64(mem_buf, env->segs[R_FS].base);
	149	}
	150	return gdb_get_reg32(mem_buf, env->segs[R_FS].base);
	151
	152	case IDX_SEG_REGS + 7:
	153	if ((env->hflags & HF_CS64_MASK) \|\| GDB_FORCE_64) {
	154	return gdb_get_reg64(mem_buf, env->segs[R_GS].base);
	155	}
	156	return gdb_get_reg32(mem_buf, env->segs[R_GS].base);
	157
	158	case IDX_SEG_REGS + 8:
	159	#ifdef TARGET_X86_64
	160	if ((env->hflags & HF_CS64_MASK) \|\| GDB_FORCE_64) {
	161	return gdb_get_reg64(mem_buf, env->kernelgsbase);
	162	}
	163	return gdb_get_reg32(mem_buf, env->kernelgsbase);
	164	#else
	165	return gdb_get_reg32(mem_buf, 0);
	166	#endif
	167
f20f9df0	168	case IDX_FP_REGS + 8:
986a2998	169	return gdb_get_reg32(mem_buf, env->fpuc);
f20f9df0	170	case IDX_FP_REGS + 9:
986a2998 AF	171	return gdb_get_reg32(mem_buf, (env->fpus & ~0x3800) \|
986a2998 AF	172	(env->fpstt & 0x7) << 11);
f20f9df0	173	case IDX_FP_REGS + 10:
986a2998	174	return gdb_get_reg32(mem_buf, 0); /* ftag */
f20f9df0	175	case IDX_FP_REGS + 11:
986a2998	176	return gdb_get_reg32(mem_buf, 0); /* fiseg */
f20f9df0	177	case IDX_FP_REGS + 12:
986a2998	178	return gdb_get_reg32(mem_buf, 0); /* fioff */
f20f9df0	179	case IDX_FP_REGS + 13:
986a2998	180	return gdb_get_reg32(mem_buf, 0); /* foseg */
f20f9df0	181	case IDX_FP_REGS + 14:
986a2998	182	return gdb_get_reg32(mem_buf, 0); /* fooff */
f20f9df0	183	case IDX_FP_REGS + 15:
986a2998	184	return gdb_get_reg32(mem_buf, 0); /* fop */
f20f9df0 AF	185
f20f9df0 AF	186	case IDX_MXCSR_REG:
986a2998	187	return gdb_get_reg32(mem_buf, env->mxcsr);
7b0f97ba DG	188
	189	case IDX_CTL_CR0_REG:
	190	if ((env->hflags & HF_CS64_MASK) \|\| GDB_FORCE_64) {
	191	return gdb_get_reg64(mem_buf, env->cr[0]);
	192	}
	193	return gdb_get_reg32(mem_buf, env->cr[0]);
	194
	195	case IDX_CTL_CR2_REG:
	196	if ((env->hflags & HF_CS64_MASK) \|\| GDB_FORCE_64) {
	197	return gdb_get_reg64(mem_buf, env->cr[2]);
	198	}
	199	return gdb_get_reg32(mem_buf, env->cr[2]);
	200
	201	case IDX_CTL_CR3_REG:
	202	if ((env->hflags & HF_CS64_MASK) \|\| GDB_FORCE_64) {
	203	return gdb_get_reg64(mem_buf, env->cr[3]);
	204	}
	205	return gdb_get_reg32(mem_buf, env->cr[3]);
	206
	207	case IDX_CTL_CR4_REG:
	208	if ((env->hflags & HF_CS64_MASK) \|\| GDB_FORCE_64) {
	209	return gdb_get_reg64(mem_buf, env->cr[4]);
	210	}
	211	return gdb_get_reg32(mem_buf, env->cr[4]);
	212
	213	case IDX_CTL_CR8_REG:
	214	#ifdef CONFIG_SOFTMMU
	215	tpr = cpu_get_apic_tpr(cpu->apic_state);
	216	#else
	217	tpr = 0;
	218	#endif
	219	if ((env->hflags & HF_CS64_MASK) \|\| GDB_FORCE_64) {
	220	return gdb_get_reg64(mem_buf, tpr);
	221	}
	222	return gdb_get_reg32(mem_buf, tpr);
	223
	224	case IDX_CTL_EFER_REG:
	225	if ((env->hflags & HF_CS64_MASK) \|\| GDB_FORCE_64) {
	226	return gdb_get_reg64(mem_buf, env->efer);
	227	}
	228	return gdb_get_reg32(mem_buf, env->efer);
f20f9df0 AF	229	}
	230	}
	231	return 0;
	232	}
	233
5b50e790	234	static int x86_cpu_gdb_load_seg(X86CPU cpu, int sreg, uint8_t mem_buf)
f20f9df0	235	{
5b50e790	236	CPUX86State *env = &cpu->env;
f20f9df0 AF	237	uint16_t selector = ldl_p(mem_buf);
	238
	239	if (selector != env->segs[sreg].selector) {
	240	#if defined(CONFIG_USER_ONLY)
	241	cpu_x86_load_seg(env, sreg, selector);
	242	#else
	243	unsigned int limit, flags;
	244	target_ulong base;
	245
	246	if (!(env->cr[0] & CR0_PE_MASK) \|\| (env->eflags & VM_MASK)) {
b98dbc90	247	int dpl = (env->eflags & VM_MASK) ? 3 : 0;
f20f9df0 AF	248	base = selector << 4;
f20f9df0 AF	249	limit = 0xffff;
b98dbc90 PB	250	flags = DESC_P_MASK \| DESC_S_MASK \| DESC_W_MASK \|
b98dbc90 PB	251	DESC_A_MASK \| (dpl << DESC_DPL_SHIFT);
f20f9df0 AF	252	} else {
	253	if (!cpu_x86_get_descr_debug(env, selector, &base, &limit,
	254	&flags)) {
	255	return 4;
	256	}
	257	}
	258	cpu_x86_load_seg_cache(env, sreg, selector, base, limit, flags);
	259	#endif
	260	}
	261	return 4;
	262	}
	263
5b50e790	264	int x86_cpu_gdb_write_register(CPUState cs, uint8_t mem_buf, int n)
f20f9df0	265	{
5b50e790 AF	266	X86CPU *cpu = X86_CPU(cs);
5b50e790 AF	267	CPUX86State *env = &cpu->env;
f20f9df0 AF	268	uint32_t tmp;
f20f9df0 AF	269
e3592bc9 DE	270	/* N.B. GDB can't deal with changes in registers or sizes in the middle
	271	of a session. So if we're in 32-bit mode on a 64-bit cpu, still act
	272	as if we're on a 64-bit cpu. */
	273
f20f9df0	274	if (n < CPU_NB_REGS) {
e3592bc9 DE	275	if (TARGET_LONG_BITS == 64) {
	276	if (env->hflags & HF_CS64_MASK) {
	277	env->regs[gpr_map[n]] = ldtul_p(mem_buf);
	278	} else if (n < CPU_NB_REGS32) {
	279	env->regs[gpr_map[n]] = ldtul_p(mem_buf) & 0xffffffffUL;
	280	}
f20f9df0 AF	281	return sizeof(target_ulong);
	282	} else if (n < CPU_NB_REGS32) {
	283	n = gpr_map32[n];
	284	env->regs[n] &= ~0xffffffffUL;
	285	env->regs[n] \|= (uint32_t)ldl_p(mem_buf);
	286	return 4;
	287	}
	288	} else if (n >= IDX_FP_REGS && n < IDX_FP_REGS + 8) {
b7b8756a AB	289	floatx80 fp = (floatx80 ) &env->fpregs[n - IDX_FP_REGS];
	290	fp->low = le64_to_cpu(* (uint64_t *) mem_buf);
	291	fp->high = le16_to_cpu(* (uint16_t *) (mem_buf + 8));
f20f9df0 AF	292	return 10;
	293	} else if (n >= IDX_XMM_REGS && n < IDX_XMM_REGS + CPU_NB_REGS) {
	294	n -= IDX_XMM_REGS;
e3592bc9	295	if (n < CPU_NB_REGS32 \|\| TARGET_LONG_BITS == 64) {
19cbd87c EH	296	env->xmm_regs[n].ZMM_Q(0) = ldq_p(mem_buf);
19cbd87c EH	297	env->xmm_regs[n].ZMM_Q(1) = ldq_p(mem_buf + 8);
f20f9df0 AF	298	return 16;
	299	}
	300	} else {
	301	switch (n) {
	302	case IDX_IP_REG:
e3592bc9 DE	303	if (TARGET_LONG_BITS == 64) {
	304	if (env->hflags & HF_CS64_MASK) {
	305	env->eip = ldq_p(mem_buf);
	306	} else {
	307	env->eip = ldq_p(mem_buf) & 0xffffffffUL;
	308	}
f20f9df0 AF	309	return 8;
	310	} else {
	311	env->eip &= ~0xffffffffUL;
	312	env->eip \|= (uint32_t)ldl_p(mem_buf);
	313	return 4;
	314	}
	315	case IDX_FLAGS_REG:
	316	env->eflags = ldl_p(mem_buf);
	317	return 4;
	318
	319	case IDX_SEG_REGS:
5b50e790	320	return x86_cpu_gdb_load_seg(cpu, R_CS, mem_buf);
f20f9df0	321	case IDX_SEG_REGS + 1:
5b50e790	322	return x86_cpu_gdb_load_seg(cpu, R_SS, mem_buf);
f20f9df0	323	case IDX_SEG_REGS + 2:
5b50e790	324	return x86_cpu_gdb_load_seg(cpu, R_DS, mem_buf);
f20f9df0	325	case IDX_SEG_REGS + 3:
5b50e790	326	return x86_cpu_gdb_load_seg(cpu, R_ES, mem_buf);
f20f9df0	327	case IDX_SEG_REGS + 4:
5b50e790	328	return x86_cpu_gdb_load_seg(cpu, R_FS, mem_buf);
f20f9df0	329	case IDX_SEG_REGS + 5:
5b50e790	330	return x86_cpu_gdb_load_seg(cpu, R_GS, mem_buf);
f20f9df0	331
7b0f97ba DG	332	case IDX_SEG_REGS + 6:
	333	if (env->hflags & HF_CS64_MASK) {
	334	env->segs[R_FS].base = ldq_p(mem_buf);
	335	return 8;
	336	}
	337	env->segs[R_FS].base = ldl_p(mem_buf);
	338	return 4;
	339
	340	case IDX_SEG_REGS + 7:
	341	if (env->hflags & HF_CS64_MASK) {
	342	env->segs[R_GS].base = ldq_p(mem_buf);
	343	return 8;
	344	}
	345	env->segs[R_GS].base = ldl_p(mem_buf);
	346	return 4;
	347
7b0f97ba	348	case IDX_SEG_REGS + 8:
5a07192a	349	#ifdef TARGET_X86_64
7b0f97ba DG	350	if (env->hflags & HF_CS64_MASK) {
	351	env->kernelgsbase = ldq_p(mem_buf);
	352	return 8;
	353	}
	354	env->kernelgsbase = ldl_p(mem_buf);
7b0f97ba	355	#endif
5a07192a	356	return 4;
7b0f97ba	357
f20f9df0	358	case IDX_FP_REGS + 8:
5bde1407	359	cpu_set_fpuc(env, ldl_p(mem_buf));
f20f9df0 AF	360	return 4;
	361	case IDX_FP_REGS + 9:
	362	tmp = ldl_p(mem_buf);
	363	env->fpstt = (tmp >> 11) & 7;
	364	env->fpus = tmp & ~0x3800;
	365	return 4;
	366	case IDX_FP_REGS + 10: /* ftag */
	367	return 4;
	368	case IDX_FP_REGS + 11: /* fiseg */
	369	return 4;
	370	case IDX_FP_REGS + 12: /* fioff */
	371	return 4;
	372	case IDX_FP_REGS + 13: /* foseg */
	373	return 4;
	374	case IDX_FP_REGS + 14: /* fooff */
	375	return 4;
	376	case IDX_FP_REGS + 15: /* fop */
	377	return 4;
	378
	379	case IDX_MXCSR_REG:
4e47e39a	380	cpu_set_mxcsr(env, ldl_p(mem_buf));
f20f9df0	381	return 4;
7b0f97ba DG	382
	383	case IDX_CTL_CR0_REG:
	384	if (env->hflags & HF_CS64_MASK) {
	385	cpu_x86_update_cr0(env, ldq_p(mem_buf));
	386	return 8;
	387	}
	388	cpu_x86_update_cr0(env, ldl_p(mem_buf));
	389	return 4;
	390
	391	case IDX_CTL_CR2_REG:
	392	if (env->hflags & HF_CS64_MASK) {
	393	env->cr[2] = ldq_p(mem_buf);
	394	return 8;
	395	}
	396	env->cr[2] = ldl_p(mem_buf);
	397	return 4;
	398
	399	case IDX_CTL_CR3_REG:
	400	if (env->hflags & HF_CS64_MASK) {
	401	cpu_x86_update_cr3(env, ldq_p(mem_buf));
	402	return 8;
	403	}
	404	cpu_x86_update_cr3(env, ldl_p(mem_buf));
	405	return 4;
	406
	407	case IDX_CTL_CR4_REG:
	408	if (env->hflags & HF_CS64_MASK) {
	409	cpu_x86_update_cr4(env, ldq_p(mem_buf));
	410	return 8;
	411	}
	412	cpu_x86_update_cr4(env, ldl_p(mem_buf));
	413	return 4;
	414
	415	case IDX_CTL_CR8_REG:
	416	if (env->hflags & HF_CS64_MASK) {
	417	#ifdef CONFIG_SOFTMMU
	418	cpu_set_apic_tpr(cpu->apic_state, ldq_p(mem_buf));
	419	#endif
	420	return 8;
	421	}
	422	#ifdef CONFIG_SOFTMMU
	423	cpu_set_apic_tpr(cpu->apic_state, ldl_p(mem_buf));
	424	#endif
	425	return 4;
	426
	427	case IDX_CTL_EFER_REG:
	428	if (env->hflags & HF_CS64_MASK) {
	429	cpu_load_efer(env, ldq_p(mem_buf));
	430	return 8;
	431	}
	432	cpu_load_efer(env, ldl_p(mem_buf));
	433	return 4;
	434
f20f9df0 AF	435	}
	436	}
	437	/* Unrecognised register. */
	438	return 0;
	439	}