[mirror_qemu.git] / target / i386 / gdbstub.c

/*
 * x86 gdb server stub
 *
 * Copyright (c) 2003-2005 Fabrice Bellard
 * Copyright (c) 2013 SUSE LINUX Products GmbH
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2.1 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */
#include "qemu/osdep.h"
#include "cpu.h"
#include "exec/gdbstub.h"

#ifdef TARGET_X86_64
static const int gpr_map[16] = {
    R_EAX, R_EBX, R_ECX, R_EDX, R_ESI, R_EDI, R_EBP, R_ESP,
    8, 9, 10, 11, 12, 13, 14, 15
};
#else
#define gpr_map gpr_map32
#endif
static const int gpr_map32[8] = { 0, 1, 2, 3, 4, 5, 6, 7 };

/*
 * Keep these in sync with assignment to
 * gdb_num_core_regs in target/i386/cpu.c
 * and with the machine description
 */

/*
 * SEG: 6 segments, plus fs_base, gs_base, kernel_gs_base
 */

/*
 * general regs ----->  8 or 16
 */
#define IDX_NB_IP       1
#define IDX_NB_FLAGS    1
#define IDX_NB_SEG      (6 + 3)
#define IDX_NB_CTL      6
#define IDX_NB_FP       16
/*
 * fpu regs ----------> 8 or 16
 */
#define IDX_NB_MXCSR    1
/*
 *          total ----> 8+1+1+9+6+16+8+1=50 or 16+1+1+9+6+16+16+1=66
 */

#define IDX_IP_REG      CPU_NB_REGS
#define IDX_FLAGS_REG   (IDX_IP_REG + IDX_NB_IP)
#define IDX_SEG_REGS    (IDX_FLAGS_REG + IDX_NB_FLAGS)
#define IDX_CTL_REGS    (IDX_SEG_REGS + IDX_NB_SEG)
#define IDX_FP_REGS     (IDX_CTL_REGS + IDX_NB_CTL)
#define IDX_XMM_REGS    (IDX_FP_REGS + IDX_NB_FP)
#define IDX_MXCSR_REG   (IDX_XMM_REGS + CPU_NB_REGS)

#define IDX_CTL_CR0_REG     (IDX_CTL_REGS + 0)
#define IDX_CTL_CR2_REG     (IDX_CTL_REGS + 1)
#define IDX_CTL_CR3_REG     (IDX_CTL_REGS + 2)
#define IDX_CTL_CR4_REG     (IDX_CTL_REGS + 3)
#define IDX_CTL_CR8_REG     (IDX_CTL_REGS + 4)
#define IDX_CTL_EFER_REG    (IDX_CTL_REGS + 5)

#ifdef TARGET_X86_64
#define GDB_FORCE_64 1
#else
#define GDB_FORCE_64 0
#endif

static int gdb_read_reg_cs64(uint32_t hflags, GByteArray *buf, target_ulong val)
{
    if ((hflags & HF_CS64_MASK) || GDB_FORCE_64) {
        return gdb_get_reg64(buf, val);
    }
    return gdb_get_reg32(buf, val);
}

static int gdb_write_reg_cs64(uint32_t hflags, uint8_t *buf, target_ulong *val)
{
    if (hflags & HF_CS64_MASK) {
        *val = ldq_p(buf);
        return 8;
    }
    *val = ldl_p(buf);
    return 4;
}

int x86_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
{
    X86CPU *cpu = X86_CPU(cs);
    CPUX86State *env = &cpu->env;

    uint64_t tpr;

    /* N.B. GDB can't deal with changes in registers or sizes in the middle
       of a session. So if we're in 32-bit mode on a 64-bit cpu, still act
       as if we're on a 64-bit cpu. */

    if (n < CPU_NB_REGS) {
        if (TARGET_LONG_BITS == 64) {
            if (env->hflags & HF_CS64_MASK) {
                return gdb_get_reg64(mem_buf, env->regs[gpr_map[n]]);
            } else if (n < CPU_NB_REGS32) {
                return gdb_get_reg64(mem_buf,
                                     env->regs[gpr_map[n]] & 0xffffffffUL);
            } else {
                return gdb_get_regl(mem_buf, 0);
            }
        } else {
            return gdb_get_reg32(mem_buf, env->regs[gpr_map32[n]]);
        }
    } else if (n >= IDX_FP_REGS && n < IDX_FP_REGS + 8) {
        floatx80 *fp = (floatx80 *) &env->fpregs[n - IDX_FP_REGS];
        int len = gdb_get_reg64(mem_buf, cpu_to_le64(fp->low));
        len += gdb_get_reg16(mem_buf, cpu_to_le16(fp->high));
        return len;
    } else if (n >= IDX_XMM_REGS && n < IDX_XMM_REGS + CPU_NB_REGS) {
        n -= IDX_XMM_REGS;
        if (n < CPU_NB_REGS32 || TARGET_LONG_BITS == 64) {
            return gdb_get_reg128(mem_buf,
                                  env->xmm_regs[n].ZMM_Q(1),
                                  env->xmm_regs[n].ZMM_Q(0));
        }
    } else {
        switch (n) {
        case IDX_IP_REG:
            if (TARGET_LONG_BITS == 64) {
                if (env->hflags & HF_CS64_MASK) {
                    return gdb_get_reg64(mem_buf, env->eip);
                } else {
                    return gdb_get_reg64(mem_buf, env->eip & 0xffffffffUL);
                }
            } else {
                return gdb_get_reg32(mem_buf, env->eip);
            }
        case IDX_FLAGS_REG:
            return gdb_get_reg32(mem_buf, env->eflags);

        case IDX_SEG_REGS:
            return gdb_get_reg32(mem_buf, env->segs[R_CS].selector);
        case IDX_SEG_REGS + 1:
            return gdb_get_reg32(mem_buf, env->segs[R_SS].selector);
        case IDX_SEG_REGS + 2:
            return gdb_get_reg32(mem_buf, env->segs[R_DS].selector);
        case IDX_SEG_REGS + 3:
            return gdb_get_reg32(mem_buf, env->segs[R_ES].selector);
        case IDX_SEG_REGS + 4:
            return gdb_get_reg32(mem_buf, env->segs[R_FS].selector);
        case IDX_SEG_REGS + 5:
            return gdb_get_reg32(mem_buf, env->segs[R_GS].selector);
        case IDX_SEG_REGS + 6:
            return gdb_read_reg_cs64(env->hflags, mem_buf, env->segs[R_FS].base);
        case IDX_SEG_REGS + 7:
            return gdb_read_reg_cs64(env->hflags, mem_buf, env->segs[R_GS].base);

        case IDX_SEG_REGS + 8:
#ifdef TARGET_X86_64
            return gdb_read_reg_cs64(env->hflags, mem_buf, env->kernelgsbase);
#else
            return gdb_get_reg32(mem_buf, 0);
#endif

        case IDX_FP_REGS + 8:
            return gdb_get_reg32(mem_buf, env->fpuc);
        case IDX_FP_REGS + 9:
            return gdb_get_reg32(mem_buf, (env->fpus & ~0x3800) |
                                          (env->fpstt & 0x7) << 11);
        case IDX_FP_REGS + 10:
            return gdb_get_reg32(mem_buf, 0); /* ftag */
        case IDX_FP_REGS + 11:
            return gdb_get_reg32(mem_buf, 0); /* fiseg */
        case IDX_FP_REGS + 12:
            return gdb_get_reg32(mem_buf, 0); /* fioff */
        case IDX_FP_REGS + 13:
            return gdb_get_reg32(mem_buf, 0); /* foseg */
        case IDX_FP_REGS + 14:
            return gdb_get_reg32(mem_buf, 0); /* fooff */
        case IDX_FP_REGS + 15:
            return gdb_get_reg32(mem_buf, 0); /* fop */

        case IDX_MXCSR_REG:
            update_mxcsr_from_sse_status(env);
            return gdb_get_reg32(mem_buf, env->mxcsr);

        case IDX_CTL_CR0_REG:
            return gdb_read_reg_cs64(env->hflags, mem_buf, env->cr[0]);
        case IDX_CTL_CR2_REG:
            return gdb_read_reg_cs64(env->hflags, mem_buf, env->cr[2]);
        case IDX_CTL_CR3_REG:
            return gdb_read_reg_cs64(env->hflags, mem_buf, env->cr[3]);
        case IDX_CTL_CR4_REG:
            return gdb_read_reg_cs64(env->hflags, mem_buf, env->cr[4]);
        case IDX_CTL_CR8_REG:
#ifndef CONFIG_USER_ONLY
            tpr = cpu_get_apic_tpr(cpu->apic_state);
#else
            tpr = 0;
#endif
            return gdb_read_reg_cs64(env->hflags, mem_buf, tpr);

        case IDX_CTL_EFER_REG:
            return gdb_read_reg_cs64(env->hflags, mem_buf, env->efer);
        }
    }
    return 0;
}

static int x86_cpu_gdb_load_seg(X86CPU *cpu, X86Seg sreg, uint8_t *mem_buf)
{
    CPUX86State *env = &cpu->env;
    uint16_t selector = ldl_p(mem_buf);

    if (selector != env->segs[sreg].selector) {
#if defined(CONFIG_USER_ONLY)
        cpu_x86_load_seg(env, sreg, selector);
#else
        unsigned int limit, flags;
        target_ulong base;

        if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
            int dpl = (env->eflags & VM_MASK) ? 3 : 0;
            base = selector << 4;
            limit = 0xffff;
            flags = DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
                    DESC_A_MASK | (dpl << DESC_DPL_SHIFT);
        } else {
            if (!cpu_x86_get_descr_debug(env, selector, &base, &limit,
                                         &flags)) {
                return 4;
            }
        }
        cpu_x86_load_seg_cache(env, sreg, selector, base, limit, flags);
#endif
    }
    return 4;
}

int x86_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
{
    X86CPU *cpu = X86_CPU(cs);
    CPUX86State *env = &cpu->env;
    target_ulong tmp;
    int len;

    /* N.B. GDB can't deal with changes in registers or sizes in the middle
       of a session. So if we're in 32-bit mode on a 64-bit cpu, still act
       as if we're on a 64-bit cpu. */

    if (n < CPU_NB_REGS) {
        if (TARGET_LONG_BITS == 64) {
            if (env->hflags & HF_CS64_MASK) {
                env->regs[gpr_map[n]] = ldtul_p(mem_buf);
            } else if (n < CPU_NB_REGS32) {
                env->regs[gpr_map[n]] = ldtul_p(mem_buf) & 0xffffffffUL;
            }
            return sizeof(target_ulong);
        } else if (n < CPU_NB_REGS32) {
            n = gpr_map32[n];
            env->regs[n] &= ~0xffffffffUL;
            env->regs[n] |= (uint32_t)ldl_p(mem_buf);
            return 4;
        }
    } else if (n >= IDX_FP_REGS && n < IDX_FP_REGS + 8) {
        floatx80 *fp = (floatx80 *) &env->fpregs[n - IDX_FP_REGS];
        fp->low = le64_to_cpu(* (uint64_t *) mem_buf);
        fp->high = le16_to_cpu(* (uint16_t *) (mem_buf + 8));
        return 10;
    } else if (n >= IDX_XMM_REGS && n < IDX_XMM_REGS + CPU_NB_REGS) {
        n -= IDX_XMM_REGS;
        if (n < CPU_NB_REGS32 || TARGET_LONG_BITS == 64) {
            env->xmm_regs[n].ZMM_Q(0) = ldq_p(mem_buf);
            env->xmm_regs[n].ZMM_Q(1) = ldq_p(mem_buf + 8);
            return 16;
        }
    } else {
        switch (n) {
        case IDX_IP_REG:
            if (TARGET_LONG_BITS == 64) {
                if (env->hflags & HF_CS64_MASK) {
                    env->eip = ldq_p(mem_buf);
                } else {
                    env->eip = ldq_p(mem_buf) & 0xffffffffUL;
                }
                return 8;
            } else {
                env->eip &= ~0xffffffffUL;
                env->eip |= (uint32_t)ldl_p(mem_buf);
                return 4;
            }
        case IDX_FLAGS_REG:
            env->eflags = ldl_p(mem_buf);
            return 4;

        case IDX_SEG_REGS:
            return x86_cpu_gdb_load_seg(cpu, R_CS, mem_buf);
        case IDX_SEG_REGS + 1:
            return x86_cpu_gdb_load_seg(cpu, R_SS, mem_buf);
        case IDX_SEG_REGS + 2:
            return x86_cpu_gdb_load_seg(cpu, R_DS, mem_buf);
        case IDX_SEG_REGS + 3:
            return x86_cpu_gdb_load_seg(cpu, R_ES, mem_buf);
        case IDX_SEG_REGS + 4:
            return x86_cpu_gdb_load_seg(cpu, R_FS, mem_buf);
        case IDX_SEG_REGS + 5:
            return x86_cpu_gdb_load_seg(cpu, R_GS, mem_buf);
        case IDX_SEG_REGS + 6:
            return gdb_write_reg_cs64(env->hflags, mem_buf, &env->segs[R_FS].base);
        case IDX_SEG_REGS + 7:
            return gdb_write_reg_cs64(env->hflags, mem_buf, &env->segs[R_GS].base);
        case IDX_SEG_REGS + 8:
#ifdef TARGET_X86_64
            return gdb_write_reg_cs64(env->hflags, mem_buf, &env->kernelgsbase);
#endif
            return 4;

        case IDX_FP_REGS + 8:
            cpu_set_fpuc(env, ldl_p(mem_buf));
            return 4;
        case IDX_FP_REGS + 9:
            tmp = ldl_p(mem_buf);
            env->fpstt = (tmp >> 11) & 7;
            env->fpus = tmp & ~0x3800;
            return 4;
        case IDX_FP_REGS + 10: /* ftag */
            return 4;
        case IDX_FP_REGS + 11: /* fiseg */
            return 4;
        case IDX_FP_REGS + 12: /* fioff */
            return 4;
        case IDX_FP_REGS + 13: /* foseg */
            return 4;
        case IDX_FP_REGS + 14: /* fooff */
            return 4;
        case IDX_FP_REGS + 15: /* fop */
            return 4;

        case IDX_MXCSR_REG:
            cpu_set_mxcsr(env, ldl_p(mem_buf));
            return 4;

        case IDX_CTL_CR0_REG:
            len = gdb_write_reg_cs64(env->hflags, mem_buf, &tmp);
#ifndef CONFIG_USER_ONLY
            cpu_x86_update_cr0(env, tmp);
#endif
            return len;

        case IDX_CTL_CR2_REG:
            len = gdb_write_reg_cs64(env->hflags, mem_buf, &tmp);
#ifndef CONFIG_USER_ONLY
            env->cr[2] = tmp;
#endif
            return len;

        case IDX_CTL_CR3_REG:
            len = gdb_write_reg_cs64(env->hflags, mem_buf, &tmp);
#ifndef CONFIG_USER_ONLY
            cpu_x86_update_cr3(env, tmp);
#endif
            return len;

        case IDX_CTL_CR4_REG:
            len = gdb_write_reg_cs64(env->hflags, mem_buf, &tmp);
#ifndef CONFIG_USER_ONLY
            cpu_x86_update_cr4(env, tmp);
#endif
            return len;

        case IDX_CTL_CR8_REG:
            len = gdb_write_reg_cs64(env->hflags, mem_buf, &tmp);
#ifndef CONFIG_USER_ONLY
            cpu_set_apic_tpr(cpu->apic_state, tmp);
#endif
            return len;

        case IDX_CTL_EFER_REG:
            len = gdb_write_reg_cs64(env->hflags, mem_buf, &tmp);
#ifndef CONFIG_USER_ONLY
            cpu_load_efer(env, tmp);
#endif
            return len;
        }
    }
    /* Unrecognised register.  */
    return 0;
}
Commit	Line	Data
f20f9df0 AF	1	/*
	2	* x86 gdb server stub
	3	*
	4	* Copyright (c) 2003-2005 Fabrice Bellard
	5	* Copyright (c) 2013 SUSE LINUX Products GmbH
	6	*
	7	* This library is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU Lesser General Public
	9	* License as published by the Free Software Foundation; either
d9ff33ad	10	* version 2.1 of the License, or (at your option) any later version.
f20f9df0 AF	11	*
	12	* This library is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	* Lesser General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU Lesser General Public
	18	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
	19	*/
b6a0aa05	20	#include "qemu/osdep.h"
33c11879	21	#include "cpu.h"
5b50e790	22	#include "exec/gdbstub.h"
f20f9df0 AF	23
	24	#ifdef TARGET_X86_64
	25	static const int gpr_map[16] = {
	26	R_EAX, R_EBX, R_ECX, R_EDX, R_ESI, R_EDI, R_EBP, R_ESP,
	27	8, 9, 10, 11, 12, 13, 14, 15
	28	};
	29	#else
	30	#define gpr_map gpr_map32
	31	#endif
	32	static const int gpr_map32[8] = { 0, 1, 2, 3, 4, 5, 6, 7 };
	33
7b0f97ba DG	34	/*
	35	* Keep these in sync with assignment to
	36	* gdb_num_core_regs in target/i386/cpu.c
	37	* and with the machine description
	38	*/
	39
	40	/*
	41	* SEG: 6 segments, plus fs_base, gs_base, kernel_gs_base
	42	*/
	43
	44	/*
	45	* general regs -----> 8 or 16
	46	*/
	47	#define IDX_NB_IP 1
	48	#define IDX_NB_FLAGS 1
	49	#define IDX_NB_SEG (6 + 3)
	50	#define IDX_NB_CTL 6
	51	#define IDX_NB_FP 16
	52	/*
	53	* fpu regs ----------> 8 or 16
	54	*/
	55	#define IDX_NB_MXCSR 1
	56	/*
	57	* total ----> 8+1+1+9+6+16+8+1=50 or 16+1+1+9+6+16+16+1=66
	58	*/
	59
f20f9df0	60	#define IDX_IP_REG CPU_NB_REGS
7b0f97ba DG	61	#define IDX_FLAGS_REG (IDX_IP_REG + IDX_NB_IP)
	62	#define IDX_SEG_REGS (IDX_FLAGS_REG + IDX_NB_FLAGS)
	63	#define IDX_CTL_REGS (IDX_SEG_REGS + IDX_NB_SEG)
	64	#define IDX_FP_REGS (IDX_CTL_REGS + IDX_NB_CTL)
	65	#define IDX_XMM_REGS (IDX_FP_REGS + IDX_NB_FP)
f20f9df0 AF	66	#define IDX_MXCSR_REG (IDX_XMM_REGS + CPU_NB_REGS)
f20f9df0 AF	67
7b0f97ba DG	68	#define IDX_CTL_CR0_REG (IDX_CTL_REGS + 0)
	69	#define IDX_CTL_CR2_REG (IDX_CTL_REGS + 1)
	70	#define IDX_CTL_CR3_REG (IDX_CTL_REGS + 2)
	71	#define IDX_CTL_CR4_REG (IDX_CTL_REGS + 3)
	72	#define IDX_CTL_CR8_REG (IDX_CTL_REGS + 4)
	73	#define IDX_CTL_EFER_REG (IDX_CTL_REGS + 5)
	74
	75	#ifdef TARGET_X86_64
	76	#define GDB_FORCE_64 1
	77	#else
	78	#define GDB_FORCE_64 0
	79	#endif
	80
4d81e285 CF	81	static int gdb_read_reg_cs64(uint32_t hflags, GByteArray *buf, target_ulong val)
	82	{
	83	if ((hflags & HF_CS64_MASK) \|\| GDB_FORCE_64) {
	84	return gdb_get_reg64(buf, val);
	85	}
	86	return gdb_get_reg32(buf, val);
	87	}
	88
	89	static int gdb_write_reg_cs64(uint32_t hflags, uint8_t buf, target_ulong val)
	90	{
	91	if (hflags & HF_CS64_MASK) {
	92	*val = ldq_p(buf);
	93	return 8;
	94	}
	95	*val = ldl_p(buf);
	96	return 4;
	97	}
7b0f97ba	98
a010bdbe	99	int x86_cpu_gdb_read_register(CPUState cs, GByteArray mem_buf, int n)
f20f9df0	100	{
5b50e790 AF	101	X86CPU *cpu = X86_CPU(cs);
	102	CPUX86State *env = &cpu->env;
	103
7b0f97ba DG	104	uint64_t tpr;
7b0f97ba DG	105
e3592bc9 DE	106	/* N.B. GDB can't deal with changes in registers or sizes in the middle
	107	of a session. So if we're in 32-bit mode on a 64-bit cpu, still act
	108	as if we're on a 64-bit cpu. */
	109
f20f9df0	110	if (n < CPU_NB_REGS) {
e3592bc9 DE	111	if (TARGET_LONG_BITS == 64) {
	112	if (env->hflags & HF_CS64_MASK) {
	113	return gdb_get_reg64(mem_buf, env->regs[gpr_map[n]]);
	114	} else if (n < CPU_NB_REGS32) {
	115	return gdb_get_reg64(mem_buf,
	116	env->regs[gpr_map[n]] & 0xffffffffUL);
	117	} else {
b7b8756a	118	return gdb_get_regl(mem_buf, 0);
e3592bc9 DE	119	}
e3592bc9 DE	120	} else {
986a2998	121	return gdb_get_reg32(mem_buf, env->regs[gpr_map32[n]]);
f20f9df0 AF	122	}
f20f9df0 AF	123	} else if (n >= IDX_FP_REGS && n < IDX_FP_REGS + 8) {
b7b8756a AB	124	floatx80 fp = (floatx80 ) &env->fpregs[n - IDX_FP_REGS];
b7b8756a AB	125	int len = gdb_get_reg64(mem_buf, cpu_to_le64(fp->low));
bbc40fef	126	len += gdb_get_reg16(mem_buf, cpu_to_le16(fp->high));
b7b8756a	127	return len;
f20f9df0 AF	128	} else if (n >= IDX_XMM_REGS && n < IDX_XMM_REGS + CPU_NB_REGS) {
f20f9df0 AF	129	n -= IDX_XMM_REGS;
e3592bc9	130	if (n < CPU_NB_REGS32 \|\| TARGET_LONG_BITS == 64) {
b7b8756a	131	return gdb_get_reg128(mem_buf,
e618e1f9 AB	132	env->xmm_regs[n].ZMM_Q(1),
e618e1f9 AB	133	env->xmm_regs[n].ZMM_Q(0));
f20f9df0 AF	134	}
	135	} else {
	136	switch (n) {
	137	case IDX_IP_REG:
e3592bc9 DE	138	if (TARGET_LONG_BITS == 64) {
	139	if (env->hflags & HF_CS64_MASK) {
	140	return gdb_get_reg64(mem_buf, env->eip);
	141	} else {
	142	return gdb_get_reg64(mem_buf, env->eip & 0xffffffffUL);
	143	}
f20f9df0	144	} else {
986a2998	145	return gdb_get_reg32(mem_buf, env->eip);
f20f9df0 AF	146	}
f20f9df0 AF	147	case IDX_FLAGS_REG:
986a2998	148	return gdb_get_reg32(mem_buf, env->eflags);
f20f9df0 AF	149
f20f9df0 AF	150	case IDX_SEG_REGS:
986a2998	151	return gdb_get_reg32(mem_buf, env->segs[R_CS].selector);
f20f9df0	152	case IDX_SEG_REGS + 1:
986a2998	153	return gdb_get_reg32(mem_buf, env->segs[R_SS].selector);
f20f9df0	154	case IDX_SEG_REGS + 2:
986a2998	155	return gdb_get_reg32(mem_buf, env->segs[R_DS].selector);
f20f9df0	156	case IDX_SEG_REGS + 3:
986a2998	157	return gdb_get_reg32(mem_buf, env->segs[R_ES].selector);
f20f9df0	158	case IDX_SEG_REGS + 4:
986a2998	159	return gdb_get_reg32(mem_buf, env->segs[R_FS].selector);
f20f9df0	160	case IDX_SEG_REGS + 5:
986a2998	161	return gdb_get_reg32(mem_buf, env->segs[R_GS].selector);
7b0f97ba	162	case IDX_SEG_REGS + 6:
4d81e285	163	return gdb_read_reg_cs64(env->hflags, mem_buf, env->segs[R_FS].base);
7b0f97ba	164	case IDX_SEG_REGS + 7:
4d81e285	165	return gdb_read_reg_cs64(env->hflags, mem_buf, env->segs[R_GS].base);
7b0f97ba DG	166
	167	case IDX_SEG_REGS + 8:
	168	#ifdef TARGET_X86_64
4d81e285	169	return gdb_read_reg_cs64(env->hflags, mem_buf, env->kernelgsbase);
7b0f97ba DG	170	#else
	171	return gdb_get_reg32(mem_buf, 0);
	172	#endif
	173
f20f9df0	174	case IDX_FP_REGS + 8:
986a2998	175	return gdb_get_reg32(mem_buf, env->fpuc);
f20f9df0	176	case IDX_FP_REGS + 9:
986a2998 AF	177	return gdb_get_reg32(mem_buf, (env->fpus & ~0x3800) \|
986a2998 AF	178	(env->fpstt & 0x7) << 11);
f20f9df0	179	case IDX_FP_REGS + 10:
986a2998	180	return gdb_get_reg32(mem_buf, 0); /* ftag */
f20f9df0	181	case IDX_FP_REGS + 11:
986a2998	182	return gdb_get_reg32(mem_buf, 0); /* fiseg */
f20f9df0	183	case IDX_FP_REGS + 12:
986a2998	184	return gdb_get_reg32(mem_buf, 0); /* fioff */
f20f9df0	185	case IDX_FP_REGS + 13:
986a2998	186	return gdb_get_reg32(mem_buf, 0); /* foseg */
f20f9df0	187	case IDX_FP_REGS + 14:
986a2998	188	return gdb_get_reg32(mem_buf, 0); /* fooff */
f20f9df0	189	case IDX_FP_REGS + 15:
986a2998	190	return gdb_get_reg32(mem_buf, 0); /* fop */
f20f9df0 AF	191
f20f9df0 AF	192	case IDX_MXCSR_REG:
418b0f93	193	update_mxcsr_from_sse_status(env);
986a2998	194	return gdb_get_reg32(mem_buf, env->mxcsr);
7b0f97ba DG	195
7b0f97ba DG	196	case IDX_CTL_CR0_REG:
4d81e285	197	return gdb_read_reg_cs64(env->hflags, mem_buf, env->cr[0]);
7b0f97ba	198	case IDX_CTL_CR2_REG:
4d81e285	199	return gdb_read_reg_cs64(env->hflags, mem_buf, env->cr[2]);
7b0f97ba	200	case IDX_CTL_CR3_REG:
4d81e285	201	return gdb_read_reg_cs64(env->hflags, mem_buf, env->cr[3]);
7b0f97ba	202	case IDX_CTL_CR4_REG:
4d81e285	203	return gdb_read_reg_cs64(env->hflags, mem_buf, env->cr[4]);
7b0f97ba	204	case IDX_CTL_CR8_REG:
4d81e285	205	#ifndef CONFIG_USER_ONLY
7b0f97ba DG	206	tpr = cpu_get_apic_tpr(cpu->apic_state);
	207	#else
	208	tpr = 0;
	209	#endif
4d81e285	210	return gdb_read_reg_cs64(env->hflags, mem_buf, tpr);
7b0f97ba DG	211
7b0f97ba DG	212	case IDX_CTL_EFER_REG:
4d81e285	213	return gdb_read_reg_cs64(env->hflags, mem_buf, env->efer);
f20f9df0 AF	214	}
	215	}
	216	return 0;
	217	}
	218
c117e5b1	219	static int x86_cpu_gdb_load_seg(X86CPU cpu, X86Seg sreg, uint8_t mem_buf)
f20f9df0	220	{
5b50e790	221	CPUX86State *env = &cpu->env;
f20f9df0 AF	222	uint16_t selector = ldl_p(mem_buf);
	223
	224	if (selector != env->segs[sreg].selector) {
	225	#if defined(CONFIG_USER_ONLY)
	226	cpu_x86_load_seg(env, sreg, selector);
	227	#else
	228	unsigned int limit, flags;
	229	target_ulong base;
	230
	231	if (!(env->cr[0] & CR0_PE_MASK) \|\| (env->eflags & VM_MASK)) {
b98dbc90	232	int dpl = (env->eflags & VM_MASK) ? 3 : 0;
f20f9df0 AF	233	base = selector << 4;
f20f9df0 AF	234	limit = 0xffff;
b98dbc90 PB	235	flags = DESC_P_MASK \| DESC_S_MASK \| DESC_W_MASK \|
b98dbc90 PB	236	DESC_A_MASK \| (dpl << DESC_DPL_SHIFT);
f20f9df0 AF	237	} else {
	238	if (!cpu_x86_get_descr_debug(env, selector, &base, &limit,
	239	&flags)) {
	240	return 4;
	241	}
	242	}
	243	cpu_x86_load_seg_cache(env, sreg, selector, base, limit, flags);
	244	#endif
	245	}
	246	return 4;
	247	}
	248
5b50e790	249	int x86_cpu_gdb_write_register(CPUState cs, uint8_t mem_buf, int n)
f20f9df0	250	{
5b50e790 AF	251	X86CPU *cpu = X86_CPU(cs);
5b50e790 AF	252	CPUX86State *env = &cpu->env;
4d81e285 CF	253	target_ulong tmp;
4d81e285 CF	254	int len;
f20f9df0	255
e3592bc9 DE	256	/* N.B. GDB can't deal with changes in registers or sizes in the middle
	257	of a session. So if we're in 32-bit mode on a 64-bit cpu, still act
	258	as if we're on a 64-bit cpu. */
	259
f20f9df0	260	if (n < CPU_NB_REGS) {
e3592bc9 DE	261	if (TARGET_LONG_BITS == 64) {
	262	if (env->hflags & HF_CS64_MASK) {
	263	env->regs[gpr_map[n]] = ldtul_p(mem_buf);
	264	} else if (n < CPU_NB_REGS32) {
	265	env->regs[gpr_map[n]] = ldtul_p(mem_buf) & 0xffffffffUL;
	266	}
f20f9df0 AF	267	return sizeof(target_ulong);
	268	} else if (n < CPU_NB_REGS32) {
	269	n = gpr_map32[n];
	270	env->regs[n] &= ~0xffffffffUL;
	271	env->regs[n] \|= (uint32_t)ldl_p(mem_buf);
	272	return 4;
	273	}
	274	} else if (n >= IDX_FP_REGS && n < IDX_FP_REGS + 8) {
b7b8756a AB	275	floatx80 fp = (floatx80 ) &env->fpregs[n - IDX_FP_REGS];
	276	fp->low = le64_to_cpu(* (uint64_t *) mem_buf);
	277	fp->high = le16_to_cpu(* (uint16_t *) (mem_buf + 8));
f20f9df0 AF	278	return 10;
	279	} else if (n >= IDX_XMM_REGS && n < IDX_XMM_REGS + CPU_NB_REGS) {
	280	n -= IDX_XMM_REGS;
e3592bc9	281	if (n < CPU_NB_REGS32 \|\| TARGET_LONG_BITS == 64) {
19cbd87c EH	282	env->xmm_regs[n].ZMM_Q(0) = ldq_p(mem_buf);
19cbd87c EH	283	env->xmm_regs[n].ZMM_Q(1) = ldq_p(mem_buf + 8);
f20f9df0 AF	284	return 16;
	285	}
	286	} else {
	287	switch (n) {
	288	case IDX_IP_REG:
e3592bc9 DE	289	if (TARGET_LONG_BITS == 64) {
	290	if (env->hflags & HF_CS64_MASK) {
	291	env->eip = ldq_p(mem_buf);
	292	} else {
	293	env->eip = ldq_p(mem_buf) & 0xffffffffUL;
	294	}
f20f9df0 AF	295	return 8;
	296	} else {
	297	env->eip &= ~0xffffffffUL;
	298	env->eip \|= (uint32_t)ldl_p(mem_buf);
	299	return 4;
	300	}
	301	case IDX_FLAGS_REG:
	302	env->eflags = ldl_p(mem_buf);
	303	return 4;
	304
	305	case IDX_SEG_REGS:
5b50e790	306	return x86_cpu_gdb_load_seg(cpu, R_CS, mem_buf);
f20f9df0	307	case IDX_SEG_REGS + 1:
5b50e790	308	return x86_cpu_gdb_load_seg(cpu, R_SS, mem_buf);
f20f9df0	309	case IDX_SEG_REGS + 2:
5b50e790	310	return x86_cpu_gdb_load_seg(cpu, R_DS, mem_buf);
f20f9df0	311	case IDX_SEG_REGS + 3:
5b50e790	312	return x86_cpu_gdb_load_seg(cpu, R_ES, mem_buf);
f20f9df0	313	case IDX_SEG_REGS + 4:
5b50e790	314	return x86_cpu_gdb_load_seg(cpu, R_FS, mem_buf);
f20f9df0	315	case IDX_SEG_REGS + 5:
5b50e790	316	return x86_cpu_gdb_load_seg(cpu, R_GS, mem_buf);
7b0f97ba	317	case IDX_SEG_REGS + 6:
4d81e285	318	return gdb_write_reg_cs64(env->hflags, mem_buf, &env->segs[R_FS].base);
7b0f97ba	319	case IDX_SEG_REGS + 7:
4d81e285	320	return gdb_write_reg_cs64(env->hflags, mem_buf, &env->segs[R_GS].base);
7b0f97ba	321	case IDX_SEG_REGS + 8:
5a07192a	322	#ifdef TARGET_X86_64
4d81e285	323	return gdb_write_reg_cs64(env->hflags, mem_buf, &env->kernelgsbase);
7b0f97ba	324	#endif
5a07192a	325	return 4;
7b0f97ba	326
f20f9df0	327	case IDX_FP_REGS + 8:
5bde1407	328	cpu_set_fpuc(env, ldl_p(mem_buf));
f20f9df0 AF	329	return 4;
	330	case IDX_FP_REGS + 9:
	331	tmp = ldl_p(mem_buf);
	332	env->fpstt = (tmp >> 11) & 7;
	333	env->fpus = tmp & ~0x3800;
	334	return 4;
	335	case IDX_FP_REGS + 10: /* ftag */
	336	return 4;
	337	case IDX_FP_REGS + 11: /* fiseg */
	338	return 4;
	339	case IDX_FP_REGS + 12: /* fioff */
	340	return 4;
	341	case IDX_FP_REGS + 13: /* foseg */
	342	return 4;
	343	case IDX_FP_REGS + 14: /* fooff */
	344	return 4;
	345	case IDX_FP_REGS + 15: /* fop */
	346	return 4;
	347
	348	case IDX_MXCSR_REG:
4e47e39a	349	cpu_set_mxcsr(env, ldl_p(mem_buf));
f20f9df0	350	return 4;
7b0f97ba DG	351
7b0f97ba DG	352	case IDX_CTL_CR0_REG:
4d81e285	353	len = gdb_write_reg_cs64(env->hflags, mem_buf, &tmp);
1852f094	354	#ifndef CONFIG_USER_ONLY
4d81e285	355	cpu_x86_update_cr0(env, tmp);
1852f094	356	#endif
4d81e285	357	return len;
7b0f97ba DG	358
7b0f97ba DG	359	case IDX_CTL_CR2_REG:
4d81e285	360	len = gdb_write_reg_cs64(env->hflags, mem_buf, &tmp);
1852f094	361	#ifndef CONFIG_USER_ONLY
4d81e285	362	env->cr[2] = tmp;
1852f094	363	#endif
4d81e285	364	return len;
7b0f97ba DG	365
7b0f97ba DG	366	case IDX_CTL_CR3_REG:
4d81e285	367	len = gdb_write_reg_cs64(env->hflags, mem_buf, &tmp);
1852f094	368	#ifndef CONFIG_USER_ONLY
4d81e285	369	cpu_x86_update_cr3(env, tmp);
1852f094	370	#endif
4d81e285	371	return len;
7b0f97ba DG	372
7b0f97ba DG	373	case IDX_CTL_CR4_REG:
4d81e285	374	len = gdb_write_reg_cs64(env->hflags, mem_buf, &tmp);
1852f094	375	#ifndef CONFIG_USER_ONLY
4d81e285	376	cpu_x86_update_cr4(env, tmp);
1852f094	377	#endif
4d81e285	378	return len;
7b0f97ba DG	379
7b0f97ba DG	380	case IDX_CTL_CR8_REG:
4d81e285 CF	381	len = gdb_write_reg_cs64(env->hflags, mem_buf, &tmp);
	382	#ifndef CONFIG_USER_ONLY
	383	cpu_set_apic_tpr(cpu->apic_state, tmp);
7b0f97ba	384	#endif
4d81e285	385	return len;
7b0f97ba DG	386
7b0f97ba DG	387	case IDX_CTL_EFER_REG:
4d81e285	388	len = gdb_write_reg_cs64(env->hflags, mem_buf, &tmp);
1852f094	389	#ifndef CONFIG_USER_ONLY
4d81e285	390	cpu_load_efer(env, tmp);
1852f094	391	#endif
4d81e285	392	return len;
f20f9df0 AF	393	}
	394	}
	395	/* Unrecognised register. */
	396	return 0;
	397	}