]>
Commit | Line | Data |
---|---|---|
c97d6d2c SAGDR |
1 | /* |
2 | * Copyright (C) 2016 Veertu Inc, | |
3 | * Copyright (C) 2017 Google Inc, | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or | |
996feed4 SAGDR |
6 | * modify it under the terms of the GNU Lesser General Public |
7 | * License as published by the Free Software Foundation; either | |
8af82b8e | 8 | * version 2.1 of the License, or (at your option) any later version. |
c97d6d2c SAGDR |
9 | * |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
996feed4 SAGDR |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
13 | * Lesser General Public License for more details. | |
c97d6d2c | 14 | * |
996feed4 SAGDR |
15 | * You should have received a copy of the GNU Lesser General Public |
16 | * License along with this program; if not, see <http://www.gnu.org/licenses/>. | |
c97d6d2c SAGDR |
17 | */ |
18 | ||
19 | ///////////////////////////////////////////////////////////////////////// | |
20 | // | |
21 | // Copyright (C) 2001-2012 The Bochs Project | |
22 | // | |
23 | // This library is free software; you can redistribute it and/or | |
24 | // modify it under the terms of the GNU Lesser General Public | |
25 | // License as published by the Free Software Foundation; either | |
8af82b8e | 26 | // version 2.1 of the License, or (at your option) any later version. |
c97d6d2c SAGDR |
27 | // |
28 | // This library is distributed in the hope that it will be useful, | |
29 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
30 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
31 | // Lesser General Public License for more details. | |
32 | // | |
33 | // You should have received a copy of the GNU Lesser General Public | |
34 | // License along with this library; if not, write to the Free Software | |
35 | // Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA | |
36 | ///////////////////////////////////////////////////////////////////////// | |
37 | ||
38 | #include "qemu/osdep.h" | |
895f9fdf | 39 | #include "panic.h" |
c97d6d2c SAGDR |
40 | #include "x86_decode.h" |
41 | #include "x86.h" | |
42 | #include "x86_emu.h" | |
43 | #include "x86_mmu.h" | |
44 | #include "x86_flags.h" | |
45 | #include "vmcs.h" | |
46 | #include "vmx.h" | |
47 | ||
48 | void hvf_handle_io(struct CPUState *cpu, uint16_t port, void *data, | |
49 | int direction, int size, uint32_t count); | |
50 | ||
e8a63257 | 51 | #define EXEC_2OP_FLAGS_CMD(env, decode, cmd, FLAGS_FUNC, save_res) \ |
c97d6d2c SAGDR |
52 | { \ |
53 | fetch_operands(env, decode, 2, true, true, false); \ | |
54 | switch (decode->operand_size) { \ | |
55 | case 1: \ | |
56 | { \ | |
57 | uint8_t v1 = (uint8_t)decode->op[0].val; \ | |
58 | uint8_t v2 = (uint8_t)decode->op[1].val; \ | |
59 | uint8_t diff = v1 cmd v2; \ | |
60 | if (save_res) { \ | |
61 | write_val_ext(env, decode->op[0].ptr, diff, 1); \ | |
62 | } \ | |
e8a63257 | 63 | FLAGS_FUNC##8(env, v1, v2, diff); \ |
c97d6d2c SAGDR |
64 | break; \ |
65 | } \ | |
66 | case 2: \ | |
67 | { \ | |
68 | uint16_t v1 = (uint16_t)decode->op[0].val; \ | |
69 | uint16_t v2 = (uint16_t)decode->op[1].val; \ | |
70 | uint16_t diff = v1 cmd v2; \ | |
71 | if (save_res) { \ | |
72 | write_val_ext(env, decode->op[0].ptr, diff, 2); \ | |
73 | } \ | |
e8a63257 | 74 | FLAGS_FUNC##16(env, v1, v2, diff); \ |
c97d6d2c SAGDR |
75 | break; \ |
76 | } \ | |
77 | case 4: \ | |
78 | { \ | |
79 | uint32_t v1 = (uint32_t)decode->op[0].val; \ | |
80 | uint32_t v2 = (uint32_t)decode->op[1].val; \ | |
81 | uint32_t diff = v1 cmd v2; \ | |
82 | if (save_res) { \ | |
83 | write_val_ext(env, decode->op[0].ptr, diff, 4); \ | |
84 | } \ | |
e8a63257 | 85 | FLAGS_FUNC##32(env, v1, v2, diff); \ |
c97d6d2c SAGDR |
86 | break; \ |
87 | } \ | |
88 | default: \ | |
89 | VM_PANIC("bad size\n"); \ | |
90 | } \ | |
91 | } \ | |
92 | ||
ff2de166 | 93 | target_ulong read_reg(CPUX86State *env, int reg, int size) |
c97d6d2c SAGDR |
94 | { |
95 | switch (size) { | |
96 | case 1: | |
167c6aef | 97 | return x86_reg(env, reg)->lx; |
c97d6d2c | 98 | case 2: |
167c6aef | 99 | return x86_reg(env, reg)->rx; |
c97d6d2c | 100 | case 4: |
167c6aef | 101 | return x86_reg(env, reg)->erx; |
c97d6d2c | 102 | case 8: |
167c6aef | 103 | return x86_reg(env, reg)->rrx; |
c97d6d2c | 104 | default: |
e62963bf | 105 | abort(); |
c97d6d2c SAGDR |
106 | } |
107 | return 0; | |
108 | } | |
109 | ||
ff2de166 | 110 | void write_reg(CPUX86State *env, int reg, target_ulong val, int size) |
c97d6d2c SAGDR |
111 | { |
112 | switch (size) { | |
113 | case 1: | |
167c6aef | 114 | x86_reg(env, reg)->lx = val; |
c97d6d2c SAGDR |
115 | break; |
116 | case 2: | |
167c6aef | 117 | x86_reg(env, reg)->rx = val; |
c97d6d2c SAGDR |
118 | break; |
119 | case 4: | |
167c6aef | 120 | x86_reg(env, reg)->rrx = (uint32_t)val; |
c97d6d2c SAGDR |
121 | break; |
122 | case 8: | |
167c6aef | 123 | x86_reg(env, reg)->rrx = val; |
c97d6d2c SAGDR |
124 | break; |
125 | default: | |
e62963bf | 126 | abort(); |
c97d6d2c SAGDR |
127 | } |
128 | } | |
129 | ||
ff2de166 | 130 | target_ulong read_val_from_reg(target_ulong reg_ptr, int size) |
c97d6d2c | 131 | { |
ff2de166 | 132 | target_ulong val; |
c97d6d2c SAGDR |
133 | |
134 | switch (size) { | |
135 | case 1: | |
136 | val = *(uint8_t *)reg_ptr; | |
137 | break; | |
138 | case 2: | |
139 | val = *(uint16_t *)reg_ptr; | |
140 | break; | |
141 | case 4: | |
142 | val = *(uint32_t *)reg_ptr; | |
143 | break; | |
144 | case 8: | |
145 | val = *(uint64_t *)reg_ptr; | |
146 | break; | |
147 | default: | |
e62963bf | 148 | abort(); |
c97d6d2c SAGDR |
149 | } |
150 | return val; | |
151 | } | |
152 | ||
ff2de166 | 153 | void write_val_to_reg(target_ulong reg_ptr, target_ulong val, int size) |
c97d6d2c SAGDR |
154 | { |
155 | switch (size) { | |
156 | case 1: | |
157 | *(uint8_t *)reg_ptr = val; | |
158 | break; | |
159 | case 2: | |
160 | *(uint16_t *)reg_ptr = val; | |
161 | break; | |
162 | case 4: | |
163 | *(uint64_t *)reg_ptr = (uint32_t)val; | |
164 | break; | |
165 | case 8: | |
166 | *(uint64_t *)reg_ptr = val; | |
167 | break; | |
168 | default: | |
e62963bf | 169 | abort(); |
c97d6d2c SAGDR |
170 | } |
171 | } | |
172 | ||
36861198 | 173 | static bool is_host_reg(CPUX86State *env, target_ulong ptr) |
c97d6d2c | 174 | { |
167c6aef | 175 | return (ptr - (target_ulong)&env->regs[0]) < sizeof(env->regs); |
c97d6d2c SAGDR |
176 | } |
177 | ||
36861198 | 178 | void write_val_ext(CPUX86State *env, target_ulong ptr, target_ulong val, int size) |
c97d6d2c SAGDR |
179 | { |
180 | if (is_host_reg(env, ptr)) { | |
181 | write_val_to_reg(ptr, val, size); | |
182 | return; | |
183 | } | |
29a0af61 | 184 | vmx_write_mem(env_cpu(env), ptr, &val, size); |
c97d6d2c SAGDR |
185 | } |
186 | ||
36861198 | 187 | uint8_t *read_mmio(CPUX86State *env, target_ulong ptr, int bytes) |
c97d6d2c | 188 | { |
fe76b09c RB |
189 | vmx_read_mem(env_cpu(env), env->hvf_mmio_buf, ptr, bytes); |
190 | return env->hvf_mmio_buf; | |
c97d6d2c SAGDR |
191 | } |
192 | ||
193 | ||
36861198 | 194 | target_ulong read_val_ext(CPUX86State *env, target_ulong ptr, int size) |
c97d6d2c | 195 | { |
ff2de166 | 196 | target_ulong val; |
c97d6d2c SAGDR |
197 | uint8_t *mmio_ptr; |
198 | ||
199 | if (is_host_reg(env, ptr)) { | |
200 | return read_val_from_reg(ptr, size); | |
201 | } | |
202 | ||
203 | mmio_ptr = read_mmio(env, ptr, size); | |
204 | switch (size) { | |
205 | case 1: | |
206 | val = *(uint8_t *)mmio_ptr; | |
207 | break; | |
208 | case 2: | |
209 | val = *(uint16_t *)mmio_ptr; | |
210 | break; | |
211 | case 4: | |
212 | val = *(uint32_t *)mmio_ptr; | |
213 | break; | |
214 | case 8: | |
215 | val = *(uint64_t *)mmio_ptr; | |
216 | break; | |
217 | default: | |
218 | VM_PANIC("bad size\n"); | |
219 | break; | |
220 | } | |
221 | return val; | |
222 | } | |
223 | ||
36861198 | 224 | static void fetch_operands(CPUX86State *env, struct x86_decode *decode, |
c97d6d2c SAGDR |
225 | int n, bool val_op0, bool val_op1, bool val_op2) |
226 | { | |
227 | int i; | |
228 | bool calc_val[3] = {val_op0, val_op1, val_op2}; | |
229 | ||
230 | for (i = 0; i < n; i++) { | |
231 | switch (decode->op[i].type) { | |
232 | case X86_VAR_IMMEDIATE: | |
233 | break; | |
234 | case X86_VAR_REG: | |
235 | VM_PANIC_ON(!decode->op[i].ptr); | |
236 | if (calc_val[i]) { | |
237 | decode->op[i].val = read_val_from_reg(decode->op[i].ptr, | |
238 | decode->operand_size); | |
239 | } | |
240 | break; | |
241 | case X86_VAR_RM: | |
242 | calc_modrm_operand(env, decode, &decode->op[i]); | |
243 | if (calc_val[i]) { | |
244 | decode->op[i].val = read_val_ext(env, decode->op[i].ptr, | |
245 | decode->operand_size); | |
246 | } | |
247 | break; | |
248 | case X86_VAR_OFFSET: | |
249 | decode->op[i].ptr = decode_linear_addr(env, decode, | |
250 | decode->op[i].ptr, | |
6701d81d | 251 | R_DS); |
c97d6d2c SAGDR |
252 | if (calc_val[i]) { |
253 | decode->op[i].val = read_val_ext(env, decode->op[i].ptr, | |
254 | decode->operand_size); | |
255 | } | |
256 | break; | |
257 | default: | |
258 | break; | |
259 | } | |
260 | } | |
261 | } | |
262 | ||
36861198 | 263 | static void exec_mov(CPUX86State *env, struct x86_decode *decode) |
c97d6d2c SAGDR |
264 | { |
265 | fetch_operands(env, decode, 2, false, true, false); | |
266 | write_val_ext(env, decode->op[0].ptr, decode->op[1].val, | |
267 | decode->operand_size); | |
268 | ||
5d32173f | 269 | env->eip += decode->len; |
c97d6d2c SAGDR |
270 | } |
271 | ||
36861198 | 272 | static void exec_add(CPUX86State *env, struct x86_decode *decode) |
c97d6d2c | 273 | { |
e8a63257 | 274 | EXEC_2OP_FLAGS_CMD(env, decode, +, SET_FLAGS_OSZAPC_ADD, true); |
5d32173f | 275 | env->eip += decode->len; |
c97d6d2c SAGDR |
276 | } |
277 | ||
36861198 | 278 | static void exec_or(CPUX86State *env, struct x86_decode *decode) |
c97d6d2c | 279 | { |
e8a63257 | 280 | EXEC_2OP_FLAGS_CMD(env, decode, |, SET_FLAGS_OSZAPC_LOGIC, true); |
5d32173f | 281 | env->eip += decode->len; |
c97d6d2c SAGDR |
282 | } |
283 | ||
36861198 | 284 | static void exec_adc(CPUX86State *env, struct x86_decode *decode) |
c97d6d2c | 285 | { |
e8a63257 | 286 | EXEC_2OP_FLAGS_CMD(env, decode, +get_CF(env)+, SET_FLAGS_OSZAPC_ADD, true); |
5d32173f | 287 | env->eip += decode->len; |
c97d6d2c SAGDR |
288 | } |
289 | ||
36861198 | 290 | static void exec_sbb(CPUX86State *env, struct x86_decode *decode) |
c97d6d2c | 291 | { |
e8a63257 | 292 | EXEC_2OP_FLAGS_CMD(env, decode, -get_CF(env)-, SET_FLAGS_OSZAPC_SUB, true); |
5d32173f | 293 | env->eip += decode->len; |
c97d6d2c SAGDR |
294 | } |
295 | ||
36861198 | 296 | static void exec_and(CPUX86State *env, struct x86_decode *decode) |
c97d6d2c | 297 | { |
e8a63257 | 298 | EXEC_2OP_FLAGS_CMD(env, decode, &, SET_FLAGS_OSZAPC_LOGIC, true); |
5d32173f | 299 | env->eip += decode->len; |
c97d6d2c SAGDR |
300 | } |
301 | ||
36861198 | 302 | static void exec_sub(CPUX86State *env, struct x86_decode *decode) |
c97d6d2c | 303 | { |
e8a63257 | 304 | EXEC_2OP_FLAGS_CMD(env, decode, -, SET_FLAGS_OSZAPC_SUB, true); |
5d32173f | 305 | env->eip += decode->len; |
c97d6d2c SAGDR |
306 | } |
307 | ||
36861198 | 308 | static void exec_xor(CPUX86State *env, struct x86_decode *decode) |
c97d6d2c | 309 | { |
e8a63257 | 310 | EXEC_2OP_FLAGS_CMD(env, decode, ^, SET_FLAGS_OSZAPC_LOGIC, true); |
5d32173f | 311 | env->eip += decode->len; |
c97d6d2c SAGDR |
312 | } |
313 | ||
36861198 | 314 | static void exec_neg(CPUX86State *env, struct x86_decode *decode) |
c97d6d2c | 315 | { |
e8a63257 | 316 | /*EXEC_2OP_FLAGS_CMD(env, decode, -, SET_FLAGS_OSZAPC_SUB, false);*/ |
c97d6d2c SAGDR |
317 | int32_t val; |
318 | fetch_operands(env, decode, 2, true, true, false); | |
319 | ||
320 | val = 0 - sign(decode->op[1].val, decode->operand_size); | |
321 | write_val_ext(env, decode->op[1].ptr, val, decode->operand_size); | |
322 | ||
323 | if (4 == decode->operand_size) { | |
e8a63257 | 324 | SET_FLAGS_OSZAPC_SUB32(env, 0, 0 - val, val); |
c97d6d2c | 325 | } else if (2 == decode->operand_size) { |
e8a63257 | 326 | SET_FLAGS_OSZAPC_SUB16(env, 0, 0 - val, val); |
c97d6d2c | 327 | } else if (1 == decode->operand_size) { |
e8a63257 | 328 | SET_FLAGS_OSZAPC_SUB8(env, 0, 0 - val, val); |
c97d6d2c SAGDR |
329 | } else { |
330 | VM_PANIC("bad op size\n"); | |
331 | } | |
332 | ||
333 | /*lflags_to_rflags(env);*/ | |
5d32173f | 334 | env->eip += decode->len; |
c97d6d2c SAGDR |
335 | } |
336 | ||
36861198 | 337 | static void exec_cmp(CPUX86State *env, struct x86_decode *decode) |
c97d6d2c | 338 | { |
e8a63257 | 339 | EXEC_2OP_FLAGS_CMD(env, decode, -, SET_FLAGS_OSZAPC_SUB, false); |
5d32173f | 340 | env->eip += decode->len; |
c97d6d2c SAGDR |
341 | } |
342 | ||
36861198 | 343 | static void exec_inc(CPUX86State *env, struct x86_decode *decode) |
c97d6d2c SAGDR |
344 | { |
345 | decode->op[1].type = X86_VAR_IMMEDIATE; | |
346 | decode->op[1].val = 0; | |
347 | ||
e8a63257 | 348 | EXEC_2OP_FLAGS_CMD(env, decode, +1+, SET_FLAGS_OSZAP_ADD, true); |
c97d6d2c | 349 | |
5d32173f | 350 | env->eip += decode->len; |
c97d6d2c SAGDR |
351 | } |
352 | ||
36861198 | 353 | static void exec_dec(CPUX86State *env, struct x86_decode *decode) |
c97d6d2c SAGDR |
354 | { |
355 | decode->op[1].type = X86_VAR_IMMEDIATE; | |
356 | decode->op[1].val = 0; | |
357 | ||
e8a63257 | 358 | EXEC_2OP_FLAGS_CMD(env, decode, -1-, SET_FLAGS_OSZAP_SUB, true); |
5d32173f | 359 | env->eip += decode->len; |
c97d6d2c SAGDR |
360 | } |
361 | ||
36861198 | 362 | static void exec_tst(CPUX86State *env, struct x86_decode *decode) |
c97d6d2c | 363 | { |
e8a63257 | 364 | EXEC_2OP_FLAGS_CMD(env, decode, &, SET_FLAGS_OSZAPC_LOGIC, false); |
5d32173f | 365 | env->eip += decode->len; |
c97d6d2c SAGDR |
366 | } |
367 | ||
36861198 | 368 | static void exec_not(CPUX86State *env, struct x86_decode *decode) |
c97d6d2c SAGDR |
369 | { |
370 | fetch_operands(env, decode, 1, true, false, false); | |
371 | ||
372 | write_val_ext(env, decode->op[0].ptr, ~decode->op[0].val, | |
373 | decode->operand_size); | |
5d32173f | 374 | env->eip += decode->len; |
c97d6d2c SAGDR |
375 | } |
376 | ||
36861198 | 377 | void exec_movzx(CPUX86State *env, struct x86_decode *decode) |
c97d6d2c SAGDR |
378 | { |
379 | int src_op_size; | |
380 | int op_size = decode->operand_size; | |
381 | ||
382 | fetch_operands(env, decode, 1, false, false, false); | |
383 | ||
384 | if (0xb6 == decode->opcode[1]) { | |
385 | src_op_size = 1; | |
386 | } else { | |
387 | src_op_size = 2; | |
388 | } | |
389 | decode->operand_size = src_op_size; | |
390 | calc_modrm_operand(env, decode, &decode->op[1]); | |
391 | decode->op[1].val = read_val_ext(env, decode->op[1].ptr, src_op_size); | |
392 | write_val_ext(env, decode->op[0].ptr, decode->op[1].val, op_size); | |
393 | ||
5d32173f | 394 | env->eip += decode->len; |
c97d6d2c SAGDR |
395 | } |
396 | ||
36861198 | 397 | static void exec_out(CPUX86State *env, struct x86_decode *decode) |
c97d6d2c SAGDR |
398 | { |
399 | switch (decode->opcode[0]) { | |
400 | case 0xe6: | |
29a0af61 | 401 | hvf_handle_io(env_cpu(env), decode->op[0].val, &AL(env), 1, 1, 1); |
c97d6d2c SAGDR |
402 | break; |
403 | case 0xe7: | |
29a0af61 | 404 | hvf_handle_io(env_cpu(env), decode->op[0].val, &RAX(env), 1, |
c97d6d2c SAGDR |
405 | decode->operand_size, 1); |
406 | break; | |
407 | case 0xee: | |
29a0af61 | 408 | hvf_handle_io(env_cpu(env), DX(env), &AL(env), 1, 1, 1); |
c97d6d2c SAGDR |
409 | break; |
410 | case 0xef: | |
29a0af61 RH |
411 | hvf_handle_io(env_cpu(env), DX(env), &RAX(env), 1, |
412 | decode->operand_size, 1); | |
c97d6d2c SAGDR |
413 | break; |
414 | default: | |
415 | VM_PANIC("Bad out opcode\n"); | |
416 | break; | |
417 | } | |
5d32173f | 418 | env->eip += decode->len; |
c97d6d2c SAGDR |
419 | } |
420 | ||
36861198 | 421 | static void exec_in(CPUX86State *env, struct x86_decode *decode) |
c97d6d2c | 422 | { |
ff2de166 | 423 | target_ulong val = 0; |
c97d6d2c SAGDR |
424 | switch (decode->opcode[0]) { |
425 | case 0xe4: | |
29a0af61 | 426 | hvf_handle_io(env_cpu(env), decode->op[0].val, &AL(env), 0, 1, 1); |
c97d6d2c SAGDR |
427 | break; |
428 | case 0xe5: | |
29a0af61 RH |
429 | hvf_handle_io(env_cpu(env), decode->op[0].val, &val, 0, |
430 | decode->operand_size, 1); | |
c97d6d2c SAGDR |
431 | if (decode->operand_size == 2) { |
432 | AX(env) = val; | |
433 | } else { | |
434 | RAX(env) = (uint32_t)val; | |
435 | } | |
436 | break; | |
437 | case 0xec: | |
29a0af61 | 438 | hvf_handle_io(env_cpu(env), DX(env), &AL(env), 0, 1, 1); |
c97d6d2c SAGDR |
439 | break; |
440 | case 0xed: | |
29a0af61 | 441 | hvf_handle_io(env_cpu(env), DX(env), &val, 0, decode->operand_size, 1); |
c97d6d2c SAGDR |
442 | if (decode->operand_size == 2) { |
443 | AX(env) = val; | |
444 | } else { | |
445 | RAX(env) = (uint32_t)val; | |
446 | } | |
447 | ||
448 | break; | |
449 | default: | |
450 | VM_PANIC("Bad in opcode\n"); | |
451 | break; | |
452 | } | |
453 | ||
5d32173f | 454 | env->eip += decode->len; |
c97d6d2c SAGDR |
455 | } |
456 | ||
36861198 | 457 | static inline void string_increment_reg(CPUX86State *env, int reg, |
c97d6d2c SAGDR |
458 | struct x86_decode *decode) |
459 | { | |
ff2de166 | 460 | target_ulong val = read_reg(env, reg, decode->addressing_size); |
967f4da2 | 461 | if (env->eflags & DF_MASK) { |
c97d6d2c SAGDR |
462 | val -= decode->operand_size; |
463 | } else { | |
464 | val += decode->operand_size; | |
465 | } | |
466 | write_reg(env, reg, val, decode->addressing_size); | |
467 | } | |
468 | ||
36861198 PMD |
469 | static inline void string_rep(CPUX86State *env, struct x86_decode *decode, |
470 | void (*func)(CPUX86State *env, | |
c97d6d2c SAGDR |
471 | struct x86_decode *ins), int rep) |
472 | { | |
ff2de166 | 473 | target_ulong rcx = read_reg(env, R_ECX, decode->addressing_size); |
c97d6d2c SAGDR |
474 | while (rcx--) { |
475 | func(env, decode); | |
6701d81d | 476 | write_reg(env, R_ECX, rcx, decode->addressing_size); |
c97d6d2c SAGDR |
477 | if ((PREFIX_REP == rep) && !get_ZF(env)) { |
478 | break; | |
479 | } | |
480 | if ((PREFIX_REPN == rep) && get_ZF(env)) { | |
481 | break; | |
482 | } | |
483 | } | |
484 | } | |
485 | ||
36861198 | 486 | static void exec_ins_single(CPUX86State *env, struct x86_decode *decode) |
c97d6d2c | 487 | { |
29a0af61 RH |
488 | target_ulong addr = linear_addr_size(env_cpu(env), RDI(env), |
489 | decode->addressing_size, R_ES); | |
c97d6d2c | 490 | |
fe76b09c | 491 | hvf_handle_io(env_cpu(env), DX(env), env->hvf_mmio_buf, 0, |
c97d6d2c | 492 | decode->operand_size, 1); |
fe76b09c | 493 | vmx_write_mem(env_cpu(env), addr, env->hvf_mmio_buf, |
29a0af61 | 494 | decode->operand_size); |
c97d6d2c | 495 | |
6701d81d | 496 | string_increment_reg(env, R_EDI, decode); |
c97d6d2c SAGDR |
497 | } |
498 | ||
36861198 | 499 | static void exec_ins(CPUX86State *env, struct x86_decode *decode) |
c97d6d2c SAGDR |
500 | { |
501 | if (decode->rep) { | |
502 | string_rep(env, decode, exec_ins_single, 0); | |
503 | } else { | |
504 | exec_ins_single(env, decode); | |
505 | } | |
506 | ||
5d32173f | 507 | env->eip += decode->len; |
c97d6d2c SAGDR |
508 | } |
509 | ||
36861198 | 510 | static void exec_outs_single(CPUX86State *env, struct x86_decode *decode) |
c97d6d2c | 511 | { |
ff2de166 | 512 | target_ulong addr = decode_linear_addr(env, decode, RSI(env), R_DS); |
c97d6d2c | 513 | |
fe76b09c | 514 | vmx_read_mem(env_cpu(env), env->hvf_mmio_buf, addr, |
29a0af61 | 515 | decode->operand_size); |
fe76b09c | 516 | hvf_handle_io(env_cpu(env), DX(env), env->hvf_mmio_buf, 1, |
c97d6d2c SAGDR |
517 | decode->operand_size, 1); |
518 | ||
6701d81d | 519 | string_increment_reg(env, R_ESI, decode); |
c97d6d2c SAGDR |
520 | } |
521 | ||
36861198 | 522 | static void exec_outs(CPUX86State *env, struct x86_decode *decode) |
c97d6d2c SAGDR |
523 | { |
524 | if (decode->rep) { | |
525 | string_rep(env, decode, exec_outs_single, 0); | |
526 | } else { | |
527 | exec_outs_single(env, decode); | |
528 | } | |
529 | ||
5d32173f | 530 | env->eip += decode->len; |
c97d6d2c SAGDR |
531 | } |
532 | ||
36861198 | 533 | static void exec_movs_single(CPUX86State *env, struct x86_decode *decode) |
c97d6d2c | 534 | { |
ff2de166 PB |
535 | target_ulong src_addr; |
536 | target_ulong dst_addr; | |
537 | target_ulong val; | |
c97d6d2c | 538 | |
6701d81d | 539 | src_addr = decode_linear_addr(env, decode, RSI(env), R_DS); |
29a0af61 RH |
540 | dst_addr = linear_addr_size(env_cpu(env), RDI(env), |
541 | decode->addressing_size, R_ES); | |
c97d6d2c SAGDR |
542 | |
543 | val = read_val_ext(env, src_addr, decode->operand_size); | |
544 | write_val_ext(env, dst_addr, val, decode->operand_size); | |
545 | ||
6701d81d PB |
546 | string_increment_reg(env, R_ESI, decode); |
547 | string_increment_reg(env, R_EDI, decode); | |
c97d6d2c SAGDR |
548 | } |
549 | ||
36861198 | 550 | static void exec_movs(CPUX86State *env, struct x86_decode *decode) |
c97d6d2c SAGDR |
551 | { |
552 | if (decode->rep) { | |
553 | string_rep(env, decode, exec_movs_single, 0); | |
554 | } else { | |
555 | exec_movs_single(env, decode); | |
556 | } | |
557 | ||
5d32173f | 558 | env->eip += decode->len; |
c97d6d2c SAGDR |
559 | } |
560 | ||
36861198 | 561 | static void exec_cmps_single(CPUX86State *env, struct x86_decode *decode) |
c97d6d2c | 562 | { |
ff2de166 PB |
563 | target_ulong src_addr; |
564 | target_ulong dst_addr; | |
c97d6d2c | 565 | |
6701d81d | 566 | src_addr = decode_linear_addr(env, decode, RSI(env), R_DS); |
29a0af61 RH |
567 | dst_addr = linear_addr_size(env_cpu(env), RDI(env), |
568 | decode->addressing_size, R_ES); | |
c97d6d2c SAGDR |
569 | |
570 | decode->op[0].type = X86_VAR_IMMEDIATE; | |
571 | decode->op[0].val = read_val_ext(env, src_addr, decode->operand_size); | |
572 | decode->op[1].type = X86_VAR_IMMEDIATE; | |
573 | decode->op[1].val = read_val_ext(env, dst_addr, decode->operand_size); | |
574 | ||
e8a63257 | 575 | EXEC_2OP_FLAGS_CMD(env, decode, -, SET_FLAGS_OSZAPC_SUB, false); |
c97d6d2c | 576 | |
6701d81d PB |
577 | string_increment_reg(env, R_ESI, decode); |
578 | string_increment_reg(env, R_EDI, decode); | |
c97d6d2c SAGDR |
579 | } |
580 | ||
36861198 | 581 | static void exec_cmps(CPUX86State *env, struct x86_decode *decode) |
c97d6d2c SAGDR |
582 | { |
583 | if (decode->rep) { | |
584 | string_rep(env, decode, exec_cmps_single, decode->rep); | |
585 | } else { | |
586 | exec_cmps_single(env, decode); | |
587 | } | |
5d32173f | 588 | env->eip += decode->len; |
c97d6d2c SAGDR |
589 | } |
590 | ||
591 | ||
36861198 | 592 | static void exec_stos_single(CPUX86State *env, struct x86_decode *decode) |
c97d6d2c | 593 | { |
ff2de166 PB |
594 | target_ulong addr; |
595 | target_ulong val; | |
c97d6d2c | 596 | |
29a0af61 RH |
597 | addr = linear_addr_size(env_cpu(env), RDI(env), |
598 | decode->addressing_size, R_ES); | |
6701d81d | 599 | val = read_reg(env, R_EAX, decode->operand_size); |
29a0af61 | 600 | vmx_write_mem(env_cpu(env), addr, &val, decode->operand_size); |
c97d6d2c | 601 | |
6701d81d | 602 | string_increment_reg(env, R_EDI, decode); |
c97d6d2c SAGDR |
603 | } |
604 | ||
605 | ||
36861198 | 606 | static void exec_stos(CPUX86State *env, struct x86_decode *decode) |
c97d6d2c SAGDR |
607 | { |
608 | if (decode->rep) { | |
609 | string_rep(env, decode, exec_stos_single, 0); | |
610 | } else { | |
611 | exec_stos_single(env, decode); | |
612 | } | |
613 | ||
5d32173f | 614 | env->eip += decode->len; |
c97d6d2c SAGDR |
615 | } |
616 | ||
36861198 | 617 | static void exec_scas_single(CPUX86State *env, struct x86_decode *decode) |
c97d6d2c | 618 | { |
ff2de166 | 619 | target_ulong addr; |
c97d6d2c | 620 | |
29a0af61 RH |
621 | addr = linear_addr_size(env_cpu(env), RDI(env), |
622 | decode->addressing_size, R_ES); | |
c97d6d2c | 623 | decode->op[1].type = X86_VAR_IMMEDIATE; |
29a0af61 | 624 | vmx_read_mem(env_cpu(env), &decode->op[1].val, addr, decode->operand_size); |
c97d6d2c | 625 | |
e8a63257 | 626 | EXEC_2OP_FLAGS_CMD(env, decode, -, SET_FLAGS_OSZAPC_SUB, false); |
6701d81d | 627 | string_increment_reg(env, R_EDI, decode); |
c97d6d2c SAGDR |
628 | } |
629 | ||
36861198 | 630 | static void exec_scas(CPUX86State *env, struct x86_decode *decode) |
c97d6d2c SAGDR |
631 | { |
632 | decode->op[0].type = X86_VAR_REG; | |
6701d81d | 633 | decode->op[0].reg = R_EAX; |
c97d6d2c SAGDR |
634 | if (decode->rep) { |
635 | string_rep(env, decode, exec_scas_single, decode->rep); | |
636 | } else { | |
637 | exec_scas_single(env, decode); | |
638 | } | |
639 | ||
5d32173f | 640 | env->eip += decode->len; |
c97d6d2c SAGDR |
641 | } |
642 | ||
36861198 | 643 | static void exec_lods_single(CPUX86State *env, struct x86_decode *decode) |
c97d6d2c | 644 | { |
ff2de166 PB |
645 | target_ulong addr; |
646 | target_ulong val = 0; | |
c97d6d2c | 647 | |
6701d81d | 648 | addr = decode_linear_addr(env, decode, RSI(env), R_DS); |
29a0af61 | 649 | vmx_read_mem(env_cpu(env), &val, addr, decode->operand_size); |
6701d81d | 650 | write_reg(env, R_EAX, val, decode->operand_size); |
c97d6d2c | 651 | |
6701d81d | 652 | string_increment_reg(env, R_ESI, decode); |
c97d6d2c SAGDR |
653 | } |
654 | ||
36861198 | 655 | static void exec_lods(CPUX86State *env, struct x86_decode *decode) |
c97d6d2c SAGDR |
656 | { |
657 | if (decode->rep) { | |
658 | string_rep(env, decode, exec_lods_single, 0); | |
659 | } else { | |
660 | exec_lods_single(env, decode); | |
661 | } | |
662 | ||
5d32173f | 663 | env->eip += decode->len; |
c97d6d2c SAGDR |
664 | } |
665 | ||
c97d6d2c SAGDR |
666 | void simulate_rdmsr(struct CPUState *cpu) |
667 | { | |
668 | X86CPU *x86_cpu = X86_CPU(cpu); | |
669 | CPUX86State *env = &x86_cpu->env; | |
027ac0cb | 670 | CPUState *cs = env_cpu(env); |
c97d6d2c SAGDR |
671 | uint32_t msr = ECX(env); |
672 | uint64_t val = 0; | |
673 | ||
674 | switch (msr) { | |
675 | case MSR_IA32_TSC: | |
b533450e | 676 | val = rdtscp() + rvmcs(cpu->hvf->fd, VMCS_TSC_OFFSET); |
c97d6d2c SAGDR |
677 | break; |
678 | case MSR_IA32_APICBASE: | |
679 | val = cpu_get_apic_base(X86_CPU(cpu)->apic_state); | |
680 | break; | |
681 | case MSR_IA32_UCODE_REV: | |
4e45aff3 | 682 | val = x86_cpu->ucode_rev; |
c97d6d2c SAGDR |
683 | break; |
684 | case MSR_EFER: | |
b533450e | 685 | val = rvmcs(cpu->hvf->fd, VMCS_GUEST_IA32_EFER); |
c97d6d2c SAGDR |
686 | break; |
687 | case MSR_FSBASE: | |
b533450e | 688 | val = rvmcs(cpu->hvf->fd, VMCS_GUEST_FS_BASE); |
c97d6d2c SAGDR |
689 | break; |
690 | case MSR_GSBASE: | |
b533450e | 691 | val = rvmcs(cpu->hvf->fd, VMCS_GUEST_GS_BASE); |
c97d6d2c SAGDR |
692 | break; |
693 | case MSR_KERNELGSBASE: | |
b533450e | 694 | val = rvmcs(cpu->hvf->fd, VMCS_HOST_FS_BASE); |
c97d6d2c SAGDR |
695 | break; |
696 | case MSR_STAR: | |
697 | abort(); | |
698 | break; | |
699 | case MSR_LSTAR: | |
700 | abort(); | |
701 | break; | |
702 | case MSR_CSTAR: | |
703 | abort(); | |
704 | break; | |
705 | case MSR_IA32_MISC_ENABLE: | |
706 | val = env->msr_ia32_misc_enable; | |
707 | break; | |
708 | case MSR_MTRRphysBase(0): | |
709 | case MSR_MTRRphysBase(1): | |
710 | case MSR_MTRRphysBase(2): | |
711 | case MSR_MTRRphysBase(3): | |
712 | case MSR_MTRRphysBase(4): | |
713 | case MSR_MTRRphysBase(5): | |
714 | case MSR_MTRRphysBase(6): | |
715 | case MSR_MTRRphysBase(7): | |
716 | val = env->mtrr_var[(ECX(env) - MSR_MTRRphysBase(0)) / 2].base; | |
717 | break; | |
718 | case MSR_MTRRphysMask(0): | |
719 | case MSR_MTRRphysMask(1): | |
720 | case MSR_MTRRphysMask(2): | |
721 | case MSR_MTRRphysMask(3): | |
722 | case MSR_MTRRphysMask(4): | |
723 | case MSR_MTRRphysMask(5): | |
724 | case MSR_MTRRphysMask(6): | |
725 | case MSR_MTRRphysMask(7): | |
726 | val = env->mtrr_var[(ECX(env) - MSR_MTRRphysMask(0)) / 2].mask; | |
727 | break; | |
728 | case MSR_MTRRfix64K_00000: | |
729 | val = env->mtrr_fixed[0]; | |
730 | break; | |
731 | case MSR_MTRRfix16K_80000: | |
732 | case MSR_MTRRfix16K_A0000: | |
733 | val = env->mtrr_fixed[ECX(env) - MSR_MTRRfix16K_80000 + 1]; | |
734 | break; | |
735 | case MSR_MTRRfix4K_C0000: | |
736 | case MSR_MTRRfix4K_C8000: | |
737 | case MSR_MTRRfix4K_D0000: | |
738 | case MSR_MTRRfix4K_D8000: | |
739 | case MSR_MTRRfix4K_E0000: | |
740 | case MSR_MTRRfix4K_E8000: | |
741 | case MSR_MTRRfix4K_F0000: | |
742 | case MSR_MTRRfix4K_F8000: | |
743 | val = env->mtrr_fixed[ECX(env) - MSR_MTRRfix4K_C0000 + 3]; | |
744 | break; | |
745 | case MSR_MTRRdefType: | |
746 | val = env->mtrr_deftype; | |
747 | break; | |
027ac0cb VY |
748 | case MSR_CORE_THREAD_COUNT: |
749 | val = cs->nr_threads * cs->nr_cores; /* thread count, bits 15..0 */ | |
750 | val |= ((uint32_t)cs->nr_cores << 16); /* core count, bits 31..16 */ | |
751 | break; | |
c97d6d2c SAGDR |
752 | default: |
753 | /* fprintf(stderr, "%s: unknown msr 0x%x\n", __func__, msr); */ | |
754 | val = 0; | |
755 | break; | |
756 | } | |
757 | ||
758 | RAX(env) = (uint32_t)val; | |
759 | RDX(env) = (uint32_t)(val >> 32); | |
760 | } | |
761 | ||
36861198 | 762 | static void exec_rdmsr(CPUX86State *env, struct x86_decode *decode) |
c97d6d2c | 763 | { |
29a0af61 | 764 | simulate_rdmsr(env_cpu(env)); |
5d32173f | 765 | env->eip += decode->len; |
c97d6d2c SAGDR |
766 | } |
767 | ||
768 | void simulate_wrmsr(struct CPUState *cpu) | |
769 | { | |
770 | X86CPU *x86_cpu = X86_CPU(cpu); | |
771 | CPUX86State *env = &x86_cpu->env; | |
772 | uint32_t msr = ECX(env); | |
773 | uint64_t data = ((uint64_t)EDX(env) << 32) | EAX(env); | |
774 | ||
775 | switch (msr) { | |
776 | case MSR_IA32_TSC: | |
c97d6d2c SAGDR |
777 | break; |
778 | case MSR_IA32_APICBASE: | |
779 | cpu_set_apic_base(X86_CPU(cpu)->apic_state, data); | |
780 | break; | |
781 | case MSR_FSBASE: | |
b533450e | 782 | wvmcs(cpu->hvf->fd, VMCS_GUEST_FS_BASE, data); |
c97d6d2c SAGDR |
783 | break; |
784 | case MSR_GSBASE: | |
b533450e | 785 | wvmcs(cpu->hvf->fd, VMCS_GUEST_GS_BASE, data); |
c97d6d2c SAGDR |
786 | break; |
787 | case MSR_KERNELGSBASE: | |
b533450e | 788 | wvmcs(cpu->hvf->fd, VMCS_HOST_FS_BASE, data); |
c97d6d2c SAGDR |
789 | break; |
790 | case MSR_STAR: | |
791 | abort(); | |
792 | break; | |
793 | case MSR_LSTAR: | |
794 | abort(); | |
795 | break; | |
796 | case MSR_CSTAR: | |
797 | abort(); | |
798 | break; | |
799 | case MSR_EFER: | |
c97d6d2c | 800 | /*printf("new efer %llx\n", EFER(cpu));*/ |
b533450e | 801 | wvmcs(cpu->hvf->fd, VMCS_GUEST_IA32_EFER, data); |
6701d81d | 802 | if (data & MSR_EFER_NXE) { |
b533450e | 803 | hv_vcpu_invalidate_tlb(cpu->hvf->fd); |
c97d6d2c SAGDR |
804 | } |
805 | break; | |
806 | case MSR_MTRRphysBase(0): | |
807 | case MSR_MTRRphysBase(1): | |
808 | case MSR_MTRRphysBase(2): | |
809 | case MSR_MTRRphysBase(3): | |
810 | case MSR_MTRRphysBase(4): | |
811 | case MSR_MTRRphysBase(5): | |
812 | case MSR_MTRRphysBase(6): | |
813 | case MSR_MTRRphysBase(7): | |
814 | env->mtrr_var[(ECX(env) - MSR_MTRRphysBase(0)) / 2].base = data; | |
815 | break; | |
816 | case MSR_MTRRphysMask(0): | |
817 | case MSR_MTRRphysMask(1): | |
818 | case MSR_MTRRphysMask(2): | |
819 | case MSR_MTRRphysMask(3): | |
820 | case MSR_MTRRphysMask(4): | |
821 | case MSR_MTRRphysMask(5): | |
822 | case MSR_MTRRphysMask(6): | |
823 | case MSR_MTRRphysMask(7): | |
824 | env->mtrr_var[(ECX(env) - MSR_MTRRphysMask(0)) / 2].mask = data; | |
825 | break; | |
826 | case MSR_MTRRfix64K_00000: | |
827 | env->mtrr_fixed[ECX(env) - MSR_MTRRfix64K_00000] = data; | |
828 | break; | |
829 | case MSR_MTRRfix16K_80000: | |
830 | case MSR_MTRRfix16K_A0000: | |
831 | env->mtrr_fixed[ECX(env) - MSR_MTRRfix16K_80000 + 1] = data; | |
832 | break; | |
833 | case MSR_MTRRfix4K_C0000: | |
834 | case MSR_MTRRfix4K_C8000: | |
835 | case MSR_MTRRfix4K_D0000: | |
836 | case MSR_MTRRfix4K_D8000: | |
837 | case MSR_MTRRfix4K_E0000: | |
838 | case MSR_MTRRfix4K_E8000: | |
839 | case MSR_MTRRfix4K_F0000: | |
840 | case MSR_MTRRfix4K_F8000: | |
841 | env->mtrr_fixed[ECX(env) - MSR_MTRRfix4K_C0000 + 3] = data; | |
842 | break; | |
843 | case MSR_MTRRdefType: | |
844 | env->mtrr_deftype = data; | |
845 | break; | |
846 | default: | |
847 | break; | |
848 | } | |
849 | ||
850 | /* Related to support known hypervisor interface */ | |
851 | /* if (g_hypervisor_iface) | |
852 | g_hypervisor_iface->wrmsr_handler(cpu, msr, data); | |
853 | ||
854 | printf("write msr %llx\n", RCX(cpu));*/ | |
855 | } | |
856 | ||
36861198 | 857 | static void exec_wrmsr(CPUX86State *env, struct x86_decode *decode) |
c97d6d2c | 858 | { |
29a0af61 | 859 | simulate_wrmsr(env_cpu(env)); |
5d32173f | 860 | env->eip += decode->len; |
c97d6d2c SAGDR |
861 | } |
862 | ||
863 | /* | |
864 | * flag: | |
865 | * 0 - bt, 1 - btc, 2 - bts, 3 - btr | |
866 | */ | |
36861198 | 867 | static void do_bt(CPUX86State *env, struct x86_decode *decode, int flag) |
c97d6d2c SAGDR |
868 | { |
869 | int32_t displacement; | |
870 | uint8_t index; | |
871 | bool cf; | |
872 | int mask = (4 == decode->operand_size) ? 0x1f : 0xf; | |
873 | ||
874 | VM_PANIC_ON(decode->rex.rex); | |
875 | ||
876 | fetch_operands(env, decode, 2, false, true, false); | |
877 | index = decode->op[1].val & mask; | |
878 | ||
879 | if (decode->op[0].type != X86_VAR_REG) { | |
880 | if (4 == decode->operand_size) { | |
881 | displacement = ((int32_t) (decode->op[1].val & 0xffffffe0)) / 32; | |
882 | decode->op[0].ptr += 4 * displacement; | |
883 | } else if (2 == decode->operand_size) { | |
884 | displacement = ((int16_t) (decode->op[1].val & 0xfff0)) / 16; | |
885 | decode->op[0].ptr += 2 * displacement; | |
886 | } else { | |
887 | VM_PANIC("bt 64bit\n"); | |
888 | } | |
889 | } | |
890 | decode->op[0].val = read_val_ext(env, decode->op[0].ptr, | |
891 | decode->operand_size); | |
892 | cf = (decode->op[0].val >> index) & 0x01; | |
893 | ||
894 | switch (flag) { | |
895 | case 0: | |
896 | set_CF(env, cf); | |
897 | return; | |
898 | case 1: | |
899 | decode->op[0].val ^= (1u << index); | |
900 | break; | |
901 | case 2: | |
902 | decode->op[0].val |= (1u << index); | |
903 | break; | |
904 | case 3: | |
905 | decode->op[0].val &= ~(1u << index); | |
906 | break; | |
907 | } | |
908 | write_val_ext(env, decode->op[0].ptr, decode->op[0].val, | |
909 | decode->operand_size); | |
910 | set_CF(env, cf); | |
911 | } | |
912 | ||
36861198 | 913 | static void exec_bt(CPUX86State *env, struct x86_decode *decode) |
c97d6d2c SAGDR |
914 | { |
915 | do_bt(env, decode, 0); | |
5d32173f | 916 | env->eip += decode->len; |
c97d6d2c SAGDR |
917 | } |
918 | ||
36861198 | 919 | static void exec_btc(CPUX86State *env, struct x86_decode *decode) |
c97d6d2c SAGDR |
920 | { |
921 | do_bt(env, decode, 1); | |
5d32173f | 922 | env->eip += decode->len; |
c97d6d2c SAGDR |
923 | } |
924 | ||
36861198 | 925 | static void exec_btr(CPUX86State *env, struct x86_decode *decode) |
c97d6d2c SAGDR |
926 | { |
927 | do_bt(env, decode, 3); | |
5d32173f | 928 | env->eip += decode->len; |
c97d6d2c SAGDR |
929 | } |
930 | ||
36861198 | 931 | static void exec_bts(CPUX86State *env, struct x86_decode *decode) |
c97d6d2c SAGDR |
932 | { |
933 | do_bt(env, decode, 2); | |
5d32173f | 934 | env->eip += decode->len; |
c97d6d2c SAGDR |
935 | } |
936 | ||
36861198 | 937 | void exec_shl(CPUX86State *env, struct x86_decode *decode) |
c97d6d2c SAGDR |
938 | { |
939 | uint8_t count; | |
940 | int of = 0, cf = 0; | |
941 | ||
942 | fetch_operands(env, decode, 2, true, true, false); | |
943 | ||
944 | count = decode->op[1].val; | |
945 | count &= 0x1f; /* count is masked to 5 bits*/ | |
946 | if (!count) { | |
947 | goto exit; | |
948 | } | |
949 | ||
950 | switch (decode->operand_size) { | |
951 | case 1: | |
952 | { | |
953 | uint8_t res = 0; | |
954 | if (count <= 8) { | |
955 | res = (decode->op[0].val << count); | |
956 | cf = (decode->op[0].val >> (8 - count)) & 0x1; | |
957 | of = cf ^ (res >> 7); | |
958 | } | |
959 | ||
960 | write_val_ext(env, decode->op[0].ptr, res, 1); | |
e8a63257 | 961 | SET_FLAGS_OSZAPC_LOGIC8(env, 0, 0, res); |
c97d6d2c SAGDR |
962 | SET_FLAGS_OxxxxC(env, of, cf); |
963 | break; | |
964 | } | |
965 | case 2: | |
966 | { | |
967 | uint16_t res = 0; | |
968 | ||
969 | /* from bochs */ | |
970 | if (count <= 16) { | |
971 | res = (decode->op[0].val << count); | |
972 | cf = (decode->op[0].val >> (16 - count)) & 0x1; | |
973 | of = cf ^ (res >> 15); /* of = cf ^ result15 */ | |
974 | } | |
975 | ||
976 | write_val_ext(env, decode->op[0].ptr, res, 2); | |
e8a63257 | 977 | SET_FLAGS_OSZAPC_LOGIC16(env, 0, 0, res); |
c97d6d2c SAGDR |
978 | SET_FLAGS_OxxxxC(env, of, cf); |
979 | break; | |
980 | } | |
981 | case 4: | |
982 | { | |
983 | uint32_t res = decode->op[0].val << count; | |
984 | ||
985 | write_val_ext(env, decode->op[0].ptr, res, 4); | |
e8a63257 | 986 | SET_FLAGS_OSZAPC_LOGIC32(env, 0, 0, res); |
c97d6d2c SAGDR |
987 | cf = (decode->op[0].val >> (32 - count)) & 0x1; |
988 | of = cf ^ (res >> 31); /* of = cf ^ result31 */ | |
989 | SET_FLAGS_OxxxxC(env, of, cf); | |
990 | break; | |
991 | } | |
992 | default: | |
993 | abort(); | |
994 | } | |
995 | ||
996 | exit: | |
997 | /* lflags_to_rflags(env); */ | |
5d32173f | 998 | env->eip += decode->len; |
c97d6d2c SAGDR |
999 | } |
1000 | ||
1001 | void exec_movsx(CPUX86State *env, struct x86_decode *decode) | |
1002 | { | |
1003 | int src_op_size; | |
1004 | int op_size = decode->operand_size; | |
1005 | ||
1006 | fetch_operands(env, decode, 2, false, false, false); | |
1007 | ||
1008 | if (0xbe == decode->opcode[1]) { | |
1009 | src_op_size = 1; | |
1010 | } else { | |
1011 | src_op_size = 2; | |
1012 | } | |
1013 | ||
1014 | decode->operand_size = src_op_size; | |
1015 | calc_modrm_operand(env, decode, &decode->op[1]); | |
1016 | decode->op[1].val = sign(read_val_ext(env, decode->op[1].ptr, src_op_size), | |
1017 | src_op_size); | |
1018 | ||
1019 | write_val_ext(env, decode->op[0].ptr, decode->op[1].val, op_size); | |
1020 | ||
5d32173f | 1021 | env->eip += decode->len; |
c97d6d2c SAGDR |
1022 | } |
1023 | ||
36861198 | 1024 | void exec_ror(CPUX86State *env, struct x86_decode *decode) |
c97d6d2c SAGDR |
1025 | { |
1026 | uint8_t count; | |
1027 | ||
1028 | fetch_operands(env, decode, 2, true, true, false); | |
1029 | count = decode->op[1].val; | |
1030 | ||
1031 | switch (decode->operand_size) { | |
1032 | case 1: | |
1033 | { | |
1034 | uint32_t bit6, bit7; | |
1035 | uint8_t res; | |
1036 | ||
1037 | if ((count & 0x07) == 0) { | |
1038 | if (count & 0x18) { | |
1039 | bit6 = ((uint8_t)decode->op[0].val >> 6) & 1; | |
1040 | bit7 = ((uint8_t)decode->op[0].val >> 7) & 1; | |
1041 | SET_FLAGS_OxxxxC(env, bit6 ^ bit7, bit7); | |
1042 | } | |
1043 | } else { | |
1044 | count &= 0x7; /* use only bottom 3 bits */ | |
1045 | res = ((uint8_t)decode->op[0].val >> count) | | |
1046 | ((uint8_t)decode->op[0].val << (8 - count)); | |
1047 | write_val_ext(env, decode->op[0].ptr, res, 1); | |
1048 | bit6 = (res >> 6) & 1; | |
1049 | bit7 = (res >> 7) & 1; | |
1050 | /* set eflags: ROR count affects the following flags: C, O */ | |
1051 | SET_FLAGS_OxxxxC(env, bit6 ^ bit7, bit7); | |
1052 | } | |
1053 | break; | |
1054 | } | |
1055 | case 2: | |
1056 | { | |
1057 | uint32_t bit14, bit15; | |
1058 | uint16_t res; | |
1059 | ||
1060 | if ((count & 0x0f) == 0) { | |
1061 | if (count & 0x10) { | |
1062 | bit14 = ((uint16_t)decode->op[0].val >> 14) & 1; | |
1063 | bit15 = ((uint16_t)decode->op[0].val >> 15) & 1; | |
1064 | /* of = result14 ^ result15 */ | |
1065 | SET_FLAGS_OxxxxC(env, bit14 ^ bit15, bit15); | |
1066 | } | |
1067 | } else { | |
1068 | count &= 0x0f; /* use only 4 LSB's */ | |
1069 | res = ((uint16_t)decode->op[0].val >> count) | | |
1070 | ((uint16_t)decode->op[0].val << (16 - count)); | |
1071 | write_val_ext(env, decode->op[0].ptr, res, 2); | |
1072 | ||
1073 | bit14 = (res >> 14) & 1; | |
1074 | bit15 = (res >> 15) & 1; | |
1075 | /* of = result14 ^ result15 */ | |
1076 | SET_FLAGS_OxxxxC(env, bit14 ^ bit15, bit15); | |
1077 | } | |
1078 | break; | |
1079 | } | |
1080 | case 4: | |
1081 | { | |
1082 | uint32_t bit31, bit30; | |
1083 | uint32_t res; | |
1084 | ||
1085 | count &= 0x1f; | |
1086 | if (count) { | |
1087 | res = ((uint32_t)decode->op[0].val >> count) | | |
1088 | ((uint32_t)decode->op[0].val << (32 - count)); | |
1089 | write_val_ext(env, decode->op[0].ptr, res, 4); | |
1090 | ||
1091 | bit31 = (res >> 31) & 1; | |
1092 | bit30 = (res >> 30) & 1; | |
1093 | /* of = result30 ^ result31 */ | |
1094 | SET_FLAGS_OxxxxC(env, bit30 ^ bit31, bit31); | |
1095 | } | |
1096 | break; | |
1097 | } | |
1098 | } | |
5d32173f | 1099 | env->eip += decode->len; |
c97d6d2c SAGDR |
1100 | } |
1101 | ||
36861198 | 1102 | void exec_rol(CPUX86State *env, struct x86_decode *decode) |
c97d6d2c SAGDR |
1103 | { |
1104 | uint8_t count; | |
1105 | ||
1106 | fetch_operands(env, decode, 2, true, true, false); | |
1107 | count = decode->op[1].val; | |
1108 | ||
1109 | switch (decode->operand_size) { | |
1110 | case 1: | |
1111 | { | |
1112 | uint32_t bit0, bit7; | |
1113 | uint8_t res; | |
1114 | ||
1115 | if ((count & 0x07) == 0) { | |
1116 | if (count & 0x18) { | |
1117 | bit0 = ((uint8_t)decode->op[0].val & 1); | |
1118 | bit7 = ((uint8_t)decode->op[0].val >> 7); | |
1119 | SET_FLAGS_OxxxxC(env, bit0 ^ bit7, bit0); | |
1120 | } | |
1121 | } else { | |
1122 | count &= 0x7; /* use only lowest 3 bits */ | |
1123 | res = ((uint8_t)decode->op[0].val << count) | | |
1124 | ((uint8_t)decode->op[0].val >> (8 - count)); | |
1125 | ||
1126 | write_val_ext(env, decode->op[0].ptr, res, 1); | |
1127 | /* set eflags: | |
1128 | * ROL count affects the following flags: C, O | |
1129 | */ | |
1130 | bit0 = (res & 1); | |
1131 | bit7 = (res >> 7); | |
1132 | SET_FLAGS_OxxxxC(env, bit0 ^ bit7, bit0); | |
1133 | } | |
1134 | break; | |
1135 | } | |
1136 | case 2: | |
1137 | { | |
1138 | uint32_t bit0, bit15; | |
1139 | uint16_t res; | |
1140 | ||
1141 | if ((count & 0x0f) == 0) { | |
1142 | if (count & 0x10) { | |
1143 | bit0 = ((uint16_t)decode->op[0].val & 0x1); | |
1144 | bit15 = ((uint16_t)decode->op[0].val >> 15); | |
1145 | /* of = cf ^ result15 */ | |
1146 | SET_FLAGS_OxxxxC(env, bit0 ^ bit15, bit0); | |
1147 | } | |
1148 | } else { | |
1149 | count &= 0x0f; /* only use bottom 4 bits */ | |
1150 | res = ((uint16_t)decode->op[0].val << count) | | |
1151 | ((uint16_t)decode->op[0].val >> (16 - count)); | |
1152 | ||
1153 | write_val_ext(env, decode->op[0].ptr, res, 2); | |
1154 | bit0 = (res & 0x1); | |
1155 | bit15 = (res >> 15); | |
1156 | /* of = cf ^ result15 */ | |
1157 | SET_FLAGS_OxxxxC(env, bit0 ^ bit15, bit0); | |
1158 | } | |
1159 | break; | |
1160 | } | |
1161 | case 4: | |
1162 | { | |
1163 | uint32_t bit0, bit31; | |
1164 | uint32_t res; | |
1165 | ||
1166 | count &= 0x1f; | |
1167 | if (count) { | |
1168 | res = ((uint32_t)decode->op[0].val << count) | | |
1169 | ((uint32_t)decode->op[0].val >> (32 - count)); | |
1170 | ||
1171 | write_val_ext(env, decode->op[0].ptr, res, 4); | |
1172 | bit0 = (res & 0x1); | |
1173 | bit31 = (res >> 31); | |
1174 | /* of = cf ^ result31 */ | |
1175 | SET_FLAGS_OxxxxC(env, bit0 ^ bit31, bit0); | |
1176 | } | |
1177 | break; | |
1178 | } | |
1179 | } | |
5d32173f | 1180 | env->eip += decode->len; |
c97d6d2c SAGDR |
1181 | } |
1182 | ||
1183 | ||
36861198 | 1184 | void exec_rcl(CPUX86State *env, struct x86_decode *decode) |
c97d6d2c SAGDR |
1185 | { |
1186 | uint8_t count; | |
1187 | int of = 0, cf = 0; | |
1188 | ||
1189 | fetch_operands(env, decode, 2, true, true, false); | |
1190 | count = decode->op[1].val & 0x1f; | |
1191 | ||
1192 | switch (decode->operand_size) { | |
1193 | case 1: | |
1194 | { | |
1195 | uint8_t op1_8 = decode->op[0].val; | |
1196 | uint8_t res; | |
1197 | count %= 9; | |
1198 | if (!count) { | |
1199 | break; | |
1200 | } | |
1201 | ||
1202 | if (1 == count) { | |
1203 | res = (op1_8 << 1) | get_CF(env); | |
1204 | } else { | |
1205 | res = (op1_8 << count) | (get_CF(env) << (count - 1)) | | |
1206 | (op1_8 >> (9 - count)); | |
1207 | } | |
1208 | ||
1209 | write_val_ext(env, decode->op[0].ptr, res, 1); | |
1210 | ||
1211 | cf = (op1_8 >> (8 - count)) & 0x01; | |
1212 | of = cf ^ (res >> 7); /* of = cf ^ result7 */ | |
1213 | SET_FLAGS_OxxxxC(env, of, cf); | |
1214 | break; | |
1215 | } | |
1216 | case 2: | |
1217 | { | |
1218 | uint16_t res; | |
1219 | uint16_t op1_16 = decode->op[0].val; | |
1220 | ||
1221 | count %= 17; | |
1222 | if (!count) { | |
1223 | break; | |
1224 | } | |
1225 | ||
1226 | if (1 == count) { | |
1227 | res = (op1_16 << 1) | get_CF(env); | |
1228 | } else if (count == 16) { | |
1229 | res = (get_CF(env) << 15) | (op1_16 >> 1); | |
1230 | } else { /* 2..15 */ | |
1231 | res = (op1_16 << count) | (get_CF(env) << (count - 1)) | | |
1232 | (op1_16 >> (17 - count)); | |
1233 | } | |
1234 | ||
1235 | write_val_ext(env, decode->op[0].ptr, res, 2); | |
1236 | ||
1237 | cf = (op1_16 >> (16 - count)) & 0x1; | |
1238 | of = cf ^ (res >> 15); /* of = cf ^ result15 */ | |
1239 | SET_FLAGS_OxxxxC(env, of, cf); | |
1240 | break; | |
1241 | } | |
1242 | case 4: | |
1243 | { | |
1244 | uint32_t res; | |
1245 | uint32_t op1_32 = decode->op[0].val; | |
1246 | ||
1247 | if (!count) { | |
1248 | break; | |
1249 | } | |
1250 | ||
1251 | if (1 == count) { | |
1252 | res = (op1_32 << 1) | get_CF(env); | |
1253 | } else { | |
1254 | res = (op1_32 << count) | (get_CF(env) << (count - 1)) | | |
1255 | (op1_32 >> (33 - count)); | |
1256 | } | |
1257 | ||
1258 | write_val_ext(env, decode->op[0].ptr, res, 4); | |
1259 | ||
1260 | cf = (op1_32 >> (32 - count)) & 0x1; | |
1261 | of = cf ^ (res >> 31); /* of = cf ^ result31 */ | |
1262 | SET_FLAGS_OxxxxC(env, of, cf); | |
1263 | break; | |
1264 | } | |
1265 | } | |
5d32173f | 1266 | env->eip += decode->len; |
c97d6d2c SAGDR |
1267 | } |
1268 | ||
36861198 | 1269 | void exec_rcr(CPUX86State *env, struct x86_decode *decode) |
c97d6d2c SAGDR |
1270 | { |
1271 | uint8_t count; | |
1272 | int of = 0, cf = 0; | |
1273 | ||
1274 | fetch_operands(env, decode, 2, true, true, false); | |
1275 | count = decode->op[1].val & 0x1f; | |
1276 | ||
1277 | switch (decode->operand_size) { | |
1278 | case 1: | |
1279 | { | |
1280 | uint8_t op1_8 = decode->op[0].val; | |
1281 | uint8_t res; | |
1282 | ||
1283 | count %= 9; | |
1284 | if (!count) { | |
1285 | break; | |
1286 | } | |
1287 | res = (op1_8 >> count) | (get_CF(env) << (8 - count)) | | |
1288 | (op1_8 << (9 - count)); | |
1289 | ||
1290 | write_val_ext(env, decode->op[0].ptr, res, 1); | |
1291 | ||
1292 | cf = (op1_8 >> (count - 1)) & 0x1; | |
1293 | of = (((res << 1) ^ res) >> 7) & 0x1; /* of = result6 ^ result7 */ | |
1294 | SET_FLAGS_OxxxxC(env, of, cf); | |
1295 | break; | |
1296 | } | |
1297 | case 2: | |
1298 | { | |
1299 | uint16_t op1_16 = decode->op[0].val; | |
1300 | uint16_t res; | |
1301 | ||
1302 | count %= 17; | |
1303 | if (!count) { | |
1304 | break; | |
1305 | } | |
1306 | res = (op1_16 >> count) | (get_CF(env) << (16 - count)) | | |
1307 | (op1_16 << (17 - count)); | |
1308 | ||
1309 | write_val_ext(env, decode->op[0].ptr, res, 2); | |
1310 | ||
1311 | cf = (op1_16 >> (count - 1)) & 0x1; | |
1312 | of = ((uint16_t)((res << 1) ^ res) >> 15) & 0x1; /* of = result15 ^ | |
1313 | result14 */ | |
1314 | SET_FLAGS_OxxxxC(env, of, cf); | |
1315 | break; | |
1316 | } | |
1317 | case 4: | |
1318 | { | |
1319 | uint32_t res; | |
1320 | uint32_t op1_32 = decode->op[0].val; | |
1321 | ||
1322 | if (!count) { | |
1323 | break; | |
1324 | } | |
1325 | ||
1326 | if (1 == count) { | |
1327 | res = (op1_32 >> 1) | (get_CF(env) << 31); | |
1328 | } else { | |
1329 | res = (op1_32 >> count) | (get_CF(env) << (32 - count)) | | |
1330 | (op1_32 << (33 - count)); | |
1331 | } | |
1332 | ||
1333 | write_val_ext(env, decode->op[0].ptr, res, 4); | |
1334 | ||
1335 | cf = (op1_32 >> (count - 1)) & 0x1; | |
1336 | of = ((res << 1) ^ res) >> 31; /* of = result30 ^ result31 */ | |
1337 | SET_FLAGS_OxxxxC(env, of, cf); | |
1338 | break; | |
1339 | } | |
1340 | } | |
5d32173f | 1341 | env->eip += decode->len; |
c97d6d2c SAGDR |
1342 | } |
1343 | ||
36861198 | 1344 | static void exec_xchg(CPUX86State *env, struct x86_decode *decode) |
c97d6d2c SAGDR |
1345 | { |
1346 | fetch_operands(env, decode, 2, true, true, false); | |
1347 | ||
1348 | write_val_ext(env, decode->op[0].ptr, decode->op[1].val, | |
1349 | decode->operand_size); | |
1350 | write_val_ext(env, decode->op[1].ptr, decode->op[0].val, | |
1351 | decode->operand_size); | |
1352 | ||
5d32173f | 1353 | env->eip += decode->len; |
c97d6d2c SAGDR |
1354 | } |
1355 | ||
36861198 | 1356 | static void exec_xadd(CPUX86State *env, struct x86_decode *decode) |
c97d6d2c | 1357 | { |
e8a63257 | 1358 | EXEC_2OP_FLAGS_CMD(env, decode, +, SET_FLAGS_OSZAPC_ADD, true); |
c97d6d2c SAGDR |
1359 | write_val_ext(env, decode->op[1].ptr, decode->op[0].val, |
1360 | decode->operand_size); | |
1361 | ||
5d32173f | 1362 | env->eip += decode->len; |
c97d6d2c SAGDR |
1363 | } |
1364 | ||
1365 | static struct cmd_handler { | |
1366 | enum x86_decode_cmd cmd; | |
36861198 | 1367 | void (*handler)(CPUX86State *env, struct x86_decode *ins); |
c97d6d2c SAGDR |
1368 | } handlers[] = { |
1369 | {X86_DECODE_CMD_INVL, NULL,}, | |
1370 | {X86_DECODE_CMD_MOV, exec_mov}, | |
1371 | {X86_DECODE_CMD_ADD, exec_add}, | |
1372 | {X86_DECODE_CMD_OR, exec_or}, | |
1373 | {X86_DECODE_CMD_ADC, exec_adc}, | |
1374 | {X86_DECODE_CMD_SBB, exec_sbb}, | |
1375 | {X86_DECODE_CMD_AND, exec_and}, | |
1376 | {X86_DECODE_CMD_SUB, exec_sub}, | |
1377 | {X86_DECODE_CMD_NEG, exec_neg}, | |
1378 | {X86_DECODE_CMD_XOR, exec_xor}, | |
1379 | {X86_DECODE_CMD_CMP, exec_cmp}, | |
1380 | {X86_DECODE_CMD_INC, exec_inc}, | |
1381 | {X86_DECODE_CMD_DEC, exec_dec}, | |
1382 | {X86_DECODE_CMD_TST, exec_tst}, | |
1383 | {X86_DECODE_CMD_NOT, exec_not}, | |
1384 | {X86_DECODE_CMD_MOVZX, exec_movzx}, | |
1385 | {X86_DECODE_CMD_OUT, exec_out}, | |
1386 | {X86_DECODE_CMD_IN, exec_in}, | |
1387 | {X86_DECODE_CMD_INS, exec_ins}, | |
1388 | {X86_DECODE_CMD_OUTS, exec_outs}, | |
1389 | {X86_DECODE_CMD_RDMSR, exec_rdmsr}, | |
1390 | {X86_DECODE_CMD_WRMSR, exec_wrmsr}, | |
1391 | {X86_DECODE_CMD_BT, exec_bt}, | |
1392 | {X86_DECODE_CMD_BTR, exec_btr}, | |
1393 | {X86_DECODE_CMD_BTC, exec_btc}, | |
1394 | {X86_DECODE_CMD_BTS, exec_bts}, | |
1395 | {X86_DECODE_CMD_SHL, exec_shl}, | |
1396 | {X86_DECODE_CMD_ROL, exec_rol}, | |
1397 | {X86_DECODE_CMD_ROR, exec_ror}, | |
1398 | {X86_DECODE_CMD_RCR, exec_rcr}, | |
1399 | {X86_DECODE_CMD_RCL, exec_rcl}, | |
1400 | /*{X86_DECODE_CMD_CPUID, exec_cpuid},*/ | |
1401 | {X86_DECODE_CMD_MOVS, exec_movs}, | |
1402 | {X86_DECODE_CMD_CMPS, exec_cmps}, | |
1403 | {X86_DECODE_CMD_STOS, exec_stos}, | |
1404 | {X86_DECODE_CMD_SCAS, exec_scas}, | |
1405 | {X86_DECODE_CMD_LODS, exec_lods}, | |
1406 | {X86_DECODE_CMD_MOVSX, exec_movsx}, | |
1407 | {X86_DECODE_CMD_XCHG, exec_xchg}, | |
1408 | {X86_DECODE_CMD_XADD, exec_xadd}, | |
1409 | }; | |
1410 | ||
1411 | static struct cmd_handler _cmd_handler[X86_DECODE_CMD_LAST]; | |
1412 | ||
1413 | static void init_cmd_handler() | |
1414 | { | |
1415 | int i; | |
1416 | for (i = 0; i < ARRAY_SIZE(handlers); i++) { | |
1417 | _cmd_handler[handlers[i].cmd] = handlers[i]; | |
1418 | } | |
1419 | } | |
1420 | ||
1421 | void load_regs(struct CPUState *cpu) | |
1422 | { | |
1423 | X86CPU *x86_cpu = X86_CPU(cpu); | |
1424 | CPUX86State *env = &x86_cpu->env; | |
1425 | ||
1426 | int i = 0; | |
b533450e AG |
1427 | RRX(env, R_EAX) = rreg(cpu->hvf->fd, HV_X86_RAX); |
1428 | RRX(env, R_EBX) = rreg(cpu->hvf->fd, HV_X86_RBX); | |
1429 | RRX(env, R_ECX) = rreg(cpu->hvf->fd, HV_X86_RCX); | |
1430 | RRX(env, R_EDX) = rreg(cpu->hvf->fd, HV_X86_RDX); | |
1431 | RRX(env, R_ESI) = rreg(cpu->hvf->fd, HV_X86_RSI); | |
1432 | RRX(env, R_EDI) = rreg(cpu->hvf->fd, HV_X86_RDI); | |
1433 | RRX(env, R_ESP) = rreg(cpu->hvf->fd, HV_X86_RSP); | |
1434 | RRX(env, R_EBP) = rreg(cpu->hvf->fd, HV_X86_RBP); | |
c97d6d2c | 1435 | for (i = 8; i < 16; i++) { |
b533450e | 1436 | RRX(env, i) = rreg(cpu->hvf->fd, HV_X86_RAX + i); |
c97d6d2c SAGDR |
1437 | } |
1438 | ||
b533450e | 1439 | env->eflags = rreg(cpu->hvf->fd, HV_X86_RFLAGS); |
c97d6d2c | 1440 | rflags_to_lflags(env); |
b533450e | 1441 | env->eip = rreg(cpu->hvf->fd, HV_X86_RIP); |
c97d6d2c SAGDR |
1442 | } |
1443 | ||
1444 | void store_regs(struct CPUState *cpu) | |
1445 | { | |
1446 | X86CPU *x86_cpu = X86_CPU(cpu); | |
1447 | CPUX86State *env = &x86_cpu->env; | |
1448 | ||
1449 | int i = 0; | |
b533450e AG |
1450 | wreg(cpu->hvf->fd, HV_X86_RAX, RAX(env)); |
1451 | wreg(cpu->hvf->fd, HV_X86_RBX, RBX(env)); | |
1452 | wreg(cpu->hvf->fd, HV_X86_RCX, RCX(env)); | |
1453 | wreg(cpu->hvf->fd, HV_X86_RDX, RDX(env)); | |
1454 | wreg(cpu->hvf->fd, HV_X86_RSI, RSI(env)); | |
1455 | wreg(cpu->hvf->fd, HV_X86_RDI, RDI(env)); | |
1456 | wreg(cpu->hvf->fd, HV_X86_RBP, RBP(env)); | |
1457 | wreg(cpu->hvf->fd, HV_X86_RSP, RSP(env)); | |
c97d6d2c | 1458 | for (i = 8; i < 16; i++) { |
b533450e | 1459 | wreg(cpu->hvf->fd, HV_X86_RAX + i, RRX(env, i)); |
c97d6d2c SAGDR |
1460 | } |
1461 | ||
1462 | lflags_to_rflags(env); | |
b533450e | 1463 | wreg(cpu->hvf->fd, HV_X86_RFLAGS, env->eflags); |
5d32173f | 1464 | macvm_set_rip(cpu, env->eip); |
c97d6d2c SAGDR |
1465 | } |
1466 | ||
36861198 | 1467 | bool exec_instruction(CPUX86State *env, struct x86_decode *ins) |
c97d6d2c SAGDR |
1468 | { |
1469 | /*if (hvf_vcpu_id(cpu)) | |
5d32173f | 1470 | printf("%d, %llx: exec_instruction %s\n", hvf_vcpu_id(cpu), env->eip, |
c97d6d2c SAGDR |
1471 | decode_cmd_to_string(ins->cmd));*/ |
1472 | ||
74682782 | 1473 | if (!_cmd_handler[ins->cmd].handler) { |
5d32173f | 1474 | printf("Unimplemented handler (%llx) for %d (%x %x) \n", env->eip, |
74682782 PB |
1475 | ins->cmd, ins->opcode[0], |
1476 | ins->opcode_len > 1 ? ins->opcode[1] : 0); | |
5d32173f | 1477 | env->eip += ins->len; |
74682782 | 1478 | return true; |
c97d6d2c | 1479 | } |
74682782 PB |
1480 | |
1481 | _cmd_handler[ins->cmd].handler(env, ins); | |
c97d6d2c SAGDR |
1482 | return true; |
1483 | } | |
1484 | ||
1485 | void init_emu() | |
1486 | { | |
1487 | init_cmd_handler(); | |
1488 | } |