[mirror_qemu.git] / target / i386 / hyperv-proto.h

/*
 * Definitions for Hyper-V guest/hypervisor interaction - x86-specific part
 *
 * Copyright (c) 2017-2018 Virtuozzo International GmbH.
 *
 * This work is licensed under the terms of the GNU GPL, version 2 or later.
 * See the COPYING file in the top-level directory.
 */

#ifndef TARGET_I386_HYPERV_PROTO_H
#define TARGET_I386_HYPERV_PROTO_H

#include "hw/hyperv/hyperv-proto.h"

#define HV_CPUID_VENDOR_AND_MAX_FUNCTIONS     0x40000000
#define HV_CPUID_INTERFACE                    0x40000001
#define HV_CPUID_VERSION                      0x40000002
#define HV_CPUID_FEATURES                     0x40000003
#define HV_CPUID_ENLIGHTMENT_INFO             0x40000004
#define HV_CPUID_IMPLEMENT_LIMITS             0x40000005
#define HV_CPUID_NESTED_FEATURES              0x4000000A
#define HV_CPUID_MIN                          0x40000005
#define HV_CPUID_MAX                          0x4000ffff
#define HV_HYPERVISOR_PRESENT_BIT             0x80000000

/*
 * HV_CPUID_FEATURES.EAX bits
 */
#define HV_VP_RUNTIME_AVAILABLE      (1u << 0)
#define HV_TIME_REF_COUNT_AVAILABLE  (1u << 1)
#define HV_SYNIC_AVAILABLE           (1u << 2)
#define HV_SYNTIMERS_AVAILABLE       (1u << 3)
#define HV_APIC_ACCESS_AVAILABLE     (1u << 4)
#define HV_HYPERCALL_AVAILABLE       (1u << 5)
#define HV_VP_INDEX_AVAILABLE        (1u << 6)
#define HV_RESET_AVAILABLE           (1u << 7)
#define HV_REFERENCE_TSC_AVAILABLE   (1u << 9)
#define HV_ACCESS_FREQUENCY_MSRS     (1u << 11)
#define HV_ACCESS_REENLIGHTENMENTS_CONTROL  (1u << 13)

/*
 * HV_CPUID_FEATURES.EDX bits
 */
#define HV_MWAIT_AVAILABLE                      (1u << 0)
#define HV_GUEST_DEBUGGING_AVAILABLE            (1u << 1)
#define HV_PERF_MONITOR_AVAILABLE               (1u << 2)
#define HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE   (1u << 3)
#define HV_HYPERCALL_PARAMS_XMM_AVAILABLE       (1u << 4)
#define HV_GUEST_IDLE_STATE_AVAILABLE           (1u << 5)
#define HV_FREQUENCY_MSRS_AVAILABLE             (1u << 8)
#define HV_GUEST_CRASH_MSR_AVAILABLE            (1u << 10)

/*
 * HV_CPUID_ENLIGHTMENT_INFO.EAX bits
 */
#define HV_AS_SWITCH_RECOMMENDED            (1u << 0)
#define HV_LOCAL_TLB_FLUSH_RECOMMENDED      (1u << 1)
#define HV_REMOTE_TLB_FLUSH_RECOMMENDED     (1u << 2)
#define HV_APIC_ACCESS_RECOMMENDED          (1u << 3)
#define HV_SYSTEM_RESET_RECOMMENDED         (1u << 4)
#define HV_RELAXED_TIMING_RECOMMENDED       (1u << 5)
#define HV_CLUSTER_IPI_RECOMMENDED          (1u << 10)
#define HV_EX_PROCESSOR_MASKS_RECOMMENDED   (1u << 11)
#define HV_ENLIGHTENED_VMCS_RECOMMENDED     (1u << 14)

/*
 * Basic virtualized MSRs
 */
#define HV_X64_MSR_GUEST_OS_ID                0x40000000
#define HV_X64_MSR_HYPERCALL                  0x40000001
#define HV_X64_MSR_VP_INDEX                   0x40000002
#define HV_X64_MSR_RESET                      0x40000003
#define HV_X64_MSR_VP_RUNTIME                 0x40000010
#define HV_X64_MSR_TIME_REF_COUNT             0x40000020
#define HV_X64_MSR_REFERENCE_TSC              0x40000021
#define HV_X64_MSR_TSC_FREQUENCY              0x40000022
#define HV_X64_MSR_APIC_FREQUENCY             0x40000023

/*
 * Virtual APIC MSRs
 */
#define HV_X64_MSR_EOI                        0x40000070
#define HV_X64_MSR_ICR                        0x40000071
#define HV_X64_MSR_TPR                        0x40000072
#define HV_X64_MSR_APIC_ASSIST_PAGE           0x40000073

/*
 * Synthetic interrupt controller MSRs
 */
#define HV_X64_MSR_SCONTROL                   0x40000080
#define HV_X64_MSR_SVERSION                   0x40000081
#define HV_X64_MSR_SIEFP                      0x40000082
#define HV_X64_MSR_SIMP                       0x40000083
#define HV_X64_MSR_EOM                        0x40000084
#define HV_X64_MSR_SINT0                      0x40000090
#define HV_X64_MSR_SINT1                      0x40000091
#define HV_X64_MSR_SINT2                      0x40000092
#define HV_X64_MSR_SINT3                      0x40000093
#define HV_X64_MSR_SINT4                      0x40000094
#define HV_X64_MSR_SINT5                      0x40000095
#define HV_X64_MSR_SINT6                      0x40000096
#define HV_X64_MSR_SINT7                      0x40000097
#define HV_X64_MSR_SINT8                      0x40000098
#define HV_X64_MSR_SINT9                      0x40000099
#define HV_X64_MSR_SINT10                     0x4000009A
#define HV_X64_MSR_SINT11                     0x4000009B
#define HV_X64_MSR_SINT12                     0x4000009C
#define HV_X64_MSR_SINT13                     0x4000009D
#define HV_X64_MSR_SINT14                     0x4000009E
#define HV_X64_MSR_SINT15                     0x4000009F

/*
 * Synthetic timer MSRs
 */
#define HV_X64_MSR_STIMER0_CONFIG               0x400000B0
#define HV_X64_MSR_STIMER0_COUNT                0x400000B1
#define HV_X64_MSR_STIMER1_CONFIG               0x400000B2
#define HV_X64_MSR_STIMER1_COUNT                0x400000B3
#define HV_X64_MSR_STIMER2_CONFIG               0x400000B4
#define HV_X64_MSR_STIMER2_COUNT                0x400000B5
#define HV_X64_MSR_STIMER3_CONFIG               0x400000B6
#define HV_X64_MSR_STIMER3_COUNT                0x400000B7

/*
 * Guest crash notification MSRs
 */
#define HV_X64_MSR_CRASH_P0                     0x40000100
#define HV_X64_MSR_CRASH_P1                     0x40000101
#define HV_X64_MSR_CRASH_P2                     0x40000102
#define HV_X64_MSR_CRASH_P3                     0x40000103
#define HV_X64_MSR_CRASH_P4                     0x40000104
#define HV_CRASH_PARAMS    (HV_X64_MSR_CRASH_P4 - HV_X64_MSR_CRASH_P0 + 1)
#define HV_X64_MSR_CRASH_CTL                    0x40000105
#define HV_CRASH_CTL_NOTIFY                     (1ull << 63)

/*
 * Reenlightenment notification MSRs
 */
#define HV_X64_MSR_REENLIGHTENMENT_CONTROL      0x40000106
#define HV_X64_MSR_TSC_EMULATION_CONTROL        0x40000107
#define HV_X64_MSR_TSC_EMULATION_STATUS         0x40000108

/*
 * Hypercall MSR bits
 */
#define HV_HYPERCALL_ENABLE                   (1u << 0)

/*
 * Synthetic interrupt controller definitions
 */
#define HV_SYNIC_VERSION                      1
#define HV_SYNIC_ENABLE                       (1u << 0)
#define HV_SIMP_ENABLE                        (1u << 0)
#define HV_SIEFP_ENABLE                       (1u << 0)
#define HV_SINT_MASKED                        (1u << 16)
#define HV_SINT_AUTO_EOI                      (1u << 17)
#define HV_SINT_VECTOR_MASK                   0xff

#define HV_STIMER_COUNT                       4


#endif
Commit	Line	Data
5e953812	1	/*
5116122a	2	* Definitions for Hyper-V guest/hypervisor interaction - x86-specific part
5e953812	3	*
5116122a	4	* Copyright (c) 2017-2018 Virtuozzo International GmbH.
5e953812 RK	5	*
	6	* This work is licensed under the terms of the GNU GPL, version 2 or later.
	7	* See the COPYING file in the top-level directory.
	8	*/
	9
	10	#ifndef TARGET_I386_HYPERV_PROTO_H
	11	#define TARGET_I386_HYPERV_PROTO_H
	12
5116122a	13	#include "hw/hyperv/hyperv-proto.h"
5e953812 RK	14
	15	#define HV_CPUID_VENDOR_AND_MAX_FUNCTIONS 0x40000000
	16	#define HV_CPUID_INTERFACE 0x40000001
	17	#define HV_CPUID_VERSION 0x40000002
	18	#define HV_CPUID_FEATURES 0x40000003
	19	#define HV_CPUID_ENLIGHTMENT_INFO 0x40000004
	20	#define HV_CPUID_IMPLEMENT_LIMITS 0x40000005
e204ac61	21	#define HV_CPUID_NESTED_FEATURES 0x4000000A
5e953812 RK	22	#define HV_CPUID_MIN 0x40000005
	23	#define HV_CPUID_MAX 0x4000ffff
	24	#define HV_HYPERVISOR_PRESENT_BIT 0x80000000
	25
	26	/*
	27	* HV_CPUID_FEATURES.EAX bits
	28	*/
	29	#define HV_VP_RUNTIME_AVAILABLE (1u << 0)
	30	#define HV_TIME_REF_COUNT_AVAILABLE (1u << 1)
	31	#define HV_SYNIC_AVAILABLE (1u << 2)
	32	#define HV_SYNTIMERS_AVAILABLE (1u << 3)
	33	#define HV_APIC_ACCESS_AVAILABLE (1u << 4)
	34	#define HV_HYPERCALL_AVAILABLE (1u << 5)
	35	#define HV_VP_INDEX_AVAILABLE (1u << 6)
	36	#define HV_RESET_AVAILABLE (1u << 7)
	37	#define HV_REFERENCE_TSC_AVAILABLE (1u << 9)
	38	#define HV_ACCESS_FREQUENCY_MSRS (1u << 11)
ba6a4fd9	39	#define HV_ACCESS_REENLIGHTENMENTS_CONTROL (1u << 13)
5e953812 RK	40
	41	/*
	42	* HV_CPUID_FEATURES.EDX bits
	43	*/
	44	#define HV_MWAIT_AVAILABLE (1u << 0)
	45	#define HV_GUEST_DEBUGGING_AVAILABLE (1u << 1)
	46	#define HV_PERF_MONITOR_AVAILABLE (1u << 2)
	47	#define HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE (1u << 3)
	48	#define HV_HYPERCALL_PARAMS_XMM_AVAILABLE (1u << 4)
	49	#define HV_GUEST_IDLE_STATE_AVAILABLE (1u << 5)
	50	#define HV_FREQUENCY_MSRS_AVAILABLE (1u << 8)
	51	#define HV_GUEST_CRASH_MSR_AVAILABLE (1u << 10)
	52
	53	/*
	54	* HV_CPUID_ENLIGHTMENT_INFO.EAX bits
	55	*/
	56	#define HV_AS_SWITCH_RECOMMENDED (1u << 0)
	57	#define HV_LOCAL_TLB_FLUSH_RECOMMENDED (1u << 1)
	58	#define HV_REMOTE_TLB_FLUSH_RECOMMENDED (1u << 2)
	59	#define HV_APIC_ACCESS_RECOMMENDED (1u << 3)
	60	#define HV_SYSTEM_RESET_RECOMMENDED (1u << 4)
	61	#define HV_RELAXED_TIMING_RECOMMENDED (1u << 5)
6b7a9830	62	#define HV_CLUSTER_IPI_RECOMMENDED (1u << 10)
47512009	63	#define HV_EX_PROCESSOR_MASKS_RECOMMENDED (1u << 11)
e204ac61	64	#define HV_ENLIGHTENED_VMCS_RECOMMENDED (1u << 14)
5e953812 RK	65
	66	/*
	67	* Basic virtualized MSRs
	68	*/
	69	#define HV_X64_MSR_GUEST_OS_ID 0x40000000
	70	#define HV_X64_MSR_HYPERCALL 0x40000001
	71	#define HV_X64_MSR_VP_INDEX 0x40000002
	72	#define HV_X64_MSR_RESET 0x40000003
	73	#define HV_X64_MSR_VP_RUNTIME 0x40000010
	74	#define HV_X64_MSR_TIME_REF_COUNT 0x40000020
	75	#define HV_X64_MSR_REFERENCE_TSC 0x40000021
	76	#define HV_X64_MSR_TSC_FREQUENCY 0x40000022
	77	#define HV_X64_MSR_APIC_FREQUENCY 0x40000023
	78
	79	/*
	80	* Virtual APIC MSRs
	81	*/
	82	#define HV_X64_MSR_EOI 0x40000070
	83	#define HV_X64_MSR_ICR 0x40000071
	84	#define HV_X64_MSR_TPR 0x40000072
	85	#define HV_X64_MSR_APIC_ASSIST_PAGE 0x40000073
	86
	87	/*
	88	* Synthetic interrupt controller MSRs
	89	*/
	90	#define HV_X64_MSR_SCONTROL 0x40000080
	91	#define HV_X64_MSR_SVERSION 0x40000081
	92	#define HV_X64_MSR_SIEFP 0x40000082
	93	#define HV_X64_MSR_SIMP 0x40000083
	94	#define HV_X64_MSR_EOM 0x40000084
	95	#define HV_X64_MSR_SINT0 0x40000090
	96	#define HV_X64_MSR_SINT1 0x40000091
	97	#define HV_X64_MSR_SINT2 0x40000092
	98	#define HV_X64_MSR_SINT3 0x40000093
	99	#define HV_X64_MSR_SINT4 0x40000094
	100	#define HV_X64_MSR_SINT5 0x40000095
	101	#define HV_X64_MSR_SINT6 0x40000096
	102	#define HV_X64_MSR_SINT7 0x40000097
	103	#define HV_X64_MSR_SINT8 0x40000098
	104	#define HV_X64_MSR_SINT9 0x40000099
	105	#define HV_X64_MSR_SINT10 0x4000009A
	106	#define HV_X64_MSR_SINT11 0x4000009B
	107	#define HV_X64_MSR_SINT12 0x4000009C
	108	#define HV_X64_MSR_SINT13 0x4000009D
	109	#define HV_X64_MSR_SINT14 0x4000009E
	110	#define HV_X64_MSR_SINT15 0x4000009F
	111
	112	/*
	113	* Synthetic timer MSRs
	114	*/
	115	#define HV_X64_MSR_STIMER0_CONFIG 0x400000B0
	116	#define HV_X64_MSR_STIMER0_COUNT 0x400000B1
	117	#define HV_X64_MSR_STIMER1_CONFIG 0x400000B2
	118	#define HV_X64_MSR_STIMER1_COUNT 0x400000B3
	119	#define HV_X64_MSR_STIMER2_CONFIG 0x400000B4
	120	#define HV_X64_MSR_STIMER2_COUNT 0x400000B5
	121	#define HV_X64_MSR_STIMER3_CONFIG 0x400000B6
	122	#define HV_X64_MSR_STIMER3_COUNT 0x400000B7
	123
	124	/*
	125	* Guest crash notification MSRs
	126	*/
	127	#define HV_X64_MSR_CRASH_P0 0x40000100
	128	#define HV_X64_MSR_CRASH_P1 0x40000101
129	#define HV_X64_MSR_CRASH_P2 0x40000102
130	#define HV_X64_MSR_CRASH_P3 0x40000103
131	#define HV_X64_MSR_CRASH_P4 0x40000104
132	#define HV_CRASH_PARAMS (HV_X64_MSR_CRASH_P4 - HV_X64_MSR_CRASH_P0 + 1)
133	#define HV_X64_MSR_CRASH_CTL 0x40000105
134	#define HV_CRASH_CTL_NOTIFY (1ull << 63)
135
ba6a4fd9 VK	136	/*
	137	* Reenlightenment notification MSRs
	138	*/
	139	#define HV_X64_MSR_REENLIGHTENMENT_CONTROL 0x40000106
	140	#define HV_X64_MSR_TSC_EMULATION_CONTROL 0x40000107
	141	#define HV_X64_MSR_TSC_EMULATION_STATUS 0x40000108
	142
5e953812 RK	143	/*
	144	* Hypercall MSR bits
	145	*/
	146	#define HV_HYPERCALL_ENABLE (1u << 0)
	147
	148	/*
	149	* Synthetic interrupt controller definitions
	150	*/
	151	#define HV_SYNIC_VERSION 1
5e953812 RK	152	#define HV_SYNIC_ENABLE (1u << 0)
	153	#define HV_SIMP_ENABLE (1u << 0)
	154	#define HV_SIEFP_ENABLE (1u << 0)
	155	#define HV_SINT_MASKED (1u << 16)
	156	#define HV_SINT_AUTO_EOI (1u << 17)
	157	#define HV_SINT_VECTOR_MASK 0xff
	158
	159	#define HV_STIMER_COUNT 4
	160
5e953812 RK	161
5e953812 RK	162	#endif