[mirror_qemu.git] / target / i386 / kvm / hyperv-proto.h

/*
 * Definitions for Hyper-V guest/hypervisor interaction - x86-specific part
 *
 * Copyright (c) 2017-2018 Virtuozzo International GmbH.
 *
 * This work is licensed under the terms of the GNU GPL, version 2 or later.
 * See the COPYING file in the top-level directory.
 */

#ifndef TARGET_I386_HYPERV_PROTO_H
#define TARGET_I386_HYPERV_PROTO_H

#include "hw/hyperv/hyperv-proto.h"

#define HV_CPUID_VENDOR_AND_MAX_FUNCTIONS     0x40000000
#define HV_CPUID_INTERFACE                    0x40000001
#define HV_CPUID_VERSION                      0x40000002
#define HV_CPUID_FEATURES                     0x40000003
#define HV_CPUID_ENLIGHTMENT_INFO             0x40000004
#define HV_CPUID_IMPLEMENT_LIMITS             0x40000005
#define HV_CPUID_NESTED_FEATURES              0x4000000A
#define HV_CPUID_SYNDBG_VENDOR_AND_MAX_FUNCTIONS    0x40000080
#define HV_CPUID_SYNDBG_INTERFACE                   0x40000081
#define HV_CPUID_SYNDBG_PLATFORM_CAPABILITIES       0x40000082
#define HV_CPUID_MIN                          0x40000005
#define HV_CPUID_MAX                          0x4000ffff
#define HV_HYPERVISOR_PRESENT_BIT             0x80000000

/*
 * HV_CPUID_FEATURES.EAX bits
 */
#define HV_VP_RUNTIME_AVAILABLE      (1u << 0)
#define HV_TIME_REF_COUNT_AVAILABLE  (1u << 1)
#define HV_SYNIC_AVAILABLE           (1u << 2)
#define HV_SYNTIMERS_AVAILABLE       (1u << 3)
#define HV_APIC_ACCESS_AVAILABLE     (1u << 4)
#define HV_HYPERCALL_AVAILABLE       (1u << 5)
#define HV_VP_INDEX_AVAILABLE        (1u << 6)
#define HV_RESET_AVAILABLE           (1u << 7)
#define HV_REFERENCE_TSC_AVAILABLE   (1u << 9)
#define HV_ACCESS_FREQUENCY_MSRS     (1u << 11)
#define HV_ACCESS_REENLIGHTENMENTS_CONTROL  (1u << 13)

/*
 * HV_CPUID_FEATURES.EBX bits
 */
#define HV_POST_MESSAGES             (1u << 4)
#define HV_SIGNAL_EVENTS             (1u << 5)

/*
 * HV_CPUID_FEATURES.EDX bits
 */
#define HV_MWAIT_AVAILABLE                      (1u << 0)
#define HV_GUEST_DEBUGGING_AVAILABLE            (1u << 1)
#define HV_PERF_MONITOR_AVAILABLE               (1u << 2)
#define HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE   (1u << 3)
#define HV_HYPERCALL_PARAMS_XMM_AVAILABLE       (1u << 4)
#define HV_GUEST_IDLE_STATE_AVAILABLE           (1u << 5)
#define HV_FREQUENCY_MSRS_AVAILABLE             (1u << 8)
#define HV_GUEST_CRASH_MSR_AVAILABLE            (1u << 10)
#define HV_FEATURE_DEBUG_MSRS_AVAILABLE         (1u << 11)
#define HV_STIMER_DIRECT_MODE_AVAILABLE         (1u << 19)

/*
 * HV_CPUID_FEATURES.EBX bits
 */
#define HV_PARTITION_DEBUGGING_ALLOWED          (1u << 12)

/*
 * HV_CPUID_ENLIGHTMENT_INFO.EAX bits
 */
#define HV_AS_SWITCH_RECOMMENDED            (1u << 0)
#define HV_LOCAL_TLB_FLUSH_RECOMMENDED      (1u << 1)
#define HV_REMOTE_TLB_FLUSH_RECOMMENDED     (1u << 2)
#define HV_APIC_ACCESS_RECOMMENDED          (1u << 3)
#define HV_SYSTEM_RESET_RECOMMENDED         (1u << 4)
#define HV_RELAXED_TIMING_RECOMMENDED       (1u << 5)
#define HV_DEPRECATING_AEOI_RECOMMENDED     (1u << 9)
#define HV_CLUSTER_IPI_RECOMMENDED          (1u << 10)
#define HV_EX_PROCESSOR_MASKS_RECOMMENDED   (1u << 11)
#define HV_ENLIGHTENED_VMCS_RECOMMENDED     (1u << 14)
#define HV_NO_NONARCH_CORESHARING           (1u << 18)

/*
 * HV_CPUID_SYNDBG_PLATFORM_CAPABILITIES.EAX bits
 */
#define HV_SYNDBG_CAP_ALLOW_KERNEL_DEBUGGING    (1u << 1)

/*
 * Basic virtualized MSRs
 */
#define HV_X64_MSR_GUEST_OS_ID                0x40000000
#define HV_X64_MSR_HYPERCALL                  0x40000001
#define HV_X64_MSR_VP_INDEX                   0x40000002
#define HV_X64_MSR_RESET                      0x40000003
#define HV_X64_MSR_VP_RUNTIME                 0x40000010
#define HV_X64_MSR_TIME_REF_COUNT             0x40000020
#define HV_X64_MSR_REFERENCE_TSC              0x40000021
#define HV_X64_MSR_TSC_FREQUENCY              0x40000022
#define HV_X64_MSR_APIC_FREQUENCY             0x40000023

/*
 * Virtual APIC MSRs
 */
#define HV_X64_MSR_EOI                        0x40000070
#define HV_X64_MSR_ICR                        0x40000071
#define HV_X64_MSR_TPR                        0x40000072
#define HV_X64_MSR_APIC_ASSIST_PAGE           0x40000073

/*
 * Synthetic interrupt controller MSRs
 */
#define HV_X64_MSR_SCONTROL                   0x40000080
#define HV_X64_MSR_SVERSION                   0x40000081
#define HV_X64_MSR_SIEFP                      0x40000082
#define HV_X64_MSR_SIMP                       0x40000083
#define HV_X64_MSR_EOM                        0x40000084
#define HV_X64_MSR_SINT0                      0x40000090
#define HV_X64_MSR_SINT1                      0x40000091
#define HV_X64_MSR_SINT2                      0x40000092
#define HV_X64_MSR_SINT3                      0x40000093
#define HV_X64_MSR_SINT4                      0x40000094
#define HV_X64_MSR_SINT5                      0x40000095
#define HV_X64_MSR_SINT6                      0x40000096
#define HV_X64_MSR_SINT7                      0x40000097
#define HV_X64_MSR_SINT8                      0x40000098
#define HV_X64_MSR_SINT9                      0x40000099
#define HV_X64_MSR_SINT10                     0x4000009A
#define HV_X64_MSR_SINT11                     0x4000009B
#define HV_X64_MSR_SINT12                     0x4000009C
#define HV_X64_MSR_SINT13                     0x4000009D
#define HV_X64_MSR_SINT14                     0x4000009E
#define HV_X64_MSR_SINT15                     0x4000009F

/*
 * Synthetic timer MSRs
 */
#define HV_X64_MSR_STIMER0_CONFIG               0x400000B0
#define HV_X64_MSR_STIMER0_COUNT                0x400000B1
#define HV_X64_MSR_STIMER1_CONFIG               0x400000B2
#define HV_X64_MSR_STIMER1_COUNT                0x400000B3
#define HV_X64_MSR_STIMER2_CONFIG               0x400000B4
#define HV_X64_MSR_STIMER2_COUNT                0x400000B5
#define HV_X64_MSR_STIMER3_CONFIG               0x400000B6
#define HV_X64_MSR_STIMER3_COUNT                0x400000B7

/*
 * Hyper-V Synthetic debug options MSR
 */
#define HV_X64_MSR_SYNDBG_CONTROL               0x400000F1
#define HV_X64_MSR_SYNDBG_STATUS                0x400000F2
#define HV_X64_MSR_SYNDBG_SEND_BUFFER           0x400000F3
#define HV_X64_MSR_SYNDBG_RECV_BUFFER           0x400000F4
#define HV_X64_MSR_SYNDBG_PENDING_BUFFER        0x400000F5
#define HV_X64_MSR_SYNDBG_OPTIONS               0x400000FF

#define HV_X64_SYNDBG_OPTION_USE_HCALLS         BIT(2)

/*
 * Guest crash notification MSRs
 */
#define HV_X64_MSR_CRASH_P0                     0x40000100
#define HV_X64_MSR_CRASH_P1                     0x40000101
#define HV_X64_MSR_CRASH_P2                     0x40000102
#define HV_X64_MSR_CRASH_P3                     0x40000103
#define HV_X64_MSR_CRASH_P4                     0x40000104
#define HV_CRASH_PARAMS    (HV_X64_MSR_CRASH_P4 - HV_X64_MSR_CRASH_P0 + 1)
#define HV_X64_MSR_CRASH_CTL                    0x40000105
#define HV_CRASH_CTL_NOTIFY                     (1ull << 63)

/*
 * Reenlightenment notification MSRs
 */
#define HV_X64_MSR_REENLIGHTENMENT_CONTROL      0x40000106
#define HV_REENLIGHTENMENT_ENABLE_BIT           (1u << 16)
#define HV_X64_MSR_TSC_EMULATION_CONTROL        0x40000107
#define HV_X64_MSR_TSC_EMULATION_STATUS         0x40000108

/*
 * Hypercall MSR bits
 */
#define HV_HYPERCALL_ENABLE                   (1u << 0)

/*
 * Synthetic interrupt controller definitions
 */
#define HV_SYNIC_VERSION                      1
#define HV_SYNIC_ENABLE                       (1u << 0)
#define HV_SIMP_ENABLE                        (1u << 0)
#define HV_SIEFP_ENABLE                       (1u << 0)
#define HV_SINT_MASKED                        (1u << 16)
#define HV_SINT_AUTO_EOI                      (1u << 17)
#define HV_SINT_VECTOR_MASK                   0xff

#define HV_STIMER_COUNT                       4

/*
 * Synthetic debugger control definitions
 */
#define HV_SYNDBG_CONTROL_SEND              (1u << 0)
#define HV_SYNDBG_CONTROL_RECV              (1u << 1)
#define HV_SYNDBG_CONTROL_SEND_SIZE(ctl)    ((ctl >> 16) & 0xffff)
#define HV_SYNDBG_STATUS_INVALID            (0)
#define HV_SYNDBG_STATUS_SEND_SUCCESS       (1u << 0)
#define HV_SYNDBG_STATUS_RECV_SUCCESS       (1u << 2)
#define HV_SYNDBG_STATUS_RESET              (1u << 3)
#define HV_SYNDBG_STATUS_SET_SIZE(st, sz)   (st | (sz << 16))

#endif
Commit	Line	Data
5e953812	1	/*
5116122a	2	* Definitions for Hyper-V guest/hypervisor interaction - x86-specific part
5e953812	3	*
5116122a	4	* Copyright (c) 2017-2018 Virtuozzo International GmbH.
5e953812 RK	5	*
	6	* This work is licensed under the terms of the GNU GPL, version 2 or later.
	7	* See the COPYING file in the top-level directory.
	8	*/
	9
	10	#ifndef TARGET_I386_HYPERV_PROTO_H
	11	#define TARGET_I386_HYPERV_PROTO_H
	12
5116122a	13	#include "hw/hyperv/hyperv-proto.h"
5e953812 RK	14
	15	#define HV_CPUID_VENDOR_AND_MAX_FUNCTIONS 0x40000000
	16	#define HV_CPUID_INTERFACE 0x40000001
	17	#define HV_CPUID_VERSION 0x40000002
	18	#define HV_CPUID_FEATURES 0x40000003
	19	#define HV_CPUID_ENLIGHTMENT_INFO 0x40000004
	20	#define HV_CPUID_IMPLEMENT_LIMITS 0x40000005
e204ac61	21	#define HV_CPUID_NESTED_FEATURES 0x4000000A
ccbdf5e8 JD	22	#define HV_CPUID_SYNDBG_VENDOR_AND_MAX_FUNCTIONS 0x40000080
	23	#define HV_CPUID_SYNDBG_INTERFACE 0x40000081
	24	#define HV_CPUID_SYNDBG_PLATFORM_CAPABILITIES 0x40000082
5e953812 RK	25	#define HV_CPUID_MIN 0x40000005
	26	#define HV_CPUID_MAX 0x4000ffff
	27	#define HV_HYPERVISOR_PRESENT_BIT 0x80000000
	28
	29	/*
	30	* HV_CPUID_FEATURES.EAX bits
	31	*/
	32	#define HV_VP_RUNTIME_AVAILABLE (1u << 0)
	33	#define HV_TIME_REF_COUNT_AVAILABLE (1u << 1)
	34	#define HV_SYNIC_AVAILABLE (1u << 2)
	35	#define HV_SYNTIMERS_AVAILABLE (1u << 3)
	36	#define HV_APIC_ACCESS_AVAILABLE (1u << 4)
	37	#define HV_HYPERCALL_AVAILABLE (1u << 5)
	38	#define HV_VP_INDEX_AVAILABLE (1u << 6)
	39	#define HV_RESET_AVAILABLE (1u << 7)
	40	#define HV_REFERENCE_TSC_AVAILABLE (1u << 9)
	41	#define HV_ACCESS_FREQUENCY_MSRS (1u << 11)
ba6a4fd9	42	#define HV_ACCESS_REENLIGHTENMENTS_CONTROL (1u << 13)
5e953812	43
cce087f6 VK	44	/*
	45	* HV_CPUID_FEATURES.EBX bits
	46	*/
	47	#define HV_POST_MESSAGES (1u << 4)
	48	#define HV_SIGNAL_EVENTS (1u << 5)
	49
5e953812 RK	50	/*
	51	* HV_CPUID_FEATURES.EDX bits
	52	*/
	53	#define HV_MWAIT_AVAILABLE (1u << 0)
	54	#define HV_GUEST_DEBUGGING_AVAILABLE (1u << 1)
	55	#define HV_PERF_MONITOR_AVAILABLE (1u << 2)
	56	#define HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE (1u << 3)
	57	#define HV_HYPERCALL_PARAMS_XMM_AVAILABLE (1u << 4)
	58	#define HV_GUEST_IDLE_STATE_AVAILABLE (1u << 5)
	59	#define HV_FREQUENCY_MSRS_AVAILABLE (1u << 8)
	60	#define HV_GUEST_CRASH_MSR_AVAILABLE (1u << 10)
ccbdf5e8	61	#define HV_FEATURE_DEBUG_MSRS_AVAILABLE (1u << 11)
128531d9	62	#define HV_STIMER_DIRECT_MODE_AVAILABLE (1u << 19)
5e953812	63
ccbdf5e8 JD	64	/*
	65	* HV_CPUID_FEATURES.EBX bits
	66	*/
	67	#define HV_PARTITION_DEBUGGING_ALLOWED (1u << 12)
	68
5e953812 RK	69	/*
	70	* HV_CPUID_ENLIGHTMENT_INFO.EAX bits
	71	*/
	72	#define HV_AS_SWITCH_RECOMMENDED (1u << 0)
	73	#define HV_LOCAL_TLB_FLUSH_RECOMMENDED (1u << 1)
	74	#define HV_REMOTE_TLB_FLUSH_RECOMMENDED (1u << 2)
	75	#define HV_APIC_ACCESS_RECOMMENDED (1u << 3)
	76	#define HV_SYSTEM_RESET_RECOMMENDED (1u << 4)
	77	#define HV_RELAXED_TIMING_RECOMMENDED (1u << 5)
e1f9a8e8	78	#define HV_DEPRECATING_AEOI_RECOMMENDED (1u << 9)
6b7a9830	79	#define HV_CLUSTER_IPI_RECOMMENDED (1u << 10)
47512009	80	#define HV_EX_PROCESSOR_MASKS_RECOMMENDED (1u << 11)
e204ac61	81	#define HV_ENLIGHTENED_VMCS_RECOMMENDED (1u << 14)
30d6ff66	82	#define HV_NO_NONARCH_CORESHARING (1u << 18)
5e953812	83
ccbdf5e8 JD	84	/*
	85	* HV_CPUID_SYNDBG_PLATFORM_CAPABILITIES.EAX bits
	86	*/
	87	#define HV_SYNDBG_CAP_ALLOW_KERNEL_DEBUGGING (1u << 1)
	88
5e953812 RK	89	/*
	90	* Basic virtualized MSRs
	91	*/
	92	#define HV_X64_MSR_GUEST_OS_ID 0x40000000
	93	#define HV_X64_MSR_HYPERCALL 0x40000001
	94	#define HV_X64_MSR_VP_INDEX 0x40000002
	95	#define HV_X64_MSR_RESET 0x40000003
	96	#define HV_X64_MSR_VP_RUNTIME 0x40000010
	97	#define HV_X64_MSR_TIME_REF_COUNT 0x40000020
	98	#define HV_X64_MSR_REFERENCE_TSC 0x40000021
	99	#define HV_X64_MSR_TSC_FREQUENCY 0x40000022
	100	#define HV_X64_MSR_APIC_FREQUENCY 0x40000023
	101
	102	/*
	103	* Virtual APIC MSRs
	104	*/
	105	#define HV_X64_MSR_EOI 0x40000070
	106	#define HV_X64_MSR_ICR 0x40000071
	107	#define HV_X64_MSR_TPR 0x40000072
	108	#define HV_X64_MSR_APIC_ASSIST_PAGE 0x40000073
	109
	110	/*
	111	* Synthetic interrupt controller MSRs
	112	*/
	113	#define HV_X64_MSR_SCONTROL 0x40000080
	114	#define HV_X64_MSR_SVERSION 0x40000081
	115	#define HV_X64_MSR_SIEFP 0x40000082
	116	#define HV_X64_MSR_SIMP 0x40000083
	117	#define HV_X64_MSR_EOM 0x40000084
	118	#define HV_X64_MSR_SINT0 0x40000090
	119	#define HV_X64_MSR_SINT1 0x40000091
	120	#define HV_X64_MSR_SINT2 0x40000092
	121	#define HV_X64_MSR_SINT3 0x40000093
	122	#define HV_X64_MSR_SINT4 0x40000094
	123	#define HV_X64_MSR_SINT5 0x40000095
	124	#define HV_X64_MSR_SINT6 0x40000096
	125	#define HV_X64_MSR_SINT7 0x40000097
	126	#define HV_X64_MSR_SINT8 0x40000098
	127	#define HV_X64_MSR_SINT9 0x40000099
	128	#define HV_X64_MSR_SINT10 0x4000009A
	129	#define HV_X64_MSR_SINT11 0x4000009B
	130	#define HV_X64_MSR_SINT12 0x4000009C
	131	#define HV_X64_MSR_SINT13 0x4000009D
	132	#define HV_X64_MSR_SINT14 0x4000009E
	133	#define HV_X64_MSR_SINT15 0x4000009F
	134
	135	/*
	136	* Synthetic timer MSRs
	137	*/
	138	#define HV_X64_MSR_STIMER0_CONFIG 0x400000B0
	139	#define HV_X64_MSR_STIMER0_COUNT 0x400000B1
	140	#define HV_X64_MSR_STIMER1_CONFIG 0x400000B2
	141	#define HV_X64_MSR_STIMER1_COUNT 0x400000B3
	142	#define HV_X64_MSR_STIMER2_CONFIG 0x400000B4
	143	#define HV_X64_MSR_STIMER2_COUNT 0x400000B5
	144	#define HV_X64_MSR_STIMER3_CONFIG 0x400000B6
	145	#define HV_X64_MSR_STIMER3_COUNT 0x400000B7
	146
ccbdf5e8 JD	147	/*
	148	* Hyper-V Synthetic debug options MSR
	149	*/
	150	#define HV_X64_MSR_SYNDBG_CONTROL 0x400000F1
	151	#define HV_X64_MSR_SYNDBG_STATUS 0x400000F2
	152	#define HV_X64_MSR_SYNDBG_SEND_BUFFER 0x400000F3
	153	#define HV_X64_MSR_SYNDBG_RECV_BUFFER 0x400000F4
	154	#define HV_X64_MSR_SYNDBG_PENDING_BUFFER 0x400000F5
	155	#define HV_X64_MSR_SYNDBG_OPTIONS 0x400000FF
	156
	157	#define HV_X64_SYNDBG_OPTION_USE_HCALLS BIT(2)
	158
5e953812 RK	159	/*
	160	* Guest crash notification MSRs
	161	*/
	162	#define HV_X64_MSR_CRASH_P0 0x40000100
	163	#define HV_X64_MSR_CRASH_P1 0x40000101
	164	#define HV_X64_MSR_CRASH_P2 0x40000102
	165	#define HV_X64_MSR_CRASH_P3 0x40000103
	166	#define HV_X64_MSR_CRASH_P4 0x40000104
	167	#define HV_CRASH_PARAMS (HV_X64_MSR_CRASH_P4 - HV_X64_MSR_CRASH_P0 + 1)
	168	#define HV_X64_MSR_CRASH_CTL 0x40000105
	169	#define HV_CRASH_CTL_NOTIFY (1ull << 63)
	170
ba6a4fd9 VK	171	/*
	172	* Reenlightenment notification MSRs
	173	*/
	174	#define HV_X64_MSR_REENLIGHTENMENT_CONTROL 0x40000106
561dbb41	175	#define HV_REENLIGHTENMENT_ENABLE_BIT (1u << 16)
ba6a4fd9 VK	176	#define HV_X64_MSR_TSC_EMULATION_CONTROL 0x40000107
	177	#define HV_X64_MSR_TSC_EMULATION_STATUS 0x40000108
	178
5e953812 RK	179	/*
	180	* Hypercall MSR bits
	181	*/
	182	#define HV_HYPERCALL_ENABLE (1u << 0)
	183
	184	/*
	185	* Synthetic interrupt controller definitions
	186	*/
	187	#define HV_SYNIC_VERSION 1
5e953812 RK	188	#define HV_SYNIC_ENABLE (1u << 0)
	189	#define HV_SIMP_ENABLE (1u << 0)
	190	#define HV_SIEFP_ENABLE (1u << 0)
	191	#define HV_SINT_MASKED (1u << 16)
	192	#define HV_SINT_AUTO_EOI (1u << 17)
	193	#define HV_SINT_VECTOR_MASK 0xff
	194
	195	#define HV_STIMER_COUNT 4
	196
ccbdf5e8 JD	197	/*
	198	* Synthetic debugger control definitions
	199	*/
	200	#define HV_SYNDBG_CONTROL_SEND (1u << 0)
	201	#define HV_SYNDBG_CONTROL_RECV (1u << 1)
	202	#define HV_SYNDBG_CONTROL_SEND_SIZE(ctl) ((ctl >> 16) & 0xffff)
	203	#define HV_SYNDBG_STATUS_INVALID (0)
	204	#define HV_SYNDBG_STATUS_SEND_SUCCESS (1u << 0)
	205	#define HV_SYNDBG_STATUS_RECV_SUCCESS (1u << 2)
	206	#define HV_SYNDBG_STATUS_RESET (1u << 3)
	207	#define HV_SYNDBG_STATUS_SET_SIZE(st, sz) (st \| (sz << 16))
5e953812 RK	208
5e953812 RK	209	#endif