[mirror_qemu.git] / target / i386 / misc_helper.c

/*
 *  x86 misc helpers
 *
 *  Copyright (c) 2003 Fabrice Bellard
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#include "qemu/osdep.h"
#include "qemu/main-loop.h"
#include "cpu.h"
#include "exec/helper-proto.h"
#include "exec/exec-all.h"
#include "exec/cpu_ldst.h"
#include "exec/address-spaces.h"

void helper_outb(CPUX86State *env, uint32_t port, uint32_t data)
{
#ifdef CONFIG_USER_ONLY
    fprintf(stderr, "outb: port=0x%04x, data=%02x\n", port, data);
#else
    address_space_stb(&address_space_io, port, data,
                      cpu_get_mem_attrs(env), NULL);
#endif
}

target_ulong helper_inb(CPUX86State *env, uint32_t port)
{
#ifdef CONFIG_USER_ONLY
    fprintf(stderr, "inb: port=0x%04x\n", port);
    return 0;
#else
    return address_space_ldub(&address_space_io, port,
                              cpu_get_mem_attrs(env), NULL);
#endif
}

void helper_outw(CPUX86State *env, uint32_t port, uint32_t data)
{
#ifdef CONFIG_USER_ONLY
    fprintf(stderr, "outw: port=0x%04x, data=%04x\n", port, data);
#else
    address_space_stw(&address_space_io, port, data,
                      cpu_get_mem_attrs(env), NULL);
#endif
}

target_ulong helper_inw(CPUX86State *env, uint32_t port)
{
#ifdef CONFIG_USER_ONLY
    fprintf(stderr, "inw: port=0x%04x\n", port);
    return 0;
#else
    return address_space_lduw(&address_space_io, port,
                              cpu_get_mem_attrs(env), NULL);
#endif
}

void helper_outl(CPUX86State *env, uint32_t port, uint32_t data)
{
#ifdef CONFIG_USER_ONLY
    fprintf(stderr, "outw: port=0x%04x, data=%08x\n", port, data);
#else
    address_space_stl(&address_space_io, port, data,
                      cpu_get_mem_attrs(env), NULL);
#endif
}

target_ulong helper_inl(CPUX86State *env, uint32_t port)
{
#ifdef CONFIG_USER_ONLY
    fprintf(stderr, "inl: port=0x%04x\n", port);
    return 0;
#else
    return address_space_ldl(&address_space_io, port,
                             cpu_get_mem_attrs(env), NULL);
#endif
}

void helper_into(CPUX86State *env, int next_eip_addend)
{
    int eflags;

    eflags = cpu_cc_compute_all(env, CC_OP);
    if (eflags & CC_O) {
        raise_interrupt(env, EXCP04_INTO, 1, 0, next_eip_addend);
    }
}

void helper_cpuid(CPUX86State *env)
{
    uint32_t eax, ebx, ecx, edx;

    cpu_svm_check_intercept_param(env, SVM_EXIT_CPUID, 0, GETPC());

    cpu_x86_cpuid(env, (uint32_t)env->regs[R_EAX], (uint32_t)env->regs[R_ECX],
                  &eax, &ebx, &ecx, &edx);
    env->regs[R_EAX] = eax;
    env->regs[R_EBX] = ebx;
    env->regs[R_ECX] = ecx;
    env->regs[R_EDX] = edx;
}

#if defined(CONFIG_USER_ONLY)
target_ulong helper_read_crN(CPUX86State *env, int reg)
{
    return 0;
}

void helper_write_crN(CPUX86State *env, int reg, target_ulong t0)
{
}
#else
target_ulong helper_read_crN(CPUX86State *env, int reg)
{
    target_ulong val;

    cpu_svm_check_intercept_param(env, SVM_EXIT_READ_CR0 + reg, 0, GETPC());
    switch (reg) {
    default:
        val = env->cr[reg];
        break;
    case 8:
        if (!(env->hflags2 & HF2_VINTR_MASK)) {
            val = cpu_get_apic_tpr(x86_env_get_cpu(env)->apic_state);
        } else {
            val = env->v_tpr;
        }
        break;
    }
    return val;
}

void helper_write_crN(CPUX86State *env, int reg, target_ulong t0)
{
    cpu_svm_check_intercept_param(env, SVM_EXIT_WRITE_CR0 + reg, 0, GETPC());
    switch (reg) {
    case 0:
        cpu_x86_update_cr0(env, t0);
        break;
    case 3:
        cpu_x86_update_cr3(env, t0);
        break;
    case 4:
        cpu_x86_update_cr4(env, t0);
        break;
    case 8:
        if (!(env->hflags2 & HF2_VINTR_MASK)) {
            qemu_mutex_lock_iothread();
            cpu_set_apic_tpr(x86_env_get_cpu(env)->apic_state, t0);
            qemu_mutex_unlock_iothread();
        }
        env->v_tpr = t0 & 0x0f;
        break;
    default:
        env->cr[reg] = t0;
        break;
    }
}
#endif

void helper_lmsw(CPUX86State *env, target_ulong t0)
{
    /* only 4 lower bits of CR0 are modified. PE cannot be set to zero
       if already set to one. */
    t0 = (env->cr[0] & ~0xe) | (t0 & 0xf);
    helper_write_crN(env, 0, t0);
}

void helper_invlpg(CPUX86State *env, target_ulong addr)
{
    X86CPU *cpu = x86_env_get_cpu(env);

    cpu_svm_check_intercept_param(env, SVM_EXIT_INVLPG, 0, GETPC());
    tlb_flush_page(CPU(cpu), addr);
}

void helper_rdtsc(CPUX86State *env)
{
    uint64_t val;

    if ((env->cr[4] & CR4_TSD_MASK) && ((env->hflags & HF_CPL_MASK) != 0)) {
        raise_exception_ra(env, EXCP0D_GPF, GETPC());
    }
    cpu_svm_check_intercept_param(env, SVM_EXIT_RDTSC, 0, GETPC());

    val = cpu_get_tsc(env) + env->tsc_offset;
    env->regs[R_EAX] = (uint32_t)(val);
    env->regs[R_EDX] = (uint32_t)(val >> 32);
}

void helper_rdtscp(CPUX86State *env)
{
    helper_rdtsc(env);
    env->regs[R_ECX] = (uint32_t)(env->tsc_aux);
}

void helper_rdpmc(CPUX86State *env)
{
    if ((env->cr[4] & CR4_PCE_MASK) && ((env->hflags & HF_CPL_MASK) != 0)) {
        raise_exception_ra(env, EXCP0D_GPF, GETPC());
    }
    cpu_svm_check_intercept_param(env, SVM_EXIT_RDPMC, 0, GETPC());

    /* currently unimplemented */
    qemu_log_mask(LOG_UNIMP, "x86: unimplemented rdpmc\n");
    raise_exception_err(env, EXCP06_ILLOP, 0);
}

#if defined(CONFIG_USER_ONLY)
void helper_wrmsr(CPUX86State *env)
{
}

void helper_rdmsr(CPUX86State *env)
{
}
#else
void helper_wrmsr(CPUX86State *env)
{
    uint64_t val;

    cpu_svm_check_intercept_param(env, SVM_EXIT_MSR, 1, GETPC());

    val = ((uint32_t)env->regs[R_EAX]) |
        ((uint64_t)((uint32_t)env->regs[R_EDX]) << 32);

    switch ((uint32_t)env->regs[R_ECX]) {
    case MSR_IA32_SYSENTER_CS:
        env->sysenter_cs = val & 0xffff;
        break;
    case MSR_IA32_SYSENTER_ESP:
        env->sysenter_esp = val;
        break;
    case MSR_IA32_SYSENTER_EIP:
        env->sysenter_eip = val;
        break;
    case MSR_IA32_APICBASE:
        cpu_set_apic_base(x86_env_get_cpu(env)->apic_state, val);
        break;
    case MSR_EFER:
        {
            uint64_t update_mask;

            update_mask = 0;
            if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_SYSCALL) {
                update_mask |= MSR_EFER_SCE;
            }
            if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
                update_mask |= MSR_EFER_LME;
            }
            if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_FFXSR) {
                update_mask |= MSR_EFER_FFXSR;
            }
            if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_NX) {
                update_mask |= MSR_EFER_NXE;
            }
            if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
                update_mask |= MSR_EFER_SVME;
            }
            if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_FFXSR) {
                update_mask |= MSR_EFER_FFXSR;
            }
            cpu_load_efer(env, (env->efer & ~update_mask) |
                          (val & update_mask));
        }
        break;
    case MSR_STAR:
        env->star = val;
        break;
    case MSR_PAT:
        env->pat = val;
        break;
    case MSR_VM_HSAVE_PA:
        env->vm_hsave = val;
        break;
#ifdef TARGET_X86_64
    case MSR_LSTAR:
        env->lstar = val;
        break;
    case MSR_CSTAR:
        env->cstar = val;
        break;
    case MSR_FMASK:
        env->fmask = val;
        break;
    case MSR_FSBASE:
        env->segs[R_FS].base = val;
        break;
    case MSR_GSBASE:
        env->segs[R_GS].base = val;
        break;
    case MSR_KERNELGSBASE:
        env->kernelgsbase = val;
        break;
#endif
    case MSR_MTRRphysBase(0):
    case MSR_MTRRphysBase(1):
    case MSR_MTRRphysBase(2):
    case MSR_MTRRphysBase(3):
    case MSR_MTRRphysBase(4):
    case MSR_MTRRphysBase(5):
    case MSR_MTRRphysBase(6):
    case MSR_MTRRphysBase(7):
        env->mtrr_var[((uint32_t)env->regs[R_ECX] -
                       MSR_MTRRphysBase(0)) / 2].base = val;
        break;
    case MSR_MTRRphysMask(0):
    case MSR_MTRRphysMask(1):
    case MSR_MTRRphysMask(2):
    case MSR_MTRRphysMask(3):
    case MSR_MTRRphysMask(4):
    case MSR_MTRRphysMask(5):
    case MSR_MTRRphysMask(6):
    case MSR_MTRRphysMask(7):
        env->mtrr_var[((uint32_t)env->regs[R_ECX] -
                       MSR_MTRRphysMask(0)) / 2].mask = val;
        break;
    case MSR_MTRRfix64K_00000:
        env->mtrr_fixed[(uint32_t)env->regs[R_ECX] -
                        MSR_MTRRfix64K_00000] = val;
        break;
    case MSR_MTRRfix16K_80000:
    case MSR_MTRRfix16K_A0000:
        env->mtrr_fixed[(uint32_t)env->regs[R_ECX] -
                        MSR_MTRRfix16K_80000 + 1] = val;
        break;
    case MSR_MTRRfix4K_C0000:
    case MSR_MTRRfix4K_C8000:
    case MSR_MTRRfix4K_D0000:
    case MSR_MTRRfix4K_D8000:
    case MSR_MTRRfix4K_E0000:
    case MSR_MTRRfix4K_E8000:
    case MSR_MTRRfix4K_F0000:
    case MSR_MTRRfix4K_F8000:
        env->mtrr_fixed[(uint32_t)env->regs[R_ECX] -
                        MSR_MTRRfix4K_C0000 + 3] = val;
        break;
    case MSR_MTRRdefType:
        env->mtrr_deftype = val;
        break;
    case MSR_MCG_STATUS:
        env->mcg_status = val;
        break;
    case MSR_MCG_CTL:
        if ((env->mcg_cap & MCG_CTL_P)
            && (val == 0 || val == ~(uint64_t)0)) {
            env->mcg_ctl = val;
        }
        break;
    case MSR_TSC_AUX:
        env->tsc_aux = val;
        break;
    case MSR_IA32_MISC_ENABLE:
        env->msr_ia32_misc_enable = val;
        break;
    case MSR_IA32_BNDCFGS:
        /* FIXME: #GP if reserved bits are set.  */
        /* FIXME: Extend highest implemented bit of linear address.  */
        env->msr_bndcfgs = val;
        cpu_sync_bndcs_hflags(env);
        break;
    default:
        if ((uint32_t)env->regs[R_ECX] >= MSR_MC0_CTL
            && (uint32_t)env->regs[R_ECX] < MSR_MC0_CTL +
            (4 * env->mcg_cap & 0xff)) {
            uint32_t offset = (uint32_t)env->regs[R_ECX] - MSR_MC0_CTL;
            if ((offset & 0x3) != 0
                || (val == 0 || val == ~(uint64_t)0)) {
                env->mce_banks[offset] = val;
            }
            break;
        }
        /* XXX: exception? */
        break;
    }
}

void helper_rdmsr(CPUX86State *env)
{
    uint64_t val;

    cpu_svm_check_intercept_param(env, SVM_EXIT_MSR, 0, GETPC());

    switch ((uint32_t)env->regs[R_ECX]) {
    case MSR_IA32_SYSENTER_CS:
        val = env->sysenter_cs;
        break;
    case MSR_IA32_SYSENTER_ESP:
        val = env->sysenter_esp;
        break;
    case MSR_IA32_SYSENTER_EIP:
        val = env->sysenter_eip;
        break;
    case MSR_IA32_APICBASE:
        val = cpu_get_apic_base(x86_env_get_cpu(env)->apic_state);
        break;
    case MSR_EFER:
        val = env->efer;
        break;
    case MSR_STAR:
        val = env->star;
        break;
    case MSR_PAT:
        val = env->pat;
        break;
    case MSR_VM_HSAVE_PA:
        val = env->vm_hsave;
        break;
    case MSR_IA32_PERF_STATUS:
        /* tsc_increment_by_tick */
        val = 1000ULL;
        /* CPU multiplier */
        val |= (((uint64_t)4ULL) << 40);
        break;
#ifdef TARGET_X86_64
    case MSR_LSTAR:
        val = env->lstar;
        break;
    case MSR_CSTAR:
        val = env->cstar;
        break;
    case MSR_FMASK:
        val = env->fmask;
        break;
    case MSR_FSBASE:
        val = env->segs[R_FS].base;
        break;
    case MSR_GSBASE:
        val = env->segs[R_GS].base;
        break;
    case MSR_KERNELGSBASE:
        val = env->kernelgsbase;
        break;
    case MSR_TSC_AUX:
        val = env->tsc_aux;
        break;
#endif
    case MSR_SMI_COUNT:
        val = env->msr_smi_count;
        break;
    case MSR_MTRRphysBase(0):
    case MSR_MTRRphysBase(1):
    case MSR_MTRRphysBase(2):
    case MSR_MTRRphysBase(3):
    case MSR_MTRRphysBase(4):
    case MSR_MTRRphysBase(5):
    case MSR_MTRRphysBase(6):
    case MSR_MTRRphysBase(7):
        val = env->mtrr_var[((uint32_t)env->regs[R_ECX] -
                             MSR_MTRRphysBase(0)) / 2].base;
        break;
    case MSR_MTRRphysMask(0):
    case MSR_MTRRphysMask(1):
    case MSR_MTRRphysMask(2):
    case MSR_MTRRphysMask(3):
    case MSR_MTRRphysMask(4):
    case MSR_MTRRphysMask(5):
    case MSR_MTRRphysMask(6):
    case MSR_MTRRphysMask(7):
        val = env->mtrr_var[((uint32_t)env->regs[R_ECX] -
                             MSR_MTRRphysMask(0)) / 2].mask;
        break;
    case MSR_MTRRfix64K_00000:
        val = env->mtrr_fixed[0];
        break;
    case MSR_MTRRfix16K_80000:
    case MSR_MTRRfix16K_A0000:
        val = env->mtrr_fixed[(uint32_t)env->regs[R_ECX] -
                              MSR_MTRRfix16K_80000 + 1];
        break;
    case MSR_MTRRfix4K_C0000:
    case MSR_MTRRfix4K_C8000:
    case MSR_MTRRfix4K_D0000:
    case MSR_MTRRfix4K_D8000:
    case MSR_MTRRfix4K_E0000:
    case MSR_MTRRfix4K_E8000:
    case MSR_MTRRfix4K_F0000:
    case MSR_MTRRfix4K_F8000:
        val = env->mtrr_fixed[(uint32_t)env->regs[R_ECX] -
                              MSR_MTRRfix4K_C0000 + 3];
        break;
    case MSR_MTRRdefType:
        val = env->mtrr_deftype;
        break;
    case MSR_MTRRcap:
        if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
            val = MSR_MTRRcap_VCNT | MSR_MTRRcap_FIXRANGE_SUPPORT |
                MSR_MTRRcap_WC_SUPPORTED;
        } else {
            /* XXX: exception? */
            val = 0;
        }
        break;
    case MSR_MCG_CAP:
        val = env->mcg_cap;
        break;
    case MSR_MCG_CTL:
        if (env->mcg_cap & MCG_CTL_P) {
            val = env->mcg_ctl;
        } else {
            val = 0;
        }
        break;
    case MSR_MCG_STATUS:
        val = env->mcg_status;
        break;
    case MSR_IA32_MISC_ENABLE:
        val = env->msr_ia32_misc_enable;
        break;
    case MSR_IA32_BNDCFGS:
        val = env->msr_bndcfgs;
        break;
    default:
        if ((uint32_t)env->regs[R_ECX] >= MSR_MC0_CTL
            && (uint32_t)env->regs[R_ECX] < MSR_MC0_CTL +
            (4 * env->mcg_cap & 0xff)) {
            uint32_t offset = (uint32_t)env->regs[R_ECX] - MSR_MC0_CTL;
            val = env->mce_banks[offset];
            break;
        }
        /* XXX: exception? */
        val = 0;
        break;
    }
    env->regs[R_EAX] = (uint32_t)(val);
    env->regs[R_EDX] = (uint32_t)(val >> 32);
}
#endif

static void do_pause(X86CPU *cpu)
{
    CPUState *cs = CPU(cpu);

    /* Just let another CPU run.  */
    cs->exception_index = EXCP_INTERRUPT;
    cpu_loop_exit(cs);
}

static void do_hlt(X86CPU *cpu)
{
    CPUState *cs = CPU(cpu);
    CPUX86State *env = &cpu->env;

    env->hflags &= ~HF_INHIBIT_IRQ_MASK; /* needed if sti is just before */
    cs->halted = 1;
    cs->exception_index = EXCP_HLT;
    cpu_loop_exit(cs);
}

void helper_hlt(CPUX86State *env, int next_eip_addend)
{
    X86CPU *cpu = x86_env_get_cpu(env);

    cpu_svm_check_intercept_param(env, SVM_EXIT_HLT, 0, GETPC());
    env->eip += next_eip_addend;

    do_hlt(cpu);
}

void helper_monitor(CPUX86State *env, target_ulong ptr)
{
    if ((uint32_t)env->regs[R_ECX] != 0) {
        raise_exception_ra(env, EXCP0D_GPF, GETPC());
    }
    /* XXX: store address? */
    cpu_svm_check_intercept_param(env, SVM_EXIT_MONITOR, 0, GETPC());
}

void helper_mwait(CPUX86State *env, int next_eip_addend)
{
    CPUState *cs;
    X86CPU *cpu;

    if ((uint32_t)env->regs[R_ECX] != 0) {
        raise_exception_ra(env, EXCP0D_GPF, GETPC());
    }
    cpu_svm_check_intercept_param(env, SVM_EXIT_MWAIT, 0, GETPC());
    env->eip += next_eip_addend;

    cpu = x86_env_get_cpu(env);
    cs = CPU(cpu);
    /* XXX: not complete but not completely erroneous */
    if (cs->cpu_index != 0 || CPU_NEXT(cs) != NULL) {
        do_pause(cpu);
    } else {
        do_hlt(cpu);
    }
}

void helper_pause(CPUX86State *env, int next_eip_addend)
{
    X86CPU *cpu = x86_env_get_cpu(env);

    cpu_svm_check_intercept_param(env, SVM_EXIT_PAUSE, 0, GETPC());
    env->eip += next_eip_addend;

    do_pause(cpu);
}

void helper_debug(CPUX86State *env)
{
    CPUState *cs = CPU(x86_env_get_cpu(env));

    cs->exception_index = EXCP_DEBUG;
    cpu_loop_exit(cs);
}

uint64_t helper_rdpkru(CPUX86State *env, uint32_t ecx)
{
    if ((env->cr[4] & CR4_PKE_MASK) == 0) {
        raise_exception_err_ra(env, EXCP06_ILLOP, 0, GETPC());
    }
    if (ecx != 0) {
        raise_exception_err_ra(env, EXCP0D_GPF, 0, GETPC());
    }

    return env->pkru;
}

void helper_wrpkru(CPUX86State *env, uint32_t ecx, uint64_t val)
{
    CPUState *cs = CPU(x86_env_get_cpu(env));

    if ((env->cr[4] & CR4_PKE_MASK) == 0) {
        raise_exception_err_ra(env, EXCP06_ILLOP, 0, GETPC());
    }
    if (ecx != 0 || (val & 0xFFFFFFFF00000000ull)) {
        raise_exception_err_ra(env, EXCP0D_GPF, 0, GETPC());
    }

    env->pkru = val;
    tlb_flush(cs);
}
Commit	Line	Data
f7b2429f BS	1	/*
	2	* x86 misc helpers
	3	*
	4	* Copyright (c) 2003 Fabrice Bellard
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
	18	*/
	19
b6a0aa05	20	#include "qemu/osdep.h"
b4e79a50	21	#include "qemu/main-loop.h"
f7b2429f	22	#include "cpu.h"
2ef6175a	23	#include "exec/helper-proto.h"
63c91552	24	#include "exec/exec-all.h"
f08b6170	25	#include "exec/cpu_ldst.h"
3f7d8464	26	#include "exec/address-spaces.h"
92fc4b58	27
3f7d8464	28	void helper_outb(CPUX86State *env, uint32_t port, uint32_t data)
f7b2429f	29	{
3f7d8464 PB	30	#ifdef CONFIG_USER_ONLY
	31	fprintf(stderr, "outb: port=0x%04x, data=%02x\n", port, data);
	32	#else
	33	address_space_stb(&address_space_io, port, data,
	34	cpu_get_mem_attrs(env), NULL);
	35	#endif
f7b2429f BS	36	}
f7b2429f BS	37
3f7d8464	38	target_ulong helper_inb(CPUX86State *env, uint32_t port)
f7b2429f	39	{
3f7d8464 PB	40	#ifdef CONFIG_USER_ONLY
	41	fprintf(stderr, "inb: port=0x%04x\n", port);
	42	return 0;
	43	#else
	44	return address_space_ldub(&address_space_io, port,
	45	cpu_get_mem_attrs(env), NULL);
	46	#endif
f7b2429f BS	47	}
f7b2429f BS	48
3f7d8464	49	void helper_outw(CPUX86State *env, uint32_t port, uint32_t data)
f7b2429f	50	{
3f7d8464 PB	51	#ifdef CONFIG_USER_ONLY
	52	fprintf(stderr, "outw: port=0x%04x, data=%04x\n", port, data);
	53	#else
	54	address_space_stw(&address_space_io, port, data,
	55	cpu_get_mem_attrs(env), NULL);
	56	#endif
f7b2429f BS	57	}
f7b2429f BS	58
3f7d8464	59	target_ulong helper_inw(CPUX86State *env, uint32_t port)
f7b2429f	60	{
3f7d8464 PB	61	#ifdef CONFIG_USER_ONLY
	62	fprintf(stderr, "inw: port=0x%04x\n", port);
	63	return 0;
	64	#else
	65	return address_space_lduw(&address_space_io, port,
	66	cpu_get_mem_attrs(env), NULL);
	67	#endif
f7b2429f BS	68	}
f7b2429f BS	69
3f7d8464	70	void helper_outl(CPUX86State *env, uint32_t port, uint32_t data)
f7b2429f	71	{
3f7d8464 PB	72	#ifdef CONFIG_USER_ONLY
	73	fprintf(stderr, "outw: port=0x%04x, data=%08x\n", port, data);
	74	#else
	75	address_space_stl(&address_space_io, port, data,
	76	cpu_get_mem_attrs(env), NULL);
	77	#endif
f7b2429f BS	78	}
f7b2429f BS	79
3f7d8464	80	target_ulong helper_inl(CPUX86State *env, uint32_t port)
f7b2429f	81	{
3f7d8464 PB	82	#ifdef CONFIG_USER_ONLY
	83	fprintf(stderr, "inl: port=0x%04x\n", port);
	84	return 0;
	85	#else
	86	return address_space_ldl(&address_space_io, port,
	87	cpu_get_mem_attrs(env), NULL);
	88	#endif
f7b2429f BS	89	}
f7b2429f BS	90
4a7443be	91	void helper_into(CPUX86State *env, int next_eip_addend)
f7b2429f BS	92	{
	93	int eflags;
	94
f0967a1a	95	eflags = cpu_cc_compute_all(env, CC_OP);
f7b2429f BS	96	if (eflags & CC_O) {
	97	raise_interrupt(env, EXCP04_INTO, 1, 0, next_eip_addend);
	98	}
	99	}
	100
4a7443be	101	void helper_cpuid(CPUX86State *env)
f7b2429f BS	102	{
	103	uint32_t eax, ebx, ecx, edx;
	104
65c9d60a	105	cpu_svm_check_intercept_param(env, SVM_EXIT_CPUID, 0, GETPC());
f7b2429f	106
90a2541b LG	107	cpu_x86_cpuid(env, (uint32_t)env->regs[R_EAX], (uint32_t)env->regs[R_ECX],
90a2541b LG	108	&eax, &ebx, &ecx, &edx);
4b34e3ad	109	env->regs[R_EAX] = eax;
70b51365	110	env->regs[R_EBX] = ebx;
a4165610	111	env->regs[R_ECX] = ecx;
00f5e6f2	112	env->regs[R_EDX] = edx;
f7b2429f BS	113	}
	114
	115	#if defined(CONFIG_USER_ONLY)
4a7443be	116	target_ulong helper_read_crN(CPUX86State *env, int reg)
f7b2429f BS	117	{
	118	return 0;
	119	}
	120
4a7443be	121	void helper_write_crN(CPUX86State *env, int reg, target_ulong t0)
f7b2429f BS	122	{
f7b2429f BS	123	}
f7b2429f	124	#else
4a7443be	125	target_ulong helper_read_crN(CPUX86State *env, int reg)
f7b2429f BS	126	{
	127	target_ulong val;
	128
65c9d60a	129	cpu_svm_check_intercept_param(env, SVM_EXIT_READ_CR0 + reg, 0, GETPC());
f7b2429f BS	130	switch (reg) {
	131	default:
	132	val = env->cr[reg];
	133	break;
	134	case 8:
	135	if (!(env->hflags2 & HF2_VINTR_MASK)) {
02e51483	136	val = cpu_get_apic_tpr(x86_env_get_cpu(env)->apic_state);
f7b2429f BS	137	} else {
	138	val = env->v_tpr;
	139	}
	140	break;
	141	}
	142	return val;
	143	}
	144
4a7443be	145	void helper_write_crN(CPUX86State *env, int reg, target_ulong t0)
f7b2429f	146	{
65c9d60a	147	cpu_svm_check_intercept_param(env, SVM_EXIT_WRITE_CR0 + reg, 0, GETPC());
f7b2429f BS	148	switch (reg) {
	149	case 0:
	150	cpu_x86_update_cr0(env, t0);
	151	break;
	152	case 3:
	153	cpu_x86_update_cr3(env, t0);
	154	break;
	155	case 4:
	156	cpu_x86_update_cr4(env, t0);
	157	break;
	158	case 8:
	159	if (!(env->hflags2 & HF2_VINTR_MASK)) {
b4e79a50	160	qemu_mutex_lock_iothread();
02e51483	161	cpu_set_apic_tpr(x86_env_get_cpu(env)->apic_state, t0);
b4e79a50	162	qemu_mutex_unlock_iothread();
f7b2429f BS	163	}
	164	env->v_tpr = t0 & 0x0f;
	165	break;
	166	default:
	167	env->cr[reg] = t0;
	168	break;
	169	}
	170	}
f7b2429f BS	171	#endif
f7b2429f BS	172
4a7443be	173	void helper_lmsw(CPUX86State *env, target_ulong t0)
f7b2429f BS	174	{
	175	/* only 4 lower bits of CR0 are modified. PE cannot be set to zero
	176	if already set to one. */
	177	t0 = (env->cr[0] & ~0xe) \| (t0 & 0xf);
4a7443be	178	helper_write_crN(env, 0, t0);
f7b2429f BS	179	}
f7b2429f BS	180
4a7443be	181	void helper_invlpg(CPUX86State *env, target_ulong addr)
f7b2429f	182	{
31b030d4 AF	183	X86CPU *cpu = x86_env_get_cpu(env);
31b030d4 AF	184
65c9d60a	185	cpu_svm_check_intercept_param(env, SVM_EXIT_INVLPG, 0, GETPC());
31b030d4	186	tlb_flush_page(CPU(cpu), addr);
f7b2429f BS	187	}
f7b2429f BS	188
4a7443be	189	void helper_rdtsc(CPUX86State *env)
f7b2429f BS	190	{
	191	uint64_t val;
	192
	193	if ((env->cr[4] & CR4_TSD_MASK) && ((env->hflags & HF_CPL_MASK) != 0)) {
4054cdec	194	raise_exception_ra(env, EXCP0D_GPF, GETPC());
f7b2429f	195	}
65c9d60a	196	cpu_svm_check_intercept_param(env, SVM_EXIT_RDTSC, 0, GETPC());
f7b2429f BS	197
f7b2429f BS	198	val = cpu_get_tsc(env) + env->tsc_offset;
4b34e3ad	199	env->regs[R_EAX] = (uint32_t)(val);
00f5e6f2	200	env->regs[R_EDX] = (uint32_t)(val >> 32);
f7b2429f BS	201	}
f7b2429f BS	202
4a7443be	203	void helper_rdtscp(CPUX86State *env)
f7b2429f	204	{
4a7443be	205	helper_rdtsc(env);
a4165610	206	env->regs[R_ECX] = (uint32_t)(env->tsc_aux);
f7b2429f BS	207	}
f7b2429f BS	208
4a7443be	209	void helper_rdpmc(CPUX86State *env)
f7b2429f BS	210	{
f7b2429f BS	211	if ((env->cr[4] & CR4_PCE_MASK) && ((env->hflags & HF_CPL_MASK) != 0)) {
4054cdec	212	raise_exception_ra(env, EXCP0D_GPF, GETPC());
f7b2429f	213	}
65c9d60a	214	cpu_svm_check_intercept_param(env, SVM_EXIT_RDPMC, 0, GETPC());
f7b2429f BS	215
	216	/* currently unimplemented */
	217	qemu_log_mask(LOG_UNIMP, "x86: unimplemented rdpmc\n");
	218	raise_exception_err(env, EXCP06_ILLOP, 0);
	219	}
	220
	221	#if defined(CONFIG_USER_ONLY)
4a7443be	222	void helper_wrmsr(CPUX86State *env)
f7b2429f BS	223	{
	224	}
	225
4a7443be	226	void helper_rdmsr(CPUX86State *env)
f7b2429f BS	227	{
	228	}
	229	#else
4a7443be	230	void helper_wrmsr(CPUX86State *env)
f7b2429f BS	231	{
	232	uint64_t val;
	233
65c9d60a	234	cpu_svm_check_intercept_param(env, SVM_EXIT_MSR, 1, GETPC());
f7b2429f	235
90a2541b LG	236	val = ((uint32_t)env->regs[R_EAX]) \|
90a2541b LG	237	((uint64_t)((uint32_t)env->regs[R_EDX]) << 32);
f7b2429f	238
a4165610	239	switch ((uint32_t)env->regs[R_ECX]) {
f7b2429f BS	240	case MSR_IA32_SYSENTER_CS:
	241	env->sysenter_cs = val & 0xffff;
	242	break;
	243	case MSR_IA32_SYSENTER_ESP:
	244	env->sysenter_esp = val;
	245	break;
	246	case MSR_IA32_SYSENTER_EIP:
	247	env->sysenter_eip = val;
	248	break;
	249	case MSR_IA32_APICBASE:
02e51483	250	cpu_set_apic_base(x86_env_get_cpu(env)->apic_state, val);
f7b2429f BS	251	break;
	252	case MSR_EFER:
	253	{
	254	uint64_t update_mask;
	255
	256	update_mask = 0;
0514ef2f	257	if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_SYSCALL) {
f7b2429f BS	258	update_mask \|= MSR_EFER_SCE;
f7b2429f BS	259	}
0514ef2f	260	if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
f7b2429f BS	261	update_mask \|= MSR_EFER_LME;
f7b2429f BS	262	}
0514ef2f	263	if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_FFXSR) {
f7b2429f BS	264	update_mask \|= MSR_EFER_FFXSR;
f7b2429f BS	265	}
0514ef2f	266	if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_NX) {
f7b2429f BS	267	update_mask \|= MSR_EFER_NXE;
f7b2429f BS	268	}
0514ef2f	269	if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
f7b2429f BS	270	update_mask \|= MSR_EFER_SVME;
f7b2429f BS	271	}
0514ef2f	272	if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_FFXSR) {
f7b2429f BS	273	update_mask \|= MSR_EFER_FFXSR;
	274	}
	275	cpu_load_efer(env, (env->efer & ~update_mask) \|
	276	(val & update_mask));
	277	}
	278	break;
	279	case MSR_STAR:
	280	env->star = val;
	281	break;
	282	case MSR_PAT:
	283	env->pat = val;
	284	break;
	285	case MSR_VM_HSAVE_PA:
	286	env->vm_hsave = val;
	287	break;
	288	#ifdef TARGET_X86_64
	289	case MSR_LSTAR:
	290	env->lstar = val;
	291	break;
	292	case MSR_CSTAR:
	293	env->cstar = val;
	294	break;
	295	case MSR_FMASK:
	296	env->fmask = val;
	297	break;
	298	case MSR_FSBASE:
	299	env->segs[R_FS].base = val;
	300	break;
	301	case MSR_GSBASE:
	302	env->segs[R_GS].base = val;
	303	break;
	304	case MSR_KERNELGSBASE:
	305	env->kernelgsbase = val;
	306	break;
	307	#endif
	308	case MSR_MTRRphysBase(0):
	309	case MSR_MTRRphysBase(1):
	310	case MSR_MTRRphysBase(2):
	311	case MSR_MTRRphysBase(3):
	312	case MSR_MTRRphysBase(4):
	313	case MSR_MTRRphysBase(5):
	314	case MSR_MTRRphysBase(6):
	315	case MSR_MTRRphysBase(7):
90a2541b LG	316	env->mtrr_var[((uint32_t)env->regs[R_ECX] -
90a2541b LG	317	MSR_MTRRphysBase(0)) / 2].base = val;
f7b2429f BS	318	break;
	319	case MSR_MTRRphysMask(0):
	320	case MSR_MTRRphysMask(1):
	321	case MSR_MTRRphysMask(2):
	322	case MSR_MTRRphysMask(3):
	323	case MSR_MTRRphysMask(4):
	324	case MSR_MTRRphysMask(5):
	325	case MSR_MTRRphysMask(6):
	326	case MSR_MTRRphysMask(7):
90a2541b LG	327	env->mtrr_var[((uint32_t)env->regs[R_ECX] -
90a2541b LG	328	MSR_MTRRphysMask(0)) / 2].mask = val;
f7b2429f BS	329	break;
f7b2429f BS	330	case MSR_MTRRfix64K_00000:
90a2541b LG	331	env->mtrr_fixed[(uint32_t)env->regs[R_ECX] -
90a2541b LG	332	MSR_MTRRfix64K_00000] = val;
f7b2429f BS	333	break;
	334	case MSR_MTRRfix16K_80000:
	335	case MSR_MTRRfix16K_A0000:
90a2541b LG	336	env->mtrr_fixed[(uint32_t)env->regs[R_ECX] -
90a2541b LG	337	MSR_MTRRfix16K_80000 + 1] = val;
f7b2429f BS	338	break;
	339	case MSR_MTRRfix4K_C0000:
	340	case MSR_MTRRfix4K_C8000:
	341	case MSR_MTRRfix4K_D0000:
	342	case MSR_MTRRfix4K_D8000:
	343	case MSR_MTRRfix4K_E0000:
	344	case MSR_MTRRfix4K_E8000:
	345	case MSR_MTRRfix4K_F0000:
	346	case MSR_MTRRfix4K_F8000:
90a2541b LG	347	env->mtrr_fixed[(uint32_t)env->regs[R_ECX] -
90a2541b LG	348	MSR_MTRRfix4K_C0000 + 3] = val;
f7b2429f BS	349	break;
	350	case MSR_MTRRdefType:
	351	env->mtrr_deftype = val;
	352	break;
	353	case MSR_MCG_STATUS:
	354	env->mcg_status = val;
	355	break;
	356	case MSR_MCG_CTL:
	357	if ((env->mcg_cap & MCG_CTL_P)
	358	&& (val == 0 \|\| val == ~(uint64_t)0)) {
	359	env->mcg_ctl = val;
	360	}
	361	break;
	362	case MSR_TSC_AUX:
	363	env->tsc_aux = val;
	364	break;
	365	case MSR_IA32_MISC_ENABLE:
	366	env->msr_ia32_misc_enable = val;
	367	break;
f4f1110e RH	368	case MSR_IA32_BNDCFGS:
	369	/* FIXME: #GP if reserved bits are set. */
	370	/* FIXME: Extend highest implemented bit of linear address. */
	371	env->msr_bndcfgs = val;
	372	cpu_sync_bndcs_hflags(env);
	373	break;
f7b2429f	374	default:
a4165610	375	if ((uint32_t)env->regs[R_ECX] >= MSR_MC0_CTL
90a2541b LG	376	&& (uint32_t)env->regs[R_ECX] < MSR_MC0_CTL +
90a2541b LG	377	(4 * env->mcg_cap & 0xff)) {
a4165610	378	uint32_t offset = (uint32_t)env->regs[R_ECX] - MSR_MC0_CTL;
f7b2429f BS	379	if ((offset & 0x3) != 0
	380	\|\| (val == 0 \|\| val == ~(uint64_t)0)) {
	381	env->mce_banks[offset] = val;
	382	}
	383	break;
	384	}
	385	/* XXX: exception? */
	386	break;
	387	}
	388	}
	389
4a7443be	390	void helper_rdmsr(CPUX86State *env)
f7b2429f BS	391	{
	392	uint64_t val;
	393
65c9d60a	394	cpu_svm_check_intercept_param(env, SVM_EXIT_MSR, 0, GETPC());
f7b2429f	395
a4165610	396	switch ((uint32_t)env->regs[R_ECX]) {
f7b2429f BS	397	case MSR_IA32_SYSENTER_CS:
	398	val = env->sysenter_cs;
	399	break;
	400	case MSR_IA32_SYSENTER_ESP:
	401	val = env->sysenter_esp;
	402	break;
	403	case MSR_IA32_SYSENTER_EIP:
	404	val = env->sysenter_eip;
	405	break;
	406	case MSR_IA32_APICBASE:
02e51483	407	val = cpu_get_apic_base(x86_env_get_cpu(env)->apic_state);
f7b2429f BS	408	break;
	409	case MSR_EFER:
	410	val = env->efer;
	411	break;
	412	case MSR_STAR:
	413	val = env->star;
	414	break;
	415	case MSR_PAT:
	416	val = env->pat;
	417	break;
	418	case MSR_VM_HSAVE_PA:
	419	val = env->vm_hsave;
	420	break;
	421	case MSR_IA32_PERF_STATUS:
	422	/* tsc_increment_by_tick */
	423	val = 1000ULL;
	424	/* CPU multiplier */
	425	val \|= (((uint64_t)4ULL) << 40);
	426	break;
	427	#ifdef TARGET_X86_64
	428	case MSR_LSTAR:
	429	val = env->lstar;
	430	break;
	431	case MSR_CSTAR:
	432	val = env->cstar;
	433	break;
	434	case MSR_FMASK:
	435	val = env->fmask;
	436	break;
	437	case MSR_FSBASE:
	438	val = env->segs[R_FS].base;
	439	break;
	440	case MSR_GSBASE:
	441	val = env->segs[R_GS].base;
	442	break;
	443	case MSR_KERNELGSBASE:
	444	val = env->kernelgsbase;
	445	break;
	446	case MSR_TSC_AUX:
	447	val = env->tsc_aux;
	448	break;
	449	#endif
1d3db6bd PB	450	case MSR_SMI_COUNT:
	451	val = env->msr_smi_count;
	452	break;
f7b2429f BS	453	case MSR_MTRRphysBase(0):
	454	case MSR_MTRRphysBase(1):
	455	case MSR_MTRRphysBase(2):
	456	case MSR_MTRRphysBase(3):
	457	case MSR_MTRRphysBase(4):
	458	case MSR_MTRRphysBase(5):
	459	case MSR_MTRRphysBase(6):
	460	case MSR_MTRRphysBase(7):
90a2541b LG	461	val = env->mtrr_var[((uint32_t)env->regs[R_ECX] -
90a2541b LG	462	MSR_MTRRphysBase(0)) / 2].base;
f7b2429f BS	463	break;
	464	case MSR_MTRRphysMask(0):
	465	case MSR_MTRRphysMask(1):
	466	case MSR_MTRRphysMask(2):
	467	case MSR_MTRRphysMask(3):
	468	case MSR_MTRRphysMask(4):
	469	case MSR_MTRRphysMask(5):
	470	case MSR_MTRRphysMask(6):
	471	case MSR_MTRRphysMask(7):
90a2541b LG	472	val = env->mtrr_var[((uint32_t)env->regs[R_ECX] -
90a2541b LG	473	MSR_MTRRphysMask(0)) / 2].mask;
f7b2429f BS	474	break;
	475	case MSR_MTRRfix64K_00000:
	476	val = env->mtrr_fixed[0];
	477	break;
	478	case MSR_MTRRfix16K_80000:
	479	case MSR_MTRRfix16K_A0000:
90a2541b LG	480	val = env->mtrr_fixed[(uint32_t)env->regs[R_ECX] -
90a2541b LG	481	MSR_MTRRfix16K_80000 + 1];
f7b2429f BS	482	break;
	483	case MSR_MTRRfix4K_C0000:
	484	case MSR_MTRRfix4K_C8000:
	485	case MSR_MTRRfix4K_D0000:
	486	case MSR_MTRRfix4K_D8000:
	487	case MSR_MTRRfix4K_E0000:
	488	case MSR_MTRRfix4K_E8000:
	489	case MSR_MTRRfix4K_F0000:
	490	case MSR_MTRRfix4K_F8000:
90a2541b LG	491	val = env->mtrr_fixed[(uint32_t)env->regs[R_ECX] -
90a2541b LG	492	MSR_MTRRfix4K_C0000 + 3];
f7b2429f BS	493	break;
	494	case MSR_MTRRdefType:
	495	val = env->mtrr_deftype;
	496	break;
	497	case MSR_MTRRcap:
0514ef2f	498	if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
f7b2429f BS	499	val = MSR_MTRRcap_VCNT \| MSR_MTRRcap_FIXRANGE_SUPPORT \|
	500	MSR_MTRRcap_WC_SUPPORTED;
	501	} else {
	502	/* XXX: exception? */
	503	val = 0;
	504	}
	505	break;
	506	case MSR_MCG_CAP:
	507	val = env->mcg_cap;
	508	break;
	509	case MSR_MCG_CTL:
	510	if (env->mcg_cap & MCG_CTL_P) {
	511	val = env->mcg_ctl;
	512	} else {
	513	val = 0;
	514	}
	515	break;
	516	case MSR_MCG_STATUS:
	517	val = env->mcg_status;
	518	break;
	519	case MSR_IA32_MISC_ENABLE:
	520	val = env->msr_ia32_misc_enable;
	521	break;
f4f1110e RH	522	case MSR_IA32_BNDCFGS:
	523	val = env->msr_bndcfgs;
	524	break;
f7b2429f	525	default:
a4165610	526	if ((uint32_t)env->regs[R_ECX] >= MSR_MC0_CTL
90a2541b LG	527	&& (uint32_t)env->regs[R_ECX] < MSR_MC0_CTL +
90a2541b LG	528	(4 * env->mcg_cap & 0xff)) {
a4165610	529	uint32_t offset = (uint32_t)env->regs[R_ECX] - MSR_MC0_CTL;
f7b2429f BS	530	val = env->mce_banks[offset];
	531	break;
	532	}
	533	/* XXX: exception? */
	534	val = 0;
	535	break;
	536	}
4b34e3ad	537	env->regs[R_EAX] = (uint32_t)(val);
00f5e6f2	538	env->regs[R_EDX] = (uint32_t)(val >> 32);
f7b2429f BS	539	}
	540	#endif
	541
81f3053b PB	542	static void do_pause(X86CPU *cpu)
81f3053b PB	543	{
27103424	544	CPUState *cs = CPU(cpu);
81f3053b PB	545
81f3053b PB	546	/* Just let another CPU run. */
27103424	547	cs->exception_index = EXCP_INTERRUPT;
5638d180	548	cpu_loop_exit(cs);
81f3053b PB	549	}
81f3053b PB	550
259186a7	551	static void do_hlt(X86CPU *cpu)
f7b2429f	552	{
259186a7 AF	553	CPUState *cs = CPU(cpu);
	554	CPUX86State *env = &cpu->env;
	555
f7b2429f	556	env->hflags &= ~HF_INHIBIT_IRQ_MASK; /* needed if sti is just before */
259186a7	557	cs->halted = 1;
27103424	558	cs->exception_index = EXCP_HLT;
5638d180	559	cpu_loop_exit(cs);
f7b2429f BS	560	}
f7b2429f BS	561
4a7443be	562	void helper_hlt(CPUX86State *env, int next_eip_addend)
f7b2429f	563	{
259186a7 AF	564	X86CPU *cpu = x86_env_get_cpu(env);
259186a7 AF	565
65c9d60a	566	cpu_svm_check_intercept_param(env, SVM_EXIT_HLT, 0, GETPC());
a78d0eab	567	env->eip += next_eip_addend;
f7b2429f	568
259186a7	569	do_hlt(cpu);
f7b2429f BS	570	}
f7b2429f BS	571
4a7443be	572	void helper_monitor(CPUX86State *env, target_ulong ptr)
f7b2429f	573	{
a4165610	574	if ((uint32_t)env->regs[R_ECX] != 0) {
4054cdec	575	raise_exception_ra(env, EXCP0D_GPF, GETPC());
f7b2429f BS	576	}
f7b2429f BS	577	/* XXX: store address? */
65c9d60a	578	cpu_svm_check_intercept_param(env, SVM_EXIT_MONITOR, 0, GETPC());
f7b2429f BS	579	}
f7b2429f BS	580
4a7443be	581	void helper_mwait(CPUX86State *env, int next_eip_addend)
f7b2429f	582	{
259186a7 AF	583	CPUState *cs;
259186a7 AF	584	X86CPU *cpu;
55e5c285	585
a4165610	586	if ((uint32_t)env->regs[R_ECX] != 0) {
4054cdec	587	raise_exception_ra(env, EXCP0D_GPF, GETPC());
f7b2429f	588	}
65c9d60a	589	cpu_svm_check_intercept_param(env, SVM_EXIT_MWAIT, 0, GETPC());
a78d0eab	590	env->eip += next_eip_addend;
f7b2429f	591
259186a7 AF	592	cpu = x86_env_get_cpu(env);
259186a7 AF	593	cs = CPU(cpu);
f7b2429f	594	/* XXX: not complete but not completely erroneous */
bdc44640	595	if (cs->cpu_index != 0 \|\| CPU_NEXT(cs) != NULL) {
81f3053b	596	do_pause(cpu);
f7b2429f	597	} else {
259186a7	598	do_hlt(cpu);
f7b2429f BS	599	}
	600	}
	601
81f3053b PB	602	void helper_pause(CPUX86State *env, int next_eip_addend)
	603	{
	604	X86CPU *cpu = x86_env_get_cpu(env);
	605
65c9d60a	606	cpu_svm_check_intercept_param(env, SVM_EXIT_PAUSE, 0, GETPC());
81f3053b PB	607	env->eip += next_eip_addend;
	608
	609	do_pause(cpu);
	610	}
	611
4a7443be	612	void helper_debug(CPUX86State *env)
f7b2429f	613	{
27103424 AF	614	CPUState *cs = CPU(x86_env_get_cpu(env));
	615
	616	cs->exception_index = EXCP_DEBUG;
5638d180	617	cpu_loop_exit(cs);
f7b2429f	618	}
0f70ed47 PB	619
	620	uint64_t helper_rdpkru(CPUX86State *env, uint32_t ecx)
	621	{
	622	if ((env->cr[4] & CR4_PKE_MASK) == 0) {
	623	raise_exception_err_ra(env, EXCP06_ILLOP, 0, GETPC());
	624	}
	625	if (ecx != 0) {
	626	raise_exception_err_ra(env, EXCP0D_GPF, 0, GETPC());
	627	}
	628
	629	return env->pkru;
	630	}
	631
	632	void helper_wrpkru(CPUX86State *env, uint32_t ecx, uint64_t val)
	633	{
	634	CPUState *cs = CPU(x86_env_get_cpu(env));
	635
	636	if ((env->cr[4] & CR4_PKE_MASK) == 0) {
	637	raise_exception_err_ra(env, EXCP06_ILLOP, 0, GETPC());
	638	}
	639	if (ecx != 0 \|\| (val & 0xFFFFFFFF00000000ull)) {
	640	raise_exception_err_ra(env, EXCP0D_GPF, 0, GETPC());
	641	}
	642
	643	env->pkru = val;
d10eb08f	644	tlb_flush(cs);
0f70ed47	645	}