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tests/tcg/i386: test-avx: add test cases for SHA new instructions
[mirror_qemu.git] / target / i386 / tcg / decode-new.c.inc
CommitLineData
b3e22b23
PB		 1/*
2 * New-style decoder for i386 instructions
3 *
4 * Copyright (c) 2022 Red Hat, Inc.
5 *
6 * Author: Paolo Bonzini <pbonzini@redhat.com>
7 *
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2.1 of the License, or (at your option) any later version.
12 *
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
17 *
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 */
21
22/*
23 * The decoder is mostly based on tables copied from the Intel SDM. As
24 * a result, most operand load and writeback is done entirely in common
25 * table-driven code using the same operand type (X86_TYPE_*) and
26 * size (X86_SIZE_*) codes used in the manual.
27 *
28 * The main difference is that the V, U and W types are extended to
29 * cover MMX as well; if an instruction is like
30 *
31 * por Pq, Qq
32 * 66 por Vx, Hx, Wx
33 *
34 * only the second row is included and the instruction is marked as a
35 * valid MMX instruction. The MMX flag directs the decoder to rewrite
36 * the V/U/H/W types to P/N/P/Q if there is no prefix, as well as changing
37 * "x" to "q" if there is no prefix.
38 *
39 * In addition, the ss/ps/sd/pd types are sometimes mushed together as "x"
40 * if the difference is expressed via prefixes. Individual instructions
41 * are separated by prefix in the generator functions.
42 *
43 * There are a couple cases in which instructions (e.g. MOVD) write the
44 * whole XMM or MM register but are established incorrectly in the manual
45 * as "d" or "q". These have to be fixed for the decoder to work correctly.
46 */
47
48#define X86_OP_NONE { 0 },
49
50#define X86_OP_GROUP3(op, op0_, s0_, op1_, s1_, op2_, s2_, ...) { \
51 .decode = glue(decode_, op), \
52 .op0 = glue(X86_TYPE_, op0_), \
53 .s0 = glue(X86_SIZE_, s0_), \
54 .op1 = glue(X86_TYPE_, op1_), \
55 .s1 = glue(X86_SIZE_, s1_), \
56 .op2 = glue(X86_TYPE_, op2_), \
57 .s2 = glue(X86_SIZE_, s2_), \
58 .is_decode = true, \
59 ## __VA_ARGS__ \
60}
61
62#define X86_OP_GROUP2(op, op0, s0, op1, s1, ...) \
63 X86_OP_GROUP3(op, op0, s0, 2op, s0, op1, s1, ## __VA_ARGS__)
64#define X86_OP_GROUP0(op, ...) \
65 X86_OP_GROUP3(op, None, None, None, None, None, None, ## __VA_ARGS__)
66
67#define X86_OP_ENTRY3(op, op0_, s0_, op1_, s1_, op2_, s2_, ...) { \
68 .gen = glue(gen_, op), \
69 .op0 = glue(X86_TYPE_, op0_), \
70 .s0 = glue(X86_SIZE_, s0_), \
71 .op1 = glue(X86_TYPE_, op1_), \
72 .s1 = glue(X86_SIZE_, s1_), \
73 .op2 = glue(X86_TYPE_, op2_), \
74 .s2 = glue(X86_SIZE_, s2_), \
75 ## __VA_ARGS__ \
76}
77
78#define X86_OP_ENTRY4(op, op0_, s0_, op1_, s1_, op2_, s2_, ...) \
79 X86_OP_ENTRY3(op, op0_, s0_, op1_, s1_, op2_, s2_, \
80 .op3 = X86_TYPE_I, .s3 = X86_SIZE_b, \
81 ## __VA_ARGS__)
82
83#define X86_OP_ENTRY2(op, op0, s0, op1, s1, ...) \
84 X86_OP_ENTRY3(op, op0, s0, 2op, s0, op1, s1, ## __VA_ARGS__)
57f6bba0
PB		 85#define X86_OP_ENTRYw(op, op0, s0, ...) \
86 X86_OP_ENTRY3(op, op0, s0, None, None, None, None, ## __VA_ARGS__)
87#define X86_OP_ENTRYr(op, op0, s0, ...) \
88 X86_OP_ENTRY3(op, None, None, None, None, op0, s0, ## __VA_ARGS__)
b3e22b23
PB		 89#define X86_OP_ENTRY0(op, ...) \
90 X86_OP_ENTRY3(op, None, None, None, None, None, None, ## __VA_ARGS__)
91
caa01fad 92#define cpuid(feat) .cpuid = X86_FEAT_##feat,
b3e22b23
PB		 93#define i64 .special = X86_SPECIAL_i64,
94#define o64 .special = X86_SPECIAL_o64,
95#define xchg .special = X86_SPECIAL_Locked,
96#define mmx .special = X86_SPECIAL_MMX,
97#define zext0 .special = X86_SPECIAL_ZExtOp0,
98#define zext2 .special = X86_SPECIAL_ZExtOp2,
16fc5726 99#define avx_movx .special = X86_SPECIAL_AVXExtMov,
b3e22b23 100
20581aad
PB		 101#define vex1 .vex_class = 1,
102#define vex1_rep3 .vex_class = 1, .vex_special = X86_VEX_REPScalar,
103#define vex2 .vex_class = 2,
104#define vex2_rep3 .vex_class = 2, .vex_special = X86_VEX_REPScalar,
105#define vex3 .vex_class = 3,
106#define vex4 .vex_class = 4,
107#define vex4_unal .vex_class = 4, .vex_special = X86_VEX_SSEUnaligned,
3d304620 108#define vex4_rep5 .vex_class = 4, .vex_special = X86_VEX_REPScalar,
20581aad
PB		 109#define vex5 .vex_class = 5,
110#define vex6 .vex_class = 6,
111#define vex7 .vex_class = 7,
112#define vex8 .vex_class = 8,
113#define vex11 .vex_class = 11,
114#define vex12 .vex_class = 12,
115#define vex13 .vex_class = 13,
116
117#define avx2_256 .vex_special = X86_VEX_AVX2_256,
118
55a33286
PB		 119#define P_00 1
120#define P_66 (1 << PREFIX_DATA)
121#define P_F3 (1 << PREFIX_REPZ)
122#define P_F2 (1 << PREFIX_REPNZ)
123
124#define p_00 .valid_prefix = P_00,
125#define p_66 .valid_prefix = P_66,
126#define p_f3 .valid_prefix = P_F3,
127#define p_f2 .valid_prefix = P_F2,
128#define p_00_66 .valid_prefix = P_00 | P_66,
129#define p_00_f3 .valid_prefix = P_00 | P_F3,
130#define p_66_f2 .valid_prefix = P_66 | P_F2,
131#define p_00_66_f3 .valid_prefix = P_00 | P_66 | P_F3,
132#define p_66_f3_f2 .valid_prefix = P_66 | P_F3 | P_F2,
133#define p_00_66_f3_f2 .valid_prefix = P_00 | P_66 | P_F3 | P_F2,
134
b3e22b23
PB		 135static uint8_t get_modrm(DisasContext *s, CPUX86State *env)
136{
137 if (!s->has_modrm) {
138 s->modrm = x86_ldub_code(env, s);
139 s->has_modrm = true;
140 }
141 return s->modrm;
142}
143
92ec056a
PB		 144static inline const X86OpEntry *decode_by_prefix(DisasContext *s, const X86OpEntry entries[4])
145{
146 if (s->prefix & PREFIX_REPNZ) {
147 return &entries[3];
148 } else if (s->prefix & PREFIX_REPZ) {
149 return &entries[2];
150 } else if (s->prefix & PREFIX_DATA) {
151 return &entries[1];
152 } else {
153 return &entries[0];
154 }
155}
156
57f6bba0
PB		 157static void decode_group15(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
158{
159 /* only includes ldmxcsr and stmxcsr, because they have AVX variants. */
160 static const X86OpEntry group15_reg[8] = {
161 };
162
163 static const X86OpEntry group15_mem[8] = {
164 [2] = X86_OP_ENTRYr(LDMXCSR, E,d, vex5),
165 [3] = X86_OP_ENTRYw(STMXCSR, E,d, vex5),
166 };
167
168 uint8_t modrm = get_modrm(s, env);
169 if ((modrm >> 6) == 3) {
170 *entry = group15_reg[(modrm >> 3) & 7];
171 } else {
172 *entry = group15_mem[(modrm >> 3) & 7];
173 }
174}
175
1d0b9261
PB		 176static void decode_group17(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
177{
178 static const X86GenFunc group17_gen[8] = {
179 NULL, gen_BLSR, gen_BLSMSK, gen_BLSI,
180 };
181 int op = (get_modrm(s, env) >> 3) & 7;
182 entry->gen = group17_gen[op];
183}
184
ce4fcb94
PB		 185static void decode_group12(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
186{
187 static const X86OpEntry opcodes_group12[8] = {
188 {},
189 {},
190 X86_OP_ENTRY3(PSRLW_i, H,x, U,x, I,b, vex7 mmx avx2_256 p_00_66),
191 {},
192 X86_OP_ENTRY3(PSRAW_i, H,x, U,x, I,b, vex7 mmx avx2_256 p_00_66),
193 {},
194 X86_OP_ENTRY3(PSLLW_i, H,x, U,x, I,b, vex7 mmx avx2_256 p_00_66),
195 {},
196 };
197
198 int op = (get_modrm(s, env) >> 3) & 7;
199 *entry = opcodes_group12[op];
200}
201
202static void decode_group13(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
203{
204 static const X86OpEntry opcodes_group13[8] = {
205 {},
206 {},
207 X86_OP_ENTRY3(PSRLD_i, H,x, U,x, I,b, vex7 mmx avx2_256 p_00_66),
208 {},
209 X86_OP_ENTRY3(PSRAD_i, H,x, U,x, I,b, vex7 mmx avx2_256 p_00_66),
210 {},
211 X86_OP_ENTRY3(PSLLD_i, H,x, U,x, I,b, vex7 mmx avx2_256 p_00_66),
212 {},
213 };
214
215 int op = (get_modrm(s, env) >> 3) & 7;
216 *entry = opcodes_group13[op];
217}
218
219static void decode_group14(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
220{
221 static const X86OpEntry opcodes_group14[8] = {
222 /* grp14 */
223 {},
224 {},
225 X86_OP_ENTRY3(PSRLQ_i, H,x, U,x, I,b, vex7 mmx avx2_256 p_00_66),
226 X86_OP_ENTRY3(PSRLDQ_i, H,x, U,x, I,b, vex7 avx2_256 p_66),
227 {},
228 {},
229 X86_OP_ENTRY3(PSLLQ_i, H,x, U,x, I,b, vex7 mmx avx2_256 p_00_66),
230 X86_OP_ENTRY3(PSLLDQ_i, H,x, U,x, I,b, vex7 avx2_256 p_66),
231 };
232
233 int op = (get_modrm(s, env) >> 3) & 7;
234 *entry = opcodes_group14[op];
235}
236
92ec056a
PB		 237static void decode_0F6F(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
238{
239 static const X86OpEntry opcodes_0F6F[4] = {
cab529b0 240 X86_OP_ENTRY3(MOVDQ, P,q, None,None, Q,q, vex5 mmx), /* movq */
92ec056a
PB		 241 X86_OP_ENTRY3(MOVDQ, V,x, None,None, W,x, vex1), /* movdqa */
242 X86_OP_ENTRY3(MOVDQ, V,x, None,None, W,x, vex4_unal), /* movdqu */
243 {},
244 };
245 *entry = *decode_by_prefix(s, opcodes_0F6F);
246}
247
ce4fcb94
PB		 248static void decode_0F70(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
249{
250 static const X86OpEntry pshufw[4] = {
251 X86_OP_ENTRY3(PSHUFW, P,q, Q,q, I,b, vex4 mmx),
252 X86_OP_ENTRY3(PSHUFD, V,x, W,x, I,b, vex4 avx2_256),
253 X86_OP_ENTRY3(PSHUFHW, V,x, W,x, I,b, vex4 avx2_256),
254 X86_OP_ENTRY3(PSHUFLW, V,x, W,x, I,b, vex4 avx2_256),
255 };
256
257 *entry = *decode_by_prefix(s, pshufw);
258}
259
260static void decode_0F77(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
261{
262 if (!(s->prefix & PREFIX_VEX)) {
263 entry->gen = gen_EMMS;
264 } else if (!s->vex_l) {
265 entry->gen = gen_VZEROUPPER;
266 entry->vex_class = 8;
267 } else {
268 entry->gen = gen_VZEROALL;
269 entry->vex_class = 8;
270 }
271}
272
d1c1a422
PB		 273static void decode_0F78(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
274{
275 static const X86OpEntry opcodes_0F78[4] = {
276 {},
afa94dab 277 X86_OP_ENTRY3(EXTRQ_i, V,x, None,None, I,w, cpuid(SSE4A)), /* AMD extension */
d1c1a422 278 {},
afa94dab 279 X86_OP_ENTRY3(INSERTQ_i, V,x, U,x, I,w, cpuid(SSE4A)), /* AMD extension */
d1c1a422
PB		 280 };
281 *entry = *decode_by_prefix(s, opcodes_0F78);
282}
283
284static void decode_0F79(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
285{
286 if (s->prefix & PREFIX_REPNZ) {
afa94dab 287 entry->gen = gen_INSERTQ_r; /* AMD extension */
d1c1a422 288 } else if (s->prefix & PREFIX_DATA) {
afa94dab 289 entry->gen = gen_EXTRQ_r; /* AMD extension */
d1c1a422
PB		 290 } else {
291 entry->gen = NULL;
292 };
293}
294
295static void decode_0F7E(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
296{
297 static const X86OpEntry opcodes_0F7E[4] = {
298 X86_OP_ENTRY3(MOVD_from, E,y, None,None, P,y, vex5 mmx),
299 X86_OP_ENTRY3(MOVD_from, E,y, None,None, V,y, vex5),
300 X86_OP_ENTRY3(MOVQ, V,x, None,None, W,q, vex5), /* wrong dest Vy on SDM! */
301 {},
302 };
303 *entry = *decode_by_prefix(s, opcodes_0F7E);
304}
305
306static void decode_0F7F(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
307{
308 static const X86OpEntry opcodes_0F7F[4] = {
cab529b0 309 X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex5 mmx), /* movq */
d1c1a422
PB		 310 X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex1), /* movdqa */
311 X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex4_unal), /* movdqu */
312 {},
313 };
314 *entry = *decode_by_prefix(s, opcodes_0F7F);
315}
316
6bbeb98d
PB		 317static void decode_0FD6(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
318{
319 static const X86OpEntry movq[4] = {
320 {},
321 X86_OP_ENTRY3(MOVQ, W,x, None, None, V,q, vex5),
322 X86_OP_ENTRY3(MOVq_dq, V,dq, None, None, N,q),
323 X86_OP_ENTRY3(MOVq_dq, P,q, None, None, U,q),
324 };
325
326 *entry = *decode_by_prefix(s, movq);
327}
328
b3e22b23 329static const X86OpEntry opcodes_0F38_00toEF[240] = {
16fc5726
PB		 330 [0x00] = X86_OP_ENTRY3(PSHUFB, V,x, H,x, W,x, vex4 cpuid(SSSE3) mmx avx2_256 p_00_66),
331 [0x01] = X86_OP_ENTRY3(PHADDW, V,x, H,x, W,x, vex4 cpuid(SSSE3) mmx avx2_256 p_00_66),
332 [0x02] = X86_OP_ENTRY3(PHADDD, V,x, H,x, W,x, vex4 cpuid(SSSE3) mmx avx2_256 p_00_66),
333 [0x03] = X86_OP_ENTRY3(PHADDSW, V,x, H,x, W,x, vex4 cpuid(SSSE3) mmx avx2_256 p_00_66),
334 [0x04] = X86_OP_ENTRY3(PMADDUBSW, V,x, H,x, W,x, vex4 cpuid(SSSE3) mmx avx2_256 p_00_66),
335 [0x05] = X86_OP_ENTRY3(PHSUBW, V,x, H,x, W,x, vex4 cpuid(SSSE3) mmx avx2_256 p_00_66),
336 [0x06] = X86_OP_ENTRY3(PHSUBD, V,x, H,x, W,x, vex4 cpuid(SSSE3) mmx avx2_256 p_00_66),
337 [0x07] = X86_OP_ENTRY3(PHSUBSW, V,x, H,x, W,x, vex4 cpuid(SSSE3) mmx avx2_256 p_00_66),
338
339 [0x10] = X86_OP_ENTRY2(PBLENDVB, V,x, W,x, vex4 cpuid(SSE41) avx2_256 p_66),
a48b2697 340 [0x13] = X86_OP_ENTRY2(VCVTPH2PS, V,x, W,xh, vex11 cpuid(F16C) p_66),
16fc5726
PB		 341 [0x14] = X86_OP_ENTRY2(BLENDVPS, V,x, W,x, vex4 cpuid(SSE41) p_66),
342 [0x15] = X86_OP_ENTRY2(BLENDVPD, V,x, W,x, vex4 cpuid(SSE41) p_66),
343 /* Listed incorrectly as type 4 */
344 [0x16] = X86_OP_ENTRY3(VPERMD, V,qq, H,qq, W,qq, vex6 cpuid(AVX2) p_66),
345 [0x17] = X86_OP_ENTRY3(VPTEST, None,None, V,x, W,x, vex4 cpuid(SSE41) p_66),
346
347 /*
348 * Source operand listed as Mq/Ux and similar in the manual; incorrectly listed
349 * as 128-bit only in 2-17.
350 */
351 [0x20] = X86_OP_ENTRY3(VPMOVSXBW, V,x, None,None, W,q, vex5 cpuid(SSE41) avx_movx avx2_256 p_66),
352 [0x21] = X86_OP_ENTRY3(VPMOVSXBD, V,x, None,None, W,d, vex5 cpuid(SSE41) avx_movx avx2_256 p_66),
353 [0x22] = X86_OP_ENTRY3(VPMOVSXBQ, V,x, None,None, W,w, vex5 cpuid(SSE41) avx_movx avx2_256 p_66),
354 [0x23] = X86_OP_ENTRY3(VPMOVSXWD, V,x, None,None, W,q, vex5 cpuid(SSE41) avx_movx avx2_256 p_66),
355 [0x24] = X86_OP_ENTRY3(VPMOVSXWQ, V,x, None,None, W,d, vex5 cpuid(SSE41) avx_movx avx2_256 p_66),
356 [0x25] = X86_OP_ENTRY3(VPMOVSXDQ, V,x, None,None, W,q, vex5 cpuid(SSE41) avx_movx avx2_256 p_66),
357
358 /* Same as PMOVSX. */
359 [0x30] = X86_OP_ENTRY3(VPMOVZXBW, V,x, None,None, W,q, vex5 cpuid(SSE41) avx_movx avx2_256 p_66),
360 [0x31] = X86_OP_ENTRY3(VPMOVZXBD, V,x, None,None, W,d, vex5 cpuid(SSE41) avx_movx avx2_256 p_66),
361 [0x32] = X86_OP_ENTRY3(VPMOVZXBQ, V,x, None,None, W,w, vex5 cpuid(SSE41) avx_movx avx2_256 p_66),
362 [0x33] = X86_OP_ENTRY3(VPMOVZXWD, V,x, None,None, W,q, vex5 cpuid(SSE41) avx_movx avx2_256 p_66),
363 [0x34] = X86_OP_ENTRY3(VPMOVZXWQ, V,x, None,None, W,d, vex5 cpuid(SSE41) avx_movx avx2_256 p_66),
364 [0x35] = X86_OP_ENTRY3(VPMOVZXDQ, V,x, None,None, W,q, vex5 cpuid(SSE41) avx_movx avx2_256 p_66),
365 [0x36] = X86_OP_ENTRY3(VPERMD, V,qq, H,qq, W,qq, vex6 cpuid(AVX2) p_66),
366 [0x37] = X86_OP_ENTRY3(PCMPGTQ, V,x, H,x, W,x, vex4 cpuid(SSE42) avx2_256 p_66),
367
368 [0x40] = X86_OP_ENTRY3(PMULLD, V,x, H,x, W,x, vex4 cpuid(SSE41) avx2_256 p_66),
369 [0x41] = X86_OP_ENTRY3(VPHMINPOSUW, V,dq, None,None, W,dq, vex4 cpuid(SSE41) p_66),
370 /* Listed incorrectly as type 4 */
371 [0x45] = X86_OP_ENTRY3(VPSRLV, V,x, H,x, W,x, vex6 cpuid(AVX2) p_66),
372 [0x46] = X86_OP_ENTRY3(VPSRAV, V,x, H,x, W,x, vex6 cpuid(AVX2) p_66),
373 [0x47] = X86_OP_ENTRY3(VPSLLV, V,x, H,x, W,x, vex6 cpuid(AVX2) p_66),
374
375 [0x90] = X86_OP_ENTRY3(VPGATHERD, V,x, H,x, M,d, vex12 cpuid(AVX2) p_66), /* vpgatherdd/q */
376 [0x91] = X86_OP_ENTRY3(VPGATHERQ, V,x, H,x, M,q, vex12 cpuid(AVX2) p_66), /* vpgatherqd/q */
377 [0x92] = X86_OP_ENTRY3(VPGATHERD, V,x, H,x, M,d, vex12 cpuid(AVX2) p_66), /* vgatherdps/d */
378 [0x93] = X86_OP_ENTRY3(VPGATHERQ, V,x, H,x, M,q, vex12 cpuid(AVX2) p_66), /* vgatherqps/d */
379
2872b0f3
PB		 380 /* Should be exception type 2 but they do not have legacy SSE equivalents? */
381 [0x96] = X86_OP_ENTRY3(VFMADDSUB132Px, V,x, H,x, W,x, vex6 cpuid(FMA) p_66),
382 [0x97] = X86_OP_ENTRY3(VFMSUBADD132Px, V,x, H,x, W,x, vex6 cpuid(FMA) p_66),
383
384 [0xa6] = X86_OP_ENTRY3(VFMADDSUB213Px, V,x, H,x, W,x, vex6 cpuid(FMA) p_66),
385 [0xa7] = X86_OP_ENTRY3(VFMSUBADD213Px, V,x, H,x, W,x, vex6 cpuid(FMA) p_66),
386
387 [0xb6] = X86_OP_ENTRY3(VFMADDSUB231Px, V,x, H,x, W,x, vex6 cpuid(FMA) p_66),
388 [0xb7] = X86_OP_ENTRY3(VFMSUBADD231Px, V,x, H,x, W,x, vex6 cpuid(FMA) p_66),
389
16fc5726
PB		 390 [0x08] = X86_OP_ENTRY3(PSIGNB, V,x, H,x, W,x, vex4 cpuid(SSSE3) mmx avx2_256 p_00_66),
391 [0x09] = X86_OP_ENTRY3(PSIGNW, V,x, H,x, W,x, vex4 cpuid(SSSE3) mmx avx2_256 p_00_66),
392 [0x0a] = X86_OP_ENTRY3(PSIGND, V,x, H,x, W,x, vex4 cpuid(SSSE3) mmx avx2_256 p_00_66),
393 [0x0b] = X86_OP_ENTRY3(PMULHRSW, V,x, H,x, W,x, vex4 cpuid(SSSE3) mmx avx2_256 p_00_66),
394 [0x0c] = X86_OP_ENTRY3(VPERMILPS, V,x, H,x, W,x, vex4 cpuid(AVX) p_00_66),
395 [0x0d] = X86_OP_ENTRY3(VPERMILPD, V,x, H,x, W,x, vex4 cpuid(AVX) p_66),
396 [0x0e] = X86_OP_ENTRY3(VTESTPS, None,None, V,x, W,x, vex4 cpuid(AVX) p_66),
397 [0x0f] = X86_OP_ENTRY3(VTESTPD, None,None, V,x, W,x, vex4 cpuid(AVX) p_66),
398
399 [0x18] = X86_OP_ENTRY3(VPBROADCASTD, V,x, None,None, W,d, vex6 cpuid(AVX) p_66), /* vbroadcastss */
400 [0x19] = X86_OP_ENTRY3(VPBROADCASTQ, V,qq, None,None, W,q, vex6 cpuid(AVX) p_66), /* vbroadcastsd */
401 [0x1a] = X86_OP_ENTRY3(VBROADCASTx128, V,qq, None,None, WM,dq,vex6 cpuid(AVX) p_66),
402 [0x1c] = X86_OP_ENTRY3(PABSB, V,x, None,None, W,x, vex4 cpuid(SSSE3) mmx avx2_256 p_00_66),
403 [0x1d] = X86_OP_ENTRY3(PABSW, V,x, None,None, W,x, vex4 cpuid(SSSE3) mmx avx2_256 p_00_66),
404 [0x1e] = X86_OP_ENTRY3(PABSD, V,x, None,None, W,x, vex4 cpuid(SSSE3) mmx avx2_256 p_00_66),
405
406 [0x28] = X86_OP_ENTRY3(PMULDQ, V,x, H,x, W,x, vex4 cpuid(SSE41) avx2_256 p_66),
407 [0x29] = X86_OP_ENTRY3(PCMPEQQ, V,x, H,x, W,x, vex4 cpuid(SSE41) avx2_256 p_66),
408 [0x2a] = X86_OP_ENTRY3(MOVDQ, V,x, None,None, WM,x, vex1 cpuid(SSE41) avx2_256 p_66), /* movntdqa */
409 [0x2b] = X86_OP_ENTRY3(VPACKUSDW, V,x, H,x, W,x, vex4 cpuid(SSE41) avx2_256 p_66),
410 [0x2c] = X86_OP_ENTRY3(VMASKMOVPS, V,x, H,x, WM,x, vex6 cpuid(AVX) p_66),
411 [0x2d] = X86_OP_ENTRY3(VMASKMOVPD, V,x, H,x, WM,x, vex6 cpuid(AVX) p_66),
412 /* Incorrectly listed as Mx,Hx,Vx in the manual */
413 [0x2e] = X86_OP_ENTRY3(VMASKMOVPS_st, M,x, V,x, H,x, vex6 cpuid(AVX) p_66),
414 [0x2f] = X86_OP_ENTRY3(VMASKMOVPD_st, M,x, V,x, H,x, vex6 cpuid(AVX) p_66),
415
416 [0x38] = X86_OP_ENTRY3(PMINSB, V,x, H,x, W,x, vex4 cpuid(SSE41) avx2_256 p_66),
417 [0x39] = X86_OP_ENTRY3(PMINSD, V,x, H,x, W,x, vex4 cpuid(SSE41) avx2_256 p_66),
418 [0x3a] = X86_OP_ENTRY3(PMINUW, V,x, H,x, W,x, vex4 cpuid(SSE41) avx2_256 p_66),
419 [0x3b] = X86_OP_ENTRY3(PMINUD, V,x, H,x, W,x, vex4 cpuid(SSE41) avx2_256 p_66),
420 [0x3c] = X86_OP_ENTRY3(PMAXSB, V,x, H,x, W,x, vex4 cpuid(SSE41) avx2_256 p_66),
421 [0x3d] = X86_OP_ENTRY3(PMAXSD, V,x, H,x, W,x, vex4 cpuid(SSE41) avx2_256 p_66),
422 [0x3e] = X86_OP_ENTRY3(PMAXUW, V,x, H,x, W,x, vex4 cpuid(SSE41) avx2_256 p_66),
423 [0x3f] = X86_OP_ENTRY3(PMAXUD, V,x, H,x, W,x, vex4 cpuid(SSE41) avx2_256 p_66),
424
425 [0x58] = X86_OP_ENTRY3(VPBROADCASTD, V,x, None,None, W,d, vex6 cpuid(AVX2) p_66),
426 [0x59] = X86_OP_ENTRY3(VPBROADCASTQ, V,x, None,None, W,q, vex6 cpuid(AVX2) p_66),
427 [0x5a] = X86_OP_ENTRY3(VBROADCASTx128, V,qq, None,None, WM,dq,vex6 cpuid(AVX2) p_66),
428
429 [0x78] = X86_OP_ENTRY3(VPBROADCASTB, V,x, None,None, W,b, vex6 cpuid(AVX2) p_66),
430 [0x79] = X86_OP_ENTRY3(VPBROADCASTW, V,x, None,None, W,w, vex6 cpuid(AVX2) p_66),
431
432 [0x8c] = X86_OP_ENTRY3(VPMASKMOV, V,x, H,x, WM,x, vex6 cpuid(AVX2) p_66),
433 [0x8e] = X86_OP_ENTRY3(VPMASKMOV_st, M,x, V,x, H,x, vex6 cpuid(AVX2) p_66),
434
2872b0f3
PB		 435 /* Should be exception type 2 or 3 but they do not have legacy SSE equivalents? */
436 [0x98] = X86_OP_ENTRY3(VFMADD132Px, V,x, H,x, W,x, vex6 cpuid(FMA) p_66),
437 [0x99] = X86_OP_ENTRY3(VFMADD132Sx, V,x, H,x, W,x, vex6 cpuid(FMA) p_66),
438 [0x9a] = X86_OP_ENTRY3(VFMSUB132Px, V,x, H,x, W,x, vex6 cpuid(FMA) p_66),
439 [0x9b] = X86_OP_ENTRY3(VFMSUB132Sx, V,x, H,x, W,x, vex6 cpuid(FMA) p_66),
440 [0x9c] = X86_OP_ENTRY3(VFNMADD132Px, V,x, H,x, W,x, vex6 cpuid(FMA) p_66),
441 [0x9d] = X86_OP_ENTRY3(VFNMADD132Sx, V,x, H,x, W,x, vex6 cpuid(FMA) p_66),
442 [0x9e] = X86_OP_ENTRY3(VFNMSUB132Px, V,x, H,x, W,x, vex6 cpuid(FMA) p_66),
443 [0x9f] = X86_OP_ENTRY3(VFNMSUB132Sx, V,x, H,x, W,x, vex6 cpuid(FMA) p_66),
444
445 [0xa8] = X86_OP_ENTRY3(VFMADD213Px, V,x, H,x, W,x, vex6 cpuid(FMA) p_66),
446 [0xa9] = X86_OP_ENTRY3(VFMADD213Sx, V,x, H,x, W,x, vex6 cpuid(FMA) p_66),
447 [0xaa] = X86_OP_ENTRY3(VFMSUB213Px, V,x, H,x, W,x, vex6 cpuid(FMA) p_66),
448 [0xab] = X86_OP_ENTRY3(VFMSUB213Sx, V,x, H,x, W,x, vex6 cpuid(FMA) p_66),
449 [0xac] = X86_OP_ENTRY3(VFNMADD213Px, V,x, H,x, W,x, vex6 cpuid(FMA) p_66),
450 [0xad] = X86_OP_ENTRY3(VFNMADD213Sx, V,x, H,x, W,x, vex6 cpuid(FMA) p_66),
451 [0xae] = X86_OP_ENTRY3(VFNMSUB213Px, V,x, H,x, W,x, vex6 cpuid(FMA) p_66),
452 [0xaf] = X86_OP_ENTRY3(VFNMSUB213Sx, V,x, H,x, W,x, vex6 cpuid(FMA) p_66),
453
454 [0xb8] = X86_OP_ENTRY3(VFMADD231Px, V,x, H,x, W,x, vex6 cpuid(FMA) p_66),
455 [0xb9] = X86_OP_ENTRY3(VFMADD231Sx, V,x, H,x, W,x, vex6 cpuid(FMA) p_66),
456 [0xba] = X86_OP_ENTRY3(VFMSUB231Px, V,x, H,x, W,x, vex6 cpuid(FMA) p_66),
457 [0xbb] = X86_OP_ENTRY3(VFMSUB231Sx, V,x, H,x, W,x, vex6 cpuid(FMA) p_66),
458 [0xbc] = X86_OP_ENTRY3(VFNMADD231Px, V,x, H,x, W,x, vex6 cpuid(FMA) p_66),
459 [0xbd] = X86_OP_ENTRY3(VFNMADD231Sx, V,x, H,x, W,x, vex6 cpuid(FMA) p_66),
460 [0xbe] = X86_OP_ENTRY3(VFNMSUB231Px, V,x, H,x, W,x, vex6 cpuid(FMA) p_66),
461 [0xbf] = X86_OP_ENTRY3(VFNMSUB231Sx, V,x, H,x, W,x, vex6 cpuid(FMA) p_66),
462
e582b629
PB		 463 [0xc8] = X86_OP_ENTRY2(SHA1NEXTE, V,dq, W,dq, cpuid(SHA_NI)),
464 [0xc9] = X86_OP_ENTRY2(SHA1MSG1, V,dq, W,dq, cpuid(SHA_NI)),
465 [0xca] = X86_OP_ENTRY2(SHA1MSG2, V,dq, W,dq, cpuid(SHA_NI)),
466 [0xcb] = X86_OP_ENTRY2(SHA256RNDS2, V,dq, W,dq, cpuid(SHA_NI)),
467 [0xcc] = X86_OP_ENTRY2(SHA256MSG1, V,dq, W,dq, cpuid(SHA_NI)),
468 [0xcd] = X86_OP_ENTRY2(SHA256MSG2, V,dq, W,dq, cpuid(SHA_NI)),
469
16fc5726
PB		 470 [0xdb] = X86_OP_ENTRY3(VAESIMC, V,dq, None,None, W,dq, vex4 cpuid(AES) p_66),
471 [0xdc] = X86_OP_ENTRY3(VAESENC, V,x, H,x, W,x, vex4 cpuid(AES) p_66),
472 [0xdd] = X86_OP_ENTRY3(VAESENCLAST, V,x, H,x, W,x, vex4 cpuid(AES) p_66),
473 [0xde] = X86_OP_ENTRY3(VAESDEC, V,x, H,x, W,x, vex4 cpuid(AES) p_66),
474 [0xdf] = X86_OP_ENTRY3(VAESDECLAST, V,x, H,x, W,x, vex4 cpuid(AES) p_66),
b3e22b23
PB		 475};
476
477/* five rows for no prefix, 66, F3, F2, 66+F2 */
478static const X86OpEntry opcodes_0F38_F0toFF[16][5] = {
1d0b9261
PB		 479 [0] = {
480 X86_OP_ENTRY3(MOVBE, G,y, M,y, None,None, cpuid(MOVBE)),
481 X86_OP_ENTRY3(MOVBE, G,w, M,w, None,None, cpuid(MOVBE)),
482 {},
483 X86_OP_ENTRY2(CRC32, G,d, E,b, cpuid(SSE42)),
484 X86_OP_ENTRY2(CRC32, G,d, E,b, cpuid(SSE42)),
485 },
486 [1] = {
487 X86_OP_ENTRY3(MOVBE, M,y, G,y, None,None, cpuid(MOVBE)),
488 X86_OP_ENTRY3(MOVBE, M,w, G,w, None,None, cpuid(MOVBE)),
489 {},
490 X86_OP_ENTRY2(CRC32, G,d, E,y, cpuid(SSE42)),
491 X86_OP_ENTRY2(CRC32, G,d, E,w, cpuid(SSE42)),
492 },
493 [2] = {
494 X86_OP_ENTRY3(ANDN, G,y, B,y, E,y, vex13 cpuid(BMI1)),
495 {},
496 {},
497 {},
498 {},
499 },
500 [3] = {
501 X86_OP_GROUP3(group17, B,y, E,y, None,None, vex13 cpuid(BMI1)),
502 {},
503 {},
504 {},
505 {},
506 },
507 [5] = {
508 X86_OP_ENTRY3(BZHI, G,y, E,y, B,y, vex13 cpuid(BMI1)),
509 {},
510 X86_OP_ENTRY3(PEXT, G,y, B,y, E,y, vex13 cpuid(BMI2)),
511 X86_OP_ENTRY3(PDEP, G,y, B,y, E,y, vex13 cpuid(BMI2)),
512 {},
513 },
514 [6] = {
515 {},
516 X86_OP_ENTRY2(ADCX, G,y, E,y, cpuid(ADX)),
517 X86_OP_ENTRY2(ADOX, G,y, E,y, cpuid(ADX)),
518 X86_OP_ENTRY3(MULX, /* B,y, */ G,y, E,y, 2,y, vex13 cpuid(BMI2)),
519 {},
520 },
521 [7] = {
522 X86_OP_ENTRY3(BEXTR, G,y, E,y, B,y, vex13 cpuid(BMI1)),
523 X86_OP_ENTRY3(SHLX, G,y, E,y, B,y, vex13 cpuid(BMI1)),
524 X86_OP_ENTRY3(SARX, G,y, E,y, B,y, vex13 cpuid(BMI1)),
525 X86_OP_ENTRY3(SHRX, G,y, E,y, B,y, vex13 cpuid(BMI1)),
526 {},
527 },
b3e22b23
PB		 528};
529
530static void decode_0F38(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
531{
532 *b = x86_ldub_code(env, s);
533 if (*b < 0xf0) {
534 *entry = opcodes_0F38_00toEF[*b];
535 } else {
536 int row = 0;
537 if (s->prefix & PREFIX_REPZ) {
538 /* The REPZ (F3) prefix has priority over 66 */
539 row = 2;
540 } else {
541 row += s->prefix & PREFIX_REPNZ ? 3 : 0;
542 row += s->prefix & PREFIX_DATA ? 1 : 0;
543 }
544 *entry = opcodes_0F38_F0toFF[*b & 15][row];
545 }
546}
547
79068477
PB		 548static void decode_VINSERTPS(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
549{
550 static const X86OpEntry
551 vinsertps_reg = X86_OP_ENTRY4(VINSERTPS_r, V,dq, H,dq, U,dq, vex5 cpuid(SSE41) p_66),
552 vinsertps_mem = X86_OP_ENTRY4(VINSERTPS_m, V,dq, H,dq, M,d, vex5 cpuid(SSE41) p_66);
553
554 int modrm = get_modrm(s, env);
555 *entry = (modrm >> 6) == 3 ? vinsertps_reg : vinsertps_mem;
556}
557
b3e22b23 558static const X86OpEntry opcodes_0F3A[256] = {
79068477
PB		 559 /*
560 * These are VEX-only, but incorrectly listed in the manual as exception type 4.
561 * Also the "qq" instructions are sometimes omitted by Table 2-17, but are VEX256
562 * only.
563 */
564 [0x00] = X86_OP_ENTRY3(VPERMQ, V,qq, W,qq, I,b, vex6 cpuid(AVX2) p_66),
565 [0x01] = X86_OP_ENTRY3(VPERMQ, V,qq, W,qq, I,b, vex6 cpuid(AVX2) p_66), /* VPERMPD */
566 [0x02] = X86_OP_ENTRY4(VBLENDPS, V,x, H,x, W,x, vex6 cpuid(AVX2) p_66), /* VPBLENDD */
567 [0x04] = X86_OP_ENTRY3(VPERMILPS_i, V,x, W,x, I,b, vex6 cpuid(AVX) p_66),
568 [0x05] = X86_OP_ENTRY3(VPERMILPD_i, V,x, W,x, I,b, vex6 cpuid(AVX) p_66),
569 [0x06] = X86_OP_ENTRY4(VPERM2x128, V,qq, H,qq, W,qq, vex6 cpuid(AVX) p_66),
570
571 [0x14] = X86_OP_ENTRY3(PEXTRB, E,b, V,dq, I,b, vex5 cpuid(SSE41) zext0 p_66),
572 [0x15] = X86_OP_ENTRY3(PEXTRW, E,w, V,dq, I,b, vex5 cpuid(SSE41) zext0 p_66),
573 [0x16] = X86_OP_ENTRY3(PEXTR, E,y, V,dq, I,b, vex5 cpuid(SSE41) p_66),
574 [0x17] = X86_OP_ENTRY3(VEXTRACTPS, E,d, V,dq, I,b, vex5 cpuid(SSE41) p_66),
a48b2697 575 [0x1d] = X86_OP_ENTRY3(VCVTPS2PH, W,xh, V,x, I,b, vex11 cpuid(F16C) p_66),
79068477
PB		 576
577 [0x20] = X86_OP_ENTRY4(PINSRB, V,dq, H,dq, E,b, vex5 cpuid(SSE41) zext2 p_66),
578 [0x21] = X86_OP_GROUP0(VINSERTPS),
579 [0x22] = X86_OP_ENTRY4(PINSR, V,dq, H,dq, E,y, vex5 cpuid(SSE41) p_66),
580
581 [0x40] = X86_OP_ENTRY4(VDDPS, V,x, H,x, W,x, vex2 cpuid(SSE41) p_66),
582 [0x41] = X86_OP_ENTRY4(VDDPD, V,dq, H,dq, W,dq, vex2 cpuid(SSE41) p_66),
583 [0x42] = X86_OP_ENTRY4(VMPSADBW, V,x, H,x, W,x, vex2 cpuid(SSE41) avx2_256 p_66),
584 [0x44] = X86_OP_ENTRY4(PCLMULQDQ, V,dq, H,dq, W,dq, vex4 cpuid(PCLMULQDQ) p_66),
585 [0x46] = X86_OP_ENTRY4(VPERM2x128, V,qq, H,qq, W,qq, vex6 cpuid(AVX2) p_66),
586
587 [0x60] = X86_OP_ENTRY4(PCMPESTRM, None,None, V,dq, W,dq, vex4_unal cpuid(SSE42) p_66),
588 [0x61] = X86_OP_ENTRY4(PCMPESTRI, None,None, V,dq, W,dq, vex4_unal cpuid(SSE42) p_66),
589 [0x62] = X86_OP_ENTRY4(PCMPISTRM, None,None, V,dq, W,dq, vex4_unal cpuid(SSE42) p_66),
590 [0x63] = X86_OP_ENTRY4(PCMPISTRI, None,None, V,dq, W,dq, vex4_unal cpuid(SSE42) p_66),
591
592 [0x08] = X86_OP_ENTRY3(VROUNDPS, V,x, W,x, I,b, vex2 cpuid(SSE41) p_66),
593 [0x09] = X86_OP_ENTRY3(VROUNDPD, V,x, W,x, I,b, vex2 cpuid(SSE41) p_66),
594 /*
595 * Not listed as four operand in the manual. Also writes and reads 128-bits
596 * from the first two operands due to the V operand picking higher entries of
597 * the H operand; the "Vss,Hss,Wss" description from the manual is incorrect.
598 * For other unary operations such as VSQRTSx this is hidden by the "REPScalar"
599 * value of vex_special, because the table lists the operand types of VSQRTPx.
600 */
601 [0x0a] = X86_OP_ENTRY4(VROUNDSS, V,x, H,x, W,ss, vex3 cpuid(SSE41) p_66),
602 [0x0b] = X86_OP_ENTRY4(VROUNDSD, V,x, H,x, W,sd, vex3 cpuid(SSE41) p_66),
603 [0x0c] = X86_OP_ENTRY4(VBLENDPS, V,x, H,x, W,x, vex4 cpuid(SSE41) p_66),
604 [0x0d] = X86_OP_ENTRY4(VBLENDPD, V,x, H,x, W,x, vex4 cpuid(SSE41) p_66),
16fc5726
PB		 605 [0x0e] = X86_OP_ENTRY4(VPBLENDW, V,x, H,x, W,x, vex4 cpuid(SSE41) avx2_256 p_66),
606 [0x0f] = X86_OP_ENTRY4(PALIGNR, V,x, H,x, W,x, vex4 cpuid(SSSE3) mmx avx2_256 p_00_66),
79068477
PB		 607
608 [0x18] = X86_OP_ENTRY4(VINSERTx128, V,qq, H,qq, W,qq, vex6 cpuid(AVX) p_66),
609 [0x19] = X86_OP_ENTRY3(VEXTRACTx128, W,dq, V,qq, I,b, vex6 cpuid(AVX) p_66),
610
611 [0x38] = X86_OP_ENTRY4(VINSERTx128, V,qq, H,qq, W,qq, vex6 cpuid(AVX2) p_66),
612 [0x39] = X86_OP_ENTRY3(VEXTRACTx128, W,dq, V,qq, I,b, vex6 cpuid(AVX2) p_66),
613
614 /* Listed incorrectly as type 4 */
615 [0x4a] = X86_OP_ENTRY4(VBLENDVPS, V,x, H,x, W,x, vex6 cpuid(AVX) p_66),
616 [0x4b] = X86_OP_ENTRY4(VBLENDVPD, V,x, H,x, W,x, vex6 cpuid(AVX) p_66),
617 [0x4c] = X86_OP_ENTRY4(VPBLENDVB, V,x, H,x, W,x, vex6 cpuid(AVX) p_66 avx2_256),
618
e582b629
PB		 619 [0xcc] = X86_OP_ENTRY3(SHA1RNDS4, V,dq, W,dq, I,b, cpuid(SHA_NI)),
620
79068477
PB		 621 [0xdf] = X86_OP_ENTRY3(VAESKEYGEN, V,dq, W,dq, I,b, vex4 cpuid(AES) p_66),
622
1d0b9261 623 [0xF0] = X86_OP_ENTRY3(RORX, G,y, E,y, I,b, vex13 cpuid(BMI2) p_f2),
b3e22b23
PB		 624};
625
626static void decode_0F3A(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
627{
628 *b = x86_ldub_code(env, s);
629 *entry = opcodes_0F3A[*b];
630}
631
7170a17e
PB		 632/*
633 * There are some mistakes in the operands in the manual, and the load/store/register
634 * cases are easiest to keep separate, so the entries for 10-17 follow simplicity and
635 * efficiency of implementation rather than copying what the manual says.
636 *
637 * In particular:
638 *
639 * 1) "VMOVSS m32, xmm1" and "VMOVSD m64, xmm1" do not support VEX.vvvv != 1111b,
640 * but this is not mentioned in the tables.
641 *
642 * 2) MOVHLPS, MOVHPS, MOVHPD, MOVLPD, MOVLPS read the high quadword of one of their
643 * operands, which must therefore be dq; MOVLPD and MOVLPS also write the high
644 * quadword of the V operand.
645 */
646static void decode_0F10(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
647{
648 static const X86OpEntry opcodes_0F10_reg[4] = {
649 X86_OP_ENTRY3(MOVDQ, V,x, None,None, W,x, vex4_unal), /* MOVUPS */
650 X86_OP_ENTRY3(MOVDQ, V,x, None,None, W,x, vex4_unal), /* MOVUPD */
cab529b0
RZ		 651 X86_OP_ENTRY3(VMOVSS, V,x, H,x, W,x, vex5),
652 X86_OP_ENTRY3(VMOVLPx, V,x, H,x, W,x, vex5), /* MOVSD */
7170a17e
PB		 653 };
654
655 static const X86OpEntry opcodes_0F10_mem[4] = {
656 X86_OP_ENTRY3(MOVDQ, V,x, None,None, W,x, vex4_unal), /* MOVUPS */
657 X86_OP_ENTRY3(MOVDQ, V,x, None,None, W,x, vex4_unal), /* MOVUPD */
cab529b0
RZ		 658 X86_OP_ENTRY3(VMOVSS_ld, V,x, H,x, M,ss, vex5),
659 X86_OP_ENTRY3(VMOVSD_ld, V,x, H,x, M,sd, vex5),
7170a17e
PB		 660 };
661
662 if ((get_modrm(s, env) >> 6) == 3) {
663 *entry = *decode_by_prefix(s, opcodes_0F10_reg);
664 } else {
665 *entry = *decode_by_prefix(s, opcodes_0F10_mem);
666 }
667}
668
669static void decode_0F11(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
670{
671 static const X86OpEntry opcodes_0F11_reg[4] = {
afa94dab
RZ		 672 X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex4), /* MOVUPS */
673 X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex4), /* MOVUPD */
cab529b0
RZ		 674 X86_OP_ENTRY3(VMOVSS, W,x, H,x, V,x, vex5),
675 X86_OP_ENTRY3(VMOVLPx, W,x, H,x, V,q, vex5), /* MOVSD */
7170a17e
PB		 676 };
677
678 static const X86OpEntry opcodes_0F11_mem[4] = {
afa94dab
RZ		 679 X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex4), /* MOVUPS */
680 X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex4), /* MOVUPD */
cab529b0
RZ		 681 X86_OP_ENTRY3(VMOVSS_st, M,ss, None,None, V,x, vex5),
682 X86_OP_ENTRY3(VMOVLPx_st, M,sd, None,None, V,x, vex5), /* MOVSD */
7170a17e
PB		 683 };
684
685 if ((get_modrm(s, env) >> 6) == 3) {
686 *entry = *decode_by_prefix(s, opcodes_0F11_reg);
687 } else {
688 *entry = *decode_by_prefix(s, opcodes_0F11_mem);
689 }
690}
691
692static void decode_0F12(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
693{
694 static const X86OpEntry opcodes_0F12_mem[4] = {
695 /*
696 * Use dq for operand for compatibility with gen_MOVSD and
697 * to allow VEX128 only.
698 */
cab529b0
RZ		 699 X86_OP_ENTRY3(VMOVLPx_ld, V,dq, H,dq, M,q, vex5), /* MOVLPS */
700 X86_OP_ENTRY3(VMOVLPx_ld, V,dq, H,dq, M,q, vex5), /* MOVLPD */
7170a17e 701 X86_OP_ENTRY3(VMOVSLDUP, V,x, None,None, W,x, vex4 cpuid(SSE3)),
cab529b0 702 X86_OP_ENTRY3(VMOVDDUP, V,x, None,None, WM,q, vex5 cpuid(SSE3)), /* qq if VEX.256 */
7170a17e
PB		 703 };
704 static const X86OpEntry opcodes_0F12_reg[4] = {
cab529b0
RZ		 705 X86_OP_ENTRY3(VMOVHLPS, V,dq, H,dq, U,dq, vex7),
706 X86_OP_ENTRY3(VMOVLPx, W,x, H,x, U,q, vex5), /* MOVLPD */
7170a17e 707 X86_OP_ENTRY3(VMOVSLDUP, V,x, None,None, U,x, vex4 cpuid(SSE3)),
cab529b0 708 X86_OP_ENTRY3(VMOVDDUP, V,x, None,None, U,x, vex5 cpuid(SSE3)),
7170a17e
PB		 709 };
710
711 if ((get_modrm(s, env) >> 6) == 3) {
712 *entry = *decode_by_prefix(s, opcodes_0F12_reg);
713 } else {
714 *entry = *decode_by_prefix(s, opcodes_0F12_mem);
715 if ((s->prefix & PREFIX_REPNZ) && s->vex_l) {
716 entry->s2 = X86_SIZE_qq;
717 }
718 }
719}
720
721static void decode_0F16(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
722{
723 static const X86OpEntry opcodes_0F16_mem[4] = {
724 /*
725 * Operand 1 technically only reads the low 64 bits, but uses dq so that
726 * it is easier to check for op0 == op1 in an endianness-neutral manner.
727 */
cab529b0
RZ		 728 X86_OP_ENTRY3(VMOVHPx_ld, V,dq, H,dq, M,q, vex5), /* MOVHPS */
729 X86_OP_ENTRY3(VMOVHPx_ld, V,dq, H,dq, M,q, vex5), /* MOVHPD */
7170a17e
PB		 730 X86_OP_ENTRY3(VMOVSHDUP, V,x, None,None, W,x, vex4 cpuid(SSE3)),
731 {},
732 };
733 static const X86OpEntry opcodes_0F16_reg[4] = {
734 /* Same as above, operand 1 could be Hq if it wasn't for big-endian. */
cab529b0
RZ		 735 X86_OP_ENTRY3(VMOVLHPS, V,dq, H,dq, U,q, vex7),
736 X86_OP_ENTRY3(VMOVHPx, V,x, H,x, U,x, vex5), /* MOVHPD */
7170a17e
PB		 737 X86_OP_ENTRY3(VMOVSHDUP, V,x, None,None, U,x, vex4 cpuid(SSE3)),
738 {},
739 };
740
741 if ((get_modrm(s, env) >> 6) == 3) {
742 *entry = *decode_by_prefix(s, opcodes_0F16_reg);
743 } else {
744 *entry = *decode_by_prefix(s, opcodes_0F16_mem);
745 }
746}
747
f8d19eec
PB		 748static void decode_0F2A(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
749{
750 static const X86OpEntry opcodes_0F2A[4] = {
751 X86_OP_ENTRY3(CVTPI2Px, V,x, None,None, Q,q),
752 X86_OP_ENTRY3(CVTPI2Px, V,x, None,None, Q,q),
753 X86_OP_ENTRY3(VCVTSI2Sx, V,x, H,x, E,y, vex3),
754 X86_OP_ENTRY3(VCVTSI2Sx, V,x, H,x, E,y, vex3),
755 };
756 *entry = *decode_by_prefix(s, opcodes_0F2A);
757}
758
759static void decode_0F2B(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
760{
761 static const X86OpEntry opcodes_0F2B[4] = {
8bf171c2
RZ		 762 X86_OP_ENTRY3(MOVDQ, M,x, None,None, V,x, vex1), /* MOVNTPS */
763 X86_OP_ENTRY3(MOVDQ, M,x, None,None, V,x, vex1), /* MOVNTPD */
764 /* AMD extensions */
f8d19eec
PB		 765 X86_OP_ENTRY3(VMOVSS_st, M,ss, None,None, V,x, vex4 cpuid(SSE4A)), /* MOVNTSS */
766 X86_OP_ENTRY3(VMOVLPx_st, M,sd, None,None, V,x, vex4 cpuid(SSE4A)), /* MOVNTSD */
767 };
768
769 *entry = *decode_by_prefix(s, opcodes_0F2B);
770}
771
772static void decode_0F2C(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
773{
774 static const X86OpEntry opcodes_0F2C[4] = {
775 /* Listed as ps/pd in the manual, but CVTTPS2PI only reads 64-bit. */
776 X86_OP_ENTRY3(CVTTPx2PI, P,q, None,None, W,q),
777 X86_OP_ENTRY3(CVTTPx2PI, P,q, None,None, W,dq),
778 X86_OP_ENTRY3(VCVTTSx2SI, G,y, None,None, W,ss, vex3),
779 X86_OP_ENTRY3(VCVTTSx2SI, G,y, None,None, W,sd, vex3),
780 };
781 *entry = *decode_by_prefix(s, opcodes_0F2C);
782}
783
784static void decode_0F2D(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
785{
786 static const X86OpEntry opcodes_0F2D[4] = {
787 /* Listed as ps/pd in the manual, but CVTPS2PI only reads 64-bit. */
788 X86_OP_ENTRY3(CVTPx2PI, P,q, None,None, W,q),
789 X86_OP_ENTRY3(CVTPx2PI, P,q, None,None, W,dq),
790 X86_OP_ENTRY3(VCVTSx2SI, G,y, None,None, W,ss, vex3),
791 X86_OP_ENTRY3(VCVTSx2SI, G,y, None,None, W,sd, vex3),
792 };
793 *entry = *decode_by_prefix(s, opcodes_0F2D);
794}
795
2b55e479
PB		 796static void decode_VxCOMISx(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
797{
798 /*
799 * VUCOMISx and VCOMISx are different and use no-prefix and 0x66 for SS and SD
800 * respectively. Scalar values usually are associated with 0xF2 and 0xF3, for
801 * which X86_VEX_REPScalar exists, but here it has to be decoded by hand.
802 */
803 entry->s1 = entry->s2 = (s->prefix & PREFIX_DATA ? X86_SIZE_sd : X86_SIZE_ss);
804 entry->gen = (*b == 0x2E ? gen_VUCOMI : gen_VCOMI);
805}
806
03b45880
PB		 807static void decode_sse_unary(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
808{
809 if (!(s->prefix & (PREFIX_REPZ | PREFIX_REPNZ))) {
810 entry->op1 = X86_TYPE_None;
811 entry->s1 = X86_SIZE_None;
812 }
813 switch (*b) {
814 case 0x51: entry->gen = gen_VSQRT; break;
815 case 0x52: entry->gen = gen_VRSQRT; break;
816 case 0x53: entry->gen = gen_VRCP; break;
03b45880
PB		 817 }
818}
819
abd41884
PB		 820static void decode_0F5A(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
821{
822 static const X86OpEntry opcodes_0F5A[4] = {
823 X86_OP_ENTRY2(VCVTPS2PD, V,x, W,xh, vex2), /* VCVTPS2PD */
824 X86_OP_ENTRY2(VCVTPD2PS, V,x, W,x, vex2), /* VCVTPD2PS */
825 X86_OP_ENTRY3(VCVTSS2SD, V,x, H,x, W,x, vex2_rep3), /* VCVTSS2SD */
826 X86_OP_ENTRY3(VCVTSD2SS, V,x, H,x, W,x, vex2_rep3), /* VCVTSD2SS */
827 };
828 *entry = *decode_by_prefix(s, opcodes_0F5A);
829}
830
03b45880
PB		 831static void decode_0F5B(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
832{
833 static const X86OpEntry opcodes_0F5B[4] = {
834 X86_OP_ENTRY2(VCVTDQ2PS, V,x, W,x, vex2),
835 X86_OP_ENTRY2(VCVTPS2DQ, V,x, W,x, vex2),
836 X86_OP_ENTRY2(VCVTTPS2DQ, V,x, W,x, vex2),
837 {},
838 };
839 *entry = *decode_by_prefix(s, opcodes_0F5B);
840}
841
6bbeb98d
PB		 842static void decode_0FE6(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
843{
844 static const X86OpEntry opcodes_0FE6[4] = {
845 {},
846 X86_OP_ENTRY2(VCVTTPD2DQ, V,x, W,x, vex2),
cab529b0 847 X86_OP_ENTRY2(VCVTDQ2PD, V,x, W,x, vex5),
6bbeb98d
PB		 848 X86_OP_ENTRY2(VCVTPD2DQ, V,x, W,x, vex2),
849 };
850 *entry = *decode_by_prefix(s, opcodes_0FE6);
851}
852
b3e22b23 853static const X86OpEntry opcodes_0F[256] = {
71a0891d
PB		 854 [0x0E] = X86_OP_ENTRY0(EMMS, cpuid(3DNOW)), /* femms */
855 /*
856 * 3DNow!'s opcode byte comes *after* modrm and displacements, making it
857 * more like an Ib operand. Dispatch to the right helper in a single gen_*
858 * function.
859 */
860 [0x0F] = X86_OP_ENTRY3(3dnow, P,q, Q,q, I,b, cpuid(3DNOW)),
861
7170a17e
PB		 862 [0x10] = X86_OP_GROUP0(0F10),
863 [0x11] = X86_OP_GROUP0(0F11),
864 [0x12] = X86_OP_GROUP0(0F12),
cab529b0 865 [0x13] = X86_OP_ENTRY3(VMOVLPx_st, M,q, None,None, V,q, vex5 p_00_66),
7170a17e
PB		 866 [0x14] = X86_OP_ENTRY3(VUNPCKLPx, V,x, H,x, W,x, vex4 p_00_66),
867 [0x15] = X86_OP_ENTRY3(VUNPCKHPx, V,x, H,x, W,x, vex4 p_00_66),
868 [0x16] = X86_OP_GROUP0(0F16),
869 /* Incorrectly listed as Mq,Vq in the manual */
cab529b0 870 [0x17] = X86_OP_ENTRY3(VMOVHPx_st, M,q, None,None, V,dq, vex5 p_00_66),
7170a17e 871
03b45880 872 [0x50] = X86_OP_ENTRY3(MOVMSK, G,y, None,None, U,x, vex7 p_00_66),
afa94dab
RZ		 873 [0x51] = X86_OP_GROUP3(sse_unary, V,x, H,x, W,x, vex2_rep3 p_00_66_f3_f2), /* sqrtps */
874 [0x52] = X86_OP_GROUP3(sse_unary, V,x, H,x, W,x, vex4_rep5 p_00_f3), /* rsqrtps */
875 [0x53] = X86_OP_GROUP3(sse_unary, V,x, H,x, W,x, vex4_rep5 p_00_f3), /* rcpps */
03b45880
PB		 876 [0x54] = X86_OP_ENTRY3(PAND, V,x, H,x, W,x, vex4 p_00_66), /* vand */
877 [0x55] = X86_OP_ENTRY3(PANDN, V,x, H,x, W,x, vex4 p_00_66), /* vandn */
878 [0x56] = X86_OP_ENTRY3(POR, V,x, H,x, W,x, vex4 p_00_66), /* vor */
879 [0x57] = X86_OP_ENTRY3(PXOR, V,x, H,x, W,x, vex4 p_00_66), /* vxor */
880
92ec056a
PB		 881 [0x60] = X86_OP_ENTRY3(PUNPCKLBW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
882 [0x61] = X86_OP_ENTRY3(PUNPCKLWD, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
883 [0x62] = X86_OP_ENTRY3(PUNPCKLDQ, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
884 [0x63] = X86_OP_ENTRY3(PACKSSWB, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
885 [0x64] = X86_OP_ENTRY3(PCMPGTB, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
886 [0x65] = X86_OP_ENTRY3(PCMPGTW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
887 [0x66] = X86_OP_ENTRY3(PCMPGTD, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
888 [0x67] = X86_OP_ENTRY3(PACKUSWB, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
889
ce4fcb94
PB		 890 [0x70] = X86_OP_GROUP0(0F70),
891 [0x71] = X86_OP_GROUP0(group12),
892 [0x72] = X86_OP_GROUP0(group13),
893 [0x73] = X86_OP_GROUP0(group14),
894 [0x74] = X86_OP_ENTRY3(PCMPEQB, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
895 [0x75] = X86_OP_ENTRY3(PCMPEQW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
896 [0x76] = X86_OP_ENTRY3(PCMPEQD, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
897 [0x77] = X86_OP_GROUP0(0F77),
898
f8d19eec
PB		 899 [0x28] = X86_OP_ENTRY3(MOVDQ, V,x, None,None, W,x, vex1 p_00_66), /* MOVAPS */
900 [0x29] = X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex1 p_00_66), /* MOVAPS */
901 [0x2A] = X86_OP_GROUP0(0F2A),
902 [0x2B] = X86_OP_GROUP0(0F2B),
903 [0x2C] = X86_OP_GROUP0(0F2C),
904 [0x2D] = X86_OP_GROUP0(0F2D),
2b55e479
PB		 905 [0x2E] = X86_OP_GROUP3(VxCOMISx, None,None, V,x, W,x, vex3 p_00_66), /* VUCOMISS/SD */
906 [0x2F] = X86_OP_GROUP3(VxCOMISx, None,None, V,x, W,x, vex3 p_00_66), /* VCOMISS/SD */
f8d19eec 907
b3e22b23
PB		 908 [0x38] = X86_OP_GROUP0(0F38),
909 [0x3a] = X86_OP_GROUP0(0F3A),
92ec056a 910
03b45880
PB		 911 [0x58] = X86_OP_ENTRY3(VADD, V,x, H,x, W,x, vex2_rep3 p_00_66_f3_f2),
912 [0x59] = X86_OP_ENTRY3(VMUL, V,x, H,x, W,x, vex2_rep3 p_00_66_f3_f2),
abd41884 913 [0x5a] = X86_OP_GROUP0(0F5A),
03b45880
PB		 914 [0x5b] = X86_OP_GROUP0(0F5B),
915 [0x5c] = X86_OP_ENTRY3(VSUB, V,x, H,x, W,x, vex2_rep3 p_00_66_f3_f2),
916 [0x5d] = X86_OP_ENTRY3(VMIN, V,x, H,x, W,x, vex2_rep3 p_00_66_f3_f2),
917 [0x5e] = X86_OP_ENTRY3(VDIV, V,x, H,x, W,x, vex2_rep3 p_00_66_f3_f2),
918 [0x5f] = X86_OP_ENTRY3(VMAX, V,x, H,x, W,x, vex2_rep3 p_00_66_f3_f2),
919
92ec056a
PB		 920 [0x68] = X86_OP_ENTRY3(PUNPCKHBW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
921 [0x69] = X86_OP_ENTRY3(PUNPCKHWD, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
922 [0x6a] = X86_OP_ENTRY3(PUNPCKHDQ, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
923 [0x6b] = X86_OP_ENTRY3(PACKSSDW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
924 [0x6c] = X86_OP_ENTRY3(PUNPCKLQDQ, V,x, H,x, W,x, vex4 p_66 avx2_256),
925 [0x6d] = X86_OP_ENTRY3(PUNPCKHQDQ, V,x, H,x, W,x, vex4 p_66 avx2_256),
926 [0x6e] = X86_OP_ENTRY3(MOVD_to, V,x, None,None, E,y, vex5 mmx p_00_66), /* wrong dest Vy on SDM! */
927 [0x6f] = X86_OP_GROUP0(0F6F),
1d0efbdb 928
d1c1a422
PB		 929 [0x78] = X86_OP_GROUP0(0F78),
930 [0x79] = X86_OP_GROUP2(0F79, V,x, U,x, cpuid(SSE4A)),
931 [0x7c] = X86_OP_ENTRY3(VHADD, V,x, H,x, W,x, vex2 cpuid(SSE3) p_66_f2),
932 [0x7d] = X86_OP_ENTRY3(VHSUB, V,x, H,x, W,x, vex2 cpuid(SSE3) p_66_f2),
933 [0x7e] = X86_OP_GROUP0(0F7E),
934 [0x7f] = X86_OP_GROUP0(0F7F),
935
57f6bba0
PB		 936 [0xae] = X86_OP_GROUP0(group15),
937
aba2b8ec
PB		 938 [0xc2] = X86_OP_ENTRY4(VCMP, V,x, H,x, W,x, vex2_rep3 p_00_66_f3_f2),
939 [0xc4] = X86_OP_ENTRY4(PINSRW, V,dq,H,dq,E,w, vex5 mmx p_00_66),
940 [0xc5] = X86_OP_ENTRY3(PEXTRW, G,d, U,dq,I,b, vex5 mmx p_00_66),
941 [0xc6] = X86_OP_ENTRY4(VSHUF, V,x, H,x, W,x, vex4 p_00_66),
942
6bbeb98d
PB		 943 [0xd0] = X86_OP_ENTRY3(VADDSUB, V,x, H,x, W,x, vex2 cpuid(SSE3) p_66_f2),
944 [0xd1] = X86_OP_ENTRY3(PSRLW_r, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
945 [0xd2] = X86_OP_ENTRY3(PSRLD_r, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
946 [0xd3] = X86_OP_ENTRY3(PSRLQ_r, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
947 [0xd4] = X86_OP_ENTRY3(PADDQ, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
948 [0xd5] = X86_OP_ENTRY3(PMULLW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
949 [0xd6] = X86_OP_GROUP0(0FD6),
950 [0xd7] = X86_OP_ENTRY3(PMOVMSKB, G,d, None,None, U,x, vex7 mmx avx2_256 p_00_66),
951
952 [0xe0] = X86_OP_ENTRY3(PAVGB, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
953 [0xe1] = X86_OP_ENTRY3(PSRAW_r, V,x, H,x, W,x, vex7 mmx avx2_256 p_00_66),
954 [0xe2] = X86_OP_ENTRY3(PSRAD_r, V,x, H,x, W,x, vex7 mmx avx2_256 p_00_66),
955 [0xe3] = X86_OP_ENTRY3(PAVGW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
956 [0xe4] = X86_OP_ENTRY3(PMULHUW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
957 [0xe5] = X86_OP_ENTRY3(PMULHW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
958 [0xe6] = X86_OP_GROUP0(0FE6),
959 [0xe7] = X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex1 mmx p_00_66), /* MOVNTQ/MOVNTDQ */
960
961 [0xf0] = X86_OP_ENTRY3(MOVDQ, V,x, None,None, WM,x, vex4_unal cpuid(SSE3) p_f2), /* LDDQU */
962 [0xf1] = X86_OP_ENTRY3(PSLLW_r, V,x, H,x, W,x, vex7 mmx avx2_256 p_00_66),
963 [0xf2] = X86_OP_ENTRY3(PSLLD_r, V,x, H,x, W,x, vex7 mmx avx2_256 p_00_66),
964 [0xf3] = X86_OP_ENTRY3(PSLLQ_r, V,x, H,x, W,x, vex7 mmx avx2_256 p_00_66),
965 [0xf4] = X86_OP_ENTRY3(PMULUDQ, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
966 [0xf5] = X86_OP_ENTRY3(PMADDWD, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
967 [0xf6] = X86_OP_ENTRY3(PSADBW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
968 [0xf7] = X86_OP_ENTRY3(MASKMOV, None,None, V,dq, U,dq, vex4_unal avx2_256 mmx p_00_66),
969
1d0efbdb
PB		 970 /* Incorrectly missing from 2-17 */
971 [0xd8] = X86_OP_ENTRY3(PSUBUSB, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
972 [0xd9] = X86_OP_ENTRY3(PSUBUSW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
973 [0xda] = X86_OP_ENTRY3(PMINUB, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
974 [0xdb] = X86_OP_ENTRY3(PAND, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
975 [0xdc] = X86_OP_ENTRY3(PADDUSB, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
976 [0xdd] = X86_OP_ENTRY3(PADDUSW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
977 [0xde] = X86_OP_ENTRY3(PMAXUB, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
978 [0xdf] = X86_OP_ENTRY3(PANDN, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
979
980 [0xe8] = X86_OP_ENTRY3(PSUBSB, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
981 [0xe9] = X86_OP_ENTRY3(PSUBSW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
982 [0xea] = X86_OP_ENTRY3(PMINSW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
983 [0xeb] = X86_OP_ENTRY3(POR, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
984 [0xec] = X86_OP_ENTRY3(PADDSB, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
985 [0xed] = X86_OP_ENTRY3(PADDSW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
986 [0xee] = X86_OP_ENTRY3(PMAXSW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
987 [0xef] = X86_OP_ENTRY3(PXOR, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
988
989 [0xf8] = X86_OP_ENTRY3(PSUBB, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
990 [0xf9] = X86_OP_ENTRY3(PSUBW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
991 [0xfa] = X86_OP_ENTRY3(PSUBD, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
992 [0xfb] = X86_OP_ENTRY3(PSUBQ, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
993 [0xfc] = X86_OP_ENTRY3(PADDB, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
994 [0xfd] = X86_OP_ENTRY3(PADDW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
995 [0xfe] = X86_OP_ENTRY3(PADDD, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
996 /* 0xff = UD0 */
b3e22b23
PB		 997};
998
999static void do_decode_0F(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
1000{
1001 *entry = opcodes_0F[*b];
1002}
1003
1004static void decode_0F(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
1005{
1006 *b = x86_ldub_code(env, s);
1007 do_decode_0F(s, env, entry, b);
1008}
1009
1010static const X86OpEntry opcodes_root[256] = {
1011 [0x0F] = X86_OP_GROUP0(0F),
1012};
1013
1014#undef mmx
20581aad
PB		 1015#undef vex1
1016#undef vex2
1017#undef vex3
1018#undef vex4
1019#undef vex4_unal
1020#undef vex5
1021#undef vex6
1022#undef vex7
1023#undef vex8
1024#undef vex11
1025#undef vex12
1026#undef vex13
b3e22b23
PB		 1027
1028/*
1029 * Decode the fixed part of the opcode and place the last
1030 * in b.
1031 */
1032static void decode_root(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
1033{
1034 *entry = opcodes_root[*b];
1035}
1036
1037
1038static int decode_modrm(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode,
1039 X86DecodedOp *op, X86OpType type)
1040{
1041 int modrm = get_modrm(s, env);
1042 if ((modrm >> 6) == 3) {
1043 if (s->prefix & PREFIX_LOCK) {
1044 decode->e.gen = gen_illegal;
1045 return 0xff;
1046 }
1047 op->n = (modrm & 7);
1048 if (type != X86_TYPE_Q && type != X86_TYPE_N) {
1049 op->n |= REX_B(s);
1050 }
1051 } else {
1052 op->has_ea = true;
1053 op->n = -1;
1054 decode->mem = gen_lea_modrm_0(env, s, get_modrm(s, env));
1055 }
1056 return modrm;
1057}
1058
1059static bool decode_op_size(DisasContext *s, X86OpEntry *e, X86OpSize size, MemOp *ot)
1060{
1061 switch (size) {
1062 case X86_SIZE_b: /* byte */
1063 *ot = MO_8;
1064 return true;
1065
1066 case X86_SIZE_d: /* 32-bit */
1067 case X86_SIZE_ss: /* SSE/AVX scalar single precision */
1068 *ot = MO_32;
1069 return true;
1070
1071 case X86_SIZE_p: /* Far pointer, return offset size */
1072 case X86_SIZE_s: /* Descriptor, return offset size */
1073 case X86_SIZE_v: /* 16/32/64-bit, based on operand size */
1074 *ot = s->dflag;
1075 return true;
1076
1077 case X86_SIZE_pi: /* MMX */
1078 case X86_SIZE_q: /* 64-bit */
1079 case X86_SIZE_sd: /* SSE/AVX scalar double precision */
1080 *ot = MO_64;
1081 return true;
1082
1083 case X86_SIZE_w: /* 16-bit */
1084 *ot = MO_16;
1085 return true;
1086
1087 case X86_SIZE_y: /* 32/64-bit, based on operand size */
1088 *ot = s->dflag == MO_16 ? MO_32 : s->dflag;
1089 return true;
1090
1091 case X86_SIZE_z: /* 16-bit for 16-bit operand size, else 32-bit */
1092 *ot = s->dflag == MO_16 ? MO_16 : MO_32;
1093 return true;
1094
1095 case X86_SIZE_dq: /* SSE/AVX 128-bit */
1096 if (e->special == X86_SPECIAL_MMX &&
1097 !(s->prefix & (PREFIX_DATA | PREFIX_REPZ | PREFIX_REPNZ))) {
1098 *ot = MO_64;
1099 return true;
1100 }
1101 if (s->vex_l && e->s0 != X86_SIZE_qq && e->s1 != X86_SIZE_qq) {
1102 return false;
1103 }
1104 *ot = MO_128;
1105 return true;
1106
1107 case X86_SIZE_qq: /* AVX 256-bit */
1108 if (!s->vex_l) {
1109 return false;
1110 }
1111 *ot = MO_256;
1112 return true;
1113
1114 case X86_SIZE_x: /* 128/256-bit, based on operand size */
1115 if (e->special == X86_SPECIAL_MMX &&
1116 !(s->prefix & (PREFIX_DATA | PREFIX_REPZ | PREFIX_REPNZ))) {
1117 *ot = MO_64;
1118 return true;
1119 }
1120 /* fall through */
1121 case X86_SIZE_ps: /* SSE/AVX packed single precision */
1122 case X86_SIZE_pd: /* SSE/AVX packed double precision */
1123 *ot = s->vex_l ? MO_256 : MO_128;
1124 return true;
1125
a48b2697 1126 case X86_SIZE_xh: /* SSE/AVX packed half register */
cf5ec664
PB		 1127 *ot = s->vex_l ? MO_128 : MO_64;
1128 return true;
1129
b3e22b23
PB		 1130 case X86_SIZE_d64: /* Default to 64-bit in 64-bit mode */
1131 *ot = CODE64(s) && s->dflag == MO_32 ? MO_64 : s->dflag;
1132 return true;
1133
1134 case X86_SIZE_f64: /* Ignore size override prefix in 64-bit mode */
1135 *ot = CODE64(s) ? MO_64 : s->dflag;
1136 return true;
1137
1138 default:
1139 *ot = -1;
1140 return true;
1141 }
1142}
1143
1144static bool decode_op(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode,
1145 X86DecodedOp *op, X86OpType type, int b)
1146{
1147 int modrm;
1148
1149 switch (type) {
1150 case X86_TYPE_None: /* Implicit or absent */
1151 case X86_TYPE_A: /* Implicit */
1152 case X86_TYPE_F: /* EFLAGS/RFLAGS */
1153 break;
1154
1155 case X86_TYPE_B: /* VEX.vvvv selects a GPR */
1156 op->unit = X86_OP_INT;
1157 op->n = s->vex_v;
1158 break;
1159
1160 case X86_TYPE_C: /* REG in the modrm byte selects a control register */
1161 op->unit = X86_OP_CR;
1162 goto get_reg;
1163
1164 case X86_TYPE_D: /* REG in the modrm byte selects a debug register */
1165 op->unit = X86_OP_DR;
1166 goto get_reg;
1167
1168 case X86_TYPE_G: /* REG in the modrm byte selects a GPR */
1169 op->unit = X86_OP_INT;
1170 goto get_reg;
1171
1172 case X86_TYPE_S: /* reg selects a segment register */
1173 op->unit = X86_OP_SEG;
1174 goto get_reg;
1175
1176 case X86_TYPE_P:
1177 op->unit = X86_OP_MMX;
1178 goto get_reg;
1179
1180 case X86_TYPE_V: /* reg in the modrm byte selects an XMM/YMM register */
1181 if (decode->e.special == X86_SPECIAL_MMX &&
1182 !(s->prefix & (PREFIX_DATA | PREFIX_REPZ | PREFIX_REPNZ))) {
1183 op->unit = X86_OP_MMX;
1184 } else {
1185 op->unit = X86_OP_SSE;
1186 }
1187 get_reg:
1188 op->n = ((get_modrm(s, env) >> 3) & 7) | REX_R(s);
1189 break;
1190
1191 case X86_TYPE_E: /* ALU modrm operand */
1192 op->unit = X86_OP_INT;
1193 goto get_modrm;
1194
1195 case X86_TYPE_Q: /* MMX modrm operand */
1196 op->unit = X86_OP_MMX;
1197 goto get_modrm;
1198
1199 case X86_TYPE_W: /* XMM/YMM modrm operand */
1200 if (decode->e.special == X86_SPECIAL_MMX &&
1201 !(s->prefix & (PREFIX_DATA | PREFIX_REPZ | PREFIX_REPNZ))) {
1202 op->unit = X86_OP_MMX;
1203 } else {
1204 op->unit = X86_OP_SSE;
1205 }
1206 goto get_modrm;
1207
1208 case X86_TYPE_N: /* R/M in the modrm byte selects an MMX register */
1209 op->unit = X86_OP_MMX;
1210 goto get_modrm_reg;
1211
1212 case X86_TYPE_U: /* R/M in the modrm byte selects an XMM/YMM register */
1213 if (decode->e.special == X86_SPECIAL_MMX &&
1214 !(s->prefix & (PREFIX_DATA | PREFIX_REPZ | PREFIX_REPNZ))) {
1215 op->unit = X86_OP_MMX;
1216 } else {
1217 op->unit = X86_OP_SSE;
1218 }
1219 goto get_modrm_reg;
1220
1221 case X86_TYPE_R: /* R/M in the modrm byte selects a register */
1222 op->unit = X86_OP_INT;
1223 get_modrm_reg:
1224 modrm = get_modrm(s, env);
1225 if ((modrm >> 6) != 3) {
1226 return false;
1227 }
1228 goto get_modrm;
1229
6bbeb98d
PB		 1230 case X86_TYPE_WM: /* modrm byte selects an XMM/YMM memory operand */
1231 op->unit = X86_OP_SSE;
1232 /* fall through */
b3e22b23
PB		 1233 case X86_TYPE_M: /* modrm byte selects a memory operand */
1234 modrm = get_modrm(s, env);
1235 if ((modrm >> 6) == 3) {
1236 return false;
1237 }
1238 get_modrm:
1239 decode_modrm(s, env, decode, op, type);
1240 break;
1241
1242 case X86_TYPE_O: /* Absolute address encoded in the instruction */
1243 op->unit = X86_OP_INT;
1244 op->has_ea = true;
1245 op->n = -1;
1246 decode->mem = (AddressParts) {
1247 .def_seg = R_DS,
1248 .base = -1,
1249 .index = -1,
1250 .disp = insn_get_addr(env, s, s->aflag)
1251 };
1252 break;
1253
1254 case X86_TYPE_H: /* For AVX, VEX.vvvv selects an XMM/YMM register */
1255 if ((s->prefix & PREFIX_VEX)) {
1256 op->unit = X86_OP_SSE;
1257 op->n = s->vex_v;
1258 break;
1259 }
1260 if (op == &decode->op[0]) {
1261 /* shifts place the destination in VEX.vvvv, use modrm */
1262 return decode_op(s, env, decode, op, decode->e.op1, b);
1263 } else {
1264 return decode_op(s, env, decode, op, decode->e.op0, b);
1265 }
1266
1267 case X86_TYPE_I: /* Immediate */
1268 op->unit = X86_OP_IMM;
1269 decode->immediate = insn_get_signed(env, s, op->ot);
1270 break;
1271
1272 case X86_TYPE_J: /* Relative offset for a jump */
1273 op->unit = X86_OP_IMM;
1274 decode->immediate = insn_get_signed(env, s, op->ot);
1275 decode->immediate += s->pc - s->cs_base;
1276 if (s->dflag == MO_16) {
1277 decode->immediate &= 0xffff;
1278 } else if (!CODE64(s)) {
1279 decode->immediate &= 0xffffffffu;
1280 }
1281 break;
1282
1283 case X86_TYPE_L: /* The upper 4 bits of the immediate select a 128-bit register */
1284 op->n = insn_get(env, s, op->ot) >> 4;
1285 break;
1286
1287 case X86_TYPE_X: /* string source */
1288 op->n = -1;
1289 decode->mem = (AddressParts) {
1290 .def_seg = R_DS,
1291 .base = R_ESI,
1292 .index = -1,
1293 };
1294 break;
1295
1296 case X86_TYPE_Y: /* string destination */
1297 op->n = -1;
1298 decode->mem = (AddressParts) {
1299 .def_seg = R_ES,
1300 .base = R_EDI,
1301 .index = -1,
1302 };
1303 break;
1304
1305 case X86_TYPE_2op:
1306 *op = decode->op[0];
1307 break;
1308
1309 case X86_TYPE_LoBits:
1310 op->n = (b & 7) | REX_B(s);
1311 op->unit = X86_OP_INT;
1312 break;
1313
1314 case X86_TYPE_0 ... X86_TYPE_7:
1315 op->n = type - X86_TYPE_0;
1316 op->unit = X86_OP_INT;
1317 break;
1318
1319 case X86_TYPE_ES ... X86_TYPE_GS:
1320 op->n = type - X86_TYPE_ES;
1321 op->unit = X86_OP_SEG;
1322 break;
1323 }
1324
1325 return true;
1326}
1327
55a33286
PB		 1328static bool validate_sse_prefix(DisasContext *s, X86OpEntry *e)
1329{
1330 uint16_t sse_prefixes;
1331
1332 if (!e->valid_prefix) {
1333 return true;
1334 }
1335 if (s->prefix & (PREFIX_REPZ | PREFIX_REPNZ)) {
1336 /* In SSE instructions, 0xF3 and 0xF2 cancel 0x66. */
1337 s->prefix &= ~PREFIX_DATA;
1338 }
1339
1340 /* Now, either zero or one bit is set in sse_prefixes. */
1341 sse_prefixes = s->prefix & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA);
1342 return e->valid_prefix & (1 << sse_prefixes);
1343}
1344
b3e22b23
PB		 1345static bool decode_insn(DisasContext *s, CPUX86State *env, X86DecodeFunc decode_func,
1346 X86DecodedInsn *decode)
1347{
1348 X86OpEntry *e = &decode->e;
1349
1350 decode_func(s, env, e, &decode->b);
1351 while (e->is_decode) {
1352 e->is_decode = false;
1353 e->decode(s, env, e, &decode->b);
1354 }
1355
55a33286
PB		 1356 if (!validate_sse_prefix(s, e)) {
1357 return false;
1358 }
1359
b3e22b23
PB		 1360 /* First compute size of operands in order to initialize s->rip_offset. */
1361 if (e->op0 != X86_TYPE_None) {
1362 if (!decode_op_size(s, e, e->s0, &decode->op[0].ot)) {
1363 return false;
1364 }
1365 if (e->op0 == X86_TYPE_I) {
1366 s->rip_offset += 1 << decode->op[0].ot;
1367 }
1368 }
1369 if (e->op1 != X86_TYPE_None) {
1370 if (!decode_op_size(s, e, e->s1, &decode->op[1].ot)) {
1371 return false;
1372 }
1373 if (e->op1 == X86_TYPE_I) {
1374 s->rip_offset += 1 << decode->op[1].ot;
1375 }
1376 }
1377 if (e->op2 != X86_TYPE_None) {
1378 if (!decode_op_size(s, e, e->s2, &decode->op[2].ot)) {
1379 return false;
1380 }
1381 if (e->op2 == X86_TYPE_I) {
1382 s->rip_offset += 1 << decode->op[2].ot;
1383 }
1384 }
1385 if (e->op3 != X86_TYPE_None) {
79068477
PB		 1386 /*
1387 * A couple instructions actually use the extra immediate byte for an Lx
1388 * register operand; those are handled in the gen_* functions as one off.
1389 */
b3e22b23
PB		 1390 assert(e->op3 == X86_TYPE_I && e->s3 == X86_SIZE_b);
1391 s->rip_offset += 1;
1392 }
1393
1394 if (e->op0 != X86_TYPE_None &&
1395 !decode_op(s, env, decode, &decode->op[0], e->op0, decode->b)) {
1396 return false;
1397 }
1398
1399 if (e->op1 != X86_TYPE_None &&
1400 !decode_op(s, env, decode, &decode->op[1], e->op1, decode->b)) {
1401 return false;
1402 }
1403
1404 if (e->op2 != X86_TYPE_None &&
1405 !decode_op(s, env, decode, &decode->op[2], e->op2, decode->b)) {
1406 return false;
1407 }
1408
1409 if (e->op3 != X86_TYPE_None) {
1410 decode->immediate = insn_get_signed(env, s, MO_8);
1411 }
1412
1413 return true;
1414}
1415
caa01fad
PB		 1416static bool has_cpuid_feature(DisasContext *s, X86CPUIDFeature cpuid)
1417{
1418 switch (cpuid) {
1419 case X86_FEAT_None:
1420 return true;
cf5ec664
PB		 1421 case X86_FEAT_F16C:
1422 return (s->cpuid_ext_features & CPUID_EXT_F16C);
2872b0f3
PB		 1423 case X86_FEAT_FMA:
1424 return (s->cpuid_ext_features & CPUID_EXT_FMA);
caa01fad
PB		 1425 case X86_FEAT_MOVBE:
1426 return (s->cpuid_ext_features & CPUID_EXT_MOVBE);
1427 case X86_FEAT_PCLMULQDQ:
1428 return (s->cpuid_ext_features & CPUID_EXT_PCLMULQDQ);
1429 case X86_FEAT_SSE:
1430 return (s->cpuid_ext_features & CPUID_SSE);
1431 case X86_FEAT_SSE2:
1432 return (s->cpuid_ext_features & CPUID_SSE2);
1433 case X86_FEAT_SSE3:
1434 return (s->cpuid_ext_features & CPUID_EXT_SSE3);
1435 case X86_FEAT_SSSE3:
1436 return (s->cpuid_ext_features & CPUID_EXT_SSSE3);
1437 case X86_FEAT_SSE41:
1438 return (s->cpuid_ext_features & CPUID_EXT_SSE41);
1439 case X86_FEAT_SSE42:
1440 return (s->cpuid_ext_features & CPUID_EXT_SSE42);
1441 case X86_FEAT_AES:
1442 if (!(s->cpuid_ext_features & CPUID_EXT_AES)) {
1443 return false;
1444 } else if (!(s->prefix & PREFIX_VEX)) {
1445 return true;
1446 } else if (!(s->cpuid_ext_features & CPUID_EXT_AVX)) {
1447 return false;
1448 } else {
1449 return !s->vex_l || (s->cpuid_7_0_ecx_features & CPUID_7_0_ECX_VAES);
1450 }
1451
1452 case X86_FEAT_AVX:
1453 return (s->cpuid_ext_features & CPUID_EXT_AVX);
1454
71a0891d
PB		 1455 case X86_FEAT_3DNOW:
1456 return (s->cpuid_ext2_features & CPUID_EXT2_3DNOW);
caa01fad
PB		 1457 case X86_FEAT_SSE4A:
1458 return (s->cpuid_ext3_features & CPUID_EXT3_SSE4A);
1459
1460 case X86_FEAT_ADX:
1461 return (s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_ADX);
1462 case X86_FEAT_BMI1:
1463 return (s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_BMI1);
1464 case X86_FEAT_BMI2:
1465 return (s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_BMI2);
1466 case X86_FEAT_AVX2:
1467 return (s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_AVX2);
e582b629
PB		 1468 case X86_FEAT_SHA_NI:
1469 return (s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_SHA_NI);
caa01fad
PB		 1470 }
1471 g_assert_not_reached();
1472}
1473
20581aad
PB		 1474static bool validate_vex(DisasContext *s, X86DecodedInsn *decode)
1475{
1476 X86OpEntry *e = &decode->e;
1477
1478 switch (e->vex_special) {
1479 case X86_VEX_REPScalar:
1480 /*
1481 * Instructions which differ between 00/66 and F2/F3 in the
1482 * exception classification and the size of the memory operand.
1483 */
3d304620 1484 assert(e->vex_class == 1 || e->vex_class == 2 || e->vex_class == 4);
20581aad 1485 if (s->prefix & (PREFIX_REPZ | PREFIX_REPNZ)) {
3d304620 1486 e->vex_class = e->vex_class < 4 ? 3 : 5;
20581aad
PB		 1487 if (s->vex_l) {
1488 goto illegal;
1489 }
1490 assert(decode->e.s2 == X86_SIZE_x);
1491 if (decode->op[2].has_ea) {
1492 decode->op[2].ot = s->prefix & PREFIX_REPZ ? MO_32 : MO_64;
1493 }
1494 }
1495 break;
1496
1497 case X86_VEX_SSEUnaligned:
1498 /* handled in sse_needs_alignment. */
1499 break;
1500
1501 case X86_VEX_AVX2_256:
1502 if ((s->prefix & PREFIX_VEX) && s->vex_l && !has_cpuid_feature(s, X86_FEAT_AVX2)) {
1503 goto illegal;
1504 }
1505 }
1506
1507 /* TODO: instructions that require VEX.W=0 (Table 2-16) */
1508
1509 switch (e->vex_class) {
1510 case 0:
1511 if (s->prefix & PREFIX_VEX) {
1512 goto illegal;
1513 }
1514 return true;
1515 case 1:
1516 case 2:
1517 case 3:
1518 case 4:
1519 case 5:
1520 case 7:
1521 if (s->prefix & PREFIX_VEX) {
1522 if (!(s->flags & HF_AVX_EN_MASK)) {
1523 goto illegal;
1524 }
38e65936
PB		 1525 } else if (e->special != X86_SPECIAL_MMX ||
1526 (s->prefix & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))) {
20581aad
PB		 1527 if (!(s->flags & HF_OSFXSR_MASK)) {
1528 goto illegal;
1529 }
1530 }
1531 break;
1532 case 12:
1533 /* Must have a VSIB byte and no address prefix. */
1534 assert(s->has_modrm);
1535 if ((s->modrm & 7) != 4 || s->aflag == MO_16) {
1536 goto illegal;
1537 }
1538
1539 /* Check no overlap between registers. */
1540 if (!decode->op[0].has_ea &&
1541 (decode->op[0].n == decode->mem.index || decode->op[0].n == decode->op[1].n)) {
1542 goto illegal;
1543 }
1544 assert(!decode->op[1].has_ea);
1545 if (decode->op[1].n == decode->mem.index) {
1546 goto illegal;
1547 }
1548 if (!decode->op[2].has_ea &&
1549 (decode->op[2].n == decode->mem.index || decode->op[2].n == decode->op[1].n)) {
1550 goto illegal;
1551 }
1552 /* fall through */
1553 case 6:
1554 case 11:
1555 if (!(s->prefix & PREFIX_VEX)) {
1556 goto illegal;
1557 }
1558 if (!(s->flags & HF_AVX_EN_MASK)) {
1559 goto illegal;
1560 }
1561 break;
1562 case 8:
ce4fcb94
PB		 1563 /* Non-VEX case handled in decode_0F77. */
1564 assert(s->prefix & PREFIX_VEX);
20581aad
PB		 1565 if (!(s->flags & HF_AVX_EN_MASK)) {
1566 goto illegal;
1567 }
1568 break;
1569 case 13:
1570 if (!(s->prefix & PREFIX_VEX)) {
1571 goto illegal;
1572 }
1573 if (s->vex_l) {
1574 goto illegal;
1575 }
1576 /* All integer instructions use VEX.vvvv, so exit. */
1577 return true;
1578 }
1579
1580 if (s->vex_v != 0 &&
1581 e->op0 != X86_TYPE_H && e->op0 != X86_TYPE_B &&
1582 e->op1 != X86_TYPE_H && e->op1 != X86_TYPE_B &&
1583 e->op2 != X86_TYPE_H && e->op2 != X86_TYPE_B) {
1584 goto illegal;
1585 }
1586
1587 if (s->flags & HF_TS_MASK) {
1588 goto nm_exception;
1589 }
1590 if (s->flags & HF_EM_MASK) {
1591 goto illegal;
1592 }
1593 return true;
1594
1595nm_exception:
1596 gen_NM_exception(s);
1597 return false;
1598illegal:
1599 gen_illegal_opcode(s);
1600 return false;
1601}
1602
b3e22b23
PB		 1603/*
1604 * Convert one instruction. s->base.is_jmp is set if the translation must
1605 * be stopped.
1606 */
1607static void disas_insn_new(DisasContext *s, CPUState *cpu, int b)
1608{
b77af26e 1609 CPUX86State *env = cpu_env(cpu);
b3e22b23
PB		 1610 bool first = true;
1611 X86DecodedInsn decode;
1612 X86DecodeFunc decode_func = decode_root;
1613
b3e22b23
PB		 1614 s->has_modrm = false;
1615
1616 next_byte:
1617 if (first) {
1618 first = false;
1619 } else {
1620 b = x86_ldub_code(env, s);
1621 }
1622 /* Collect prefixes. */
1623 switch (b) {
1624 case 0xf3:
1625 s->prefix |= PREFIX_REPZ;
1626 s->prefix &= ~PREFIX_REPNZ;
1627 goto next_byte;
1628 case 0xf2:
1629 s->prefix |= PREFIX_REPNZ;
1630 s->prefix &= ~PREFIX_REPZ;
1631 goto next_byte;
1632 case 0xf0:
1633 s->prefix |= PREFIX_LOCK;
1634 goto next_byte;
1635 case 0x2e:
1636 s->override = R_CS;
1637 goto next_byte;
1638 case 0x36:
1639 s->override = R_SS;
1640 goto next_byte;
1641 case 0x3e:
1642 s->override = R_DS;
1643 goto next_byte;
1644 case 0x26:
1645 s->override = R_ES;
1646 goto next_byte;
1647 case 0x64:
1648 s->override = R_FS;
1649 goto next_byte;
1650 case 0x65:
1651 s->override = R_GS;
1652 goto next_byte;
1653 case 0x66:
1654 s->prefix |= PREFIX_DATA;
1655 goto next_byte;
1656 case 0x67:
1657 s->prefix |= PREFIX_ADR;
1658 goto next_byte;
1659#ifdef TARGET_X86_64
1660 case 0x40 ... 0x4f:
1661 if (CODE64(s)) {
1662 /* REX prefix */
1663 s->prefix |= PREFIX_REX;
1664 s->vex_w = (b >> 3) & 1;
1665 s->rex_r = (b & 0x4) << 1;
1666 s->rex_x = (b & 0x2) << 2;
1667 s->rex_b = (b & 0x1) << 3;
1668 goto next_byte;
1669 }
1670 break;
1671#endif
1672 case 0xc5: /* 2-byte VEX */
1673 case 0xc4: /* 3-byte VEX */
1674 /*
1675 * VEX prefixes cannot be used except in 32-bit mode.
1676 * Otherwise the instruction is LES or LDS.
1677 */
1678 if (CODE32(s) && !VM86(s)) {
1679 static const int pp_prefix[4] = {
1680 0, PREFIX_DATA, PREFIX_REPZ, PREFIX_REPNZ
1681 };
1682 int vex3, vex2 = x86_ldub_code(env, s);
1683
1684 if (!CODE64(s) && (vex2 & 0xc0) != 0xc0) {
1685 /*
1686 * 4.1.4.6: In 32-bit mode, bits [7:6] must be 11b,
1687 * otherwise the instruction is LES or LDS.
1688 */
1689 s->pc--; /* rewind the advance_pc() x86_ldub_code() did */
1690 break;
1691 }
1692
1693 /* 4.1.1-4.1.3: No preceding lock, 66, f2, f3, or rex prefixes. */
1694 if (s->prefix & (PREFIX_REPZ | PREFIX_REPNZ
1695 | PREFIX_LOCK | PREFIX_DATA | PREFIX_REX)) {
1696 goto illegal_op;
1697 }
1698#ifdef TARGET_X86_64
1699 s->rex_r = (~vex2 >> 4) & 8;
1700#endif
1701 if (b == 0xc5) {
1702 /* 2-byte VEX prefix: RVVVVlpp, implied 0f leading opcode byte */
1703 vex3 = vex2;
1704 decode_func = decode_0F;
1705 } else {
1706 /* 3-byte VEX prefix: RXBmmmmm wVVVVlpp */
1707 vex3 = x86_ldub_code(env, s);
1708#ifdef TARGET_X86_64
1709 s->rex_x = (~vex2 >> 3) & 8;
1710 s->rex_b = (~vex2 >> 2) & 8;
1711#endif
1712 s->vex_w = (vex3 >> 7) & 1;
1713 switch (vex2 & 0x1f) {
1714 case 0x01: /* Implied 0f leading opcode bytes. */
1715 decode_func = decode_0F;
1716 break;
1717 case 0x02: /* Implied 0f 38 leading opcode bytes. */
1718 decode_func = decode_0F38;
1719 break;
1720 case 0x03: /* Implied 0f 3a leading opcode bytes. */
1721 decode_func = decode_0F3A;
1722 break;
1723 default: /* Reserved for future use. */
1724 goto unknown_op;
1725 }
1726 }
1727 s->vex_v = (~vex3 >> 3) & 0xf;
1728 s->vex_l = (vex3 >> 2) & 1;
1729 s->prefix |= pp_prefix[vex3 & 3] | PREFIX_VEX;
1730 }
1731 break;
1732 default:
1733 if (b >= 0x100) {
1734 b -= 0x100;
1735 decode_func = do_decode_0F;
1736 }
1737 break;
1738 }
1739
1740 /* Post-process prefixes. */
1741 if (CODE64(s)) {
1742 /*
1743 * In 64-bit mode, the default data size is 32-bit. Select 64-bit
1744 * data with rex_w, and 16-bit data with 0x66; rex_w takes precedence
1745 * over 0x66 if both are present.
1746 */
1747 s->dflag = (REX_W(s) ? MO_64 : s->prefix & PREFIX_DATA ? MO_16 : MO_32);
1748 /* In 64-bit mode, 0x67 selects 32-bit addressing. */
1749 s->aflag = (s->prefix & PREFIX_ADR ? MO_32 : MO_64);
1750 } else {
1751 /* In 16/32-bit mode, 0x66 selects the opposite data size. */
1752 if (CODE32(s) ^ ((s->prefix & PREFIX_DATA) != 0)) {
1753 s->dflag = MO_32;
1754 } else {
1755 s->dflag = MO_16;
1756 }
1757 /* In 16/32-bit mode, 0x67 selects the opposite addressing. */
1758 if (CODE32(s) ^ ((s->prefix & PREFIX_ADR) != 0)) {
1759 s->aflag = MO_32;
1760 } else {
1761 s->aflag = MO_16;
1762 }
1763 }
1764
1765 memset(&decode, 0, sizeof(decode));
1766 decode.b = b;
1767 if (!decode_insn(s, env, decode_func, &decode)) {
1768 goto illegal_op;
1769 }
1770 if (!decode.e.gen) {
1771 goto unknown_op;
1772 }
1773
caa01fad
PB		 1774 if (!has_cpuid_feature(s, decode.e.cpuid)) {
1775 goto illegal_op;
1776 }
1777
b3e22b23
PB		 1778 switch (decode.e.special) {
1779 case X86_SPECIAL_None:
1780 break;
1781
1782 case X86_SPECIAL_Locked:
1783 if (decode.op[0].has_ea) {
1784 s->prefix |= PREFIX_LOCK;
1785 }
1786 break;
1787
1788 case X86_SPECIAL_ProtMode:
1789 if (!PE(s) || VM86(s)) {
1790 goto illegal_op;
1791 }
1792 break;
1793
1794 case X86_SPECIAL_i64:
1795 if (CODE64(s)) {
1796 goto illegal_op;
1797 }
1798 break;
1799 case X86_SPECIAL_o64:
1800 if (!CODE64(s)) {
1801 goto illegal_op;
1802 }
1803 break;
1804
1805 case X86_SPECIAL_ZExtOp0:
1806 assert(decode.op[0].unit == X86_OP_INT);
1807 if (!decode.op[0].has_ea) {
1808 decode.op[0].ot = MO_32;
1809 }
1810 break;
1811
1812 case X86_SPECIAL_ZExtOp2:
1813 assert(decode.op[2].unit == X86_OP_INT);
1814 if (!decode.op[2].has_ea) {
1815 decode.op[2].ot = MO_32;
1816 }
1817 break;
1818
16fc5726
PB		 1819 case X86_SPECIAL_AVXExtMov:
1820 if (!decode.op[2].has_ea) {
1821 decode.op[2].ot = s->vex_l ? MO_256 : MO_128;
1822 } else if (s->vex_l) {
1823 decode.op[2].ot++;
1824 }
1825 break;
1826
b2ea6450 1827 default:
b3e22b23
PB		 1828 break;
1829 }
1830
20581aad
PB		 1831 if (!validate_vex(s, &decode)) {
1832 return;
1833 }
b2ea6450
MB		 1834 if (decode.e.special == X86_SPECIAL_MMX &&
1835 !(s->prefix & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))) {
ad75a51e 1836 gen_helper_enter_mmx(tcg_env);
b2ea6450
MB		 1837 }
1838
b3e22b23 1839 if (decode.op[0].has_ea || decode.op[1].has_ea || decode.op[2].has_ea) {
20581aad 1840 gen_load_ea(s, &decode.mem, decode.e.vex_class == 12);
b3e22b23 1841 }
6ba13999
PB		 1842 if (s->prefix & PREFIX_LOCK) {
1843 if (decode.op[0].unit != X86_OP_INT || !decode.op[0].has_ea) {
1844 goto illegal_op;
1845 }
1846 gen_load(s, &decode, 2, s->T1);
1847 decode.e.gen(s, env, &decode);
1848 } else {
1849 if (decode.op[0].unit == X86_OP_MMX) {
1850 compute_mmx_offset(&decode.op[0]);
1851 } else if (decode.op[0].unit == X86_OP_SSE) {
1852 compute_xmm_offset(&decode.op[0]);
1853 }
1854 gen_load(s, &decode, 1, s->T0);
1855 gen_load(s, &decode, 2, s->T1);
1856 decode.e.gen(s, env, &decode);
1857 gen_writeback(s, &decode, 0, s->T0);
1858 }
b3e22b23
PB		 1859 return;
1860 illegal_op:
1861 gen_illegal_opcode(s);
1862 return;
1863 unknown_op:
1864 gen_unknown_opcode(env, s);
1865}
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