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target/i386: document more deviations from the manual
[mirror_qemu.git] / target / i386 / tcg / decode-new.c.inc
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b3e22b23
PB		 1/*
2 * New-style decoder for i386 instructions
3 *
4 * Copyright (c) 2022 Red Hat, Inc.
5 *
6 * Author: Paolo Bonzini <pbonzini@redhat.com>
7 *
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2.1 of the License, or (at your option) any later version.
12 *
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
17 *
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 */
21
22/*
23 * The decoder is mostly based on tables copied from the Intel SDM. As
24 * a result, most operand load and writeback is done entirely in common
25 * table-driven code using the same operand type (X86_TYPE_*) and
e000687f
PB		 26 * size (X86_SIZE_*) codes used in the manual. There are a few differences
27 * though.
28 *
8147df44
PB		 29 * Operand sizes
30 * -------------
31 *
32 * The manual lists d64 ("cannot encode 32-bit size in 64-bit mode") and f64
33 * ("cannot encode 16-bit or 32-bit size in 64-bit mode") as modifiers of the
34 * "v" or "z" sizes. The decoder simply makes them separate operand sizes.
35 *
e000687f
PB		 36 * Vector operands
37 * ---------------
b3e22b23
PB		 38 *
39 * The main difference is that the V, U and W types are extended to
40 * cover MMX as well; if an instruction is like
41 *
42 * por Pq, Qq
43 * 66 por Vx, Hx, Wx
44 *
45 * only the second row is included and the instruction is marked as a
46 * valid MMX instruction. The MMX flag directs the decoder to rewrite
47 * the V/U/H/W types to P/N/P/Q if there is no prefix, as well as changing
48 * "x" to "q" if there is no prefix.
49 *
50 * In addition, the ss/ps/sd/pd types are sometimes mushed together as "x"
51 * if the difference is expressed via prefixes. Individual instructions
52 * are separated by prefix in the generator functions.
53 *
8147df44
PB		 54 * There is a custom size "xh" used to address half of a SSE/AVX operand.
55 * This points to a 64-bit operand for SSE operations, 128-bit operand
56 * for 256-bit AVX operands, etc. It is used for conversion operations
57 * such as VCVTPH2PS or VCVTSS2SD.
58 *
b3e22b23
PB		 59 * There are a couple cases in which instructions (e.g. MOVD) write the
60 * whole XMM or MM register but are established incorrectly in the manual
61 * as "d" or "q". These have to be fixed for the decoder to work correctly.
e000687f
PB		 62 *
63 * VEX exception classes
64 * ---------------------
65 *
66 * Speaking about imprecisions in the manual, the decoder treats all
67 * exception-class 4 instructions as having an optional VEX prefix, and
68 * all exception-class 6 instructions as having a mandatory VEX prefix.
69 * This is true except for a dozen instructions; these are in exception
70 * class 4 but do not ignore the VEX.W bit (which does not even exist
71 * without a VEX prefix). These instructions are mostly listed in Intel's
72 * table 2-16, but with a few exceptions.
73 *
74 * The AMD manual has more precise subclasses for exceptions, and unlike Intel
75 * they list the VEX.W requirements in the exception classes as well (except
76 * when they don't). AMD describes class 6 as "AVX Mixed Memory Argument"
77 * without defining what a mixed memory argument is, but still use 4 as the
78 * primary exception class... except when they don't.
79 *
80 * The summary is:
81 * Intel AMD VEX.W note
82 * -------------------------------------------------------------------
83 * vpblendd 4 4J 0
84 * vpblendvb 4 4E-X 0 (*)
85 * vpbroadcastq 6 6D 0 (+)
86 * vpermd/vpermps 4 4H 0 (§)
87 * vpermq/vpermpd 4 4H-1 1 (§)
88 * vpermilpd/vpermilps 4 6E 0 (^)
89 * vpmaskmovd 6 4K significant (^)
90 * vpsllv 4 4K significant
91 * vpsrav 4 4J 0
92 * vpsrlv 4 4K significant
93 * vtestps/vtestpd 4 4G 0
94 *
95 * (*) AMD lists VPBLENDVB as related to SSE4.1 PBLENDVB, which may
96 * explain why it is considered exception class 4. However,
97 * Intel says that VEX-only instructions should be in class 6...
98 *
99 * (+) Not found in Intel's table 2-16
100 *
101 * (§) 4H and 4H-1 do not mention VEX.W requirements, which are
102 * however present in the description of the instruction
103 *
104 * (^) these are the two cases in which Intel and AMD disagree on the
105 * primary exception class
b3e22b23
PB		 106 */
107
108#define X86_OP_NONE { 0 },
109
110#define X86_OP_GROUP3(op, op0_, s0_, op1_, s1_, op2_, s2_, ...) { \
111 .decode = glue(decode_, op), \
112 .op0 = glue(X86_TYPE_, op0_), \
113 .s0 = glue(X86_SIZE_, s0_), \
114 .op1 = glue(X86_TYPE_, op1_), \
115 .s1 = glue(X86_SIZE_, s1_), \
116 .op2 = glue(X86_TYPE_, op2_), \
117 .s2 = glue(X86_SIZE_, s2_), \
118 .is_decode = true, \
119 ## __VA_ARGS__ \
120}
121
122#define X86_OP_GROUP2(op, op0, s0, op1, s1, ...) \
123 X86_OP_GROUP3(op, op0, s0, 2op, s0, op1, s1, ## __VA_ARGS__)
124#define X86_OP_GROUP0(op, ...) \
125 X86_OP_GROUP3(op, None, None, None, None, None, None, ## __VA_ARGS__)
126
127#define X86_OP_ENTRY3(op, op0_, s0_, op1_, s1_, op2_, s2_, ...) { \
128 .gen = glue(gen_, op), \
129 .op0 = glue(X86_TYPE_, op0_), \
130 .s0 = glue(X86_SIZE_, s0_), \
131 .op1 = glue(X86_TYPE_, op1_), \
132 .s1 = glue(X86_SIZE_, s1_), \
133 .op2 = glue(X86_TYPE_, op2_), \
134 .s2 = glue(X86_SIZE_, s2_), \
135 ## __VA_ARGS__ \
136}
137
138#define X86_OP_ENTRY4(op, op0_, s0_, op1_, s1_, op2_, s2_, ...) \
139 X86_OP_ENTRY3(op, op0_, s0_, op1_, s1_, op2_, s2_, \
140 .op3 = X86_TYPE_I, .s3 = X86_SIZE_b, \
141 ## __VA_ARGS__)
142
143#define X86_OP_ENTRY2(op, op0, s0, op1, s1, ...) \
144 X86_OP_ENTRY3(op, op0, s0, 2op, s0, op1, s1, ## __VA_ARGS__)
57f6bba0
PB		 145#define X86_OP_ENTRYw(op, op0, s0, ...) \
146 X86_OP_ENTRY3(op, op0, s0, None, None, None, None, ## __VA_ARGS__)
147#define X86_OP_ENTRYr(op, op0, s0, ...) \
148 X86_OP_ENTRY3(op, None, None, None, None, op0, s0, ## __VA_ARGS__)
b3e22b23
PB		 149#define X86_OP_ENTRY0(op, ...) \
150 X86_OP_ENTRY3(op, None, None, None, None, None, None, ## __VA_ARGS__)
151
caa01fad 152#define cpuid(feat) .cpuid = X86_FEAT_##feat,
b3e22b23
PB		 153#define xchg .special = X86_SPECIAL_Locked,
154#define mmx .special = X86_SPECIAL_MMX,
155#define zext0 .special = X86_SPECIAL_ZExtOp0,
156#define zext2 .special = X86_SPECIAL_ZExtOp2,
16fc5726 157#define avx_movx .special = X86_SPECIAL_AVXExtMov,
b3e22b23 158
20581aad
PB		 159#define vex1 .vex_class = 1,
160#define vex1_rep3 .vex_class = 1, .vex_special = X86_VEX_REPScalar,
161#define vex2 .vex_class = 2,
162#define vex2_rep3 .vex_class = 2, .vex_special = X86_VEX_REPScalar,
163#define vex3 .vex_class = 3,
164#define vex4 .vex_class = 4,
165#define vex4_unal .vex_class = 4, .vex_special = X86_VEX_SSEUnaligned,
3d304620 166#define vex4_rep5 .vex_class = 4, .vex_special = X86_VEX_REPScalar,
20581aad
PB		 167#define vex5 .vex_class = 5,
168#define vex6 .vex_class = 6,
169#define vex7 .vex_class = 7,
170#define vex8 .vex_class = 8,
171#define vex11 .vex_class = 11,
172#define vex12 .vex_class = 12,
173#define vex13 .vex_class = 13,
174
183e6679
PB		 175#define chk(a) .check = X86_CHECK_##a,
176#define svm(a) .intercept = SVM_EXIT_##a,
177
20581aad
PB		 178#define avx2_256 .vex_special = X86_VEX_AVX2_256,
179
55a33286
PB		 180#define P_00 1
181#define P_66 (1 << PREFIX_DATA)
182#define P_F3 (1 << PREFIX_REPZ)
183#define P_F2 (1 << PREFIX_REPNZ)
184
185#define p_00 .valid_prefix = P_00,
186#define p_66 .valid_prefix = P_66,
187#define p_f3 .valid_prefix = P_F3,
188#define p_f2 .valid_prefix = P_F2,
189#define p_00_66 .valid_prefix = P_00 | P_66,
190#define p_00_f3 .valid_prefix = P_00 | P_F3,
191#define p_66_f2 .valid_prefix = P_66 | P_F2,
192#define p_00_66_f3 .valid_prefix = P_00 | P_66 | P_F3,
193#define p_66_f3_f2 .valid_prefix = P_66 | P_F3 | P_F2,
194#define p_00_66_f3_f2 .valid_prefix = P_00 | P_66 | P_F3 | P_F2,
195
b3e22b23
PB		 196static uint8_t get_modrm(DisasContext *s, CPUX86State *env)
197{
198 if (!s->has_modrm) {
199 s->modrm = x86_ldub_code(env, s);
200 s->has_modrm = true;
201 }
202 return s->modrm;
203}
204
92ec056a
PB		 205static inline const X86OpEntry *decode_by_prefix(DisasContext *s, const X86OpEntry entries[4])
206{
207 if (s->prefix & PREFIX_REPNZ) {
208 return &entries[3];
209 } else if (s->prefix & PREFIX_REPZ) {
210 return &entries[2];
211 } else if (s->prefix & PREFIX_DATA) {
212 return &entries[1];
213 } else {
214 return &entries[0];
215 }
216}
217
57f6bba0
PB		 218static void decode_group15(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
219{
220 /* only includes ldmxcsr and stmxcsr, because they have AVX variants. */
221 static const X86OpEntry group15_reg[8] = {
222 };
223
224 static const X86OpEntry group15_mem[8] = {
183e6679
PB		 225 [2] = X86_OP_ENTRYr(LDMXCSR, E,d, vex5 chk(VEX128)),
226 [3] = X86_OP_ENTRYw(STMXCSR, E,d, vex5 chk(VEX128)),
57f6bba0
PB		 227 };
228
229 uint8_t modrm = get_modrm(s, env);
230 if ((modrm >> 6) == 3) {
231 *entry = group15_reg[(modrm >> 3) & 7];
232 } else {
233 *entry = group15_mem[(modrm >> 3) & 7];
234 }
235}
236
1d0b9261
PB		 237static void decode_group17(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
238{
239 static const X86GenFunc group17_gen[8] = {
240 NULL, gen_BLSR, gen_BLSMSK, gen_BLSI,
241 };
242 int op = (get_modrm(s, env) >> 3) & 7;
243 entry->gen = group17_gen[op];
244}
245
ce4fcb94
PB		 246static void decode_group12(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
247{
248 static const X86OpEntry opcodes_group12[8] = {
249 {},
250 {},
251 X86_OP_ENTRY3(PSRLW_i, H,x, U,x, I,b, vex7 mmx avx2_256 p_00_66),
252 {},
253 X86_OP_ENTRY3(PSRAW_i, H,x, U,x, I,b, vex7 mmx avx2_256 p_00_66),
254 {},
255 X86_OP_ENTRY3(PSLLW_i, H,x, U,x, I,b, vex7 mmx avx2_256 p_00_66),
256 {},
257 };
258
259 int op = (get_modrm(s, env) >> 3) & 7;
260 *entry = opcodes_group12[op];
261}
262
263static void decode_group13(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
264{
265 static const X86OpEntry opcodes_group13[8] = {
266 {},
267 {},
268 X86_OP_ENTRY3(PSRLD_i, H,x, U,x, I,b, vex7 mmx avx2_256 p_00_66),
269 {},
270 X86_OP_ENTRY3(PSRAD_i, H,x, U,x, I,b, vex7 mmx avx2_256 p_00_66),
271 {},
272 X86_OP_ENTRY3(PSLLD_i, H,x, U,x, I,b, vex7 mmx avx2_256 p_00_66),
273 {},
274 };
275
276 int op = (get_modrm(s, env) >> 3) & 7;
277 *entry = opcodes_group13[op];
278}
279
280static void decode_group14(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
281{
282 static const X86OpEntry opcodes_group14[8] = {
283 /* grp14 */
284 {},
285 {},
286 X86_OP_ENTRY3(PSRLQ_i, H,x, U,x, I,b, vex7 mmx avx2_256 p_00_66),
287 X86_OP_ENTRY3(PSRLDQ_i, H,x, U,x, I,b, vex7 avx2_256 p_66),
288 {},
289 {},
290 X86_OP_ENTRY3(PSLLQ_i, H,x, U,x, I,b, vex7 mmx avx2_256 p_00_66),
291 X86_OP_ENTRY3(PSLLDQ_i, H,x, U,x, I,b, vex7 avx2_256 p_66),
292 };
293
294 int op = (get_modrm(s, env) >> 3) & 7;
295 *entry = opcodes_group14[op];
296}
297
92ec056a
PB		 298static void decode_0F6F(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
299{
300 static const X86OpEntry opcodes_0F6F[4] = {
cab529b0 301 X86_OP_ENTRY3(MOVDQ, P,q, None,None, Q,q, vex5 mmx), /* movq */
92ec056a
PB		 302 X86_OP_ENTRY3(MOVDQ, V,x, None,None, W,x, vex1), /* movdqa */
303 X86_OP_ENTRY3(MOVDQ, V,x, None,None, W,x, vex4_unal), /* movdqu */
304 {},
305 };
306 *entry = *decode_by_prefix(s, opcodes_0F6F);
307}
308
ce4fcb94
PB		 309static void decode_0F70(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
310{
311 static const X86OpEntry pshufw[4] = {
312 X86_OP_ENTRY3(PSHUFW, P,q, Q,q, I,b, vex4 mmx),
313 X86_OP_ENTRY3(PSHUFD, V,x, W,x, I,b, vex4 avx2_256),
314 X86_OP_ENTRY3(PSHUFHW, V,x, W,x, I,b, vex4 avx2_256),
315 X86_OP_ENTRY3(PSHUFLW, V,x, W,x, I,b, vex4 avx2_256),
316 };
317
318 *entry = *decode_by_prefix(s, pshufw);
319}
320
321static void decode_0F77(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
322{
323 if (!(s->prefix & PREFIX_VEX)) {
324 entry->gen = gen_EMMS;
325 } else if (!s->vex_l) {
326 entry->gen = gen_VZEROUPPER;
327 entry->vex_class = 8;
328 } else {
329 entry->gen = gen_VZEROALL;
330 entry->vex_class = 8;
331 }
332}
333
d1c1a422
PB		 334static void decode_0F78(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
335{
336 static const X86OpEntry opcodes_0F78[4] = {
337 {},
afa94dab 338 X86_OP_ENTRY3(EXTRQ_i, V,x, None,None, I,w, cpuid(SSE4A)), /* AMD extension */
d1c1a422 339 {},
afa94dab 340 X86_OP_ENTRY3(INSERTQ_i, V,x, U,x, I,w, cpuid(SSE4A)), /* AMD extension */
d1c1a422
PB		 341 };
342 *entry = *decode_by_prefix(s, opcodes_0F78);
343}
344
345static void decode_0F79(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
346{
347 if (s->prefix & PREFIX_REPNZ) {
afa94dab 348 entry->gen = gen_INSERTQ_r; /* AMD extension */
d1c1a422 349 } else if (s->prefix & PREFIX_DATA) {
afa94dab 350 entry->gen = gen_EXTRQ_r; /* AMD extension */
d1c1a422
PB		 351 } else {
352 entry->gen = NULL;
353 };
354}
355
356static void decode_0F7E(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
357{
358 static const X86OpEntry opcodes_0F7E[4] = {
359 X86_OP_ENTRY3(MOVD_from, E,y, None,None, P,y, vex5 mmx),
360 X86_OP_ENTRY3(MOVD_from, E,y, None,None, V,y, vex5),
361 X86_OP_ENTRY3(MOVQ, V,x, None,None, W,q, vex5), /* wrong dest Vy on SDM! */
362 {},
363 };
364 *entry = *decode_by_prefix(s, opcodes_0F7E);
365}
366
367static void decode_0F7F(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
368{
369 static const X86OpEntry opcodes_0F7F[4] = {
cab529b0 370 X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex5 mmx), /* movq */
d1c1a422
PB		 371 X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex1), /* movdqa */
372 X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex4_unal), /* movdqu */
373 {},
374 };
375 *entry = *decode_by_prefix(s, opcodes_0F7F);
376}
377
6bbeb98d
PB		 378static void decode_0FD6(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
379{
380 static const X86OpEntry movq[4] = {
381 {},
382 X86_OP_ENTRY3(MOVQ, W,x, None, None, V,q, vex5),
383 X86_OP_ENTRY3(MOVq_dq, V,dq, None, None, N,q),
384 X86_OP_ENTRY3(MOVq_dq, P,q, None, None, U,q),
385 };
386
387 *entry = *decode_by_prefix(s, movq);
388}
389
b3e22b23 390static const X86OpEntry opcodes_0F38_00toEF[240] = {
16fc5726
PB		 391 [0x00] = X86_OP_ENTRY3(PSHUFB, V,x, H,x, W,x, vex4 cpuid(SSSE3) mmx avx2_256 p_00_66),
392 [0x01] = X86_OP_ENTRY3(PHADDW, V,x, H,x, W,x, vex4 cpuid(SSSE3) mmx avx2_256 p_00_66),
393 [0x02] = X86_OP_ENTRY3(PHADDD, V,x, H,x, W,x, vex4 cpuid(SSSE3) mmx avx2_256 p_00_66),
394 [0x03] = X86_OP_ENTRY3(PHADDSW, V,x, H,x, W,x, vex4 cpuid(SSSE3) mmx avx2_256 p_00_66),
395 [0x04] = X86_OP_ENTRY3(PMADDUBSW, V,x, H,x, W,x, vex4 cpuid(SSSE3) mmx avx2_256 p_00_66),
396 [0x05] = X86_OP_ENTRY3(PHSUBW, V,x, H,x, W,x, vex4 cpuid(SSSE3) mmx avx2_256 p_00_66),
397 [0x06] = X86_OP_ENTRY3(PHSUBD, V,x, H,x, W,x, vex4 cpuid(SSSE3) mmx avx2_256 p_00_66),
398 [0x07] = X86_OP_ENTRY3(PHSUBSW, V,x, H,x, W,x, vex4 cpuid(SSSE3) mmx avx2_256 p_00_66),
399
400 [0x10] = X86_OP_ENTRY2(PBLENDVB, V,x, W,x, vex4 cpuid(SSE41) avx2_256 p_66),
e000687f 401 [0x13] = X86_OP_ENTRY2(VCVTPH2PS, V,x, W,xh, vex11 chk(W0) cpuid(F16C) p_66),
16fc5726
PB		 402 [0x14] = X86_OP_ENTRY2(BLENDVPS, V,x, W,x, vex4 cpuid(SSE41) p_66),
403 [0x15] = X86_OP_ENTRY2(BLENDVPD, V,x, W,x, vex4 cpuid(SSE41) p_66),
404 /* Listed incorrectly as type 4 */
e000687f 405 [0x16] = X86_OP_ENTRY3(VPERMD, V,qq, H,qq, W,qq, vex6 chk(W0) cpuid(AVX2) p_66), /* vpermps */
16fc5726
PB		 406 [0x17] = X86_OP_ENTRY3(VPTEST, None,None, V,x, W,x, vex4 cpuid(SSE41) p_66),
407
408 /*
409 * Source operand listed as Mq/Ux and similar in the manual; incorrectly listed
410 * as 128-bit only in 2-17.
411 */
412 [0x20] = X86_OP_ENTRY3(VPMOVSXBW, V,x, None,None, W,q, vex5 cpuid(SSE41) avx_movx avx2_256 p_66),
413 [0x21] = X86_OP_ENTRY3(VPMOVSXBD, V,x, None,None, W,d, vex5 cpuid(SSE41) avx_movx avx2_256 p_66),
414 [0x22] = X86_OP_ENTRY3(VPMOVSXBQ, V,x, None,None, W,w, vex5 cpuid(SSE41) avx_movx avx2_256 p_66),
415 [0x23] = X86_OP_ENTRY3(VPMOVSXWD, V,x, None,None, W,q, vex5 cpuid(SSE41) avx_movx avx2_256 p_66),
416 [0x24] = X86_OP_ENTRY3(VPMOVSXWQ, V,x, None,None, W,d, vex5 cpuid(SSE41) avx_movx avx2_256 p_66),
417 [0x25] = X86_OP_ENTRY3(VPMOVSXDQ, V,x, None,None, W,q, vex5 cpuid(SSE41) avx_movx avx2_256 p_66),
418
419 /* Same as PMOVSX. */
420 [0x30] = X86_OP_ENTRY3(VPMOVZXBW, V,x, None,None, W,q, vex5 cpuid(SSE41) avx_movx avx2_256 p_66),
421 [0x31] = X86_OP_ENTRY3(VPMOVZXBD, V,x, None,None, W,d, vex5 cpuid(SSE41) avx_movx avx2_256 p_66),
422 [0x32] = X86_OP_ENTRY3(VPMOVZXBQ, V,x, None,None, W,w, vex5 cpuid(SSE41) avx_movx avx2_256 p_66),
423 [0x33] = X86_OP_ENTRY3(VPMOVZXWD, V,x, None,None, W,q, vex5 cpuid(SSE41) avx_movx avx2_256 p_66),
424 [0x34] = X86_OP_ENTRY3(VPMOVZXWQ, V,x, None,None, W,d, vex5 cpuid(SSE41) avx_movx avx2_256 p_66),
425 [0x35] = X86_OP_ENTRY3(VPMOVZXDQ, V,x, None,None, W,q, vex5 cpuid(SSE41) avx_movx avx2_256 p_66),
e000687f 426 [0x36] = X86_OP_ENTRY3(VPERMD, V,qq, H,qq, W,qq, vex6 chk(W0) cpuid(AVX2) p_66),
16fc5726
PB		 427 [0x37] = X86_OP_ENTRY3(PCMPGTQ, V,x, H,x, W,x, vex4 cpuid(SSE42) avx2_256 p_66),
428
429 [0x40] = X86_OP_ENTRY3(PMULLD, V,x, H,x, W,x, vex4 cpuid(SSE41) avx2_256 p_66),
430 [0x41] = X86_OP_ENTRY3(VPHMINPOSUW, V,dq, None,None, W,dq, vex4 cpuid(SSE41) p_66),
431 /* Listed incorrectly as type 4 */
432 [0x45] = X86_OP_ENTRY3(VPSRLV, V,x, H,x, W,x, vex6 cpuid(AVX2) p_66),
e000687f 433 [0x46] = X86_OP_ENTRY3(VPSRAV, V,x, H,x, W,x, vex6 chk(W0) cpuid(AVX2) p_66),
16fc5726
PB		 434 [0x47] = X86_OP_ENTRY3(VPSLLV, V,x, H,x, W,x, vex6 cpuid(AVX2) p_66),
435
436 [0x90] = X86_OP_ENTRY3(VPGATHERD, V,x, H,x, M,d, vex12 cpuid(AVX2) p_66), /* vpgatherdd/q */
437 [0x91] = X86_OP_ENTRY3(VPGATHERQ, V,x, H,x, M,q, vex12 cpuid(AVX2) p_66), /* vpgatherqd/q */
438 [0x92] = X86_OP_ENTRY3(VPGATHERD, V,x, H,x, M,d, vex12 cpuid(AVX2) p_66), /* vgatherdps/d */
439 [0x93] = X86_OP_ENTRY3(VPGATHERQ, V,x, H,x, M,q, vex12 cpuid(AVX2) p_66), /* vgatherqps/d */
440
2872b0f3
PB		 441 /* Should be exception type 2 but they do not have legacy SSE equivalents? */
442 [0x96] = X86_OP_ENTRY3(VFMADDSUB132Px, V,x, H,x, W,x, vex6 cpuid(FMA) p_66),
443 [0x97] = X86_OP_ENTRY3(VFMSUBADD132Px, V,x, H,x, W,x, vex6 cpuid(FMA) p_66),
444
445 [0xa6] = X86_OP_ENTRY3(VFMADDSUB213Px, V,x, H,x, W,x, vex6 cpuid(FMA) p_66),
446 [0xa7] = X86_OP_ENTRY3(VFMSUBADD213Px, V,x, H,x, W,x, vex6 cpuid(FMA) p_66),
447
448 [0xb6] = X86_OP_ENTRY3(VFMADDSUB231Px, V,x, H,x, W,x, vex6 cpuid(FMA) p_66),
449 [0xb7] = X86_OP_ENTRY3(VFMSUBADD231Px, V,x, H,x, W,x, vex6 cpuid(FMA) p_66),
450
16fc5726
PB		 451 [0x08] = X86_OP_ENTRY3(PSIGNB, V,x, H,x, W,x, vex4 cpuid(SSSE3) mmx avx2_256 p_00_66),
452 [0x09] = X86_OP_ENTRY3(PSIGNW, V,x, H,x, W,x, vex4 cpuid(SSSE3) mmx avx2_256 p_00_66),
453 [0x0a] = X86_OP_ENTRY3(PSIGND, V,x, H,x, W,x, vex4 cpuid(SSSE3) mmx avx2_256 p_00_66),
454 [0x0b] = X86_OP_ENTRY3(PMULHRSW, V,x, H,x, W,x, vex4 cpuid(SSSE3) mmx avx2_256 p_00_66),
e000687f
PB		 455 /* Listed incorrectly as type 4 */
456 [0x0c] = X86_OP_ENTRY3(VPERMILPS, V,x, H,x, W,x, vex6 chk(W0) cpuid(AVX) p_00_66),
457 [0x0d] = X86_OP_ENTRY3(VPERMILPD, V,x, H,x, W,x, vex6 chk(W0) cpuid(AVX) p_66),
458 [0x0e] = X86_OP_ENTRY3(VTESTPS, None,None, V,x, W,x, vex6 chk(W0) cpuid(AVX) p_66),
459 [0x0f] = X86_OP_ENTRY3(VTESTPD, None,None, V,x, W,x, vex6 chk(W0) cpuid(AVX) p_66),
460
461 [0x18] = X86_OP_ENTRY3(VPBROADCASTD, V,x, None,None, W,d, vex6 chk(W0) cpuid(AVX) p_66), /* vbroadcastss */
462 [0x19] = X86_OP_ENTRY3(VPBROADCASTQ, V,qq, None,None, W,q, vex6 chk(W0) cpuid(AVX) p_66), /* vbroadcastsd */
463 [0x1a] = X86_OP_ENTRY3(VBROADCASTx128, V,qq, None,None, WM,dq,vex6 chk(W0) cpuid(AVX) p_66),
16fc5726
PB		 464 [0x1c] = X86_OP_ENTRY3(PABSB, V,x, None,None, W,x, vex4 cpuid(SSSE3) mmx avx2_256 p_00_66),
465 [0x1d] = X86_OP_ENTRY3(PABSW, V,x, None,None, W,x, vex4 cpuid(SSSE3) mmx avx2_256 p_00_66),
466 [0x1e] = X86_OP_ENTRY3(PABSD, V,x, None,None, W,x, vex4 cpuid(SSSE3) mmx avx2_256 p_00_66),
467
468 [0x28] = X86_OP_ENTRY3(PMULDQ, V,x, H,x, W,x, vex4 cpuid(SSE41) avx2_256 p_66),
469 [0x29] = X86_OP_ENTRY3(PCMPEQQ, V,x, H,x, W,x, vex4 cpuid(SSE41) avx2_256 p_66),
470 [0x2a] = X86_OP_ENTRY3(MOVDQ, V,x, None,None, WM,x, vex1 cpuid(SSE41) avx2_256 p_66), /* movntdqa */
471 [0x2b] = X86_OP_ENTRY3(VPACKUSDW, V,x, H,x, W,x, vex4 cpuid(SSE41) avx2_256 p_66),
e000687f
PB		 472 [0x2c] = X86_OP_ENTRY3(VMASKMOVPS, V,x, H,x, WM,x, vex6 chk(W0) cpuid(AVX) p_66),
473 [0x2d] = X86_OP_ENTRY3(VMASKMOVPD, V,x, H,x, WM,x, vex6 chk(W0) cpuid(AVX) p_66),
16fc5726 474 /* Incorrectly listed as Mx,Hx,Vx in the manual */
e000687f
PB		 475 [0x2e] = X86_OP_ENTRY3(VMASKMOVPS_st, M,x, V,x, H,x, vex6 chk(W0) cpuid(AVX) p_66),
476 [0x2f] = X86_OP_ENTRY3(VMASKMOVPD_st, M,x, V,x, H,x, vex6 chk(W0) cpuid(AVX) p_66),
16fc5726
PB		 477
478 [0x38] = X86_OP_ENTRY3(PMINSB, V,x, H,x, W,x, vex4 cpuid(SSE41) avx2_256 p_66),
479 [0x39] = X86_OP_ENTRY3(PMINSD, V,x, H,x, W,x, vex4 cpuid(SSE41) avx2_256 p_66),
480 [0x3a] = X86_OP_ENTRY3(PMINUW, V,x, H,x, W,x, vex4 cpuid(SSE41) avx2_256 p_66),
481 [0x3b] = X86_OP_ENTRY3(PMINUD, V,x, H,x, W,x, vex4 cpuid(SSE41) avx2_256 p_66),
482 [0x3c] = X86_OP_ENTRY3(PMAXSB, V,x, H,x, W,x, vex4 cpuid(SSE41) avx2_256 p_66),
483 [0x3d] = X86_OP_ENTRY3(PMAXSD, V,x, H,x, W,x, vex4 cpuid(SSE41) avx2_256 p_66),
484 [0x3e] = X86_OP_ENTRY3(PMAXUW, V,x, H,x, W,x, vex4 cpuid(SSE41) avx2_256 p_66),
485 [0x3f] = X86_OP_ENTRY3(PMAXUD, V,x, H,x, W,x, vex4 cpuid(SSE41) avx2_256 p_66),
486
e000687f
PB		 487 /* VPBROADCASTQ not listed as W0 in table 2-16 */
488 [0x58] = X86_OP_ENTRY3(VPBROADCASTD, V,x, None,None, W,d, vex6 chk(W0) cpuid(AVX2) p_66),
489 [0x59] = X86_OP_ENTRY3(VPBROADCASTQ, V,x, None,None, W,q, vex6 chk(W0) cpuid(AVX2) p_66),
490 [0x5a] = X86_OP_ENTRY3(VBROADCASTx128, V,qq, None,None, WM,dq,vex6 chk(W0) cpuid(AVX2) p_66),
16fc5726 491
e000687f
PB		 492 [0x78] = X86_OP_ENTRY3(VPBROADCASTB, V,x, None,None, W,b, vex6 chk(W0) cpuid(AVX2) p_66),
493 [0x79] = X86_OP_ENTRY3(VPBROADCASTW, V,x, None,None, W,w, vex6 chk(W0) cpuid(AVX2) p_66),
16fc5726
PB		 494
495 [0x8c] = X86_OP_ENTRY3(VPMASKMOV, V,x, H,x, WM,x, vex6 cpuid(AVX2) p_66),
496 [0x8e] = X86_OP_ENTRY3(VPMASKMOV_st, M,x, V,x, H,x, vex6 cpuid(AVX2) p_66),
497
2872b0f3
PB		 498 /* Should be exception type 2 or 3 but they do not have legacy SSE equivalents? */
499 [0x98] = X86_OP_ENTRY3(VFMADD132Px, V,x, H,x, W,x, vex6 cpuid(FMA) p_66),
500 [0x99] = X86_OP_ENTRY3(VFMADD132Sx, V,x, H,x, W,x, vex6 cpuid(FMA) p_66),
501 [0x9a] = X86_OP_ENTRY3(VFMSUB132Px, V,x, H,x, W,x, vex6 cpuid(FMA) p_66),
502 [0x9b] = X86_OP_ENTRY3(VFMSUB132Sx, V,x, H,x, W,x, vex6 cpuid(FMA) p_66),
503 [0x9c] = X86_OP_ENTRY3(VFNMADD132Px, V,x, H,x, W,x, vex6 cpuid(FMA) p_66),
504 [0x9d] = X86_OP_ENTRY3(VFNMADD132Sx, V,x, H,x, W,x, vex6 cpuid(FMA) p_66),
505 [0x9e] = X86_OP_ENTRY3(VFNMSUB132Px, V,x, H,x, W,x, vex6 cpuid(FMA) p_66),
506 [0x9f] = X86_OP_ENTRY3(VFNMSUB132Sx, V,x, H,x, W,x, vex6 cpuid(FMA) p_66),
507
508 [0xa8] = X86_OP_ENTRY3(VFMADD213Px, V,x, H,x, W,x, vex6 cpuid(FMA) p_66),
509 [0xa9] = X86_OP_ENTRY3(VFMADD213Sx, V,x, H,x, W,x, vex6 cpuid(FMA) p_66),
510 [0xaa] = X86_OP_ENTRY3(VFMSUB213Px, V,x, H,x, W,x, vex6 cpuid(FMA) p_66),
511 [0xab] = X86_OP_ENTRY3(VFMSUB213Sx, V,x, H,x, W,x, vex6 cpuid(FMA) p_66),
512 [0xac] = X86_OP_ENTRY3(VFNMADD213Px, V,x, H,x, W,x, vex6 cpuid(FMA) p_66),
513 [0xad] = X86_OP_ENTRY3(VFNMADD213Sx, V,x, H,x, W,x, vex6 cpuid(FMA) p_66),
514 [0xae] = X86_OP_ENTRY3(VFNMSUB213Px, V,x, H,x, W,x, vex6 cpuid(FMA) p_66),
515 [0xaf] = X86_OP_ENTRY3(VFNMSUB213Sx, V,x, H,x, W,x, vex6 cpuid(FMA) p_66),
516
517 [0xb8] = X86_OP_ENTRY3(VFMADD231Px, V,x, H,x, W,x, vex6 cpuid(FMA) p_66),
518 [0xb9] = X86_OP_ENTRY3(VFMADD231Sx, V,x, H,x, W,x, vex6 cpuid(FMA) p_66),
519 [0xba] = X86_OP_ENTRY3(VFMSUB231Px, V,x, H,x, W,x, vex6 cpuid(FMA) p_66),
520 [0xbb] = X86_OP_ENTRY3(VFMSUB231Sx, V,x, H,x, W,x, vex6 cpuid(FMA) p_66),
521 [0xbc] = X86_OP_ENTRY3(VFNMADD231Px, V,x, H,x, W,x, vex6 cpuid(FMA) p_66),
522 [0xbd] = X86_OP_ENTRY3(VFNMADD231Sx, V,x, H,x, W,x, vex6 cpuid(FMA) p_66),
523 [0xbe] = X86_OP_ENTRY3(VFNMSUB231Px, V,x, H,x, W,x, vex6 cpuid(FMA) p_66),
524 [0xbf] = X86_OP_ENTRY3(VFNMSUB231Sx, V,x, H,x, W,x, vex6 cpuid(FMA) p_66),
525
e582b629
PB		 526 [0xc8] = X86_OP_ENTRY2(SHA1NEXTE, V,dq, W,dq, cpuid(SHA_NI)),
527 [0xc9] = X86_OP_ENTRY2(SHA1MSG1, V,dq, W,dq, cpuid(SHA_NI)),
528 [0xca] = X86_OP_ENTRY2(SHA1MSG2, V,dq, W,dq, cpuid(SHA_NI)),
529 [0xcb] = X86_OP_ENTRY2(SHA256RNDS2, V,dq, W,dq, cpuid(SHA_NI)),
530 [0xcc] = X86_OP_ENTRY2(SHA256MSG1, V,dq, W,dq, cpuid(SHA_NI)),
531 [0xcd] = X86_OP_ENTRY2(SHA256MSG2, V,dq, W,dq, cpuid(SHA_NI)),
532
16fc5726
PB		 533 [0xdb] = X86_OP_ENTRY3(VAESIMC, V,dq, None,None, W,dq, vex4 cpuid(AES) p_66),
534 [0xdc] = X86_OP_ENTRY3(VAESENC, V,x, H,x, W,x, vex4 cpuid(AES) p_66),
535 [0xdd] = X86_OP_ENTRY3(VAESENCLAST, V,x, H,x, W,x, vex4 cpuid(AES) p_66),
536 [0xde] = X86_OP_ENTRY3(VAESDEC, V,x, H,x, W,x, vex4 cpuid(AES) p_66),
537 [0xdf] = X86_OP_ENTRY3(VAESDECLAST, V,x, H,x, W,x, vex4 cpuid(AES) p_66),
b3e22b23
PB		 538};
539
540/* five rows for no prefix, 66, F3, F2, 66+F2 */
541static const X86OpEntry opcodes_0F38_F0toFF[16][5] = {
1d0b9261
PB		 542 [0] = {
543 X86_OP_ENTRY3(MOVBE, G,y, M,y, None,None, cpuid(MOVBE)),
544 X86_OP_ENTRY3(MOVBE, G,w, M,w, None,None, cpuid(MOVBE)),
545 {},
546 X86_OP_ENTRY2(CRC32, G,d, E,b, cpuid(SSE42)),
547 X86_OP_ENTRY2(CRC32, G,d, E,b, cpuid(SSE42)),
548 },
549 [1] = {
550 X86_OP_ENTRY3(MOVBE, M,y, G,y, None,None, cpuid(MOVBE)),
551 X86_OP_ENTRY3(MOVBE, M,w, G,w, None,None, cpuid(MOVBE)),
552 {},
553 X86_OP_ENTRY2(CRC32, G,d, E,y, cpuid(SSE42)),
554 X86_OP_ENTRY2(CRC32, G,d, E,w, cpuid(SSE42)),
555 },
556 [2] = {
557 X86_OP_ENTRY3(ANDN, G,y, B,y, E,y, vex13 cpuid(BMI1)),
558 {},
559 {},
560 {},
561 {},
562 },
563 [3] = {
564 X86_OP_GROUP3(group17, B,y, E,y, None,None, vex13 cpuid(BMI1)),
565 {},
566 {},
567 {},
568 {},
569 },
570 [5] = {
571 X86_OP_ENTRY3(BZHI, G,y, E,y, B,y, vex13 cpuid(BMI1)),
572 {},
573 X86_OP_ENTRY3(PEXT, G,y, B,y, E,y, vex13 cpuid(BMI2)),
574 X86_OP_ENTRY3(PDEP, G,y, B,y, E,y, vex13 cpuid(BMI2)),
575 {},
576 },
577 [6] = {
578 {},
579 X86_OP_ENTRY2(ADCX, G,y, E,y, cpuid(ADX)),
580 X86_OP_ENTRY2(ADOX, G,y, E,y, cpuid(ADX)),
581 X86_OP_ENTRY3(MULX, /* B,y, */ G,y, E,y, 2,y, vex13 cpuid(BMI2)),
582 {},
583 },
584 [7] = {
585 X86_OP_ENTRY3(BEXTR, G,y, E,y, B,y, vex13 cpuid(BMI1)),
586 X86_OP_ENTRY3(SHLX, G,y, E,y, B,y, vex13 cpuid(BMI1)),
587 X86_OP_ENTRY3(SARX, G,y, E,y, B,y, vex13 cpuid(BMI1)),
588 X86_OP_ENTRY3(SHRX, G,y, E,y, B,y, vex13 cpuid(BMI1)),
589 {},
590 },
b3e22b23
PB		 591};
592
593static void decode_0F38(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
594{
595 *b = x86_ldub_code(env, s);
596 if (*b < 0xf0) {
597 *entry = opcodes_0F38_00toEF[*b];
598 } else {
599 int row = 0;
600 if (s->prefix & PREFIX_REPZ) {
601 /* The REPZ (F3) prefix has priority over 66 */
602 row = 2;
603 } else {
604 row += s->prefix & PREFIX_REPNZ ? 3 : 0;
605 row += s->prefix & PREFIX_DATA ? 1 : 0;
606 }
607 *entry = opcodes_0F38_F0toFF[*b & 15][row];
608 }
609}
610
79068477
PB		 611static void decode_VINSERTPS(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
612{
613 static const X86OpEntry
614 vinsertps_reg = X86_OP_ENTRY4(VINSERTPS_r, V,dq, H,dq, U,dq, vex5 cpuid(SSE41) p_66),
615 vinsertps_mem = X86_OP_ENTRY4(VINSERTPS_m, V,dq, H,dq, M,d, vex5 cpuid(SSE41) p_66);
616
617 int modrm = get_modrm(s, env);
618 *entry = (modrm >> 6) == 3 ? vinsertps_reg : vinsertps_mem;
619}
620
b3e22b23 621static const X86OpEntry opcodes_0F3A[256] = {
79068477
PB		 622 /*
623 * These are VEX-only, but incorrectly listed in the manual as exception type 4.
624 * Also the "qq" instructions are sometimes omitted by Table 2-17, but are VEX256
625 * only.
626 */
e000687f
PB		 627 [0x00] = X86_OP_ENTRY3(VPERMQ, V,qq, W,qq, I,b, vex6 chk(W1) cpuid(AVX2) p_66),
628 [0x01] = X86_OP_ENTRY3(VPERMQ, V,qq, W,qq, I,b, vex6 chk(W1) cpuid(AVX2) p_66), /* VPERMPD */
629 [0x02] = X86_OP_ENTRY4(VBLENDPS, V,x, H,x, W,x, vex6 chk(W0) cpuid(AVX2) p_66), /* VPBLENDD */
630 [0x04] = X86_OP_ENTRY3(VPERMILPS_i, V,x, W,x, I,b, vex6 chk(W0) cpuid(AVX) p_66),
631 [0x05] = X86_OP_ENTRY3(VPERMILPD_i, V,x, W,x, I,b, vex6 chk(W0) cpuid(AVX) p_66),
632 [0x06] = X86_OP_ENTRY4(VPERM2x128, V,qq, H,qq, W,qq, vex6 chk(W0) cpuid(AVX) p_66),
79068477
PB		 633
634 [0x14] = X86_OP_ENTRY3(PEXTRB, E,b, V,dq, I,b, vex5 cpuid(SSE41) zext0 p_66),
635 [0x15] = X86_OP_ENTRY3(PEXTRW, E,w, V,dq, I,b, vex5 cpuid(SSE41) zext0 p_66),
636 [0x16] = X86_OP_ENTRY3(PEXTR, E,y, V,dq, I,b, vex5 cpuid(SSE41) p_66),
637 [0x17] = X86_OP_ENTRY3(VEXTRACTPS, E,d, V,dq, I,b, vex5 cpuid(SSE41) p_66),
e000687f 638 [0x1d] = X86_OP_ENTRY3(VCVTPS2PH, W,xh, V,x, I,b, vex11 chk(W0) cpuid(F16C) p_66),
79068477
PB		 639
640 [0x20] = X86_OP_ENTRY4(PINSRB, V,dq, H,dq, E,b, vex5 cpuid(SSE41) zext2 p_66),
641 [0x21] = X86_OP_GROUP0(VINSERTPS),
642 [0x22] = X86_OP_ENTRY4(PINSR, V,dq, H,dq, E,y, vex5 cpuid(SSE41) p_66),
643
644 [0x40] = X86_OP_ENTRY4(VDDPS, V,x, H,x, W,x, vex2 cpuid(SSE41) p_66),
645 [0x41] = X86_OP_ENTRY4(VDDPD, V,dq, H,dq, W,dq, vex2 cpuid(SSE41) p_66),
646 [0x42] = X86_OP_ENTRY4(VMPSADBW, V,x, H,x, W,x, vex2 cpuid(SSE41) avx2_256 p_66),
647 [0x44] = X86_OP_ENTRY4(PCLMULQDQ, V,dq, H,dq, W,dq, vex4 cpuid(PCLMULQDQ) p_66),
e000687f 648 [0x46] = X86_OP_ENTRY4(VPERM2x128, V,qq, H,qq, W,qq, vex6 chk(W0) cpuid(AVX2) p_66),
79068477
PB		 649
650 [0x60] = X86_OP_ENTRY4(PCMPESTRM, None,None, V,dq, W,dq, vex4_unal cpuid(SSE42) p_66),
651 [0x61] = X86_OP_ENTRY4(PCMPESTRI, None,None, V,dq, W,dq, vex4_unal cpuid(SSE42) p_66),
652 [0x62] = X86_OP_ENTRY4(PCMPISTRM, None,None, V,dq, W,dq, vex4_unal cpuid(SSE42) p_66),
653 [0x63] = X86_OP_ENTRY4(PCMPISTRI, None,None, V,dq, W,dq, vex4_unal cpuid(SSE42) p_66),
654
655 [0x08] = X86_OP_ENTRY3(VROUNDPS, V,x, W,x, I,b, vex2 cpuid(SSE41) p_66),
656 [0x09] = X86_OP_ENTRY3(VROUNDPD, V,x, W,x, I,b, vex2 cpuid(SSE41) p_66),
657 /*
658 * Not listed as four operand in the manual. Also writes and reads 128-bits
659 * from the first two operands due to the V operand picking higher entries of
660 * the H operand; the "Vss,Hss,Wss" description from the manual is incorrect.
661 * For other unary operations such as VSQRTSx this is hidden by the "REPScalar"
662 * value of vex_special, because the table lists the operand types of VSQRTPx.
663 */
664 [0x0a] = X86_OP_ENTRY4(VROUNDSS, V,x, H,x, W,ss, vex3 cpuid(SSE41) p_66),
665 [0x0b] = X86_OP_ENTRY4(VROUNDSD, V,x, H,x, W,sd, vex3 cpuid(SSE41) p_66),
666 [0x0c] = X86_OP_ENTRY4(VBLENDPS, V,x, H,x, W,x, vex4 cpuid(SSE41) p_66),
667 [0x0d] = X86_OP_ENTRY4(VBLENDPD, V,x, H,x, W,x, vex4 cpuid(SSE41) p_66),
16fc5726
PB		 668 [0x0e] = X86_OP_ENTRY4(VPBLENDW, V,x, H,x, W,x, vex4 cpuid(SSE41) avx2_256 p_66),
669 [0x0f] = X86_OP_ENTRY4(PALIGNR, V,x, H,x, W,x, vex4 cpuid(SSSE3) mmx avx2_256 p_00_66),
79068477 670
e000687f
PB		 671 [0x18] = X86_OP_ENTRY4(VINSERTx128, V,qq, H,qq, W,qq, vex6 chk(W0) cpuid(AVX) p_66),
672 [0x19] = X86_OP_ENTRY3(VEXTRACTx128, W,dq, V,qq, I,b, vex6 chk(W0) cpuid(AVX) p_66),
79068477 673
e000687f
PB		 674 [0x38] = X86_OP_ENTRY4(VINSERTx128, V,qq, H,qq, W,qq, vex6 chk(W0) cpuid(AVX2) p_66),
675 [0x39] = X86_OP_ENTRY3(VEXTRACTx128, W,dq, V,qq, I,b, vex6 chk(W0) cpuid(AVX2) p_66),
79068477
PB		 676
677 /* Listed incorrectly as type 4 */
e000687f
PB		 678 [0x4a] = X86_OP_ENTRY4(VBLENDVPS, V,x, H,x, W,x, vex6 chk(W0) cpuid(AVX) p_66),
679 [0x4b] = X86_OP_ENTRY4(VBLENDVPD, V,x, H,x, W,x, vex6 chk(W0) cpuid(AVX) p_66),
680 [0x4c] = X86_OP_ENTRY4(VPBLENDVB, V,x, H,x, W,x, vex6 chk(W0) cpuid(AVX) p_66 avx2_256),
79068477 681
e582b629
PB		 682 [0xcc] = X86_OP_ENTRY3(SHA1RNDS4, V,dq, W,dq, I,b, cpuid(SHA_NI)),
683
79068477
PB		 684 [0xdf] = X86_OP_ENTRY3(VAESKEYGEN, V,dq, W,dq, I,b, vex4 cpuid(AES) p_66),
685
1d0b9261 686 [0xF0] = X86_OP_ENTRY3(RORX, G,y, E,y, I,b, vex13 cpuid(BMI2) p_f2),
b3e22b23
PB		 687};
688
689static void decode_0F3A(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
690{
691 *b = x86_ldub_code(env, s);
692 *entry = opcodes_0F3A[*b];
693}
694
7170a17e
PB		 695/*
696 * There are some mistakes in the operands in the manual, and the load/store/register
697 * cases are easiest to keep separate, so the entries for 10-17 follow simplicity and
698 * efficiency of implementation rather than copying what the manual says.
699 *
700 * In particular:
701 *
702 * 1) "VMOVSS m32, xmm1" and "VMOVSD m64, xmm1" do not support VEX.vvvv != 1111b,
703 * but this is not mentioned in the tables.
704 *
705 * 2) MOVHLPS, MOVHPS, MOVHPD, MOVLPD, MOVLPS read the high quadword of one of their
706 * operands, which must therefore be dq; MOVLPD and MOVLPS also write the high
707 * quadword of the V operand.
708 */
709static void decode_0F10(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
710{
711 static const X86OpEntry opcodes_0F10_reg[4] = {
712 X86_OP_ENTRY3(MOVDQ, V,x, None,None, W,x, vex4_unal), /* MOVUPS */
713 X86_OP_ENTRY3(MOVDQ, V,x, None,None, W,x, vex4_unal), /* MOVUPD */
cab529b0
RZ		 714 X86_OP_ENTRY3(VMOVSS, V,x, H,x, W,x, vex5),
715 X86_OP_ENTRY3(VMOVLPx, V,x, H,x, W,x, vex5), /* MOVSD */
7170a17e
PB		 716 };
717
718 static const X86OpEntry opcodes_0F10_mem[4] = {
719 X86_OP_ENTRY3(MOVDQ, V,x, None,None, W,x, vex4_unal), /* MOVUPS */
720 X86_OP_ENTRY3(MOVDQ, V,x, None,None, W,x, vex4_unal), /* MOVUPD */
cab529b0
RZ		 721 X86_OP_ENTRY3(VMOVSS_ld, V,x, H,x, M,ss, vex5),
722 X86_OP_ENTRY3(VMOVSD_ld, V,x, H,x, M,sd, vex5),
7170a17e
PB		 723 };
724
725 if ((get_modrm(s, env) >> 6) == 3) {
726 *entry = *decode_by_prefix(s, opcodes_0F10_reg);
727 } else {
728 *entry = *decode_by_prefix(s, opcodes_0F10_mem);
729 }
730}
731
732static void decode_0F11(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
733{
734 static const X86OpEntry opcodes_0F11_reg[4] = {
afa94dab
RZ		 735 X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex4), /* MOVUPS */
736 X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex4), /* MOVUPD */
cab529b0
RZ		 737 X86_OP_ENTRY3(VMOVSS, W,x, H,x, V,x, vex5),
738 X86_OP_ENTRY3(VMOVLPx, W,x, H,x, V,q, vex5), /* MOVSD */
7170a17e
PB		 739 };
740
741 static const X86OpEntry opcodes_0F11_mem[4] = {
afa94dab
RZ		 742 X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex4), /* MOVUPS */
743 X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex4), /* MOVUPD */
cab529b0
RZ		 744 X86_OP_ENTRY3(VMOVSS_st, M,ss, None,None, V,x, vex5),
745 X86_OP_ENTRY3(VMOVLPx_st, M,sd, None,None, V,x, vex5), /* MOVSD */
7170a17e
PB		 746 };
747
748 if ((get_modrm(s, env) >> 6) == 3) {
749 *entry = *decode_by_prefix(s, opcodes_0F11_reg);
750 } else {
751 *entry = *decode_by_prefix(s, opcodes_0F11_mem);
752 }
753}
754
755static void decode_0F12(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
756{
757 static const X86OpEntry opcodes_0F12_mem[4] = {
758 /*
759 * Use dq for operand for compatibility with gen_MOVSD and
760 * to allow VEX128 only.
761 */
cab529b0
RZ		 762 X86_OP_ENTRY3(VMOVLPx_ld, V,dq, H,dq, M,q, vex5), /* MOVLPS */
763 X86_OP_ENTRY3(VMOVLPx_ld, V,dq, H,dq, M,q, vex5), /* MOVLPD */
7170a17e 764 X86_OP_ENTRY3(VMOVSLDUP, V,x, None,None, W,x, vex4 cpuid(SSE3)),
cab529b0 765 X86_OP_ENTRY3(VMOVDDUP, V,x, None,None, WM,q, vex5 cpuid(SSE3)), /* qq if VEX.256 */
7170a17e
PB		 766 };
767 static const X86OpEntry opcodes_0F12_reg[4] = {
cab529b0
RZ		 768 X86_OP_ENTRY3(VMOVHLPS, V,dq, H,dq, U,dq, vex7),
769 X86_OP_ENTRY3(VMOVLPx, W,x, H,x, U,q, vex5), /* MOVLPD */
7170a17e 770 X86_OP_ENTRY3(VMOVSLDUP, V,x, None,None, U,x, vex4 cpuid(SSE3)),
cab529b0 771 X86_OP_ENTRY3(VMOVDDUP, V,x, None,None, U,x, vex5 cpuid(SSE3)),
7170a17e
PB		 772 };
773
774 if ((get_modrm(s, env) >> 6) == 3) {
775 *entry = *decode_by_prefix(s, opcodes_0F12_reg);
776 } else {
777 *entry = *decode_by_prefix(s, opcodes_0F12_mem);
778 if ((s->prefix & PREFIX_REPNZ) && s->vex_l) {
779 entry->s2 = X86_SIZE_qq;
780 }
781 }
782}
783
784static void decode_0F16(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
785{
786 static const X86OpEntry opcodes_0F16_mem[4] = {
787 /*
788 * Operand 1 technically only reads the low 64 bits, but uses dq so that
789 * it is easier to check for op0 == op1 in an endianness-neutral manner.
790 */
cab529b0
RZ		 791 X86_OP_ENTRY3(VMOVHPx_ld, V,dq, H,dq, M,q, vex5), /* MOVHPS */
792 X86_OP_ENTRY3(VMOVHPx_ld, V,dq, H,dq, M,q, vex5), /* MOVHPD */
7170a17e
PB		 793 X86_OP_ENTRY3(VMOVSHDUP, V,x, None,None, W,x, vex4 cpuid(SSE3)),
794 {},
795 };
796 static const X86OpEntry opcodes_0F16_reg[4] = {
797 /* Same as above, operand 1 could be Hq if it wasn't for big-endian. */
cab529b0
RZ		 798 X86_OP_ENTRY3(VMOVLHPS, V,dq, H,dq, U,q, vex7),
799 X86_OP_ENTRY3(VMOVHPx, V,x, H,x, U,x, vex5), /* MOVHPD */
7170a17e
PB		 800 X86_OP_ENTRY3(VMOVSHDUP, V,x, None,None, U,x, vex4 cpuid(SSE3)),
801 {},
802 };
803
804 if ((get_modrm(s, env) >> 6) == 3) {
805 *entry = *decode_by_prefix(s, opcodes_0F16_reg);
806 } else {
807 *entry = *decode_by_prefix(s, opcodes_0F16_mem);
808 }
809}
810
f8d19eec
PB		 811static void decode_0F2A(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
812{
813 static const X86OpEntry opcodes_0F2A[4] = {
814 X86_OP_ENTRY3(CVTPI2Px, V,x, None,None, Q,q),
815 X86_OP_ENTRY3(CVTPI2Px, V,x, None,None, Q,q),
816 X86_OP_ENTRY3(VCVTSI2Sx, V,x, H,x, E,y, vex3),
817 X86_OP_ENTRY3(VCVTSI2Sx, V,x, H,x, E,y, vex3),
818 };
819 *entry = *decode_by_prefix(s, opcodes_0F2A);
820}
821
822static void decode_0F2B(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
823{
824 static const X86OpEntry opcodes_0F2B[4] = {
8bf171c2
RZ		 825 X86_OP_ENTRY3(MOVDQ, M,x, None,None, V,x, vex1), /* MOVNTPS */
826 X86_OP_ENTRY3(MOVDQ, M,x, None,None, V,x, vex1), /* MOVNTPD */
827 /* AMD extensions */
f8d19eec
PB		 828 X86_OP_ENTRY3(VMOVSS_st, M,ss, None,None, V,x, vex4 cpuid(SSE4A)), /* MOVNTSS */
829 X86_OP_ENTRY3(VMOVLPx_st, M,sd, None,None, V,x, vex4 cpuid(SSE4A)), /* MOVNTSD */
830 };
831
832 *entry = *decode_by_prefix(s, opcodes_0F2B);
833}
834
835static void decode_0F2C(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
836{
837 static const X86OpEntry opcodes_0F2C[4] = {
838 /* Listed as ps/pd in the manual, but CVTTPS2PI only reads 64-bit. */
839 X86_OP_ENTRY3(CVTTPx2PI, P,q, None,None, W,q),
840 X86_OP_ENTRY3(CVTTPx2PI, P,q, None,None, W,dq),
841 X86_OP_ENTRY3(VCVTTSx2SI, G,y, None,None, W,ss, vex3),
842 X86_OP_ENTRY3(VCVTTSx2SI, G,y, None,None, W,sd, vex3),
843 };
844 *entry = *decode_by_prefix(s, opcodes_0F2C);
845}
846
847static void decode_0F2D(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
848{
849 static const X86OpEntry opcodes_0F2D[4] = {
850 /* Listed as ps/pd in the manual, but CVTPS2PI only reads 64-bit. */
851 X86_OP_ENTRY3(CVTPx2PI, P,q, None,None, W,q),
852 X86_OP_ENTRY3(CVTPx2PI, P,q, None,None, W,dq),
853 X86_OP_ENTRY3(VCVTSx2SI, G,y, None,None, W,ss, vex3),
854 X86_OP_ENTRY3(VCVTSx2SI, G,y, None,None, W,sd, vex3),
855 };
856 *entry = *decode_by_prefix(s, opcodes_0F2D);
857}
858
2b55e479
PB		 859static void decode_VxCOMISx(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
860{
861 /*
862 * VUCOMISx and VCOMISx are different and use no-prefix and 0x66 for SS and SD
863 * respectively. Scalar values usually are associated with 0xF2 and 0xF3, for
864 * which X86_VEX_REPScalar exists, but here it has to be decoded by hand.
865 */
866 entry->s1 = entry->s2 = (s->prefix & PREFIX_DATA ? X86_SIZE_sd : X86_SIZE_ss);
867 entry->gen = (*b == 0x2E ? gen_VUCOMI : gen_VCOMI);
868}
869
03b45880
PB		 870static void decode_sse_unary(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
871{
872 if (!(s->prefix & (PREFIX_REPZ | PREFIX_REPNZ))) {
873 entry->op1 = X86_TYPE_None;
874 entry->s1 = X86_SIZE_None;
875 }
876 switch (*b) {
877 case 0x51: entry->gen = gen_VSQRT; break;
878 case 0x52: entry->gen = gen_VRSQRT; break;
879 case 0x53: entry->gen = gen_VRCP; break;
03b45880
PB		 880 }
881}
882
abd41884
PB		 883static void decode_0F5A(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
884{
885 static const X86OpEntry opcodes_0F5A[4] = {
886 X86_OP_ENTRY2(VCVTPS2PD, V,x, W,xh, vex2), /* VCVTPS2PD */
887 X86_OP_ENTRY2(VCVTPD2PS, V,x, W,x, vex2), /* VCVTPD2PS */
888 X86_OP_ENTRY3(VCVTSS2SD, V,x, H,x, W,x, vex2_rep3), /* VCVTSS2SD */
889 X86_OP_ENTRY3(VCVTSD2SS, V,x, H,x, W,x, vex2_rep3), /* VCVTSD2SS */
890 };
891 *entry = *decode_by_prefix(s, opcodes_0F5A);
892}
893
03b45880
PB		 894static void decode_0F5B(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
895{
896 static const X86OpEntry opcodes_0F5B[4] = {
897 X86_OP_ENTRY2(VCVTDQ2PS, V,x, W,x, vex2),
898 X86_OP_ENTRY2(VCVTPS2DQ, V,x, W,x, vex2),
899 X86_OP_ENTRY2(VCVTTPS2DQ, V,x, W,x, vex2),
900 {},
901 };
902 *entry = *decode_by_prefix(s, opcodes_0F5B);
903}
904
6bbeb98d
PB		 905static void decode_0FE6(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
906{
907 static const X86OpEntry opcodes_0FE6[4] = {
908 {},
909 X86_OP_ENTRY2(VCVTTPD2DQ, V,x, W,x, vex2),
cab529b0 910 X86_OP_ENTRY2(VCVTDQ2PD, V,x, W,x, vex5),
6bbeb98d
PB		 911 X86_OP_ENTRY2(VCVTPD2DQ, V,x, W,x, vex2),
912 };
913 *entry = *decode_by_prefix(s, opcodes_0FE6);
914}
915
b3e22b23 916static const X86OpEntry opcodes_0F[256] = {
71a0891d
PB		 917 [0x0E] = X86_OP_ENTRY0(EMMS, cpuid(3DNOW)), /* femms */
918 /*
919 * 3DNow!'s opcode byte comes *after* modrm and displacements, making it
920 * more like an Ib operand. Dispatch to the right helper in a single gen_*
921 * function.
922 */
923 [0x0F] = X86_OP_ENTRY3(3dnow, P,q, Q,q, I,b, cpuid(3DNOW)),
924
7170a17e
PB		 925 [0x10] = X86_OP_GROUP0(0F10),
926 [0x11] = X86_OP_GROUP0(0F11),
927 [0x12] = X86_OP_GROUP0(0F12),
cab529b0 928 [0x13] = X86_OP_ENTRY3(VMOVLPx_st, M,q, None,None, V,q, vex5 p_00_66),
7170a17e
PB		 929 [0x14] = X86_OP_ENTRY3(VUNPCKLPx, V,x, H,x, W,x, vex4 p_00_66),
930 [0x15] = X86_OP_ENTRY3(VUNPCKHPx, V,x, H,x, W,x, vex4 p_00_66),
931 [0x16] = X86_OP_GROUP0(0F16),
932 /* Incorrectly listed as Mq,Vq in the manual */
cab529b0 933 [0x17] = X86_OP_ENTRY3(VMOVHPx_st, M,q, None,None, V,dq, vex5 p_00_66),
7170a17e 934
03b45880 935 [0x50] = X86_OP_ENTRY3(MOVMSK, G,y, None,None, U,x, vex7 p_00_66),
afa94dab
RZ		 936 [0x51] = X86_OP_GROUP3(sse_unary, V,x, H,x, W,x, vex2_rep3 p_00_66_f3_f2), /* sqrtps */
937 [0x52] = X86_OP_GROUP3(sse_unary, V,x, H,x, W,x, vex4_rep5 p_00_f3), /* rsqrtps */
938 [0x53] = X86_OP_GROUP3(sse_unary, V,x, H,x, W,x, vex4_rep5 p_00_f3), /* rcpps */
03b45880
PB		 939 [0x54] = X86_OP_ENTRY3(PAND, V,x, H,x, W,x, vex4 p_00_66), /* vand */
940 [0x55] = X86_OP_ENTRY3(PANDN, V,x, H,x, W,x, vex4 p_00_66), /* vandn */
941 [0x56] = X86_OP_ENTRY3(POR, V,x, H,x, W,x, vex4 p_00_66), /* vor */
942 [0x57] = X86_OP_ENTRY3(PXOR, V,x, H,x, W,x, vex4 p_00_66), /* vxor */
943
92ec056a
PB		 944 [0x60] = X86_OP_ENTRY3(PUNPCKLBW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
945 [0x61] = X86_OP_ENTRY3(PUNPCKLWD, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
946 [0x62] = X86_OP_ENTRY3(PUNPCKLDQ, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
947 [0x63] = X86_OP_ENTRY3(PACKSSWB, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
948 [0x64] = X86_OP_ENTRY3(PCMPGTB, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
949 [0x65] = X86_OP_ENTRY3(PCMPGTW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
950 [0x66] = X86_OP_ENTRY3(PCMPGTD, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
951 [0x67] = X86_OP_ENTRY3(PACKUSWB, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
952
ce4fcb94
PB		 953 [0x70] = X86_OP_GROUP0(0F70),
954 [0x71] = X86_OP_GROUP0(group12),
955 [0x72] = X86_OP_GROUP0(group13),
956 [0x73] = X86_OP_GROUP0(group14),
957 [0x74] = X86_OP_ENTRY3(PCMPEQB, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
958 [0x75] = X86_OP_ENTRY3(PCMPEQW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
959 [0x76] = X86_OP_ENTRY3(PCMPEQD, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
960 [0x77] = X86_OP_GROUP0(0F77),
961
f8d19eec
PB		 962 [0x28] = X86_OP_ENTRY3(MOVDQ, V,x, None,None, W,x, vex1 p_00_66), /* MOVAPS */
963 [0x29] = X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex1 p_00_66), /* MOVAPS */
964 [0x2A] = X86_OP_GROUP0(0F2A),
965 [0x2B] = X86_OP_GROUP0(0F2B),
966 [0x2C] = X86_OP_GROUP0(0F2C),
967 [0x2D] = X86_OP_GROUP0(0F2D),
2b55e479
PB		 968 [0x2E] = X86_OP_GROUP3(VxCOMISx, None,None, V,x, W,x, vex3 p_00_66), /* VUCOMISS/SD */
969 [0x2F] = X86_OP_GROUP3(VxCOMISx, None,None, V,x, W,x, vex3 p_00_66), /* VCOMISS/SD */
f8d19eec 970
b3e22b23
PB		 971 [0x38] = X86_OP_GROUP0(0F38),
972 [0x3a] = X86_OP_GROUP0(0F3A),
92ec056a 973
03b45880
PB		 974 [0x58] = X86_OP_ENTRY3(VADD, V,x, H,x, W,x, vex2_rep3 p_00_66_f3_f2),
975 [0x59] = X86_OP_ENTRY3(VMUL, V,x, H,x, W,x, vex2_rep3 p_00_66_f3_f2),
abd41884 976 [0x5a] = X86_OP_GROUP0(0F5A),
03b45880
PB		 977 [0x5b] = X86_OP_GROUP0(0F5B),
978 [0x5c] = X86_OP_ENTRY3(VSUB, V,x, H,x, W,x, vex2_rep3 p_00_66_f3_f2),
979 [0x5d] = X86_OP_ENTRY3(VMIN, V,x, H,x, W,x, vex2_rep3 p_00_66_f3_f2),
980 [0x5e] = X86_OP_ENTRY3(VDIV, V,x, H,x, W,x, vex2_rep3 p_00_66_f3_f2),
981 [0x5f] = X86_OP_ENTRY3(VMAX, V,x, H,x, W,x, vex2_rep3 p_00_66_f3_f2),
982
92ec056a
PB		 983 [0x68] = X86_OP_ENTRY3(PUNPCKHBW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
984 [0x69] = X86_OP_ENTRY3(PUNPCKHWD, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
985 [0x6a] = X86_OP_ENTRY3(PUNPCKHDQ, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
986 [0x6b] = X86_OP_ENTRY3(PACKSSDW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
987 [0x6c] = X86_OP_ENTRY3(PUNPCKLQDQ, V,x, H,x, W,x, vex4 p_66 avx2_256),
988 [0x6d] = X86_OP_ENTRY3(PUNPCKHQDQ, V,x, H,x, W,x, vex4 p_66 avx2_256),
989 [0x6e] = X86_OP_ENTRY3(MOVD_to, V,x, None,None, E,y, vex5 mmx p_00_66), /* wrong dest Vy on SDM! */
990 [0x6f] = X86_OP_GROUP0(0F6F),
1d0efbdb 991
d1c1a422
PB		 992 [0x78] = X86_OP_GROUP0(0F78),
993 [0x79] = X86_OP_GROUP2(0F79, V,x, U,x, cpuid(SSE4A)),
994 [0x7c] = X86_OP_ENTRY3(VHADD, V,x, H,x, W,x, vex2 cpuid(SSE3) p_66_f2),
995 [0x7d] = X86_OP_ENTRY3(VHSUB, V,x, H,x, W,x, vex2 cpuid(SSE3) p_66_f2),
996 [0x7e] = X86_OP_GROUP0(0F7E),
997 [0x7f] = X86_OP_GROUP0(0F7F),
998
57f6bba0
PB		 999 [0xae] = X86_OP_GROUP0(group15),
1000
aba2b8ec
PB		 1001 [0xc2] = X86_OP_ENTRY4(VCMP, V,x, H,x, W,x, vex2_rep3 p_00_66_f3_f2),
1002 [0xc4] = X86_OP_ENTRY4(PINSRW, V,dq,H,dq,E,w, vex5 mmx p_00_66),
1003 [0xc5] = X86_OP_ENTRY3(PEXTRW, G,d, U,dq,I,b, vex5 mmx p_00_66),
1004 [0xc6] = X86_OP_ENTRY4(VSHUF, V,x, H,x, W,x, vex4 p_00_66),
1005
6bbeb98d
PB		 1006 [0xd0] = X86_OP_ENTRY3(VADDSUB, V,x, H,x, W,x, vex2 cpuid(SSE3) p_66_f2),
1007 [0xd1] = X86_OP_ENTRY3(PSRLW_r, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
1008 [0xd2] = X86_OP_ENTRY3(PSRLD_r, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
1009 [0xd3] = X86_OP_ENTRY3(PSRLQ_r, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
1010 [0xd4] = X86_OP_ENTRY3(PADDQ, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
1011 [0xd5] = X86_OP_ENTRY3(PMULLW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
1012 [0xd6] = X86_OP_GROUP0(0FD6),
1013 [0xd7] = X86_OP_ENTRY3(PMOVMSKB, G,d, None,None, U,x, vex7 mmx avx2_256 p_00_66),
1014
1015 [0xe0] = X86_OP_ENTRY3(PAVGB, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
1016 [0xe1] = X86_OP_ENTRY3(PSRAW_r, V,x, H,x, W,x, vex7 mmx avx2_256 p_00_66),
1017 [0xe2] = X86_OP_ENTRY3(PSRAD_r, V,x, H,x, W,x, vex7 mmx avx2_256 p_00_66),
1018 [0xe3] = X86_OP_ENTRY3(PAVGW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
1019 [0xe4] = X86_OP_ENTRY3(PMULHUW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
1020 [0xe5] = X86_OP_ENTRY3(PMULHW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
1021 [0xe6] = X86_OP_GROUP0(0FE6),
1022 [0xe7] = X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex1 mmx p_00_66), /* MOVNTQ/MOVNTDQ */
1023
1024 [0xf0] = X86_OP_ENTRY3(MOVDQ, V,x, None,None, WM,x, vex4_unal cpuid(SSE3) p_f2), /* LDDQU */
1025 [0xf1] = X86_OP_ENTRY3(PSLLW_r, V,x, H,x, W,x, vex7 mmx avx2_256 p_00_66),
1026 [0xf2] = X86_OP_ENTRY3(PSLLD_r, V,x, H,x, W,x, vex7 mmx avx2_256 p_00_66),
1027 [0xf3] = X86_OP_ENTRY3(PSLLQ_r, V,x, H,x, W,x, vex7 mmx avx2_256 p_00_66),
1028 [0xf4] = X86_OP_ENTRY3(PMULUDQ, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
1029 [0xf5] = X86_OP_ENTRY3(PMADDWD, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
1030 [0xf6] = X86_OP_ENTRY3(PSADBW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
1031 [0xf7] = X86_OP_ENTRY3(MASKMOV, None,None, V,dq, U,dq, vex4_unal avx2_256 mmx p_00_66),
1032
1d0efbdb
PB		 1033 /* Incorrectly missing from 2-17 */
1034 [0xd8] = X86_OP_ENTRY3(PSUBUSB, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
1035 [0xd9] = X86_OP_ENTRY3(PSUBUSW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
1036 [0xda] = X86_OP_ENTRY3(PMINUB, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
1037 [0xdb] = X86_OP_ENTRY3(PAND, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
1038 [0xdc] = X86_OP_ENTRY3(PADDUSB, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
1039 [0xdd] = X86_OP_ENTRY3(PADDUSW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
1040 [0xde] = X86_OP_ENTRY3(PMAXUB, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
1041 [0xdf] = X86_OP_ENTRY3(PANDN, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
1042
1043 [0xe8] = X86_OP_ENTRY3(PSUBSB, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
1044 [0xe9] = X86_OP_ENTRY3(PSUBSW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
1045 [0xea] = X86_OP_ENTRY3(PMINSW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
1046 [0xeb] = X86_OP_ENTRY3(POR, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
1047 [0xec] = X86_OP_ENTRY3(PADDSB, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
1048 [0xed] = X86_OP_ENTRY3(PADDSW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
1049 [0xee] = X86_OP_ENTRY3(PMAXSW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
1050 [0xef] = X86_OP_ENTRY3(PXOR, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
1051
1052 [0xf8] = X86_OP_ENTRY3(PSUBB, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
1053 [0xf9] = X86_OP_ENTRY3(PSUBW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
1054 [0xfa] = X86_OP_ENTRY3(PSUBD, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
1055 [0xfb] = X86_OP_ENTRY3(PSUBQ, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
1056 [0xfc] = X86_OP_ENTRY3(PADDB, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
1057 [0xfd] = X86_OP_ENTRY3(PADDW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
1058 [0xfe] = X86_OP_ENTRY3(PADDD, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
1059 /* 0xff = UD0 */
b3e22b23
PB		 1060};
1061
1062static void do_decode_0F(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
1063{
1064 *entry = opcodes_0F[*b];
1065}
1066
1067static void decode_0F(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
1068{
1069 *b = x86_ldub_code(env, s);
1070 do_decode_0F(s, env, entry, b);
1071}
1072
1073static const X86OpEntry opcodes_root[256] = {
1074 [0x0F] = X86_OP_GROUP0(0F),
1075};
1076
1077#undef mmx
20581aad
PB		 1078#undef vex1
1079#undef vex2
1080#undef vex3
1081#undef vex4
1082#undef vex4_unal
1083#undef vex5
1084#undef vex6
1085#undef vex7
1086#undef vex8
1087#undef vex11
1088#undef vex12
1089#undef vex13
b3e22b23
PB		 1090
1091/*
1092 * Decode the fixed part of the opcode and place the last
1093 * in b.
1094 */
1095static void decode_root(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
1096{
1097 *entry = opcodes_root[*b];
1098}
1099
1100
1101static int decode_modrm(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode,
1102 X86DecodedOp *op, X86OpType type)
1103{
1104 int modrm = get_modrm(s, env);
1105 if ((modrm >> 6) == 3) {
1106 if (s->prefix & PREFIX_LOCK) {
1107 decode->e.gen = gen_illegal;
1108 return 0xff;
1109 }
1110 op->n = (modrm & 7);
1111 if (type != X86_TYPE_Q && type != X86_TYPE_N) {
1112 op->n |= REX_B(s);
1113 }
1114 } else {
1115 op->has_ea = true;
1116 op->n = -1;
1117 decode->mem = gen_lea_modrm_0(env, s, get_modrm(s, env));
1118 }
1119 return modrm;
1120}
1121
1122static bool decode_op_size(DisasContext *s, X86OpEntry *e, X86OpSize size, MemOp *ot)
1123{
1124 switch (size) {
1125 case X86_SIZE_b: /* byte */
1126 *ot = MO_8;
1127 return true;
1128
1129 case X86_SIZE_d: /* 32-bit */
1130 case X86_SIZE_ss: /* SSE/AVX scalar single precision */
1131 *ot = MO_32;
1132 return true;
1133
1134 case X86_SIZE_p: /* Far pointer, return offset size */
1135 case X86_SIZE_s: /* Descriptor, return offset size */
1136 case X86_SIZE_v: /* 16/32/64-bit, based on operand size */
1137 *ot = s->dflag;
1138 return true;
1139
1140 case X86_SIZE_pi: /* MMX */
1141 case X86_SIZE_q: /* 64-bit */
1142 case X86_SIZE_sd: /* SSE/AVX scalar double precision */
1143 *ot = MO_64;
1144 return true;
1145
1146 case X86_SIZE_w: /* 16-bit */
1147 *ot = MO_16;
1148 return true;
1149
1150 case X86_SIZE_y: /* 32/64-bit, based on operand size */
1151 *ot = s->dflag == MO_16 ? MO_32 : s->dflag;
1152 return true;
1153
1154 case X86_SIZE_z: /* 16-bit for 16-bit operand size, else 32-bit */
1155 *ot = s->dflag == MO_16 ? MO_16 : MO_32;
1156 return true;
1157
1158 case X86_SIZE_dq: /* SSE/AVX 128-bit */
1159 if (e->special == X86_SPECIAL_MMX &&
1160 !(s->prefix & (PREFIX_DATA | PREFIX_REPZ | PREFIX_REPNZ))) {
1161 *ot = MO_64;
1162 return true;
1163 }
1164 if (s->vex_l && e->s0 != X86_SIZE_qq && e->s1 != X86_SIZE_qq) {
1165 return false;
1166 }
1167 *ot = MO_128;
1168 return true;
1169
1170 case X86_SIZE_qq: /* AVX 256-bit */
1171 if (!s->vex_l) {
1172 return false;
1173 }
1174 *ot = MO_256;
1175 return true;
1176
1177 case X86_SIZE_x: /* 128/256-bit, based on operand size */
1178 if (e->special == X86_SPECIAL_MMX &&
1179 !(s->prefix & (PREFIX_DATA | PREFIX_REPZ | PREFIX_REPNZ))) {
1180 *ot = MO_64;
1181 return true;
1182 }
1183 /* fall through */
1184 case X86_SIZE_ps: /* SSE/AVX packed single precision */
1185 case X86_SIZE_pd: /* SSE/AVX packed double precision */
1186 *ot = s->vex_l ? MO_256 : MO_128;
1187 return true;
1188
a48b2697 1189 case X86_SIZE_xh: /* SSE/AVX packed half register */
cf5ec664
PB		 1190 *ot = s->vex_l ? MO_128 : MO_64;
1191 return true;
1192
b3e22b23
PB		 1193 case X86_SIZE_d64: /* Default to 64-bit in 64-bit mode */
1194 *ot = CODE64(s) && s->dflag == MO_32 ? MO_64 : s->dflag;
1195 return true;
1196
1197 case X86_SIZE_f64: /* Ignore size override prefix in 64-bit mode */
1198 *ot = CODE64(s) ? MO_64 : s->dflag;
1199 return true;
1200
1201 default:
1202 *ot = -1;
1203 return true;
1204 }
1205}
1206
1207static bool decode_op(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode,
1208 X86DecodedOp *op, X86OpType type, int b)
1209{
1210 int modrm;
1211
1212 switch (type) {
1213 case X86_TYPE_None: /* Implicit or absent */
1214 case X86_TYPE_A: /* Implicit */
1215 case X86_TYPE_F: /* EFLAGS/RFLAGS */
1216 break;
1217
1218 case X86_TYPE_B: /* VEX.vvvv selects a GPR */
1219 op->unit = X86_OP_INT;
1220 op->n = s->vex_v;
1221 break;
1222
1223 case X86_TYPE_C: /* REG in the modrm byte selects a control register */
1224 op->unit = X86_OP_CR;
1225 goto get_reg;
1226
1227 case X86_TYPE_D: /* REG in the modrm byte selects a debug register */
1228 op->unit = X86_OP_DR;
1229 goto get_reg;
1230
1231 case X86_TYPE_G: /* REG in the modrm byte selects a GPR */
1232 op->unit = X86_OP_INT;
1233 goto get_reg;
1234
1235 case X86_TYPE_S: /* reg selects a segment register */
1236 op->unit = X86_OP_SEG;
1237 goto get_reg;
1238
1239 case X86_TYPE_P:
1240 op->unit = X86_OP_MMX;
1241 goto get_reg;
1242
1243 case X86_TYPE_V: /* reg in the modrm byte selects an XMM/YMM register */
1244 if (decode->e.special == X86_SPECIAL_MMX &&
1245 !(s->prefix & (PREFIX_DATA | PREFIX_REPZ | PREFIX_REPNZ))) {
1246 op->unit = X86_OP_MMX;
1247 } else {
1248 op->unit = X86_OP_SSE;
1249 }
1250 get_reg:
1251 op->n = ((get_modrm(s, env) >> 3) & 7) | REX_R(s);
1252 break;
1253
1254 case X86_TYPE_E: /* ALU modrm operand */
1255 op->unit = X86_OP_INT;
1256 goto get_modrm;
1257
1258 case X86_TYPE_Q: /* MMX modrm operand */
1259 op->unit = X86_OP_MMX;
1260 goto get_modrm;
1261
1262 case X86_TYPE_W: /* XMM/YMM modrm operand */
1263 if (decode->e.special == X86_SPECIAL_MMX &&
1264 !(s->prefix & (PREFIX_DATA | PREFIX_REPZ | PREFIX_REPNZ))) {
1265 op->unit = X86_OP_MMX;
1266 } else {
1267 op->unit = X86_OP_SSE;
1268 }
1269 goto get_modrm;
1270
1271 case X86_TYPE_N: /* R/M in the modrm byte selects an MMX register */
1272 op->unit = X86_OP_MMX;
1273 goto get_modrm_reg;
1274
1275 case X86_TYPE_U: /* R/M in the modrm byte selects an XMM/YMM register */
1276 if (decode->e.special == X86_SPECIAL_MMX &&
1277 !(s->prefix & (PREFIX_DATA | PREFIX_REPZ | PREFIX_REPNZ))) {
1278 op->unit = X86_OP_MMX;
1279 } else {
1280 op->unit = X86_OP_SSE;
1281 }
1282 goto get_modrm_reg;
1283
1284 case X86_TYPE_R: /* R/M in the modrm byte selects a register */
1285 op->unit = X86_OP_INT;
1286 get_modrm_reg:
1287 modrm = get_modrm(s, env);
1288 if ((modrm >> 6) != 3) {
1289 return false;
1290 }
1291 goto get_modrm;
1292
6bbeb98d
PB		 1293 case X86_TYPE_WM: /* modrm byte selects an XMM/YMM memory operand */
1294 op->unit = X86_OP_SSE;
1295 /* fall through */
b3e22b23
PB		 1296 case X86_TYPE_M: /* modrm byte selects a memory operand */
1297 modrm = get_modrm(s, env);
1298 if ((modrm >> 6) == 3) {
1299 return false;
1300 }
1301 get_modrm:
1302 decode_modrm(s, env, decode, op, type);
1303 break;
1304
1305 case X86_TYPE_O: /* Absolute address encoded in the instruction */
1306 op->unit = X86_OP_INT;
1307 op->has_ea = true;
1308 op->n = -1;
1309 decode->mem = (AddressParts) {
1310 .def_seg = R_DS,
1311 .base = -1,
1312 .index = -1,
1313 .disp = insn_get_addr(env, s, s->aflag)
1314 };
1315 break;
1316
1317 case X86_TYPE_H: /* For AVX, VEX.vvvv selects an XMM/YMM register */
1318 if ((s->prefix & PREFIX_VEX)) {
1319 op->unit = X86_OP_SSE;
1320 op->n = s->vex_v;
1321 break;
1322 }
1323 if (op == &decode->op[0]) {
1324 /* shifts place the destination in VEX.vvvv, use modrm */
1325 return decode_op(s, env, decode, op, decode->e.op1, b);
1326 } else {
1327 return decode_op(s, env, decode, op, decode->e.op0, b);
1328 }
1329
1330 case X86_TYPE_I: /* Immediate */
1331 op->unit = X86_OP_IMM;
1332 decode->immediate = insn_get_signed(env, s, op->ot);
1333 break;
1334
1335 case X86_TYPE_J: /* Relative offset for a jump */
1336 op->unit = X86_OP_IMM;
1337 decode->immediate = insn_get_signed(env, s, op->ot);
1338 decode->immediate += s->pc - s->cs_base;
1339 if (s->dflag == MO_16) {
1340 decode->immediate &= 0xffff;
1341 } else if (!CODE64(s)) {
1342 decode->immediate &= 0xffffffffu;
1343 }
1344 break;
1345
1346 case X86_TYPE_L: /* The upper 4 bits of the immediate select a 128-bit register */
1347 op->n = insn_get(env, s, op->ot) >> 4;
1348 break;
1349
1350 case X86_TYPE_X: /* string source */
1351 op->n = -1;
1352 decode->mem = (AddressParts) {
1353 .def_seg = R_DS,
1354 .base = R_ESI,
1355 .index = -1,
1356 };
1357 break;
1358
1359 case X86_TYPE_Y: /* string destination */
1360 op->n = -1;
1361 decode->mem = (AddressParts) {
1362 .def_seg = R_ES,
1363 .base = R_EDI,
1364 .index = -1,
1365 };
1366 break;
1367
1368 case X86_TYPE_2op:
1369 *op = decode->op[0];
1370 break;
1371
1372 case X86_TYPE_LoBits:
1373 op->n = (b & 7) | REX_B(s);
1374 op->unit = X86_OP_INT;
1375 break;
1376
1377 case X86_TYPE_0 ... X86_TYPE_7:
1378 op->n = type - X86_TYPE_0;
1379 op->unit = X86_OP_INT;
1380 break;
1381
1382 case X86_TYPE_ES ... X86_TYPE_GS:
1383 op->n = type - X86_TYPE_ES;
1384 op->unit = X86_OP_SEG;
1385 break;
1386 }
1387
1388 return true;
1389}
1390
55a33286
PB		 1391static bool validate_sse_prefix(DisasContext *s, X86OpEntry *e)
1392{
1393 uint16_t sse_prefixes;
1394
1395 if (!e->valid_prefix) {
1396 return true;
1397 }
1398 if (s->prefix & (PREFIX_REPZ | PREFIX_REPNZ)) {
1399 /* In SSE instructions, 0xF3 and 0xF2 cancel 0x66. */
1400 s->prefix &= ~PREFIX_DATA;
1401 }
1402
1403 /* Now, either zero or one bit is set in sse_prefixes. */
1404 sse_prefixes = s->prefix & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA);
1405 return e->valid_prefix & (1 << sse_prefixes);
1406}
1407
b3e22b23
PB		 1408static bool decode_insn(DisasContext *s, CPUX86State *env, X86DecodeFunc decode_func,
1409 X86DecodedInsn *decode)
1410{
1411 X86OpEntry *e = &decode->e;
1412
1413 decode_func(s, env, e, &decode->b);
1414 while (e->is_decode) {
1415 e->is_decode = false;
1416 e->decode(s, env, e, &decode->b);
1417 }
1418
55a33286
PB		 1419 if (!validate_sse_prefix(s, e)) {
1420 return false;
1421 }
1422
b3e22b23
PB		 1423 /* First compute size of operands in order to initialize s->rip_offset. */
1424 if (e->op0 != X86_TYPE_None) {
1425 if (!decode_op_size(s, e, e->s0, &decode->op[0].ot)) {
1426 return false;
1427 }
1428 if (e->op0 == X86_TYPE_I) {
1429 s->rip_offset += 1 << decode->op[0].ot;
1430 }
1431 }
1432 if (e->op1 != X86_TYPE_None) {
1433 if (!decode_op_size(s, e, e->s1, &decode->op[1].ot)) {
1434 return false;
1435 }
1436 if (e->op1 == X86_TYPE_I) {
1437 s->rip_offset += 1 << decode->op[1].ot;
1438 }
1439 }
1440 if (e->op2 != X86_TYPE_None) {
1441 if (!decode_op_size(s, e, e->s2, &decode->op[2].ot)) {
1442 return false;
1443 }
1444 if (e->op2 == X86_TYPE_I) {
1445 s->rip_offset += 1 << decode->op[2].ot;
1446 }
1447 }
1448 if (e->op3 != X86_TYPE_None) {
79068477
PB		 1449 /*
1450 * A couple instructions actually use the extra immediate byte for an Lx
1451 * register operand; those are handled in the gen_* functions as one off.
1452 */
b3e22b23
PB		 1453 assert(e->op3 == X86_TYPE_I && e->s3 == X86_SIZE_b);
1454 s->rip_offset += 1;
1455 }
1456
1457 if (e->op0 != X86_TYPE_None &&
1458 !decode_op(s, env, decode, &decode->op[0], e->op0, decode->b)) {
1459 return false;
1460 }
1461
1462 if (e->op1 != X86_TYPE_None &&
1463 !decode_op(s, env, decode, &decode->op[1], e->op1, decode->b)) {
1464 return false;
1465 }
1466
1467 if (e->op2 != X86_TYPE_None &&
1468 !decode_op(s, env, decode, &decode->op[2], e->op2, decode->b)) {
1469 return false;
1470 }
1471
1472 if (e->op3 != X86_TYPE_None) {
1473 decode->immediate = insn_get_signed(env, s, MO_8);
1474 }
1475
1476 return true;
1477}
1478
caa01fad
PB		 1479static bool has_cpuid_feature(DisasContext *s, X86CPUIDFeature cpuid)
1480{
1481 switch (cpuid) {
1482 case X86_FEAT_None:
1483 return true;
cf5ec664
PB		 1484 case X86_FEAT_F16C:
1485 return (s->cpuid_ext_features & CPUID_EXT_F16C);
2872b0f3
PB		 1486 case X86_FEAT_FMA:
1487 return (s->cpuid_ext_features & CPUID_EXT_FMA);
caa01fad
PB		 1488 case X86_FEAT_MOVBE:
1489 return (s->cpuid_ext_features & CPUID_EXT_MOVBE);
1490 case X86_FEAT_PCLMULQDQ:
1491 return (s->cpuid_ext_features & CPUID_EXT_PCLMULQDQ);
1492 case X86_FEAT_SSE:
1493 return (s->cpuid_ext_features & CPUID_SSE);
1494 case X86_FEAT_SSE2:
1495 return (s->cpuid_ext_features & CPUID_SSE2);
1496 case X86_FEAT_SSE3:
1497 return (s->cpuid_ext_features & CPUID_EXT_SSE3);
1498 case X86_FEAT_SSSE3:
1499 return (s->cpuid_ext_features & CPUID_EXT_SSSE3);
1500 case X86_FEAT_SSE41:
1501 return (s->cpuid_ext_features & CPUID_EXT_SSE41);
1502 case X86_FEAT_SSE42:
1503 return (s->cpuid_ext_features & CPUID_EXT_SSE42);
1504 case X86_FEAT_AES:
1505 if (!(s->cpuid_ext_features & CPUID_EXT_AES)) {
1506 return false;
1507 } else if (!(s->prefix & PREFIX_VEX)) {
1508 return true;
1509 } else if (!(s->cpuid_ext_features & CPUID_EXT_AVX)) {
1510 return false;
1511 } else {
1512 return !s->vex_l || (s->cpuid_7_0_ecx_features & CPUID_7_0_ECX_VAES);
1513 }
1514
1515 case X86_FEAT_AVX:
1516 return (s->cpuid_ext_features & CPUID_EXT_AVX);
1517
71a0891d
PB		 1518 case X86_FEAT_3DNOW:
1519 return (s->cpuid_ext2_features & CPUID_EXT2_3DNOW);
caa01fad
PB		 1520 case X86_FEAT_SSE4A:
1521 return (s->cpuid_ext3_features & CPUID_EXT3_SSE4A);
1522
1523 case X86_FEAT_ADX:
1524 return (s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_ADX);
1525 case X86_FEAT_BMI1:
1526 return (s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_BMI1);
1527 case X86_FEAT_BMI2:
1528 return (s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_BMI2);
1529 case X86_FEAT_AVX2:
1530 return (s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_AVX2);
e582b629
PB		 1531 case X86_FEAT_SHA_NI:
1532 return (s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_SHA_NI);
caa01fad
PB		 1533 }
1534 g_assert_not_reached();
1535}
1536
20581aad
PB		 1537static bool validate_vex(DisasContext *s, X86DecodedInsn *decode)
1538{
1539 X86OpEntry *e = &decode->e;
1540
1541 switch (e->vex_special) {
1542 case X86_VEX_REPScalar:
1543 /*
1544 * Instructions which differ between 00/66 and F2/F3 in the
1545 * exception classification and the size of the memory operand.
1546 */
3d304620 1547 assert(e->vex_class == 1 || e->vex_class == 2 || e->vex_class == 4);
20581aad 1548 if (s->prefix & (PREFIX_REPZ | PREFIX_REPNZ)) {
3d304620 1549 e->vex_class = e->vex_class < 4 ? 3 : 5;
20581aad
PB		 1550 if (s->vex_l) {
1551 goto illegal;
1552 }
1553 assert(decode->e.s2 == X86_SIZE_x);
1554 if (decode->op[2].has_ea) {
1555 decode->op[2].ot = s->prefix & PREFIX_REPZ ? MO_32 : MO_64;
1556 }
1557 }
1558 break;
1559
1560 case X86_VEX_SSEUnaligned:
1561 /* handled in sse_needs_alignment. */
1562 break;
1563
1564 case X86_VEX_AVX2_256:
1565 if ((s->prefix & PREFIX_VEX) && s->vex_l && !has_cpuid_feature(s, X86_FEAT_AVX2)) {
1566 goto illegal;
1567 }
1568 }
1569
20581aad
PB		 1570 switch (e->vex_class) {
1571 case 0:
1572 if (s->prefix & PREFIX_VEX) {
1573 goto illegal;
1574 }
1575 return true;
1576 case 1:
1577 case 2:
1578 case 3:
1579 case 4:
1580 case 5:
1581 case 7:
1582 if (s->prefix & PREFIX_VEX) {
1583 if (!(s->flags & HF_AVX_EN_MASK)) {
1584 goto illegal;
1585 }
38e65936
PB		 1586 } else if (e->special != X86_SPECIAL_MMX ||
1587 (s->prefix & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))) {
20581aad
PB		 1588 if (!(s->flags & HF_OSFXSR_MASK)) {
1589 goto illegal;
1590 }
1591 }
1592 break;
1593 case 12:
1594 /* Must have a VSIB byte and no address prefix. */
1595 assert(s->has_modrm);
1596 if ((s->modrm & 7) != 4 || s->aflag == MO_16) {
1597 goto illegal;
1598 }
1599
1600 /* Check no overlap between registers. */
1601 if (!decode->op[0].has_ea &&
1602 (decode->op[0].n == decode->mem.index || decode->op[0].n == decode->op[1].n)) {
1603 goto illegal;
1604 }
1605 assert(!decode->op[1].has_ea);
1606 if (decode->op[1].n == decode->mem.index) {
1607 goto illegal;
1608 }
1609 if (!decode->op[2].has_ea &&
1610 (decode->op[2].n == decode->mem.index || decode->op[2].n == decode->op[1].n)) {
1611 goto illegal;
1612 }
1613 /* fall through */
1614 case 6:
1615 case 11:
1616 if (!(s->prefix & PREFIX_VEX)) {
1617 goto illegal;
1618 }
1619 if (!(s->flags & HF_AVX_EN_MASK)) {
1620 goto illegal;
1621 }
1622 break;
1623 case 8:
ce4fcb94
PB		 1624 /* Non-VEX case handled in decode_0F77. */
1625 assert(s->prefix & PREFIX_VEX);
20581aad
PB		 1626 if (!(s->flags & HF_AVX_EN_MASK)) {
1627 goto illegal;
1628 }
1629 break;
1630 case 13:
1631 if (!(s->prefix & PREFIX_VEX)) {
1632 goto illegal;
1633 }
1634 if (s->vex_l) {
1635 goto illegal;
1636 }
1637 /* All integer instructions use VEX.vvvv, so exit. */
1638 return true;
1639 }
1640
1641 if (s->vex_v != 0 &&
1642 e->op0 != X86_TYPE_H && e->op0 != X86_TYPE_B &&
1643 e->op1 != X86_TYPE_H && e->op1 != X86_TYPE_B &&
1644 e->op2 != X86_TYPE_H && e->op2 != X86_TYPE_B) {
1645 goto illegal;
1646 }
1647
1648 if (s->flags & HF_TS_MASK) {
1649 goto nm_exception;
1650 }
1651 if (s->flags & HF_EM_MASK) {
1652 goto illegal;
1653 }
183e6679 1654
e000687f
PB		 1655 if (e->check) {
1656 if (e->check & X86_CHECK_VEX128) {
1657 if (s->vex_l) {
1658 goto illegal;
1659 }
1660 }
1661 if (e->check & X86_CHECK_W0) {
1662 if (s->vex_w) {
1663 goto illegal;
1664 }
1665 }
1666 if (e->check & X86_CHECK_W1) {
1667 if (!s->vex_w) {
1668 goto illegal;
1669 }
183e6679
PB		 1670 }
1671 }
20581aad
PB		 1672 return true;
1673
1674nm_exception:
1675 gen_NM_exception(s);
1676 return false;
1677illegal:
1678 gen_illegal_opcode(s);
1679 return false;
1680}
1681
b3e22b23
PB		 1682/*
1683 * Convert one instruction. s->base.is_jmp is set if the translation must
1684 * be stopped.
1685 */
1686static void disas_insn_new(DisasContext *s, CPUState *cpu, int b)
1687{
b77af26e 1688 CPUX86State *env = cpu_env(cpu);
b3e22b23
PB		 1689 bool first = true;
1690 X86DecodedInsn decode;
1691 X86DecodeFunc decode_func = decode_root;
1692
b3e22b23
PB		 1693 s->has_modrm = false;
1694
1695 next_byte:
1696 if (first) {
1697 first = false;
1698 } else {
1699 b = x86_ldub_code(env, s);
1700 }
1701 /* Collect prefixes. */
1702 switch (b) {
1703 case 0xf3:
1704 s->prefix |= PREFIX_REPZ;
1705 s->prefix &= ~PREFIX_REPNZ;
1706 goto next_byte;
1707 case 0xf2:
1708 s->prefix |= PREFIX_REPNZ;
1709 s->prefix &= ~PREFIX_REPZ;
1710 goto next_byte;
1711 case 0xf0:
1712 s->prefix |= PREFIX_LOCK;
1713 goto next_byte;
1714 case 0x2e:
1715 s->override = R_CS;
1716 goto next_byte;
1717 case 0x36:
1718 s->override = R_SS;
1719 goto next_byte;
1720 case 0x3e:
1721 s->override = R_DS;
1722 goto next_byte;
1723 case 0x26:
1724 s->override = R_ES;
1725 goto next_byte;
1726 case 0x64:
1727 s->override = R_FS;
1728 goto next_byte;
1729 case 0x65:
1730 s->override = R_GS;
1731 goto next_byte;
1732 case 0x66:
1733 s->prefix |= PREFIX_DATA;
1734 goto next_byte;
1735 case 0x67:
1736 s->prefix |= PREFIX_ADR;
1737 goto next_byte;
1738#ifdef TARGET_X86_64
1739 case 0x40 ... 0x4f:
1740 if (CODE64(s)) {
1741 /* REX prefix */
1742 s->prefix |= PREFIX_REX;
1743 s->vex_w = (b >> 3) & 1;
1744 s->rex_r = (b & 0x4) << 1;
1745 s->rex_x = (b & 0x2) << 2;
1746 s->rex_b = (b & 0x1) << 3;
1747 goto next_byte;
1748 }
1749 break;
1750#endif
1751 case 0xc5: /* 2-byte VEX */
1752 case 0xc4: /* 3-byte VEX */
1753 /*
1754 * VEX prefixes cannot be used except in 32-bit mode.
1755 * Otherwise the instruction is LES or LDS.
1756 */
1757 if (CODE32(s) && !VM86(s)) {
1758 static const int pp_prefix[4] = {
1759 0, PREFIX_DATA, PREFIX_REPZ, PREFIX_REPNZ
1760 };
1761 int vex3, vex2 = x86_ldub_code(env, s);
1762
1763 if (!CODE64(s) && (vex2 & 0xc0) != 0xc0) {
1764 /*
1765 * 4.1.4.6: In 32-bit mode, bits [7:6] must be 11b,
1766 * otherwise the instruction is LES or LDS.
1767 */
1768 s->pc--; /* rewind the advance_pc() x86_ldub_code() did */
1769 break;
1770 }
1771
1772 /* 4.1.1-4.1.3: No preceding lock, 66, f2, f3, or rex prefixes. */
1773 if (s->prefix & (PREFIX_REPZ | PREFIX_REPNZ
1774 | PREFIX_LOCK | PREFIX_DATA | PREFIX_REX)) {
1775 goto illegal_op;
1776 }
1777#ifdef TARGET_X86_64
1778 s->rex_r = (~vex2 >> 4) & 8;
1779#endif
1780 if (b == 0xc5) {
1781 /* 2-byte VEX prefix: RVVVVlpp, implied 0f leading opcode byte */
1782 vex3 = vex2;
1783 decode_func = decode_0F;
1784 } else {
1785 /* 3-byte VEX prefix: RXBmmmmm wVVVVlpp */
1786 vex3 = x86_ldub_code(env, s);
1787#ifdef TARGET_X86_64
1788 s->rex_x = (~vex2 >> 3) & 8;
1789 s->rex_b = (~vex2 >> 2) & 8;
1790#endif
1791 s->vex_w = (vex3 >> 7) & 1;
1792 switch (vex2 & 0x1f) {
1793 case 0x01: /* Implied 0f leading opcode bytes. */
1794 decode_func = decode_0F;
1795 break;
1796 case 0x02: /* Implied 0f 38 leading opcode bytes. */
1797 decode_func = decode_0F38;
1798 break;
1799 case 0x03: /* Implied 0f 3a leading opcode bytes. */
1800 decode_func = decode_0F3A;
1801 break;
1802 default: /* Reserved for future use. */
1803 goto unknown_op;
1804 }
1805 }
1806 s->vex_v = (~vex3 >> 3) & 0xf;
1807 s->vex_l = (vex3 >> 2) & 1;
1808 s->prefix |= pp_prefix[vex3 & 3] | PREFIX_VEX;
1809 }
1810 break;
1811 default:
1812 if (b >= 0x100) {
1813 b -= 0x100;
1814 decode_func = do_decode_0F;
1815 }
1816 break;
1817 }
1818
1819 /* Post-process prefixes. */
1820 if (CODE64(s)) {
1821 /*
1822 * In 64-bit mode, the default data size is 32-bit. Select 64-bit
1823 * data with rex_w, and 16-bit data with 0x66; rex_w takes precedence
1824 * over 0x66 if both are present.
1825 */
1826 s->dflag = (REX_W(s) ? MO_64 : s->prefix & PREFIX_DATA ? MO_16 : MO_32);
1827 /* In 64-bit mode, 0x67 selects 32-bit addressing. */
1828 s->aflag = (s->prefix & PREFIX_ADR ? MO_32 : MO_64);
1829 } else {
1830 /* In 16/32-bit mode, 0x66 selects the opposite data size. */
1831 if (CODE32(s) ^ ((s->prefix & PREFIX_DATA) != 0)) {
1832 s->dflag = MO_32;
1833 } else {
1834 s->dflag = MO_16;
1835 }
1836 /* In 16/32-bit mode, 0x67 selects the opposite addressing. */
1837 if (CODE32(s) ^ ((s->prefix & PREFIX_ADR) != 0)) {
1838 s->aflag = MO_32;
1839 } else {
1840 s->aflag = MO_16;
1841 }
1842 }
1843
1844 memset(&decode, 0, sizeof(decode));
1845 decode.b = b;
1846 if (!decode_insn(s, env, decode_func, &decode)) {
1847 goto illegal_op;
1848 }
1849 if (!decode.e.gen) {
1850 goto unknown_op;
1851 }
1852
caa01fad
PB		 1853 if (!has_cpuid_feature(s, decode.e.cpuid)) {
1854 goto illegal_op;
1855 }
1856
183e6679
PB		 1857 /* Checks that result in #UD come first. */
1858 if (decode.e.check) {
1859 if (decode.e.check & X86_CHECK_i64) {
1860 if (CODE64(s)) {
1861 goto illegal_op;
1862 }
1863 }
1864 if (decode.e.check & X86_CHECK_o64) {
1865 if (!CODE64(s)) {
1866 goto illegal_op;
1867 }
1868 }
1869 if (decode.e.check & X86_CHECK_prot) {
1870 if (!PE(s) || VM86(s)) {
1871 goto illegal_op;
1872 }
1873 }
1874 }
1875
b3e22b23
PB		 1876 switch (decode.e.special) {
1877 case X86_SPECIAL_None:
1878 break;
1879
1880 case X86_SPECIAL_Locked:
1881 if (decode.op[0].has_ea) {
1882 s->prefix |= PREFIX_LOCK;
1883 }
1884 break;
1885
b3e22b23
PB		 1886 case X86_SPECIAL_ZExtOp0:
1887 assert(decode.op[0].unit == X86_OP_INT);
1888 if (!decode.op[0].has_ea) {
1889 decode.op[0].ot = MO_32;
1890 }
1891 break;
1892
1893 case X86_SPECIAL_ZExtOp2:
1894 assert(decode.op[2].unit == X86_OP_INT);
1895 if (!decode.op[2].has_ea) {
1896 decode.op[2].ot = MO_32;
1897 }
1898 break;
1899
16fc5726
PB		 1900 case X86_SPECIAL_AVXExtMov:
1901 if (!decode.op[2].has_ea) {
1902 decode.op[2].ot = s->vex_l ? MO_256 : MO_128;
1903 } else if (s->vex_l) {
1904 decode.op[2].ot++;
1905 }
1906 break;
1907
b2ea6450 1908 default:
b3e22b23
PB		 1909 break;
1910 }
1911
20581aad
PB		 1912 if (!validate_vex(s, &decode)) {
1913 return;
1914 }
183e6679
PB		 1915
1916 /*
1917 * Checks that result in #GP or VMEXIT come second. Intercepts are
1918 * generally checked after non-memory exceptions (i.e. before all
1919 * exceptions if there is no memory operand). Exceptions are
1920 * vm86 checks (INTn, IRET, PUSHF/POPF), RSM and XSETBV (!).
1921 *
1922 * RSM and XSETBV will be handled in the gen_* functions
1923 * instead of using chk().
1924 */
1925 if (decode.e.check & X86_CHECK_cpl0) {
1926 if (CPL(s) != 0) {
1927 goto gp_fault;
1928 }
1929 }
1930 if (decode.e.intercept && unlikely(GUEST(s))) {
1931 gen_helper_svm_check_intercept(tcg_env,
1932 tcg_constant_i32(decode.e.intercept));
1933 }
1934 if (decode.e.check) {
1935 if ((decode.e.check & X86_CHECK_vm86_iopl) && VM86(s)) {
1936 if (IOPL(s) < 3) {
1937 goto gp_fault;
1938 }
1939 } else if (decode.e.check & X86_CHECK_cpl_iopl) {
1940 if (IOPL(s) < CPL(s)) {
1941 goto gp_fault;
1942 }
1943 }
1944 }
1945
b2ea6450
MB		 1946 if (decode.e.special == X86_SPECIAL_MMX &&
1947 !(s->prefix & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))) {
ad75a51e 1948 gen_helper_enter_mmx(tcg_env);
b2ea6450
MB		 1949 }
1950
b3e22b23 1951 if (decode.op[0].has_ea || decode.op[1].has_ea || decode.op[2].has_ea) {
20581aad 1952 gen_load_ea(s, &decode.mem, decode.e.vex_class == 12);
b3e22b23 1953 }
6ba13999
PB		 1954 if (s->prefix & PREFIX_LOCK) {
1955 if (decode.op[0].unit != X86_OP_INT || !decode.op[0].has_ea) {
1956 goto illegal_op;
1957 }
1958 gen_load(s, &decode, 2, s->T1);
1959 decode.e.gen(s, env, &decode);
1960 } else {
1961 if (decode.op[0].unit == X86_OP_MMX) {
1962 compute_mmx_offset(&decode.op[0]);
1963 } else if (decode.op[0].unit == X86_OP_SSE) {
1964 compute_xmm_offset(&decode.op[0]);
1965 }
1966 gen_load(s, &decode, 1, s->T0);
1967 gen_load(s, &decode, 2, s->T1);
1968 decode.e.gen(s, env, &decode);
1969 gen_writeback(s, &decode, 0, s->T0);
1970 }
b3e22b23 1971 return;
183e6679
PB		 1972 gp_fault:
1973 gen_exception_gpf(s);
1974 return;
b3e22b23
PB		 1975 illegal_op:
1976 gen_illegal_opcode(s);
1977 return;
1978 unknown_op:
1979 gen_unknown_opcode(env, s);
1980}
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