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Merge tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu into...
[mirror_qemu.git] / target / i386 / tcg / seg_helper.c
CommitLineData
eaa728ee 1/*
10774999
BS		 2 * x86 segmentation related helpers:
3 * TSS, interrupts, system calls, jumps and call/task gates, descriptors
eaa728ee
FB		 4 *
5 * Copyright (c) 2003 Fabrice Bellard
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
d9ff33ad 10 * version 2.1 of the License, or (at your option) any later version.
eaa728ee
FB		 11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
8167ee88 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
eaa728ee 19 */
83dae095 20
b6a0aa05 21#include "qemu/osdep.h"
3e457172 22#include "cpu.h"
1de7afc9 23#include "qemu/log.h"
2ef6175a 24#include "exec/helper-proto.h"
63c91552 25#include "exec/exec-all.h"
f08b6170 26#include "exec/cpu_ldst.h"
508127e2 27#include "exec/log.h"
ed69e831 28#include "helper-tcg.h"
30493a03 29#include "seg_helper.h"
8a201bd4 30
50fcc7cb
GW		 31int get_pg_mode(CPUX86State *env)
32{
33 int pg_mode = 0;
34 if (!(env->cr[0] & CR0_PG_MASK)) {
35 return 0;
36 }
37 if (env->cr[0] & CR0_WP_MASK) {
38 pg_mode |= PG_MODE_WP;
39 }
40 if (env->cr[4] & CR4_PAE_MASK) {
41 pg_mode |= PG_MODE_PAE;
42 if (env->efer & MSR_EFER_NXE) {
43 pg_mode |= PG_MODE_NXE;
44 }
45 }
46 if (env->cr[4] & CR4_PSE_MASK) {
47 pg_mode |= PG_MODE_PSE;
48 }
49 if (env->cr[4] & CR4_SMEP_MASK) {
50 pg_mode |= PG_MODE_SMEP;
51 }
52 if (env->hflags & HF_LMA_MASK) {
53 pg_mode |= PG_MODE_LMA;
54 if (env->cr[4] & CR4_PKE_MASK) {
55 pg_mode |= PG_MODE_PKE;
56 }
57 if (env->cr[4] & CR4_PKS_MASK) {
58 pg_mode |= PG_MODE_PKS;
59 }
60 if (env->cr[4] & CR4_LA57_MASK) {
61 pg_mode |= PG_MODE_LA57;
62 }
63 }
64 return pg_mode;
65}
66
eaa728ee 67/* return non zero if error */
100ec099
PD		 68static inline int load_segment_ra(CPUX86State *env, uint32_t *e1_ptr,
69 uint32_t *e2_ptr, int selector,
70 uintptr_t retaddr)
eaa728ee
FB		 71{
72 SegmentCache *dt;
73 int index;
74 target_ulong ptr;
75
20054ef0 76 if (selector & 0x4) {
eaa728ee 77 dt = &env->ldt;
20054ef0 78 } else {
eaa728ee 79 dt = &env->gdt;
20054ef0 80 }
eaa728ee 81 index = selector & ~7;
20054ef0 82 if ((index + 7) > dt->limit) {
eaa728ee 83 return -1;
20054ef0 84 }
eaa728ee 85 ptr = dt->base + index;
100ec099
PD		 86 *e1_ptr = cpu_ldl_kernel_ra(env, ptr, retaddr);
87 *e2_ptr = cpu_ldl_kernel_ra(env, ptr + 4, retaddr);
eaa728ee
FB		 88 return 0;
89}
90
100ec099
PD		 91static inline int load_segment(CPUX86State *env, uint32_t *e1_ptr,
92 uint32_t *e2_ptr, int selector)
93{
94 return load_segment_ra(env, e1_ptr, e2_ptr, selector, 0);
95}
96
eaa728ee
FB		 97static inline unsigned int get_seg_limit(uint32_t e1, uint32_t e2)
98{
99 unsigned int limit;
20054ef0 100
eaa728ee 101 limit = (e1 & 0xffff) | (e2 & 0x000f0000);
20054ef0 102 if (e2 & DESC_G_MASK) {
eaa728ee 103 limit = (limit << 12) | 0xfff;
20054ef0 104 }
eaa728ee
FB		 105 return limit;
106}
107
108static inline uint32_t get_seg_base(uint32_t e1, uint32_t e2)
109{
20054ef0 110 return (e1 >> 16) | ((e2 & 0xff) << 16) | (e2 & 0xff000000);
eaa728ee
FB		 111}
112
20054ef0
BS		 113static inline void load_seg_cache_raw_dt(SegmentCache *sc, uint32_t e1,
114 uint32_t e2)
eaa728ee
FB		 115{
116 sc->base = get_seg_base(e1, e2);
117 sc->limit = get_seg_limit(e1, e2);
118 sc->flags = e2;
119}
120
121/* init the segment cache in vm86 mode. */
2999a0b2 122static inline void load_seg_vm(CPUX86State *env, int seg, int selector)
eaa728ee
FB		 123{
124 selector &= 0xffff;
b98dbc90
PB		 125
126 cpu_x86_load_seg_cache(env, seg, selector, (selector << 4), 0xffff,
127 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
128 DESC_A_MASK | (3 << DESC_DPL_SHIFT));
eaa728ee
FB		 129}
130
2999a0b2 131static inline void get_ss_esp_from_tss(CPUX86State *env, uint32_t *ss_ptr,
100ec099
PD		 132 uint32_t *esp_ptr, int dpl,
133 uintptr_t retaddr)
eaa728ee 134{
6aa9e42f 135 X86CPU *cpu = env_archcpu(env);
eaa728ee
FB		 136 int type, index, shift;
137
138#if 0
139 {
140 int i;
141 printf("TR: base=%p limit=%x\n", env->tr.base, env->tr.limit);
20054ef0 142 for (i = 0; i < env->tr.limit; i++) {
eaa728ee 143 printf("%02x ", env->tr.base[i]);
20054ef0
BS		 144 if ((i & 7) == 7) {
145 printf("\n");
146 }
eaa728ee
FB		 147 }
148 printf("\n");
149 }
150#endif
151
20054ef0 152 if (!(env->tr.flags & DESC_P_MASK)) {
a47dddd7 153 cpu_abort(CPU(cpu), "invalid tss");
20054ef0 154 }
eaa728ee 155 type = (env->tr.flags >> DESC_TYPE_SHIFT) & 0xf;
20054ef0 156 if ((type & 7) != 1) {
a47dddd7 157 cpu_abort(CPU(cpu), "invalid tss type");
20054ef0 158 }
eaa728ee
FB		 159 shift = type >> 3;
160 index = (dpl * 4 + 2) << shift;
20054ef0 161 if (index + (4 << shift) - 1 > env->tr.limit) {
100ec099 162 raise_exception_err_ra(env, EXCP0A_TSS, env->tr.selector & 0xfffc, retaddr);
20054ef0 163 }
eaa728ee 164 if (shift == 0) {
100ec099
PD		 165 *esp_ptr = cpu_lduw_kernel_ra(env, env->tr.base + index, retaddr);
166 *ss_ptr = cpu_lduw_kernel_ra(env, env->tr.base + index + 2, retaddr);
eaa728ee 167 } else {
100ec099
PD		 168 *esp_ptr = cpu_ldl_kernel_ra(env, env->tr.base + index, retaddr);
169 *ss_ptr = cpu_lduw_kernel_ra(env, env->tr.base + index + 4, retaddr);
eaa728ee
FB		 170 }
171}
172
c117e5b1
PMD		 173static void tss_load_seg(CPUX86State *env, X86Seg seg_reg, int selector,
174 int cpl, uintptr_t retaddr)
eaa728ee
FB		 175{
176 uint32_t e1, e2;
d3b54918 177 int rpl, dpl;
eaa728ee
FB		 178
179 if ((selector & 0xfffc) != 0) {
100ec099
PD		 180 if (load_segment_ra(env, &e1, &e2, selector, retaddr) != 0) {
181 raise_exception_err_ra(env, EXCP0A_TSS, selector & 0xfffc, retaddr);
20054ef0
BS		 182 }
183 if (!(e2 & DESC_S_MASK)) {
100ec099 184 raise_exception_err_ra(env, EXCP0A_TSS, selector & 0xfffc, retaddr);
20054ef0 185 }
eaa728ee
FB		 186 rpl = selector & 3;
187 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
eaa728ee 188 if (seg_reg == R_CS) {
20054ef0 189 if (!(e2 & DESC_CS_MASK)) {
100ec099 190 raise_exception_err_ra(env, EXCP0A_TSS, selector & 0xfffc, retaddr);
20054ef0 191 }
20054ef0 192 if (dpl != rpl) {
100ec099 193 raise_exception_err_ra(env, EXCP0A_TSS, selector & 0xfffc, retaddr);
20054ef0 194 }
eaa728ee
FB		 195 } else if (seg_reg == R_SS) {
196 /* SS must be writable data */
20054ef0 197 if ((e2 & DESC_CS_MASK) || !(e2 & DESC_W_MASK)) {
100ec099 198 raise_exception_err_ra(env, EXCP0A_TSS, selector & 0xfffc, retaddr);
20054ef0
BS		 199 }
200 if (dpl != cpl || dpl != rpl) {
100ec099 201 raise_exception_err_ra(env, EXCP0A_TSS, selector & 0xfffc, retaddr);
20054ef0 202 }
eaa728ee
FB		 203 } else {
204 /* not readable code */
20054ef0 205 if ((e2 & DESC_CS_MASK) && !(e2 & DESC_R_MASK)) {
100ec099 206 raise_exception_err_ra(env, EXCP0A_TSS, selector & 0xfffc, retaddr);
20054ef0 207 }
eaa728ee
FB		 208 /* if data or non conforming code, checks the rights */
209 if (((e2 >> DESC_TYPE_SHIFT) & 0xf) < 12) {
20054ef0 210 if (dpl < cpl || dpl < rpl) {
100ec099 211 raise_exception_err_ra(env, EXCP0A_TSS, selector & 0xfffc, retaddr);
20054ef0 212 }
eaa728ee
FB		 213 }
214 }
20054ef0 215 if (!(e2 & DESC_P_MASK)) {
100ec099 216 raise_exception_err_ra(env, EXCP0B_NOSEG, selector & 0xfffc, retaddr);
20054ef0 217 }
eaa728ee 218 cpu_x86_load_seg_cache(env, seg_reg, selector,
20054ef0
BS		 219 get_seg_base(e1, e2),
220 get_seg_limit(e1, e2),
221 e2);
eaa728ee 222 } else {
20054ef0 223 if (seg_reg == R_SS || seg_reg == R_CS) {
100ec099 224 raise_exception_err_ra(env, EXCP0A_TSS, selector & 0xfffc, retaddr);
20054ef0 225 }
eaa728ee
FB		 226 }
227}
228
229#define SWITCH_TSS_JMP 0
230#define SWITCH_TSS_IRET 1
231#define SWITCH_TSS_CALL 2
232
233/* XXX: restore CPU state in registers (PowerPC case) */
100ec099
PD		 234static void switch_tss_ra(CPUX86State *env, int tss_selector,
235 uint32_t e1, uint32_t e2, int source,
236 uint32_t next_eip, uintptr_t retaddr)
eaa728ee
FB		 237{
238 int tss_limit, tss_limit_max, type, old_tss_limit_max, old_type, v1, v2, i;
239 target_ulong tss_base;
240 uint32_t new_regs[8], new_segs[6];
241 uint32_t new_eflags, new_eip, new_cr3, new_ldt, new_trap;
242 uint32_t old_eflags, eflags_mask;
243 SegmentCache *dt;
244 int index;
245 target_ulong ptr;
246
247 type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
20054ef0
BS		 248 LOG_PCALL("switch_tss: sel=0x%04x type=%d src=%d\n", tss_selector, type,
249 source);
eaa728ee
FB		 250
251 /* if task gate, we read the TSS segment and we load it */
252 if (type == 5) {
20054ef0 253 if (!(e2 & DESC_P_MASK)) {
100ec099 254 raise_exception_err_ra(env, EXCP0B_NOSEG, tss_selector & 0xfffc, retaddr);
20054ef0 255 }
eaa728ee 256 tss_selector = e1 >> 16;
20054ef0 257 if (tss_selector & 4) {
100ec099 258 raise_exception_err_ra(env, EXCP0A_TSS, tss_selector & 0xfffc, retaddr);
20054ef0 259 }
100ec099
PD		 260 if (load_segment_ra(env, &e1, &e2, tss_selector, retaddr) != 0) {
261 raise_exception_err_ra(env, EXCP0D_GPF, tss_selector & 0xfffc, retaddr);
20054ef0
BS		 262 }
263 if (e2 & DESC_S_MASK) {
100ec099 264 raise_exception_err_ra(env, EXCP0D_GPF, tss_selector & 0xfffc, retaddr);
20054ef0 265 }
eaa728ee 266 type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
20054ef0 267 if ((type & 7) != 1) {
100ec099 268 raise_exception_err_ra(env, EXCP0D_GPF, tss_selector & 0xfffc, retaddr);
20054ef0 269 }
eaa728ee
FB		 270 }
271
20054ef0 272 if (!(e2 & DESC_P_MASK)) {
100ec099 273 raise_exception_err_ra(env, EXCP0B_NOSEG, tss_selector & 0xfffc, retaddr);
20054ef0 274 }
eaa728ee 275
20054ef0 276 if (type & 8) {
eaa728ee 277 tss_limit_max = 103;
20054ef0 278 } else {
eaa728ee 279 tss_limit_max = 43;
20054ef0 280 }
eaa728ee
FB		 281 tss_limit = get_seg_limit(e1, e2);
282 tss_base = get_seg_base(e1, e2);
283 if ((tss_selector & 4) != 0 ||
20054ef0 284 tss_limit < tss_limit_max) {
100ec099 285 raise_exception_err_ra(env, EXCP0A_TSS, tss_selector & 0xfffc, retaddr);
20054ef0 286 }
eaa728ee 287 old_type = (env->tr.flags >> DESC_TYPE_SHIFT) & 0xf;
20054ef0 288 if (old_type & 8) {
eaa728ee 289 old_tss_limit_max = 103;
20054ef0 290 } else {
eaa728ee 291 old_tss_limit_max = 43;
20054ef0 292 }
eaa728ee
FB		 293
294 /* read all the registers from the new TSS */
295 if (type & 8) {
296 /* 32 bit */
100ec099
PD		 297 new_cr3 = cpu_ldl_kernel_ra(env, tss_base + 0x1c, retaddr);
298 new_eip = cpu_ldl_kernel_ra(env, tss_base + 0x20, retaddr);
299 new_eflags = cpu_ldl_kernel_ra(env, tss_base + 0x24, retaddr);
20054ef0 300 for (i = 0; i < 8; i++) {
100ec099
PD		 301 new_regs[i] = cpu_ldl_kernel_ra(env, tss_base + (0x28 + i * 4),
302 retaddr);
20054ef0
BS		 303 }
304 for (i = 0; i < 6; i++) {
100ec099
PD		 305 new_segs[i] = cpu_lduw_kernel_ra(env, tss_base + (0x48 + i * 4),
306 retaddr);
20054ef0 307 }
100ec099
PD		 308 new_ldt = cpu_lduw_kernel_ra(env, tss_base + 0x60, retaddr);
309 new_trap = cpu_ldl_kernel_ra(env, tss_base + 0x64, retaddr);
eaa728ee
FB		 310 } else {
311 /* 16 bit */
312 new_cr3 = 0;
100ec099
PD		 313 new_eip = cpu_lduw_kernel_ra(env, tss_base + 0x0e, retaddr);
314 new_eflags = cpu_lduw_kernel_ra(env, tss_base + 0x10, retaddr);
20054ef0 315 for (i = 0; i < 8; i++) {
a5505f6b 316 new_regs[i] = cpu_lduw_kernel_ra(env, tss_base + (0x12 + i * 2), retaddr);
20054ef0
BS		 317 }
318 for (i = 0; i < 4; i++) {
28f6aa11 319 new_segs[i] = cpu_lduw_kernel_ra(env, tss_base + (0x22 + i * 2),
100ec099 320 retaddr);
20054ef0 321 }
100ec099 322 new_ldt = cpu_lduw_kernel_ra(env, tss_base + 0x2a, retaddr);
eaa728ee
FB		 323 new_segs[R_FS] = 0;
324 new_segs[R_GS] = 0;
325 new_trap = 0;
326 }
4581cbcd
BS		 327 /* XXX: avoid a compiler warning, see
328 http://support.amd.com/us/Processor_TechDocs/24593.pdf
329 chapters 12.2.5 and 13.2.4 on how to implement TSS Trap bit */
330 (void)new_trap;
eaa728ee
FB		 331
332 /* NOTE: we must avoid memory exceptions during the task switch,
333 so we make dummy accesses before */
334 /* XXX: it can still fail in some cases, so a bigger hack is
335 necessary to valid the TLB after having done the accesses */
336
100ec099
PD		 337 v1 = cpu_ldub_kernel_ra(env, env->tr.base, retaddr);
338 v2 = cpu_ldub_kernel_ra(env, env->tr.base + old_tss_limit_max, retaddr);
339 cpu_stb_kernel_ra(env, env->tr.base, v1, retaddr);
340 cpu_stb_kernel_ra(env, env->tr.base + old_tss_limit_max, v2, retaddr);
eaa728ee
FB		 341
342 /* clear busy bit (it is restartable) */
343 if (source == SWITCH_TSS_JMP || source == SWITCH_TSS_IRET) {
344 target_ulong ptr;
345 uint32_t e2;
20054ef0 346
eaa728ee 347 ptr = env->gdt.base + (env->tr.selector & ~7);
100ec099 348 e2 = cpu_ldl_kernel_ra(env, ptr + 4, retaddr);
eaa728ee 349 e2 &= ~DESC_TSS_BUSY_MASK;
100ec099 350 cpu_stl_kernel_ra(env, ptr + 4, e2, retaddr);
eaa728ee 351 }
997ff0d9 352 old_eflags = cpu_compute_eflags(env);
20054ef0 353 if (source == SWITCH_TSS_IRET) {
eaa728ee 354 old_eflags &= ~NT_MASK;
20054ef0 355 }
eaa728ee
FB		 356
357 /* save the current state in the old TSS */
1b627f38 358 if (old_type & 8) {
eaa728ee 359 /* 32 bit */
100ec099
PD		 360 cpu_stl_kernel_ra(env, env->tr.base + 0x20, next_eip, retaddr);
361 cpu_stl_kernel_ra(env, env->tr.base + 0x24, old_eflags, retaddr);
362 cpu_stl_kernel_ra(env, env->tr.base + (0x28 + 0 * 4), env->regs[R_EAX], retaddr);
363 cpu_stl_kernel_ra(env, env->tr.base + (0x28 + 1 * 4), env->regs[R_ECX], retaddr);
364 cpu_stl_kernel_ra(env, env->tr.base + (0x28 + 2 * 4), env->regs[R_EDX], retaddr);
365 cpu_stl_kernel_ra(env, env->tr.base + (0x28 + 3 * 4), env->regs[R_EBX], retaddr);
366 cpu_stl_kernel_ra(env, env->tr.base + (0x28 + 4 * 4), env->regs[R_ESP], retaddr);
367 cpu_stl_kernel_ra(env, env->tr.base + (0x28 + 5 * 4), env->regs[R_EBP], retaddr);
368 cpu_stl_kernel_ra(env, env->tr.base + (0x28 + 6 * 4), env->regs[R_ESI], retaddr);
369 cpu_stl_kernel_ra(env, env->tr.base + (0x28 + 7 * 4), env->regs[R_EDI], retaddr);
20054ef0 370 for (i = 0; i < 6; i++) {
100ec099
PD		 371 cpu_stw_kernel_ra(env, env->tr.base + (0x48 + i * 4),
372 env->segs[i].selector, retaddr);
20054ef0 373 }
eaa728ee
FB		 374 } else {
375 /* 16 bit */
100ec099
PD		 376 cpu_stw_kernel_ra(env, env->tr.base + 0x0e, next_eip, retaddr);
377 cpu_stw_kernel_ra(env, env->tr.base + 0x10, old_eflags, retaddr);
378 cpu_stw_kernel_ra(env, env->tr.base + (0x12 + 0 * 2), env->regs[R_EAX], retaddr);
379 cpu_stw_kernel_ra(env, env->tr.base + (0x12 + 1 * 2), env->regs[R_ECX], retaddr);
380 cpu_stw_kernel_ra(env, env->tr.base + (0x12 + 2 * 2), env->regs[R_EDX], retaddr);
381 cpu_stw_kernel_ra(env, env->tr.base + (0x12 + 3 * 2), env->regs[R_EBX], retaddr);
382 cpu_stw_kernel_ra(env, env->tr.base + (0x12 + 4 * 2), env->regs[R_ESP], retaddr);
383 cpu_stw_kernel_ra(env, env->tr.base + (0x12 + 5 * 2), env->regs[R_EBP], retaddr);
384 cpu_stw_kernel_ra(env, env->tr.base + (0x12 + 6 * 2), env->regs[R_ESI], retaddr);
385 cpu_stw_kernel_ra(env, env->tr.base + (0x12 + 7 * 2), env->regs[R_EDI], retaddr);
20054ef0 386 for (i = 0; i < 4; i++) {
28f6aa11 387 cpu_stw_kernel_ra(env, env->tr.base + (0x22 + i * 2),
100ec099 388 env->segs[i].selector, retaddr);
20054ef0 389 }
eaa728ee
FB		 390 }
391
392 /* now if an exception occurs, it will occurs in the next task
393 context */
394
395 if (source == SWITCH_TSS_CALL) {
100ec099 396 cpu_stw_kernel_ra(env, tss_base, env->tr.selector, retaddr);
eaa728ee
FB		 397 new_eflags |= NT_MASK;
398 }
399
400 /* set busy bit */
401 if (source == SWITCH_TSS_JMP || source == SWITCH_TSS_CALL) {
402 target_ulong ptr;
403 uint32_t e2;
20054ef0 404
eaa728ee 405 ptr = env->gdt.base + (tss_selector & ~7);
100ec099 406 e2 = cpu_ldl_kernel_ra(env, ptr + 4, retaddr);
eaa728ee 407 e2 |= DESC_TSS_BUSY_MASK;
100ec099 408 cpu_stl_kernel_ra(env, ptr + 4, e2, retaddr);
eaa728ee
FB		 409 }
410
411 /* set the new CPU state */
412 /* from this point, any exception which occurs can give problems */
413 env->cr[0] |= CR0_TS_MASK;
414 env->hflags |= HF_TS_MASK;
415 env->tr.selector = tss_selector;
416 env->tr.base = tss_base;
417 env->tr.limit = tss_limit;
418 env->tr.flags = e2 & ~DESC_TSS_BUSY_MASK;
419
420 if ((type & 8) && (env->cr[0] & CR0_PG_MASK)) {
421 cpu_x86_update_cr3(env, new_cr3);
422 }
423
424 /* load all registers without an exception, then reload them with
425 possible exception */
426 env->eip = new_eip;
427 eflags_mask = TF_MASK | AC_MASK | ID_MASK |
428 IF_MASK | IOPL_MASK | VM_MASK | RF_MASK | NT_MASK;
a5505f6b
PB		 429 if (type & 8) {
430 cpu_load_eflags(env, new_eflags, eflags_mask);
431 for (i = 0; i < 8; i++) {
432 env->regs[i] = new_regs[i];
433 }
434 } else {
435 cpu_load_eflags(env, new_eflags, eflags_mask & 0xffff);
436 for (i = 0; i < 8; i++) {
437 env->regs[i] = (env->regs[i] & 0xffff0000) | new_regs[i];
438 }
20054ef0 439 }
eaa728ee 440 if (new_eflags & VM_MASK) {
20054ef0 441 for (i = 0; i < 6; i++) {
2999a0b2 442 load_seg_vm(env, i, new_segs[i]);
20054ef0 443 }
eaa728ee 444 } else {
eaa728ee 445 /* first just selectors as the rest may trigger exceptions */
20054ef0 446 for (i = 0; i < 6; i++) {
eaa728ee 447 cpu_x86_load_seg_cache(env, i, new_segs[i], 0, 0, 0);
20054ef0 448 }
eaa728ee
FB		 449 }
450
451 env->ldt.selector = new_ldt & ~4;
452 env->ldt.base = 0;
453 env->ldt.limit = 0;
454 env->ldt.flags = 0;
455
456 /* load the LDT */
20054ef0 457 if (new_ldt & 4) {
100ec099 458 raise_exception_err_ra(env, EXCP0A_TSS, new_ldt & 0xfffc, retaddr);
20054ef0 459 }
eaa728ee
FB		 460
461 if ((new_ldt & 0xfffc) != 0) {
462 dt = &env->gdt;
463 index = new_ldt & ~7;
20054ef0 464 if ((index + 7) > dt->limit) {
100ec099 465 raise_exception_err_ra(env, EXCP0A_TSS, new_ldt & 0xfffc, retaddr);
20054ef0 466 }
eaa728ee 467 ptr = dt->base + index;
100ec099
PD		 468 e1 = cpu_ldl_kernel_ra(env, ptr, retaddr);
469 e2 = cpu_ldl_kernel_ra(env, ptr + 4, retaddr);
20054ef0 470 if ((e2 & DESC_S_MASK) || ((e2 >> DESC_TYPE_SHIFT) & 0xf) != 2) {
100ec099 471 raise_exception_err_ra(env, EXCP0A_TSS, new_ldt & 0xfffc, retaddr);
20054ef0
BS		 472 }
473 if (!(e2 & DESC_P_MASK)) {
100ec099 474 raise_exception_err_ra(env, EXCP0A_TSS, new_ldt & 0xfffc, retaddr);
20054ef0 475 }
eaa728ee
FB		 476 load_seg_cache_raw_dt(&env->ldt, e1, e2);
477 }
478
479 /* load the segments */
480 if (!(new_eflags & VM_MASK)) {
d3b54918 481 int cpl = new_segs[R_CS] & 3;
100ec099
PD		 482 tss_load_seg(env, R_CS, new_segs[R_CS], cpl, retaddr);
483 tss_load_seg(env, R_SS, new_segs[R_SS], cpl, retaddr);
484 tss_load_seg(env, R_ES, new_segs[R_ES], cpl, retaddr);
485 tss_load_seg(env, R_DS, new_segs[R_DS], cpl, retaddr);
486 tss_load_seg(env, R_FS, new_segs[R_FS], cpl, retaddr);
487 tss_load_seg(env, R_GS, new_segs[R_GS], cpl, retaddr);
eaa728ee
FB		 488 }
489
a78d0eab 490 /* check that env->eip is in the CS segment limits */
eaa728ee 491 if (new_eip > env->segs[R_CS].limit) {
20054ef0 492 /* XXX: different exception if CALL? */
100ec099 493 raise_exception_err_ra(env, EXCP0D_GPF, 0, retaddr);
eaa728ee 494 }
01df040b
AL		 495
496#ifndef CONFIG_USER_ONLY
497 /* reset local breakpoints */
428065ce 498 if (env->dr[7] & DR7_LOCAL_BP_MASK) {
93d00d0f 499 cpu_x86_update_dr7(env, env->dr[7] & ~DR7_LOCAL_BP_MASK);
01df040b
AL		 500 }
501#endif
eaa728ee
FB		 502}
503
100ec099
PD		 504static void switch_tss(CPUX86State *env, int tss_selector,
505 uint32_t e1, uint32_t e2, int source,
506 uint32_t next_eip)
507{
508 switch_tss_ra(env, tss_selector, e1, e2, source, next_eip, 0);
509}
510
eaa728ee
FB		 511static inline unsigned int get_sp_mask(unsigned int e2)
512{
0aca0605
AO		 513#ifdef TARGET_X86_64
514 if (e2 & DESC_L_MASK) {
515 return 0;
516 } else
517#endif
20054ef0 518 if (e2 & DESC_B_MASK) {
eaa728ee 519 return 0xffffffff;
20054ef0 520 } else {
eaa728ee 521 return 0xffff;
20054ef0 522 }
eaa728ee
FB		 523}
524
30493a03 525int exception_has_error_code(int intno)
2ed51f5b 526{
20054ef0
BS		 527 switch (intno) {
528 case 8:
529 case 10:
530 case 11:
531 case 12:
532 case 13:
533 case 14:
534 case 17:
535 return 1;
536 }
537 return 0;
2ed51f5b
AL		 538}
539
eaa728ee 540#ifdef TARGET_X86_64
08b3ded6
LG		 541#define SET_ESP(val, sp_mask) \
542 do { \
543 if ((sp_mask) == 0xffff) { \
544 env->regs[R_ESP] = (env->regs[R_ESP] & ~0xffff) | \
545 ((val) & 0xffff); \
546 } else if ((sp_mask) == 0xffffffffLL) { \
547 env->regs[R_ESP] = (uint32_t)(val); \
548 } else { \
549 env->regs[R_ESP] = (val); \
550 } \
20054ef0 551 } while (0)
eaa728ee 552#else
08b3ded6
LG		 553#define SET_ESP(val, sp_mask) \
554 do { \
555 env->regs[R_ESP] = (env->regs[R_ESP] & ~(sp_mask)) | \
556 ((val) & (sp_mask)); \
20054ef0 557 } while (0)
eaa728ee
FB		 558#endif
559
c0a04f0e
AL		 560/* in 64-bit machines, this can overflow. So this segment addition macro
561 * can be used to trim the value to 32-bit whenever needed */
562#define SEG_ADDL(ssp, sp, sp_mask) ((uint32_t)((ssp) + (sp & (sp_mask))))
563
eaa728ee 564/* XXX: add a is_user flag to have proper security support */
100ec099 565#define PUSHW_RA(ssp, sp, sp_mask, val, ra) \
329e607d
BS		 566 { \
567 sp -= 2; \
100ec099 568 cpu_stw_kernel_ra(env, (ssp) + (sp & (sp_mask)), (val), ra); \
20054ef0 569 }
eaa728ee 570
100ec099 571#define PUSHL_RA(ssp, sp, sp_mask, val, ra) \
20054ef0
BS		 572 { \
573 sp -= 4; \
100ec099 574 cpu_stl_kernel_ra(env, SEG_ADDL(ssp, sp, sp_mask), (uint32_t)(val), ra); \
20054ef0 575 }
eaa728ee 576
100ec099 577#define POPW_RA(ssp, sp, sp_mask, val, ra) \
329e607d 578 { \
100ec099 579 val = cpu_lduw_kernel_ra(env, (ssp) + (sp & (sp_mask)), ra); \
329e607d 580 sp += 2; \
20054ef0 581 }
eaa728ee 582
100ec099 583#define POPL_RA(ssp, sp, sp_mask, val, ra) \
329e607d 584 { \
100ec099 585 val = (uint32_t)cpu_ldl_kernel_ra(env, SEG_ADDL(ssp, sp, sp_mask), ra); \
329e607d 586 sp += 4; \
20054ef0 587 }
eaa728ee 588
100ec099
PD		 589#define PUSHW(ssp, sp, sp_mask, val) PUSHW_RA(ssp, sp, sp_mask, val, 0)
590#define PUSHL(ssp, sp, sp_mask, val) PUSHL_RA(ssp, sp, sp_mask, val, 0)
591#define POPW(ssp, sp, sp_mask, val) POPW_RA(ssp, sp, sp_mask, val, 0)
592#define POPL(ssp, sp, sp_mask, val) POPL_RA(ssp, sp, sp_mask, val, 0)
593
eaa728ee 594/* protected mode interrupt */
2999a0b2
BS		 595static void do_interrupt_protected(CPUX86State *env, int intno, int is_int,
596 int error_code, unsigned int next_eip,
597 int is_hw)
eaa728ee
FB		 598{
599 SegmentCache *dt;
600 target_ulong ptr, ssp;
601 int type, dpl, selector, ss_dpl, cpl;
602 int has_error_code, new_stack, shift;
1c918eba 603 uint32_t e1, e2, offset, ss = 0, esp, ss_e1 = 0, ss_e2 = 0;
eaa728ee 604 uint32_t old_eip, sp_mask;
87446327 605 int vm86 = env->eflags & VM_MASK;
eaa728ee 606
eaa728ee 607 has_error_code = 0;
20054ef0
BS		 608 if (!is_int && !is_hw) {
609 has_error_code = exception_has_error_code(intno);
610 }
611 if (is_int) {
eaa728ee 612 old_eip = next_eip;
20054ef0 613 } else {
eaa728ee 614 old_eip = env->eip;
20054ef0 615 }
eaa728ee
FB		 616
617 dt = &env->idt;
20054ef0 618 if (intno * 8 + 7 > dt->limit) {
77b2bc2c 619 raise_exception_err(env, EXCP0D_GPF, intno * 8 + 2);
20054ef0 620 }
eaa728ee 621 ptr = dt->base + intno * 8;
329e607d
BS		 622 e1 = cpu_ldl_kernel(env, ptr);
623 e2 = cpu_ldl_kernel(env, ptr + 4);
eaa728ee
FB		 624 /* check gate type */
625 type = (e2 >> DESC_TYPE_SHIFT) & 0x1f;
20054ef0 626 switch (type) {
eaa728ee 627 case 5: /* task gate */
3df1a3d0
PM		 628 case 6: /* 286 interrupt gate */
629 case 7: /* 286 trap gate */
630 case 14: /* 386 interrupt gate */
631 case 15: /* 386 trap gate */
632 break;
633 default:
634 raise_exception_err(env, EXCP0D_GPF, intno * 8 + 2);
635 break;
636 }
637 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
638 cpl = env->hflags & HF_CPL_MASK;
639 /* check privilege if software int */
640 if (is_int && dpl < cpl) {
641 raise_exception_err(env, EXCP0D_GPF, intno * 8 + 2);
642 }
643
644 if (type == 5) {
645 /* task gate */
eaa728ee 646 /* must do that check here to return the correct error code */
20054ef0 647 if (!(e2 & DESC_P_MASK)) {
77b2bc2c 648 raise_exception_err(env, EXCP0B_NOSEG, intno * 8 + 2);
20054ef0 649 }
2999a0b2 650 switch_tss(env, intno * 8, e1, e2, SWITCH_TSS_CALL, old_eip);
eaa728ee
FB		 651 if (has_error_code) {
652 int type;
653 uint32_t mask;
20054ef0 654
eaa728ee
FB		 655 /* push the error code */
656 type = (env->tr.flags >> DESC_TYPE_SHIFT) & 0xf;
657 shift = type >> 3;
20054ef0 658 if (env->segs[R_SS].flags & DESC_B_MASK) {
eaa728ee 659 mask = 0xffffffff;
20054ef0 660 } else {
eaa728ee 661 mask = 0xffff;
20054ef0 662 }
08b3ded6 663 esp = (env->regs[R_ESP] - (2 << shift)) & mask;
eaa728ee 664 ssp = env->segs[R_SS].base + esp;
20054ef0 665 if (shift) {
329e607d 666 cpu_stl_kernel(env, ssp, error_code);
20054ef0 667 } else {
329e607d 668 cpu_stw_kernel(env, ssp, error_code);
20054ef0 669 }
eaa728ee
FB		 670 SET_ESP(esp, mask);
671 }
672 return;
20054ef0 673 }
3df1a3d0
PM		 674
675 /* Otherwise, trap or interrupt gate */
676
eaa728ee 677 /* check valid bit */
20054ef0 678 if (!(e2 & DESC_P_MASK)) {
77b2bc2c 679 raise_exception_err(env, EXCP0B_NOSEG, intno * 8 + 2);
20054ef0 680 }
eaa728ee
FB		 681 selector = e1 >> 16;
682 offset = (e2 & 0xffff0000) | (e1 & 0x0000ffff);
20054ef0 683 if ((selector & 0xfffc) == 0) {
77b2bc2c 684 raise_exception_err(env, EXCP0D_GPF, 0);
20054ef0 685 }
2999a0b2 686 if (load_segment(env, &e1, &e2, selector) != 0) {
77b2bc2c 687 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
20054ef0
BS		 688 }
689 if (!(e2 & DESC_S_MASK) || !(e2 & (DESC_CS_MASK))) {
77b2bc2c 690 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
20054ef0 691 }
eaa728ee 692 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
20054ef0 693 if (dpl > cpl) {
77b2bc2c 694 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
20054ef0
BS		 695 }
696 if (!(e2 & DESC_P_MASK)) {
77b2bc2c 697 raise_exception_err(env, EXCP0B_NOSEG, selector & 0xfffc);
20054ef0 698 }
1110bfe6
PB		 699 if (e2 & DESC_C_MASK) {
700 dpl = cpl;
701 }
702 if (dpl < cpl) {
eaa728ee 703 /* to inner privilege */
100ec099 704 get_ss_esp_from_tss(env, &ss, &esp, dpl, 0);
20054ef0 705 if ((ss & 0xfffc) == 0) {
77b2bc2c 706 raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
20054ef0
BS		 707 }
708 if ((ss & 3) != dpl) {
77b2bc2c 709 raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
20054ef0 710 }
2999a0b2 711 if (load_segment(env, &ss_e1, &ss_e2, ss) != 0) {
77b2bc2c 712 raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
20054ef0 713 }
eaa728ee 714 ss_dpl = (ss_e2 >> DESC_DPL_SHIFT) & 3;
20054ef0 715 if (ss_dpl != dpl) {
77b2bc2c 716 raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
20054ef0 717 }
eaa728ee
FB		 718 if (!(ss_e2 & DESC_S_MASK) ||
719 (ss_e2 & DESC_CS_MASK) ||
20054ef0 720 !(ss_e2 & DESC_W_MASK)) {
77b2bc2c 721 raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
20054ef0
BS		 722 }
723 if (!(ss_e2 & DESC_P_MASK)) {
77b2bc2c 724 raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
20054ef0 725 }
eaa728ee
FB		 726 new_stack = 1;
727 sp_mask = get_sp_mask(ss_e2);
728 ssp = get_seg_base(ss_e1, ss_e2);
1110bfe6 729 } else {
eaa728ee 730 /* to same privilege */
87446327 731 if (vm86) {
77b2bc2c 732 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
20054ef0 733 }
eaa728ee
FB		 734 new_stack = 0;
735 sp_mask = get_sp_mask(env->segs[R_SS].flags);
736 ssp = env->segs[R_SS].base;
08b3ded6 737 esp = env->regs[R_ESP];
eaa728ee
FB		 738 }
739
740 shift = type >> 3;
741
742#if 0
743 /* XXX: check that enough room is available */
744 push_size = 6 + (new_stack << 2) + (has_error_code << 1);
87446327 745 if (vm86) {
eaa728ee 746 push_size += 8;
20054ef0 747 }
eaa728ee
FB		 748 push_size <<= shift;
749#endif
750 if (shift == 1) {
751 if (new_stack) {
87446327 752 if (vm86) {
eaa728ee
FB		 753 PUSHL(ssp, esp, sp_mask, env->segs[R_GS].selector);
754 PUSHL(ssp, esp, sp_mask, env->segs[R_FS].selector);
755 PUSHL(ssp, esp, sp_mask, env->segs[R_DS].selector);
756 PUSHL(ssp, esp, sp_mask, env->segs[R_ES].selector);
757 }
758 PUSHL(ssp, esp, sp_mask, env->segs[R_SS].selector);
08b3ded6 759 PUSHL(ssp, esp, sp_mask, env->regs[R_ESP]);
eaa728ee 760 }
997ff0d9 761 PUSHL(ssp, esp, sp_mask, cpu_compute_eflags(env));
eaa728ee
FB		 762 PUSHL(ssp, esp, sp_mask, env->segs[R_CS].selector);
763 PUSHL(ssp, esp, sp_mask, old_eip);
764 if (has_error_code) {
765 PUSHL(ssp, esp, sp_mask, error_code);
766 }
767 } else {
768 if (new_stack) {
87446327 769 if (vm86) {
eaa728ee
FB		 770 PUSHW(ssp, esp, sp_mask, env->segs[R_GS].selector);
771 PUSHW(ssp, esp, sp_mask, env->segs[R_FS].selector);
772 PUSHW(ssp, esp, sp_mask, env->segs[R_DS].selector);
773 PUSHW(ssp, esp, sp_mask, env->segs[R_ES].selector);
774 }
775 PUSHW(ssp, esp, sp_mask, env->segs[R_SS].selector);
08b3ded6 776 PUSHW(ssp, esp, sp_mask, env->regs[R_ESP]);
eaa728ee 777 }
997ff0d9 778 PUSHW(ssp, esp, sp_mask, cpu_compute_eflags(env));
eaa728ee
FB		 779 PUSHW(ssp, esp, sp_mask, env->segs[R_CS].selector);
780 PUSHW(ssp, esp, sp_mask, old_eip);
781 if (has_error_code) {
782 PUSHW(ssp, esp, sp_mask, error_code);
783 }
784 }
785
fd460606
KC		 786 /* interrupt gate clear IF mask */
787 if ((type & 1) == 0) {
788 env->eflags &= ~IF_MASK;
789 }
790 env->eflags &= ~(TF_MASK | VM_MASK | RF_MASK | NT_MASK);
791
eaa728ee 792 if (new_stack) {
87446327 793 if (vm86) {
eaa728ee
FB		 794 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0, 0);
795 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0, 0);
796 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0, 0);
797 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0, 0);
798 }
799 ss = (ss & ~3) | dpl;
800 cpu_x86_load_seg_cache(env, R_SS, ss,
801 ssp, get_seg_limit(ss_e1, ss_e2), ss_e2);
802 }
803 SET_ESP(esp, sp_mask);
804
805 selector = (selector & ~3) | dpl;
806 cpu_x86_load_seg_cache(env, R_CS, selector,
807 get_seg_base(e1, e2),
808 get_seg_limit(e1, e2),
809 e2);
eaa728ee 810 env->eip = offset;
eaa728ee
FB		 811}
812
813#ifdef TARGET_X86_64
814
100ec099 815#define PUSHQ_RA(sp, val, ra) \
20054ef0
BS		 816 { \
817 sp -= 8; \
100ec099 818 cpu_stq_kernel_ra(env, sp, (val), ra); \
20054ef0 819 }
eaa728ee 820
100ec099 821#define POPQ_RA(sp, val, ra) \
20054ef0 822 { \
100ec099 823 val = cpu_ldq_kernel_ra(env, sp, ra); \
20054ef0
BS		 824 sp += 8; \
825 }
eaa728ee 826
100ec099
PD		 827#define PUSHQ(sp, val) PUSHQ_RA(sp, val, 0)
828#define POPQ(sp, val) POPQ_RA(sp, val, 0)
829
2999a0b2 830static inline target_ulong get_rsp_from_tss(CPUX86State *env, int level)
eaa728ee 831{
6aa9e42f 832 X86CPU *cpu = env_archcpu(env);
50fcc7cb
GW		 833 int index, pg_mode;
834 target_ulong rsp;
835 int32_t sext;
eaa728ee
FB		 836
837#if 0
838 printf("TR: base=" TARGET_FMT_lx " limit=%x\n",
839 env->tr.base, env->tr.limit);
840#endif
841
20054ef0 842 if (!(env->tr.flags & DESC_P_MASK)) {
a47dddd7 843 cpu_abort(CPU(cpu), "invalid tss");
20054ef0 844 }
eaa728ee 845 index = 8 * level + 4;
20054ef0 846 if ((index + 7) > env->tr.limit) {
77b2bc2c 847 raise_exception_err(env, EXCP0A_TSS, env->tr.selector & 0xfffc);
20054ef0 848 }
50fcc7cb
GW		 849
850 rsp = cpu_ldq_kernel(env, env->tr.base + index);
851
852 /* test virtual address sign extension */
853 pg_mode = get_pg_mode(env);
854 sext = (int64_t)rsp >> (pg_mode & PG_MODE_LA57 ? 56 : 47);
855 if (sext != 0 && sext != -1) {
856 raise_exception_err(env, EXCP0C_STACK, 0);
857 }
858
859 return rsp;
eaa728ee
FB		 860}
861
862/* 64 bit interrupt */
2999a0b2
BS		 863static void do_interrupt64(CPUX86State *env, int intno, int is_int,
864 int error_code, target_ulong next_eip, int is_hw)
eaa728ee
FB		 865{
866 SegmentCache *dt;
867 target_ulong ptr;
868 int type, dpl, selector, cpl, ist;
869 int has_error_code, new_stack;
870 uint32_t e1, e2, e3, ss;
871 target_ulong old_eip, esp, offset;
eaa728ee 872
eaa728ee 873 has_error_code = 0;
20054ef0
BS		 874 if (!is_int && !is_hw) {
875 has_error_code = exception_has_error_code(intno);
876 }
877 if (is_int) {
eaa728ee 878 old_eip = next_eip;
20054ef0 879 } else {
eaa728ee 880 old_eip = env->eip;
20054ef0 881 }
eaa728ee
FB		 882
883 dt = &env->idt;
20054ef0 884 if (intno * 16 + 15 > dt->limit) {
b585edca 885 raise_exception_err(env, EXCP0D_GPF, intno * 8 + 2);
20054ef0 886 }
eaa728ee 887 ptr = dt->base + intno * 16;
329e607d
BS		 888 e1 = cpu_ldl_kernel(env, ptr);
889 e2 = cpu_ldl_kernel(env, ptr + 4);
890 e3 = cpu_ldl_kernel(env, ptr + 8);
eaa728ee
FB		 891 /* check gate type */
892 type = (e2 >> DESC_TYPE_SHIFT) & 0x1f;
20054ef0 893 switch (type) {
eaa728ee
FB		 894 case 14: /* 386 interrupt gate */
895 case 15: /* 386 trap gate */
896 break;
897 default:
b585edca 898 raise_exception_err(env, EXCP0D_GPF, intno * 8 + 2);
eaa728ee
FB		 899 break;
900 }
901 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
902 cpl = env->hflags & HF_CPL_MASK;
1235fc06 903 /* check privilege if software int */
20054ef0 904 if (is_int && dpl < cpl) {
b585edca 905 raise_exception_err(env, EXCP0D_GPF, intno * 8 + 2);
20054ef0 906 }
eaa728ee 907 /* check valid bit */
20054ef0 908 if (!(e2 & DESC_P_MASK)) {
b585edca 909 raise_exception_err(env, EXCP0B_NOSEG, intno * 8 + 2);
20054ef0 910 }
eaa728ee
FB		 911 selector = e1 >> 16;
912 offset = ((target_ulong)e3 << 32) | (e2 & 0xffff0000) | (e1 & 0x0000ffff);
913 ist = e2 & 7;
20054ef0 914 if ((selector & 0xfffc) == 0) {
77b2bc2c 915 raise_exception_err(env, EXCP0D_GPF, 0);
20054ef0 916 }
eaa728ee 917
2999a0b2 918 if (load_segment(env, &e1, &e2, selector) != 0) {
77b2bc2c 919 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
20054ef0
BS		 920 }
921 if (!(e2 & DESC_S_MASK) || !(e2 & (DESC_CS_MASK))) {
77b2bc2c 922 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
20054ef0 923 }
eaa728ee 924 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
20054ef0 925 if (dpl > cpl) {
77b2bc2c 926 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
20054ef0
BS		 927 }
928 if (!(e2 & DESC_P_MASK)) {
77b2bc2c 929 raise_exception_err(env, EXCP0B_NOSEG, selector & 0xfffc);
20054ef0
BS		 930 }
931 if (!(e2 & DESC_L_MASK) || (e2 & DESC_B_MASK)) {
77b2bc2c 932 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
20054ef0 933 }
1110bfe6
PB		 934 if (e2 & DESC_C_MASK) {
935 dpl = cpl;
936 }
937 if (dpl < cpl || ist != 0) {
eaa728ee 938 /* to inner privilege */
eaa728ee 939 new_stack = 1;
ae67dc72
PB		 940 esp = get_rsp_from_tss(env, ist != 0 ? ist + 3 : dpl);
941 ss = 0;
1110bfe6 942 } else {
eaa728ee 943 /* to same privilege */
20054ef0 944 if (env->eflags & VM_MASK) {
77b2bc2c 945 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
20054ef0 946 }
eaa728ee 947 new_stack = 0;
ae67dc72 948 esp = env->regs[R_ESP];
e95e9b88 949 }
ae67dc72 950 esp &= ~0xfLL; /* align stack */
eaa728ee
FB		 951
952 PUSHQ(esp, env->segs[R_SS].selector);
08b3ded6 953 PUSHQ(esp, env->regs[R_ESP]);
997ff0d9 954 PUSHQ(esp, cpu_compute_eflags(env));
eaa728ee
FB		 955 PUSHQ(esp, env->segs[R_CS].selector);
956 PUSHQ(esp, old_eip);
957 if (has_error_code) {
958 PUSHQ(esp, error_code);
959 }
960
fd460606
KC		 961 /* interrupt gate clear IF mask */
962 if ((type & 1) == 0) {
963 env->eflags &= ~IF_MASK;
964 }
965 env->eflags &= ~(TF_MASK | VM_MASK | RF_MASK | NT_MASK);
966
eaa728ee
FB		 967 if (new_stack) {
968 ss = 0 | dpl;
e95e9b88 969 cpu_x86_load_seg_cache(env, R_SS, ss, 0, 0, dpl << DESC_DPL_SHIFT);
eaa728ee 970 }
08b3ded6 971 env->regs[R_ESP] = esp;
eaa728ee
FB		 972
973 selector = (selector & ~3) | dpl;
974 cpu_x86_load_seg_cache(env, R_CS, selector,
975 get_seg_base(e1, e2),
976 get_seg_limit(e1, e2),
977 e2);
eaa728ee 978 env->eip = offset;
eaa728ee 979}
63fd8ef0 980#endif /* TARGET_X86_64 */
eaa728ee 981
2999a0b2 982void helper_sysret(CPUX86State *env, int dflag)
eaa728ee
FB		 983{
984 int cpl, selector;
985
986 if (!(env->efer & MSR_EFER_SCE)) {
100ec099 987 raise_exception_err_ra(env, EXCP06_ILLOP, 0, GETPC());
eaa728ee
FB		 988 }
989 cpl = env->hflags & HF_CPL_MASK;
990 if (!(env->cr[0] & CR0_PE_MASK) || cpl != 0) {
100ec099 991 raise_exception_err_ra(env, EXCP0D_GPF, 0, GETPC());
eaa728ee
FB		 992 }
993 selector = (env->star >> 48) & 0xffff;
63fd8ef0 994#ifdef TARGET_X86_64
eaa728ee 995 if (env->hflags & HF_LMA_MASK) {
fd460606
KC		 996 cpu_load_eflags(env, (uint32_t)(env->regs[11]), TF_MASK | AC_MASK
997 | ID_MASK | IF_MASK | IOPL_MASK | VM_MASK | RF_MASK |
998 NT_MASK);
eaa728ee
FB		 999 if (dflag == 2) {
1000 cpu_x86_load_seg_cache(env, R_CS, (selector + 16) | 3,
1001 0, 0xffffffff,
1002 DESC_G_MASK | DESC_P_MASK |
1003 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
1004 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK |
1005 DESC_L_MASK);
a4165610 1006 env->eip = env->regs[R_ECX];
eaa728ee
FB		 1007 } else {
1008 cpu_x86_load_seg_cache(env, R_CS, selector | 3,
1009 0, 0xffffffff,
1010 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
1011 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
1012 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK);
a4165610 1013 env->eip = (uint32_t)env->regs[R_ECX];
eaa728ee 1014 }
ac576229 1015 cpu_x86_load_seg_cache(env, R_SS, (selector + 8) | 3,
eaa728ee
FB		 1016 0, 0xffffffff,
1017 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
1018 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
1019 DESC_W_MASK | DESC_A_MASK);
63fd8ef0
PB		 1020 } else
1021#endif
1022 {
fd460606 1023 env->eflags |= IF_MASK;
eaa728ee
FB		 1024 cpu_x86_load_seg_cache(env, R_CS, selector | 3,
1025 0, 0xffffffff,
1026 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
1027 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
1028 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK);
a4165610 1029 env->eip = (uint32_t)env->regs[R_ECX];
ac576229 1030 cpu_x86_load_seg_cache(env, R_SS, (selector + 8) | 3,
eaa728ee
FB		 1031 0, 0xffffffff,
1032 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
1033 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
1034 DESC_W_MASK | DESC_A_MASK);
eaa728ee 1035 }
eaa728ee
FB		 1036}
1037
1038/* real mode interrupt */
2999a0b2
BS		 1039static void do_interrupt_real(CPUX86State *env, int intno, int is_int,
1040 int error_code, unsigned int next_eip)
eaa728ee
FB		 1041{
1042 SegmentCache *dt;
1043 target_ulong ptr, ssp;
1044 int selector;
1045 uint32_t offset, esp;
1046 uint32_t old_cs, old_eip;
eaa728ee 1047
20054ef0 1048 /* real mode (simpler!) */
eaa728ee 1049 dt = &env->idt;
20054ef0 1050 if (intno * 4 + 3 > dt->limit) {
77b2bc2c 1051 raise_exception_err(env, EXCP0D_GPF, intno * 8 + 2);
20054ef0 1052 }
eaa728ee 1053 ptr = dt->base + intno * 4;
329e607d
BS		 1054 offset = cpu_lduw_kernel(env, ptr);
1055 selector = cpu_lduw_kernel(env, ptr + 2);
08b3ded6 1056 esp = env->regs[R_ESP];
eaa728ee 1057 ssp = env->segs[R_SS].base;
20054ef0 1058 if (is_int) {
eaa728ee 1059 old_eip = next_eip;
20054ef0 1060 } else {
eaa728ee 1061 old_eip = env->eip;
20054ef0 1062 }
eaa728ee 1063 old_cs = env->segs[R_CS].selector;
20054ef0 1064 /* XXX: use SS segment size? */
997ff0d9 1065 PUSHW(ssp, esp, 0xffff, cpu_compute_eflags(env));
eaa728ee
FB		 1066 PUSHW(ssp, esp, 0xffff, old_cs);
1067 PUSHW(ssp, esp, 0xffff, old_eip);
1068
1069 /* update processor state */
08b3ded6 1070 env->regs[R_ESP] = (env->regs[R_ESP] & ~0xffff) | (esp & 0xffff);
eaa728ee
FB		 1071 env->eip = offset;
1072 env->segs[R_CS].selector = selector;
1073 env->segs[R_CS].base = (selector << 4);
1074 env->eflags &= ~(IF_MASK | TF_MASK | AC_MASK | RF_MASK);
1075}
1076
eaa728ee
FB		 1077/*
1078 * Begin execution of an interruption. is_int is TRUE if coming from
a78d0eab 1079 * the int instruction. next_eip is the env->eip value AFTER the interrupt
eaa728ee
FB		 1080 * instruction. It is only relevant if is_int is TRUE.
1081 */
30493a03
CF		 1082void do_interrupt_all(X86CPU *cpu, int intno, int is_int,
1083 int error_code, target_ulong next_eip, int is_hw)
eaa728ee 1084{
ca4c810a
AF		 1085 CPUX86State *env = &cpu->env;
1086
8fec2b8c 1087 if (qemu_loglevel_mask(CPU_LOG_INT)) {
eaa728ee
FB		 1088 if ((env->cr[0] & CR0_PE_MASK)) {
1089 static int count;
20054ef0
BS		 1090
1091 qemu_log("%6d: v=%02x e=%04x i=%d cpl=%d IP=%04x:" TARGET_FMT_lx
1092 " pc=" TARGET_FMT_lx " SP=%04x:" TARGET_FMT_lx,
1093 count, intno, error_code, is_int,
1094 env->hflags & HF_CPL_MASK,
a78d0eab
LG		 1095 env->segs[R_CS].selector, env->eip,
1096 (int)env->segs[R_CS].base + env->eip,
08b3ded6 1097 env->segs[R_SS].selector, env->regs[R_ESP]);
eaa728ee 1098 if (intno == 0x0e) {
93fcfe39 1099 qemu_log(" CR2=" TARGET_FMT_lx, env->cr[2]);
eaa728ee 1100 } else {
4b34e3ad 1101 qemu_log(" env->regs[R_EAX]=" TARGET_FMT_lx, env->regs[R_EAX]);
eaa728ee 1102 }
93fcfe39 1103 qemu_log("\n");
a0762859 1104 log_cpu_state(CPU(cpu), CPU_DUMP_CCOP);
eaa728ee
FB		 1105#if 0
1106 {
1107 int i;
9bd5494e 1108 target_ulong ptr;
20054ef0 1109
93fcfe39 1110 qemu_log(" code=");
eaa728ee 1111 ptr = env->segs[R_CS].base + env->eip;
20054ef0 1112 for (i = 0; i < 16; i++) {
93fcfe39 1113 qemu_log(" %02x", ldub(ptr + i));
eaa728ee 1114 }
93fcfe39 1115 qemu_log("\n");
eaa728ee
FB		 1116 }
1117#endif
1118 count++;
1119 }
1120 }
1121 if (env->cr[0] & CR0_PE_MASK) {
00ea18d1 1122#if !defined(CONFIG_USER_ONLY)
f8dc4c64 1123 if (env->hflags & HF_GUEST_MASK) {
2999a0b2 1124 handle_even_inj(env, intno, is_int, error_code, is_hw, 0);
20054ef0 1125 }
00ea18d1 1126#endif
eb38c52c 1127#ifdef TARGET_X86_64
eaa728ee 1128 if (env->hflags & HF_LMA_MASK) {
2999a0b2 1129 do_interrupt64(env, intno, is_int, error_code, next_eip, is_hw);
eaa728ee
FB		 1130 } else
1131#endif
1132 {
2999a0b2
BS		 1133 do_interrupt_protected(env, intno, is_int, error_code, next_eip,
1134 is_hw);
eaa728ee
FB		 1135 }
1136 } else {
00ea18d1 1137#if !defined(CONFIG_USER_ONLY)
f8dc4c64 1138 if (env->hflags & HF_GUEST_MASK) {
2999a0b2 1139 handle_even_inj(env, intno, is_int, error_code, is_hw, 1);
20054ef0 1140 }
00ea18d1 1141#endif
2999a0b2 1142 do_interrupt_real(env, intno, is_int, error_code, next_eip);
eaa728ee 1143 }
2ed51f5b 1144
00ea18d1 1145#if !defined(CONFIG_USER_ONLY)
f8dc4c64 1146 if (env->hflags & HF_GUEST_MASK) {
fdfba1a2 1147 CPUState *cs = CPU(cpu);
b216aa6c 1148 uint32_t event_inj = x86_ldl_phys(cs, env->vm_vmcb +
20054ef0
BS		 1149 offsetof(struct vmcb,
1150 control.event_inj));
1151
b216aa6c 1152 x86_stl_phys(cs,
ab1da857 1153 env->vm_vmcb + offsetof(struct vmcb, control.event_inj),
20054ef0 1154 event_inj & ~SVM_EVTINJ_VALID);
2ed51f5b 1155 }
00ea18d1 1156#endif
eaa728ee
FB		 1157}
1158
2999a0b2 1159void do_interrupt_x86_hardirq(CPUX86State *env, int intno, int is_hw)
e694d4e2 1160{
6aa9e42f 1161 do_interrupt_all(env_archcpu(env), intno, 0, 0, 0, is_hw);
e694d4e2
BS		 1162}
1163
2999a0b2 1164void helper_lldt(CPUX86State *env, int selector)
eaa728ee
FB		 1165{
1166 SegmentCache *dt;
1167 uint32_t e1, e2;
1168 int index, entry_limit;
1169 target_ulong ptr;
1170
1171 selector &= 0xffff;
1172 if ((selector & 0xfffc) == 0) {
1173 /* XXX: NULL selector case: invalid LDT */
1174 env->ldt.base = 0;
1175 env->ldt.limit = 0;
1176 } else {
20054ef0 1177 if (selector & 0x4) {
100ec099 1178 raise_exception_err_ra(env, EXCP0D_GPF, selector & 0xfffc, GETPC());
20054ef0 1179 }
eaa728ee
FB		 1180 dt = &env->gdt;
1181 index = selector & ~7;
1182#ifdef TARGET_X86_64
20054ef0 1183 if (env->hflags & HF_LMA_MASK) {
eaa728ee 1184 entry_limit = 15;
20054ef0 1185 } else
eaa728ee 1186#endif
20054ef0 1187 {
eaa728ee 1188 entry_limit = 7;
20054ef0
BS		 1189 }
1190 if ((index + entry_limit) > dt->limit) {
100ec099 1191 raise_exception_err_ra(env, EXCP0D_GPF, selector & 0xfffc, GETPC());
20054ef0 1192 }
eaa728ee 1193 ptr = dt->base + index;
100ec099
PD		 1194 e1 = cpu_ldl_kernel_ra(env, ptr, GETPC());
1195 e2 = cpu_ldl_kernel_ra(env, ptr + 4, GETPC());
20054ef0 1196 if ((e2 & DESC_S_MASK) || ((e2 >> DESC_TYPE_SHIFT) & 0xf) != 2) {
100ec099 1197 raise_exception_err_ra(env, EXCP0D_GPF, selector & 0xfffc, GETPC());
20054ef0
BS		 1198 }
1199 if (!(e2 & DESC_P_MASK)) {
100ec099 1200 raise_exception_err_ra(env, EXCP0B_NOSEG, selector & 0xfffc, GETPC());
20054ef0 1201 }
eaa728ee
FB		 1202#ifdef TARGET_X86_64
1203 if (env->hflags & HF_LMA_MASK) {
1204 uint32_t e3;
20054ef0 1205
100ec099 1206 e3 = cpu_ldl_kernel_ra(env, ptr + 8, GETPC());
eaa728ee
FB		 1207 load_seg_cache_raw_dt(&env->ldt, e1, e2);
1208 env->ldt.base |= (target_ulong)e3 << 32;
1209 } else
1210#endif
1211 {
1212 load_seg_cache_raw_dt(&env->ldt, e1, e2);
1213 }
1214 }
1215 env->ldt.selector = selector;
1216}
1217
2999a0b2 1218void helper_ltr(CPUX86State *env, int selector)
eaa728ee
FB		 1219{
1220 SegmentCache *dt;
1221 uint32_t e1, e2;
1222 int index, type, entry_limit;
1223 target_ulong ptr;
1224
1225 selector &= 0xffff;
1226 if ((selector & 0xfffc) == 0) {
1227 /* NULL selector case: invalid TR */
1228 env->tr.base = 0;
1229 env->tr.limit = 0;
1230 env->tr.flags = 0;
1231 } else {
20054ef0 1232 if (selector & 0x4) {
100ec099 1233 raise_exception_err_ra(env, EXCP0D_GPF, selector & 0xfffc, GETPC());
20054ef0 1234 }
eaa728ee
FB		 1235 dt = &env->gdt;
1236 index = selector & ~7;
1237#ifdef TARGET_X86_64
20054ef0 1238 if (env->hflags & HF_LMA_MASK) {
eaa728ee 1239 entry_limit = 15;
20054ef0 1240 } else
eaa728ee 1241#endif
20054ef0 1242 {
eaa728ee 1243 entry_limit = 7;
20054ef0
BS		 1244 }
1245 if ((index + entry_limit) > dt->limit) {
100ec099 1246 raise_exception_err_ra(env, EXCP0D_GPF, selector & 0xfffc, GETPC());
20054ef0 1247 }
eaa728ee 1248 ptr = dt->base + index;
100ec099
PD		 1249 e1 = cpu_ldl_kernel_ra(env, ptr, GETPC());
1250 e2 = cpu_ldl_kernel_ra(env, ptr + 4, GETPC());
eaa728ee
FB		 1251 type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
1252 if ((e2 & DESC_S_MASK) ||
20054ef0 1253 (type != 1 && type != 9)) {
100ec099 1254 raise_exception_err_ra(env, EXCP0D_GPF, selector & 0xfffc, GETPC());
20054ef0
BS		 1255 }
1256 if (!(e2 & DESC_P_MASK)) {
100ec099 1257 raise_exception_err_ra(env, EXCP0B_NOSEG, selector & 0xfffc, GETPC());
20054ef0 1258 }
eaa728ee
FB		 1259#ifdef TARGET_X86_64
1260 if (env->hflags & HF_LMA_MASK) {
1261 uint32_t e3, e4;
20054ef0 1262
100ec099
PD		 1263 e3 = cpu_ldl_kernel_ra(env, ptr + 8, GETPC());
1264 e4 = cpu_ldl_kernel_ra(env, ptr + 12, GETPC());
20054ef0 1265 if ((e4 >> DESC_TYPE_SHIFT) & 0xf) {
100ec099 1266 raise_exception_err_ra(env, EXCP0D_GPF, selector & 0xfffc, GETPC());
20054ef0 1267 }
eaa728ee
FB		 1268 load_seg_cache_raw_dt(&env->tr, e1, e2);
1269 env->tr.base |= (target_ulong)e3 << 32;
1270 } else
1271#endif
1272 {
1273 load_seg_cache_raw_dt(&env->tr, e1, e2);
1274 }
1275 e2 |= DESC_TSS_BUSY_MASK;
100ec099 1276 cpu_stl_kernel_ra(env, ptr + 4, e2, GETPC());
eaa728ee
FB		 1277 }
1278 env->tr.selector = selector;
1279}
1280
1281/* only works if protected mode and not VM86. seg_reg must be != R_CS */
2999a0b2 1282void helper_load_seg(CPUX86State *env, int seg_reg, int selector)
eaa728ee
FB		 1283{
1284 uint32_t e1, e2;
1285 int cpl, dpl, rpl;
1286 SegmentCache *dt;
1287 int index;
1288 target_ulong ptr;
1289
1290 selector &= 0xffff;
1291 cpl = env->hflags & HF_CPL_MASK;
1292 if ((selector & 0xfffc) == 0) {
1293 /* null selector case */
1294 if (seg_reg == R_SS
1295#ifdef TARGET_X86_64
1296 && (!(env->hflags & HF_CS64_MASK) || cpl == 3)
1297#endif
20054ef0 1298 ) {
100ec099 1299 raise_exception_err_ra(env, EXCP0D_GPF, 0, GETPC());
20054ef0 1300 }
eaa728ee
FB		 1301 cpu_x86_load_seg_cache(env, seg_reg, selector, 0, 0, 0);
1302 } else {
1303
20054ef0 1304 if (selector & 0x4) {
eaa728ee 1305 dt = &env->ldt;
20054ef0 1306 } else {
eaa728ee 1307 dt = &env->gdt;
20054ef0 1308 }
eaa728ee 1309 index = selector & ~7;
20054ef0 1310 if ((index + 7) > dt->limit) {
100ec099 1311 raise_exception_err_ra(env, EXCP0D_GPF, selector & 0xfffc, GETPC());
20054ef0 1312 }
eaa728ee 1313 ptr = dt->base + index;
100ec099
PD		 1314 e1 = cpu_ldl_kernel_ra(env, ptr, GETPC());
1315 e2 = cpu_ldl_kernel_ra(env, ptr + 4, GETPC());
eaa728ee 1316
20054ef0 1317 if (!(e2 & DESC_S_MASK)) {
100ec099 1318 raise_exception_err_ra(env, EXCP0D_GPF, selector & 0xfffc, GETPC());
20054ef0 1319 }
eaa728ee
FB		 1320 rpl = selector & 3;
1321 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1322 if (seg_reg == R_SS) {
1323 /* must be writable segment */
20054ef0 1324 if ((e2 & DESC_CS_MASK) || !(e2 & DESC_W_MASK)) {
100ec099 1325 raise_exception_err_ra(env, EXCP0D_GPF, selector & 0xfffc, GETPC());
20054ef0
BS		 1326 }
1327 if (rpl != cpl || dpl != cpl) {
100ec099 1328 raise_exception_err_ra(env, EXCP0D_GPF, selector & 0xfffc, GETPC());
20054ef0 1329 }
eaa728ee
FB		 1330 } else {
1331 /* must be readable segment */
20054ef0 1332 if ((e2 & (DESC_CS_MASK | DESC_R_MASK)) == DESC_CS_MASK) {
100ec099 1333 raise_exception_err_ra(env, EXCP0D_GPF, selector & 0xfffc, GETPC());
20054ef0 1334 }
eaa728ee
FB		 1335
1336 if (!(e2 & DESC_CS_MASK) || !(e2 & DESC_C_MASK)) {
1337 /* if not conforming code, test rights */
20054ef0 1338 if (dpl < cpl || dpl < rpl) {
100ec099 1339 raise_exception_err_ra(env, EXCP0D_GPF, selector & 0xfffc, GETPC());
20054ef0 1340 }
eaa728ee
FB		 1341 }
1342 }
1343
1344 if (!(e2 & DESC_P_MASK)) {
20054ef0 1345 if (seg_reg == R_SS) {
100ec099 1346 raise_exception_err_ra(env, EXCP0C_STACK, selector & 0xfffc, GETPC());
20054ef0 1347 } else {
100ec099 1348 raise_exception_err_ra(env, EXCP0B_NOSEG, selector & 0xfffc, GETPC());
20054ef0 1349 }
eaa728ee
FB		 1350 }
1351
1352 /* set the access bit if not already set */
1353 if (!(e2 & DESC_A_MASK)) {
1354 e2 |= DESC_A_MASK;
100ec099 1355 cpu_stl_kernel_ra(env, ptr + 4, e2, GETPC());
eaa728ee
FB		 1356 }
1357
1358 cpu_x86_load_seg_cache(env, seg_reg, selector,
1359 get_seg_base(e1, e2),
1360 get_seg_limit(e1, e2),
1361 e2);
1362#if 0
93fcfe39 1363 qemu_log("load_seg: sel=0x%04x base=0x%08lx limit=0x%08lx flags=%08x\n",
eaa728ee
FB		 1364 selector, (unsigned long)sc->base, sc->limit, sc->flags);
1365#endif
1366 }
1367}
1368
1369/* protected mode jump */
2999a0b2 1370void helper_ljmp_protected(CPUX86State *env, int new_cs, target_ulong new_eip,
100ec099 1371 target_ulong next_eip)
eaa728ee
FB		 1372{
1373 int gate_cs, type;
1374 uint32_t e1, e2, cpl, dpl, rpl, limit;
eaa728ee 1375
20054ef0 1376 if ((new_cs & 0xfffc) == 0) {
100ec099 1377 raise_exception_err_ra(env, EXCP0D_GPF, 0, GETPC());
20054ef0 1378 }
100ec099
PD		 1379 if (load_segment_ra(env, &e1, &e2, new_cs, GETPC()) != 0) {
1380 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, GETPC());
20054ef0 1381 }
eaa728ee
FB		 1382 cpl = env->hflags & HF_CPL_MASK;
1383 if (e2 & DESC_S_MASK) {
20054ef0 1384 if (!(e2 & DESC_CS_MASK)) {
100ec099 1385 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, GETPC());
20054ef0 1386 }
eaa728ee
FB		 1387 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1388 if (e2 & DESC_C_MASK) {
1389 /* conforming code segment */
20054ef0 1390 if (dpl > cpl) {
100ec099 1391 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, GETPC());
20054ef0 1392 }
eaa728ee
FB		 1393 } else {
1394 /* non conforming code segment */
1395 rpl = new_cs & 3;
20054ef0 1396 if (rpl > cpl) {
100ec099 1397 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, GETPC());
20054ef0
BS		 1398 }
1399 if (dpl != cpl) {
100ec099 1400 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, GETPC());
20054ef0 1401 }
eaa728ee 1402 }
20054ef0 1403 if (!(e2 & DESC_P_MASK)) {
100ec099 1404 raise_exception_err_ra(env, EXCP0B_NOSEG, new_cs & 0xfffc, GETPC());
20054ef0 1405 }
eaa728ee
FB		 1406 limit = get_seg_limit(e1, e2);
1407 if (new_eip > limit &&
db7196db
AO		 1408 (!(env->hflags & HF_LMA_MASK) || !(e2 & DESC_L_MASK))) {
1409 raise_exception_err_ra(env, EXCP0D_GPF, 0, GETPC());
20054ef0 1410 }
eaa728ee
FB		 1411 cpu_x86_load_seg_cache(env, R_CS, (new_cs & 0xfffc) | cpl,
1412 get_seg_base(e1, e2), limit, e2);
a78d0eab 1413 env->eip = new_eip;
eaa728ee
FB		 1414 } else {
1415 /* jump to call or task gate */
1416 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1417 rpl = new_cs & 3;
1418 cpl = env->hflags & HF_CPL_MASK;
1419 type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
0aca0605
AO		 1420
1421#ifdef TARGET_X86_64
1422 if (env->efer & MSR_EFER_LMA) {
1423 if (type != 12) {
1424 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, GETPC());
1425 }
1426 }
1427#endif
20054ef0 1428 switch (type) {
eaa728ee
FB		 1429 case 1: /* 286 TSS */
1430 case 9: /* 386 TSS */
1431 case 5: /* task gate */
20054ef0 1432 if (dpl < cpl || dpl < rpl) {
100ec099 1433 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, GETPC());
20054ef0 1434 }
100ec099 1435 switch_tss_ra(env, new_cs, e1, e2, SWITCH_TSS_JMP, next_eip, GETPC());
eaa728ee
FB		 1436 break;
1437 case 4: /* 286 call gate */
1438 case 12: /* 386 call gate */
20054ef0 1439 if ((dpl < cpl) || (dpl < rpl)) {
100ec099 1440 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, GETPC());
20054ef0
BS		 1441 }
1442 if (!(e2 & DESC_P_MASK)) {
100ec099 1443 raise_exception_err_ra(env, EXCP0B_NOSEG, new_cs & 0xfffc, GETPC());
20054ef0 1444 }
eaa728ee
FB		 1445 gate_cs = e1 >> 16;
1446 new_eip = (e1 & 0xffff);
20054ef0 1447 if (type == 12) {
eaa728ee 1448 new_eip |= (e2 & 0xffff0000);
20054ef0 1449 }
0aca0605
AO		 1450
1451#ifdef TARGET_X86_64
1452 if (env->efer & MSR_EFER_LMA) {
1453 /* load the upper 8 bytes of the 64-bit call gate */
1454 if (load_segment_ra(env, &e1, &e2, new_cs + 8, GETPC())) {
1455 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc,
1456 GETPC());
1457 }
1458 type = (e2 >> DESC_TYPE_SHIFT) & 0x1f;
1459 if (type != 0) {
1460 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc,
1461 GETPC());
1462 }
1463 new_eip |= ((target_ulong)e1) << 32;
1464 }
1465#endif
1466
100ec099
PD		 1467 if (load_segment_ra(env, &e1, &e2, gate_cs, GETPC()) != 0) {
1468 raise_exception_err_ra(env, EXCP0D_GPF, gate_cs & 0xfffc, GETPC());
20054ef0 1469 }
eaa728ee
FB		 1470 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1471 /* must be code segment */
1472 if (((e2 & (DESC_S_MASK | DESC_CS_MASK)) !=
20054ef0 1473 (DESC_S_MASK | DESC_CS_MASK))) {
100ec099 1474 raise_exception_err_ra(env, EXCP0D_GPF, gate_cs & 0xfffc, GETPC());
20054ef0 1475 }
eaa728ee 1476 if (((e2 & DESC_C_MASK) && (dpl > cpl)) ||
20054ef0 1477 (!(e2 & DESC_C_MASK) && (dpl != cpl))) {
100ec099 1478 raise_exception_err_ra(env, EXCP0D_GPF, gate_cs & 0xfffc, GETPC());
20054ef0 1479 }
0aca0605
AO		 1480#ifdef TARGET_X86_64
1481 if (env->efer & MSR_EFER_LMA) {
1482 if (!(e2 & DESC_L_MASK)) {
1483 raise_exception_err_ra(env, EXCP0D_GPF, gate_cs & 0xfffc, GETPC());
1484 }
1485 if (e2 & DESC_B_MASK) {
1486 raise_exception_err_ra(env, EXCP0D_GPF, gate_cs & 0xfffc, GETPC());
1487 }
1488 }
1489#endif
20054ef0 1490 if (!(e2 & DESC_P_MASK)) {
100ec099 1491 raise_exception_err_ra(env, EXCP0D_GPF, gate_cs & 0xfffc, GETPC());
20054ef0 1492 }
eaa728ee 1493 limit = get_seg_limit(e1, e2);
0aca0605
AO		 1494 if (new_eip > limit &&
1495 (!(env->hflags & HF_LMA_MASK) || !(e2 & DESC_L_MASK))) {
100ec099 1496 raise_exception_err_ra(env, EXCP0D_GPF, 0, GETPC());
20054ef0 1497 }
eaa728ee
FB		 1498 cpu_x86_load_seg_cache(env, R_CS, (gate_cs & 0xfffc) | cpl,
1499 get_seg_base(e1, e2), limit, e2);
a78d0eab 1500 env->eip = new_eip;
eaa728ee
FB		 1501 break;
1502 default:
100ec099 1503 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, GETPC());
eaa728ee
FB		 1504 break;
1505 }
1506 }
1507}
1508
1509/* real mode call */
8c03ab9f
RH		 1510void helper_lcall_real(CPUX86State *env, uint32_t new_cs, uint32_t new_eip,
1511 int shift, uint32_t next_eip)
eaa728ee 1512{
eaa728ee
FB		 1513 uint32_t esp, esp_mask;
1514 target_ulong ssp;
1515
08b3ded6 1516 esp = env->regs[R_ESP];
eaa728ee
FB		 1517 esp_mask = get_sp_mask(env->segs[R_SS].flags);
1518 ssp = env->segs[R_SS].base;
1519 if (shift) {
100ec099
PD		 1520 PUSHL_RA(ssp, esp, esp_mask, env->segs[R_CS].selector, GETPC());
1521 PUSHL_RA(ssp, esp, esp_mask, next_eip, GETPC());
eaa728ee 1522 } else {
100ec099
PD		 1523 PUSHW_RA(ssp, esp, esp_mask, env->segs[R_CS].selector, GETPC());
1524 PUSHW_RA(ssp, esp, esp_mask, next_eip, GETPC());
eaa728ee
FB		 1525 }
1526
1527 SET_ESP(esp, esp_mask);
1528 env->eip = new_eip;
1529 env->segs[R_CS].selector = new_cs;
1530 env->segs[R_CS].base = (new_cs << 4);
1531}
1532
1533/* protected mode call */
2999a0b2 1534void helper_lcall_protected(CPUX86State *env, int new_cs, target_ulong new_eip,
100ec099 1535 int shift, target_ulong next_eip)
eaa728ee
FB		 1536{
1537 int new_stack, i;
0aca0605
AO		 1538 uint32_t e1, e2, cpl, dpl, rpl, selector, param_count;
1539 uint32_t ss = 0, ss_e1 = 0, ss_e2 = 0, type, ss_dpl, sp_mask;
eaa728ee 1540 uint32_t val, limit, old_sp_mask;
0aca0605 1541 target_ulong ssp, old_ssp, offset, sp;
eaa728ee 1542
0aca0605 1543 LOG_PCALL("lcall %04x:" TARGET_FMT_lx " s=%d\n", new_cs, new_eip, shift);
6aa9e42f 1544 LOG_PCALL_STATE(env_cpu(env));
20054ef0 1545 if ((new_cs & 0xfffc) == 0) {
100ec099 1546 raise_exception_err_ra(env, EXCP0D_GPF, 0, GETPC());
20054ef0 1547 }
100ec099
PD		 1548 if (load_segment_ra(env, &e1, &e2, new_cs, GETPC()) != 0) {
1549 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, GETPC());
20054ef0 1550 }
eaa728ee 1551 cpl = env->hflags & HF_CPL_MASK;
d12d51d5 1552 LOG_PCALL("desc=%08x:%08x\n", e1, e2);
eaa728ee 1553 if (e2 & DESC_S_MASK) {
20054ef0 1554 if (!(e2 & DESC_CS_MASK)) {
100ec099 1555 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, GETPC());
20054ef0 1556 }
eaa728ee
FB		 1557 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1558 if (e2 & DESC_C_MASK) {
1559 /* conforming code segment */
20054ef0 1560 if (dpl > cpl) {
100ec099 1561 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, GETPC());
20054ef0 1562 }
eaa728ee
FB		 1563 } else {
1564 /* non conforming code segment */
1565 rpl = new_cs & 3;
20054ef0 1566 if (rpl > cpl) {
100ec099 1567 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, GETPC());
20054ef0
BS		 1568 }
1569 if (dpl != cpl) {
100ec099 1570 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, GETPC());
20054ef0 1571 }
eaa728ee 1572 }
20054ef0 1573 if (!(e2 & DESC_P_MASK)) {
100ec099 1574 raise_exception_err_ra(env, EXCP0B_NOSEG, new_cs & 0xfffc, GETPC());
20054ef0 1575 }
eaa728ee
FB		 1576
1577#ifdef TARGET_X86_64
1578 /* XXX: check 16/32 bit cases in long mode */
1579 if (shift == 2) {
1580 target_ulong rsp;
20054ef0 1581
eaa728ee 1582 /* 64 bit case */
08b3ded6 1583 rsp = env->regs[R_ESP];
100ec099
PD		 1584 PUSHQ_RA(rsp, env->segs[R_CS].selector, GETPC());
1585 PUSHQ_RA(rsp, next_eip, GETPC());
eaa728ee 1586 /* from this point, not restartable */
08b3ded6 1587 env->regs[R_ESP] = rsp;
eaa728ee
FB		 1588 cpu_x86_load_seg_cache(env, R_CS, (new_cs & 0xfffc) | cpl,
1589 get_seg_base(e1, e2),
1590 get_seg_limit(e1, e2), e2);
a78d0eab 1591 env->eip = new_eip;
eaa728ee
FB		 1592 } else
1593#endif
1594 {
08b3ded6 1595 sp = env->regs[R_ESP];
eaa728ee
FB		 1596 sp_mask = get_sp_mask(env->segs[R_SS].flags);
1597 ssp = env->segs[R_SS].base;
1598 if (shift) {
100ec099
PD		 1599 PUSHL_RA(ssp, sp, sp_mask, env->segs[R_CS].selector, GETPC());
1600 PUSHL_RA(ssp, sp, sp_mask, next_eip, GETPC());
eaa728ee 1601 } else {
100ec099
PD		 1602 PUSHW_RA(ssp, sp, sp_mask, env->segs[R_CS].selector, GETPC());
1603 PUSHW_RA(ssp, sp, sp_mask, next_eip, GETPC());
eaa728ee
FB		 1604 }
1605
1606 limit = get_seg_limit(e1, e2);
20054ef0 1607 if (new_eip > limit) {
100ec099 1608 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, GETPC());
20054ef0 1609 }
eaa728ee
FB		 1610 /* from this point, not restartable */
1611 SET_ESP(sp, sp_mask);
1612 cpu_x86_load_seg_cache(env, R_CS, (new_cs & 0xfffc) | cpl,
1613 get_seg_base(e1, e2), limit, e2);
a78d0eab 1614 env->eip = new_eip;
eaa728ee
FB		 1615 }
1616 } else {
1617 /* check gate type */
1618 type = (e2 >> DESC_TYPE_SHIFT) & 0x1f;
1619 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1620 rpl = new_cs & 3;
0aca0605
AO		 1621
1622#ifdef TARGET_X86_64
1623 if (env->efer & MSR_EFER_LMA) {
1624 if (type != 12) {
1625 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, GETPC());
1626 }
1627 }
1628#endif
1629
20054ef0 1630 switch (type) {
eaa728ee
FB		 1631 case 1: /* available 286 TSS */
1632 case 9: /* available 386 TSS */
1633 case 5: /* task gate */
20054ef0 1634 if (dpl < cpl || dpl < rpl) {
100ec099 1635 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, GETPC());
20054ef0 1636 }
100ec099 1637 switch_tss_ra(env, new_cs, e1, e2, SWITCH_TSS_CALL, next_eip, GETPC());
eaa728ee
FB		 1638 return;
1639 case 4: /* 286 call gate */
1640 case 12: /* 386 call gate */
1641 break;
1642 default:
100ec099 1643 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, GETPC());
eaa728ee
FB		 1644 break;
1645 }
1646 shift = type >> 3;
1647
20054ef0 1648 if (dpl < cpl || dpl < rpl) {
100ec099 1649 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, GETPC());
20054ef0 1650 }
eaa728ee 1651 /* check valid bit */
20054ef0 1652 if (!(e2 & DESC_P_MASK)) {
100ec099 1653 raise_exception_err_ra(env, EXCP0B_NOSEG, new_cs & 0xfffc, GETPC());
20054ef0 1654 }
eaa728ee 1655 selector = e1 >> 16;
eaa728ee 1656 param_count = e2 & 0x1f;
0aca0605
AO		 1657 offset = (e2 & 0xffff0000) | (e1 & 0x0000ffff);
1658#ifdef TARGET_X86_64
1659 if (env->efer & MSR_EFER_LMA) {
1660 /* load the upper 8 bytes of the 64-bit call gate */
1661 if (load_segment_ra(env, &e1, &e2, new_cs + 8, GETPC())) {
1662 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc,
1663 GETPC());
1664 }
1665 type = (e2 >> DESC_TYPE_SHIFT) & 0x1f;
1666 if (type != 0) {
1667 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc,
1668 GETPC());
1669 }
1670 offset |= ((target_ulong)e1) << 32;
1671 }
1672#endif
20054ef0 1673 if ((selector & 0xfffc) == 0) {
100ec099 1674 raise_exception_err_ra(env, EXCP0D_GPF, 0, GETPC());
20054ef0 1675 }
eaa728ee 1676
100ec099
PD		 1677 if (load_segment_ra(env, &e1, &e2, selector, GETPC()) != 0) {
1678 raise_exception_err_ra(env, EXCP0D_GPF, selector & 0xfffc, GETPC());
20054ef0
BS		 1679 }
1680 if (!(e2 & DESC_S_MASK) || !(e2 & (DESC_CS_MASK))) {
100ec099 1681 raise_exception_err_ra(env, EXCP0D_GPF, selector & 0xfffc, GETPC());
20054ef0 1682 }
eaa728ee 1683 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
20054ef0 1684 if (dpl > cpl) {
100ec099 1685 raise_exception_err_ra(env, EXCP0D_GPF, selector & 0xfffc, GETPC());
20054ef0 1686 }
0aca0605
AO		 1687#ifdef TARGET_X86_64
1688 if (env->efer & MSR_EFER_LMA) {
1689 if (!(e2 & DESC_L_MASK)) {
1690 raise_exception_err_ra(env, EXCP0D_GPF, selector & 0xfffc, GETPC());
1691 }
1692 if (e2 & DESC_B_MASK) {
1693 raise_exception_err_ra(env, EXCP0D_GPF, selector & 0xfffc, GETPC());
1694 }
1695 shift++;
1696 }
1697#endif
20054ef0 1698 if (!(e2 & DESC_P_MASK)) {
100ec099 1699 raise_exception_err_ra(env, EXCP0B_NOSEG, selector & 0xfffc, GETPC());
20054ef0 1700 }
eaa728ee
FB		 1701
1702 if (!(e2 & DESC_C_MASK) && dpl < cpl) {
1703 /* to inner privilege */
0aca0605
AO		 1704#ifdef TARGET_X86_64
1705 if (shift == 2) {
1706 sp = get_rsp_from_tss(env, dpl);
1707 ss = dpl; /* SS = NULL selector with RPL = new CPL */
1708 new_stack = 1;
1709 sp_mask = 0;
1710 ssp = 0; /* SS base is always zero in IA-32e mode */
1711 LOG_PCALL("new ss:rsp=%04x:%016llx env->regs[R_ESP]="
1712 TARGET_FMT_lx "\n", ss, sp, env->regs[R_ESP]);
1713 } else
1714#endif
1715 {
1716 uint32_t sp32;
1717 get_ss_esp_from_tss(env, &ss, &sp32, dpl, GETPC());
1718 LOG_PCALL("new ss:esp=%04x:%08x param_count=%d env->regs[R_ESP]="
1719 TARGET_FMT_lx "\n", ss, sp32, param_count,
1720 env->regs[R_ESP]);
1721 sp = sp32;
1722 if ((ss & 0xfffc) == 0) {
1723 raise_exception_err_ra(env, EXCP0A_TSS, ss & 0xfffc, GETPC());
1724 }
1725 if ((ss & 3) != dpl) {
1726 raise_exception_err_ra(env, EXCP0A_TSS, ss & 0xfffc, GETPC());
1727 }
1728 if (load_segment_ra(env, &ss_e1, &ss_e2, ss, GETPC()) != 0) {
1729 raise_exception_err_ra(env, EXCP0A_TSS, ss & 0xfffc, GETPC());
1730 }
1731 ss_dpl = (ss_e2 >> DESC_DPL_SHIFT) & 3;
1732 if (ss_dpl != dpl) {
1733 raise_exception_err_ra(env, EXCP0A_TSS, ss & 0xfffc, GETPC());
1734 }
1735 if (!(ss_e2 & DESC_S_MASK) ||
1736 (ss_e2 & DESC_CS_MASK) ||
1737 !(ss_e2 & DESC_W_MASK)) {
1738 raise_exception_err_ra(env, EXCP0A_TSS, ss & 0xfffc, GETPC());
1739 }
1740 if (!(ss_e2 & DESC_P_MASK)) {
1741 raise_exception_err_ra(env, EXCP0A_TSS, ss & 0xfffc, GETPC());
1742 }
1743
1744 sp_mask = get_sp_mask(ss_e2);
1745 ssp = get_seg_base(ss_e1, ss_e2);
20054ef0 1746 }
eaa728ee 1747
20054ef0 1748 /* push_size = ((param_count * 2) + 8) << shift; */
eaa728ee
FB		 1749
1750 old_sp_mask = get_sp_mask(env->segs[R_SS].flags);
1751 old_ssp = env->segs[R_SS].base;
0aca0605
AO		 1752#ifdef TARGET_X86_64
1753 if (shift == 2) {
1754 /* XXX: verify if new stack address is canonical */
1755 PUSHQ_RA(sp, env->segs[R_SS].selector, GETPC());
1756 PUSHQ_RA(sp, env->regs[R_ESP], GETPC());
1757 /* parameters aren't supported for 64-bit call gates */
1758 } else
1759#endif
1760 if (shift == 1) {
100ec099
PD		 1761 PUSHL_RA(ssp, sp, sp_mask, env->segs[R_SS].selector, GETPC());
1762 PUSHL_RA(ssp, sp, sp_mask, env->regs[R_ESP], GETPC());
20054ef0 1763 for (i = param_count - 1; i >= 0; i--) {
100ec099
PD		 1764 val = cpu_ldl_kernel_ra(env, old_ssp +
1765 ((env->regs[R_ESP] + i * 4) &
1766 old_sp_mask), GETPC());
1767 PUSHL_RA(ssp, sp, sp_mask, val, GETPC());
eaa728ee
FB		 1768 }
1769 } else {
100ec099
PD		 1770 PUSHW_RA(ssp, sp, sp_mask, env->segs[R_SS].selector, GETPC());
1771 PUSHW_RA(ssp, sp, sp_mask, env->regs[R_ESP], GETPC());
20054ef0 1772 for (i = param_count - 1; i >= 0; i--) {
100ec099
PD		 1773 val = cpu_lduw_kernel_ra(env, old_ssp +
1774 ((env->regs[R_ESP] + i * 2) &
1775 old_sp_mask), GETPC());
1776 PUSHW_RA(ssp, sp, sp_mask, val, GETPC());
eaa728ee
FB		 1777 }
1778 }
1779 new_stack = 1;
1780 } else {
1781 /* to same privilege */
08b3ded6 1782 sp = env->regs[R_ESP];
eaa728ee
FB		 1783 sp_mask = get_sp_mask(env->segs[R_SS].flags);
1784 ssp = env->segs[R_SS].base;
20054ef0 1785 /* push_size = (4 << shift); */
eaa728ee
FB		 1786 new_stack = 0;
1787 }
1788
0aca0605
AO		 1789#ifdef TARGET_X86_64
1790 if (shift == 2) {
1791 PUSHQ_RA(sp, env->segs[R_CS].selector, GETPC());
1792 PUSHQ_RA(sp, next_eip, GETPC());
1793 } else
1794#endif
1795 if (shift == 1) {
100ec099
PD		 1796 PUSHL_RA(ssp, sp, sp_mask, env->segs[R_CS].selector, GETPC());
1797 PUSHL_RA(ssp, sp, sp_mask, next_eip, GETPC());
eaa728ee 1798 } else {
100ec099
PD		 1799 PUSHW_RA(ssp, sp, sp_mask, env->segs[R_CS].selector, GETPC());
1800 PUSHW_RA(ssp, sp, sp_mask, next_eip, GETPC());
eaa728ee
FB		 1801 }
1802
1803 /* from this point, not restartable */
1804
1805 if (new_stack) {
0aca0605
AO		 1806#ifdef TARGET_X86_64
1807 if (shift == 2) {
1808 cpu_x86_load_seg_cache(env, R_SS, ss, 0, 0, 0);
1809 } else
1810#endif
1811 {
1812 ss = (ss & ~3) | dpl;
1813 cpu_x86_load_seg_cache(env, R_SS, ss,
1814 ssp,
1815 get_seg_limit(ss_e1, ss_e2),
1816 ss_e2);
1817 }
eaa728ee
FB		 1818 }
1819
1820 selector = (selector & ~3) | dpl;
1821 cpu_x86_load_seg_cache(env, R_CS, selector,
1822 get_seg_base(e1, e2),
1823 get_seg_limit(e1, e2),
1824 e2);
eaa728ee 1825 SET_ESP(sp, sp_mask);
a78d0eab 1826 env->eip = offset;
eaa728ee 1827 }
eaa728ee
FB		 1828}
1829
1830/* real and vm86 mode iret */
2999a0b2 1831void helper_iret_real(CPUX86State *env, int shift)
eaa728ee
FB		 1832{
1833 uint32_t sp, new_cs, new_eip, new_eflags, sp_mask;
1834 target_ulong ssp;
1835 int eflags_mask;
1836
20054ef0 1837 sp_mask = 0xffff; /* XXXX: use SS segment size? */
08b3ded6 1838 sp = env->regs[R_ESP];
eaa728ee
FB		 1839 ssp = env->segs[R_SS].base;
1840 if (shift == 1) {
1841 /* 32 bits */
100ec099
PD		 1842 POPL_RA(ssp, sp, sp_mask, new_eip, GETPC());
1843 POPL_RA(ssp, sp, sp_mask, new_cs, GETPC());
eaa728ee 1844 new_cs &= 0xffff;
100ec099 1845 POPL_RA(ssp, sp, sp_mask, new_eflags, GETPC());
eaa728ee
FB		 1846 } else {
1847 /* 16 bits */
100ec099
PD		 1848 POPW_RA(ssp, sp, sp_mask, new_eip, GETPC());
1849 POPW_RA(ssp, sp, sp_mask, new_cs, GETPC());
1850 POPW_RA(ssp, sp, sp_mask, new_eflags, GETPC());
eaa728ee 1851 }
08b3ded6 1852 env->regs[R_ESP] = (env->regs[R_ESP] & ~sp_mask) | (sp & sp_mask);
bdadc0b5 1853 env->segs[R_CS].selector = new_cs;
1854 env->segs[R_CS].base = (new_cs << 4);
eaa728ee 1855 env->eip = new_eip;
20054ef0
BS		 1856 if (env->eflags & VM_MASK) {
1857 eflags_mask = TF_MASK | AC_MASK | ID_MASK | IF_MASK | RF_MASK |
1858 NT_MASK;
1859 } else {
1860 eflags_mask = TF_MASK | AC_MASK | ID_MASK | IF_MASK | IOPL_MASK |
1861 RF_MASK | NT_MASK;
1862 }
1863 if (shift == 0) {
eaa728ee 1864 eflags_mask &= 0xffff;
20054ef0 1865 }
997ff0d9 1866 cpu_load_eflags(env, new_eflags, eflags_mask);
db620f46 1867 env->hflags2 &= ~HF2_NMI_MASK;
eaa728ee
FB		 1868}
1869
c117e5b1 1870static inline void validate_seg(CPUX86State *env, X86Seg seg_reg, int cpl)
eaa728ee
FB		 1871{
1872 int dpl;
1873 uint32_t e2;
1874
1875 /* XXX: on x86_64, we do not want to nullify FS and GS because
1876 they may still contain a valid base. I would be interested to
1877 know how a real x86_64 CPU behaves */
1878 if ((seg_reg == R_FS || seg_reg == R_GS) &&
20054ef0 1879 (env->segs[seg_reg].selector & 0xfffc) == 0) {
eaa728ee 1880 return;
20054ef0 1881 }
eaa728ee
FB		 1882
1883 e2 = env->segs[seg_reg].flags;
1884 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1885 if (!(e2 & DESC_CS_MASK) || !(e2 & DESC_C_MASK)) {
1886 /* data or non conforming code segment */
1887 if (dpl < cpl) {
c2ba0515
BM		 1888 cpu_x86_load_seg_cache(env, seg_reg, 0,
1889 env->segs[seg_reg].base,
1890 env->segs[seg_reg].limit,
1891 env->segs[seg_reg].flags & ~DESC_P_MASK);
eaa728ee
FB		 1892 }
1893 }
1894}
1895
1896/* protected mode iret */
2999a0b2 1897static inline void helper_ret_protected(CPUX86State *env, int shift,
100ec099
PD		 1898 int is_iret, int addend,
1899 uintptr_t retaddr)
eaa728ee
FB		 1900{
1901 uint32_t new_cs, new_eflags, new_ss;
1902 uint32_t new_es, new_ds, new_fs, new_gs;
1903 uint32_t e1, e2, ss_e1, ss_e2;
1904 int cpl, dpl, rpl, eflags_mask, iopl;
1905 target_ulong ssp, sp, new_eip, new_esp, sp_mask;
1906
1907#ifdef TARGET_X86_64
20054ef0 1908 if (shift == 2) {
eaa728ee 1909 sp_mask = -1;
20054ef0 1910 } else
eaa728ee 1911#endif
20054ef0 1912 {
eaa728ee 1913 sp_mask = get_sp_mask(env->segs[R_SS].flags);
20054ef0 1914 }
08b3ded6 1915 sp = env->regs[R_ESP];
eaa728ee
FB		 1916 ssp = env->segs[R_SS].base;
1917 new_eflags = 0; /* avoid warning */
1918#ifdef TARGET_X86_64
1919 if (shift == 2) {
100ec099
PD		 1920 POPQ_RA(sp, new_eip, retaddr);
1921 POPQ_RA(sp, new_cs, retaddr);
eaa728ee
FB		 1922 new_cs &= 0xffff;
1923 if (is_iret) {
100ec099 1924 POPQ_RA(sp, new_eflags, retaddr);
eaa728ee
FB		 1925 }
1926 } else
1927#endif
20054ef0
BS		 1928 {
1929 if (shift == 1) {
1930 /* 32 bits */
100ec099
PD		 1931 POPL_RA(ssp, sp, sp_mask, new_eip, retaddr);
1932 POPL_RA(ssp, sp, sp_mask, new_cs, retaddr);
20054ef0
BS		 1933 new_cs &= 0xffff;
1934 if (is_iret) {
100ec099 1935 POPL_RA(ssp, sp, sp_mask, new_eflags, retaddr);
20054ef0
BS		 1936 if (new_eflags & VM_MASK) {
1937 goto return_to_vm86;
1938 }
1939 }
1940 } else {
1941 /* 16 bits */
100ec099
PD		 1942 POPW_RA(ssp, sp, sp_mask, new_eip, retaddr);
1943 POPW_RA(ssp, sp, sp_mask, new_cs, retaddr);
20054ef0 1944 if (is_iret) {
100ec099 1945 POPW_RA(ssp, sp, sp_mask, new_eflags, retaddr);
20054ef0 1946 }
eaa728ee 1947 }
eaa728ee 1948 }
d12d51d5
AL		 1949 LOG_PCALL("lret new %04x:" TARGET_FMT_lx " s=%d addend=0x%x\n",
1950 new_cs, new_eip, shift, addend);
6aa9e42f 1951 LOG_PCALL_STATE(env_cpu(env));
20054ef0 1952 if ((new_cs & 0xfffc) == 0) {
100ec099 1953 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, retaddr);
20054ef0 1954 }
100ec099
PD		 1955 if (load_segment_ra(env, &e1, &e2, new_cs, retaddr) != 0) {
1956 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, retaddr);
20054ef0 1957 }
eaa728ee 1958 if (!(e2 & DESC_S_MASK) ||
20054ef0 1959 !(e2 & DESC_CS_MASK)) {
100ec099 1960 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, retaddr);
20054ef0 1961 }
eaa728ee
FB		 1962 cpl = env->hflags & HF_CPL_MASK;
1963 rpl = new_cs & 3;
20054ef0 1964 if (rpl < cpl) {
100ec099 1965 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, retaddr);
20054ef0 1966 }
eaa728ee
FB		 1967 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1968 if (e2 & DESC_C_MASK) {
20054ef0 1969 if (dpl > rpl) {
100ec099 1970 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, retaddr);
20054ef0 1971 }
eaa728ee 1972 } else {
20054ef0 1973 if (dpl != rpl) {
100ec099 1974 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, retaddr);
20054ef0 1975 }
eaa728ee 1976 }
20054ef0 1977 if (!(e2 & DESC_P_MASK)) {
100ec099 1978 raise_exception_err_ra(env, EXCP0B_NOSEG, new_cs & 0xfffc, retaddr);
20054ef0 1979 }
eaa728ee
FB		 1980
1981 sp += addend;
1982 if (rpl == cpl && (!(env->hflags & HF_CS64_MASK) ||
1983 ((env->hflags & HF_CS64_MASK) && !is_iret))) {
1235fc06 1984 /* return to same privilege level */
eaa728ee
FB		 1985 cpu_x86_load_seg_cache(env, R_CS, new_cs,
1986 get_seg_base(e1, e2),
1987 get_seg_limit(e1, e2),
1988 e2);
1989 } else {
1990 /* return to different privilege level */
1991#ifdef TARGET_X86_64
1992 if (shift == 2) {
100ec099
PD		 1993 POPQ_RA(sp, new_esp, retaddr);
1994 POPQ_RA(sp, new_ss, retaddr);
eaa728ee
FB		 1995 new_ss &= 0xffff;
1996 } else
1997#endif
20054ef0
BS		 1998 {
1999 if (shift == 1) {
2000 /* 32 bits */
100ec099
PD		 2001 POPL_RA(ssp, sp, sp_mask, new_esp, retaddr);
2002 POPL_RA(ssp, sp, sp_mask, new_ss, retaddr);
20054ef0
BS		 2003 new_ss &= 0xffff;
2004 } else {
2005 /* 16 bits */
100ec099
PD		 2006 POPW_RA(ssp, sp, sp_mask, new_esp, retaddr);
2007 POPW_RA(ssp, sp, sp_mask, new_ss, retaddr);
20054ef0 2008 }
eaa728ee 2009 }
d12d51d5 2010 LOG_PCALL("new ss:esp=%04x:" TARGET_FMT_lx "\n",
20054ef0 2011 new_ss, new_esp);
eaa728ee
FB		 2012 if ((new_ss & 0xfffc) == 0) {
2013#ifdef TARGET_X86_64
20054ef0
BS		 2014 /* NULL ss is allowed in long mode if cpl != 3 */
2015 /* XXX: test CS64? */
eaa728ee
FB		 2016 if ((env->hflags & HF_LMA_MASK) && rpl != 3) {
2017 cpu_x86_load_seg_cache(env, R_SS, new_ss,
2018 0, 0xffffffff,
2019 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
2020 DESC_S_MASK | (rpl << DESC_DPL_SHIFT) |
2021 DESC_W_MASK | DESC_A_MASK);
20054ef0 2022 ss_e2 = DESC_B_MASK; /* XXX: should not be needed? */
eaa728ee
FB		 2023 } else
2024#endif
2025 {
100ec099 2026 raise_exception_err_ra(env, EXCP0D_GPF, 0, retaddr);
eaa728ee
FB		 2027 }
2028 } else {
20054ef0 2029 if ((new_ss & 3) != rpl) {
100ec099 2030 raise_exception_err_ra(env, EXCP0D_GPF, new_ss & 0xfffc, retaddr);
20054ef0 2031 }
100ec099
PD		 2032 if (load_segment_ra(env, &ss_e1, &ss_e2, new_ss, retaddr) != 0) {
2033 raise_exception_err_ra(env, EXCP0D_GPF, new_ss & 0xfffc, retaddr);
20054ef0 2034 }
eaa728ee
FB		 2035 if (!(ss_e2 & DESC_S_MASK) ||
2036 (ss_e2 & DESC_CS_MASK) ||
20054ef0 2037 !(ss_e2 & DESC_W_MASK)) {
100ec099 2038 raise_exception_err_ra(env, EXCP0D_GPF, new_ss & 0xfffc, retaddr);
20054ef0 2039 }
eaa728ee 2040 dpl = (ss_e2 >> DESC_DPL_SHIFT) & 3;
20054ef0 2041 if (dpl != rpl) {
100ec099 2042 raise_exception_err_ra(env, EXCP0D_GPF, new_ss & 0xfffc, retaddr);
20054ef0
BS		 2043 }
2044 if (!(ss_e2 & DESC_P_MASK)) {
100ec099 2045 raise_exception_err_ra(env, EXCP0B_NOSEG, new_ss & 0xfffc, retaddr);
20054ef0 2046 }
eaa728ee
FB		 2047 cpu_x86_load_seg_cache(env, R_SS, new_ss,
2048 get_seg_base(ss_e1, ss_e2),
2049 get_seg_limit(ss_e1, ss_e2),
2050 ss_e2);
2051 }
2052
2053 cpu_x86_load_seg_cache(env, R_CS, new_cs,
2054 get_seg_base(e1, e2),
2055 get_seg_limit(e1, e2),
2056 e2);
eaa728ee
FB		 2057 sp = new_esp;
2058#ifdef TARGET_X86_64
20054ef0 2059 if (env->hflags & HF_CS64_MASK) {
eaa728ee 2060 sp_mask = -1;
20054ef0 2061 } else
eaa728ee 2062#endif
20054ef0 2063 {
eaa728ee 2064 sp_mask = get_sp_mask(ss_e2);
20054ef0 2065 }
eaa728ee
FB		 2066
2067 /* validate data segments */
2999a0b2
BS		 2068 validate_seg(env, R_ES, rpl);
2069 validate_seg(env, R_DS, rpl);
2070 validate_seg(env, R_FS, rpl);
2071 validate_seg(env, R_GS, rpl);
eaa728ee
FB		 2072
2073 sp += addend;
2074 }
2075 SET_ESP(sp, sp_mask);
2076 env->eip = new_eip;
2077 if (is_iret) {
2078 /* NOTE: 'cpl' is the _old_ CPL */
2079 eflags_mask = TF_MASK | AC_MASK | ID_MASK | RF_MASK | NT_MASK;
20054ef0 2080 if (cpl == 0) {
eaa728ee 2081 eflags_mask |= IOPL_MASK;
20054ef0 2082 }
eaa728ee 2083 iopl = (env->eflags >> IOPL_SHIFT) & 3;
20054ef0 2084 if (cpl <= iopl) {
eaa728ee 2085 eflags_mask |= IF_MASK;
20054ef0
BS		 2086 }
2087 if (shift == 0) {
eaa728ee 2088 eflags_mask &= 0xffff;
20054ef0 2089 }
997ff0d9 2090 cpu_load_eflags(env, new_eflags, eflags_mask);
eaa728ee
FB		 2091 }
2092 return;
2093
2094 return_to_vm86:
100ec099
PD		 2095 POPL_RA(ssp, sp, sp_mask, new_esp, retaddr);
2096 POPL_RA(ssp, sp, sp_mask, new_ss, retaddr);
2097 POPL_RA(ssp, sp, sp_mask, new_es, retaddr);
2098 POPL_RA(ssp, sp, sp_mask, new_ds, retaddr);
2099 POPL_RA(ssp, sp, sp_mask, new_fs, retaddr);
2100 POPL_RA(ssp, sp, sp_mask, new_gs, retaddr);
eaa728ee
FB		 2101
2102 /* modify processor state */
997ff0d9
BS		 2103 cpu_load_eflags(env, new_eflags, TF_MASK | AC_MASK | ID_MASK |
2104 IF_MASK | IOPL_MASK | VM_MASK | NT_MASK | VIF_MASK |
2105 VIP_MASK);
2999a0b2 2106 load_seg_vm(env, R_CS, new_cs & 0xffff);
2999a0b2
BS		 2107 load_seg_vm(env, R_SS, new_ss & 0xffff);
2108 load_seg_vm(env, R_ES, new_es & 0xffff);
2109 load_seg_vm(env, R_DS, new_ds & 0xffff);
2110 load_seg_vm(env, R_FS, new_fs & 0xffff);
2111 load_seg_vm(env, R_GS, new_gs & 0xffff);
eaa728ee
FB		 2112
2113 env->eip = new_eip & 0xffff;
08b3ded6 2114 env->regs[R_ESP] = new_esp;
eaa728ee
FB		 2115}
2116
2999a0b2 2117void helper_iret_protected(CPUX86State *env, int shift, int next_eip)
eaa728ee
FB		 2118{
2119 int tss_selector, type;
2120 uint32_t e1, e2;
2121
2122 /* specific case for TSS */
2123 if (env->eflags & NT_MASK) {
2124#ifdef TARGET_X86_64
20054ef0 2125 if (env->hflags & HF_LMA_MASK) {
100ec099 2126 raise_exception_err_ra(env, EXCP0D_GPF, 0, GETPC());
20054ef0 2127 }
eaa728ee 2128#endif
100ec099 2129 tss_selector = cpu_lduw_kernel_ra(env, env->tr.base + 0, GETPC());
20054ef0 2130 if (tss_selector & 4) {
100ec099 2131 raise_exception_err_ra(env, EXCP0A_TSS, tss_selector & 0xfffc, GETPC());
20054ef0 2132 }
100ec099
PD		 2133 if (load_segment_ra(env, &e1, &e2, tss_selector, GETPC()) != 0) {
2134 raise_exception_err_ra(env, EXCP0A_TSS, tss_selector & 0xfffc, GETPC());
20054ef0 2135 }
eaa728ee
FB		 2136 type = (e2 >> DESC_TYPE_SHIFT) & 0x17;
2137 /* NOTE: we check both segment and busy TSS */
20054ef0 2138 if (type != 3) {
100ec099 2139 raise_exception_err_ra(env, EXCP0A_TSS, tss_selector & 0xfffc, GETPC());
20054ef0 2140 }
100ec099 2141 switch_tss_ra(env, tss_selector, e1, e2, SWITCH_TSS_IRET, next_eip, GETPC());
eaa728ee 2142 } else {
100ec099 2143 helper_ret_protected(env, shift, 1, 0, GETPC());
eaa728ee 2144 }
db620f46 2145 env->hflags2 &= ~HF2_NMI_MASK;
eaa728ee
FB		 2146}
2147
2999a0b2 2148void helper_lret_protected(CPUX86State *env, int shift, int addend)
eaa728ee 2149{
100ec099 2150 helper_ret_protected(env, shift, 0, addend, GETPC());
eaa728ee
FB		 2151}
2152
2999a0b2 2153void helper_sysenter(CPUX86State *env)
eaa728ee
FB		 2154{
2155 if (env->sysenter_cs == 0) {
100ec099 2156 raise_exception_err_ra(env, EXCP0D_GPF, 0, GETPC());
eaa728ee
FB		 2157 }
2158 env->eflags &= ~(VM_MASK | IF_MASK | RF_MASK);
2436b61a
AZ		 2159
2160#ifdef TARGET_X86_64
2161 if (env->hflags & HF_LMA_MASK) {
2162 cpu_x86_load_seg_cache(env, R_CS, env->sysenter_cs & 0xfffc,
2163 0, 0xffffffff,
2164 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
2165 DESC_S_MASK |
20054ef0
BS		 2166 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK |
2167 DESC_L_MASK);
2436b61a
AZ		 2168 } else
2169#endif
2170 {
2171 cpu_x86_load_seg_cache(env, R_CS, env->sysenter_cs & 0xfffc,
2172 0, 0xffffffff,
2173 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
2174 DESC_S_MASK |
2175 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK);
2176 }
eaa728ee
FB		 2177 cpu_x86_load_seg_cache(env, R_SS, (env->sysenter_cs + 8) & 0xfffc,
2178 0, 0xffffffff,
2179 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
2180 DESC_S_MASK |
2181 DESC_W_MASK | DESC_A_MASK);
08b3ded6 2182 env->regs[R_ESP] = env->sysenter_esp;
a78d0eab 2183 env->eip = env->sysenter_eip;
eaa728ee
FB		 2184}
2185
2999a0b2 2186void helper_sysexit(CPUX86State *env, int dflag)
eaa728ee
FB		 2187{
2188 int cpl;
2189
2190 cpl = env->hflags & HF_CPL_MASK;
2191 if (env->sysenter_cs == 0 || cpl != 0) {
100ec099 2192 raise_exception_err_ra(env, EXCP0D_GPF, 0, GETPC());
eaa728ee 2193 }
2436b61a
AZ		 2194#ifdef TARGET_X86_64
2195 if (dflag == 2) {
20054ef0
BS		 2196 cpu_x86_load_seg_cache(env, R_CS, ((env->sysenter_cs + 32) & 0xfffc) |
2197 3, 0, 0xffffffff,
2436b61a
AZ		 2198 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
2199 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
20054ef0
BS		 2200 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK |
2201 DESC_L_MASK);
2202 cpu_x86_load_seg_cache(env, R_SS, ((env->sysenter_cs + 40) & 0xfffc) |
2203 3, 0, 0xffffffff,
2436b61a
AZ		 2204 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
2205 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
2206 DESC_W_MASK | DESC_A_MASK);
2207 } else
2208#endif
2209 {
20054ef0
BS		 2210 cpu_x86_load_seg_cache(env, R_CS, ((env->sysenter_cs + 16) & 0xfffc) |
2211 3, 0, 0xffffffff,
2436b61a
AZ		 2212 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
2213 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
2214 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK);
20054ef0
BS		 2215 cpu_x86_load_seg_cache(env, R_SS, ((env->sysenter_cs + 24) & 0xfffc) |
2216 3, 0, 0xffffffff,
2436b61a
AZ		 2217 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
2218 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
2219 DESC_W_MASK | DESC_A_MASK);
2220 }
08b3ded6 2221 env->regs[R_ESP] = env->regs[R_ECX];
a78d0eab 2222 env->eip = env->regs[R_EDX];
eaa728ee
FB		 2223}
2224
2999a0b2 2225target_ulong helper_lsl(CPUX86State *env, target_ulong selector1)
eaa728ee
FB		 2226{
2227 unsigned int limit;
2228 uint32_t e1, e2, eflags, selector;
2229 int rpl, dpl, cpl, type;
2230
2231 selector = selector1 & 0xffff;
f0967a1a 2232 eflags = cpu_cc_compute_all(env, CC_OP);
20054ef0 2233 if ((selector & 0xfffc) == 0) {
dc1ded53 2234 goto fail;
20054ef0 2235 }
100ec099 2236 if (load_segment_ra(env, &e1, &e2, selector, GETPC()) != 0) {
eaa728ee 2237 goto fail;
20054ef0 2238 }
eaa728ee
FB		 2239 rpl = selector & 3;
2240 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2241 cpl = env->hflags & HF_CPL_MASK;
2242 if (e2 & DESC_S_MASK) {
2243 if ((e2 & DESC_CS_MASK) && (e2 & DESC_C_MASK)) {
2244 /* conforming */
2245 } else {
20054ef0 2246 if (dpl < cpl || dpl < rpl) {
eaa728ee 2247 goto fail;
20054ef0 2248 }
eaa728ee
FB		 2249 }
2250 } else {
2251 type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
20054ef0 2252 switch (type) {
eaa728ee
FB		 2253 case 1:
2254 case 2:
2255 case 3:
2256 case 9:
2257 case 11:
2258 break;
2259 default:
2260 goto fail;
2261 }
2262 if (dpl < cpl || dpl < rpl) {
2263 fail:
2264 CC_SRC = eflags & ~CC_Z;
2265 return 0;
2266 }
2267 }
2268 limit = get_seg_limit(e1, e2);
2269 CC_SRC = eflags | CC_Z;
2270 return limit;
2271}
2272
2999a0b2 2273target_ulong helper_lar(CPUX86State *env, target_ulong selector1)
eaa728ee
FB		 2274{
2275 uint32_t e1, e2, eflags, selector;
2276 int rpl, dpl, cpl, type;
2277
2278 selector = selector1 & 0xffff;
f0967a1a 2279 eflags = cpu_cc_compute_all(env, CC_OP);
20054ef0 2280 if ((selector & 0xfffc) == 0) {
eaa728ee 2281 goto fail;
20054ef0 2282 }
100ec099 2283 if (load_segment_ra(env, &e1, &e2, selector, GETPC()) != 0) {
eaa728ee 2284 goto fail;
20054ef0 2285 }
eaa728ee
FB		 2286 rpl = selector & 3;
2287 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2288 cpl = env->hflags & HF_CPL_MASK;
2289 if (e2 & DESC_S_MASK) {
2290 if ((e2 & DESC_CS_MASK) && (e2 & DESC_C_MASK)) {
2291 /* conforming */
2292 } else {
20054ef0 2293 if (dpl < cpl || dpl < rpl) {
eaa728ee 2294 goto fail;
20054ef0 2295 }
eaa728ee
FB		 2296 }
2297 } else {
2298 type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
20054ef0 2299 switch (type) {
eaa728ee
FB		 2300 case 1:
2301 case 2:
2302 case 3:
2303 case 4:
2304 case 5:
2305 case 9:
2306 case 11:
2307 case 12:
2308 break;
2309 default:
2310 goto fail;
2311 }
2312 if (dpl < cpl || dpl < rpl) {
2313 fail:
2314 CC_SRC = eflags & ~CC_Z;
2315 return 0;
2316 }
2317 }
2318 CC_SRC = eflags | CC_Z;
2319 return e2 & 0x00f0ff00;
2320}
2321
2999a0b2 2322void helper_verr(CPUX86State *env, target_ulong selector1)
eaa728ee
FB		 2323{
2324 uint32_t e1, e2, eflags, selector;
2325 int rpl, dpl, cpl;
2326
2327 selector = selector1 & 0xffff;
f0967a1a 2328 eflags = cpu_cc_compute_all(env, CC_OP);
20054ef0 2329 if ((selector & 0xfffc) == 0) {
eaa728ee 2330 goto fail;
20054ef0 2331 }
100ec099 2332 if (load_segment_ra(env, &e1, &e2, selector, GETPC()) != 0) {
eaa728ee 2333 goto fail;
20054ef0
BS		 2334 }
2335 if (!(e2 & DESC_S_MASK)) {
eaa728ee 2336 goto fail;
20054ef0 2337 }
eaa728ee
FB		 2338 rpl = selector & 3;
2339 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2340 cpl = env->hflags & HF_CPL_MASK;
2341 if (e2 & DESC_CS_MASK) {
20054ef0 2342 if (!(e2 & DESC_R_MASK)) {
eaa728ee 2343 goto fail;
20054ef0 2344 }
eaa728ee 2345 if (!(e2 & DESC_C_MASK)) {
20054ef0 2346 if (dpl < cpl || dpl < rpl) {
eaa728ee 2347 goto fail;
20054ef0 2348 }
eaa728ee
FB		 2349 }
2350 } else {
2351 if (dpl < cpl || dpl < rpl) {
2352 fail:
2353 CC_SRC = eflags & ~CC_Z;
2354 return;
2355 }
2356 }
2357 CC_SRC = eflags | CC_Z;
2358}
2359
2999a0b2 2360void helper_verw(CPUX86State *env, target_ulong selector1)
eaa728ee
FB		 2361{
2362 uint32_t e1, e2, eflags, selector;
2363 int rpl, dpl, cpl;
2364
2365 selector = selector1 & 0xffff;
f0967a1a 2366 eflags = cpu_cc_compute_all(env, CC_OP);
20054ef0 2367 if ((selector & 0xfffc) == 0) {
eaa728ee 2368 goto fail;
20054ef0 2369 }
100ec099 2370 if (load_segment_ra(env, &e1, &e2, selector, GETPC()) != 0) {
eaa728ee 2371 goto fail;
20054ef0
BS		 2372 }
2373 if (!(e2 & DESC_S_MASK)) {
eaa728ee 2374 goto fail;
20054ef0 2375 }
eaa728ee
FB		 2376 rpl = selector & 3;
2377 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2378 cpl = env->hflags & HF_CPL_MASK;
2379 if (e2 & DESC_CS_MASK) {
2380 goto fail;
2381 } else {
20054ef0 2382 if (dpl < cpl || dpl < rpl) {
eaa728ee 2383 goto fail;
20054ef0 2384 }
eaa728ee
FB		 2385 if (!(e2 & DESC_W_MASK)) {
2386 fail:
2387 CC_SRC = eflags & ~CC_Z;
2388 return;
2389 }
2390 }
2391 CC_SRC = eflags | CC_Z;
2392}
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