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ed69e831 CF |
1 | /* |
2 | * i386 TCG cpu class initialization | |
3 | * | |
4 | * Copyright (c) 2003 Fabrice Bellard | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #include "qemu/osdep.h" | |
21 | #include "cpu.h" | |
ed69e831 | 22 | #include "helper-tcg.h" |
f5cc5a5c CF |
23 | #include "qemu/accel.h" |
24 | #include "hw/core/accel-cpu.h" | |
ed69e831 | 25 | |
222f3e6f | 26 | #include "tcg-cpu.h" |
ed69e831 CF |
27 | |
28 | /* Frob eflags into and out of the CPU temporary format. */ | |
29 | ||
30 | static void x86_cpu_exec_enter(CPUState *cs) | |
31 | { | |
32 | X86CPU *cpu = X86_CPU(cs); | |
33 | CPUX86State *env = &cpu->env; | |
34 | ||
35 | CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); | |
36 | env->df = 1 - (2 * ((env->eflags >> 10) & 1)); | |
37 | CC_OP = CC_OP_EFLAGS; | |
38 | env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); | |
39 | } | |
40 | ||
41 | static void x86_cpu_exec_exit(CPUState *cs) | |
42 | { | |
43 | X86CPU *cpu = X86_CPU(cs); | |
44 | CPUX86State *env = &cpu->env; | |
45 | ||
46 | env->eflags = cpu_compute_eflags(env); | |
47 | } | |
48 | ||
04a37d4c RH |
49 | static void x86_cpu_synchronize_from_tb(CPUState *cs, |
50 | const TranslationBlock *tb) | |
ed69e831 | 51 | { |
2e3afe8e AJ |
52 | /* The instruction pointer is always up to date with CF_PCREL. */ |
53 | if (!(tb_cflags(tb) & CF_PCREL)) { | |
b77af26e | 54 | CPUX86State *env = cpu_env(cs); |
b5e0d5d2 RH |
55 | |
56 | if (tb->flags & HF_CS64_MASK) { | |
57 | env->eip = tb->pc; | |
58 | } else { | |
59 | env->eip = (uint32_t)(tb->pc - tb->cs_base); | |
60 | } | |
e3a79e0e | 61 | } |
ed69e831 CF |
62 | } |
63 | ||
434382e6 RH |
64 | static void x86_restore_state_to_opc(CPUState *cs, |
65 | const TranslationBlock *tb, | |
66 | const uint64_t *data) | |
67 | { | |
68 | X86CPU *cpu = X86_CPU(cs); | |
69 | CPUX86State *env = &cpu->env; | |
70 | int cc_op = data[1]; | |
729ba8e9 | 71 | uint64_t new_pc; |
434382e6 | 72 | |
2e3afe8e | 73 | if (tb_cflags(tb) & CF_PCREL) { |
729ba8e9 PB |
74 | /* |
75 | * data[0] in PC-relative TBs is also a linear address, i.e. an address with | |
76 | * the CS base added, because it is not guaranteed that EIP bits 12 and higher | |
77 | * stay the same across the translation block. Add the CS base back before | |
78 | * replacing the low bits, and subtract it below just like for !CF_PCREL. | |
79 | */ | |
80 | uint64_t pc = env->eip + tb->cs_base; | |
81 | new_pc = (pc & TARGET_PAGE_MASK) | data[0]; | |
434382e6 | 82 | } else { |
729ba8e9 | 83 | new_pc = data[0]; |
434382e6 | 84 | } |
729ba8e9 PB |
85 | if (tb->flags & HF_CS64_MASK) { |
86 | env->eip = new_pc; | |
87 | } else { | |
88 | env->eip = (uint32_t)(new_pc - tb->cs_base); | |
89 | } | |
90 | ||
434382e6 RH |
91 | if (cc_op != CC_OP_DYNAMIC) { |
92 | env->cc_op = cc_op; | |
93 | } | |
94 | } | |
95 | ||
7b9810ea RH |
96 | #ifndef CONFIG_USER_ONLY |
97 | static bool x86_debug_check_breakpoint(CPUState *cs) | |
98 | { | |
99 | X86CPU *cpu = X86_CPU(cs); | |
100 | CPUX86State *env = &cpu->env; | |
101 | ||
102 | /* RF disables all architectural breakpoints. */ | |
103 | return !(env->eflags & RF_MASK); | |
104 | } | |
105 | #endif | |
106 | ||
78271684 CF |
107 | #include "hw/core/tcg-cpu-ops.h" |
108 | ||
1764ad70 | 109 | static const TCGCPUOps x86_tcg_ops = { |
78271684 CF |
110 | .initialize = tcg_x86_init, |
111 | .synchronize_from_tb = x86_cpu_synchronize_from_tb, | |
434382e6 | 112 | .restore_state_to_opc = x86_restore_state_to_opc, |
78271684 CF |
113 | .cpu_exec_enter = x86_cpu_exec_enter, |
114 | .cpu_exec_exit = x86_cpu_exec_exit, | |
12096421 PMD |
115 | #ifdef CONFIG_USER_ONLY |
116 | .fake_user_interrupt = x86_cpu_do_interrupt, | |
f74bd157 | 117 | .record_sigsegv = x86_cpu_record_sigsegv, |
958e1dd1 | 118 | .record_sigbus = x86_cpu_record_sigbus, |
12096421 | 119 | #else |
f74bd157 | 120 | .tlb_fill = x86_cpu_tlb_fill, |
12096421 | 121 | .do_interrupt = x86_cpu_do_interrupt, |
60466472 | 122 | .cpu_exec_interrupt = x86_cpu_exec_interrupt, |
958e1dd1 | 123 | .do_unaligned_access = x86_cpu_do_unaligned_access, |
78271684 | 124 | .debug_excp_handler = breakpoint_handler, |
7b9810ea | 125 | .debug_check_breakpoint = x86_debug_check_breakpoint, |
6ae75481 | 126 | .need_replay_interrupt = x86_need_replay_interrupt, |
78271684 CF |
127 | #endif /* !CONFIG_USER_ONLY */ |
128 | }; | |
129 | ||
e129593f | 130 | static void x86_tcg_cpu_init_ops(AccelCPUClass *accel_cpu, CPUClass *cc) |
ed69e831 | 131 | { |
cc3f2be6 | 132 | /* for x86, all cpus use the same set of operations */ |
78271684 | 133 | cc->tcg_ops = &x86_tcg_ops; |
ed69e831 | 134 | } |
f5cc5a5c | 135 | |
e129593f | 136 | static void x86_tcg_cpu_class_init(CPUClass *cc) |
cc3f2be6 | 137 | { |
e129593f | 138 | cc->init_accel_cpu = x86_tcg_cpu_init_ops; |
cc3f2be6 CF |
139 | } |
140 | ||
e129593f | 141 | static void x86_tcg_cpu_xsave_init(void) |
fea45008 DE |
142 | { |
143 | #define XO(bit, field) \ | |
144 | x86_ext_save_areas[bit].offset = offsetof(X86XSaveArea, field); | |
145 | ||
146 | XO(XSTATE_FP_BIT, legacy); | |
147 | XO(XSTATE_SSE_BIT, legacy); | |
148 | XO(XSTATE_YMM_BIT, avx_state); | |
149 | XO(XSTATE_BNDREGS_BIT, bndreg_state); | |
150 | XO(XSTATE_BNDCSR_BIT, bndcsr_state); | |
151 | XO(XSTATE_OPMASK_BIT, opmask_state); | |
152 | XO(XSTATE_ZMM_Hi256_BIT, zmm_hi256_state); | |
153 | XO(XSTATE_Hi16_ZMM_BIT, hi16_zmm_state); | |
154 | XO(XSTATE_PKRU_BIT, pkru_state); | |
155 | ||
156 | #undef XO | |
157 | } | |
158 | ||
f5cc5a5c | 159 | /* |
5b8978d8 CF |
160 | * TCG-specific defaults that override cpudef models when using TCG. |
161 | * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. | |
f5cc5a5c | 162 | */ |
e129593f | 163 | static PropValue x86_tcg_default_props[] = { |
f5cc5a5c CF |
164 | { "vme", "off" }, |
165 | { NULL, NULL }, | |
166 | }; | |
167 | ||
e129593f | 168 | static void x86_tcg_cpu_instance_init(CPUState *cs) |
f5cc5a5c CF |
169 | { |
170 | X86CPU *cpu = X86_CPU(cs); | |
5b8978d8 CF |
171 | X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu); |
172 | ||
173 | if (xcc->model) { | |
174 | /* Special cases not set in the X86CPUDefinition structs: */ | |
e129593f | 175 | x86_cpu_apply_props(cpu, x86_tcg_default_props); |
5b8978d8 | 176 | } |
fea45008 | 177 | |
e129593f | 178 | x86_tcg_cpu_xsave_init(); |
f5cc5a5c CF |
179 | } |
180 | ||
e129593f | 181 | static void x86_tcg_cpu_accel_class_init(ObjectClass *oc, void *data) |
f5cc5a5c CF |
182 | { |
183 | AccelCPUClass *acc = ACCEL_CPU_CLASS(oc); | |
184 | ||
222f3e6f | 185 | #ifndef CONFIG_USER_ONLY |
6294e502 | 186 | acc->cpu_target_realize = tcg_cpu_realizefn; |
222f3e6f PB |
187 | #endif /* CONFIG_USER_ONLY */ |
188 | ||
e129593f PMD |
189 | acc->cpu_class_init = x86_tcg_cpu_class_init; |
190 | acc->cpu_instance_init = x86_tcg_cpu_instance_init; | |
f5cc5a5c | 191 | } |
e129593f | 192 | static const TypeInfo x86_tcg_cpu_accel_type_info = { |
f5cc5a5c CF |
193 | .name = ACCEL_CPU_NAME("tcg"), |
194 | ||
195 | .parent = TYPE_ACCEL_CPU, | |
e129593f | 196 | .class_init = x86_tcg_cpu_accel_class_init, |
f5cc5a5c CF |
197 | .abstract = true, |
198 | }; | |
e129593f | 199 | static void x86_tcg_cpu_accel_register_types(void) |
f5cc5a5c | 200 | { |
e129593f | 201 | type_register_static(&x86_tcg_cpu_accel_type_info); |
f5cc5a5c | 202 | } |
e129593f | 203 | type_init(x86_tcg_cpu_accel_register_types); |