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81ea0e13 MW |
1 | /* |
2 | * LatticeMico32 virtual CPU header. | |
3 | * | |
4 | * Copyright (c) 2010 Michael Walle <michael@walle.cc> | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
07f5a258 MA |
20 | #ifndef LM32_CPU_H |
21 | #define LM32_CPU_H | |
81ea0e13 | 22 | |
81ea0e13 | 23 | #include "qemu-common.h" |
6adb9c54 | 24 | #include "cpu-qom.h" |
022c62cb | 25 | #include "exec/cpu-defs.h" |
74433bf0 RH |
26 | |
27 | #define CPUArchState struct CPULM32State | |
28 | ||
81ea0e13 | 29 | struct CPULM32State; |
9b9a970a | 30 | typedef struct CPULM32State CPULM32State; |
81ea0e13 | 31 | |
97ed5ccd | 32 | static inline int cpu_mmu_index(CPULM32State *env, bool ifetch) |
81ea0e13 MW |
33 | { |
34 | return 0; | |
35 | } | |
36 | ||
81ea0e13 MW |
37 | /* Exceptions indices */ |
38 | enum { | |
39 | EXCP_RESET = 0, | |
40 | EXCP_BREAKPOINT, | |
41 | EXCP_INSN_BUS_ERROR, | |
42 | EXCP_WATCHPOINT, | |
43 | EXCP_DATA_BUS_ERROR, | |
44 | EXCP_DIVIDE_BY_ZERO, | |
45 | EXCP_IRQ, | |
46 | EXCP_SYSTEMCALL | |
47 | }; | |
48 | ||
49 | /* Registers */ | |
50 | enum { | |
51 | R_R0 = 0, R_R1, R_R2, R_R3, R_R4, R_R5, R_R6, R_R7, R_R8, R_R9, R_R10, | |
52 | R_R11, R_R12, R_R13, R_R14, R_R15, R_R16, R_R17, R_R18, R_R19, R_R20, | |
53 | R_R21, R_R22, R_R23, R_R24, R_R25, R_R26, R_R27, R_R28, R_R29, R_R30, | |
54 | R_R31 | |
55 | }; | |
56 | ||
57 | /* Register aliases */ | |
58 | enum { | |
59 | R_GP = R_R26, | |
60 | R_FP = R_R27, | |
61 | R_SP = R_R28, | |
62 | R_RA = R_R29, | |
63 | R_EA = R_R30, | |
64 | R_BA = R_R31 | |
65 | }; | |
66 | ||
67 | /* IE flags */ | |
68 | enum { | |
69 | IE_IE = (1<<0), | |
70 | IE_EIE = (1<<1), | |
71 | IE_BIE = (1<<2), | |
72 | }; | |
73 | ||
74 | /* DC flags */ | |
75 | enum { | |
76 | DC_SS = (1<<0), | |
77 | DC_RE = (1<<1), | |
78 | DC_C0 = (1<<2), | |
79 | DC_C1 = (1<<3), | |
80 | DC_C2 = (1<<4), | |
81 | DC_C3 = (1<<5), | |
82 | }; | |
83 | ||
84 | /* CFG mask */ | |
85 | enum { | |
86 | CFG_M = (1<<0), | |
87 | CFG_D = (1<<1), | |
88 | CFG_S = (1<<2), | |
89 | CFG_U = (1<<3), | |
90 | CFG_X = (1<<4), | |
91 | CFG_CC = (1<<5), | |
92 | CFG_IC = (1<<6), | |
93 | CFG_DC = (1<<7), | |
94 | CFG_G = (1<<8), | |
95 | CFG_H = (1<<9), | |
96 | CFG_R = (1<<10), | |
97 | CFG_J = (1<<11), | |
98 | CFG_INT_SHIFT = 12, | |
99 | CFG_BP_SHIFT = 18, | |
100 | CFG_WP_SHIFT = 22, | |
101 | CFG_REV_SHIFT = 26, | |
102 | }; | |
103 | ||
104 | /* CSRs */ | |
105 | enum { | |
106 | CSR_IE = 0x00, | |
107 | CSR_IM = 0x01, | |
108 | CSR_IP = 0x02, | |
109 | CSR_ICC = 0x03, | |
110 | CSR_DCC = 0x04, | |
111 | CSR_CC = 0x05, | |
112 | CSR_CFG = 0x06, | |
113 | CSR_EBA = 0x07, | |
114 | CSR_DC = 0x08, | |
115 | CSR_DEBA = 0x09, | |
116 | CSR_JTX = 0x0e, | |
117 | CSR_JRX = 0x0f, | |
118 | CSR_BP0 = 0x10, | |
119 | CSR_BP1 = 0x11, | |
120 | CSR_BP2 = 0x12, | |
121 | CSR_BP3 = 0x13, | |
122 | CSR_WP0 = 0x18, | |
123 | CSR_WP1 = 0x19, | |
124 | CSR_WP2 = 0x1a, | |
125 | CSR_WP3 = 0x1b, | |
126 | }; | |
127 | ||
128 | enum { | |
129 | LM32_FEATURE_MULTIPLY = 1, | |
130 | LM32_FEATURE_DIVIDE = 2, | |
131 | LM32_FEATURE_SHIFT = 4, | |
132 | LM32_FEATURE_SIGN_EXTEND = 8, | |
133 | LM32_FEATURE_I_CACHE = 16, | |
134 | LM32_FEATURE_D_CACHE = 32, | |
135 | LM32_FEATURE_CYCLE_COUNT = 64, | |
136 | }; | |
137 | ||
138 | enum { | |
139 | LM32_FLAG_IGNORE_MSB = 1, | |
140 | }; | |
141 | ||
ae7d54d4 | 142 | struct CPULM32State { |
81ea0e13 MW |
143 | /* general registers */ |
144 | uint32_t regs[32]; | |
145 | ||
146 | /* special registers */ | |
147 | uint32_t pc; /* program counter */ | |
148 | uint32_t ie; /* interrupt enable */ | |
149 | uint32_t icc; /* instruction cache control */ | |
150 | uint32_t dcc; /* data cache control */ | |
151 | uint32_t cc; /* cycle counter */ | |
152 | uint32_t cfg; /* configuration */ | |
153 | ||
154 | /* debug registers */ | |
155 | uint32_t dc; /* debug control */ | |
3dd3a2b9 MW |
156 | uint32_t bp[4]; /* breakpoints */ |
157 | uint32_t wp[4]; /* watchpoints */ | |
158 | ||
f0c3c505 | 159 | struct CPUBreakpoint *cpu_breakpoint[4]; |
ff4700b0 | 160 | struct CPUWatchpoint *cpu_watchpoint[4]; |
81ea0e13 | 161 | |
1f5c00cf AB |
162 | /* Fields up to this point are cleared by a CPU reset */ |
163 | struct {} end_reset_fields; | |
164 | ||
81ea0e13 MW |
165 | CPU_COMMON |
166 | ||
f0c3c505 | 167 | /* Fields from here on are preserved across CPU reset. */ |
81ea0e13 MW |
168 | uint32_t eba; /* exception base address */ |
169 | uint32_t deba; /* debug exception base address */ | |
170 | ||
171 | /* interrupt controller handle for callbacks */ | |
172 | DeviceState *pic_state; | |
173 | /* JTAG UART handle for callbacks */ | |
174 | DeviceState *juart_state; | |
175 | ||
176 | /* processor core features */ | |
81ea0e13 | 177 | uint32_t flags; |
81ea0e13 | 178 | |
ae7d54d4 | 179 | }; |
81ea0e13 | 180 | |
6adb9c54 PB |
181 | /** |
182 | * LM32CPU: | |
183 | * @env: #CPULM32State | |
184 | * | |
185 | * A LatticeMico32 CPU. | |
186 | */ | |
187 | struct LM32CPU { | |
188 | /*< private >*/ | |
189 | CPUState parent_obj; | |
190 | /*< public >*/ | |
191 | ||
192 | CPULM32State env; | |
193 | ||
194 | uint32_t revision; | |
195 | uint8_t num_interrupts; | |
196 | uint8_t num_breakpoints; | |
197 | uint8_t num_watchpoints; | |
198 | uint32_t features; | |
199 | }; | |
200 | ||
201 | static inline LM32CPU *lm32_env_get_cpu(CPULM32State *env) | |
202 | { | |
203 | return container_of(env, LM32CPU, env); | |
204 | } | |
205 | ||
206 | #define ENV_GET_CPU(e) CPU(lm32_env_get_cpu(e)) | |
207 | ||
208 | #define ENV_OFFSET offsetof(LM32CPU, env) | |
209 | ||
210 | #ifndef CONFIG_USER_ONLY | |
211 | extern const struct VMStateDescription vmstate_lm32_cpu; | |
212 | #endif | |
213 | ||
214 | void lm32_cpu_do_interrupt(CPUState *cpu); | |
215 | bool lm32_cpu_exec_interrupt(CPUState *cs, int int_req); | |
90c84c56 | 216 | void lm32_cpu_dump_state(CPUState *cpu, FILE *f, int flags); |
6adb9c54 PB |
217 | hwaddr lm32_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); |
218 | int lm32_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); | |
219 | int lm32_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); | |
220 | ||
3dd3a2b9 MW |
221 | typedef enum { |
222 | LM32_WP_DISABLED = 0, | |
223 | LM32_WP_READ, | |
224 | LM32_WP_WRITE, | |
225 | LM32_WP_READ_WRITE, | |
226 | } lm32_wp_t; | |
227 | ||
228 | static inline lm32_wp_t lm32_wp_type(uint32_t dc, int idx) | |
229 | { | |
230 | assert(idx < 4); | |
231 | return (dc >> (idx+1)*2) & 0x3; | |
232 | } | |
233 | ||
81ea0e13 MW |
234 | /* you can call this signal handler from your SIGBUS and SIGSEGV |
235 | signal handlers to inform the virtual CPU of exceptions. non zero | |
236 | is returned if the signal was handled by the virtual CPU. */ | |
237 | int cpu_lm32_signal_handler(int host_signum, void *pinfo, | |
238 | void *puc); | |
0442428a | 239 | void lm32_cpu_list(void); |
81ea0e13 | 240 | void lm32_translate_init(void); |
6393c08d | 241 | void cpu_lm32_set_phys_msb_ignore(CPULM32State *env, int value); |
3dd3a2b9 | 242 | void QEMU_NORETURN raise_exception(CPULM32State *env, int index); |
86025ee4 | 243 | void lm32_debug_excp_handler(CPUState *cs); |
3dd3a2b9 MW |
244 | void lm32_breakpoint_insert(CPULM32State *env, int index, target_ulong address); |
245 | void lm32_breakpoint_remove(CPULM32State *env, int index); | |
246 | void lm32_watchpoint_insert(CPULM32State *env, int index, target_ulong address, | |
247 | lm32_wp_t wp_type); | |
248 | void lm32_watchpoint_remove(CPULM32State *env, int index); | |
f7bbcfb5 | 249 | bool lm32_cpu_do_semihosting(CPUState *cs); |
81ea0e13 | 250 | |
c6678108 IM |
251 | #define LM32_CPU_TYPE_SUFFIX "-" TYPE_LM32_CPU |
252 | #define LM32_CPU_TYPE_NAME(model) model LM32_CPU_TYPE_SUFFIX | |
0dacec87 | 253 | #define CPU_RESOLVING_TYPE TYPE_LM32_CPU |
c6678108 | 254 | |
34f4aa83 | 255 | #define cpu_list lm32_cpu_list |
81ea0e13 MW |
256 | #define cpu_signal_handler cpu_lm32_signal_handler |
257 | ||
ae0d4c0b RH |
258 | bool lm32_cpu_tlb_fill(CPUState *cs, vaddr address, int size, |
259 | MMUAccessType access_type, int mmu_idx, | |
260 | bool probe, uintptr_t retaddr); | |
81ea0e13 | 261 | |
022c62cb | 262 | #include "exec/cpu-all.h" |
81ea0e13 | 263 | |
6393c08d | 264 | static inline void cpu_get_tb_cpu_state(CPULM32State *env, target_ulong *pc, |
89fee74a | 265 | target_ulong *cs_base, uint32_t *flags) |
81ea0e13 MW |
266 | { |
267 | *pc = env->pc; | |
268 | *cs_base = 0; | |
269 | *flags = 0; | |
270 | } | |
f081c76c | 271 | |
81ea0e13 | 272 | #endif |