[mirror_qemu.git] / target / loongarch / cpu-csr.h

/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
 * QEMU LoongArch CSRs
 *
 * Copyright (c) 2021 Loongson Technology Corporation Limited
 */

#ifndef LOONGARCH_CPU_CSR_H
#define LOONGARCH_CPU_CSR_H

#include "hw/registerfields.h"

/* Based on kernel definitions: arch/loongarch/include/asm/loongarch.h */

/* Basic CSRs */
#define LOONGARCH_CSR_CRMD           0x0 /* Current mode info */

#define LOONGARCH_CSR_PRMD           0x1 /* Prev-exception mode info */
FIELD(CSR_PRMD, PPLV, 0, 2)
FIELD(CSR_PRMD, PIE, 2, 1)
FIELD(CSR_PRMD, PWE, 3, 1)

#define LOONGARCH_CSR_EUEN           0x2 /* Extended unit enable */
FIELD(CSR_EUEN, FPE, 0, 1)
FIELD(CSR_EUEN, SXE, 1, 1)
FIELD(CSR_EUEN, ASXE, 2, 1)
FIELD(CSR_EUEN, BTE, 3, 1)

#define LOONGARCH_CSR_MISC           0x3 /* Misc config */
FIELD(CSR_MISC, VA32, 0, 4)
FIELD(CSR_MISC, DRDTL, 4, 4)
FIELD(CSR_MISC, RPCNTL, 8, 4)
FIELD(CSR_MISC, ALCL, 12, 4)
FIELD(CSR_MISC, DWPL, 16, 3)

#define LOONGARCH_CSR_ECFG           0x4 /* Exception config */
FIELD(CSR_ECFG, LIE, 0, 13)
FIELD(CSR_ECFG, VS, 16, 3)

#define LOONGARCH_CSR_ESTAT          0x5 /* Exception status */
FIELD(CSR_ESTAT, IS, 0, 13)
FIELD(CSR_ESTAT, ECODE, 16, 6)
FIELD(CSR_ESTAT, ESUBCODE, 22, 9)

#define LOONGARCH_CSR_ERA            0x6 /* Exception return address */

#define LOONGARCH_CSR_BADV           0x7 /* Bad virtual address */

#define LOONGARCH_CSR_BADI           0x8 /* Bad instruction */

#define LOONGARCH_CSR_EENTRY         0xc /* Exception entry address */

/* TLB related CSRs */
#define LOONGARCH_CSR_TLBIDX         0x10 /* TLB Index, EHINV, PageSize, NP */
FIELD(CSR_TLBIDX, INDEX, 0, 12)
FIELD(CSR_TLBIDX, PS, 24, 6)
FIELD(CSR_TLBIDX, NE, 31, 1)

#define LOONGARCH_CSR_TLBEHI         0x11 /* TLB EntryHi */
FIELD(CSR_TLBEHI_32, VPPN, 13, 19)
FIELD(CSR_TLBEHI_64, VPPN, 13, 35)

#define LOONGARCH_CSR_TLBELO0        0x12 /* TLB EntryLo0 */
#define LOONGARCH_CSR_TLBELO1        0x13 /* TLB EntryLo1 */
FIELD(TLBENTRY, V, 0, 1)
FIELD(TLBENTRY, D, 1, 1)
FIELD(TLBENTRY, PLV, 2, 2)
FIELD(TLBENTRY, MAT, 4, 2)
FIELD(TLBENTRY, G, 6, 1)
FIELD(TLBENTRY_32, PPN, 8, 24)
FIELD(TLBENTRY_64, PPN, 12, 36)
FIELD(TLBENTRY_64, NR, 61, 1)
FIELD(TLBENTRY_64, NX, 62, 1)
FIELD(TLBENTRY_64, RPLV, 63, 1)

#define LOONGARCH_CSR_ASID           0x18 /* Address space identifier */
FIELD(CSR_ASID, ASID, 0, 10)
FIELD(CSR_ASID, ASIDBITS, 16, 8)

/* Page table base address when badv[47] = 0 */
#define LOONGARCH_CSR_PGDL           0x19
/* Page table base address when badv[47] = 1 */
#define LOONGARCH_CSR_PGDH           0x1a

#define LOONGARCH_CSR_PGD            0x1b /* Page table base address */

/* Page walk controller's low addr */
#define LOONGARCH_CSR_PWCL           0x1c
FIELD(CSR_PWCL, PTBASE, 0, 5)
FIELD(CSR_PWCL, PTWIDTH, 5, 5)
FIELD(CSR_PWCL, DIR1_BASE, 10, 5)
FIELD(CSR_PWCL, DIR1_WIDTH, 15, 5)
FIELD(CSR_PWCL, DIR2_BASE, 20, 5)
FIELD(CSR_PWCL, DIR2_WIDTH, 25, 5)
FIELD(CSR_PWCL, PTEWIDTH, 30, 2)

/* Page walk controller's high addr */
#define LOONGARCH_CSR_PWCH           0x1d
FIELD(CSR_PWCH, DIR3_BASE, 0, 6)
FIELD(CSR_PWCH, DIR3_WIDTH, 6, 6)
FIELD(CSR_PWCH, DIR4_BASE, 12, 6)
FIELD(CSR_PWCH, DIR4_WIDTH, 18, 6)

#define LOONGARCH_CSR_STLBPS         0x1e /* Stlb page size */
FIELD(CSR_STLBPS, PS, 0, 5)

#define LOONGARCH_CSR_RVACFG         0x1f /* Reduced virtual address config */
FIELD(CSR_RVACFG, RBITS, 0, 4)

/* Config CSRs */
#define LOONGARCH_CSR_CPUID          0x20 /* CPU core id */

#define LOONGARCH_CSR_PRCFG1         0x21 /* Config1 */
FIELD(CSR_PRCFG1, SAVE_NUM, 0, 4)
FIELD(CSR_PRCFG1, TIMER_BITS, 4, 8)
FIELD(CSR_PRCFG1, VSMAX, 12, 3)

#define LOONGARCH_CSR_PRCFG2         0x22 /* Config2 */

#define LOONGARCH_CSR_PRCFG3         0x23 /* Config3 */
FIELD(CSR_PRCFG3, TLB_TYPE, 0, 4)
FIELD(CSR_PRCFG3, MTLB_ENTRY, 4, 8)
FIELD(CSR_PRCFG3, STLB_WAYS, 12, 8)
FIELD(CSR_PRCFG3, STLB_SETS, 20, 8)

/*
 * Save registers count can read from PRCFG1.SAVE_NUM
 * The Min count is 1. Max count is 15.
 */
#define LOONGARCH_CSR_SAVE(N)        (0x30 + N)

/* Timer CSRs */
#define LOONGARCH_CSR_TID            0x40 /* Timer ID */

#define LOONGARCH_CSR_TCFG           0x41 /* Timer config */
FIELD(CSR_TCFG, EN, 0, 1)
FIELD(CSR_TCFG, PERIODIC, 1, 1)
FIELD(CSR_TCFG, INIT_VAL, 2, 46)

#define LOONGARCH_CSR_TVAL           0x42 /* Timer ticks remain */

#define LOONGARCH_CSR_CNTC           0x43 /* Timer offset */

#define LOONGARCH_CSR_TICLR          0x44 /* Timer interrupt clear */

/* LLBCTL CSRs */
#define LOONGARCH_CSR_LLBCTL         0x60 /* LLBit control */
FIELD(CSR_LLBCTL, ROLLB, 0, 1)
FIELD(CSR_LLBCTL, WCLLB, 1, 1)
FIELD(CSR_LLBCTL, KLO, 2, 1)

/* Implement dependent */
#define LOONGARCH_CSR_IMPCTL1        0x80 /* LoongArch config1 */

#define LOONGARCH_CSR_IMPCTL2        0x81 /* LoongArch config2*/

/* TLB Refill CSRs */
#define LOONGARCH_CSR_TLBRENTRY      0x88 /* TLB refill exception address */
#define LOONGARCH_CSR_TLBRBADV       0x89 /* TLB refill badvaddr */
#define LOONGARCH_CSR_TLBRERA        0x8a /* TLB refill ERA */
#define LOONGARCH_CSR_TLBRSAVE       0x8b /* KScratch for TLB refill */
FIELD(CSR_TLBRERA, ISTLBR, 0, 1)
FIELD(CSR_TLBRERA, PC, 2, 62)
#define LOONGARCH_CSR_TLBRELO0       0x8c /* TLB refill entrylo0 */
#define LOONGARCH_CSR_TLBRELO1       0x8d /* TLB refill entrylo1 */
#define LOONGARCH_CSR_TLBREHI        0x8e /* TLB refill entryhi */
FIELD(CSR_TLBREHI, PS, 0, 6)
FIELD(CSR_TLBREHI_32, VPPN, 13, 19)
FIELD(CSR_TLBREHI_64, VPPN, 13, 35)
#define LOONGARCH_CSR_TLBRPRMD       0x8f /* TLB refill mode info */
FIELD(CSR_TLBRPRMD, PPLV, 0, 2)
FIELD(CSR_TLBRPRMD, PIE, 2, 1)
FIELD(CSR_TLBRPRMD, PWE, 4, 1)

/* Machine Error CSRs */
#define LOONGARCH_CSR_MERRCTL        0x90 /* ERRCTL */
FIELD(CSR_MERRCTL, ISMERR, 0, 1)
#define LOONGARCH_CSR_MERRINFO1      0x91
#define LOONGARCH_CSR_MERRINFO2      0x92
#define LOONGARCH_CSR_MERRENTRY      0x93 /* MError exception base */
#define LOONGARCH_CSR_MERRERA        0x94 /* MError exception PC */
#define LOONGARCH_CSR_MERRSAVE       0x95 /* KScratch for error exception */

#define LOONGARCH_CSR_CTAG           0x98 /* TagLo + TagHi */

/* Direct map windows CSRs*/
#define LOONGARCH_CSR_DMW(N)         (0x180 + N)
FIELD(CSR_DMW, PLV0, 0, 1)
FIELD(CSR_DMW, PLV1, 1, 1)
FIELD(CSR_DMW, PLV2, 2, 1)
FIELD(CSR_DMW, PLV3, 3, 1)
FIELD(CSR_DMW, MAT, 4, 2)
FIELD(CSR_DMW_32, PSEG, 25, 3)
FIELD(CSR_DMW_32, VSEG, 29, 3)
FIELD(CSR_DMW_64, VSEG, 60, 4)

/* Debug CSRs */
#define LOONGARCH_CSR_DBG            0x500 /* debug config */
FIELD(CSR_DBG, DST, 0, 1)
FIELD(CSR_DBG, DREV, 1, 7)
FIELD(CSR_DBG, DEI, 8, 1)
FIELD(CSR_DBG, DCL, 9, 1)
FIELD(CSR_DBG, DFW, 10, 1)
FIELD(CSR_DBG, DMW, 11, 1)
FIELD(CSR_DBG, ECODE, 16, 6)

#define LOONGARCH_CSR_DERA           0x501 /* Debug era */
#define LOONGARCH_CSR_DSAVE          0x502 /* Debug save */

#endif /* LOONGARCH_CPU_CSR_H */
Commit	Line	Data
398cecb9 XY	1	/* SPDX-License-Identifier: GPL-2.0-or-later */
	2	/*
	3	* QEMU LoongArch CSRs
	4	*
	5	* Copyright (c) 2021 Loongson Technology Corporation Limited
	6	*/
	7
	8	#ifndef LOONGARCH_CPU_CSR_H
	9	#define LOONGARCH_CPU_CSR_H
	10
	11	#include "hw/registerfields.h"
	12
8b81968c	13	/* Based on kernel definitions: arch/loongarch/include/asm/loongarch.h */
398cecb9 XY	14
	15	/* Basic CSRs */
	16	#define LOONGARCH_CSR_CRMD 0x0 /* Current mode info */
	17
	18	#define LOONGARCH_CSR_PRMD 0x1 /* Prev-exception mode info */
	19	FIELD(CSR_PRMD, PPLV, 0, 2)
	20	FIELD(CSR_PRMD, PIE, 2, 1)
	21	FIELD(CSR_PRMD, PWE, 3, 1)
	22
	23	#define LOONGARCH_CSR_EUEN 0x2 /* Extended unit enable */
	24	FIELD(CSR_EUEN, FPE, 0, 1)
	25	FIELD(CSR_EUEN, SXE, 1, 1)
	26	FIELD(CSR_EUEN, ASXE, 2, 1)
	27	FIELD(CSR_EUEN, BTE, 3, 1)
	28
	29	#define LOONGARCH_CSR_MISC 0x3 /* Misc config */
	30	FIELD(CSR_MISC, VA32, 0, 4)
	31	FIELD(CSR_MISC, DRDTL, 4, 4)
	32	FIELD(CSR_MISC, RPCNTL, 8, 4)
	33	FIELD(CSR_MISC, ALCL, 12, 4)
	34	FIELD(CSR_MISC, DWPL, 16, 3)
	35
	36	#define LOONGARCH_CSR_ECFG 0x4 /* Exception config */
	37	FIELD(CSR_ECFG, LIE, 0, 13)
	38	FIELD(CSR_ECFG, VS, 16, 3)
	39
	40	#define LOONGARCH_CSR_ESTAT 0x5 /* Exception status */
	41	FIELD(CSR_ESTAT, IS, 0, 13)
	42	FIELD(CSR_ESTAT, ECODE, 16, 6)
	43	FIELD(CSR_ESTAT, ESUBCODE, 22, 9)
	44
	45	#define LOONGARCH_CSR_ERA 0x6 /* Exception return address */
	46
	47	#define LOONGARCH_CSR_BADV 0x7 /* Bad virtual address */
	48
	49	#define LOONGARCH_CSR_BADI 0x8 /* Bad instruction */
	50
	51	#define LOONGARCH_CSR_EENTRY 0xc /* Exception entry address */
	52
	53	/* TLB related CSRs */
	54	#define LOONGARCH_CSR_TLBIDX 0x10 /* TLB Index, EHINV, PageSize, NP */
	55	FIELD(CSR_TLBIDX, INDEX, 0, 12)
	56	FIELD(CSR_TLBIDX, PS, 24, 6)
	57	FIELD(CSR_TLBIDX, NE, 31, 1)
	58
	59	#define LOONGARCH_CSR_TLBEHI 0x11 /* TLB EntryHi */
50fffcc4 JC	60	FIELD(CSR_TLBEHI_32, VPPN, 13, 19)
50fffcc4 JC	61	FIELD(CSR_TLBEHI_64, VPPN, 13, 35)
398cecb9 XY	62
	63	#define LOONGARCH_CSR_TLBELO0 0x12 /* TLB EntryLo0 */
	64	#define LOONGARCH_CSR_TLBELO1 0x13 /* TLB EntryLo1 */
	65	FIELD(TLBENTRY, V, 0, 1)
	66	FIELD(TLBENTRY, D, 1, 1)
	67	FIELD(TLBENTRY, PLV, 2, 2)
	68	FIELD(TLBENTRY, MAT, 4, 2)
	69	FIELD(TLBENTRY, G, 6, 1)
e70bb6fb JC	70	FIELD(TLBENTRY_32, PPN, 8, 24)
	71	FIELD(TLBENTRY_64, PPN, 12, 36)
	72	FIELD(TLBENTRY_64, NR, 61, 1)
	73	FIELD(TLBENTRY_64, NX, 62, 1)
	74	FIELD(TLBENTRY_64, RPLV, 63, 1)
398cecb9 XY	75
	76	#define LOONGARCH_CSR_ASID 0x18 /* Address space identifier */
	77	FIELD(CSR_ASID, ASID, 0, 10)
	78	FIELD(CSR_ASID, ASIDBITS, 16, 8)
	79
	80	/* Page table base address when badv[47] = 0 */
	81	#define LOONGARCH_CSR_PGDL 0x19
	82	/* Page table base address when badv[47] = 1 */
	83	#define LOONGARCH_CSR_PGDH 0x1a
	84
	85	#define LOONGARCH_CSR_PGD 0x1b /* Page table base address */
	86
	87	/* Page walk controller's low addr */
	88	#define LOONGARCH_CSR_PWCL 0x1c
	89	FIELD(CSR_PWCL, PTBASE, 0, 5)
	90	FIELD(CSR_PWCL, PTWIDTH, 5, 5)
	91	FIELD(CSR_PWCL, DIR1_BASE, 10, 5)
	92	FIELD(CSR_PWCL, DIR1_WIDTH, 15, 5)
	93	FIELD(CSR_PWCL, DIR2_BASE, 20, 5)
	94	FIELD(CSR_PWCL, DIR2_WIDTH, 25, 5)
	95	FIELD(CSR_PWCL, PTEWIDTH, 30, 2)
	96
	97	/* Page walk controller's high addr */
	98	#define LOONGARCH_CSR_PWCH 0x1d
	99	FIELD(CSR_PWCH, DIR3_BASE, 0, 6)
	100	FIELD(CSR_PWCH, DIR3_WIDTH, 6, 6)
	101	FIELD(CSR_PWCH, DIR4_BASE, 12, 6)
	102	FIELD(CSR_PWCH, DIR4_WIDTH, 18, 6)
	103
	104	#define LOONGARCH_CSR_STLBPS 0x1e /* Stlb page size */
	105	FIELD(CSR_STLBPS, PS, 0, 5)
	106
	107	#define LOONGARCH_CSR_RVACFG 0x1f /* Reduced virtual address config */
	108	FIELD(CSR_RVACFG, RBITS, 0, 4)
	109
	110	/* Config CSRs */
	111	#define LOONGARCH_CSR_CPUID 0x20 /* CPU core id */
	112
	113	#define LOONGARCH_CSR_PRCFG1 0x21 /* Config1 */
	114	FIELD(CSR_PRCFG1, SAVE_NUM, 0, 4)
	115	FIELD(CSR_PRCFG1, TIMER_BITS, 4, 8)
	116	FIELD(CSR_PRCFG1, VSMAX, 12, 3)
	117
	118	#define LOONGARCH_CSR_PRCFG2 0x22 /* Config2 */
	119
	120	#define LOONGARCH_CSR_PRCFG3 0x23 /* Config3 */
	121	FIELD(CSR_PRCFG3, TLB_TYPE, 0, 4)
	122	FIELD(CSR_PRCFG3, MTLB_ENTRY, 4, 8)
	123	FIELD(CSR_PRCFG3, STLB_WAYS, 12, 8)
	124	FIELD(CSR_PRCFG3, STLB_SETS, 20, 8)
	125
	126	/*
	127	* Save registers count can read from PRCFG1.SAVE_NUM
	128	* The Min count is 1. Max count is 15.
	129	*/
	130	#define LOONGARCH_CSR_SAVE(N) (0x30 + N)
	131
	132	/* Timer CSRs */
	133	#define LOONGARCH_CSR_TID 0x40 /* Timer ID */
	134
	135	#define LOONGARCH_CSR_TCFG 0x41 /* Timer config */
	136	FIELD(CSR_TCFG, EN, 0, 1)
	137	FIELD(CSR_TCFG, PERIODIC, 1, 1)
	138	FIELD(CSR_TCFG, INIT_VAL, 2, 46)
139
140	#define LOONGARCH_CSR_TVAL 0x42 /* Timer ticks remain */
141
142	#define LOONGARCH_CSR_CNTC 0x43 /* Timer offset */
143
144	#define LOONGARCH_CSR_TICLR 0x44 /* Timer interrupt clear */
145
146	/* LLBCTL CSRs */
147	#define LOONGARCH_CSR_LLBCTL 0x60 /* LLBit control */
148	FIELD(CSR_LLBCTL, ROLLB, 0, 1)
149	FIELD(CSR_LLBCTL, WCLLB, 1, 1)
150	FIELD(CSR_LLBCTL, KLO, 2, 1)
151
152	/* Implement dependent */
153	#define LOONGARCH_CSR_IMPCTL1 0x80 /* LoongArch config1 */
154
155	#define LOONGARCH_CSR_IMPCTL2 0x81 /* LoongArch config2*/
156
157	/* TLB Refill CSRs */
158	#define LOONGARCH_CSR_TLBRENTRY 0x88 /* TLB refill exception address */
159	#define LOONGARCH_CSR_TLBRBADV 0x89 /* TLB refill badvaddr */
160	#define LOONGARCH_CSR_TLBRERA 0x8a /* TLB refill ERA */
161	#define LOONGARCH_CSR_TLBRSAVE 0x8b /* KScratch for TLB refill */
162	FIELD(CSR_TLBRERA, ISTLBR, 0, 1)
163	FIELD(CSR_TLBRERA, PC, 2, 62)
164	#define LOONGARCH_CSR_TLBRELO0 0x8c /* TLB refill entrylo0 */
165	#define LOONGARCH_CSR_TLBRELO1 0x8d /* TLB refill entrylo1 */
166	#define LOONGARCH_CSR_TLBREHI 0x8e /* TLB refill entryhi */
167	FIELD(CSR_TLBREHI, PS, 0, 6)
50fffcc4 JC	168	FIELD(CSR_TLBREHI_32, VPPN, 13, 19)
50fffcc4 JC	169	FIELD(CSR_TLBREHI_64, VPPN, 13, 35)
398cecb9 XY	170	#define LOONGARCH_CSR_TLBRPRMD 0x8f /* TLB refill mode info */
	171	FIELD(CSR_TLBRPRMD, PPLV, 0, 2)
	172	FIELD(CSR_TLBRPRMD, PIE, 2, 1)
	173	FIELD(CSR_TLBRPRMD, PWE, 4, 1)
	174
	175	/* Machine Error CSRs */
	176	#define LOONGARCH_CSR_MERRCTL 0x90 /* ERRCTL */
	177	FIELD(CSR_MERRCTL, ISMERR, 0, 1)
	178	#define LOONGARCH_CSR_MERRINFO1 0x91
	179	#define LOONGARCH_CSR_MERRINFO2 0x92
	180	#define LOONGARCH_CSR_MERRENTRY 0x93 /* MError exception base */
	181	#define LOONGARCH_CSR_MERRERA 0x94 /* MError exception PC */
	182	#define LOONGARCH_CSR_MERRSAVE 0x95 /* KScratch for error exception */
	183
	184	#define LOONGARCH_CSR_CTAG 0x98 /* TagLo + TagHi */
	185
	186	/* Direct map windows CSRs*/
	187	#define LOONGARCH_CSR_DMW(N) (0x180 + N)
	188	FIELD(CSR_DMW, PLV0, 0, 1)
	189	FIELD(CSR_DMW, PLV1, 1, 1)
	190	FIELD(CSR_DMW, PLV2, 2, 1)
	191	FIELD(CSR_DMW, PLV3, 3, 1)
	192	FIELD(CSR_DMW, MAT, 4, 2)
eece5764 JC	193	FIELD(CSR_DMW_32, PSEG, 25, 3)
	194	FIELD(CSR_DMW_32, VSEG, 29, 3)
	195	FIELD(CSR_DMW_64, VSEG, 60, 4)
398cecb9 XY	196
	197	/* Debug CSRs */
	198	#define LOONGARCH_CSR_DBG 0x500 /* debug config */
	199	FIELD(CSR_DBG, DST, 0, 1)
	200	FIELD(CSR_DBG, DREV, 1, 7)
	201	FIELD(CSR_DBG, DEI, 8, 1)
	202	FIELD(CSR_DBG, DCL, 9, 1)
	203	FIELD(CSR_DBG, DFW, 10, 1)
	204	FIELD(CSR_DBG, DMW, 11, 1)
	205	FIELD(CSR_DBG, ECODE, 16, 6)
	206
	207	#define LOONGARCH_CSR_DERA 0x501 /* Debug era */
	208	#define LOONGARCH_CSR_DSAVE 0x502 /* Debug save */
	209
	210	#endif /* LOONGARCH_CPU_CSR_H */