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f8da88d7 SG |
1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
2 | /* | |
3 | * LoongArch translation routines. | |
4 | * | |
5 | * Copyright (c) 2021 Loongson Technology Corporation Limited | |
6 | */ | |
7 | ||
8 | #ifndef TARGET_LOONGARCH_TRANSLATE_H | |
9 | #define TARGET_LOONGARCH_TRANSLATE_H | |
10 | ||
11 | #include "exec/translator.h" | |
12 | ||
ec3a9518 | 13 | #define TRANS(NAME, AVAIL, FUNC, ...) \ |
143d6785 | 14 | static bool trans_##NAME(DisasContext *ctx, arg_##NAME * a) \ |
ec3a9518 SG |
15 | { return avail_##AVAIL(ctx) && FUNC(ctx, a, __VA_ARGS__); } |
16 | ||
17 | #define avail_ALL(C) true | |
c0c0461e SG |
18 | #define avail_64(C) (FIELD_EX32((C)->cpucfg1, CPUCFG1, ARCH) == \ |
19 | CPUCFG1_ARCH_LA64) | |
95e2ca24 SG |
20 | #define avail_FP(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, FP)) |
21 | #define avail_FP_SP(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, FP_SP)) | |
22 | #define avail_FP_DP(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, FP_DP)) | |
70c8d5ea | 23 | #define avail_LSPW(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, LSPW)) |
b139ddf1 | 24 | #define avail_LAM(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, LAM)) |
ebf288b4 | 25 | #define avail_LSX(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, LSX)) |
cf61aef3 | 26 | #define avail_LASX(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, LASX)) |
a380c6f1 | 27 | #define avail_IOCSR(C) (FIELD_EX32((C)->cpucfg1, CPUCFG1, IOCSR)) |
143d6785 SG |
28 | |
29 | /* | |
30 | * If an operation is being performed on less than TARGET_LONG_BITS, | |
31 | * it may require the inputs to be sign- or zero-extended; which will | |
32 | * depend on the exact operation being performed. | |
33 | */ | |
34 | typedef enum { | |
35 | EXT_NONE, | |
36 | EXT_SIGN, | |
37 | EXT_ZERO, | |
38 | } DisasExtend; | |
39 | ||
f8da88d7 SG |
40 | typedef struct DisasContext { |
41 | DisasContextBase base; | |
42 | target_ulong page_start; | |
43 | uint32_t opcode; | |
c8885b88 RW |
44 | uint16_t mem_idx; |
45 | uint16_t plv; | |
57b4f1ac | 46 | int vl; /* Vector length */ |
143d6785 | 47 | TCGv zero; |
39665820 JC |
48 | bool la64; /* LoongArch64 mode */ |
49 | bool va32; /* 32-bit virtual address */ | |
c0c0461e | 50 | uint32_t cpucfg1; |
95e2ca24 | 51 | uint32_t cpucfg2; |
f8da88d7 SG |
52 | } DisasContext; |
53 | ||
54 | void generate_exception(DisasContext *ctx, int excp); | |
55 | ||
56 | extern TCGv cpu_gpr[32], cpu_pc; | |
57 | extern TCGv_i32 cpu_fscr0; | |
58 | extern TCGv_i64 cpu_fpr[32]; | |
59 | ||
60 | #endif |