[mirror_qemu.git] / target / loongarch / translate.h

/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
 * LoongArch translation routines.
 *
 * Copyright (c) 2021 Loongson Technology Corporation Limited
 */

#ifndef TARGET_LOONGARCH_TRANSLATE_H
#define TARGET_LOONGARCH_TRANSLATE_H

#include "exec/translator.h"

#define TRANS(NAME, FUNC, ...) \
    static bool trans_##NAME(DisasContext *ctx, arg_##NAME * a) \
    { return FUNC(ctx, a, __VA_ARGS__); }

/*
 * If an operation is being performed on less than TARGET_LONG_BITS,
 * it may require the inputs to be sign- or zero-extended; which will
 * depend on the exact operation being performed.
 */
typedef enum {
    EXT_NONE,
    EXT_SIGN,
    EXT_ZERO,
} DisasExtend;

typedef struct DisasContext {
    DisasContextBase base;
    target_ulong page_start;
    uint32_t opcode;
    uint16_t mem_idx;
    uint16_t plv;
    TCGv zero;
    /* Space for 3 operands plus 1 extra for address computation. */
    TCGv temp[4];
    uint8_t ntemp;
} DisasContext;

void generate_exception(DisasContext *ctx, int excp);

extern TCGv cpu_gpr[32], cpu_pc;
extern TCGv_i32 cpu_fscr0;
extern TCGv_i64 cpu_fpr[32];

#endif
Commit	Line	Data
f8da88d7 SG	1	/* SPDX-License-Identifier: GPL-2.0-or-later */
	2	/*
	3	* LoongArch translation routines.
	4	*
	5	* Copyright (c) 2021 Loongson Technology Corporation Limited
	6	*/
	7
	8	#ifndef TARGET_LOONGARCH_TRANSLATE_H
	9	#define TARGET_LOONGARCH_TRANSLATE_H
	10
	11	#include "exec/translator.h"
	12
143d6785 SG	13	#define TRANS(NAME, FUNC, ...) \
	14	static bool trans_##NAME(DisasContext ctx, arg_##NAME a) \
	15	{ return FUNC(ctx, a, __VA_ARGS__); }
	16
	17	/*
	18	* If an operation is being performed on less than TARGET_LONG_BITS,
	19	* it may require the inputs to be sign- or zero-extended; which will
	20	* depend on the exact operation being performed.
	21	*/
	22	typedef enum {
	23	EXT_NONE,
	24	EXT_SIGN,
	25	EXT_ZERO,
	26	} DisasExtend;
	27
f8da88d7 SG	28	typedef struct DisasContext {
	29	DisasContextBase base;
	30	target_ulong page_start;
	31	uint32_t opcode;
c8885b88 RW	32	uint16_t mem_idx;
c8885b88 RW	33	uint16_t plv;
143d6785 SG	34	TCGv zero;
	35	/* Space for 3 operands plus 1 extra for address computation. */
	36	TCGv temp[4];
	37	uint8_t ntemp;
f8da88d7 SG	38	} DisasContext;
	39
	40	void generate_exception(DisasContext *ctx, int excp);
	41
	42	extern TCGv cpu_gpr[32], cpu_pc;
	43	extern TCGv_i32 cpu_fscr0;
	44	extern TCGv_i64 cpu_fpr[32];
	45
	46	#endif