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Commit | Line | Data |
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e6e5906b PB |
1 | /* |
2 | * m68k translation | |
5fafdf24 | 3 | * |
0633879f | 4 | * Copyright (c) 2005-2007 CodeSourcery |
e6e5906b PB |
5 | * Written by Paul Brook |
6 | * | |
7 | * This library is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU Lesser General Public | |
9 | * License as published by the Free Software Foundation; either | |
10 | * version 2 of the License, or (at your option) any later version. | |
11 | * | |
12 | * This library is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 18 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
e6e5906b | 19 | */ |
e6e5906b | 20 | |
d8416665 | 21 | #include "qemu/osdep.h" |
e6e5906b | 22 | #include "cpu.h" |
76cad711 | 23 | #include "disas/disas.h" |
63c91552 | 24 | #include "exec/exec-all.h" |
57fec1fe | 25 | #include "tcg-op.h" |
1de7afc9 | 26 | #include "qemu/log.h" |
f08b6170 | 27 | #include "exec/cpu_ldst.h" |
e1f3808e | 28 | |
2ef6175a RH |
29 | #include "exec/helper-proto.h" |
30 | #include "exec/helper-gen.h" | |
e6e5906b | 31 | |
a7e30d84 | 32 | #include "trace-tcg.h" |
508127e2 | 33 | #include "exec/log.h" |
a7e30d84 LV |
34 | |
35 | ||
0633879f PB |
36 | //#define DEBUG_DISPATCH 1 |
37 | ||
815a6742 | 38 | /* Fake floating point. */ |
815a6742 | 39 | #define tcg_gen_mov_f64 tcg_gen_mov_i64 |
815a6742 | 40 | #define tcg_gen_qemu_ldf64 tcg_gen_qemu_ld64 |
815a6742 | 41 | #define tcg_gen_qemu_stf64 tcg_gen_qemu_st64 |
815a6742 | 42 | |
e1f3808e | 43 | #define DEFO32(name, offset) static TCGv QREG_##name; |
a7812ae4 PB |
44 | #define DEFO64(name, offset) static TCGv_i64 QREG_##name; |
45 | #define DEFF64(name, offset) static TCGv_i64 QREG_##name; | |
e1f3808e PB |
46 | #include "qregs.def" |
47 | #undef DEFO32 | |
48 | #undef DEFO64 | |
49 | #undef DEFF64 | |
50 | ||
259186a7 | 51 | static TCGv_i32 cpu_halted; |
27103424 | 52 | static TCGv_i32 cpu_exception_index; |
259186a7 | 53 | |
1bcea73e | 54 | static TCGv_env cpu_env; |
e1f3808e PB |
55 | |
56 | static char cpu_reg_names[3*8*3 + 5*4]; | |
57 | static TCGv cpu_dregs[8]; | |
58 | static TCGv cpu_aregs[8]; | |
a7812ae4 PB |
59 | static TCGv_i64 cpu_fregs[8]; |
60 | static TCGv_i64 cpu_macc[4]; | |
e1f3808e | 61 | |
8a1e52b6 | 62 | #define REG(insn, pos) (((insn) >> (pos)) & 7) |
bcc098b0 | 63 | #define DREG(insn, pos) cpu_dregs[REG(insn, pos)] |
8a1e52b6 | 64 | #define AREG(insn, pos) get_areg(s, REG(insn, pos)) |
bcc098b0 | 65 | #define FREG(insn, pos) cpu_fregs[REG(insn, pos)] |
8a1e52b6 RH |
66 | #define MACREG(acc) cpu_macc[acc] |
67 | #define QREG_SP get_areg(s, 7) | |
e1f3808e PB |
68 | |
69 | static TCGv NULL_QREG; | |
a7812ae4 | 70 | #define IS_NULL_QREG(t) (TCGV_EQUAL(t, NULL_QREG)) |
e1f3808e PB |
71 | /* Used to distinguish stores from bad addressing modes. */ |
72 | static TCGv store_dummy; | |
73 | ||
022c62cb | 74 | #include "exec/gen-icount.h" |
2e70f6ef | 75 | |
e1f3808e PB |
76 | void m68k_tcg_init(void) |
77 | { | |
78 | char *p; | |
79 | int i; | |
80 | ||
e1ccc054 | 81 | cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); |
7c255043 | 82 | tcg_ctx.tcg_env = cpu_env; |
e1ccc054 RH |
83 | |
84 | #define DEFO32(name, offset) \ | |
85 | QREG_##name = tcg_global_mem_new_i32(cpu_env, \ | |
86 | offsetof(CPUM68KState, offset), #name); | |
87 | #define DEFO64(name, offset) \ | |
88 | QREG_##name = tcg_global_mem_new_i64(cpu_env, \ | |
89 | offsetof(CPUM68KState, offset), #name); | |
90 | #define DEFF64(name, offset) DEFO64(name, offset) | |
e1f3808e PB |
91 | #include "qregs.def" |
92 | #undef DEFO32 | |
93 | #undef DEFO64 | |
94 | #undef DEFF64 | |
95 | ||
e1ccc054 | 96 | cpu_halted = tcg_global_mem_new_i32(cpu_env, |
259186a7 AF |
97 | -offsetof(M68kCPU, env) + |
98 | offsetof(CPUState, halted), "HALTED"); | |
e1ccc054 | 99 | cpu_exception_index = tcg_global_mem_new_i32(cpu_env, |
27103424 AF |
100 | -offsetof(M68kCPU, env) + |
101 | offsetof(CPUState, exception_index), | |
102 | "EXCEPTION"); | |
259186a7 | 103 | |
e1f3808e PB |
104 | p = cpu_reg_names; |
105 | for (i = 0; i < 8; i++) { | |
106 | sprintf(p, "D%d", i); | |
e1ccc054 | 107 | cpu_dregs[i] = tcg_global_mem_new(cpu_env, |
e1f3808e PB |
108 | offsetof(CPUM68KState, dregs[i]), p); |
109 | p += 3; | |
110 | sprintf(p, "A%d", i); | |
e1ccc054 | 111 | cpu_aregs[i] = tcg_global_mem_new(cpu_env, |
e1f3808e PB |
112 | offsetof(CPUM68KState, aregs[i]), p); |
113 | p += 3; | |
114 | sprintf(p, "F%d", i); | |
e1ccc054 | 115 | cpu_fregs[i] = tcg_global_mem_new_i64(cpu_env, |
e1f3808e PB |
116 | offsetof(CPUM68KState, fregs[i]), p); |
117 | p += 3; | |
118 | } | |
119 | for (i = 0; i < 4; i++) { | |
120 | sprintf(p, "ACC%d", i); | |
e1ccc054 | 121 | cpu_macc[i] = tcg_global_mem_new_i64(cpu_env, |
e1f3808e PB |
122 | offsetof(CPUM68KState, macc[i]), p); |
123 | p += 5; | |
124 | } | |
125 | ||
e1ccc054 RH |
126 | NULL_QREG = tcg_global_mem_new(cpu_env, -4, "NULL"); |
127 | store_dummy = tcg_global_mem_new(cpu_env, -8, "NULL"); | |
e1f3808e PB |
128 | } |
129 | ||
e6e5906b PB |
130 | /* internal defines */ |
131 | typedef struct DisasContext { | |
e6dbd3b3 | 132 | CPUM68KState *env; |
510ff0b7 | 133 | target_ulong insn_pc; /* Start of the current instruction. */ |
e6e5906b PB |
134 | target_ulong pc; |
135 | int is_jmp; | |
9fdb533f | 136 | CCOp cc_op; /* Current CC operation */ |
620c6cf6 | 137 | int cc_op_synced; |
0633879f | 138 | int user; |
e6e5906b PB |
139 | uint32_t fpcr; |
140 | struct TranslationBlock *tb; | |
141 | int singlestep_enabled; | |
a7812ae4 PB |
142 | TCGv_i64 mactmp; |
143 | int done_mac; | |
8a1e52b6 RH |
144 | int writeback_mask; |
145 | TCGv writeback[8]; | |
e6e5906b PB |
146 | } DisasContext; |
147 | ||
8a1e52b6 RH |
148 | static TCGv get_areg(DisasContext *s, unsigned regno) |
149 | { | |
150 | if (s->writeback_mask & (1 << regno)) { | |
151 | return s->writeback[regno]; | |
152 | } else { | |
153 | return cpu_aregs[regno]; | |
154 | } | |
155 | } | |
156 | ||
157 | static void delay_set_areg(DisasContext *s, unsigned regno, | |
158 | TCGv val, bool give_temp) | |
159 | { | |
160 | if (s->writeback_mask & (1 << regno)) { | |
161 | if (give_temp) { | |
162 | tcg_temp_free(s->writeback[regno]); | |
163 | s->writeback[regno] = val; | |
164 | } else { | |
165 | tcg_gen_mov_i32(s->writeback[regno], val); | |
166 | } | |
167 | } else { | |
168 | s->writeback_mask |= 1 << regno; | |
169 | if (give_temp) { | |
170 | s->writeback[regno] = val; | |
171 | } else { | |
172 | TCGv tmp = tcg_temp_new(); | |
173 | s->writeback[regno] = tmp; | |
174 | tcg_gen_mov_i32(tmp, val); | |
175 | } | |
176 | } | |
177 | } | |
178 | ||
179 | static void do_writebacks(DisasContext *s) | |
180 | { | |
181 | unsigned mask = s->writeback_mask; | |
182 | if (mask) { | |
183 | s->writeback_mask = 0; | |
184 | do { | |
185 | unsigned regno = ctz32(mask); | |
186 | tcg_gen_mov_i32(cpu_aregs[regno], s->writeback[regno]); | |
187 | tcg_temp_free(s->writeback[regno]); | |
188 | mask &= mask - 1; | |
189 | } while (mask); | |
190 | } | |
191 | } | |
192 | ||
e6e5906b PB |
193 | #define DISAS_JUMP_NEXT 4 |
194 | ||
0633879f PB |
195 | #if defined(CONFIG_USER_ONLY) |
196 | #define IS_USER(s) 1 | |
197 | #else | |
198 | #define IS_USER(s) s->user | |
199 | #endif | |
200 | ||
e6e5906b PB |
201 | /* XXX: move that elsewhere */ |
202 | /* ??? Fix exceptions. */ | |
203 | static void *gen_throws_exception; | |
204 | #define gen_last_qop NULL | |
205 | ||
d4d79bb1 | 206 | typedef void (*disas_proc)(CPUM68KState *env, DisasContext *s, uint16_t insn); |
e6e5906b | 207 | |
0633879f | 208 | #ifdef DEBUG_DISPATCH |
d4d79bb1 BS |
209 | #define DISAS_INSN(name) \ |
210 | static void real_disas_##name(CPUM68KState *env, DisasContext *s, \ | |
211 | uint16_t insn); \ | |
212 | static void disas_##name(CPUM68KState *env, DisasContext *s, \ | |
213 | uint16_t insn) \ | |
214 | { \ | |
215 | qemu_log("Dispatch " #name "\n"); \ | |
a1ff1930 | 216 | real_disas_##name(env, s, insn); \ |
d4d79bb1 BS |
217 | } \ |
218 | static void real_disas_##name(CPUM68KState *env, DisasContext *s, \ | |
219 | uint16_t insn) | |
0633879f | 220 | #else |
d4d79bb1 BS |
221 | #define DISAS_INSN(name) \ |
222 | static void disas_##name(CPUM68KState *env, DisasContext *s, \ | |
223 | uint16_t insn) | |
0633879f | 224 | #endif |
e6e5906b | 225 | |
9fdb533f | 226 | static const uint8_t cc_op_live[CC_OP_NB] = { |
620c6cf6 | 227 | [CC_OP_FLAGS] = CCF_C | CCF_V | CCF_Z | CCF_N | CCF_X, |
db3d7945 LV |
228 | [CC_OP_ADDB ... CC_OP_ADDL] = CCF_X | CCF_N | CCF_V, |
229 | [CC_OP_SUBB ... CC_OP_SUBL] = CCF_X | CCF_N | CCF_V, | |
230 | [CC_OP_CMPB ... CC_OP_CMPL] = CCF_X | CCF_N | CCF_V, | |
620c6cf6 | 231 | [CC_OP_LOGIC] = CCF_X | CCF_N |
9fdb533f LV |
232 | }; |
233 | ||
234 | static void set_cc_op(DisasContext *s, CCOp op) | |
235 | { | |
620c6cf6 | 236 | CCOp old_op = s->cc_op; |
9fdb533f LV |
237 | int dead; |
238 | ||
620c6cf6 | 239 | if (old_op == op) { |
9fdb533f LV |
240 | return; |
241 | } | |
620c6cf6 RH |
242 | s->cc_op = op; |
243 | s->cc_op_synced = 0; | |
9fdb533f | 244 | |
620c6cf6 RH |
245 | /* Discard CC computation that will no longer be used. |
246 | Note that X and N are never dead. */ | |
247 | dead = cc_op_live[old_op] & ~cc_op_live[op]; | |
248 | if (dead & CCF_C) { | |
249 | tcg_gen_discard_i32(QREG_CC_C); | |
9fdb533f | 250 | } |
620c6cf6 RH |
251 | if (dead & CCF_Z) { |
252 | tcg_gen_discard_i32(QREG_CC_Z); | |
9fdb533f | 253 | } |
620c6cf6 RH |
254 | if (dead & CCF_V) { |
255 | tcg_gen_discard_i32(QREG_CC_V); | |
9fdb533f | 256 | } |
9fdb533f LV |
257 | } |
258 | ||
259 | /* Update the CPU env CC_OP state. */ | |
620c6cf6 | 260 | static void update_cc_op(DisasContext *s) |
9fdb533f | 261 | { |
620c6cf6 RH |
262 | if (!s->cc_op_synced) { |
263 | s->cc_op_synced = 1; | |
9fdb533f LV |
264 | tcg_gen_movi_i32(QREG_CC_OP, s->cc_op); |
265 | } | |
266 | } | |
267 | ||
e6e5906b PB |
268 | /* Generate a load from the specified address. Narrow values are |
269 | sign extended to full register width. */ | |
e1f3808e | 270 | static inline TCGv gen_load(DisasContext * s, int opsize, TCGv addr, int sign) |
e6e5906b | 271 | { |
e1f3808e PB |
272 | TCGv tmp; |
273 | int index = IS_USER(s); | |
a7812ae4 | 274 | tmp = tcg_temp_new_i32(); |
e6e5906b PB |
275 | switch(opsize) { |
276 | case OS_BYTE: | |
e6e5906b | 277 | if (sign) |
e1f3808e | 278 | tcg_gen_qemu_ld8s(tmp, addr, index); |
e6e5906b | 279 | else |
e1f3808e | 280 | tcg_gen_qemu_ld8u(tmp, addr, index); |
e6e5906b PB |
281 | break; |
282 | case OS_WORD: | |
e6e5906b | 283 | if (sign) |
e1f3808e | 284 | tcg_gen_qemu_ld16s(tmp, addr, index); |
e6e5906b | 285 | else |
e1f3808e | 286 | tcg_gen_qemu_ld16u(tmp, addr, index); |
e6e5906b PB |
287 | break; |
288 | case OS_LONG: | |
e6e5906b | 289 | case OS_SINGLE: |
a7812ae4 | 290 | tcg_gen_qemu_ld32u(tmp, addr, index); |
e6e5906b PB |
291 | break; |
292 | default: | |
7372c2b9 | 293 | g_assert_not_reached(); |
e6e5906b PB |
294 | } |
295 | gen_throws_exception = gen_last_qop; | |
296 | return tmp; | |
297 | } | |
298 | ||
a7812ae4 PB |
299 | static inline TCGv_i64 gen_load64(DisasContext * s, TCGv addr) |
300 | { | |
301 | TCGv_i64 tmp; | |
302 | int index = IS_USER(s); | |
a7812ae4 PB |
303 | tmp = tcg_temp_new_i64(); |
304 | tcg_gen_qemu_ldf64(tmp, addr, index); | |
305 | gen_throws_exception = gen_last_qop; | |
306 | return tmp; | |
307 | } | |
308 | ||
e6e5906b | 309 | /* Generate a store. */ |
e1f3808e | 310 | static inline void gen_store(DisasContext *s, int opsize, TCGv addr, TCGv val) |
e6e5906b | 311 | { |
e1f3808e | 312 | int index = IS_USER(s); |
e6e5906b PB |
313 | switch(opsize) { |
314 | case OS_BYTE: | |
e1f3808e | 315 | tcg_gen_qemu_st8(val, addr, index); |
e6e5906b PB |
316 | break; |
317 | case OS_WORD: | |
e1f3808e | 318 | tcg_gen_qemu_st16(val, addr, index); |
e6e5906b PB |
319 | break; |
320 | case OS_LONG: | |
e6e5906b | 321 | case OS_SINGLE: |
a7812ae4 | 322 | tcg_gen_qemu_st32(val, addr, index); |
e6e5906b PB |
323 | break; |
324 | default: | |
7372c2b9 | 325 | g_assert_not_reached(); |
e6e5906b PB |
326 | } |
327 | gen_throws_exception = gen_last_qop; | |
328 | } | |
329 | ||
a7812ae4 PB |
330 | static inline void gen_store64(DisasContext *s, TCGv addr, TCGv_i64 val) |
331 | { | |
332 | int index = IS_USER(s); | |
a7812ae4 PB |
333 | tcg_gen_qemu_stf64(val, addr, index); |
334 | gen_throws_exception = gen_last_qop; | |
335 | } | |
336 | ||
e1f3808e PB |
337 | typedef enum { |
338 | EA_STORE, | |
339 | EA_LOADU, | |
340 | EA_LOADS | |
341 | } ea_what; | |
342 | ||
e6e5906b PB |
343 | /* Generate an unsigned load if VAL is 0 a signed load if val is -1, |
344 | otherwise generate a store. */ | |
e1f3808e PB |
345 | static TCGv gen_ldst(DisasContext *s, int opsize, TCGv addr, TCGv val, |
346 | ea_what what) | |
e6e5906b | 347 | { |
e1f3808e | 348 | if (what == EA_STORE) { |
0633879f | 349 | gen_store(s, opsize, addr, val); |
e1f3808e | 350 | return store_dummy; |
e6e5906b | 351 | } else { |
e1f3808e | 352 | return gen_load(s, opsize, addr, what == EA_LOADS); |
e6e5906b PB |
353 | } |
354 | } | |
355 | ||
28b68cd7 LV |
356 | /* Read a 16-bit immediate constant */ |
357 | static inline uint16_t read_im16(CPUM68KState *env, DisasContext *s) | |
358 | { | |
359 | uint16_t im; | |
360 | im = cpu_lduw_code(env, s->pc); | |
361 | s->pc += 2; | |
362 | return im; | |
363 | } | |
364 | ||
365 | /* Read an 8-bit immediate constant */ | |
366 | static inline uint8_t read_im8(CPUM68KState *env, DisasContext *s) | |
367 | { | |
368 | return read_im16(env, s); | |
369 | } | |
370 | ||
e6dbd3b3 | 371 | /* Read a 32-bit immediate constant. */ |
d4d79bb1 | 372 | static inline uint32_t read_im32(CPUM68KState *env, DisasContext *s) |
e6dbd3b3 PB |
373 | { |
374 | uint32_t im; | |
28b68cd7 LV |
375 | im = read_im16(env, s) << 16; |
376 | im |= 0xffff & read_im16(env, s); | |
e6dbd3b3 PB |
377 | return im; |
378 | } | |
379 | ||
380 | /* Calculate and address index. */ | |
8a1e52b6 | 381 | static TCGv gen_addr_index(DisasContext *s, uint16_t ext, TCGv tmp) |
e6dbd3b3 | 382 | { |
e1f3808e | 383 | TCGv add; |
e6dbd3b3 PB |
384 | int scale; |
385 | ||
386 | add = (ext & 0x8000) ? AREG(ext, 12) : DREG(ext, 12); | |
387 | if ((ext & 0x800) == 0) { | |
e1f3808e | 388 | tcg_gen_ext16s_i32(tmp, add); |
e6dbd3b3 PB |
389 | add = tmp; |
390 | } | |
391 | scale = (ext >> 9) & 3; | |
392 | if (scale != 0) { | |
e1f3808e | 393 | tcg_gen_shli_i32(tmp, add, scale); |
e6dbd3b3 PB |
394 | add = tmp; |
395 | } | |
396 | return add; | |
397 | } | |
398 | ||
e1f3808e PB |
399 | /* Handle a base + index + displacement effective addresss. |
400 | A NULL_QREG base means pc-relative. */ | |
a4356126 | 401 | static TCGv gen_lea_indexed(CPUM68KState *env, DisasContext *s, TCGv base) |
e6e5906b | 402 | { |
e6e5906b PB |
403 | uint32_t offset; |
404 | uint16_t ext; | |
e1f3808e PB |
405 | TCGv add; |
406 | TCGv tmp; | |
e6dbd3b3 | 407 | uint32_t bd, od; |
e6e5906b PB |
408 | |
409 | offset = s->pc; | |
28b68cd7 | 410 | ext = read_im16(env, s); |
e6dbd3b3 PB |
411 | |
412 | if ((ext & 0x800) == 0 && !m68k_feature(s->env, M68K_FEATURE_WORD_INDEX)) | |
e1f3808e | 413 | return NULL_QREG; |
e6dbd3b3 | 414 | |
d8633620 LV |
415 | if (m68k_feature(s->env, M68K_FEATURE_M68000) && |
416 | !m68k_feature(s->env, M68K_FEATURE_SCALED_INDEX)) { | |
417 | ext &= ~(3 << 9); | |
418 | } | |
419 | ||
e6dbd3b3 PB |
420 | if (ext & 0x100) { |
421 | /* full extension word format */ | |
422 | if (!m68k_feature(s->env, M68K_FEATURE_EXT_FULL)) | |
e1f3808e | 423 | return NULL_QREG; |
e6dbd3b3 PB |
424 | |
425 | if ((ext & 0x30) > 0x10) { | |
426 | /* base displacement */ | |
427 | if ((ext & 0x30) == 0x20) { | |
28b68cd7 | 428 | bd = (int16_t)read_im16(env, s); |
e6dbd3b3 | 429 | } else { |
d4d79bb1 | 430 | bd = read_im32(env, s); |
e6dbd3b3 PB |
431 | } |
432 | } else { | |
433 | bd = 0; | |
434 | } | |
a7812ae4 | 435 | tmp = tcg_temp_new(); |
e6dbd3b3 PB |
436 | if ((ext & 0x44) == 0) { |
437 | /* pre-index */ | |
8a1e52b6 | 438 | add = gen_addr_index(s, ext, tmp); |
e6dbd3b3 | 439 | } else { |
e1f3808e | 440 | add = NULL_QREG; |
e6dbd3b3 PB |
441 | } |
442 | if ((ext & 0x80) == 0) { | |
443 | /* base not suppressed */ | |
e1f3808e | 444 | if (IS_NULL_QREG(base)) { |
351326a6 | 445 | base = tcg_const_i32(offset + bd); |
e6dbd3b3 PB |
446 | bd = 0; |
447 | } | |
e1f3808e PB |
448 | if (!IS_NULL_QREG(add)) { |
449 | tcg_gen_add_i32(tmp, add, base); | |
e6dbd3b3 PB |
450 | add = tmp; |
451 | } else { | |
452 | add = base; | |
453 | } | |
454 | } | |
e1f3808e | 455 | if (!IS_NULL_QREG(add)) { |
e6dbd3b3 | 456 | if (bd != 0) { |
e1f3808e | 457 | tcg_gen_addi_i32(tmp, add, bd); |
e6dbd3b3 PB |
458 | add = tmp; |
459 | } | |
460 | } else { | |
351326a6 | 461 | add = tcg_const_i32(bd); |
e6dbd3b3 PB |
462 | } |
463 | if ((ext & 3) != 0) { | |
464 | /* memory indirect */ | |
465 | base = gen_load(s, OS_LONG, add, 0); | |
466 | if ((ext & 0x44) == 4) { | |
8a1e52b6 | 467 | add = gen_addr_index(s, ext, tmp); |
e1f3808e | 468 | tcg_gen_add_i32(tmp, add, base); |
e6dbd3b3 PB |
469 | add = tmp; |
470 | } else { | |
471 | add = base; | |
472 | } | |
473 | if ((ext & 3) > 1) { | |
474 | /* outer displacement */ | |
475 | if ((ext & 3) == 2) { | |
28b68cd7 | 476 | od = (int16_t)read_im16(env, s); |
e6dbd3b3 | 477 | } else { |
d4d79bb1 | 478 | od = read_im32(env, s); |
e6dbd3b3 PB |
479 | } |
480 | } else { | |
481 | od = 0; | |
482 | } | |
483 | if (od != 0) { | |
e1f3808e | 484 | tcg_gen_addi_i32(tmp, add, od); |
e6dbd3b3 PB |
485 | add = tmp; |
486 | } | |
487 | } | |
e6e5906b | 488 | } else { |
e6dbd3b3 | 489 | /* brief extension word format */ |
a7812ae4 | 490 | tmp = tcg_temp_new(); |
8a1e52b6 | 491 | add = gen_addr_index(s, ext, tmp); |
e1f3808e PB |
492 | if (!IS_NULL_QREG(base)) { |
493 | tcg_gen_add_i32(tmp, add, base); | |
e6dbd3b3 | 494 | if ((int8_t)ext) |
e1f3808e | 495 | tcg_gen_addi_i32(tmp, tmp, (int8_t)ext); |
e6dbd3b3 | 496 | } else { |
e1f3808e | 497 | tcg_gen_addi_i32(tmp, add, offset + (int8_t)ext); |
e6dbd3b3 PB |
498 | } |
499 | add = tmp; | |
e6e5906b | 500 | } |
e6dbd3b3 | 501 | return add; |
e6e5906b PB |
502 | } |
503 | ||
db3d7945 LV |
504 | /* Sign or zero extend a value. */ |
505 | ||
506 | static inline void gen_ext(TCGv res, TCGv val, int opsize, int sign) | |
507 | { | |
508 | switch (opsize) { | |
509 | case OS_BYTE: | |
510 | if (sign) { | |
511 | tcg_gen_ext8s_i32(res, val); | |
512 | } else { | |
513 | tcg_gen_ext8u_i32(res, val); | |
514 | } | |
515 | break; | |
516 | case OS_WORD: | |
517 | if (sign) { | |
518 | tcg_gen_ext16s_i32(res, val); | |
519 | } else { | |
520 | tcg_gen_ext16u_i32(res, val); | |
521 | } | |
522 | break; | |
523 | case OS_LONG: | |
524 | tcg_gen_mov_i32(res, val); | |
525 | break; | |
526 | default: | |
527 | g_assert_not_reached(); | |
528 | } | |
529 | } | |
530 | ||
e6e5906b | 531 | /* Evaluate all the CC flags. */ |
9fdb533f | 532 | |
620c6cf6 | 533 | static void gen_flush_flags(DisasContext *s) |
e6e5906b | 534 | { |
36f0399d | 535 | TCGv t0, t1; |
620c6cf6 RH |
536 | |
537 | switch (s->cc_op) { | |
538 | case CC_OP_FLAGS: | |
e6e5906b | 539 | return; |
36f0399d | 540 | |
db3d7945 LV |
541 | case CC_OP_ADDB: |
542 | case CC_OP_ADDW: | |
543 | case CC_OP_ADDL: | |
36f0399d RH |
544 | tcg_gen_mov_i32(QREG_CC_C, QREG_CC_X); |
545 | tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N); | |
546 | /* Compute signed overflow for addition. */ | |
547 | t0 = tcg_temp_new(); | |
548 | t1 = tcg_temp_new(); | |
549 | tcg_gen_sub_i32(t0, QREG_CC_N, QREG_CC_V); | |
db3d7945 | 550 | gen_ext(t0, t0, s->cc_op - CC_OP_ADDB, 1); |
36f0399d RH |
551 | tcg_gen_xor_i32(t1, QREG_CC_N, QREG_CC_V); |
552 | tcg_gen_xor_i32(QREG_CC_V, QREG_CC_V, t0); | |
553 | tcg_temp_free(t0); | |
554 | tcg_gen_andc_i32(QREG_CC_V, t1, QREG_CC_V); | |
555 | tcg_temp_free(t1); | |
556 | break; | |
557 | ||
db3d7945 LV |
558 | case CC_OP_SUBB: |
559 | case CC_OP_SUBW: | |
560 | case CC_OP_SUBL: | |
36f0399d RH |
561 | tcg_gen_mov_i32(QREG_CC_C, QREG_CC_X); |
562 | tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N); | |
563 | /* Compute signed overflow for subtraction. */ | |
564 | t0 = tcg_temp_new(); | |
565 | t1 = tcg_temp_new(); | |
566 | tcg_gen_add_i32(t0, QREG_CC_N, QREG_CC_V); | |
db3d7945 | 567 | gen_ext(t0, t0, s->cc_op - CC_OP_SUBB, 1); |
36f0399d RH |
568 | tcg_gen_xor_i32(t1, QREG_CC_N, QREG_CC_V); |
569 | tcg_gen_xor_i32(QREG_CC_V, QREG_CC_V, t0); | |
570 | tcg_temp_free(t0); | |
571 | tcg_gen_and_i32(QREG_CC_V, QREG_CC_V, t1); | |
572 | tcg_temp_free(t1); | |
573 | break; | |
574 | ||
db3d7945 LV |
575 | case CC_OP_CMPB: |
576 | case CC_OP_CMPW: | |
577 | case CC_OP_CMPL: | |
36f0399d RH |
578 | tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_C, QREG_CC_N, QREG_CC_V); |
579 | tcg_gen_sub_i32(QREG_CC_Z, QREG_CC_N, QREG_CC_V); | |
db3d7945 | 580 | gen_ext(QREG_CC_Z, QREG_CC_Z, s->cc_op - CC_OP_CMPB, 1); |
36f0399d RH |
581 | /* Compute signed overflow for subtraction. */ |
582 | t0 = tcg_temp_new(); | |
583 | tcg_gen_xor_i32(t0, QREG_CC_Z, QREG_CC_N); | |
584 | tcg_gen_xor_i32(QREG_CC_V, QREG_CC_V, QREG_CC_N); | |
585 | tcg_gen_and_i32(QREG_CC_V, QREG_CC_V, t0); | |
586 | tcg_temp_free(t0); | |
587 | tcg_gen_mov_i32(QREG_CC_N, QREG_CC_Z); | |
588 | break; | |
589 | ||
590 | case CC_OP_LOGIC: | |
591 | tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N); | |
592 | tcg_gen_movi_i32(QREG_CC_C, 0); | |
593 | tcg_gen_movi_i32(QREG_CC_V, 0); | |
594 | break; | |
595 | ||
620c6cf6 RH |
596 | case CC_OP_DYNAMIC: |
597 | gen_helper_flush_flags(cpu_env, QREG_CC_OP); | |
695576db | 598 | s->cc_op_synced = 1; |
620c6cf6 | 599 | break; |
36f0399d | 600 | |
620c6cf6 | 601 | default: |
36f0399d RH |
602 | t0 = tcg_const_i32(s->cc_op); |
603 | gen_helper_flush_flags(cpu_env, t0); | |
604 | tcg_temp_free(t0); | |
695576db | 605 | s->cc_op_synced = 1; |
620c6cf6 RH |
606 | break; |
607 | } | |
608 | ||
609 | /* Note that flush_flags also assigned to env->cc_op. */ | |
610 | s->cc_op = CC_OP_FLAGS; | |
620c6cf6 RH |
611 | } |
612 | ||
db3d7945 | 613 | static inline TCGv gen_extend(TCGv val, int opsize, int sign) |
620c6cf6 RH |
614 | { |
615 | TCGv tmp; | |
616 | ||
617 | if (opsize == OS_LONG) { | |
618 | tmp = val; | |
619 | } else { | |
620 | tmp = tcg_temp_new(); | |
621 | gen_ext(tmp, val, opsize, sign); | |
622 | } | |
623 | ||
624 | return tmp; | |
625 | } | |
5dbb6784 LV |
626 | |
627 | static void gen_logic_cc(DisasContext *s, TCGv val, int opsize) | |
e1f3808e | 628 | { |
620c6cf6 RH |
629 | gen_ext(QREG_CC_N, val, opsize, 1); |
630 | set_cc_op(s, CC_OP_LOGIC); | |
e1f3808e PB |
631 | } |
632 | ||
ff99b952 LV |
633 | static void gen_update_cc_cmp(DisasContext *s, TCGv dest, TCGv src, int opsize) |
634 | { | |
635 | tcg_gen_mov_i32(QREG_CC_N, dest); | |
636 | tcg_gen_mov_i32(QREG_CC_V, src); | |
637 | set_cc_op(s, CC_OP_CMPB + opsize); | |
638 | } | |
639 | ||
db3d7945 | 640 | static void gen_update_cc_add(TCGv dest, TCGv src, int opsize) |
e1f3808e | 641 | { |
db3d7945 | 642 | gen_ext(QREG_CC_N, dest, opsize, 1); |
620c6cf6 | 643 | tcg_gen_mov_i32(QREG_CC_V, src); |
e1f3808e PB |
644 | } |
645 | ||
e6e5906b PB |
646 | static inline int opsize_bytes(int opsize) |
647 | { | |
648 | switch (opsize) { | |
649 | case OS_BYTE: return 1; | |
650 | case OS_WORD: return 2; | |
651 | case OS_LONG: return 4; | |
652 | case OS_SINGLE: return 4; | |
653 | case OS_DOUBLE: return 8; | |
7ef25cdd LV |
654 | case OS_EXTENDED: return 12; |
655 | case OS_PACKED: return 12; | |
656 | default: | |
657 | g_assert_not_reached(); | |
658 | } | |
659 | } | |
660 | ||
661 | static inline int insn_opsize(int insn) | |
662 | { | |
663 | switch ((insn >> 6) & 3) { | |
664 | case 0: return OS_BYTE; | |
665 | case 1: return OS_WORD; | |
666 | case 2: return OS_LONG; | |
e6e5906b | 667 | default: |
7372c2b9 | 668 | g_assert_not_reached(); |
e6e5906b PB |
669 | } |
670 | } | |
671 | ||
672 | /* Assign value to a register. If the width is less than the register width | |
673 | only the low part of the register is set. */ | |
e1f3808e | 674 | static void gen_partset_reg(int opsize, TCGv reg, TCGv val) |
e6e5906b | 675 | { |
e1f3808e | 676 | TCGv tmp; |
e6e5906b PB |
677 | switch (opsize) { |
678 | case OS_BYTE: | |
e1f3808e | 679 | tcg_gen_andi_i32(reg, reg, 0xffffff00); |
a7812ae4 | 680 | tmp = tcg_temp_new(); |
e1f3808e PB |
681 | tcg_gen_ext8u_i32(tmp, val); |
682 | tcg_gen_or_i32(reg, reg, tmp); | |
2b5e2170 | 683 | tcg_temp_free(tmp); |
e6e5906b PB |
684 | break; |
685 | case OS_WORD: | |
e1f3808e | 686 | tcg_gen_andi_i32(reg, reg, 0xffff0000); |
a7812ae4 | 687 | tmp = tcg_temp_new(); |
e1f3808e PB |
688 | tcg_gen_ext16u_i32(tmp, val); |
689 | tcg_gen_or_i32(reg, reg, tmp); | |
2b5e2170 | 690 | tcg_temp_free(tmp); |
e6e5906b PB |
691 | break; |
692 | case OS_LONG: | |
e6e5906b | 693 | case OS_SINGLE: |
a7812ae4 | 694 | tcg_gen_mov_i32(reg, val); |
e6e5906b PB |
695 | break; |
696 | default: | |
7372c2b9 | 697 | g_assert_not_reached(); |
e6e5906b PB |
698 | } |
699 | } | |
700 | ||
e6e5906b | 701 | /* Generate code for an "effective address". Does not adjust the base |
1addc7c5 | 702 | register for autoincrement addressing modes. */ |
f84aab26 RH |
703 | static TCGv gen_lea_mode(CPUM68KState *env, DisasContext *s, |
704 | int mode, int reg0, int opsize) | |
e6e5906b | 705 | { |
e1f3808e PB |
706 | TCGv reg; |
707 | TCGv tmp; | |
e6e5906b PB |
708 | uint16_t ext; |
709 | uint32_t offset; | |
710 | ||
f84aab26 | 711 | switch (mode) { |
e6e5906b PB |
712 | case 0: /* Data register direct. */ |
713 | case 1: /* Address register direct. */ | |
e1f3808e | 714 | return NULL_QREG; |
e6e5906b | 715 | case 3: /* Indirect postincrement. */ |
f2224f2c RH |
716 | if (opsize == OS_UNSIZED) { |
717 | return NULL_QREG; | |
718 | } | |
719 | /* fallthru */ | |
720 | case 2: /* Indirect register */ | |
f84aab26 | 721 | return get_areg(s, reg0); |
e6e5906b | 722 | case 4: /* Indirect predecrememnt. */ |
f2224f2c RH |
723 | if (opsize == OS_UNSIZED) { |
724 | return NULL_QREG; | |
725 | } | |
f84aab26 | 726 | reg = get_areg(s, reg0); |
a7812ae4 | 727 | tmp = tcg_temp_new(); |
727d937b LV |
728 | if (reg0 == 7 && opsize == OS_BYTE && |
729 | m68k_feature(s->env, M68K_FEATURE_M68000)) { | |
730 | tcg_gen_subi_i32(tmp, reg, 2); | |
731 | } else { | |
732 | tcg_gen_subi_i32(tmp, reg, opsize_bytes(opsize)); | |
733 | } | |
e6e5906b PB |
734 | return tmp; |
735 | case 5: /* Indirect displacement. */ | |
f84aab26 | 736 | reg = get_areg(s, reg0); |
a7812ae4 | 737 | tmp = tcg_temp_new(); |
28b68cd7 | 738 | ext = read_im16(env, s); |
e1f3808e | 739 | tcg_gen_addi_i32(tmp, reg, (int16_t)ext); |
e6e5906b PB |
740 | return tmp; |
741 | case 6: /* Indirect index + displacement. */ | |
f84aab26 | 742 | reg = get_areg(s, reg0); |
a4356126 | 743 | return gen_lea_indexed(env, s, reg); |
e6e5906b | 744 | case 7: /* Other */ |
f84aab26 | 745 | switch (reg0) { |
e6e5906b | 746 | case 0: /* Absolute short. */ |
28b68cd7 | 747 | offset = (int16_t)read_im16(env, s); |
351326a6 | 748 | return tcg_const_i32(offset); |
e6e5906b | 749 | case 1: /* Absolute long. */ |
d4d79bb1 | 750 | offset = read_im32(env, s); |
351326a6 | 751 | return tcg_const_i32(offset); |
e6e5906b | 752 | case 2: /* pc displacement */ |
e6e5906b | 753 | offset = s->pc; |
28b68cd7 | 754 | offset += (int16_t)read_im16(env, s); |
351326a6 | 755 | return tcg_const_i32(offset); |
e6e5906b | 756 | case 3: /* pc index+displacement. */ |
a4356126 | 757 | return gen_lea_indexed(env, s, NULL_QREG); |
e6e5906b PB |
758 | case 4: /* Immediate. */ |
759 | default: | |
e1f3808e | 760 | return NULL_QREG; |
e6e5906b PB |
761 | } |
762 | } | |
763 | /* Should never happen. */ | |
e1f3808e | 764 | return NULL_QREG; |
e6e5906b PB |
765 | } |
766 | ||
f84aab26 RH |
767 | static TCGv gen_lea(CPUM68KState *env, DisasContext *s, uint16_t insn, |
768 | int opsize) | |
e6e5906b | 769 | { |
f84aab26 RH |
770 | int mode = extract32(insn, 3, 3); |
771 | int reg0 = REG(insn, 0); | |
772 | return gen_lea_mode(env, s, mode, reg0, opsize); | |
e6e5906b PB |
773 | } |
774 | ||
f84aab26 | 775 | /* Generate code to load/store a value from/into an EA. If WHAT > 0 this is |
e6e5906b PB |
776 | a write otherwise it is a read (0 == sign extend, -1 == zero extend). |
777 | ADDRP is non-null for readwrite operands. */ | |
f84aab26 RH |
778 | static TCGv gen_ea_mode(CPUM68KState *env, DisasContext *s, int mode, int reg0, |
779 | int opsize, TCGv val, TCGv *addrp, ea_what what) | |
e6e5906b | 780 | { |
f84aab26 RH |
781 | TCGv reg, tmp, result; |
782 | int32_t offset; | |
e6e5906b | 783 | |
f84aab26 | 784 | switch (mode) { |
e6e5906b | 785 | case 0: /* Data register direct. */ |
f84aab26 | 786 | reg = cpu_dregs[reg0]; |
e1f3808e | 787 | if (what == EA_STORE) { |
e6e5906b | 788 | gen_partset_reg(opsize, reg, val); |
e1f3808e | 789 | return store_dummy; |
e6e5906b | 790 | } else { |
e1f3808e | 791 | return gen_extend(reg, opsize, what == EA_LOADS); |
e6e5906b PB |
792 | } |
793 | case 1: /* Address register direct. */ | |
f84aab26 | 794 | reg = get_areg(s, reg0); |
e1f3808e PB |
795 | if (what == EA_STORE) { |
796 | tcg_gen_mov_i32(reg, val); | |
797 | return store_dummy; | |
e6e5906b | 798 | } else { |
e1f3808e | 799 | return gen_extend(reg, opsize, what == EA_LOADS); |
e6e5906b PB |
800 | } |
801 | case 2: /* Indirect register */ | |
f84aab26 | 802 | reg = get_areg(s, reg0); |
e1f3808e | 803 | return gen_ldst(s, opsize, reg, val, what); |
e6e5906b | 804 | case 3: /* Indirect postincrement. */ |
f84aab26 | 805 | reg = get_areg(s, reg0); |
e1f3808e | 806 | result = gen_ldst(s, opsize, reg, val, what); |
8a1e52b6 RH |
807 | if (what == EA_STORE || !addrp) { |
808 | TCGv tmp = tcg_temp_new(); | |
727d937b LV |
809 | if (reg0 == 7 && opsize == OS_BYTE && |
810 | m68k_feature(s->env, M68K_FEATURE_M68000)) { | |
811 | tcg_gen_addi_i32(tmp, reg, 2); | |
812 | } else { | |
813 | tcg_gen_addi_i32(tmp, reg, opsize_bytes(opsize)); | |
814 | } | |
f84aab26 | 815 | delay_set_areg(s, reg0, tmp, true); |
8a1e52b6 | 816 | } |
e6e5906b PB |
817 | return result; |
818 | case 4: /* Indirect predecrememnt. */ | |
f84aab26 RH |
819 | if (addrp && what == EA_STORE) { |
820 | tmp = *addrp; | |
821 | } else { | |
822 | tmp = gen_lea_mode(env, s, mode, reg0, opsize); | |
823 | if (IS_NULL_QREG(tmp)) { | |
824 | return tmp; | |
e6e5906b | 825 | } |
f84aab26 RH |
826 | if (addrp) { |
827 | *addrp = tmp; | |
e6e5906b PB |
828 | } |
829 | } | |
f84aab26 RH |
830 | result = gen_ldst(s, opsize, tmp, val, what); |
831 | if (what == EA_STORE || !addrp) { | |
832 | delay_set_areg(s, reg0, tmp, false); | |
833 | } | |
e6e5906b PB |
834 | return result; |
835 | case 5: /* Indirect displacement. */ | |
836 | case 6: /* Indirect index + displacement. */ | |
f84aab26 RH |
837 | do_indirect: |
838 | if (addrp && what == EA_STORE) { | |
839 | tmp = *addrp; | |
840 | } else { | |
841 | tmp = gen_lea_mode(env, s, mode, reg0, opsize); | |
842 | if (IS_NULL_QREG(tmp)) { | |
843 | return tmp; | |
844 | } | |
845 | if (addrp) { | |
846 | *addrp = tmp; | |
847 | } | |
848 | } | |
849 | return gen_ldst(s, opsize, tmp, val, what); | |
e6e5906b | 850 | case 7: /* Other */ |
f84aab26 | 851 | switch (reg0) { |
e6e5906b PB |
852 | case 0: /* Absolute short. */ |
853 | case 1: /* Absolute long. */ | |
854 | case 2: /* pc displacement */ | |
855 | case 3: /* pc index+displacement. */ | |
f84aab26 | 856 | goto do_indirect; |
e6e5906b PB |
857 | case 4: /* Immediate. */ |
858 | /* Sign extend values for consistency. */ | |
859 | switch (opsize) { | |
860 | case OS_BYTE: | |
31871141 | 861 | if (what == EA_LOADS) { |
28b68cd7 | 862 | offset = (int8_t)read_im8(env, s); |
31871141 | 863 | } else { |
28b68cd7 | 864 | offset = read_im8(env, s); |
31871141 | 865 | } |
e6e5906b PB |
866 | break; |
867 | case OS_WORD: | |
31871141 | 868 | if (what == EA_LOADS) { |
28b68cd7 | 869 | offset = (int16_t)read_im16(env, s); |
31871141 | 870 | } else { |
28b68cd7 | 871 | offset = read_im16(env, s); |
31871141 | 872 | } |
e6e5906b PB |
873 | break; |
874 | case OS_LONG: | |
d4d79bb1 | 875 | offset = read_im32(env, s); |
e6e5906b PB |
876 | break; |
877 | default: | |
7372c2b9 | 878 | g_assert_not_reached(); |
e6e5906b | 879 | } |
e1f3808e | 880 | return tcg_const_i32(offset); |
e6e5906b | 881 | default: |
e1f3808e | 882 | return NULL_QREG; |
e6e5906b PB |
883 | } |
884 | } | |
885 | /* Should never happen. */ | |
e1f3808e | 886 | return NULL_QREG; |
e6e5906b PB |
887 | } |
888 | ||
f84aab26 RH |
889 | static TCGv gen_ea(CPUM68KState *env, DisasContext *s, uint16_t insn, |
890 | int opsize, TCGv val, TCGv *addrp, ea_what what) | |
891 | { | |
892 | int mode = extract32(insn, 3, 3); | |
893 | int reg0 = REG(insn, 0); | |
894 | return gen_ea_mode(env, s, mode, reg0, opsize, val, addrp, what); | |
895 | } | |
896 | ||
6a432295 RH |
897 | typedef struct { |
898 | TCGCond tcond; | |
899 | bool g1; | |
900 | bool g2; | |
901 | TCGv v1; | |
902 | TCGv v2; | |
903 | } DisasCompare; | |
904 | ||
905 | static void gen_cc_cond(DisasCompare *c, DisasContext *s, int cond) | |
e6e5906b | 906 | { |
620c6cf6 RH |
907 | TCGv tmp, tmp2; |
908 | TCGCond tcond; | |
9d896621 | 909 | CCOp op = s->cc_op; |
e6e5906b | 910 | |
9d896621 | 911 | /* The CC_OP_CMP form can handle most normal comparisons directly. */ |
db3d7945 | 912 | if (op == CC_OP_CMPB || op == CC_OP_CMPW || op == CC_OP_CMPL) { |
9d896621 RH |
913 | c->g1 = c->g2 = 1; |
914 | c->v1 = QREG_CC_N; | |
915 | c->v2 = QREG_CC_V; | |
916 | switch (cond) { | |
917 | case 2: /* HI */ | |
918 | case 3: /* LS */ | |
919 | tcond = TCG_COND_LEU; | |
920 | goto done; | |
921 | case 4: /* CC */ | |
922 | case 5: /* CS */ | |
923 | tcond = TCG_COND_LTU; | |
924 | goto done; | |
925 | case 6: /* NE */ | |
926 | case 7: /* EQ */ | |
927 | tcond = TCG_COND_EQ; | |
928 | goto done; | |
929 | case 10: /* PL */ | |
930 | case 11: /* MI */ | |
931 | c->g1 = c->g2 = 0; | |
932 | c->v2 = tcg_const_i32(0); | |
933 | c->v1 = tmp = tcg_temp_new(); | |
934 | tcg_gen_sub_i32(tmp, QREG_CC_N, QREG_CC_V); | |
db3d7945 | 935 | gen_ext(tmp, tmp, op - CC_OP_CMPB, 1); |
9d896621 RH |
936 | /* fallthru */ |
937 | case 12: /* GE */ | |
938 | case 13: /* LT */ | |
939 | tcond = TCG_COND_LT; | |
940 | goto done; | |
941 | case 14: /* GT */ | |
942 | case 15: /* LE */ | |
943 | tcond = TCG_COND_LE; | |
944 | goto done; | |
945 | } | |
946 | } | |
6a432295 RH |
947 | |
948 | c->g1 = 1; | |
949 | c->g2 = 0; | |
950 | c->v2 = tcg_const_i32(0); | |
951 | ||
e6e5906b PB |
952 | switch (cond) { |
953 | case 0: /* T */ | |
e6e5906b | 954 | case 1: /* F */ |
6a432295 RH |
955 | c->v1 = c->v2; |
956 | tcond = TCG_COND_NEVER; | |
9d896621 RH |
957 | goto done; |
958 | case 14: /* GT (!(Z || (N ^ V))) */ | |
959 | case 15: /* LE (Z || (N ^ V)) */ | |
960 | /* Logic operations clear V, which simplifies LE to (Z || N), | |
961 | and since Z and N are co-located, this becomes a normal | |
962 | comparison vs N. */ | |
963 | if (op == CC_OP_LOGIC) { | |
964 | c->v1 = QREG_CC_N; | |
965 | tcond = TCG_COND_LE; | |
966 | goto done; | |
967 | } | |
6a432295 | 968 | break; |
9d896621 RH |
969 | case 12: /* GE (!(N ^ V)) */ |
970 | case 13: /* LT (N ^ V) */ | |
971 | /* Logic operations clear V, which simplifies this to N. */ | |
972 | if (op != CC_OP_LOGIC) { | |
973 | break; | |
974 | } | |
975 | /* fallthru */ | |
976 | case 10: /* PL (!N) */ | |
977 | case 11: /* MI (N) */ | |
978 | /* Several cases represent N normally. */ | |
db3d7945 LV |
979 | if (op == CC_OP_ADDB || op == CC_OP_ADDW || op == CC_OP_ADDL || |
980 | op == CC_OP_SUBB || op == CC_OP_SUBW || op == CC_OP_SUBL || | |
981 | op == CC_OP_LOGIC) { | |
9d896621 RH |
982 | c->v1 = QREG_CC_N; |
983 | tcond = TCG_COND_LT; | |
984 | goto done; | |
985 | } | |
986 | break; | |
987 | case 6: /* NE (!Z) */ | |
988 | case 7: /* EQ (Z) */ | |
989 | /* Some cases fold Z into N. */ | |
db3d7945 LV |
990 | if (op == CC_OP_ADDB || op == CC_OP_ADDW || op == CC_OP_ADDL || |
991 | op == CC_OP_SUBB || op == CC_OP_SUBW || op == CC_OP_SUBL || | |
992 | op == CC_OP_LOGIC) { | |
9d896621 RH |
993 | tcond = TCG_COND_EQ; |
994 | c->v1 = QREG_CC_N; | |
995 | goto done; | |
996 | } | |
997 | break; | |
998 | case 4: /* CC (!C) */ | |
999 | case 5: /* CS (C) */ | |
1000 | /* Some cases fold C into X. */ | |
db3d7945 LV |
1001 | if (op == CC_OP_ADDB || op == CC_OP_ADDW || op == CC_OP_ADDL || |
1002 | op == CC_OP_ADDB || op == CC_OP_ADDW || op == CC_OP_ADDL) { | |
9d896621 RH |
1003 | tcond = TCG_COND_NE; |
1004 | c->v1 = QREG_CC_X; | |
1005 | goto done; | |
1006 | } | |
1007 | /* fallthru */ | |
1008 | case 8: /* VC (!V) */ | |
1009 | case 9: /* VS (V) */ | |
1010 | /* Logic operations clear V and C. */ | |
1011 | if (op == CC_OP_LOGIC) { | |
1012 | tcond = TCG_COND_NEVER; | |
1013 | c->v1 = c->v2; | |
1014 | goto done; | |
1015 | } | |
1016 | break; | |
1017 | } | |
1018 | ||
1019 | /* Otherwise, flush flag state to CC_OP_FLAGS. */ | |
1020 | gen_flush_flags(s); | |
1021 | ||
1022 | switch (cond) { | |
1023 | case 0: /* T */ | |
1024 | case 1: /* F */ | |
1025 | default: | |
1026 | /* Invalid, or handled above. */ | |
1027 | abort(); | |
620c6cf6 | 1028 | case 2: /* HI (!C && !Z) -> !(C || Z)*/ |
e6e5906b | 1029 | case 3: /* LS (C || Z) */ |
6a432295 RH |
1030 | c->v1 = tmp = tcg_temp_new(); |
1031 | c->g1 = 0; | |
1032 | tcg_gen_setcond_i32(TCG_COND_EQ, tmp, QREG_CC_Z, c->v2); | |
620c6cf6 | 1033 | tcg_gen_or_i32(tmp, tmp, QREG_CC_C); |
6a432295 | 1034 | tcond = TCG_COND_NE; |
e6e5906b PB |
1035 | break; |
1036 | case 4: /* CC (!C) */ | |
e6e5906b | 1037 | case 5: /* CS (C) */ |
6a432295 RH |
1038 | c->v1 = QREG_CC_C; |
1039 | tcond = TCG_COND_NE; | |
e6e5906b PB |
1040 | break; |
1041 | case 6: /* NE (!Z) */ | |
e6e5906b | 1042 | case 7: /* EQ (Z) */ |
6a432295 RH |
1043 | c->v1 = QREG_CC_Z; |
1044 | tcond = TCG_COND_EQ; | |
e6e5906b PB |
1045 | break; |
1046 | case 8: /* VC (!V) */ | |
e6e5906b | 1047 | case 9: /* VS (V) */ |
6a432295 RH |
1048 | c->v1 = QREG_CC_V; |
1049 | tcond = TCG_COND_LT; | |
e6e5906b PB |
1050 | break; |
1051 | case 10: /* PL (!N) */ | |
e6e5906b | 1052 | case 11: /* MI (N) */ |
6a432295 RH |
1053 | c->v1 = QREG_CC_N; |
1054 | tcond = TCG_COND_LT; | |
e6e5906b PB |
1055 | break; |
1056 | case 12: /* GE (!(N ^ V)) */ | |
e6e5906b | 1057 | case 13: /* LT (N ^ V) */ |
6a432295 RH |
1058 | c->v1 = tmp = tcg_temp_new(); |
1059 | c->g1 = 0; | |
620c6cf6 | 1060 | tcg_gen_xor_i32(tmp, QREG_CC_N, QREG_CC_V); |
6a432295 | 1061 | tcond = TCG_COND_LT; |
e6e5906b PB |
1062 | break; |
1063 | case 14: /* GT (!(Z || (N ^ V))) */ | |
e6e5906b | 1064 | case 15: /* LE (Z || (N ^ V)) */ |
6a432295 RH |
1065 | c->v1 = tmp = tcg_temp_new(); |
1066 | c->g1 = 0; | |
1067 | tcg_gen_setcond_i32(TCG_COND_EQ, tmp, QREG_CC_Z, c->v2); | |
620c6cf6 RH |
1068 | tcg_gen_neg_i32(tmp, tmp); |
1069 | tmp2 = tcg_temp_new(); | |
1070 | tcg_gen_xor_i32(tmp2, QREG_CC_N, QREG_CC_V); | |
1071 | tcg_gen_or_i32(tmp, tmp, tmp2); | |
6a432295 RH |
1072 | tcg_temp_free(tmp2); |
1073 | tcond = TCG_COND_LT; | |
e6e5906b | 1074 | break; |
e6e5906b | 1075 | } |
9d896621 RH |
1076 | |
1077 | done: | |
6a432295 RH |
1078 | if ((cond & 1) == 0) { |
1079 | tcond = tcg_invert_cond(tcond); | |
1080 | } | |
1081 | c->tcond = tcond; | |
1082 | } | |
1083 | ||
1084 | static void free_cond(DisasCompare *c) | |
1085 | { | |
1086 | if (!c->g1) { | |
1087 | tcg_temp_free(c->v1); | |
1088 | } | |
1089 | if (!c->g2) { | |
1090 | tcg_temp_free(c->v2); | |
1091 | } | |
1092 | } | |
1093 | ||
1094 | static void gen_jmpcc(DisasContext *s, int cond, TCGLabel *l1) | |
1095 | { | |
1096 | DisasCompare c; | |
1097 | ||
1098 | gen_cc_cond(&c, s, cond); | |
1099 | update_cc_op(s); | |
1100 | tcg_gen_brcond_i32(c.tcond, c.v1, c.v2, l1); | |
1101 | free_cond(&c); | |
e6e5906b PB |
1102 | } |
1103 | ||
0633879f PB |
1104 | /* Force a TB lookup after an instruction that changes the CPU state. */ |
1105 | static void gen_lookup_tb(DisasContext *s) | |
1106 | { | |
9fdb533f | 1107 | update_cc_op(s); |
e1f3808e | 1108 | tcg_gen_movi_i32(QREG_PC, s->pc); |
0633879f PB |
1109 | s->is_jmp = DISAS_UPDATE; |
1110 | } | |
1111 | ||
e1f3808e PB |
1112 | /* Generate a jump to an immediate address. */ |
1113 | static void gen_jmp_im(DisasContext *s, uint32_t dest) | |
1114 | { | |
9fdb533f | 1115 | update_cc_op(s); |
e1f3808e PB |
1116 | tcg_gen_movi_i32(QREG_PC, dest); |
1117 | s->is_jmp = DISAS_JUMP; | |
1118 | } | |
1119 | ||
1120 | /* Generate a jump to the address in qreg DEST. */ | |
1121 | static void gen_jmp(DisasContext *s, TCGv dest) | |
e6e5906b | 1122 | { |
9fdb533f | 1123 | update_cc_op(s); |
e1f3808e | 1124 | tcg_gen_mov_i32(QREG_PC, dest); |
e6e5906b PB |
1125 | s->is_jmp = DISAS_JUMP; |
1126 | } | |
1127 | ||
2b5e2170 LV |
1128 | static void gen_raise_exception(int nr) |
1129 | { | |
1130 | TCGv_i32 tmp = tcg_const_i32(nr); | |
1131 | ||
1132 | gen_helper_raise_exception(cpu_env, tmp); | |
1133 | tcg_temp_free_i32(tmp); | |
1134 | } | |
1135 | ||
e6e5906b PB |
1136 | static void gen_exception(DisasContext *s, uint32_t where, int nr) |
1137 | { | |
9fdb533f | 1138 | update_cc_op(s); |
e1f3808e | 1139 | gen_jmp_im(s, where); |
2b5e2170 | 1140 | gen_raise_exception(nr); |
e6e5906b PB |
1141 | } |
1142 | ||
510ff0b7 PB |
1143 | static inline void gen_addr_fault(DisasContext *s) |
1144 | { | |
1145 | gen_exception(s, s->insn_pc, EXCP_ADDRESS); | |
1146 | } | |
1147 | ||
d4d79bb1 BS |
1148 | #define SRC_EA(env, result, opsize, op_sign, addrp) do { \ |
1149 | result = gen_ea(env, s, insn, opsize, NULL_QREG, addrp, \ | |
1150 | op_sign ? EA_LOADS : EA_LOADU); \ | |
1151 | if (IS_NULL_QREG(result)) { \ | |
1152 | gen_addr_fault(s); \ | |
1153 | return; \ | |
1154 | } \ | |
510ff0b7 PB |
1155 | } while (0) |
1156 | ||
d4d79bb1 BS |
1157 | #define DEST_EA(env, insn, opsize, val, addrp) do { \ |
1158 | TCGv ea_result = gen_ea(env, s, insn, opsize, val, addrp, EA_STORE); \ | |
1159 | if (IS_NULL_QREG(ea_result)) { \ | |
1160 | gen_addr_fault(s); \ | |
1161 | return; \ | |
1162 | } \ | |
510ff0b7 PB |
1163 | } while (0) |
1164 | ||
90aa39a1 SF |
1165 | static inline bool use_goto_tb(DisasContext *s, uint32_t dest) |
1166 | { | |
1167 | #ifndef CONFIG_USER_ONLY | |
1168 | return (s->tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) || | |
1169 | (s->insn_pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK); | |
1170 | #else | |
1171 | return true; | |
1172 | #endif | |
1173 | } | |
1174 | ||
e6e5906b PB |
1175 | /* Generate a jump to an immediate address. */ |
1176 | static void gen_jmp_tb(DisasContext *s, int n, uint32_t dest) | |
1177 | { | |
551bd27f | 1178 | if (unlikely(s->singlestep_enabled)) { |
e6e5906b | 1179 | gen_exception(s, dest, EXCP_DEBUG); |
90aa39a1 | 1180 | } else if (use_goto_tb(s, dest)) { |
57fec1fe | 1181 | tcg_gen_goto_tb(n); |
e1f3808e | 1182 | tcg_gen_movi_i32(QREG_PC, dest); |
90aa39a1 | 1183 | tcg_gen_exit_tb((uintptr_t)s->tb + n); |
e6e5906b | 1184 | } else { |
e1f3808e | 1185 | gen_jmp_im(s, dest); |
57fec1fe | 1186 | tcg_gen_exit_tb(0); |
e6e5906b PB |
1187 | } |
1188 | s->is_jmp = DISAS_TB_JUMP; | |
1189 | } | |
1190 | ||
d5a3cf33 LV |
1191 | DISAS_INSN(scc) |
1192 | { | |
1193 | DisasCompare c; | |
1194 | int cond; | |
1195 | TCGv tmp; | |
1196 | ||
1197 | cond = (insn >> 8) & 0xf; | |
1198 | gen_cc_cond(&c, s, cond); | |
1199 | ||
1200 | tmp = tcg_temp_new(); | |
1201 | tcg_gen_setcond_i32(c.tcond, tmp, c.v1, c.v2); | |
1202 | free_cond(&c); | |
1203 | ||
1204 | tcg_gen_neg_i32(tmp, tmp); | |
1205 | DEST_EA(env, insn, OS_BYTE, tmp, NULL); | |
1206 | tcg_temp_free(tmp); | |
1207 | } | |
1208 | ||
beff27ab LV |
1209 | DISAS_INSN(dbcc) |
1210 | { | |
1211 | TCGLabel *l1; | |
1212 | TCGv reg; | |
1213 | TCGv tmp; | |
1214 | int16_t offset; | |
1215 | uint32_t base; | |
1216 | ||
1217 | reg = DREG(insn, 0); | |
1218 | base = s->pc; | |
1219 | offset = (int16_t)read_im16(env, s); | |
1220 | l1 = gen_new_label(); | |
1221 | gen_jmpcc(s, (insn >> 8) & 0xf, l1); | |
1222 | ||
1223 | tmp = tcg_temp_new(); | |
1224 | tcg_gen_ext16s_i32(tmp, reg); | |
1225 | tcg_gen_addi_i32(tmp, tmp, -1); | |
1226 | gen_partset_reg(OS_WORD, reg, tmp); | |
1227 | tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, -1, l1); | |
1228 | gen_jmp_tb(s, 1, base + offset); | |
1229 | gen_set_label(l1); | |
1230 | gen_jmp_tb(s, 0, s->pc); | |
1231 | } | |
1232 | ||
e6e5906b PB |
1233 | DISAS_INSN(undef_mac) |
1234 | { | |
1235 | gen_exception(s, s->pc - 2, EXCP_LINEA); | |
1236 | } | |
1237 | ||
1238 | DISAS_INSN(undef_fpu) | |
1239 | { | |
1240 | gen_exception(s, s->pc - 2, EXCP_LINEF); | |
1241 | } | |
1242 | ||
1243 | DISAS_INSN(undef) | |
1244 | { | |
72d2e4b6 RH |
1245 | /* ??? This is both instructions that are as yet unimplemented |
1246 | for the 680x0 series, as well as those that are implemented | |
1247 | but actually illegal for CPU32 or pre-68020. */ | |
1248 | qemu_log_mask(LOG_UNIMP, "Illegal instruction: %04x @ %08x", | |
1249 | insn, s->pc - 2); | |
e6e5906b | 1250 | gen_exception(s, s->pc - 2, EXCP_UNSUPPORTED); |
e6e5906b PB |
1251 | } |
1252 | ||
1253 | DISAS_INSN(mulw) | |
1254 | { | |
e1f3808e PB |
1255 | TCGv reg; |
1256 | TCGv tmp; | |
1257 | TCGv src; | |
e6e5906b PB |
1258 | int sign; |
1259 | ||
1260 | sign = (insn & 0x100) != 0; | |
1261 | reg = DREG(insn, 9); | |
a7812ae4 | 1262 | tmp = tcg_temp_new(); |
e6e5906b | 1263 | if (sign) |
e1f3808e | 1264 | tcg_gen_ext16s_i32(tmp, reg); |
e6e5906b | 1265 | else |
e1f3808e | 1266 | tcg_gen_ext16u_i32(tmp, reg); |
d4d79bb1 | 1267 | SRC_EA(env, src, OS_WORD, sign, NULL); |
e1f3808e PB |
1268 | tcg_gen_mul_i32(tmp, tmp, src); |
1269 | tcg_gen_mov_i32(reg, tmp); | |
4a18cd44 | 1270 | gen_logic_cc(s, tmp, OS_LONG); |
2b5e2170 | 1271 | tcg_temp_free(tmp); |
e6e5906b PB |
1272 | } |
1273 | ||
1274 | DISAS_INSN(divw) | |
1275 | { | |
e6e5906b | 1276 | int sign; |
0ccb9c1d LV |
1277 | TCGv src; |
1278 | TCGv destr; | |
1279 | ||
1280 | /* divX.w <EA>,Dn 32/16 -> 16r:16q */ | |
e6e5906b PB |
1281 | |
1282 | sign = (insn & 0x100) != 0; | |
0ccb9c1d LV |
1283 | |
1284 | /* dest.l / src.w */ | |
1285 | ||
d4d79bb1 | 1286 | SRC_EA(env, src, OS_WORD, sign, NULL); |
0ccb9c1d | 1287 | destr = tcg_const_i32(REG(insn, 9)); |
e6e5906b | 1288 | if (sign) { |
0ccb9c1d | 1289 | gen_helper_divsw(cpu_env, destr, src); |
e6e5906b | 1290 | } else { |
0ccb9c1d | 1291 | gen_helper_divuw(cpu_env, destr, src); |
e6e5906b | 1292 | } |
0ccb9c1d | 1293 | tcg_temp_free(destr); |
620c6cf6 | 1294 | |
9fdb533f | 1295 | set_cc_op(s, CC_OP_FLAGS); |
e6e5906b PB |
1296 | } |
1297 | ||
1298 | DISAS_INSN(divl) | |
1299 | { | |
0ccb9c1d LV |
1300 | TCGv num, reg, den; |
1301 | int sign; | |
e6e5906b PB |
1302 | uint16_t ext; |
1303 | ||
28b68cd7 | 1304 | ext = read_im16(env, s); |
0ccb9c1d LV |
1305 | |
1306 | sign = (ext & 0x0800) != 0; | |
1307 | ||
1308 | if (ext & 0x400) { | |
1309 | if (!m68k_feature(s->env, M68K_FEATURE_QUAD_MULDIV)) { | |
1310 | gen_exception(s, s->insn_pc, EXCP_ILLEGAL); | |
1311 | return; | |
1312 | } | |
1313 | ||
1314 | /* divX.l <EA>, Dr:Dq 64/32 -> 32r:32q */ | |
1315 | ||
1316 | SRC_EA(env, den, OS_LONG, 0, NULL); | |
1317 | num = tcg_const_i32(REG(ext, 12)); | |
1318 | reg = tcg_const_i32(REG(ext, 0)); | |
1319 | if (sign) { | |
1320 | gen_helper_divsll(cpu_env, num, reg, den); | |
1321 | } else { | |
1322 | gen_helper_divull(cpu_env, num, reg, den); | |
1323 | } | |
1324 | tcg_temp_free(reg); | |
1325 | tcg_temp_free(num); | |
1326 | set_cc_op(s, CC_OP_FLAGS); | |
e6e5906b PB |
1327 | return; |
1328 | } | |
0ccb9c1d LV |
1329 | |
1330 | /* divX.l <EA>, Dq 32/32 -> 32q */ | |
1331 | /* divXl.l <EA>, Dr:Dq 32/32 -> 32r:32q */ | |
1332 | ||
d4d79bb1 | 1333 | SRC_EA(env, den, OS_LONG, 0, NULL); |
0ccb9c1d LV |
1334 | num = tcg_const_i32(REG(ext, 12)); |
1335 | reg = tcg_const_i32(REG(ext, 0)); | |
1336 | if (sign) { | |
1337 | gen_helper_divsl(cpu_env, num, reg, den); | |
e6e5906b | 1338 | } else { |
0ccb9c1d | 1339 | gen_helper_divul(cpu_env, num, reg, den); |
e6e5906b | 1340 | } |
0ccb9c1d LV |
1341 | tcg_temp_free(reg); |
1342 | tcg_temp_free(num); | |
1343 | ||
9fdb533f | 1344 | set_cc_op(s, CC_OP_FLAGS); |
e6e5906b PB |
1345 | } |
1346 | ||
fb5543d8 LV |
1347 | static void bcd_add(TCGv dest, TCGv src) |
1348 | { | |
1349 | TCGv t0, t1; | |
1350 | ||
1351 | /* dest10 = dest10 + src10 + X | |
1352 | * | |
1353 | * t1 = src | |
1354 | * t2 = t1 + 0x066 | |
1355 | * t3 = t2 + dest + X | |
1356 | * t4 = t2 ^ dest | |
1357 | * t5 = t3 ^ t4 | |
1358 | * t6 = ~t5 & 0x110 | |
1359 | * t7 = (t6 >> 2) | (t6 >> 3) | |
1360 | * return t3 - t7 | |
1361 | */ | |
1362 | ||
1363 | /* t1 = (src + 0x066) + dest + X | |
1364 | * = result with some possible exceding 0x6 | |
1365 | */ | |
1366 | ||
1367 | t0 = tcg_const_i32(0x066); | |
1368 | tcg_gen_add_i32(t0, t0, src); | |
1369 | ||
1370 | t1 = tcg_temp_new(); | |
1371 | tcg_gen_add_i32(t1, t0, dest); | |
1372 | tcg_gen_add_i32(t1, t1, QREG_CC_X); | |
1373 | ||
1374 | /* we will remove exceding 0x6 where there is no carry */ | |
1375 | ||
1376 | /* t0 = (src + 0x0066) ^ dest | |
1377 | * = t1 without carries | |
1378 | */ | |
1379 | ||
1380 | tcg_gen_xor_i32(t0, t0, dest); | |
1381 | ||
1382 | /* extract the carries | |
1383 | * t0 = t0 ^ t1 | |
1384 | * = only the carries | |
1385 | */ | |
1386 | ||
1387 | tcg_gen_xor_i32(t0, t0, t1); | |
1388 | ||
1389 | /* generate 0x1 where there is no carry | |
1390 | * and for each 0x10, generate a 0x6 | |
1391 | */ | |
1392 | ||
1393 | tcg_gen_shri_i32(t0, t0, 3); | |
1394 | tcg_gen_not_i32(t0, t0); | |
1395 | tcg_gen_andi_i32(t0, t0, 0x22); | |
1396 | tcg_gen_add_i32(dest, t0, t0); | |
1397 | tcg_gen_add_i32(dest, dest, t0); | |
1398 | tcg_temp_free(t0); | |
1399 | ||
1400 | /* remove the exceding 0x6 | |
1401 | * for digits that have not generated a carry | |
1402 | */ | |
1403 | ||
1404 | tcg_gen_sub_i32(dest, t1, dest); | |
1405 | tcg_temp_free(t1); | |
1406 | } | |
1407 | ||
1408 | static void bcd_sub(TCGv dest, TCGv src) | |
1409 | { | |
1410 | TCGv t0, t1, t2; | |
1411 | ||
1412 | /* dest10 = dest10 - src10 - X | |
1413 | * = bcd_add(dest + 1 - X, 0x199 - src) | |
1414 | */ | |
1415 | ||
1416 | /* t0 = 0x066 + (0x199 - src) */ | |
1417 | ||
1418 | t0 = tcg_temp_new(); | |
1419 | tcg_gen_subfi_i32(t0, 0x1ff, src); | |
1420 | ||
1421 | /* t1 = t0 + dest + 1 - X*/ | |
1422 | ||
1423 | t1 = tcg_temp_new(); | |
1424 | tcg_gen_add_i32(t1, t0, dest); | |
1425 | tcg_gen_addi_i32(t1, t1, 1); | |
1426 | tcg_gen_sub_i32(t1, t1, QREG_CC_X); | |
1427 | ||
1428 | /* t2 = t0 ^ dest */ | |
1429 | ||
1430 | t2 = tcg_temp_new(); | |
1431 | tcg_gen_xor_i32(t2, t0, dest); | |
1432 | ||
1433 | /* t0 = t1 ^ t2 */ | |
1434 | ||
1435 | tcg_gen_xor_i32(t0, t1, t2); | |
1436 | ||
1437 | /* t2 = ~t0 & 0x110 | |
1438 | * t0 = (t2 >> 2) | (t2 >> 3) | |
1439 | * | |
1440 | * to fit on 8bit operands, changed in: | |
1441 | * | |
1442 | * t2 = ~(t0 >> 3) & 0x22 | |
1443 | * t0 = t2 + t2 | |
1444 | * t0 = t0 + t2 | |
1445 | */ | |
1446 | ||
1447 | tcg_gen_shri_i32(t2, t0, 3); | |
1448 | tcg_gen_not_i32(t2, t2); | |
1449 | tcg_gen_andi_i32(t2, t2, 0x22); | |
1450 | tcg_gen_add_i32(t0, t2, t2); | |
1451 | tcg_gen_add_i32(t0, t0, t2); | |
1452 | tcg_temp_free(t2); | |
1453 | ||
1454 | /* return t1 - t0 */ | |
1455 | ||
1456 | tcg_gen_sub_i32(dest, t1, t0); | |
1457 | tcg_temp_free(t0); | |
1458 | tcg_temp_free(t1); | |
1459 | } | |
1460 | ||
1461 | static void bcd_flags(TCGv val) | |
1462 | { | |
1463 | tcg_gen_andi_i32(QREG_CC_C, val, 0x0ff); | |
1464 | tcg_gen_or_i32(QREG_CC_Z, QREG_CC_Z, QREG_CC_C); | |
1465 | ||
1466 | tcg_gen_shri_i32(QREG_CC_C, val, 8); | |
1467 | tcg_gen_andi_i32(QREG_CC_C, QREG_CC_C, 1); | |
1468 | ||
1469 | tcg_gen_mov_i32(QREG_CC_X, QREG_CC_C); | |
1470 | } | |
1471 | ||
1472 | DISAS_INSN(abcd_reg) | |
1473 | { | |
1474 | TCGv src; | |
1475 | TCGv dest; | |
1476 | ||
1477 | gen_flush_flags(s); /* !Z is sticky */ | |
1478 | ||
1479 | src = gen_extend(DREG(insn, 0), OS_BYTE, 0); | |
1480 | dest = gen_extend(DREG(insn, 9), OS_BYTE, 0); | |
1481 | bcd_add(dest, src); | |
1482 | gen_partset_reg(OS_BYTE, DREG(insn, 9), dest); | |
1483 | ||
1484 | bcd_flags(dest); | |
1485 | } | |
1486 | ||
1487 | DISAS_INSN(abcd_mem) | |
1488 | { | |
1489 | TCGv src, dest, addr; | |
1490 | ||
1491 | gen_flush_flags(s); /* !Z is sticky */ | |
1492 | ||
1493 | /* Indirect pre-decrement load (mode 4) */ | |
1494 | ||
1495 | src = gen_ea_mode(env, s, 4, REG(insn, 0), OS_BYTE, | |
1496 | NULL_QREG, NULL, EA_LOADU); | |
1497 | dest = gen_ea_mode(env, s, 4, REG(insn, 9), OS_BYTE, | |
1498 | NULL_QREG, &addr, EA_LOADU); | |
1499 | ||
1500 | bcd_add(dest, src); | |
1501 | ||
1502 | gen_ea_mode(env, s, 4, REG(insn, 9), OS_BYTE, dest, &addr, EA_STORE); | |
1503 | ||
1504 | bcd_flags(dest); | |
1505 | } | |
1506 | ||
1507 | DISAS_INSN(sbcd_reg) | |
1508 | { | |
1509 | TCGv src, dest; | |
1510 | ||
1511 | gen_flush_flags(s); /* !Z is sticky */ | |
1512 | ||
1513 | src = gen_extend(DREG(insn, 0), OS_BYTE, 0); | |
1514 | dest = gen_extend(DREG(insn, 9), OS_BYTE, 0); | |
1515 | ||
1516 | bcd_sub(dest, src); | |
1517 | ||
1518 | gen_partset_reg(OS_BYTE, DREG(insn, 9), dest); | |
1519 | ||
1520 | bcd_flags(dest); | |
1521 | } | |
1522 | ||
1523 | DISAS_INSN(sbcd_mem) | |
1524 | { | |
1525 | TCGv src, dest, addr; | |
1526 | ||
1527 | gen_flush_flags(s); /* !Z is sticky */ | |
1528 | ||
1529 | /* Indirect pre-decrement load (mode 4) */ | |
1530 | ||
1531 | src = gen_ea_mode(env, s, 4, REG(insn, 0), OS_BYTE, | |
1532 | NULL_QREG, NULL, EA_LOADU); | |
1533 | dest = gen_ea_mode(env, s, 4, REG(insn, 9), OS_BYTE, | |
1534 | NULL_QREG, &addr, EA_LOADU); | |
1535 | ||
1536 | bcd_sub(dest, src); | |
1537 | ||
1538 | gen_ea_mode(env, s, 4, REG(insn, 9), OS_BYTE, dest, &addr, EA_STORE); | |
1539 | ||
1540 | bcd_flags(dest); | |
1541 | } | |
1542 | ||
1543 | DISAS_INSN(nbcd) | |
1544 | { | |
1545 | TCGv src, dest; | |
1546 | TCGv addr; | |
1547 | ||
1548 | gen_flush_flags(s); /* !Z is sticky */ | |
1549 | ||
1550 | SRC_EA(env, src, OS_BYTE, 0, &addr); | |
1551 | ||
1552 | dest = tcg_const_i32(0); | |
1553 | bcd_sub(dest, src); | |
1554 | ||
1555 | DEST_EA(env, insn, OS_BYTE, dest, &addr); | |
1556 | ||
1557 | bcd_flags(dest); | |
1558 | ||
1559 | tcg_temp_free(dest); | |
1560 | } | |
1561 | ||
e6e5906b PB |
1562 | DISAS_INSN(addsub) |
1563 | { | |
e1f3808e PB |
1564 | TCGv reg; |
1565 | TCGv dest; | |
1566 | TCGv src; | |
1567 | TCGv tmp; | |
1568 | TCGv addr; | |
e6e5906b | 1569 | int add; |
8a370c6c | 1570 | int opsize; |
e6e5906b PB |
1571 | |
1572 | add = (insn & 0x4000) != 0; | |
8a370c6c LV |
1573 | opsize = insn_opsize(insn); |
1574 | reg = gen_extend(DREG(insn, 9), opsize, 1); | |
a7812ae4 | 1575 | dest = tcg_temp_new(); |
e6e5906b | 1576 | if (insn & 0x100) { |
8a370c6c | 1577 | SRC_EA(env, tmp, opsize, 1, &addr); |
e6e5906b PB |
1578 | src = reg; |
1579 | } else { | |
1580 | tmp = reg; | |
8a370c6c | 1581 | SRC_EA(env, src, opsize, 1, NULL); |
e6e5906b PB |
1582 | } |
1583 | if (add) { | |
e1f3808e | 1584 | tcg_gen_add_i32(dest, tmp, src); |
f9083519 | 1585 | tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, dest, src); |
8a370c6c | 1586 | set_cc_op(s, CC_OP_ADDB + opsize); |
e6e5906b | 1587 | } else { |
f9083519 | 1588 | tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, tmp, src); |
e1f3808e | 1589 | tcg_gen_sub_i32(dest, tmp, src); |
8a370c6c | 1590 | set_cc_op(s, CC_OP_SUBB + opsize); |
e6e5906b | 1591 | } |
8a370c6c | 1592 | gen_update_cc_add(dest, src, opsize); |
e6e5906b | 1593 | if (insn & 0x100) { |
8a370c6c | 1594 | DEST_EA(env, insn, opsize, dest, &addr); |
e6e5906b | 1595 | } else { |
8a370c6c | 1596 | gen_partset_reg(opsize, DREG(insn, 9), dest); |
e6e5906b | 1597 | } |
8a370c6c | 1598 | tcg_temp_free(dest); |
e6e5906b PB |
1599 | } |
1600 | ||
e6e5906b PB |
1601 | /* Reverse the order of the bits in REG. */ |
1602 | DISAS_INSN(bitrev) | |
1603 | { | |
e1f3808e | 1604 | TCGv reg; |
e6e5906b | 1605 | reg = DREG(insn, 0); |
e1f3808e | 1606 | gen_helper_bitrev(reg, reg); |
e6e5906b PB |
1607 | } |
1608 | ||
1609 | DISAS_INSN(bitop_reg) | |
1610 | { | |
1611 | int opsize; | |
1612 | int op; | |
e1f3808e PB |
1613 | TCGv src1; |
1614 | TCGv src2; | |
1615 | TCGv tmp; | |
1616 | TCGv addr; | |
1617 | TCGv dest; | |
e6e5906b PB |
1618 | |
1619 | if ((insn & 0x38) != 0) | |
1620 | opsize = OS_BYTE; | |
1621 | else | |
1622 | opsize = OS_LONG; | |
1623 | op = (insn >> 6) & 3; | |
d4d79bb1 | 1624 | SRC_EA(env, src1, opsize, 0, op ? &addr: NULL); |
e6e5906b | 1625 | |
3c980d2e LV |
1626 | gen_flush_flags(s); |
1627 | src2 = tcg_temp_new(); | |
e6e5906b | 1628 | if (opsize == OS_BYTE) |
3c980d2e | 1629 | tcg_gen_andi_i32(src2, DREG(insn, 9), 7); |
e6e5906b | 1630 | else |
3c980d2e | 1631 | tcg_gen_andi_i32(src2, DREG(insn, 9), 31); |
620c6cf6 | 1632 | |
3c980d2e LV |
1633 | tmp = tcg_const_i32(1); |
1634 | tcg_gen_shl_i32(tmp, tmp, src2); | |
1635 | tcg_temp_free(src2); | |
620c6cf6 | 1636 | |
3c980d2e | 1637 | tcg_gen_and_i32(QREG_CC_Z, src1, tmp); |
620c6cf6 | 1638 | |
3c980d2e | 1639 | dest = tcg_temp_new(); |
e6e5906b PB |
1640 | switch (op) { |
1641 | case 1: /* bchg */ | |
3c980d2e | 1642 | tcg_gen_xor_i32(dest, src1, tmp); |
e6e5906b PB |
1643 | break; |
1644 | case 2: /* bclr */ | |
3c980d2e | 1645 | tcg_gen_andc_i32(dest, src1, tmp); |
e6e5906b PB |
1646 | break; |
1647 | case 3: /* bset */ | |
3c980d2e | 1648 | tcg_gen_or_i32(dest, src1, tmp); |
e6e5906b PB |
1649 | break; |
1650 | default: /* btst */ | |
1651 | break; | |
1652 | } | |
3c980d2e | 1653 | tcg_temp_free(tmp); |
620c6cf6 | 1654 | if (op) { |
d4d79bb1 | 1655 | DEST_EA(env, insn, opsize, dest, &addr); |
620c6cf6 RH |
1656 | } |
1657 | tcg_temp_free(dest); | |
e6e5906b PB |
1658 | } |
1659 | ||
1660 | DISAS_INSN(sats) | |
1661 | { | |
e1f3808e | 1662 | TCGv reg; |
e6e5906b | 1663 | reg = DREG(insn, 0); |
e6e5906b | 1664 | gen_flush_flags(s); |
620c6cf6 | 1665 | gen_helper_sats(reg, reg, QREG_CC_V); |
5dbb6784 | 1666 | gen_logic_cc(s, reg, OS_LONG); |
e6e5906b PB |
1667 | } |
1668 | ||
e1f3808e | 1669 | static void gen_push(DisasContext *s, TCGv val) |
e6e5906b | 1670 | { |
e1f3808e | 1671 | TCGv tmp; |
e6e5906b | 1672 | |
a7812ae4 | 1673 | tmp = tcg_temp_new(); |
e1f3808e | 1674 | tcg_gen_subi_i32(tmp, QREG_SP, 4); |
0633879f | 1675 | gen_store(s, OS_LONG, tmp, val); |
e1f3808e | 1676 | tcg_gen_mov_i32(QREG_SP, tmp); |
2b5e2170 | 1677 | tcg_temp_free(tmp); |
e6e5906b PB |
1678 | } |
1679 | ||
7b542eb9 LV |
1680 | static TCGv mreg(int reg) |
1681 | { | |
1682 | if (reg < 8) { | |
1683 | /* Dx */ | |
1684 | return cpu_dregs[reg]; | |
1685 | } | |
1686 | /* Ax */ | |
1687 | return cpu_aregs[reg & 7]; | |
1688 | } | |
1689 | ||
e6e5906b PB |
1690 | DISAS_INSN(movem) |
1691 | { | |
7b542eb9 LV |
1692 | TCGv addr, incr, tmp, r[16]; |
1693 | int is_load = (insn & 0x0400) != 0; | |
1694 | int opsize = (insn & 0x40) != 0 ? OS_LONG : OS_WORD; | |
1695 | uint16_t mask = read_im16(env, s); | |
1696 | int mode = extract32(insn, 3, 3); | |
1697 | int reg0 = REG(insn, 0); | |
e6e5906b | 1698 | int i; |
e6e5906b | 1699 | |
7b542eb9 LV |
1700 | tmp = cpu_aregs[reg0]; |
1701 | ||
1702 | switch (mode) { | |
1703 | case 0: /* data register direct */ | |
1704 | case 1: /* addr register direct */ | |
1705 | do_addr_fault: | |
510ff0b7 PB |
1706 | gen_addr_fault(s); |
1707 | return; | |
7b542eb9 LV |
1708 | |
1709 | case 2: /* indirect */ | |
1710 | break; | |
1711 | ||
1712 | case 3: /* indirect post-increment */ | |
1713 | if (!is_load) { | |
1714 | /* post-increment is not allowed */ | |
1715 | goto do_addr_fault; | |
1716 | } | |
1717 | break; | |
1718 | ||
1719 | case 4: /* indirect pre-decrement */ | |
1720 | if (is_load) { | |
1721 | /* pre-decrement is not allowed */ | |
1722 | goto do_addr_fault; | |
1723 | } | |
1724 | /* We want a bare copy of the address reg, without any pre-decrement | |
1725 | adjustment, as gen_lea would provide. */ | |
1726 | break; | |
1727 | ||
1728 | default: | |
1729 | tmp = gen_lea_mode(env, s, mode, reg0, opsize); | |
1730 | if (IS_NULL_QREG(tmp)) { | |
1731 | goto do_addr_fault; | |
1732 | } | |
1733 | break; | |
510ff0b7 | 1734 | } |
7b542eb9 | 1735 | |
a7812ae4 | 1736 | addr = tcg_temp_new(); |
e1f3808e | 1737 | tcg_gen_mov_i32(addr, tmp); |
7b542eb9 LV |
1738 | incr = tcg_const_i32(opsize_bytes(opsize)); |
1739 | ||
1740 | if (is_load) { | |
1741 | /* memory to register */ | |
1742 | for (i = 0; i < 16; i++) { | |
1743 | if (mask & (1 << i)) { | |
1744 | r[i] = gen_load(s, opsize, addr, 1); | |
1745 | tcg_gen_add_i32(addr, addr, incr); | |
1746 | } | |
1747 | } | |
1748 | for (i = 0; i < 16; i++) { | |
1749 | if (mask & (1 << i)) { | |
1750 | tcg_gen_mov_i32(mreg(i), r[i]); | |
1751 | tcg_temp_free(r[i]); | |
1752 | } | |
1753 | } | |
1754 | if (mode == 3) { | |
1755 | /* post-increment: movem (An)+,X */ | |
1756 | tcg_gen_mov_i32(cpu_aregs[reg0], addr); | |
1757 | } | |
1758 | } else { | |
1759 | /* register to memory */ | |
1760 | if (mode == 4) { | |
1761 | /* pre-decrement: movem X,-(An) */ | |
1762 | for (i = 15; i >= 0; i--) { | |
1763 | if ((mask << i) & 0x8000) { | |
1764 | tcg_gen_sub_i32(addr, addr, incr); | |
1765 | if (reg0 + 8 == i && | |
1766 | m68k_feature(s->env, M68K_FEATURE_EXT_FULL)) { | |
1767 | /* M68020+: if the addressing register is the | |
1768 | * register moved to memory, the value written | |
1769 | * is the initial value decremented by the size of | |
1770 | * the operation, regardless of how many actual | |
1771 | * stores have been performed until this point. | |
1772 | * M68000/M68010: the value is the initial value. | |
1773 | */ | |
1774 | tmp = tcg_temp_new(); | |
1775 | tcg_gen_sub_i32(tmp, cpu_aregs[reg0], incr); | |
1776 | gen_store(s, opsize, addr, tmp); | |
1777 | tcg_temp_free(tmp); | |
1778 | } else { | |
1779 | gen_store(s, opsize, addr, mreg(i)); | |
1780 | } | |
1781 | } | |
1782 | } | |
1783 | tcg_gen_mov_i32(cpu_aregs[reg0], addr); | |
1784 | } else { | |
1785 | for (i = 0; i < 16; i++) { | |
1786 | if (mask & (1 << i)) { | |
1787 | gen_store(s, opsize, addr, mreg(i)); | |
1788 | tcg_gen_add_i32(addr, addr, incr); | |
1789 | } | |
e6e5906b | 1790 | } |
e6e5906b PB |
1791 | } |
1792 | } | |
7b542eb9 LV |
1793 | |
1794 | tcg_temp_free(incr); | |
1795 | tcg_temp_free(addr); | |
e6e5906b PB |
1796 | } |
1797 | ||
1798 | DISAS_INSN(bitop_im) | |
1799 | { | |
1800 | int opsize; | |
1801 | int op; | |
e1f3808e | 1802 | TCGv src1; |
e6e5906b PB |
1803 | uint32_t mask; |
1804 | int bitnum; | |
e1f3808e PB |
1805 | TCGv tmp; |
1806 | TCGv addr; | |
e6e5906b PB |
1807 | |
1808 | if ((insn & 0x38) != 0) | |
1809 | opsize = OS_BYTE; | |
1810 | else | |
1811 | opsize = OS_LONG; | |
1812 | op = (insn >> 6) & 3; | |
1813 | ||
28b68cd7 | 1814 | bitnum = read_im16(env, s); |
fe53c2be LV |
1815 | if (m68k_feature(s->env, M68K_FEATURE_M68000)) { |
1816 | if (bitnum & 0xfe00) { | |
1817 | disas_undef(env, s, insn); | |
1818 | return; | |
1819 | } | |
1820 | } else { | |
1821 | if (bitnum & 0xff00) { | |
1822 | disas_undef(env, s, insn); | |
1823 | return; | |
1824 | } | |
e6e5906b PB |
1825 | } |
1826 | ||
d4d79bb1 | 1827 | SRC_EA(env, src1, opsize, 0, op ? &addr: NULL); |
e6e5906b | 1828 | |
3c980d2e | 1829 | gen_flush_flags(s); |
e6e5906b PB |
1830 | if (opsize == OS_BYTE) |
1831 | bitnum &= 7; | |
1832 | else | |
1833 | bitnum &= 31; | |
1834 | mask = 1 << bitnum; | |
1835 | ||
3c980d2e | 1836 | tcg_gen_andi_i32(QREG_CC_Z, src1, mask); |
620c6cf6 | 1837 | |
e1f3808e | 1838 | if (op) { |
620c6cf6 | 1839 | tmp = tcg_temp_new(); |
e1f3808e PB |
1840 | switch (op) { |
1841 | case 1: /* bchg */ | |
1842 | tcg_gen_xori_i32(tmp, src1, mask); | |
1843 | break; | |
1844 | case 2: /* bclr */ | |
1845 | tcg_gen_andi_i32(tmp, src1, ~mask); | |
1846 | break; | |
1847 | case 3: /* bset */ | |
1848 | tcg_gen_ori_i32(tmp, src1, mask); | |
1849 | break; | |
1850 | default: /* btst */ | |
1851 | break; | |
1852 | } | |
d4d79bb1 | 1853 | DEST_EA(env, insn, opsize, tmp, &addr); |
620c6cf6 | 1854 | tcg_temp_free(tmp); |
e6e5906b | 1855 | } |
e6e5906b | 1856 | } |
620c6cf6 | 1857 | |
e6e5906b PB |
1858 | DISAS_INSN(arith_im) |
1859 | { | |
1860 | int op; | |
92c62548 | 1861 | TCGv im; |
e1f3808e PB |
1862 | TCGv src1; |
1863 | TCGv dest; | |
1864 | TCGv addr; | |
92c62548 | 1865 | int opsize; |
e6e5906b PB |
1866 | |
1867 | op = (insn >> 9) & 7; | |
92c62548 LV |
1868 | opsize = insn_opsize(insn); |
1869 | switch (opsize) { | |
1870 | case OS_BYTE: | |
1871 | im = tcg_const_i32((int8_t)read_im8(env, s)); | |
1872 | break; | |
1873 | case OS_WORD: | |
1874 | im = tcg_const_i32((int16_t)read_im16(env, s)); | |
1875 | break; | |
1876 | case OS_LONG: | |
1877 | im = tcg_const_i32(read_im32(env, s)); | |
1878 | break; | |
1879 | default: | |
1880 | abort(); | |
1881 | } | |
1882 | SRC_EA(env, src1, opsize, 1, (op == 6) ? NULL : &addr); | |
a7812ae4 | 1883 | dest = tcg_temp_new(); |
e6e5906b PB |
1884 | switch (op) { |
1885 | case 0: /* ori */ | |
92c62548 LV |
1886 | tcg_gen_or_i32(dest, src1, im); |
1887 | gen_logic_cc(s, dest, opsize); | |
e6e5906b PB |
1888 | break; |
1889 | case 1: /* andi */ | |
92c62548 LV |
1890 | tcg_gen_and_i32(dest, src1, im); |
1891 | gen_logic_cc(s, dest, opsize); | |
e6e5906b PB |
1892 | break; |
1893 | case 2: /* subi */ | |
92c62548 LV |
1894 | tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, src1, im); |
1895 | tcg_gen_sub_i32(dest, src1, im); | |
1896 | gen_update_cc_add(dest, im, opsize); | |
1897 | set_cc_op(s, CC_OP_SUBB + opsize); | |
e6e5906b PB |
1898 | break; |
1899 | case 3: /* addi */ | |
92c62548 LV |
1900 | tcg_gen_add_i32(dest, src1, im); |
1901 | gen_update_cc_add(dest, im, opsize); | |
1902 | tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, dest, im); | |
1903 | set_cc_op(s, CC_OP_ADDB + opsize); | |
e6e5906b PB |
1904 | break; |
1905 | case 5: /* eori */ | |
92c62548 LV |
1906 | tcg_gen_xor_i32(dest, src1, im); |
1907 | gen_logic_cc(s, dest, opsize); | |
e6e5906b PB |
1908 | break; |
1909 | case 6: /* cmpi */ | |
92c62548 | 1910 | gen_update_cc_cmp(s, src1, im, opsize); |
e6e5906b PB |
1911 | break; |
1912 | default: | |
1913 | abort(); | |
1914 | } | |
92c62548 | 1915 | tcg_temp_free(im); |
e6e5906b | 1916 | if (op != 6) { |
92c62548 | 1917 | DEST_EA(env, insn, opsize, dest, &addr); |
e6e5906b | 1918 | } |
92c62548 | 1919 | tcg_temp_free(dest); |
e6e5906b PB |
1920 | } |
1921 | ||
14f94406 LV |
1922 | DISAS_INSN(cas) |
1923 | { | |
1924 | int opsize; | |
1925 | TCGv addr; | |
1926 | uint16_t ext; | |
1927 | TCGv load; | |
1928 | TCGv cmp; | |
1929 | TCGMemOp opc; | |
1930 | ||
1931 | switch ((insn >> 9) & 3) { | |
1932 | case 1: | |
1933 | opsize = OS_BYTE; | |
1934 | opc = MO_SB; | |
1935 | break; | |
1936 | case 2: | |
1937 | opsize = OS_WORD; | |
1938 | opc = MO_TESW; | |
1939 | break; | |
1940 | case 3: | |
1941 | opsize = OS_LONG; | |
1942 | opc = MO_TESL; | |
1943 | break; | |
1944 | default: | |
1945 | g_assert_not_reached(); | |
1946 | } | |
14f94406 LV |
1947 | |
1948 | ext = read_im16(env, s); | |
1949 | ||
1950 | /* cas Dc,Du,<EA> */ | |
1951 | ||
1952 | addr = gen_lea(env, s, insn, opsize); | |
1953 | if (IS_NULL_QREG(addr)) { | |
1954 | gen_addr_fault(s); | |
1955 | return; | |
1956 | } | |
1957 | ||
1958 | cmp = gen_extend(DREG(ext, 0), opsize, 1); | |
1959 | ||
1960 | /* if <EA> == Dc then | |
1961 | * <EA> = Du | |
1962 | * Dc = <EA> (because <EA> == Dc) | |
1963 | * else | |
1964 | * Dc = <EA> | |
1965 | */ | |
1966 | ||
1967 | load = tcg_temp_new(); | |
1968 | tcg_gen_atomic_cmpxchg_i32(load, addr, cmp, DREG(ext, 6), | |
1969 | IS_USER(s), opc); | |
1970 | /* update flags before setting cmp to load */ | |
1971 | gen_update_cc_cmp(s, load, cmp, opsize); | |
1972 | gen_partset_reg(opsize, DREG(ext, 0), load); | |
1973 | ||
1974 | tcg_temp_free(load); | |
308feb93 LV |
1975 | |
1976 | switch (extract32(insn, 3, 3)) { | |
1977 | case 3: /* Indirect postincrement. */ | |
1978 | tcg_gen_addi_i32(AREG(insn, 0), addr, opsize_bytes(opsize)); | |
1979 | break; | |
1980 | case 4: /* Indirect predecrememnt. */ | |
1981 | tcg_gen_mov_i32(AREG(insn, 0), addr); | |
1982 | break; | |
1983 | } | |
14f94406 LV |
1984 | } |
1985 | ||
1986 | DISAS_INSN(cas2w) | |
1987 | { | |
1988 | uint16_t ext1, ext2; | |
1989 | TCGv addr1, addr2; | |
1990 | TCGv regs; | |
1991 | ||
1992 | /* cas2 Dc1:Dc2,Du1:Du2,(Rn1):(Rn2) */ | |
1993 | ||
1994 | ext1 = read_im16(env, s); | |
1995 | ||
1996 | if (ext1 & 0x8000) { | |
1997 | /* Address Register */ | |
1998 | addr1 = AREG(ext1, 12); | |
1999 | } else { | |
2000 | /* Data Register */ | |
2001 | addr1 = DREG(ext1, 12); | |
2002 | } | |
2003 | ||
2004 | ext2 = read_im16(env, s); | |
2005 | if (ext2 & 0x8000) { | |
2006 | /* Address Register */ | |
2007 | addr2 = AREG(ext2, 12); | |
2008 | } else { | |
2009 | /* Data Register */ | |
2010 | addr2 = DREG(ext2, 12); | |
2011 | } | |
2012 | ||
2013 | /* if (R1) == Dc1 && (R2) == Dc2 then | |
2014 | * (R1) = Du1 | |
2015 | * (R2) = Du2 | |
2016 | * else | |
2017 | * Dc1 = (R1) | |
2018 | * Dc2 = (R2) | |
2019 | */ | |
2020 | ||
2021 | regs = tcg_const_i32(REG(ext2, 6) | | |
2022 | (REG(ext1, 6) << 3) | | |
2023 | (REG(ext2, 0) << 6) | | |
2024 | (REG(ext1, 0) << 9)); | |
2025 | gen_helper_cas2w(cpu_env, regs, addr1, addr2); | |
2026 | tcg_temp_free(regs); | |
2027 | ||
2028 | /* Note that cas2w also assigned to env->cc_op. */ | |
2029 | s->cc_op = CC_OP_CMPW; | |
2030 | s->cc_op_synced = 1; | |
2031 | } | |
2032 | ||
2033 | DISAS_INSN(cas2l) | |
2034 | { | |
2035 | uint16_t ext1, ext2; | |
2036 | TCGv addr1, addr2, regs; | |
2037 | ||
2038 | /* cas2 Dc1:Dc2,Du1:Du2,(Rn1):(Rn2) */ | |
2039 | ||
2040 | ext1 = read_im16(env, s); | |
2041 | ||
2042 | if (ext1 & 0x8000) { | |
2043 | /* Address Register */ | |
2044 | addr1 = AREG(ext1, 12); | |
2045 | } else { | |
2046 | /* Data Register */ | |
2047 | addr1 = DREG(ext1, 12); | |
2048 | } | |
2049 | ||
2050 | ext2 = read_im16(env, s); | |
2051 | if (ext2 & 0x8000) { | |
2052 | /* Address Register */ | |
2053 | addr2 = AREG(ext2, 12); | |
2054 | } else { | |
2055 | /* Data Register */ | |
2056 | addr2 = DREG(ext2, 12); | |
2057 | } | |
2058 | ||
2059 | /* if (R1) == Dc1 && (R2) == Dc2 then | |
2060 | * (R1) = Du1 | |
2061 | * (R2) = Du2 | |
2062 | * else | |
2063 | * Dc1 = (R1) | |
2064 | * Dc2 = (R2) | |
2065 | */ | |
2066 | ||
2067 | regs = tcg_const_i32(REG(ext2, 6) | | |
2068 | (REG(ext1, 6) << 3) | | |
2069 | (REG(ext2, 0) << 6) | | |
2070 | (REG(ext1, 0) << 9)); | |
2071 | gen_helper_cas2l(cpu_env, regs, addr1, addr2); | |
2072 | tcg_temp_free(regs); | |
2073 | ||
2074 | /* Note that cas2l also assigned to env->cc_op. */ | |
2075 | s->cc_op = CC_OP_CMPL; | |
2076 | s->cc_op_synced = 1; | |
2077 | } | |
2078 | ||
e6e5906b PB |
2079 | DISAS_INSN(byterev) |
2080 | { | |
e1f3808e | 2081 | TCGv reg; |
e6e5906b PB |
2082 | |
2083 | reg = DREG(insn, 0); | |
66896cb8 | 2084 | tcg_gen_bswap32_i32(reg, reg); |
e6e5906b PB |
2085 | } |
2086 | ||
2087 | DISAS_INSN(move) | |
2088 | { | |
e1f3808e PB |
2089 | TCGv src; |
2090 | TCGv dest; | |
e6e5906b PB |
2091 | int op; |
2092 | int opsize; | |
2093 | ||
2094 | switch (insn >> 12) { | |
2095 | case 1: /* move.b */ | |
2096 | opsize = OS_BYTE; | |
2097 | break; | |
2098 | case 2: /* move.l */ | |
2099 | opsize = OS_LONG; | |
2100 | break; | |
2101 | case 3: /* move.w */ | |
2102 | opsize = OS_WORD; | |
2103 | break; | |
2104 | default: | |
2105 | abort(); | |
2106 | } | |
d4d79bb1 | 2107 | SRC_EA(env, src, opsize, 1, NULL); |
e6e5906b PB |
2108 | op = (insn >> 6) & 7; |
2109 | if (op == 1) { | |
2110 | /* movea */ | |
2111 | /* The value will already have been sign extended. */ | |
2112 | dest = AREG(insn, 9); | |
e1f3808e | 2113 | tcg_gen_mov_i32(dest, src); |
e6e5906b PB |
2114 | } else { |
2115 | /* normal move */ | |
2116 | uint16_t dest_ea; | |
2117 | dest_ea = ((insn >> 9) & 7) | (op << 3); | |
d4d79bb1 | 2118 | DEST_EA(env, dest_ea, opsize, src, NULL); |
e6e5906b | 2119 | /* This will be correct because loads sign extend. */ |
5dbb6784 | 2120 | gen_logic_cc(s, src, opsize); |
e6e5906b PB |
2121 | } |
2122 | } | |
2123 | ||
2124 | DISAS_INSN(negx) | |
2125 | { | |
a665a820 RH |
2126 | TCGv z; |
2127 | TCGv src; | |
2128 | TCGv addr; | |
2129 | int opsize; | |
e6e5906b | 2130 | |
a665a820 RH |
2131 | opsize = insn_opsize(insn); |
2132 | SRC_EA(env, src, opsize, 1, &addr); | |
2133 | ||
2134 | gen_flush_flags(s); /* compute old Z */ | |
2135 | ||
2136 | /* Perform substract with borrow. | |
2137 | * (X, N) = -(src + X); | |
2138 | */ | |
2139 | ||
2140 | z = tcg_const_i32(0); | |
2141 | tcg_gen_add2_i32(QREG_CC_N, QREG_CC_X, src, z, QREG_CC_X, z); | |
2142 | tcg_gen_sub2_i32(QREG_CC_N, QREG_CC_X, z, z, QREG_CC_N, QREG_CC_X); | |
2143 | tcg_temp_free(z); | |
2144 | gen_ext(QREG_CC_N, QREG_CC_N, opsize, 1); | |
2145 | ||
2146 | tcg_gen_andi_i32(QREG_CC_X, QREG_CC_X, 1); | |
2147 | ||
2148 | /* Compute signed-overflow for negation. The normal formula for | |
2149 | * subtraction is (res ^ src) & (src ^ dest), but with dest==0 | |
2150 | * this simplies to res & src. | |
2151 | */ | |
2152 | ||
2153 | tcg_gen_and_i32(QREG_CC_V, QREG_CC_N, src); | |
2154 | ||
2155 | /* Copy the rest of the results into place. */ | |
2156 | tcg_gen_or_i32(QREG_CC_Z, QREG_CC_Z, QREG_CC_N); /* !Z is sticky */ | |
2157 | tcg_gen_mov_i32(QREG_CC_C, QREG_CC_X); | |
2158 | ||
2159 | set_cc_op(s, CC_OP_FLAGS); | |
2160 | ||
2161 | /* result is in QREG_CC_N */ | |
2162 | ||
2163 | DEST_EA(env, insn, opsize, QREG_CC_N, &addr); | |
e6e5906b PB |
2164 | } |
2165 | ||
2166 | DISAS_INSN(lea) | |
2167 | { | |
e1f3808e PB |
2168 | TCGv reg; |
2169 | TCGv tmp; | |
e6e5906b PB |
2170 | |
2171 | reg = AREG(insn, 9); | |
d4d79bb1 | 2172 | tmp = gen_lea(env, s, insn, OS_LONG); |
e1f3808e | 2173 | if (IS_NULL_QREG(tmp)) { |
510ff0b7 PB |
2174 | gen_addr_fault(s); |
2175 | return; | |
2176 | } | |
e1f3808e | 2177 | tcg_gen_mov_i32(reg, tmp); |
e6e5906b PB |
2178 | } |
2179 | ||
2180 | DISAS_INSN(clr) | |
2181 | { | |
2182 | int opsize; | |
2b5e2170 LV |
2183 | TCGv zero; |
2184 | ||
2185 | zero = tcg_const_i32(0); | |
e6e5906b | 2186 | |
7ef25cdd | 2187 | opsize = insn_opsize(insn); |
2b5e2170 LV |
2188 | DEST_EA(env, insn, opsize, zero, NULL); |
2189 | gen_logic_cc(s, zero, opsize); | |
2190 | tcg_temp_free(zero); | |
e6e5906b PB |
2191 | } |
2192 | ||
e1f3808e | 2193 | static TCGv gen_get_ccr(DisasContext *s) |
e6e5906b | 2194 | { |
e1f3808e | 2195 | TCGv dest; |
e6e5906b PB |
2196 | |
2197 | gen_flush_flags(s); | |
620c6cf6 | 2198 | update_cc_op(s); |
a7812ae4 | 2199 | dest = tcg_temp_new(); |
620c6cf6 | 2200 | gen_helper_get_ccr(dest, cpu_env); |
0633879f PB |
2201 | return dest; |
2202 | } | |
2203 | ||
2204 | DISAS_INSN(move_from_ccr) | |
2205 | { | |
e1f3808e | 2206 | TCGv ccr; |
0633879f PB |
2207 | |
2208 | ccr = gen_get_ccr(s); | |
7c0eb318 | 2209 | DEST_EA(env, insn, OS_WORD, ccr, NULL); |
e6e5906b PB |
2210 | } |
2211 | ||
2212 | DISAS_INSN(neg) | |
2213 | { | |
e1f3808e | 2214 | TCGv src1; |
227de713 LV |
2215 | TCGv dest; |
2216 | TCGv addr; | |
2217 | int opsize; | |
e6e5906b | 2218 | |
227de713 LV |
2219 | opsize = insn_opsize(insn); |
2220 | SRC_EA(env, src1, opsize, 1, &addr); | |
2221 | dest = tcg_temp_new(); | |
2222 | tcg_gen_neg_i32(dest, src1); | |
2223 | set_cc_op(s, CC_OP_SUBB + opsize); | |
2224 | gen_update_cc_add(dest, src1, opsize); | |
2225 | tcg_gen_setcondi_i32(TCG_COND_NE, QREG_CC_X, dest, 0); | |
2226 | DEST_EA(env, insn, opsize, dest, &addr); | |
2227 | tcg_temp_free(dest); | |
e6e5906b PB |
2228 | } |
2229 | ||
0633879f PB |
2230 | static void gen_set_sr_im(DisasContext *s, uint16_t val, int ccr_only) |
2231 | { | |
620c6cf6 RH |
2232 | if (ccr_only) { |
2233 | tcg_gen_movi_i32(QREG_CC_C, val & CCF_C ? 1 : 0); | |
2234 | tcg_gen_movi_i32(QREG_CC_V, val & CCF_V ? -1 : 0); | |
2235 | tcg_gen_movi_i32(QREG_CC_Z, val & CCF_Z ? 0 : 1); | |
2236 | tcg_gen_movi_i32(QREG_CC_N, val & CCF_N ? -1 : 0); | |
2237 | tcg_gen_movi_i32(QREG_CC_X, val & CCF_X ? 1 : 0); | |
2238 | } else { | |
2239 | gen_helper_set_sr(cpu_env, tcg_const_i32(val)); | |
0633879f | 2240 | } |
9fdb533f | 2241 | set_cc_op(s, CC_OP_FLAGS); |
0633879f PB |
2242 | } |
2243 | ||
620c6cf6 RH |
2244 | static void gen_set_sr(CPUM68KState *env, DisasContext *s, uint16_t insn, |
2245 | int ccr_only) | |
e6e5906b | 2246 | { |
620c6cf6 RH |
2247 | if ((insn & 0x38) == 0) { |
2248 | if (ccr_only) { | |
2249 | gen_helper_set_ccr(cpu_env, DREG(insn, 0)); | |
2250 | } else { | |
2251 | gen_helper_set_sr(cpu_env, DREG(insn, 0)); | |
2252 | } | |
2253 | set_cc_op(s, CC_OP_FLAGS); | |
2254 | } else if ((insn & 0x3f) == 0x3c) { | |
2255 | uint16_t val; | |
2256 | val = read_im16(env, s); | |
2257 | gen_set_sr_im(s, val, ccr_only); | |
2258 | } else { | |
2259 | disas_undef(env, s, insn); | |
7c0eb318 LV |
2260 | } |
2261 | } | |
e6e5906b | 2262 | |
7c0eb318 | 2263 | |
0633879f PB |
2264 | DISAS_INSN(move_to_ccr) |
2265 | { | |
620c6cf6 | 2266 | gen_set_sr(env, s, insn, 1); |
0633879f PB |
2267 | } |
2268 | ||
e6e5906b PB |
2269 | DISAS_INSN(not) |
2270 | { | |
ea4f2a84 LV |
2271 | TCGv src1; |
2272 | TCGv dest; | |
2273 | TCGv addr; | |
2274 | int opsize; | |
e6e5906b | 2275 | |
ea4f2a84 LV |
2276 | opsize = insn_opsize(insn); |
2277 | SRC_EA(env, src1, opsize, 1, &addr); | |
2278 | dest = tcg_temp_new(); | |
2279 | tcg_gen_not_i32(dest, src1); | |
2280 | DEST_EA(env, insn, opsize, dest, &addr); | |
2281 | gen_logic_cc(s, dest, opsize); | |
e6e5906b PB |
2282 | } |
2283 | ||
2284 | DISAS_INSN(swap) | |
2285 | { | |
e1f3808e PB |
2286 | TCGv src1; |
2287 | TCGv src2; | |
2288 | TCGv reg; | |
e6e5906b | 2289 | |
a7812ae4 PB |
2290 | src1 = tcg_temp_new(); |
2291 | src2 = tcg_temp_new(); | |
e6e5906b | 2292 | reg = DREG(insn, 0); |
e1f3808e PB |
2293 | tcg_gen_shli_i32(src1, reg, 16); |
2294 | tcg_gen_shri_i32(src2, reg, 16); | |
2295 | tcg_gen_or_i32(reg, src1, src2); | |
2b5e2170 LV |
2296 | tcg_temp_free(src2); |
2297 | tcg_temp_free(src1); | |
5dbb6784 | 2298 | gen_logic_cc(s, reg, OS_LONG); |
e6e5906b PB |
2299 | } |
2300 | ||
71600eda LV |
2301 | DISAS_INSN(bkpt) |
2302 | { | |
2303 | gen_exception(s, s->pc - 2, EXCP_DEBUG); | |
2304 | } | |
2305 | ||
e6e5906b PB |
2306 | DISAS_INSN(pea) |
2307 | { | |
e1f3808e | 2308 | TCGv tmp; |
e6e5906b | 2309 | |
d4d79bb1 | 2310 | tmp = gen_lea(env, s, insn, OS_LONG); |
e1f3808e | 2311 | if (IS_NULL_QREG(tmp)) { |
510ff0b7 PB |
2312 | gen_addr_fault(s); |
2313 | return; | |
2314 | } | |
0633879f | 2315 | gen_push(s, tmp); |
e6e5906b PB |
2316 | } |
2317 | ||
2318 | DISAS_INSN(ext) | |
2319 | { | |
e6e5906b | 2320 | int op; |
e1f3808e PB |
2321 | TCGv reg; |
2322 | TCGv tmp; | |
e6e5906b PB |
2323 | |
2324 | reg = DREG(insn, 0); | |
2325 | op = (insn >> 6) & 7; | |
a7812ae4 | 2326 | tmp = tcg_temp_new(); |
e6e5906b | 2327 | if (op == 3) |
e1f3808e | 2328 | tcg_gen_ext16s_i32(tmp, reg); |
e6e5906b | 2329 | else |
e1f3808e | 2330 | tcg_gen_ext8s_i32(tmp, reg); |
e6e5906b PB |
2331 | if (op == 2) |
2332 | gen_partset_reg(OS_WORD, reg, tmp); | |
2333 | else | |
e1f3808e | 2334 | tcg_gen_mov_i32(reg, tmp); |
5dbb6784 | 2335 | gen_logic_cc(s, tmp, OS_LONG); |
2b5e2170 | 2336 | tcg_temp_free(tmp); |
e6e5906b PB |
2337 | } |
2338 | ||
2339 | DISAS_INSN(tst) | |
2340 | { | |
2341 | int opsize; | |
e1f3808e | 2342 | TCGv tmp; |
e6e5906b | 2343 | |
7ef25cdd | 2344 | opsize = insn_opsize(insn); |
d4d79bb1 | 2345 | SRC_EA(env, tmp, opsize, 1, NULL); |
5dbb6784 | 2346 | gen_logic_cc(s, tmp, opsize); |
e6e5906b PB |
2347 | } |
2348 | ||
2349 | DISAS_INSN(pulse) | |
2350 | { | |
2351 | /* Implemented as a NOP. */ | |
2352 | } | |
2353 | ||
2354 | DISAS_INSN(illegal) | |
2355 | { | |
2356 | gen_exception(s, s->pc - 2, EXCP_ILLEGAL); | |
2357 | } | |
2358 | ||
2359 | /* ??? This should be atomic. */ | |
2360 | DISAS_INSN(tas) | |
2361 | { | |
e1f3808e PB |
2362 | TCGv dest; |
2363 | TCGv src1; | |
2364 | TCGv addr; | |
e6e5906b | 2365 | |
a7812ae4 | 2366 | dest = tcg_temp_new(); |
d4d79bb1 | 2367 | SRC_EA(env, src1, OS_BYTE, 1, &addr); |
5dbb6784 | 2368 | gen_logic_cc(s, src1, OS_BYTE); |
e1f3808e | 2369 | tcg_gen_ori_i32(dest, src1, 0x80); |
d4d79bb1 | 2370 | DEST_EA(env, insn, OS_BYTE, dest, &addr); |
2b5e2170 | 2371 | tcg_temp_free(dest); |
e6e5906b PB |
2372 | } |
2373 | ||
2374 | DISAS_INSN(mull) | |
2375 | { | |
2376 | uint16_t ext; | |
e1f3808e | 2377 | TCGv src1; |
8be95def | 2378 | int sign; |
e6e5906b | 2379 | |
28b68cd7 | 2380 | ext = read_im16(env, s); |
8be95def LV |
2381 | |
2382 | sign = ext & 0x800; | |
2383 | ||
2384 | if (ext & 0x400) { | |
2385 | if (!m68k_feature(s->env, M68K_FEATURE_QUAD_MULDIV)) { | |
2386 | gen_exception(s, s->pc - 4, EXCP_UNSUPPORTED); | |
2387 | return; | |
2388 | } | |
2389 | ||
2390 | SRC_EA(env, src1, OS_LONG, 0, NULL); | |
2391 | ||
2392 | if (sign) { | |
2393 | tcg_gen_muls2_i32(QREG_CC_Z, QREG_CC_N, src1, DREG(ext, 12)); | |
2394 | } else { | |
2395 | tcg_gen_mulu2_i32(QREG_CC_Z, QREG_CC_N, src1, DREG(ext, 12)); | |
2396 | } | |
2397 | /* if Dl == Dh, 68040 returns low word */ | |
2398 | tcg_gen_mov_i32(DREG(ext, 0), QREG_CC_N); | |
2399 | tcg_gen_mov_i32(DREG(ext, 12), QREG_CC_Z); | |
2400 | tcg_gen_or_i32(QREG_CC_Z, QREG_CC_Z, QREG_CC_N); | |
2401 | ||
2402 | tcg_gen_movi_i32(QREG_CC_V, 0); | |
2403 | tcg_gen_movi_i32(QREG_CC_C, 0); | |
2404 | ||
2405 | set_cc_op(s, CC_OP_FLAGS); | |
e6e5906b PB |
2406 | return; |
2407 | } | |
d4d79bb1 | 2408 | SRC_EA(env, src1, OS_LONG, 0, NULL); |
8be95def LV |
2409 | if (m68k_feature(s->env, M68K_FEATURE_M68000)) { |
2410 | tcg_gen_movi_i32(QREG_CC_C, 0); | |
2411 | if (sign) { | |
2412 | tcg_gen_muls2_i32(QREG_CC_N, QREG_CC_V, src1, DREG(ext, 12)); | |
2413 | /* QREG_CC_V is -(QREG_CC_V != (QREG_CC_N >> 31)) */ | |
2414 | tcg_gen_sari_i32(QREG_CC_Z, QREG_CC_N, 31); | |
2415 | tcg_gen_setcond_i32(TCG_COND_NE, QREG_CC_V, QREG_CC_V, QREG_CC_Z); | |
2416 | } else { | |
2417 | tcg_gen_mulu2_i32(QREG_CC_N, QREG_CC_V, src1, DREG(ext, 12)); | |
2418 | /* QREG_CC_V is -(QREG_CC_V != 0), use QREG_CC_C as 0 */ | |
2419 | tcg_gen_setcond_i32(TCG_COND_NE, QREG_CC_V, QREG_CC_V, QREG_CC_C); | |
2420 | } | |
2421 | tcg_gen_neg_i32(QREG_CC_V, QREG_CC_V); | |
2422 | tcg_gen_mov_i32(DREG(ext, 12), QREG_CC_N); | |
2423 | ||
2424 | tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N); | |
2425 | ||
2426 | set_cc_op(s, CC_OP_FLAGS); | |
2427 | } else { | |
2428 | /* The upper 32 bits of the product are discarded, so | |
2429 | muls.l and mulu.l are functionally equivalent. */ | |
2430 | tcg_gen_mul_i32(DREG(ext, 12), src1, DREG(ext, 12)); | |
2431 | gen_logic_cc(s, DREG(ext, 12), OS_LONG); | |
2432 | } | |
e6e5906b PB |
2433 | } |
2434 | ||
c630e436 | 2435 | static void gen_link(DisasContext *s, uint16_t insn, int32_t offset) |
e6e5906b | 2436 | { |
e1f3808e PB |
2437 | TCGv reg; |
2438 | TCGv tmp; | |
e6e5906b | 2439 | |
e6e5906b | 2440 | reg = AREG(insn, 0); |
a7812ae4 | 2441 | tmp = tcg_temp_new(); |
e1f3808e | 2442 | tcg_gen_subi_i32(tmp, QREG_SP, 4); |
0633879f | 2443 | gen_store(s, OS_LONG, tmp, reg); |
c630e436 | 2444 | if ((insn & 7) != 7) { |
e1f3808e | 2445 | tcg_gen_mov_i32(reg, tmp); |
c630e436 | 2446 | } |
e1f3808e | 2447 | tcg_gen_addi_i32(QREG_SP, tmp, offset); |
c630e436 LV |
2448 | tcg_temp_free(tmp); |
2449 | } | |
2450 | ||
2451 | DISAS_INSN(link) | |
2452 | { | |
2453 | int16_t offset; | |
2454 | ||
2455 | offset = read_im16(env, s); | |
2456 | gen_link(s, insn, offset); | |
2457 | } | |
2458 | ||
2459 | DISAS_INSN(linkl) | |
2460 | { | |
2461 | int32_t offset; | |
2462 | ||
2463 | offset = read_im32(env, s); | |
2464 | gen_link(s, insn, offset); | |
e6e5906b PB |
2465 | } |
2466 | ||
2467 | DISAS_INSN(unlk) | |
2468 | { | |
e1f3808e PB |
2469 | TCGv src; |
2470 | TCGv reg; | |
2471 | TCGv tmp; | |
e6e5906b | 2472 | |
a7812ae4 | 2473 | src = tcg_temp_new(); |
e6e5906b | 2474 | reg = AREG(insn, 0); |
e1f3808e | 2475 | tcg_gen_mov_i32(src, reg); |
0633879f | 2476 | tmp = gen_load(s, OS_LONG, src, 0); |
e1f3808e PB |
2477 | tcg_gen_mov_i32(reg, tmp); |
2478 | tcg_gen_addi_i32(QREG_SP, src, 4); | |
2b5e2170 | 2479 | tcg_temp_free(src); |
e6e5906b PB |
2480 | } |
2481 | ||
2482 | DISAS_INSN(nop) | |
2483 | { | |
2484 | } | |
2485 | ||
2486 | DISAS_INSN(rts) | |
2487 | { | |
e1f3808e | 2488 | TCGv tmp; |
e6e5906b | 2489 | |
0633879f | 2490 | tmp = gen_load(s, OS_LONG, QREG_SP, 0); |
e1f3808e | 2491 | tcg_gen_addi_i32(QREG_SP, QREG_SP, 4); |
e6e5906b PB |
2492 | gen_jmp(s, tmp); |
2493 | } | |
2494 | ||
2495 | DISAS_INSN(jump) | |
2496 | { | |
e1f3808e | 2497 | TCGv tmp; |
e6e5906b PB |
2498 | |
2499 | /* Load the target address first to ensure correct exception | |
2500 | behavior. */ | |
d4d79bb1 | 2501 | tmp = gen_lea(env, s, insn, OS_LONG); |
e1f3808e | 2502 | if (IS_NULL_QREG(tmp)) { |
510ff0b7 PB |
2503 | gen_addr_fault(s); |
2504 | return; | |
2505 | } | |
e6e5906b PB |
2506 | if ((insn & 0x40) == 0) { |
2507 | /* jsr */ | |
351326a6 | 2508 | gen_push(s, tcg_const_i32(s->pc)); |
e6e5906b PB |
2509 | } |
2510 | gen_jmp(s, tmp); | |
2511 | } | |
2512 | ||
2513 | DISAS_INSN(addsubq) | |
2514 | { | |
8a370c6c | 2515 | TCGv src; |
e1f3808e | 2516 | TCGv dest; |
8a370c6c LV |
2517 | TCGv val; |
2518 | int imm; | |
e1f3808e | 2519 | TCGv addr; |
8a370c6c | 2520 | int opsize; |
e6e5906b | 2521 | |
8a370c6c LV |
2522 | if ((insn & 070) == 010) { |
2523 | /* Operation on address register is always long. */ | |
2524 | opsize = OS_LONG; | |
2525 | } else { | |
2526 | opsize = insn_opsize(insn); | |
2527 | } | |
2528 | SRC_EA(env, src, opsize, 1, &addr); | |
2529 | imm = (insn >> 9) & 7; | |
2530 | if (imm == 0) { | |
2531 | imm = 8; | |
2532 | } | |
2533 | val = tcg_const_i32(imm); | |
a7812ae4 | 2534 | dest = tcg_temp_new(); |
8a370c6c | 2535 | tcg_gen_mov_i32(dest, src); |
e6e5906b PB |
2536 | if ((insn & 0x38) == 0x08) { |
2537 | /* Don't update condition codes if the destination is an | |
2538 | address register. */ | |
2539 | if (insn & 0x0100) { | |
8a370c6c | 2540 | tcg_gen_sub_i32(dest, dest, val); |
e6e5906b | 2541 | } else { |
8a370c6c | 2542 | tcg_gen_add_i32(dest, dest, val); |
e6e5906b PB |
2543 | } |
2544 | } else { | |
2545 | if (insn & 0x0100) { | |
8a370c6c LV |
2546 | tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, dest, val); |
2547 | tcg_gen_sub_i32(dest, dest, val); | |
2548 | set_cc_op(s, CC_OP_SUBB + opsize); | |
e6e5906b | 2549 | } else { |
8a370c6c LV |
2550 | tcg_gen_add_i32(dest, dest, val); |
2551 | tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, dest, val); | |
2552 | set_cc_op(s, CC_OP_ADDB + opsize); | |
e6e5906b | 2553 | } |
8a370c6c | 2554 | gen_update_cc_add(dest, val, opsize); |
e6e5906b | 2555 | } |
2b5e2170 | 2556 | tcg_temp_free(val); |
8a370c6c | 2557 | DEST_EA(env, insn, opsize, dest, &addr); |
2b5e2170 | 2558 | tcg_temp_free(dest); |
e6e5906b PB |
2559 | } |
2560 | ||
2561 | DISAS_INSN(tpf) | |
2562 | { | |
2563 | switch (insn & 7) { | |
2564 | case 2: /* One extension word. */ | |
2565 | s->pc += 2; | |
2566 | break; | |
2567 | case 3: /* Two extension words. */ | |
2568 | s->pc += 4; | |
2569 | break; | |
2570 | case 4: /* No extension words. */ | |
2571 | break; | |
2572 | default: | |
d4d79bb1 | 2573 | disas_undef(env, s, insn); |
e6e5906b PB |
2574 | } |
2575 | } | |
2576 | ||
2577 | DISAS_INSN(branch) | |
2578 | { | |
2579 | int32_t offset; | |
2580 | uint32_t base; | |
2581 | int op; | |
42a268c2 | 2582 | TCGLabel *l1; |
3b46e624 | 2583 | |
e6e5906b PB |
2584 | base = s->pc; |
2585 | op = (insn >> 8) & 0xf; | |
2586 | offset = (int8_t)insn; | |
2587 | if (offset == 0) { | |
28b68cd7 | 2588 | offset = (int16_t)read_im16(env, s); |
e6e5906b | 2589 | } else if (offset == -1) { |
d4d79bb1 | 2590 | offset = read_im32(env, s); |
e6e5906b PB |
2591 | } |
2592 | if (op == 1) { | |
2593 | /* bsr */ | |
351326a6 | 2594 | gen_push(s, tcg_const_i32(s->pc)); |
e6e5906b | 2595 | } |
e6e5906b PB |
2596 | if (op > 1) { |
2597 | /* Bcc */ | |
2598 | l1 = gen_new_label(); | |
2599 | gen_jmpcc(s, ((insn >> 8) & 0xf) ^ 1, l1); | |
2600 | gen_jmp_tb(s, 1, base + offset); | |
2601 | gen_set_label(l1); | |
2602 | gen_jmp_tb(s, 0, s->pc); | |
2603 | } else { | |
2604 | /* Unconditional branch. */ | |
2605 | gen_jmp_tb(s, 0, base + offset); | |
2606 | } | |
2607 | } | |
2608 | ||
2609 | DISAS_INSN(moveq) | |
2610 | { | |
2b5e2170 LV |
2611 | tcg_gen_movi_i32(DREG(insn, 9), (int8_t)insn); |
2612 | gen_logic_cc(s, DREG(insn, 9), OS_LONG); | |
e6e5906b PB |
2613 | } |
2614 | ||
2615 | DISAS_INSN(mvzs) | |
2616 | { | |
2617 | int opsize; | |
e1f3808e PB |
2618 | TCGv src; |
2619 | TCGv reg; | |
e6e5906b PB |
2620 | |
2621 | if (insn & 0x40) | |
2622 | opsize = OS_WORD; | |
2623 | else | |
2624 | opsize = OS_BYTE; | |
d4d79bb1 | 2625 | SRC_EA(env, src, opsize, (insn & 0x80) == 0, NULL); |
e6e5906b | 2626 | reg = DREG(insn, 9); |
e1f3808e | 2627 | tcg_gen_mov_i32(reg, src); |
5dbb6784 | 2628 | gen_logic_cc(s, src, opsize); |
e6e5906b PB |
2629 | } |
2630 | ||
2631 | DISAS_INSN(or) | |
2632 | { | |
e1f3808e PB |
2633 | TCGv reg; |
2634 | TCGv dest; | |
2635 | TCGv src; | |
2636 | TCGv addr; | |
020a4659 | 2637 | int opsize; |
e6e5906b | 2638 | |
020a4659 LV |
2639 | opsize = insn_opsize(insn); |
2640 | reg = gen_extend(DREG(insn, 9), opsize, 0); | |
a7812ae4 | 2641 | dest = tcg_temp_new(); |
e6e5906b | 2642 | if (insn & 0x100) { |
020a4659 | 2643 | SRC_EA(env, src, opsize, 0, &addr); |
e1f3808e | 2644 | tcg_gen_or_i32(dest, src, reg); |
020a4659 | 2645 | DEST_EA(env, insn, opsize, dest, &addr); |
e6e5906b | 2646 | } else { |
020a4659 | 2647 | SRC_EA(env, src, opsize, 0, NULL); |
e1f3808e | 2648 | tcg_gen_or_i32(dest, src, reg); |
020a4659 | 2649 | gen_partset_reg(opsize, DREG(insn, 9), dest); |
e6e5906b | 2650 | } |
020a4659 | 2651 | gen_logic_cc(s, dest, opsize); |
2b5e2170 | 2652 | tcg_temp_free(dest); |
e6e5906b PB |
2653 | } |
2654 | ||
2655 | DISAS_INSN(suba) | |
2656 | { | |
e1f3808e PB |
2657 | TCGv src; |
2658 | TCGv reg; | |
e6e5906b | 2659 | |
415f4b62 | 2660 | SRC_EA(env, src, (insn & 0x100) ? OS_LONG : OS_WORD, 1, NULL); |
e6e5906b | 2661 | reg = AREG(insn, 9); |
e1f3808e | 2662 | tcg_gen_sub_i32(reg, reg, src); |
e6e5906b PB |
2663 | } |
2664 | ||
a665a820 | 2665 | static inline void gen_subx(DisasContext *s, TCGv src, TCGv dest, int opsize) |
e6e5906b | 2666 | { |
a665a820 RH |
2667 | TCGv tmp; |
2668 | ||
2669 | gen_flush_flags(s); /* compute old Z */ | |
2670 | ||
2671 | /* Perform substract with borrow. | |
2672 | * (X, N) = dest - (src + X); | |
2673 | */ | |
2674 | ||
2675 | tmp = tcg_const_i32(0); | |
2676 | tcg_gen_add2_i32(QREG_CC_N, QREG_CC_X, src, tmp, QREG_CC_X, tmp); | |
2677 | tcg_gen_sub2_i32(QREG_CC_N, QREG_CC_X, dest, tmp, QREG_CC_N, QREG_CC_X); | |
2678 | gen_ext(QREG_CC_N, QREG_CC_N, opsize, 1); | |
2679 | tcg_gen_andi_i32(QREG_CC_X, QREG_CC_X, 1); | |
2680 | ||
2681 | /* Compute signed-overflow for substract. */ | |
2682 | ||
2683 | tcg_gen_xor_i32(QREG_CC_V, QREG_CC_N, dest); | |
2684 | tcg_gen_xor_i32(tmp, dest, src); | |
2685 | tcg_gen_and_i32(QREG_CC_V, QREG_CC_V, tmp); | |
2686 | tcg_temp_free(tmp); | |
2687 | ||
2688 | /* Copy the rest of the results into place. */ | |
2689 | tcg_gen_or_i32(QREG_CC_Z, QREG_CC_Z, QREG_CC_N); /* !Z is sticky */ | |
2690 | tcg_gen_mov_i32(QREG_CC_C, QREG_CC_X); | |
2691 | ||
2692 | set_cc_op(s, CC_OP_FLAGS); | |
2693 | ||
2694 | /* result is in QREG_CC_N */ | |
2695 | } | |
2696 | ||
2697 | DISAS_INSN(subx_reg) | |
2698 | { | |
2699 | TCGv dest; | |
e1f3808e | 2700 | TCGv src; |
a665a820 | 2701 | int opsize; |
e6e5906b | 2702 | |
a665a820 RH |
2703 | opsize = insn_opsize(insn); |
2704 | ||
2705 | src = gen_extend(DREG(insn, 0), opsize, 1); | |
2706 | dest = gen_extend(DREG(insn, 9), opsize, 1); | |
2707 | ||
2708 | gen_subx(s, src, dest, opsize); | |
2709 | ||
2710 | gen_partset_reg(opsize, DREG(insn, 9), QREG_CC_N); | |
2711 | } | |
2712 | ||
2713 | DISAS_INSN(subx_mem) | |
2714 | { | |
2715 | TCGv src; | |
2716 | TCGv addr_src; | |
2717 | TCGv dest; | |
2718 | TCGv addr_dest; | |
2719 | int opsize; | |
2720 | ||
2721 | opsize = insn_opsize(insn); | |
2722 | ||
2723 | addr_src = AREG(insn, 0); | |
2724 | tcg_gen_subi_i32(addr_src, addr_src, opsize); | |
2725 | src = gen_load(s, opsize, addr_src, 1); | |
2726 | ||
2727 | addr_dest = AREG(insn, 9); | |
2728 | tcg_gen_subi_i32(addr_dest, addr_dest, opsize); | |
2729 | dest = gen_load(s, opsize, addr_dest, 1); | |
2730 | ||
2731 | gen_subx(s, src, dest, opsize); | |
2732 | ||
2733 | gen_store(s, opsize, addr_dest, QREG_CC_N); | |
e6e5906b PB |
2734 | } |
2735 | ||
2736 | DISAS_INSN(mov3q) | |
2737 | { | |
e1f3808e | 2738 | TCGv src; |
e6e5906b PB |
2739 | int val; |
2740 | ||
2741 | val = (insn >> 9) & 7; | |
2742 | if (val == 0) | |
2743 | val = -1; | |
351326a6 | 2744 | src = tcg_const_i32(val); |
5dbb6784 | 2745 | gen_logic_cc(s, src, OS_LONG); |
d4d79bb1 | 2746 | DEST_EA(env, insn, OS_LONG, src, NULL); |
2b5e2170 | 2747 | tcg_temp_free(src); |
e6e5906b PB |
2748 | } |
2749 | ||
2750 | DISAS_INSN(cmp) | |
2751 | { | |
e1f3808e PB |
2752 | TCGv src; |
2753 | TCGv reg; | |
e6e5906b PB |
2754 | int opsize; |
2755 | ||
5dbb6784 | 2756 | opsize = insn_opsize(insn); |
ff99b952 LV |
2757 | SRC_EA(env, src, opsize, 1, NULL); |
2758 | reg = gen_extend(DREG(insn, 9), opsize, 1); | |
2759 | gen_update_cc_cmp(s, reg, src, opsize); | |
e6e5906b PB |
2760 | } |
2761 | ||
2762 | DISAS_INSN(cmpa) | |
2763 | { | |
2764 | int opsize; | |
e1f3808e PB |
2765 | TCGv src; |
2766 | TCGv reg; | |
e6e5906b PB |
2767 | |
2768 | if (insn & 0x100) { | |
2769 | opsize = OS_LONG; | |
2770 | } else { | |
2771 | opsize = OS_WORD; | |
2772 | } | |
d4d79bb1 | 2773 | SRC_EA(env, src, opsize, 1, NULL); |
e6e5906b | 2774 | reg = AREG(insn, 9); |
5436c29d | 2775 | gen_update_cc_cmp(s, reg, src, OS_LONG); |
e6e5906b PB |
2776 | } |
2777 | ||
817af1c7 LV |
2778 | DISAS_INSN(cmpm) |
2779 | { | |
2780 | int opsize = insn_opsize(insn); | |
2781 | TCGv src, dst; | |
2782 | ||
2783 | /* Post-increment load (mode 3) from Ay. */ | |
2784 | src = gen_ea_mode(env, s, 3, REG(insn, 0), opsize, | |
2785 | NULL_QREG, NULL, EA_LOADS); | |
2786 | /* Post-increment load (mode 3) from Ax. */ | |
2787 | dst = gen_ea_mode(env, s, 3, REG(insn, 9), opsize, | |
2788 | NULL_QREG, NULL, EA_LOADS); | |
2789 | ||
2790 | gen_update_cc_cmp(s, dst, src, opsize); | |
2791 | } | |
2792 | ||
e6e5906b PB |
2793 | DISAS_INSN(eor) |
2794 | { | |
e1f3808e | 2795 | TCGv src; |
e1f3808e PB |
2796 | TCGv dest; |
2797 | TCGv addr; | |
eec37aec | 2798 | int opsize; |
e6e5906b | 2799 | |
eec37aec LV |
2800 | opsize = insn_opsize(insn); |
2801 | ||
2802 | SRC_EA(env, src, opsize, 0, &addr); | |
a7812ae4 | 2803 | dest = tcg_temp_new(); |
eec37aec LV |
2804 | tcg_gen_xor_i32(dest, src, DREG(insn, 9)); |
2805 | gen_logic_cc(s, dest, opsize); | |
2806 | DEST_EA(env, insn, opsize, dest, &addr); | |
2b5e2170 | 2807 | tcg_temp_free(dest); |
e6e5906b PB |
2808 | } |
2809 | ||
29cf437d LV |
2810 | static void do_exg(TCGv reg1, TCGv reg2) |
2811 | { | |
2812 | TCGv temp = tcg_temp_new(); | |
2813 | tcg_gen_mov_i32(temp, reg1); | |
2814 | tcg_gen_mov_i32(reg1, reg2); | |
2815 | tcg_gen_mov_i32(reg2, temp); | |
2816 | tcg_temp_free(temp); | |
2817 | } | |
2818 | ||
c090c97d | 2819 | DISAS_INSN(exg_dd) |
29cf437d LV |
2820 | { |
2821 | /* exchange Dx and Dy */ | |
2822 | do_exg(DREG(insn, 9), DREG(insn, 0)); | |
2823 | } | |
2824 | ||
c090c97d | 2825 | DISAS_INSN(exg_aa) |
29cf437d LV |
2826 | { |
2827 | /* exchange Ax and Ay */ | |
2828 | do_exg(AREG(insn, 9), AREG(insn, 0)); | |
2829 | } | |
2830 | ||
2831 | DISAS_INSN(exg_da) | |
2832 | { | |
2833 | /* exchange Dx and Ay */ | |
2834 | do_exg(DREG(insn, 9), AREG(insn, 0)); | |
2835 | } | |
2836 | ||
e6e5906b PB |
2837 | DISAS_INSN(and) |
2838 | { | |
e1f3808e PB |
2839 | TCGv src; |
2840 | TCGv reg; | |
2841 | TCGv dest; | |
2842 | TCGv addr; | |
52dc23c5 | 2843 | int opsize; |
e6e5906b | 2844 | |
a7812ae4 | 2845 | dest = tcg_temp_new(); |
52dc23c5 LV |
2846 | |
2847 | opsize = insn_opsize(insn); | |
2848 | reg = DREG(insn, 9); | |
e6e5906b | 2849 | if (insn & 0x100) { |
52dc23c5 | 2850 | SRC_EA(env, src, opsize, 0, &addr); |
e1f3808e | 2851 | tcg_gen_and_i32(dest, src, reg); |
52dc23c5 | 2852 | DEST_EA(env, insn, opsize, dest, &addr); |
e6e5906b | 2853 | } else { |
52dc23c5 | 2854 | SRC_EA(env, src, opsize, 0, NULL); |
e1f3808e | 2855 | tcg_gen_and_i32(dest, src, reg); |
52dc23c5 | 2856 | gen_partset_reg(opsize, reg, dest); |
e6e5906b | 2857 | } |
52dc23c5 | 2858 | gen_logic_cc(s, dest, opsize); |
2b5e2170 | 2859 | tcg_temp_free(dest); |
e6e5906b PB |
2860 | } |
2861 | ||
2862 | DISAS_INSN(adda) | |
2863 | { | |
e1f3808e PB |
2864 | TCGv src; |
2865 | TCGv reg; | |
e6e5906b | 2866 | |
415f4b62 | 2867 | SRC_EA(env, src, (insn & 0x100) ? OS_LONG : OS_WORD, 1, NULL); |
e6e5906b | 2868 | reg = AREG(insn, 9); |
e1f3808e | 2869 | tcg_gen_add_i32(reg, reg, src); |
e6e5906b PB |
2870 | } |
2871 | ||
a665a820 | 2872 | static inline void gen_addx(DisasContext *s, TCGv src, TCGv dest, int opsize) |
e6e5906b | 2873 | { |
a665a820 RH |
2874 | TCGv tmp; |
2875 | ||
2876 | gen_flush_flags(s); /* compute old Z */ | |
2877 | ||
2878 | /* Perform addition with carry. | |
2879 | * (X, N) = src + dest + X; | |
2880 | */ | |
2881 | ||
2882 | tmp = tcg_const_i32(0); | |
2883 | tcg_gen_add2_i32(QREG_CC_N, QREG_CC_X, QREG_CC_X, tmp, dest, tmp); | |
2884 | tcg_gen_add2_i32(QREG_CC_N, QREG_CC_X, QREG_CC_N, QREG_CC_X, src, tmp); | |
2885 | gen_ext(QREG_CC_N, QREG_CC_N, opsize, 1); | |
2886 | ||
2887 | /* Compute signed-overflow for addition. */ | |
2888 | ||
2889 | tcg_gen_xor_i32(QREG_CC_V, QREG_CC_N, src); | |
2890 | tcg_gen_xor_i32(tmp, dest, src); | |
2891 | tcg_gen_andc_i32(QREG_CC_V, QREG_CC_V, tmp); | |
2892 | tcg_temp_free(tmp); | |
2893 | ||
2894 | /* Copy the rest of the results into place. */ | |
2895 | tcg_gen_or_i32(QREG_CC_Z, QREG_CC_Z, QREG_CC_N); /* !Z is sticky */ | |
2896 | tcg_gen_mov_i32(QREG_CC_C, QREG_CC_X); | |
2897 | ||
2898 | set_cc_op(s, CC_OP_FLAGS); | |
2899 | ||
2900 | /* result is in QREG_CC_N */ | |
2901 | } | |
2902 | ||
2903 | DISAS_INSN(addx_reg) | |
2904 | { | |
2905 | TCGv dest; | |
e1f3808e | 2906 | TCGv src; |
a665a820 | 2907 | int opsize; |
e6e5906b | 2908 | |
a665a820 RH |
2909 | opsize = insn_opsize(insn); |
2910 | ||
2911 | dest = gen_extend(DREG(insn, 9), opsize, 1); | |
2912 | src = gen_extend(DREG(insn, 0), opsize, 1); | |
2913 | ||
2914 | gen_addx(s, src, dest, opsize); | |
2915 | ||
2916 | gen_partset_reg(opsize, DREG(insn, 9), QREG_CC_N); | |
2917 | } | |
2918 | ||
2919 | DISAS_INSN(addx_mem) | |
2920 | { | |
2921 | TCGv src; | |
2922 | TCGv addr_src; | |
2923 | TCGv dest; | |
2924 | TCGv addr_dest; | |
2925 | int opsize; | |
2926 | ||
2927 | opsize = insn_opsize(insn); | |
2928 | ||
2929 | addr_src = AREG(insn, 0); | |
2930 | tcg_gen_subi_i32(addr_src, addr_src, opsize_bytes(opsize)); | |
2931 | src = gen_load(s, opsize, addr_src, 1); | |
2932 | ||
2933 | addr_dest = AREG(insn, 9); | |
2934 | tcg_gen_subi_i32(addr_dest, addr_dest, opsize_bytes(opsize)); | |
2935 | dest = gen_load(s, opsize, addr_dest, 1); | |
2936 | ||
2937 | gen_addx(s, src, dest, opsize); | |
2938 | ||
2939 | gen_store(s, opsize, addr_dest, QREG_CC_N); | |
e6e5906b PB |
2940 | } |
2941 | ||
367790cc | 2942 | static inline void shift_im(DisasContext *s, uint16_t insn, int opsize) |
e6e5906b | 2943 | { |
367790cc RH |
2944 | int count = (insn >> 9) & 7; |
2945 | int logical = insn & 8; | |
2946 | int left = insn & 0x100; | |
2947 | int bits = opsize_bytes(opsize) * 8; | |
2948 | TCGv reg = gen_extend(DREG(insn, 0), opsize, !logical); | |
2949 | ||
2950 | if (count == 0) { | |
2951 | count = 8; | |
2952 | } | |
2953 | ||
2954 | tcg_gen_movi_i32(QREG_CC_V, 0); | |
2955 | if (left) { | |
2956 | tcg_gen_shri_i32(QREG_CC_C, reg, bits - count); | |
2957 | tcg_gen_shli_i32(QREG_CC_N, reg, count); | |
2958 | ||
2959 | /* Note that ColdFire always clears V (done above), | |
2960 | while M68000 sets if the most significant bit is changed at | |
2961 | any time during the shift operation */ | |
2962 | if (!logical && m68k_feature(s->env, M68K_FEATURE_M68000)) { | |
2963 | /* if shift count >= bits, V is (reg != 0) */ | |
2964 | if (count >= bits) { | |
2965 | tcg_gen_setcond_i32(TCG_COND_NE, QREG_CC_V, reg, QREG_CC_V); | |
2966 | } else { | |
2967 | TCGv t0 = tcg_temp_new(); | |
2968 | tcg_gen_sari_i32(QREG_CC_V, reg, bits - 1); | |
2969 | tcg_gen_sari_i32(t0, reg, bits - count - 1); | |
2970 | tcg_gen_setcond_i32(TCG_COND_NE, QREG_CC_V, QREG_CC_V, t0); | |
2971 | tcg_temp_free(t0); | |
2972 | } | |
2973 | tcg_gen_neg_i32(QREG_CC_V, QREG_CC_V); | |
2974 | } | |
2975 | } else { | |
2976 | tcg_gen_shri_i32(QREG_CC_C, reg, count - 1); | |
2977 | if (logical) { | |
2978 | tcg_gen_shri_i32(QREG_CC_N, reg, count); | |
2979 | } else { | |
2980 | tcg_gen_sari_i32(QREG_CC_N, reg, count); | |
2981 | } | |
2982 | } | |
2983 | ||
2984 | gen_ext(QREG_CC_N, QREG_CC_N, opsize, 1); | |
2985 | tcg_gen_andi_i32(QREG_CC_C, QREG_CC_C, 1); | |
2986 | tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N); | |
2987 | tcg_gen_mov_i32(QREG_CC_X, QREG_CC_C); | |
e6e5906b | 2988 | |
367790cc | 2989 | gen_partset_reg(opsize, DREG(insn, 0), QREG_CC_N); |
620c6cf6 | 2990 | set_cc_op(s, CC_OP_FLAGS); |
367790cc | 2991 | } |
620c6cf6 | 2992 | |
367790cc RH |
2993 | static inline void shift_reg(DisasContext *s, uint16_t insn, int opsize) |
2994 | { | |
2995 | int logical = insn & 8; | |
2996 | int left = insn & 0x100; | |
2997 | int bits = opsize_bytes(opsize) * 8; | |
2998 | TCGv reg = gen_extend(DREG(insn, 0), opsize, !logical); | |
2999 | TCGv s32; | |
3000 | TCGv_i64 t64, s64; | |
3001 | ||
3002 | t64 = tcg_temp_new_i64(); | |
3003 | s64 = tcg_temp_new_i64(); | |
3004 | s32 = tcg_temp_new(); | |
3005 | ||
3006 | /* Note that m68k truncates the shift count modulo 64, not 32. | |
3007 | In addition, a 64-bit shift makes it easy to find "the last | |
3008 | bit shifted out", for the carry flag. */ | |
3009 | tcg_gen_andi_i32(s32, DREG(insn, 9), 63); | |
3010 | tcg_gen_extu_i32_i64(s64, s32); | |
3011 | tcg_gen_extu_i32_i64(t64, reg); | |
3012 | ||
3013 | /* Optimistically set V=0. Also used as a zero source below. */ | |
3014 | tcg_gen_movi_i32(QREG_CC_V, 0); | |
3015 | if (left) { | |
3016 | tcg_gen_shl_i64(t64, t64, s64); | |
3017 | ||
3018 | if (opsize == OS_LONG) { | |
3019 | tcg_gen_extr_i64_i32(QREG_CC_N, QREG_CC_C, t64); | |
3020 | /* Note that C=0 if shift count is 0, and we get that for free. */ | |
3021 | } else { | |
3022 | TCGv zero = tcg_const_i32(0); | |
3023 | tcg_gen_extrl_i64_i32(QREG_CC_N, t64); | |
3024 | tcg_gen_shri_i32(QREG_CC_C, QREG_CC_N, bits); | |
3025 | tcg_gen_movcond_i32(TCG_COND_EQ, QREG_CC_C, | |
3026 | s32, zero, zero, QREG_CC_C); | |
3027 | tcg_temp_free(zero); | |
3028 | } | |
3029 | tcg_gen_andi_i32(QREG_CC_C, QREG_CC_C, 1); | |
3030 | ||
3031 | /* X = C, but only if the shift count was non-zero. */ | |
3032 | tcg_gen_movcond_i32(TCG_COND_NE, QREG_CC_X, s32, QREG_CC_V, | |
3033 | QREG_CC_C, QREG_CC_X); | |
3034 | ||
3035 | /* M68000 sets V if the most significant bit is changed at | |
3036 | * any time during the shift operation. Do this via creating | |
3037 | * an extension of the sign bit, comparing, and discarding | |
3038 | * the bits below the sign bit. I.e. | |
3039 | * int64_t s = (intN_t)reg; | |
3040 | * int64_t t = (int64_t)(intN_t)reg << count; | |
3041 | * V = ((s ^ t) & (-1 << (bits - 1))) != 0 | |
3042 | */ | |
3043 | if (!logical && m68k_feature(s->env, M68K_FEATURE_M68000)) { | |
3044 | TCGv_i64 tt = tcg_const_i64(32); | |
3045 | /* if shift is greater than 32, use 32 */ | |
3046 | tcg_gen_movcond_i64(TCG_COND_GT, s64, s64, tt, tt, s64); | |
3047 | tcg_temp_free_i64(tt); | |
3048 | /* Sign extend the input to 64 bits; re-do the shift. */ | |
3049 | tcg_gen_ext_i32_i64(t64, reg); | |
3050 | tcg_gen_shl_i64(s64, t64, s64); | |
3051 | /* Clear all bits that are unchanged. */ | |
3052 | tcg_gen_xor_i64(t64, t64, s64); | |
3053 | /* Ignore the bits below the sign bit. */ | |
3054 | tcg_gen_andi_i64(t64, t64, -1ULL << (bits - 1)); | |
3055 | /* If any bits remain set, we have overflow. */ | |
3056 | tcg_gen_setcondi_i64(TCG_COND_NE, t64, t64, 0); | |
3057 | tcg_gen_extrl_i64_i32(QREG_CC_V, t64); | |
3058 | tcg_gen_neg_i32(QREG_CC_V, QREG_CC_V); | |
3059 | } | |
e6e5906b | 3060 | } else { |
367790cc RH |
3061 | tcg_gen_shli_i64(t64, t64, 32); |
3062 | if (logical) { | |
3063 | tcg_gen_shr_i64(t64, t64, s64); | |
e6e5906b | 3064 | } else { |
367790cc | 3065 | tcg_gen_sar_i64(t64, t64, s64); |
e6e5906b | 3066 | } |
367790cc RH |
3067 | tcg_gen_extr_i64_i32(QREG_CC_C, QREG_CC_N, t64); |
3068 | ||
3069 | /* Note that C=0 if shift count is 0, and we get that for free. */ | |
3070 | tcg_gen_shri_i32(QREG_CC_C, QREG_CC_C, 31); | |
3071 | ||
3072 | /* X = C, but only if the shift count was non-zero. */ | |
3073 | tcg_gen_movcond_i32(TCG_COND_NE, QREG_CC_X, s32, QREG_CC_V, | |
3074 | QREG_CC_C, QREG_CC_X); | |
e6e5906b | 3075 | } |
367790cc RH |
3076 | gen_ext(QREG_CC_N, QREG_CC_N, opsize, 1); |
3077 | tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N); | |
3078 | ||
3079 | tcg_temp_free(s32); | |
3080 | tcg_temp_free_i64(s64); | |
3081 | tcg_temp_free_i64(t64); | |
3082 | ||
3083 | /* Write back the result. */ | |
3084 | gen_partset_reg(opsize, DREG(insn, 0), QREG_CC_N); | |
3085 | set_cc_op(s, CC_OP_FLAGS); | |
3086 | } | |
3087 | ||
3088 | DISAS_INSN(shift8_im) | |
3089 | { | |
3090 | shift_im(s, insn, OS_BYTE); | |
3091 | } | |
3092 | ||
3093 | DISAS_INSN(shift16_im) | |
3094 | { | |
3095 | shift_im(s, insn, OS_WORD); | |
3096 | } | |
3097 | ||
3098 | DISAS_INSN(shift_im) | |
3099 | { | |
3100 | shift_im(s, insn, OS_LONG); | |
3101 | } | |
3102 | ||
3103 | DISAS_INSN(shift8_reg) | |
3104 | { | |
3105 | shift_reg(s, insn, OS_BYTE); | |
3106 | } | |
3107 | ||
3108 | DISAS_INSN(shift16_reg) | |
3109 | { | |
3110 | shift_reg(s, insn, OS_WORD); | |
e6e5906b PB |
3111 | } |
3112 | ||
3113 | DISAS_INSN(shift_reg) | |
3114 | { | |
367790cc RH |
3115 | shift_reg(s, insn, OS_LONG); |
3116 | } | |
e6e5906b | 3117 | |
367790cc RH |
3118 | DISAS_INSN(shift_mem) |
3119 | { | |
3120 | int logical = insn & 8; | |
3121 | int left = insn & 0x100; | |
3122 | TCGv src; | |
3123 | TCGv addr; | |
3124 | ||
3125 | SRC_EA(env, src, OS_WORD, !logical, &addr); | |
3126 | tcg_gen_movi_i32(QREG_CC_V, 0); | |
3127 | if (left) { | |
3128 | tcg_gen_shri_i32(QREG_CC_C, src, 15); | |
3129 | tcg_gen_shli_i32(QREG_CC_N, src, 1); | |
3130 | ||
3131 | /* Note that ColdFire always clears V, | |
3132 | while M68000 sets if the most significant bit is changed at | |
3133 | any time during the shift operation */ | |
3134 | if (!logical && m68k_feature(s->env, M68K_FEATURE_M68000)) { | |
3135 | src = gen_extend(src, OS_WORD, 1); | |
3136 | tcg_gen_xor_i32(QREG_CC_V, QREG_CC_N, src); | |
3137 | } | |
e6e5906b | 3138 | } else { |
367790cc RH |
3139 | tcg_gen_mov_i32(QREG_CC_C, src); |
3140 | if (logical) { | |
3141 | tcg_gen_shri_i32(QREG_CC_N, src, 1); | |
e6e5906b | 3142 | } else { |
367790cc | 3143 | tcg_gen_sari_i32(QREG_CC_N, src, 1); |
e6e5906b PB |
3144 | } |
3145 | } | |
367790cc RH |
3146 | |
3147 | gen_ext(QREG_CC_N, QREG_CC_N, OS_WORD, 1); | |
3148 | tcg_gen_andi_i32(QREG_CC_C, QREG_CC_C, 1); | |
3149 | tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N); | |
3150 | tcg_gen_mov_i32(QREG_CC_X, QREG_CC_C); | |
3151 | ||
3152 | DEST_EA(env, insn, OS_WORD, QREG_CC_N, &addr); | |
620c6cf6 | 3153 | set_cc_op(s, CC_OP_FLAGS); |
e6e5906b PB |
3154 | } |
3155 | ||
0194cf31 LV |
3156 | static void rotate(TCGv reg, TCGv shift, int left, int size) |
3157 | { | |
3158 | switch (size) { | |
3159 | case 8: | |
3160 | /* Replicate the 8-bit input so that a 32-bit rotate works. */ | |
3161 | tcg_gen_ext8u_i32(reg, reg); | |
3162 | tcg_gen_muli_i32(reg, reg, 0x01010101); | |
3163 | goto do_long; | |
3164 | case 16: | |
3165 | /* Replicate the 16-bit input so that a 32-bit rotate works. */ | |
3166 | tcg_gen_deposit_i32(reg, reg, reg, 16, 16); | |
3167 | goto do_long; | |
3168 | do_long: | |
3169 | default: | |
3170 | if (left) { | |
3171 | tcg_gen_rotl_i32(reg, reg, shift); | |
3172 | } else { | |
3173 | tcg_gen_rotr_i32(reg, reg, shift); | |
3174 | } | |
3175 | } | |
3176 | ||
3177 | /* compute flags */ | |
3178 | ||
3179 | switch (size) { | |
3180 | case 8: | |
3181 | tcg_gen_ext8s_i32(reg, reg); | |
3182 | break; | |
3183 | case 16: | |
3184 | tcg_gen_ext16s_i32(reg, reg); | |
3185 | break; | |
3186 | default: | |
3187 | break; | |
3188 | } | |
3189 | ||
3190 | /* QREG_CC_X is not affected */ | |
3191 | ||
3192 | tcg_gen_mov_i32(QREG_CC_N, reg); | |
3193 | tcg_gen_mov_i32(QREG_CC_Z, reg); | |
3194 | ||
3195 | if (left) { | |
3196 | tcg_gen_andi_i32(QREG_CC_C, reg, 1); | |
3197 | } else { | |
3198 | tcg_gen_shri_i32(QREG_CC_C, reg, 31); | |
3199 | } | |
3200 | ||
3201 | tcg_gen_movi_i32(QREG_CC_V, 0); /* always cleared */ | |
3202 | } | |
3203 | ||
3204 | static void rotate_x_flags(TCGv reg, TCGv X, int size) | |
3205 | { | |
3206 | switch (size) { | |
3207 | case 8: | |
3208 | tcg_gen_ext8s_i32(reg, reg); | |
3209 | break; | |
3210 | case 16: | |
3211 | tcg_gen_ext16s_i32(reg, reg); | |
3212 | break; | |
3213 | default: | |
3214 | break; | |
3215 | } | |
3216 | tcg_gen_mov_i32(QREG_CC_N, reg); | |
3217 | tcg_gen_mov_i32(QREG_CC_Z, reg); | |
3218 | tcg_gen_mov_i32(QREG_CC_X, X); | |
3219 | tcg_gen_mov_i32(QREG_CC_C, X); | |
3220 | tcg_gen_movi_i32(QREG_CC_V, 0); | |
3221 | } | |
3222 | ||
3223 | /* Result of rotate_x() is valid if 0 <= shift <= size */ | |
3224 | static TCGv rotate_x(TCGv reg, TCGv shift, int left, int size) | |
3225 | { | |
3226 | TCGv X, shl, shr, shx, sz, zero; | |
3227 | ||
3228 | sz = tcg_const_i32(size); | |
3229 | ||
3230 | shr = tcg_temp_new(); | |
3231 | shl = tcg_temp_new(); | |
3232 | shx = tcg_temp_new(); | |
3233 | if (left) { | |
3234 | tcg_gen_mov_i32(shl, shift); /* shl = shift */ | |
3235 | tcg_gen_movi_i32(shr, size + 1); | |
3236 | tcg_gen_sub_i32(shr, shr, shift); /* shr = size + 1 - shift */ | |
3237 | tcg_gen_subi_i32(shx, shift, 1); /* shx = shift - 1 */ | |
3238 | /* shx = shx < 0 ? size : shx; */ | |
3239 | zero = tcg_const_i32(0); | |
3240 | tcg_gen_movcond_i32(TCG_COND_LT, shx, shx, zero, sz, shx); | |
3241 | tcg_temp_free(zero); | |
3242 | } else { | |
3243 | tcg_gen_mov_i32(shr, shift); /* shr = shift */ | |
3244 | tcg_gen_movi_i32(shl, size + 1); | |
3245 | tcg_gen_sub_i32(shl, shl, shift); /* shl = size + 1 - shift */ | |
3246 | tcg_gen_sub_i32(shx, sz, shift); /* shx = size - shift */ | |
3247 | } | |
3248 | ||
3249 | /* reg = (reg << shl) | (reg >> shr) | (x << shx); */ | |
3250 | ||
3251 | tcg_gen_shl_i32(shl, reg, shl); | |
3252 | tcg_gen_shr_i32(shr, reg, shr); | |
3253 | tcg_gen_or_i32(reg, shl, shr); | |
3254 | tcg_temp_free(shl); | |
3255 | tcg_temp_free(shr); | |
3256 | tcg_gen_shl_i32(shx, QREG_CC_X, shx); | |
3257 | tcg_gen_or_i32(reg, reg, shx); | |
3258 | tcg_temp_free(shx); | |
3259 | ||
3260 | /* X = (reg >> size) & 1 */ | |
3261 | ||
3262 | X = tcg_temp_new(); | |
3263 | tcg_gen_shr_i32(X, reg, sz); | |
3264 | tcg_gen_andi_i32(X, X, 1); | |
3265 | tcg_temp_free(sz); | |
3266 | ||
3267 | return X; | |
3268 | } | |
3269 | ||
3270 | /* Result of rotate32_x() is valid if 0 <= shift < 33 */ | |
3271 | static TCGv rotate32_x(TCGv reg, TCGv shift, int left) | |
3272 | { | |
3273 | TCGv_i64 t0, shift64; | |
3274 | TCGv X, lo, hi, zero; | |
3275 | ||
3276 | shift64 = tcg_temp_new_i64(); | |
3277 | tcg_gen_extu_i32_i64(shift64, shift); | |
3278 | ||
3279 | t0 = tcg_temp_new_i64(); | |
3280 | ||
3281 | X = tcg_temp_new(); | |
3282 | lo = tcg_temp_new(); | |
3283 | hi = tcg_temp_new(); | |
3284 | ||
3285 | if (left) { | |
3286 | /* create [reg:X:..] */ | |
3287 | ||
3288 | tcg_gen_shli_i32(lo, QREG_CC_X, 31); | |
3289 | tcg_gen_concat_i32_i64(t0, lo, reg); | |
3290 | ||
3291 | /* rotate */ | |
3292 | ||
3293 | tcg_gen_rotl_i64(t0, t0, shift64); | |
3294 | tcg_temp_free_i64(shift64); | |
3295 | ||
3296 | /* result is [reg:..:reg:X] */ | |
3297 | ||
3298 | tcg_gen_extr_i64_i32(lo, hi, t0); | |
3299 | tcg_gen_andi_i32(X, lo, 1); | |
3300 | ||
3301 | tcg_gen_shri_i32(lo, lo, 1); | |
3302 | } else { | |
3303 | /* create [..:X:reg] */ | |
3304 | ||
3305 | tcg_gen_concat_i32_i64(t0, reg, QREG_CC_X); | |
3306 | ||
3307 | tcg_gen_rotr_i64(t0, t0, shift64); | |
3308 | tcg_temp_free_i64(shift64); | |
3309 | ||
3310 | /* result is value: [X:reg:..:reg] */ | |
3311 | ||
3312 | tcg_gen_extr_i64_i32(lo, hi, t0); | |
3313 | ||
3314 | /* extract X */ | |
3315 | ||
3316 | tcg_gen_shri_i32(X, hi, 31); | |
3317 | ||
3318 | /* extract result */ | |
3319 | ||
3320 | tcg_gen_shli_i32(hi, hi, 1); | |
3321 | } | |
3322 | tcg_temp_free_i64(t0); | |
3323 | tcg_gen_or_i32(lo, lo, hi); | |
3324 | tcg_temp_free(hi); | |
3325 | ||
3326 | /* if shift == 0, register and X are not affected */ | |
3327 | ||
3328 | zero = tcg_const_i32(0); | |
3329 | tcg_gen_movcond_i32(TCG_COND_EQ, X, shift, zero, QREG_CC_X, X); | |
3330 | tcg_gen_movcond_i32(TCG_COND_EQ, reg, shift, zero, reg, lo); | |
3331 | tcg_temp_free(zero); | |
3332 | tcg_temp_free(lo); | |
3333 | ||
3334 | return X; | |
3335 | } | |
3336 | ||
3337 | DISAS_INSN(rotate_im) | |
3338 | { | |
3339 | TCGv shift; | |
3340 | int tmp; | |
3341 | int left = (insn & 0x100); | |
3342 | ||
3343 | tmp = (insn >> 9) & 7; | |
3344 | if (tmp == 0) { | |
3345 | tmp = 8; | |
3346 | } | |
3347 | ||
3348 | shift = tcg_const_i32(tmp); | |
3349 | if (insn & 8) { | |
3350 | rotate(DREG(insn, 0), shift, left, 32); | |
3351 | } else { | |
3352 | TCGv X = rotate32_x(DREG(insn, 0), shift, left); | |
3353 | rotate_x_flags(DREG(insn, 0), X, 32); | |
3354 | tcg_temp_free(X); | |
3355 | } | |
3356 | tcg_temp_free(shift); | |
3357 | ||
3358 | set_cc_op(s, CC_OP_FLAGS); | |
3359 | } | |
3360 | ||
3361 | DISAS_INSN(rotate8_im) | |
3362 | { | |
3363 | int left = (insn & 0x100); | |
3364 | TCGv reg; | |
3365 | TCGv shift; | |
3366 | int tmp; | |
3367 | ||
3368 | reg = gen_extend(DREG(insn, 0), OS_BYTE, 0); | |
3369 | ||
3370 | tmp = (insn >> 9) & 7; | |
3371 | if (tmp == 0) { | |
3372 | tmp = 8; | |
3373 | } | |
3374 | ||
3375 | shift = tcg_const_i32(tmp); | |
3376 | if (insn & 8) { | |
3377 | rotate(reg, shift, left, 8); | |
3378 | } else { | |
3379 | TCGv X = rotate_x(reg, shift, left, 8); | |
3380 | rotate_x_flags(reg, X, 8); | |
3381 | tcg_temp_free(X); | |
3382 | } | |
3383 | tcg_temp_free(shift); | |
3384 | gen_partset_reg(OS_BYTE, DREG(insn, 0), reg); | |
3385 | set_cc_op(s, CC_OP_FLAGS); | |
3386 | } | |
3387 | ||
3388 | DISAS_INSN(rotate16_im) | |
3389 | { | |
3390 | int left = (insn & 0x100); | |
3391 | TCGv reg; | |
3392 | TCGv shift; | |
3393 | int tmp; | |
3394 | ||
3395 | reg = gen_extend(DREG(insn, 0), OS_WORD, 0); | |
3396 | tmp = (insn >> 9) & 7; | |
3397 | if (tmp == 0) { | |
3398 | tmp = 8; | |
3399 | } | |
3400 | ||
3401 | shift = tcg_const_i32(tmp); | |
3402 | if (insn & 8) { | |
3403 | rotate(reg, shift, left, 16); | |
3404 | } else { | |
3405 | TCGv X = rotate_x(reg, shift, left, 16); | |
3406 | rotate_x_flags(reg, X, 16); | |
3407 | tcg_temp_free(X); | |
3408 | } | |
3409 | tcg_temp_free(shift); | |
3410 | gen_partset_reg(OS_WORD, DREG(insn, 0), reg); | |
3411 | set_cc_op(s, CC_OP_FLAGS); | |
3412 | } | |
3413 | ||
3414 | DISAS_INSN(rotate_reg) | |
3415 | { | |
3416 | TCGv reg; | |
3417 | TCGv src; | |
3418 | TCGv t0, t1; | |
3419 | int left = (insn & 0x100); | |
3420 | ||
3421 | reg = DREG(insn, 0); | |
3422 | src = DREG(insn, 9); | |
3423 | /* shift in [0..63] */ | |
3424 | t0 = tcg_temp_new(); | |
3425 | tcg_gen_andi_i32(t0, src, 63); | |
3426 | t1 = tcg_temp_new_i32(); | |
3427 | if (insn & 8) { | |
3428 | tcg_gen_andi_i32(t1, src, 31); | |
3429 | rotate(reg, t1, left, 32); | |
3430 | /* if shift == 0, clear C */ | |
3431 | tcg_gen_movcond_i32(TCG_COND_EQ, QREG_CC_C, | |
3432 | t0, QREG_CC_V /* 0 */, | |
3433 | QREG_CC_V /* 0 */, QREG_CC_C); | |
3434 | } else { | |
3435 | TCGv X; | |
3436 | /* modulo 33 */ | |
3437 | tcg_gen_movi_i32(t1, 33); | |
3438 | tcg_gen_remu_i32(t1, t0, t1); | |
3439 | X = rotate32_x(DREG(insn, 0), t1, left); | |
3440 | rotate_x_flags(DREG(insn, 0), X, 32); | |
3441 | tcg_temp_free(X); | |
3442 | } | |
3443 | tcg_temp_free(t1); | |
3444 | tcg_temp_free(t0); | |
3445 | set_cc_op(s, CC_OP_FLAGS); | |
3446 | } | |
3447 | ||
3448 | DISAS_INSN(rotate8_reg) | |
3449 | { | |
3450 | TCGv reg; | |
3451 | TCGv src; | |
3452 | TCGv t0, t1; | |
3453 | int left = (insn & 0x100); | |
3454 | ||
3455 | reg = gen_extend(DREG(insn, 0), OS_BYTE, 0); | |
3456 | src = DREG(insn, 9); | |
3457 | /* shift in [0..63] */ | |
3458 | t0 = tcg_temp_new_i32(); | |
3459 | tcg_gen_andi_i32(t0, src, 63); | |
3460 | t1 = tcg_temp_new_i32(); | |
3461 | if (insn & 8) { | |
3462 | tcg_gen_andi_i32(t1, src, 7); | |
3463 | rotate(reg, t1, left, 8); | |
3464 | /* if shift == 0, clear C */ | |
3465 | tcg_gen_movcond_i32(TCG_COND_EQ, QREG_CC_C, | |
3466 | t0, QREG_CC_V /* 0 */, | |
3467 | QREG_CC_V /* 0 */, QREG_CC_C); | |
3468 | } else { | |
3469 | TCGv X; | |
3470 | /* modulo 9 */ | |
3471 | tcg_gen_movi_i32(t1, 9); | |
3472 | tcg_gen_remu_i32(t1, t0, t1); | |
3473 | X = rotate_x(reg, t1, left, 8); | |
3474 | rotate_x_flags(reg, X, 8); | |
3475 | tcg_temp_free(X); | |
3476 | } | |
3477 | tcg_temp_free(t1); | |
3478 | tcg_temp_free(t0); | |
3479 | gen_partset_reg(OS_BYTE, DREG(insn, 0), reg); | |
3480 | set_cc_op(s, CC_OP_FLAGS); | |
3481 | } | |
3482 | ||
3483 | DISAS_INSN(rotate16_reg) | |
3484 | { | |
3485 | TCGv reg; | |
3486 | TCGv src; | |
3487 | TCGv t0, t1; | |
3488 | int left = (insn & 0x100); | |
3489 | ||
3490 | reg = gen_extend(DREG(insn, 0), OS_WORD, 0); | |
3491 | src = DREG(insn, 9); | |
3492 | /* shift in [0..63] */ | |
3493 | t0 = tcg_temp_new_i32(); | |
3494 | tcg_gen_andi_i32(t0, src, 63); | |
3495 | t1 = tcg_temp_new_i32(); | |
3496 | if (insn & 8) { | |
3497 | tcg_gen_andi_i32(t1, src, 15); | |
3498 | rotate(reg, t1, left, 16); | |
3499 | /* if shift == 0, clear C */ | |
3500 | tcg_gen_movcond_i32(TCG_COND_EQ, QREG_CC_C, | |
3501 | t0, QREG_CC_V /* 0 */, | |
3502 | QREG_CC_V /* 0 */, QREG_CC_C); | |
3503 | } else { | |
3504 | TCGv X; | |
3505 | /* modulo 17 */ | |
3506 | tcg_gen_movi_i32(t1, 17); | |
3507 | tcg_gen_remu_i32(t1, t0, t1); | |
3508 | X = rotate_x(reg, t1, left, 16); | |
3509 | rotate_x_flags(reg, X, 16); | |
3510 | tcg_temp_free(X); | |
3511 | } | |
3512 | tcg_temp_free(t1); | |
3513 | tcg_temp_free(t0); | |
3514 | gen_partset_reg(OS_WORD, DREG(insn, 0), reg); | |
3515 | set_cc_op(s, CC_OP_FLAGS); | |
3516 | } | |
3517 | ||
3518 | DISAS_INSN(rotate_mem) | |
3519 | { | |
3520 | TCGv src; | |
3521 | TCGv addr; | |
3522 | TCGv shift; | |
3523 | int left = (insn & 0x100); | |
3524 | ||
3525 | SRC_EA(env, src, OS_WORD, 0, &addr); | |
3526 | ||
3527 | shift = tcg_const_i32(1); | |
3528 | if (insn & 0x0200) { | |
3529 | rotate(src, shift, left, 16); | |
3530 | } else { | |
3531 | TCGv X = rotate_x(src, shift, left, 16); | |
3532 | rotate_x_flags(src, X, 16); | |
3533 | tcg_temp_free(X); | |
3534 | } | |
3535 | tcg_temp_free(shift); | |
3536 | DEST_EA(env, insn, OS_WORD, src, &addr); | |
3537 | set_cc_op(s, CC_OP_FLAGS); | |
3538 | } | |
3539 | ||
ac815f46 RH |
3540 | DISAS_INSN(bfext_reg) |
3541 | { | |
3542 | int ext = read_im16(env, s); | |
3543 | int is_sign = insn & 0x200; | |
3544 | TCGv src = DREG(insn, 0); | |
3545 | TCGv dst = DREG(ext, 12); | |
3546 | int len = ((extract32(ext, 0, 5) - 1) & 31) + 1; | |
3547 | int ofs = extract32(ext, 6, 5); /* big bit-endian */ | |
3548 | int pos = 32 - ofs - len; /* little bit-endian */ | |
3549 | TCGv tmp = tcg_temp_new(); | |
3550 | TCGv shift; | |
3551 | ||
3552 | /* In general, we're going to rotate the field so that it's at the | |
3553 | top of the word and then right-shift by the compliment of the | |
3554 | width to extend the field. */ | |
3555 | if (ext & 0x20) { | |
3556 | /* Variable width. */ | |
3557 | if (ext & 0x800) { | |
3558 | /* Variable offset. */ | |
3559 | tcg_gen_andi_i32(tmp, DREG(ext, 6), 31); | |
3560 | tcg_gen_rotl_i32(tmp, src, tmp); | |
3561 | } else { | |
3562 | tcg_gen_rotli_i32(tmp, src, ofs); | |
3563 | } | |
3564 | ||
3565 | shift = tcg_temp_new(); | |
3566 | tcg_gen_neg_i32(shift, DREG(ext, 0)); | |
3567 | tcg_gen_andi_i32(shift, shift, 31); | |
3568 | tcg_gen_sar_i32(QREG_CC_N, tmp, shift); | |
3569 | if (is_sign) { | |
3570 | tcg_gen_mov_i32(dst, QREG_CC_N); | |
3571 | } else { | |
3572 | tcg_gen_shr_i32(dst, tmp, shift); | |
3573 | } | |
3574 | tcg_temp_free(shift); | |
3575 | } else { | |
3576 | /* Immediate width. */ | |
3577 | if (ext & 0x800) { | |
3578 | /* Variable offset */ | |
3579 | tcg_gen_andi_i32(tmp, DREG(ext, 6), 31); | |
3580 | tcg_gen_rotl_i32(tmp, src, tmp); | |
3581 | src = tmp; | |
3582 | pos = 32 - len; | |
3583 | } else { | |
3584 | /* Immediate offset. If the field doesn't wrap around the | |
3585 | end of the word, rely on (s)extract completely. */ | |
3586 | if (pos < 0) { | |
3587 | tcg_gen_rotli_i32(tmp, src, ofs); | |
3588 | src = tmp; | |
3589 | pos = 32 - len; | |
3590 | } | |
3591 | } | |
3592 | ||
3593 | tcg_gen_sextract_i32(QREG_CC_N, src, pos, len); | |
3594 | if (is_sign) { | |
3595 | tcg_gen_mov_i32(dst, QREG_CC_N); | |
3596 | } else { | |
3597 | tcg_gen_extract_i32(dst, src, pos, len); | |
3598 | } | |
3599 | } | |
3600 | ||
3601 | tcg_temp_free(tmp); | |
3602 | set_cc_op(s, CC_OP_LOGIC); | |
3603 | } | |
3604 | ||
f2224f2c RH |
3605 | DISAS_INSN(bfext_mem) |
3606 | { | |
3607 | int ext = read_im16(env, s); | |
3608 | int is_sign = insn & 0x200; | |
3609 | TCGv dest = DREG(ext, 12); | |
3610 | TCGv addr, len, ofs; | |
3611 | ||
3612 | addr = gen_lea(env, s, insn, OS_UNSIZED); | |
3613 | if (IS_NULL_QREG(addr)) { | |
3614 | gen_addr_fault(s); | |
3615 | return; | |
3616 | } | |
3617 | ||
3618 | if (ext & 0x20) { | |
3619 | len = DREG(ext, 0); | |
3620 | } else { | |
3621 | len = tcg_const_i32(extract32(ext, 0, 5)); | |
3622 | } | |
3623 | if (ext & 0x800) { | |
3624 | ofs = DREG(ext, 6); | |
3625 | } else { | |
3626 | ofs = tcg_const_i32(extract32(ext, 6, 5)); | |
3627 | } | |
3628 | ||
3629 | if (is_sign) { | |
3630 | gen_helper_bfexts_mem(dest, cpu_env, addr, ofs, len); | |
3631 | tcg_gen_mov_i32(QREG_CC_N, dest); | |
3632 | } else { | |
3633 | TCGv_i64 tmp = tcg_temp_new_i64(); | |
3634 | gen_helper_bfextu_mem(tmp, cpu_env, addr, ofs, len); | |
3635 | tcg_gen_extr_i64_i32(dest, QREG_CC_N, tmp); | |
3636 | tcg_temp_free_i64(tmp); | |
3637 | } | |
3638 | set_cc_op(s, CC_OP_LOGIC); | |
3639 | ||
3640 | if (!(ext & 0x20)) { | |
3641 | tcg_temp_free(len); | |
3642 | } | |
3643 | if (!(ext & 0x800)) { | |
3644 | tcg_temp_free(ofs); | |
3645 | } | |
3646 | } | |
3647 | ||
ac815f46 RH |
3648 | DISAS_INSN(bfop_reg) |
3649 | { | |
3650 | int ext = read_im16(env, s); | |
3651 | TCGv src = DREG(insn, 0); | |
3652 | int len = ((extract32(ext, 0, 5) - 1) & 31) + 1; | |
3653 | int ofs = extract32(ext, 6, 5); /* big bit-endian */ | |
a45f1763 RH |
3654 | TCGv mask, tofs, tlen; |
3655 | ||
3656 | TCGV_UNUSED(tofs); | |
3657 | TCGV_UNUSED(tlen); | |
3658 | if ((insn & 0x0f00) == 0x0d00) { /* bfffo */ | |
3659 | tofs = tcg_temp_new(); | |
3660 | tlen = tcg_temp_new(); | |
3661 | } | |
ac815f46 RH |
3662 | |
3663 | if ((ext & 0x820) == 0) { | |
3664 | /* Immediate width and offset. */ | |
3665 | uint32_t maski = 0x7fffffffu >> (len - 1); | |
3666 | if (ofs + len <= 32) { | |
3667 | tcg_gen_shli_i32(QREG_CC_N, src, ofs); | |
3668 | } else { | |
3669 | tcg_gen_rotli_i32(QREG_CC_N, src, ofs); | |
3670 | } | |
3671 | tcg_gen_andi_i32(QREG_CC_N, QREG_CC_N, ~maski); | |
3672 | mask = tcg_const_i32(ror32(maski, ofs)); | |
a45f1763 RH |
3673 | if (!TCGV_IS_UNUSED(tofs)) { |
3674 | tcg_gen_movi_i32(tofs, ofs); | |
3675 | tcg_gen_movi_i32(tlen, len); | |
3676 | } | |
ac815f46 RH |
3677 | } else { |
3678 | TCGv tmp = tcg_temp_new(); | |
3679 | if (ext & 0x20) { | |
3680 | /* Variable width */ | |
3681 | tcg_gen_subi_i32(tmp, DREG(ext, 0), 1); | |
3682 | tcg_gen_andi_i32(tmp, tmp, 31); | |
3683 | mask = tcg_const_i32(0x7fffffffu); | |
3684 | tcg_gen_shr_i32(mask, mask, tmp); | |
a45f1763 RH |
3685 | if (!TCGV_IS_UNUSED(tlen)) { |
3686 | tcg_gen_addi_i32(tlen, tmp, 1); | |
3687 | } | |
ac815f46 RH |
3688 | } else { |
3689 | /* Immediate width */ | |
3690 | mask = tcg_const_i32(0x7fffffffu >> (len - 1)); | |
a45f1763 RH |
3691 | if (!TCGV_IS_UNUSED(tlen)) { |
3692 | tcg_gen_movi_i32(tlen, len); | |
3693 | } | |
ac815f46 RH |
3694 | } |
3695 | if (ext & 0x800) { | |
3696 | /* Variable offset */ | |
3697 | tcg_gen_andi_i32(tmp, DREG(ext, 6), 31); | |
3698 | tcg_gen_rotl_i32(QREG_CC_N, src, tmp); | |
3699 | tcg_gen_andc_i32(QREG_CC_N, QREG_CC_N, mask); | |
3700 | tcg_gen_rotr_i32(mask, mask, tmp); | |
a45f1763 RH |
3701 | if (!TCGV_IS_UNUSED(tofs)) { |
3702 | tcg_gen_mov_i32(tofs, tmp); | |
3703 | } | |
ac815f46 RH |
3704 | } else { |
3705 | /* Immediate offset (and variable width) */ | |
3706 | tcg_gen_rotli_i32(QREG_CC_N, src, ofs); | |
3707 | tcg_gen_andc_i32(QREG_CC_N, QREG_CC_N, mask); | |
3708 | tcg_gen_rotri_i32(mask, mask, ofs); | |
a45f1763 RH |
3709 | if (!TCGV_IS_UNUSED(tofs)) { |
3710 | tcg_gen_movi_i32(tofs, ofs); | |
3711 | } | |
ac815f46 RH |
3712 | } |
3713 | tcg_temp_free(tmp); | |
3714 | } | |
3715 | set_cc_op(s, CC_OP_LOGIC); | |
3716 | ||
3717 | switch (insn & 0x0f00) { | |
3718 | case 0x0a00: /* bfchg */ | |
3719 | tcg_gen_eqv_i32(src, src, mask); | |
3720 | break; | |
3721 | case 0x0c00: /* bfclr */ | |
3722 | tcg_gen_and_i32(src, src, mask); | |
3723 | break; | |
a45f1763 RH |
3724 | case 0x0d00: /* bfffo */ |
3725 | gen_helper_bfffo_reg(DREG(ext, 12), QREG_CC_N, tofs, tlen); | |
3726 | tcg_temp_free(tlen); | |
3727 | tcg_temp_free(tofs); | |
3728 | break; | |
ac815f46 RH |
3729 | case 0x0e00: /* bfset */ |
3730 | tcg_gen_orc_i32(src, src, mask); | |
3731 | break; | |
3732 | case 0x0800: /* bftst */ | |
3733 | /* flags already set; no other work to do. */ | |
3734 | break; | |
3735 | default: | |
3736 | g_assert_not_reached(); | |
3737 | } | |
3738 | tcg_temp_free(mask); | |
3739 | } | |
3740 | ||
f2224f2c RH |
3741 | DISAS_INSN(bfop_mem) |
3742 | { | |
3743 | int ext = read_im16(env, s); | |
3744 | TCGv addr, len, ofs; | |
a45f1763 | 3745 | TCGv_i64 t64; |
f2224f2c RH |
3746 | |
3747 | addr = gen_lea(env, s, insn, OS_UNSIZED); | |
3748 | if (IS_NULL_QREG(addr)) { | |
3749 | gen_addr_fault(s); | |
3750 | return; | |
3751 | } | |
3752 | ||
3753 | if (ext & 0x20) { | |
3754 | len = DREG(ext, 0); | |
3755 | } else { | |
3756 | len = tcg_const_i32(extract32(ext, 0, 5)); | |
3757 | } | |
3758 | if (ext & 0x800) { | |
3759 | ofs = DREG(ext, 6); | |
3760 | } else { | |
3761 | ofs = tcg_const_i32(extract32(ext, 6, 5)); | |
3762 | } | |
3763 | ||
3764 | switch (insn & 0x0f00) { | |
3765 | case 0x0a00: /* bfchg */ | |
3766 | gen_helper_bfchg_mem(QREG_CC_N, cpu_env, addr, ofs, len); | |
3767 | break; | |
3768 | case 0x0c00: /* bfclr */ | |
3769 | gen_helper_bfclr_mem(QREG_CC_N, cpu_env, addr, ofs, len); | |
3770 | break; | |
a45f1763 RH |
3771 | case 0x0d00: /* bfffo */ |
3772 | t64 = tcg_temp_new_i64(); | |
3773 | gen_helper_bfffo_mem(t64, cpu_env, addr, ofs, len); | |
3774 | tcg_gen_extr_i64_i32(DREG(ext, 12), QREG_CC_N, t64); | |
3775 | tcg_temp_free_i64(t64); | |
3776 | break; | |
f2224f2c RH |
3777 | case 0x0e00: /* bfset */ |
3778 | gen_helper_bfset_mem(QREG_CC_N, cpu_env, addr, ofs, len); | |
3779 | break; | |
3780 | case 0x0800: /* bftst */ | |
3781 | gen_helper_bfexts_mem(QREG_CC_N, cpu_env, addr, ofs, len); | |
3782 | break; | |
3783 | default: | |
3784 | g_assert_not_reached(); | |
3785 | } | |
3786 | set_cc_op(s, CC_OP_LOGIC); | |
3787 | ||
3788 | if (!(ext & 0x20)) { | |
3789 | tcg_temp_free(len); | |
3790 | } | |
3791 | if (!(ext & 0x800)) { | |
3792 | tcg_temp_free(ofs); | |
3793 | } | |
3794 | } | |
3795 | ||
ac815f46 RH |
3796 | DISAS_INSN(bfins_reg) |
3797 | { | |
3798 | int ext = read_im16(env, s); | |
3799 | TCGv dst = DREG(insn, 0); | |
3800 | TCGv src = DREG(ext, 12); | |
3801 | int len = ((extract32(ext, 0, 5) - 1) & 31) + 1; | |
3802 | int ofs = extract32(ext, 6, 5); /* big bit-endian */ | |
3803 | int pos = 32 - ofs - len; /* little bit-endian */ | |
3804 | TCGv tmp; | |
3805 | ||
3806 | tmp = tcg_temp_new(); | |
3807 | ||
3808 | if (ext & 0x20) { | |
3809 | /* Variable width */ | |
3810 | tcg_gen_neg_i32(tmp, DREG(ext, 0)); | |
3811 | tcg_gen_andi_i32(tmp, tmp, 31); | |
3812 | tcg_gen_shl_i32(QREG_CC_N, src, tmp); | |
3813 | } else { | |
3814 | /* Immediate width */ | |
3815 | tcg_gen_shli_i32(QREG_CC_N, src, 32 - len); | |
3816 | } | |
3817 | set_cc_op(s, CC_OP_LOGIC); | |
3818 | ||
3819 | /* Immediate width and offset */ | |
3820 | if ((ext & 0x820) == 0) { | |
3821 | /* Check for suitability for deposit. */ | |
3822 | if (pos >= 0) { | |
3823 | tcg_gen_deposit_i32(dst, dst, src, pos, len); | |
3824 | } else { | |
3825 | uint32_t maski = -2U << (len - 1); | |
3826 | uint32_t roti = (ofs + len) & 31; | |
3827 | tcg_gen_andi_i32(tmp, src, ~maski); | |
3828 | tcg_gen_rotri_i32(tmp, tmp, roti); | |
3829 | tcg_gen_andi_i32(dst, dst, ror32(maski, roti)); | |
3830 | tcg_gen_or_i32(dst, dst, tmp); | |
3831 | } | |
3832 | } else { | |
3833 | TCGv mask = tcg_temp_new(); | |
3834 | TCGv rot = tcg_temp_new(); | |
3835 | ||
3836 | if (ext & 0x20) { | |
3837 | /* Variable width */ | |
3838 | tcg_gen_subi_i32(rot, DREG(ext, 0), 1); | |
3839 | tcg_gen_andi_i32(rot, rot, 31); | |
3840 | tcg_gen_movi_i32(mask, -2); | |
3841 | tcg_gen_shl_i32(mask, mask, rot); | |
3842 | tcg_gen_mov_i32(rot, DREG(ext, 0)); | |
3843 | tcg_gen_andc_i32(tmp, src, mask); | |
3844 | } else { | |
3845 | /* Immediate width (variable offset) */ | |
3846 | uint32_t maski = -2U << (len - 1); | |
3847 | tcg_gen_andi_i32(tmp, src, ~maski); | |
3848 | tcg_gen_movi_i32(mask, maski); | |
3849 | tcg_gen_movi_i32(rot, len & 31); | |
3850 | } | |
3851 | if (ext & 0x800) { | |
3852 | /* Variable offset */ | |
3853 | tcg_gen_add_i32(rot, rot, DREG(ext, 6)); | |
3854 | } else { | |
3855 | /* Immediate offset (variable width) */ | |
3856 | tcg_gen_addi_i32(rot, rot, ofs); | |
3857 | } | |
3858 | tcg_gen_andi_i32(rot, rot, 31); | |
3859 | tcg_gen_rotr_i32(mask, mask, rot); | |
3860 | tcg_gen_rotr_i32(tmp, tmp, rot); | |
3861 | tcg_gen_and_i32(dst, dst, mask); | |
3862 | tcg_gen_or_i32(dst, dst, tmp); | |
3863 | ||
3864 | tcg_temp_free(rot); | |
3865 | tcg_temp_free(mask); | |
3866 | } | |
3867 | tcg_temp_free(tmp); | |
3868 | } | |
3869 | ||
f2224f2c RH |
3870 | DISAS_INSN(bfins_mem) |
3871 | { | |
3872 | int ext = read_im16(env, s); | |
3873 | TCGv src = DREG(ext, 12); | |
3874 | TCGv addr, len, ofs; | |
3875 | ||
3876 | addr = gen_lea(env, s, insn, OS_UNSIZED); | |
3877 | if (IS_NULL_QREG(addr)) { | |
3878 | gen_addr_fault(s); | |
3879 | return; | |
3880 | } | |
3881 | ||
3882 | if (ext & 0x20) { | |
3883 | len = DREG(ext, 0); | |
3884 | } else { | |
3885 | len = tcg_const_i32(extract32(ext, 0, 5)); | |
3886 | } | |
3887 | if (ext & 0x800) { | |
3888 | ofs = DREG(ext, 6); | |
3889 | } else { | |
3890 | ofs = tcg_const_i32(extract32(ext, 6, 5)); | |
3891 | } | |
3892 | ||
3893 | gen_helper_bfins_mem(QREG_CC_N, cpu_env, addr, src, ofs, len); | |
3894 | set_cc_op(s, CC_OP_LOGIC); | |
3895 | ||
3896 | if (!(ext & 0x20)) { | |
3897 | tcg_temp_free(len); | |
3898 | } | |
3899 | if (!(ext & 0x800)) { | |
3900 | tcg_temp_free(ofs); | |
3901 | } | |
3902 | } | |
3903 | ||
e6e5906b PB |
3904 | DISAS_INSN(ff1) |
3905 | { | |
e1f3808e | 3906 | TCGv reg; |
821f7e76 | 3907 | reg = DREG(insn, 0); |
5dbb6784 | 3908 | gen_logic_cc(s, reg, OS_LONG); |
e1f3808e | 3909 | gen_helper_ff1(reg, reg); |
e6e5906b PB |
3910 | } |
3911 | ||
e1f3808e | 3912 | static TCGv gen_get_sr(DisasContext *s) |
0633879f | 3913 | { |
e1f3808e PB |
3914 | TCGv ccr; |
3915 | TCGv sr; | |
0633879f PB |
3916 | |
3917 | ccr = gen_get_ccr(s); | |
a7812ae4 | 3918 | sr = tcg_temp_new(); |
e1f3808e PB |
3919 | tcg_gen_andi_i32(sr, QREG_SR, 0xffe0); |
3920 | tcg_gen_or_i32(sr, sr, ccr); | |
0633879f PB |
3921 | return sr; |
3922 | } | |
3923 | ||
e6e5906b PB |
3924 | DISAS_INSN(strldsr) |
3925 | { | |
3926 | uint16_t ext; | |
3927 | uint32_t addr; | |
3928 | ||
3929 | addr = s->pc - 2; | |
28b68cd7 | 3930 | ext = read_im16(env, s); |
0633879f | 3931 | if (ext != 0x46FC) { |
e6e5906b | 3932 | gen_exception(s, addr, EXCP_UNSUPPORTED); |
0633879f PB |
3933 | return; |
3934 | } | |
28b68cd7 | 3935 | ext = read_im16(env, s); |
0633879f | 3936 | if (IS_USER(s) || (ext & SR_S) == 0) { |
e6e5906b | 3937 | gen_exception(s, addr, EXCP_PRIVILEGE); |
0633879f PB |
3938 | return; |
3939 | } | |
3940 | gen_push(s, gen_get_sr(s)); | |
3941 | gen_set_sr_im(s, ext, 0); | |
e6e5906b PB |
3942 | } |
3943 | ||
3944 | DISAS_INSN(move_from_sr) | |
3945 | { | |
e1f3808e | 3946 | TCGv sr; |
0633879f | 3947 | |
7c0eb318 | 3948 | if (IS_USER(s) && !m68k_feature(env, M68K_FEATURE_M68000)) { |
0633879f PB |
3949 | gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); |
3950 | return; | |
3951 | } | |
3952 | sr = gen_get_sr(s); | |
7c0eb318 | 3953 | DEST_EA(env, insn, OS_WORD, sr, NULL); |
e6e5906b PB |
3954 | } |
3955 | ||
3956 | DISAS_INSN(move_to_sr) | |
3957 | { | |
0633879f PB |
3958 | if (IS_USER(s)) { |
3959 | gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); | |
3960 | return; | |
3961 | } | |
620c6cf6 | 3962 | gen_set_sr(env, s, insn, 0); |
0633879f | 3963 | gen_lookup_tb(s); |
e6e5906b PB |
3964 | } |
3965 | ||
3966 | DISAS_INSN(move_from_usp) | |
3967 | { | |
0633879f PB |
3968 | if (IS_USER(s)) { |
3969 | gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); | |
3970 | return; | |
3971 | } | |
2a8327e8 GU |
3972 | tcg_gen_ld_i32(AREG(insn, 0), cpu_env, |
3973 | offsetof(CPUM68KState, sp[M68K_USP])); | |
e6e5906b PB |
3974 | } |
3975 | ||
3976 | DISAS_INSN(move_to_usp) | |
3977 | { | |
0633879f PB |
3978 | if (IS_USER(s)) { |
3979 | gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); | |
3980 | return; | |
3981 | } | |
2a8327e8 GU |
3982 | tcg_gen_st_i32(AREG(insn, 0), cpu_env, |
3983 | offsetof(CPUM68KState, sp[M68K_USP])); | |
e6e5906b PB |
3984 | } |
3985 | ||
3986 | DISAS_INSN(halt) | |
3987 | { | |
e1f3808e | 3988 | gen_exception(s, s->pc, EXCP_HALT_INSN); |
e6e5906b PB |
3989 | } |
3990 | ||
3991 | DISAS_INSN(stop) | |
3992 | { | |
0633879f PB |
3993 | uint16_t ext; |
3994 | ||
3995 | if (IS_USER(s)) { | |
3996 | gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); | |
3997 | return; | |
3998 | } | |
3999 | ||
28b68cd7 | 4000 | ext = read_im16(env, s); |
0633879f PB |
4001 | |
4002 | gen_set_sr_im(s, ext, 0); | |
259186a7 | 4003 | tcg_gen_movi_i32(cpu_halted, 1); |
e1f3808e | 4004 | gen_exception(s, s->pc, EXCP_HLT); |
e6e5906b PB |
4005 | } |
4006 | ||
4007 | DISAS_INSN(rte) | |
4008 | { | |
0633879f PB |
4009 | if (IS_USER(s)) { |
4010 | gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); | |
4011 | return; | |
4012 | } | |
4013 | gen_exception(s, s->pc - 2, EXCP_RTE); | |
e6e5906b PB |
4014 | } |
4015 | ||
4016 | DISAS_INSN(movec) | |
4017 | { | |
0633879f | 4018 | uint16_t ext; |
e1f3808e | 4019 | TCGv reg; |
0633879f PB |
4020 | |
4021 | if (IS_USER(s)) { | |
4022 | gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); | |
4023 | return; | |
4024 | } | |
4025 | ||
28b68cd7 | 4026 | ext = read_im16(env, s); |
0633879f PB |
4027 | |
4028 | if (ext & 0x8000) { | |
4029 | reg = AREG(ext, 12); | |
4030 | } else { | |
4031 | reg = DREG(ext, 12); | |
4032 | } | |
e1f3808e | 4033 | gen_helper_movec(cpu_env, tcg_const_i32(ext & 0xfff), reg); |
0633879f | 4034 | gen_lookup_tb(s); |
e6e5906b PB |
4035 | } |
4036 | ||
4037 | DISAS_INSN(intouch) | |
4038 | { | |
0633879f PB |
4039 | if (IS_USER(s)) { |
4040 | gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); | |
4041 | return; | |
4042 | } | |
4043 | /* ICache fetch. Implement as no-op. */ | |
e6e5906b PB |
4044 | } |
4045 | ||
4046 | DISAS_INSN(cpushl) | |
4047 | { | |
0633879f PB |
4048 | if (IS_USER(s)) { |
4049 | gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); | |
4050 | return; | |
4051 | } | |
4052 | /* Cache push/invalidate. Implement as no-op. */ | |
e6e5906b PB |
4053 | } |
4054 | ||
4055 | DISAS_INSN(wddata) | |
4056 | { | |
4057 | gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); | |
4058 | } | |
4059 | ||
4060 | DISAS_INSN(wdebug) | |
4061 | { | |
a47dddd7 AF |
4062 | M68kCPU *cpu = m68k_env_get_cpu(env); |
4063 | ||
0633879f PB |
4064 | if (IS_USER(s)) { |
4065 | gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); | |
4066 | return; | |
4067 | } | |
4068 | /* TODO: Implement wdebug. */ | |
a47dddd7 | 4069 | cpu_abort(CPU(cpu), "WDEBUG not implemented"); |
e6e5906b PB |
4070 | } |
4071 | ||
4072 | DISAS_INSN(trap) | |
4073 | { | |
4074 | gen_exception(s, s->pc - 2, EXCP_TRAP0 + (insn & 0xf)); | |
4075 | } | |
4076 | ||
4077 | /* ??? FP exceptions are not implemented. Most exceptions are deferred until | |
4078 | immediately before the next FP instruction is executed. */ | |
4079 | DISAS_INSN(fpu) | |
4080 | { | |
4081 | uint16_t ext; | |
a7812ae4 | 4082 | int32_t offset; |
e6e5906b | 4083 | int opmode; |
a7812ae4 PB |
4084 | TCGv_i64 src; |
4085 | TCGv_i64 dest; | |
4086 | TCGv_i64 res; | |
4087 | TCGv tmp32; | |
e6e5906b | 4088 | int round; |
a7812ae4 | 4089 | int set_dest; |
e6e5906b PB |
4090 | int opsize; |
4091 | ||
28b68cd7 | 4092 | ext = read_im16(env, s); |
e6e5906b PB |
4093 | opmode = ext & 0x7f; |
4094 | switch ((ext >> 13) & 7) { | |
4095 | case 0: case 2: | |
4096 | break; | |
4097 | case 1: | |
4098 | goto undef; | |
4099 | case 3: /* fmove out */ | |
4100 | src = FREG(ext, 7); | |
a7812ae4 | 4101 | tmp32 = tcg_temp_new_i32(); |
e6e5906b PB |
4102 | /* fmove */ |
4103 | /* ??? TODO: Proper behavior on overflow. */ | |
4104 | switch ((ext >> 10) & 7) { | |
4105 | case 0: | |
4106 | opsize = OS_LONG; | |
a7812ae4 | 4107 | gen_helper_f64_to_i32(tmp32, cpu_env, src); |
e6e5906b PB |
4108 | break; |
4109 | case 1: | |
4110 | opsize = OS_SINGLE; | |
a7812ae4 | 4111 | gen_helper_f64_to_f32(tmp32, cpu_env, src); |
e6e5906b PB |
4112 | break; |
4113 | case 4: | |
4114 | opsize = OS_WORD; | |
a7812ae4 | 4115 | gen_helper_f64_to_i32(tmp32, cpu_env, src); |
e6e5906b | 4116 | break; |
a7812ae4 PB |
4117 | case 5: /* OS_DOUBLE */ |
4118 | tcg_gen_mov_i32(tmp32, AREG(insn, 0)); | |
c59b97aa | 4119 | switch ((insn >> 3) & 7) { |
a7812ae4 PB |
4120 | case 2: |
4121 | case 3: | |
243ee8f7 | 4122 | break; |
a7812ae4 PB |
4123 | case 4: |
4124 | tcg_gen_addi_i32(tmp32, tmp32, -8); | |
4125 | break; | |
4126 | case 5: | |
d4d79bb1 | 4127 | offset = cpu_ldsw_code(env, s->pc); |
a7812ae4 PB |
4128 | s->pc += 2; |
4129 | tcg_gen_addi_i32(tmp32, tmp32, offset); | |
4130 | break; | |
4131 | default: | |
4132 | goto undef; | |
4133 | } | |
4134 | gen_store64(s, tmp32, src); | |
c59b97aa | 4135 | switch ((insn >> 3) & 7) { |
a7812ae4 PB |
4136 | case 3: |
4137 | tcg_gen_addi_i32(tmp32, tmp32, 8); | |
4138 | tcg_gen_mov_i32(AREG(insn, 0), tmp32); | |
4139 | break; | |
4140 | case 4: | |
4141 | tcg_gen_mov_i32(AREG(insn, 0), tmp32); | |
4142 | break; | |
4143 | } | |
4144 | tcg_temp_free_i32(tmp32); | |
4145 | return; | |
e6e5906b PB |
4146 | case 6: |
4147 | opsize = OS_BYTE; | |
a7812ae4 | 4148 | gen_helper_f64_to_i32(tmp32, cpu_env, src); |
e6e5906b PB |
4149 | break; |
4150 | default: | |
4151 | goto undef; | |
4152 | } | |
d4d79bb1 | 4153 | DEST_EA(env, insn, opsize, tmp32, NULL); |
a7812ae4 | 4154 | tcg_temp_free_i32(tmp32); |
e6e5906b PB |
4155 | return; |
4156 | case 4: /* fmove to control register. */ | |
4157 | switch ((ext >> 10) & 7) { | |
4158 | case 4: /* FPCR */ | |
4159 | /* Not implemented. Ignore writes. */ | |
4160 | break; | |
4161 | case 1: /* FPIAR */ | |
4162 | case 2: /* FPSR */ | |
4163 | default: | |
4164 | cpu_abort(NULL, "Unimplemented: fmove to control %d", | |
4165 | (ext >> 10) & 7); | |
4166 | } | |
4167 | break; | |
4168 | case 5: /* fmove from control register. */ | |
4169 | switch ((ext >> 10) & 7) { | |
4170 | case 4: /* FPCR */ | |
4171 | /* Not implemented. Always return zero. */ | |
351326a6 | 4172 | tmp32 = tcg_const_i32(0); |
e6e5906b PB |
4173 | break; |
4174 | case 1: /* FPIAR */ | |
4175 | case 2: /* FPSR */ | |
4176 | default: | |
4177 | cpu_abort(NULL, "Unimplemented: fmove from control %d", | |
4178 | (ext >> 10) & 7); | |
4179 | goto undef; | |
4180 | } | |
d4d79bb1 | 4181 | DEST_EA(env, insn, OS_LONG, tmp32, NULL); |
e6e5906b | 4182 | break; |
5fafdf24 | 4183 | case 6: /* fmovem */ |
e6e5906b PB |
4184 | case 7: |
4185 | { | |
e1f3808e PB |
4186 | TCGv addr; |
4187 | uint16_t mask; | |
4188 | int i; | |
4189 | if ((ext & 0x1f00) != 0x1000 || (ext & 0xff) == 0) | |
4190 | goto undef; | |
d4d79bb1 | 4191 | tmp32 = gen_lea(env, s, insn, OS_LONG); |
a7812ae4 | 4192 | if (IS_NULL_QREG(tmp32)) { |
e1f3808e PB |
4193 | gen_addr_fault(s); |
4194 | return; | |
4195 | } | |
a7812ae4 PB |
4196 | addr = tcg_temp_new_i32(); |
4197 | tcg_gen_mov_i32(addr, tmp32); | |
e1f3808e PB |
4198 | mask = 0x80; |
4199 | for (i = 0; i < 8; i++) { | |
4200 | if (ext & mask) { | |
e1f3808e PB |
4201 | dest = FREG(i, 0); |
4202 | if (ext & (1 << 13)) { | |
4203 | /* store */ | |
4204 | tcg_gen_qemu_stf64(dest, addr, IS_USER(s)); | |
4205 | } else { | |
4206 | /* load */ | |
4207 | tcg_gen_qemu_ldf64(dest, addr, IS_USER(s)); | |
4208 | } | |
4209 | if (ext & (mask - 1)) | |
4210 | tcg_gen_addi_i32(addr, addr, 8); | |
e6e5906b | 4211 | } |
e1f3808e | 4212 | mask >>= 1; |
e6e5906b | 4213 | } |
18307f26 | 4214 | tcg_temp_free_i32(addr); |
e6e5906b PB |
4215 | } |
4216 | return; | |
4217 | } | |
4218 | if (ext & (1 << 14)) { | |
e6e5906b PB |
4219 | /* Source effective address. */ |
4220 | switch ((ext >> 10) & 7) { | |
4221 | case 0: opsize = OS_LONG; break; | |
4222 | case 1: opsize = OS_SINGLE; break; | |
4223 | case 4: opsize = OS_WORD; break; | |
4224 | case 5: opsize = OS_DOUBLE; break; | |
4225 | case 6: opsize = OS_BYTE; break; | |
4226 | default: | |
4227 | goto undef; | |
4228 | } | |
e6e5906b | 4229 | if (opsize == OS_DOUBLE) { |
a7812ae4 PB |
4230 | tmp32 = tcg_temp_new_i32(); |
4231 | tcg_gen_mov_i32(tmp32, AREG(insn, 0)); | |
c59b97aa | 4232 | switch ((insn >> 3) & 7) { |
a7812ae4 PB |
4233 | case 2: |
4234 | case 3: | |
243ee8f7 | 4235 | break; |
a7812ae4 PB |
4236 | case 4: |
4237 | tcg_gen_addi_i32(tmp32, tmp32, -8); | |
4238 | break; | |
4239 | case 5: | |
d4d79bb1 | 4240 | offset = cpu_ldsw_code(env, s->pc); |
a7812ae4 PB |
4241 | s->pc += 2; |
4242 | tcg_gen_addi_i32(tmp32, tmp32, offset); | |
4243 | break; | |
4244 | case 7: | |
d4d79bb1 | 4245 | offset = cpu_ldsw_code(env, s->pc); |
a7812ae4 PB |
4246 | offset += s->pc - 2; |
4247 | s->pc += 2; | |
4248 | tcg_gen_addi_i32(tmp32, tmp32, offset); | |
4249 | break; | |
4250 | default: | |
4251 | goto undef; | |
4252 | } | |
4253 | src = gen_load64(s, tmp32); | |
c59b97aa | 4254 | switch ((insn >> 3) & 7) { |
a7812ae4 PB |
4255 | case 3: |
4256 | tcg_gen_addi_i32(tmp32, tmp32, 8); | |
4257 | tcg_gen_mov_i32(AREG(insn, 0), tmp32); | |
4258 | break; | |
4259 | case 4: | |
4260 | tcg_gen_mov_i32(AREG(insn, 0), tmp32); | |
4261 | break; | |
4262 | } | |
4263 | tcg_temp_free_i32(tmp32); | |
e6e5906b | 4264 | } else { |
d4d79bb1 | 4265 | SRC_EA(env, tmp32, opsize, 1, NULL); |
a7812ae4 | 4266 | src = tcg_temp_new_i64(); |
e6e5906b PB |
4267 | switch (opsize) { |
4268 | case OS_LONG: | |
4269 | case OS_WORD: | |
4270 | case OS_BYTE: | |
a7812ae4 | 4271 | gen_helper_i32_to_f64(src, cpu_env, tmp32); |
e6e5906b PB |
4272 | break; |
4273 | case OS_SINGLE: | |
a7812ae4 | 4274 | gen_helper_f32_to_f64(src, cpu_env, tmp32); |
e6e5906b PB |
4275 | break; |
4276 | } | |
4277 | } | |
4278 | } else { | |
4279 | /* Source register. */ | |
4280 | src = FREG(ext, 10); | |
4281 | } | |
4282 | dest = FREG(ext, 7); | |
a7812ae4 | 4283 | res = tcg_temp_new_i64(); |
e6e5906b | 4284 | if (opmode != 0x3a) |
e1f3808e | 4285 | tcg_gen_mov_f64(res, dest); |
e6e5906b | 4286 | round = 1; |
a7812ae4 | 4287 | set_dest = 1; |
e6e5906b PB |
4288 | switch (opmode) { |
4289 | case 0: case 0x40: case 0x44: /* fmove */ | |
e1f3808e | 4290 | tcg_gen_mov_f64(res, src); |
e6e5906b PB |
4291 | break; |
4292 | case 1: /* fint */ | |
e1f3808e | 4293 | gen_helper_iround_f64(res, cpu_env, src); |
e6e5906b PB |
4294 | round = 0; |
4295 | break; | |
4296 | case 3: /* fintrz */ | |
e1f3808e | 4297 | gen_helper_itrunc_f64(res, cpu_env, src); |
e6e5906b PB |
4298 | round = 0; |
4299 | break; | |
4300 | case 4: case 0x41: case 0x45: /* fsqrt */ | |
e1f3808e | 4301 | gen_helper_sqrt_f64(res, cpu_env, src); |
e6e5906b PB |
4302 | break; |
4303 | case 0x18: case 0x58: case 0x5c: /* fabs */ | |
e1f3808e | 4304 | gen_helper_abs_f64(res, src); |
e6e5906b PB |
4305 | break; |
4306 | case 0x1a: case 0x5a: case 0x5e: /* fneg */ | |
e1f3808e | 4307 | gen_helper_chs_f64(res, src); |
e6e5906b PB |
4308 | break; |
4309 | case 0x20: case 0x60: case 0x64: /* fdiv */ | |
e1f3808e | 4310 | gen_helper_div_f64(res, cpu_env, res, src); |
e6e5906b PB |
4311 | break; |
4312 | case 0x22: case 0x62: case 0x66: /* fadd */ | |
e1f3808e | 4313 | gen_helper_add_f64(res, cpu_env, res, src); |
e6e5906b PB |
4314 | break; |
4315 | case 0x23: case 0x63: case 0x67: /* fmul */ | |
e1f3808e | 4316 | gen_helper_mul_f64(res, cpu_env, res, src); |
e6e5906b PB |
4317 | break; |
4318 | case 0x28: case 0x68: case 0x6c: /* fsub */ | |
e1f3808e | 4319 | gen_helper_sub_f64(res, cpu_env, res, src); |
e6e5906b PB |
4320 | break; |
4321 | case 0x38: /* fcmp */ | |
e1f3808e | 4322 | gen_helper_sub_cmp_f64(res, cpu_env, res, src); |
a7812ae4 | 4323 | set_dest = 0; |
e6e5906b PB |
4324 | round = 0; |
4325 | break; | |
4326 | case 0x3a: /* ftst */ | |
e1f3808e | 4327 | tcg_gen_mov_f64(res, src); |
a7812ae4 | 4328 | set_dest = 0; |
e6e5906b PB |
4329 | round = 0; |
4330 | break; | |
4331 | default: | |
4332 | goto undef; | |
4333 | } | |
a7812ae4 PB |
4334 | if (ext & (1 << 14)) { |
4335 | tcg_temp_free_i64(src); | |
4336 | } | |
e6e5906b PB |
4337 | if (round) { |
4338 | if (opmode & 0x40) { | |
4339 | if ((opmode & 0x4) != 0) | |
4340 | round = 0; | |
4341 | } else if ((s->fpcr & M68K_FPCR_PREC) == 0) { | |
4342 | round = 0; | |
4343 | } | |
4344 | } | |
4345 | if (round) { | |
a7812ae4 | 4346 | TCGv tmp = tcg_temp_new_i32(); |
e1f3808e PB |
4347 | gen_helper_f64_to_f32(tmp, cpu_env, res); |
4348 | gen_helper_f32_to_f64(res, cpu_env, tmp); | |
a7812ae4 | 4349 | tcg_temp_free_i32(tmp); |
5fafdf24 | 4350 | } |
e1f3808e | 4351 | tcg_gen_mov_f64(QREG_FP_RESULT, res); |
a7812ae4 | 4352 | if (set_dest) { |
e1f3808e | 4353 | tcg_gen_mov_f64(dest, res); |
e6e5906b | 4354 | } |
a7812ae4 | 4355 | tcg_temp_free_i64(res); |
e6e5906b PB |
4356 | return; |
4357 | undef: | |
a7812ae4 | 4358 | /* FIXME: Is this right for offset addressing modes? */ |
e6e5906b | 4359 | s->pc -= 2; |
d4d79bb1 | 4360 | disas_undef_fpu(env, s, insn); |
e6e5906b PB |
4361 | } |
4362 | ||
4363 | DISAS_INSN(fbcc) | |
4364 | { | |
4365 | uint32_t offset; | |
4366 | uint32_t addr; | |
e1f3808e | 4367 | TCGv flag; |
42a268c2 | 4368 | TCGLabel *l1; |
e6e5906b PB |
4369 | |
4370 | addr = s->pc; | |
d4d79bb1 | 4371 | offset = cpu_ldsw_code(env, s->pc); |
e6e5906b PB |
4372 | s->pc += 2; |
4373 | if (insn & (1 << 6)) { | |
28b68cd7 | 4374 | offset = (offset << 16) | read_im16(env, s); |
e6e5906b PB |
4375 | } |
4376 | ||
4377 | l1 = gen_new_label(); | |
4378 | /* TODO: Raise BSUN exception. */ | |
a7812ae4 | 4379 | flag = tcg_temp_new(); |
e1f3808e | 4380 | gen_helper_compare_f64(flag, cpu_env, QREG_FP_RESULT); |
e6e5906b PB |
4381 | /* Jump to l1 if condition is true. */ |
4382 | switch (insn & 0xf) { | |
4383 | case 0: /* f */ | |
4384 | break; | |
4385 | case 1: /* eq (=0) */ | |
e1f3808e | 4386 | tcg_gen_brcond_i32(TCG_COND_EQ, flag, tcg_const_i32(0), l1); |
e6e5906b PB |
4387 | break; |
4388 | case 2: /* ogt (=1) */ | |
e1f3808e | 4389 | tcg_gen_brcond_i32(TCG_COND_EQ, flag, tcg_const_i32(1), l1); |
e6e5906b PB |
4390 | break; |
4391 | case 3: /* oge (=0 or =1) */ | |
e1f3808e | 4392 | tcg_gen_brcond_i32(TCG_COND_LEU, flag, tcg_const_i32(1), l1); |
e6e5906b PB |
4393 | break; |
4394 | case 4: /* olt (=-1) */ | |
e1f3808e | 4395 | tcg_gen_brcond_i32(TCG_COND_LT, flag, tcg_const_i32(0), l1); |
e6e5906b PB |
4396 | break; |
4397 | case 5: /* ole (=-1 or =0) */ | |
e1f3808e | 4398 | tcg_gen_brcond_i32(TCG_COND_LE, flag, tcg_const_i32(0), l1); |
e6e5906b PB |
4399 | break; |
4400 | case 6: /* ogl (=-1 or =1) */ | |
e1f3808e PB |
4401 | tcg_gen_andi_i32(flag, flag, 1); |
4402 | tcg_gen_brcond_i32(TCG_COND_NE, flag, tcg_const_i32(0), l1); | |
e6e5906b PB |
4403 | break; |
4404 | case 7: /* or (=2) */ | |
e1f3808e | 4405 | tcg_gen_brcond_i32(TCG_COND_EQ, flag, tcg_const_i32(2), l1); |
e6e5906b PB |
4406 | break; |
4407 | case 8: /* un (<2) */ | |
e1f3808e | 4408 | tcg_gen_brcond_i32(TCG_COND_LT, flag, tcg_const_i32(2), l1); |
e6e5906b PB |
4409 | break; |
4410 | case 9: /* ueq (=0 or =2) */ | |
e1f3808e PB |
4411 | tcg_gen_andi_i32(flag, flag, 1); |
4412 | tcg_gen_brcond_i32(TCG_COND_EQ, flag, tcg_const_i32(0), l1); | |
e6e5906b PB |
4413 | break; |
4414 | case 10: /* ugt (>0) */ | |
e1f3808e | 4415 | tcg_gen_brcond_i32(TCG_COND_GT, flag, tcg_const_i32(0), l1); |
e6e5906b PB |
4416 | break; |
4417 | case 11: /* uge (>=0) */ | |
e1f3808e | 4418 | tcg_gen_brcond_i32(TCG_COND_GE, flag, tcg_const_i32(0), l1); |
e6e5906b PB |
4419 | break; |
4420 | case 12: /* ult (=-1 or =2) */ | |
e1f3808e | 4421 | tcg_gen_brcond_i32(TCG_COND_GEU, flag, tcg_const_i32(2), l1); |
e6e5906b PB |
4422 | break; |
4423 | case 13: /* ule (!=1) */ | |
e1f3808e | 4424 | tcg_gen_brcond_i32(TCG_COND_NE, flag, tcg_const_i32(1), l1); |
e6e5906b PB |
4425 | break; |
4426 | case 14: /* ne (!=0) */ | |
e1f3808e | 4427 | tcg_gen_brcond_i32(TCG_COND_NE, flag, tcg_const_i32(0), l1); |
e6e5906b PB |
4428 | break; |
4429 | case 15: /* t */ | |
e1f3808e | 4430 | tcg_gen_br(l1); |
e6e5906b PB |
4431 | break; |
4432 | } | |
4433 | gen_jmp_tb(s, 0, s->pc); | |
4434 | gen_set_label(l1); | |
4435 | gen_jmp_tb(s, 1, addr + offset); | |
4436 | } | |
4437 | ||
0633879f PB |
4438 | DISAS_INSN(frestore) |
4439 | { | |
a47dddd7 AF |
4440 | M68kCPU *cpu = m68k_env_get_cpu(env); |
4441 | ||
0633879f | 4442 | /* TODO: Implement frestore. */ |
a47dddd7 | 4443 | cpu_abort(CPU(cpu), "FRESTORE not implemented"); |
0633879f PB |
4444 | } |
4445 | ||
4446 | DISAS_INSN(fsave) | |
4447 | { | |
a47dddd7 AF |
4448 | M68kCPU *cpu = m68k_env_get_cpu(env); |
4449 | ||
0633879f | 4450 | /* TODO: Implement fsave. */ |
a47dddd7 | 4451 | cpu_abort(CPU(cpu), "FSAVE not implemented"); |
0633879f PB |
4452 | } |
4453 | ||
e1f3808e | 4454 | static inline TCGv gen_mac_extract_word(DisasContext *s, TCGv val, int upper) |
acf930aa | 4455 | { |
a7812ae4 | 4456 | TCGv tmp = tcg_temp_new(); |
acf930aa PB |
4457 | if (s->env->macsr & MACSR_FI) { |
4458 | if (upper) | |
e1f3808e | 4459 | tcg_gen_andi_i32(tmp, val, 0xffff0000); |
acf930aa | 4460 | else |
e1f3808e | 4461 | tcg_gen_shli_i32(tmp, val, 16); |
acf930aa PB |
4462 | } else if (s->env->macsr & MACSR_SU) { |
4463 | if (upper) | |
e1f3808e | 4464 | tcg_gen_sari_i32(tmp, val, 16); |
acf930aa | 4465 | else |
e1f3808e | 4466 | tcg_gen_ext16s_i32(tmp, val); |
acf930aa PB |
4467 | } else { |
4468 | if (upper) | |
e1f3808e | 4469 | tcg_gen_shri_i32(tmp, val, 16); |
acf930aa | 4470 | else |
e1f3808e | 4471 | tcg_gen_ext16u_i32(tmp, val); |
acf930aa PB |
4472 | } |
4473 | return tmp; | |
4474 | } | |
4475 | ||
e1f3808e PB |
4476 | static void gen_mac_clear_flags(void) |
4477 | { | |
4478 | tcg_gen_andi_i32(QREG_MACSR, QREG_MACSR, | |
4479 | ~(MACSR_V | MACSR_Z | MACSR_N | MACSR_EV)); | |
4480 | } | |
4481 | ||
acf930aa PB |
4482 | DISAS_INSN(mac) |
4483 | { | |
e1f3808e PB |
4484 | TCGv rx; |
4485 | TCGv ry; | |
acf930aa PB |
4486 | uint16_t ext; |
4487 | int acc; | |
e1f3808e PB |
4488 | TCGv tmp; |
4489 | TCGv addr; | |
4490 | TCGv loadval; | |
acf930aa | 4491 | int dual; |
e1f3808e PB |
4492 | TCGv saved_flags; |
4493 | ||
a7812ae4 PB |
4494 | if (!s->done_mac) { |
4495 | s->mactmp = tcg_temp_new_i64(); | |
4496 | s->done_mac = 1; | |
4497 | } | |
acf930aa | 4498 | |
28b68cd7 | 4499 | ext = read_im16(env, s); |
acf930aa PB |
4500 | |
4501 | acc = ((insn >> 7) & 1) | ((ext >> 3) & 2); | |
4502 | dual = ((insn & 0x30) != 0 && (ext & 3) != 0); | |
d315c888 | 4503 | if (dual && !m68k_feature(s->env, M68K_FEATURE_CF_EMAC_B)) { |
d4d79bb1 | 4504 | disas_undef(env, s, insn); |
d315c888 PB |
4505 | return; |
4506 | } | |
acf930aa PB |
4507 | if (insn & 0x30) { |
4508 | /* MAC with load. */ | |
d4d79bb1 | 4509 | tmp = gen_lea(env, s, insn, OS_LONG); |
a7812ae4 | 4510 | addr = tcg_temp_new(); |
e1f3808e | 4511 | tcg_gen_and_i32(addr, tmp, QREG_MAC_MASK); |
acf930aa PB |
4512 | /* Load the value now to ensure correct exception behavior. |
4513 | Perform writeback after reading the MAC inputs. */ | |
4514 | loadval = gen_load(s, OS_LONG, addr, 0); | |
4515 | ||
4516 | acc ^= 1; | |
4517 | rx = (ext & 0x8000) ? AREG(ext, 12) : DREG(insn, 12); | |
4518 | ry = (ext & 8) ? AREG(ext, 0) : DREG(ext, 0); | |
4519 | } else { | |
e1f3808e | 4520 | loadval = addr = NULL_QREG; |
acf930aa PB |
4521 | rx = (insn & 0x40) ? AREG(insn, 9) : DREG(insn, 9); |
4522 | ry = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0); | |
4523 | } | |
4524 | ||
e1f3808e PB |
4525 | gen_mac_clear_flags(); |
4526 | #if 0 | |
acf930aa | 4527 | l1 = -1; |
e1f3808e | 4528 | /* Disabled because conditional branches clobber temporary vars. */ |
acf930aa PB |
4529 | if ((s->env->macsr & MACSR_OMC) != 0 && !dual) { |
4530 | /* Skip the multiply if we know we will ignore it. */ | |
4531 | l1 = gen_new_label(); | |
a7812ae4 | 4532 | tmp = tcg_temp_new(); |
e1f3808e | 4533 | tcg_gen_andi_i32(tmp, QREG_MACSR, 1 << (acc + 8)); |
acf930aa PB |
4534 | gen_op_jmp_nz32(tmp, l1); |
4535 | } | |
e1f3808e | 4536 | #endif |
acf930aa PB |
4537 | |
4538 | if ((ext & 0x0800) == 0) { | |
4539 | /* Word. */ | |
4540 | rx = gen_mac_extract_word(s, rx, (ext & 0x80) != 0); | |
4541 | ry = gen_mac_extract_word(s, ry, (ext & 0x40) != 0); | |
4542 | } | |
4543 | if (s->env->macsr & MACSR_FI) { | |
e1f3808e | 4544 | gen_helper_macmulf(s->mactmp, cpu_env, rx, ry); |
acf930aa PB |
4545 | } else { |
4546 | if (s->env->macsr & MACSR_SU) | |
e1f3808e | 4547 | gen_helper_macmuls(s->mactmp, cpu_env, rx, ry); |
acf930aa | 4548 | else |
e1f3808e | 4549 | gen_helper_macmulu(s->mactmp, cpu_env, rx, ry); |
acf930aa PB |
4550 | switch ((ext >> 9) & 3) { |
4551 | case 1: | |
e1f3808e | 4552 | tcg_gen_shli_i64(s->mactmp, s->mactmp, 1); |
acf930aa PB |
4553 | break; |
4554 | case 3: | |
e1f3808e | 4555 | tcg_gen_shri_i64(s->mactmp, s->mactmp, 1); |
acf930aa PB |
4556 | break; |
4557 | } | |
4558 | } | |
4559 | ||
4560 | if (dual) { | |
4561 | /* Save the overflow flag from the multiply. */ | |
a7812ae4 | 4562 | saved_flags = tcg_temp_new(); |
e1f3808e PB |
4563 | tcg_gen_mov_i32(saved_flags, QREG_MACSR); |
4564 | } else { | |
4565 | saved_flags = NULL_QREG; | |
acf930aa PB |
4566 | } |
4567 | ||
e1f3808e PB |
4568 | #if 0 |
4569 | /* Disabled because conditional branches clobber temporary vars. */ | |
acf930aa PB |
4570 | if ((s->env->macsr & MACSR_OMC) != 0 && dual) { |
4571 | /* Skip the accumulate if the value is already saturated. */ | |
4572 | l1 = gen_new_label(); | |
a7812ae4 | 4573 | tmp = tcg_temp_new(); |
351326a6 | 4574 | gen_op_and32(tmp, QREG_MACSR, tcg_const_i32(MACSR_PAV0 << acc)); |
acf930aa PB |
4575 | gen_op_jmp_nz32(tmp, l1); |
4576 | } | |
e1f3808e | 4577 | #endif |
acf930aa PB |
4578 | |
4579 | if (insn & 0x100) | |
e1f3808e | 4580 | tcg_gen_sub_i64(MACREG(acc), MACREG(acc), s->mactmp); |
acf930aa | 4581 | else |
e1f3808e | 4582 | tcg_gen_add_i64(MACREG(acc), MACREG(acc), s->mactmp); |
acf930aa PB |
4583 | |
4584 | if (s->env->macsr & MACSR_FI) | |
e1f3808e | 4585 | gen_helper_macsatf(cpu_env, tcg_const_i32(acc)); |
acf930aa | 4586 | else if (s->env->macsr & MACSR_SU) |
e1f3808e | 4587 | gen_helper_macsats(cpu_env, tcg_const_i32(acc)); |
acf930aa | 4588 | else |
e1f3808e | 4589 | gen_helper_macsatu(cpu_env, tcg_const_i32(acc)); |
acf930aa | 4590 | |
e1f3808e PB |
4591 | #if 0 |
4592 | /* Disabled because conditional branches clobber temporary vars. */ | |
acf930aa PB |
4593 | if (l1 != -1) |
4594 | gen_set_label(l1); | |
e1f3808e | 4595 | #endif |
acf930aa PB |
4596 | |
4597 | if (dual) { | |
4598 | /* Dual accumulate variant. */ | |
4599 | acc = (ext >> 2) & 3; | |
4600 | /* Restore the overflow flag from the multiplier. */ | |
e1f3808e PB |
4601 | tcg_gen_mov_i32(QREG_MACSR, saved_flags); |
4602 | #if 0 | |
4603 | /* Disabled because conditional branches clobber temporary vars. */ | |
acf930aa PB |
4604 | if ((s->env->macsr & MACSR_OMC) != 0) { |
4605 | /* Skip the accumulate if the value is already saturated. */ | |
4606 | l1 = gen_new_label(); | |
a7812ae4 | 4607 | tmp = tcg_temp_new(); |
351326a6 | 4608 | gen_op_and32(tmp, QREG_MACSR, tcg_const_i32(MACSR_PAV0 << acc)); |
acf930aa PB |
4609 | gen_op_jmp_nz32(tmp, l1); |
4610 | } | |
e1f3808e | 4611 | #endif |
acf930aa | 4612 | if (ext & 2) |
e1f3808e | 4613 | tcg_gen_sub_i64(MACREG(acc), MACREG(acc), s->mactmp); |
acf930aa | 4614 | else |
e1f3808e | 4615 | tcg_gen_add_i64(MACREG(acc), MACREG(acc), s->mactmp); |
acf930aa | 4616 | if (s->env->macsr & MACSR_FI) |
e1f3808e | 4617 | gen_helper_macsatf(cpu_env, tcg_const_i32(acc)); |
acf930aa | 4618 | else if (s->env->macsr & MACSR_SU) |
e1f3808e | 4619 | gen_helper_macsats(cpu_env, tcg_const_i32(acc)); |
acf930aa | 4620 | else |
e1f3808e PB |
4621 | gen_helper_macsatu(cpu_env, tcg_const_i32(acc)); |
4622 | #if 0 | |
4623 | /* Disabled because conditional branches clobber temporary vars. */ | |
acf930aa PB |
4624 | if (l1 != -1) |
4625 | gen_set_label(l1); | |
e1f3808e | 4626 | #endif |
acf930aa | 4627 | } |
e1f3808e | 4628 | gen_helper_mac_set_flags(cpu_env, tcg_const_i32(acc)); |
acf930aa PB |
4629 | |
4630 | if (insn & 0x30) { | |
e1f3808e | 4631 | TCGv rw; |
acf930aa | 4632 | rw = (insn & 0x40) ? AREG(insn, 9) : DREG(insn, 9); |
e1f3808e | 4633 | tcg_gen_mov_i32(rw, loadval); |
acf930aa PB |
4634 | /* FIXME: Should address writeback happen with the masked or |
4635 | unmasked value? */ | |
4636 | switch ((insn >> 3) & 7) { | |
4637 | case 3: /* Post-increment. */ | |
e1f3808e | 4638 | tcg_gen_addi_i32(AREG(insn, 0), addr, 4); |
acf930aa PB |
4639 | break; |
4640 | case 4: /* Pre-decrement. */ | |
e1f3808e | 4641 | tcg_gen_mov_i32(AREG(insn, 0), addr); |
acf930aa PB |
4642 | } |
4643 | } | |
4644 | } | |
4645 | ||
4646 | DISAS_INSN(from_mac) | |
4647 | { | |
e1f3808e | 4648 | TCGv rx; |
a7812ae4 | 4649 | TCGv_i64 acc; |
e1f3808e | 4650 | int accnum; |
acf930aa PB |
4651 | |
4652 | rx = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0); | |
e1f3808e PB |
4653 | accnum = (insn >> 9) & 3; |
4654 | acc = MACREG(accnum); | |
acf930aa | 4655 | if (s->env->macsr & MACSR_FI) { |
a7812ae4 | 4656 | gen_helper_get_macf(rx, cpu_env, acc); |
acf930aa | 4657 | } else if ((s->env->macsr & MACSR_OMC) == 0) { |
ecc7b3aa | 4658 | tcg_gen_extrl_i64_i32(rx, acc); |
acf930aa | 4659 | } else if (s->env->macsr & MACSR_SU) { |
e1f3808e | 4660 | gen_helper_get_macs(rx, acc); |
acf930aa | 4661 | } else { |
e1f3808e PB |
4662 | gen_helper_get_macu(rx, acc); |
4663 | } | |
4664 | if (insn & 0x40) { | |
4665 | tcg_gen_movi_i64(acc, 0); | |
4666 | tcg_gen_andi_i32(QREG_MACSR, QREG_MACSR, ~(MACSR_PAV0 << accnum)); | |
acf930aa | 4667 | } |
acf930aa PB |
4668 | } |
4669 | ||
4670 | DISAS_INSN(move_mac) | |
4671 | { | |
e1f3808e | 4672 | /* FIXME: This can be done without a helper. */ |
acf930aa | 4673 | int src; |
e1f3808e | 4674 | TCGv dest; |
acf930aa | 4675 | src = insn & 3; |
e1f3808e PB |
4676 | dest = tcg_const_i32((insn >> 9) & 3); |
4677 | gen_helper_mac_move(cpu_env, dest, tcg_const_i32(src)); | |
4678 | gen_mac_clear_flags(); | |
4679 | gen_helper_mac_set_flags(cpu_env, dest); | |
acf930aa PB |
4680 | } |
4681 | ||
4682 | DISAS_INSN(from_macsr) | |
4683 | { | |
e1f3808e | 4684 | TCGv reg; |
acf930aa PB |
4685 | |
4686 | reg = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0); | |
e1f3808e | 4687 | tcg_gen_mov_i32(reg, QREG_MACSR); |
acf930aa PB |
4688 | } |
4689 | ||
4690 | DISAS_INSN(from_mask) | |
4691 | { | |
e1f3808e | 4692 | TCGv reg; |
acf930aa | 4693 | reg = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0); |
e1f3808e | 4694 | tcg_gen_mov_i32(reg, QREG_MAC_MASK); |
acf930aa PB |
4695 | } |
4696 | ||
4697 | DISAS_INSN(from_mext) | |
4698 | { | |
e1f3808e PB |
4699 | TCGv reg; |
4700 | TCGv acc; | |
acf930aa | 4701 | reg = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0); |
e1f3808e | 4702 | acc = tcg_const_i32((insn & 0x400) ? 2 : 0); |
acf930aa | 4703 | if (s->env->macsr & MACSR_FI) |
e1f3808e | 4704 | gen_helper_get_mac_extf(reg, cpu_env, acc); |
acf930aa | 4705 | else |
e1f3808e | 4706 | gen_helper_get_mac_exti(reg, cpu_env, acc); |
acf930aa PB |
4707 | } |
4708 | ||
4709 | DISAS_INSN(macsr_to_ccr) | |
4710 | { | |
620c6cf6 RH |
4711 | TCGv tmp = tcg_temp_new(); |
4712 | tcg_gen_andi_i32(tmp, QREG_MACSR, 0xf); | |
4713 | gen_helper_set_sr(cpu_env, tmp); | |
4714 | tcg_temp_free(tmp); | |
9fdb533f | 4715 | set_cc_op(s, CC_OP_FLAGS); |
acf930aa PB |
4716 | } |
4717 | ||
4718 | DISAS_INSN(to_mac) | |
4719 | { | |
a7812ae4 | 4720 | TCGv_i64 acc; |
e1f3808e PB |
4721 | TCGv val; |
4722 | int accnum; | |
4723 | accnum = (insn >> 9) & 3; | |
4724 | acc = MACREG(accnum); | |
d4d79bb1 | 4725 | SRC_EA(env, val, OS_LONG, 0, NULL); |
acf930aa | 4726 | if (s->env->macsr & MACSR_FI) { |
e1f3808e PB |
4727 | tcg_gen_ext_i32_i64(acc, val); |
4728 | tcg_gen_shli_i64(acc, acc, 8); | |
acf930aa | 4729 | } else if (s->env->macsr & MACSR_SU) { |
e1f3808e | 4730 | tcg_gen_ext_i32_i64(acc, val); |
acf930aa | 4731 | } else { |
e1f3808e | 4732 | tcg_gen_extu_i32_i64(acc, val); |
acf930aa | 4733 | } |
e1f3808e PB |
4734 | tcg_gen_andi_i32(QREG_MACSR, QREG_MACSR, ~(MACSR_PAV0 << accnum)); |
4735 | gen_mac_clear_flags(); | |
4736 | gen_helper_mac_set_flags(cpu_env, tcg_const_i32(accnum)); | |
acf930aa PB |
4737 | } |
4738 | ||
4739 | DISAS_INSN(to_macsr) | |
4740 | { | |
e1f3808e | 4741 | TCGv val; |
d4d79bb1 | 4742 | SRC_EA(env, val, OS_LONG, 0, NULL); |
e1f3808e | 4743 | gen_helper_set_macsr(cpu_env, val); |
acf930aa PB |
4744 | gen_lookup_tb(s); |
4745 | } | |
4746 | ||
4747 | DISAS_INSN(to_mask) | |
4748 | { | |
e1f3808e | 4749 | TCGv val; |
d4d79bb1 | 4750 | SRC_EA(env, val, OS_LONG, 0, NULL); |
e1f3808e | 4751 | tcg_gen_ori_i32(QREG_MAC_MASK, val, 0xffff0000); |
acf930aa PB |
4752 | } |
4753 | ||
4754 | DISAS_INSN(to_mext) | |
4755 | { | |
e1f3808e PB |
4756 | TCGv val; |
4757 | TCGv acc; | |
d4d79bb1 | 4758 | SRC_EA(env, val, OS_LONG, 0, NULL); |
e1f3808e | 4759 | acc = tcg_const_i32((insn & 0x400) ? 2 : 0); |
acf930aa | 4760 | if (s->env->macsr & MACSR_FI) |
e1f3808e | 4761 | gen_helper_set_mac_extf(cpu_env, val, acc); |
acf930aa | 4762 | else if (s->env->macsr & MACSR_SU) |
e1f3808e | 4763 | gen_helper_set_mac_exts(cpu_env, val, acc); |
acf930aa | 4764 | else |
e1f3808e | 4765 | gen_helper_set_mac_extu(cpu_env, val, acc); |
acf930aa PB |
4766 | } |
4767 | ||
e6e5906b PB |
4768 | static disas_proc opcode_table[65536]; |
4769 | ||
4770 | static void | |
4771 | register_opcode (disas_proc proc, uint16_t opcode, uint16_t mask) | |
4772 | { | |
4773 | int i; | |
4774 | int from; | |
4775 | int to; | |
4776 | ||
4777 | /* Sanity check. All set bits must be included in the mask. */ | |
5fc4adf6 PB |
4778 | if (opcode & ~mask) { |
4779 | fprintf(stderr, | |
4780 | "qemu internal error: bogus opcode definition %04x/%04x\n", | |
4781 | opcode, mask); | |
e6e5906b | 4782 | abort(); |
5fc4adf6 | 4783 | } |
e6e5906b PB |
4784 | /* This could probably be cleverer. For now just optimize the case where |
4785 | the top bits are known. */ | |
4786 | /* Find the first zero bit in the mask. */ | |
4787 | i = 0x8000; | |
4788 | while ((i & mask) != 0) | |
4789 | i >>= 1; | |
4790 | /* Iterate over all combinations of this and lower bits. */ | |
4791 | if (i == 0) | |
4792 | i = 1; | |
4793 | else | |
4794 | i <<= 1; | |
4795 | from = opcode & ~(i - 1); | |
4796 | to = from + i; | |
0633879f | 4797 | for (i = from; i < to; i++) { |
e6e5906b PB |
4798 | if ((i & mask) == opcode) |
4799 | opcode_table[i] = proc; | |
0633879f | 4800 | } |
e6e5906b PB |
4801 | } |
4802 | ||
4803 | /* Register m68k opcode handlers. Order is important. | |
4804 | Later insn override earlier ones. */ | |
0402f767 | 4805 | void register_m68k_insns (CPUM68KState *env) |
e6e5906b | 4806 | { |
b2085257 JPAG |
4807 | /* Build the opcode table only once to avoid |
4808 | multithreading issues. */ | |
4809 | if (opcode_table[0] != NULL) { | |
4810 | return; | |
4811 | } | |
f076803b LV |
4812 | |
4813 | /* use BASE() for instruction available | |
4814 | * for CF_ISA_A and M68000. | |
4815 | */ | |
4816 | #define BASE(name, opcode, mask) \ | |
4817 | register_opcode(disas_##name, 0x##opcode, 0x##mask) | |
d315c888 | 4818 | #define INSN(name, opcode, mask, feature) do { \ |
0402f767 | 4819 | if (m68k_feature(env, M68K_FEATURE_##feature)) \ |
f076803b | 4820 | BASE(name, opcode, mask); \ |
d315c888 | 4821 | } while(0) |
f076803b | 4822 | BASE(undef, 0000, 0000); |
0402f767 | 4823 | INSN(arith_im, 0080, fff8, CF_ISA_A); |
f076803b LV |
4824 | INSN(arith_im, 0000, ff00, M68000); |
4825 | INSN(undef, 00c0, ffc0, M68000); | |
d315c888 | 4826 | INSN(bitrev, 00c0, fff8, CF_ISA_APLUSC); |
f076803b LV |
4827 | BASE(bitop_reg, 0100, f1c0); |
4828 | BASE(bitop_reg, 0140, f1c0); | |
4829 | BASE(bitop_reg, 0180, f1c0); | |
4830 | BASE(bitop_reg, 01c0, f1c0); | |
0402f767 | 4831 | INSN(arith_im, 0280, fff8, CF_ISA_A); |
f076803b LV |
4832 | INSN(arith_im, 0200, ff00, M68000); |
4833 | INSN(undef, 02c0, ffc0, M68000); | |
d315c888 | 4834 | INSN(byterev, 02c0, fff8, CF_ISA_APLUSC); |
0402f767 | 4835 | INSN(arith_im, 0480, fff8, CF_ISA_A); |
f076803b LV |
4836 | INSN(arith_im, 0400, ff00, M68000); |
4837 | INSN(undef, 04c0, ffc0, M68000); | |
4838 | INSN(arith_im, 0600, ff00, M68000); | |
4839 | INSN(undef, 06c0, ffc0, M68000); | |
d315c888 | 4840 | INSN(ff1, 04c0, fff8, CF_ISA_APLUSC); |
0402f767 | 4841 | INSN(arith_im, 0680, fff8, CF_ISA_A); |
0402f767 | 4842 | INSN(arith_im, 0c00, ff38, CF_ISA_A); |
f076803b LV |
4843 | INSN(arith_im, 0c00, ff00, M68000); |
4844 | BASE(bitop_im, 0800, ffc0); | |
4845 | BASE(bitop_im, 0840, ffc0); | |
4846 | BASE(bitop_im, 0880, ffc0); | |
4847 | BASE(bitop_im, 08c0, ffc0); | |
4848 | INSN(arith_im, 0a80, fff8, CF_ISA_A); | |
4849 | INSN(arith_im, 0a00, ff00, M68000); | |
14f94406 LV |
4850 | INSN(cas, 0ac0, ffc0, CAS); |
4851 | INSN(cas, 0cc0, ffc0, CAS); | |
4852 | INSN(cas, 0ec0, ffc0, CAS); | |
4853 | INSN(cas2w, 0cfc, ffff, CAS); | |
4854 | INSN(cas2l, 0efc, ffff, CAS); | |
f076803b LV |
4855 | BASE(move, 1000, f000); |
4856 | BASE(move, 2000, f000); | |
4857 | BASE(move, 3000, f000); | |
d315c888 | 4858 | INSN(strldsr, 40e7, ffff, CF_ISA_APLUSC); |
0402f767 | 4859 | INSN(negx, 4080, fff8, CF_ISA_A); |
a665a820 RH |
4860 | INSN(negx, 4000, ff00, M68000); |
4861 | INSN(undef, 40c0, ffc0, M68000); | |
0402f767 | 4862 | INSN(move_from_sr, 40c0, fff8, CF_ISA_A); |
f076803b LV |
4863 | INSN(move_from_sr, 40c0, ffc0, M68000); |
4864 | BASE(lea, 41c0, f1c0); | |
4865 | BASE(clr, 4200, ff00); | |
4866 | BASE(undef, 42c0, ffc0); | |
0402f767 | 4867 | INSN(move_from_ccr, 42c0, fff8, CF_ISA_A); |
7c0eb318 | 4868 | INSN(move_from_ccr, 42c0, ffc0, M68000); |
0402f767 | 4869 | INSN(neg, 4480, fff8, CF_ISA_A); |
f076803b LV |
4870 | INSN(neg, 4400, ff00, M68000); |
4871 | INSN(undef, 44c0, ffc0, M68000); | |
4872 | BASE(move_to_ccr, 44c0, ffc0); | |
0402f767 | 4873 | INSN(not, 4680, fff8, CF_ISA_A); |
f076803b LV |
4874 | INSN(not, 4600, ff00, M68000); |
4875 | INSN(undef, 46c0, ffc0, M68000); | |
0402f767 | 4876 | INSN(move_to_sr, 46c0, ffc0, CF_ISA_A); |
fb5543d8 | 4877 | INSN(nbcd, 4800, ffc0, M68000); |
c630e436 | 4878 | INSN(linkl, 4808, fff8, M68000); |
f076803b LV |
4879 | BASE(pea, 4840, ffc0); |
4880 | BASE(swap, 4840, fff8); | |
71600eda | 4881 | INSN(bkpt, 4848, fff8, BKPT); |
7b542eb9 LV |
4882 | INSN(movem, 48d0, fbf8, CF_ISA_A); |
4883 | INSN(movem, 48e8, fbf8, CF_ISA_A); | |
4884 | INSN(movem, 4880, fb80, M68000); | |
f076803b LV |
4885 | BASE(ext, 4880, fff8); |
4886 | BASE(ext, 48c0, fff8); | |
4887 | BASE(ext, 49c0, fff8); | |
4888 | BASE(tst, 4a00, ff00); | |
0402f767 | 4889 | INSN(tas, 4ac0, ffc0, CF_ISA_B); |
f076803b | 4890 | INSN(tas, 4ac0, ffc0, M68000); |
0402f767 PB |
4891 | INSN(halt, 4ac8, ffff, CF_ISA_A); |
4892 | INSN(pulse, 4acc, ffff, CF_ISA_A); | |
f076803b | 4893 | BASE(illegal, 4afc, ffff); |
0402f767 | 4894 | INSN(mull, 4c00, ffc0, CF_ISA_A); |
f076803b | 4895 | INSN(mull, 4c00, ffc0, LONG_MULDIV); |
0402f767 | 4896 | INSN(divl, 4c40, ffc0, CF_ISA_A); |
f076803b | 4897 | INSN(divl, 4c40, ffc0, LONG_MULDIV); |
0402f767 | 4898 | INSN(sats, 4c80, fff8, CF_ISA_B); |
f076803b LV |
4899 | BASE(trap, 4e40, fff0); |
4900 | BASE(link, 4e50, fff8); | |
4901 | BASE(unlk, 4e58, fff8); | |
20dcee94 PB |
4902 | INSN(move_to_usp, 4e60, fff8, USP); |
4903 | INSN(move_from_usp, 4e68, fff8, USP); | |
f076803b LV |
4904 | BASE(nop, 4e71, ffff); |
4905 | BASE(stop, 4e72, ffff); | |
4906 | BASE(rte, 4e73, ffff); | |
4907 | BASE(rts, 4e75, ffff); | |
0402f767 | 4908 | INSN(movec, 4e7b, ffff, CF_ISA_A); |
f076803b | 4909 | BASE(jump, 4e80, ffc0); |
8a370c6c | 4910 | BASE(jump, 4ec0, ffc0); |
f076803b | 4911 | INSN(addsubq, 5000, f080, M68000); |
8a370c6c | 4912 | BASE(addsubq, 5080, f0c0); |
d5a3cf33 LV |
4913 | INSN(scc, 50c0, f0f8, CF_ISA_A); /* Scc.B Dx */ |
4914 | INSN(scc, 50c0, f0c0, M68000); /* Scc.B <EA> */ | |
beff27ab | 4915 | INSN(dbcc, 50c8, f0f8, M68000); |
0402f767 | 4916 | INSN(tpf, 51f8, fff8, CF_ISA_A); |
d315c888 PB |
4917 | |
4918 | /* Branch instructions. */ | |
f076803b | 4919 | BASE(branch, 6000, f000); |
d315c888 | 4920 | /* Disable long branch instructions, then add back the ones we want. */ |
f076803b | 4921 | BASE(undef, 60ff, f0ff); /* All long branches. */ |
d315c888 PB |
4922 | INSN(branch, 60ff, f0ff, CF_ISA_B); |
4923 | INSN(undef, 60ff, ffff, CF_ISA_B); /* bra.l */ | |
4924 | INSN(branch, 60ff, ffff, BRAL); | |
f076803b | 4925 | INSN(branch, 60ff, f0ff, BCCL); |
d315c888 | 4926 | |
f076803b | 4927 | BASE(moveq, 7000, f100); |
0402f767 | 4928 | INSN(mvzs, 7100, f100, CF_ISA_B); |
f076803b LV |
4929 | BASE(or, 8000, f000); |
4930 | BASE(divw, 80c0, f0c0); | |
fb5543d8 LV |
4931 | INSN(sbcd_reg, 8100, f1f8, M68000); |
4932 | INSN(sbcd_mem, 8108, f1f8, M68000); | |
f076803b | 4933 | BASE(addsub, 9000, f000); |
a665a820 RH |
4934 | INSN(undef, 90c0, f0c0, CF_ISA_A); |
4935 | INSN(subx_reg, 9180, f1f8, CF_ISA_A); | |
4936 | INSN(subx_reg, 9100, f138, M68000); | |
4937 | INSN(subx_mem, 9108, f138, M68000); | |
0402f767 | 4938 | INSN(suba, 91c0, f1c0, CF_ISA_A); |
415f4b62 | 4939 | INSN(suba, 90c0, f0c0, M68000); |
acf930aa | 4940 | |
f076803b | 4941 | BASE(undef_mac, a000, f000); |
acf930aa PB |
4942 | INSN(mac, a000, f100, CF_EMAC); |
4943 | INSN(from_mac, a180, f9b0, CF_EMAC); | |
4944 | INSN(move_mac, a110, f9fc, CF_EMAC); | |
4945 | INSN(from_macsr,a980, f9f0, CF_EMAC); | |
4946 | INSN(from_mask, ad80, fff0, CF_EMAC); | |
4947 | INSN(from_mext, ab80, fbf0, CF_EMAC); | |
4948 | INSN(macsr_to_ccr, a9c0, ffff, CF_EMAC); | |
4949 | INSN(to_mac, a100, f9c0, CF_EMAC); | |
4950 | INSN(to_macsr, a900, ffc0, CF_EMAC); | |
4951 | INSN(to_mext, ab00, fbc0, CF_EMAC); | |
4952 | INSN(to_mask, ad00, ffc0, CF_EMAC); | |
4953 | ||
0402f767 PB |
4954 | INSN(mov3q, a140, f1c0, CF_ISA_B); |
4955 | INSN(cmp, b000, f1c0, CF_ISA_B); /* cmp.b */ | |
4956 | INSN(cmp, b040, f1c0, CF_ISA_B); /* cmp.w */ | |
4957 | INSN(cmpa, b0c0, f1c0, CF_ISA_B); /* cmpa.w */ | |
4958 | INSN(cmp, b080, f1c0, CF_ISA_A); | |
4959 | INSN(cmpa, b1c0, f1c0, CF_ISA_A); | |
f076803b LV |
4960 | INSN(cmp, b000, f100, M68000); |
4961 | INSN(eor, b100, f100, M68000); | |
817af1c7 | 4962 | INSN(cmpm, b108, f138, M68000); |
f076803b | 4963 | INSN(cmpa, b0c0, f0c0, M68000); |
0402f767 | 4964 | INSN(eor, b180, f1c0, CF_ISA_A); |
f076803b | 4965 | BASE(and, c000, f000); |
29cf437d LV |
4966 | INSN(exg_dd, c140, f1f8, M68000); |
4967 | INSN(exg_aa, c148, f1f8, M68000); | |
4968 | INSN(exg_da, c188, f1f8, M68000); | |
f076803b | 4969 | BASE(mulw, c0c0, f0c0); |
fb5543d8 LV |
4970 | INSN(abcd_reg, c100, f1f8, M68000); |
4971 | INSN(abcd_mem, c108, f1f8, M68000); | |
f076803b | 4972 | BASE(addsub, d000, f000); |
a665a820 RH |
4973 | INSN(undef, d0c0, f0c0, CF_ISA_A); |
4974 | INSN(addx_reg, d180, f1f8, CF_ISA_A); | |
4975 | INSN(addx_reg, d100, f138, M68000); | |
4976 | INSN(addx_mem, d108, f138, M68000); | |
0402f767 | 4977 | INSN(adda, d1c0, f1c0, CF_ISA_A); |
f076803b | 4978 | INSN(adda, d0c0, f0c0, M68000); |
0402f767 PB |
4979 | INSN(shift_im, e080, f0f0, CF_ISA_A); |
4980 | INSN(shift_reg, e0a0, f0f0, CF_ISA_A); | |
367790cc RH |
4981 | INSN(shift8_im, e000, f0f0, M68000); |
4982 | INSN(shift16_im, e040, f0f0, M68000); | |
4983 | INSN(shift_im, e080, f0f0, M68000); | |
4984 | INSN(shift8_reg, e020, f0f0, M68000); | |
4985 | INSN(shift16_reg, e060, f0f0, M68000); | |
4986 | INSN(shift_reg, e0a0, f0f0, M68000); | |
4987 | INSN(shift_mem, e0c0, fcc0, M68000); | |
0194cf31 LV |
4988 | INSN(rotate_im, e090, f0f0, M68000); |
4989 | INSN(rotate8_im, e010, f0f0, M68000); | |
4990 | INSN(rotate16_im, e050, f0f0, M68000); | |
4991 | INSN(rotate_reg, e0b0, f0f0, M68000); | |
4992 | INSN(rotate8_reg, e030, f0f0, M68000); | |
4993 | INSN(rotate16_reg, e070, f0f0, M68000); | |
4994 | INSN(rotate_mem, e4c0, fcc0, M68000); | |
f2224f2c RH |
4995 | INSN(bfext_mem, e9c0, fdc0, BITFIELD); /* bfextu & bfexts */ |
4996 | INSN(bfext_reg, e9c0, fdf8, BITFIELD); | |
4997 | INSN(bfins_mem, efc0, ffc0, BITFIELD); | |
ac815f46 | 4998 | INSN(bfins_reg, efc0, fff8, BITFIELD); |
f2224f2c | 4999 | INSN(bfop_mem, eac0, ffc0, BITFIELD); /* bfchg */ |
ac815f46 | 5000 | INSN(bfop_reg, eac0, fff8, BITFIELD); /* bfchg */ |
f2224f2c | 5001 | INSN(bfop_mem, ecc0, ffc0, BITFIELD); /* bfclr */ |
ac815f46 | 5002 | INSN(bfop_reg, ecc0, fff8, BITFIELD); /* bfclr */ |
a45f1763 RH |
5003 | INSN(bfop_mem, edc0, ffc0, BITFIELD); /* bfffo */ |
5004 | INSN(bfop_reg, edc0, fff8, BITFIELD); /* bfffo */ | |
f2224f2c | 5005 | INSN(bfop_mem, eec0, ffc0, BITFIELD); /* bfset */ |
ac815f46 | 5006 | INSN(bfop_reg, eec0, fff8, BITFIELD); /* bfset */ |
f2224f2c | 5007 | INSN(bfop_mem, e8c0, ffc0, BITFIELD); /* bftst */ |
ac815f46 | 5008 | INSN(bfop_reg, e8c0, fff8, BITFIELD); /* bftst */ |
0402f767 | 5009 | INSN(undef_fpu, f000, f000, CF_ISA_A); |
e6e5906b PB |
5010 | INSN(fpu, f200, ffc0, CF_FPU); |
5011 | INSN(fbcc, f280, ffc0, CF_FPU); | |
0633879f PB |
5012 | INSN(frestore, f340, ffc0, CF_FPU); |
5013 | INSN(fsave, f340, ffc0, CF_FPU); | |
0402f767 PB |
5014 | INSN(intouch, f340, ffc0, CF_ISA_A); |
5015 | INSN(cpushl, f428, ff38, CF_ISA_A); | |
5016 | INSN(wddata, fb00, ff00, CF_ISA_A); | |
5017 | INSN(wdebug, fbc0, ffc0, CF_ISA_A); | |
e6e5906b PB |
5018 | #undef INSN |
5019 | } | |
5020 | ||
5021 | /* ??? Some of this implementation is not exception safe. We should always | |
5022 | write back the result to memory before setting the condition codes. */ | |
2b3e3cfe | 5023 | static void disas_m68k_insn(CPUM68KState * env, DisasContext *s) |
e6e5906b | 5024 | { |
8a1e52b6 | 5025 | uint16_t insn = read_im16(env, s); |
d4d79bb1 | 5026 | opcode_table[insn](env, s, insn); |
8a1e52b6 | 5027 | do_writebacks(s); |
e6e5906b PB |
5028 | } |
5029 | ||
e6e5906b | 5030 | /* generate intermediate code for basic block 'tb'. */ |
4e5e1215 | 5031 | void gen_intermediate_code(CPUM68KState *env, TranslationBlock *tb) |
e6e5906b | 5032 | { |
4e5e1215 | 5033 | M68kCPU *cpu = m68k_env_get_cpu(env); |
ed2803da | 5034 | CPUState *cs = CPU(cpu); |
e6e5906b | 5035 | DisasContext dc1, *dc = &dc1; |
e6e5906b PB |
5036 | target_ulong pc_start; |
5037 | int pc_offset; | |
2e70f6ef PB |
5038 | int num_insns; |
5039 | int max_insns; | |
e6e5906b PB |
5040 | |
5041 | /* generate intermediate code */ | |
5042 | pc_start = tb->pc; | |
3b46e624 | 5043 | |
e6e5906b PB |
5044 | dc->tb = tb; |
5045 | ||
e6dbd3b3 | 5046 | dc->env = env; |
e6e5906b PB |
5047 | dc->is_jmp = DISAS_NEXT; |
5048 | dc->pc = pc_start; | |
5049 | dc->cc_op = CC_OP_DYNAMIC; | |
620c6cf6 | 5050 | dc->cc_op_synced = 1; |
ed2803da | 5051 | dc->singlestep_enabled = cs->singlestep_enabled; |
e6e5906b | 5052 | dc->fpcr = env->fpcr; |
0633879f | 5053 | dc->user = (env->sr & SR_S) == 0; |
a7812ae4 | 5054 | dc->done_mac = 0; |
8a1e52b6 | 5055 | dc->writeback_mask = 0; |
2e70f6ef PB |
5056 | num_insns = 0; |
5057 | max_insns = tb->cflags & CF_COUNT_MASK; | |
190ce7fb | 5058 | if (max_insns == 0) { |
2e70f6ef | 5059 | max_insns = CF_COUNT_MASK; |
190ce7fb RH |
5060 | } |
5061 | if (max_insns > TCG_MAX_INSNS) { | |
5062 | max_insns = TCG_MAX_INSNS; | |
5063 | } | |
2e70f6ef | 5064 | |
cd42d5b2 | 5065 | gen_tb_start(tb); |
e6e5906b | 5066 | do { |
e6e5906b PB |
5067 | pc_offset = dc->pc - pc_start; |
5068 | gen_throws_exception = NULL; | |
20a8856e | 5069 | tcg_gen_insn_start(dc->pc, dc->cc_op); |
959082fc | 5070 | num_insns++; |
667b8e29 | 5071 | |
b933066a RH |
5072 | if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) { |
5073 | gen_exception(dc, dc->pc, EXCP_DEBUG); | |
5074 | dc->is_jmp = DISAS_JUMP; | |
522a0d4e RH |
5075 | /* The address covered by the breakpoint must be included in |
5076 | [tb->pc, tb->pc + tb->size) in order to for it to be | |
5077 | properly cleared -- thus we increment the PC here so that | |
5078 | the logic setting tb->size below does the right thing. */ | |
5079 | dc->pc += 2; | |
b933066a RH |
5080 | break; |
5081 | } | |
5082 | ||
959082fc | 5083 | if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) { |
2e70f6ef | 5084 | gen_io_start(); |
667b8e29 RH |
5085 | } |
5086 | ||
510ff0b7 | 5087 | dc->insn_pc = dc->pc; |
e6e5906b | 5088 | disas_m68k_insn(env, dc); |
fe700adb | 5089 | } while (!dc->is_jmp && !tcg_op_buf_full() && |
ed2803da | 5090 | !cs->singlestep_enabled && |
1b530a6d | 5091 | !singlestep && |
2e70f6ef PB |
5092 | (pc_offset) < (TARGET_PAGE_SIZE - 32) && |
5093 | num_insns < max_insns); | |
e6e5906b | 5094 | |
2e70f6ef PB |
5095 | if (tb->cflags & CF_LAST_IO) |
5096 | gen_io_end(); | |
ed2803da | 5097 | if (unlikely(cs->singlestep_enabled)) { |
e6e5906b PB |
5098 | /* Make sure the pc is updated, and raise a debug exception. */ |
5099 | if (!dc->is_jmp) { | |
9fdb533f | 5100 | update_cc_op(dc); |
e1f3808e | 5101 | tcg_gen_movi_i32(QREG_PC, dc->pc); |
e6e5906b | 5102 | } |
31871141 | 5103 | gen_helper_raise_exception(cpu_env, tcg_const_i32(EXCP_DEBUG)); |
e6e5906b PB |
5104 | } else { |
5105 | switch(dc->is_jmp) { | |
5106 | case DISAS_NEXT: | |
9fdb533f | 5107 | update_cc_op(dc); |
e6e5906b PB |
5108 | gen_jmp_tb(dc, 0, dc->pc); |
5109 | break; | |
5110 | default: | |
5111 | case DISAS_JUMP: | |
5112 | case DISAS_UPDATE: | |
9fdb533f | 5113 | update_cc_op(dc); |
e6e5906b | 5114 | /* indicate that the hash table must be used to find the next TB */ |
57fec1fe | 5115 | tcg_gen_exit_tb(0); |
e6e5906b PB |
5116 | break; |
5117 | case DISAS_TB_JUMP: | |
5118 | /* nothing more to generate */ | |
5119 | break; | |
5120 | } | |
5121 | } | |
806f352d | 5122 | gen_tb_end(tb, num_insns); |
e6e5906b PB |
5123 | |
5124 | #ifdef DEBUG_DISAS | |
4910e6e4 RH |
5125 | if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) |
5126 | && qemu_log_in_addr_range(pc_start)) { | |
1ee73216 | 5127 | qemu_log_lock(); |
93fcfe39 AL |
5128 | qemu_log("----------------\n"); |
5129 | qemu_log("IN: %s\n", lookup_symbol(pc_start)); | |
d49190c4 | 5130 | log_target_disas(cs, pc_start, dc->pc - pc_start, 0); |
93fcfe39 | 5131 | qemu_log("\n"); |
1ee73216 | 5132 | qemu_log_unlock(); |
e6e5906b PB |
5133 | } |
5134 | #endif | |
4e5e1215 RH |
5135 | tb->size = dc->pc - pc_start; |
5136 | tb->icount = num_insns; | |
e6e5906b PB |
5137 | } |
5138 | ||
878096ee AF |
5139 | void m68k_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, |
5140 | int flags) | |
e6e5906b | 5141 | { |
878096ee AF |
5142 | M68kCPU *cpu = M68K_CPU(cs); |
5143 | CPUM68KState *env = &cpu->env; | |
e6e5906b PB |
5144 | int i; |
5145 | uint16_t sr; | |
5146 | CPU_DoubleU u; | |
5147 | for (i = 0; i < 8; i++) | |
5148 | { | |
5149 | u.d = env->fregs[i]; | |
8e394cca RH |
5150 | cpu_fprintf(f, "D%d = %08x A%d = %08x F%d = %08x%08x (%12g)\n", |
5151 | i, env->dregs[i], i, env->aregs[i], | |
5152 | i, u.l.upper, u.l.lower, *(double *)&u.d); | |
e6e5906b PB |
5153 | } |
5154 | cpu_fprintf (f, "PC = %08x ", env->pc); | |
99c51448 | 5155 | sr = env->sr | cpu_m68k_get_ccr(env); |
8e394cca RH |
5156 | cpu_fprintf(f, "SR = %04x %c%c%c%c%c ", sr, (sr & CCF_X) ? 'X' : '-', |
5157 | (sr & CCF_N) ? 'N' : '-', (sr & CCF_Z) ? 'Z' : '-', | |
5158 | (sr & CCF_V) ? 'V' : '-', (sr & CCF_C) ? 'C' : '-'); | |
8fc7cc58 | 5159 | cpu_fprintf (f, "FPRESULT = %12g\n", *(double *)&env->fp_result); |
e6e5906b PB |
5160 | } |
5161 | ||
bad729e2 RH |
5162 | void restore_state_to_opc(CPUM68KState *env, TranslationBlock *tb, |
5163 | target_ulong *data) | |
d2856f1a | 5164 | { |
20a8856e | 5165 | int cc_op = data[1]; |
bad729e2 | 5166 | env->pc = data[0]; |
20a8856e LV |
5167 | if (cc_op != CC_OP_DYNAMIC) { |
5168 | env->cc_op = cc_op; | |
5169 | } | |
d2856f1a | 5170 | } |