]>
Commit | Line | Data |
---|---|---|
b77f98ca AF |
1 | /* |
2 | * QEMU MicroBlaze CPU | |
3 | * | |
61b6208f AF |
4 | * Copyright (c) 2009 Edgar E. Iglesias |
5 | * Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd. | |
b77f98ca | 6 | * Copyright (c) 2012 SUSE LINUX Products GmbH |
73c69456 | 7 | * Copyright (c) 2009 Edgar E. Iglesias, Axis Communications AB. |
b77f98ca AF |
8 | * |
9 | * This library is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU Lesser General Public | |
11 | * License as published by the Free Software Foundation; either | |
12 | * version 2.1 of the License, or (at your option) any later version. | |
13 | * | |
14 | * This library is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
17 | * Lesser General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU Lesser General Public | |
20 | * License along with this library; if not, see | |
21 | * <http://www.gnu.org/licenses/lgpl-2.1.html> | |
22 | */ | |
23 | ||
8fd9dece | 24 | #include "qemu/osdep.h" |
da34e65c | 25 | #include "qapi/error.h" |
b77f98ca AF |
26 | #include "cpu.h" |
27 | #include "qemu-common.h" | |
a1bff71c | 28 | #include "hw/qdev-properties.h" |
3ce8b2bc | 29 | #include "migration/vmstate.h" |
63c91552 | 30 | #include "exec/exec-all.h" |
b77f98ca | 31 | |
72e38754 AF |
32 | static const struct { |
33 | const char *name; | |
34 | uint8_t version_id; | |
35 | } mb_cpu_lookup[] = { | |
36 | /* These key value are as per MBV field in PVR0 */ | |
37 | {"5.00.a", 0x01}, | |
38 | {"5.00.b", 0x02}, | |
39 | {"5.00.c", 0x03}, | |
40 | {"6.00.a", 0x04}, | |
41 | {"6.00.b", 0x06}, | |
42 | {"7.00.a", 0x05}, | |
43 | {"7.00.b", 0x07}, | |
44 | {"7.10.a", 0x08}, | |
45 | {"7.10.b", 0x09}, | |
46 | {"7.10.c", 0x0a}, | |
47 | {"7.10.d", 0x0b}, | |
48 | {"7.20.a", 0x0c}, | |
49 | {"7.20.b", 0x0d}, | |
50 | {"7.20.c", 0x0e}, | |
51 | {"7.20.d", 0x0f}, | |
52 | {"7.30.a", 0x10}, | |
53 | {"7.30.b", 0x11}, | |
54 | {"8.00.a", 0x12}, | |
55 | {"8.00.b", 0x13}, | |
56 | {"8.10.a", 0x14}, | |
57 | {"8.20.a", 0x15}, | |
58 | {"8.20.b", 0x16}, | |
59 | {"8.30.a", 0x17}, | |
60 | {"8.40.a", 0x18}, | |
61 | {"8.40.b", 0x19}, | |
62 | {"8.50.a", 0x1A}, | |
63 | {"9.0", 0x1B}, | |
64 | {"9.1", 0x1D}, | |
65 | {"9.2", 0x1F}, | |
66 | {"9.3", 0x20}, | |
d79fcbc2 EI |
67 | {"9.4", 0x21}, |
68 | {"9.5", 0x22}, | |
69 | {"9.6", 0x23}, | |
72e38754 AF |
70 | {NULL, 0}, |
71 | }; | |
b77f98ca | 72 | |
f45748f1 AF |
73 | static void mb_cpu_set_pc(CPUState *cs, vaddr value) |
74 | { | |
75 | MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); | |
76 | ||
77 | cpu->env.sregs[SR_PC] = value; | |
78 | } | |
79 | ||
8c2e1b00 AF |
80 | static bool mb_cpu_has_work(CPUState *cs) |
81 | { | |
82 | return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI); | |
83 | } | |
84 | ||
73c69456 AF |
85 | #ifndef CONFIG_USER_ONLY |
86 | static void microblaze_cpu_set_irq(void *opaque, int irq, int level) | |
87 | { | |
88 | MicroBlazeCPU *cpu = opaque; | |
89 | CPUState *cs = CPU(cpu); | |
90 | int type = irq ? CPU_INTERRUPT_NMI : CPU_INTERRUPT_HARD; | |
91 | ||
92 | if (level) { | |
93 | cpu_interrupt(cs, type); | |
94 | } else { | |
95 | cpu_reset_interrupt(cs, type); | |
96 | } | |
97 | } | |
98 | #endif | |
99 | ||
b77f98ca AF |
100 | /* CPUClass::reset() */ |
101 | static void mb_cpu_reset(CPUState *s) | |
102 | { | |
103 | MicroBlazeCPU *cpu = MICROBLAZE_CPU(s); | |
104 | MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(cpu); | |
105 | CPUMBState *env = &cpu->env; | |
106 | ||
107 | mcc->parent_reset(s); | |
108 | ||
1f5c00cf | 109 | memset(env, 0, offsetof(CPUMBState, end_reset_fields)); |
8cc9b43f | 110 | env->res_addr = RES_ADDR_NONE; |
61b6208f AF |
111 | |
112 | /* Disable stack protector. */ | |
113 | env->shr = ~0; | |
114 | ||
5250ced8 AF |
115 | env->sregs[SR_PC] = cpu->cfg.base_vectors; |
116 | ||
8bac2242 AF |
117 | #if defined(CONFIG_USER_ONLY) |
118 | /* start in user mode with interrupts enabled. */ | |
119 | env->sregs[SR_MSR] = MSR_EE | MSR_IE | MSR_VM | MSR_UM; | |
120 | #else | |
121 | env->sregs[SR_MSR] = 0; | |
122 | mmu_init(&env->mmu); | |
123 | env->mmu.c_mmu = 3; | |
124 | env->mmu.c_mmu_tlb_access = 3; | |
125 | env->mmu.c_mmu_zones = 16; | |
126 | #endif | |
127 | } | |
128 | ||
efc6674b PC |
129 | static void mb_disas_set_info(CPUState *cpu, disassemble_info *info) |
130 | { | |
131 | info->mach = bfd_arch_microblaze; | |
132 | info->print_insn = print_insn_microblaze; | |
133 | } | |
134 | ||
8bac2242 AF |
135 | static void mb_cpu_realizefn(DeviceState *dev, Error **errp) |
136 | { | |
137 | CPUState *cs = CPU(dev); | |
138 | MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(dev); | |
139 | MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); | |
140 | CPUMBState *env = &cpu->env; | |
72e38754 AF |
141 | uint8_t version_code = 0; |
142 | int i = 0; | |
ce5b1bbf LV |
143 | Error *local_err = NULL; |
144 | ||
145 | cpu_exec_realizefn(cs, &local_err); | |
146 | if (local_err != NULL) { | |
147 | error_propagate(errp, local_err); | |
148 | return; | |
149 | } | |
8bac2242 AF |
150 | |
151 | qemu_init_vcpu(cs); | |
152 | ||
47709e4c | 153 | env->pvr.regs[0] = PVR0_USE_HW_MUL_MASK \ |
61b6208f AF |
154 | | PVR0_USE_EXC_MASK \ |
155 | | PVR0_USE_ICACHE_MASK \ | |
3e922505 | 156 | | PVR0_USE_DCACHE_MASK; |
61b6208f AF |
157 | env->pvr.regs[2] = PVR2_D_OPB_MASK \ |
158 | | PVR2_D_LMB_MASK \ | |
159 | | PVR2_I_OPB_MASK \ | |
160 | | PVR2_I_LMB_MASK \ | |
161 | | PVR2_USE_MSR_INSTR \ | |
162 | | PVR2_USE_PCMP_INSTR \ | |
61b6208f AF |
163 | | PVR2_USE_HW_MUL_MASK \ |
164 | | PVR2_USE_MUL64_MASK \ | |
61b6208f AF |
165 | | PVR2_FPU_EXC_MASK \ |
166 | | 0; | |
9aaaa181 | 167 | |
72e38754 AF |
168 | for (i = 0; mb_cpu_lookup[i].name && cpu->cfg.version; i++) { |
169 | if (strcmp(mb_cpu_lookup[i].name, cpu->cfg.version) == 0) { | |
170 | version_code = mb_cpu_lookup[i].version_id; | |
171 | break; | |
172 | } | |
173 | } | |
174 | ||
175 | if (!version_code) { | |
176 | qemu_log("Invalid MicroBlaze version number: %s\n", cpu->cfg.version); | |
177 | } | |
178 | ||
4e5d45ae | 179 | env->pvr.regs[0] |= (cpu->cfg.stackprot ? PVR0_SPROT_MASK : 0) | |
71446123 | 180 | (cpu->cfg.use_fpu ? PVR0_USE_FPU_MASK : 0) | |
7faa66aa | 181 | (cpu->cfg.use_barrel ? PVR0_USE_BARREL_MASK : 0) | |
47709e4c | 182 | (cpu->cfg.use_div ? PVR0_USE_DIV_MASK : 0) | |
a88bbb00 | 183 | (cpu->cfg.use_mmu ? PVR0_USE_MMU_MASK : 0) | |
72e38754 | 184 | (cpu->cfg.endi ? PVR0_ENDI_MASK : 0) | |
79549c99 | 185 | (version_code << PVR0_VERSION_SHIFT) | |
6fad9e98 | 186 | (cpu->cfg.pvr == C_PVR_FULL ? PVR0_PVR_FULL_MASK : 0); |
4e5d45ae | 187 | |
be67e9ab | 188 | env->pvr.regs[2] |= (cpu->cfg.use_fpu ? PVR2_USE_FPU_MASK : 0) | |
7faa66aa | 189 | (cpu->cfg.use_fpu > 1 ? PVR2_USE_FPU2_MASK : 0) | |
47709e4c EI |
190 | (cpu->cfg.use_barrel ? PVR2_USE_BARREL_MASK : 0) | |
191 | (cpu->cfg.use_div ? PVR2_USE_DIV_MASK : 0); | |
9aaaa181 | 192 | |
a6c3ed24 AF |
193 | env->pvr.regs[5] |= cpu->cfg.dcache_writeback ? |
194 | PVR5_DCACHE_WRITEBACK_MASK : 0; | |
195 | ||
61b6208f AF |
196 | env->pvr.regs[10] = 0x0c000000; /* Default to spartan 3a dsp family. */ |
197 | env->pvr.regs[11] = PVR11_USE_MMU | (16 << 17); | |
198 | ||
746b03b2 AF |
199 | mcc->parent_realize(dev, errp); |
200 | } | |
201 | ||
d0e71ef5 AF |
202 | static void mb_cpu_initfn(Object *obj) |
203 | { | |
c05efcb1 | 204 | CPUState *cs = CPU(obj); |
d0e71ef5 AF |
205 | MicroBlazeCPU *cpu = MICROBLAZE_CPU(obj); |
206 | CPUMBState *env = &cpu->env; | |
cd0c24f9 | 207 | static bool tcg_initialized; |
d0e71ef5 | 208 | |
c05efcb1 | 209 | cs->env_ptr = env; |
d0e71ef5 AF |
210 | |
211 | set_float_rounding_mode(float_round_nearest_even, &env->fp_status); | |
cd0c24f9 | 212 | |
73c69456 AF |
213 | #ifndef CONFIG_USER_ONLY |
214 | /* Inbound IRQ and FIR lines */ | |
215 | qdev_init_gpio_in(DEVICE(cpu), microblaze_cpu_set_irq, 2); | |
216 | #endif | |
217 | ||
cd0c24f9 AF |
218 | if (tcg_enabled() && !tcg_initialized) { |
219 | tcg_initialized = true; | |
220 | mb_tcg_init(); | |
221 | } | |
d0e71ef5 AF |
222 | } |
223 | ||
3ce8b2bc AF |
224 | static const VMStateDescription vmstate_mb_cpu = { |
225 | .name = "cpu", | |
226 | .unmigratable = 1, | |
227 | }; | |
228 | ||
a1bff71c | 229 | static Property mb_properties[] = { |
f27183ab | 230 | DEFINE_PROP_UINT32("base-vectors", MicroBlazeCPU, cfg.base_vectors, 0), |
9aaaa181 | 231 | DEFINE_PROP_BOOL("use-stack-protection", MicroBlazeCPU, cfg.stackprot, |
f44c475c | 232 | false), |
4e5d45ae AF |
233 | /* If use-fpu > 0 - FPU is enabled |
234 | * If use-fpu = 2 - Floating point conversion and square root instructions | |
235 | * are enabled | |
236 | */ | |
be67e9ab | 237 | DEFINE_PROP_UINT8("use-fpu", MicroBlazeCPU, cfg.use_fpu, 2), |
7faa66aa | 238 | DEFINE_PROP_BOOL("use-barrel", MicroBlazeCPU, cfg.use_barrel, true), |
47709e4c | 239 | DEFINE_PROP_BOOL("use-div", MicroBlazeCPU, cfg.use_div, true), |
71446123 | 240 | DEFINE_PROP_BOOL("use-mmu", MicroBlazeCPU, cfg.use_mmu, true), |
a6c3ed24 AF |
241 | DEFINE_PROP_BOOL("dcache-writeback", MicroBlazeCPU, cfg.dcache_writeback, |
242 | false), | |
a88bbb00 | 243 | DEFINE_PROP_BOOL("endianness", MicroBlazeCPU, cfg.endi, false), |
72e38754 | 244 | DEFINE_PROP_STRING("version", MicroBlazeCPU, cfg.version), |
6fad9e98 | 245 | DEFINE_PROP_UINT8("pvr", MicroBlazeCPU, cfg.pvr, C_PVR_FULL), |
a1bff71c EI |
246 | DEFINE_PROP_END_OF_LIST(), |
247 | }; | |
248 | ||
b77f98ca AF |
249 | static void mb_cpu_class_init(ObjectClass *oc, void *data) |
250 | { | |
3ce8b2bc | 251 | DeviceClass *dc = DEVICE_CLASS(oc); |
b77f98ca AF |
252 | CPUClass *cc = CPU_CLASS(oc); |
253 | MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_CLASS(oc); | |
254 | ||
746b03b2 AF |
255 | mcc->parent_realize = dc->realize; |
256 | dc->realize = mb_cpu_realizefn; | |
257 | ||
b77f98ca AF |
258 | mcc->parent_reset = cc->reset; |
259 | cc->reset = mb_cpu_reset; | |
3ce8b2bc | 260 | |
8c2e1b00 | 261 | cc->has_work = mb_cpu_has_work; |
97a8ea5a | 262 | cc->do_interrupt = mb_cpu_do_interrupt; |
29cd33d3 | 263 | cc->cpu_exec_interrupt = mb_cpu_exec_interrupt; |
878096ee | 264 | cc->dump_state = mb_cpu_dump_state; |
f45748f1 | 265 | cc->set_pc = mb_cpu_set_pc; |
5b50e790 AF |
266 | cc->gdb_read_register = mb_cpu_gdb_read_register; |
267 | cc->gdb_write_register = mb_cpu_gdb_write_register; | |
7510454e AF |
268 | #ifdef CONFIG_USER_ONLY |
269 | cc->handle_mmu_fault = mb_cpu_handle_mmu_fault; | |
270 | #else | |
00b941e5 AF |
271 | cc->do_unassigned_access = mb_cpu_unassigned_access; |
272 | cc->get_phys_page_debug = mb_cpu_get_phys_page_debug; | |
273 | #endif | |
3ce8b2bc | 274 | dc->vmsd = &vmstate_mb_cpu; |
a1bff71c | 275 | dc->props = mb_properties; |
a0e372f0 | 276 | cc->gdb_num_core_regs = 32 + 5; |
efc6674b PC |
277 | |
278 | cc->disas_set_info = mb_disas_set_info; | |
b77f98ca AF |
279 | } |
280 | ||
281 | static const TypeInfo mb_cpu_type_info = { | |
282 | .name = TYPE_MICROBLAZE_CPU, | |
283 | .parent = TYPE_CPU, | |
284 | .instance_size = sizeof(MicroBlazeCPU), | |
d0e71ef5 | 285 | .instance_init = mb_cpu_initfn, |
b77f98ca AF |
286 | .class_size = sizeof(MicroBlazeCPUClass), |
287 | .class_init = mb_cpu_class_init, | |
288 | }; | |
289 | ||
290 | static void mb_cpu_register_types(void) | |
291 | { | |
292 | type_register_static(&mb_cpu_type_info); | |
293 | } | |
294 | ||
295 | type_init(mb_cpu_register_types) |